1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "stringpool.h"
40 #include "diagnostic-core.h"
41 #include "insn-attr.h"
44 #include "fold-const.h"
46 #include "stor-layout.h"
48 #include "print-tree.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
57 #include "sched-int.h"
59 #include "gimple-fold.h"
60 #include "gimple-iterator.h"
61 #include "gimple-ssa.h"
62 #include "gimple-walk.h"
65 #include "tm-constrs.h"
66 #include "tree-vectorizer.h"
67 #include "target-globals.h"
70 #include "tree-pass.h"
73 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
76 #include "gstab.h" /* for N_SLINE */
78 #include "case-cfn-macros.h"
80 #include "tree-ssa-propagate.h"
82 /* This file should be included last. */
83 #include "target-def.h"
85 #ifndef TARGET_NO_PROTOTYPE
86 #define TARGET_NO_PROTOTYPE 0
89 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
90 systems will also set long double to be IEEE 128-bit. AIX and Darwin
91 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
92 those systems will not pick up this default. This needs to be after all
93 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
95 #ifndef TARGET_IEEEQUAD_DEFAULT
96 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
97 #define TARGET_IEEEQUAD_DEFAULT 1
99 #define TARGET_IEEEQUAD_DEFAULT 0
103 #define min(A,B) ((A) < (B) ? (A) : (B))
104 #define max(A,B) ((A) > (B) ? (A) : (B))
106 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
108 /* Structure used to define the rs6000 stack */
109 typedef struct rs6000_stack {
110 int reload_completed; /* stack info won't change from here on */
111 int first_gp_reg_save; /* first callee saved GP register used */
112 int first_fp_reg_save; /* first callee saved FP register used */
113 int first_altivec_reg_save; /* first callee saved AltiVec register used */
114 int lr_save_p; /* true if the link reg needs to be saved */
115 int cr_save_p; /* true if the CR reg needs to be saved */
116 unsigned int vrsave_mask; /* mask of vec registers to save */
117 int push_p; /* true if we need to allocate stack space */
118 int calls_p; /* true if the function makes any calls */
119 int world_save_p; /* true if we're saving *everything*:
120 r13-r31, cr, f14-f31, vrsave, v20-v31 */
121 enum rs6000_abi abi; /* which ABI to use */
122 int gp_save_offset; /* offset to save GP regs from initial SP */
123 int fp_save_offset; /* offset to save FP regs from initial SP */
124 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
125 int lr_save_offset; /* offset to save LR from initial SP */
126 int cr_save_offset; /* offset to save CR from initial SP */
127 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
128 int varargs_save_offset; /* offset to save the varargs registers */
129 int ehrd_offset; /* offset to EH return data */
130 int ehcr_offset; /* offset to EH CR field data */
131 int reg_size; /* register size (4 or 8) */
132 HOST_WIDE_INT vars_size; /* variable save area size */
133 int parm_size; /* outgoing parameter size */
134 int save_size; /* save area size */
135 int fixed_size; /* fixed size of stack frame */
136 int gp_size; /* size of saved GP registers */
137 int fp_size; /* size of saved FP registers */
138 int altivec_size; /* size of saved AltiVec registers */
139 int cr_size; /* size to hold CR if not in fixed area */
140 int vrsave_size; /* size to hold VRSAVE */
141 int altivec_padding_size; /* size of altivec alignment padding */
142 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
146 /* A C structure for machine-specific, per-function data.
147 This is added to the cfun structure. */
148 typedef struct GTY(()) machine_function
150 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
151 int ra_needs_full_frame;
152 /* Flags if __builtin_return_address (0) was used. */
154 /* Cache lr_save_p after expansion of builtin_eh_return. */
156 /* Whether we need to save the TOC to the reserved stack location in the
157 function prologue. */
158 bool save_toc_in_prologue;
159 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
160 varargs save area. */
161 HOST_WIDE_INT varargs_save_offset;
162 /* Alternative internal arg pointer for -fsplit-stack. */
163 rtx split_stack_arg_pointer;
164 bool split_stack_argp_used;
165 /* Flag if r2 setup is needed with ELFv2 ABI. */
166 bool r2_setup_needed;
167 /* The number of components we use for separate shrink-wrapping. */
169 /* The components already handled by separate shrink-wrapping, which should
170 not be considered by the prologue and epilogue. */
171 bool gpr_is_wrapped_separately[32];
172 bool fpr_is_wrapped_separately[32];
173 bool lr_is_wrapped_separately;
174 bool toc_is_wrapped_separately;
177 /* Support targetm.vectorize.builtin_mask_for_load. */
178 static GTY(()) tree altivec_builtin_mask_for_load;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 static int rs6000_pic_labelno;
188 /* Counter for labels which are to be placed in .fixup. */
189 int fixuplabelno = 0;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
195 /* Specify the machine mode that pointers have. After generation of rtl, the
196 compiler makes no further distinction between pointers and any other objects
197 of this machine mode. */
198 scalar_int_mode rs6000_pmode;
200 /* Width in bits of a pointer. */
201 unsigned rs6000_pointer_size;
203 #ifdef HAVE_AS_GNU_ATTRIBUTE
204 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
205 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
207 /* Flag whether floating point values have been passed/returned.
208 Note that this doesn't say whether fprs are used, since the
209 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
210 should be set for soft-float values passed in gprs and ieee128
211 values passed in vsx registers. */
212 static bool rs6000_passes_float;
213 static bool rs6000_passes_long_double;
214 /* Flag whether vector values have been passed/returned. */
215 static bool rs6000_passes_vector;
216 /* Flag whether small (<= 8 byte) structures have been returned. */
217 static bool rs6000_returns_struct;
220 /* Value is TRUE if register/mode pair is acceptable. */
221 static bool rs6000_hard_regno_mode_ok_p
222 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
224 /* Maximum number of registers needed for a given register class and mode. */
225 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
227 /* How many registers are needed for a given register and mode. */
228 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
230 /* Map register number to register class. */
231 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
233 static int dbg_cost_ctrl;
235 /* Built in types. */
236 tree rs6000_builtin_types[RS6000_BTI_MAX];
237 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
239 /* Flag to say the TOC is initialized */
240 int toc_initialized, need_toc_init;
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *tls_data_section;
250 static GTY(()) section *tls_private_data_section;
251 static GTY(()) section *read_only_private_data_section;
252 static GTY(()) section *sdata2_section;
253 static GTY(()) section *toc_section;
255 struct builtin_description
257 const HOST_WIDE_INT mask;
258 const enum insn_code icode;
259 const char *const name;
260 const enum rs6000_builtins code;
263 /* Describe the vector unit used for modes. */
264 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
265 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
267 /* Register classes for various constraints that are based on the target
269 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
271 /* Describe the alignment of a vector. */
272 int rs6000_vector_align[NUM_MACHINE_MODES];
274 /* Map selected modes to types for builtins. */
275 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
277 /* What modes to automatically generate reciprocal divide estimate (fre) and
278 reciprocal sqrt (frsqrte) for. */
279 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
281 /* Masks to determine which reciprocal esitmate instructions to generate
283 enum rs6000_recip_mask {
284 RECIP_SF_DIV = 0x001, /* Use divide estimate */
285 RECIP_DF_DIV = 0x002,
286 RECIP_V4SF_DIV = 0x004,
287 RECIP_V2DF_DIV = 0x008,
289 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
290 RECIP_DF_RSQRT = 0x020,
291 RECIP_V4SF_RSQRT = 0x040,
292 RECIP_V2DF_RSQRT = 0x080,
294 /* Various combination of flags for -mrecip=xxx. */
296 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
297 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
298 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
300 RECIP_HIGH_PRECISION = RECIP_ALL,
302 /* On low precision machines like the power5, don't enable double precision
303 reciprocal square root estimate, since it isn't accurate enough. */
304 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
307 /* -mrecip options. */
310 const char *string; /* option name */
311 unsigned int mask; /* mask bits to set */
312 } recip_options[] = {
313 { "all", RECIP_ALL },
314 { "none", RECIP_NONE },
315 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
317 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
318 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
319 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
320 | RECIP_V2DF_RSQRT) },
321 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
322 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
325 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
331 { "power9", PPC_PLATFORM_POWER9 },
332 { "power8", PPC_PLATFORM_POWER8 },
333 { "power7", PPC_PLATFORM_POWER7 },
334 { "power6x", PPC_PLATFORM_POWER6X },
335 { "power6", PPC_PLATFORM_POWER6 },
336 { "power5+", PPC_PLATFORM_POWER5_PLUS },
337 { "power5", PPC_PLATFORM_POWER5 },
338 { "ppc970", PPC_PLATFORM_PPC970 },
339 { "power4", PPC_PLATFORM_POWER4 },
340 { "ppca2", PPC_PLATFORM_PPCA2 },
341 { "ppc476", PPC_PLATFORM_PPC476 },
342 { "ppc464", PPC_PLATFORM_PPC464 },
343 { "ppc440", PPC_PLATFORM_PPC440 },
344 { "ppc405", PPC_PLATFORM_PPC405 },
345 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
348 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
354 } cpu_supports_info[] = {
355 /* AT_HWCAP masks. */
356 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
357 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
358 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
359 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
360 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
361 { "booke", PPC_FEATURE_BOOKE, 0 },
362 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
363 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
364 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
365 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
366 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
367 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
368 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
369 { "notb", PPC_FEATURE_NO_TB, 0 },
370 { "pa6t", PPC_FEATURE_PA6T, 0 },
371 { "power4", PPC_FEATURE_POWER4, 0 },
372 { "power5", PPC_FEATURE_POWER5, 0 },
373 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
374 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
375 { "ppc32", PPC_FEATURE_32, 0 },
376 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
377 { "ppc64", PPC_FEATURE_64, 0 },
378 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
379 { "smt", PPC_FEATURE_SMT, 0 },
380 { "spe", PPC_FEATURE_HAS_SPE, 0 },
381 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
382 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
383 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
385 /* AT_HWCAP2 masks. */
386 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
387 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
388 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
389 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
390 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
391 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
392 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
393 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
394 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
395 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
396 { "darn", PPC_FEATURE2_DARN, 1 },
397 { "scv", PPC_FEATURE2_SCV, 1 }
400 /* On PowerPC, we have a limited number of target clones that we care about
401 which means we can use an array to hold the options, rather than having more
402 elaborate data structures to identify each possible variation. Order the
403 clones from the default to the highest ISA. */
405 CLONE_DEFAULT = 0, /* default clone. */
406 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
407 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
408 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
409 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
413 /* Map compiler ISA bits into HWCAP names. */
415 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
416 const char *name; /* name to use in __builtin_cpu_supports. */
419 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
420 { 0, "" }, /* Default options. */
421 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
422 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
423 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
424 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
428 /* Newer LIBCs explicitly export this symbol to declare that they provide
429 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
430 reference to this symbol whenever we expand a CPU builtin, so that
431 we never link against an old LIBC. */
432 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
434 /* True if we have expanded a CPU builtin. */
437 /* Pointer to function (in rs6000-c.c) that can define or undefine target
438 macros that have changed. Languages that don't support the preprocessor
439 don't link in rs6000-c.c, so we can't call it directly. */
440 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
442 /* Simplfy register classes into simpler classifications. We assume
443 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
444 check for standard register classes (gpr/floating/altivec/vsx) and
445 floating/vector classes (float/altivec/vsx). */
447 enum rs6000_reg_type {
458 /* Map register class to register type. */
459 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
461 /* First/last register type for the 'normal' register types (i.e. general
462 purpose, floating point, altivec, and VSX registers). */
463 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
465 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
468 /* Register classes we care about in secondary reload or go if legitimate
469 address. We only need to worry about GPR, FPR, and Altivec registers here,
470 along an ANY field that is the OR of the 3 register classes. */
472 enum rs6000_reload_reg_type {
473 RELOAD_REG_GPR, /* General purpose registers. */
474 RELOAD_REG_FPR, /* Traditional floating point regs. */
475 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
476 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
480 /* For setting up register classes, loop through the 3 register classes mapping
481 into real registers, and skip the ANY class, which is just an OR of the
483 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
484 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
486 /* Map reload register type to a register in the register class. */
487 struct reload_reg_map_type {
488 const char *name; /* Register class name. */
489 int reg; /* Register in the register class. */
492 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
493 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
494 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
495 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
496 { "Any", -1 }, /* RELOAD_REG_ANY. */
499 /* Mask bits for each register class, indexed per mode. Historically the
500 compiler has been more restrictive which types can do PRE_MODIFY instead of
501 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
502 typedef unsigned char addr_mask_type;
504 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
505 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
506 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
507 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
508 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
509 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
510 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
511 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
513 /* Register type masks based on the type, of valid addressing modes. */
514 struct rs6000_reg_addr {
515 enum insn_code reload_load; /* INSN to reload for loading. */
516 enum insn_code reload_store; /* INSN to reload for storing. */
517 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
518 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
519 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
520 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
521 /* INSNs for fusing addi with loads
522 or stores for each reg. class. */
523 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
524 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
525 /* INSNs for fusing addis with loads
526 or stores for each reg. class. */
527 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
528 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
529 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
530 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
531 bool fused_toc; /* Mode supports TOC fusion. */
534 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
536 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
538 mode_supports_pre_incdec_p (machine_mode mode)
540 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
544 /* Helper function to say whether a mode supports PRE_MODIFY. */
546 mode_supports_pre_modify_p (machine_mode mode)
548 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
552 /* Given that there exists at least one variable that is set (produced)
553 by OUT_INSN and read (consumed) by IN_INSN, return true iff
554 IN_INSN represents one or more memory store operations and none of
555 the variables set by OUT_INSN is used by IN_INSN as the address of a
556 store operation. If either IN_INSN or OUT_INSN does not represent
557 a "single" RTL SET expression (as loosely defined by the
558 implementation of the single_set function) or a PARALLEL with only
559 SETs, CLOBBERs, and USEs inside, this function returns false.
561 This rs6000-specific version of store_data_bypass_p checks for
562 certain conditions that result in assertion failures (and internal
563 compiler errors) in the generic store_data_bypass_p function and
564 returns false rather than calling store_data_bypass_p if one of the
565 problematic conditions is detected. */
568 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
575 in_set = single_set (in_insn);
578 if (MEM_P (SET_DEST (in_set)))
580 out_set = single_set (out_insn);
583 out_pat = PATTERN (out_insn);
584 if (GET_CODE (out_pat) == PARALLEL)
586 for (i = 0; i < XVECLEN (out_pat, 0); i++)
588 out_exp = XVECEXP (out_pat, 0, i);
589 if ((GET_CODE (out_exp) == CLOBBER)
590 || (GET_CODE (out_exp) == USE))
592 else if (GET_CODE (out_exp) != SET)
601 in_pat = PATTERN (in_insn);
602 if (GET_CODE (in_pat) != PARALLEL)
605 for (i = 0; i < XVECLEN (in_pat, 0); i++)
607 in_exp = XVECEXP (in_pat, 0, i);
608 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
610 else if (GET_CODE (in_exp) != SET)
613 if (MEM_P (SET_DEST (in_exp)))
615 out_set = single_set (out_insn);
618 out_pat = PATTERN (out_insn);
619 if (GET_CODE (out_pat) != PARALLEL)
621 for (j = 0; j < XVECLEN (out_pat, 0); j++)
623 out_exp = XVECEXP (out_pat, 0, j);
624 if ((GET_CODE (out_exp) == CLOBBER)
625 || (GET_CODE (out_exp) == USE))
627 else if (GET_CODE (out_exp) != SET)
634 return store_data_bypass_p (out_insn, in_insn);
637 /* Return true if we have D-form addressing in altivec registers. */
639 mode_supports_vmx_dform (machine_mode mode)
641 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
644 /* Return true if we have D-form addressing in VSX registers. This addressing
645 is more limited than normal d-form addressing in that the offset must be
646 aligned on a 16-byte boundary. */
648 mode_supports_vsx_dform_quad (machine_mode mode)
650 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
655 /* Processor costs (relative to an add) */
657 const struct processor_costs *rs6000_cost;
659 /* Instruction size costs on 32bit processors. */
661 struct processor_costs size32_cost = {
662 COSTS_N_INSNS (1), /* mulsi */
663 COSTS_N_INSNS (1), /* mulsi_const */
664 COSTS_N_INSNS (1), /* mulsi_const9 */
665 COSTS_N_INSNS (1), /* muldi */
666 COSTS_N_INSNS (1), /* divsi */
667 COSTS_N_INSNS (1), /* divdi */
668 COSTS_N_INSNS (1), /* fp */
669 COSTS_N_INSNS (1), /* dmul */
670 COSTS_N_INSNS (1), /* sdiv */
671 COSTS_N_INSNS (1), /* ddiv */
672 32, /* cache line size */
676 0, /* SF->DF convert */
679 /* Instruction size costs on 64bit processors. */
681 struct processor_costs size64_cost = {
682 COSTS_N_INSNS (1), /* mulsi */
683 COSTS_N_INSNS (1), /* mulsi_const */
684 COSTS_N_INSNS (1), /* mulsi_const9 */
685 COSTS_N_INSNS (1), /* muldi */
686 COSTS_N_INSNS (1), /* divsi */
687 COSTS_N_INSNS (1), /* divdi */
688 COSTS_N_INSNS (1), /* fp */
689 COSTS_N_INSNS (1), /* dmul */
690 COSTS_N_INSNS (1), /* sdiv */
691 COSTS_N_INSNS (1), /* ddiv */
692 128, /* cache line size */
696 0, /* SF->DF convert */
699 /* Instruction costs on RS64A processors. */
701 struct processor_costs rs64a_cost = {
702 COSTS_N_INSNS (20), /* mulsi */
703 COSTS_N_INSNS (12), /* mulsi_const */
704 COSTS_N_INSNS (8), /* mulsi_const9 */
705 COSTS_N_INSNS (34), /* muldi */
706 COSTS_N_INSNS (65), /* divsi */
707 COSTS_N_INSNS (67), /* divdi */
708 COSTS_N_INSNS (4), /* fp */
709 COSTS_N_INSNS (4), /* dmul */
710 COSTS_N_INSNS (31), /* sdiv */
711 COSTS_N_INSNS (31), /* ddiv */
712 128, /* cache line size */
716 0, /* SF->DF convert */
719 /* Instruction costs on MPCCORE processors. */
721 struct processor_costs mpccore_cost = {
722 COSTS_N_INSNS (2), /* mulsi */
723 COSTS_N_INSNS (2), /* mulsi_const */
724 COSTS_N_INSNS (2), /* mulsi_const9 */
725 COSTS_N_INSNS (2), /* muldi */
726 COSTS_N_INSNS (6), /* divsi */
727 COSTS_N_INSNS (6), /* divdi */
728 COSTS_N_INSNS (4), /* fp */
729 COSTS_N_INSNS (5), /* dmul */
730 COSTS_N_INSNS (10), /* sdiv */
731 COSTS_N_INSNS (17), /* ddiv */
732 32, /* cache line size */
736 0, /* SF->DF convert */
739 /* Instruction costs on PPC403 processors. */
741 struct processor_costs ppc403_cost = {
742 COSTS_N_INSNS (4), /* mulsi */
743 COSTS_N_INSNS (4), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (4), /* muldi */
746 COSTS_N_INSNS (33), /* divsi */
747 COSTS_N_INSNS (33), /* divdi */
748 COSTS_N_INSNS (11), /* fp */
749 COSTS_N_INSNS (11), /* dmul */
750 COSTS_N_INSNS (11), /* sdiv */
751 COSTS_N_INSNS (11), /* ddiv */
752 32, /* cache line size */
756 0, /* SF->DF convert */
759 /* Instruction costs on PPC405 processors. */
761 struct processor_costs ppc405_cost = {
762 COSTS_N_INSNS (5), /* mulsi */
763 COSTS_N_INSNS (4), /* mulsi_const */
764 COSTS_N_INSNS (3), /* mulsi_const9 */
765 COSTS_N_INSNS (5), /* muldi */
766 COSTS_N_INSNS (35), /* divsi */
767 COSTS_N_INSNS (35), /* divdi */
768 COSTS_N_INSNS (11), /* fp */
769 COSTS_N_INSNS (11), /* dmul */
770 COSTS_N_INSNS (11), /* sdiv */
771 COSTS_N_INSNS (11), /* ddiv */
772 32, /* cache line size */
776 0, /* SF->DF convert */
779 /* Instruction costs on PPC440 processors. */
781 struct processor_costs ppc440_cost = {
782 COSTS_N_INSNS (3), /* mulsi */
783 COSTS_N_INSNS (2), /* mulsi_const */
784 COSTS_N_INSNS (2), /* mulsi_const9 */
785 COSTS_N_INSNS (3), /* muldi */
786 COSTS_N_INSNS (34), /* divsi */
787 COSTS_N_INSNS (34), /* divdi */
788 COSTS_N_INSNS (5), /* fp */
789 COSTS_N_INSNS (5), /* dmul */
790 COSTS_N_INSNS (19), /* sdiv */
791 COSTS_N_INSNS (33), /* ddiv */
792 32, /* cache line size */
796 0, /* SF->DF convert */
799 /* Instruction costs on PPC476 processors. */
801 struct processor_costs ppc476_cost = {
802 COSTS_N_INSNS (4), /* mulsi */
803 COSTS_N_INSNS (4), /* mulsi_const */
804 COSTS_N_INSNS (4), /* mulsi_const9 */
805 COSTS_N_INSNS (4), /* muldi */
806 COSTS_N_INSNS (11), /* divsi */
807 COSTS_N_INSNS (11), /* divdi */
808 COSTS_N_INSNS (6), /* fp */
809 COSTS_N_INSNS (6), /* dmul */
810 COSTS_N_INSNS (19), /* sdiv */
811 COSTS_N_INSNS (33), /* ddiv */
812 32, /* l1 cache line size */
816 0, /* SF->DF convert */
819 /* Instruction costs on PPC601 processors. */
821 struct processor_costs ppc601_cost = {
822 COSTS_N_INSNS (5), /* mulsi */
823 COSTS_N_INSNS (5), /* mulsi_const */
824 COSTS_N_INSNS (5), /* mulsi_const9 */
825 COSTS_N_INSNS (5), /* muldi */
826 COSTS_N_INSNS (36), /* divsi */
827 COSTS_N_INSNS (36), /* divdi */
828 COSTS_N_INSNS (4), /* fp */
829 COSTS_N_INSNS (5), /* dmul */
830 COSTS_N_INSNS (17), /* sdiv */
831 COSTS_N_INSNS (31), /* ddiv */
832 32, /* cache line size */
836 0, /* SF->DF convert */
839 /* Instruction costs on PPC603 processors. */
841 struct processor_costs ppc603_cost = {
842 COSTS_N_INSNS (5), /* mulsi */
843 COSTS_N_INSNS (3), /* mulsi_const */
844 COSTS_N_INSNS (2), /* mulsi_const9 */
845 COSTS_N_INSNS (5), /* muldi */
846 COSTS_N_INSNS (37), /* divsi */
847 COSTS_N_INSNS (37), /* divdi */
848 COSTS_N_INSNS (3), /* fp */
849 COSTS_N_INSNS (4), /* dmul */
850 COSTS_N_INSNS (18), /* sdiv */
851 COSTS_N_INSNS (33), /* ddiv */
852 32, /* cache line size */
856 0, /* SF->DF convert */
859 /* Instruction costs on PPC604 processors. */
861 struct processor_costs ppc604_cost = {
862 COSTS_N_INSNS (4), /* mulsi */
863 COSTS_N_INSNS (4), /* mulsi_const */
864 COSTS_N_INSNS (4), /* mulsi_const9 */
865 COSTS_N_INSNS (4), /* muldi */
866 COSTS_N_INSNS (20), /* divsi */
867 COSTS_N_INSNS (20), /* divdi */
868 COSTS_N_INSNS (3), /* fp */
869 COSTS_N_INSNS (3), /* dmul */
870 COSTS_N_INSNS (18), /* sdiv */
871 COSTS_N_INSNS (32), /* ddiv */
872 32, /* cache line size */
876 0, /* SF->DF convert */
879 /* Instruction costs on PPC604e processors. */
881 struct processor_costs ppc604e_cost = {
882 COSTS_N_INSNS (2), /* mulsi */
883 COSTS_N_INSNS (2), /* mulsi_const */
884 COSTS_N_INSNS (2), /* mulsi_const9 */
885 COSTS_N_INSNS (2), /* muldi */
886 COSTS_N_INSNS (20), /* divsi */
887 COSTS_N_INSNS (20), /* divdi */
888 COSTS_N_INSNS (3), /* fp */
889 COSTS_N_INSNS (3), /* dmul */
890 COSTS_N_INSNS (18), /* sdiv */
891 COSTS_N_INSNS (32), /* ddiv */
892 32, /* cache line size */
896 0, /* SF->DF convert */
899 /* Instruction costs on PPC620 processors. */
901 struct processor_costs ppc620_cost = {
902 COSTS_N_INSNS (5), /* mulsi */
903 COSTS_N_INSNS (4), /* mulsi_const */
904 COSTS_N_INSNS (3), /* mulsi_const9 */
905 COSTS_N_INSNS (7), /* muldi */
906 COSTS_N_INSNS (21), /* divsi */
907 COSTS_N_INSNS (37), /* divdi */
908 COSTS_N_INSNS (3), /* fp */
909 COSTS_N_INSNS (3), /* dmul */
910 COSTS_N_INSNS (18), /* sdiv */
911 COSTS_N_INSNS (32), /* ddiv */
912 128, /* cache line size */
916 0, /* SF->DF convert */
919 /* Instruction costs on PPC630 processors. */
921 struct processor_costs ppc630_cost = {
922 COSTS_N_INSNS (5), /* mulsi */
923 COSTS_N_INSNS (4), /* mulsi_const */
924 COSTS_N_INSNS (3), /* mulsi_const9 */
925 COSTS_N_INSNS (7), /* muldi */
926 COSTS_N_INSNS (21), /* divsi */
927 COSTS_N_INSNS (37), /* divdi */
928 COSTS_N_INSNS (3), /* fp */
929 COSTS_N_INSNS (3), /* dmul */
930 COSTS_N_INSNS (17), /* sdiv */
931 COSTS_N_INSNS (21), /* ddiv */
932 128, /* cache line size */
936 0, /* SF->DF convert */
939 /* Instruction costs on Cell processor. */
940 /* COSTS_N_INSNS (1) ~ one add. */
942 struct processor_costs ppccell_cost = {
943 COSTS_N_INSNS (9/2)+2, /* mulsi */
944 COSTS_N_INSNS (6/2), /* mulsi_const */
945 COSTS_N_INSNS (6/2), /* mulsi_const9 */
946 COSTS_N_INSNS (15/2)+2, /* muldi */
947 COSTS_N_INSNS (38/2), /* divsi */
948 COSTS_N_INSNS (70/2), /* divdi */
949 COSTS_N_INSNS (10/2), /* fp */
950 COSTS_N_INSNS (10/2), /* dmul */
951 COSTS_N_INSNS (74/2), /* sdiv */
952 COSTS_N_INSNS (74/2), /* ddiv */
953 128, /* cache line size */
957 0, /* SF->DF convert */
960 /* Instruction costs on PPC750 and PPC7400 processors. */
962 struct processor_costs ppc750_cost = {
963 COSTS_N_INSNS (5), /* mulsi */
964 COSTS_N_INSNS (3), /* mulsi_const */
965 COSTS_N_INSNS (2), /* mulsi_const9 */
966 COSTS_N_INSNS (5), /* muldi */
967 COSTS_N_INSNS (17), /* divsi */
968 COSTS_N_INSNS (17), /* divdi */
969 COSTS_N_INSNS (3), /* fp */
970 COSTS_N_INSNS (3), /* dmul */
971 COSTS_N_INSNS (17), /* sdiv */
972 COSTS_N_INSNS (31), /* ddiv */
973 32, /* cache line size */
977 0, /* SF->DF convert */
980 /* Instruction costs on PPC7450 processors. */
982 struct processor_costs ppc7450_cost = {
983 COSTS_N_INSNS (4), /* mulsi */
984 COSTS_N_INSNS (3), /* mulsi_const */
985 COSTS_N_INSNS (3), /* mulsi_const9 */
986 COSTS_N_INSNS (4), /* muldi */
987 COSTS_N_INSNS (23), /* divsi */
988 COSTS_N_INSNS (23), /* divdi */
989 COSTS_N_INSNS (5), /* fp */
990 COSTS_N_INSNS (5), /* dmul */
991 COSTS_N_INSNS (21), /* sdiv */
992 COSTS_N_INSNS (35), /* ddiv */
993 32, /* cache line size */
997 0, /* SF->DF convert */
1000 /* Instruction costs on PPC8540 processors. */
1002 struct processor_costs ppc8540_cost = {
1003 COSTS_N_INSNS (4), /* mulsi */
1004 COSTS_N_INSNS (4), /* mulsi_const */
1005 COSTS_N_INSNS (4), /* mulsi_const9 */
1006 COSTS_N_INSNS (4), /* muldi */
1007 COSTS_N_INSNS (19), /* divsi */
1008 COSTS_N_INSNS (19), /* divdi */
1009 COSTS_N_INSNS (4), /* fp */
1010 COSTS_N_INSNS (4), /* dmul */
1011 COSTS_N_INSNS (29), /* sdiv */
1012 COSTS_N_INSNS (29), /* ddiv */
1013 32, /* cache line size */
1016 1, /* prefetch streams /*/
1017 0, /* SF->DF convert */
1020 /* Instruction costs on E300C2 and E300C3 cores. */
1022 struct processor_costs ppce300c2c3_cost = {
1023 COSTS_N_INSNS (4), /* mulsi */
1024 COSTS_N_INSNS (4), /* mulsi_const */
1025 COSTS_N_INSNS (4), /* mulsi_const9 */
1026 COSTS_N_INSNS (4), /* muldi */
1027 COSTS_N_INSNS (19), /* divsi */
1028 COSTS_N_INSNS (19), /* divdi */
1029 COSTS_N_INSNS (3), /* fp */
1030 COSTS_N_INSNS (4), /* dmul */
1031 COSTS_N_INSNS (18), /* sdiv */
1032 COSTS_N_INSNS (33), /* ddiv */
1036 1, /* prefetch streams /*/
1037 0, /* SF->DF convert */
1040 /* Instruction costs on PPCE500MC processors. */
1042 struct processor_costs ppce500mc_cost = {
1043 COSTS_N_INSNS (4), /* mulsi */
1044 COSTS_N_INSNS (4), /* mulsi_const */
1045 COSTS_N_INSNS (4), /* mulsi_const9 */
1046 COSTS_N_INSNS (4), /* muldi */
1047 COSTS_N_INSNS (14), /* divsi */
1048 COSTS_N_INSNS (14), /* divdi */
1049 COSTS_N_INSNS (8), /* fp */
1050 COSTS_N_INSNS (10), /* dmul */
1051 COSTS_N_INSNS (36), /* sdiv */
1052 COSTS_N_INSNS (66), /* ddiv */
1053 64, /* cache line size */
1056 1, /* prefetch streams /*/
1057 0, /* SF->DF convert */
1060 /* Instruction costs on PPCE500MC64 processors. */
1062 struct processor_costs ppce500mc64_cost = {
1063 COSTS_N_INSNS (4), /* mulsi */
1064 COSTS_N_INSNS (4), /* mulsi_const */
1065 COSTS_N_INSNS (4), /* mulsi_const9 */
1066 COSTS_N_INSNS (4), /* muldi */
1067 COSTS_N_INSNS (14), /* divsi */
1068 COSTS_N_INSNS (14), /* divdi */
1069 COSTS_N_INSNS (4), /* fp */
1070 COSTS_N_INSNS (10), /* dmul */
1071 COSTS_N_INSNS (36), /* sdiv */
1072 COSTS_N_INSNS (66), /* ddiv */
1073 64, /* cache line size */
1076 1, /* prefetch streams /*/
1077 0, /* SF->DF convert */
1080 /* Instruction costs on PPCE5500 processors. */
1082 struct processor_costs ppce5500_cost = {
1083 COSTS_N_INSNS (5), /* mulsi */
1084 COSTS_N_INSNS (5), /* mulsi_const */
1085 COSTS_N_INSNS (4), /* mulsi_const9 */
1086 COSTS_N_INSNS (5), /* muldi */
1087 COSTS_N_INSNS (14), /* divsi */
1088 COSTS_N_INSNS (14), /* divdi */
1089 COSTS_N_INSNS (7), /* fp */
1090 COSTS_N_INSNS (10), /* dmul */
1091 COSTS_N_INSNS (36), /* sdiv */
1092 COSTS_N_INSNS (66), /* ddiv */
1093 64, /* cache line size */
1096 1, /* prefetch streams /*/
1097 0, /* SF->DF convert */
1100 /* Instruction costs on PPCE6500 processors. */
1102 struct processor_costs ppce6500_cost = {
1103 COSTS_N_INSNS (5), /* mulsi */
1104 COSTS_N_INSNS (5), /* mulsi_const */
1105 COSTS_N_INSNS (4), /* mulsi_const9 */
1106 COSTS_N_INSNS (5), /* muldi */
1107 COSTS_N_INSNS (14), /* divsi */
1108 COSTS_N_INSNS (14), /* divdi */
1109 COSTS_N_INSNS (7), /* fp */
1110 COSTS_N_INSNS (10), /* dmul */
1111 COSTS_N_INSNS (36), /* sdiv */
1112 COSTS_N_INSNS (66), /* ddiv */
1113 64, /* cache line size */
1116 1, /* prefetch streams /*/
1117 0, /* SF->DF convert */
1120 /* Instruction costs on AppliedMicro Titan processors. */
1122 struct processor_costs titan_cost = {
1123 COSTS_N_INSNS (5), /* mulsi */
1124 COSTS_N_INSNS (5), /* mulsi_const */
1125 COSTS_N_INSNS (5), /* mulsi_const9 */
1126 COSTS_N_INSNS (5), /* muldi */
1127 COSTS_N_INSNS (18), /* divsi */
1128 COSTS_N_INSNS (18), /* divdi */
1129 COSTS_N_INSNS (10), /* fp */
1130 COSTS_N_INSNS (10), /* dmul */
1131 COSTS_N_INSNS (46), /* sdiv */
1132 COSTS_N_INSNS (72), /* ddiv */
1133 32, /* cache line size */
1136 1, /* prefetch streams /*/
1137 0, /* SF->DF convert */
1140 /* Instruction costs on POWER4 and POWER5 processors. */
1142 struct processor_costs power4_cost = {
1143 COSTS_N_INSNS (3), /* mulsi */
1144 COSTS_N_INSNS (2), /* mulsi_const */
1145 COSTS_N_INSNS (2), /* mulsi_const9 */
1146 COSTS_N_INSNS (4), /* muldi */
1147 COSTS_N_INSNS (18), /* divsi */
1148 COSTS_N_INSNS (34), /* divdi */
1149 COSTS_N_INSNS (3), /* fp */
1150 COSTS_N_INSNS (3), /* dmul */
1151 COSTS_N_INSNS (17), /* sdiv */
1152 COSTS_N_INSNS (17), /* ddiv */
1153 128, /* cache line size */
1155 1024, /* l2 cache */
1156 8, /* prefetch streams /*/
1157 0, /* SF->DF convert */
1160 /* Instruction costs on POWER6 processors. */
1162 struct processor_costs power6_cost = {
1163 COSTS_N_INSNS (8), /* mulsi */
1164 COSTS_N_INSNS (8), /* mulsi_const */
1165 COSTS_N_INSNS (8), /* mulsi_const9 */
1166 COSTS_N_INSNS (8), /* muldi */
1167 COSTS_N_INSNS (22), /* divsi */
1168 COSTS_N_INSNS (28), /* divdi */
1169 COSTS_N_INSNS (3), /* fp */
1170 COSTS_N_INSNS (3), /* dmul */
1171 COSTS_N_INSNS (13), /* sdiv */
1172 COSTS_N_INSNS (16), /* ddiv */
1173 128, /* cache line size */
1175 2048, /* l2 cache */
1176 16, /* prefetch streams */
1177 0, /* SF->DF convert */
1180 /* Instruction costs on POWER7 processors. */
1182 struct processor_costs power7_cost = {
1183 COSTS_N_INSNS (2), /* mulsi */
1184 COSTS_N_INSNS (2), /* mulsi_const */
1185 COSTS_N_INSNS (2), /* mulsi_const9 */
1186 COSTS_N_INSNS (2), /* muldi */
1187 COSTS_N_INSNS (18), /* divsi */
1188 COSTS_N_INSNS (34), /* divdi */
1189 COSTS_N_INSNS (3), /* fp */
1190 COSTS_N_INSNS (3), /* dmul */
1191 COSTS_N_INSNS (13), /* sdiv */
1192 COSTS_N_INSNS (16), /* ddiv */
1193 128, /* cache line size */
1196 12, /* prefetch streams */
1197 COSTS_N_INSNS (3), /* SF->DF convert */
1200 /* Instruction costs on POWER8 processors. */
1202 struct processor_costs power8_cost = {
1203 COSTS_N_INSNS (3), /* mulsi */
1204 COSTS_N_INSNS (3), /* mulsi_const */
1205 COSTS_N_INSNS (3), /* mulsi_const9 */
1206 COSTS_N_INSNS (3), /* muldi */
1207 COSTS_N_INSNS (19), /* divsi */
1208 COSTS_N_INSNS (35), /* divdi */
1209 COSTS_N_INSNS (3), /* fp */
1210 COSTS_N_INSNS (3), /* dmul */
1211 COSTS_N_INSNS (14), /* sdiv */
1212 COSTS_N_INSNS (17), /* ddiv */
1213 128, /* cache line size */
1216 12, /* prefetch streams */
1217 COSTS_N_INSNS (3), /* SF->DF convert */
1220 /* Instruction costs on POWER9 processors. */
1222 struct processor_costs power9_cost = {
1223 COSTS_N_INSNS (3), /* mulsi */
1224 COSTS_N_INSNS (3), /* mulsi_const */
1225 COSTS_N_INSNS (3), /* mulsi_const9 */
1226 COSTS_N_INSNS (3), /* muldi */
1227 COSTS_N_INSNS (8), /* divsi */
1228 COSTS_N_INSNS (12), /* divdi */
1229 COSTS_N_INSNS (3), /* fp */
1230 COSTS_N_INSNS (3), /* dmul */
1231 COSTS_N_INSNS (13), /* sdiv */
1232 COSTS_N_INSNS (18), /* ddiv */
1233 128, /* cache line size */
1236 8, /* prefetch streams */
1237 COSTS_N_INSNS (3), /* SF->DF convert */
1240 /* Instruction costs on POWER A2 processors. */
1242 struct processor_costs ppca2_cost = {
1243 COSTS_N_INSNS (16), /* mulsi */
1244 COSTS_N_INSNS (16), /* mulsi_const */
1245 COSTS_N_INSNS (16), /* mulsi_const9 */
1246 COSTS_N_INSNS (16), /* muldi */
1247 COSTS_N_INSNS (22), /* divsi */
1248 COSTS_N_INSNS (28), /* divdi */
1249 COSTS_N_INSNS (3), /* fp */
1250 COSTS_N_INSNS (3), /* dmul */
1251 COSTS_N_INSNS (59), /* sdiv */
1252 COSTS_N_INSNS (72), /* ddiv */
1255 2048, /* l2 cache */
1256 16, /* prefetch streams */
1257 0, /* SF->DF convert */
1261 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1262 #undef RS6000_BUILTIN_0
1263 #undef RS6000_BUILTIN_1
1264 #undef RS6000_BUILTIN_2
1265 #undef RS6000_BUILTIN_3
1266 #undef RS6000_BUILTIN_A
1267 #undef RS6000_BUILTIN_D
1268 #undef RS6000_BUILTIN_H
1269 #undef RS6000_BUILTIN_P
1270 #undef RS6000_BUILTIN_Q
1271 #undef RS6000_BUILTIN_X
1273 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1274 { NAME, ICODE, MASK, ATTR },
1276 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 struct rs6000_builtin_info_type {
1305 const enum insn_code icode;
1306 const HOST_WIDE_INT mask;
1307 const unsigned attr;
1310 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1312 #include "rs6000-builtin.def"
1315 #undef RS6000_BUILTIN_0
1316 #undef RS6000_BUILTIN_1
1317 #undef RS6000_BUILTIN_2
1318 #undef RS6000_BUILTIN_3
1319 #undef RS6000_BUILTIN_A
1320 #undef RS6000_BUILTIN_D
1321 #undef RS6000_BUILTIN_H
1322 #undef RS6000_BUILTIN_P
1323 #undef RS6000_BUILTIN_Q
1324 #undef RS6000_BUILTIN_X
1326 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1327 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1330 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1331 static struct machine_function * rs6000_init_machine_status (void);
1332 static int rs6000_ra_ever_killed (void);
1333 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1334 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1337 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1338 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1339 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1340 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1342 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1344 static bool is_microcoded_insn (rtx_insn *);
1345 static bool is_nonpipeline_insn (rtx_insn *);
1346 static bool is_cracked_insn (rtx_insn *);
1347 static bool is_load_insn (rtx, rtx *);
1348 static bool is_store_insn (rtx, rtx *);
1349 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1350 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1351 static bool insn_must_be_first_in_group (rtx_insn *);
1352 static bool insn_must_be_last_in_group (rtx_insn *);
1353 static void altivec_init_builtins (void);
1354 static tree builtin_function_type (machine_mode, machine_mode,
1355 machine_mode, machine_mode,
1356 enum rs6000_builtins, const char *name);
1357 static void rs6000_common_init_builtins (void);
1358 static void paired_init_builtins (void);
1359 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1360 static void htm_init_builtins (void);
1361 static rs6000_stack_t *rs6000_stack_info (void);
1362 static void is_altivec_return_reg (rtx, void *);
1363 int easy_vector_constant (rtx, machine_mode);
1364 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1365 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1366 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1369 static void macho_branch_islands (void);
1371 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1373 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1375 static bool rs6000_mode_dependent_address (const_rtx);
1376 static bool rs6000_debug_mode_dependent_address (const_rtx);
1377 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1382 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1383 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1385 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1388 static bool rs6000_debug_can_change_mode_class (machine_mode,
1391 static bool rs6000_save_toc_in_prologue_p (void);
1392 static rtx rs6000_internal_arg_pointer (void);
1394 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1396 = rs6000_legitimize_reload_address;
1398 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1399 = rs6000_mode_dependent_address;
1401 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1403 = rs6000_secondary_reload_class;
1405 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1406 = rs6000_preferred_reload_class;
1408 const int INSN_NOT_AVAILABLE = -1;
1410 static void rs6000_print_isa_options (FILE *, int, const char *,
1412 static void rs6000_print_builtin_options (FILE *, int, const char *,
1414 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1416 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1417 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1418 enum rs6000_reg_type,
1420 secondary_reload_info *,
1422 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1423 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1424 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1426 /* Hash table stuff for keeping track of TOC entries. */
1428 struct GTY((for_user)) toc_hash_struct
1430 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1431 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1433 machine_mode key_mode;
1437 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1439 static hashval_t hash (toc_hash_struct *);
1440 static bool equal (toc_hash_struct *, toc_hash_struct *);
1443 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1445 /* Hash table to keep track of the argument types for builtin functions. */
1447 struct GTY((for_user)) builtin_hash_struct
1450 machine_mode mode[4]; /* return value + 3 arguments. */
1451 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1454 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1456 static hashval_t hash (builtin_hash_struct *);
1457 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1460 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1463 /* Default register names. */
1464 char rs6000_reg_names[][8] =
1466 "0", "1", "2", "3", "4", "5", "6", "7",
1467 "8", "9", "10", "11", "12", "13", "14", "15",
1468 "16", "17", "18", "19", "20", "21", "22", "23",
1469 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1474 "mq", "lr", "ctr","ap",
1475 "0", "1", "2", "3", "4", "5", "6", "7",
1477 /* AltiVec registers. */
1478 "0", "1", "2", "3", "4", "5", "6", "7",
1479 "8", "9", "10", "11", "12", "13", "14", "15",
1480 "16", "17", "18", "19", "20", "21", "22", "23",
1481 "24", "25", "26", "27", "28", "29", "30", "31",
1483 /* Soft frame pointer. */
1485 /* HTM SPR registers. */
1486 "tfhar", "tfiar", "texasr"
1489 #ifdef TARGET_REGNAMES
1490 static const char alt_reg_names[][8] =
1492 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1493 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1494 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1495 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1496 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1497 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1498 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1499 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1500 "mq", "lr", "ctr", "ap",
1501 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1503 /* AltiVec registers. */
1504 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1505 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1506 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1507 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1509 /* Soft frame pointer. */
1511 /* HTM SPR registers. */
1512 "tfhar", "tfiar", "texasr"
1516 /* Table of valid machine attributes. */
1518 static const struct attribute_spec rs6000_attribute_table[] =
1520 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1521 affects_type_identity } */
1522 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1524 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1526 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1528 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1530 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1532 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1533 SUBTARGET_ATTRIBUTE_TABLE,
1535 { NULL, 0, 0, false, false, false, NULL, false }
1538 #ifndef TARGET_PROFILE_KERNEL
1539 #define TARGET_PROFILE_KERNEL 0
1542 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1543 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1545 /* Initialize the GCC target structure. */
1546 #undef TARGET_ATTRIBUTE_TABLE
1547 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1548 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1549 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1550 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1551 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1553 #undef TARGET_ASM_ALIGNED_DI_OP
1554 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1556 /* Default unaligned ops are only provided for ELF. Find the ops needed
1557 for non-ELF systems. */
1558 #ifndef OBJECT_FORMAT_ELF
1560 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1562 #undef TARGET_ASM_UNALIGNED_HI_OP
1563 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1564 #undef TARGET_ASM_UNALIGNED_SI_OP
1565 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1566 #undef TARGET_ASM_UNALIGNED_DI_OP
1567 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1570 #undef TARGET_ASM_UNALIGNED_HI_OP
1571 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1572 #undef TARGET_ASM_UNALIGNED_SI_OP
1573 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1574 #undef TARGET_ASM_UNALIGNED_DI_OP
1575 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1576 #undef TARGET_ASM_ALIGNED_DI_OP
1577 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1581 /* This hook deals with fixups for relocatable code and DI-mode objects
1583 #undef TARGET_ASM_INTEGER
1584 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1586 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1587 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1588 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1591 #undef TARGET_SET_UP_BY_PROLOGUE
1592 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1594 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1595 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1596 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1597 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1598 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1600 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1601 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1602 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1604 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1605 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1607 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1608 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1610 #undef TARGET_INTERNAL_ARG_POINTER
1611 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1613 #undef TARGET_HAVE_TLS
1614 #define TARGET_HAVE_TLS HAVE_AS_TLS
1616 #undef TARGET_CANNOT_FORCE_CONST_MEM
1617 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1619 #undef TARGET_DELEGITIMIZE_ADDRESS
1620 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1622 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1623 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1625 #undef TARGET_LEGITIMATE_COMBINED_INSN
1626 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1628 #undef TARGET_ASM_FUNCTION_PROLOGUE
1629 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1630 #undef TARGET_ASM_FUNCTION_EPILOGUE
1631 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1633 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1634 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1636 #undef TARGET_LEGITIMIZE_ADDRESS
1637 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1639 #undef TARGET_SCHED_VARIABLE_ISSUE
1640 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1642 #undef TARGET_SCHED_ISSUE_RATE
1643 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1644 #undef TARGET_SCHED_ADJUST_COST
1645 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1646 #undef TARGET_SCHED_ADJUST_PRIORITY
1647 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1648 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1649 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1650 #undef TARGET_SCHED_INIT
1651 #define TARGET_SCHED_INIT rs6000_sched_init
1652 #undef TARGET_SCHED_FINISH
1653 #define TARGET_SCHED_FINISH rs6000_sched_finish
1654 #undef TARGET_SCHED_REORDER
1655 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1656 #undef TARGET_SCHED_REORDER2
1657 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1659 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1660 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1662 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1663 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1665 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1666 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1667 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1668 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1669 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1670 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1671 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1672 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1674 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1675 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1677 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1678 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1679 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1680 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1681 rs6000_builtin_support_vector_misalignment
1682 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1683 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1684 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1685 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1686 rs6000_builtin_vectorization_cost
1687 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1688 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1689 rs6000_preferred_simd_mode
1690 #undef TARGET_VECTORIZE_INIT_COST
1691 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1692 #undef TARGET_VECTORIZE_ADD_STMT_COST
1693 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1694 #undef TARGET_VECTORIZE_FINISH_COST
1695 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1696 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1697 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1699 #undef TARGET_INIT_BUILTINS
1700 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1701 #undef TARGET_BUILTIN_DECL
1702 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1704 #undef TARGET_FOLD_BUILTIN
1705 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1706 #undef TARGET_GIMPLE_FOLD_BUILTIN
1707 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1709 #undef TARGET_EXPAND_BUILTIN
1710 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1712 #undef TARGET_MANGLE_TYPE
1713 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1715 #undef TARGET_INIT_LIBFUNCS
1716 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1719 #undef TARGET_BINDS_LOCAL_P
1720 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1723 #undef TARGET_MS_BITFIELD_LAYOUT_P
1724 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1726 #undef TARGET_ASM_OUTPUT_MI_THUNK
1727 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1729 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1730 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1732 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1733 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1735 #undef TARGET_REGISTER_MOVE_COST
1736 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1737 #undef TARGET_MEMORY_MOVE_COST
1738 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1739 #undef TARGET_CANNOT_COPY_INSN_P
1740 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1741 #undef TARGET_RTX_COSTS
1742 #define TARGET_RTX_COSTS rs6000_rtx_costs
1743 #undef TARGET_ADDRESS_COST
1744 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1745 #undef TARGET_INSN_COST
1746 #define TARGET_INSN_COST rs6000_insn_cost
1748 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1749 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1751 #undef TARGET_PROMOTE_FUNCTION_MODE
1752 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1754 #undef TARGET_RETURN_IN_MEMORY
1755 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1757 #undef TARGET_RETURN_IN_MSB
1758 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1760 #undef TARGET_SETUP_INCOMING_VARARGS
1761 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1763 /* Always strict argument naming on rs6000. */
1764 #undef TARGET_STRICT_ARGUMENT_NAMING
1765 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1766 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1767 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1768 #undef TARGET_SPLIT_COMPLEX_ARG
1769 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1770 #undef TARGET_MUST_PASS_IN_STACK
1771 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1772 #undef TARGET_PASS_BY_REFERENCE
1773 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1774 #undef TARGET_ARG_PARTIAL_BYTES
1775 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1776 #undef TARGET_FUNCTION_ARG_ADVANCE
1777 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1778 #undef TARGET_FUNCTION_ARG
1779 #define TARGET_FUNCTION_ARG rs6000_function_arg
1780 #undef TARGET_FUNCTION_ARG_PADDING
1781 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1782 #undef TARGET_FUNCTION_ARG_BOUNDARY
1783 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1785 #undef TARGET_BUILD_BUILTIN_VA_LIST
1786 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1788 #undef TARGET_EXPAND_BUILTIN_VA_START
1789 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1791 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1792 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1794 #undef TARGET_EH_RETURN_FILTER_MODE
1795 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1797 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1798 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1800 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1801 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1803 #undef TARGET_FLOATN_MODE
1804 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1806 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1807 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1809 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1810 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1812 #undef TARGET_MD_ASM_ADJUST
1813 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1815 #undef TARGET_OPTION_OVERRIDE
1816 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1818 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1820 rs6000_builtin_vectorized_function
1822 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1823 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1824 rs6000_builtin_md_vectorized_function
1826 #undef TARGET_STACK_PROTECT_GUARD
1827 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1830 #undef TARGET_STACK_PROTECT_FAIL
1831 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1835 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1836 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1839 /* Use a 32-bit anchor range. This leads to sequences like:
1841 addis tmp,anchor,high
1844 where tmp itself acts as an anchor, and can be shared between
1845 accesses to the same 64k page. */
1846 #undef TARGET_MIN_ANCHOR_OFFSET
1847 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1848 #undef TARGET_MAX_ANCHOR_OFFSET
1849 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1850 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1851 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1852 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1853 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1855 #undef TARGET_BUILTIN_RECIPROCAL
1856 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1858 #undef TARGET_SECONDARY_RELOAD
1859 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1860 #undef TARGET_SECONDARY_MEMORY_NEEDED
1861 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1862 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1863 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1865 #undef TARGET_LEGITIMATE_ADDRESS_P
1866 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1868 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1869 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1871 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1872 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1874 #undef TARGET_CAN_ELIMINATE
1875 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1877 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1878 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1880 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1881 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1883 #undef TARGET_TRAMPOLINE_INIT
1884 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1886 #undef TARGET_FUNCTION_VALUE
1887 #define TARGET_FUNCTION_VALUE rs6000_function_value
1889 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1890 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1892 #undef TARGET_OPTION_SAVE
1893 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1895 #undef TARGET_OPTION_RESTORE
1896 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1898 #undef TARGET_OPTION_PRINT
1899 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1901 #undef TARGET_CAN_INLINE_P
1902 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1904 #undef TARGET_SET_CURRENT_FUNCTION
1905 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1907 #undef TARGET_LEGITIMATE_CONSTANT_P
1908 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1910 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1911 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1913 #undef TARGET_CAN_USE_DOLOOP_P
1914 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1916 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1917 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1919 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1920 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1921 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1922 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1923 #undef TARGET_UNWIND_WORD_MODE
1924 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1926 #undef TARGET_OFFLOAD_OPTIONS
1927 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1929 #undef TARGET_C_MODE_FOR_SUFFIX
1930 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1932 #undef TARGET_INVALID_BINARY_OP
1933 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1935 #undef TARGET_OPTAB_SUPPORTED_P
1936 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1938 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1939 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1941 #undef TARGET_COMPARE_VERSION_PRIORITY
1942 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1944 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1945 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1946 rs6000_generate_version_dispatcher_body
1948 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1949 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1950 rs6000_get_function_versions_dispatcher
1952 #undef TARGET_OPTION_FUNCTION_VERSIONS
1953 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1955 #undef TARGET_HARD_REGNO_NREGS
1956 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1957 #undef TARGET_HARD_REGNO_MODE_OK
1958 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1960 #undef TARGET_MODES_TIEABLE_P
1961 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1963 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1964 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1965 rs6000_hard_regno_call_part_clobbered
1967 #undef TARGET_SLOW_UNALIGNED_ACCESS
1968 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1970 #undef TARGET_CAN_CHANGE_MODE_CLASS
1971 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1973 #undef TARGET_CONSTANT_ALIGNMENT
1974 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1976 #undef TARGET_STARTING_FRAME_OFFSET
1977 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1980 /* Processor table. */
1983 const char *const name; /* Canonical processor name. */
1984 const enum processor_type processor; /* Processor type enum value. */
1985 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1988 static struct rs6000_ptt const processor_target_table[] =
1990 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1991 #include "rs6000-cpus.def"
1995 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1999 rs6000_cpu_name_lookup (const char *name)
2005 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2006 if (! strcmp (name, processor_target_table[i].name))
2014 /* Return number of consecutive hard regs needed starting at reg REGNO
2015 to hold something of mode MODE.
2016 This is ordinarily the length in words of a value of mode MODE
2017 but can be less for certain modes in special long registers.
2019 POWER and PowerPC GPRs hold 32 bits worth;
2020 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2023 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2025 unsigned HOST_WIDE_INT reg_size;
2027 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2028 128-bit floating point that can go in vector registers, which has VSX
2029 memory addressing. */
2030 if (FP_REGNO_P (regno))
2031 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2032 ? UNITS_PER_VSX_WORD
2033 : UNITS_PER_FP_WORD);
2035 else if (ALTIVEC_REGNO_P (regno))
2036 reg_size = UNITS_PER_ALTIVEC_WORD;
2039 reg_size = UNITS_PER_WORD;
2041 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2044 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2047 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2049 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2051 if (COMPLEX_MODE_P (mode))
2052 mode = GET_MODE_INNER (mode);
2054 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2055 register combinations, and use PTImode where we need to deal with quad
2056 word memory operations. Don't allow quad words in the argument or frame
2057 pointer registers, just registers 0..31. */
2058 if (mode == PTImode)
2059 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2060 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2061 && ((regno & 1) == 0));
2063 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2064 implementations. Don't allow an item to be split between a FP register
2065 and an Altivec register. Allow TImode in all VSX registers if the user
2067 if (TARGET_VSX && VSX_REGNO_P (regno)
2068 && (VECTOR_MEM_VSX_P (mode)
2069 || FLOAT128_VECTOR_P (mode)
2070 || reg_addr[mode].scalar_in_vmx_p
2072 || (TARGET_VADDUQM && mode == V1TImode)))
2074 if (FP_REGNO_P (regno))
2075 return FP_REGNO_P (last_regno);
2077 if (ALTIVEC_REGNO_P (regno))
2079 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2082 return ALTIVEC_REGNO_P (last_regno);
2086 /* The GPRs can hold any mode, but values bigger than one register
2087 cannot go past R31. */
2088 if (INT_REGNO_P (regno))
2089 return INT_REGNO_P (last_regno);
2091 /* The float registers (except for VSX vector modes) can only hold floating
2092 modes and DImode. */
2093 if (FP_REGNO_P (regno))
2095 if (FLOAT128_VECTOR_P (mode))
2098 if (SCALAR_FLOAT_MODE_P (mode)
2099 && (mode != TDmode || (regno % 2) == 0)
2100 && FP_REGNO_P (last_regno))
2103 if (GET_MODE_CLASS (mode) == MODE_INT)
2105 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2108 if (TARGET_P8_VECTOR && (mode == SImode))
2111 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2115 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
2116 && PAIRED_VECTOR_MODE (mode))
2122 /* The CR register can only hold CC modes. */
2123 if (CR_REGNO_P (regno))
2124 return GET_MODE_CLASS (mode) == MODE_CC;
2126 if (CA_REGNO_P (regno))
2127 return mode == Pmode || mode == SImode;
2129 /* AltiVec only in AldyVec registers. */
2130 if (ALTIVEC_REGNO_P (regno))
2131 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2132 || mode == V1TImode);
2134 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2135 and it must be able to fit within the register set. */
2137 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2140 /* Implement TARGET_HARD_REGNO_NREGS. */
2143 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2145 return rs6000_hard_regno_nregs[mode][regno];
2148 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2151 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2153 return rs6000_hard_regno_mode_ok_p[mode][regno];
2156 /* Implement TARGET_MODES_TIEABLE_P.
2158 PTImode cannot tie with other modes because PTImode is restricted to even
2159 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2162 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2163 128-bit floating point on VSX systems ties with other vectors. */
2166 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2168 if (mode1 == PTImode)
2169 return mode2 == PTImode;
2170 if (mode2 == PTImode)
2173 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2174 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2175 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2178 if (SCALAR_FLOAT_MODE_P (mode1))
2179 return SCALAR_FLOAT_MODE_P (mode2);
2180 if (SCALAR_FLOAT_MODE_P (mode2))
2183 if (GET_MODE_CLASS (mode1) == MODE_CC)
2184 return GET_MODE_CLASS (mode2) == MODE_CC;
2185 if (GET_MODE_CLASS (mode2) == MODE_CC)
2188 if (PAIRED_VECTOR_MODE (mode1))
2189 return PAIRED_VECTOR_MODE (mode2);
2190 if (PAIRED_VECTOR_MODE (mode2))
2196 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2199 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2203 && GET_MODE_SIZE (mode) > 4
2204 && INT_REGNO_P (regno))
2208 && FP_REGNO_P (regno)
2209 && GET_MODE_SIZE (mode) > 8
2210 && !FLOAT128_2REG_P (mode))
2216 /* Print interesting facts about registers. */
2218 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2222 for (r = first_regno; r <= last_regno; ++r)
2224 const char *comma = "";
2227 if (first_regno == last_regno)
2228 fprintf (stderr, "%s:\t", reg_name);
2230 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2233 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2234 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2238 fprintf (stderr, ",\n\t");
2243 if (rs6000_hard_regno_nregs[m][r] > 1)
2244 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2245 rs6000_hard_regno_nregs[m][r]);
2247 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2252 if (call_used_regs[r])
2256 fprintf (stderr, ",\n\t");
2261 len += fprintf (stderr, "%s%s", comma, "call-used");
2269 fprintf (stderr, ",\n\t");
2274 len += fprintf (stderr, "%s%s", comma, "fixed");
2280 fprintf (stderr, ",\n\t");
2284 len += fprintf (stderr, "%sreg-class = %s", comma,
2285 reg_class_names[(int)rs6000_regno_regclass[r]]);
2290 fprintf (stderr, ",\n\t");
2294 fprintf (stderr, "%sregno = %d\n", comma, r);
2299 rs6000_debug_vector_unit (enum rs6000_vector v)
2305 case VECTOR_NONE: ret = "none"; break;
2306 case VECTOR_ALTIVEC: ret = "altivec"; break;
2307 case VECTOR_VSX: ret = "vsx"; break;
2308 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2309 case VECTOR_PAIRED: ret = "paired"; break;
2310 case VECTOR_OTHER: ret = "other"; break;
2311 default: ret = "unknown"; break;
2317 /* Inner function printing just the address mask for a particular reload
2319 DEBUG_FUNCTION char *
2320 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2325 if ((mask & RELOAD_REG_VALID) != 0)
2327 else if (keep_spaces)
2330 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2332 else if (keep_spaces)
2335 if ((mask & RELOAD_REG_INDEXED) != 0)
2337 else if (keep_spaces)
2340 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2342 else if ((mask & RELOAD_REG_OFFSET) != 0)
2344 else if (keep_spaces)
2347 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2349 else if (keep_spaces)
2352 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2354 else if (keep_spaces)
2357 if ((mask & RELOAD_REG_AND_M16) != 0)
2359 else if (keep_spaces)
2367 /* Print the address masks in a human readble fashion. */
2369 rs6000_debug_print_mode (ssize_t m)
2375 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2376 for (rc = 0; rc < N_RELOAD_REG; rc++)
2377 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2378 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2380 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2381 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2382 fprintf (stderr, " Reload=%c%c",
2383 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2384 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2386 spaces += sizeof (" Reload=sl") - 1;
2388 if (reg_addr[m].scalar_in_vmx_p)
2390 fprintf (stderr, "%*s Upper=y", spaces, "");
2394 spaces += sizeof (" Upper=y") - 1;
2396 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2397 || reg_addr[m].fused_toc);
2400 for (rc = 0; rc < N_RELOAD_REG; rc++)
2402 if (rc != RELOAD_REG_ANY)
2404 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2405 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2406 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2407 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2408 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2410 fuse_extra_p = true;
2419 fprintf (stderr, "%*s Fuse:", spaces, "");
2422 for (rc = 0; rc < N_RELOAD_REG; rc++)
2424 if (rc != RELOAD_REG_ANY)
2428 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2430 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2435 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2437 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2442 if (load == '-' && store == '-')
2446 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2447 reload_reg_map[rc].name[0], load, store);
2453 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2455 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2459 spaces += sizeof (" P8gpr") - 1;
2461 if (reg_addr[m].fused_toc)
2463 fprintf (stderr, "%*sToc", (spaces + 1), "");
2467 spaces += sizeof (" Toc") - 1;
2470 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2472 if (rs6000_vector_unit[m] != VECTOR_NONE
2473 || rs6000_vector_mem[m] != VECTOR_NONE)
2475 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2477 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2478 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2481 fputs ("\n", stderr);
2484 #define DEBUG_FMT_ID "%-32s= "
2485 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2486 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2487 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2489 /* Print various interesting information with -mdebug=reg. */
2491 rs6000_debug_reg_global (void)
2493 static const char *const tf[2] = { "false", "true" };
2494 const char *nl = (const char *)0;
2497 char costly_num[20];
2499 char flags_buffer[40];
2500 const char *costly_str;
2501 const char *nop_str;
2502 const char *trace_str;
2503 const char *abi_str;
2504 const char *cmodel_str;
2505 struct cl_target_option cl_opts;
2507 /* Modes we want tieable information on. */
2508 static const machine_mode print_tieable_modes[] = {
2544 /* Virtual regs we are interested in. */
2545 const static struct {
2546 int regno; /* register number. */
2547 const char *name; /* register name. */
2548 } virtual_regs[] = {
2549 { STACK_POINTER_REGNUM, "stack pointer:" },
2550 { TOC_REGNUM, "toc: " },
2551 { STATIC_CHAIN_REGNUM, "static chain: " },
2552 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2553 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2554 { ARG_POINTER_REGNUM, "arg pointer: " },
2555 { FRAME_POINTER_REGNUM, "frame pointer:" },
2556 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2557 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2558 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2559 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2560 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2561 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2562 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2563 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2564 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2567 fputs ("\nHard register information:\n", stderr);
2568 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2569 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2570 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2573 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2574 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2575 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2576 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2577 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2578 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2580 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2581 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2582 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2586 "d reg_class = %s\n"
2587 "f reg_class = %s\n"
2588 "v reg_class = %s\n"
2589 "wa reg_class = %s\n"
2590 "wb reg_class = %s\n"
2591 "wd reg_class = %s\n"
2592 "we reg_class = %s\n"
2593 "wf reg_class = %s\n"
2594 "wg reg_class = %s\n"
2595 "wh reg_class = %s\n"
2596 "wi reg_class = %s\n"
2597 "wj reg_class = %s\n"
2598 "wk reg_class = %s\n"
2599 "wl reg_class = %s\n"
2600 "wm reg_class = %s\n"
2601 "wo reg_class = %s\n"
2602 "wp reg_class = %s\n"
2603 "wq reg_class = %s\n"
2604 "wr reg_class = %s\n"
2605 "ws reg_class = %s\n"
2606 "wt reg_class = %s\n"
2607 "wu reg_class = %s\n"
2608 "wv reg_class = %s\n"
2609 "ww reg_class = %s\n"
2610 "wx reg_class = %s\n"
2611 "wy reg_class = %s\n"
2612 "wz reg_class = %s\n"
2613 "wA reg_class = %s\n"
2614 "wH reg_class = %s\n"
2615 "wI reg_class = %s\n"
2616 "wJ reg_class = %s\n"
2617 "wK reg_class = %s\n"
2619 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2620 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2621 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2622 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2653 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2654 rs6000_debug_print_mode (m);
2656 fputs ("\n", stderr);
2658 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2660 machine_mode mode1 = print_tieable_modes[m1];
2661 bool first_time = true;
2663 nl = (const char *)0;
2664 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2666 machine_mode mode2 = print_tieable_modes[m2];
2667 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2671 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2676 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2681 fputs ("\n", stderr);
2687 if (rs6000_recip_control)
2689 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2691 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2692 if (rs6000_recip_bits[m])
2695 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2697 (RS6000_RECIP_AUTO_RE_P (m)
2699 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2700 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2702 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2705 fputs ("\n", stderr);
2708 if (rs6000_cpu_index >= 0)
2710 const char *name = processor_target_table[rs6000_cpu_index].name;
2712 = processor_target_table[rs6000_cpu_index].target_enable;
2714 sprintf (flags_buffer, "-mcpu=%s flags", name);
2715 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2718 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2720 if (rs6000_tune_index >= 0)
2722 const char *name = processor_target_table[rs6000_tune_index].name;
2724 = processor_target_table[rs6000_tune_index].target_enable;
2726 sprintf (flags_buffer, "-mtune=%s flags", name);
2727 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2730 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2732 cl_target_option_save (&cl_opts, &global_options);
2733 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2736 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2737 rs6000_isa_flags_explicit);
2739 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2740 rs6000_builtin_mask);
2742 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2744 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2745 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2747 switch (rs6000_sched_costly_dep)
2749 case max_dep_latency:
2750 costly_str = "max_dep_latency";
2754 costly_str = "no_dep_costly";
2757 case all_deps_costly:
2758 costly_str = "all_deps_costly";
2761 case true_store_to_load_dep_costly:
2762 costly_str = "true_store_to_load_dep_costly";
2765 case store_to_load_dep_costly:
2766 costly_str = "store_to_load_dep_costly";
2770 costly_str = costly_num;
2771 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2775 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2777 switch (rs6000_sched_insert_nops)
2779 case sched_finish_regroup_exact:
2780 nop_str = "sched_finish_regroup_exact";
2783 case sched_finish_pad_groups:
2784 nop_str = "sched_finish_pad_groups";
2787 case sched_finish_none:
2788 nop_str = "sched_finish_none";
2793 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2797 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2799 switch (rs6000_sdata)
2806 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2810 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2814 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2819 switch (rs6000_traceback)
2821 case traceback_default: trace_str = "default"; break;
2822 case traceback_none: trace_str = "none"; break;
2823 case traceback_part: trace_str = "part"; break;
2824 case traceback_full: trace_str = "full"; break;
2825 default: trace_str = "unknown"; break;
2828 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2830 switch (rs6000_current_cmodel)
2832 case CMODEL_SMALL: cmodel_str = "small"; break;
2833 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2834 case CMODEL_LARGE: cmodel_str = "large"; break;
2835 default: cmodel_str = "unknown"; break;
2838 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2840 switch (rs6000_current_abi)
2842 case ABI_NONE: abi_str = "none"; break;
2843 case ABI_AIX: abi_str = "aix"; break;
2844 case ABI_ELFv2: abi_str = "ELFv2"; break;
2845 case ABI_V4: abi_str = "V4"; break;
2846 case ABI_DARWIN: abi_str = "darwin"; break;
2847 default: abi_str = "unknown"; break;
2850 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2852 if (rs6000_altivec_abi)
2853 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2855 if (rs6000_darwin64_abi)
2856 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2858 fprintf (stderr, DEBUG_FMT_S, "single_float",
2859 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2861 fprintf (stderr, DEBUG_FMT_S, "double_float",
2862 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2864 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2865 (TARGET_SOFT_FLOAT ? "true" : "false"));
2867 if (TARGET_LINK_STACK)
2868 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2870 if (TARGET_P8_FUSION)
2874 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2875 if (TARGET_TOC_FUSION)
2876 strcat (options, ", toc");
2878 if (TARGET_P8_FUSION_SIGN)
2879 strcat (options, ", sign");
2881 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2884 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2885 TARGET_SECURE_PLT ? "secure" : "bss");
2886 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2887 aix_struct_return ? "aix" : "sysv");
2888 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2889 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2890 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2891 tf[!!rs6000_align_branch_targets]);
2892 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2893 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2894 rs6000_long_double_type_size);
2895 if (rs6000_long_double_type_size == 128)
2897 fprintf (stderr, DEBUG_FMT_S, "long double type",
2898 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2899 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2900 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2902 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2903 (int)rs6000_sched_restricted_insns_priority);
2904 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2906 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2907 (int)RS6000_BUILTIN_COUNT);
2909 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2910 (int)TARGET_FLOAT128_ENABLE_TYPE);
2913 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2914 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2916 if (TARGET_DIRECT_MOVE_128)
2917 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2918 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2922 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2923 legitimate address support to figure out the appropriate addressing to
2927 rs6000_setup_reg_addr_masks (void)
2929 ssize_t rc, reg, m, nregs;
2930 addr_mask_type any_addr_mask, addr_mask;
2932 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2934 machine_mode m2 = (machine_mode) m;
2935 bool complex_p = false;
2936 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2939 if (COMPLEX_MODE_P (m2))
2942 m2 = GET_MODE_INNER (m2);
2945 msize = GET_MODE_SIZE (m2);
2947 /* SDmode is special in that we want to access it only via REG+REG
2948 addressing on power7 and above, since we want to use the LFIWZX and
2949 STFIWZX instructions to load it. */
2950 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2953 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2956 reg = reload_reg_map[rc].reg;
2958 /* Can mode values go in the GPR/FPR/Altivec registers? */
2959 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2961 bool small_int_vsx_p = (small_int_p
2962 && (rc == RELOAD_REG_FPR
2963 || rc == RELOAD_REG_VMX));
2965 nregs = rs6000_hard_regno_nregs[m][reg];
2966 addr_mask |= RELOAD_REG_VALID;
2968 /* Indicate if the mode takes more than 1 physical register. If
2969 it takes a single register, indicate it can do REG+REG
2970 addressing. Small integers in VSX registers can only do
2971 REG+REG addressing. */
2972 if (small_int_vsx_p)
2973 addr_mask |= RELOAD_REG_INDEXED;
2974 else if (nregs > 1 || m == BLKmode || complex_p)
2975 addr_mask |= RELOAD_REG_MULTIPLE;
2977 addr_mask |= RELOAD_REG_INDEXED;
2979 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2980 addressing. If we allow scalars into Altivec registers,
2981 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2984 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2986 && !VECTOR_MODE_P (m2)
2987 && !FLOAT128_VECTOR_P (m2)
2989 && !small_int_vsx_p)
2991 addr_mask |= RELOAD_REG_PRE_INCDEC;
2993 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2994 we don't allow PRE_MODIFY for some multi-register
2999 addr_mask |= RELOAD_REG_PRE_MODIFY;
3003 if (TARGET_POWERPC64)
3004 addr_mask |= RELOAD_REG_PRE_MODIFY;
3010 addr_mask |= RELOAD_REG_PRE_MODIFY;
3016 /* GPR and FPR registers can do REG+OFFSET addressing, except
3017 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3018 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3019 if ((addr_mask != 0) && !indexed_only_p
3021 && (rc == RELOAD_REG_GPR
3022 || ((msize == 8 || m2 == SFmode)
3023 && (rc == RELOAD_REG_FPR
3024 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3025 addr_mask |= RELOAD_REG_OFFSET;
3027 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3028 instructions are enabled. The offset for 128-bit VSX registers is
3029 only 12-bits. While GPRs can handle the full offset range, VSX
3030 registers can only handle the restricted range. */
3031 else if ((addr_mask != 0) && !indexed_only_p
3032 && msize == 16 && TARGET_P9_VECTOR
3033 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3034 || (m2 == TImode && TARGET_VSX)))
3036 addr_mask |= RELOAD_REG_OFFSET;
3037 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3038 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3041 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3042 addressing on 128-bit types. */
3043 if (rc == RELOAD_REG_VMX && msize == 16
3044 && (addr_mask & RELOAD_REG_VALID) != 0)
3045 addr_mask |= RELOAD_REG_AND_M16;
3047 reg_addr[m].addr_mask[rc] = addr_mask;
3048 any_addr_mask |= addr_mask;
3051 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3056 /* Initialize the various global tables that are based on register size. */
3058 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3064 /* Precalculate REGNO_REG_CLASS. */
3065 rs6000_regno_regclass[0] = GENERAL_REGS;
3066 for (r = 1; r < 32; ++r)
3067 rs6000_regno_regclass[r] = BASE_REGS;
3069 for (r = 32; r < 64; ++r)
3070 rs6000_regno_regclass[r] = FLOAT_REGS;
3072 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3073 rs6000_regno_regclass[r] = NO_REGS;
3075 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3076 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3078 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3079 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3080 rs6000_regno_regclass[r] = CR_REGS;
3082 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3083 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3084 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3085 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3086 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3087 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3088 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3089 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3090 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3091 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3093 /* Precalculate register class to simpler reload register class. We don't
3094 need all of the register classes that are combinations of different
3095 classes, just the simple ones that have constraint letters. */
3096 for (c = 0; c < N_REG_CLASSES; c++)
3097 reg_class_to_reg_type[c] = NO_REG_TYPE;
3099 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3100 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3101 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3102 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3103 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3104 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3105 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3106 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3107 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3108 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3112 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3113 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3117 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3118 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3121 /* Precalculate the valid memory formats as well as the vector information,
3122 this must be set up before the rs6000_hard_regno_nregs_internal calls
3124 gcc_assert ((int)VECTOR_NONE == 0);
3125 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3126 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3128 gcc_assert ((int)CODE_FOR_nothing == 0);
3129 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3131 gcc_assert ((int)NO_REGS == 0);
3132 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3134 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3135 believes it can use native alignment or still uses 128-bit alignment. */
3136 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3147 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3148 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3149 if (TARGET_FLOAT128_TYPE)
3151 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3152 rs6000_vector_align[KFmode] = 128;
3154 if (FLOAT128_IEEE_P (TFmode))
3156 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3157 rs6000_vector_align[TFmode] = 128;
3161 /* V2DF mode, VSX only. */
3164 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3165 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3166 rs6000_vector_align[V2DFmode] = align64;
3169 /* V4SF mode, either VSX or Altivec. */
3172 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3173 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3174 rs6000_vector_align[V4SFmode] = align32;
3176 else if (TARGET_ALTIVEC)
3178 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3179 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3180 rs6000_vector_align[V4SFmode] = align32;
3183 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3187 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3188 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3189 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3190 rs6000_vector_align[V4SImode] = align32;
3191 rs6000_vector_align[V8HImode] = align32;
3192 rs6000_vector_align[V16QImode] = align32;
3196 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3197 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3198 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3202 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3203 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3204 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3208 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3209 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3212 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3213 rs6000_vector_unit[V2DImode]
3214 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3215 rs6000_vector_align[V2DImode] = align64;
3217 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3218 rs6000_vector_unit[V1TImode]
3219 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3220 rs6000_vector_align[V1TImode] = 128;
3223 /* DFmode, see if we want to use the VSX unit. Memory is handled
3224 differently, so don't set rs6000_vector_mem. */
3227 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3228 rs6000_vector_align[DFmode] = 64;
3231 /* SFmode, see if we want to use the VSX unit. */
3232 if (TARGET_P8_VECTOR)
3234 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3235 rs6000_vector_align[SFmode] = 32;
3238 /* Allow TImode in VSX register and set the VSX memory macros. */
3241 rs6000_vector_mem[TImode] = VECTOR_VSX;
3242 rs6000_vector_align[TImode] = align64;
3245 /* TODO add paired floating point vector support. */
3247 /* Register class constraints for the constraints that depend on compile
3248 switches. When the VSX code was added, different constraints were added
3249 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3250 of the VSX registers are used. The register classes for scalar floating
3251 point types is set, based on whether we allow that type into the upper
3252 (Altivec) registers. GCC has register classes to target the Altivec
3253 registers for load/store operations, to select using a VSX memory
3254 operation instead of the traditional floating point operation. The
3257 d - Register class to use with traditional DFmode instructions.
3258 f - Register class to use with traditional SFmode instructions.
3259 v - Altivec register.
3260 wa - Any VSX register.
3261 wc - Reserved to represent individual CR bits (used in LLVM).
3262 wd - Preferred register class for V2DFmode.
3263 wf - Preferred register class for V4SFmode.
3264 wg - Float register for power6x move insns.
3265 wh - FP register for direct move instructions.
3266 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3267 wj - FP or VSX register to hold 64-bit integers for direct moves.
3268 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3269 wl - Float register if we can do 32-bit signed int loads.
3270 wm - VSX register for ISA 2.07 direct move operations.
3271 wn - always NO_REGS.
3272 wr - GPR if 64-bit mode is permitted.
3273 ws - Register class to do ISA 2.06 DF operations.
3274 wt - VSX register for TImode in VSX registers.
3275 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3276 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3277 ww - Register class to do SF conversions in with VSX operations.
3278 wx - Float register if we can do 32-bit int stores.
3279 wy - Register class to do ISA 2.07 SF operations.
3280 wz - Float register if we can do 32-bit unsigned int loads.
3281 wH - Altivec register if SImode is allowed in VSX registers.
3282 wI - VSX register if SImode is allowed in VSX registers.
3283 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3284 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3286 if (TARGET_HARD_FLOAT)
3287 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3289 if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
3290 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3294 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3295 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3296 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3297 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3298 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3299 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3300 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3303 /* Add conditional constraints based on various options, to allow us to
3304 collapse multiple insn patterns. */
3306 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3308 if (TARGET_MFPGPR) /* DFmode */
3309 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3312 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3314 if (TARGET_DIRECT_MOVE)
3316 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3317 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3318 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3319 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3320 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3321 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3324 if (TARGET_POWERPC64)
3326 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3327 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3330 if (TARGET_P8_VECTOR) /* SFmode */
3332 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3333 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3334 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3336 else if (TARGET_VSX)
3337 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3340 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3343 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3345 if (TARGET_FLOAT128_TYPE)
3347 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3348 if (FLOAT128_IEEE_P (TFmode))
3349 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3352 if (TARGET_P9_VECTOR)
3354 /* Support for new D-form instructions. */
3355 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3357 /* Support for ISA 3.0 (power9) vectors. */
3358 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3361 /* Support for new direct moves (ISA 3.0 + 64bit). */
3362 if (TARGET_DIRECT_MOVE_128)
3363 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3365 /* Support small integers in VSX registers. */
3366 if (TARGET_P8_VECTOR)
3368 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3369 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3370 if (TARGET_P9_VECTOR)
3372 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3373 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3377 /* Set up the reload helper and direct move functions. */
3378 if (TARGET_VSX || TARGET_ALTIVEC)
3382 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3383 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3384 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3385 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3386 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3387 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3388 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3389 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3390 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3391 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3392 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3393 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3394 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3395 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3396 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3397 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3398 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3399 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3400 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3401 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3403 if (FLOAT128_VECTOR_P (KFmode))
3405 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3406 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3409 if (FLOAT128_VECTOR_P (TFmode))
3411 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3412 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3415 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3417 if (TARGET_NO_SDMODE_STACK)
3419 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3420 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3425 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3426 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3429 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3431 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3432 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3433 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3434 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3435 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3436 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3437 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3438 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3439 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3441 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3442 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3443 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3444 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3445 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3446 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3447 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3448 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3449 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3451 if (FLOAT128_VECTOR_P (KFmode))
3453 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3454 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3457 if (FLOAT128_VECTOR_P (TFmode))
3459 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3460 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3466 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3467 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3468 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3469 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3470 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3471 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3472 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3473 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3474 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3475 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3476 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3477 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3478 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3479 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3480 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3481 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3482 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3483 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3484 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3485 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3487 if (FLOAT128_VECTOR_P (KFmode))
3489 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3490 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3493 if (FLOAT128_IEEE_P (TFmode))
3495 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3496 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3499 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3501 if (TARGET_NO_SDMODE_STACK)
3503 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3504 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3509 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3510 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3513 if (TARGET_DIRECT_MOVE)
3515 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3516 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3517 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3521 reg_addr[DFmode].scalar_in_vmx_p = true;
3522 reg_addr[DImode].scalar_in_vmx_p = true;
3524 if (TARGET_P8_VECTOR)
3526 reg_addr[SFmode].scalar_in_vmx_p = true;
3527 reg_addr[SImode].scalar_in_vmx_p = true;
3529 if (TARGET_P9_VECTOR)
3531 reg_addr[HImode].scalar_in_vmx_p = true;
3532 reg_addr[QImode].scalar_in_vmx_p = true;
3537 /* Setup the fusion operations. */
3538 if (TARGET_P8_FUSION)
3540 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3541 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3542 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3544 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3547 if (TARGET_P9_FUSION)
3550 enum machine_mode mode; /* mode of the fused type. */
3551 enum machine_mode pmode; /* pointer mode. */
3552 enum rs6000_reload_reg_type rtype; /* register type. */
3553 enum insn_code load; /* load insn. */
3554 enum insn_code store; /* store insn. */
3557 static const struct fuse_insns addis_insns[] = {
3558 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3559 CODE_FOR_fusion_vsx_di_sf_load,
3560 CODE_FOR_fusion_vsx_di_sf_store },
3562 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3563 CODE_FOR_fusion_vsx_si_sf_load,
3564 CODE_FOR_fusion_vsx_si_sf_store },
3566 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3567 CODE_FOR_fusion_vsx_di_df_load,
3568 CODE_FOR_fusion_vsx_di_df_store },
3570 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3571 CODE_FOR_fusion_vsx_si_df_load,
3572 CODE_FOR_fusion_vsx_si_df_store },
3574 { E_DImode, E_DImode, RELOAD_REG_FPR,
3575 CODE_FOR_fusion_vsx_di_di_load,
3576 CODE_FOR_fusion_vsx_di_di_store },
3578 { E_DImode, E_SImode, RELOAD_REG_FPR,
3579 CODE_FOR_fusion_vsx_si_di_load,
3580 CODE_FOR_fusion_vsx_si_di_store },
3582 { E_QImode, E_DImode, RELOAD_REG_GPR,
3583 CODE_FOR_fusion_gpr_di_qi_load,
3584 CODE_FOR_fusion_gpr_di_qi_store },
3586 { E_QImode, E_SImode, RELOAD_REG_GPR,
3587 CODE_FOR_fusion_gpr_si_qi_load,
3588 CODE_FOR_fusion_gpr_si_qi_store },
3590 { E_HImode, E_DImode, RELOAD_REG_GPR,
3591 CODE_FOR_fusion_gpr_di_hi_load,
3592 CODE_FOR_fusion_gpr_di_hi_store },
3594 { E_HImode, E_SImode, RELOAD_REG_GPR,
3595 CODE_FOR_fusion_gpr_si_hi_load,
3596 CODE_FOR_fusion_gpr_si_hi_store },
3598 { E_SImode, E_DImode, RELOAD_REG_GPR,
3599 CODE_FOR_fusion_gpr_di_si_load,
3600 CODE_FOR_fusion_gpr_di_si_store },
3602 { E_SImode, E_SImode, RELOAD_REG_GPR,
3603 CODE_FOR_fusion_gpr_si_si_load,
3604 CODE_FOR_fusion_gpr_si_si_store },
3606 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3607 CODE_FOR_fusion_gpr_di_sf_load,
3608 CODE_FOR_fusion_gpr_di_sf_store },
3610 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3611 CODE_FOR_fusion_gpr_si_sf_load,
3612 CODE_FOR_fusion_gpr_si_sf_store },
3614 { E_DImode, E_DImode, RELOAD_REG_GPR,
3615 CODE_FOR_fusion_gpr_di_di_load,
3616 CODE_FOR_fusion_gpr_di_di_store },
3618 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3619 CODE_FOR_fusion_gpr_di_df_load,
3620 CODE_FOR_fusion_gpr_di_df_store },
3623 machine_mode cur_pmode = Pmode;
3626 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3628 machine_mode xmode = addis_insns[i].mode;
3629 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3631 if (addis_insns[i].pmode != cur_pmode)
3634 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3637 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3638 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3640 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3642 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3643 = addis_insns[i].load;
3644 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3645 = addis_insns[i].store;
3650 /* Note which types we support fusing TOC setup plus memory insn. We only do
3651 fused TOCs for medium/large code models. */
3652 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3653 && (TARGET_CMODEL != CMODEL_SMALL))
3655 reg_addr[QImode].fused_toc = true;
3656 reg_addr[HImode].fused_toc = true;
3657 reg_addr[SImode].fused_toc = true;
3658 reg_addr[DImode].fused_toc = true;
3659 if (TARGET_HARD_FLOAT)
3661 if (TARGET_SINGLE_FLOAT)
3662 reg_addr[SFmode].fused_toc = true;
3663 if (TARGET_DOUBLE_FLOAT)
3664 reg_addr[DFmode].fused_toc = true;
3668 /* Precalculate HARD_REGNO_NREGS. */
3669 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3670 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3671 rs6000_hard_regno_nregs[m][r]
3672 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3674 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3675 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3676 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3677 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3678 rs6000_hard_regno_mode_ok_p[m][r] = true;
3680 /* Precalculate CLASS_MAX_NREGS sizes. */
3681 for (c = 0; c < LIM_REG_CLASSES; ++c)
3685 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3686 reg_size = UNITS_PER_VSX_WORD;
3688 else if (c == ALTIVEC_REGS)
3689 reg_size = UNITS_PER_ALTIVEC_WORD;
3691 else if (c == FLOAT_REGS)
3692 reg_size = UNITS_PER_FP_WORD;
3695 reg_size = UNITS_PER_WORD;
3697 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3699 machine_mode m2 = (machine_mode)m;
3700 int reg_size2 = reg_size;
3702 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3704 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3705 reg_size2 = UNITS_PER_FP_WORD;
3707 rs6000_class_max_nregs[m][c]
3708 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3712 /* Calculate which modes to automatically generate code to use a the
3713 reciprocal divide and square root instructions. In the future, possibly
3714 automatically generate the instructions even if the user did not specify
3715 -mrecip. The older machines double precision reciprocal sqrt estimate is
3716 not accurate enough. */
3717 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3719 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3721 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3722 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3723 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3724 if (VECTOR_UNIT_VSX_P (V2DFmode))
3725 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3727 if (TARGET_FRSQRTES)
3728 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3730 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3731 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3732 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3733 if (VECTOR_UNIT_VSX_P (V2DFmode))
3734 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3736 if (rs6000_recip_control)
3738 if (!flag_finite_math_only)
3739 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3741 if (flag_trapping_math)
3742 warning (0, "%qs requires %qs or %qs", "-mrecip",
3743 "-fno-trapping-math", "-ffast-math");
3744 if (!flag_reciprocal_math)
3745 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3747 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3749 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3750 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3751 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3753 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3754 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3755 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3757 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3758 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3759 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3761 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3762 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3763 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3765 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3766 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3767 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3769 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3770 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3771 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3773 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3774 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3775 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3777 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3778 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3779 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3783 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3784 legitimate address support to figure out the appropriate addressing to
3786 rs6000_setup_reg_addr_masks ();
3788 if (global_init_p || TARGET_DEBUG_TARGET)
3790 if (TARGET_DEBUG_REG)
3791 rs6000_debug_reg_global ();
3793 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3795 "SImode variable mult cost = %d\n"
3796 "SImode constant mult cost = %d\n"
3797 "SImode short constant mult cost = %d\n"
3798 "DImode multipliciation cost = %d\n"
3799 "SImode division cost = %d\n"
3800 "DImode division cost = %d\n"
3801 "Simple fp operation cost = %d\n"
3802 "DFmode multiplication cost = %d\n"
3803 "SFmode division cost = %d\n"
3804 "DFmode division cost = %d\n"
3805 "cache line size = %d\n"
3806 "l1 cache size = %d\n"
3807 "l2 cache size = %d\n"
3808 "simultaneous prefetches = %d\n"
3811 rs6000_cost->mulsi_const,
3812 rs6000_cost->mulsi_const9,
3820 rs6000_cost->cache_line_size,
3821 rs6000_cost->l1_cache_size,
3822 rs6000_cost->l2_cache_size,
3823 rs6000_cost->simultaneous_prefetches);
3828 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3831 darwin_rs6000_override_options (void)
3833 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3835 rs6000_altivec_abi = 1;
3836 TARGET_ALTIVEC_VRSAVE = 1;
3837 rs6000_current_abi = ABI_DARWIN;
3839 if (DEFAULT_ABI == ABI_DARWIN
3841 darwin_one_byte_bool = 1;
3843 if (TARGET_64BIT && ! TARGET_POWERPC64)
3845 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3846 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3850 rs6000_default_long_calls = 1;
3851 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3854 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3856 if (!flag_mkernel && !flag_apple_kext
3858 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3859 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3861 /* Unless the user (not the configurer) has explicitly overridden
3862 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3863 G4 unless targeting the kernel. */
3866 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3867 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3868 && ! global_options_set.x_rs6000_cpu_index)
3870 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3875 /* If not otherwise specified by a target, make 'long double' equivalent to
3878 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3879 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3882 /* Return the builtin mask of the various options used that could affect which
3883 builtins were used. In the past we used target_flags, but we've run out of
3884 bits, and some options like PAIRED are no longer in target_flags. */
3887 rs6000_builtin_mask_calculate (void)
3889 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3890 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3891 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3892 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3893 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3894 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3895 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3896 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3897 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3898 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3899 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3900 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3901 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3902 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3903 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3904 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3905 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3906 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3907 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3908 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
3909 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3910 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3913 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3914 to clobber the XER[CA] bit because clobbering that bit without telling
3915 the compiler worked just fine with versions of GCC before GCC 5, and
3916 breaking a lot of older code in ways that are hard to track down is
3917 not such a great idea. */
3920 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3921 vec<const char *> &/*constraints*/,
3922 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3924 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3925 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3929 /* Override command line options.
3931 Combine build-specific configuration information with options
3932 specified on the command line to set various state variables which
3933 influence code generation, optimization, and expansion of built-in
3934 functions. Assure that command-line configuration preferences are
3935 compatible with each other and with the build configuration; issue
3936 warnings while adjusting configuration or error messages while
3937 rejecting configuration.
3939 Upon entry to this function:
3941 This function is called once at the beginning of
3942 compilation, and then again at the start and end of compiling
3943 each section of code that has a different configuration, as
3944 indicated, for example, by adding the
3946 __attribute__((__target__("cpu=power9")))
3948 qualifier to a function definition or, for example, by bracketing
3951 #pragma GCC target("altivec")
3955 #pragma GCC reset_options
3957 directives. Parameter global_init_p is true for the initial
3958 invocation, which initializes global variables, and false for all
3959 subsequent invocations.
3962 Various global state information is assumed to be valid. This
3963 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3964 default CPU specified at build configure time, TARGET_DEFAULT,
3965 representing the default set of option flags for the default
3966 target, and global_options_set.x_rs6000_isa_flags, representing
3967 which options were requested on the command line.
3969 Upon return from this function:
3971 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3972 was set by name on the command line. Additionally, if certain
3973 attributes are automatically enabled or disabled by this function
3974 in order to assure compatibility between options and
3975 configuration, the flags associated with those attributes are
3976 also set. By setting these "explicit bits", we avoid the risk
3977 that other code might accidentally overwrite these particular
3978 attributes with "default values".
3980 The various bits of rs6000_isa_flags are set to indicate the
3981 target options that have been selected for the most current
3982 compilation efforts. This has the effect of also turning on the
3983 associated TARGET_XXX values since these are macros which are
3984 generally defined to test the corresponding bit of the
3985 rs6000_isa_flags variable.
3987 The variable rs6000_builtin_mask is set to represent the target
3988 options for the most current compilation efforts, consistent with
3989 the current contents of rs6000_isa_flags. This variable controls
3990 expansion of built-in functions.
3992 Various other global variables and fields of global structures
3993 (over 50 in all) are initialized to reflect the desired options
3994 for the most current compilation efforts. */
3997 rs6000_option_override_internal (bool global_init_p)
4001 HOST_WIDE_INT set_masks;
4002 HOST_WIDE_INT ignore_masks;
4005 struct cl_target_option *main_target_opt
4006 = ((global_init_p || target_option_default_node == NULL)
4007 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4009 /* Print defaults. */
4010 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4011 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4013 /* Remember the explicit arguments. */
4015 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4017 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4018 library functions, so warn about it. The flag may be useful for
4019 performance studies from time to time though, so don't disable it
4021 if (global_options_set.x_rs6000_alignment_flags
4022 && rs6000_alignment_flags == MASK_ALIGN_POWER
4023 && DEFAULT_ABI == ABI_DARWIN
4025 warning (0, "%qs is not supported for 64-bit Darwin;"
4026 " it is incompatible with the installed C and C++ libraries",
4029 /* Numerous experiment shows that IRA based loop pressure
4030 calculation works better for RTL loop invariant motion on targets
4031 with enough (>= 32) registers. It is an expensive optimization.
4032 So it is on only for peak performance. */
4033 if (optimize >= 3 && global_init_p
4034 && !global_options_set.x_flag_ira_loop_pressure)
4035 flag_ira_loop_pressure = 1;
4037 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4038 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4039 options were already specified. */
4040 if (flag_sanitize & SANITIZE_USER_ADDRESS
4041 && !global_options_set.x_flag_asynchronous_unwind_tables)
4042 flag_asynchronous_unwind_tables = 1;
4044 /* Set the pointer size. */
4047 rs6000_pmode = DImode;
4048 rs6000_pointer_size = 64;
4052 rs6000_pmode = SImode;
4053 rs6000_pointer_size = 32;
4056 /* Some OSs don't support saving the high part of 64-bit registers on context
4057 switch. Other OSs don't support saving Altivec registers. On those OSs,
4058 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4059 if the user wants either, the user must explicitly specify them and we
4060 won't interfere with the user's specification. */
4062 set_masks = POWERPC_MASKS;
4063 #ifdef OS_MISSING_POWERPC64
4064 if (OS_MISSING_POWERPC64)
4065 set_masks &= ~OPTION_MASK_POWERPC64;
4067 #ifdef OS_MISSING_ALTIVEC
4068 if (OS_MISSING_ALTIVEC)
4069 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4070 | OTHER_VSX_VECTOR_MASKS);
4073 /* Don't override by the processor default if given explicitly. */
4074 set_masks &= ~rs6000_isa_flags_explicit;
4076 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4077 the cpu in a target attribute or pragma, but did not specify a tuning
4078 option, use the cpu for the tuning option rather than the option specified
4079 with -mtune on the command line. Process a '--with-cpu' configuration
4080 request as an implicit --cpu. */
4081 if (rs6000_cpu_index >= 0)
4082 cpu_index = rs6000_cpu_index;
4083 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4084 cpu_index = main_target_opt->x_rs6000_cpu_index;
4085 else if (OPTION_TARGET_CPU_DEFAULT)
4086 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4090 const char *unavailable_cpu = NULL;
4091 switch (processor_target_table[cpu_index].processor)
4093 #ifndef HAVE_AS_POWER9
4094 case PROCESSOR_POWER9:
4095 unavailable_cpu = "power9";
4098 #ifndef HAVE_AS_POWER8
4099 case PROCESSOR_POWER8:
4100 unavailable_cpu = "power8";
4103 #ifndef HAVE_AS_POPCNTD
4104 case PROCESSOR_POWER7:
4105 unavailable_cpu = "power7";
4109 case PROCESSOR_POWER6:
4110 unavailable_cpu = "power6";
4113 #ifndef HAVE_AS_POPCNTB
4114 case PROCESSOR_POWER5:
4115 unavailable_cpu = "power5";
4121 if (unavailable_cpu)
4124 warning (0, "will not generate %qs instructions because "
4125 "assembler lacks %qs support", unavailable_cpu,
4130 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4131 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4132 with those from the cpu, except for options that were explicitly set. If
4133 we don't have a cpu, do not override the target bits set in
4137 rs6000_cpu_index = cpu_index;
4138 rs6000_isa_flags &= ~set_masks;
4139 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4144 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4145 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4146 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4147 to using rs6000_isa_flags, we need to do the initialization here.
4149 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4150 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4151 HOST_WIDE_INT flags;
4153 flags = TARGET_DEFAULT;
4156 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4157 const char *default_cpu = (!TARGET_POWERPC64
4162 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4163 flags = processor_target_table[default_cpu_index].target_enable;
4165 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4168 if (rs6000_tune_index >= 0)
4169 tune_index = rs6000_tune_index;
4170 else if (cpu_index >= 0)
4171 rs6000_tune_index = tune_index = cpu_index;
4175 enum processor_type tune_proc
4176 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4179 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4180 if (processor_target_table[i].processor == tune_proc)
4187 gcc_assert (tune_index >= 0);
4188 rs6000_cpu = processor_target_table[tune_index].processor;
4190 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4191 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4192 || rs6000_cpu == PROCESSOR_PPCE5500)
4195 error ("AltiVec not supported in this target");
4198 /* If we are optimizing big endian systems for space, use the load/store
4199 multiple and string instructions. */
4200 if (BYTES_BIG_ENDIAN && optimize_size)
4201 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
4202 | OPTION_MASK_STRING);
4204 /* Don't allow -mmultiple or -mstring on little endian systems
4205 unless the cpu is a 750, because the hardware doesn't support the
4206 instructions used in little endian mode, and causes an alignment
4207 trap. The 750 does not cause an alignment trap (except when the
4208 target is unaligned). */
4210 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
4212 if (TARGET_MULTIPLE)
4214 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4215 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4216 warning (0, "%qs is not supported on little endian systems",
4222 rs6000_isa_flags &= ~OPTION_MASK_STRING;
4223 if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
4224 warning (0, "%qs is not supported on little endian systems",
4229 /* If little-endian, default to -mstrict-align on older processors.
4230 Testing for htm matches power8 and later. */
4231 if (!BYTES_BIG_ENDIAN
4232 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4233 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4235 /* -maltivec={le,be} implies -maltivec. */
4236 if (rs6000_altivec_element_order != 0)
4237 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
4239 /* Disallow -maltivec=le in big endian mode for now. This is not
4240 known to be useful for anyone. */
4241 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
4243 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4244 rs6000_altivec_element_order = 0;
4247 if (!rs6000_fold_gimple)
4249 "gimple folding of rs6000 builtins has been disabled.\n");
4251 /* Add some warnings for VSX. */
4254 const char *msg = NULL;
4255 if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
4257 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4258 msg = N_("-mvsx requires hardware floating point");
4261 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4262 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4265 else if (TARGET_PAIRED_FLOAT)
4266 msg = N_("-mvsx and -mpaired are incompatible");
4267 else if (TARGET_AVOID_XFORM > 0)
4268 msg = N_("-mvsx needs indexed addressing");
4269 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4270 & OPTION_MASK_ALTIVEC))
4272 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4273 msg = N_("-mvsx and -mno-altivec are incompatible");
4275 msg = N_("-mno-altivec disables vsx");
4281 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4282 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4286 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4287 the -mcpu setting to enable options that conflict. */
4288 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4289 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4290 | OPTION_MASK_ALTIVEC
4291 | OPTION_MASK_VSX)) != 0)
4292 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4293 | OPTION_MASK_DIRECT_MOVE)
4294 & ~rs6000_isa_flags_explicit);
4296 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4297 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4299 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4300 off all of the options that depend on those flags. */
4301 ignore_masks = rs6000_disable_incompatible_switches ();
4303 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4304 unless the user explicitly used the -mno-<option> to disable the code. */
4305 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4306 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4307 else if (TARGET_P9_MINMAX)
4311 if (cpu_index == PROCESSOR_POWER9)
4313 /* legacy behavior: allow -mcpu=power9 with certain
4314 capabilities explicitly disabled. */
4315 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4318 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4319 "for <xxx> less than power9", "-mcpu");
4321 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4322 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4323 & rs6000_isa_flags_explicit))
4324 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4325 were explicitly cleared. */
4326 error ("%qs incompatible with explicitly disabled options",
4329 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4331 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4332 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4333 else if (TARGET_VSX)
4334 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4335 else if (TARGET_POPCNTD)
4336 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4337 else if (TARGET_DFP)
4338 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4339 else if (TARGET_CMPB)
4340 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4341 else if (TARGET_FPRND)
4342 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4343 else if (TARGET_POPCNTB)
4344 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4345 else if (TARGET_ALTIVEC)
4346 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4348 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4350 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4351 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4352 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4355 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4357 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4358 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4359 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4362 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4364 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4365 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4366 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4369 if (TARGET_P8_VECTOR && !TARGET_VSX)
4371 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4372 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4373 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4374 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4376 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4377 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4378 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4382 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4384 rs6000_isa_flags |= OPTION_MASK_VSX;
4385 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4389 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4391 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4392 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4393 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4396 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4397 silently turn off quad memory mode. */
4398 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4400 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4401 warning (0, N_("-mquad-memory requires 64-bit mode"));
4403 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4404 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4406 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4407 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4410 /* Non-atomic quad memory load/store are disabled for little endian, since
4411 the words are reversed, but atomic operations can still be done by
4412 swapping the words. */
4413 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4415 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4416 warning (0, N_("-mquad-memory is not available in little endian "
4419 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4422 /* Assume if the user asked for normal quad memory instructions, they want
4423 the atomic versions as well, unless they explicity told us not to use quad
4424 word atomic instructions. */
4425 if (TARGET_QUAD_MEMORY
4426 && !TARGET_QUAD_MEMORY_ATOMIC
4427 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4428 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4430 /* If we can shrink-wrap the TOC register save separately, then use
4431 -msave-toc-indirect unless explicitly disabled. */
4432 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4433 && flag_shrink_wrap_separate
4434 && optimize_function_for_speed_p (cfun))
4435 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4437 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4438 generating power8 instructions. */
4439 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4440 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4441 & OPTION_MASK_P8_FUSION);
4443 /* Setting additional fusion flags turns on base fusion. */
4444 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4446 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4448 if (TARGET_P8_FUSION_SIGN)
4449 error ("%qs requires %qs", "-mpower8-fusion-sign",
4452 if (TARGET_TOC_FUSION)
4453 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4455 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4458 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4461 /* Power9 fusion is a superset over power8 fusion. */
4462 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4464 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4466 /* We prefer to not mention undocumented options in
4467 error messages. However, if users have managed to select
4468 power9-fusion without selecting power8-fusion, they
4469 already know about undocumented flags. */
4470 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4471 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4474 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4477 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4478 generating power9 instructions. */
4479 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4480 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4481 & OPTION_MASK_P9_FUSION);
4483 /* Power8 does not fuse sign extended loads with the addis. If we are
4484 optimizing at high levels for speed, convert a sign extended load into a
4485 zero extending load, and an explicit sign extension. */
4486 if (TARGET_P8_FUSION
4487 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4488 && optimize_function_for_speed_p (cfun)
4490 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4492 /* TOC fusion requires 64-bit and medium/large code model. */
4493 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4495 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4496 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4497 warning (0, N_("-mtoc-fusion requires 64-bit"));
4500 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4502 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4503 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4504 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4507 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4509 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4510 && (TARGET_CMODEL != CMODEL_SMALL)
4511 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4512 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4514 /* ISA 3.0 vector instructions include ISA 2.07. */
4515 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4517 /* We prefer to not mention undocumented options in
4518 error messages. However, if users have managed to select
4519 power9-vector without selecting power8-vector, they
4520 already know about undocumented flags. */
4521 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4522 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4523 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4524 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4526 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4527 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4528 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4532 /* OPTION_MASK_P9_VECTOR is explicit and
4533 OPTION_MASK_P8_VECTOR is not explicit. */
4534 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4535 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4539 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4540 support. If we only have ISA 2.06 support, and the user did not specify
4541 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4542 but we don't enable the full vectorization support */
4543 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4544 TARGET_ALLOW_MOVMISALIGN = 1;
4546 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4548 if (TARGET_ALLOW_MOVMISALIGN > 0
4549 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4550 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4552 TARGET_ALLOW_MOVMISALIGN = 0;
4555 /* Determine when unaligned vector accesses are permitted, and when
4556 they are preferred over masked Altivec loads. Note that if
4557 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4558 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4560 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4564 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4565 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4567 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4570 else if (!TARGET_ALLOW_MOVMISALIGN)
4572 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4573 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4574 "-mallow-movmisalign");
4576 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4580 /* Set long double size before the IEEE 128-bit tests. */
4581 if (!global_options_set.x_rs6000_long_double_type_size)
4583 if (main_target_opt != NULL
4584 && (main_target_opt->x_rs6000_long_double_type_size
4585 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4586 error ("target attribute or pragma changes long double size");
4588 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4591 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4592 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4593 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4594 those systems will not pick up this default. Warn if the user changes the
4595 default unless -Wno-psabi. */
4596 if (!global_options_set.x_rs6000_ieeequad)
4597 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4599 else if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4601 static bool warned_change_long_double;
4602 if (!warned_change_long_double)
4604 warned_change_long_double = true;
4605 if (TARGET_IEEEQUAD)
4606 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4608 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4612 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4613 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4614 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4615 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4616 the keyword as well as the type. */
4617 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4619 /* IEEE 128-bit floating point requires VSX support. */
4620 if (TARGET_FLOAT128_KEYWORD)
4624 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4625 error ("%qs requires VSX support", "-mfloat128");
4627 TARGET_FLOAT128_TYPE = 0;
4628 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4629 | OPTION_MASK_FLOAT128_HW);
4631 else if (!TARGET_FLOAT128_TYPE)
4633 TARGET_FLOAT128_TYPE = 1;
4634 warning (0, "The -mfloat128 option may not be fully supported");
4638 /* Enable the __float128 keyword under Linux by default. */
4639 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4640 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4641 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4643 /* If we have are supporting the float128 type and full ISA 3.0 support,
4644 enable -mfloat128-hardware by default. However, don't enable the
4645 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4646 because sometimes the compiler wants to put things in an integer
4647 container, and if we don't have __int128 support, it is impossible. */
4648 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4649 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4650 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4651 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4653 if (TARGET_FLOAT128_HW
4654 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4656 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4657 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4659 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4662 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4664 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4665 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4667 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4670 /* Print the options after updating the defaults. */
4671 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4672 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4674 /* E500mc does "better" if we inline more aggressively. Respect the
4675 user's opinion, though. */
4676 if (rs6000_block_move_inline_limit == 0
4677 && (rs6000_cpu == PROCESSOR_PPCE500MC
4678 || rs6000_cpu == PROCESSOR_PPCE500MC64
4679 || rs6000_cpu == PROCESSOR_PPCE5500
4680 || rs6000_cpu == PROCESSOR_PPCE6500))
4681 rs6000_block_move_inline_limit = 128;
4683 /* store_one_arg depends on expand_block_move to handle at least the
4684 size of reg_parm_stack_space. */
4685 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4686 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4690 /* If the appropriate debug option is enabled, replace the target hooks
4691 with debug versions that call the real version and then prints
4692 debugging information. */
4693 if (TARGET_DEBUG_COST)
4695 targetm.rtx_costs = rs6000_debug_rtx_costs;
4696 targetm.address_cost = rs6000_debug_address_cost;
4697 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4700 if (TARGET_DEBUG_ADDR)
4702 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4703 targetm.legitimize_address = rs6000_debug_legitimize_address;
4704 rs6000_secondary_reload_class_ptr
4705 = rs6000_debug_secondary_reload_class;
4706 targetm.secondary_memory_needed
4707 = rs6000_debug_secondary_memory_needed;
4708 targetm.can_change_mode_class
4709 = rs6000_debug_can_change_mode_class;
4710 rs6000_preferred_reload_class_ptr
4711 = rs6000_debug_preferred_reload_class;
4712 rs6000_legitimize_reload_address_ptr
4713 = rs6000_debug_legitimize_reload_address;
4714 rs6000_mode_dependent_address_ptr
4715 = rs6000_debug_mode_dependent_address;
4718 if (rs6000_veclibabi_name)
4720 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4721 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4724 error ("unknown vectorization library ABI type (%qs) for "
4725 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4731 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4732 target attribute or pragma which automatically enables both options,
4733 unless the altivec ABI was set. This is set by default for 64-bit, but
4735 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4737 TARGET_FLOAT128_TYPE = 0;
4738 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4739 | OPTION_MASK_FLOAT128_KEYWORD)
4740 & ~rs6000_isa_flags_explicit);
4743 /* Enable Altivec ABI for AIX -maltivec. */
4744 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4746 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4747 error ("target attribute or pragma changes AltiVec ABI");
4749 rs6000_altivec_abi = 1;
4752 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4753 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4754 be explicitly overridden in either case. */
4757 if (!global_options_set.x_rs6000_altivec_abi
4758 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4760 if (main_target_opt != NULL &&
4761 !main_target_opt->x_rs6000_altivec_abi)
4762 error ("target attribute or pragma changes AltiVec ABI");
4764 rs6000_altivec_abi = 1;
4768 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4769 So far, the only darwin64 targets are also MACH-O. */
4771 && DEFAULT_ABI == ABI_DARWIN
4774 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4775 error ("target attribute or pragma changes darwin64 ABI");
4778 rs6000_darwin64_abi = 1;
4779 /* Default to natural alignment, for better performance. */
4780 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4784 /* Place FP constants in the constant pool instead of TOC
4785 if section anchors enabled. */
4786 if (flag_section_anchors
4787 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4788 TARGET_NO_FP_IN_TOC = 1;
4790 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4791 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4793 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4794 SUBTARGET_OVERRIDE_OPTIONS;
4796 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4797 SUBSUBTARGET_OVERRIDE_OPTIONS;
4799 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4800 SUB3TARGET_OVERRIDE_OPTIONS;
4803 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4804 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4806 /* For the E500 family of cores, reset the single/double FP flags to let us
4807 check that they remain constant across attributes or pragmas. Also,
4808 clear a possible request for string instructions, not supported and which
4809 we might have silently queried above for -Os. */
4813 case PROCESSOR_PPC8540:
4814 case PROCESSOR_PPC8548:
4815 case PROCESSOR_PPCE500MC:
4816 case PROCESSOR_PPCE500MC64:
4817 case PROCESSOR_PPCE5500:
4818 case PROCESSOR_PPCE6500:
4819 rs6000_single_float = 0;
4820 rs6000_double_float = 0;
4821 rs6000_isa_flags &= ~OPTION_MASK_STRING;
4828 if (main_target_opt)
4830 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
4831 error ("target attribute or pragma changes single precision floating "
4833 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
4834 error ("target attribute or pragma changes double precision floating "
4838 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
4839 && rs6000_cpu != PROCESSOR_POWER5
4840 && rs6000_cpu != PROCESSOR_POWER6
4841 && rs6000_cpu != PROCESSOR_POWER7
4842 && rs6000_cpu != PROCESSOR_POWER8
4843 && rs6000_cpu != PROCESSOR_POWER9
4844 && rs6000_cpu != PROCESSOR_PPCA2
4845 && rs6000_cpu != PROCESSOR_CELL
4846 && rs6000_cpu != PROCESSOR_PPC476);
4847 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
4848 || rs6000_cpu == PROCESSOR_POWER5
4849 || rs6000_cpu == PROCESSOR_POWER7
4850 || rs6000_cpu == PROCESSOR_POWER8);
4851 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
4852 || rs6000_cpu == PROCESSOR_POWER5
4853 || rs6000_cpu == PROCESSOR_POWER6
4854 || rs6000_cpu == PROCESSOR_POWER7
4855 || rs6000_cpu == PROCESSOR_POWER8
4856 || rs6000_cpu == PROCESSOR_POWER9
4857 || rs6000_cpu == PROCESSOR_PPCE500MC
4858 || rs6000_cpu == PROCESSOR_PPCE500MC64
4859 || rs6000_cpu == PROCESSOR_PPCE5500
4860 || rs6000_cpu == PROCESSOR_PPCE6500);
4862 /* Allow debug switches to override the above settings. These are set to -1
4863 in rs6000.opt to indicate the user hasn't directly set the switch. */
4864 if (TARGET_ALWAYS_HINT >= 0)
4865 rs6000_always_hint = TARGET_ALWAYS_HINT;
4867 if (TARGET_SCHED_GROUPS >= 0)
4868 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4870 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4871 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4873 rs6000_sched_restricted_insns_priority
4874 = (rs6000_sched_groups ? 1 : 0);
4876 /* Handle -msched-costly-dep option. */
4877 rs6000_sched_costly_dep
4878 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4880 if (rs6000_sched_costly_dep_str)
4882 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4883 rs6000_sched_costly_dep = no_dep_costly;
4884 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4885 rs6000_sched_costly_dep = all_deps_costly;
4886 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4887 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4888 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4889 rs6000_sched_costly_dep = store_to_load_dep_costly;
4891 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4892 atoi (rs6000_sched_costly_dep_str));
4895 /* Handle -minsert-sched-nops option. */
4896 rs6000_sched_insert_nops
4897 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4899 if (rs6000_sched_insert_nops_str)
4901 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4902 rs6000_sched_insert_nops = sched_finish_none;
4903 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4904 rs6000_sched_insert_nops = sched_finish_pad_groups;
4905 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4906 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4908 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4909 atoi (rs6000_sched_insert_nops_str));
4912 /* Handle stack protector */
4913 if (!global_options_set.x_rs6000_stack_protector_guard)
4914 #ifdef TARGET_THREAD_SSP_OFFSET
4915 rs6000_stack_protector_guard = SSP_TLS;
4917 rs6000_stack_protector_guard = SSP_GLOBAL;
4920 #ifdef TARGET_THREAD_SSP_OFFSET
4921 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4922 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4925 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4928 const char *str = rs6000_stack_protector_guard_offset_str;
4931 long offset = strtol (str, &endp, 0);
4932 if (!*str || *endp || errno)
4933 error ("%qs is not a valid number in %qs", str,
4934 "-mstack-protector-guard-offset=");
4936 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4937 || (TARGET_64BIT && (offset & 3)))
4938 error ("%qs is not a valid offset in %qs", str,
4939 "-mstack-protector-guard-offset=");
4941 rs6000_stack_protector_guard_offset = offset;
4944 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4946 const char *str = rs6000_stack_protector_guard_reg_str;
4947 int reg = decode_reg_name (str);
4949 if (!IN_RANGE (reg, 1, 31))
4950 error ("%qs is not a valid base register in %qs", str,
4951 "-mstack-protector-guard-reg=");
4953 rs6000_stack_protector_guard_reg = reg;
4956 if (rs6000_stack_protector_guard == SSP_TLS
4957 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4958 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4962 #ifdef TARGET_REGNAMES
4963 /* If the user desires alternate register names, copy in the
4964 alternate names now. */
4965 if (TARGET_REGNAMES)
4966 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4969 /* Set aix_struct_return last, after the ABI is determined.
4970 If -maix-struct-return or -msvr4-struct-return was explicitly
4971 used, don't override with the ABI default. */
4972 if (!global_options_set.x_aix_struct_return)
4973 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4976 /* IBM XL compiler defaults to unsigned bitfields. */
4977 if (TARGET_XL_COMPAT)
4978 flag_signed_bitfields = 0;
4981 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4982 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4984 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4986 /* We can only guarantee the availability of DI pseudo-ops when
4987 assembling for 64-bit targets. */
4990 targetm.asm_out.aligned_op.di = NULL;
4991 targetm.asm_out.unaligned_op.di = NULL;
4995 /* Set branch target alignment, if not optimizing for size. */
4998 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4999 aligned 8byte to avoid misprediction by the branch predictor. */
5000 if (rs6000_cpu == PROCESSOR_TITAN
5001 || rs6000_cpu == PROCESSOR_CELL)
5003 if (align_functions <= 0)
5004 align_functions = 8;
5005 if (align_jumps <= 0)
5007 if (align_loops <= 0)
5010 if (rs6000_align_branch_targets)
5012 if (align_functions <= 0)
5013 align_functions = 16;
5014 if (align_jumps <= 0)
5016 if (align_loops <= 0)
5018 can_override_loop_align = 1;
5022 if (align_jumps_max_skip <= 0)
5023 align_jumps_max_skip = 15;
5024 if (align_loops_max_skip <= 0)
5025 align_loops_max_skip = 15;
5028 /* Arrange to save and restore machine status around nested functions. */
5029 init_machine_status = rs6000_init_machine_status;
5031 /* We should always be splitting complex arguments, but we can't break
5032 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5033 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
5034 targetm.calls.split_complex_arg = NULL;
5036 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5037 if (DEFAULT_ABI == ABI_AIX)
5038 targetm.calls.custom_function_descriptors = 0;
5041 /* Initialize rs6000_cost with the appropriate target costs. */
5043 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
5047 case PROCESSOR_RS64A:
5048 rs6000_cost = &rs64a_cost;
5051 case PROCESSOR_MPCCORE:
5052 rs6000_cost = &mpccore_cost;
5055 case PROCESSOR_PPC403:
5056 rs6000_cost = &ppc403_cost;
5059 case PROCESSOR_PPC405:
5060 rs6000_cost = &ppc405_cost;
5063 case PROCESSOR_PPC440:
5064 rs6000_cost = &ppc440_cost;
5067 case PROCESSOR_PPC476:
5068 rs6000_cost = &ppc476_cost;
5071 case PROCESSOR_PPC601:
5072 rs6000_cost = &ppc601_cost;
5075 case PROCESSOR_PPC603:
5076 rs6000_cost = &ppc603_cost;
5079 case PROCESSOR_PPC604:
5080 rs6000_cost = &ppc604_cost;
5083 case PROCESSOR_PPC604e:
5084 rs6000_cost = &ppc604e_cost;
5087 case PROCESSOR_PPC620:
5088 rs6000_cost = &ppc620_cost;
5091 case PROCESSOR_PPC630:
5092 rs6000_cost = &ppc630_cost;
5095 case PROCESSOR_CELL:
5096 rs6000_cost = &ppccell_cost;
5099 case PROCESSOR_PPC750:
5100 case PROCESSOR_PPC7400:
5101 rs6000_cost = &ppc750_cost;
5104 case PROCESSOR_PPC7450:
5105 rs6000_cost = &ppc7450_cost;
5108 case PROCESSOR_PPC8540:
5109 case PROCESSOR_PPC8548:
5110 rs6000_cost = &ppc8540_cost;
5113 case PROCESSOR_PPCE300C2:
5114 case PROCESSOR_PPCE300C3:
5115 rs6000_cost = &ppce300c2c3_cost;
5118 case PROCESSOR_PPCE500MC:
5119 rs6000_cost = &ppce500mc_cost;
5122 case PROCESSOR_PPCE500MC64:
5123 rs6000_cost = &ppce500mc64_cost;
5126 case PROCESSOR_PPCE5500:
5127 rs6000_cost = &ppce5500_cost;
5130 case PROCESSOR_PPCE6500:
5131 rs6000_cost = &ppce6500_cost;
5134 case PROCESSOR_TITAN:
5135 rs6000_cost = &titan_cost;
5138 case PROCESSOR_POWER4:
5139 case PROCESSOR_POWER5:
5140 rs6000_cost = &power4_cost;
5143 case PROCESSOR_POWER6:
5144 rs6000_cost = &power6_cost;
5147 case PROCESSOR_POWER7:
5148 rs6000_cost = &power7_cost;
5151 case PROCESSOR_POWER8:
5152 rs6000_cost = &power8_cost;
5155 case PROCESSOR_POWER9:
5156 rs6000_cost = &power9_cost;
5159 case PROCESSOR_PPCA2:
5160 rs6000_cost = &ppca2_cost;
5169 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5170 rs6000_cost->simultaneous_prefetches,
5171 global_options.x_param_values,
5172 global_options_set.x_param_values);
5173 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5174 global_options.x_param_values,
5175 global_options_set.x_param_values);
5176 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5177 rs6000_cost->cache_line_size,
5178 global_options.x_param_values,
5179 global_options_set.x_param_values);
5180 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5181 global_options.x_param_values,
5182 global_options_set.x_param_values);
5184 /* Increase loop peeling limits based on performance analysis. */
5185 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5186 global_options.x_param_values,
5187 global_options_set.x_param_values);
5188 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5189 global_options.x_param_values,
5190 global_options_set.x_param_values);
5192 /* Use the 'model' -fsched-pressure algorithm by default. */
5193 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5194 SCHED_PRESSURE_MODEL,
5195 global_options.x_param_values,
5196 global_options_set.x_param_values);
5198 /* If using typedef char *va_list, signal that
5199 __builtin_va_start (&ap, 0) can be optimized to
5200 ap = __builtin_next_arg (0). */
5201 if (DEFAULT_ABI != ABI_V4)
5202 targetm.expand_builtin_va_start = NULL;
5205 /* Set up single/double float flags.
5206 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5207 then set both flags. */
5208 if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
5209 rs6000_single_float = rs6000_double_float = 1;
5211 /* If not explicitly specified via option, decide whether to generate indexed
5212 load/store instructions. A value of -1 indicates that the
5213 initial value of this variable has not been overwritten. During
5214 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5215 if (TARGET_AVOID_XFORM == -1)
5216 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5217 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5218 need indexed accesses and the type used is the scalar type of the element
5219 being loaded or stored. */
5220 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
5221 && !TARGET_ALTIVEC);
5223 /* Set the -mrecip options. */
5224 if (rs6000_recip_name)
5226 char *p = ASTRDUP (rs6000_recip_name);
5228 unsigned int mask, i;
5231 while ((q = strtok (p, ",")) != NULL)
5242 if (!strcmp (q, "default"))
5243 mask = ((TARGET_RECIP_PRECISION)
5244 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5247 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5248 if (!strcmp (q, recip_options[i].string))
5250 mask = recip_options[i].mask;
5254 if (i == ARRAY_SIZE (recip_options))
5256 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5264 rs6000_recip_control &= ~mask;
5266 rs6000_recip_control |= mask;
5270 /* Set the builtin mask of the various options used that could affect which
5271 builtins were used. In the past we used target_flags, but we've run out
5272 of bits, and some options like PAIRED are no longer in target_flags. */
5273 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5274 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5275 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5276 rs6000_builtin_mask);
5278 /* Initialize all of the registers. */
5279 rs6000_init_hard_regno_mode_ok (global_init_p);
5281 /* Save the initial options in case the user does function specific options */
5283 target_option_default_node = target_option_current_node
5284 = build_target_option_node (&global_options);
5286 /* If not explicitly specified via option, decide whether to generate the
5287 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5288 if (TARGET_LINK_STACK == -1)
5289 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
5294 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5295 define the target cpu type. */
5298 rs6000_option_override (void)
5300 (void) rs6000_option_override_internal (true);
5304 /* Implement targetm.vectorize.builtin_mask_for_load. */
5306 rs6000_builtin_mask_for_load (void)
5308 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5309 if ((TARGET_ALTIVEC && !TARGET_VSX)
5310 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5311 return altivec_builtin_mask_for_load;
5316 /* Implement LOOP_ALIGN. */
5318 rs6000_loop_align (rtx label)
5323 /* Don't override loop alignment if -falign-loops was specified. */
5324 if (!can_override_loop_align)
5325 return align_loops_log;
5327 bb = BLOCK_FOR_INSN (label);
5328 ninsns = num_loop_insns(bb->loop_father);
5330 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5331 if (ninsns > 4 && ninsns <= 8
5332 && (rs6000_cpu == PROCESSOR_POWER4
5333 || rs6000_cpu == PROCESSOR_POWER5
5334 || rs6000_cpu == PROCESSOR_POWER6
5335 || rs6000_cpu == PROCESSOR_POWER7
5336 || rs6000_cpu == PROCESSOR_POWER8
5337 || rs6000_cpu == PROCESSOR_POWER9))
5340 return align_loops_log;
5343 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5345 rs6000_loop_align_max_skip (rtx_insn *label)
5347 return (1 << rs6000_loop_align (label)) - 1;
5350 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5351 after applying N number of iterations. This routine does not determine
5352 how may iterations are required to reach desired alignment. */
5355 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5362 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5365 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5375 /* Assuming that all other types are naturally aligned. CHECKME! */
5380 /* Return true if the vector misalignment factor is supported by the
5383 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5390 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5393 /* Return if movmisalign pattern is not supported for this mode. */
5394 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5397 if (misalignment == -1)
5399 /* Misalignment factor is unknown at compile time but we know
5400 it's word aligned. */
5401 if (rs6000_vector_alignment_reachable (type, is_packed))
5403 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5405 if (element_size == 64 || element_size == 32)
5412 /* VSX supports word-aligned vector. */
5413 if (misalignment % 4 == 0)
5419 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5421 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5422 tree vectype, int misalign)
5427 switch (type_of_cost)
5437 case cond_branch_not_taken:
5446 case vec_promote_demote:
5452 case cond_branch_taken:
5455 case unaligned_load:
5456 case vector_gather_load:
5457 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5460 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5462 elements = TYPE_VECTOR_SUBPARTS (vectype);
5464 /* Double word aligned. */
5472 /* Double word aligned. */
5476 /* Unknown misalignment. */
5489 /* Misaligned loads are not supported. */
5494 case unaligned_store:
5495 case vector_scatter_store:
5496 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5499 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5501 elements = TYPE_VECTOR_SUBPARTS (vectype);
5503 /* Double word aligned. */
5511 /* Double word aligned. */
5515 /* Unknown misalignment. */
5528 /* Misaligned stores are not supported. */
5534 /* This is a rough approximation assuming non-constant elements
5535 constructed into a vector via element insertion. FIXME:
5536 vec_construct is not granular enough for uniformly good
5537 decisions. If the initialization is a splat, this is
5538 cheaper than we estimate. Improve this someday. */
5539 elem_type = TREE_TYPE (vectype);
5540 /* 32-bit vectors loaded into registers are stored as double
5541 precision, so we need 2 permutes, 2 converts, and 1 merge
5542 to construct a vector of short floats from them. */
5543 if (SCALAR_FLOAT_TYPE_P (elem_type)
5544 && TYPE_PRECISION (elem_type) == 32)
5546 /* On POWER9, integer vector types are built up in GPRs and then
5547 use a direct move (2 cycles). For POWER8 this is even worse,
5548 as we need two direct moves and a merge, and the direct moves
5550 else if (INTEGRAL_TYPE_P (elem_type))
5552 if (TARGET_P9_VECTOR)
5553 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5555 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5558 /* V2DFmode doesn't need a direct move. */
5566 /* Implement targetm.vectorize.preferred_simd_mode. */
5569 rs6000_preferred_simd_mode (scalar_mode mode)
5578 if (TARGET_ALTIVEC || TARGET_VSX)
5595 if (TARGET_PAIRED_FLOAT
5601 typedef struct _rs6000_cost_data
5603 struct loop *loop_info;
5607 /* Test for likely overcommitment of vector hardware resources. If a
5608 loop iteration is relatively large, and too large a percentage of
5609 instructions in the loop are vectorized, the cost model may not
5610 adequately reflect delays from unavailable vector resources.
5611 Penalize the loop body cost for this case. */
5614 rs6000_density_test (rs6000_cost_data *data)
5616 const int DENSITY_PCT_THRESHOLD = 85;
5617 const int DENSITY_SIZE_THRESHOLD = 70;
5618 const int DENSITY_PENALTY = 10;
5619 struct loop *loop = data->loop_info;
5620 basic_block *bbs = get_loop_body (loop);
5621 int nbbs = loop->num_nodes;
5622 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5625 for (i = 0; i < nbbs; i++)
5627 basic_block bb = bbs[i];
5628 gimple_stmt_iterator gsi;
5630 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5632 gimple *stmt = gsi_stmt (gsi);
5633 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5635 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5636 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5642 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5644 if (density_pct > DENSITY_PCT_THRESHOLD
5645 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5647 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5648 if (dump_enabled_p ())
5649 dump_printf_loc (MSG_NOTE, vect_location,
5650 "density %d%%, cost %d exceeds threshold, penalizing "
5651 "loop body cost by %d%%", density_pct,
5652 vec_cost + not_vec_cost, DENSITY_PENALTY);
5656 /* Implement targetm.vectorize.init_cost. */
5658 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5659 instruction is needed by the vectorization. */
5660 static bool rs6000_vect_nonmem;
5663 rs6000_init_cost (struct loop *loop_info)
5665 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5666 data->loop_info = loop_info;
5667 data->cost[vect_prologue] = 0;
5668 data->cost[vect_body] = 0;
5669 data->cost[vect_epilogue] = 0;
5670 rs6000_vect_nonmem = false;
5674 /* Implement targetm.vectorize.add_stmt_cost. */
5677 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5678 struct _stmt_vec_info *stmt_info, int misalign,
5679 enum vect_cost_model_location where)
5681 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5682 unsigned retval = 0;
5684 if (flag_vect_cost_model)
5686 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5687 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5689 /* Statements in an inner loop relative to the loop being
5690 vectorized are weighted more heavily. The value here is
5691 arbitrary and could potentially be improved with analysis. */
5692 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5693 count *= 50; /* FIXME. */
5695 retval = (unsigned) (count * stmt_cost);
5696 cost_data->cost[where] += retval;
5698 /* Check whether we're doing something other than just a copy loop.
5699 Not all such loops may be profitably vectorized; see
5700 rs6000_finish_cost. */
5701 if ((kind == vec_to_scalar || kind == vec_perm
5702 || kind == vec_promote_demote || kind == vec_construct
5703 || kind == scalar_to_vec)
5704 || (where == vect_body && kind == vector_stmt))
5705 rs6000_vect_nonmem = true;
5711 /* Implement targetm.vectorize.finish_cost. */
5714 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5715 unsigned *body_cost, unsigned *epilogue_cost)
5717 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5719 if (cost_data->loop_info)
5720 rs6000_density_test (cost_data);
5722 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5723 that require versioning for any reason. The vectorization is at
5724 best a wash inside the loop, and the versioning checks make
5725 profitability highly unlikely and potentially quite harmful. */
5726 if (cost_data->loop_info)
5728 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5729 if (!rs6000_vect_nonmem
5730 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5731 && LOOP_REQUIRES_VERSIONING (vec_info))
5732 cost_data->cost[vect_body] += 10000;
5735 *prologue_cost = cost_data->cost[vect_prologue];
5736 *body_cost = cost_data->cost[vect_body];
5737 *epilogue_cost = cost_data->cost[vect_epilogue];
5740 /* Implement targetm.vectorize.destroy_cost_data. */
5743 rs6000_destroy_cost_data (void *data)
5748 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5749 library with vectorized intrinsics. */
5752 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5756 const char *suffix = NULL;
5757 tree fntype, new_fndecl, bdecl = NULL_TREE;
5760 machine_mode el_mode, in_mode;
5763 /* Libmass is suitable for unsafe math only as it does not correctly support
5764 parts of IEEE with the required precision such as denormals. Only support
5765 it if we have VSX to use the simd d2 or f4 functions.
5766 XXX: Add variable length support. */
5767 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5770 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5771 n = TYPE_VECTOR_SUBPARTS (type_out);
5772 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5773 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5774 if (el_mode != in_mode
5810 if (el_mode == DFmode && n == 2)
5812 bdecl = mathfn_built_in (double_type_node, fn);
5813 suffix = "d2"; /* pow -> powd2 */
5815 else if (el_mode == SFmode && n == 4)
5817 bdecl = mathfn_built_in (float_type_node, fn);
5818 suffix = "4"; /* powf -> powf4 */
5830 gcc_assert (suffix != NULL);
5831 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5835 strcpy (name, bname + sizeof ("__builtin_") - 1);
5836 strcat (name, suffix);
5839 fntype = build_function_type_list (type_out, type_in, NULL);
5840 else if (n_args == 2)
5841 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5845 /* Build a function declaration for the vectorized function. */
5846 new_fndecl = build_decl (BUILTINS_LOCATION,
5847 FUNCTION_DECL, get_identifier (name), fntype);
5848 TREE_PUBLIC (new_fndecl) = 1;
5849 DECL_EXTERNAL (new_fndecl) = 1;
5850 DECL_IS_NOVOPS (new_fndecl) = 1;
5851 TREE_READONLY (new_fndecl) = 1;
5856 /* Returns a function decl for a vectorized version of the builtin function
5857 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5858 if it is not available. */
5861 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5864 machine_mode in_mode, out_mode;
5867 if (TARGET_DEBUG_BUILTIN)
5868 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5869 combined_fn_name (combined_fn (fn)),
5870 GET_MODE_NAME (TYPE_MODE (type_out)),
5871 GET_MODE_NAME (TYPE_MODE (type_in)));
5873 if (TREE_CODE (type_out) != VECTOR_TYPE
5874 || TREE_CODE (type_in) != VECTOR_TYPE)
5877 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5878 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5879 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5880 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5885 if (VECTOR_UNIT_VSX_P (V2DFmode)
5886 && out_mode == DFmode && out_n == 2
5887 && in_mode == DFmode && in_n == 2)
5888 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5889 if (VECTOR_UNIT_VSX_P (V4SFmode)
5890 && out_mode == SFmode && out_n == 4
5891 && in_mode == SFmode && in_n == 4)
5892 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5893 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5894 && out_mode == SFmode && out_n == 4
5895 && in_mode == SFmode && in_n == 4)
5896 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5899 if (VECTOR_UNIT_VSX_P (V2DFmode)
5900 && out_mode == DFmode && out_n == 2
5901 && in_mode == DFmode && in_n == 2)
5902 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5903 if (VECTOR_UNIT_VSX_P (V4SFmode)
5904 && out_mode == SFmode && out_n == 4
5905 && in_mode == SFmode && in_n == 4)
5906 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5907 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5908 && out_mode == SFmode && out_n == 4
5909 && in_mode == SFmode && in_n == 4)
5910 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5913 if (VECTOR_UNIT_VSX_P (V2DFmode)
5914 && out_mode == DFmode && out_n == 2
5915 && in_mode == DFmode && in_n == 2)
5916 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5917 if (VECTOR_UNIT_VSX_P (V4SFmode)
5918 && out_mode == SFmode && out_n == 4
5919 && in_mode == SFmode && in_n == 4)
5920 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5921 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5922 && out_mode == SFmode && out_n == 4
5923 && in_mode == SFmode && in_n == 4)
5924 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5927 if (VECTOR_UNIT_VSX_P (V2DFmode)
5928 && out_mode == DFmode && out_n == 2
5929 && in_mode == DFmode && in_n == 2)
5930 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5931 if (VECTOR_UNIT_VSX_P (V4SFmode)
5932 && out_mode == SFmode && out_n == 4
5933 && in_mode == SFmode && in_n == 4)
5934 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5935 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5936 && out_mode == SFmode && out_n == 4
5937 && in_mode == SFmode && in_n == 4)
5938 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5941 if (VECTOR_UNIT_VSX_P (V2DFmode)
5942 && out_mode == DFmode && out_n == 2
5943 && in_mode == DFmode && in_n == 2)
5944 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5945 if (VECTOR_UNIT_VSX_P (V4SFmode)
5946 && out_mode == SFmode && out_n == 4
5947 && in_mode == SFmode && in_n == 4)
5948 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5949 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5950 && out_mode == SFmode && out_n == 4
5951 && in_mode == SFmode && in_n == 4)
5952 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5955 if (VECTOR_UNIT_VSX_P (V2DFmode)
5956 && flag_unsafe_math_optimizations
5957 && out_mode == DFmode && out_n == 2
5958 && in_mode == DFmode && in_n == 2)
5959 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5960 if (VECTOR_UNIT_VSX_P (V4SFmode)
5961 && flag_unsafe_math_optimizations
5962 && out_mode == SFmode && out_n == 4
5963 && in_mode == SFmode && in_n == 4)
5964 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5967 if (VECTOR_UNIT_VSX_P (V2DFmode)
5968 && !flag_trapping_math
5969 && out_mode == DFmode && out_n == 2
5970 && in_mode == DFmode && in_n == 2)
5971 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5972 if (VECTOR_UNIT_VSX_P (V4SFmode)
5973 && !flag_trapping_math
5974 && out_mode == SFmode && out_n == 4
5975 && in_mode == SFmode && in_n == 4)
5976 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5982 /* Generate calls to libmass if appropriate. */
5983 if (rs6000_veclib_handler)
5984 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5989 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5992 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5995 machine_mode in_mode, out_mode;
5998 if (TARGET_DEBUG_BUILTIN)
5999 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
6000 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
6001 GET_MODE_NAME (TYPE_MODE (type_out)),
6002 GET_MODE_NAME (TYPE_MODE (type_in)));
6004 if (TREE_CODE (type_out) != VECTOR_TYPE
6005 || TREE_CODE (type_in) != VECTOR_TYPE)
6008 out_mode = TYPE_MODE (TREE_TYPE (type_out));
6009 out_n = TYPE_VECTOR_SUBPARTS (type_out);
6010 in_mode = TYPE_MODE (TREE_TYPE (type_in));
6011 in_n = TYPE_VECTOR_SUBPARTS (type_in);
6013 enum rs6000_builtins fn
6014 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
6017 case RS6000_BUILTIN_RSQRTF:
6018 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6019 && out_mode == SFmode && out_n == 4
6020 && in_mode == SFmode && in_n == 4)
6021 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
6023 case RS6000_BUILTIN_RSQRT:
6024 if (VECTOR_UNIT_VSX_P (V2DFmode)
6025 && out_mode == DFmode && out_n == 2
6026 && in_mode == DFmode && in_n == 2)
6027 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
6029 case RS6000_BUILTIN_RECIPF:
6030 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6031 && out_mode == SFmode && out_n == 4
6032 && in_mode == SFmode && in_n == 4)
6033 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
6035 case RS6000_BUILTIN_RECIP:
6036 if (VECTOR_UNIT_VSX_P (V2DFmode)
6037 && out_mode == DFmode && out_n == 2
6038 && in_mode == DFmode && in_n == 2)
6039 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
6047 /* Default CPU string for rs6000*_file_start functions. */
6048 static const char *rs6000_default_cpu;
6050 /* Do anything needed at the start of the asm file. */
6053 rs6000_file_start (void)
6056 const char *start = buffer;
6057 FILE *file = asm_out_file;
6059 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6061 default_file_start ();
6063 if (flag_verbose_asm)
6065 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6067 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6069 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6073 if (global_options_set.x_rs6000_cpu_index)
6075 fprintf (file, "%s -mcpu=%s", start,
6076 processor_target_table[rs6000_cpu_index].name);
6080 if (global_options_set.x_rs6000_tune_index)
6082 fprintf (file, "%s -mtune=%s", start,
6083 processor_target_table[rs6000_tune_index].name);
6087 if (PPC405_ERRATUM77)
6089 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6093 #ifdef USING_ELFOS_H
6094 switch (rs6000_sdata)
6096 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6097 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6098 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6099 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6102 if (rs6000_sdata && g_switch_value)
6104 fprintf (file, "%s -G %d", start,
6114 #ifdef USING_ELFOS_H
6115 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6116 && !global_options_set.x_rs6000_cpu_index)
6118 fputs ("\t.machine ", asm_out_file);
6119 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6120 fputs ("power9\n", asm_out_file);
6121 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6122 fputs ("power8\n", asm_out_file);
6123 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6124 fputs ("power7\n", asm_out_file);
6125 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6126 fputs ("power6\n", asm_out_file);
6127 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6128 fputs ("power5\n", asm_out_file);
6129 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6130 fputs ("power4\n", asm_out_file);
6131 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6132 fputs ("ppc64\n", asm_out_file);
6134 fputs ("ppc\n", asm_out_file);
6138 if (DEFAULT_ABI == ABI_ELFv2)
6139 fprintf (file, "\t.abiversion 2\n");
6143 /* Return nonzero if this function is known to have a null epilogue. */
6146 direct_return (void)
6148 if (reload_completed)
6150 rs6000_stack_t *info = rs6000_stack_info ();
6152 if (info->first_gp_reg_save == 32
6153 && info->first_fp_reg_save == 64
6154 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6155 && ! info->lr_save_p
6156 && ! info->cr_save_p
6157 && info->vrsave_size == 0
6165 /* Return the number of instructions it takes to form a constant in an
6166 integer register. */
6169 num_insns_constant_wide (HOST_WIDE_INT value)
6171 /* signed constant loadable with addi */
6172 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6175 /* constant loadable with addis */
6176 else if ((value & 0xffff) == 0
6177 && (value >> 31 == -1 || value >> 31 == 0))
6180 else if (TARGET_POWERPC64)
6182 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6183 HOST_WIDE_INT high = value >> 31;
6185 if (high == 0 || high == -1)
6191 return num_insns_constant_wide (high) + 1;
6193 return num_insns_constant_wide (low) + 1;
6195 return (num_insns_constant_wide (high)
6196 + num_insns_constant_wide (low) + 1);
6204 num_insns_constant (rtx op, machine_mode mode)
6206 HOST_WIDE_INT low, high;
6208 switch (GET_CODE (op))
6211 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6212 && rs6000_is_valid_and_mask (op, mode))
6215 return num_insns_constant_wide (INTVAL (op));
6217 case CONST_WIDE_INT:
6220 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6221 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6222 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6227 if (mode == SFmode || mode == SDmode)
6231 if (DECIMAL_FLOAT_MODE_P (mode))
6232 REAL_VALUE_TO_TARGET_DECIMAL32
6233 (*CONST_DOUBLE_REAL_VALUE (op), l);
6235 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6236 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6240 if (DECIMAL_FLOAT_MODE_P (mode))
6241 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6243 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6244 high = l[WORDS_BIG_ENDIAN == 0];
6245 low = l[WORDS_BIG_ENDIAN != 0];
6248 return (num_insns_constant_wide (low)
6249 + num_insns_constant_wide (high));
6252 if ((high == 0 && low >= 0)
6253 || (high == -1 && low < 0))
6254 return num_insns_constant_wide (low);
6256 else if (rs6000_is_valid_and_mask (op, mode))
6260 return num_insns_constant_wide (high) + 1;
6263 return (num_insns_constant_wide (high)
6264 + num_insns_constant_wide (low) + 1);
6272 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6273 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6274 corresponding element of the vector, but for V4SFmode and V2SFmode,
6275 the corresponding "float" is interpreted as an SImode integer. */
6278 const_vector_elt_as_int (rtx op, unsigned int elt)
6282 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6283 gcc_assert (GET_MODE (op) != V2DImode
6284 && GET_MODE (op) != V2DFmode);
6286 tmp = CONST_VECTOR_ELT (op, elt);
6287 if (GET_MODE (op) == V4SFmode
6288 || GET_MODE (op) == V2SFmode)
6289 tmp = gen_lowpart (SImode, tmp);
6290 return INTVAL (tmp);
6293 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6294 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6295 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6296 all items are set to the same value and contain COPIES replicas of the
6297 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6298 operand and the others are set to the value of the operand's msb. */
6301 vspltis_constant (rtx op, unsigned step, unsigned copies)
6303 machine_mode mode = GET_MODE (op);
6304 machine_mode inner = GET_MODE_INNER (mode);
6312 HOST_WIDE_INT splat_val;
6313 HOST_WIDE_INT msb_val;
6315 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6318 nunits = GET_MODE_NUNITS (mode);
6319 bitsize = GET_MODE_BITSIZE (inner);
6320 mask = GET_MODE_MASK (inner);
6322 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6324 msb_val = val >= 0 ? 0 : -1;
6326 /* Construct the value to be splatted, if possible. If not, return 0. */
6327 for (i = 2; i <= copies; i *= 2)
6329 HOST_WIDE_INT small_val;
6331 small_val = splat_val >> bitsize;
6333 if (splat_val != ((HOST_WIDE_INT)
6334 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6335 | (small_val & mask)))
6337 splat_val = small_val;
6340 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6341 if (EASY_VECTOR_15 (splat_val))
6344 /* Also check if we can splat, and then add the result to itself. Do so if
6345 the value is positive, of if the splat instruction is using OP's mode;
6346 for splat_val < 0, the splat and the add should use the same mode. */
6347 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6348 && (splat_val >= 0 || (step == 1 && copies == 1)))
6351 /* Also check if are loading up the most significant bit which can be done by
6352 loading up -1 and shifting the value left by -1. */
6353 else if (EASY_VECTOR_MSB (splat_val, inner))
6359 /* Check if VAL is present in every STEP-th element, and the
6360 other elements are filled with its most significant bit. */
6361 for (i = 1; i < nunits; ++i)
6363 HOST_WIDE_INT desired_val;
6364 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6365 if ((i & (step - 1)) == 0)
6368 desired_val = msb_val;
6370 if (desired_val != const_vector_elt_as_int (op, elt))
6377 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6378 instruction, filling in the bottom elements with 0 or -1.
6380 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6381 for the number of zeroes to shift in, or negative for the number of 0xff
6384 OP is a CONST_VECTOR. */
6387 vspltis_shifted (rtx op)
6389 machine_mode mode = GET_MODE (op);
6390 machine_mode inner = GET_MODE_INNER (mode);
6398 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6401 /* We need to create pseudo registers to do the shift, so don't recognize
6402 shift vector constants after reload. */
6403 if (!can_create_pseudo_p ())
6406 nunits = GET_MODE_NUNITS (mode);
6407 mask = GET_MODE_MASK (inner);
6409 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6411 /* Check if the value can really be the operand of a vspltis[bhw]. */
6412 if (EASY_VECTOR_15 (val))
6415 /* Also check if we are loading up the most significant bit which can be done
6416 by loading up -1 and shifting the value left by -1. */
6417 else if (EASY_VECTOR_MSB (val, inner))
6423 /* Check if VAL is present in every STEP-th element until we find elements
6424 that are 0 or all 1 bits. */
6425 for (i = 1; i < nunits; ++i)
6427 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6428 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6430 /* If the value isn't the splat value, check for the remaining elements
6436 for (j = i+1; j < nunits; ++j)
6438 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6439 if (const_vector_elt_as_int (op, elt2) != 0)
6443 return (nunits - i) * GET_MODE_SIZE (inner);
6446 else if ((elt_val & mask) == mask)
6448 for (j = i+1; j < nunits; ++j)
6450 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6451 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6455 return -((nunits - i) * GET_MODE_SIZE (inner));
6463 /* If all elements are equal, we don't need to do VLSDOI. */
6468 /* Return true if OP is of the given MODE and can be synthesized
6469 with a vspltisb, vspltish or vspltisw. */
6472 easy_altivec_constant (rtx op, machine_mode mode)
6474 unsigned step, copies;
6476 if (mode == VOIDmode)
6477 mode = GET_MODE (op);
6478 else if (mode != GET_MODE (op))
6481 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6483 if (mode == V2DFmode)
6484 return zero_constant (op, mode);
6486 else if (mode == V2DImode)
6488 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6489 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6492 if (zero_constant (op, mode))
6495 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6496 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6502 /* V1TImode is a special container for TImode. Ignore for now. */
6503 else if (mode == V1TImode)
6506 /* Start with a vspltisw. */
6507 step = GET_MODE_NUNITS (mode) / 4;
6510 if (vspltis_constant (op, step, copies))
6513 /* Then try with a vspltish. */
6519 if (vspltis_constant (op, step, copies))
6522 /* And finally a vspltisb. */
6528 if (vspltis_constant (op, step, copies))
6531 if (vspltis_shifted (op) != 0)
6537 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6538 result is OP. Abort if it is not possible. */
6541 gen_easy_altivec_constant (rtx op)
6543 machine_mode mode = GET_MODE (op);
6544 int nunits = GET_MODE_NUNITS (mode);
6545 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6546 unsigned step = nunits / 4;
6547 unsigned copies = 1;
6549 /* Start with a vspltisw. */
6550 if (vspltis_constant (op, step, copies))
6551 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6553 /* Then try with a vspltish. */
6559 if (vspltis_constant (op, step, copies))
6560 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6562 /* And finally a vspltisb. */
6568 if (vspltis_constant (op, step, copies))
6569 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6574 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6575 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6577 Return the number of instructions needed (1 or 2) into the address pointed
6580 Return the constant that is being split via CONSTANT_PTR. */
6583 xxspltib_constant_p (rtx op,
6588 size_t nunits = GET_MODE_NUNITS (mode);
6590 HOST_WIDE_INT value;
6593 /* Set the returned values to out of bound values. */
6594 *num_insns_ptr = -1;
6595 *constant_ptr = 256;
6597 if (!TARGET_P9_VECTOR)
6600 if (mode == VOIDmode)
6601 mode = GET_MODE (op);
6603 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6606 /* Handle (vec_duplicate <constant>). */
6607 if (GET_CODE (op) == VEC_DUPLICATE)
6609 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6610 && mode != V2DImode)
6613 element = XEXP (op, 0);
6614 if (!CONST_INT_P (element))
6617 value = INTVAL (element);
6618 if (!IN_RANGE (value, -128, 127))
6622 /* Handle (const_vector [...]). */
6623 else if (GET_CODE (op) == CONST_VECTOR)
6625 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6626 && mode != V2DImode)
6629 element = CONST_VECTOR_ELT (op, 0);
6630 if (!CONST_INT_P (element))
6633 value = INTVAL (element);
6634 if (!IN_RANGE (value, -128, 127))
6637 for (i = 1; i < nunits; i++)
6639 element = CONST_VECTOR_ELT (op, i);
6640 if (!CONST_INT_P (element))
6643 if (value != INTVAL (element))
6648 /* Handle integer constants being loaded into the upper part of the VSX
6649 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6650 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6651 else if (CONST_INT_P (op))
6653 if (!SCALAR_INT_MODE_P (mode))
6656 value = INTVAL (op);
6657 if (!IN_RANGE (value, -128, 127))
6660 if (!IN_RANGE (value, -1, 0))
6662 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6665 if (EASY_VECTOR_15 (value))
6673 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6674 sign extend. Special case 0/-1 to allow getting any VSX register instead
6675 of an Altivec register. */
6676 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6677 && EASY_VECTOR_15 (value))
6680 /* Return # of instructions and the constant byte for XXSPLTIB. */
6681 if (mode == V16QImode)
6684 else if (IN_RANGE (value, -1, 0))
6690 *constant_ptr = (int) value;
6695 output_vec_const_move (rtx *operands)
6703 mode = GET_MODE (dest);
6707 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6708 int xxspltib_value = 256;
6711 if (zero_constant (vec, mode))
6713 if (TARGET_P9_VECTOR)
6714 return "xxspltib %x0,0";
6716 else if (dest_vmx_p)
6717 return "vspltisw %0,0";
6720 return "xxlxor %x0,%x0,%x0";
6723 if (all_ones_constant (vec, mode))
6725 if (TARGET_P9_VECTOR)
6726 return "xxspltib %x0,255";
6728 else if (dest_vmx_p)
6729 return "vspltisw %0,-1";
6731 else if (TARGET_P8_VECTOR)
6732 return "xxlorc %x0,%x0,%x0";
6738 if (TARGET_P9_VECTOR
6739 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6743 operands[2] = GEN_INT (xxspltib_value & 0xff);
6744 return "xxspltib %x0,%2";
6755 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6756 if (zero_constant (vec, mode))
6757 return "vspltisw %0,0";
6759 if (all_ones_constant (vec, mode))
6760 return "vspltisw %0,-1";
6762 /* Do we need to construct a value using VSLDOI? */
6763 shift = vspltis_shifted (vec);
6767 splat_vec = gen_easy_altivec_constant (vec);
6768 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6769 operands[1] = XEXP (splat_vec, 0);
6770 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6773 switch (GET_MODE (splat_vec))
6776 return "vspltisw %0,%1";
6779 return "vspltish %0,%1";
6782 return "vspltisb %0,%1";
6792 /* Initialize TARGET of vector PAIRED to VALS. */
6795 paired_expand_vector_init (rtx target, rtx vals)
6797 machine_mode mode = GET_MODE (target);
6798 int n_elts = GET_MODE_NUNITS (mode);
6800 rtx x, new_rtx, tmp, constant_op, op1, op2;
6803 for (i = 0; i < n_elts; ++i)
6805 x = XVECEXP (vals, 0, i);
6806 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6811 /* Load from constant pool. */
6812 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
6818 /* The vector is initialized only with non-constants. */
6819 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
6820 XVECEXP (vals, 0, 1));
6822 emit_move_insn (target, new_rtx);
6826 /* One field is non-constant and the other one is a constant. Load the
6827 constant from the constant pool and use ps_merge instruction to
6828 construct the whole vector. */
6829 op1 = XVECEXP (vals, 0, 0);
6830 op2 = XVECEXP (vals, 0, 1);
6832 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
6834 tmp = gen_reg_rtx (GET_MODE (constant_op));
6835 emit_move_insn (tmp, constant_op);
6837 if (CONSTANT_P (op1))
6838 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
6840 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
6842 emit_move_insn (target, new_rtx);
6846 paired_expand_vector_move (rtx operands[])
6848 rtx op0 = operands[0], op1 = operands[1];
6850 emit_move_insn (op0, op1);
6853 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6854 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6855 operands for the relation operation COND. This is a recursive
6859 paired_emit_vector_compare (enum rtx_code rcode,
6860 rtx dest, rtx op0, rtx op1,
6861 rtx cc_op0, rtx cc_op1)
6863 rtx tmp = gen_reg_rtx (V2SFmode);
6866 gcc_assert (TARGET_PAIRED_FLOAT);
6867 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
6873 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6877 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6878 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
6882 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
6885 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6888 tmp1 = gen_reg_rtx (V2SFmode);
6889 max = gen_reg_rtx (V2SFmode);
6890 min = gen_reg_rtx (V2SFmode);
6891 gen_reg_rtx (V2SFmode);
6893 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6894 emit_insn (gen_selv2sf4
6895 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6896 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
6897 emit_insn (gen_selv2sf4
6898 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6899 emit_insn (gen_subv2sf3 (tmp1, min, max));
6900 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
6903 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
6906 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6909 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
6912 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6915 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
6924 /* Emit vector conditional expression.
6925 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6926 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6929 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
6930 rtx cond, rtx cc_op0, rtx cc_op1)
6932 enum rtx_code rcode = GET_CODE (cond);
6934 if (!TARGET_PAIRED_FLOAT)
6937 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
6942 /* Initialize vector TARGET to VALS. */
6945 rs6000_expand_vector_init (rtx target, rtx vals)
6947 machine_mode mode = GET_MODE (target);
6948 machine_mode inner_mode = GET_MODE_INNER (mode);
6949 int n_elts = GET_MODE_NUNITS (mode);
6950 int n_var = 0, one_var = -1;
6951 bool all_same = true, all_const_zero = true;
6955 for (i = 0; i < n_elts; ++i)
6957 x = XVECEXP (vals, 0, i);
6958 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6959 ++n_var, one_var = i;
6960 else if (x != CONST0_RTX (inner_mode))
6961 all_const_zero = false;
6963 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6969 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6970 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6971 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6973 /* Zero register. */
6974 emit_move_insn (target, CONST0_RTX (mode));
6977 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6979 /* Splat immediate. */
6980 emit_insn (gen_rtx_SET (target, const_vec));
6985 /* Load from constant pool. */
6986 emit_move_insn (target, const_vec);
6991 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6992 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6996 size_t num_elements = all_same ? 1 : 2;
6997 for (i = 0; i < num_elements; i++)
6999 op[i] = XVECEXP (vals, 0, i);
7000 /* Just in case there is a SUBREG with a smaller mode, do a
7002 if (GET_MODE (op[i]) != inner_mode)
7004 rtx tmp = gen_reg_rtx (inner_mode);
7005 convert_move (tmp, op[i], 0);
7008 /* Allow load with splat double word. */
7009 else if (MEM_P (op[i]))
7012 op[i] = force_reg (inner_mode, op[i]);
7014 else if (!REG_P (op[i]))
7015 op[i] = force_reg (inner_mode, op[i]);
7020 if (mode == V2DFmode)
7021 emit_insn (gen_vsx_splat_v2df (target, op[0]));
7023 emit_insn (gen_vsx_splat_v2di (target, op[0]));
7027 if (mode == V2DFmode)
7028 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
7030 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
7035 /* Special case initializing vector int if we are on 64-bit systems with
7036 direct move or we have the ISA 3.0 instructions. */
7037 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
7038 && TARGET_DIRECT_MOVE_64BIT)
7042 rtx element0 = XVECEXP (vals, 0, 0);
7043 if (MEM_P (element0))
7044 element0 = rs6000_address_for_fpconvert (element0);
7046 element0 = force_reg (SImode, element0);
7048 if (TARGET_P9_VECTOR)
7049 emit_insn (gen_vsx_splat_v4si (target, element0));
7052 rtx tmp = gen_reg_rtx (DImode);
7053 emit_insn (gen_zero_extendsidi2 (tmp, element0));
7054 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
7063 for (i = 0; i < 4; i++)
7065 elements[i] = XVECEXP (vals, 0, i);
7066 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
7067 elements[i] = copy_to_mode_reg (SImode, elements[i]);
7070 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
7071 elements[2], elements[3]));
7076 /* With single precision floating point on VSX, know that internally single
7077 precision is actually represented as a double, and either make 2 V2DF
7078 vectors, and convert these vectors to single precision, or do one
7079 conversion, and splat the result to the other elements. */
7080 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
7084 rtx element0 = XVECEXP (vals, 0, 0);
7086 if (TARGET_P9_VECTOR)
7088 if (MEM_P (element0))
7089 element0 = rs6000_address_for_fpconvert (element0);
7091 emit_insn (gen_vsx_splat_v4sf (target, element0));
7096 rtx freg = gen_reg_rtx (V4SFmode);
7097 rtx sreg = force_reg (SFmode, element0);
7098 rtx cvt = (TARGET_XSCVDPSPN
7099 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
7100 : gen_vsx_xscvdpsp_scalar (freg, sreg));
7103 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
7109 rtx dbl_even = gen_reg_rtx (V2DFmode);
7110 rtx dbl_odd = gen_reg_rtx (V2DFmode);
7111 rtx flt_even = gen_reg_rtx (V4SFmode);
7112 rtx flt_odd = gen_reg_rtx (V4SFmode);
7113 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
7114 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
7115 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
7116 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
7118 /* Use VMRGEW if we can instead of doing a permute. */
7119 if (TARGET_P8_VECTOR)
7121 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
7122 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
7123 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7124 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7125 if (BYTES_BIG_ENDIAN)
7126 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
7128 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
7132 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
7133 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
7134 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7135 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7136 rs6000_expand_extract_even (target, flt_even, flt_odd);
7142 /* Special case initializing vector short/char that are splats if we are on
7143 64-bit systems with direct move. */
7144 if (all_same && TARGET_DIRECT_MOVE_64BIT
7145 && (mode == V16QImode || mode == V8HImode))
7147 rtx op0 = XVECEXP (vals, 0, 0);
7148 rtx di_tmp = gen_reg_rtx (DImode);
7151 op0 = force_reg (GET_MODE_INNER (mode), op0);
7153 if (mode == V16QImode)
7155 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
7156 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
7160 if (mode == V8HImode)
7162 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
7163 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
7168 /* Store value to stack temp. Load vector element. Splat. However, splat
7169 of 64-bit items is not supported on Altivec. */
7170 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
7172 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7173 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
7174 XVECEXP (vals, 0, 0));
7175 x = gen_rtx_UNSPEC (VOIDmode,
7176 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7177 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7179 gen_rtx_SET (target, mem),
7181 x = gen_rtx_VEC_SELECT (inner_mode, target,
7182 gen_rtx_PARALLEL (VOIDmode,
7183 gen_rtvec (1, const0_rtx)));
7184 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
7188 /* One field is non-constant. Load constant then overwrite
7192 rtx copy = copy_rtx (vals);
7194 /* Load constant part of vector, substitute neighboring value for
7196 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
7197 rs6000_expand_vector_init (target, copy);
7199 /* Insert variable. */
7200 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7204 /* Construct the vector in memory one field at a time
7205 and load the whole vector. */
7206 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7207 for (i = 0; i < n_elts; i++)
7208 emit_move_insn (adjust_address_nv (mem, inner_mode,
7209 i * GET_MODE_SIZE (inner_mode)),
7210 XVECEXP (vals, 0, i));
7211 emit_move_insn (target, mem);
7214 /* Set field ELT of TARGET to VAL. */
7217 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7219 machine_mode mode = GET_MODE (target);
7220 machine_mode inner_mode = GET_MODE_INNER (mode);
7221 rtx reg = gen_reg_rtx (mode);
7223 int width = GET_MODE_SIZE (inner_mode);
7226 val = force_reg (GET_MODE (val), val);
7228 if (VECTOR_MEM_VSX_P (mode))
7230 rtx insn = NULL_RTX;
7231 rtx elt_rtx = GEN_INT (elt);
7233 if (mode == V2DFmode)
7234 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7236 else if (mode == V2DImode)
7237 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7239 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7241 if (mode == V4SImode)
7242 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7243 else if (mode == V8HImode)
7244 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7245 else if (mode == V16QImode)
7246 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7247 else if (mode == V4SFmode)
7248 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7258 /* Simplify setting single element vectors like V1TImode. */
7259 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7261 emit_move_insn (target, gen_lowpart (mode, val));
7265 /* Load single variable value. */
7266 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7267 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7268 x = gen_rtx_UNSPEC (VOIDmode,
7269 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7270 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7272 gen_rtx_SET (reg, mem),
7275 /* Linear sequence. */
7276 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7277 for (i = 0; i < 16; ++i)
7278 XVECEXP (mask, 0, i) = GEN_INT (i);
7280 /* Set permute mask to insert element into target. */
7281 for (i = 0; i < width; ++i)
7282 XVECEXP (mask, 0, elt*width + i)
7283 = GEN_INT (i + 0x10);
7284 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7286 if (BYTES_BIG_ENDIAN)
7287 x = gen_rtx_UNSPEC (mode,
7288 gen_rtvec (3, target, reg,
7289 force_reg (V16QImode, x)),
7293 if (TARGET_P9_VECTOR)
7294 x = gen_rtx_UNSPEC (mode,
7295 gen_rtvec (3, target, reg,
7296 force_reg (V16QImode, x)),
7300 /* Invert selector. We prefer to generate VNAND on P8 so
7301 that future fusion opportunities can kick in, but must
7302 generate VNOR elsewhere. */
7303 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7304 rtx iorx = (TARGET_P8_VECTOR
7305 ? gen_rtx_IOR (V16QImode, notx, notx)
7306 : gen_rtx_AND (V16QImode, notx, notx));
7307 rtx tmp = gen_reg_rtx (V16QImode);
7308 emit_insn (gen_rtx_SET (tmp, iorx));
7310 /* Permute with operands reversed and adjusted selector. */
7311 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7316 emit_insn (gen_rtx_SET (target, x));
7319 /* Extract field ELT from VEC into TARGET. */
7322 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7324 machine_mode mode = GET_MODE (vec);
7325 machine_mode inner_mode = GET_MODE_INNER (mode);
7328 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7335 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7336 emit_move_insn (target, gen_lowpart (TImode, vec));
7339 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7342 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7345 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7348 if (TARGET_DIRECT_MOVE_64BIT)
7350 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7356 if (TARGET_DIRECT_MOVE_64BIT)
7358 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7364 if (TARGET_DIRECT_MOVE_64BIT)
7366 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7372 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7373 && TARGET_DIRECT_MOVE_64BIT)
7375 if (GET_MODE (elt) != DImode)
7377 rtx tmp = gen_reg_rtx (DImode);
7378 convert_move (tmp, elt, 0);
7381 else if (!REG_P (elt))
7382 elt = force_reg (DImode, elt);
7387 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7391 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7395 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7399 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7403 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7407 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7415 gcc_assert (CONST_INT_P (elt));
7417 /* Allocate mode-sized buffer. */
7418 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7420 emit_move_insn (mem, vec);
7422 /* Add offset to field within buffer matching vector element. */
7423 mem = adjust_address_nv (mem, inner_mode,
7424 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7426 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7429 /* Helper function to return the register number of a RTX. */
7431 regno_or_subregno (rtx op)
7435 else if (SUBREG_P (op))
7436 return subreg_regno (op);
7441 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7442 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7443 temporary (BASE_TMP) to fixup the address. Return the new memory address
7444 that is valid for reads or writes to a given register (SCALAR_REG). */
7447 rs6000_adjust_vec_address (rtx scalar_reg,
7451 machine_mode scalar_mode)
7453 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7454 rtx addr = XEXP (mem, 0);
7459 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7460 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7462 /* Calculate what we need to add to the address to get the element
7464 if (CONST_INT_P (element))
7465 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7468 int byte_shift = exact_log2 (scalar_size);
7469 gcc_assert (byte_shift >= 0);
7471 if (byte_shift == 0)
7472 element_offset = element;
7476 if (TARGET_POWERPC64)
7477 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7479 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7481 element_offset = base_tmp;
7485 /* Create the new address pointing to the element within the vector. If we
7486 are adding 0, we don't have to change the address. */
7487 if (element_offset == const0_rtx)
7490 /* A simple indirect address can be converted into a reg + offset
7492 else if (REG_P (addr) || SUBREG_P (addr))
7493 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7495 /* Optimize D-FORM addresses with constant offset with a constant element, to
7496 include the element offset in the address directly. */
7497 else if (GET_CODE (addr) == PLUS)
7499 rtx op0 = XEXP (addr, 0);
7500 rtx op1 = XEXP (addr, 1);
7503 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7504 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7506 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7507 rtx offset_rtx = GEN_INT (offset);
7509 if (IN_RANGE (offset, -32768, 32767)
7510 && (scalar_size < 8 || (offset & 0x3) == 0))
7511 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7514 emit_move_insn (base_tmp, offset_rtx);
7515 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7520 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7521 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7523 /* Note, ADDI requires the register being added to be a base
7524 register. If the register was R0, load it up into the temporary
7527 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7529 insn = gen_add3_insn (base_tmp, op1, element_offset);
7530 gcc_assert (insn != NULL_RTX);
7535 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7537 insn = gen_add3_insn (base_tmp, element_offset, op1);
7538 gcc_assert (insn != NULL_RTX);
7544 emit_move_insn (base_tmp, op1);
7545 emit_insn (gen_add2_insn (base_tmp, element_offset));
7548 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7554 emit_move_insn (base_tmp, addr);
7555 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7558 /* If we have a PLUS, we need to see whether the particular register class
7559 allows for D-FORM or X-FORM addressing. */
7560 if (GET_CODE (new_addr) == PLUS)
7562 rtx op1 = XEXP (new_addr, 1);
7563 addr_mask_type addr_mask;
7564 int scalar_regno = regno_or_subregno (scalar_reg);
7566 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7567 if (INT_REGNO_P (scalar_regno))
7568 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7570 else if (FP_REGNO_P (scalar_regno))
7571 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7573 else if (ALTIVEC_REGNO_P (scalar_regno))
7574 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7579 if (REG_P (op1) || SUBREG_P (op1))
7580 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7582 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7585 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7586 valid_addr_p = true;
7589 valid_addr_p = false;
7593 emit_move_insn (base_tmp, new_addr);
7594 new_addr = base_tmp;
7597 return change_address (mem, scalar_mode, new_addr);
7600 /* Split a variable vec_extract operation into the component instructions. */
7603 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7606 machine_mode mode = GET_MODE (src);
7607 machine_mode scalar_mode = GET_MODE (dest);
7608 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7609 int byte_shift = exact_log2 (scalar_size);
7611 gcc_assert (byte_shift >= 0);
7613 /* If we are given a memory address, optimize to load just the element. We
7614 don't have to adjust the vector element number on little endian
7618 gcc_assert (REG_P (tmp_gpr));
7619 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7620 tmp_gpr, scalar_mode));
7624 else if (REG_P (src) || SUBREG_P (src))
7626 int bit_shift = byte_shift + 3;
7628 int dest_regno = regno_or_subregno (dest);
7629 int src_regno = regno_or_subregno (src);
7630 int element_regno = regno_or_subregno (element);
7632 gcc_assert (REG_P (tmp_gpr));
7634 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7635 a general purpose register. */
7636 if (TARGET_P9_VECTOR
7637 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7638 && INT_REGNO_P (dest_regno)
7639 && ALTIVEC_REGNO_P (src_regno)
7640 && INT_REGNO_P (element_regno))
7642 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7643 rtx element_si = gen_rtx_REG (SImode, element_regno);
7645 if (mode == V16QImode)
7646 emit_insn (VECTOR_ELT_ORDER_BIG
7647 ? gen_vextublx (dest_si, element_si, src)
7648 : gen_vextubrx (dest_si, element_si, src));
7650 else if (mode == V8HImode)
7652 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7653 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7654 emit_insn (VECTOR_ELT_ORDER_BIG
7655 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7656 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7662 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7663 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7664 emit_insn (VECTOR_ELT_ORDER_BIG
7665 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7666 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7673 gcc_assert (REG_P (tmp_altivec));
7675 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7676 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7677 will shift the element into the upper position (adding 3 to convert a
7678 byte shift into a bit shift). */
7679 if (scalar_size == 8)
7681 if (!VECTOR_ELT_ORDER_BIG)
7683 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7689 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7691 emit_insn (gen_rtx_SET (tmp_gpr,
7692 gen_rtx_AND (DImode,
7693 gen_rtx_ASHIFT (DImode,
7700 if (!VECTOR_ELT_ORDER_BIG)
7702 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7704 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7705 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7711 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7714 /* Get the value into the lower byte of the Altivec register where VSLO
7716 if (TARGET_P9_VECTOR)
7717 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7718 else if (can_create_pseudo_p ())
7719 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7722 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7723 emit_move_insn (tmp_di, tmp_gpr);
7724 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7727 /* Do the VSLO to get the value into the final location. */
7731 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7735 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7740 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7741 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7742 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7743 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7746 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7754 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7755 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7756 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7757 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7759 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7760 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7761 GEN_INT (64 - (8 * scalar_size))));
7775 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7776 two SImode values. */
7779 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7781 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7783 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7785 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7786 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7788 emit_move_insn (dest, GEN_INT (const1 | const2));
7792 /* Put si1 into upper 32-bits of dest. */
7793 if (CONST_INT_P (si1))
7794 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7797 /* Generate RLDIC. */
7798 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7799 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7800 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7801 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7802 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7803 emit_insn (gen_rtx_SET (dest, and_rtx));
7806 /* Put si2 into the temporary. */
7807 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7808 if (CONST_INT_P (si2))
7809 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7811 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7813 /* Combine the two parts. */
7814 emit_insn (gen_iordi3 (dest, dest, tmp));
7818 /* Split a V4SI initialization. */
7821 rs6000_split_v4si_init (rtx operands[])
7823 rtx dest = operands[0];
7825 /* Destination is a GPR, build up the two DImode parts in place. */
7826 if (REG_P (dest) || SUBREG_P (dest))
7828 int d_regno = regno_or_subregno (dest);
7829 rtx scalar1 = operands[1];
7830 rtx scalar2 = operands[2];
7831 rtx scalar3 = operands[3];
7832 rtx scalar4 = operands[4];
7833 rtx tmp1 = operands[5];
7834 rtx tmp2 = operands[6];
7836 /* Even though we only need one temporary (plus the destination, which
7837 has an early clobber constraint, try to use two temporaries, one for
7838 each double word created. That way the 2nd insn scheduling pass can
7839 rearrange things so the two parts are done in parallel. */
7840 if (BYTES_BIG_ENDIAN)
7842 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7843 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7844 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7845 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7849 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7850 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7851 gcc_assert (!VECTOR_ELT_ORDER_BIG);
7852 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7853 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7862 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7863 selects whether the alignment is abi mandated, optional, or
7864 both abi and optional alignment. */
7867 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7869 if (how != align_opt)
7871 if (TREE_CODE (type) == VECTOR_TYPE)
7873 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
7878 else if (align < 128)
7883 if (how != align_abi)
7885 if (TREE_CODE (type) == ARRAY_TYPE
7886 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7888 if (align < BITS_PER_WORD)
7889 align = BITS_PER_WORD;
7896 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7897 instructions simply ignore the low bits; VSX memory instructions
7898 are aligned to 4 or 8 bytes. */
7901 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7903 return (STRICT_ALIGNMENT
7904 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7905 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7906 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7907 && (int) align < VECTOR_ALIGN (mode)))));
7910 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7913 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7915 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7917 if (computed != 128)
7920 if (!warned && warn_psabi)
7923 inform (input_location,
7924 "the layout of aggregates containing vectors with"
7925 " %d-byte alignment has changed in GCC 5",
7926 computed / BITS_PER_UNIT);
7929 /* In current GCC there is no special case. */
7936 /* AIX increases natural record alignment to doubleword if the first
7937 field is an FP double while the FP fields remain word aligned. */
7940 rs6000_special_round_type_align (tree type, unsigned int computed,
7941 unsigned int specified)
7943 unsigned int align = MAX (computed, specified);
7944 tree field = TYPE_FIELDS (type);
7946 /* Skip all non field decls */
7947 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7948 field = DECL_CHAIN (field);
7950 if (field != NULL && field != type)
7952 type = TREE_TYPE (field);
7953 while (TREE_CODE (type) == ARRAY_TYPE)
7954 type = TREE_TYPE (type);
7956 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7957 align = MAX (align, 64);
7963 /* Darwin increases record alignment to the natural alignment of
7967 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7968 unsigned int specified)
7970 unsigned int align = MAX (computed, specified);
7972 if (TYPE_PACKED (type))
7975 /* Find the first field, looking down into aggregates. */
7977 tree field = TYPE_FIELDS (type);
7978 /* Skip all non field decls */
7979 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7980 field = DECL_CHAIN (field);
7983 /* A packed field does not contribute any extra alignment. */
7984 if (DECL_PACKED (field))
7986 type = TREE_TYPE (field);
7987 while (TREE_CODE (type) == ARRAY_TYPE)
7988 type = TREE_TYPE (type);
7989 } while (AGGREGATE_TYPE_P (type));
7991 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7992 align = MAX (align, TYPE_ALIGN (type));
7997 /* Return 1 for an operand in small memory on V.4/eabi. */
8000 small_data_operand (rtx op ATTRIBUTE_UNUSED,
8001 machine_mode mode ATTRIBUTE_UNUSED)
8006 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
8009 if (DEFAULT_ABI != ABI_V4)
8012 if (GET_CODE (op) == SYMBOL_REF)
8015 else if (GET_CODE (op) != CONST
8016 || GET_CODE (XEXP (op, 0)) != PLUS
8017 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
8018 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
8023 rtx sum = XEXP (op, 0);
8024 HOST_WIDE_INT summand;
8026 /* We have to be careful here, because it is the referenced address
8027 that must be 32k from _SDA_BASE_, not just the symbol. */
8028 summand = INTVAL (XEXP (sum, 1));
8029 if (summand < 0 || summand > g_switch_value)
8032 sym_ref = XEXP (sum, 0);
8035 return SYMBOL_REF_SMALL_P (sym_ref);
8041 /* Return true if either operand is a general purpose register. */
8044 gpr_or_gpr_p (rtx op0, rtx op1)
8046 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
8047 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
8050 /* Return true if this is a move direct operation between GPR registers and
8051 floating point/VSX registers. */
8054 direct_move_p (rtx op0, rtx op1)
8058 if (!REG_P (op0) || !REG_P (op1))
8061 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
8064 regno0 = REGNO (op0);
8065 regno1 = REGNO (op1);
8066 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
8069 if (INT_REGNO_P (regno0))
8070 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
8072 else if (INT_REGNO_P (regno1))
8074 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
8077 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
8084 /* Return true if the OFFSET is valid for the quad address instructions that
8085 use d-form (register + offset) addressing. */
8088 quad_address_offset_p (HOST_WIDE_INT offset)
8090 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
8093 /* Return true if the ADDR is an acceptable address for a quad memory
8094 operation of mode MODE (either LQ/STQ for general purpose registers, or
8095 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8096 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8097 3.0 LXV/STXV instruction. */
8100 quad_address_p (rtx addr, machine_mode mode, bool strict)
8104 if (GET_MODE_SIZE (mode) != 16)
8107 if (legitimate_indirect_address_p (addr, strict))
8110 if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
8113 if (GET_CODE (addr) != PLUS)
8116 op0 = XEXP (addr, 0);
8117 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
8120 op1 = XEXP (addr, 1);
8121 if (!CONST_INT_P (op1))
8124 return quad_address_offset_p (INTVAL (op1));
8127 /* Return true if this is a load or store quad operation. This function does
8128 not handle the atomic quad memory instructions. */
8131 quad_load_store_p (rtx op0, rtx op1)
8135 if (!TARGET_QUAD_MEMORY)
8138 else if (REG_P (op0) && MEM_P (op1))
8139 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
8140 && quad_memory_operand (op1, GET_MODE (op1))
8141 && !reg_overlap_mentioned_p (op0, op1));
8143 else if (MEM_P (op0) && REG_P (op1))
8144 ret = (quad_memory_operand (op0, GET_MODE (op0))
8145 && quad_int_reg_operand (op1, GET_MODE (op1)));
8150 if (TARGET_DEBUG_ADDR)
8152 fprintf (stderr, "\n========== quad_load_store, return %s\n",
8153 ret ? "true" : "false");
8154 debug_rtx (gen_rtx_SET (op0, op1));
8160 /* Given an address, return a constant offset term if one exists. */
8163 address_offset (rtx op)
8165 if (GET_CODE (op) == PRE_INC
8166 || GET_CODE (op) == PRE_DEC)
8168 else if (GET_CODE (op) == PRE_MODIFY
8169 || GET_CODE (op) == LO_SUM)
8172 if (GET_CODE (op) == CONST)
8175 if (GET_CODE (op) == PLUS)
8178 if (CONST_INT_P (op))
8184 /* Return true if the MEM operand is a memory operand suitable for use
8185 with a (full width, possibly multiple) gpr load/store. On
8186 powerpc64 this means the offset must be divisible by 4.
8187 Implements 'Y' constraint.
8189 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8190 a constraint function we know the operand has satisfied a suitable
8191 memory predicate. Also accept some odd rtl generated by reload
8192 (see rs6000_legitimize_reload_address for various forms). It is
8193 important that reload rtl be accepted by appropriate constraints
8194 but not by the operand predicate.
8196 Offsetting a lo_sum should not be allowed, except where we know by
8197 alignment that a 32k boundary is not crossed, but see the ???
8198 comment in rs6000_legitimize_reload_address. Note that by
8199 "offsetting" here we mean a further offset to access parts of the
8200 MEM. It's fine to have a lo_sum where the inner address is offset
8201 from a sym, since the same sym+offset will appear in the high part
8202 of the address calculation. */
8205 mem_operand_gpr (rtx op, machine_mode mode)
8207 unsigned HOST_WIDE_INT offset;
8209 rtx addr = XEXP (op, 0);
8211 op = address_offset (addr);
8215 offset = INTVAL (op);
8216 if (TARGET_POWERPC64 && (offset & 3) != 0)
8219 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8223 if (GET_CODE (addr) == LO_SUM)
8224 /* For lo_sum addresses, we must allow any offset except one that
8225 causes a wrap, so test only the low 16 bits. */
8226 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8228 return offset + 0x8000 < 0x10000u - extra;
8231 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8232 enforce an offset divisible by 4 even for 32-bit. */
8235 mem_operand_ds_form (rtx op, machine_mode mode)
8237 unsigned HOST_WIDE_INT offset;
8239 rtx addr = XEXP (op, 0);
8241 if (!offsettable_address_p (false, mode, addr))
8244 op = address_offset (addr);
8248 offset = INTVAL (op);
8249 if ((offset & 3) != 0)
8252 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8256 if (GET_CODE (addr) == LO_SUM)
8257 /* For lo_sum addresses, we must allow any offset except one that
8258 causes a wrap, so test only the low 16 bits. */
8259 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8261 return offset + 0x8000 < 0x10000u - extra;
8264 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8267 reg_offset_addressing_ok_p (machine_mode mode)
8281 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8282 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8283 a vector mode, if we want to use the VSX registers to move it around,
8284 we need to restrict ourselves to reg+reg addressing. Similarly for
8285 IEEE 128-bit floating point that is passed in a single vector
8287 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8288 return mode_supports_vsx_dform_quad (mode);
8293 /* Paired vector modes. Only reg+reg addressing is valid. */
8294 if (TARGET_PAIRED_FLOAT)
8299 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8300 addressing for the LFIWZX and STFIWX instructions. */
8301 if (TARGET_NO_SDMODE_STACK)
8313 virtual_stack_registers_memory_p (rtx op)
8317 if (GET_CODE (op) == REG)
8318 regnum = REGNO (op);
8320 else if (GET_CODE (op) == PLUS
8321 && GET_CODE (XEXP (op, 0)) == REG
8322 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8323 regnum = REGNO (XEXP (op, 0));
8328 return (regnum >= FIRST_VIRTUAL_REGISTER
8329 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8332 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8333 is known to not straddle a 32k boundary. This function is used
8334 to determine whether -mcmodel=medium code can use TOC pointer
8335 relative addressing for OP. This means the alignment of the TOC
8336 pointer must also be taken into account, and unfortunately that is
8339 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8340 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8344 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8348 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8350 if (GET_CODE (op) != SYMBOL_REF)
8353 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8355 if (mode_supports_vsx_dform_quad (mode))
8358 dsize = GET_MODE_SIZE (mode);
8359 decl = SYMBOL_REF_DECL (op);
8365 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8366 replacing memory addresses with an anchor plus offset. We
8367 could find the decl by rummaging around in the block->objects
8368 VEC for the given offset but that seems like too much work. */
8369 dalign = BITS_PER_UNIT;
8370 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8371 && SYMBOL_REF_ANCHOR_P (op)
8372 && SYMBOL_REF_BLOCK (op) != NULL)
8374 struct object_block *block = SYMBOL_REF_BLOCK (op);
8376 dalign = block->alignment;
8377 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8379 else if (CONSTANT_POOL_ADDRESS_P (op))
8381 /* It would be nice to have get_pool_align().. */
8382 machine_mode cmode = get_pool_mode (op);
8384 dalign = GET_MODE_ALIGNMENT (cmode);
8387 else if (DECL_P (decl))
8389 dalign = DECL_ALIGN (decl);
8393 /* Allow BLKmode when the entire object is known to not
8394 cross a 32k boundary. */
8395 if (!DECL_SIZE_UNIT (decl))
8398 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8401 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8405 dalign /= BITS_PER_UNIT;
8406 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8407 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8408 return dalign >= dsize;
8414 /* Find how many bits of the alignment we know for this access. */
8415 dalign /= BITS_PER_UNIT;
8416 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8417 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8419 lsb = offset & -offset;
8423 return dalign >= dsize;
8427 constant_pool_expr_p (rtx op)
8431 split_const (op, &base, &offset);
8432 return (GET_CODE (base) == SYMBOL_REF
8433 && CONSTANT_POOL_ADDRESS_P (base)
8434 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8437 /* These are only used to pass through from print_operand/print_operand_address
8438 to rs6000_output_addr_const_extra over the intervening function
8439 output_addr_const which is not target code. */
8440 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8442 /* Return true if OP is a toc pointer relative address (the output
8443 of create_TOC_reference). If STRICT, do not match non-split
8444 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8445 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8446 TOCREL_OFFSET_RET respectively. */
8449 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8450 const_rtx *tocrel_offset_ret)
8455 if (TARGET_CMODEL != CMODEL_SMALL)
8457 /* When strict ensure we have everything tidy. */
8459 && !(GET_CODE (op) == LO_SUM
8460 && REG_P (XEXP (op, 0))
8461 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8464 /* When not strict, allow non-split TOC addresses and also allow
8465 (lo_sum (high ..)) TOC addresses created during reload. */
8466 if (GET_CODE (op) == LO_SUM)
8470 const_rtx tocrel_base = op;
8471 const_rtx tocrel_offset = const0_rtx;
8473 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8475 tocrel_base = XEXP (op, 0);
8476 tocrel_offset = XEXP (op, 1);
8479 if (tocrel_base_ret)
8480 *tocrel_base_ret = tocrel_base;
8481 if (tocrel_offset_ret)
8482 *tocrel_offset_ret = tocrel_offset;
8484 return (GET_CODE (tocrel_base) == UNSPEC
8485 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8488 /* Return true if X is a constant pool address, and also for cmodel=medium
8489 if X is a toc-relative address known to be offsettable within MODE. */
8492 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8495 const_rtx tocrel_base, tocrel_offset;
8496 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8497 && (TARGET_CMODEL != CMODEL_MEDIUM
8498 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8500 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8501 INTVAL (tocrel_offset), mode)));
8505 legitimate_small_data_p (machine_mode mode, rtx x)
8507 return (DEFAULT_ABI == ABI_V4
8508 && !flag_pic && !TARGET_TOC
8509 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8510 && small_data_operand (x, mode));
8514 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8515 bool strict, bool worst_case)
8517 unsigned HOST_WIDE_INT offset;
8520 if (GET_CODE (x) != PLUS)
8522 if (!REG_P (XEXP (x, 0)))
8524 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8526 if (mode_supports_vsx_dform_quad (mode))
8527 return quad_address_p (x, mode, strict);
8528 if (!reg_offset_addressing_ok_p (mode))
8529 return virtual_stack_registers_memory_p (x);
8530 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8532 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8535 offset = INTVAL (XEXP (x, 1));
8541 /* Paired single modes: offset addressing isn't valid. */
8547 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8549 if (VECTOR_MEM_VSX_P (mode))
8554 if (!TARGET_POWERPC64)
8556 else if (offset & 3)
8569 if (!TARGET_POWERPC64)
8571 else if (offset & 3)
8580 return offset < 0x10000 - extra;
8584 legitimate_indexed_address_p (rtx x, int strict)
8588 if (GET_CODE (x) != PLUS)
8594 return (REG_P (op0) && REG_P (op1)
8595 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8596 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8597 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8598 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8602 avoiding_indexed_address_p (machine_mode mode)
8604 /* Avoid indexed addressing for modes that have non-indexed
8605 load/store instruction forms. */
8606 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8610 legitimate_indirect_address_p (rtx x, int strict)
8612 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8616 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8618 if (!TARGET_MACHO || !flag_pic
8619 || mode != SImode || GET_CODE (x) != MEM)
8623 if (GET_CODE (x) != LO_SUM)
8625 if (GET_CODE (XEXP (x, 0)) != REG)
8627 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8631 return CONSTANT_P (x);
8635 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8637 if (GET_CODE (x) != LO_SUM)
8639 if (GET_CODE (XEXP (x, 0)) != REG)
8641 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8643 /* quad word addresses are restricted, and we can't use LO_SUM. */
8644 if (mode_supports_vsx_dform_quad (mode))
8648 if (TARGET_ELF || TARGET_MACHO)
8652 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8654 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8655 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8656 recognizes some LO_SUM addresses as valid although this
8657 function says opposite. In most cases, LRA through different
8658 transformations can generate correct code for address reloads.
8659 It can not manage only some LO_SUM cases. So we need to add
8660 code analogous to one in rs6000_legitimize_reload_address for
8661 LOW_SUM here saying that some addresses are still valid. */
8662 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8663 && small_toc_ref (x, VOIDmode));
8664 if (TARGET_TOC && ! large_toc_ok)
8666 if (GET_MODE_NUNITS (mode) != 1)
8668 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8669 && !(/* ??? Assume floating point reg based on mode? */
8670 TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
8671 && (mode == DFmode || mode == DDmode)))
8674 return CONSTANT_P (x) || large_toc_ok;
8681 /* Try machine-dependent ways of modifying an illegitimate address
8682 to be legitimate. If we find one, return the new, valid address.
8683 This is used from only one place: `memory_address' in explow.c.
8685 OLDX is the address as it was before break_out_memory_refs was
8686 called. In some cases it is useful to look at this to decide what
8689 It is always safe for this function to do nothing. It exists to
8690 recognize opportunities to optimize the output.
8692 On RS/6000, first check for the sum of a register with a constant
8693 integer that is out of range. If so, generate code to add the
8694 constant with the low-order 16 bits masked to the register and force
8695 this result into another register (this can be done with `cau').
8696 Then generate an address of REG+(CONST&0xffff), allowing for the
8697 possibility of bit 16 being a one.
8699 Then check for the sum of a register and something not constant, try to
8700 load the other things into a register and return the sum. */
8703 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8708 if (!reg_offset_addressing_ok_p (mode)
8709 || mode_supports_vsx_dform_quad (mode))
8711 if (virtual_stack_registers_memory_p (x))
8714 /* In theory we should not be seeing addresses of the form reg+0,
8715 but just in case it is generated, optimize it away. */
8716 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8717 return force_reg (Pmode, XEXP (x, 0));
8719 /* For TImode with load/store quad, restrict addresses to just a single
8720 pointer, so it works with both GPRs and VSX registers. */
8721 /* Make sure both operands are registers. */
8722 else if (GET_CODE (x) == PLUS
8723 && (mode != TImode || !TARGET_VSX))
8724 return gen_rtx_PLUS (Pmode,
8725 force_reg (Pmode, XEXP (x, 0)),
8726 force_reg (Pmode, XEXP (x, 1)));
8728 return force_reg (Pmode, x);
8730 if (GET_CODE (x) == SYMBOL_REF)
8732 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8734 return rs6000_legitimize_tls_address (x, model);
8746 /* As in legitimate_offset_address_p we do not assume
8747 worst-case. The mode here is just a hint as to the registers
8748 used. A TImode is usually in gprs, but may actually be in
8749 fprs. Leave worst-case scenario for reload to handle via
8750 insn constraints. PTImode is only GPRs. */
8757 if (GET_CODE (x) == PLUS
8758 && GET_CODE (XEXP (x, 0)) == REG
8759 && GET_CODE (XEXP (x, 1)) == CONST_INT
8760 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8762 && !PAIRED_VECTOR_MODE (mode))
8764 HOST_WIDE_INT high_int, low_int;
8766 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8767 if (low_int >= 0x8000 - extra)
8769 high_int = INTVAL (XEXP (x, 1)) - low_int;
8770 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8771 GEN_INT (high_int)), 0);
8772 return plus_constant (Pmode, sum, low_int);
8774 else if (GET_CODE (x) == PLUS
8775 && GET_CODE (XEXP (x, 0)) == REG
8776 && GET_CODE (XEXP (x, 1)) != CONST_INT
8777 && GET_MODE_NUNITS (mode) == 1
8778 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8779 || (/* ??? Assume floating point reg based on mode? */
8780 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8781 && (mode == DFmode || mode == DDmode)))
8782 && !avoiding_indexed_address_p (mode))
8784 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8785 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8787 else if (PAIRED_VECTOR_MODE (mode))
8791 /* We accept [reg + reg]. */
8793 if (GET_CODE (x) == PLUS)
8795 rtx op1 = XEXP (x, 0);
8796 rtx op2 = XEXP (x, 1);
8799 op1 = force_reg (Pmode, op1);
8800 op2 = force_reg (Pmode, op2);
8802 /* We can't always do [reg + reg] for these, because [reg +
8803 reg + offset] is not a legitimate addressing mode. */
8804 y = gen_rtx_PLUS (Pmode, op1, op2);
8806 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
8807 return force_reg (Pmode, y);
8812 return force_reg (Pmode, x);
8814 else if ((TARGET_ELF
8816 || !MACHO_DYNAMIC_NO_PIC_P
8822 && GET_CODE (x) != CONST_INT
8823 && GET_CODE (x) != CONST_WIDE_INT
8824 && GET_CODE (x) != CONST_DOUBLE
8826 && GET_MODE_NUNITS (mode) == 1
8827 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8828 || (/* ??? Assume floating point reg based on mode? */
8829 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8830 && (mode == DFmode || mode == DDmode))))
8832 rtx reg = gen_reg_rtx (Pmode);
8834 emit_insn (gen_elf_high (reg, x));
8836 emit_insn (gen_macho_high (reg, x));
8837 return gen_rtx_LO_SUM (Pmode, reg, x);
8840 && GET_CODE (x) == SYMBOL_REF
8841 && constant_pool_expr_p (x)
8842 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8843 return create_TOC_reference (x, NULL_RTX);
8848 /* Debug version of rs6000_legitimize_address. */
8850 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8856 ret = rs6000_legitimize_address (x, oldx, mode);
8857 insns = get_insns ();
8863 "\nrs6000_legitimize_address: mode %s, old code %s, "
8864 "new code %s, modified\n",
8865 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8866 GET_RTX_NAME (GET_CODE (ret)));
8868 fprintf (stderr, "Original address:\n");
8871 fprintf (stderr, "oldx:\n");
8874 fprintf (stderr, "New address:\n");
8879 fprintf (stderr, "Insns added:\n");
8880 debug_rtx_list (insns, 20);
8886 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8887 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8898 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8899 We need to emit DTP-relative relocations. */
8901 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8903 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8908 fputs ("\t.long\t", file);
8911 fputs (DOUBLE_INT_ASM_OP, file);
8916 output_addr_const (file, x);
8918 fputs ("@dtprel+0x8000", file);
8919 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8921 switch (SYMBOL_REF_TLS_MODEL (x))
8925 case TLS_MODEL_LOCAL_EXEC:
8926 fputs ("@le", file);
8928 case TLS_MODEL_INITIAL_EXEC:
8929 fputs ("@ie", file);
8931 case TLS_MODEL_GLOBAL_DYNAMIC:
8932 case TLS_MODEL_LOCAL_DYNAMIC:
8941 /* Return true if X is a symbol that refers to real (rather than emulated)
8945 rs6000_real_tls_symbol_ref_p (rtx x)
8947 return (GET_CODE (x) == SYMBOL_REF
8948 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8951 /* In the name of slightly smaller debug output, and to cater to
8952 general assembler lossage, recognize various UNSPEC sequences
8953 and turn them back into a direct symbol reference. */
8956 rs6000_delegitimize_address (rtx orig_x)
8960 orig_x = delegitimize_mem_from_attrs (orig_x);
8966 if (TARGET_CMODEL != CMODEL_SMALL
8967 && GET_CODE (y) == LO_SUM)
8971 if (GET_CODE (y) == PLUS
8972 && GET_MODE (y) == Pmode
8973 && CONST_INT_P (XEXP (y, 1)))
8975 offset = XEXP (y, 1);
8979 if (GET_CODE (y) == UNSPEC
8980 && XINT (y, 1) == UNSPEC_TOCREL)
8982 y = XVECEXP (y, 0, 0);
8985 /* Do not associate thread-local symbols with the original
8986 constant pool symbol. */
8988 && GET_CODE (y) == SYMBOL_REF
8989 && CONSTANT_POOL_ADDRESS_P (y)
8990 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8994 if (offset != NULL_RTX)
8995 y = gen_rtx_PLUS (Pmode, y, offset);
8996 if (!MEM_P (orig_x))
8999 return replace_equiv_address_nv (orig_x, y);
9003 && GET_CODE (orig_x) == LO_SUM
9004 && GET_CODE (XEXP (orig_x, 1)) == CONST)
9006 y = XEXP (XEXP (orig_x, 1), 0);
9007 if (GET_CODE (y) == UNSPEC
9008 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
9009 return XVECEXP (y, 0, 0);
9015 /* Return true if X shouldn't be emitted into the debug info.
9016 The linker doesn't like .toc section references from
9017 .debug_* sections, so reject .toc section symbols. */
9020 rs6000_const_not_ok_for_debug_p (rtx x)
9022 if (GET_CODE (x) == UNSPEC)
9024 if (GET_CODE (x) == SYMBOL_REF
9025 && CONSTANT_POOL_ADDRESS_P (x))
9027 rtx c = get_pool_constant (x);
9028 machine_mode cmode = get_pool_mode (x);
9029 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
9037 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9040 rs6000_legitimate_combined_insn (rtx_insn *insn)
9042 int icode = INSN_CODE (insn);
9044 /* Reject creating doloop insns. Combine should not be allowed
9045 to create these for a number of reasons:
9046 1) In a nested loop, if combine creates one of these in an
9047 outer loop and the register allocator happens to allocate ctr
9048 to the outer loop insn, then the inner loop can't use ctr.
9049 Inner loops ought to be more highly optimized.
9050 2) Combine often wants to create one of these from what was
9051 originally a three insn sequence, first combining the three
9052 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9053 allocated ctr, the splitter takes use back to the three insn
9054 sequence. It's better to stop combine at the two insn
9056 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9057 insns, the register allocator sometimes uses floating point
9058 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9059 jump insn and output reloads are not implemented for jumps,
9060 the ctrsi/ctrdi splitters need to handle all possible cases.
9061 That's a pain, and it gets to be seriously difficult when a
9062 splitter that runs after reload needs memory to transfer from
9063 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9064 for the difficult case. It's better to not create problems
9065 in the first place. */
9066 if (icode != CODE_FOR_nothing
9067 && (icode == CODE_FOR_ctrsi_internal1
9068 || icode == CODE_FOR_ctrdi_internal1
9069 || icode == CODE_FOR_ctrsi_internal2
9070 || icode == CODE_FOR_ctrdi_internal2))
9076 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9078 static GTY(()) rtx rs6000_tls_symbol;
9080 rs6000_tls_get_addr (void)
9082 if (!rs6000_tls_symbol)
9083 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
9085 return rs6000_tls_symbol;
9088 /* Construct the SYMBOL_REF for TLS GOT references. */
9090 static GTY(()) rtx rs6000_got_symbol;
9092 rs6000_got_sym (void)
9094 if (!rs6000_got_symbol)
9096 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9097 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
9098 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
9101 return rs6000_got_symbol;
9104 /* AIX Thread-Local Address support. */
9107 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
9109 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
9113 name = XSTR (addr, 0);
9114 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9115 or the symbol will be in TLS private data section. */
9116 if (name[strlen (name) - 1] != ']'
9117 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
9118 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
9120 tlsname = XALLOCAVEC (char, strlen (name) + 4);
9121 strcpy (tlsname, name);
9123 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
9124 tlsaddr = copy_rtx (addr);
9125 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
9130 /* Place addr into TOC constant pool. */
9131 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
9133 /* Output the TOC entry and create the MEM referencing the value. */
9134 if (constant_pool_expr_p (XEXP (sym, 0))
9135 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
9137 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
9138 mem = gen_const_mem (Pmode, tocref);
9139 set_mem_alias_set (mem, get_TOC_alias_set ());
9144 /* Use global-dynamic for local-dynamic. */
9145 if (model == TLS_MODEL_GLOBAL_DYNAMIC
9146 || model == TLS_MODEL_LOCAL_DYNAMIC)
9148 /* Create new TOC reference for @m symbol. */
9149 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
9150 tlsname = XALLOCAVEC (char, strlen (name) + 1);
9151 strcpy (tlsname, "*LCM");
9152 strcat (tlsname, name + 3);
9153 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
9154 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
9155 tocref = create_TOC_reference (modaddr, NULL_RTX);
9156 rtx modmem = gen_const_mem (Pmode, tocref);
9157 set_mem_alias_set (modmem, get_TOC_alias_set ());
9159 rtx modreg = gen_reg_rtx (Pmode);
9160 emit_insn (gen_rtx_SET (modreg, modmem));
9162 tmpreg = gen_reg_rtx (Pmode);
9163 emit_insn (gen_rtx_SET (tmpreg, mem));
9165 dest = gen_reg_rtx (Pmode);
9167 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
9169 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
9172 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9173 else if (TARGET_32BIT)
9175 tlsreg = gen_reg_rtx (SImode);
9176 emit_insn (gen_tls_get_tpointer (tlsreg));
9179 tlsreg = gen_rtx_REG (DImode, 13);
9181 /* Load the TOC value into temporary register. */
9182 tmpreg = gen_reg_rtx (Pmode);
9183 emit_insn (gen_rtx_SET (tmpreg, mem));
9184 set_unique_reg_note (get_last_insn (), REG_EQUAL,
9185 gen_rtx_MINUS (Pmode, addr, tlsreg));
9187 /* Add TOC symbol value to TLS pointer. */
9188 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
9193 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9194 this (thread-local) address. */
9197 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
9202 return rs6000_legitimize_tls_address_aix (addr, model);
9204 dest = gen_reg_rtx (Pmode);
9205 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
9211 tlsreg = gen_rtx_REG (Pmode, 13);
9212 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
9216 tlsreg = gen_rtx_REG (Pmode, 2);
9217 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
9221 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
9225 tmp = gen_reg_rtx (Pmode);
9228 tlsreg = gen_rtx_REG (Pmode, 13);
9229 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
9233 tlsreg = gen_rtx_REG (Pmode, 2);
9234 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
9238 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
9240 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
9245 rtx r3, got, tga, tmp1, tmp2, call_insn;
9247 /* We currently use relocations like @got@tlsgd for tls, which
9248 means the linker will handle allocation of tls entries, placing
9249 them in the .got section. So use a pointer to the .got section,
9250 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9251 or to secondary GOT sections used by 32-bit -fPIC. */
9253 got = gen_rtx_REG (Pmode, 2);
9257 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9260 rtx gsym = rs6000_got_sym ();
9261 got = gen_reg_rtx (Pmode);
9263 rs6000_emit_move (got, gsym, Pmode);
9268 tmp1 = gen_reg_rtx (Pmode);
9269 tmp2 = gen_reg_rtx (Pmode);
9270 mem = gen_const_mem (Pmode, tmp1);
9271 lab = gen_label_rtx ();
9272 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9273 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9274 if (TARGET_LINK_STACK)
9275 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9276 emit_move_insn (tmp2, mem);
9277 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9278 set_unique_reg_note (last, REG_EQUAL, gsym);
9283 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9285 tga = rs6000_tls_get_addr ();
9286 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9289 r3 = gen_rtx_REG (Pmode, 3);
9290 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9293 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9295 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9297 else if (DEFAULT_ABI == ABI_V4)
9298 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9301 call_insn = last_call_insn ();
9302 PATTERN (call_insn) = insn;
9303 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9304 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9305 pic_offset_table_rtx);
9307 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9309 tga = rs6000_tls_get_addr ();
9310 tmp1 = gen_reg_rtx (Pmode);
9311 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9314 r3 = gen_rtx_REG (Pmode, 3);
9315 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9318 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9320 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9322 else if (DEFAULT_ABI == ABI_V4)
9323 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9326 call_insn = last_call_insn ();
9327 PATTERN (call_insn) = insn;
9328 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9329 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9330 pic_offset_table_rtx);
9332 if (rs6000_tls_size == 16)
9335 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9337 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9339 else if (rs6000_tls_size == 32)
9341 tmp2 = gen_reg_rtx (Pmode);
9343 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9345 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9348 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9350 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9354 tmp2 = gen_reg_rtx (Pmode);
9356 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9358 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9360 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9366 /* IE, or 64-bit offset LE. */
9367 tmp2 = gen_reg_rtx (Pmode);
9369 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9371 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9374 insn = gen_tls_tls_64 (dest, tmp2, addr);
9376 insn = gen_tls_tls_32 (dest, tmp2, addr);
9384 /* Only create the global variable for the stack protect guard if we are using
9385 the global flavor of that guard. */
9387 rs6000_init_stack_protect_guard (void)
9389 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9390 return default_stack_protect_guard ();
9395 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9398 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9400 if (GET_CODE (x) == HIGH
9401 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9404 /* A TLS symbol in the TOC cannot contain a sum. */
9405 if (GET_CODE (x) == CONST
9406 && GET_CODE (XEXP (x, 0)) == PLUS
9407 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9408 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9411 /* Do not place an ELF TLS symbol in the constant pool. */
9412 return TARGET_ELF && tls_referenced_p (x);
9415 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9416 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9417 can be addressed relative to the toc pointer. */
9420 use_toc_relative_ref (rtx sym, machine_mode mode)
9422 return ((constant_pool_expr_p (sym)
9423 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9424 get_pool_mode (sym)))
9425 || (TARGET_CMODEL == CMODEL_MEDIUM
9426 && SYMBOL_REF_LOCAL_P (sym)
9427 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9430 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9431 replace the input X, or the original X if no replacement is called for.
9432 The output parameter *WIN is 1 if the calling macro should goto WIN,
9435 For RS/6000, we wish to handle large displacements off a base
9436 register by splitting the addend across an addiu/addis and the mem insn.
9437 This cuts number of extra insns needed from 3 to 1.
9439 On Darwin, we use this to generate code for floating point constants.
9440 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9441 The Darwin code is inside #if TARGET_MACHO because only then are the
9442 machopic_* functions defined. */
9444 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9445 int opnum, int type,
9446 int ind_levels ATTRIBUTE_UNUSED, int *win)
9448 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9449 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9451 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9452 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9455 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9456 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9457 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9458 && TARGET_P9_VECTOR)
9459 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9460 && TARGET_P9_VECTOR)))
9461 reg_offset_p = false;
9463 /* We must recognize output that we have already generated ourselves. */
9464 if (GET_CODE (x) == PLUS
9465 && GET_CODE (XEXP (x, 0)) == PLUS
9466 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9467 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9468 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9470 if (TARGET_DEBUG_ADDR)
9472 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9475 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9476 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9477 opnum, (enum reload_type) type);
9482 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9483 if (GET_CODE (x) == LO_SUM
9484 && GET_CODE (XEXP (x, 0)) == HIGH)
9486 if (TARGET_DEBUG_ADDR)
9488 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9491 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9492 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9493 opnum, (enum reload_type) type);
9499 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9500 && GET_CODE (x) == LO_SUM
9501 && GET_CODE (XEXP (x, 0)) == PLUS
9502 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9503 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9504 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9505 && machopic_operand_p (XEXP (x, 1)))
9507 /* Result of previous invocation of this function on Darwin
9508 floating point constant. */
9509 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9510 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9511 opnum, (enum reload_type) type);
9517 if (TARGET_CMODEL != CMODEL_SMALL
9520 && small_toc_ref (x, VOIDmode))
9522 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9523 x = gen_rtx_LO_SUM (Pmode, hi, x);
9524 if (TARGET_DEBUG_ADDR)
9526 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9529 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9530 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9531 opnum, (enum reload_type) type);
9536 if (GET_CODE (x) == PLUS
9537 && REG_P (XEXP (x, 0))
9538 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9539 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9540 && CONST_INT_P (XEXP (x, 1))
9542 && !PAIRED_VECTOR_MODE (mode)
9543 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9545 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9546 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9548 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9550 /* Check for 32-bit overflow or quad addresses with one of the
9551 four least significant bits set. */
9552 if (high + low != val
9553 || (quad_offset_p && (low & 0xf)))
9559 /* Reload the high part into a base reg; leave the low part
9560 in the mem directly. */
9562 x = gen_rtx_PLUS (GET_MODE (x),
9563 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9567 if (TARGET_DEBUG_ADDR)
9569 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9572 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9573 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9574 opnum, (enum reload_type) type);
9579 if (GET_CODE (x) == SYMBOL_REF
9582 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9583 && !PAIRED_VECTOR_MODE (mode)
9585 && DEFAULT_ABI == ABI_DARWIN
9586 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9587 && machopic_symbol_defined_p (x)
9589 && DEFAULT_ABI == ABI_V4
9592 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9593 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9595 ??? Assume floating point reg based on mode? This assumption is
9596 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9597 where reload ends up doing a DFmode load of a constant from
9598 mem using two gprs. Unfortunately, at this point reload
9599 hasn't yet selected regs so poking around in reload data
9600 won't help and even if we could figure out the regs reliably,
9601 we'd still want to allow this transformation when the mem is
9602 naturally aligned. Since we say the address is good here, we
9603 can't disable offsets from LO_SUMs in mem_operand_gpr.
9604 FIXME: Allow offset from lo_sum for other modes too, when
9605 mem is sufficiently aligned.
9607 Also disallow this if the type can go in VMX/Altivec registers, since
9608 those registers do not have d-form (reg+offset) address modes. */
9609 && !reg_addr[mode].scalar_in_vmx_p
9614 && (mode != TImode || !TARGET_VSX)
9616 && (mode != DImode || TARGET_POWERPC64)
9617 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9618 || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
9623 rtx offset = machopic_gen_offset (x);
9624 x = gen_rtx_LO_SUM (GET_MODE (x),
9625 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9626 gen_rtx_HIGH (Pmode, offset)), offset);
9630 x = gen_rtx_LO_SUM (GET_MODE (x),
9631 gen_rtx_HIGH (Pmode, x), x);
9633 if (TARGET_DEBUG_ADDR)
9635 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9638 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9639 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9640 opnum, (enum reload_type) type);
9645 /* Reload an offset address wrapped by an AND that represents the
9646 masking of the lower bits. Strip the outer AND and let reload
9647 convert the offset address into an indirect address. For VSX,
9648 force reload to create the address with an AND in a separate
9649 register, because we can't guarantee an altivec register will
9651 if (VECTOR_MEM_ALTIVEC_P (mode)
9652 && GET_CODE (x) == AND
9653 && GET_CODE (XEXP (x, 0)) == PLUS
9654 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9655 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9656 && GET_CODE (XEXP (x, 1)) == CONST_INT
9657 && INTVAL (XEXP (x, 1)) == -16)
9667 && GET_CODE (x) == SYMBOL_REF
9668 && use_toc_relative_ref (x, mode))
9670 x = create_TOC_reference (x, NULL_RTX);
9671 if (TARGET_CMODEL != CMODEL_SMALL)
9673 if (TARGET_DEBUG_ADDR)
9675 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9678 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9679 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9680 opnum, (enum reload_type) type);
9689 /* Debug version of rs6000_legitimize_reload_address. */
9691 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9692 int opnum, int type,
9693 int ind_levels, int *win)
9695 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9698 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9699 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9700 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9704 fprintf (stderr, "Same address returned\n");
9706 fprintf (stderr, "NULL returned\n");
9709 fprintf (stderr, "New address:\n");
9716 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9717 that is a valid memory address for an instruction.
9718 The MODE argument is the machine mode for the MEM expression
9719 that wants to use this address.
9721 On the RS/6000, there are four valid address: a SYMBOL_REF that
9722 refers to a constant pool entry of an address (or the sum of it
9723 plus a constant), a short (16-bit signed) constant plus a register,
9724 the sum of two registers, or a register indirect, possibly with an
9725 auto-increment. For DFmode, DDmode and DImode with a constant plus
9726 register, we must ensure that both words are addressable or PowerPC64
9727 with offset word aligned.
9729 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9730 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9731 because adjacent memory cells are accessed by adding word-sized offsets
9732 during assembly output. */
9734 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9736 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9737 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9739 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9740 if (VECTOR_MEM_ALTIVEC_P (mode)
9741 && GET_CODE (x) == AND
9742 && GET_CODE (XEXP (x, 1)) == CONST_INT
9743 && INTVAL (XEXP (x, 1)) == -16)
9746 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9748 if (legitimate_indirect_address_p (x, reg_ok_strict))
9751 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9752 && mode_supports_pre_incdec_p (mode)
9753 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9755 /* Handle restricted vector d-form offsets in ISA 3.0. */
9758 if (quad_address_p (x, mode, reg_ok_strict))
9761 else if (virtual_stack_registers_memory_p (x))
9764 else if (reg_offset_p)
9766 if (legitimate_small_data_p (mode, x))
9768 if (legitimate_constant_pool_address_p (x, mode,
9769 reg_ok_strict || lra_in_progress))
9771 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9772 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9776 /* For TImode, if we have TImode in VSX registers, only allow register
9777 indirect addresses. This will allow the values to go in either GPRs
9778 or VSX registers without reloading. The vector types would tend to
9779 go into VSX registers, so we allow REG+REG, while TImode seems
9780 somewhat split, in that some uses are GPR based, and some VSX based. */
9781 /* FIXME: We could loosen this by changing the following to
9782 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9783 but currently we cannot allow REG+REG addressing for TImode. See
9784 PR72827 for complete details on how this ends up hoodwinking DSE. */
9785 if (mode == TImode && TARGET_VSX)
9787 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9790 && GET_CODE (x) == PLUS
9791 && GET_CODE (XEXP (x, 0)) == REG
9792 && (XEXP (x, 0) == virtual_stack_vars_rtx
9793 || XEXP (x, 0) == arg_pointer_rtx)
9794 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9796 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9798 if (!FLOAT128_2REG_P (mode)
9799 && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9801 || (mode != DFmode && mode != DDmode))
9802 && (TARGET_POWERPC64 || mode != DImode)
9803 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9805 && !avoiding_indexed_address_p (mode)
9806 && legitimate_indexed_address_p (x, reg_ok_strict))
9808 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9809 && mode_supports_pre_modify_p (mode)
9810 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9811 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9812 reg_ok_strict, false)
9813 || (!avoiding_indexed_address_p (mode)
9814 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9815 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9817 if (reg_offset_p && !quad_offset_p
9818 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9823 /* Debug version of rs6000_legitimate_address_p. */
9825 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9828 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9830 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9831 "strict = %d, reload = %s, code = %s\n",
9832 ret ? "true" : "false",
9833 GET_MODE_NAME (mode),
9835 (reload_completed ? "after" : "before"),
9836 GET_RTX_NAME (GET_CODE (x)));
9842 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9845 rs6000_mode_dependent_address_p (const_rtx addr,
9846 addr_space_t as ATTRIBUTE_UNUSED)
9848 return rs6000_mode_dependent_address_ptr (addr);
9851 /* Go to LABEL if ADDR (a legitimate address expression)
9852 has an effect that depends on the machine mode it is used for.
9854 On the RS/6000 this is true of all integral offsets (since AltiVec
9855 and VSX modes don't allow them) or is a pre-increment or decrement.
9857 ??? Except that due to conceptual problems in offsettable_address_p
9858 we can't really report the problems of integral offsets. So leave
9859 this assuming that the adjustable offset must be valid for the
9860 sub-words of a TFmode operand, which is what we had before. */
9863 rs6000_mode_dependent_address (const_rtx addr)
9865 switch (GET_CODE (addr))
9868 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9869 is considered a legitimate address before reload, so there
9870 are no offset restrictions in that case. Note that this
9871 condition is safe in strict mode because any address involving
9872 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9873 been rejected as illegitimate. */
9874 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9875 && XEXP (addr, 0) != arg_pointer_rtx
9876 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9878 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9879 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9884 /* Anything in the constant pool is sufficiently aligned that
9885 all bytes have the same high part address. */
9886 return !legitimate_constant_pool_address_p (addr, QImode, false);
9888 /* Auto-increment cases are now treated generically in recog.c. */
9890 return TARGET_UPDATE;
9892 /* AND is only allowed in Altivec loads. */
9903 /* Debug version of rs6000_mode_dependent_address. */
9905 rs6000_debug_mode_dependent_address (const_rtx addr)
9907 bool ret = rs6000_mode_dependent_address (addr);
9909 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9910 ret ? "true" : "false");
9916 /* Implement FIND_BASE_TERM. */
9919 rs6000_find_base_term (rtx op)
9924 if (GET_CODE (base) == CONST)
9925 base = XEXP (base, 0);
9926 if (GET_CODE (base) == PLUS)
9927 base = XEXP (base, 0);
9928 if (GET_CODE (base) == UNSPEC)
9929 switch (XINT (base, 1))
9932 case UNSPEC_MACHOPIC_OFFSET:
9933 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9934 for aliasing purposes. */
9935 return XVECEXP (base, 0, 0);
9941 /* More elaborate version of recog's offsettable_memref_p predicate
9942 that works around the ??? note of rs6000_mode_dependent_address.
9943 In particular it accepts
9945 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9947 in 32-bit mode, that the recog predicate rejects. */
9950 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
9957 /* First mimic offsettable_memref_p. */
9958 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
9961 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9962 the latter predicate knows nothing about the mode of the memory
9963 reference and, therefore, assumes that it is the largest supported
9964 mode (TFmode). As a consequence, legitimate offsettable memory
9965 references are rejected. rs6000_legitimate_offset_address_p contains
9966 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9967 at least with a little bit of help here given that we know the
9968 actual registers used. */
9969 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9970 || GET_MODE_SIZE (reg_mode) == 4);
9971 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9975 /* Determine the reassociation width to be used in reassociate_bb.
9976 This takes into account how many parallel operations we
9977 can actually do of a given type, and also the latency.
9981 vect add/sub/mul 2/cycle
9982 fp add/sub/mul 2/cycle
9987 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9992 case PROCESSOR_POWER8:
9993 case PROCESSOR_POWER9:
9994 if (DECIMAL_FLOAT_MODE_P (mode))
9996 if (VECTOR_MODE_P (mode))
9998 if (INTEGRAL_MODE_P (mode))
9999 return opc == MULT_EXPR ? 4 : 6;
10000 if (FLOAT_MODE_P (mode))
10009 /* Change register usage conditional on target flags. */
10011 rs6000_conditional_register_usage (void)
10015 if (TARGET_DEBUG_TARGET)
10016 fprintf (stderr, "rs6000_conditional_register_usage called\n");
10018 /* Set MQ register fixed (already call_used) so that it will not be
10020 fixed_regs[64] = 1;
10022 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10024 fixed_regs[13] = call_used_regs[13]
10025 = call_really_used_regs[13] = 1;
10027 /* Conditionally disable FPRs. */
10028 if (TARGET_SOFT_FLOAT)
10029 for (i = 32; i < 64; i++)
10030 fixed_regs[i] = call_used_regs[i]
10031 = call_really_used_regs[i] = 1;
10033 /* The TOC register is not killed across calls in a way that is
10034 visible to the compiler. */
10035 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10036 call_really_used_regs[2] = 0;
10038 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
10039 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10041 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10042 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10043 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10044 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10046 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
10047 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10048 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10049 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10051 if (TARGET_TOC && TARGET_MINIMAL_TOC)
10052 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10053 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10055 if (!TARGET_ALTIVEC && !TARGET_VSX)
10057 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10058 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10059 call_really_used_regs[VRSAVE_REGNO] = 1;
10062 if (TARGET_ALTIVEC || TARGET_VSX)
10063 global_regs[VSCR_REGNO] = 1;
10065 if (TARGET_ALTIVEC_ABI)
10067 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
10068 call_used_regs[i] = call_really_used_regs[i] = 1;
10070 /* AIX reserves VR20:31 in non-extended ABI mode. */
10072 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
10073 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10078 /* Output insns to set DEST equal to the constant SOURCE as a series of
10079 lis, ori and shl instructions and return TRUE. */
10082 rs6000_emit_set_const (rtx dest, rtx source)
10084 machine_mode mode = GET_MODE (dest);
10089 gcc_checking_assert (CONST_INT_P (source));
10090 c = INTVAL (source);
10095 emit_insn (gen_rtx_SET (dest, source));
10099 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
10101 emit_insn (gen_rtx_SET (copy_rtx (temp),
10102 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
10103 emit_insn (gen_rtx_SET (dest,
10104 gen_rtx_IOR (SImode, copy_rtx (temp),
10105 GEN_INT (c & 0xffff))));
10109 if (!TARGET_POWERPC64)
10113 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
10115 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
10117 emit_move_insn (hi, GEN_INT (c >> 32));
10118 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
10119 emit_move_insn (lo, GEN_INT (c));
10122 rs6000_emit_set_long_const (dest, c);
10126 gcc_unreachable ();
10129 insn = get_last_insn ();
10130 set = single_set (insn);
10131 if (! CONSTANT_P (SET_SRC (set)))
10132 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
10137 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10138 Output insns to set DEST equal to the constant C as a series of
10139 lis, ori and shl instructions. */
10142 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
10145 HOST_WIDE_INT ud1, ud2, ud3, ud4;
10155 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
10156 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
10157 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
10159 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
10160 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
10162 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10164 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10165 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10167 emit_move_insn (dest,
10168 gen_rtx_IOR (DImode, copy_rtx (temp),
10171 else if (ud3 == 0 && ud4 == 0)
10173 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10175 gcc_assert (ud2 & 0x8000);
10176 emit_move_insn (copy_rtx (temp),
10177 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10179 emit_move_insn (copy_rtx (temp),
10180 gen_rtx_IOR (DImode, copy_rtx (temp),
10182 emit_move_insn (dest,
10183 gen_rtx_ZERO_EXTEND (DImode,
10184 gen_lowpart (SImode,
10185 copy_rtx (temp))));
10187 else if ((ud4 == 0xffff && (ud3 & 0x8000))
10188 || (ud4 == 0 && ! (ud3 & 0x8000)))
10190 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10192 emit_move_insn (copy_rtx (temp),
10193 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
10195 emit_move_insn (copy_rtx (temp),
10196 gen_rtx_IOR (DImode, copy_rtx (temp),
10198 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10199 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10202 emit_move_insn (dest,
10203 gen_rtx_IOR (DImode, copy_rtx (temp),
10208 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10210 emit_move_insn (copy_rtx (temp),
10211 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
10213 emit_move_insn (copy_rtx (temp),
10214 gen_rtx_IOR (DImode, copy_rtx (temp),
10217 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
10218 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10221 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10222 gen_rtx_IOR (DImode, copy_rtx (temp),
10223 GEN_INT (ud2 << 16)));
10225 emit_move_insn (dest,
10226 gen_rtx_IOR (DImode, copy_rtx (temp),
10231 /* Helper for the following. Get rid of [r+r] memory refs
10232 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10235 rs6000_eliminate_indexed_memrefs (rtx operands[2])
10237 if (GET_CODE (operands[0]) == MEM
10238 && GET_CODE (XEXP (operands[0], 0)) != REG
10239 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
10240 GET_MODE (operands[0]), false))
10242 = replace_equiv_address (operands[0],
10243 copy_addr_to_reg (XEXP (operands[0], 0)));
10245 if (GET_CODE (operands[1]) == MEM
10246 && GET_CODE (XEXP (operands[1], 0)) != REG
10247 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10248 GET_MODE (operands[1]), false))
10250 = replace_equiv_address (operands[1],
10251 copy_addr_to_reg (XEXP (operands[1], 0)));
10254 /* Generate a vector of constants to permute MODE for a little-endian
10255 storage operation by swapping the two halves of a vector. */
10257 rs6000_const_vec (machine_mode mode)
10285 v = rtvec_alloc (subparts);
10287 for (i = 0; i < subparts / 2; ++i)
10288 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10289 for (i = subparts / 2; i < subparts; ++i)
10290 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10295 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10296 store operation. */
10298 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10300 /* Scalar permutations are easier to express in integer modes rather than
10301 floating-point modes, so cast them here. We use V1TImode instead
10302 of TImode to ensure that the values don't go through GPRs. */
10303 if (FLOAT128_VECTOR_P (mode))
10305 dest = gen_lowpart (V1TImode, dest);
10306 source = gen_lowpart (V1TImode, source);
10310 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10312 if (mode == TImode || mode == V1TImode)
10313 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10317 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10318 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10322 /* Emit a little-endian load from vector memory location SOURCE to VSX
10323 register DEST in mode MODE. The load is done with two permuting
10324 insn's that represent an lxvd2x and xxpermdi. */
10326 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10328 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10330 if (mode == TImode || mode == V1TImode)
10333 dest = gen_lowpart (V2DImode, dest);
10334 source = adjust_address (source, V2DImode, 0);
10337 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10338 rs6000_emit_le_vsx_permute (tmp, source, mode);
10339 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10342 /* Emit a little-endian store to vector memory location DEST from VSX
10343 register SOURCE in mode MODE. The store is done with two permuting
10344 insn's that represent an xxpermdi and an stxvd2x. */
10346 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10348 /* This should never be called during or after LRA, because it does
10349 not re-permute the source register. It is intended only for use
10351 gcc_assert (!lra_in_progress && !reload_completed);
10353 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10355 if (mode == TImode || mode == V1TImode)
10358 dest = adjust_address (dest, V2DImode, 0);
10359 source = gen_lowpart (V2DImode, source);
10362 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10363 rs6000_emit_le_vsx_permute (tmp, source, mode);
10364 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10367 /* Emit a sequence representing a little-endian VSX load or store,
10368 moving data from SOURCE to DEST in mode MODE. This is done
10369 separately from rs6000_emit_move to ensure it is called only
10370 during expand. LE VSX loads and stores introduced later are
10371 handled with a split. The expand-time RTL generation allows
10372 us to optimize away redundant pairs of register-permutes. */
10374 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10376 gcc_assert (!BYTES_BIG_ENDIAN
10377 && VECTOR_MEM_VSX_P (mode)
10378 && !TARGET_P9_VECTOR
10379 && !gpr_or_gpr_p (dest, source)
10380 && (MEM_P (source) ^ MEM_P (dest)));
10382 if (MEM_P (source))
10384 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10385 rs6000_emit_le_vsx_load (dest, source, mode);
10389 if (!REG_P (source))
10390 source = force_reg (mode, source);
10391 rs6000_emit_le_vsx_store (dest, source, mode);
10395 /* Return whether a SFmode or SImode move can be done without converting one
10396 mode to another. This arrises when we have:
10398 (SUBREG:SF (REG:SI ...))
10399 (SUBREG:SI (REG:SF ...))
10401 and one of the values is in a floating point/vector register, where SFmode
10402 scalars are stored in DFmode format. */
10405 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10407 if (TARGET_ALLOW_SF_SUBREG)
10410 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10413 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10416 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10417 if (SUBREG_P (dest))
10419 rtx dest_subreg = SUBREG_REG (dest);
10420 rtx src_subreg = SUBREG_REG (src);
10421 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10428 /* Helper function to change moves with:
10430 (SUBREG:SF (REG:SI)) and
10431 (SUBREG:SI (REG:SF))
10433 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10434 values are stored as DFmode values in the VSX registers. We need to convert
10435 the bits before we can use a direct move or operate on the bits in the
10436 vector register as an integer type.
10438 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10441 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10443 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10444 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10445 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10447 rtx inner_source = SUBREG_REG (source);
10448 machine_mode inner_mode = GET_MODE (inner_source);
10450 if (mode == SImode && inner_mode == SFmode)
10452 emit_insn (gen_movsi_from_sf (dest, inner_source));
10456 if (mode == SFmode && inner_mode == SImode)
10458 emit_insn (gen_movsf_from_si (dest, inner_source));
10466 /* Emit a move from SOURCE to DEST in mode MODE. */
10468 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10471 operands[0] = dest;
10472 operands[1] = source;
10474 if (TARGET_DEBUG_ADDR)
10477 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10478 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10479 GET_MODE_NAME (mode),
10482 can_create_pseudo_p ());
10484 fprintf (stderr, "source:\n");
10485 debug_rtx (source);
10488 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10489 if (CONST_WIDE_INT_P (operands[1])
10490 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10492 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10493 gcc_unreachable ();
10496 /* See if we need to special case SImode/SFmode SUBREG moves. */
10497 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10498 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10501 /* Check if GCC is setting up a block move that will end up using FP
10502 registers as temporaries. We must make sure this is acceptable. */
10503 if (GET_CODE (operands[0]) == MEM
10504 && GET_CODE (operands[1]) == MEM
10506 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10507 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10508 && ! (rs6000_slow_unaligned_access (SImode,
10509 (MEM_ALIGN (operands[0]) > 32
10510 ? 32 : MEM_ALIGN (operands[0])))
10511 || rs6000_slow_unaligned_access (SImode,
10512 (MEM_ALIGN (operands[1]) > 32
10513 ? 32 : MEM_ALIGN (operands[1]))))
10514 && ! MEM_VOLATILE_P (operands [0])
10515 && ! MEM_VOLATILE_P (operands [1]))
10517 emit_move_insn (adjust_address (operands[0], SImode, 0),
10518 adjust_address (operands[1], SImode, 0));
10519 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10520 adjust_address (copy_rtx (operands[1]), SImode, 4));
10524 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10525 && !gpc_reg_operand (operands[1], mode))
10526 operands[1] = force_reg (mode, operands[1]);
10528 /* Recognize the case where operand[1] is a reference to thread-local
10529 data and load its address to a register. */
10530 if (tls_referenced_p (operands[1]))
10532 enum tls_model model;
10533 rtx tmp = operands[1];
10536 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10538 addend = XEXP (XEXP (tmp, 0), 1);
10539 tmp = XEXP (XEXP (tmp, 0), 0);
10542 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10543 model = SYMBOL_REF_TLS_MODEL (tmp);
10544 gcc_assert (model != 0);
10546 tmp = rs6000_legitimize_tls_address (tmp, model);
10549 tmp = gen_rtx_PLUS (mode, tmp, addend);
10550 tmp = force_operand (tmp, operands[0]);
10555 /* 128-bit constant floating-point values on Darwin should really be loaded
10556 as two parts. However, this premature splitting is a problem when DFmode
10557 values can go into Altivec registers. */
10558 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10559 && GET_CODE (operands[1]) == CONST_DOUBLE)
10561 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10562 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10564 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10565 GET_MODE_SIZE (DFmode)),
10566 simplify_gen_subreg (DFmode, operands[1], mode,
10567 GET_MODE_SIZE (DFmode)),
10572 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10573 p1:SD) if p1 is not of floating point class and p0 is spilled as
10574 we can have no analogous movsd_store for this. */
10575 if (lra_in_progress && mode == DDmode
10576 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10577 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10578 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10579 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10582 int regno = REGNO (SUBREG_REG (operands[1]));
10584 if (regno >= FIRST_PSEUDO_REGISTER)
10586 cl = reg_preferred_class (regno);
10587 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10589 if (regno >= 0 && ! FP_REGNO_P (regno))
10592 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10593 operands[1] = SUBREG_REG (operands[1]);
10596 if (lra_in_progress
10598 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10599 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10600 && (REG_P (operands[1])
10601 || (GET_CODE (operands[1]) == SUBREG
10602 && REG_P (SUBREG_REG (operands[1])))))
10604 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10605 ? SUBREG_REG (operands[1]) : operands[1]);
10608 if (regno >= FIRST_PSEUDO_REGISTER)
10610 cl = reg_preferred_class (regno);
10611 gcc_assert (cl != NO_REGS);
10612 regno = ira_class_hard_regs[cl][0];
10614 if (FP_REGNO_P (regno))
10616 if (GET_MODE (operands[0]) != DDmode)
10617 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10618 emit_insn (gen_movsd_store (operands[0], operands[1]));
10620 else if (INT_REGNO_P (regno))
10621 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10626 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10627 p:DD)) if p0 is not of floating point class and p1 is spilled as
10628 we can have no analogous movsd_load for this. */
10629 if (lra_in_progress && mode == DDmode
10630 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10631 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10632 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10633 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10636 int regno = REGNO (SUBREG_REG (operands[0]));
10638 if (regno >= FIRST_PSEUDO_REGISTER)
10640 cl = reg_preferred_class (regno);
10641 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10643 if (regno >= 0 && ! FP_REGNO_P (regno))
10646 operands[0] = SUBREG_REG (operands[0]);
10647 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10650 if (lra_in_progress
10652 && (REG_P (operands[0])
10653 || (GET_CODE (operands[0]) == SUBREG
10654 && REG_P (SUBREG_REG (operands[0]))))
10655 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10656 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10658 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10659 ? SUBREG_REG (operands[0]) : operands[0]);
10662 if (regno >= FIRST_PSEUDO_REGISTER)
10664 cl = reg_preferred_class (regno);
10665 gcc_assert (cl != NO_REGS);
10666 regno = ira_class_hard_regs[cl][0];
10668 if (FP_REGNO_P (regno))
10670 if (GET_MODE (operands[1]) != DDmode)
10671 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10672 emit_insn (gen_movsd_load (operands[0], operands[1]));
10674 else if (INT_REGNO_P (regno))
10675 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10681 /* FIXME: In the long term, this switch statement should go away
10682 and be replaced by a sequence of tests based on things like
10688 if (CONSTANT_P (operands[1])
10689 && GET_CODE (operands[1]) != CONST_INT)
10690 operands[1] = force_const_mem (mode, operands[1]);
10697 if (FLOAT128_2REG_P (mode))
10698 rs6000_eliminate_indexed_memrefs (operands);
10705 if (CONSTANT_P (operands[1])
10706 && ! easy_fp_constant (operands[1], mode))
10707 operands[1] = force_const_mem (mode, operands[1]);
10719 if (CONSTANT_P (operands[1])
10720 && !easy_vector_constant (operands[1], mode))
10721 operands[1] = force_const_mem (mode, operands[1]);
10726 /* Use default pattern for address of ELF small data */
10729 && DEFAULT_ABI == ABI_V4
10730 && (GET_CODE (operands[1]) == SYMBOL_REF
10731 || GET_CODE (operands[1]) == CONST)
10732 && small_data_operand (operands[1], mode))
10734 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10738 if (DEFAULT_ABI == ABI_V4
10739 && mode == Pmode && mode == SImode
10740 && flag_pic == 1 && got_operand (operands[1], mode))
10742 emit_insn (gen_movsi_got (operands[0], operands[1]));
10746 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10750 && CONSTANT_P (operands[1])
10751 && GET_CODE (operands[1]) != HIGH
10752 && GET_CODE (operands[1]) != CONST_INT)
10754 rtx target = (!can_create_pseudo_p ()
10756 : gen_reg_rtx (mode));
10758 /* If this is a function address on -mcall-aixdesc,
10759 convert it to the address of the descriptor. */
10760 if (DEFAULT_ABI == ABI_AIX
10761 && GET_CODE (operands[1]) == SYMBOL_REF
10762 && XSTR (operands[1], 0)[0] == '.')
10764 const char *name = XSTR (operands[1], 0);
10766 while (*name == '.')
10768 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10769 CONSTANT_POOL_ADDRESS_P (new_ref)
10770 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10771 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10772 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10773 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10774 operands[1] = new_ref;
10777 if (DEFAULT_ABI == ABI_DARWIN)
10780 if (MACHO_DYNAMIC_NO_PIC_P)
10782 /* Take care of any required data indirection. */
10783 operands[1] = rs6000_machopic_legitimize_pic_address (
10784 operands[1], mode, operands[0]);
10785 if (operands[0] != operands[1])
10786 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10790 emit_insn (gen_macho_high (target, operands[1]));
10791 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10795 emit_insn (gen_elf_high (target, operands[1]));
10796 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10800 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10801 and we have put it in the TOC, we just need to make a TOC-relative
10802 reference to it. */
10804 && GET_CODE (operands[1]) == SYMBOL_REF
10805 && use_toc_relative_ref (operands[1], mode))
10806 operands[1] = create_TOC_reference (operands[1], operands[0]);
10807 else if (mode == Pmode
10808 && CONSTANT_P (operands[1])
10809 && GET_CODE (operands[1]) != HIGH
10810 && ((GET_CODE (operands[1]) != CONST_INT
10811 && ! easy_fp_constant (operands[1], mode))
10812 || (GET_CODE (operands[1]) == CONST_INT
10813 && (num_insns_constant (operands[1], mode)
10814 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10815 || (GET_CODE (operands[0]) == REG
10816 && FP_REGNO_P (REGNO (operands[0]))))
10817 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10818 && (TARGET_CMODEL == CMODEL_SMALL
10819 || can_create_pseudo_p ()
10820 || (REG_P (operands[0])
10821 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10825 /* Darwin uses a special PIC legitimizer. */
10826 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10829 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10831 if (operands[0] != operands[1])
10832 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10837 /* If we are to limit the number of things we put in the TOC and
10838 this is a symbol plus a constant we can add in one insn,
10839 just put the symbol in the TOC and add the constant. */
10840 if (GET_CODE (operands[1]) == CONST
10841 && TARGET_NO_SUM_IN_TOC
10842 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10843 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10844 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10845 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10846 && ! side_effects_p (operands[0]))
10849 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10850 rtx other = XEXP (XEXP (operands[1], 0), 1);
10852 sym = force_reg (mode, sym);
10853 emit_insn (gen_add3_insn (operands[0], sym, other));
10857 operands[1] = force_const_mem (mode, operands[1]);
10860 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10861 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10863 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10865 operands[1] = gen_const_mem (mode, tocref);
10866 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10872 if (!VECTOR_MEM_VSX_P (TImode))
10873 rs6000_eliminate_indexed_memrefs (operands);
10877 rs6000_eliminate_indexed_memrefs (operands);
10881 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10884 /* Above, we may have called force_const_mem which may have returned
10885 an invalid address. If we can, fix this up; otherwise, reload will
10886 have to deal with it. */
10887 if (GET_CODE (operands[1]) == MEM)
10888 operands[1] = validize_mem (operands[1]);
10890 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10893 /* Nonzero if we can use a floating-point register to pass this arg. */
10894 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10895 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10896 && (CUM)->fregno <= FP_ARG_MAX_REG \
10897 && TARGET_HARD_FLOAT)
10899 /* Nonzero if we can use an AltiVec register to pass this arg. */
10900 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10901 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10902 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10903 && TARGET_ALTIVEC_ABI \
10906 /* Walk down the type tree of TYPE counting consecutive base elements.
10907 If *MODEP is VOIDmode, then set it to the first valid floating point
10908 or vector type. If a non-floating point or vector type is found, or
10909 if a floating point or vector type that doesn't match a non-VOIDmode
10910 *MODEP is found, then return -1, otherwise return the count in the
10914 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10917 HOST_WIDE_INT size;
10919 switch (TREE_CODE (type))
10922 mode = TYPE_MODE (type);
10923 if (!SCALAR_FLOAT_MODE_P (mode))
10926 if (*modep == VOIDmode)
10929 if (*modep == mode)
10935 mode = TYPE_MODE (TREE_TYPE (type));
10936 if (!SCALAR_FLOAT_MODE_P (mode))
10939 if (*modep == VOIDmode)
10942 if (*modep == mode)
10948 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10951 /* Use V4SImode as representative of all 128-bit vector types. */
10952 size = int_size_in_bytes (type);
10962 if (*modep == VOIDmode)
10965 /* Vector modes are considered to be opaque: two vectors are
10966 equivalent for the purposes of being homogeneous aggregates
10967 if they are the same size. */
10968 if (*modep == mode)
10976 tree index = TYPE_DOMAIN (type);
10978 /* Can't handle incomplete types nor sizes that are not
10980 if (!COMPLETE_TYPE_P (type)
10981 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10984 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10987 || !TYPE_MAX_VALUE (index)
10988 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10989 || !TYPE_MIN_VALUE (index)
10990 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10994 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10995 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10997 /* There must be no padding. */
10998 if (wi::to_wide (TYPE_SIZE (type))
10999 != count * GET_MODE_BITSIZE (*modep))
11011 /* Can't handle incomplete types nor sizes that are not
11013 if (!COMPLETE_TYPE_P (type)
11014 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11017 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11019 if (TREE_CODE (field) != FIELD_DECL)
11022 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11025 count += sub_count;
11028 /* There must be no padding. */
11029 if (wi::to_wide (TYPE_SIZE (type))
11030 != count * GET_MODE_BITSIZE (*modep))
11037 case QUAL_UNION_TYPE:
11039 /* These aren't very interesting except in a degenerate case. */
11044 /* Can't handle incomplete types nor sizes that are not
11046 if (!COMPLETE_TYPE_P (type)
11047 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11050 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11052 if (TREE_CODE (field) != FIELD_DECL)
11055 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11058 count = count > sub_count ? count : sub_count;
11061 /* There must be no padding. */
11062 if (wi::to_wide (TYPE_SIZE (type))
11063 != count * GET_MODE_BITSIZE (*modep))
11076 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11077 float or vector aggregate that shall be passed in FP/vector registers
11078 according to the ELFv2 ABI, return the homogeneous element mode in
11079 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11081 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11084 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
11085 machine_mode *elt_mode,
11088 /* Note that we do not accept complex types at the top level as
11089 homogeneous aggregates; these types are handled via the
11090 targetm.calls.split_complex_arg mechanism. Complex types
11091 can be elements of homogeneous aggregates, however. */
11092 if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))
11094 machine_mode field_mode = VOIDmode;
11095 int field_count = rs6000_aggregate_candidate (type, &field_mode);
11097 if (field_count > 0)
11099 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
11100 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
11102 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11103 up to AGGR_ARG_NUM_REG registers. */
11104 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
11107 *elt_mode = field_mode;
11109 *n_elts = field_count;
11122 /* Return a nonzero value to say to return the function value in
11123 memory, just as large structures are always returned. TYPE will be
11124 the data type of the value, and FNTYPE will be the type of the
11125 function doing the returning, or @code{NULL} for libcalls.
11127 The AIX ABI for the RS/6000 specifies that all structures are
11128 returned in memory. The Darwin ABI does the same.
11130 For the Darwin 64 Bit ABI, a function result can be returned in
11131 registers or in memory, depending on the size of the return data
11132 type. If it is returned in registers, the value occupies the same
11133 registers as it would if it were the first and only function
11134 argument. Otherwise, the function places its result in memory at
11135 the location pointed to by GPR3.
11137 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11138 but a draft put them in memory, and GCC used to implement the draft
11139 instead of the final standard. Therefore, aix_struct_return
11140 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11141 compatibility can change DRAFT_V4_STRUCT_RET to override the
11142 default, and -m switches get the final word. See
11143 rs6000_option_override_internal for more details.
11145 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11146 long double support is enabled. These values are returned in memory.
11148 int_size_in_bytes returns -1 for variable size objects, which go in
11149 memory always. The cast to unsigned makes -1 > 8. */
11152 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
11154 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11156 && rs6000_darwin64_abi
11157 && TREE_CODE (type) == RECORD_TYPE
11158 && int_size_in_bytes (type) > 0)
11160 CUMULATIVE_ARGS valcum;
11164 valcum.fregno = FP_ARG_MIN_REG;
11165 valcum.vregno = ALTIVEC_ARG_MIN_REG;
11166 /* Do a trial code generation as if this were going to be passed
11167 as an argument; if any part goes in memory, we return NULL. */
11168 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
11171 /* Otherwise fall through to more conventional ABI rules. */
11174 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11175 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
11179 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11180 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
11181 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
11184 if (AGGREGATE_TYPE_P (type)
11185 && (aix_struct_return
11186 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
11189 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11190 modes only exist for GCC vector types if -maltivec. */
11191 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
11192 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11195 /* Return synthetic vectors in memory. */
11196 if (TREE_CODE (type) == VECTOR_TYPE
11197 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11199 static bool warned_for_return_big_vectors = false;
11200 if (!warned_for_return_big_vectors)
11202 warning (OPT_Wpsabi, "GCC vector returned by reference: "
11203 "non-standard ABI extension with no compatibility "
11205 warned_for_return_big_vectors = true;
11210 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11211 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11217 /* Specify whether values returned in registers should be at the most
11218 significant end of a register. We want aggregates returned by
11219 value to match the way aggregates are passed to functions. */
11222 rs6000_return_in_msb (const_tree valtype)
11224 return (DEFAULT_ABI == ABI_ELFv2
11225 && BYTES_BIG_ENDIAN
11226 && AGGREGATE_TYPE_P (valtype)
11227 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11231 #ifdef HAVE_AS_GNU_ATTRIBUTE
11232 /* Return TRUE if a call to function FNDECL may be one that
11233 potentially affects the function calling ABI of the object file. */
11236 call_ABI_of_interest (tree fndecl)
11238 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11240 struct cgraph_node *c_node;
11242 /* Libcalls are always interesting. */
11243 if (fndecl == NULL_TREE)
11246 /* Any call to an external function is interesting. */
11247 if (DECL_EXTERNAL (fndecl))
11250 /* Interesting functions that we are emitting in this object file. */
11251 c_node = cgraph_node::get (fndecl);
11252 c_node = c_node->ultimate_alias_target ();
11253 return !c_node->only_called_directly_p ();
11259 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11260 for a call to a function whose data type is FNTYPE.
11261 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11263 For incoming args we set the number of arguments in the prototype large
11264 so we never return a PARALLEL. */
11267 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11268 rtx libname ATTRIBUTE_UNUSED, int incoming,
11269 int libcall, int n_named_args,
11270 tree fndecl ATTRIBUTE_UNUSED,
11271 machine_mode return_mode ATTRIBUTE_UNUSED)
11273 static CUMULATIVE_ARGS zero_cumulative;
11275 *cum = zero_cumulative;
11277 cum->fregno = FP_ARG_MIN_REG;
11278 cum->vregno = ALTIVEC_ARG_MIN_REG;
11279 cum->prototype = (fntype && prototype_p (fntype));
11280 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11281 ? CALL_LIBCALL : CALL_NORMAL);
11282 cum->sysv_gregno = GP_ARG_MIN_REG;
11283 cum->stdarg = stdarg_p (fntype);
11284 cum->libcall = libcall;
11286 cum->nargs_prototype = 0;
11287 if (incoming || cum->prototype)
11288 cum->nargs_prototype = n_named_args;
11290 /* Check for a longcall attribute. */
11291 if ((!fntype && rs6000_default_long_calls)
11293 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11294 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11295 cum->call_cookie |= CALL_LONG;
11297 if (TARGET_DEBUG_ARG)
11299 fprintf (stderr, "\ninit_cumulative_args:");
11302 tree ret_type = TREE_TYPE (fntype);
11303 fprintf (stderr, " ret code = %s,",
11304 get_tree_code_name (TREE_CODE (ret_type)));
11307 if (cum->call_cookie & CALL_LONG)
11308 fprintf (stderr, " longcall,");
11310 fprintf (stderr, " proto = %d, nargs = %d\n",
11311 cum->prototype, cum->nargs_prototype);
11314 #ifdef HAVE_AS_GNU_ATTRIBUTE
11315 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11317 cum->escapes = call_ABI_of_interest (fndecl);
11324 return_type = TREE_TYPE (fntype);
11325 return_mode = TYPE_MODE (return_type);
11328 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11330 if (return_type != NULL)
11332 if (TREE_CODE (return_type) == RECORD_TYPE
11333 && TYPE_TRANSPARENT_AGGR (return_type))
11335 return_type = TREE_TYPE (first_field (return_type));
11336 return_mode = TYPE_MODE (return_type);
11338 if (AGGREGATE_TYPE_P (return_type)
11339 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11341 rs6000_returns_struct = true;
11343 if (SCALAR_FLOAT_MODE_P (return_mode))
11345 rs6000_passes_float = true;
11346 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11347 && (FLOAT128_IBM_P (return_mode)
11348 || FLOAT128_IEEE_P (return_mode)
11349 || (return_type != NULL
11350 && (TYPE_MAIN_VARIANT (return_type)
11351 == long_double_type_node))))
11352 rs6000_passes_long_double = true;
11354 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
11355 || PAIRED_VECTOR_MODE (return_mode))
11356 rs6000_passes_vector = true;
11363 && TARGET_ALTIVEC_ABI
11364 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11366 error ("cannot return value in vector register because"
11367 " altivec instructions are disabled, use %qs"
11368 " to enable them", "-maltivec");
11372 /* The mode the ABI uses for a word. This is not the same as word_mode
11373 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11375 static scalar_int_mode
11376 rs6000_abi_word_mode (void)
11378 return TARGET_32BIT ? SImode : DImode;
11381 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11383 rs6000_offload_options (void)
11386 return xstrdup ("-foffload-abi=lp64");
11388 return xstrdup ("-foffload-abi=ilp32");
11391 /* On rs6000, function arguments are promoted, as are function return
11394 static machine_mode
11395 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11397 int *punsignedp ATTRIBUTE_UNUSED,
11400 PROMOTE_MODE (mode, *punsignedp, type);
11405 /* Return true if TYPE must be passed on the stack and not in registers. */
11408 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11410 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11411 return must_pass_in_stack_var_size (mode, type);
11413 return must_pass_in_stack_var_size_or_pad (mode, type);
11417 is_complex_IBM_long_double (machine_mode mode)
11419 return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode);
11422 /* Whether ABI_V4 passes MODE args to a function in floating point
11426 abi_v4_pass_in_fpr (machine_mode mode)
11428 if (!TARGET_HARD_FLOAT)
11430 if (TARGET_SINGLE_FLOAT && mode == SFmode)
11432 if (TARGET_DOUBLE_FLOAT && mode == DFmode)
11434 /* ABI_V4 passes complex IBM long double in 8 gprs.
11435 Stupid, but we can't change the ABI now. */
11436 if (is_complex_IBM_long_double (mode))
11438 if (FLOAT128_2REG_P (mode))
11440 if (DECIMAL_FLOAT_MODE_P (mode))
11445 /* Implement TARGET_FUNCTION_ARG_PADDING.
11447 For the AIX ABI structs are always stored left shifted in their
11450 static pad_direction
11451 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11453 #ifndef AGGREGATE_PADDING_FIXED
11454 #define AGGREGATE_PADDING_FIXED 0
11456 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11457 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11460 if (!AGGREGATE_PADDING_FIXED)
11462 /* GCC used to pass structures of the same size as integer types as
11463 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11464 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11465 passed padded downward, except that -mstrict-align further
11466 muddied the water in that multi-component structures of 2 and 4
11467 bytes in size were passed padded upward.
11469 The following arranges for best compatibility with previous
11470 versions of gcc, but removes the -mstrict-align dependency. */
11471 if (BYTES_BIG_ENDIAN)
11473 HOST_WIDE_INT size = 0;
11475 if (mode == BLKmode)
11477 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11478 size = int_size_in_bytes (type);
11481 size = GET_MODE_SIZE (mode);
11483 if (size == 1 || size == 2 || size == 4)
11484 return PAD_DOWNWARD;
11489 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11491 if (type != 0 && AGGREGATE_TYPE_P (type))
11495 /* Fall back to the default. */
11496 return default_function_arg_padding (mode, type);
11499 /* If defined, a C expression that gives the alignment boundary, in bits,
11500 of an argument with the specified mode and type. If it is not defined,
11501 PARM_BOUNDARY is used for all arguments.
11503 V.4 wants long longs and doubles to be double word aligned. Just
11504 testing the mode size is a boneheaded way to do this as it means
11505 that other types such as complex int are also double word aligned.
11506 However, we're stuck with this because changing the ABI might break
11507 existing library interfaces.
11509 Quadword align Altivec/VSX vectors.
11510 Quadword align large synthetic vector types. */
11512 static unsigned int
11513 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11515 machine_mode elt_mode;
11518 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11520 if (DEFAULT_ABI == ABI_V4
11521 && (GET_MODE_SIZE (mode) == 8
11522 || (TARGET_HARD_FLOAT
11523 && !is_complex_IBM_long_double (mode)
11524 && FLOAT128_2REG_P (mode))))
11526 else if (FLOAT128_VECTOR_P (mode))
11528 else if (PAIRED_VECTOR_MODE (mode)
11529 || (type && TREE_CODE (type) == VECTOR_TYPE
11530 && int_size_in_bytes (type) >= 8
11531 && int_size_in_bytes (type) < 16))
11533 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11534 || (type && TREE_CODE (type) == VECTOR_TYPE
11535 && int_size_in_bytes (type) >= 16))
11538 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11539 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11540 -mcompat-align-parm is used. */
11541 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11542 || DEFAULT_ABI == ABI_ELFv2)
11543 && type && TYPE_ALIGN (type) > 64)
11545 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11546 or homogeneous float/vector aggregates here. We already handled
11547 vector aggregates above, but still need to check for float here. */
11548 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11549 && !SCALAR_FLOAT_MODE_P (elt_mode));
11551 /* We used to check for BLKmode instead of the above aggregate type
11552 check. Warn when this results in any difference to the ABI. */
11553 if (aggregate_p != (mode == BLKmode))
11555 static bool warned;
11556 if (!warned && warn_psabi)
11559 inform (input_location,
11560 "the ABI of passing aggregates with %d-byte alignment"
11561 " has changed in GCC 5",
11562 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11570 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11571 implement the "aggregate type" check as a BLKmode check here; this
11572 means certain aggregate types are in fact not aligned. */
11573 if (TARGET_MACHO && rs6000_darwin64_abi
11575 && type && TYPE_ALIGN (type) > 64)
11578 return PARM_BOUNDARY;
11581 /* The offset in words to the start of the parameter save area. */
11583 static unsigned int
11584 rs6000_parm_offset (void)
11586 return (DEFAULT_ABI == ABI_V4 ? 2
11587 : DEFAULT_ABI == ABI_ELFv2 ? 4
11591 /* For a function parm of MODE and TYPE, return the starting word in
11592 the parameter area. NWORDS of the parameter area are already used. */
11594 static unsigned int
11595 rs6000_parm_start (machine_mode mode, const_tree type,
11596 unsigned int nwords)
11598 unsigned int align;
11600 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11601 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11604 /* Compute the size (in words) of a function argument. */
11606 static unsigned long
11607 rs6000_arg_size (machine_mode mode, const_tree type)
11609 unsigned long size;
11611 if (mode != BLKmode)
11612 size = GET_MODE_SIZE (mode);
11614 size = int_size_in_bytes (type);
11617 return (size + 3) >> 2;
11619 return (size + 7) >> 3;
11622 /* Use this to flush pending int fields. */
11625 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11626 HOST_WIDE_INT bitpos, int final)
11628 unsigned int startbit, endbit;
11629 int intregs, intoffset;
11631 /* Handle the situations where a float is taking up the first half
11632 of the GPR, and the other half is empty (typically due to
11633 alignment restrictions). We can detect this by a 8-byte-aligned
11634 int field, or by seeing that this is the final flush for this
11635 argument. Count the word and continue on. */
11636 if (cum->floats_in_gpr == 1
11637 && (cum->intoffset % 64 == 0
11638 || (cum->intoffset == -1 && final)))
11641 cum->floats_in_gpr = 0;
11644 if (cum->intoffset == -1)
11647 intoffset = cum->intoffset;
11648 cum->intoffset = -1;
11649 cum->floats_in_gpr = 0;
11651 if (intoffset % BITS_PER_WORD != 0)
11653 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11654 if (!int_mode_for_size (bits, 0).exists ())
11656 /* We couldn't find an appropriate mode, which happens,
11657 e.g., in packed structs when there are 3 bytes to load.
11658 Back intoffset back to the beginning of the word in this
11660 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11664 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11665 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11666 intregs = (endbit - startbit) / BITS_PER_WORD;
11667 cum->words += intregs;
11668 /* words should be unsigned. */
11669 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11671 int pad = (endbit/BITS_PER_WORD) - cum->words;
11676 /* The darwin64 ABI calls for us to recurse down through structs,
11677 looking for elements passed in registers. Unfortunately, we have
11678 to track int register count here also because of misalignments
11679 in powerpc alignment mode. */
11682 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11684 HOST_WIDE_INT startbitpos)
11688 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11689 if (TREE_CODE (f) == FIELD_DECL)
11691 HOST_WIDE_INT bitpos = startbitpos;
11692 tree ftype = TREE_TYPE (f);
11694 if (ftype == error_mark_node)
11696 mode = TYPE_MODE (ftype);
11698 if (DECL_SIZE (f) != 0
11699 && tree_fits_uhwi_p (bit_position (f)))
11700 bitpos += int_bit_position (f);
11702 /* ??? FIXME: else assume zero offset. */
11704 if (TREE_CODE (ftype) == RECORD_TYPE)
11705 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11706 else if (USE_FP_FOR_ARG_P (cum, mode))
11708 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11709 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11710 cum->fregno += n_fpregs;
11711 /* Single-precision floats present a special problem for
11712 us, because they are smaller than an 8-byte GPR, and so
11713 the structure-packing rules combined with the standard
11714 varargs behavior mean that we want to pack float/float
11715 and float/int combinations into a single register's
11716 space. This is complicated by the arg advance flushing,
11717 which works on arbitrarily large groups of int-type
11719 if (mode == SFmode)
11721 if (cum->floats_in_gpr == 1)
11723 /* Two floats in a word; count the word and reset
11724 the float count. */
11726 cum->floats_in_gpr = 0;
11728 else if (bitpos % 64 == 0)
11730 /* A float at the beginning of an 8-byte word;
11731 count it and put off adjusting cum->words until
11732 we see if a arg advance flush is going to do it
11734 cum->floats_in_gpr++;
11738 /* The float is at the end of a word, preceded
11739 by integer fields, so the arg advance flush
11740 just above has already set cum->words and
11741 everything is taken care of. */
11745 cum->words += n_fpregs;
11747 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11749 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11753 else if (cum->intoffset == -1)
11754 cum->intoffset = bitpos;
11758 /* Check for an item that needs to be considered specially under the darwin 64
11759 bit ABI. These are record types where the mode is BLK or the structure is
11760 8 bytes in size. */
11762 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11764 return rs6000_darwin64_abi
11765 && ((mode == BLKmode
11766 && TREE_CODE (type) == RECORD_TYPE
11767 && int_size_in_bytes (type) > 0)
11768 || (type && TREE_CODE (type) == RECORD_TYPE
11769 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11772 /* Update the data in CUM to advance over an argument
11773 of mode MODE and data type TYPE.
11774 (TYPE is null for libcalls where that information may not be available.)
11776 Note that for args passed by reference, function_arg will be called
11777 with MODE and TYPE set to that of the pointer to the arg, not the arg
11781 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11782 const_tree type, bool named, int depth)
11784 machine_mode elt_mode;
11787 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11789 /* Only tick off an argument if we're not recursing. */
11791 cum->nargs_prototype--;
11793 #ifdef HAVE_AS_GNU_ATTRIBUTE
11794 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11797 if (SCALAR_FLOAT_MODE_P (mode))
11799 rs6000_passes_float = true;
11800 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11801 && (FLOAT128_IBM_P (mode)
11802 || FLOAT128_IEEE_P (mode)
11804 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11805 rs6000_passes_long_double = true;
11807 if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11808 || (PAIRED_VECTOR_MODE (mode)
11810 && cum->sysv_gregno <= GP_ARG_MAX_REG))
11811 rs6000_passes_vector = true;
11815 if (TARGET_ALTIVEC_ABI
11816 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11817 || (type && TREE_CODE (type) == VECTOR_TYPE
11818 && int_size_in_bytes (type) == 16)))
11820 bool stack = false;
11822 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11824 cum->vregno += n_elts;
11826 if (!TARGET_ALTIVEC)
11827 error ("cannot pass argument in vector register because"
11828 " altivec instructions are disabled, use %qs"
11829 " to enable them", "-maltivec");
11831 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11832 even if it is going to be passed in a vector register.
11833 Darwin does the same for variable-argument functions. */
11834 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11836 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11846 /* Vector parameters must be 16-byte aligned. In 32-bit
11847 mode this means we need to take into account the offset
11848 to the parameter save area. In 64-bit mode, they just
11849 have to start on an even word, since the parameter save
11850 area is 16-byte aligned. */
11852 align = -(rs6000_parm_offset () + cum->words) & 3;
11854 align = cum->words & 1;
11855 cum->words += align + rs6000_arg_size (mode, type);
11857 if (TARGET_DEBUG_ARG)
11859 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11860 cum->words, align);
11861 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11862 cum->nargs_prototype, cum->prototype,
11863 GET_MODE_NAME (mode));
11867 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11869 int size = int_size_in_bytes (type);
11870 /* Variable sized types have size == -1 and are
11871 treated as if consisting entirely of ints.
11872 Pad to 16 byte boundary if needed. */
11873 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11874 && (cum->words % 2) != 0)
11876 /* For varargs, we can just go up by the size of the struct. */
11878 cum->words += (size + 7) / 8;
11881 /* It is tempting to say int register count just goes up by
11882 sizeof(type)/8, but this is wrong in a case such as
11883 { int; double; int; } [powerpc alignment]. We have to
11884 grovel through the fields for these too. */
11885 cum->intoffset = 0;
11886 cum->floats_in_gpr = 0;
11887 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11888 rs6000_darwin64_record_arg_advance_flush (cum,
11889 size * BITS_PER_UNIT, 1);
11891 if (TARGET_DEBUG_ARG)
11893 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11894 cum->words, TYPE_ALIGN (type), size);
11896 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11897 cum->nargs_prototype, cum->prototype,
11898 GET_MODE_NAME (mode));
11901 else if (DEFAULT_ABI == ABI_V4)
11903 if (abi_v4_pass_in_fpr (mode))
11905 /* _Decimal128 must use an even/odd register pair. This assumes
11906 that the register number is odd when fregno is odd. */
11907 if (mode == TDmode && (cum->fregno % 2) == 1)
11910 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11911 <= FP_ARG_V4_MAX_REG)
11912 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11915 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11916 if (mode == DFmode || FLOAT128_IBM_P (mode)
11917 || mode == DDmode || mode == TDmode)
11918 cum->words += cum->words & 1;
11919 cum->words += rs6000_arg_size (mode, type);
11924 int n_words = rs6000_arg_size (mode, type);
11925 int gregno = cum->sysv_gregno;
11927 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11928 As does any other 2 word item such as complex int due to a
11929 historical mistake. */
11931 gregno += (1 - gregno) & 1;
11933 /* Multi-reg args are not split between registers and stack. */
11934 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11936 /* Long long is aligned on the stack. So are other 2 word
11937 items such as complex int due to a historical mistake. */
11939 cum->words += cum->words & 1;
11940 cum->words += n_words;
11943 /* Note: continuing to accumulate gregno past when we've started
11944 spilling to the stack indicates the fact that we've started
11945 spilling to the stack to expand_builtin_saveregs. */
11946 cum->sysv_gregno = gregno + n_words;
11949 if (TARGET_DEBUG_ARG)
11951 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11952 cum->words, cum->fregno);
11953 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11954 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11955 fprintf (stderr, "mode = %4s, named = %d\n",
11956 GET_MODE_NAME (mode), named);
11961 int n_words = rs6000_arg_size (mode, type);
11962 int start_words = cum->words;
11963 int align_words = rs6000_parm_start (mode, type, start_words);
11965 cum->words = align_words + n_words;
11967 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11969 /* _Decimal128 must be passed in an even/odd float register pair.
11970 This assumes that the register number is odd when fregno is
11972 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11974 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11977 if (TARGET_DEBUG_ARG)
11979 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11980 cum->words, cum->fregno);
11981 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11982 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11983 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11984 named, align_words - start_words, depth);
11990 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11991 const_tree type, bool named)
11993 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11997 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11998 structure between cum->intoffset and bitpos to integer registers. */
12001 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
12002 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
12005 unsigned int regno;
12006 unsigned int startbit, endbit;
12007 int this_regno, intregs, intoffset;
12010 if (cum->intoffset == -1)
12013 intoffset = cum->intoffset;
12014 cum->intoffset = -1;
12016 /* If this is the trailing part of a word, try to only load that
12017 much into the register. Otherwise load the whole register. Note
12018 that in the latter case we may pick up unwanted bits. It's not a
12019 problem at the moment but may wish to revisit. */
12021 if (intoffset % BITS_PER_WORD != 0)
12023 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
12024 if (!int_mode_for_size (bits, 0).exists (&mode))
12026 /* We couldn't find an appropriate mode, which happens,
12027 e.g., in packed structs when there are 3 bytes to load.
12028 Back intoffset back to the beginning of the word in this
12030 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
12037 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
12038 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
12039 intregs = (endbit - startbit) / BITS_PER_WORD;
12040 this_regno = cum->words + intoffset / BITS_PER_WORD;
12042 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
12043 cum->use_stack = 1;
12045 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
12049 intoffset /= BITS_PER_UNIT;
12052 regno = GP_ARG_MIN_REG + this_regno;
12053 reg = gen_rtx_REG (mode, regno);
12055 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
12058 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
12062 while (intregs > 0);
12065 /* Recursive workhorse for the following. */
12068 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
12069 HOST_WIDE_INT startbitpos, rtx rvec[],
12074 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
12075 if (TREE_CODE (f) == FIELD_DECL)
12077 HOST_WIDE_INT bitpos = startbitpos;
12078 tree ftype = TREE_TYPE (f);
12080 if (ftype == error_mark_node)
12082 mode = TYPE_MODE (ftype);
12084 if (DECL_SIZE (f) != 0
12085 && tree_fits_uhwi_p (bit_position (f)))
12086 bitpos += int_bit_position (f);
12088 /* ??? FIXME: else assume zero offset. */
12090 if (TREE_CODE (ftype) == RECORD_TYPE)
12091 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
12092 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
12094 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
12098 case E_SCmode: mode = SFmode; break;
12099 case E_DCmode: mode = DFmode; break;
12100 case E_TCmode: mode = TFmode; break;
12104 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12105 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
12107 gcc_assert (cum->fregno == FP_ARG_MAX_REG
12108 && (mode == TFmode || mode == TDmode));
12109 /* Long double or _Decimal128 split over regs and memory. */
12110 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12114 = gen_rtx_EXPR_LIST (VOIDmode,
12115 gen_rtx_REG (mode, cum->fregno++),
12116 GEN_INT (bitpos / BITS_PER_UNIT));
12117 if (FLOAT128_2REG_P (mode))
12120 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
12122 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12124 = gen_rtx_EXPR_LIST (VOIDmode,
12125 gen_rtx_REG (mode, cum->vregno++),
12126 GEN_INT (bitpos / BITS_PER_UNIT));
12128 else if (cum->intoffset == -1)
12129 cum->intoffset = bitpos;
12133 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12134 the register(s) to be used for each field and subfield of a struct
12135 being passed by value, along with the offset of where the
12136 register's value may be found in the block. FP fields go in FP
12137 register, vector fields go in vector registers, and everything
12138 else goes in int registers, packed as in memory.
12140 This code is also used for function return values. RETVAL indicates
12141 whether this is the case.
12143 Much of this is taken from the SPARC V9 port, which has a similar
12144 calling convention. */
12147 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
12148 bool named, bool retval)
12150 rtx rvec[FIRST_PSEUDO_REGISTER];
12151 int k = 1, kbase = 1;
12152 HOST_WIDE_INT typesize = int_size_in_bytes (type);
12153 /* This is a copy; modifications are not visible to our caller. */
12154 CUMULATIVE_ARGS copy_cum = *orig_cum;
12155 CUMULATIVE_ARGS *cum = ©_cum;
12157 /* Pad to 16 byte boundary if needed. */
12158 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
12159 && (cum->words % 2) != 0)
12162 cum->intoffset = 0;
12163 cum->use_stack = 0;
12164 cum->named = named;
12166 /* Put entries into rvec[] for individual FP and vector fields, and
12167 for the chunks of memory that go in int regs. Note we start at
12168 element 1; 0 is reserved for an indication of using memory, and
12169 may or may not be filled in below. */
12170 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
12171 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
12173 /* If any part of the struct went on the stack put all of it there.
12174 This hack is because the generic code for
12175 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12176 parts of the struct are not at the beginning. */
12177 if (cum->use_stack)
12180 return NULL_RTX; /* doesn't go in registers at all */
12182 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12184 if (k > 1 || cum->use_stack)
12185 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
12190 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12193 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
12198 rtx rvec[GP_ARG_NUM_REG + 1];
12200 if (align_words >= GP_ARG_NUM_REG)
12203 n_units = rs6000_arg_size (mode, type);
12205 /* Optimize the simple case where the arg fits in one gpr, except in
12206 the case of BLKmode due to assign_parms assuming that registers are
12207 BITS_PER_WORD wide. */
12209 || (n_units == 1 && mode != BLKmode))
12210 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12213 if (align_words + n_units > GP_ARG_NUM_REG)
12214 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12215 using a magic NULL_RTX component.
12216 This is not strictly correct. Only some of the arg belongs in
12217 memory, not all of it. However, the normal scheme using
12218 function_arg_partial_nregs can result in unusual subregs, eg.
12219 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12220 store the whole arg to memory is often more efficient than code
12221 to store pieces, and we know that space is available in the right
12222 place for the whole arg. */
12223 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12228 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12229 rtx off = GEN_INT (i++ * 4);
12230 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12232 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12234 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12237 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12238 but must also be copied into the parameter save area starting at
12239 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12240 to the GPRs and/or memory. Return the number of elements used. */
12243 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12244 int align_words, rtx *rvec)
12248 if (align_words < GP_ARG_NUM_REG)
12250 int n_words = rs6000_arg_size (mode, type);
12252 if (align_words + n_words > GP_ARG_NUM_REG
12254 || (TARGET_32BIT && TARGET_POWERPC64))
12256 /* If this is partially on the stack, then we only
12257 include the portion actually in registers here. */
12258 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12261 if (align_words + n_words > GP_ARG_NUM_REG)
12263 /* Not all of the arg fits in gprs. Say that it goes in memory
12264 too, using a magic NULL_RTX component. Also see comment in
12265 rs6000_mixed_function_arg for why the normal
12266 function_arg_partial_nregs scheme doesn't work in this case. */
12267 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12272 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12273 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12274 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12276 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12280 /* The whole arg fits in gprs. */
12281 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12282 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12287 /* It's entirely in memory. */
12288 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12294 /* RVEC is a vector of K components of an argument of mode MODE.
12295 Construct the final function_arg return value from it. */
12298 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12300 gcc_assert (k >= 1);
12302 /* Avoid returning a PARALLEL in the trivial cases. */
12305 if (XEXP (rvec[0], 0) == NULL_RTX)
12308 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12309 return XEXP (rvec[0], 0);
12312 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12315 /* Determine where to put an argument to a function.
12316 Value is zero to push the argument on the stack,
12317 or a hard register in which to store the argument.
12319 MODE is the argument's machine mode.
12320 TYPE is the data type of the argument (as a tree).
12321 This is null for libcalls where that information may
12323 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12324 the preceding args and about the function being called. It is
12325 not modified in this routine.
12326 NAMED is nonzero if this argument is a named parameter
12327 (otherwise it is an extra parameter matching an ellipsis).
12329 On RS/6000 the first eight words of non-FP are normally in registers
12330 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12331 Under V.4, the first 8 FP args are in registers.
12333 If this is floating-point and no prototype is specified, we use
12334 both an FP and integer register (or possibly FP reg and stack). Library
12335 functions (when CALL_LIBCALL is set) always have the proper types for args,
12336 so we can pass the FP value just in one register. emit_library_function
12337 doesn't support PARALLEL anyway.
12339 Note that for args passed by reference, function_arg will be called
12340 with MODE and TYPE set to that of the pointer to the arg, not the arg
12344 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12345 const_tree type, bool named)
12347 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12348 enum rs6000_abi abi = DEFAULT_ABI;
12349 machine_mode elt_mode;
12352 /* Return a marker to indicate whether CR1 needs to set or clear the
12353 bit that V.4 uses to say fp args were passed in registers.
12354 Assume that we don't need the marker for software floating point,
12355 or compiler generated library calls. */
12356 if (mode == VOIDmode)
12359 && (cum->call_cookie & CALL_LIBCALL) == 0
12361 || (cum->nargs_prototype < 0
12362 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12363 && TARGET_HARD_FLOAT)
12364 return GEN_INT (cum->call_cookie
12365 | ((cum->fregno == FP_ARG_MIN_REG)
12366 ? CALL_V4_SET_FP_ARGS
12367 : CALL_V4_CLEAR_FP_ARGS));
12369 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12372 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12374 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12376 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12377 if (rslt != NULL_RTX)
12379 /* Else fall through to usual handling. */
12382 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12384 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12388 /* Do we also need to pass this argument in the parameter save area?
12389 Library support functions for IEEE 128-bit are assumed to not need the
12390 value passed both in GPRs and in vector registers. */
12391 if (TARGET_64BIT && !cum->prototype
12392 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12394 int align_words = ROUND_UP (cum->words, 2);
12395 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12398 /* Describe where this argument goes in the vector registers. */
12399 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12401 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12402 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12403 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12406 return rs6000_finish_function_arg (mode, rvec, k);
12408 else if (TARGET_ALTIVEC_ABI
12409 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12410 || (type && TREE_CODE (type) == VECTOR_TYPE
12411 && int_size_in_bytes (type) == 16)))
12413 if (named || abi == ABI_V4)
12417 /* Vector parameters to varargs functions under AIX or Darwin
12418 get passed in memory and possibly also in GPRs. */
12419 int align, align_words, n_words;
12420 machine_mode part_mode;
12422 /* Vector parameters must be 16-byte aligned. In 32-bit
12423 mode this means we need to take into account the offset
12424 to the parameter save area. In 64-bit mode, they just
12425 have to start on an even word, since the parameter save
12426 area is 16-byte aligned. */
12428 align = -(rs6000_parm_offset () + cum->words) & 3;
12430 align = cum->words & 1;
12431 align_words = cum->words + align;
12433 /* Out of registers? Memory, then. */
12434 if (align_words >= GP_ARG_NUM_REG)
12437 if (TARGET_32BIT && TARGET_POWERPC64)
12438 return rs6000_mixed_function_arg (mode, type, align_words);
12440 /* The vector value goes in GPRs. Only the part of the
12441 value in GPRs is reported here. */
12443 n_words = rs6000_arg_size (mode, type);
12444 if (align_words + n_words > GP_ARG_NUM_REG)
12445 /* Fortunately, there are only two possibilities, the value
12446 is either wholly in GPRs or half in GPRs and half not. */
12447 part_mode = DImode;
12449 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12453 else if (abi == ABI_V4)
12455 if (abi_v4_pass_in_fpr (mode))
12457 /* _Decimal128 must use an even/odd register pair. This assumes
12458 that the register number is odd when fregno is odd. */
12459 if (mode == TDmode && (cum->fregno % 2) == 1)
12462 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12463 <= FP_ARG_V4_MAX_REG)
12464 return gen_rtx_REG (mode, cum->fregno);
12470 int n_words = rs6000_arg_size (mode, type);
12471 int gregno = cum->sysv_gregno;
12473 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12474 As does any other 2 word item such as complex int due to a
12475 historical mistake. */
12477 gregno += (1 - gregno) & 1;
12479 /* Multi-reg args are not split between registers and stack. */
12480 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12483 if (TARGET_32BIT && TARGET_POWERPC64)
12484 return rs6000_mixed_function_arg (mode, type,
12485 gregno - GP_ARG_MIN_REG);
12486 return gen_rtx_REG (mode, gregno);
12491 int align_words = rs6000_parm_start (mode, type, cum->words);
12493 /* _Decimal128 must be passed in an even/odd float register pair.
12494 This assumes that the register number is odd when fregno is odd. */
12495 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12498 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12500 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12503 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12506 /* Do we also need to pass this argument in the parameter
12508 if (type && (cum->nargs_prototype <= 0
12509 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12510 && TARGET_XL_COMPAT
12511 && align_words >= GP_ARG_NUM_REG)))
12512 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12514 /* Describe where this argument goes in the fprs. */
12515 for (i = 0; i < n_elts
12516 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12518 /* Check if the argument is split over registers and memory.
12519 This can only ever happen for long double or _Decimal128;
12520 complex types are handled via split_complex_arg. */
12521 machine_mode fmode = elt_mode;
12522 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12524 gcc_assert (FLOAT128_2REG_P (fmode));
12525 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12528 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12529 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12530 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12533 /* If there were not enough FPRs to hold the argument, the rest
12534 usually goes into memory. However, if the current position
12535 is still within the register parameter area, a portion may
12536 actually have to go into GPRs.
12538 Note that it may happen that the portion of the argument
12539 passed in the first "half" of the first GPR was already
12540 passed in the last FPR as well.
12542 For unnamed arguments, we already set up GPRs to cover the
12543 whole argument in rs6000_psave_function_arg, so there is
12544 nothing further to do at this point. */
12545 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12546 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12547 && cum->nargs_prototype > 0)
12549 static bool warned;
12551 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12552 int n_words = rs6000_arg_size (mode, type);
12554 align_words += fpr_words;
12555 n_words -= fpr_words;
12559 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12560 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12561 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12563 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12565 if (!warned && warn_psabi)
12568 inform (input_location,
12569 "the ABI of passing homogeneous float aggregates"
12570 " has changed in GCC 5");
12574 return rs6000_finish_function_arg (mode, rvec, k);
12576 else if (align_words < GP_ARG_NUM_REG)
12578 if (TARGET_32BIT && TARGET_POWERPC64)
12579 return rs6000_mixed_function_arg (mode, type, align_words);
12581 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12588 /* For an arg passed partly in registers and partly in memory, this is
12589 the number of bytes passed in registers. For args passed entirely in
12590 registers or entirely in memory, zero. When an arg is described by a
12591 PARALLEL, perhaps using more than one register type, this function
12592 returns the number of bytes used by the first element of the PARALLEL. */
12595 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12596 tree type, bool named)
12598 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12599 bool passed_in_gprs = true;
12602 machine_mode elt_mode;
12605 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12607 if (DEFAULT_ABI == ABI_V4)
12610 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12612 /* If we are passing this arg in the fixed parameter save area (gprs or
12613 memory) as well as VRs, we do not use the partial bytes mechanism;
12614 instead, rs6000_function_arg will return a PARALLEL including a memory
12615 element as necessary. Library support functions for IEEE 128-bit are
12616 assumed to not need the value passed both in GPRs and in vector
12618 if (TARGET_64BIT && !cum->prototype
12619 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12622 /* Otherwise, we pass in VRs only. Check for partial copies. */
12623 passed_in_gprs = false;
12624 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12625 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12628 /* In this complicated case we just disable the partial_nregs code. */
12629 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12632 align_words = rs6000_parm_start (mode, type, cum->words);
12634 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12636 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12638 /* If we are passing this arg in the fixed parameter save area
12639 (gprs or memory) as well as FPRs, we do not use the partial
12640 bytes mechanism; instead, rs6000_function_arg will return a
12641 PARALLEL including a memory element as necessary. */
12643 && (cum->nargs_prototype <= 0
12644 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12645 && TARGET_XL_COMPAT
12646 && align_words >= GP_ARG_NUM_REG)))
12649 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12650 passed_in_gprs = false;
12651 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12653 /* Compute number of bytes / words passed in FPRs. If there
12654 is still space available in the register parameter area
12655 *after* that amount, a part of the argument will be passed
12656 in GPRs. In that case, the total amount passed in any
12657 registers is equal to the amount that would have been passed
12658 in GPRs if everything were passed there, so we fall back to
12659 the GPR code below to compute the appropriate value. */
12660 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12661 * MIN (8, GET_MODE_SIZE (elt_mode)));
12662 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12664 if (align_words + fpr_words < GP_ARG_NUM_REG)
12665 passed_in_gprs = true;
12672 && align_words < GP_ARG_NUM_REG
12673 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12674 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12676 if (ret != 0 && TARGET_DEBUG_ARG)
12677 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12682 /* A C expression that indicates when an argument must be passed by
12683 reference. If nonzero for an argument, a copy of that argument is
12684 made in memory and a pointer to the argument is passed instead of
12685 the argument itself. The pointer is passed in whatever way is
12686 appropriate for passing a pointer to that type.
12688 Under V.4, aggregates and long double are passed by reference.
12690 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12691 reference unless the AltiVec vector extension ABI is in force.
12693 As an extension to all ABIs, variable sized types are passed by
12697 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12698 machine_mode mode, const_tree type,
12699 bool named ATTRIBUTE_UNUSED)
12704 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12705 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12707 if (TARGET_DEBUG_ARG)
12708 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12712 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12714 if (TARGET_DEBUG_ARG)
12715 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12719 if (int_size_in_bytes (type) < 0)
12721 if (TARGET_DEBUG_ARG)
12722 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12726 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12727 modes only exist for GCC vector types if -maltivec. */
12728 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12730 if (TARGET_DEBUG_ARG)
12731 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12735 /* Pass synthetic vectors in memory. */
12736 if (TREE_CODE (type) == VECTOR_TYPE
12737 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12739 static bool warned_for_pass_big_vectors = false;
12740 if (TARGET_DEBUG_ARG)
12741 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12742 if (!warned_for_pass_big_vectors)
12744 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12745 "non-standard ABI extension with no compatibility "
12747 warned_for_pass_big_vectors = true;
12755 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12756 already processes. Return true if the parameter must be passed
12757 (fully or partially) on the stack. */
12760 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12766 /* Catch errors. */
12767 if (type == NULL || type == error_mark_node)
12770 /* Handle types with no storage requirement. */
12771 if (TYPE_MODE (type) == VOIDmode)
12774 /* Handle complex types. */
12775 if (TREE_CODE (type) == COMPLEX_TYPE)
12776 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12777 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12779 /* Handle transparent aggregates. */
12780 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12781 && TYPE_TRANSPARENT_AGGR (type))
12782 type = TREE_TYPE (first_field (type));
12784 /* See if this arg was passed by invisible reference. */
12785 if (pass_by_reference (get_cumulative_args (args_so_far),
12786 TYPE_MODE (type), type, true))
12787 type = build_pointer_type (type);
12789 /* Find mode as it is passed by the ABI. */
12790 unsignedp = TYPE_UNSIGNED (type);
12791 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12793 /* If we must pass in stack, we need a stack. */
12794 if (rs6000_must_pass_in_stack (mode, type))
12797 /* If there is no incoming register, we need a stack. */
12798 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12799 if (entry_parm == NULL)
12802 /* Likewise if we need to pass both in registers and on the stack. */
12803 if (GET_CODE (entry_parm) == PARALLEL
12804 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12807 /* Also true if we're partially in registers and partially not. */
12808 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12811 /* Update info on where next arg arrives in registers. */
12812 rs6000_function_arg_advance (args_so_far, mode, type, true);
12816 /* Return true if FUN has no prototype, has a variable argument
12817 list, or passes any parameter in memory. */
12820 rs6000_function_parms_need_stack (tree fun, bool incoming)
12822 tree fntype, result;
12823 CUMULATIVE_ARGS args_so_far_v;
12824 cumulative_args_t args_so_far;
12827 /* Must be a libcall, all of which only use reg parms. */
12832 fntype = TREE_TYPE (fun);
12834 /* Varargs functions need the parameter save area. */
12835 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12838 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12839 args_so_far = pack_cumulative_args (&args_so_far_v);
12841 /* When incoming, we will have been passed the function decl.
12842 It is necessary to use the decl to handle K&R style functions,
12843 where TYPE_ARG_TYPES may not be available. */
12846 gcc_assert (DECL_P (fun));
12847 result = DECL_RESULT (fun);
12850 result = TREE_TYPE (fntype);
12852 if (result && aggregate_value_p (result, fntype))
12854 if (!TYPE_P (result))
12855 result = TREE_TYPE (result);
12856 result = build_pointer_type (result);
12857 rs6000_parm_needs_stack (args_so_far, result);
12864 for (parm = DECL_ARGUMENTS (fun);
12865 parm && parm != void_list_node;
12866 parm = TREE_CHAIN (parm))
12867 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12872 function_args_iterator args_iter;
12875 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12876 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12883 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12884 usually a constant depending on the ABI. However, in the ELFv2 ABI
12885 the register parameter area is optional when calling a function that
12886 has a prototype is scope, has no variable argument list, and passes
12887 all parameters in registers. */
12890 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12892 int reg_parm_stack_space;
12894 switch (DEFAULT_ABI)
12897 reg_parm_stack_space = 0;
12902 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12906 /* ??? Recomputing this every time is a bit expensive. Is there
12907 a place to cache this information? */
12908 if (rs6000_function_parms_need_stack (fun, incoming))
12909 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12911 reg_parm_stack_space = 0;
12915 return reg_parm_stack_space;
12919 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12922 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12927 for (i = 0; i < nregs; i++)
12929 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12930 if (reload_completed)
12932 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12935 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12936 i * GET_MODE_SIZE (reg_mode));
12939 tem = replace_equiv_address (tem, XEXP (tem, 0));
12943 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12947 /* Perform any needed actions needed for a function that is receiving a
12948 variable number of arguments.
12952 MODE and TYPE are the mode and type of the current parameter.
12954 PRETEND_SIZE is a variable that should be set to the amount of stack
12955 that must be pushed by the prolog to pretend that our caller pushed
12958 Normally, this macro will push all remaining incoming registers on the
12959 stack and set PRETEND_SIZE to the length of the registers pushed. */
12962 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12963 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12966 CUMULATIVE_ARGS next_cum;
12967 int reg_size = TARGET_32BIT ? 4 : 8;
12968 rtx save_area = NULL_RTX, mem;
12969 int first_reg_offset;
12970 alias_set_type set;
12972 /* Skip the last named argument. */
12973 next_cum = *get_cumulative_args (cum);
12974 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12976 if (DEFAULT_ABI == ABI_V4)
12978 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12982 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12983 HOST_WIDE_INT offset = 0;
12985 /* Try to optimize the size of the varargs save area.
12986 The ABI requires that ap.reg_save_area is doubleword
12987 aligned, but we don't need to allocate space for all
12988 the bytes, only those to which we actually will save
12990 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12991 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12992 if (TARGET_HARD_FLOAT
12993 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12994 && cfun->va_list_fpr_size)
12997 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12998 * UNITS_PER_FP_WORD;
12999 if (cfun->va_list_fpr_size
13000 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13001 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
13003 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13004 * UNITS_PER_FP_WORD;
13008 offset = -((first_reg_offset * reg_size) & ~7);
13009 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
13011 gpr_reg_num = cfun->va_list_gpr_size;
13012 if (reg_size == 4 && (first_reg_offset & 1))
13015 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
13018 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
13019 * UNITS_PER_FP_WORD
13020 - (int) (GP_ARG_NUM_REG * reg_size);
13022 if (gpr_size + fpr_size)
13025 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
13026 gcc_assert (GET_CODE (reg_save_area) == MEM);
13027 reg_save_area = XEXP (reg_save_area, 0);
13028 if (GET_CODE (reg_save_area) == PLUS)
13030 gcc_assert (XEXP (reg_save_area, 0)
13031 == virtual_stack_vars_rtx);
13032 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
13033 offset += INTVAL (XEXP (reg_save_area, 1));
13036 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
13039 cfun->machine->varargs_save_offset = offset;
13040 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
13045 first_reg_offset = next_cum.words;
13046 save_area = crtl->args.internal_arg_pointer;
13048 if (targetm.calls.must_pass_in_stack (mode, type))
13049 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
13052 set = get_varargs_alias_set ();
13053 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
13054 && cfun->va_list_gpr_size)
13056 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
13058 if (va_list_gpr_counter_field)
13059 /* V4 va_list_gpr_size counts number of registers needed. */
13060 n_gpr = cfun->va_list_gpr_size;
13062 /* char * va_list instead counts number of bytes needed. */
13063 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
13068 mem = gen_rtx_MEM (BLKmode,
13069 plus_constant (Pmode, save_area,
13070 first_reg_offset * reg_size));
13071 MEM_NOTRAP_P (mem) = 1;
13072 set_mem_alias_set (mem, set);
13073 set_mem_align (mem, BITS_PER_WORD);
13075 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
13079 /* Save FP registers if needed. */
13080 if (DEFAULT_ABI == ABI_V4
13081 && TARGET_HARD_FLOAT
13083 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13084 && cfun->va_list_fpr_size)
13086 int fregno = next_cum.fregno, nregs;
13087 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
13088 rtx lab = gen_label_rtx ();
13089 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
13090 * UNITS_PER_FP_WORD);
13093 (gen_rtx_SET (pc_rtx,
13094 gen_rtx_IF_THEN_ELSE (VOIDmode,
13095 gen_rtx_NE (VOIDmode, cr1,
13097 gen_rtx_LABEL_REF (VOIDmode, lab),
13101 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
13102 fregno++, off += UNITS_PER_FP_WORD, nregs++)
13104 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13106 plus_constant (Pmode, save_area, off));
13107 MEM_NOTRAP_P (mem) = 1;
13108 set_mem_alias_set (mem, set);
13109 set_mem_align (mem, GET_MODE_ALIGNMENT (
13110 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13111 ? DFmode : SFmode));
13112 emit_move_insn (mem, gen_rtx_REG (
13113 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13114 ? DFmode : SFmode, fregno));
13121 /* Create the va_list data type. */
13124 rs6000_build_builtin_va_list (void)
13126 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
13128 /* For AIX, prefer 'char *' because that's what the system
13129 header files like. */
13130 if (DEFAULT_ABI != ABI_V4)
13131 return build_pointer_type (char_type_node);
13133 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
13134 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
13135 get_identifier ("__va_list_tag"), record);
13137 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
13138 unsigned_char_type_node);
13139 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
13140 unsigned_char_type_node);
13141 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13142 every user file. */
13143 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13144 get_identifier ("reserved"), short_unsigned_type_node);
13145 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13146 get_identifier ("overflow_arg_area"),
13148 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13149 get_identifier ("reg_save_area"),
13152 va_list_gpr_counter_field = f_gpr;
13153 va_list_fpr_counter_field = f_fpr;
13155 DECL_FIELD_CONTEXT (f_gpr) = record;
13156 DECL_FIELD_CONTEXT (f_fpr) = record;
13157 DECL_FIELD_CONTEXT (f_res) = record;
13158 DECL_FIELD_CONTEXT (f_ovf) = record;
13159 DECL_FIELD_CONTEXT (f_sav) = record;
13161 TYPE_STUB_DECL (record) = type_decl;
13162 TYPE_NAME (record) = type_decl;
13163 TYPE_FIELDS (record) = f_gpr;
13164 DECL_CHAIN (f_gpr) = f_fpr;
13165 DECL_CHAIN (f_fpr) = f_res;
13166 DECL_CHAIN (f_res) = f_ovf;
13167 DECL_CHAIN (f_ovf) = f_sav;
13169 layout_type (record);
13171 /* The correct type is an array type of one element. */
13172 return build_array_type (record, build_index_type (size_zero_node));
13175 /* Implement va_start. */
13178 rs6000_va_start (tree valist, rtx nextarg)
13180 HOST_WIDE_INT words, n_gpr, n_fpr;
13181 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13182 tree gpr, fpr, ovf, sav, t;
13184 /* Only SVR4 needs something special. */
13185 if (DEFAULT_ABI != ABI_V4)
13187 std_expand_builtin_va_start (valist, nextarg);
13191 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13192 f_fpr = DECL_CHAIN (f_gpr);
13193 f_res = DECL_CHAIN (f_fpr);
13194 f_ovf = DECL_CHAIN (f_res);
13195 f_sav = DECL_CHAIN (f_ovf);
13197 valist = build_simple_mem_ref (valist);
13198 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13199 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13201 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13203 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13206 /* Count number of gp and fp argument registers used. */
13207 words = crtl->args.info.words;
13208 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
13210 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
13213 if (TARGET_DEBUG_ARG)
13214 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
13215 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
13216 words, n_gpr, n_fpr);
13218 if (cfun->va_list_gpr_size)
13220 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13221 build_int_cst (NULL_TREE, n_gpr));
13222 TREE_SIDE_EFFECTS (t) = 1;
13223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13226 if (cfun->va_list_fpr_size)
13228 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13229 build_int_cst (NULL_TREE, n_fpr));
13230 TREE_SIDE_EFFECTS (t) = 1;
13231 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13233 #ifdef HAVE_AS_GNU_ATTRIBUTE
13234 if (call_ABI_of_interest (cfun->decl))
13235 rs6000_passes_float = true;
13239 /* Find the overflow area. */
13240 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13242 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13243 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13244 TREE_SIDE_EFFECTS (t) = 1;
13245 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13247 /* If there were no va_arg invocations, don't set up the register
13249 if (!cfun->va_list_gpr_size
13250 && !cfun->va_list_fpr_size
13251 && n_gpr < GP_ARG_NUM_REG
13252 && n_fpr < FP_ARG_V4_MAX_REG)
13255 /* Find the register save area. */
13256 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13257 if (cfun->machine->varargs_save_offset)
13258 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13259 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13260 TREE_SIDE_EFFECTS (t) = 1;
13261 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13264 /* Implement va_arg. */
13267 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13268 gimple_seq *post_p)
13270 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13271 tree gpr, fpr, ovf, sav, reg, t, u;
13272 int size, rsize, n_reg, sav_ofs, sav_scale;
13273 tree lab_false, lab_over, addr;
13275 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13279 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13281 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13282 return build_va_arg_indirect_ref (t);
13285 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13286 earlier version of gcc, with the property that it always applied alignment
13287 adjustments to the va-args (even for zero-sized types). The cheapest way
13288 to deal with this is to replicate the effect of the part of
13289 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13291 We don't need to check for pass-by-reference because of the test above.
13292 We can return a simplifed answer, since we know there's no offset to add. */
13295 && rs6000_darwin64_abi)
13296 || DEFAULT_ABI == ABI_ELFv2
13297 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13298 && integer_zerop (TYPE_SIZE (type)))
13300 unsigned HOST_WIDE_INT align, boundary;
13301 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13302 align = PARM_BOUNDARY / BITS_PER_UNIT;
13303 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13304 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13305 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13306 boundary /= BITS_PER_UNIT;
13307 if (boundary > align)
13310 /* This updates arg ptr by the amount that would be necessary
13311 to align the zero-sized (but not zero-alignment) item. */
13312 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13313 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13314 gimplify_and_add (t, pre_p);
13316 t = fold_convert (sizetype, valist_tmp);
13317 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13318 fold_convert (TREE_TYPE (valist),
13319 fold_build2 (BIT_AND_EXPR, sizetype, t,
13320 size_int (-boundary))));
13321 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13322 gimplify_and_add (t, pre_p);
13324 /* Since it is zero-sized there's no increment for the item itself. */
13325 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13326 return build_va_arg_indirect_ref (valist_tmp);
13329 if (DEFAULT_ABI != ABI_V4)
13331 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13333 tree elem_type = TREE_TYPE (type);
13334 machine_mode elem_mode = TYPE_MODE (elem_type);
13335 int elem_size = GET_MODE_SIZE (elem_mode);
13337 if (elem_size < UNITS_PER_WORD)
13339 tree real_part, imag_part;
13340 gimple_seq post = NULL;
13342 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13344 /* Copy the value into a temporary, lest the formal temporary
13345 be reused out from under us. */
13346 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13347 gimple_seq_add_seq (pre_p, post);
13349 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13352 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13356 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13359 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13360 f_fpr = DECL_CHAIN (f_gpr);
13361 f_res = DECL_CHAIN (f_fpr);
13362 f_ovf = DECL_CHAIN (f_res);
13363 f_sav = DECL_CHAIN (f_ovf);
13365 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13366 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13368 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13370 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13373 size = int_size_in_bytes (type);
13374 rsize = (size + 3) / 4;
13375 int pad = 4 * rsize - size;
13378 machine_mode mode = TYPE_MODE (type);
13379 if (abi_v4_pass_in_fpr (mode))
13381 /* FP args go in FP registers, if present. */
13383 n_reg = (size + 7) / 8;
13384 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
13385 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
13386 if (mode != SFmode && mode != SDmode)
13391 /* Otherwise into GP registers. */
13400 /* Pull the value out of the saved registers.... */
13403 addr = create_tmp_var (ptr_type_node, "addr");
13405 /* AltiVec vectors never go in registers when -mabi=altivec. */
13406 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13410 lab_false = create_artificial_label (input_location);
13411 lab_over = create_artificial_label (input_location);
13413 /* Long long is aligned in the registers. As are any other 2 gpr
13414 item such as complex int due to a historical mistake. */
13416 if (n_reg == 2 && reg == gpr)
13419 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13420 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13421 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13422 unshare_expr (reg), u);
13424 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13425 reg number is 0 for f1, so we want to make it odd. */
13426 else if (reg == fpr && mode == TDmode)
13428 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13429 build_int_cst (TREE_TYPE (reg), 1));
13430 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13433 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13434 t = build2 (GE_EXPR, boolean_type_node, u, t);
13435 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13436 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13437 gimplify_and_add (t, pre_p);
13441 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13443 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13444 build_int_cst (TREE_TYPE (reg), n_reg));
13445 u = fold_convert (sizetype, u);
13446 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13447 t = fold_build_pointer_plus (t, u);
13449 /* _Decimal32 varargs are located in the second word of the 64-bit
13450 FP register for 32-bit binaries. */
13451 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13452 t = fold_build_pointer_plus_hwi (t, size);
13454 /* Args are passed right-aligned. */
13455 if (BYTES_BIG_ENDIAN)
13456 t = fold_build_pointer_plus_hwi (t, pad);
13458 gimplify_assign (addr, t, pre_p);
13460 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13462 stmt = gimple_build_label (lab_false);
13463 gimple_seq_add_stmt (pre_p, stmt);
13465 if ((n_reg == 2 && !regalign) || n_reg > 2)
13467 /* Ensure that we don't find any more args in regs.
13468 Alignment has taken care of for special cases. */
13469 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13473 /* ... otherwise out of the overflow area. */
13475 /* Care for on-stack alignment if needed. */
13479 t = fold_build_pointer_plus_hwi (t, align - 1);
13480 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13481 build_int_cst (TREE_TYPE (t), -align));
13484 /* Args are passed right-aligned. */
13485 if (BYTES_BIG_ENDIAN)
13486 t = fold_build_pointer_plus_hwi (t, pad);
13488 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13490 gimplify_assign (unshare_expr (addr), t, pre_p);
13492 t = fold_build_pointer_plus_hwi (t, size);
13493 gimplify_assign (unshare_expr (ovf), t, pre_p);
13497 stmt = gimple_build_label (lab_over);
13498 gimple_seq_add_stmt (pre_p, stmt);
13501 if (STRICT_ALIGNMENT
13502 && (TYPE_ALIGN (type)
13503 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13505 /* The value (of type complex double, for example) may not be
13506 aligned in memory in the saved registers, so copy via a
13507 temporary. (This is the same code as used for SPARC.) */
13508 tree tmp = create_tmp_var (type, "va_arg_tmp");
13509 tree dest_addr = build_fold_addr_expr (tmp);
13511 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13512 3, dest_addr, addr, size_int (rsize * 4));
13514 gimplify_and_add (copy, pre_p);
13518 addr = fold_convert (ptrtype, addr);
13519 return build_va_arg_indirect_ref (addr);
13525 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13528 unsigned classify = rs6000_builtin_info[(int)code].attr;
13529 const char *attr_string = "";
13531 gcc_assert (name != NULL);
13532 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13534 if (rs6000_builtin_decls[(int)code])
13535 fatal_error (input_location,
13536 "internal error: builtin function %qs already processed",
13539 rs6000_builtin_decls[(int)code] = t =
13540 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13542 /* Set any special attributes. */
13543 if ((classify & RS6000_BTC_CONST) != 0)
13545 /* const function, function only depends on the inputs. */
13546 TREE_READONLY (t) = 1;
13547 TREE_NOTHROW (t) = 1;
13548 attr_string = ", const";
13550 else if ((classify & RS6000_BTC_PURE) != 0)
13552 /* pure function, function can read global memory, but does not set any
13554 DECL_PURE_P (t) = 1;
13555 TREE_NOTHROW (t) = 1;
13556 attr_string = ", pure";
13558 else if ((classify & RS6000_BTC_FP) != 0)
13560 /* Function is a math function. If rounding mode is on, then treat the
13561 function as not reading global memory, but it can have arbitrary side
13562 effects. If it is off, then assume the function is a const function.
13563 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13564 builtin-attribute.def that is used for the math functions. */
13565 TREE_NOTHROW (t) = 1;
13566 if (flag_rounding_math)
13568 DECL_PURE_P (t) = 1;
13569 DECL_IS_NOVOPS (t) = 1;
13570 attr_string = ", fp, pure";
13574 TREE_READONLY (t) = 1;
13575 attr_string = ", fp, const";
13578 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13579 gcc_unreachable ();
13581 if (TARGET_DEBUG_BUILTIN)
13582 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13583 (int)code, name, attr_string);
13586 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13588 #undef RS6000_BUILTIN_0
13589 #undef RS6000_BUILTIN_1
13590 #undef RS6000_BUILTIN_2
13591 #undef RS6000_BUILTIN_3
13592 #undef RS6000_BUILTIN_A
13593 #undef RS6000_BUILTIN_D
13594 #undef RS6000_BUILTIN_H
13595 #undef RS6000_BUILTIN_P
13596 #undef RS6000_BUILTIN_Q
13597 #undef RS6000_BUILTIN_X
13599 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13600 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13601 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13602 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13603 { MASK, ICODE, NAME, ENUM },
13605 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13606 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13607 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13608 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13609 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13610 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13612 static const struct builtin_description bdesc_3arg[] =
13614 #include "rs6000-builtin.def"
13617 /* DST operations: void foo (void *, const int, const char). */
13619 #undef RS6000_BUILTIN_0
13620 #undef RS6000_BUILTIN_1
13621 #undef RS6000_BUILTIN_2
13622 #undef RS6000_BUILTIN_3
13623 #undef RS6000_BUILTIN_A
13624 #undef RS6000_BUILTIN_D
13625 #undef RS6000_BUILTIN_H
13626 #undef RS6000_BUILTIN_P
13627 #undef RS6000_BUILTIN_Q
13628 #undef RS6000_BUILTIN_X
13630 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13631 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13632 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13633 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13634 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13635 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13636 { MASK, ICODE, NAME, ENUM },
13638 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13639 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13640 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13641 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13643 static const struct builtin_description bdesc_dst[] =
13645 #include "rs6000-builtin.def"
13648 /* Simple binary operations: VECc = foo (VECa, VECb). */
13650 #undef RS6000_BUILTIN_0
13651 #undef RS6000_BUILTIN_1
13652 #undef RS6000_BUILTIN_2
13653 #undef RS6000_BUILTIN_3
13654 #undef RS6000_BUILTIN_A
13655 #undef RS6000_BUILTIN_D
13656 #undef RS6000_BUILTIN_H
13657 #undef RS6000_BUILTIN_P
13658 #undef RS6000_BUILTIN_Q
13659 #undef RS6000_BUILTIN_X
13661 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13662 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13663 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13664 { MASK, ICODE, NAME, ENUM },
13666 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13667 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13668 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13669 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13670 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13671 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13672 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13674 static const struct builtin_description bdesc_2arg[] =
13676 #include "rs6000-builtin.def"
13679 #undef RS6000_BUILTIN_0
13680 #undef RS6000_BUILTIN_1
13681 #undef RS6000_BUILTIN_2
13682 #undef RS6000_BUILTIN_3
13683 #undef RS6000_BUILTIN_A
13684 #undef RS6000_BUILTIN_D
13685 #undef RS6000_BUILTIN_H
13686 #undef RS6000_BUILTIN_P
13687 #undef RS6000_BUILTIN_Q
13688 #undef RS6000_BUILTIN_X
13690 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13691 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13692 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13693 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13694 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13695 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13696 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13697 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13698 { MASK, ICODE, NAME, ENUM },
13700 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13701 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13703 /* AltiVec predicates. */
13705 static const struct builtin_description bdesc_altivec_preds[] =
13707 #include "rs6000-builtin.def"
13710 /* PAIRED predicates. */
13711 #undef RS6000_BUILTIN_0
13712 #undef RS6000_BUILTIN_1
13713 #undef RS6000_BUILTIN_2
13714 #undef RS6000_BUILTIN_3
13715 #undef RS6000_BUILTIN_A
13716 #undef RS6000_BUILTIN_D
13717 #undef RS6000_BUILTIN_H
13718 #undef RS6000_BUILTIN_P
13719 #undef RS6000_BUILTIN_Q
13720 #undef RS6000_BUILTIN_X
13722 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13723 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13724 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13725 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13726 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13727 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13728 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13729 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13730 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13731 { MASK, ICODE, NAME, ENUM },
13733 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13735 static const struct builtin_description bdesc_paired_preds[] =
13737 #include "rs6000-builtin.def"
13740 /* ABS* operations. */
13742 #undef RS6000_BUILTIN_0
13743 #undef RS6000_BUILTIN_1
13744 #undef RS6000_BUILTIN_2
13745 #undef RS6000_BUILTIN_3
13746 #undef RS6000_BUILTIN_A
13747 #undef RS6000_BUILTIN_D
13748 #undef RS6000_BUILTIN_H
13749 #undef RS6000_BUILTIN_P
13750 #undef RS6000_BUILTIN_Q
13751 #undef RS6000_BUILTIN_X
13753 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13754 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13755 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13756 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13757 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13758 { MASK, ICODE, NAME, ENUM },
13760 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13761 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13762 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13763 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13764 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13766 static const struct builtin_description bdesc_abs[] =
13768 #include "rs6000-builtin.def"
13771 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13774 #undef RS6000_BUILTIN_0
13775 #undef RS6000_BUILTIN_1
13776 #undef RS6000_BUILTIN_2
13777 #undef RS6000_BUILTIN_3
13778 #undef RS6000_BUILTIN_A
13779 #undef RS6000_BUILTIN_D
13780 #undef RS6000_BUILTIN_H
13781 #undef RS6000_BUILTIN_P
13782 #undef RS6000_BUILTIN_Q
13783 #undef RS6000_BUILTIN_X
13785 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13786 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13787 { MASK, ICODE, NAME, ENUM },
13789 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13790 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13791 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13792 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13793 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13794 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13795 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13796 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13798 static const struct builtin_description bdesc_1arg[] =
13800 #include "rs6000-builtin.def"
13803 /* Simple no-argument operations: result = __builtin_darn_32 () */
13805 #undef RS6000_BUILTIN_0
13806 #undef RS6000_BUILTIN_1
13807 #undef RS6000_BUILTIN_2
13808 #undef RS6000_BUILTIN_3
13809 #undef RS6000_BUILTIN_A
13810 #undef RS6000_BUILTIN_D
13811 #undef RS6000_BUILTIN_H
13812 #undef RS6000_BUILTIN_P
13813 #undef RS6000_BUILTIN_Q
13814 #undef RS6000_BUILTIN_X
13816 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13817 { MASK, ICODE, NAME, ENUM },
13819 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13820 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13821 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13822 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13823 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13824 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13825 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13826 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13827 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13829 static const struct builtin_description bdesc_0arg[] =
13831 #include "rs6000-builtin.def"
13834 /* HTM builtins. */
13835 #undef RS6000_BUILTIN_0
13836 #undef RS6000_BUILTIN_1
13837 #undef RS6000_BUILTIN_2
13838 #undef RS6000_BUILTIN_3
13839 #undef RS6000_BUILTIN_A
13840 #undef RS6000_BUILTIN_D
13841 #undef RS6000_BUILTIN_H
13842 #undef RS6000_BUILTIN_P
13843 #undef RS6000_BUILTIN_Q
13844 #undef RS6000_BUILTIN_X
13846 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13847 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13848 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13849 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13850 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13851 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13852 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13853 { MASK, ICODE, NAME, ENUM },
13855 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13856 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13857 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13859 static const struct builtin_description bdesc_htm[] =
13861 #include "rs6000-builtin.def"
13864 #undef RS6000_BUILTIN_0
13865 #undef RS6000_BUILTIN_1
13866 #undef RS6000_BUILTIN_2
13867 #undef RS6000_BUILTIN_3
13868 #undef RS6000_BUILTIN_A
13869 #undef RS6000_BUILTIN_D
13870 #undef RS6000_BUILTIN_H
13871 #undef RS6000_BUILTIN_P
13872 #undef RS6000_BUILTIN_Q
13874 /* Return true if a builtin function is overloaded. */
13876 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13878 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13882 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13884 return rs6000_builtin_info[(int)fncode].name;
13887 /* Expand an expression EXP that calls a builtin without arguments. */
13889 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13892 machine_mode tmode = insn_data[icode].operand[0].mode;
13894 if (icode == CODE_FOR_nothing)
13895 /* Builtin not supported on this processor. */
13899 || GET_MODE (target) != tmode
13900 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13901 target = gen_reg_rtx (tmode);
13903 pat = GEN_FCN (icode) (target);
13913 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13916 tree arg0 = CALL_EXPR_ARG (exp, 0);
13917 tree arg1 = CALL_EXPR_ARG (exp, 1);
13918 rtx op0 = expand_normal (arg0);
13919 rtx op1 = expand_normal (arg1);
13920 machine_mode mode0 = insn_data[icode].operand[0].mode;
13921 machine_mode mode1 = insn_data[icode].operand[1].mode;
13923 if (icode == CODE_FOR_nothing)
13924 /* Builtin not supported on this processor. */
13927 /* If we got invalid arguments bail out before generating bad rtl. */
13928 if (arg0 == error_mark_node || arg1 == error_mark_node)
13931 if (GET_CODE (op0) != CONST_INT
13932 || INTVAL (op0) > 255
13933 || INTVAL (op0) < 0)
13935 error ("argument 1 must be an 8-bit field value");
13939 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13940 op0 = copy_to_mode_reg (mode0, op0);
13942 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13943 op1 = copy_to_mode_reg (mode1, op1);
13945 pat = GEN_FCN (icode) (op0, op1);
13954 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13957 tree arg0 = CALL_EXPR_ARG (exp, 0);
13958 rtx op0 = expand_normal (arg0);
13959 machine_mode tmode = insn_data[icode].operand[0].mode;
13960 machine_mode mode0 = insn_data[icode].operand[1].mode;
13962 if (icode == CODE_FOR_nothing)
13963 /* Builtin not supported on this processor. */
13966 /* If we got invalid arguments bail out before generating bad rtl. */
13967 if (arg0 == error_mark_node)
13970 if (icode == CODE_FOR_altivec_vspltisb
13971 || icode == CODE_FOR_altivec_vspltish
13972 || icode == CODE_FOR_altivec_vspltisw)
13974 /* Only allow 5-bit *signed* literals. */
13975 if (GET_CODE (op0) != CONST_INT
13976 || INTVAL (op0) > 15
13977 || INTVAL (op0) < -16)
13979 error ("argument 1 must be a 5-bit signed literal");
13980 return CONST0_RTX (tmode);
13985 || GET_MODE (target) != tmode
13986 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13987 target = gen_reg_rtx (tmode);
13989 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13990 op0 = copy_to_mode_reg (mode0, op0);
13992 pat = GEN_FCN (icode) (target, op0);
14001 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
14003 rtx pat, scratch1, scratch2;
14004 tree arg0 = CALL_EXPR_ARG (exp, 0);
14005 rtx op0 = expand_normal (arg0);
14006 machine_mode tmode = insn_data[icode].operand[0].mode;
14007 machine_mode mode0 = insn_data[icode].operand[1].mode;
14009 /* If we have invalid arguments, bail out before generating bad rtl. */
14010 if (arg0 == error_mark_node)
14014 || GET_MODE (target) != tmode
14015 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14016 target = gen_reg_rtx (tmode);
14018 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14019 op0 = copy_to_mode_reg (mode0, op0);
14021 scratch1 = gen_reg_rtx (mode0);
14022 scratch2 = gen_reg_rtx (mode0);
14024 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
14033 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
14036 tree arg0 = CALL_EXPR_ARG (exp, 0);
14037 tree arg1 = CALL_EXPR_ARG (exp, 1);
14038 rtx op0 = expand_normal (arg0);
14039 rtx op1 = expand_normal (arg1);
14040 machine_mode tmode = insn_data[icode].operand[0].mode;
14041 machine_mode mode0 = insn_data[icode].operand[1].mode;
14042 machine_mode mode1 = insn_data[icode].operand[2].mode;
14044 if (icode == CODE_FOR_nothing)
14045 /* Builtin not supported on this processor. */
14048 /* If we got invalid arguments bail out before generating bad rtl. */
14049 if (arg0 == error_mark_node || arg1 == error_mark_node)
14052 if (icode == CODE_FOR_altivec_vcfux
14053 || icode == CODE_FOR_altivec_vcfsx
14054 || icode == CODE_FOR_altivec_vctsxs
14055 || icode == CODE_FOR_altivec_vctuxs
14056 || icode == CODE_FOR_altivec_vspltb
14057 || icode == CODE_FOR_altivec_vsplth
14058 || icode == CODE_FOR_altivec_vspltw)
14060 /* Only allow 5-bit unsigned literals. */
14062 if (TREE_CODE (arg1) != INTEGER_CST
14063 || TREE_INT_CST_LOW (arg1) & ~0x1f)
14065 error ("argument 2 must be a 5-bit unsigned literal");
14066 return CONST0_RTX (tmode);
14069 else if (icode == CODE_FOR_dfptstsfi_eq_dd
14070 || icode == CODE_FOR_dfptstsfi_lt_dd
14071 || icode == CODE_FOR_dfptstsfi_gt_dd
14072 || icode == CODE_FOR_dfptstsfi_unordered_dd
14073 || icode == CODE_FOR_dfptstsfi_eq_td
14074 || icode == CODE_FOR_dfptstsfi_lt_td
14075 || icode == CODE_FOR_dfptstsfi_gt_td
14076 || icode == CODE_FOR_dfptstsfi_unordered_td)
14078 /* Only allow 6-bit unsigned literals. */
14080 if (TREE_CODE (arg0) != INTEGER_CST
14081 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
14083 error ("argument 1 must be a 6-bit unsigned literal");
14084 return CONST0_RTX (tmode);
14087 else if (icode == CODE_FOR_xststdcqp
14088 || icode == CODE_FOR_xststdcdp
14089 || icode == CODE_FOR_xststdcsp
14090 || icode == CODE_FOR_xvtstdcdp
14091 || icode == CODE_FOR_xvtstdcsp)
14093 /* Only allow 7-bit unsigned literals. */
14095 if (TREE_CODE (arg1) != INTEGER_CST
14096 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
14098 error ("argument 2 must be a 7-bit unsigned literal");
14099 return CONST0_RTX (tmode);
14102 else if (icode == CODE_FOR_unpackv1ti
14103 || icode == CODE_FOR_unpackkf
14104 || icode == CODE_FOR_unpacktf
14105 || icode == CODE_FOR_unpackif
14106 || icode == CODE_FOR_unpacktd)
14108 /* Only allow 1-bit unsigned literals. */
14110 if (TREE_CODE (arg1) != INTEGER_CST
14111 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
14113 error ("argument 2 must be a 1-bit unsigned literal");
14114 return CONST0_RTX (tmode);
14119 || GET_MODE (target) != tmode
14120 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14121 target = gen_reg_rtx (tmode);
14123 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14124 op0 = copy_to_mode_reg (mode0, op0);
14125 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14126 op1 = copy_to_mode_reg (mode1, op1);
14128 pat = GEN_FCN (icode) (target, op0, op1);
14137 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
14140 tree cr6_form = CALL_EXPR_ARG (exp, 0);
14141 tree arg0 = CALL_EXPR_ARG (exp, 1);
14142 tree arg1 = CALL_EXPR_ARG (exp, 2);
14143 rtx op0 = expand_normal (arg0);
14144 rtx op1 = expand_normal (arg1);
14145 machine_mode tmode = SImode;
14146 machine_mode mode0 = insn_data[icode].operand[1].mode;
14147 machine_mode mode1 = insn_data[icode].operand[2].mode;
14150 if (TREE_CODE (cr6_form) != INTEGER_CST)
14152 error ("argument 1 of %qs must be a constant",
14153 "__builtin_altivec_predicate");
14157 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
14159 gcc_assert (mode0 == mode1);
14161 /* If we have invalid arguments, bail out before generating bad rtl. */
14162 if (arg0 == error_mark_node || arg1 == error_mark_node)
14166 || GET_MODE (target) != tmode
14167 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14168 target = gen_reg_rtx (tmode);
14170 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14171 op0 = copy_to_mode_reg (mode0, op0);
14172 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14173 op1 = copy_to_mode_reg (mode1, op1);
14175 /* Note that for many of the relevant operations (e.g. cmpne or
14176 cmpeq) with float or double operands, it makes more sense for the
14177 mode of the allocated scratch register to select a vector of
14178 integer. But the choice to copy the mode of operand 0 was made
14179 long ago and there are no plans to change it. */
14180 scratch = gen_reg_rtx (mode0);
14182 pat = GEN_FCN (icode) (scratch, op0, op1);
14187 /* The vec_any* and vec_all* predicates use the same opcodes for two
14188 different operations, but the bits in CR6 will be different
14189 depending on what information we want. So we have to play tricks
14190 with CR6 to get the right bits out.
14192 If you think this is disgusting, look at the specs for the
14193 AltiVec predicates. */
14195 switch (cr6_form_int)
14198 emit_insn (gen_cr6_test_for_zero (target));
14201 emit_insn (gen_cr6_test_for_zero_reverse (target));
14204 emit_insn (gen_cr6_test_for_lt (target));
14207 emit_insn (gen_cr6_test_for_lt_reverse (target));
14210 error ("argument 1 of %qs is out of range",
14211 "__builtin_altivec_predicate");
14219 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
14222 tree arg0 = CALL_EXPR_ARG (exp, 0);
14223 tree arg1 = CALL_EXPR_ARG (exp, 1);
14224 machine_mode tmode = insn_data[icode].operand[0].mode;
14225 machine_mode mode0 = Pmode;
14226 machine_mode mode1 = Pmode;
14227 rtx op0 = expand_normal (arg0);
14228 rtx op1 = expand_normal (arg1);
14230 if (icode == CODE_FOR_nothing)
14231 /* Builtin not supported on this processor. */
14234 /* If we got invalid arguments bail out before generating bad rtl. */
14235 if (arg0 == error_mark_node || arg1 == error_mark_node)
14239 || GET_MODE (target) != tmode
14240 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14241 target = gen_reg_rtx (tmode);
14243 op1 = copy_to_mode_reg (mode1, op1);
14245 if (op0 == const0_rtx)
14247 addr = gen_rtx_MEM (tmode, op1);
14251 op0 = copy_to_mode_reg (mode0, op0);
14252 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
14255 pat = GEN_FCN (icode) (target, addr);
14264 /* Return a constant vector for use as a little-endian permute control vector
14265 to reverse the order of elements of the given vector mode. */
14267 swap_selector_for_mode (machine_mode mode)
14269 /* These are little endian vectors, so their elements are reversed
14270 from what you would normally expect for a permute control vector. */
14271 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14272 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14273 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14274 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14275 unsigned int *swaparray, i;
14292 swaparray = swap16;
14295 gcc_unreachable ();
14298 for (i = 0; i < 16; ++i)
14299 perm[i] = GEN_INT (swaparray[i]);
14301 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
14305 swap_endian_selector_for_mode (machine_mode mode)
14307 unsigned int le_swap1[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14308 unsigned int le_swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14309 unsigned int le_swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14310 unsigned int le_swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14311 unsigned int le_swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14313 unsigned int be_swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14314 unsigned int be_swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14315 unsigned int be_swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14316 unsigned int be_swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14317 unsigned int be_swap16[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14318 unsigned int *swaparray, i;
14321 if (VECTOR_ELT_ORDER_BIG)
14325 swaparray = le_swap1;
14329 swaparray = le_swap2;
14333 swaparray = le_swap4;
14336 swaparray = le_swap8;
14339 swaparray = le_swap16;
14342 gcc_unreachable ();
14348 swaparray = be_swap1;
14352 swaparray = be_swap2;
14356 swaparray = be_swap4;
14359 swaparray = be_swap8;
14362 swaparray = be_swap16;
14365 gcc_unreachable ();
14368 for (i = 0; i < 16; ++i)
14369 perm[i] = GEN_INT (swaparray[i]);
14371 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
14372 gen_rtvec_v (16, perm)));
14375 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14376 with -maltivec=be specified. Issue the load followed by an element-
14377 reversing permute. */
14379 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14381 rtx tmp = gen_reg_rtx (mode);
14382 rtx load = gen_rtx_SET (tmp, op1);
14383 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14384 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
14385 rtx sel = swap_selector_for_mode (mode);
14386 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
14388 gcc_assert (REG_P (op0));
14390 emit_insn (gen_rtx_SET (op0, vperm));
14393 /* Generate code for a "stvxl" built-in for a little endian target with
14394 -maltivec=be specified. Issue the store preceded by an element-reversing
14397 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14399 rtx tmp = gen_reg_rtx (mode);
14400 rtx store = gen_rtx_SET (op0, tmp);
14401 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14402 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
14403 rtx sel = swap_selector_for_mode (mode);
14406 gcc_assert (REG_P (op1));
14407 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14408 emit_insn (gen_rtx_SET (tmp, vperm));
14412 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14413 specified. Issue the store preceded by an element-reversing permute. */
14415 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14417 machine_mode inner_mode = GET_MODE_INNER (mode);
14418 rtx tmp = gen_reg_rtx (mode);
14419 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
14420 rtx sel = swap_selector_for_mode (mode);
14423 gcc_assert (REG_P (op1));
14424 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14425 emit_insn (gen_rtx_SET (tmp, vperm));
14426 emit_insn (gen_rtx_SET (op0, stvx));
14430 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14433 tree arg0 = CALL_EXPR_ARG (exp, 0);
14434 tree arg1 = CALL_EXPR_ARG (exp, 1);
14435 machine_mode tmode = insn_data[icode].operand[0].mode;
14436 machine_mode mode0 = Pmode;
14437 machine_mode mode1 = Pmode;
14438 rtx op0 = expand_normal (arg0);
14439 rtx op1 = expand_normal (arg1);
14441 if (icode == CODE_FOR_nothing)
14442 /* Builtin not supported on this processor. */
14445 /* If we got invalid arguments bail out before generating bad rtl. */
14446 if (arg0 == error_mark_node || arg1 == error_mark_node)
14450 || GET_MODE (target) != tmode
14451 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14452 target = gen_reg_rtx (tmode);
14454 op1 = copy_to_mode_reg (mode1, op1);
14456 /* For LVX, express the RTL accurately by ANDing the address with -16.
14457 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14458 so the raw address is fine. */
14459 if (icode == CODE_FOR_altivec_lvx_v2df_2op
14460 || icode == CODE_FOR_altivec_lvx_v2di_2op
14461 || icode == CODE_FOR_altivec_lvx_v4sf_2op
14462 || icode == CODE_FOR_altivec_lvx_v4si_2op
14463 || icode == CODE_FOR_altivec_lvx_v8hi_2op
14464 || icode == CODE_FOR_altivec_lvx_v16qi_2op)
14467 if (op0 == const0_rtx)
14471 op0 = copy_to_mode_reg (mode0, op0);
14472 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14474 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14475 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14477 /* For -maltivec=be, emit the load and follow it up with a
14478 permute to swap the elements. */
14479 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14481 rtx temp = gen_reg_rtx (tmode);
14482 emit_insn (gen_rtx_SET (temp, addr));
14484 rtx sel = swap_selector_for_mode (tmode);
14485 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
14487 emit_insn (gen_rtx_SET (target, vperm));
14490 emit_insn (gen_rtx_SET (target, addr));
14494 if (op0 == const0_rtx)
14495 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14498 op0 = copy_to_mode_reg (mode0, op0);
14499 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14500 gen_rtx_PLUS (Pmode, op1, op0));
14503 pat = GEN_FCN (icode) (target, addr);
14513 altivec_expand_xl_be_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14516 tree arg0 = CALL_EXPR_ARG (exp, 0);
14517 tree arg1 = CALL_EXPR_ARG (exp, 1);
14518 machine_mode tmode = insn_data[icode].operand[0].mode;
14519 machine_mode mode0 = Pmode;
14520 machine_mode mode1 = Pmode;
14521 rtx op0 = expand_normal (arg0);
14522 rtx op1 = expand_normal (arg1);
14524 if (icode == CODE_FOR_nothing)
14525 /* Builtin not supported on this processor. */
14528 /* If we got invalid arguments bail out before generating bad rtl. */
14529 if (arg0 == error_mark_node || arg1 == error_mark_node)
14533 || GET_MODE (target) != tmode
14534 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14535 target = gen_reg_rtx (tmode);
14537 op1 = copy_to_mode_reg (mode1, op1);
14539 if (op0 == const0_rtx)
14540 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14543 op0 = copy_to_mode_reg (mode0, op0);
14544 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14545 gen_rtx_PLUS (Pmode, op1, op0));
14548 pat = GEN_FCN (icode) (target, addr);
14553 /* Reverse element order of elements if in LE mode */
14554 if (!VECTOR_ELT_ORDER_BIG)
14556 rtx sel = swap_selector_for_mode (tmode);
14557 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, target, target, sel),
14559 emit_insn (gen_rtx_SET (target, vperm));
14565 paired_expand_stv_builtin (enum insn_code icode, tree exp)
14567 tree arg0 = CALL_EXPR_ARG (exp, 0);
14568 tree arg1 = CALL_EXPR_ARG (exp, 1);
14569 tree arg2 = CALL_EXPR_ARG (exp, 2);
14570 rtx op0 = expand_normal (arg0);
14571 rtx op1 = expand_normal (arg1);
14572 rtx op2 = expand_normal (arg2);
14574 machine_mode tmode = insn_data[icode].operand[0].mode;
14575 machine_mode mode1 = Pmode;
14576 machine_mode mode2 = Pmode;
14578 /* Invalid arguments. Bail before doing anything stoopid! */
14579 if (arg0 == error_mark_node
14580 || arg1 == error_mark_node
14581 || arg2 == error_mark_node)
14584 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
14585 op0 = copy_to_mode_reg (tmode, op0);
14587 op2 = copy_to_mode_reg (mode2, op2);
14589 if (op1 == const0_rtx)
14591 addr = gen_rtx_MEM (tmode, op2);
14595 op1 = copy_to_mode_reg (mode1, op1);
14596 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
14599 pat = GEN_FCN (icode) (addr, op0);
14606 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14609 tree arg0 = CALL_EXPR_ARG (exp, 0);
14610 tree arg1 = CALL_EXPR_ARG (exp, 1);
14611 tree arg2 = CALL_EXPR_ARG (exp, 2);
14612 rtx op0 = expand_normal (arg0);
14613 rtx op1 = expand_normal (arg1);
14614 rtx op2 = expand_normal (arg2);
14615 machine_mode mode0 = insn_data[icode].operand[0].mode;
14616 machine_mode mode1 = insn_data[icode].operand[1].mode;
14617 machine_mode mode2 = insn_data[icode].operand[2].mode;
14619 if (icode == CODE_FOR_nothing)
14620 /* Builtin not supported on this processor. */
14623 /* If we got invalid arguments bail out before generating bad rtl. */
14624 if (arg0 == error_mark_node
14625 || arg1 == error_mark_node
14626 || arg2 == error_mark_node)
14629 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14630 op0 = copy_to_mode_reg (mode0, op0);
14631 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14632 op1 = copy_to_mode_reg (mode1, op1);
14633 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14634 op2 = copy_to_mode_reg (mode2, op2);
14636 pat = GEN_FCN (icode) (op0, op1, op2);
14644 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14646 tree arg0 = CALL_EXPR_ARG (exp, 0);
14647 tree arg1 = CALL_EXPR_ARG (exp, 1);
14648 tree arg2 = CALL_EXPR_ARG (exp, 2);
14649 rtx op0 = expand_normal (arg0);
14650 rtx op1 = expand_normal (arg1);
14651 rtx op2 = expand_normal (arg2);
14652 rtx pat, addr, rawaddr;
14653 machine_mode tmode = insn_data[icode].operand[0].mode;
14654 machine_mode smode = insn_data[icode].operand[1].mode;
14655 machine_mode mode1 = Pmode;
14656 machine_mode mode2 = Pmode;
14658 /* Invalid arguments. Bail before doing anything stoopid! */
14659 if (arg0 == error_mark_node
14660 || arg1 == error_mark_node
14661 || arg2 == error_mark_node)
14664 op2 = copy_to_mode_reg (mode2, op2);
14666 /* For STVX, express the RTL accurately by ANDing the address with -16.
14667 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14668 so the raw address is fine. */
14669 if (icode == CODE_FOR_altivec_stvx_v2df_2op
14670 || icode == CODE_FOR_altivec_stvx_v2di_2op
14671 || icode == CODE_FOR_altivec_stvx_v4sf_2op
14672 || icode == CODE_FOR_altivec_stvx_v4si_2op
14673 || icode == CODE_FOR_altivec_stvx_v8hi_2op
14674 || icode == CODE_FOR_altivec_stvx_v16qi_2op)
14676 if (op1 == const0_rtx)
14680 op1 = copy_to_mode_reg (mode1, op1);
14681 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14684 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14685 addr = gen_rtx_MEM (tmode, addr);
14687 op0 = copy_to_mode_reg (tmode, op0);
14689 /* For -maltivec=be, emit a permute to swap the elements, followed
14691 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14693 rtx temp = gen_reg_rtx (tmode);
14694 rtx sel = swap_selector_for_mode (tmode);
14695 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
14697 emit_insn (gen_rtx_SET (temp, vperm));
14698 emit_insn (gen_rtx_SET (addr, temp));
14701 emit_insn (gen_rtx_SET (addr, op0));
14705 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14706 op0 = copy_to_mode_reg (smode, op0);
14708 if (op1 == const0_rtx)
14709 addr = gen_rtx_MEM (tmode, op2);
14712 op1 = copy_to_mode_reg (mode1, op1);
14713 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14716 pat = GEN_FCN (icode) (addr, op0);
14724 /* Return the appropriate SPR number associated with the given builtin. */
14725 static inline HOST_WIDE_INT
14726 htm_spr_num (enum rs6000_builtins code)
14728 if (code == HTM_BUILTIN_GET_TFHAR
14729 || code == HTM_BUILTIN_SET_TFHAR)
14731 else if (code == HTM_BUILTIN_GET_TFIAR
14732 || code == HTM_BUILTIN_SET_TFIAR)
14734 else if (code == HTM_BUILTIN_GET_TEXASR
14735 || code == HTM_BUILTIN_SET_TEXASR)
14737 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14738 || code == HTM_BUILTIN_SET_TEXASRU);
14739 return TEXASRU_SPR;
14742 /* Return the appropriate SPR regno associated with the given builtin. */
14743 static inline HOST_WIDE_INT
14744 htm_spr_regno (enum rs6000_builtins code)
14746 if (code == HTM_BUILTIN_GET_TFHAR
14747 || code == HTM_BUILTIN_SET_TFHAR)
14748 return TFHAR_REGNO;
14749 else if (code == HTM_BUILTIN_GET_TFIAR
14750 || code == HTM_BUILTIN_SET_TFIAR)
14751 return TFIAR_REGNO;
14752 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14753 || code == HTM_BUILTIN_SET_TEXASR
14754 || code == HTM_BUILTIN_GET_TEXASRU
14755 || code == HTM_BUILTIN_SET_TEXASRU);
14756 return TEXASR_REGNO;
14759 /* Return the correct ICODE value depending on whether we are
14760 setting or reading the HTM SPRs. */
14761 static inline enum insn_code
14762 rs6000_htm_spr_icode (bool nonvoid)
14765 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14767 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14770 /* Expand the HTM builtin in EXP and store the result in TARGET.
14771 Store true in *EXPANDEDP if we found a builtin to expand. */
14773 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14775 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14776 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14777 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14778 const struct builtin_description *d;
14783 if (!TARGET_POWERPC64
14784 && (fcode == HTM_BUILTIN_TABORTDC
14785 || fcode == HTM_BUILTIN_TABORTDCI))
14787 size_t uns_fcode = (size_t)fcode;
14788 const char *name = rs6000_builtin_info[uns_fcode].name;
14789 error ("builtin %qs is only valid in 64-bit mode", name);
14793 /* Expand the HTM builtins. */
14795 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14796 if (d->code == fcode)
14798 rtx op[MAX_HTM_OPERANDS], pat;
14801 call_expr_arg_iterator iter;
14802 unsigned attr = rs6000_builtin_info[fcode].attr;
14803 enum insn_code icode = d->icode;
14804 const struct insn_operand_data *insn_op;
14805 bool uses_spr = (attr & RS6000_BTC_SPR);
14809 icode = rs6000_htm_spr_icode (nonvoid);
14810 insn_op = &insn_data[icode].operand[0];
14814 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14816 || GET_MODE (target) != tmode
14817 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14818 target = gen_reg_rtx (tmode);
14820 op[nopnds++] = target;
14823 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14825 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14828 insn_op = &insn_data[icode].operand[nopnds];
14830 op[nopnds] = expand_normal (arg);
14832 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14834 if (!strcmp (insn_op->constraint, "n"))
14836 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14837 if (!CONST_INT_P (op[nopnds]))
14838 error ("argument %d must be an unsigned literal", arg_num);
14840 error ("argument %d is an unsigned literal that is "
14841 "out of range", arg_num);
14844 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14850 /* Handle the builtins for extended mnemonics. These accept
14851 no arguments, but map to builtins that take arguments. */
14854 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14855 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14856 op[nopnds++] = GEN_INT (1);
14858 attr |= RS6000_BTC_UNARY;
14860 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14861 op[nopnds++] = GEN_INT (0);
14863 attr |= RS6000_BTC_UNARY;
14869 /* If this builtin accesses SPRs, then pass in the appropriate
14870 SPR number and SPR regno as the last two operands. */
14873 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14874 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14875 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14877 /* If this builtin accesses a CR, then pass in a scratch
14878 CR as the last operand. */
14879 else if (attr & RS6000_BTC_CR)
14880 { cr = gen_reg_rtx (CCmode);
14886 int expected_nopnds = 0;
14887 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14888 expected_nopnds = 1;
14889 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14890 expected_nopnds = 2;
14891 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14892 expected_nopnds = 3;
14893 if (!(attr & RS6000_BTC_VOID))
14894 expected_nopnds += 1;
14896 expected_nopnds += 2;
14898 gcc_assert (nopnds == expected_nopnds
14899 && nopnds <= MAX_HTM_OPERANDS);
14905 pat = GEN_FCN (icode) (op[0]);
14908 pat = GEN_FCN (icode) (op[0], op[1]);
14911 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14914 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14917 gcc_unreachable ();
14923 if (attr & RS6000_BTC_CR)
14925 if (fcode == HTM_BUILTIN_TBEGIN)
14927 /* Emit code to set TARGET to true or false depending on
14928 whether the tbegin. instruction successfully or failed
14929 to start a transaction. We do this by placing the 1's
14930 complement of CR's EQ bit into TARGET. */
14931 rtx scratch = gen_reg_rtx (SImode);
14932 emit_insn (gen_rtx_SET (scratch,
14933 gen_rtx_EQ (SImode, cr,
14935 emit_insn (gen_rtx_SET (target,
14936 gen_rtx_XOR (SImode, scratch,
14941 /* Emit code to copy the 4-bit condition register field
14942 CR into the least significant end of register TARGET. */
14943 rtx scratch1 = gen_reg_rtx (SImode);
14944 rtx scratch2 = gen_reg_rtx (SImode);
14945 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14946 emit_insn (gen_movcc (subreg, cr));
14947 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14948 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14957 *expandedp = false;
14961 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14964 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14967 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14968 if (fcode == RS6000_BUILTIN_CPU_INIT)
14971 if (target == 0 || GET_MODE (target) != SImode)
14972 target = gen_reg_rtx (SImode);
14974 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14975 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14976 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14977 to a STRING_CST. */
14978 if (TREE_CODE (arg) == ARRAY_REF
14979 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14980 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14981 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14982 arg = TREE_OPERAND (arg, 0);
14984 if (TREE_CODE (arg) != STRING_CST)
14986 error ("builtin %qs only accepts a string argument",
14987 rs6000_builtin_info[(size_t) fcode].name);
14991 if (fcode == RS6000_BUILTIN_CPU_IS)
14993 const char *cpu = TREE_STRING_POINTER (arg);
14994 rtx cpuid = NULL_RTX;
14995 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14996 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14998 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14999 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
15002 if (cpuid == NULL_RTX)
15004 /* Invalid CPU argument. */
15005 error ("cpu %qs is an invalid argument to builtin %qs",
15006 cpu, rs6000_builtin_info[(size_t) fcode].name);
15010 rtx platform = gen_reg_rtx (SImode);
15011 rtx tcbmem = gen_const_mem (SImode,
15012 gen_rtx_PLUS (Pmode,
15013 gen_rtx_REG (Pmode, TLS_REGNUM),
15014 GEN_INT (TCB_PLATFORM_OFFSET)));
15015 emit_move_insn (platform, tcbmem);
15016 emit_insn (gen_eqsi3 (target, platform, cpuid));
15018 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
15020 const char *hwcap = TREE_STRING_POINTER (arg);
15021 rtx mask = NULL_RTX;
15023 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
15024 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
15026 mask = GEN_INT (cpu_supports_info[i].mask);
15027 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
15030 if (mask == NULL_RTX)
15032 /* Invalid HWCAP argument. */
15033 error ("%s %qs is an invalid argument to builtin %qs",
15034 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
15038 rtx tcb_hwcap = gen_reg_rtx (SImode);
15039 rtx tcbmem = gen_const_mem (SImode,
15040 gen_rtx_PLUS (Pmode,
15041 gen_rtx_REG (Pmode, TLS_REGNUM),
15042 GEN_INT (hwcap_offset)));
15043 emit_move_insn (tcb_hwcap, tcbmem);
15044 rtx scratch1 = gen_reg_rtx (SImode);
15045 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
15046 rtx scratch2 = gen_reg_rtx (SImode);
15047 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
15048 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
15051 gcc_unreachable ();
15053 /* Record that we have expanded a CPU builtin, so that we can later
15054 emit a reference to the special symbol exported by LIBC to ensure we
15055 do not link against an old LIBC that doesn't support this feature. */
15056 cpu_builtin_p = true;
15059 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
15060 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
15062 /* For old LIBCs, always return FALSE. */
15063 emit_move_insn (target, GEN_INT (0));
15064 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
15070 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
15073 tree arg0 = CALL_EXPR_ARG (exp, 0);
15074 tree arg1 = CALL_EXPR_ARG (exp, 1);
15075 tree arg2 = CALL_EXPR_ARG (exp, 2);
15076 rtx op0 = expand_normal (arg0);
15077 rtx op1 = expand_normal (arg1);
15078 rtx op2 = expand_normal (arg2);
15079 machine_mode tmode = insn_data[icode].operand[0].mode;
15080 machine_mode mode0 = insn_data[icode].operand[1].mode;
15081 machine_mode mode1 = insn_data[icode].operand[2].mode;
15082 machine_mode mode2 = insn_data[icode].operand[3].mode;
15084 if (icode == CODE_FOR_nothing)
15085 /* Builtin not supported on this processor. */
15088 /* If we got invalid arguments bail out before generating bad rtl. */
15089 if (arg0 == error_mark_node
15090 || arg1 == error_mark_node
15091 || arg2 == error_mark_node)
15094 /* Check and prepare argument depending on the instruction code.
15096 Note that a switch statement instead of the sequence of tests
15097 would be incorrect as many of the CODE_FOR values could be
15098 CODE_FOR_nothing and that would yield multiple alternatives
15099 with identical values. We'd never reach here at runtime in
15101 if (icode == CODE_FOR_altivec_vsldoi_v4sf
15102 || icode == CODE_FOR_altivec_vsldoi_v2df
15103 || icode == CODE_FOR_altivec_vsldoi_v4si
15104 || icode == CODE_FOR_altivec_vsldoi_v8hi
15105 || icode == CODE_FOR_altivec_vsldoi_v16qi)
15107 /* Only allow 4-bit unsigned literals. */
15109 if (TREE_CODE (arg2) != INTEGER_CST
15110 || TREE_INT_CST_LOW (arg2) & ~0xf)
15112 error ("argument 3 must be a 4-bit unsigned literal");
15113 return CONST0_RTX (tmode);
15116 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
15117 || icode == CODE_FOR_vsx_xxpermdi_v2di
15118 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
15119 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
15120 || icode == CODE_FOR_vsx_xxpermdi_v1ti
15121 || icode == CODE_FOR_vsx_xxpermdi_v4sf
15122 || icode == CODE_FOR_vsx_xxpermdi_v4si
15123 || icode == CODE_FOR_vsx_xxpermdi_v8hi
15124 || icode == CODE_FOR_vsx_xxpermdi_v16qi
15125 || icode == CODE_FOR_vsx_xxsldwi_v16qi
15126 || icode == CODE_FOR_vsx_xxsldwi_v8hi
15127 || icode == CODE_FOR_vsx_xxsldwi_v4si
15128 || icode == CODE_FOR_vsx_xxsldwi_v4sf
15129 || icode == CODE_FOR_vsx_xxsldwi_v2di
15130 || icode == CODE_FOR_vsx_xxsldwi_v2df)
15132 /* Only allow 2-bit unsigned literals. */
15134 if (TREE_CODE (arg2) != INTEGER_CST
15135 || TREE_INT_CST_LOW (arg2) & ~0x3)
15137 error ("argument 3 must be a 2-bit unsigned literal");
15138 return CONST0_RTX (tmode);
15141 else if (icode == CODE_FOR_vsx_set_v2df
15142 || icode == CODE_FOR_vsx_set_v2di
15143 || icode == CODE_FOR_bcdadd
15144 || icode == CODE_FOR_bcdadd_lt
15145 || icode == CODE_FOR_bcdadd_eq
15146 || icode == CODE_FOR_bcdadd_gt
15147 || icode == CODE_FOR_bcdsub
15148 || icode == CODE_FOR_bcdsub_lt
15149 || icode == CODE_FOR_bcdsub_eq
15150 || icode == CODE_FOR_bcdsub_gt)
15152 /* Only allow 1-bit unsigned literals. */
15154 if (TREE_CODE (arg2) != INTEGER_CST
15155 || TREE_INT_CST_LOW (arg2) & ~0x1)
15157 error ("argument 3 must be a 1-bit unsigned literal");
15158 return CONST0_RTX (tmode);
15161 else if (icode == CODE_FOR_dfp_ddedpd_dd
15162 || icode == CODE_FOR_dfp_ddedpd_td)
15164 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15166 if (TREE_CODE (arg0) != INTEGER_CST
15167 || TREE_INT_CST_LOW (arg2) & ~0x3)
15169 error ("argument 1 must be 0 or 2");
15170 return CONST0_RTX (tmode);
15173 else if (icode == CODE_FOR_dfp_denbcd_dd
15174 || icode == CODE_FOR_dfp_denbcd_td)
15176 /* Only allow 1-bit unsigned literals. */
15178 if (TREE_CODE (arg0) != INTEGER_CST
15179 || TREE_INT_CST_LOW (arg0) & ~0x1)
15181 error ("argument 1 must be a 1-bit unsigned literal");
15182 return CONST0_RTX (tmode);
15185 else if (icode == CODE_FOR_dfp_dscli_dd
15186 || icode == CODE_FOR_dfp_dscli_td
15187 || icode == CODE_FOR_dfp_dscri_dd
15188 || icode == CODE_FOR_dfp_dscri_td)
15190 /* Only allow 6-bit unsigned literals. */
15192 if (TREE_CODE (arg1) != INTEGER_CST
15193 || TREE_INT_CST_LOW (arg1) & ~0x3f)
15195 error ("argument 2 must be a 6-bit unsigned literal");
15196 return CONST0_RTX (tmode);
15199 else if (icode == CODE_FOR_crypto_vshasigmaw
15200 || icode == CODE_FOR_crypto_vshasigmad)
15202 /* Check whether the 2nd and 3rd arguments are integer constants and in
15203 range and prepare arguments. */
15205 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
15207 error ("argument 2 must be 0 or 1");
15208 return CONST0_RTX (tmode);
15212 if (TREE_CODE (arg2) != INTEGER_CST
15213 || wi::geu_p (wi::to_wide (arg2), 16))
15215 error ("argument 3 must be in the range 0..15");
15216 return CONST0_RTX (tmode);
15221 || GET_MODE (target) != tmode
15222 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15223 target = gen_reg_rtx (tmode);
15225 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15226 op0 = copy_to_mode_reg (mode0, op0);
15227 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15228 op1 = copy_to_mode_reg (mode1, op1);
15229 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15230 op2 = copy_to_mode_reg (mode2, op2);
15232 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
15233 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
15235 pat = GEN_FCN (icode) (target, op0, op1, op2);
15243 /* Expand the lvx builtins. */
15245 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
15247 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15248 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15250 machine_mode tmode, mode0;
15252 enum insn_code icode;
15256 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
15257 icode = CODE_FOR_vector_altivec_load_v16qi;
15259 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
15260 icode = CODE_FOR_vector_altivec_load_v8hi;
15262 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
15263 icode = CODE_FOR_vector_altivec_load_v4si;
15265 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
15266 icode = CODE_FOR_vector_altivec_load_v4sf;
15268 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
15269 icode = CODE_FOR_vector_altivec_load_v2df;
15271 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
15272 icode = CODE_FOR_vector_altivec_load_v2di;
15274 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
15275 icode = CODE_FOR_vector_altivec_load_v1ti;
15278 *expandedp = false;
15284 arg0 = CALL_EXPR_ARG (exp, 0);
15285 op0 = expand_normal (arg0);
15286 tmode = insn_data[icode].operand[0].mode;
15287 mode0 = insn_data[icode].operand[1].mode;
15290 || GET_MODE (target) != tmode
15291 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15292 target = gen_reg_rtx (tmode);
15294 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15295 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15297 pat = GEN_FCN (icode) (target, op0);
15304 /* Expand the stvx builtins. */
15306 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15309 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15310 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15312 machine_mode mode0, mode1;
15314 enum insn_code icode;
15318 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
15319 icode = CODE_FOR_vector_altivec_store_v16qi;
15321 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
15322 icode = CODE_FOR_vector_altivec_store_v8hi;
15324 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
15325 icode = CODE_FOR_vector_altivec_store_v4si;
15327 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
15328 icode = CODE_FOR_vector_altivec_store_v4sf;
15330 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
15331 icode = CODE_FOR_vector_altivec_store_v2df;
15333 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
15334 icode = CODE_FOR_vector_altivec_store_v2di;
15336 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
15337 icode = CODE_FOR_vector_altivec_store_v1ti;
15340 *expandedp = false;
15344 arg0 = CALL_EXPR_ARG (exp, 0);
15345 arg1 = CALL_EXPR_ARG (exp, 1);
15346 op0 = expand_normal (arg0);
15347 op1 = expand_normal (arg1);
15348 mode0 = insn_data[icode].operand[0].mode;
15349 mode1 = insn_data[icode].operand[1].mode;
15351 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15352 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15353 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15354 op1 = copy_to_mode_reg (mode1, op1);
15356 pat = GEN_FCN (icode) (op0, op1);
15364 /* Expand the dst builtins. */
15366 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15369 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15370 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15371 tree arg0, arg1, arg2;
15372 machine_mode mode0, mode1;
15373 rtx pat, op0, op1, op2;
15374 const struct builtin_description *d;
15377 *expandedp = false;
15379 /* Handle DST variants. */
15381 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
15382 if (d->code == fcode)
15384 arg0 = CALL_EXPR_ARG (exp, 0);
15385 arg1 = CALL_EXPR_ARG (exp, 1);
15386 arg2 = CALL_EXPR_ARG (exp, 2);
15387 op0 = expand_normal (arg0);
15388 op1 = expand_normal (arg1);
15389 op2 = expand_normal (arg2);
15390 mode0 = insn_data[d->icode].operand[0].mode;
15391 mode1 = insn_data[d->icode].operand[1].mode;
15393 /* Invalid arguments, bail out before generating bad rtl. */
15394 if (arg0 == error_mark_node
15395 || arg1 == error_mark_node
15396 || arg2 == error_mark_node)
15401 if (TREE_CODE (arg2) != INTEGER_CST
15402 || TREE_INT_CST_LOW (arg2) & ~0x3)
15404 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
15408 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15409 op0 = copy_to_mode_reg (Pmode, op0);
15410 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15411 op1 = copy_to_mode_reg (mode1, op1);
15413 pat = GEN_FCN (d->icode) (op0, op1, op2);
15423 /* Expand vec_init builtin. */
15425 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
15427 machine_mode tmode = TYPE_MODE (type);
15428 machine_mode inner_mode = GET_MODE_INNER (tmode);
15429 int i, n_elt = GET_MODE_NUNITS (tmode);
15431 gcc_assert (VECTOR_MODE_P (tmode));
15432 gcc_assert (n_elt == call_expr_nargs (exp));
15434 if (!target || !register_operand (target, tmode))
15435 target = gen_reg_rtx (tmode);
15437 /* If we have a vector compromised of a single element, such as V1TImode, do
15438 the initialization directly. */
15439 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
15441 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
15442 emit_move_insn (target, gen_lowpart (tmode, x));
15446 rtvec v = rtvec_alloc (n_elt);
15448 for (i = 0; i < n_elt; ++i)
15450 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
15451 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15454 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
15460 /* Return the integer constant in ARG. Constrain it to be in the range
15461 of the subparts of VEC_TYPE; issue an error if not. */
15464 get_element_number (tree vec_type, tree arg)
15466 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15468 if (!tree_fits_uhwi_p (arg)
15469 || (elt = tree_to_uhwi (arg), elt > max))
15471 error ("selector must be an integer constant in the range 0..%wi", max);
15478 /* Expand vec_set builtin. */
15480 altivec_expand_vec_set_builtin (tree exp)
15482 machine_mode tmode, mode1;
15483 tree arg0, arg1, arg2;
15487 arg0 = CALL_EXPR_ARG (exp, 0);
15488 arg1 = CALL_EXPR_ARG (exp, 1);
15489 arg2 = CALL_EXPR_ARG (exp, 2);
15491 tmode = TYPE_MODE (TREE_TYPE (arg0));
15492 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15493 gcc_assert (VECTOR_MODE_P (tmode));
15495 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
15496 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
15497 elt = get_element_number (TREE_TYPE (arg0), arg2);
15499 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15500 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15502 op0 = force_reg (tmode, op0);
15503 op1 = force_reg (mode1, op1);
15505 rs6000_expand_vector_set (op0, op1, elt);
15510 /* Expand vec_ext builtin. */
15512 altivec_expand_vec_ext_builtin (tree exp, rtx target)
15514 machine_mode tmode, mode0;
15519 arg0 = CALL_EXPR_ARG (exp, 0);
15520 arg1 = CALL_EXPR_ARG (exp, 1);
15522 op0 = expand_normal (arg0);
15523 op1 = expand_normal (arg1);
15525 /* Call get_element_number to validate arg1 if it is a constant. */
15526 if (TREE_CODE (arg1) == INTEGER_CST)
15527 (void) get_element_number (TREE_TYPE (arg0), arg1);
15529 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15530 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15531 gcc_assert (VECTOR_MODE_P (mode0));
15533 op0 = force_reg (mode0, op0);
15535 if (optimize || !target || !register_operand (target, tmode))
15536 target = gen_reg_rtx (tmode);
15538 rs6000_expand_vector_extract (target, op0, op1);
15543 /* Expand the builtin in EXP and store the result in TARGET. Store
15544 true in *EXPANDEDP if we found a builtin to expand. */
15546 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
15548 const struct builtin_description *d;
15550 enum insn_code icode;
15551 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15552 tree arg0, arg1, arg2;
15554 machine_mode tmode, mode0;
15555 enum rs6000_builtins fcode
15556 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15558 if (rs6000_overloaded_builtin_p (fcode))
15561 error ("unresolved overload for Altivec builtin %qF", fndecl);
15563 /* Given it is invalid, just generate a normal call. */
15564 return expand_call (exp, target, false);
15567 target = altivec_expand_ld_builtin (exp, target, expandedp);
15571 target = altivec_expand_st_builtin (exp, target, expandedp);
15575 target = altivec_expand_dst_builtin (exp, target, expandedp);
15583 case ALTIVEC_BUILTIN_STVX_V2DF:
15584 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
15585 case ALTIVEC_BUILTIN_STVX_V2DI:
15586 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
15587 case ALTIVEC_BUILTIN_STVX_V4SF:
15588 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
15589 case ALTIVEC_BUILTIN_STVX:
15590 case ALTIVEC_BUILTIN_STVX_V4SI:
15591 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
15592 case ALTIVEC_BUILTIN_STVX_V8HI:
15593 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
15594 case ALTIVEC_BUILTIN_STVX_V16QI:
15595 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
15596 case ALTIVEC_BUILTIN_STVEBX:
15597 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
15598 case ALTIVEC_BUILTIN_STVEHX:
15599 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
15600 case ALTIVEC_BUILTIN_STVEWX:
15601 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
15602 case ALTIVEC_BUILTIN_STVXL_V2DF:
15603 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
15604 case ALTIVEC_BUILTIN_STVXL_V2DI:
15605 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
15606 case ALTIVEC_BUILTIN_STVXL_V4SF:
15607 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
15608 case ALTIVEC_BUILTIN_STVXL:
15609 case ALTIVEC_BUILTIN_STVXL_V4SI:
15610 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
15611 case ALTIVEC_BUILTIN_STVXL_V8HI:
15612 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
15613 case ALTIVEC_BUILTIN_STVXL_V16QI:
15614 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
15616 case ALTIVEC_BUILTIN_STVLX:
15617 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
15618 case ALTIVEC_BUILTIN_STVLXL:
15619 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
15620 case ALTIVEC_BUILTIN_STVRX:
15621 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
15622 case ALTIVEC_BUILTIN_STVRXL:
15623 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
15625 case P9V_BUILTIN_STXVL:
15626 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
15628 case P9V_BUILTIN_XST_LEN_R:
15629 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
15631 case VSX_BUILTIN_STXVD2X_V1TI:
15632 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
15633 case VSX_BUILTIN_STXVD2X_V2DF:
15634 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
15635 case VSX_BUILTIN_STXVD2X_V2DI:
15636 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
15637 case VSX_BUILTIN_STXVW4X_V4SF:
15638 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
15639 case VSX_BUILTIN_STXVW4X_V4SI:
15640 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
15641 case VSX_BUILTIN_STXVW4X_V8HI:
15642 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
15643 case VSX_BUILTIN_STXVW4X_V16QI:
15644 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
15646 /* For the following on big endian, it's ok to use any appropriate
15647 unaligned-supporting store, so use a generic expander. For
15648 little-endian, the exact element-reversing instruction must
15650 case VSX_BUILTIN_ST_ELEMREV_V2DF:
15652 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
15653 : CODE_FOR_vsx_st_elemrev_v2df);
15654 return altivec_expand_stv_builtin (code, exp);
15656 case VSX_BUILTIN_ST_ELEMREV_V2DI:
15658 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
15659 : CODE_FOR_vsx_st_elemrev_v2di);
15660 return altivec_expand_stv_builtin (code, exp);
15662 case VSX_BUILTIN_ST_ELEMREV_V4SF:
15664 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
15665 : CODE_FOR_vsx_st_elemrev_v4sf);
15666 return altivec_expand_stv_builtin (code, exp);
15668 case VSX_BUILTIN_ST_ELEMREV_V4SI:
15670 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
15671 : CODE_FOR_vsx_st_elemrev_v4si);
15672 return altivec_expand_stv_builtin (code, exp);
15674 case VSX_BUILTIN_ST_ELEMREV_V8HI:
15676 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
15677 : CODE_FOR_vsx_st_elemrev_v8hi);
15678 return altivec_expand_stv_builtin (code, exp);
15680 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15682 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15683 : CODE_FOR_vsx_st_elemrev_v16qi);
15684 return altivec_expand_stv_builtin (code, exp);
15687 case ALTIVEC_BUILTIN_MFVSCR:
15688 icode = CODE_FOR_altivec_mfvscr;
15689 tmode = insn_data[icode].operand[0].mode;
15692 || GET_MODE (target) != tmode
15693 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15694 target = gen_reg_rtx (tmode);
15696 pat = GEN_FCN (icode) (target);
15702 case ALTIVEC_BUILTIN_MTVSCR:
15703 icode = CODE_FOR_altivec_mtvscr;
15704 arg0 = CALL_EXPR_ARG (exp, 0);
15705 op0 = expand_normal (arg0);
15706 mode0 = insn_data[icode].operand[0].mode;
15708 /* If we got invalid arguments bail out before generating bad rtl. */
15709 if (arg0 == error_mark_node)
15712 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15713 op0 = copy_to_mode_reg (mode0, op0);
15715 pat = GEN_FCN (icode) (op0);
15720 case ALTIVEC_BUILTIN_DSSALL:
15721 emit_insn (gen_altivec_dssall ());
15724 case ALTIVEC_BUILTIN_DSS:
15725 icode = CODE_FOR_altivec_dss;
15726 arg0 = CALL_EXPR_ARG (exp, 0);
15728 op0 = expand_normal (arg0);
15729 mode0 = insn_data[icode].operand[0].mode;
15731 /* If we got invalid arguments bail out before generating bad rtl. */
15732 if (arg0 == error_mark_node)
15735 if (TREE_CODE (arg0) != INTEGER_CST
15736 || TREE_INT_CST_LOW (arg0) & ~0x3)
15738 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15742 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15743 op0 = copy_to_mode_reg (mode0, op0);
15745 emit_insn (gen_altivec_dss (op0));
15748 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15749 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15750 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15751 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15752 case VSX_BUILTIN_VEC_INIT_V2DF:
15753 case VSX_BUILTIN_VEC_INIT_V2DI:
15754 case VSX_BUILTIN_VEC_INIT_V1TI:
15755 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15757 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15758 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15759 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15760 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15761 case VSX_BUILTIN_VEC_SET_V2DF:
15762 case VSX_BUILTIN_VEC_SET_V2DI:
15763 case VSX_BUILTIN_VEC_SET_V1TI:
15764 return altivec_expand_vec_set_builtin (exp);
15766 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15767 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15768 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15769 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15770 case VSX_BUILTIN_VEC_EXT_V2DF:
15771 case VSX_BUILTIN_VEC_EXT_V2DI:
15772 case VSX_BUILTIN_VEC_EXT_V1TI:
15773 return altivec_expand_vec_ext_builtin (exp, target);
15775 case P9V_BUILTIN_VEXTRACT4B:
15776 case P9V_BUILTIN_VEC_VEXTRACT4B:
15777 arg1 = CALL_EXPR_ARG (exp, 1);
15780 /* Generate a normal call if it is invalid. */
15781 if (arg1 == error_mark_node)
15782 return expand_call (exp, target, false);
15784 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15786 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15787 return expand_call (exp, target, false);
15791 case P9V_BUILTIN_VINSERT4B:
15792 case P9V_BUILTIN_VINSERT4B_DI:
15793 case P9V_BUILTIN_VEC_VINSERT4B:
15794 arg2 = CALL_EXPR_ARG (exp, 2);
15797 /* Generate a normal call if it is invalid. */
15798 if (arg2 == error_mark_node)
15799 return expand_call (exp, target, false);
15801 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15803 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15804 return expand_call (exp, target, false);
15810 /* Fall through. */
15813 /* Expand abs* operations. */
15815 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15816 if (d->code == fcode)
15817 return altivec_expand_abs_builtin (d->icode, exp, target);
15819 /* Expand the AltiVec predicates. */
15820 d = bdesc_altivec_preds;
15821 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15822 if (d->code == fcode)
15823 return altivec_expand_predicate_builtin (d->icode, exp, target);
15825 /* LV* are funky. We initialized them differently. */
15828 case ALTIVEC_BUILTIN_LVSL:
15829 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15830 exp, target, false);
15831 case ALTIVEC_BUILTIN_LVSR:
15832 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15833 exp, target, false);
15834 case ALTIVEC_BUILTIN_LVEBX:
15835 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15836 exp, target, false);
15837 case ALTIVEC_BUILTIN_LVEHX:
15838 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15839 exp, target, false);
15840 case ALTIVEC_BUILTIN_LVEWX:
15841 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15842 exp, target, false);
15843 case ALTIVEC_BUILTIN_LVXL_V2DF:
15844 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15845 exp, target, false);
15846 case ALTIVEC_BUILTIN_LVXL_V2DI:
15847 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15848 exp, target, false);
15849 case ALTIVEC_BUILTIN_LVXL_V4SF:
15850 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15851 exp, target, false);
15852 case ALTIVEC_BUILTIN_LVXL:
15853 case ALTIVEC_BUILTIN_LVXL_V4SI:
15854 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15855 exp, target, false);
15856 case ALTIVEC_BUILTIN_LVXL_V8HI:
15857 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15858 exp, target, false);
15859 case ALTIVEC_BUILTIN_LVXL_V16QI:
15860 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15861 exp, target, false);
15862 case ALTIVEC_BUILTIN_LVX_V2DF:
15863 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
15864 exp, target, false);
15865 case ALTIVEC_BUILTIN_LVX_V2DI:
15866 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
15867 exp, target, false);
15868 case ALTIVEC_BUILTIN_LVX_V4SF:
15869 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
15870 exp, target, false);
15871 case ALTIVEC_BUILTIN_LVX:
15872 case ALTIVEC_BUILTIN_LVX_V4SI:
15873 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
15874 exp, target, false);
15875 case ALTIVEC_BUILTIN_LVX_V8HI:
15876 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
15877 exp, target, false);
15878 case ALTIVEC_BUILTIN_LVX_V16QI:
15879 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
15880 exp, target, false);
15881 case ALTIVEC_BUILTIN_LVLX:
15882 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15883 exp, target, true);
15884 case ALTIVEC_BUILTIN_LVLXL:
15885 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15886 exp, target, true);
15887 case ALTIVEC_BUILTIN_LVRX:
15888 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15889 exp, target, true);
15890 case ALTIVEC_BUILTIN_LVRXL:
15891 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15892 exp, target, true);
15893 case VSX_BUILTIN_LXVD2X_V1TI:
15894 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15895 exp, target, false);
15896 case VSX_BUILTIN_LXVD2X_V2DF:
15897 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15898 exp, target, false);
15899 case VSX_BUILTIN_LXVD2X_V2DI:
15900 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15901 exp, target, false);
15902 case VSX_BUILTIN_LXVW4X_V4SF:
15903 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15904 exp, target, false);
15905 case VSX_BUILTIN_LXVW4X_V4SI:
15906 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15907 exp, target, false);
15908 case VSX_BUILTIN_LXVW4X_V8HI:
15909 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15910 exp, target, false);
15911 case VSX_BUILTIN_LXVW4X_V16QI:
15912 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15913 exp, target, false);
15914 /* For the following on big endian, it's ok to use any appropriate
15915 unaligned-supporting load, so use a generic expander. For
15916 little-endian, the exact element-reversing instruction must
15918 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15920 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15921 : CODE_FOR_vsx_ld_elemrev_v2df);
15922 return altivec_expand_lv_builtin (code, exp, target, false);
15924 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15926 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15927 : CODE_FOR_vsx_ld_elemrev_v2di);
15928 return altivec_expand_lv_builtin (code, exp, target, false);
15930 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15932 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15933 : CODE_FOR_vsx_ld_elemrev_v4sf);
15934 return altivec_expand_lv_builtin (code, exp, target, false);
15936 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15938 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15939 : CODE_FOR_vsx_ld_elemrev_v4si);
15940 return altivec_expand_lv_builtin (code, exp, target, false);
15942 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15944 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15945 : CODE_FOR_vsx_ld_elemrev_v8hi);
15946 return altivec_expand_lv_builtin (code, exp, target, false);
15948 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15950 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15951 : CODE_FOR_vsx_ld_elemrev_v16qi);
15952 return altivec_expand_lv_builtin (code, exp, target, false);
15957 /* Fall through. */
15960 /* XL_BE We initialized them to always load in big endian order. */
15963 case VSX_BUILTIN_XL_BE_V2DI:
15965 enum insn_code code = CODE_FOR_vsx_load_v2di;
15966 return altivec_expand_xl_be_builtin (code, exp, target, false);
15969 case VSX_BUILTIN_XL_BE_V4SI:
15971 enum insn_code code = CODE_FOR_vsx_load_v4si;
15972 return altivec_expand_xl_be_builtin (code, exp, target, false);
15975 case VSX_BUILTIN_XL_BE_V8HI:
15977 enum insn_code code = CODE_FOR_vsx_load_v8hi;
15978 return altivec_expand_xl_be_builtin (code, exp, target, false);
15981 case VSX_BUILTIN_XL_BE_V16QI:
15983 enum insn_code code = CODE_FOR_vsx_load_v16qi;
15984 return altivec_expand_xl_be_builtin (code, exp, target, false);
15987 case VSX_BUILTIN_XL_BE_V2DF:
15989 enum insn_code code = CODE_FOR_vsx_load_v2df;
15990 return altivec_expand_xl_be_builtin (code, exp, target, false);
15993 case VSX_BUILTIN_XL_BE_V4SF:
15995 enum insn_code code = CODE_FOR_vsx_load_v4sf;
15996 return altivec_expand_xl_be_builtin (code, exp, target, false);
16001 /* Fall through. */
16004 *expandedp = false;
16008 /* Expand the builtin in EXP and store the result in TARGET. Store
16009 true in *EXPANDEDP if we found a builtin to expand. */
16011 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
16013 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16014 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16015 const struct builtin_description *d;
16022 case PAIRED_BUILTIN_STX:
16023 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
16024 case PAIRED_BUILTIN_LX:
16025 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
16028 /* Fall through. */
16031 /* Expand the paired predicates. */
16032 d = bdesc_paired_preds;
16033 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
16034 if (d->code == fcode)
16035 return paired_expand_predicate_builtin (d->icode, exp, target);
16037 *expandedp = false;
16042 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
16044 rtx pat, scratch, tmp;
16045 tree form = CALL_EXPR_ARG (exp, 0);
16046 tree arg0 = CALL_EXPR_ARG (exp, 1);
16047 tree arg1 = CALL_EXPR_ARG (exp, 2);
16048 rtx op0 = expand_normal (arg0);
16049 rtx op1 = expand_normal (arg1);
16050 machine_mode mode0 = insn_data[icode].operand[1].mode;
16051 machine_mode mode1 = insn_data[icode].operand[2].mode;
16053 enum rtx_code code;
16055 if (TREE_CODE (form) != INTEGER_CST)
16057 error ("argument 1 of %s must be a constant",
16058 "__builtin_paired_predicate");
16062 form_int = TREE_INT_CST_LOW (form);
16064 gcc_assert (mode0 == mode1);
16066 if (arg0 == error_mark_node || arg1 == error_mark_node)
16070 || GET_MODE (target) != SImode
16071 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
16072 target = gen_reg_rtx (SImode);
16073 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
16074 op0 = copy_to_mode_reg (mode0, op0);
16075 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
16076 op1 = copy_to_mode_reg (mode1, op1);
16078 scratch = gen_reg_rtx (CCFPmode);
16080 pat = GEN_FCN (icode) (scratch, op0, op1);
16102 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
16105 error ("argument 1 of %qs is out of range",
16106 "__builtin_paired_predicate");
16110 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
16111 emit_move_insn (target, tmp);
16115 /* Raise an error message for a builtin function that is called without the
16116 appropriate target options being set. */
16119 rs6000_invalid_builtin (enum rs6000_builtins fncode)
16121 size_t uns_fncode = (size_t) fncode;
16122 const char *name = rs6000_builtin_info[uns_fncode].name;
16123 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
16125 gcc_assert (name != NULL);
16126 if ((fnmask & RS6000_BTM_CELL) != 0)
16127 error ("builtin function %qs is only valid for the cell processor", name);
16128 else if ((fnmask & RS6000_BTM_VSX) != 0)
16129 error ("builtin function %qs requires the %qs option", name, "-mvsx");
16130 else if ((fnmask & RS6000_BTM_HTM) != 0)
16131 error ("builtin function %qs requires the %qs option", name, "-mhtm");
16132 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
16133 error ("builtin function %qs requires the %qs option", name, "-maltivec");
16134 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
16135 error ("builtin function %qs requires the %qs option", name, "-mpaired");
16136 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16137 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16138 error ("builtin function %qs requires the %qs and %qs options",
16139 name, "-mhard-dfp", "-mpower8-vector");
16140 else if ((fnmask & RS6000_BTM_DFP) != 0)
16141 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
16142 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
16143 error ("builtin function %qs requires the %qs option", name,
16144 "-mpower8-vector");
16145 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16146 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16147 error ("builtin function %qs requires the %qs and %qs options",
16148 name, "-mcpu=power9", "-m64");
16149 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
16150 error ("builtin function %qs requires the %qs option", name,
16152 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16153 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16154 error ("builtin function %qs requires the %qs and %qs options",
16155 name, "-mcpu=power9", "-m64");
16156 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
16157 error ("builtin function %qs requires the %qs option", name,
16159 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16160 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16161 error ("builtin function %qs requires the %qs and %qs options",
16162 name, "-mhard-float", "-mlong-double-128");
16163 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
16164 error ("builtin function %qs requires the %qs option", name,
16166 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
16167 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
16169 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
16170 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
16172 error ("builtin function %qs is not supported with the current options",
16176 /* Target hook for early folding of built-ins, shamelessly stolen
16180 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
16181 int n_args ATTRIBUTE_UNUSED,
16182 tree *args ATTRIBUTE_UNUSED,
16183 bool ignore ATTRIBUTE_UNUSED)
16185 #ifdef SUBTARGET_FOLD_BUILTIN
16186 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
16192 /* Helper function to sort out which built-ins may be valid without having
16195 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
16199 case ALTIVEC_BUILTIN_STVX_V16QI:
16200 case ALTIVEC_BUILTIN_STVX_V8HI:
16201 case ALTIVEC_BUILTIN_STVX_V4SI:
16202 case ALTIVEC_BUILTIN_STVX_V4SF:
16203 case ALTIVEC_BUILTIN_STVX_V2DI:
16204 case ALTIVEC_BUILTIN_STVX_V2DF:
16211 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16212 a constant, use rs6000_fold_builtin.) */
16215 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
16217 gimple *stmt = gsi_stmt (*gsi);
16218 tree fndecl = gimple_call_fndecl (stmt);
16219 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
16220 enum rs6000_builtins fn_code
16221 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16222 tree arg0, arg1, lhs;
16224 size_t uns_fncode = (size_t) fn_code;
16225 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
16226 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
16227 const char *fn_name2 = (icode != CODE_FOR_nothing)
16228 ? get_insn_name ((int) icode)
16231 if (TARGET_DEBUG_BUILTIN)
16232 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
16233 fn_code, fn_name1, fn_name2);
16235 if (!rs6000_fold_gimple)
16238 /* Prevent gimple folding for code that does not have a LHS, unless it is
16239 allowed per the rs6000_builtin_valid_without_lhs helper function. */
16240 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
16245 /* Flavors of vec_add. We deliberately don't expand
16246 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16247 TImode, resulting in much poorer code generation. */
16248 case ALTIVEC_BUILTIN_VADDUBM:
16249 case ALTIVEC_BUILTIN_VADDUHM:
16250 case ALTIVEC_BUILTIN_VADDUWM:
16251 case P8V_BUILTIN_VADDUDM:
16252 case ALTIVEC_BUILTIN_VADDFP:
16253 case VSX_BUILTIN_XVADDDP:
16255 arg0 = gimple_call_arg (stmt, 0);
16256 arg1 = gimple_call_arg (stmt, 1);
16257 lhs = gimple_call_lhs (stmt);
16258 gimple *g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
16259 gimple_set_location (g, gimple_location (stmt));
16260 gsi_replace (gsi, g, true);
16263 /* Flavors of vec_sub. We deliberately don't expand
16264 P8V_BUILTIN_VSUBUQM. */
16265 case ALTIVEC_BUILTIN_VSUBUBM:
16266 case ALTIVEC_BUILTIN_VSUBUHM:
16267 case ALTIVEC_BUILTIN_VSUBUWM:
16268 case P8V_BUILTIN_VSUBUDM:
16269 case ALTIVEC_BUILTIN_VSUBFP:
16270 case VSX_BUILTIN_XVSUBDP:
16272 arg0 = gimple_call_arg (stmt, 0);
16273 arg1 = gimple_call_arg (stmt, 1);
16274 lhs = gimple_call_lhs (stmt);
16275 gimple *g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
16276 gimple_set_location (g, gimple_location (stmt));
16277 gsi_replace (gsi, g, true);
16280 case VSX_BUILTIN_XVMULSP:
16281 case VSX_BUILTIN_XVMULDP:
16283 arg0 = gimple_call_arg (stmt, 0);
16284 arg1 = gimple_call_arg (stmt, 1);
16285 lhs = gimple_call_lhs (stmt);
16286 gimple *g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
16287 gimple_set_location (g, gimple_location (stmt));
16288 gsi_replace (gsi, g, true);
16291 /* Even element flavors of vec_mul (signed). */
16292 case ALTIVEC_BUILTIN_VMULESB:
16293 case ALTIVEC_BUILTIN_VMULESH:
16294 case ALTIVEC_BUILTIN_VMULESW:
16295 /* Even element flavors of vec_mul (unsigned). */
16296 case ALTIVEC_BUILTIN_VMULEUB:
16297 case ALTIVEC_BUILTIN_VMULEUH:
16298 case ALTIVEC_BUILTIN_VMULEUW:
16300 arg0 = gimple_call_arg (stmt, 0);
16301 arg1 = gimple_call_arg (stmt, 1);
16302 lhs = gimple_call_lhs (stmt);
16303 gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
16304 gimple_set_location (g, gimple_location (stmt));
16305 gsi_replace (gsi, g, true);
16308 /* Odd element flavors of vec_mul (signed). */
16309 case ALTIVEC_BUILTIN_VMULOSB:
16310 case ALTIVEC_BUILTIN_VMULOSH:
16311 case ALTIVEC_BUILTIN_VMULOSW:
16312 /* Odd element flavors of vec_mul (unsigned). */
16313 case ALTIVEC_BUILTIN_VMULOUB:
16314 case ALTIVEC_BUILTIN_VMULOUH:
16315 case ALTIVEC_BUILTIN_VMULOUW:
16317 arg0 = gimple_call_arg (stmt, 0);
16318 arg1 = gimple_call_arg (stmt, 1);
16319 lhs = gimple_call_lhs (stmt);
16320 gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
16321 gimple_set_location (g, gimple_location (stmt));
16322 gsi_replace (gsi, g, true);
16325 /* Flavors of vec_div (Integer). */
16326 case VSX_BUILTIN_DIV_V2DI:
16327 case VSX_BUILTIN_UDIV_V2DI:
16329 arg0 = gimple_call_arg (stmt, 0);
16330 arg1 = gimple_call_arg (stmt, 1);
16331 lhs = gimple_call_lhs (stmt);
16332 gimple *g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
16333 gimple_set_location (g, gimple_location (stmt));
16334 gsi_replace (gsi, g, true);
16337 /* Flavors of vec_div (Float). */
16338 case VSX_BUILTIN_XVDIVSP:
16339 case VSX_BUILTIN_XVDIVDP:
16341 arg0 = gimple_call_arg (stmt, 0);
16342 arg1 = gimple_call_arg (stmt, 1);
16343 lhs = gimple_call_lhs (stmt);
16344 gimple *g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
16345 gimple_set_location (g, gimple_location (stmt));
16346 gsi_replace (gsi, g, true);
16349 /* Flavors of vec_and. */
16350 case ALTIVEC_BUILTIN_VAND:
16352 arg0 = gimple_call_arg (stmt, 0);
16353 arg1 = gimple_call_arg (stmt, 1);
16354 lhs = gimple_call_lhs (stmt);
16355 gimple *g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
16356 gimple_set_location (g, gimple_location (stmt));
16357 gsi_replace (gsi, g, true);
16360 /* Flavors of vec_andc. */
16361 case ALTIVEC_BUILTIN_VANDC:
16363 arg0 = gimple_call_arg (stmt, 0);
16364 arg1 = gimple_call_arg (stmt, 1);
16365 lhs = gimple_call_lhs (stmt);
16366 tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16367 gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1);
16368 gimple_set_location (g, gimple_location (stmt));
16369 gsi_insert_before(gsi, g, GSI_SAME_STMT);
16370 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
16371 gimple_set_location (g, gimple_location (stmt));
16372 gsi_replace (gsi, g, true);
16375 /* Flavors of vec_nand. */
16376 case P8V_BUILTIN_VEC_NAND:
16377 case P8V_BUILTIN_NAND_V16QI:
16378 case P8V_BUILTIN_NAND_V8HI:
16379 case P8V_BUILTIN_NAND_V4SI:
16380 case P8V_BUILTIN_NAND_V4SF:
16381 case P8V_BUILTIN_NAND_V2DF:
16382 case P8V_BUILTIN_NAND_V2DI:
16384 arg0 = gimple_call_arg (stmt, 0);
16385 arg1 = gimple_call_arg (stmt, 1);
16386 lhs = gimple_call_lhs (stmt);
16387 tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16388 gimple *g = gimple_build_assign(temp, BIT_AND_EXPR, arg0, arg1);
16389 gimple_set_location (g, gimple_location (stmt));
16390 gsi_insert_before(gsi, g, GSI_SAME_STMT);
16391 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16392 gimple_set_location (g, gimple_location (stmt));
16393 gsi_replace (gsi, g, true);
16396 /* Flavors of vec_or. */
16397 case ALTIVEC_BUILTIN_VOR:
16399 arg0 = gimple_call_arg (stmt, 0);
16400 arg1 = gimple_call_arg (stmt, 1);
16401 lhs = gimple_call_lhs (stmt);
16402 gimple *g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
16403 gimple_set_location (g, gimple_location (stmt));
16404 gsi_replace (gsi, g, true);
16407 /* flavors of vec_orc. */
16408 case P8V_BUILTIN_ORC_V16QI:
16409 case P8V_BUILTIN_ORC_V8HI:
16410 case P8V_BUILTIN_ORC_V4SI:
16411 case P8V_BUILTIN_ORC_V4SF:
16412 case P8V_BUILTIN_ORC_V2DF:
16413 case P8V_BUILTIN_ORC_V2DI:
16415 arg0 = gimple_call_arg (stmt, 0);
16416 arg1 = gimple_call_arg (stmt, 1);
16417 lhs = gimple_call_lhs (stmt);
16418 tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16419 gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1);
16420 gimple_set_location (g, gimple_location (stmt));
16421 gsi_insert_before(gsi, g, GSI_SAME_STMT);
16422 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
16423 gimple_set_location (g, gimple_location (stmt));
16424 gsi_replace (gsi, g, true);
16427 /* Flavors of vec_xor. */
16428 case ALTIVEC_BUILTIN_VXOR:
16430 arg0 = gimple_call_arg (stmt, 0);
16431 arg1 = gimple_call_arg (stmt, 1);
16432 lhs = gimple_call_lhs (stmt);
16433 gimple *g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
16434 gimple_set_location (g, gimple_location (stmt));
16435 gsi_replace (gsi, g, true);
16438 /* Flavors of vec_nor. */
16439 case ALTIVEC_BUILTIN_VNOR:
16441 arg0 = gimple_call_arg (stmt, 0);
16442 arg1 = gimple_call_arg (stmt, 1);
16443 lhs = gimple_call_lhs (stmt);
16444 tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16445 gimple *g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
16446 gimple_set_location (g, gimple_location (stmt));
16447 gsi_insert_before(gsi, g, GSI_SAME_STMT);
16448 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16449 gimple_set_location (g, gimple_location (stmt));
16450 gsi_replace (gsi, g, true);
16453 /* flavors of vec_abs. */
16454 case ALTIVEC_BUILTIN_ABS_V16QI:
16455 case ALTIVEC_BUILTIN_ABS_V8HI:
16456 case ALTIVEC_BUILTIN_ABS_V4SI:
16457 case ALTIVEC_BUILTIN_ABS_V4SF:
16458 case P8V_BUILTIN_ABS_V2DI:
16459 case VSX_BUILTIN_XVABSDP:
16461 arg0 = gimple_call_arg (stmt, 0);
16462 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16463 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16465 lhs = gimple_call_lhs (stmt);
16466 gimple *g = gimple_build_assign (lhs, ABS_EXPR, arg0);
16467 gimple_set_location (g, gimple_location (stmt));
16468 gsi_replace (gsi, g, true);
16471 /* flavors of vec_min. */
16472 case VSX_BUILTIN_XVMINDP:
16473 case P8V_BUILTIN_VMINSD:
16474 case P8V_BUILTIN_VMINUD:
16475 case ALTIVEC_BUILTIN_VMINSB:
16476 case ALTIVEC_BUILTIN_VMINSH:
16477 case ALTIVEC_BUILTIN_VMINSW:
16478 case ALTIVEC_BUILTIN_VMINUB:
16479 case ALTIVEC_BUILTIN_VMINUH:
16480 case ALTIVEC_BUILTIN_VMINUW:
16481 case ALTIVEC_BUILTIN_VMINFP:
16483 arg0 = gimple_call_arg (stmt, 0);
16484 arg1 = gimple_call_arg (stmt, 1);
16485 lhs = gimple_call_lhs (stmt);
16486 gimple *g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
16487 gimple_set_location (g, gimple_location (stmt));
16488 gsi_replace (gsi, g, true);
16491 /* flavors of vec_max. */
16492 case VSX_BUILTIN_XVMAXDP:
16493 case P8V_BUILTIN_VMAXSD:
16494 case P8V_BUILTIN_VMAXUD:
16495 case ALTIVEC_BUILTIN_VMAXSB:
16496 case ALTIVEC_BUILTIN_VMAXSH:
16497 case ALTIVEC_BUILTIN_VMAXSW:
16498 case ALTIVEC_BUILTIN_VMAXUB:
16499 case ALTIVEC_BUILTIN_VMAXUH:
16500 case ALTIVEC_BUILTIN_VMAXUW:
16501 case ALTIVEC_BUILTIN_VMAXFP:
16503 arg0 = gimple_call_arg (stmt, 0);
16504 arg1 = gimple_call_arg (stmt, 1);
16505 lhs = gimple_call_lhs (stmt);
16506 gimple *g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
16507 gimple_set_location (g, gimple_location (stmt));
16508 gsi_replace (gsi, g, true);
16511 /* Flavors of vec_eqv. */
16512 case P8V_BUILTIN_EQV_V16QI:
16513 case P8V_BUILTIN_EQV_V8HI:
16514 case P8V_BUILTIN_EQV_V4SI:
16515 case P8V_BUILTIN_EQV_V4SF:
16516 case P8V_BUILTIN_EQV_V2DF:
16517 case P8V_BUILTIN_EQV_V2DI:
16519 arg0 = gimple_call_arg (stmt, 0);
16520 arg1 = gimple_call_arg (stmt, 1);
16521 lhs = gimple_call_lhs (stmt);
16522 tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16523 gimple *g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
16524 gimple_set_location (g, gimple_location (stmt));
16525 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16526 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16527 gimple_set_location (g, gimple_location (stmt));
16528 gsi_replace (gsi, g, true);
16531 /* Flavors of vec_rotate_left. */
16532 case ALTIVEC_BUILTIN_VRLB:
16533 case ALTIVEC_BUILTIN_VRLH:
16534 case ALTIVEC_BUILTIN_VRLW:
16535 case P8V_BUILTIN_VRLD:
16537 arg0 = gimple_call_arg (stmt, 0);
16538 arg1 = gimple_call_arg (stmt, 1);
16539 lhs = gimple_call_lhs (stmt);
16540 gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
16541 gimple_set_location (g, gimple_location (stmt));
16542 gsi_replace (gsi, g, true);
16545 /* Flavors of vector shift right algebraic.
16546 vec_sra{b,h,w} -> vsra{b,h,w}. */
16547 case ALTIVEC_BUILTIN_VSRAB:
16548 case ALTIVEC_BUILTIN_VSRAH:
16549 case ALTIVEC_BUILTIN_VSRAW:
16550 case P8V_BUILTIN_VSRAD:
16552 arg0 = gimple_call_arg (stmt, 0);
16553 arg1 = gimple_call_arg (stmt, 1);
16554 lhs = gimple_call_lhs (stmt);
16555 gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
16556 gimple_set_location (g, gimple_location (stmt));
16557 gsi_replace (gsi, g, true);
16560 /* Flavors of vector shift left.
16561 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16562 case ALTIVEC_BUILTIN_VSLB:
16563 case ALTIVEC_BUILTIN_VSLH:
16564 case ALTIVEC_BUILTIN_VSLW:
16565 case P8V_BUILTIN_VSLD:
16567 arg0 = gimple_call_arg (stmt, 0);
16568 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16569 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16571 arg1 = gimple_call_arg (stmt, 1);
16572 lhs = gimple_call_lhs (stmt);
16573 gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
16574 gimple_set_location (g, gimple_location (stmt));
16575 gsi_replace (gsi, g, true);
16578 /* Flavors of vector shift right. */
16579 case ALTIVEC_BUILTIN_VSRB:
16580 case ALTIVEC_BUILTIN_VSRH:
16581 case ALTIVEC_BUILTIN_VSRW:
16582 case P8V_BUILTIN_VSRD:
16584 arg0 = gimple_call_arg (stmt, 0);
16585 arg1 = gimple_call_arg (stmt, 1);
16586 lhs = gimple_call_lhs (stmt);
16587 gimple_seq stmts = NULL;
16588 /* Convert arg0 to unsigned. */
16590 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
16591 unsigned_type_for (TREE_TYPE (arg0)), arg0);
16593 = gimple_build (&stmts, RSHIFT_EXPR,
16594 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
16595 /* Convert result back to the lhs type. */
16596 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
16597 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16598 update_call_from_tree (gsi, res);
16601 /* Vector loads. */
16602 case ALTIVEC_BUILTIN_LVX_V16QI:
16603 case ALTIVEC_BUILTIN_LVX_V8HI:
16604 case ALTIVEC_BUILTIN_LVX_V4SI:
16605 case ALTIVEC_BUILTIN_LVX_V4SF:
16606 case ALTIVEC_BUILTIN_LVX_V2DI:
16607 case ALTIVEC_BUILTIN_LVX_V2DF:
16609 arg0 = gimple_call_arg (stmt, 0); // offset
16610 arg1 = gimple_call_arg (stmt, 1); // address
16611 /* Do not fold for -maltivec=be on LE targets. */
16612 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16614 lhs = gimple_call_lhs (stmt);
16615 location_t loc = gimple_location (stmt);
16616 /* Since arg1 may be cast to a different type, just use ptr_type_node
16617 here instead of trying to enforce TBAA on pointer types. */
16618 tree arg1_type = ptr_type_node;
16619 tree lhs_type = TREE_TYPE (lhs);
16620 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16621 the tree using the value from arg0. The resulting type will match
16622 the type of arg1. */
16623 gimple_seq stmts = NULL;
16624 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
16625 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16626 arg1_type, arg1, temp_offset);
16627 /* Mask off any lower bits from the address. */
16628 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16629 arg1_type, temp_addr,
16630 build_int_cst (arg1_type, -16));
16631 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16632 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16633 take an offset, but since we've already incorporated the offset
16634 above, here we just pass in a zero. */
16636 g = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
16637 build_int_cst (arg1_type, 0)));
16638 gimple_set_location (g, loc);
16639 gsi_replace (gsi, g, true);
16642 /* Vector stores. */
16643 case ALTIVEC_BUILTIN_STVX_V16QI:
16644 case ALTIVEC_BUILTIN_STVX_V8HI:
16645 case ALTIVEC_BUILTIN_STVX_V4SI:
16646 case ALTIVEC_BUILTIN_STVX_V4SF:
16647 case ALTIVEC_BUILTIN_STVX_V2DI:
16648 case ALTIVEC_BUILTIN_STVX_V2DF:
16650 /* Do not fold for -maltivec=be on LE targets. */
16651 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16653 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
16654 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
16655 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
16656 location_t loc = gimple_location (stmt);
16657 tree arg0_type = TREE_TYPE (arg0);
16658 /* Use ptr_type_node (no TBAA) for the arg2_type.
16659 FIXME: (Richard) "A proper fix would be to transition this type as
16660 seen from the frontend to GIMPLE, for example in a similar way we
16661 do for MEM_REFs by piggy-backing that on an extra argument, a
16662 constant zero pointer of the alias pointer type to use (which would
16663 also serve as a type indicator of the store itself). I'd use a
16664 target specific internal function for this (not sure if we can have
16665 those target specific, but I guess if it's folded away then that's
16666 fine) and get away with the overload set."
16668 tree arg2_type = ptr_type_node;
16669 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16670 the tree using the value from arg0. The resulting type will match
16671 the type of arg2. */
16672 gimple_seq stmts = NULL;
16673 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
16674 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16675 arg2_type, arg2, temp_offset);
16676 /* Mask off any lower bits from the address. */
16677 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16678 arg2_type, temp_addr,
16679 build_int_cst (arg2_type, -16));
16680 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16681 /* The desired gimple result should be similar to:
16682 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
16684 g = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
16685 build_int_cst (arg2_type, 0)), arg0);
16686 gimple_set_location (g, loc);
16687 gsi_replace (gsi, g, true);
16691 /* Vector Fused multiply-add (fma). */
16692 case ALTIVEC_BUILTIN_VMADDFP:
16693 case VSX_BUILTIN_XVMADDDP:
16694 case ALTIVEC_BUILTIN_VMLADDUHM:
16696 arg0 = gimple_call_arg (stmt, 0);
16697 arg1 = gimple_call_arg (stmt, 1);
16698 tree arg2 = gimple_call_arg (stmt, 2);
16699 lhs = gimple_call_lhs (stmt);
16700 gimple *g = gimple_build_assign (lhs, FMA_EXPR , arg0, arg1, arg2);
16701 gimple_set_location (g, gimple_location (stmt));
16702 gsi_replace (gsi, g, true);
16707 if (TARGET_DEBUG_BUILTIN)
16708 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16709 fn_code, fn_name1, fn_name2);
16716 /* Expand an expression EXP that calls a built-in function,
16717 with result going to TARGET if that's convenient
16718 (and in mode MODE if that's convenient).
16719 SUBTARGET may be used as the target for computing one of EXP's operands.
16720 IGNORE is nonzero if the value is to be ignored. */
16723 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16724 machine_mode mode ATTRIBUTE_UNUSED,
16725 int ignore ATTRIBUTE_UNUSED)
16727 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16728 enum rs6000_builtins fcode
16729 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16730 size_t uns_fcode = (size_t)fcode;
16731 const struct builtin_description *d;
16735 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16736 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16738 if (TARGET_DEBUG_BUILTIN)
16740 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16741 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16742 const char *name2 = (icode != CODE_FOR_nothing)
16743 ? get_insn_name ((int) icode)
16747 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16749 default: name3 = "unknown"; break;
16750 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16751 case RS6000_BTC_UNARY: name3 = "unary"; break;
16752 case RS6000_BTC_BINARY: name3 = "binary"; break;
16753 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16754 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16755 case RS6000_BTC_ABS: name3 = "abs"; break;
16756 case RS6000_BTC_DST: name3 = "dst"; break;
16761 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16762 (name1) ? name1 : "---", fcode,
16763 (name2) ? name2 : "---", (int) icode,
16765 func_valid_p ? "" : ", not valid");
16770 rs6000_invalid_builtin (fcode);
16772 /* Given it is invalid, just generate a normal call. */
16773 return expand_call (exp, target, ignore);
16778 case RS6000_BUILTIN_RECIP:
16779 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16781 case RS6000_BUILTIN_RECIPF:
16782 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16784 case RS6000_BUILTIN_RSQRTF:
16785 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16787 case RS6000_BUILTIN_RSQRT:
16788 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16790 case POWER7_BUILTIN_BPERMD:
16791 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16792 ? CODE_FOR_bpermd_di
16793 : CODE_FOR_bpermd_si), exp, target);
16795 case RS6000_BUILTIN_GET_TB:
16796 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16799 case RS6000_BUILTIN_MFTB:
16800 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16801 ? CODE_FOR_rs6000_mftb_di
16802 : CODE_FOR_rs6000_mftb_si),
16805 case RS6000_BUILTIN_MFFS:
16806 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16808 case RS6000_BUILTIN_MTFSF:
16809 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16811 case RS6000_BUILTIN_CPU_INIT:
16812 case RS6000_BUILTIN_CPU_IS:
16813 case RS6000_BUILTIN_CPU_SUPPORTS:
16814 return cpu_expand_builtin (fcode, exp, target);
16816 case FLOAT128_BUILTIN_SQRTF128_ODD:
16817 return rs6000_expand_unop_builtin (TARGET_IEEEQUAD
16818 ? CODE_FOR_sqrttf2_odd
16819 : CODE_FOR_sqrtkf2_odd, exp, target);
16821 case FLOAT128_BUILTIN_TRUNCF128_ODD:
16822 return rs6000_expand_unop_builtin (TARGET_IEEEQUAD
16823 ? CODE_FOR_trunctfdf2_odd
16824 : CODE_FOR_trunckfdf2_odd, exp, target);
16826 case FLOAT128_BUILTIN_ADDF128_ODD:
16827 return rs6000_expand_binop_builtin (TARGET_IEEEQUAD
16828 ? CODE_FOR_addtf3_odd
16829 : CODE_FOR_addkf3_odd, exp, target);
16831 case FLOAT128_BUILTIN_SUBF128_ODD:
16832 return rs6000_expand_binop_builtin (TARGET_IEEEQUAD
16833 ? CODE_FOR_subtf3_odd
16834 : CODE_FOR_subkf3_odd, exp, target);
16836 case FLOAT128_BUILTIN_MULF128_ODD:
16837 return rs6000_expand_binop_builtin (TARGET_IEEEQUAD
16838 ? CODE_FOR_multf3_odd
16839 : CODE_FOR_mulkf3_odd, exp, target);
16841 case FLOAT128_BUILTIN_DIVF128_ODD:
16842 return rs6000_expand_binop_builtin (TARGET_IEEEQUAD
16843 ? CODE_FOR_divtf3_odd
16844 : CODE_FOR_divkf3_odd, exp, target);
16846 case FLOAT128_BUILTIN_FMAF128_ODD:
16847 return rs6000_expand_ternop_builtin (TARGET_IEEEQUAD
16848 ? CODE_FOR_fmatf4_odd
16849 : CODE_FOR_fmakf4_odd, exp, target);
16851 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16852 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16854 int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16855 : (int) CODE_FOR_altivec_lvsl_direct);
16856 machine_mode tmode = insn_data[icode].operand[0].mode;
16857 machine_mode mode = insn_data[icode].operand[1].mode;
16861 gcc_assert (TARGET_ALTIVEC);
16863 arg = CALL_EXPR_ARG (exp, 0);
16864 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16865 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16866 addr = memory_address (mode, op);
16867 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16871 /* For the load case need to negate the address. */
16872 op = gen_reg_rtx (GET_MODE (addr));
16873 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16875 op = gen_rtx_MEM (mode, op);
16878 || GET_MODE (target) != tmode
16879 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16880 target = gen_reg_rtx (tmode);
16882 pat = GEN_FCN (icode) (target, op);
16890 case ALTIVEC_BUILTIN_VCFUX:
16891 case ALTIVEC_BUILTIN_VCFSX:
16892 case ALTIVEC_BUILTIN_VCTUXS:
16893 case ALTIVEC_BUILTIN_VCTSXS:
16894 /* FIXME: There's got to be a nicer way to handle this case than
16895 constructing a new CALL_EXPR. */
16896 if (call_expr_nargs (exp) == 1)
16898 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16899 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16907 if (TARGET_ALTIVEC)
16909 ret = altivec_expand_builtin (exp, target, &success);
16914 if (TARGET_PAIRED_FLOAT)
16916 ret = paired_expand_builtin (exp, target, &success);
16923 ret = htm_expand_builtin (exp, target, &success);
16929 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16930 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16931 gcc_assert (attr == RS6000_BTC_UNARY
16932 || attr == RS6000_BTC_BINARY
16933 || attr == RS6000_BTC_TERNARY
16934 || attr == RS6000_BTC_SPECIAL);
16936 /* Handle simple unary operations. */
16938 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16939 if (d->code == fcode)
16940 return rs6000_expand_unop_builtin (d->icode, exp, target);
16942 /* Handle simple binary operations. */
16944 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16945 if (d->code == fcode)
16946 return rs6000_expand_binop_builtin (d->icode, exp, target);
16948 /* Handle simple ternary operations. */
16950 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16951 if (d->code == fcode)
16952 return rs6000_expand_ternop_builtin (d->icode, exp, target);
16954 /* Handle simple no-argument operations. */
16956 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16957 if (d->code == fcode)
16958 return rs6000_expand_zeroop_builtin (d->icode, target);
16960 gcc_unreachable ();
16963 /* Create a builtin vector type with a name. Taking care not to give
16964 the canonical type a name. */
16967 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16969 tree result = build_vector_type (elt_type, num_elts);
16971 /* Copy so we don't give the canonical type a name. */
16972 result = build_variant_type_copy (result);
16974 add_builtin_type (name, result);
16980 rs6000_init_builtins (void)
16986 if (TARGET_DEBUG_BUILTIN)
16987 fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
16988 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
16989 (TARGET_ALTIVEC) ? ", altivec" : "",
16990 (TARGET_VSX) ? ", vsx" : "");
16992 V2SI_type_node = build_vector_type (intSI_type_node, 2);
16993 V2SF_type_node = build_vector_type (float_type_node, 2);
16994 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16995 : "__vector long long",
16996 intDI_type_node, 2);
16997 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16998 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16999 intSI_type_node, 4);
17000 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
17001 V8HI_type_node = rs6000_vector_type ("__vector signed short",
17002 intHI_type_node, 8);
17003 V16QI_type_node = rs6000_vector_type ("__vector signed char",
17004 intQI_type_node, 16);
17006 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
17007 unsigned_intQI_type_node, 16);
17008 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
17009 unsigned_intHI_type_node, 8);
17010 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
17011 unsigned_intSI_type_node, 4);
17012 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17013 ? "__vector unsigned long"
17014 : "__vector unsigned long long",
17015 unsigned_intDI_type_node, 2);
17017 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
17018 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
17019 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
17020 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
17022 const_str_type_node
17023 = build_pointer_type (build_qualified_type (char_type_node,
17026 /* We use V1TI mode as a special container to hold __int128_t items that
17027 must live in VSX registers. */
17028 if (intTI_type_node)
17030 V1TI_type_node = rs6000_vector_type ("__vector __int128",
17031 intTI_type_node, 1);
17032 unsigned_V1TI_type_node
17033 = rs6000_vector_type ("__vector unsigned __int128",
17034 unsigned_intTI_type_node, 1);
17037 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
17038 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
17039 'vector unsigned short'. */
17041 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
17042 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17043 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
17044 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
17045 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17047 long_integer_type_internal_node = long_integer_type_node;
17048 long_unsigned_type_internal_node = long_unsigned_type_node;
17049 long_long_integer_type_internal_node = long_long_integer_type_node;
17050 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
17051 intQI_type_internal_node = intQI_type_node;
17052 uintQI_type_internal_node = unsigned_intQI_type_node;
17053 intHI_type_internal_node = intHI_type_node;
17054 uintHI_type_internal_node = unsigned_intHI_type_node;
17055 intSI_type_internal_node = intSI_type_node;
17056 uintSI_type_internal_node = unsigned_intSI_type_node;
17057 intDI_type_internal_node = intDI_type_node;
17058 uintDI_type_internal_node = unsigned_intDI_type_node;
17059 intTI_type_internal_node = intTI_type_node;
17060 uintTI_type_internal_node = unsigned_intTI_type_node;
17061 float_type_internal_node = float_type_node;
17062 double_type_internal_node = double_type_node;
17063 long_double_type_internal_node = long_double_type_node;
17064 dfloat64_type_internal_node = dfloat64_type_node;
17065 dfloat128_type_internal_node = dfloat128_type_node;
17066 void_type_internal_node = void_type_node;
17068 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
17069 IFmode is the IBM extended 128-bit format that is a pair of doubles.
17070 TFmode will be either IEEE 128-bit floating point or the IBM double-double
17071 format that uses a pair of doubles, depending on the switches and
17074 If we don't support for either 128-bit IBM double double or IEEE 128-bit
17075 floating point, we need make sure the type is non-zero or else self-test
17076 fails during bootstrap.
17078 We don't register a built-in type for __ibm128 if the type is the same as
17079 long double. Instead we add a #define for __ibm128 in
17080 rs6000_cpu_cpp_builtins to long double.
17082 For IEEE 128-bit floating point, always create the type __ieee128. If the
17083 user used -mfloat128, rs6000-c.c will create a define from __float128 to
17085 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
17087 ibm128_float_type_node = make_node (REAL_TYPE);
17088 TYPE_PRECISION (ibm128_float_type_node) = 128;
17089 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
17090 layout_type (ibm128_float_type_node);
17092 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
17096 ibm128_float_type_node = long_double_type_node;
17098 if (TARGET_FLOAT128_TYPE)
17100 ieee128_float_type_node = float128_type_node;
17101 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
17106 ieee128_float_type_node = long_double_type_node;
17108 /* Initialize the modes for builtin_function_type, mapping a machine mode to
17110 builtin_mode_to_type[QImode][0] = integer_type_node;
17111 builtin_mode_to_type[HImode][0] = integer_type_node;
17112 builtin_mode_to_type[SImode][0] = intSI_type_node;
17113 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
17114 builtin_mode_to_type[DImode][0] = intDI_type_node;
17115 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
17116 builtin_mode_to_type[TImode][0] = intTI_type_node;
17117 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
17118 builtin_mode_to_type[SFmode][0] = float_type_node;
17119 builtin_mode_to_type[DFmode][0] = double_type_node;
17120 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
17121 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
17122 builtin_mode_to_type[TFmode][0] = long_double_type_node;
17123 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
17124 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
17125 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
17126 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
17127 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
17128 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
17129 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
17130 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
17131 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
17132 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
17133 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
17134 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
17135 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
17136 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
17137 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
17138 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
17140 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
17141 TYPE_NAME (bool_char_type_node) = tdecl;
17143 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
17144 TYPE_NAME (bool_short_type_node) = tdecl;
17146 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
17147 TYPE_NAME (bool_int_type_node) = tdecl;
17149 tdecl = add_builtin_type ("__pixel", pixel_type_node);
17150 TYPE_NAME (pixel_type_node) = tdecl;
17152 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
17153 bool_char_type_node, 16);
17154 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
17155 bool_short_type_node, 8);
17156 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
17157 bool_int_type_node, 4);
17158 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17159 ? "__vector __bool long"
17160 : "__vector __bool long long",
17161 bool_long_type_node, 2);
17162 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
17163 pixel_type_node, 8);
17165 /* Paired builtins are only available if you build a compiler with the
17166 appropriate options, so only create those builtins with the appropriate
17167 compiler option. Create Altivec and VSX builtins on machines with at
17168 least the general purpose extensions (970 and newer) to allow the use of
17169 the target attribute. */
17170 if (TARGET_PAIRED_FLOAT)
17171 paired_init_builtins ();
17172 if (TARGET_EXTRA_BUILTINS)
17173 altivec_init_builtins ();
17175 htm_init_builtins ();
17177 if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
17178 rs6000_common_init_builtins ();
17180 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
17181 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
17182 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
17184 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
17185 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
17186 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
17188 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
17189 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
17190 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
17192 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
17193 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
17194 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
17196 mode = (TARGET_64BIT) ? DImode : SImode;
17197 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
17198 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
17199 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
17201 ftype = build_function_type_list (unsigned_intDI_type_node,
17203 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
17206 ftype = build_function_type_list (unsigned_intDI_type_node,
17209 ftype = build_function_type_list (unsigned_intSI_type_node,
17211 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
17213 ftype = build_function_type_list (double_type_node, NULL_TREE);
17214 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
17216 ftype = build_function_type_list (void_type_node,
17217 intSI_type_node, double_type_node,
17219 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
17221 ftype = build_function_type_list (void_type_node, NULL_TREE);
17222 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
17224 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
17226 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
17227 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
17229 ftype = build_function_type_list (ieee128_float_type_node,
17230 ieee128_float_type_node, NULL_TREE);
17231 def_builtin ("__builtin_sqrtf128_round_to_odd", ftype,
17232 FLOAT128_BUILTIN_SQRTF128_ODD);
17233 def_builtin ("__builtin_truncf128_round_to_odd", ftype,
17234 FLOAT128_BUILTIN_TRUNCF128_ODD);
17236 ftype = build_function_type_list (ieee128_float_type_node,
17237 ieee128_float_type_node,
17238 ieee128_float_type_node, NULL_TREE);
17239 def_builtin ("__builtin_addf128_round_to_odd", ftype,
17240 FLOAT128_BUILTIN_ADDF128_ODD);
17241 def_builtin ("__builtin_subf128_round_to_odd", ftype,
17242 FLOAT128_BUILTIN_SUBF128_ODD);
17243 def_builtin ("__builtin_mulf128_round_to_odd", ftype,
17244 FLOAT128_BUILTIN_MULF128_ODD);
17245 def_builtin ("__builtin_divf128_round_to_odd", ftype,
17246 FLOAT128_BUILTIN_DIVF128_ODD);
17248 ftype = build_function_type_list (ieee128_float_type_node,
17249 ieee128_float_type_node,
17250 ieee128_float_type_node,
17251 ieee128_float_type_node, NULL_TREE);
17252 def_builtin ("__builtin_fmaf128_round_to_odd", ftype,
17253 FLOAT128_BUILTIN_FMAF128_ODD);
17255 /* AIX libm provides clog as __clog. */
17256 if (TARGET_XCOFF &&
17257 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
17258 set_user_assembler_name (tdecl, "__clog");
17260 #ifdef SUBTARGET_INIT_BUILTINS
17261 SUBTARGET_INIT_BUILTINS;
17265 /* Returns the rs6000 builtin decl for CODE. */
17268 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
17270 HOST_WIDE_INT fnmask;
17272 if (code >= RS6000_BUILTIN_COUNT)
17273 return error_mark_node;
17275 fnmask = rs6000_builtin_info[code].mask;
17276 if ((fnmask & rs6000_builtin_mask) != fnmask)
17278 rs6000_invalid_builtin ((enum rs6000_builtins)code);
17279 return error_mark_node;
17282 return rs6000_builtin_decls[code];
17286 paired_init_builtins (void)
17288 const struct builtin_description *d;
17290 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17292 tree int_ftype_int_v2sf_v2sf
17293 = build_function_type_list (integer_type_node,
17298 tree pcfloat_type_node =
17299 build_pointer_type (build_qualified_type
17300 (float_type_node, TYPE_QUAL_CONST));
17302 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
17303 long_integer_type_node,
17306 tree void_ftype_v2sf_long_pcfloat =
17307 build_function_type_list (void_type_node,
17309 long_integer_type_node,
17314 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
17315 PAIRED_BUILTIN_LX);
17318 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
17319 PAIRED_BUILTIN_STX);
17322 d = bdesc_paired_preds;
17323 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
17326 HOST_WIDE_INT mask = d->mask;
17328 if ((mask & builtin_mask) != mask)
17330 if (TARGET_DEBUG_BUILTIN)
17331 fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
17336 /* Cannot define builtin if the instruction is disabled. */
17337 gcc_assert (d->icode != CODE_FOR_nothing);
17339 if (TARGET_DEBUG_BUILTIN)
17340 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
17341 (int)i, get_insn_name (d->icode), (int)d->icode,
17342 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
17344 switch (insn_data[d->icode].operand[1].mode)
17347 type = int_ftype_int_v2sf_v2sf;
17350 gcc_unreachable ();
17353 def_builtin (d->name, type, d->code);
17358 altivec_init_builtins (void)
17360 const struct builtin_description *d;
17364 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17366 tree pvoid_type_node = build_pointer_type (void_type_node);
17368 tree pcvoid_type_node
17369 = build_pointer_type (build_qualified_type (void_type_node,
17372 tree int_ftype_opaque
17373 = build_function_type_list (integer_type_node,
17374 opaque_V4SI_type_node, NULL_TREE);
17375 tree opaque_ftype_opaque
17376 = build_function_type_list (integer_type_node, NULL_TREE);
17377 tree opaque_ftype_opaque_int
17378 = build_function_type_list (opaque_V4SI_type_node,
17379 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
17380 tree opaque_ftype_opaque_opaque_int
17381 = build_function_type_list (opaque_V4SI_type_node,
17382 opaque_V4SI_type_node, opaque_V4SI_type_node,
17383 integer_type_node, NULL_TREE);
17384 tree opaque_ftype_opaque_opaque_opaque
17385 = build_function_type_list (opaque_V4SI_type_node,
17386 opaque_V4SI_type_node, opaque_V4SI_type_node,
17387 opaque_V4SI_type_node, NULL_TREE);
17388 tree opaque_ftype_opaque_opaque
17389 = build_function_type_list (opaque_V4SI_type_node,
17390 opaque_V4SI_type_node, opaque_V4SI_type_node,
17392 tree int_ftype_int_opaque_opaque
17393 = build_function_type_list (integer_type_node,
17394 integer_type_node, opaque_V4SI_type_node,
17395 opaque_V4SI_type_node, NULL_TREE);
17396 tree int_ftype_int_v4si_v4si
17397 = build_function_type_list (integer_type_node,
17398 integer_type_node, V4SI_type_node,
17399 V4SI_type_node, NULL_TREE);
17400 tree int_ftype_int_v2di_v2di
17401 = build_function_type_list (integer_type_node,
17402 integer_type_node, V2DI_type_node,
17403 V2DI_type_node, NULL_TREE);
17404 tree void_ftype_v4si
17405 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
17406 tree v8hi_ftype_void
17407 = build_function_type_list (V8HI_type_node, NULL_TREE);
17408 tree void_ftype_void
17409 = build_function_type_list (void_type_node, NULL_TREE);
17410 tree void_ftype_int
17411 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
17413 tree opaque_ftype_long_pcvoid
17414 = build_function_type_list (opaque_V4SI_type_node,
17415 long_integer_type_node, pcvoid_type_node,
17417 tree v16qi_ftype_long_pcvoid
17418 = build_function_type_list (V16QI_type_node,
17419 long_integer_type_node, pcvoid_type_node,
17421 tree v8hi_ftype_long_pcvoid
17422 = build_function_type_list (V8HI_type_node,
17423 long_integer_type_node, pcvoid_type_node,
17425 tree v4si_ftype_long_pcvoid
17426 = build_function_type_list (V4SI_type_node,
17427 long_integer_type_node, pcvoid_type_node,
17429 tree v4sf_ftype_long_pcvoid
17430 = build_function_type_list (V4SF_type_node,
17431 long_integer_type_node, pcvoid_type_node,
17433 tree v2df_ftype_long_pcvoid
17434 = build_function_type_list (V2DF_type_node,
17435 long_integer_type_node, pcvoid_type_node,
17437 tree v2di_ftype_long_pcvoid
17438 = build_function_type_list (V2DI_type_node,
17439 long_integer_type_node, pcvoid_type_node,
17442 tree void_ftype_opaque_long_pvoid
17443 = build_function_type_list (void_type_node,
17444 opaque_V4SI_type_node, long_integer_type_node,
17445 pvoid_type_node, NULL_TREE);
17446 tree void_ftype_v4si_long_pvoid
17447 = build_function_type_list (void_type_node,
17448 V4SI_type_node, long_integer_type_node,
17449 pvoid_type_node, NULL_TREE);
17450 tree void_ftype_v16qi_long_pvoid
17451 = build_function_type_list (void_type_node,
17452 V16QI_type_node, long_integer_type_node,
17453 pvoid_type_node, NULL_TREE);
17455 tree void_ftype_v16qi_pvoid_long
17456 = build_function_type_list (void_type_node,
17457 V16QI_type_node, pvoid_type_node,
17458 long_integer_type_node, NULL_TREE);
17460 tree void_ftype_v8hi_long_pvoid
17461 = build_function_type_list (void_type_node,
17462 V8HI_type_node, long_integer_type_node,
17463 pvoid_type_node, NULL_TREE);
17464 tree void_ftype_v4sf_long_pvoid
17465 = build_function_type_list (void_type_node,
17466 V4SF_type_node, long_integer_type_node,
17467 pvoid_type_node, NULL_TREE);
17468 tree void_ftype_v2df_long_pvoid
17469 = build_function_type_list (void_type_node,
17470 V2DF_type_node, long_integer_type_node,
17471 pvoid_type_node, NULL_TREE);
17472 tree void_ftype_v2di_long_pvoid
17473 = build_function_type_list (void_type_node,
17474 V2DI_type_node, long_integer_type_node,
17475 pvoid_type_node, NULL_TREE);
17476 tree int_ftype_int_v8hi_v8hi
17477 = build_function_type_list (integer_type_node,
17478 integer_type_node, V8HI_type_node,
17479 V8HI_type_node, NULL_TREE);
17480 tree int_ftype_int_v16qi_v16qi
17481 = build_function_type_list (integer_type_node,
17482 integer_type_node, V16QI_type_node,
17483 V16QI_type_node, NULL_TREE);
17484 tree int_ftype_int_v4sf_v4sf
17485 = build_function_type_list (integer_type_node,
17486 integer_type_node, V4SF_type_node,
17487 V4SF_type_node, NULL_TREE);
17488 tree int_ftype_int_v2df_v2df
17489 = build_function_type_list (integer_type_node,
17490 integer_type_node, V2DF_type_node,
17491 V2DF_type_node, NULL_TREE);
17492 tree v2di_ftype_v2di
17493 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
17494 tree v4si_ftype_v4si
17495 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17496 tree v8hi_ftype_v8hi
17497 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17498 tree v16qi_ftype_v16qi
17499 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17500 tree v4sf_ftype_v4sf
17501 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17502 tree v2df_ftype_v2df
17503 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17504 tree void_ftype_pcvoid_int_int
17505 = build_function_type_list (void_type_node,
17506 pcvoid_type_node, integer_type_node,
17507 integer_type_node, NULL_TREE);
17509 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
17510 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
17511 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
17512 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
17513 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
17514 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
17515 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
17516 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
17517 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
17518 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
17519 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
17520 ALTIVEC_BUILTIN_LVXL_V2DF);
17521 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
17522 ALTIVEC_BUILTIN_LVXL_V2DI);
17523 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
17524 ALTIVEC_BUILTIN_LVXL_V4SF);
17525 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
17526 ALTIVEC_BUILTIN_LVXL_V4SI);
17527 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
17528 ALTIVEC_BUILTIN_LVXL_V8HI);
17529 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
17530 ALTIVEC_BUILTIN_LVXL_V16QI);
17531 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
17532 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
17533 ALTIVEC_BUILTIN_LVX_V2DF);
17534 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
17535 ALTIVEC_BUILTIN_LVX_V2DI);
17536 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
17537 ALTIVEC_BUILTIN_LVX_V4SF);
17538 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
17539 ALTIVEC_BUILTIN_LVX_V4SI);
17540 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
17541 ALTIVEC_BUILTIN_LVX_V8HI);
17542 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
17543 ALTIVEC_BUILTIN_LVX_V16QI);
17544 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
17545 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
17546 ALTIVEC_BUILTIN_STVX_V2DF);
17547 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
17548 ALTIVEC_BUILTIN_STVX_V2DI);
17549 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
17550 ALTIVEC_BUILTIN_STVX_V4SF);
17551 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
17552 ALTIVEC_BUILTIN_STVX_V4SI);
17553 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
17554 ALTIVEC_BUILTIN_STVX_V8HI);
17555 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
17556 ALTIVEC_BUILTIN_STVX_V16QI);
17557 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
17558 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
17559 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
17560 ALTIVEC_BUILTIN_STVXL_V2DF);
17561 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
17562 ALTIVEC_BUILTIN_STVXL_V2DI);
17563 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
17564 ALTIVEC_BUILTIN_STVXL_V4SF);
17565 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
17566 ALTIVEC_BUILTIN_STVXL_V4SI);
17567 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
17568 ALTIVEC_BUILTIN_STVXL_V8HI);
17569 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
17570 ALTIVEC_BUILTIN_STVXL_V16QI);
17571 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
17572 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
17573 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
17574 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
17575 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
17576 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
17577 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
17578 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
17579 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
17580 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
17581 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
17582 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
17583 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
17584 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
17585 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
17586 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
17588 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
17589 VSX_BUILTIN_LXVD2X_V2DF);
17590 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
17591 VSX_BUILTIN_LXVD2X_V2DI);
17592 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
17593 VSX_BUILTIN_LXVW4X_V4SF);
17594 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
17595 VSX_BUILTIN_LXVW4X_V4SI);
17596 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
17597 VSX_BUILTIN_LXVW4X_V8HI);
17598 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
17599 VSX_BUILTIN_LXVW4X_V16QI);
17600 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
17601 VSX_BUILTIN_STXVD2X_V2DF);
17602 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
17603 VSX_BUILTIN_STXVD2X_V2DI);
17604 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
17605 VSX_BUILTIN_STXVW4X_V4SF);
17606 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
17607 VSX_BUILTIN_STXVW4X_V4SI);
17608 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
17609 VSX_BUILTIN_STXVW4X_V8HI);
17610 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
17611 VSX_BUILTIN_STXVW4X_V16QI);
17613 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
17614 VSX_BUILTIN_LD_ELEMREV_V2DF);
17615 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
17616 VSX_BUILTIN_LD_ELEMREV_V2DI);
17617 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
17618 VSX_BUILTIN_LD_ELEMREV_V4SF);
17619 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
17620 VSX_BUILTIN_LD_ELEMREV_V4SI);
17621 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
17622 VSX_BUILTIN_ST_ELEMREV_V2DF);
17623 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
17624 VSX_BUILTIN_ST_ELEMREV_V2DI);
17625 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17626 VSX_BUILTIN_ST_ELEMREV_V4SF);
17627 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17628 VSX_BUILTIN_ST_ELEMREV_V4SI);
17630 def_builtin ("__builtin_vsx_le_be_v8hi", v8hi_ftype_long_pcvoid,
17631 VSX_BUILTIN_XL_BE_V8HI);
17632 def_builtin ("__builtin_vsx_le_be_v4si", v4si_ftype_long_pcvoid,
17633 VSX_BUILTIN_XL_BE_V4SI);
17634 def_builtin ("__builtin_vsx_le_be_v2di", v2di_ftype_long_pcvoid,
17635 VSX_BUILTIN_XL_BE_V2DI);
17636 def_builtin ("__builtin_vsx_le_be_v4sf", v4sf_ftype_long_pcvoid,
17637 VSX_BUILTIN_XL_BE_V4SF);
17638 def_builtin ("__builtin_vsx_le_be_v2df", v2df_ftype_long_pcvoid,
17639 VSX_BUILTIN_XL_BE_V2DF);
17640 def_builtin ("__builtin_vsx_le_be_v16qi", v16qi_ftype_long_pcvoid,
17641 VSX_BUILTIN_XL_BE_V16QI);
17643 if (TARGET_P9_VECTOR)
17645 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
17646 VSX_BUILTIN_LD_ELEMREV_V8HI);
17647 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
17648 VSX_BUILTIN_LD_ELEMREV_V16QI);
17649 def_builtin ("__builtin_vsx_st_elemrev_v8hi",
17650 void_ftype_v8hi_long_pvoid, VSX_BUILTIN_ST_ELEMREV_V8HI);
17651 def_builtin ("__builtin_vsx_st_elemrev_v16qi",
17652 void_ftype_v16qi_long_pvoid, VSX_BUILTIN_ST_ELEMREV_V16QI);
17656 rs6000_builtin_decls[(int) VSX_BUILTIN_LD_ELEMREV_V8HI]
17657 = rs6000_builtin_decls[(int) VSX_BUILTIN_LXVW4X_V8HI];
17658 rs6000_builtin_decls[(int) VSX_BUILTIN_LD_ELEMREV_V16QI]
17659 = rs6000_builtin_decls[(int) VSX_BUILTIN_LXVW4X_V16QI];
17660 rs6000_builtin_decls[(int) VSX_BUILTIN_ST_ELEMREV_V8HI]
17661 = rs6000_builtin_decls[(int) VSX_BUILTIN_STXVW4X_V8HI];
17662 rs6000_builtin_decls[(int) VSX_BUILTIN_ST_ELEMREV_V16QI]
17663 = rs6000_builtin_decls[(int) VSX_BUILTIN_STXVW4X_V16QI];
17666 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17667 VSX_BUILTIN_VEC_LD);
17668 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17669 VSX_BUILTIN_VEC_ST);
17670 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17671 VSX_BUILTIN_VEC_XL);
17672 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17673 VSX_BUILTIN_VEC_XL_BE);
17674 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17675 VSX_BUILTIN_VEC_XST);
17677 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17678 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17679 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17681 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17682 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17683 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17684 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17685 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17686 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17687 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17688 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17689 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17690 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17691 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17692 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17694 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17695 ALTIVEC_BUILTIN_VEC_ADDE);
17696 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17697 ALTIVEC_BUILTIN_VEC_ADDEC);
17698 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17699 ALTIVEC_BUILTIN_VEC_CMPNE);
17700 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17701 ALTIVEC_BUILTIN_VEC_MUL);
17702 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17703 ALTIVEC_BUILTIN_VEC_SUBE);
17704 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17705 ALTIVEC_BUILTIN_VEC_SUBEC);
17707 /* Cell builtins. */
17708 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17709 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17710 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17711 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17713 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17714 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17715 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17716 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17718 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17719 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17720 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17721 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17723 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17724 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17725 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17726 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17728 if (TARGET_P9_VECTOR)
17730 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17731 P9V_BUILTIN_STXVL);
17732 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17733 P9V_BUILTIN_XST_LEN_R);
17736 /* Add the DST variants. */
17738 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17740 HOST_WIDE_INT mask = d->mask;
17742 /* It is expected that these dst built-in functions may have
17743 d->icode equal to CODE_FOR_nothing. */
17744 if ((mask & builtin_mask) != mask)
17746 if (TARGET_DEBUG_BUILTIN)
17747 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17751 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17754 /* Initialize the predicates. */
17755 d = bdesc_altivec_preds;
17756 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17758 machine_mode mode1;
17760 HOST_WIDE_INT mask = d->mask;
17762 if ((mask & builtin_mask) != mask)
17764 if (TARGET_DEBUG_BUILTIN)
17765 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17770 if (rs6000_overloaded_builtin_p (d->code))
17774 /* Cannot define builtin if the instruction is disabled. */
17775 gcc_assert (d->icode != CODE_FOR_nothing);
17776 mode1 = insn_data[d->icode].operand[1].mode;
17782 type = int_ftype_int_opaque_opaque;
17785 type = int_ftype_int_v2di_v2di;
17788 type = int_ftype_int_v4si_v4si;
17791 type = int_ftype_int_v8hi_v8hi;
17794 type = int_ftype_int_v16qi_v16qi;
17797 type = int_ftype_int_v4sf_v4sf;
17800 type = int_ftype_int_v2df_v2df;
17803 gcc_unreachable ();
17806 def_builtin (d->name, type, d->code);
17809 /* Initialize the abs* operators. */
17811 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17813 machine_mode mode0;
17815 HOST_WIDE_INT mask = d->mask;
17817 if ((mask & builtin_mask) != mask)
17819 if (TARGET_DEBUG_BUILTIN)
17820 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17825 /* Cannot define builtin if the instruction is disabled. */
17826 gcc_assert (d->icode != CODE_FOR_nothing);
17827 mode0 = insn_data[d->icode].operand[0].mode;
17832 type = v2di_ftype_v2di;
17835 type = v4si_ftype_v4si;
17838 type = v8hi_ftype_v8hi;
17841 type = v16qi_ftype_v16qi;
17844 type = v4sf_ftype_v4sf;
17847 type = v2df_ftype_v2df;
17850 gcc_unreachable ();
17853 def_builtin (d->name, type, d->code);
17856 /* Initialize target builtin that implements
17857 targetm.vectorize.builtin_mask_for_load. */
17859 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17860 v16qi_ftype_long_pcvoid,
17861 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17862 BUILT_IN_MD, NULL, NULL_TREE);
17863 TREE_READONLY (decl) = 1;
17864 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17865 altivec_builtin_mask_for_load = decl;
17867 /* Access to the vec_init patterns. */
17868 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17869 integer_type_node, integer_type_node,
17870 integer_type_node, NULL_TREE);
17871 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17873 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17874 short_integer_type_node,
17875 short_integer_type_node,
17876 short_integer_type_node,
17877 short_integer_type_node,
17878 short_integer_type_node,
17879 short_integer_type_node,
17880 short_integer_type_node, NULL_TREE);
17881 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17883 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17884 char_type_node, char_type_node,
17885 char_type_node, char_type_node,
17886 char_type_node, char_type_node,
17887 char_type_node, char_type_node,
17888 char_type_node, char_type_node,
17889 char_type_node, char_type_node,
17890 char_type_node, char_type_node,
17891 char_type_node, NULL_TREE);
17892 def_builtin ("__builtin_vec_init_v16qi", ftype,
17893 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17895 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17896 float_type_node, float_type_node,
17897 float_type_node, NULL_TREE);
17898 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17900 /* VSX builtins. */
17901 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17902 double_type_node, NULL_TREE);
17903 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17905 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17906 intDI_type_node, NULL_TREE);
17907 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17909 /* Access to the vec_set patterns. */
17910 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17912 integer_type_node, NULL_TREE);
17913 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17915 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17917 integer_type_node, NULL_TREE);
17918 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17920 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17922 integer_type_node, NULL_TREE);
17923 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17925 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17927 integer_type_node, NULL_TREE);
17928 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17930 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17932 integer_type_node, NULL_TREE);
17933 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17935 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17937 integer_type_node, NULL_TREE);
17938 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17940 /* Access to the vec_extract patterns. */
17941 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17942 integer_type_node, NULL_TREE);
17943 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17945 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17946 integer_type_node, NULL_TREE);
17947 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17949 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17950 integer_type_node, NULL_TREE);
17951 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17953 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17954 integer_type_node, NULL_TREE);
17955 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17957 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17958 integer_type_node, NULL_TREE);
17959 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17961 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17962 integer_type_node, NULL_TREE);
17963 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17966 if (V1TI_type_node)
17968 tree v1ti_ftype_long_pcvoid
17969 = build_function_type_list (V1TI_type_node,
17970 long_integer_type_node, pcvoid_type_node,
17972 tree void_ftype_v1ti_long_pvoid
17973 = build_function_type_list (void_type_node,
17974 V1TI_type_node, long_integer_type_node,
17975 pvoid_type_node, NULL_TREE);
17976 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17977 VSX_BUILTIN_LXVD2X_V1TI);
17978 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17979 VSX_BUILTIN_STXVD2X_V1TI);
17980 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17981 NULL_TREE, NULL_TREE);
17982 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17983 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17985 integer_type_node, NULL_TREE);
17986 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17987 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17988 integer_type_node, NULL_TREE);
17989 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17995 htm_init_builtins (void)
17997 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17998 const struct builtin_description *d;
18002 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
18004 tree op[MAX_HTM_OPERANDS], type;
18005 HOST_WIDE_INT mask = d->mask;
18006 unsigned attr = rs6000_builtin_info[d->code].attr;
18007 bool void_func = (attr & RS6000_BTC_VOID);
18008 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
18010 tree gpr_type_node;
18014 /* It is expected that these htm built-in functions may have
18015 d->icode equal to CODE_FOR_nothing. */
18017 if (TARGET_32BIT && TARGET_POWERPC64)
18018 gpr_type_node = long_long_unsigned_type_node;
18020 gpr_type_node = long_unsigned_type_node;
18022 if (attr & RS6000_BTC_SPR)
18024 rettype = gpr_type_node;
18025 argtype = gpr_type_node;
18027 else if (d->code == HTM_BUILTIN_TABORTDC
18028 || d->code == HTM_BUILTIN_TABORTDCI)
18030 rettype = unsigned_type_node;
18031 argtype = gpr_type_node;
18035 rettype = unsigned_type_node;
18036 argtype = unsigned_type_node;
18039 if ((mask & builtin_mask) != mask)
18041 if (TARGET_DEBUG_BUILTIN)
18042 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
18048 if (TARGET_DEBUG_BUILTIN)
18049 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
18050 (long unsigned) i);
18054 op[nopnds++] = (void_func) ? void_type_node : rettype;
18056 if (attr_args == RS6000_BTC_UNARY)
18057 op[nopnds++] = argtype;
18058 else if (attr_args == RS6000_BTC_BINARY)
18060 op[nopnds++] = argtype;
18061 op[nopnds++] = argtype;
18063 else if (attr_args == RS6000_BTC_TERNARY)
18065 op[nopnds++] = argtype;
18066 op[nopnds++] = argtype;
18067 op[nopnds++] = argtype;
18073 type = build_function_type_list (op[0], NULL_TREE);
18076 type = build_function_type_list (op[0], op[1], NULL_TREE);
18079 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
18082 type = build_function_type_list (op[0], op[1], op[2], op[3],
18086 gcc_unreachable ();
18089 def_builtin (d->name, type, d->code);
18093 /* Hash function for builtin functions with up to 3 arguments and a return
18096 builtin_hasher::hash (builtin_hash_struct *bh)
18101 for (i = 0; i < 4; i++)
18103 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
18104 ret = (ret * 2) + bh->uns_p[i];
18110 /* Compare builtin hash entries H1 and H2 for equivalence. */
18112 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
18114 return ((p1->mode[0] == p2->mode[0])
18115 && (p1->mode[1] == p2->mode[1])
18116 && (p1->mode[2] == p2->mode[2])
18117 && (p1->mode[3] == p2->mode[3])
18118 && (p1->uns_p[0] == p2->uns_p[0])
18119 && (p1->uns_p[1] == p2->uns_p[1])
18120 && (p1->uns_p[2] == p2->uns_p[2])
18121 && (p1->uns_p[3] == p2->uns_p[3]));
18124 /* Map types for builtin functions with an explicit return type and up to 3
18125 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18126 of the argument. */
18128 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
18129 machine_mode mode_arg1, machine_mode mode_arg2,
18130 enum rs6000_builtins builtin, const char *name)
18132 struct builtin_hash_struct h;
18133 struct builtin_hash_struct *h2;
18136 tree ret_type = NULL_TREE;
18137 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
18139 /* Create builtin_hash_table. */
18140 if (builtin_hash_table == NULL)
18141 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
18143 h.type = NULL_TREE;
18144 h.mode[0] = mode_ret;
18145 h.mode[1] = mode_arg0;
18146 h.mode[2] = mode_arg1;
18147 h.mode[3] = mode_arg2;
18153 /* If the builtin is a type that produces unsigned results or takes unsigned
18154 arguments, and it is returned as a decl for the vectorizer (such as
18155 widening multiplies, permute), make sure the arguments and return value
18156 are type correct. */
18159 /* unsigned 1 argument functions. */
18160 case CRYPTO_BUILTIN_VSBOX:
18161 case P8V_BUILTIN_VGBBD:
18162 case MISC_BUILTIN_CDTBCD:
18163 case MISC_BUILTIN_CBCDTD:
18168 /* unsigned 2 argument functions. */
18169 case ALTIVEC_BUILTIN_VMULEUB:
18170 case ALTIVEC_BUILTIN_VMULEUH:
18171 case ALTIVEC_BUILTIN_VMULEUW:
18172 case ALTIVEC_BUILTIN_VMULOUB:
18173 case ALTIVEC_BUILTIN_VMULOUH:
18174 case ALTIVEC_BUILTIN_VMULOUW:
18175 case CRYPTO_BUILTIN_VCIPHER:
18176 case CRYPTO_BUILTIN_VCIPHERLAST:
18177 case CRYPTO_BUILTIN_VNCIPHER:
18178 case CRYPTO_BUILTIN_VNCIPHERLAST:
18179 case CRYPTO_BUILTIN_VPMSUMB:
18180 case CRYPTO_BUILTIN_VPMSUMH:
18181 case CRYPTO_BUILTIN_VPMSUMW:
18182 case CRYPTO_BUILTIN_VPMSUMD:
18183 case CRYPTO_BUILTIN_VPMSUM:
18184 case MISC_BUILTIN_ADDG6S:
18185 case MISC_BUILTIN_DIVWEU:
18186 case MISC_BUILTIN_DIVWEUO:
18187 case MISC_BUILTIN_DIVDEU:
18188 case MISC_BUILTIN_DIVDEUO:
18189 case VSX_BUILTIN_UDIV_V2DI:
18190 case ALTIVEC_BUILTIN_VMAXUB:
18191 case ALTIVEC_BUILTIN_VMINUB:
18192 case ALTIVEC_BUILTIN_VMAXUH:
18193 case ALTIVEC_BUILTIN_VMINUH:
18194 case ALTIVEC_BUILTIN_VMAXUW:
18195 case ALTIVEC_BUILTIN_VMINUW:
18196 case P8V_BUILTIN_VMAXUD:
18197 case P8V_BUILTIN_VMINUD:
18203 /* unsigned 3 argument functions. */
18204 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
18205 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
18206 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
18207 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
18208 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
18209 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
18210 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
18211 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
18212 case VSX_BUILTIN_VPERM_16QI_UNS:
18213 case VSX_BUILTIN_VPERM_8HI_UNS:
18214 case VSX_BUILTIN_VPERM_4SI_UNS:
18215 case VSX_BUILTIN_VPERM_2DI_UNS:
18216 case VSX_BUILTIN_XXSEL_16QI_UNS:
18217 case VSX_BUILTIN_XXSEL_8HI_UNS:
18218 case VSX_BUILTIN_XXSEL_4SI_UNS:
18219 case VSX_BUILTIN_XXSEL_2DI_UNS:
18220 case CRYPTO_BUILTIN_VPERMXOR:
18221 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
18222 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
18223 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
18224 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
18225 case CRYPTO_BUILTIN_VSHASIGMAW:
18226 case CRYPTO_BUILTIN_VSHASIGMAD:
18227 case CRYPTO_BUILTIN_VSHASIGMA:
18234 /* signed permute functions with unsigned char mask. */
18235 case ALTIVEC_BUILTIN_VPERM_16QI:
18236 case ALTIVEC_BUILTIN_VPERM_8HI:
18237 case ALTIVEC_BUILTIN_VPERM_4SI:
18238 case ALTIVEC_BUILTIN_VPERM_4SF:
18239 case ALTIVEC_BUILTIN_VPERM_2DI:
18240 case ALTIVEC_BUILTIN_VPERM_2DF:
18241 case VSX_BUILTIN_VPERM_16QI:
18242 case VSX_BUILTIN_VPERM_8HI:
18243 case VSX_BUILTIN_VPERM_4SI:
18244 case VSX_BUILTIN_VPERM_4SF:
18245 case VSX_BUILTIN_VPERM_2DI:
18246 case VSX_BUILTIN_VPERM_2DF:
18250 /* unsigned args, signed return. */
18251 case VSX_BUILTIN_XVCVUXDSP:
18252 case VSX_BUILTIN_XVCVUXDDP_UNS:
18253 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
18257 /* signed args, unsigned return. */
18258 case VSX_BUILTIN_XVCVDPUXDS_UNS:
18259 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
18260 case MISC_BUILTIN_UNPACK_TD:
18261 case MISC_BUILTIN_UNPACK_V1TI:
18265 /* unsigned arguments for 128-bit pack instructions. */
18266 case MISC_BUILTIN_PACK_TD:
18267 case MISC_BUILTIN_PACK_V1TI:
18272 /* unsigned second arguments (vector shift right). */
18273 case ALTIVEC_BUILTIN_VSRB:
18274 case ALTIVEC_BUILTIN_VSRH:
18275 case ALTIVEC_BUILTIN_VSRW:
18276 case P8V_BUILTIN_VSRD:
18284 /* Figure out how many args are present. */
18285 while (num_args > 0 && h.mode[num_args] == VOIDmode)
18288 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
18289 if (!ret_type && h.uns_p[0])
18290 ret_type = builtin_mode_to_type[h.mode[0]][0];
18293 fatal_error (input_location,
18294 "internal error: builtin function %qs had an unexpected "
18295 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
18297 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
18298 arg_type[i] = NULL_TREE;
18300 for (i = 0; i < num_args; i++)
18302 int m = (int) h.mode[i+1];
18303 int uns_p = h.uns_p[i+1];
18305 arg_type[i] = builtin_mode_to_type[m][uns_p];
18306 if (!arg_type[i] && uns_p)
18307 arg_type[i] = builtin_mode_to_type[m][0];
18310 fatal_error (input_location,
18311 "internal error: builtin function %qs, argument %d "
18312 "had unexpected argument type %qs", name, i,
18313 GET_MODE_NAME (m));
18316 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
18317 if (*found == NULL)
18319 h2 = ggc_alloc<builtin_hash_struct> ();
18323 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
18324 arg_type[2], NULL_TREE);
18327 return (*found)->type;
18331 rs6000_common_init_builtins (void)
18333 const struct builtin_description *d;
18336 tree opaque_ftype_opaque = NULL_TREE;
18337 tree opaque_ftype_opaque_opaque = NULL_TREE;
18338 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
18339 tree v2si_ftype = NULL_TREE;
18340 tree v2si_ftype_qi = NULL_TREE;
18341 tree v2si_ftype_v2si_qi = NULL_TREE;
18342 tree v2si_ftype_int_qi = NULL_TREE;
18343 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18345 if (!TARGET_PAIRED_FLOAT)
18347 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
18348 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
18351 /* Paired builtins are only available if you build a compiler with the
18352 appropriate options, so only create those builtins with the appropriate
18353 compiler option. Create Altivec and VSX builtins on machines with at
18354 least the general purpose extensions (970 and newer) to allow the use of
18355 the target attribute.. */
18357 if (TARGET_EXTRA_BUILTINS)
18358 builtin_mask |= RS6000_BTM_COMMON;
18360 /* Add the ternary operators. */
18362 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
18365 HOST_WIDE_INT mask = d->mask;
18367 if ((mask & builtin_mask) != mask)
18369 if (TARGET_DEBUG_BUILTIN)
18370 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
18374 if (rs6000_overloaded_builtin_p (d->code))
18376 if (! (type = opaque_ftype_opaque_opaque_opaque))
18377 type = opaque_ftype_opaque_opaque_opaque
18378 = build_function_type_list (opaque_V4SI_type_node,
18379 opaque_V4SI_type_node,
18380 opaque_V4SI_type_node,
18381 opaque_V4SI_type_node,
18386 enum insn_code icode = d->icode;
18389 if (TARGET_DEBUG_BUILTIN)
18390 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18396 if (icode == CODE_FOR_nothing)
18398 if (TARGET_DEBUG_BUILTIN)
18399 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
18405 type = builtin_function_type (insn_data[icode].operand[0].mode,
18406 insn_data[icode].operand[1].mode,
18407 insn_data[icode].operand[2].mode,
18408 insn_data[icode].operand[3].mode,
18412 def_builtin (d->name, type, d->code);
18415 /* Add the binary operators. */
18417 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
18419 machine_mode mode0, mode1, mode2;
18421 HOST_WIDE_INT mask = d->mask;
18423 if ((mask & builtin_mask) != mask)
18425 if (TARGET_DEBUG_BUILTIN)
18426 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
18430 if (rs6000_overloaded_builtin_p (d->code))
18432 if (! (type = opaque_ftype_opaque_opaque))
18433 type = opaque_ftype_opaque_opaque
18434 = build_function_type_list (opaque_V4SI_type_node,
18435 opaque_V4SI_type_node,
18436 opaque_V4SI_type_node,
18441 enum insn_code icode = d->icode;
18444 if (TARGET_DEBUG_BUILTIN)
18445 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18451 if (icode == CODE_FOR_nothing)
18453 if (TARGET_DEBUG_BUILTIN)
18454 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
18460 mode0 = insn_data[icode].operand[0].mode;
18461 mode1 = insn_data[icode].operand[1].mode;
18462 mode2 = insn_data[icode].operand[2].mode;
18464 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
18466 if (! (type = v2si_ftype_v2si_qi))
18467 type = v2si_ftype_v2si_qi
18468 = build_function_type_list (opaque_V2SI_type_node,
18469 opaque_V2SI_type_node,
18474 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
18475 && mode2 == QImode)
18477 if (! (type = v2si_ftype_int_qi))
18478 type = v2si_ftype_int_qi
18479 = build_function_type_list (opaque_V2SI_type_node,
18486 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
18490 def_builtin (d->name, type, d->code);
18493 /* Add the simple unary operators. */
18495 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
18497 machine_mode mode0, mode1;
18499 HOST_WIDE_INT mask = d->mask;
18501 if ((mask & builtin_mask) != mask)
18503 if (TARGET_DEBUG_BUILTIN)
18504 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
18508 if (rs6000_overloaded_builtin_p (d->code))
18510 if (! (type = opaque_ftype_opaque))
18511 type = opaque_ftype_opaque
18512 = build_function_type_list (opaque_V4SI_type_node,
18513 opaque_V4SI_type_node,
18518 enum insn_code icode = d->icode;
18521 if (TARGET_DEBUG_BUILTIN)
18522 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18528 if (icode == CODE_FOR_nothing)
18530 if (TARGET_DEBUG_BUILTIN)
18531 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
18537 mode0 = insn_data[icode].operand[0].mode;
18538 mode1 = insn_data[icode].operand[1].mode;
18540 if (mode0 == V2SImode && mode1 == QImode)
18542 if (! (type = v2si_ftype_qi))
18543 type = v2si_ftype_qi
18544 = build_function_type_list (opaque_V2SI_type_node,
18550 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
18554 def_builtin (d->name, type, d->code);
18557 /* Add the simple no-argument operators. */
18559 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
18561 machine_mode mode0;
18563 HOST_WIDE_INT mask = d->mask;
18565 if ((mask & builtin_mask) != mask)
18567 if (TARGET_DEBUG_BUILTIN)
18568 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
18571 if (rs6000_overloaded_builtin_p (d->code))
18573 if (!opaque_ftype_opaque)
18574 opaque_ftype_opaque
18575 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
18576 type = opaque_ftype_opaque;
18580 enum insn_code icode = d->icode;
18583 if (TARGET_DEBUG_BUILTIN)
18584 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18585 (long unsigned) i);
18588 if (icode == CODE_FOR_nothing)
18590 if (TARGET_DEBUG_BUILTIN)
18592 "rs6000_builtin, skip no-argument %s (no code)\n",
18596 mode0 = insn_data[icode].operand[0].mode;
18597 if (mode0 == V2SImode)
18599 /* code for paired single */
18600 if (! (type = v2si_ftype))
18603 = build_function_type_list (opaque_V2SI_type_node,
18609 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
18612 def_builtin (d->name, type, d->code);
18616 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18618 init_float128_ibm (machine_mode mode)
18620 if (!TARGET_XL_COMPAT)
18622 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
18623 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
18624 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
18625 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
18627 if (!TARGET_HARD_FLOAT)
18629 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
18630 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
18631 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
18632 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
18633 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
18634 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
18635 set_optab_libfunc (le_optab, mode, "__gcc_qle");
18636 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
18638 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
18639 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
18640 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
18641 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
18642 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
18643 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
18644 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
18645 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
18650 set_optab_libfunc (add_optab, mode, "_xlqadd");
18651 set_optab_libfunc (sub_optab, mode, "_xlqsub");
18652 set_optab_libfunc (smul_optab, mode, "_xlqmul");
18653 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
18656 /* Add various conversions for IFmode to use the traditional TFmode
18658 if (mode == IFmode)
18660 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
18661 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
18662 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
18663 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
18664 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
18665 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
18667 if (TARGET_POWERPC64)
18669 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
18670 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
18671 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
18672 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
18677 /* Set up IEEE 128-bit floating point routines. Use different names if the
18678 arguments can be passed in a vector register. The historical PowerPC
18679 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18680 continue to use that if we aren't using vector registers to pass IEEE
18681 128-bit floating point. */
18684 init_float128_ieee (machine_mode mode)
18686 if (FLOAT128_VECTOR_P (mode))
18688 set_optab_libfunc (add_optab, mode, "__addkf3");
18689 set_optab_libfunc (sub_optab, mode, "__subkf3");
18690 set_optab_libfunc (neg_optab, mode, "__negkf2");
18691 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18692 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18693 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18694 set_optab_libfunc (abs_optab, mode, "__abstkf2");
18696 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18697 set_optab_libfunc (ne_optab, mode, "__nekf2");
18698 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18699 set_optab_libfunc (ge_optab, mode, "__gekf2");
18700 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18701 set_optab_libfunc (le_optab, mode, "__lekf2");
18702 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18704 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18705 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18706 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18707 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18709 set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
18710 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18711 set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
18713 set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
18714 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18715 set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
18717 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
18718 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
18719 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
18720 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
18721 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
18722 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
18724 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18725 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18726 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18727 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18729 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18730 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18731 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18732 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18734 if (TARGET_POWERPC64)
18736 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18737 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18738 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18739 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18745 set_optab_libfunc (add_optab, mode, "_q_add");
18746 set_optab_libfunc (sub_optab, mode, "_q_sub");
18747 set_optab_libfunc (neg_optab, mode, "_q_neg");
18748 set_optab_libfunc (smul_optab, mode, "_q_mul");
18749 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18750 if (TARGET_PPC_GPOPT)
18751 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18753 set_optab_libfunc (eq_optab, mode, "_q_feq");
18754 set_optab_libfunc (ne_optab, mode, "_q_fne");
18755 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18756 set_optab_libfunc (ge_optab, mode, "_q_fge");
18757 set_optab_libfunc (lt_optab, mode, "_q_flt");
18758 set_optab_libfunc (le_optab, mode, "_q_fle");
18760 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18761 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18762 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18763 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18764 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18765 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18766 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18767 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18772 rs6000_init_libfuncs (void)
18774 /* __float128 support. */
18775 if (TARGET_FLOAT128_TYPE)
18777 init_float128_ibm (IFmode);
18778 init_float128_ieee (KFmode);
18781 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18782 if (TARGET_LONG_DOUBLE_128)
18784 if (!TARGET_IEEEQUAD)
18785 init_float128_ibm (TFmode);
18787 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18789 init_float128_ieee (TFmode);
18793 /* Emit a potentially record-form instruction, setting DST from SRC.
18794 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18795 signed comparison of DST with zero. If DOT is 1, the generated RTL
18796 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18797 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18798 a separate COMPARE. */
18801 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18805 emit_move_insn (dst, src);
18809 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18811 emit_move_insn (dst, src);
18812 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18816 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18819 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18820 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18824 rtx set = gen_rtx_SET (dst, src);
18825 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18830 /* A validation routine: say whether CODE, a condition code, and MODE
18831 match. The other alternatives either don't make sense or should
18832 never be generated. */
18835 validate_condition_mode (enum rtx_code code, machine_mode mode)
18837 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18838 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18839 && GET_MODE_CLASS (mode) == MODE_CC);
18841 /* These don't make sense. */
18842 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18843 || mode != CCUNSmode);
18845 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18846 || mode == CCUNSmode);
18848 gcc_assert (mode == CCFPmode
18849 || (code != ORDERED && code != UNORDERED
18850 && code != UNEQ && code != LTGT
18851 && code != UNGT && code != UNLT
18852 && code != UNGE && code != UNLE));
18854 /* These should never be generated except for
18855 flag_finite_math_only. */
18856 gcc_assert (mode != CCFPmode
18857 || flag_finite_math_only
18858 || (code != LE && code != GE
18859 && code != UNEQ && code != LTGT
18860 && code != UNGT && code != UNLT));
18862 /* These are invalid; the information is not there. */
18863 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18867 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18868 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18869 not zero, store there the bit offset (counted from the right) where
18870 the single stretch of 1 bits begins; and similarly for B, the bit
18871 offset where it ends. */
18874 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18876 unsigned HOST_WIDE_INT val = INTVAL (mask);
18877 unsigned HOST_WIDE_INT bit;
18879 int n = GET_MODE_PRECISION (mode);
18881 if (mode != DImode && mode != SImode)
18884 if (INTVAL (mask) >= 0)
18887 ne = exact_log2 (bit);
18888 nb = exact_log2 (val + bit);
18890 else if (val + 1 == 0)
18899 nb = exact_log2 (bit);
18900 ne = exact_log2 (val + bit);
18905 ne = exact_log2 (bit);
18906 if (val + bit == 0)
18914 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18925 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18926 or rldicr instruction, to implement an AND with it in mode MODE. */
18929 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18933 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18936 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18938 if (mode == DImode)
18939 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18941 /* For SImode, rlwinm can do everything. */
18942 if (mode == SImode)
18943 return (nb < 32 && ne < 32);
18948 /* Return the instruction template for an AND with mask in mode MODE, with
18949 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18952 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18956 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18957 gcc_unreachable ();
18959 if (mode == DImode && ne == 0)
18961 operands[3] = GEN_INT (63 - nb);
18963 return "rldicl. %0,%1,0,%3";
18964 return "rldicl %0,%1,0,%3";
18967 if (mode == DImode && nb == 63)
18969 operands[3] = GEN_INT (63 - ne);
18971 return "rldicr. %0,%1,0,%3";
18972 return "rldicr %0,%1,0,%3";
18975 if (nb < 32 && ne < 32)
18977 operands[3] = GEN_INT (31 - nb);
18978 operands[4] = GEN_INT (31 - ne);
18980 return "rlwinm. %0,%1,0,%3,%4";
18981 return "rlwinm %0,%1,0,%3,%4";
18984 gcc_unreachable ();
18987 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18988 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18989 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18992 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18996 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18999 int n = GET_MODE_PRECISION (mode);
19002 if (CONST_INT_P (XEXP (shift, 1)))
19004 sh = INTVAL (XEXP (shift, 1));
19005 if (sh < 0 || sh >= n)
19009 rtx_code code = GET_CODE (shift);
19011 /* Convert any shift by 0 to a rotate, to simplify below code. */
19015 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19016 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19018 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19024 /* DImode rotates need rld*. */
19025 if (mode == DImode && code == ROTATE)
19026 return (nb == 63 || ne == 0 || ne == sh);
19028 /* SImode rotates need rlw*. */
19029 if (mode == SImode && code == ROTATE)
19030 return (nb < 32 && ne < 32 && sh < 32);
19032 /* Wrap-around masks are only okay for rotates. */
19036 /* Variable shifts are only okay for rotates. */
19040 /* Don't allow ASHIFT if the mask is wrong for that. */
19041 if (code == ASHIFT && ne < sh)
19044 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
19045 if the mask is wrong for that. */
19046 if (nb < 32 && ne < 32 && sh < 32
19047 && !(code == LSHIFTRT && nb >= 32 - sh))
19050 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
19051 if the mask is wrong for that. */
19052 if (code == LSHIFTRT)
19054 if (nb == 63 || ne == 0 || ne == sh)
19055 return !(code == LSHIFTRT && nb >= sh);
19060 /* Return the instruction template for a shift with mask in mode MODE, with
19061 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19064 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
19068 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19069 gcc_unreachable ();
19071 if (mode == DImode && ne == 0)
19073 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19074 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
19075 operands[3] = GEN_INT (63 - nb);
19077 return "rld%I2cl. %0,%1,%2,%3";
19078 return "rld%I2cl %0,%1,%2,%3";
19081 if (mode == DImode && nb == 63)
19083 operands[3] = GEN_INT (63 - ne);
19085 return "rld%I2cr. %0,%1,%2,%3";
19086 return "rld%I2cr %0,%1,%2,%3";
19090 && GET_CODE (operands[4]) != LSHIFTRT
19091 && CONST_INT_P (operands[2])
19092 && ne == INTVAL (operands[2]))
19094 operands[3] = GEN_INT (63 - nb);
19096 return "rld%I2c. %0,%1,%2,%3";
19097 return "rld%I2c %0,%1,%2,%3";
19100 if (nb < 32 && ne < 32)
19102 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19103 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19104 operands[3] = GEN_INT (31 - nb);
19105 operands[4] = GEN_INT (31 - ne);
19106 /* This insn can also be a 64-bit rotate with mask that really makes
19107 it just a shift right (with mask); the %h below are to adjust for
19108 that situation (shift count is >= 32 in that case). */
19110 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19111 return "rlw%I2nm %0,%1,%h2,%3,%4";
19114 gcc_unreachable ();
19117 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19118 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19119 ASHIFT, or LSHIFTRT) in mode MODE. */
19122 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
19126 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19129 int n = GET_MODE_PRECISION (mode);
19131 int sh = INTVAL (XEXP (shift, 1));
19132 if (sh < 0 || sh >= n)
19135 rtx_code code = GET_CODE (shift);
19137 /* Convert any shift by 0 to a rotate, to simplify below code. */
19141 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19142 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19144 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19150 /* DImode rotates need rldimi. */
19151 if (mode == DImode && code == ROTATE)
19154 /* SImode rotates need rlwimi. */
19155 if (mode == SImode && code == ROTATE)
19156 return (nb < 32 && ne < 32 && sh < 32);
19158 /* Wrap-around masks are only okay for rotates. */
19162 /* Don't allow ASHIFT if the mask is wrong for that. */
19163 if (code == ASHIFT && ne < sh)
19166 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19167 if the mask is wrong for that. */
19168 if (nb < 32 && ne < 32 && sh < 32
19169 && !(code == LSHIFTRT && nb >= 32 - sh))
19172 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19173 if the mask is wrong for that. */
19174 if (code == LSHIFTRT)
19177 return !(code == LSHIFTRT && nb >= sh);
19182 /* Return the instruction template for an insert with mask in mode MODE, with
19183 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19186 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
19190 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19191 gcc_unreachable ();
19193 /* Prefer rldimi because rlwimi is cracked. */
19194 if (TARGET_POWERPC64
19195 && (!dot || mode == DImode)
19196 && GET_CODE (operands[4]) != LSHIFTRT
19197 && ne == INTVAL (operands[2]))
19199 operands[3] = GEN_INT (63 - nb);
19201 return "rldimi. %0,%1,%2,%3";
19202 return "rldimi %0,%1,%2,%3";
19205 if (nb < 32 && ne < 32)
19207 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19208 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19209 operands[3] = GEN_INT (31 - nb);
19210 operands[4] = GEN_INT (31 - ne);
19212 return "rlwimi. %0,%1,%2,%3,%4";
19213 return "rlwimi %0,%1,%2,%3,%4";
19216 gcc_unreachable ();
19219 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19220 using two machine instructions. */
19223 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
19225 /* There are two kinds of AND we can handle with two insns:
19226 1) those we can do with two rl* insn;
19229 We do not handle that last case yet. */
19231 /* If there is just one stretch of ones, we can do it. */
19232 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
19235 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19236 one insn, we can do the whole thing with two. */
19237 unsigned HOST_WIDE_INT val = INTVAL (c);
19238 unsigned HOST_WIDE_INT bit1 = val & -val;
19239 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19240 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19241 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19242 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
19245 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19246 If EXPAND is true, split rotate-and-mask instructions we generate to
19247 their constituent parts as well (this is used during expand); if DOT
19248 is 1, make the last insn a record-form instruction clobbering the
19249 destination GPR and setting the CC reg (from operands[3]); if 2, set
19250 that GPR as well as the CC reg. */
19253 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
19255 gcc_assert (!(expand && dot));
19257 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
19259 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19260 shift right. This generates better code than doing the masks without
19261 shifts, or shifting first right and then left. */
19263 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
19265 gcc_assert (mode == DImode);
19267 int shift = 63 - nb;
19270 rtx tmp1 = gen_reg_rtx (DImode);
19271 rtx tmp2 = gen_reg_rtx (DImode);
19272 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
19273 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
19274 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
19278 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
19279 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
19280 emit_move_insn (operands[0], tmp);
19281 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
19282 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19287 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19288 that does the rest. */
19289 unsigned HOST_WIDE_INT bit1 = val & -val;
19290 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19291 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19292 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19294 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
19295 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
19297 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
19299 /* Two "no-rotate"-and-mask instructions, for SImode. */
19300 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
19302 gcc_assert (mode == SImode);
19304 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19305 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
19306 emit_move_insn (reg, tmp);
19307 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19308 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19312 gcc_assert (mode == DImode);
19314 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19315 insns; we have to do the first in SImode, because it wraps. */
19316 if (mask2 <= 0xffffffff
19317 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
19319 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19320 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
19322 rtx reg_low = gen_lowpart (SImode, reg);
19323 emit_move_insn (reg_low, tmp);
19324 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19325 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19329 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19330 at the top end), rotate back and clear the other hole. */
19331 int right = exact_log2 (bit3);
19332 int left = 64 - right;
19334 /* Rotate the mask too. */
19335 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
19339 rtx tmp1 = gen_reg_rtx (DImode);
19340 rtx tmp2 = gen_reg_rtx (DImode);
19341 rtx tmp3 = gen_reg_rtx (DImode);
19342 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
19343 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
19344 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
19345 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
19349 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
19350 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
19351 emit_move_insn (operands[0], tmp);
19352 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
19353 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
19354 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19358 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19359 for lfq and stfq insns iff the registers are hard registers. */
19362 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
19364 /* We might have been passed a SUBREG. */
19365 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
19368 /* We might have been passed non floating point registers. */
19369 if (!FP_REGNO_P (REGNO (reg1))
19370 || !FP_REGNO_P (REGNO (reg2)))
19373 return (REGNO (reg1) == REGNO (reg2) - 1);
19376 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19377 addr1 and addr2 must be in consecutive memory locations
19378 (addr2 == addr1 + 8). */
19381 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
19384 unsigned int reg1, reg2;
19385 int offset1, offset2;
19387 /* The mems cannot be volatile. */
19388 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
19391 addr1 = XEXP (mem1, 0);
19392 addr2 = XEXP (mem2, 0);
19394 /* Extract an offset (if used) from the first addr. */
19395 if (GET_CODE (addr1) == PLUS)
19397 /* If not a REG, return zero. */
19398 if (GET_CODE (XEXP (addr1, 0)) != REG)
19402 reg1 = REGNO (XEXP (addr1, 0));
19403 /* The offset must be constant! */
19404 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
19406 offset1 = INTVAL (XEXP (addr1, 1));
19409 else if (GET_CODE (addr1) != REG)
19413 reg1 = REGNO (addr1);
19414 /* This was a simple (mem (reg)) expression. Offset is 0. */
19418 /* And now for the second addr. */
19419 if (GET_CODE (addr2) == PLUS)
19421 /* If not a REG, return zero. */
19422 if (GET_CODE (XEXP (addr2, 0)) != REG)
19426 reg2 = REGNO (XEXP (addr2, 0));
19427 /* The offset must be constant. */
19428 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
19430 offset2 = INTVAL (XEXP (addr2, 1));
19433 else if (GET_CODE (addr2) != REG)
19437 reg2 = REGNO (addr2);
19438 /* This was a simple (mem (reg)) expression. Offset is 0. */
19442 /* Both of these must have the same base register. */
19446 /* The offset for the second addr must be 8 more than the first addr. */
19447 if (offset2 != offset1 + 8)
19450 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19455 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19456 need to use DDmode, in all other cases we can use the same mode. */
19457 static machine_mode
19458 rs6000_secondary_memory_needed_mode (machine_mode mode)
19460 if (lra_in_progress && mode == SDmode)
19465 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19466 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19467 only work on the traditional altivec registers, note if an altivec register
19470 static enum rs6000_reg_type
19471 register_to_reg_type (rtx reg, bool *is_altivec)
19473 HOST_WIDE_INT regno;
19474 enum reg_class rclass;
19476 if (GET_CODE (reg) == SUBREG)
19477 reg = SUBREG_REG (reg);
19480 return NO_REG_TYPE;
19482 regno = REGNO (reg);
19483 if (regno >= FIRST_PSEUDO_REGISTER)
19485 if (!lra_in_progress && !reload_completed)
19486 return PSEUDO_REG_TYPE;
19488 regno = true_regnum (reg);
19489 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
19490 return PSEUDO_REG_TYPE;
19493 gcc_assert (regno >= 0);
19495 if (is_altivec && ALTIVEC_REGNO_P (regno))
19496 *is_altivec = true;
19498 rclass = rs6000_regno_regclass[regno];
19499 return reg_class_to_reg_type[(int)rclass];
19502 /* Helper function to return the cost of adding a TOC entry address. */
19505 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
19509 if (TARGET_CMODEL != CMODEL_SMALL)
19510 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
19513 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
19518 /* Helper function for rs6000_secondary_reload to determine whether the memory
19519 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19520 needs reloading. Return negative if the memory is not handled by the memory
19521 helper functions and to try a different reload method, 0 if no additional
19522 instructions are need, and positive to give the extra cost for the
19526 rs6000_secondary_reload_memory (rtx addr,
19527 enum reg_class rclass,
19530 int extra_cost = 0;
19531 rtx reg, and_arg, plus_arg0, plus_arg1;
19532 addr_mask_type addr_mask;
19533 const char *type = NULL;
19534 const char *fail_msg = NULL;
19536 if (GPR_REG_CLASS_P (rclass))
19537 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19539 else if (rclass == FLOAT_REGS)
19540 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19542 else if (rclass == ALTIVEC_REGS)
19543 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19545 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19546 else if (rclass == VSX_REGS)
19547 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
19548 & ~RELOAD_REG_AND_M16);
19550 /* If the register allocator hasn't made up its mind yet on the register
19551 class to use, settle on defaults to use. */
19552 else if (rclass == NO_REGS)
19554 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
19555 & ~RELOAD_REG_AND_M16);
19557 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
19558 addr_mask &= ~(RELOAD_REG_INDEXED
19559 | RELOAD_REG_PRE_INCDEC
19560 | RELOAD_REG_PRE_MODIFY);
19566 /* If the register isn't valid in this register class, just return now. */
19567 if ((addr_mask & RELOAD_REG_VALID) == 0)
19569 if (TARGET_DEBUG_ADDR)
19572 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19573 "not valid in class\n",
19574 GET_MODE_NAME (mode), reg_class_names[rclass]);
19581 switch (GET_CODE (addr))
19583 /* Does the register class supports auto update forms for this mode? We
19584 don't need a scratch register, since the powerpc only supports
19585 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19588 reg = XEXP (addr, 0);
19589 if (!base_reg_operand (addr, GET_MODE (reg)))
19591 fail_msg = "no base register #1";
19595 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19603 reg = XEXP (addr, 0);
19604 plus_arg1 = XEXP (addr, 1);
19605 if (!base_reg_operand (reg, GET_MODE (reg))
19606 || GET_CODE (plus_arg1) != PLUS
19607 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
19609 fail_msg = "bad PRE_MODIFY";
19613 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19620 /* Do we need to simulate AND -16 to clear the bottom address bits used
19621 in VMX load/stores? Only allow the AND for vector sizes. */
19623 and_arg = XEXP (addr, 0);
19624 if (GET_MODE_SIZE (mode) != 16
19625 || GET_CODE (XEXP (addr, 1)) != CONST_INT
19626 || INTVAL (XEXP (addr, 1)) != -16)
19628 fail_msg = "bad Altivec AND #1";
19632 if (rclass != ALTIVEC_REGS)
19634 if (legitimate_indirect_address_p (and_arg, false))
19637 else if (legitimate_indexed_address_p (and_arg, false))
19642 fail_msg = "bad Altivec AND #2";
19650 /* If this is an indirect address, make sure it is a base register. */
19653 if (!legitimate_indirect_address_p (addr, false))
19660 /* If this is an indexed address, make sure the register class can handle
19661 indexed addresses for this mode. */
19663 plus_arg0 = XEXP (addr, 0);
19664 plus_arg1 = XEXP (addr, 1);
19666 /* (plus (plus (reg) (constant)) (constant)) is generated during
19667 push_reload processing, so handle it now. */
19668 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19670 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19677 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19678 push_reload processing, so handle it now. */
19679 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19681 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19684 type = "indexed #2";
19688 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19690 fail_msg = "no base register #2";
19694 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19696 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19697 || !legitimate_indexed_address_p (addr, false))
19704 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19705 && CONST_INT_P (plus_arg1))
19707 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19710 type = "vector d-form offset";
19714 /* Make sure the register class can handle offset addresses. */
19715 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19717 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19720 type = "offset #2";
19726 fail_msg = "bad PLUS";
19733 /* Quad offsets are restricted and can't handle normal addresses. */
19734 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19737 type = "vector d-form lo_sum";
19740 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19742 fail_msg = "bad LO_SUM";
19746 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19753 /* Static addresses need to create a TOC entry. */
19757 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19760 type = "vector d-form lo_sum #2";
19766 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19770 /* TOC references look like offsetable memory. */
19772 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19774 fail_msg = "bad UNSPEC";
19778 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19781 type = "vector d-form lo_sum #3";
19784 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19787 type = "toc reference";
19793 fail_msg = "bad address";
19798 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19800 if (extra_cost < 0)
19802 "rs6000_secondary_reload_memory error: mode = %s, "
19803 "class = %s, addr_mask = '%s', %s\n",
19804 GET_MODE_NAME (mode),
19805 reg_class_names[rclass],
19806 rs6000_debug_addr_mask (addr_mask, false),
19807 (fail_msg != NULL) ? fail_msg : "<bad address>");
19811 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19812 "addr_mask = '%s', extra cost = %d, %s\n",
19813 GET_MODE_NAME (mode),
19814 reg_class_names[rclass],
19815 rs6000_debug_addr_mask (addr_mask, false),
19817 (type) ? type : "<none>");
19825 /* Helper function for rs6000_secondary_reload to return true if a move to a
19826 different register classe is really a simple move. */
19829 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19830 enum rs6000_reg_type from_type,
19833 int size = GET_MODE_SIZE (mode);
19835 /* Add support for various direct moves available. In this function, we only
19836 look at cases where we don't need any extra registers, and one or more
19837 simple move insns are issued. Originally small integers are not allowed
19838 in FPR/VSX registers. Single precision binary floating is not a simple
19839 move because we need to convert to the single precision memory layout.
19840 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19841 need special direct move handling, which we do not support yet. */
19842 if (TARGET_DIRECT_MOVE
19843 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19844 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19846 if (TARGET_POWERPC64)
19848 /* ISA 2.07: MTVSRD or MVFVSRD. */
19852 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19853 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19857 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19858 if (TARGET_P8_VECTOR)
19860 if (mode == SImode)
19863 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19867 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19868 if (mode == SDmode)
19872 /* Power6+: MFTGPR or MFFGPR. */
19873 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19874 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19875 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19878 /* Move to/from SPR. */
19879 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19880 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19881 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19887 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19888 special direct moves that involve allocating an extra register, return the
19889 insn code of the helper function if there is such a function or
19890 CODE_FOR_nothing if not. */
19893 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19894 enum rs6000_reg_type from_type,
19896 secondary_reload_info *sri,
19900 enum insn_code icode = CODE_FOR_nothing;
19902 int size = GET_MODE_SIZE (mode);
19904 if (TARGET_POWERPC64 && size == 16)
19906 /* Handle moving 128-bit values from GPRs to VSX point registers on
19907 ISA 2.07 (power8, power9) when running in 64-bit mode using
19908 XXPERMDI to glue the two 64-bit values back together. */
19909 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19911 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19912 icode = reg_addr[mode].reload_vsx_gpr;
19915 /* Handle moving 128-bit values from VSX point registers to GPRs on
19916 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19917 bottom 64-bit value. */
19918 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19920 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19921 icode = reg_addr[mode].reload_gpr_vsx;
19925 else if (TARGET_POWERPC64 && mode == SFmode)
19927 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19929 cost = 3; /* xscvdpspn, mfvsrd, and. */
19930 icode = reg_addr[mode].reload_gpr_vsx;
19933 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19935 cost = 2; /* mtvsrz, xscvspdpn. */
19936 icode = reg_addr[mode].reload_vsx_gpr;
19940 else if (!TARGET_POWERPC64 && size == 8)
19942 /* Handle moving 64-bit values from GPRs to floating point registers on
19943 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19944 32-bit values back together. Altivec register classes must be handled
19945 specially since a different instruction is used, and the secondary
19946 reload support requires a single instruction class in the scratch
19947 register constraint. However, right now TFmode is not allowed in
19948 Altivec registers, so the pattern will never match. */
19949 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19951 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19952 icode = reg_addr[mode].reload_fpr_gpr;
19956 if (icode != CODE_FOR_nothing)
19961 sri->icode = icode;
19962 sri->extra_cost = cost;
19969 /* Return whether a move between two register classes can be done either
19970 directly (simple move) or via a pattern that uses a single extra temporary
19971 (using ISA 2.07's direct move in this case. */
19974 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19975 enum rs6000_reg_type from_type,
19977 secondary_reload_info *sri,
19980 /* Fall back to load/store reloads if either type is not a register. */
19981 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19984 /* If we haven't allocated registers yet, assume the move can be done for the
19985 standard register types. */
19986 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19987 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19988 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19991 /* Moves to the same set of registers is a simple move for non-specialized
19993 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19996 /* Check whether a simple move can be done directly. */
19997 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
20001 sri->icode = CODE_FOR_nothing;
20002 sri->extra_cost = 0;
20007 /* Now check if we can do it in a few steps. */
20008 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
20012 /* Inform reload about cases where moving X with a mode MODE to a register in
20013 RCLASS requires an extra scratch or immediate register. Return the class
20014 needed for the immediate register.
20016 For VSX and Altivec, we may need a register to convert sp+offset into
20019 For misaligned 64-bit gpr loads and stores we need a register to
20020 convert an offset address to indirect. */
20023 rs6000_secondary_reload (bool in_p,
20025 reg_class_t rclass_i,
20027 secondary_reload_info *sri)
20029 enum reg_class rclass = (enum reg_class) rclass_i;
20030 reg_class_t ret = ALL_REGS;
20031 enum insn_code icode;
20032 bool default_p = false;
20033 bool done_p = false;
20035 /* Allow subreg of memory before/during reload. */
20036 bool memory_p = (MEM_P (x)
20037 || (!reload_completed && GET_CODE (x) == SUBREG
20038 && MEM_P (SUBREG_REG (x))));
20040 sri->icode = CODE_FOR_nothing;
20041 sri->t_icode = CODE_FOR_nothing;
20042 sri->extra_cost = 0;
20044 ? reg_addr[mode].reload_load
20045 : reg_addr[mode].reload_store);
20047 if (REG_P (x) || register_operand (x, mode))
20049 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
20050 bool altivec_p = (rclass == ALTIVEC_REGS);
20051 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
20054 std::swap (to_type, from_type);
20056 /* Can we do a direct move of some sort? */
20057 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
20060 icode = (enum insn_code)sri->icode;
20067 /* Make sure 0.0 is not reloaded or forced into memory. */
20068 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
20075 /* If this is a scalar floating point value and we want to load it into the
20076 traditional Altivec registers, do it via a move via a traditional floating
20077 point register, unless we have D-form addressing. Also make sure that
20078 non-zero constants use a FPR. */
20079 if (!done_p && reg_addr[mode].scalar_in_vmx_p
20080 && !mode_supports_vmx_dform (mode)
20081 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20082 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
20089 /* Handle reload of load/stores if we have reload helper functions. */
20090 if (!done_p && icode != CODE_FOR_nothing && memory_p)
20092 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
20095 if (extra_cost >= 0)
20099 if (extra_cost > 0)
20101 sri->extra_cost = extra_cost;
20102 sri->icode = icode;
20107 /* Handle unaligned loads and stores of integer registers. */
20108 if (!done_p && TARGET_POWERPC64
20109 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20111 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
20113 rtx addr = XEXP (x, 0);
20114 rtx off = address_offset (addr);
20116 if (off != NULL_RTX)
20118 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20119 unsigned HOST_WIDE_INT offset = INTVAL (off);
20121 /* We need a secondary reload when our legitimate_address_p
20122 says the address is good (as otherwise the entire address
20123 will be reloaded), and the offset is not a multiple of
20124 four or we have an address wrap. Address wrap will only
20125 occur for LO_SUMs since legitimate_offset_address_p
20126 rejects addresses for 16-byte mems that will wrap. */
20127 if (GET_CODE (addr) == LO_SUM
20128 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20129 && ((offset & 3) != 0
20130 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
20131 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
20132 && (offset & 3) != 0))
20134 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20136 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
20137 : CODE_FOR_reload_di_load);
20139 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
20140 : CODE_FOR_reload_di_store);
20141 sri->extra_cost = 2;
20152 if (!done_p && !TARGET_POWERPC64
20153 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20155 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
20157 rtx addr = XEXP (x, 0);
20158 rtx off = address_offset (addr);
20160 if (off != NULL_RTX)
20162 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20163 unsigned HOST_WIDE_INT offset = INTVAL (off);
20165 /* We need a secondary reload when our legitimate_address_p
20166 says the address is good (as otherwise the entire address
20167 will be reloaded), and we have a wrap.
20169 legitimate_lo_sum_address_p allows LO_SUM addresses to
20170 have any offset so test for wrap in the low 16 bits.
20172 legitimate_offset_address_p checks for the range
20173 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20174 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20175 [0x7ff4,0x7fff] respectively, so test for the
20176 intersection of these ranges, [0x7ffc,0x7fff] and
20177 [0x7ff4,0x7ff7] respectively.
20179 Note that the address we see here may have been
20180 manipulated by legitimize_reload_address. */
20181 if (GET_CODE (addr) == LO_SUM
20182 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
20183 : offset - (0x8000 - extra) < UNITS_PER_WORD)
20186 sri->icode = CODE_FOR_reload_si_load;
20188 sri->icode = CODE_FOR_reload_si_store;
20189 sri->extra_cost = 2;
20204 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
20206 gcc_assert (ret != ALL_REGS);
20208 if (TARGET_DEBUG_ADDR)
20211 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20213 reg_class_names[ret],
20214 in_p ? "true" : "false",
20215 reg_class_names[rclass],
20216 GET_MODE_NAME (mode));
20218 if (reload_completed)
20219 fputs (", after reload", stderr);
20222 fputs (", done_p not set", stderr);
20225 fputs (", default secondary reload", stderr);
20227 if (sri->icode != CODE_FOR_nothing)
20228 fprintf (stderr, ", reload func = %s, extra cost = %d",
20229 insn_data[sri->icode].name, sri->extra_cost);
20231 else if (sri->extra_cost > 0)
20232 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
20234 fputs ("\n", stderr);
20241 /* Better tracing for rs6000_secondary_reload_inner. */
20244 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
20249 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
20251 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
20252 store_p ? "store" : "load");
20255 set = gen_rtx_SET (mem, reg);
20257 set = gen_rtx_SET (reg, mem);
20259 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
20260 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
20263 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
20264 ATTRIBUTE_NORETURN;
20267 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
20270 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
20271 gcc_unreachable ();
20274 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20275 reload helper functions. These were identified in
20276 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20277 reload, it calls the insns:
20278 reload_<RELOAD:mode>_<P:mptrsize>_store
20279 reload_<RELOAD:mode>_<P:mptrsize>_load
20281 which in turn calls this function, to do whatever is necessary to create
20282 valid addresses. */
20285 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
20287 int regno = true_regnum (reg);
20288 machine_mode mode = GET_MODE (reg);
20289 addr_mask_type addr_mask;
20292 rtx op_reg, op0, op1;
20297 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
20298 || !base_reg_operand (scratch, GET_MODE (scratch)))
20299 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20301 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
20302 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
20304 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
20305 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
20307 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
20308 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
20311 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20313 /* Make sure the mode is valid in this register class. */
20314 if ((addr_mask & RELOAD_REG_VALID) == 0)
20315 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20317 if (TARGET_DEBUG_ADDR)
20318 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
20320 new_addr = addr = XEXP (mem, 0);
20321 switch (GET_CODE (addr))
20323 /* Does the register class support auto update forms for this mode? If
20324 not, do the update now. We don't need a scratch register, since the
20325 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20328 op_reg = XEXP (addr, 0);
20329 if (!base_reg_operand (op_reg, Pmode))
20330 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20332 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
20334 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
20340 op0 = XEXP (addr, 0);
20341 op1 = XEXP (addr, 1);
20342 if (!base_reg_operand (op0, Pmode)
20343 || GET_CODE (op1) != PLUS
20344 || !rtx_equal_p (op0, XEXP (op1, 0)))
20345 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20347 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
20349 emit_insn (gen_rtx_SET (op0, op1));
20354 /* Do we need to simulate AND -16 to clear the bottom address bits used
20355 in VMX load/stores? */
20357 op0 = XEXP (addr, 0);
20358 op1 = XEXP (addr, 1);
20359 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
20361 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
20364 else if (GET_CODE (op1) == PLUS)
20366 emit_insn (gen_rtx_SET (scratch, op1));
20371 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20373 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
20374 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
20375 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
20376 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
20377 new_addr = scratch;
20381 /* If this is an indirect address, make sure it is a base register. */
20384 if (!base_reg_operand (addr, GET_MODE (addr)))
20386 emit_insn (gen_rtx_SET (scratch, addr));
20387 new_addr = scratch;
20391 /* If this is an indexed address, make sure the register class can handle
20392 indexed addresses for this mode. */
20394 op0 = XEXP (addr, 0);
20395 op1 = XEXP (addr, 1);
20396 if (!base_reg_operand (op0, Pmode))
20397 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20399 else if (int_reg_operand (op1, Pmode))
20401 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20403 emit_insn (gen_rtx_SET (scratch, addr));
20404 new_addr = scratch;
20408 else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
20410 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
20411 || !quad_address_p (addr, mode, false))
20413 emit_insn (gen_rtx_SET (scratch, addr));
20414 new_addr = scratch;
20418 /* Make sure the register class can handle offset addresses. */
20419 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
20421 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20423 emit_insn (gen_rtx_SET (scratch, addr));
20424 new_addr = scratch;
20429 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20434 op0 = XEXP (addr, 0);
20435 op1 = XEXP (addr, 1);
20436 if (!base_reg_operand (op0, Pmode))
20437 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20439 else if (int_reg_operand (op1, Pmode))
20441 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20443 emit_insn (gen_rtx_SET (scratch, addr));
20444 new_addr = scratch;
20448 /* Quad offsets are restricted and can't handle normal addresses. */
20449 else if (mode_supports_vsx_dform_quad (mode))
20451 emit_insn (gen_rtx_SET (scratch, addr));
20452 new_addr = scratch;
20455 /* Make sure the register class can handle offset addresses. */
20456 else if (legitimate_lo_sum_address_p (mode, addr, false))
20458 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20460 emit_insn (gen_rtx_SET (scratch, addr));
20461 new_addr = scratch;
20466 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20473 rs6000_emit_move (scratch, addr, Pmode);
20474 new_addr = scratch;
20478 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20481 /* Adjust the address if it changed. */
20482 if (addr != new_addr)
20484 mem = replace_equiv_address_nv (mem, new_addr);
20485 if (TARGET_DEBUG_ADDR)
20486 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20489 /* Now create the move. */
20491 emit_insn (gen_rtx_SET (mem, reg));
20493 emit_insn (gen_rtx_SET (reg, mem));
20498 /* Convert reloads involving 64-bit gprs and misaligned offset
20499 addressing, or multiple 32-bit gprs and offsets that are too large,
20500 to use indirect addressing. */
20503 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
20505 int regno = true_regnum (reg);
20506 enum reg_class rclass;
20508 rtx scratch_or_premodify = scratch;
20510 if (TARGET_DEBUG_ADDR)
20512 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
20513 store_p ? "store" : "load");
20514 fprintf (stderr, "reg:\n");
20516 fprintf (stderr, "mem:\n");
20518 fprintf (stderr, "scratch:\n");
20519 debug_rtx (scratch);
20522 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
20523 gcc_assert (GET_CODE (mem) == MEM);
20524 rclass = REGNO_REG_CLASS (regno);
20525 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
20526 addr = XEXP (mem, 0);
20528 if (GET_CODE (addr) == PRE_MODIFY)
20530 gcc_assert (REG_P (XEXP (addr, 0))
20531 && GET_CODE (XEXP (addr, 1)) == PLUS
20532 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
20533 scratch_or_premodify = XEXP (addr, 0);
20534 if (!HARD_REGISTER_P (scratch_or_premodify))
20535 /* If we have a pseudo here then reload will have arranged
20536 to have it replaced, but only in the original insn.
20537 Use the replacement here too. */
20538 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
20540 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20541 expressions from the original insn, without unsharing them.
20542 Any RTL that points into the original insn will of course
20543 have register replacements applied. That is why we don't
20544 need to look for replacements under the PLUS. */
20545 addr = XEXP (addr, 1);
20547 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
20549 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
20551 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
20553 /* Now create the move. */
20555 emit_insn (gen_rtx_SET (mem, reg));
20557 emit_insn (gen_rtx_SET (reg, mem));
20562 /* Given an rtx X being reloaded into a reg required to be
20563 in class CLASS, return the class of reg to actually use.
20564 In general this is just CLASS; but on some machines
20565 in some cases it is preferable to use a more restrictive class.
20567 On the RS/6000, we have to return NO_REGS when we want to reload a
20568 floating-point CONST_DOUBLE to force it to be copied to memory.
20570 We also don't want to reload integer values into floating-point
20571 registers if we can at all help it. In fact, this can
20572 cause reload to die, if it tries to generate a reload of CTR
20573 into a FP register and discovers it doesn't have the memory location
20576 ??? Would it be a good idea to have reload do the converse, that is
20577 try to reload floating modes into FP registers if possible?
20580 static enum reg_class
20581 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
20583 machine_mode mode = GET_MODE (x);
20584 bool is_constant = CONSTANT_P (x);
20586 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20587 reload class for it. */
20588 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20589 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
20592 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
20593 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
20596 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20597 the reloading of address expressions using PLUS into floating point
20599 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
20603 /* Zero is always allowed in all VSX registers. */
20604 if (x == CONST0_RTX (mode))
20607 /* If this is a vector constant that can be formed with a few Altivec
20608 instructions, we want altivec registers. */
20609 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
20610 return ALTIVEC_REGS;
20612 /* If this is an integer constant that can easily be loaded into
20613 vector registers, allow it. */
20614 if (CONST_INT_P (x))
20616 HOST_WIDE_INT value = INTVAL (x);
20618 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20619 2.06 can generate it in the Altivec registers with
20623 if (TARGET_P8_VECTOR)
20625 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20626 return ALTIVEC_REGS;
20631 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20632 a sign extend in the Altivec registers. */
20633 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
20634 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
20635 return ALTIVEC_REGS;
20638 /* Force constant to memory. */
20642 /* D-form addressing can easily reload the value. */
20643 if (mode_supports_vmx_dform (mode)
20644 || mode_supports_vsx_dform_quad (mode))
20647 /* If this is a scalar floating point value and we don't have D-form
20648 addressing, prefer the traditional floating point registers so that we
20649 can use D-form (register+offset) addressing. */
20650 if (rclass == VSX_REGS
20651 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
20654 /* Prefer the Altivec registers if Altivec is handling the vector
20655 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20657 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20658 || mode == V1TImode)
20659 return ALTIVEC_REGS;
20664 if (is_constant || GET_CODE (x) == PLUS)
20666 if (reg_class_subset_p (GENERAL_REGS, rclass))
20667 return GENERAL_REGS;
20668 if (reg_class_subset_p (BASE_REGS, rclass))
20673 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20674 return GENERAL_REGS;
20679 /* Debug version of rs6000_preferred_reload_class. */
20680 static enum reg_class
20681 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20683 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20686 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20688 reg_class_names[ret], reg_class_names[rclass],
20689 GET_MODE_NAME (GET_MODE (x)));
20695 /* If we are copying between FP or AltiVec registers and anything else, we need
20696 a memory location. The exception is when we are targeting ppc64 and the
20697 move to/from fpr to gpr instructions are available. Also, under VSX, you
20698 can copy vector registers from the FP register set to the Altivec register
20699 set and vice versa. */
20702 rs6000_secondary_memory_needed (machine_mode mode,
20703 reg_class_t from_class,
20704 reg_class_t to_class)
20706 enum rs6000_reg_type from_type, to_type;
20707 bool altivec_p = ((from_class == ALTIVEC_REGS)
20708 || (to_class == ALTIVEC_REGS));
20710 /* If a simple/direct move is available, we don't need secondary memory */
20711 from_type = reg_class_to_reg_type[(int)from_class];
20712 to_type = reg_class_to_reg_type[(int)to_class];
20714 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20715 (secondary_reload_info *)0, altivec_p))
20718 /* If we have a floating point or vector register class, we need to use
20719 memory to transfer the data. */
20720 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20726 /* Debug version of rs6000_secondary_memory_needed. */
20728 rs6000_debug_secondary_memory_needed (machine_mode mode,
20729 reg_class_t from_class,
20730 reg_class_t to_class)
20732 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20735 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20736 "to_class = %s, mode = %s\n",
20737 ret ? "true" : "false",
20738 reg_class_names[from_class],
20739 reg_class_names[to_class],
20740 GET_MODE_NAME (mode));
20745 /* Return the register class of a scratch register needed to copy IN into
20746 or out of a register in RCLASS in MODE. If it can be done directly,
20747 NO_REGS is returned. */
20749 static enum reg_class
20750 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20755 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20757 && MACHOPIC_INDIRECT
20761 /* We cannot copy a symbolic operand directly into anything
20762 other than BASE_REGS for TARGET_ELF. So indicate that a
20763 register from BASE_REGS is needed as an intermediate
20766 On Darwin, pic addresses require a load from memory, which
20767 needs a base register. */
20768 if (rclass != BASE_REGS
20769 && (GET_CODE (in) == SYMBOL_REF
20770 || GET_CODE (in) == HIGH
20771 || GET_CODE (in) == LABEL_REF
20772 || GET_CODE (in) == CONST))
20776 if (GET_CODE (in) == REG)
20778 regno = REGNO (in);
20779 if (regno >= FIRST_PSEUDO_REGISTER)
20781 regno = true_regnum (in);
20782 if (regno >= FIRST_PSEUDO_REGISTER)
20786 else if (GET_CODE (in) == SUBREG)
20788 regno = true_regnum (in);
20789 if (regno >= FIRST_PSEUDO_REGISTER)
20795 /* If we have VSX register moves, prefer moving scalar values between
20796 Altivec registers and GPR by going via an FPR (and then via memory)
20797 instead of reloading the secondary memory address for Altivec moves. */
20799 && GET_MODE_SIZE (mode) < 16
20800 && !mode_supports_vmx_dform (mode)
20801 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20802 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20803 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20804 && (regno >= 0 && INT_REGNO_P (regno)))))
20807 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20809 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20810 || (regno >= 0 && INT_REGNO_P (regno)))
20813 /* Constants, memory, and VSX registers can go into VSX registers (both the
20814 traditional floating point and the altivec registers). */
20815 if (rclass == VSX_REGS
20816 && (regno == -1 || VSX_REGNO_P (regno)))
20819 /* Constants, memory, and FP registers can go into FP registers. */
20820 if ((regno == -1 || FP_REGNO_P (regno))
20821 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20822 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20824 /* Memory, and AltiVec registers can go into AltiVec registers. */
20825 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20826 && rclass == ALTIVEC_REGS)
20829 /* We can copy among the CR registers. */
20830 if ((rclass == CR_REGS || rclass == CR0_REGS)
20831 && regno >= 0 && CR_REGNO_P (regno))
20834 /* Otherwise, we need GENERAL_REGS. */
20835 return GENERAL_REGS;
20838 /* Debug version of rs6000_secondary_reload_class. */
20839 static enum reg_class
20840 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20841 machine_mode mode, rtx in)
20843 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20845 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20846 "mode = %s, input rtx:\n",
20847 reg_class_names[ret], reg_class_names[rclass],
20848 GET_MODE_NAME (mode));
20854 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20857 rs6000_can_change_mode_class (machine_mode from,
20859 reg_class_t rclass)
20861 unsigned from_size = GET_MODE_SIZE (from);
20862 unsigned to_size = GET_MODE_SIZE (to);
20864 if (from_size != to_size)
20866 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20868 if (reg_classes_intersect_p (xclass, rclass))
20870 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20871 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20872 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20873 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20875 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20876 single register under VSX because the scalar part of the register
20877 is in the upper 64-bits, and not the lower 64-bits. Types like
20878 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20879 IEEE floating point can't overlap, and neither can small
20882 if (to_float128_vector_p && from_float128_vector_p)
20885 else if (to_float128_vector_p || from_float128_vector_p)
20888 /* TDmode in floating-mode registers must always go into a register
20889 pair with the most significant word in the even-numbered register
20890 to match ISA requirements. In little-endian mode, this does not
20891 match subreg numbering, so we cannot allow subregs. */
20892 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20895 if (from_size < 8 || to_size < 8)
20898 if (from_size == 8 && (8 * to_nregs) != to_size)
20901 if (to_size == 8 && (8 * from_nregs) != from_size)
20910 /* Since the VSX register set includes traditional floating point registers
20911 and altivec registers, just check for the size being different instead of
20912 trying to check whether the modes are vector modes. Otherwise it won't
20913 allow say DF and DI to change classes. For types like TFmode and TDmode
20914 that take 2 64-bit registers, rather than a single 128-bit register, don't
20915 allow subregs of those types to other 128 bit types. */
20916 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20918 unsigned num_regs = (from_size + 15) / 16;
20919 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20920 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20923 return (from_size == 8 || from_size == 16);
20926 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20927 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20933 /* Debug version of rs6000_can_change_mode_class. */
20935 rs6000_debug_can_change_mode_class (machine_mode from,
20937 reg_class_t rclass)
20939 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20942 "rs6000_can_change_mode_class, return %s, from = %s, "
20943 "to = %s, rclass = %s\n",
20944 ret ? "true" : "false",
20945 GET_MODE_NAME (from), GET_MODE_NAME (to),
20946 reg_class_names[rclass]);
20951 /* Return a string to do a move operation of 128 bits of data. */
20954 rs6000_output_move_128bit (rtx operands[])
20956 rtx dest = operands[0];
20957 rtx src = operands[1];
20958 machine_mode mode = GET_MODE (dest);
20961 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20962 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20966 dest_regno = REGNO (dest);
20967 dest_gpr_p = INT_REGNO_P (dest_regno);
20968 dest_fp_p = FP_REGNO_P (dest_regno);
20969 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20970 dest_vsx_p = dest_fp_p | dest_vmx_p;
20975 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20980 src_regno = REGNO (src);
20981 src_gpr_p = INT_REGNO_P (src_regno);
20982 src_fp_p = FP_REGNO_P (src_regno);
20983 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20984 src_vsx_p = src_fp_p | src_vmx_p;
20989 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20992 /* Register moves. */
20993 if (dest_regno >= 0 && src_regno >= 0)
21000 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
21001 return (WORDS_BIG_ENDIAN
21002 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
21003 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
21005 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
21009 else if (TARGET_VSX && dest_vsx_p)
21012 return "xxlor %x0,%x1,%x1";
21014 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
21015 return (WORDS_BIG_ENDIAN
21016 ? "mtvsrdd %x0,%1,%L1"
21017 : "mtvsrdd %x0,%L1,%1");
21019 else if (TARGET_DIRECT_MOVE && src_gpr_p)
21023 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
21024 return "vor %0,%1,%1";
21026 else if (dest_fp_p && src_fp_p)
21031 else if (dest_regno >= 0 && MEM_P (src))
21035 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21041 else if (TARGET_ALTIVEC && dest_vmx_p
21042 && altivec_indexed_or_indirect_operand (src, mode))
21043 return "lvx %0,%y1";
21045 else if (TARGET_VSX && dest_vsx_p)
21047 if (mode_supports_vsx_dform_quad (mode)
21048 && quad_address_p (XEXP (src, 0), mode, true))
21049 return "lxv %x0,%1";
21051 else if (TARGET_P9_VECTOR)
21052 return "lxvx %x0,%y1";
21054 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21055 return "lxvw4x %x0,%y1";
21058 return "lxvd2x %x0,%y1";
21061 else if (TARGET_ALTIVEC && dest_vmx_p)
21062 return "lvx %0,%y1";
21064 else if (dest_fp_p)
21069 else if (src_regno >= 0 && MEM_P (dest))
21073 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21074 return "stq %1,%0";
21079 else if (TARGET_ALTIVEC && src_vmx_p
21080 && altivec_indexed_or_indirect_operand (src, mode))
21081 return "stvx %1,%y0";
21083 else if (TARGET_VSX && src_vsx_p)
21085 if (mode_supports_vsx_dform_quad (mode)
21086 && quad_address_p (XEXP (dest, 0), mode, true))
21087 return "stxv %x1,%0";
21089 else if (TARGET_P9_VECTOR)
21090 return "stxvx %x1,%y0";
21092 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21093 return "stxvw4x %x1,%y0";
21096 return "stxvd2x %x1,%y0";
21099 else if (TARGET_ALTIVEC && src_vmx_p)
21100 return "stvx %1,%y0";
21107 else if (dest_regno >= 0
21108 && (GET_CODE (src) == CONST_INT
21109 || GET_CODE (src) == CONST_WIDE_INT
21110 || GET_CODE (src) == CONST_DOUBLE
21111 || GET_CODE (src) == CONST_VECTOR))
21116 else if ((dest_vmx_p && TARGET_ALTIVEC)
21117 || (dest_vsx_p && TARGET_VSX))
21118 return output_vec_const_move (operands);
21121 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
21124 /* Validate a 128-bit move. */
21126 rs6000_move_128bit_ok_p (rtx operands[])
21128 machine_mode mode = GET_MODE (operands[0]);
21129 return (gpc_reg_operand (operands[0], mode)
21130 || gpc_reg_operand (operands[1], mode));
21133 /* Return true if a 128-bit move needs to be split. */
21135 rs6000_split_128bit_ok_p (rtx operands[])
21137 if (!reload_completed)
21140 if (!gpr_or_gpr_p (operands[0], operands[1]))
21143 if (quad_load_store_p (operands[0], operands[1]))
21150 /* Given a comparison operation, return the bit number in CCR to test. We
21151 know this is a valid comparison.
21153 SCC_P is 1 if this is for an scc. That means that %D will have been
21154 used instead of %C, so the bits will be in different places.
21156 Return -1 if OP isn't a valid comparison for some reason. */
21159 ccr_bit (rtx op, int scc_p)
21161 enum rtx_code code = GET_CODE (op);
21162 machine_mode cc_mode;
21167 if (!COMPARISON_P (op))
21170 reg = XEXP (op, 0);
21172 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
21174 cc_mode = GET_MODE (reg);
21175 cc_regnum = REGNO (reg);
21176 base_bit = 4 * (cc_regnum - CR0_REGNO);
21178 validate_condition_mode (code, cc_mode);
21180 /* When generating a sCOND operation, only positive conditions are
21183 || code == EQ || code == GT || code == LT || code == UNORDERED
21184 || code == GTU || code == LTU);
21189 return scc_p ? base_bit + 3 : base_bit + 2;
21191 return base_bit + 2;
21192 case GT: case GTU: case UNLE:
21193 return base_bit + 1;
21194 case LT: case LTU: case UNGE:
21196 case ORDERED: case UNORDERED:
21197 return base_bit + 3;
21200 /* If scc, we will have done a cror to put the bit in the
21201 unordered position. So test that bit. For integer, this is ! LT
21202 unless this is an scc insn. */
21203 return scc_p ? base_bit + 3 : base_bit;
21206 return scc_p ? base_bit + 3 : base_bit + 1;
21209 gcc_unreachable ();
21213 /* Return the GOT register. */
21216 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
21218 /* The second flow pass currently (June 1999) can't update
21219 regs_ever_live without disturbing other parts of the compiler, so
21220 update it here to make the prolog/epilogue code happy. */
21221 if (!can_create_pseudo_p ()
21222 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21223 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
21225 crtl->uses_pic_offset_table = 1;
21227 return pic_offset_table_rtx;
21230 static rs6000_stack_t stack_info;
21232 /* Function to init struct machine_function.
21233 This will be called, via a pointer variable,
21234 from push_function_context. */
21236 static struct machine_function *
21237 rs6000_init_machine_status (void)
21239 stack_info.reload_completed = 0;
21240 return ggc_cleared_alloc<machine_function> ();
21243 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21245 /* Write out a function code label. */
21248 rs6000_output_function_entry (FILE *file, const char *fname)
21250 if (fname[0] != '.')
21252 switch (DEFAULT_ABI)
21255 gcc_unreachable ();
21261 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
21271 RS6000_OUTPUT_BASENAME (file, fname);
21274 /* Print an operand. Recognize special options, documented below. */
21277 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21278 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21280 #define SMALL_DATA_RELOC "sda21"
21281 #define SMALL_DATA_REG 0
21285 print_operand (FILE *file, rtx x, int code)
21288 unsigned HOST_WIDE_INT uval;
21292 /* %a is output_address. */
21294 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21298 /* Like 'J' but get to the GT bit only. */
21299 gcc_assert (REG_P (x));
21301 /* Bit 1 is GT bit. */
21302 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
21304 /* Add one for shift count in rlinm for scc. */
21305 fprintf (file, "%d", i + 1);
21309 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21312 output_operand_lossage ("invalid %%e value");
21317 if ((uval & 0xffff) == 0 && uval != 0)
21322 /* X is a CR register. Print the number of the EQ bit of the CR */
21323 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21324 output_operand_lossage ("invalid %%E value");
21326 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
21330 /* X is a CR register. Print the shift count needed to move it
21331 to the high-order four bits. */
21332 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21333 output_operand_lossage ("invalid %%f value");
21335 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
21339 /* Similar, but print the count for the rotate in the opposite
21341 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21342 output_operand_lossage ("invalid %%F value");
21344 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
21348 /* X is a constant integer. If it is negative, print "m",
21349 otherwise print "z". This is to make an aze or ame insn. */
21350 if (GET_CODE (x) != CONST_INT)
21351 output_operand_lossage ("invalid %%G value");
21352 else if (INTVAL (x) >= 0)
21359 /* If constant, output low-order five bits. Otherwise, write
21362 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
21364 print_operand (file, x, 0);
21368 /* If constant, output low-order six bits. Otherwise, write
21371 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
21373 print_operand (file, x, 0);
21377 /* Print `i' if this is a constant, else nothing. */
21383 /* Write the bit number in CCR for jump. */
21384 i = ccr_bit (x, 0);
21386 output_operand_lossage ("invalid %%j code");
21388 fprintf (file, "%d", i);
21392 /* Similar, but add one for shift count in rlinm for scc and pass
21393 scc flag to `ccr_bit'. */
21394 i = ccr_bit (x, 1);
21396 output_operand_lossage ("invalid %%J code");
21398 /* If we want bit 31, write a shift count of zero, not 32. */
21399 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21403 /* X must be a constant. Write the 1's complement of the
21406 output_operand_lossage ("invalid %%k value");
21408 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
21412 /* X must be a symbolic constant on ELF. Write an
21413 expression suitable for an 'addi' that adds in the low 16
21414 bits of the MEM. */
21415 if (GET_CODE (x) == CONST)
21417 if (GET_CODE (XEXP (x, 0)) != PLUS
21418 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
21419 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
21420 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
21421 output_operand_lossage ("invalid %%K value");
21423 print_operand_address (file, x);
21424 fputs ("@l", file);
21427 /* %l is output_asm_label. */
21430 /* Write second word of DImode or DFmode reference. Works on register
21431 or non-indexed memory only. */
21433 fputs (reg_names[REGNO (x) + 1], file);
21434 else if (MEM_P (x))
21436 machine_mode mode = GET_MODE (x);
21437 /* Handle possible auto-increment. Since it is pre-increment and
21438 we have already done it, we can just use an offset of word. */
21439 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21440 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21441 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21443 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21444 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21447 output_address (mode, XEXP (adjust_address_nv (x, SImode,
21451 if (small_data_operand (x, GET_MODE (x)))
21452 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21453 reg_names[SMALL_DATA_REG]);
21458 /* Write the number of elements in the vector times 4. */
21459 if (GET_CODE (x) != PARALLEL)
21460 output_operand_lossage ("invalid %%N value");
21462 fprintf (file, "%d", XVECLEN (x, 0) * 4);
21466 /* Similar, but subtract 1 first. */
21467 if (GET_CODE (x) != PARALLEL)
21468 output_operand_lossage ("invalid %%O value");
21470 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
21474 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21477 || (i = exact_log2 (INTVAL (x))) < 0)
21478 output_operand_lossage ("invalid %%p value");
21480 fprintf (file, "%d", i);
21484 /* The operand must be an indirect memory reference. The result
21485 is the register name. */
21486 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
21487 || REGNO (XEXP (x, 0)) >= 32)
21488 output_operand_lossage ("invalid %%P value");
21490 fputs (reg_names[REGNO (XEXP (x, 0))], file);
21494 /* This outputs the logical code corresponding to a boolean
21495 expression. The expression may have one or both operands
21496 negated (if one, only the first one). For condition register
21497 logical operations, it will also treat the negated
21498 CR codes as NOTs, but not handle NOTs of them. */
21500 const char *const *t = 0;
21502 enum rtx_code code = GET_CODE (x);
21503 static const char * const tbl[3][3] = {
21504 { "and", "andc", "nor" },
21505 { "or", "orc", "nand" },
21506 { "xor", "eqv", "xor" } };
21510 else if (code == IOR)
21512 else if (code == XOR)
21515 output_operand_lossage ("invalid %%q value");
21517 if (GET_CODE (XEXP (x, 0)) != NOT)
21521 if (GET_CODE (XEXP (x, 1)) == NOT)
21532 if (! TARGET_MFCRF)
21538 /* X is a CR register. Print the mask for `mtcrf'. */
21539 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21540 output_operand_lossage ("invalid %%R value");
21542 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
21546 /* Low 5 bits of 32 - value */
21548 output_operand_lossage ("invalid %%s value");
21550 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
21554 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21555 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
21557 /* Bit 3 is OV bit. */
21558 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
21560 /* If we want bit 31, write a shift count of zero, not 32. */
21561 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21565 /* Print the symbolic name of a branch target register. */
21566 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
21567 && REGNO (x) != CTR_REGNO))
21568 output_operand_lossage ("invalid %%T value");
21569 else if (REGNO (x) == LR_REGNO)
21570 fputs ("lr", file);
21572 fputs ("ctr", file);
21576 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21577 for use in unsigned operand. */
21580 output_operand_lossage ("invalid %%u value");
21585 if ((uval & 0xffff) == 0)
21588 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
21592 /* High-order 16 bits of constant for use in signed operand. */
21594 output_operand_lossage ("invalid %%v value");
21596 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
21597 (INTVAL (x) >> 16) & 0xffff);
21601 /* Print `u' if this has an auto-increment or auto-decrement. */
21603 && (GET_CODE (XEXP (x, 0)) == PRE_INC
21604 || GET_CODE (XEXP (x, 0)) == PRE_DEC
21605 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
21610 /* Print the trap code for this operand. */
21611 switch (GET_CODE (x))
21614 fputs ("eq", file); /* 4 */
21617 fputs ("ne", file); /* 24 */
21620 fputs ("lt", file); /* 16 */
21623 fputs ("le", file); /* 20 */
21626 fputs ("gt", file); /* 8 */
21629 fputs ("ge", file); /* 12 */
21632 fputs ("llt", file); /* 2 */
21635 fputs ("lle", file); /* 6 */
21638 fputs ("lgt", file); /* 1 */
21641 fputs ("lge", file); /* 5 */
21644 gcc_unreachable ();
21649 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21652 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21653 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21655 print_operand (file, x, 0);
21659 /* X is a FPR or Altivec register used in a VSX context. */
21660 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21661 output_operand_lossage ("invalid %%x value");
21664 int reg = REGNO (x);
21665 int vsx_reg = (FP_REGNO_P (reg)
21667 : reg - FIRST_ALTIVEC_REGNO + 32);
21669 #ifdef TARGET_REGNAMES
21670 if (TARGET_REGNAMES)
21671 fprintf (file, "%%vs%d", vsx_reg);
21674 fprintf (file, "%d", vsx_reg);
21680 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21681 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21682 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21687 /* Like 'L', for third word of TImode/PTImode */
21689 fputs (reg_names[REGNO (x) + 2], file);
21690 else if (MEM_P (x))
21692 machine_mode mode = GET_MODE (x);
21693 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21694 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21695 output_address (mode, plus_constant (Pmode,
21696 XEXP (XEXP (x, 0), 0), 8));
21697 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21698 output_address (mode, plus_constant (Pmode,
21699 XEXP (XEXP (x, 0), 0), 8));
21701 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21702 if (small_data_operand (x, GET_MODE (x)))
21703 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21704 reg_names[SMALL_DATA_REG]);
21709 /* X is a SYMBOL_REF. Write out the name preceded by a
21710 period and without any trailing data in brackets. Used for function
21711 names. If we are configured for System V (or the embedded ABI) on
21712 the PowerPC, do not emit the period, since those systems do not use
21713 TOCs and the like. */
21714 gcc_assert (GET_CODE (x) == SYMBOL_REF);
21716 /* For macho, check to see if we need a stub. */
21719 const char *name = XSTR (x, 0);
21721 if (darwin_emit_branch_islands
21722 && MACHOPIC_INDIRECT
21723 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21724 name = machopic_indirection_name (x, /*stub_p=*/true);
21726 assemble_name (file, name);
21728 else if (!DOT_SYMBOLS)
21729 assemble_name (file, XSTR (x, 0));
21731 rs6000_output_function_entry (file, XSTR (x, 0));
21735 /* Like 'L', for last word of TImode/PTImode. */
21737 fputs (reg_names[REGNO (x) + 3], file);
21738 else if (MEM_P (x))
21740 machine_mode mode = GET_MODE (x);
21741 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21742 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21743 output_address (mode, plus_constant (Pmode,
21744 XEXP (XEXP (x, 0), 0), 12));
21745 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21746 output_address (mode, plus_constant (Pmode,
21747 XEXP (XEXP (x, 0), 0), 12));
21749 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21750 if (small_data_operand (x, GET_MODE (x)))
21751 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21752 reg_names[SMALL_DATA_REG]);
21756 /* Print AltiVec memory operand. */
21761 gcc_assert (MEM_P (x));
21765 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
21766 && GET_CODE (tmp) == AND
21767 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21768 && INTVAL (XEXP (tmp, 1)) == -16)
21769 tmp = XEXP (tmp, 0);
21770 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21771 && GET_CODE (tmp) == PRE_MODIFY)
21772 tmp = XEXP (tmp, 1);
21774 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21777 if (GET_CODE (tmp) != PLUS
21778 || !REG_P (XEXP (tmp, 0))
21779 || !REG_P (XEXP (tmp, 1)))
21781 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21785 if (REGNO (XEXP (tmp, 0)) == 0)
21786 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21787 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21789 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21790 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21797 fprintf (file, "%s", reg_names[REGNO (x)]);
21798 else if (MEM_P (x))
21800 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21801 know the width from the mode. */
21802 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21803 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21804 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21805 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21806 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21807 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21808 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21809 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21811 output_address (GET_MODE (x), XEXP (x, 0));
21815 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21816 /* This hack along with a corresponding hack in
21817 rs6000_output_addr_const_extra arranges to output addends
21818 where the assembler expects to find them. eg.
21819 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21820 without this hack would be output as "x@toc+4". We
21822 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21824 output_addr_const (file, x);
21829 if (const char *name = get_some_local_dynamic_name ())
21830 assemble_name (file, name);
21832 output_operand_lossage ("'%%&' used without any "
21833 "local dynamic TLS references");
21837 output_operand_lossage ("invalid %%xn code");
21841 /* Print the address of an operand. */
21844 print_operand_address (FILE *file, rtx x)
21847 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21848 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21849 || GET_CODE (x) == LABEL_REF)
21851 output_addr_const (file, x);
21852 if (small_data_operand (x, GET_MODE (x)))
21853 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21854 reg_names[SMALL_DATA_REG]);
21856 gcc_assert (!TARGET_TOC);
21858 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21859 && REG_P (XEXP (x, 1)))
21861 if (REGNO (XEXP (x, 0)) == 0)
21862 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21863 reg_names[ REGNO (XEXP (x, 0)) ]);
21865 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21866 reg_names[ REGNO (XEXP (x, 1)) ]);
21868 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21869 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21870 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21871 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21873 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21874 && CONSTANT_P (XEXP (x, 1)))
21876 fprintf (file, "lo16(");
21877 output_addr_const (file, XEXP (x, 1));
21878 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21882 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21883 && CONSTANT_P (XEXP (x, 1)))
21885 output_addr_const (file, XEXP (x, 1));
21886 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21889 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21891 /* This hack along with a corresponding hack in
21892 rs6000_output_addr_const_extra arranges to output addends
21893 where the assembler expects to find them. eg.
21895 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21896 without this hack would be output as "x@toc+8@l(9)". We
21897 want "x+8@toc@l(9)". */
21898 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21899 if (GET_CODE (x) == LO_SUM)
21900 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21902 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21905 gcc_unreachable ();
21908 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21911 rs6000_output_addr_const_extra (FILE *file, rtx x)
21913 if (GET_CODE (x) == UNSPEC)
21914 switch (XINT (x, 1))
21916 case UNSPEC_TOCREL:
21917 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21918 && REG_P (XVECEXP (x, 0, 1))
21919 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21920 output_addr_const (file, XVECEXP (x, 0, 0));
21921 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21923 if (INTVAL (tocrel_offset_oac) >= 0)
21924 fprintf (file, "+");
21925 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21927 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21930 assemble_name (file, toc_label_name);
21933 else if (TARGET_ELF)
21934 fputs ("@toc", file);
21938 case UNSPEC_MACHOPIC_OFFSET:
21939 output_addr_const (file, XVECEXP (x, 0, 0));
21941 machopic_output_function_base_name (file);
21948 /* Target hook for assembling integer objects. The PowerPC version has
21949 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21950 is defined. It also needs to handle DI-mode objects on 64-bit
21954 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21956 #ifdef RELOCATABLE_NEEDS_FIXUP
21957 /* Special handling for SI values. */
21958 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21960 static int recurse = 0;
21962 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21963 the .fixup section. Since the TOC section is already relocated, we
21964 don't need to mark it here. We used to skip the text section, but it
21965 should never be valid for relocated addresses to be placed in the text
21967 if (DEFAULT_ABI == ABI_V4
21968 && (TARGET_RELOCATABLE || flag_pic > 1)
21969 && in_section != toc_section
21971 && !CONST_SCALAR_INT_P (x)
21977 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21979 ASM_OUTPUT_LABEL (asm_out_file, buf);
21980 fprintf (asm_out_file, "\t.long\t(");
21981 output_addr_const (asm_out_file, x);
21982 fprintf (asm_out_file, ")@fixup\n");
21983 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21984 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21985 fprintf (asm_out_file, "\t.long\t");
21986 assemble_name (asm_out_file, buf);
21987 fprintf (asm_out_file, "\n\t.previous\n");
21991 /* Remove initial .'s to turn a -mcall-aixdesc function
21992 address into the address of the descriptor, not the function
21994 else if (GET_CODE (x) == SYMBOL_REF
21995 && XSTR (x, 0)[0] == '.'
21996 && DEFAULT_ABI == ABI_AIX)
21998 const char *name = XSTR (x, 0);
21999 while (*name == '.')
22002 fprintf (asm_out_file, "\t.long\t%s\n", name);
22006 #endif /* RELOCATABLE_NEEDS_FIXUP */
22007 return default_assemble_integer (x, size, aligned_p);
22010 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
22011 /* Emit an assembler directive to set symbol visibility for DECL to
22012 VISIBILITY_TYPE. */
22015 rs6000_assemble_visibility (tree decl, int vis)
22020 /* Functions need to have their entry point symbol visibility set as
22021 well as their descriptor symbol visibility. */
22022 if (DEFAULT_ABI == ABI_AIX
22024 && TREE_CODE (decl) == FUNCTION_DECL)
22026 static const char * const visibility_types[] = {
22027 NULL, "protected", "hidden", "internal"
22030 const char *name, *type;
22032 name = ((* targetm.strip_name_encoding)
22033 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
22034 type = visibility_types[vis];
22036 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
22037 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
22040 default_assemble_visibility (decl, vis);
22045 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
22047 /* Reversal of FP compares takes care -- an ordered compare
22048 becomes an unordered compare and vice versa. */
22049 if (mode == CCFPmode
22050 && (!flag_finite_math_only
22051 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
22052 || code == UNEQ || code == LTGT))
22053 return reverse_condition_maybe_unordered (code);
22055 return reverse_condition (code);
22058 /* Generate a compare for CODE. Return a brand-new rtx that
22059 represents the result of the compare. */
22062 rs6000_generate_compare (rtx cmp, machine_mode mode)
22064 machine_mode comp_mode;
22065 rtx compare_result;
22066 enum rtx_code code = GET_CODE (cmp);
22067 rtx op0 = XEXP (cmp, 0);
22068 rtx op1 = XEXP (cmp, 1);
22070 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22071 comp_mode = CCmode;
22072 else if (FLOAT_MODE_P (mode))
22073 comp_mode = CCFPmode;
22074 else if (code == GTU || code == LTU
22075 || code == GEU || code == LEU)
22076 comp_mode = CCUNSmode;
22077 else if ((code == EQ || code == NE)
22078 && unsigned_reg_p (op0)
22079 && (unsigned_reg_p (op1)
22080 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
22081 /* These are unsigned values, perhaps there will be a later
22082 ordering compare that can be shared with this one. */
22083 comp_mode = CCUNSmode;
22085 comp_mode = CCmode;
22087 /* If we have an unsigned compare, make sure we don't have a signed value as
22089 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
22090 && INTVAL (op1) < 0)
22092 op0 = copy_rtx_if_shared (op0);
22093 op1 = force_reg (GET_MODE (op0), op1);
22094 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
22097 /* First, the compare. */
22098 compare_result = gen_reg_rtx (comp_mode);
22100 /* IEEE 128-bit support in VSX registers when we do not have hardware
22102 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22104 rtx libfunc = NULL_RTX;
22105 bool check_nan = false;
22112 libfunc = optab_libfunc (eq_optab, mode);
22117 libfunc = optab_libfunc (ge_optab, mode);
22122 libfunc = optab_libfunc (le_optab, mode);
22127 libfunc = optab_libfunc (unord_optab, mode);
22128 code = (code == UNORDERED) ? NE : EQ;
22134 libfunc = optab_libfunc (ge_optab, mode);
22135 code = (code == UNGE) ? GE : GT;
22141 libfunc = optab_libfunc (le_optab, mode);
22142 code = (code == UNLE) ? LE : LT;
22148 libfunc = optab_libfunc (eq_optab, mode);
22149 code = (code = UNEQ) ? EQ : NE;
22153 gcc_unreachable ();
22156 gcc_assert (libfunc);
22159 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22160 SImode, op0, mode, op1, mode);
22162 /* The library signals an exception for signalling NaNs, so we need to
22163 handle isgreater, etc. by first checking isordered. */
22166 rtx ne_rtx, normal_dest, unord_dest;
22167 rtx unord_func = optab_libfunc (unord_optab, mode);
22168 rtx join_label = gen_label_rtx ();
22169 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
22170 rtx unord_cmp = gen_reg_rtx (comp_mode);
22173 /* Test for either value being a NaN. */
22174 gcc_assert (unord_func);
22175 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
22176 SImode, op0, mode, op1, mode);
22178 /* Set value (0) if either value is a NaN, and jump to the join
22180 dest = gen_reg_rtx (SImode);
22181 emit_move_insn (dest, const1_rtx);
22182 emit_insn (gen_rtx_SET (unord_cmp,
22183 gen_rtx_COMPARE (comp_mode, unord_dest,
22186 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
22187 emit_jump_insn (gen_rtx_SET (pc_rtx,
22188 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
22192 /* Do the normal comparison, knowing that the values are not
22194 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22195 SImode, op0, mode, op1, mode);
22197 emit_insn (gen_cstoresi4 (dest,
22198 gen_rtx_fmt_ee (code, SImode, normal_dest,
22200 normal_dest, const0_rtx));
22202 /* Join NaN and non-Nan paths. Compare dest against 0. */
22203 emit_label (join_label);
22207 emit_insn (gen_rtx_SET (compare_result,
22208 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
22213 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22214 CLOBBERs to match cmptf_internal2 pattern. */
22215 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
22216 && FLOAT128_IBM_P (GET_MODE (op0))
22217 && TARGET_HARD_FLOAT)
22218 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22220 gen_rtx_SET (compare_result,
22221 gen_rtx_COMPARE (comp_mode, op0, op1)),
22222 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22223 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22224 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22225 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22226 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22227 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22228 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22229 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22230 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
22231 else if (GET_CODE (op1) == UNSPEC
22232 && XINT (op1, 1) == UNSPEC_SP_TEST)
22234 rtx op1b = XVECEXP (op1, 0, 0);
22235 comp_mode = CCEQmode;
22236 compare_result = gen_reg_rtx (CCEQmode);
22238 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
22240 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
22243 emit_insn (gen_rtx_SET (compare_result,
22244 gen_rtx_COMPARE (comp_mode, op0, op1)));
22247 /* Some kinds of FP comparisons need an OR operation;
22248 under flag_finite_math_only we don't bother. */
22249 if (FLOAT_MODE_P (mode)
22250 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
22251 && !flag_finite_math_only
22252 && (code == LE || code == GE
22253 || code == UNEQ || code == LTGT
22254 || code == UNGT || code == UNLT))
22256 enum rtx_code or1, or2;
22257 rtx or1_rtx, or2_rtx, compare2_rtx;
22258 rtx or_result = gen_reg_rtx (CCEQmode);
22262 case LE: or1 = LT; or2 = EQ; break;
22263 case GE: or1 = GT; or2 = EQ; break;
22264 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
22265 case LTGT: or1 = LT; or2 = GT; break;
22266 case UNGT: or1 = UNORDERED; or2 = GT; break;
22267 case UNLT: or1 = UNORDERED; or2 = LT; break;
22268 default: gcc_unreachable ();
22270 validate_condition_mode (or1, comp_mode);
22271 validate_condition_mode (or2, comp_mode);
22272 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
22273 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
22274 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
22275 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
22277 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
22279 compare_result = or_result;
22283 validate_condition_mode (code, GET_MODE (compare_result));
22285 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
22289 /* Return the diagnostic message string if the binary operation OP is
22290 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22293 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
22297 machine_mode mode1 = TYPE_MODE (type1);
22298 machine_mode mode2 = TYPE_MODE (type2);
22300 /* For complex modes, use the inner type. */
22301 if (COMPLEX_MODE_P (mode1))
22302 mode1 = GET_MODE_INNER (mode1);
22304 if (COMPLEX_MODE_P (mode2))
22305 mode2 = GET_MODE_INNER (mode2);
22307 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22308 double to intermix unless -mfloat128-convert. */
22309 if (mode1 == mode2)
22312 if (!TARGET_FLOAT128_CVT)
22314 if ((mode1 == KFmode && mode2 == IFmode)
22315 || (mode1 == IFmode && mode2 == KFmode))
22316 return N_("__float128 and __ibm128 cannot be used in the same "
22319 if (TARGET_IEEEQUAD
22320 && ((mode1 == IFmode && mode2 == TFmode)
22321 || (mode1 == TFmode && mode2 == IFmode)))
22322 return N_("__ibm128 and long double cannot be used in the same "
22325 if (!TARGET_IEEEQUAD
22326 && ((mode1 == KFmode && mode2 == TFmode)
22327 || (mode1 == TFmode && mode2 == KFmode)))
22328 return N_("__float128 and long double cannot be used in the same "
22336 /* Expand floating point conversion to/from __float128 and __ibm128. */
22339 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
22341 machine_mode dest_mode = GET_MODE (dest);
22342 machine_mode src_mode = GET_MODE (src);
22343 convert_optab cvt = unknown_optab;
22344 bool do_move = false;
22345 rtx libfunc = NULL_RTX;
22347 typedef rtx (*rtx_2func_t) (rtx, rtx);
22348 rtx_2func_t hw_convert = (rtx_2func_t)0;
22352 rtx_2func_t from_df;
22353 rtx_2func_t from_sf;
22354 rtx_2func_t from_si_sign;
22355 rtx_2func_t from_si_uns;
22356 rtx_2func_t from_di_sign;
22357 rtx_2func_t from_di_uns;
22360 rtx_2func_t to_si_sign;
22361 rtx_2func_t to_si_uns;
22362 rtx_2func_t to_di_sign;
22363 rtx_2func_t to_di_uns;
22364 } hw_conversions[2] = {
22365 /* convertions to/from KFmode */
22367 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
22368 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
22369 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
22370 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
22371 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
22372 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
22373 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
22374 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
22375 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
22376 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
22377 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
22378 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
22381 /* convertions to/from TFmode */
22383 gen_extenddftf2_hw, /* TFmode <- DFmode. */
22384 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22385 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22386 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22387 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22388 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22389 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22390 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22391 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22392 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22393 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22394 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22398 if (dest_mode == src_mode)
22399 gcc_unreachable ();
22401 /* Eliminate memory operations. */
22403 src = force_reg (src_mode, src);
22407 rtx tmp = gen_reg_rtx (dest_mode);
22408 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22409 rs6000_emit_move (dest, tmp, dest_mode);
22413 /* Convert to IEEE 128-bit floating point. */
22414 if (FLOAT128_IEEE_P (dest_mode))
22416 if (dest_mode == KFmode)
22418 else if (dest_mode == TFmode)
22421 gcc_unreachable ();
22427 hw_convert = hw_conversions[kf_or_tf].from_df;
22432 hw_convert = hw_conversions[kf_or_tf].from_sf;
22438 if (FLOAT128_IBM_P (src_mode))
22447 cvt = ufloat_optab;
22448 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22452 cvt = sfloat_optab;
22453 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22460 cvt = ufloat_optab;
22461 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22465 cvt = sfloat_optab;
22466 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22471 gcc_unreachable ();
22475 /* Convert from IEEE 128-bit floating point. */
22476 else if (FLOAT128_IEEE_P (src_mode))
22478 if (src_mode == KFmode)
22480 else if (src_mode == TFmode)
22483 gcc_unreachable ();
22489 hw_convert = hw_conversions[kf_or_tf].to_df;
22494 hw_convert = hw_conversions[kf_or_tf].to_sf;
22500 if (FLOAT128_IBM_P (dest_mode))
22510 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22515 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22523 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22528 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22533 gcc_unreachable ();
22537 /* Both IBM format. */
22538 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22542 gcc_unreachable ();
22544 /* Handle conversion between TFmode/KFmode. */
22546 emit_move_insn (dest, gen_lowpart (dest_mode, src));
22548 /* Handle conversion if we have hardware support. */
22549 else if (TARGET_FLOAT128_HW && hw_convert)
22550 emit_insn ((hw_convert) (dest, src));
22552 /* Call an external function to do the conversion. */
22553 else if (cvt != unknown_optab)
22555 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22556 gcc_assert (libfunc != NULL_RTX);
22558 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22561 gcc_assert (dest2 != NULL_RTX);
22562 if (!rtx_equal_p (dest, dest2))
22563 emit_move_insn (dest, dest2);
22567 gcc_unreachable ();
22573 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22574 can be used as that dest register. Return the dest register. */
22577 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22579 if (op2 == const0_rtx)
22582 if (GET_CODE (scratch) == SCRATCH)
22583 scratch = gen_reg_rtx (mode);
22585 if (logical_operand (op2, mode))
22586 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22588 emit_insn (gen_rtx_SET (scratch,
22589 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22595 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22598 machine_mode op_mode;
22599 enum rtx_code cond_code;
22600 rtx result = operands[0];
22602 condition_rtx = rs6000_generate_compare (operands[1], mode);
22603 cond_code = GET_CODE (condition_rtx);
22605 if (cond_code == NE
22606 || cond_code == GE || cond_code == LE
22607 || cond_code == GEU || cond_code == LEU
22608 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22610 rtx not_result = gen_reg_rtx (CCEQmode);
22611 rtx not_op, rev_cond_rtx;
22612 machine_mode cc_mode;
22614 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22616 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22617 SImode, XEXP (condition_rtx, 0), const0_rtx);
22618 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22619 emit_insn (gen_rtx_SET (not_result, not_op));
22620 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22623 op_mode = GET_MODE (XEXP (operands[1], 0));
22624 if (op_mode == VOIDmode)
22625 op_mode = GET_MODE (XEXP (operands[1], 1));
22627 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22629 PUT_MODE (condition_rtx, DImode);
22630 convert_move (result, condition_rtx, 0);
22634 PUT_MODE (condition_rtx, SImode);
22635 emit_insn (gen_rtx_SET (result, condition_rtx));
22639 /* Emit a branch of kind CODE to location LOC. */
22642 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22644 rtx condition_rtx, loc_ref;
22646 condition_rtx = rs6000_generate_compare (operands[0], mode);
22647 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22648 emit_jump_insn (gen_rtx_SET (pc_rtx,
22649 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22650 loc_ref, pc_rtx)));
22653 /* Return the string to output a conditional branch to LABEL, which is
22654 the operand template of the label, or NULL if the branch is really a
22655 conditional return.
22657 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22658 condition code register and its mode specifies what kind of
22659 comparison we made.
22661 REVERSED is nonzero if we should reverse the sense of the comparison.
22663 INSN is the insn. */
22666 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22668 static char string[64];
22669 enum rtx_code code = GET_CODE (op);
22670 rtx cc_reg = XEXP (op, 0);
22671 machine_mode mode = GET_MODE (cc_reg);
22672 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22673 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22674 int really_reversed = reversed ^ need_longbranch;
22680 validate_condition_mode (code, mode);
22682 /* Work out which way this really branches. We could use
22683 reverse_condition_maybe_unordered here always but this
22684 makes the resulting assembler clearer. */
22685 if (really_reversed)
22687 /* Reversal of FP compares takes care -- an ordered compare
22688 becomes an unordered compare and vice versa. */
22689 if (mode == CCFPmode)
22690 code = reverse_condition_maybe_unordered (code);
22692 code = reverse_condition (code);
22697 /* Not all of these are actually distinct opcodes, but
22698 we distinguish them for clarity of the resulting assembler. */
22699 case NE: case LTGT:
22700 ccode = "ne"; break;
22701 case EQ: case UNEQ:
22702 ccode = "eq"; break;
22704 ccode = "ge"; break;
22705 case GT: case GTU: case UNGT:
22706 ccode = "gt"; break;
22708 ccode = "le"; break;
22709 case LT: case LTU: case UNLT:
22710 ccode = "lt"; break;
22711 case UNORDERED: ccode = "un"; break;
22712 case ORDERED: ccode = "nu"; break;
22713 case UNGE: ccode = "nl"; break;
22714 case UNLE: ccode = "ng"; break;
22716 gcc_unreachable ();
22719 /* Maybe we have a guess as to how likely the branch is. */
22721 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22722 if (note != NULL_RTX)
22724 /* PROB is the difference from 50%. */
22725 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22726 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22728 /* Only hint for highly probable/improbable branches on newer cpus when
22729 we have real profile data, as static prediction overrides processor
22730 dynamic prediction. For older cpus we may as well always hint, but
22731 assume not taken for branches that are very close to 50% as a
22732 mispredicted taken branch is more expensive than a
22733 mispredicted not-taken branch. */
22734 if (rs6000_always_hint
22735 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22736 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22737 && br_prob_note_reliable_p (note)))
22739 if (abs (prob) > REG_BR_PROB_BASE / 20
22740 && ((prob > 0) ^ need_longbranch))
22748 s += sprintf (s, "b%slr%s ", ccode, pred);
22750 s += sprintf (s, "b%s%s ", ccode, pred);
22752 /* We need to escape any '%' characters in the reg_names string.
22753 Assume they'd only be the first character.... */
22754 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22756 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22760 /* If the branch distance was too far, we may have to use an
22761 unconditional branch to go the distance. */
22762 if (need_longbranch)
22763 s += sprintf (s, ",$+8\n\tb %s", label);
22765 s += sprintf (s, ",%s", label);
22771 /* Return insn for VSX or Altivec comparisons. */
22774 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22777 machine_mode mode = GET_MODE (op0);
22785 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22796 mask = gen_reg_rtx (mode);
22797 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22804 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22805 DMODE is expected destination mode. This is a recursive function. */
22808 rs6000_emit_vector_compare (enum rtx_code rcode,
22810 machine_mode dmode)
22813 bool swap_operands = false;
22814 bool try_again = false;
22816 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22817 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22819 /* See if the comparison works as is. */
22820 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22828 swap_operands = true;
22833 swap_operands = true;
22841 /* Invert condition and try again.
22842 e.g., A != B becomes ~(A==B). */
22844 enum rtx_code rev_code;
22845 enum insn_code nor_code;
22848 rev_code = reverse_condition_maybe_unordered (rcode);
22849 if (rev_code == UNKNOWN)
22852 nor_code = optab_handler (one_cmpl_optab, dmode);
22853 if (nor_code == CODE_FOR_nothing)
22856 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22860 mask = gen_reg_rtx (dmode);
22861 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22869 /* Try GT/GTU/LT/LTU OR EQ */
22872 enum insn_code ior_code;
22873 enum rtx_code new_code;
22894 gcc_unreachable ();
22897 ior_code = optab_handler (ior_optab, dmode);
22898 if (ior_code == CODE_FOR_nothing)
22901 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22905 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22909 mask = gen_reg_rtx (dmode);
22910 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22921 std::swap (op0, op1);
22923 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22928 /* You only get two chances. */
22932 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22933 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22934 operands for the relation operation COND. */
22937 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22938 rtx cond, rtx cc_op0, rtx cc_op1)
22940 machine_mode dest_mode = GET_MODE (dest);
22941 machine_mode mask_mode = GET_MODE (cc_op0);
22942 enum rtx_code rcode = GET_CODE (cond);
22943 machine_mode cc_mode = CCmode;
22946 bool invert_move = false;
22948 if (VECTOR_UNIT_NONE_P (dest_mode))
22951 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22952 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22956 /* Swap operands if we can, and fall back to doing the operation as
22957 specified, and doing a NOR to invert the test. */
22963 /* Invert condition and try again.
22964 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22965 invert_move = true;
22966 rcode = reverse_condition_maybe_unordered (rcode);
22967 if (rcode == UNKNOWN)
22973 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22975 /* Invert condition to avoid compound test. */
22976 invert_move = true;
22977 rcode = reverse_condition (rcode);
22985 /* Mark unsigned tests with CCUNSmode. */
22986 cc_mode = CCUNSmode;
22988 /* Invert condition to avoid compound test if necessary. */
22989 if (rcode == GEU || rcode == LEU)
22991 invert_move = true;
22992 rcode = reverse_condition (rcode);
23000 /* Get the vector mask for the given relational operations. */
23001 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
23007 std::swap (op_true, op_false);
23009 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
23010 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
23011 && (GET_CODE (op_true) == CONST_VECTOR
23012 || GET_CODE (op_false) == CONST_VECTOR))
23014 rtx constant_0 = CONST0_RTX (dest_mode);
23015 rtx constant_m1 = CONSTM1_RTX (dest_mode);
23017 if (op_true == constant_m1 && op_false == constant_0)
23019 emit_move_insn (dest, mask);
23023 else if (op_true == constant_0 && op_false == constant_m1)
23025 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
23029 /* If we can't use the vector comparison directly, perhaps we can use
23030 the mask for the true or false fields, instead of loading up a
23032 if (op_true == constant_m1)
23035 if (op_false == constant_0)
23039 if (!REG_P (op_true) && !SUBREG_P (op_true))
23040 op_true = force_reg (dest_mode, op_true);
23042 if (!REG_P (op_false) && !SUBREG_P (op_false))
23043 op_false = force_reg (dest_mode, op_false);
23045 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
23046 CONST0_RTX (dest_mode));
23047 emit_insn (gen_rtx_SET (dest,
23048 gen_rtx_IF_THEN_ELSE (dest_mode,
23055 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
23056 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
23057 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
23058 hardware has no such operation. */
23061 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23063 enum rtx_code code = GET_CODE (op);
23064 rtx op0 = XEXP (op, 0);
23065 rtx op1 = XEXP (op, 1);
23066 machine_mode compare_mode = GET_MODE (op0);
23067 machine_mode result_mode = GET_MODE (dest);
23068 bool max_p = false;
23070 if (result_mode != compare_mode)
23073 if (code == GE || code == GT)
23075 else if (code == LE || code == LT)
23080 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
23083 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
23089 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
23093 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
23094 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
23095 operands of the last comparison is nonzero/true, FALSE_COND if it is
23096 zero/false. Return 0 if the hardware has no such operation. */
23099 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23101 enum rtx_code code = GET_CODE (op);
23102 rtx op0 = XEXP (op, 0);
23103 rtx op1 = XEXP (op, 1);
23104 machine_mode result_mode = GET_MODE (dest);
23109 if (!can_create_pseudo_p ())
23122 code = swap_condition (code);
23123 std::swap (op0, op1);
23130 /* Generate: [(parallel [(set (dest)
23131 (if_then_else (op (cmp1) (cmp2))
23134 (clobber (scratch))])]. */
23136 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
23137 cmove_rtx = gen_rtx_SET (dest,
23138 gen_rtx_IF_THEN_ELSE (result_mode,
23143 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
23144 emit_insn (gen_rtx_PARALLEL (VOIDmode,
23145 gen_rtvec (2, cmove_rtx, clobber_rtx)));
23150 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23151 operands of the last comparison is nonzero/true, FALSE_COND if it
23152 is zero/false. Return 0 if the hardware has no such operation. */
23155 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23157 enum rtx_code code = GET_CODE (op);
23158 rtx op0 = XEXP (op, 0);
23159 rtx op1 = XEXP (op, 1);
23160 machine_mode compare_mode = GET_MODE (op0);
23161 machine_mode result_mode = GET_MODE (dest);
23163 bool is_against_zero;
23165 /* These modes should always match. */
23166 if (GET_MODE (op1) != compare_mode
23167 /* In the isel case however, we can use a compare immediate, so
23168 op1 may be a small constant. */
23169 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
23171 if (GET_MODE (true_cond) != result_mode)
23173 if (GET_MODE (false_cond) != result_mode)
23176 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23177 if (TARGET_P9_MINMAX
23178 && (compare_mode == SFmode || compare_mode == DFmode)
23179 && (result_mode == SFmode || result_mode == DFmode))
23181 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
23184 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
23188 /* Don't allow using floating point comparisons for integer results for
23190 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
23193 /* First, work out if the hardware can do this at all, or
23194 if it's too slow.... */
23195 if (!FLOAT_MODE_P (compare_mode))
23198 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
23202 is_against_zero = op1 == CONST0_RTX (compare_mode);
23204 /* A floating-point subtract might overflow, underflow, or produce
23205 an inexact result, thus changing the floating-point flags, so it
23206 can't be generated if we care about that. It's safe if one side
23207 of the construct is zero, since then no subtract will be
23209 if (SCALAR_FLOAT_MODE_P (compare_mode)
23210 && flag_trapping_math && ! is_against_zero)
23213 /* Eliminate half of the comparisons by switching operands, this
23214 makes the remaining code simpler. */
23215 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
23216 || code == LTGT || code == LT || code == UNLE)
23218 code = reverse_condition_maybe_unordered (code);
23220 true_cond = false_cond;
23224 /* UNEQ and LTGT take four instructions for a comparison with zero,
23225 it'll probably be faster to use a branch here too. */
23226 if (code == UNEQ && HONOR_NANS (compare_mode))
23229 /* We're going to try to implement comparisons by performing
23230 a subtract, then comparing against zero. Unfortunately,
23231 Inf - Inf is NaN which is not zero, and so if we don't
23232 know that the operand is finite and the comparison
23233 would treat EQ different to UNORDERED, we can't do it. */
23234 if (HONOR_INFINITIES (compare_mode)
23235 && code != GT && code != UNGE
23236 && (GET_CODE (op1) != CONST_DOUBLE
23237 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
23238 /* Constructs of the form (a OP b ? a : b) are safe. */
23239 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
23240 || (! rtx_equal_p (op0, true_cond)
23241 && ! rtx_equal_p (op1, true_cond))))
23244 /* At this point we know we can use fsel. */
23246 /* Reduce the comparison to a comparison against zero. */
23247 if (! is_against_zero)
23249 temp = gen_reg_rtx (compare_mode);
23250 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
23252 op1 = CONST0_RTX (compare_mode);
23255 /* If we don't care about NaNs we can reduce some of the comparisons
23256 down to faster ones. */
23257 if (! HONOR_NANS (compare_mode))
23263 true_cond = false_cond;
23276 /* Now, reduce everything down to a GE. */
23283 temp = gen_reg_rtx (compare_mode);
23284 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23289 temp = gen_reg_rtx (compare_mode);
23290 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
23295 temp = gen_reg_rtx (compare_mode);
23296 emit_insn (gen_rtx_SET (temp,
23297 gen_rtx_NEG (compare_mode,
23298 gen_rtx_ABS (compare_mode, op0))));
23303 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23304 temp = gen_reg_rtx (result_mode);
23305 emit_insn (gen_rtx_SET (temp,
23306 gen_rtx_IF_THEN_ELSE (result_mode,
23307 gen_rtx_GE (VOIDmode,
23309 true_cond, false_cond)));
23310 false_cond = true_cond;
23313 temp = gen_reg_rtx (compare_mode);
23314 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23319 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23320 temp = gen_reg_rtx (result_mode);
23321 emit_insn (gen_rtx_SET (temp,
23322 gen_rtx_IF_THEN_ELSE (result_mode,
23323 gen_rtx_GE (VOIDmode,
23325 true_cond, false_cond)));
23326 true_cond = false_cond;
23329 temp = gen_reg_rtx (compare_mode);
23330 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23335 gcc_unreachable ();
23338 emit_insn (gen_rtx_SET (dest,
23339 gen_rtx_IF_THEN_ELSE (result_mode,
23340 gen_rtx_GE (VOIDmode,
23342 true_cond, false_cond)));
23346 /* Same as above, but for ints (isel). */
23349 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23351 rtx condition_rtx, cr;
23352 machine_mode mode = GET_MODE (dest);
23353 enum rtx_code cond_code;
23354 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
23357 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
23360 /* We still have to do the compare, because isel doesn't do a
23361 compare, it just looks at the CRx bits set by a previous compare
23363 condition_rtx = rs6000_generate_compare (op, mode);
23364 cond_code = GET_CODE (condition_rtx);
23365 cr = XEXP (condition_rtx, 0);
23366 signedp = GET_MODE (cr) == CCmode;
23368 isel_func = (mode == SImode
23369 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
23370 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
23374 case LT: case GT: case LTU: case GTU: case EQ:
23375 /* isel handles these directly. */
23379 /* We need to swap the sense of the comparison. */
23381 std::swap (false_cond, true_cond);
23382 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23387 false_cond = force_reg (mode, false_cond);
23388 if (true_cond != const0_rtx)
23389 true_cond = force_reg (mode, true_cond);
23391 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23397 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23399 machine_mode mode = GET_MODE (op0);
23403 /* VSX/altivec have direct min/max insns. */
23404 if ((code == SMAX || code == SMIN)
23405 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23406 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23408 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23412 if (code == SMAX || code == SMIN)
23417 if (code == SMAX || code == UMAX)
23418 target = emit_conditional_move (dest, c, op0, op1, mode,
23419 op0, op1, mode, 0);
23421 target = emit_conditional_move (dest, c, op0, op1, mode,
23422 op1, op0, mode, 0);
23423 gcc_assert (target);
23424 if (target != dest)
23425 emit_move_insn (dest, target);
23428 /* Split a signbit operation on 64-bit machines with direct move. Also allow
23429 for the value to come from memory or if it is already loaded into a GPR. */
23432 rs6000_split_signbit (rtx dest, rtx src)
23434 machine_mode d_mode = GET_MODE (dest);
23435 machine_mode s_mode = GET_MODE (src);
23436 rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
23437 rtx shift_reg = dest_di;
23439 gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
23443 rtx mem = (WORDS_BIG_ENDIAN
23444 ? adjust_address (src, DImode, 0)
23445 : adjust_address (src, DImode, 8));
23446 emit_insn (gen_rtx_SET (dest_di, mem));
23451 unsigned int r = reg_or_subregno (src);
23453 if (INT_REGNO_P (r))
23454 shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
23458 /* Generate the special mfvsrd instruction to get it in a GPR. */
23459 gcc_assert (VSX_REGNO_P (r));
23460 if (s_mode == KFmode)
23461 emit_insn (gen_signbitkf2_dm2 (dest_di, src));
23463 emit_insn (gen_signbittf2_dm2 (dest_di, src));
23467 emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
23471 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23472 COND is true. Mark the jump as unlikely to be taken. */
23475 emit_unlikely_jump (rtx cond, rtx label)
23477 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23478 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23479 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23482 /* A subroutine of the atomic operation splitters. Emit a load-locked
23483 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23484 the zero_extend operation. */
23487 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23489 rtx (*fn) (rtx, rtx) = NULL;
23494 fn = gen_load_lockedqi;
23497 fn = gen_load_lockedhi;
23500 if (GET_MODE (mem) == QImode)
23501 fn = gen_load_lockedqi_si;
23502 else if (GET_MODE (mem) == HImode)
23503 fn = gen_load_lockedhi_si;
23505 fn = gen_load_lockedsi;
23508 fn = gen_load_lockeddi;
23511 fn = gen_load_lockedti;
23514 gcc_unreachable ();
23516 emit_insn (fn (reg, mem));
23519 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23520 instruction in MODE. */
23523 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23525 rtx (*fn) (rtx, rtx, rtx) = NULL;
23530 fn = gen_store_conditionalqi;
23533 fn = gen_store_conditionalhi;
23536 fn = gen_store_conditionalsi;
23539 fn = gen_store_conditionaldi;
23542 fn = gen_store_conditionalti;
23545 gcc_unreachable ();
23548 /* Emit sync before stwcx. to address PPC405 Erratum. */
23549 if (PPC405_ERRATUM77)
23550 emit_insn (gen_hwsync ());
23552 emit_insn (fn (res, mem, val));
23555 /* Expand barriers before and after a load_locked/store_cond sequence. */
23558 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23560 rtx addr = XEXP (mem, 0);
23562 if (!legitimate_indirect_address_p (addr, reload_completed)
23563 && !legitimate_indexed_address_p (addr, reload_completed))
23565 addr = force_reg (Pmode, addr);
23566 mem = replace_equiv_address_nv (mem, addr);
23571 case MEMMODEL_RELAXED:
23572 case MEMMODEL_CONSUME:
23573 case MEMMODEL_ACQUIRE:
23575 case MEMMODEL_RELEASE:
23576 case MEMMODEL_ACQ_REL:
23577 emit_insn (gen_lwsync ());
23579 case MEMMODEL_SEQ_CST:
23580 emit_insn (gen_hwsync ());
23583 gcc_unreachable ();
23589 rs6000_post_atomic_barrier (enum memmodel model)
23593 case MEMMODEL_RELAXED:
23594 case MEMMODEL_CONSUME:
23595 case MEMMODEL_RELEASE:
23597 case MEMMODEL_ACQUIRE:
23598 case MEMMODEL_ACQ_REL:
23599 case MEMMODEL_SEQ_CST:
23600 emit_insn (gen_isync ());
23603 gcc_unreachable ();
23607 /* A subroutine of the various atomic expanders. For sub-word operations,
23608 we must adjust things to operate on SImode. Given the original MEM,
23609 return a new aligned memory. Also build and return the quantities by
23610 which to shift and mask. */
23613 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23615 rtx addr, align, shift, mask, mem;
23616 HOST_WIDE_INT shift_mask;
23617 machine_mode mode = GET_MODE (orig_mem);
23619 /* For smaller modes, we have to implement this via SImode. */
23620 shift_mask = (mode == QImode ? 0x18 : 0x10);
23622 addr = XEXP (orig_mem, 0);
23623 addr = force_reg (GET_MODE (addr), addr);
23625 /* Aligned memory containing subword. Generate a new memory. We
23626 do not want any of the existing MEM_ATTR data, as we're now
23627 accessing memory outside the original object. */
23628 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23629 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23630 mem = gen_rtx_MEM (SImode, align);
23631 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23632 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23633 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23635 /* Shift amount for subword relative to aligned word. */
23636 shift = gen_reg_rtx (SImode);
23637 addr = gen_lowpart (SImode, addr);
23638 rtx tmp = gen_reg_rtx (SImode);
23639 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23640 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23641 if (BYTES_BIG_ENDIAN)
23642 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23643 shift, 1, OPTAB_LIB_WIDEN);
23646 /* Mask for insertion. */
23647 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23648 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23654 /* A subroutine of the various atomic expanders. For sub-word operands,
23655 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23658 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23662 x = gen_reg_rtx (SImode);
23663 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23664 gen_rtx_NOT (SImode, mask),
23667 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23672 /* A subroutine of the various atomic expanders. For sub-word operands,
23673 extract WIDE to NARROW via SHIFT. */
23676 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23678 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23679 wide, 1, OPTAB_LIB_WIDEN);
23680 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23683 /* Expand an atomic compare and swap operation. */
23686 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23688 rtx boolval, retval, mem, oldval, newval, cond;
23689 rtx label1, label2, x, mask, shift;
23690 machine_mode mode, orig_mode;
23691 enum memmodel mod_s, mod_f;
23694 boolval = operands[0];
23695 retval = operands[1];
23697 oldval = operands[3];
23698 newval = operands[4];
23699 is_weak = (INTVAL (operands[5]) != 0);
23700 mod_s = memmodel_base (INTVAL (operands[6]));
23701 mod_f = memmodel_base (INTVAL (operands[7]));
23702 orig_mode = mode = GET_MODE (mem);
23704 mask = shift = NULL_RTX;
23705 if (mode == QImode || mode == HImode)
23707 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23708 lwarx and shift/mask operations. With power8, we need to do the
23709 comparison in SImode, but the store is still done in QI/HImode. */
23710 oldval = convert_modes (SImode, mode, oldval, 1);
23712 if (!TARGET_SYNC_HI_QI)
23714 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23716 /* Shift and mask OLDVAL into position with the word. */
23717 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23718 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23720 /* Shift and mask NEWVAL into position within the word. */
23721 newval = convert_modes (SImode, mode, newval, 1);
23722 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23723 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23726 /* Prepare to adjust the return value. */
23727 retval = gen_reg_rtx (SImode);
23730 else if (reg_overlap_mentioned_p (retval, oldval))
23731 oldval = copy_to_reg (oldval);
23733 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23734 oldval = copy_to_mode_reg (mode, oldval);
23736 if (reg_overlap_mentioned_p (retval, newval))
23737 newval = copy_to_reg (newval);
23739 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23744 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23745 emit_label (XEXP (label1, 0));
23747 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23749 emit_load_locked (mode, retval, mem);
23753 x = expand_simple_binop (SImode, AND, retval, mask,
23754 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23756 cond = gen_reg_rtx (CCmode);
23757 /* If we have TImode, synthesize a comparison. */
23758 if (mode != TImode)
23759 x = gen_rtx_COMPARE (CCmode, x, oldval);
23762 rtx xor1_result = gen_reg_rtx (DImode);
23763 rtx xor2_result = gen_reg_rtx (DImode);
23764 rtx or_result = gen_reg_rtx (DImode);
23765 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23766 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23767 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23768 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23770 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23771 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23772 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23773 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23776 emit_insn (gen_rtx_SET (cond, x));
23778 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23779 emit_unlikely_jump (x, label2);
23783 x = rs6000_mask_atomic_subword (retval, newval, mask);
23785 emit_store_conditional (orig_mode, cond, mem, x);
23789 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23790 emit_unlikely_jump (x, label1);
23793 if (!is_mm_relaxed (mod_f))
23794 emit_label (XEXP (label2, 0));
23796 rs6000_post_atomic_barrier (mod_s);
23798 if (is_mm_relaxed (mod_f))
23799 emit_label (XEXP (label2, 0));
23802 rs6000_finish_atomic_subword (operands[1], retval, shift);
23803 else if (mode != GET_MODE (operands[1]))
23804 convert_move (operands[1], retval, 1);
23806 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23807 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23808 emit_insn (gen_rtx_SET (boolval, x));
23811 /* Expand an atomic exchange operation. */
23814 rs6000_expand_atomic_exchange (rtx operands[])
23816 rtx retval, mem, val, cond;
23818 enum memmodel model;
23819 rtx label, x, mask, shift;
23821 retval = operands[0];
23824 model = memmodel_base (INTVAL (operands[3]));
23825 mode = GET_MODE (mem);
23827 mask = shift = NULL_RTX;
23828 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23830 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23832 /* Shift and mask VAL into position with the word. */
23833 val = convert_modes (SImode, mode, val, 1);
23834 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23835 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23837 /* Prepare to adjust the return value. */
23838 retval = gen_reg_rtx (SImode);
23842 mem = rs6000_pre_atomic_barrier (mem, model);
23844 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23845 emit_label (XEXP (label, 0));
23847 emit_load_locked (mode, retval, mem);
23851 x = rs6000_mask_atomic_subword (retval, val, mask);
23853 cond = gen_reg_rtx (CCmode);
23854 emit_store_conditional (mode, cond, mem, x);
23856 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23857 emit_unlikely_jump (x, label);
23859 rs6000_post_atomic_barrier (model);
23862 rs6000_finish_atomic_subword (operands[0], retval, shift);
23865 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23866 to perform. MEM is the memory on which to operate. VAL is the second
23867 operand of the binary operator. BEFORE and AFTER are optional locations to
23868 return the value of MEM either before of after the operation. MODEL_RTX
23869 is a CONST_INT containing the memory model to use. */
23872 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23873 rtx orig_before, rtx orig_after, rtx model_rtx)
23875 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23876 machine_mode mode = GET_MODE (mem);
23877 machine_mode store_mode = mode;
23878 rtx label, x, cond, mask, shift;
23879 rtx before = orig_before, after = orig_after;
23881 mask = shift = NULL_RTX;
23882 /* On power8, we want to use SImode for the operation. On previous systems,
23883 use the operation in a subword and shift/mask to get the proper byte or
23885 if (mode == QImode || mode == HImode)
23887 if (TARGET_SYNC_HI_QI)
23889 val = convert_modes (SImode, mode, val, 1);
23891 /* Prepare to adjust the return value. */
23892 before = gen_reg_rtx (SImode);
23894 after = gen_reg_rtx (SImode);
23899 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23901 /* Shift and mask VAL into position with the word. */
23902 val = convert_modes (SImode, mode, val, 1);
23903 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23904 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23910 /* We've already zero-extended VAL. That is sufficient to
23911 make certain that it does not affect other bits. */
23916 /* If we make certain that all of the other bits in VAL are
23917 set, that will be sufficient to not affect other bits. */
23918 x = gen_rtx_NOT (SImode, mask);
23919 x = gen_rtx_IOR (SImode, x, val);
23920 emit_insn (gen_rtx_SET (val, x));
23927 /* These will all affect bits outside the field and need
23928 adjustment via MASK within the loop. */
23932 gcc_unreachable ();
23935 /* Prepare to adjust the return value. */
23936 before = gen_reg_rtx (SImode);
23938 after = gen_reg_rtx (SImode);
23939 store_mode = mode = SImode;
23943 mem = rs6000_pre_atomic_barrier (mem, model);
23945 label = gen_label_rtx ();
23946 emit_label (label);
23947 label = gen_rtx_LABEL_REF (VOIDmode, label);
23949 if (before == NULL_RTX)
23950 before = gen_reg_rtx (mode);
23952 emit_load_locked (mode, before, mem);
23956 x = expand_simple_binop (mode, AND, before, val,
23957 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23958 after = expand_simple_unop (mode, NOT, x, after, 1);
23962 after = expand_simple_binop (mode, code, before, val,
23963 after, 1, OPTAB_LIB_WIDEN);
23969 x = expand_simple_binop (SImode, AND, after, mask,
23970 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23971 x = rs6000_mask_atomic_subword (before, x, mask);
23973 else if (store_mode != mode)
23974 x = convert_modes (store_mode, mode, x, 1);
23976 cond = gen_reg_rtx (CCmode);
23977 emit_store_conditional (store_mode, cond, mem, x);
23979 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23980 emit_unlikely_jump (x, label);
23982 rs6000_post_atomic_barrier (model);
23986 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23987 then do the calcuations in a SImode register. */
23989 rs6000_finish_atomic_subword (orig_before, before, shift);
23991 rs6000_finish_atomic_subword (orig_after, after, shift);
23993 else if (store_mode != mode)
23995 /* QImode/HImode on machines with lbarx/lharx where we do the native
23996 operation and then do the calcuations in a SImode register. */
23998 convert_move (orig_before, before, 1);
24000 convert_move (orig_after, after, 1);
24002 else if (orig_after && after != orig_after)
24003 emit_move_insn (orig_after, after);
24006 /* Emit instructions to move SRC to DST. Called by splitters for
24007 multi-register moves. It will emit at most one instruction for
24008 each register that is accessed; that is, it won't emit li/lis pairs
24009 (or equivalent for 64-bit code). One of SRC or DST must be a hard
24013 rs6000_split_multireg_move (rtx dst, rtx src)
24015 /* The register number of the first register being moved. */
24017 /* The mode that is to be moved. */
24019 /* The mode that the move is being done in, and its size. */
24020 machine_mode reg_mode;
24022 /* The number of registers that will be moved. */
24025 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
24026 mode = GET_MODE (dst);
24027 nregs = hard_regno_nregs (reg, mode);
24028 if (FP_REGNO_P (reg))
24029 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
24030 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
24031 else if (ALTIVEC_REGNO_P (reg))
24032 reg_mode = V16QImode;
24034 reg_mode = word_mode;
24035 reg_mode_size = GET_MODE_SIZE (reg_mode);
24037 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
24039 /* TDmode residing in FP registers is special, since the ISA requires that
24040 the lower-numbered word of a register pair is always the most significant
24041 word, even in little-endian mode. This does not match the usual subreg
24042 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
24043 the appropriate constituent registers "by hand" in little-endian mode.
24045 Note we do not need to check for destructive overlap here since TDmode
24046 can only reside in even/odd register pairs. */
24047 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
24052 for (i = 0; i < nregs; i++)
24054 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
24055 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
24057 p_src = simplify_gen_subreg (reg_mode, src, mode,
24058 i * reg_mode_size);
24060 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
24061 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
24063 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
24064 i * reg_mode_size);
24066 emit_insn (gen_rtx_SET (p_dst, p_src));
24072 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
24074 /* Move register range backwards, if we might have destructive
24077 for (i = nregs - 1; i >= 0; i--)
24078 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24079 i * reg_mode_size),
24080 simplify_gen_subreg (reg_mode, src, mode,
24081 i * reg_mode_size)));
24087 bool used_update = false;
24088 rtx restore_basereg = NULL_RTX;
24090 if (MEM_P (src) && INT_REGNO_P (reg))
24094 if (GET_CODE (XEXP (src, 0)) == PRE_INC
24095 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
24098 breg = XEXP (XEXP (src, 0), 0);
24099 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
24100 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
24101 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
24102 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24103 src = replace_equiv_address (src, breg);
24105 else if (! rs6000_offsettable_memref_p (src, reg_mode))
24107 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
24109 rtx basereg = XEXP (XEXP (src, 0), 0);
24112 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
24113 emit_insn (gen_rtx_SET (ndst,
24114 gen_rtx_MEM (reg_mode,
24116 used_update = true;
24119 emit_insn (gen_rtx_SET (basereg,
24120 XEXP (XEXP (src, 0), 1)));
24121 src = replace_equiv_address (src, basereg);
24125 rtx basereg = gen_rtx_REG (Pmode, reg);
24126 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
24127 src = replace_equiv_address (src, basereg);
24131 breg = XEXP (src, 0);
24132 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
24133 breg = XEXP (breg, 0);
24135 /* If the base register we are using to address memory is
24136 also a destination reg, then change that register last. */
24138 && REGNO (breg) >= REGNO (dst)
24139 && REGNO (breg) < REGNO (dst) + nregs)
24140 j = REGNO (breg) - REGNO (dst);
24142 else if (MEM_P (dst) && INT_REGNO_P (reg))
24146 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
24147 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
24150 breg = XEXP (XEXP (dst, 0), 0);
24151 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
24152 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
24153 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
24155 /* We have to update the breg before doing the store.
24156 Use store with update, if available. */
24160 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24161 emit_insn (TARGET_32BIT
24162 ? (TARGET_POWERPC64
24163 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
24164 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
24165 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
24166 used_update = true;
24169 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24170 dst = replace_equiv_address (dst, breg);
24172 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
24173 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
24175 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
24177 rtx basereg = XEXP (XEXP (dst, 0), 0);
24180 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24181 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
24184 used_update = true;
24187 emit_insn (gen_rtx_SET (basereg,
24188 XEXP (XEXP (dst, 0), 1)));
24189 dst = replace_equiv_address (dst, basereg);
24193 rtx basereg = XEXP (XEXP (dst, 0), 0);
24194 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
24195 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
24197 && REG_P (offsetreg)
24198 && REGNO (basereg) != REGNO (offsetreg));
24199 if (REGNO (basereg) == 0)
24201 rtx tmp = offsetreg;
24202 offsetreg = basereg;
24205 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
24206 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
24207 dst = replace_equiv_address (dst, basereg);
24210 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
24211 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
24214 for (i = 0; i < nregs; i++)
24216 /* Calculate index to next subword. */
24221 /* If compiler already emitted move of first word by
24222 store with update, no need to do anything. */
24223 if (j == 0 && used_update)
24226 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24227 j * reg_mode_size),
24228 simplify_gen_subreg (reg_mode, src, mode,
24229 j * reg_mode_size)));
24231 if (restore_basereg != NULL_RTX)
24232 emit_insn (restore_basereg);
24237 /* This page contains routines that are used to determine what the
24238 function prologue and epilogue code will do and write them out. */
24240 /* Determine whether the REG is really used. */
24243 save_reg_p (int reg)
24245 /* We need to mark the PIC offset register live for the same conditions
24246 as it is set up, or otherwise it won't be saved before we clobber it. */
24248 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
24250 /* When calling eh_return, we must return true for all the cases
24251 where conditional_register_usage marks the PIC offset reg
24253 if (TARGET_TOC && TARGET_MINIMAL_TOC
24254 && (crtl->calls_eh_return
24255 || df_regs_ever_live_p (reg)
24256 || !constant_pool_empty_p ()))
24259 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
24264 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
24267 /* Return the first fixed-point register that is required to be
24268 saved. 32 if none. */
24271 first_reg_to_save (void)
24275 /* Find lowest numbered live register. */
24276 for (first_reg = 13; first_reg <= 31; first_reg++)
24277 if (save_reg_p (first_reg))
24282 && crtl->uses_pic_offset_table
24283 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
24284 return RS6000_PIC_OFFSET_TABLE_REGNUM;
24290 /* Similar, for FP regs. */
24293 first_fp_reg_to_save (void)
24297 /* Find lowest numbered live register. */
24298 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
24299 if (save_reg_p (first_reg))
24305 /* Similar, for AltiVec regs. */
24308 first_altivec_reg_to_save (void)
24312 /* Stack frame remains as is unless we are in AltiVec ABI. */
24313 if (! TARGET_ALTIVEC_ABI)
24314 return LAST_ALTIVEC_REGNO + 1;
24316 /* On Darwin, the unwind routines are compiled without
24317 TARGET_ALTIVEC, and use save_world to save/restore the
24318 altivec registers when necessary. */
24319 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24320 && ! TARGET_ALTIVEC)
24321 return FIRST_ALTIVEC_REGNO + 20;
24323 /* Find lowest numbered live register. */
24324 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
24325 if (save_reg_p (i))
24331 /* Return a 32-bit mask of the AltiVec registers we need to set in
24332 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24333 the 32-bit word is 0. */
24335 static unsigned int
24336 compute_vrsave_mask (void)
24338 unsigned int i, mask = 0;
24340 /* On Darwin, the unwind routines are compiled without
24341 TARGET_ALTIVEC, and use save_world to save/restore the
24342 call-saved altivec registers when necessary. */
24343 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24344 && ! TARGET_ALTIVEC)
24347 /* First, find out if we use _any_ altivec registers. */
24348 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
24349 if (df_regs_ever_live_p (i))
24350 mask |= ALTIVEC_REG_BIT (i);
24355 /* Next, remove the argument registers from the set. These must
24356 be in the VRSAVE mask set by the caller, so we don't need to add
24357 them in again. More importantly, the mask we compute here is
24358 used to generate CLOBBERs in the set_vrsave insn, and we do not
24359 wish the argument registers to die. */
24360 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
24361 mask &= ~ALTIVEC_REG_BIT (i);
24363 /* Similarly, remove the return value from the set. */
24366 diddle_return_value (is_altivec_return_reg, &yes);
24368 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
24374 /* For a very restricted set of circumstances, we can cut down the
24375 size of prologues/epilogues by calling our own save/restore-the-world
24379 compute_save_world_info (rs6000_stack_t *info)
24381 info->world_save_p = 1;
24383 = (WORLD_SAVE_P (info)
24384 && DEFAULT_ABI == ABI_DARWIN
24385 && !cfun->has_nonlocal_label
24386 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
24387 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
24388 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
24389 && info->cr_save_p);
24391 /* This will not work in conjunction with sibcalls. Make sure there
24392 are none. (This check is expensive, but seldom executed.) */
24393 if (WORLD_SAVE_P (info))
24396 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
24397 if (CALL_P (insn) && SIBLING_CALL_P (insn))
24399 info->world_save_p = 0;
24404 if (WORLD_SAVE_P (info))
24406 /* Even if we're not touching VRsave, make sure there's room on the
24407 stack for it, if it looks like we're calling SAVE_WORLD, which
24408 will attempt to save it. */
24409 info->vrsave_size = 4;
24411 /* If we are going to save the world, we need to save the link register too. */
24412 info->lr_save_p = 1;
24414 /* "Save" the VRsave register too if we're saving the world. */
24415 if (info->vrsave_mask == 0)
24416 info->vrsave_mask = compute_vrsave_mask ();
24418 /* Because the Darwin register save/restore routines only handle
24419 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24421 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
24422 && (info->first_altivec_reg_save
24423 >= FIRST_SAVED_ALTIVEC_REGNO));
24431 is_altivec_return_reg (rtx reg, void *xyes)
24433 bool *yes = (bool *) xyes;
24434 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24439 /* Return whether REG is a global user reg or has been specifed by
24440 -ffixed-REG. We should not restore these, and so cannot use
24441 lmw or out-of-line restore functions if there are any. We also
24442 can't save them (well, emit frame notes for them), because frame
24443 unwinding during exception handling will restore saved registers. */
24446 fixed_reg_p (int reg)
24448 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24449 backend sets it, overriding anything the user might have given. */
24450 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24451 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24452 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24453 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24456 return fixed_regs[reg];
24459 /* Determine the strategy for savings/restoring registers. */
24462 SAVE_MULTIPLE = 0x1,
24463 SAVE_INLINE_GPRS = 0x2,
24464 SAVE_INLINE_FPRS = 0x4,
24465 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24466 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24467 SAVE_INLINE_VRS = 0x20,
24468 REST_MULTIPLE = 0x100,
24469 REST_INLINE_GPRS = 0x200,
24470 REST_INLINE_FPRS = 0x400,
24471 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24472 REST_INLINE_VRS = 0x1000
24476 rs6000_savres_strategy (rs6000_stack_t *info,
24477 bool using_static_chain_p)
24481 /* Select between in-line and out-of-line save and restore of regs.
24482 First, all the obvious cases where we don't use out-of-line. */
24483 if (crtl->calls_eh_return
24484 || cfun->machine->ra_need_lr)
24485 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24486 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24487 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24489 if (info->first_gp_reg_save == 32)
24490 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24492 if (info->first_fp_reg_save == 64
24493 /* The out-of-line FP routines use double-precision stores;
24494 we can't use those routines if we don't have such stores. */
24495 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
24496 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24498 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24499 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24501 /* Define cutoff for using out-of-line functions to save registers. */
24502 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24504 if (!optimize_size)
24506 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24507 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24508 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24512 /* Prefer out-of-line restore if it will exit. */
24513 if (info->first_fp_reg_save > 61)
24514 strategy |= SAVE_INLINE_FPRS;
24515 if (info->first_gp_reg_save > 29)
24517 if (info->first_fp_reg_save == 64)
24518 strategy |= SAVE_INLINE_GPRS;
24520 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24522 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24523 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24526 else if (DEFAULT_ABI == ABI_DARWIN)
24528 if (info->first_fp_reg_save > 60)
24529 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24530 if (info->first_gp_reg_save > 29)
24531 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24532 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24536 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24537 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24538 || info->first_fp_reg_save > 61)
24539 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24540 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24541 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24544 /* Don't bother to try to save things out-of-line if r11 is occupied
24545 by the static chain. It would require too much fiddling and the
24546 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24547 pointer on Darwin, and AIX uses r1 or r12. */
24548 if (using_static_chain_p
24549 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24550 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24552 | SAVE_INLINE_VRS);
24554 /* Don't ever restore fixed regs. That means we can't use the
24555 out-of-line register restore functions if a fixed reg is in the
24556 range of regs restored. */
24557 if (!(strategy & REST_INLINE_FPRS))
24558 for (int i = info->first_fp_reg_save; i < 64; i++)
24561 strategy |= REST_INLINE_FPRS;
24565 /* We can only use the out-of-line routines to restore fprs if we've
24566 saved all the registers from first_fp_reg_save in the prologue.
24567 Otherwise, we risk loading garbage. Of course, if we have saved
24568 out-of-line then we know we haven't skipped any fprs. */
24569 if ((strategy & SAVE_INLINE_FPRS)
24570 && !(strategy & REST_INLINE_FPRS))
24571 for (int i = info->first_fp_reg_save; i < 64; i++)
24572 if (!save_reg_p (i))
24574 strategy |= REST_INLINE_FPRS;
24578 /* Similarly, for altivec regs. */
24579 if (!(strategy & REST_INLINE_VRS))
24580 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24583 strategy |= REST_INLINE_VRS;
24587 if ((strategy & SAVE_INLINE_VRS)
24588 && !(strategy & REST_INLINE_VRS))
24589 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24590 if (!save_reg_p (i))
24592 strategy |= REST_INLINE_VRS;
24596 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24597 saved is an out-of-line save or restore. Set up the value for
24598 the next test (excluding out-of-line gprs). */
24599 bool lr_save_p = (info->lr_save_p
24600 || !(strategy & SAVE_INLINE_FPRS)
24601 || !(strategy & SAVE_INLINE_VRS)
24602 || !(strategy & REST_INLINE_FPRS)
24603 || !(strategy & REST_INLINE_VRS));
24605 if (TARGET_MULTIPLE
24606 && !TARGET_POWERPC64
24607 && info->first_gp_reg_save < 31
24608 && !(flag_shrink_wrap
24609 && flag_shrink_wrap_separate
24610 && optimize_function_for_speed_p (cfun)))
24613 for (int i = info->first_gp_reg_save; i < 32; i++)
24614 if (save_reg_p (i))
24618 /* Don't use store multiple if only one reg needs to be
24619 saved. This can occur for example when the ABI_V4 pic reg
24620 (r30) needs to be saved to make calls, but r31 is not
24622 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24625 /* Prefer store multiple for saves over out-of-line
24626 routines, since the store-multiple instruction will
24627 always be smaller. */
24628 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24630 /* The situation is more complicated with load multiple.
24631 We'd prefer to use the out-of-line routines for restores,
24632 since the "exit" out-of-line routines can handle the
24633 restore of LR and the frame teardown. However if doesn't
24634 make sense to use the out-of-line routine if that is the
24635 only reason we'd need to save LR, and we can't use the
24636 "exit" out-of-line gpr restore if we have saved some
24637 fprs; In those cases it is advantageous to use load
24638 multiple when available. */
24639 if (info->first_fp_reg_save != 64 || !lr_save_p)
24640 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24644 /* Using the "exit" out-of-line routine does not improve code size
24645 if using it would require lr to be saved and if only saving one
24647 else if (!lr_save_p && info->first_gp_reg_save > 29)
24648 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24650 /* Don't ever restore fixed regs. */
24651 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24652 for (int i = info->first_gp_reg_save; i < 32; i++)
24653 if (fixed_reg_p (i))
24655 strategy |= REST_INLINE_GPRS;
24656 strategy &= ~REST_MULTIPLE;
24660 /* We can only use load multiple or the out-of-line routines to
24661 restore gprs if we've saved all the registers from
24662 first_gp_reg_save. Otherwise, we risk loading garbage.
24663 Of course, if we have saved out-of-line or used stmw then we know
24664 we haven't skipped any gprs. */
24665 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24666 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24667 for (int i = info->first_gp_reg_save; i < 32; i++)
24668 if (!save_reg_p (i))
24670 strategy |= REST_INLINE_GPRS;
24671 strategy &= ~REST_MULTIPLE;
24675 if (TARGET_ELF && TARGET_64BIT)
24677 if (!(strategy & SAVE_INLINE_FPRS))
24678 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24679 else if (!(strategy & SAVE_INLINE_GPRS)
24680 && info->first_fp_reg_save == 64)
24681 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24683 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24684 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24686 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24687 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24692 /* Calculate the stack information for the current function. This is
24693 complicated by having two separate calling sequences, the AIX calling
24694 sequence and the V.4 calling sequence.
24696 AIX (and Darwin/Mac OS X) stack frames look like:
24698 SP----> +---------------------------------------+
24699 | back chain to caller | 0 0
24700 +---------------------------------------+
24701 | saved CR | 4 8 (8-11)
24702 +---------------------------------------+
24704 +---------------------------------------+
24705 | reserved for compilers | 12 24
24706 +---------------------------------------+
24707 | reserved for binders | 16 32
24708 +---------------------------------------+
24709 | saved TOC pointer | 20 40
24710 +---------------------------------------+
24711 | Parameter save area (+padding*) (P) | 24 48
24712 +---------------------------------------+
24713 | Alloca space (A) | 24+P etc.
24714 +---------------------------------------+
24715 | Local variable space (L) | 24+P+A
24716 +---------------------------------------+
24717 | Float/int conversion temporary (X) | 24+P+A+L
24718 +---------------------------------------+
24719 | Save area for AltiVec registers (W) | 24+P+A+L+X
24720 +---------------------------------------+
24721 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24722 +---------------------------------------+
24723 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24724 +---------------------------------------+
24725 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24726 +---------------------------------------+
24727 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24728 +---------------------------------------+
24729 old SP->| back chain to caller's caller |
24730 +---------------------------------------+
24732 * If the alloca area is present, the parameter save area is
24733 padded so that the former starts 16-byte aligned.
24735 The required alignment for AIX configurations is two words (i.e., 8
24738 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24740 SP----> +---------------------------------------+
24741 | Back chain to caller | 0
24742 +---------------------------------------+
24743 | Save area for CR | 8
24744 +---------------------------------------+
24746 +---------------------------------------+
24747 | Saved TOC pointer | 24
24748 +---------------------------------------+
24749 | Parameter save area (+padding*) (P) | 32
24750 +---------------------------------------+
24751 | Alloca space (A) | 32+P
24752 +---------------------------------------+
24753 | Local variable space (L) | 32+P+A
24754 +---------------------------------------+
24755 | Save area for AltiVec registers (W) | 32+P+A+L
24756 +---------------------------------------+
24757 | AltiVec alignment padding (Y) | 32+P+A+L+W
24758 +---------------------------------------+
24759 | Save area for GP registers (G) | 32+P+A+L+W+Y
24760 +---------------------------------------+
24761 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24762 +---------------------------------------+
24763 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24764 +---------------------------------------+
24766 * If the alloca area is present, the parameter save area is
24767 padded so that the former starts 16-byte aligned.
24769 V.4 stack frames look like:
24771 SP----> +---------------------------------------+
24772 | back chain to caller | 0
24773 +---------------------------------------+
24774 | caller's saved LR | 4
24775 +---------------------------------------+
24776 | Parameter save area (+padding*) (P) | 8
24777 +---------------------------------------+
24778 | Alloca space (A) | 8+P
24779 +---------------------------------------+
24780 | Varargs save area (V) | 8+P+A
24781 +---------------------------------------+
24782 | Local variable space (L) | 8+P+A+V
24783 +---------------------------------------+
24784 | Float/int conversion temporary (X) | 8+P+A+V+L
24785 +---------------------------------------+
24786 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24787 +---------------------------------------+
24788 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24789 +---------------------------------------+
24790 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24791 +---------------------------------------+
24792 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24793 +---------------------------------------+
24794 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24795 +---------------------------------------+
24796 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24797 +---------------------------------------+
24798 old SP->| back chain to caller's caller |
24799 +---------------------------------------+
24801 * If the alloca area is present and the required alignment is
24802 16 bytes, the parameter save area is padded so that the
24803 alloca area starts 16-byte aligned.
24805 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24806 given. (But note below and in sysv4.h that we require only 8 and
24807 may round up the size of our stack frame anyways. The historical
24808 reason is early versions of powerpc-linux which didn't properly
24809 align the stack at program startup. A happy side-effect is that
24810 -mno-eabi libraries can be used with -meabi programs.)
24812 The EABI configuration defaults to the V.4 layout. However,
24813 the stack alignment requirements may differ. If -mno-eabi is not
24814 given, the required stack alignment is 8 bytes; if -mno-eabi is
24815 given, the required alignment is 16 bytes. (But see V.4 comment
24818 #ifndef ABI_STACK_BOUNDARY
24819 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24822 static rs6000_stack_t *
24823 rs6000_stack_info (void)
24825 /* We should never be called for thunks, we are not set up for that. */
24826 gcc_assert (!cfun->is_thunk);
24828 rs6000_stack_t *info = &stack_info;
24829 int reg_size = TARGET_32BIT ? 4 : 8;
24834 HOST_WIDE_INT non_fixed_size;
24835 bool using_static_chain_p;
24837 if (reload_completed && info->reload_completed)
24840 memset (info, 0, sizeof (*info));
24841 info->reload_completed = reload_completed;
24843 /* Select which calling sequence. */
24844 info->abi = DEFAULT_ABI;
24846 /* Calculate which registers need to be saved & save area size. */
24847 info->first_gp_reg_save = first_reg_to_save ();
24848 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24849 even if it currently looks like we won't. Reload may need it to
24850 get at a constant; if so, it will have already created a constant
24851 pool entry for it. */
24852 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24853 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24854 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24855 && crtl->uses_const_pool
24856 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24857 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24859 first_gp = info->first_gp_reg_save;
24861 info->gp_size = reg_size * (32 - first_gp);
24863 info->first_fp_reg_save = first_fp_reg_to_save ();
24864 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24866 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24867 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24868 - info->first_altivec_reg_save);
24870 /* Does this function call anything? */
24871 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24873 /* Determine if we need to save the condition code registers. */
24874 if (save_reg_p (CR2_REGNO)
24875 || save_reg_p (CR3_REGNO)
24876 || save_reg_p (CR4_REGNO))
24878 info->cr_save_p = 1;
24879 if (DEFAULT_ABI == ABI_V4)
24880 info->cr_size = reg_size;
24883 /* If the current function calls __builtin_eh_return, then we need
24884 to allocate stack space for registers that will hold data for
24885 the exception handler. */
24886 if (crtl->calls_eh_return)
24889 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24892 ehrd_size = i * UNITS_PER_WORD;
24897 /* In the ELFv2 ABI, we also need to allocate space for separate
24898 CR field save areas if the function calls __builtin_eh_return. */
24899 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24901 /* This hard-codes that we have three call-saved CR fields. */
24902 ehcr_size = 3 * reg_size;
24903 /* We do *not* use the regular CR save mechanism. */
24904 info->cr_save_p = 0;
24909 /* Determine various sizes. */
24910 info->reg_size = reg_size;
24911 info->fixed_size = RS6000_SAVE_AREA;
24912 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24913 if (cfun->calls_alloca)
24915 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24916 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24918 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24919 TARGET_ALTIVEC ? 16 : 8);
24920 if (FRAME_GROWS_DOWNWARD)
24922 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24923 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24924 - (info->fixed_size + info->vars_size + info->parm_size);
24926 if (TARGET_ALTIVEC_ABI)
24927 info->vrsave_mask = compute_vrsave_mask ();
24929 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24930 info->vrsave_size = 4;
24932 compute_save_world_info (info);
24934 /* Calculate the offsets. */
24935 switch (DEFAULT_ABI)
24939 gcc_unreachable ();
24944 info->fp_save_offset = -info->fp_size;
24945 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24947 if (TARGET_ALTIVEC_ABI)
24949 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24951 /* Align stack so vector save area is on a quadword boundary.
24952 The padding goes above the vectors. */
24953 if (info->altivec_size != 0)
24954 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24956 info->altivec_save_offset = info->vrsave_save_offset
24957 - info->altivec_padding_size
24958 - info->altivec_size;
24959 gcc_assert (info->altivec_size == 0
24960 || info->altivec_save_offset % 16 == 0);
24962 /* Adjust for AltiVec case. */
24963 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24966 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24968 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24969 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24970 info->lr_save_offset = 2*reg_size;
24974 info->fp_save_offset = -info->fp_size;
24975 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24976 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24978 if (TARGET_ALTIVEC_ABI)
24980 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24982 /* Align stack so vector save area is on a quadword boundary. */
24983 if (info->altivec_size != 0)
24984 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24986 info->altivec_save_offset = info->vrsave_save_offset
24987 - info->altivec_padding_size
24988 - info->altivec_size;
24990 /* Adjust for AltiVec case. */
24991 info->ehrd_offset = info->altivec_save_offset;
24994 info->ehrd_offset = info->cr_save_offset;
24996 info->ehrd_offset -= ehrd_size;
24997 info->lr_save_offset = reg_size;
25000 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
25001 info->save_size = RS6000_ALIGN (info->fp_size
25003 + info->altivec_size
25004 + info->altivec_padding_size
25008 + info->vrsave_size,
25011 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
25013 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
25014 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
25016 /* Determine if we need to save the link register. */
25018 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25020 && !TARGET_PROFILE_KERNEL)
25021 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
25022 #ifdef TARGET_RELOCATABLE
25023 || (DEFAULT_ABI == ABI_V4
25024 && (TARGET_RELOCATABLE || flag_pic > 1)
25025 && !constant_pool_empty_p ())
25027 || rs6000_ra_ever_killed ())
25028 info->lr_save_p = 1;
25030 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
25031 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
25032 && call_used_regs[STATIC_CHAIN_REGNUM]);
25033 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
25035 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
25036 || !(info->savres_strategy & SAVE_INLINE_FPRS)
25037 || !(info->savres_strategy & SAVE_INLINE_VRS)
25038 || !(info->savres_strategy & REST_INLINE_GPRS)
25039 || !(info->savres_strategy & REST_INLINE_FPRS)
25040 || !(info->savres_strategy & REST_INLINE_VRS))
25041 info->lr_save_p = 1;
25043 if (info->lr_save_p)
25044 df_set_regs_ever_live (LR_REGNO, true);
25046 /* Determine if we need to allocate any stack frame:
25048 For AIX we need to push the stack if a frame pointer is needed
25049 (because the stack might be dynamically adjusted), if we are
25050 debugging, if we make calls, or if the sum of fp_save, gp_save,
25051 and local variables are more than the space needed to save all
25052 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
25053 + 18*8 = 288 (GPR13 reserved).
25055 For V.4 we don't have the stack cushion that AIX uses, but assume
25056 that the debugger can handle stackless frames. */
25061 else if (DEFAULT_ABI == ABI_V4)
25062 info->push_p = non_fixed_size != 0;
25064 else if (frame_pointer_needed)
25067 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
25071 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
25077 debug_stack_info (rs6000_stack_t *info)
25079 const char *abi_string;
25082 info = rs6000_stack_info ();
25084 fprintf (stderr, "\nStack information for function %s:\n",
25085 ((current_function_decl && DECL_NAME (current_function_decl))
25086 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
25091 default: abi_string = "Unknown"; break;
25092 case ABI_NONE: abi_string = "NONE"; break;
25093 case ABI_AIX: abi_string = "AIX"; break;
25094 case ABI_ELFv2: abi_string = "ELFv2"; break;
25095 case ABI_DARWIN: abi_string = "Darwin"; break;
25096 case ABI_V4: abi_string = "V.4"; break;
25099 fprintf (stderr, "\tABI = %5s\n", abi_string);
25101 if (TARGET_ALTIVEC_ABI)
25102 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
25104 if (info->first_gp_reg_save != 32)
25105 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
25107 if (info->first_fp_reg_save != 64)
25108 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
25110 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
25111 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
25112 info->first_altivec_reg_save);
25114 if (info->lr_save_p)
25115 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
25117 if (info->cr_save_p)
25118 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
25120 if (info->vrsave_mask)
25121 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
25124 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
25127 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
25130 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
25133 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
25135 if (info->altivec_size)
25136 fprintf (stderr, "\taltivec_save_offset = %5d\n",
25137 info->altivec_save_offset);
25139 if (info->vrsave_size)
25140 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
25141 info->vrsave_save_offset);
25143 if (info->lr_save_p)
25144 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
25146 if (info->cr_save_p)
25147 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
25149 if (info->varargs_save_offset)
25150 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
25152 if (info->total_size)
25153 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25156 if (info->vars_size)
25157 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25160 if (info->parm_size)
25161 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
25163 if (info->fixed_size)
25164 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
25167 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
25170 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
25172 if (info->altivec_size)
25173 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
25175 if (info->vrsave_size)
25176 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
25178 if (info->altivec_padding_size)
25179 fprintf (stderr, "\taltivec_padding_size= %5d\n",
25180 info->altivec_padding_size);
25183 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
25185 if (info->save_size)
25186 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
25188 if (info->reg_size != 4)
25189 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
25191 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
25193 fprintf (stderr, "\n");
25197 rs6000_return_addr (int count, rtx frame)
25199 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25200 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25202 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
25204 cfun->machine->ra_needs_full_frame = 1;
25207 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25208 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25209 frame = stack_pointer_rtx;
25210 rtx prev_frame_addr = memory_address (Pmode, frame);
25211 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
25212 rtx lr_save_off = plus_constant (Pmode,
25213 prev_frame, RETURN_ADDRESS_OFFSET);
25214 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
25215 return gen_rtx_MEM (Pmode, lr_save_addr);
25218 cfun->machine->ra_need_lr = 1;
25219 return get_hard_reg_initial_val (Pmode, LR_REGNO);
25222 /* Say whether a function is a candidate for sibcall handling or not. */
25225 rs6000_function_ok_for_sibcall (tree decl, tree exp)
25230 fntype = TREE_TYPE (decl);
25232 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
25234 /* We can't do it if the called function has more vector parameters
25235 than the current function; there's nowhere to put the VRsave code. */
25236 if (TARGET_ALTIVEC_ABI
25237 && TARGET_ALTIVEC_VRSAVE
25238 && !(decl && decl == current_function_decl))
25240 function_args_iterator args_iter;
25244 /* Functions with vector parameters are required to have a
25245 prototype, so the argument type info must be available
25247 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
25248 if (TREE_CODE (type) == VECTOR_TYPE
25249 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25252 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
25253 if (TREE_CODE (type) == VECTOR_TYPE
25254 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25261 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25262 functions, because the callee may have a different TOC pointer to
25263 the caller and there's no way to ensure we restore the TOC when
25264 we return. With the secure-plt SYSV ABI we can't make non-local
25265 calls when -fpic/PIC because the plt call stubs use r30. */
25266 if (DEFAULT_ABI == ABI_DARWIN
25267 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25269 && !DECL_EXTERNAL (decl)
25270 && !DECL_WEAK (decl)
25271 && (*targetm.binds_local_p) (decl))
25272 || (DEFAULT_ABI == ABI_V4
25273 && (!TARGET_SECURE_PLT
25276 && (*targetm.binds_local_p) (decl)))))
25278 tree attr_list = TYPE_ATTRIBUTES (fntype);
25280 if (!lookup_attribute ("longcall", attr_list)
25281 || lookup_attribute ("shortcall", attr_list))
25289 rs6000_ra_ever_killed (void)
25295 if (cfun->is_thunk)
25298 if (cfun->machine->lr_save_state)
25299 return cfun->machine->lr_save_state - 1;
25301 /* regs_ever_live has LR marked as used if any sibcalls are present,
25302 but this should not force saving and restoring in the
25303 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25304 clobbers LR, so that is inappropriate. */
25306 /* Also, the prologue can generate a store into LR that
25307 doesn't really count, like this:
25310 bcl to set PIC register
25314 When we're called from the epilogue, we need to avoid counting
25315 this as a store. */
25317 push_topmost_sequence ();
25318 top = get_insns ();
25319 pop_topmost_sequence ();
25320 reg = gen_rtx_REG (Pmode, LR_REGNO);
25322 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
25328 if (!SIBLING_CALL_P (insn))
25331 else if (find_regno_note (insn, REG_INC, LR_REGNO))
25333 else if (set_of (reg, insn) != NULL_RTX
25334 && !prologue_epilogue_contains (insn))
25341 /* Emit instructions needed to load the TOC register.
25342 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25343 a constant pool; or for SVR4 -fpic. */
25346 rs6000_emit_load_toc_table (int fromprolog)
25349 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
25351 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
25354 rtx lab, tmp1, tmp2, got;
25356 lab = gen_label_rtx ();
25357 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
25358 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25361 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25365 got = rs6000_got_sym ();
25366 tmp1 = tmp2 = dest;
25369 tmp1 = gen_reg_rtx (Pmode);
25370 tmp2 = gen_reg_rtx (Pmode);
25372 emit_insn (gen_load_toc_v4_PIC_1 (lab));
25373 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
25374 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
25375 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
25377 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
25379 emit_insn (gen_load_toc_v4_pic_si ());
25380 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25382 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
25385 rtx temp0 = (fromprolog
25386 ? gen_rtx_REG (Pmode, 0)
25387 : gen_reg_rtx (Pmode));
25393 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25394 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25396 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25397 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25399 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25400 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25401 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25407 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25409 lab = gen_label_rtx ();
25410 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25411 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25412 if (TARGET_LINK_STACK)
25413 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25414 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25416 emit_insn (gen_addsi3 (dest, temp0, dest));
25418 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25420 /* This is for AIX code running in non-PIC ELF32. */
25421 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25424 emit_insn (gen_elf_high (dest, realsym));
25425 emit_insn (gen_elf_low (dest, dest, realsym));
25429 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25432 emit_insn (gen_load_toc_aix_si (dest));
25434 emit_insn (gen_load_toc_aix_di (dest));
25438 /* Emit instructions to restore the link register after determining where
25439 its value has been stored. */
25442 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25444 rs6000_stack_t *info = rs6000_stack_info ();
25447 operands[0] = source;
25448 operands[1] = scratch;
25450 if (info->lr_save_p)
25452 rtx frame_rtx = stack_pointer_rtx;
25453 HOST_WIDE_INT sp_offset = 0;
25456 if (frame_pointer_needed
25457 || cfun->calls_alloca
25458 || info->total_size > 32767)
25460 tmp = gen_frame_mem (Pmode, frame_rtx);
25461 emit_move_insn (operands[1], tmp);
25462 frame_rtx = operands[1];
25464 else if (info->push_p)
25465 sp_offset = info->total_size;
25467 tmp = plus_constant (Pmode, frame_rtx,
25468 info->lr_save_offset + sp_offset);
25469 tmp = gen_frame_mem (Pmode, tmp);
25470 emit_move_insn (tmp, operands[0]);
25473 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25475 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25476 state of lr_save_p so any change from here on would be a bug. In
25477 particular, stop rs6000_ra_ever_killed from considering the SET
25478 of lr we may have added just above. */
25479 cfun->machine->lr_save_state = info->lr_save_p + 1;
25482 static GTY(()) alias_set_type set = -1;
25485 get_TOC_alias_set (void)
25488 set = new_alias_set ();
25492 /* This returns nonzero if the current function uses the TOC. This is
25493 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25494 is generated by the ABI_V4 load_toc_* patterns.
25495 Return 2 instead of 1 if the load_toc_* pattern is in the function
25496 partition that doesn't start the function. */
25504 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25508 rtx pat = PATTERN (insn);
25511 if (GET_CODE (pat) == PARALLEL)
25512 for (i = 0; i < XVECLEN (pat, 0); i++)
25514 rtx sub = XVECEXP (pat, 0, i);
25515 if (GET_CODE (sub) == USE)
25517 sub = XEXP (sub, 0);
25518 if (GET_CODE (sub) == UNSPEC
25519 && XINT (sub, 1) == UNSPEC_TOC)
25524 else if (crtl->has_bb_partition
25526 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25534 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25536 rtx tocrel, tocreg, hi;
25538 if (TARGET_DEBUG_ADDR)
25540 if (GET_CODE (symbol) == SYMBOL_REF)
25541 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25545 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25546 GET_RTX_NAME (GET_CODE (symbol)));
25547 debug_rtx (symbol);
25551 if (!can_create_pseudo_p ())
25552 df_set_regs_ever_live (TOC_REGISTER, true);
25554 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25555 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25556 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25559 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25560 if (largetoc_reg != NULL)
25562 emit_move_insn (largetoc_reg, hi);
25565 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25568 /* Issue assembly directives that create a reference to the given DWARF
25569 FRAME_TABLE_LABEL from the current function section. */
25571 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25573 fprintf (asm_out_file, "\t.ref %s\n",
25574 (* targetm.strip_name_encoding) (frame_table_label));
25577 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25578 and the change to the stack pointer. */
25581 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25588 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25589 if (hard_frame_needed)
25590 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25591 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25592 || (hard_frame_needed
25593 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25596 p = rtvec_alloc (i);
25599 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25600 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25603 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25606 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25607 and set the appropriate attributes for the generated insn. Return the
25608 first insn which adjusts the stack pointer or the last insn before
25609 the stack adjustment loop.
25611 SIZE_INT is used to create the CFI note for the allocation.
25613 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25614 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25616 ORIG_SP contains the backchain value that must be stored at *sp. */
25619 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25623 rtx size_rtx = GEN_INT (-size_int);
25624 if (size_int > 32767)
25626 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25627 /* Need a note here so that try_split doesn't get confused. */
25628 if (get_last_insn () == NULL_RTX)
25629 emit_note (NOTE_INSN_DELETED);
25630 insn = emit_move_insn (tmp_reg, size_rtx);
25631 try_split (PATTERN (insn), insn, 0);
25632 size_rtx = tmp_reg;
25635 if (Pmode == SImode)
25636 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25641 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
25645 rtx par = PATTERN (insn);
25646 gcc_assert (GET_CODE (par) == PARALLEL);
25647 rtx set = XVECEXP (par, 0, 0);
25648 gcc_assert (GET_CODE (set) == SET);
25649 rtx mem = SET_DEST (set);
25650 gcc_assert (MEM_P (mem));
25651 MEM_NOTRAP_P (mem) = 1;
25652 set_mem_alias_set (mem, get_frame_alias_set ());
25654 RTX_FRAME_RELATED_P (insn) = 1;
25655 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25656 gen_rtx_SET (stack_pointer_rtx,
25657 gen_rtx_PLUS (Pmode,
25659 GEN_INT (-size_int))));
25661 /* Emit a blockage to ensure the allocation/probing insns are
25662 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25663 note for similar reasons. */
25664 if (flag_stack_clash_protection)
25666 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25667 emit_insn (gen_blockage ());
25673 static HOST_WIDE_INT
25674 get_stack_clash_protection_probe_interval (void)
25676 return (HOST_WIDE_INT_1U
25677 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25680 static HOST_WIDE_INT
25681 get_stack_clash_protection_guard_size (void)
25683 return (HOST_WIDE_INT_1U
25684 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25687 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25688 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25690 COPY_REG, if non-null, should contain a copy of the original
25691 stack pointer at exit from this function.
25693 This is subtly different than the Ada probing in that it tries hard to
25694 prevent attacks that jump the stack guard. Thus it is never allowed to
25695 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25696 space without a suitable probe. */
25698 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25701 rtx orig_sp = copy_reg;
25703 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25705 /* Round the size down to a multiple of PROBE_INTERVAL. */
25706 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25708 /* If explicitly requested,
25709 or the rounded size is not the same as the original size
25710 or the the rounded size is greater than a page,
25711 then we will need a copy of the original stack pointer. */
25712 if (rounded_size != orig_size
25713 || rounded_size > probe_interval
25716 /* If the caller did not request a copy of the incoming stack
25717 pointer, then we use r0 to hold the copy. */
25719 orig_sp = gen_rtx_REG (Pmode, 0);
25720 emit_move_insn (orig_sp, stack_pointer_rtx);
25723 /* There's three cases here.
25725 One is a single probe which is the most common and most efficiently
25726 implemented as it does not have to have a copy of the original
25727 stack pointer if there are no residuals.
25729 Second is unrolled allocation/probes which we use if there's just
25730 a few of them. It needs to save the original stack pointer into a
25731 temporary for use as a source register in the allocation/probe.
25733 Last is a loop. This is the most uncommon case and least efficient. */
25734 rtx_insn *retval = NULL;
25735 if (rounded_size == probe_interval)
25737 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25739 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25741 else if (rounded_size <= 8 * probe_interval)
25743 /* The ABI requires using the store with update insns to allocate
25744 space and store the backchain into the stack
25746 So we save the current stack pointer into a temporary, then
25747 emit the store-with-update insns to store the saved stack pointer
25748 into the right location in each new page. */
25749 for (int i = 0; i < rounded_size; i += probe_interval)
25752 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25754 /* Save the first stack adjustment in RETVAL. */
25759 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25763 /* Compute the ending address. */
25765 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25766 rtx rs = GEN_INT (-rounded_size);
25768 if (add_operand (rs, Pmode))
25769 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25772 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25773 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25774 stack_pointer_rtx));
25775 /* Describe the effect of INSN to the CFI engine. */
25776 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25777 gen_rtx_SET (end_addr,
25778 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25781 RTX_FRAME_RELATED_P (insn) = 1;
25783 /* Emit the loop. */
25785 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25786 stack_pointer_rtx, orig_sp,
25789 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25790 stack_pointer_rtx, orig_sp,
25792 RTX_FRAME_RELATED_P (retval) = 1;
25793 /* Describe the effect of INSN to the CFI engine. */
25794 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25795 gen_rtx_SET (stack_pointer_rtx, end_addr));
25797 /* Emit a blockage to ensure the allocation/probing insns are
25798 not optimized, combined, removed, etc. Other cases handle this
25799 within their call to rs6000_emit_allocate_stack_1. */
25800 emit_insn (gen_blockage ());
25802 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25805 if (orig_size != rounded_size)
25807 /* Allocate (and implicitly probe) any residual space. */
25808 HOST_WIDE_INT residual = orig_size - rounded_size;
25810 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25812 /* If the residual was the only allocation, then we can return the
25813 allocating insn. */
25821 /* Emit the correct code for allocating stack space, as insns.
25822 If COPY_REG, make sure a copy of the old frame is left there.
25823 The generated code may use hard register 0 as a temporary. */
25826 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25829 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25830 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25831 rtx todec = gen_int_mode (-size, Pmode);
25833 if (INTVAL (todec) != -size)
25835 warning (0, "stack frame too large");
25836 emit_insn (gen_trap ());
25840 if (crtl->limit_stack)
25842 if (REG_P (stack_limit_rtx)
25843 && REGNO (stack_limit_rtx) > 1
25844 && REGNO (stack_limit_rtx) <= 31)
25847 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25850 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25852 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25854 && DEFAULT_ABI == ABI_V4
25857 rtx toload = gen_rtx_CONST (VOIDmode,
25858 gen_rtx_PLUS (Pmode,
25862 emit_insn (gen_elf_high (tmp_reg, toload));
25863 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25864 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25868 warning (0, "stack limit expression is not supported");
25871 if (flag_stack_clash_protection)
25873 if (size < get_stack_clash_protection_guard_size ())
25874 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25877 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25880 /* If we asked for a copy with an offset, then we still need add in
25882 if (copy_reg && copy_off)
25883 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25891 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25893 emit_move_insn (copy_reg, stack_reg);
25896 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25897 it now and set the alias set/attributes. The above gen_*_update
25898 calls will generate a PARALLEL with the MEM set being the first
25900 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25904 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25906 #if PROBE_INTERVAL > 32768
25907 #error Cannot use indexed addressing mode for stack probing
25910 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25911 inclusive. These are offsets from the current stack pointer. */
25914 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25916 /* See if we have a constant small number of probes to generate. If so,
25917 that's the easy case. */
25918 if (first + size <= 32768)
25922 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25923 it exceeds SIZE. If only one probe is needed, this will not
25924 generate any code. Then probe at FIRST + SIZE. */
25925 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25926 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25929 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25933 /* Otherwise, do the same as above, but in a loop. Note that we must be
25934 extra careful with variables wrapping around because we might be at
25935 the very top (or the very bottom) of the address space and we have
25936 to be able to handle this case properly; in particular, we use an
25937 equality test for the loop condition. */
25940 HOST_WIDE_INT rounded_size;
25941 rtx r12 = gen_rtx_REG (Pmode, 12);
25942 rtx r0 = gen_rtx_REG (Pmode, 0);
25944 /* Sanity check for the addressing mode we're going to use. */
25945 gcc_assert (first <= 32768);
25947 /* Step 1: round SIZE to the previous multiple of the interval. */
25949 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25952 /* Step 2: compute initial and final value of the loop counter. */
25954 /* TEST_ADDR = SP + FIRST. */
25955 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25958 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25959 if (rounded_size > 32768)
25961 emit_move_insn (r0, GEN_INT (-rounded_size));
25962 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25965 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25969 /* Step 3: the loop
25973 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25976 while (TEST_ADDR != LAST_ADDR)
25978 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25979 until it is equal to ROUNDED_SIZE. */
25982 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25984 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25987 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25988 that SIZE is equal to ROUNDED_SIZE. */
25990 if (size != rounded_size)
25991 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25995 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25996 addresses, not offsets. */
25998 static const char *
25999 output_probe_stack_range_1 (rtx reg1, rtx reg2)
26001 static int labelno = 0;
26005 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
26008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
26010 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
26012 xops[1] = GEN_INT (-PROBE_INTERVAL);
26013 output_asm_insn ("addi %0,%0,%1", xops);
26015 /* Probe at TEST_ADDR. */
26016 xops[1] = gen_rtx_REG (Pmode, 0);
26017 output_asm_insn ("stw %1,0(%0)", xops);
26019 /* Test if TEST_ADDR == LAST_ADDR. */
26022 output_asm_insn ("cmpd 0,%0,%1", xops);
26024 output_asm_insn ("cmpw 0,%0,%1", xops);
26027 fputs ("\tbne 0,", asm_out_file);
26028 assemble_name_raw (asm_out_file, loop_lab);
26029 fputc ('\n', asm_out_file);
26034 /* This function is called when rs6000_frame_related is processing
26035 SETs within a PARALLEL, and returns whether the REGNO save ought to
26036 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
26037 for out-of-line register save functions, store multiple, and the
26038 Darwin world_save. They may contain registers that don't really
26042 interesting_frame_related_regno (unsigned int regno)
26044 /* Saves apparently of r0 are actually saving LR. It doesn't make
26045 sense to substitute the regno here to test save_reg_p (LR_REGNO).
26046 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
26047 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
26048 as frame related. */
26051 /* If we see CR2 then we are here on a Darwin world save. Saves of
26052 CR2 signify the whole CR is being saved. This is a long-standing
26053 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
26054 that CR needs to be saved. */
26055 if (regno == CR2_REGNO)
26057 /* Omit frame info for any user-defined global regs. If frame info
26058 is supplied for them, frame unwinding will restore a user reg.
26059 Also omit frame info for any reg we don't need to save, as that
26060 bloats frame info and can cause problems with shrink wrapping.
26061 Since global regs won't be seen as needing to be saved, both of
26062 these conditions are covered by save_reg_p. */
26063 return save_reg_p (regno);
26066 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
26067 addresses, not offsets.
26069 REG2 contains the backchain that must be stored into *sp at each allocation.
26071 This is subtly different than the Ada probing above in that it tries hard
26072 to prevent attacks that jump the stack guard. Thus, it is never allowed
26073 to allocate more than PROBE_INTERVAL bytes of stack space without a
26076 static const char *
26077 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
26079 static int labelno = 0;
26083 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
26085 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
26087 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
26089 /* This allocates and probes. */
26092 xops[2] = GEN_INT (-probe_interval);
26094 output_asm_insn ("stdu %1,%2(%0)", xops);
26096 output_asm_insn ("stwu %1,%2(%0)", xops);
26098 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
26102 output_asm_insn ("cmpd 0,%0,%1", xops);
26104 output_asm_insn ("cmpw 0,%0,%1", xops);
26106 fputs ("\tbne 0,", asm_out_file);
26107 assemble_name_raw (asm_out_file, loop_lab);
26108 fputc ('\n', asm_out_file);
26113 /* Wrapper around the output_probe_stack_range routines. */
26115 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
26117 if (flag_stack_clash_protection)
26118 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
26120 return output_probe_stack_range_1 (reg1, reg3);
26123 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
26124 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
26125 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
26126 deduce these equivalences by itself so it wasn't necessary to hold
26127 its hand so much. Don't be tempted to always supply d2_f_d_e with
26128 the actual cfa register, ie. r31 when we are using a hard frame
26129 pointer. That fails when saving regs off r1, and sched moves the
26130 r31 setup past the reg saves. */
26133 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
26134 rtx reg2, rtx repl2)
26138 if (REGNO (reg) == STACK_POINTER_REGNUM)
26140 gcc_checking_assert (val == 0);
26144 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26147 rtx pat = PATTERN (insn);
26148 if (!repl && !reg2)
26150 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26151 if (GET_CODE (pat) == PARALLEL)
26152 for (int i = 0; i < XVECLEN (pat, 0); i++)
26153 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26155 rtx set = XVECEXP (pat, 0, i);
26157 if (!REG_P (SET_SRC (set))
26158 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26159 RTX_FRAME_RELATED_P (set) = 1;
26161 RTX_FRAME_RELATED_P (insn) = 1;
26165 /* We expect that 'pat' is either a SET or a PARALLEL containing
26166 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26167 are important so they all have to be marked RTX_FRAME_RELATED_P.
26168 Call simplify_replace_rtx on the SETs rather than the whole insn
26169 so as to leave the other stuff alone (for example USE of r12). */
26171 set_used_flags (pat);
26172 if (GET_CODE (pat) == SET)
26175 pat = simplify_replace_rtx (pat, reg, repl);
26177 pat = simplify_replace_rtx (pat, reg2, repl2);
26179 else if (GET_CODE (pat) == PARALLEL)
26181 pat = shallow_copy_rtx (pat);
26182 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
26184 for (int i = 0; i < XVECLEN (pat, 0); i++)
26185 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26187 rtx set = XVECEXP (pat, 0, i);
26190 set = simplify_replace_rtx (set, reg, repl);
26192 set = simplify_replace_rtx (set, reg2, repl2);
26193 XVECEXP (pat, 0, i) = set;
26195 if (!REG_P (SET_SRC (set))
26196 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26197 RTX_FRAME_RELATED_P (set) = 1;
26201 gcc_unreachable ();
26203 RTX_FRAME_RELATED_P (insn) = 1;
26204 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
26209 /* Returns an insn that has a vrsave set operation with the
26210 appropriate CLOBBERs. */
26213 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
26216 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
26217 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26220 = gen_rtx_SET (vrsave,
26221 gen_rtx_UNSPEC_VOLATILE (SImode,
26222 gen_rtvec (2, reg, vrsave),
26223 UNSPECV_SET_VRSAVE));
26227 /* We need to clobber the registers in the mask so the scheduler
26228 does not move sets to VRSAVE before sets of AltiVec registers.
26230 However, if the function receives nonlocal gotos, reload will set
26231 all call saved registers live. We will end up with:
26233 (set (reg 999) (mem))
26234 (parallel [ (set (reg vrsave) (unspec blah))
26235 (clobber (reg 999))])
26237 The clobber will cause the store into reg 999 to be dead, and
26238 flow will attempt to delete an epilogue insn. In this case, we
26239 need an unspec use/set of the register. */
26241 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
26242 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
26244 if (!epiloguep || call_used_regs [i])
26245 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
26246 gen_rtx_REG (V4SImode, i));
26249 rtx reg = gen_rtx_REG (V4SImode, i);
26252 = gen_rtx_SET (reg,
26253 gen_rtx_UNSPEC (V4SImode,
26254 gen_rtvec (1, reg), 27));
26258 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
26260 for (i = 0; i < nclobs; ++i)
26261 XVECEXP (insn, 0, i) = clobs[i];
26267 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
26271 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
26272 mem = gen_frame_mem (GET_MODE (reg), addr);
26273 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
26277 gen_frame_load (rtx reg, rtx frame_reg, int offset)
26279 return gen_frame_set (reg, frame_reg, offset, false);
26283 gen_frame_store (rtx reg, rtx frame_reg, int offset)
26285 return gen_frame_set (reg, frame_reg, offset, true);
26288 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26289 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26292 emit_frame_save (rtx frame_reg, machine_mode mode,
26293 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
26297 /* Some cases that need register indexed addressing. */
26298 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
26299 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
26301 reg = gen_rtx_REG (mode, regno);
26302 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
26303 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
26304 NULL_RTX, NULL_RTX);
26307 /* Emit an offset memory reference suitable for a frame store, while
26308 converting to a valid addressing mode. */
26311 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
26313 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
26316 #ifndef TARGET_FIX_AND_CONTINUE
26317 #define TARGET_FIX_AND_CONTINUE 0
26320 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26321 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26322 #define LAST_SAVRES_REGISTER 31
26323 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26334 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
26336 /* Temporary holding space for an out-of-line register save/restore
26338 static char savres_routine_name[30];
26340 /* Return the name for an out-of-line register save/restore routine.
26341 We are saving/restoring GPRs if GPR is true. */
26344 rs6000_savres_routine_name (int regno, int sel)
26346 const char *prefix = "";
26347 const char *suffix = "";
26349 /* Different targets are supposed to define
26350 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26351 routine name could be defined with:
26353 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26355 This is a nice idea in practice, but in reality, things are
26356 complicated in several ways:
26358 - ELF targets have save/restore routines for GPRs.
26360 - PPC64 ELF targets have routines for save/restore of GPRs that
26361 differ in what they do with the link register, so having a set
26362 prefix doesn't work. (We only use one of the save routines at
26363 the moment, though.)
26365 - PPC32 elf targets have "exit" versions of the restore routines
26366 that restore the link register and can save some extra space.
26367 These require an extra suffix. (There are also "tail" versions
26368 of the restore routines and "GOT" versions of the save routines,
26369 but we don't generate those at present. Same problems apply,
26372 We deal with all this by synthesizing our own prefix/suffix and
26373 using that for the simple sprintf call shown above. */
26374 if (DEFAULT_ABI == ABI_V4)
26379 if ((sel & SAVRES_REG) == SAVRES_GPR)
26380 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
26381 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26382 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
26383 else if ((sel & SAVRES_REG) == SAVRES_VR)
26384 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26388 if ((sel & SAVRES_LR))
26391 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26393 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26394 /* No out-of-line save/restore routines for GPRs on AIX. */
26395 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26399 if ((sel & SAVRES_REG) == SAVRES_GPR)
26400 prefix = ((sel & SAVRES_SAVE)
26401 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26402 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26403 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26405 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26406 if ((sel & SAVRES_LR))
26407 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26411 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26412 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26415 else if ((sel & SAVRES_REG) == SAVRES_VR)
26416 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26421 if (DEFAULT_ABI == ABI_DARWIN)
26423 /* The Darwin approach is (slightly) different, in order to be
26424 compatible with code generated by the system toolchain. There is a
26425 single symbol for the start of save sequence, and the code here
26426 embeds an offset into that code on the basis of the first register
26428 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26429 if ((sel & SAVRES_REG) == SAVRES_GPR)
26430 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26431 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26432 (regno - 13) * 4, prefix, regno);
26433 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26434 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26435 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26436 else if ((sel & SAVRES_REG) == SAVRES_VR)
26437 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26438 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26443 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26445 return savres_routine_name;
26448 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26449 We are saving/restoring GPRs if GPR is true. */
26452 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26454 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26455 ? info->first_gp_reg_save
26456 : (sel & SAVRES_REG) == SAVRES_FPR
26457 ? info->first_fp_reg_save - 32
26458 : (sel & SAVRES_REG) == SAVRES_VR
26459 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26464 /* Don't generate bogus routine names. */
26465 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26466 && regno <= LAST_SAVRES_REGISTER
26467 && select >= 0 && select <= 12);
26469 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26475 name = rs6000_savres_routine_name (regno, sel);
26477 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26478 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26479 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26485 /* Emit a sequence of insns, including a stack tie if needed, for
26486 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26487 reset the stack pointer, but move the base of the frame into
26488 reg UPDT_REGNO for use by out-of-line register restore routines. */
26491 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26492 unsigned updt_regno)
26494 /* If there is nothing to do, don't do anything. */
26495 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26498 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26500 /* This blockage is needed so that sched doesn't decide to move
26501 the sp change before the register restores. */
26502 if (DEFAULT_ABI == ABI_V4)
26503 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26504 GEN_INT (frame_off)));
26506 /* If we are restoring registers out-of-line, we will be using the
26507 "exit" variants of the restore routines, which will reset the
26508 stack for us. But we do need to point updt_reg into the
26509 right place for those routines. */
26510 if (frame_off != 0)
26511 return emit_insn (gen_add3_insn (updt_reg_rtx,
26512 frame_reg_rtx, GEN_INT (frame_off)));
26514 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26519 /* Return the register number used as a pointer by out-of-line
26520 save/restore functions. */
26522 static inline unsigned
26523 ptr_regno_for_savres (int sel)
26525 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26526 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26527 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26530 /* Construct a parallel rtx describing the effect of a call to an
26531 out-of-line register save/restore routine, and emit the insn
26532 or jump_insn as appropriate. */
26535 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26536 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26537 machine_mode reg_mode, int sel)
26540 int offset, start_reg, end_reg, n_regs, use_reg;
26541 int reg_size = GET_MODE_SIZE (reg_mode);
26548 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26549 ? info->first_gp_reg_save
26550 : (sel & SAVRES_REG) == SAVRES_FPR
26551 ? info->first_fp_reg_save
26552 : (sel & SAVRES_REG) == SAVRES_VR
26553 ? info->first_altivec_reg_save
26555 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26557 : (sel & SAVRES_REG) == SAVRES_FPR
26559 : (sel & SAVRES_REG) == SAVRES_VR
26560 ? LAST_ALTIVEC_REGNO + 1
26562 n_regs = end_reg - start_reg;
26563 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26564 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26567 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26568 RTVEC_ELT (p, offset++) = ret_rtx;
26570 RTVEC_ELT (p, offset++)
26571 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
26573 sym = rs6000_savres_routine_sym (info, sel);
26574 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26576 use_reg = ptr_regno_for_savres (sel);
26577 if ((sel & SAVRES_REG) == SAVRES_VR)
26579 /* Vector regs are saved/restored using [reg+reg] addressing. */
26580 RTVEC_ELT (p, offset++)
26581 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26582 RTVEC_ELT (p, offset++)
26583 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26586 RTVEC_ELT (p, offset++)
26587 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26589 for (i = 0; i < end_reg - start_reg; i++)
26590 RTVEC_ELT (p, i + offset)
26591 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26592 frame_reg_rtx, save_area_offset + reg_size * i,
26593 (sel & SAVRES_SAVE) != 0);
26595 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26596 RTVEC_ELT (p, i + offset)
26597 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26599 par = gen_rtx_PARALLEL (VOIDmode, p);
26601 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26603 insn = emit_jump_insn (par);
26604 JUMP_LABEL (insn) = ret_rtx;
26607 insn = emit_insn (par);
26611 /* Emit prologue code to store CR fields that need to be saved into REG. This
26612 function should only be called when moving the non-volatile CRs to REG, it
26613 is not a general purpose routine to move the entire set of CRs to REG.
26614 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26618 rs6000_emit_prologue_move_from_cr (rtx reg)
26620 /* Only the ELFv2 ABI allows storing only selected fields. */
26621 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26623 int i, cr_reg[8], count = 0;
26625 /* Collect CR fields that must be saved. */
26626 for (i = 0; i < 8; i++)
26627 if (save_reg_p (CR0_REGNO + i))
26628 cr_reg[count++] = i;
26630 /* If it's just a single one, use mfcrf. */
26633 rtvec p = rtvec_alloc (1);
26634 rtvec r = rtvec_alloc (2);
26635 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26636 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26638 = gen_rtx_SET (reg,
26639 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26641 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26645 /* ??? It might be better to handle count == 2 / 3 cases here
26646 as well, using logical operations to combine the values. */
26649 emit_insn (gen_prologue_movesi_from_cr (reg));
26652 /* Return whether the split-stack arg pointer (r12) is used. */
26655 split_stack_arg_pointer_used_p (void)
26657 /* If the pseudo holding the arg pointer is no longer a pseudo,
26658 then the arg pointer is used. */
26659 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26660 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26661 || (REGNO (cfun->machine->split_stack_arg_pointer)
26662 < FIRST_PSEUDO_REGISTER)))
26665 /* Unfortunately we also need to do some code scanning, since
26666 r12 may have been substituted for the pseudo. */
26668 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26669 FOR_BB_INSNS (bb, insn)
26670 if (NONDEBUG_INSN_P (insn))
26672 /* A call destroys r12. */
26677 FOR_EACH_INSN_USE (use, insn)
26679 rtx x = DF_REF_REG (use);
26680 if (REG_P (x) && REGNO (x) == 12)
26684 FOR_EACH_INSN_DEF (def, insn)
26686 rtx x = DF_REF_REG (def);
26687 if (REG_P (x) && REGNO (x) == 12)
26691 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26694 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26697 rs6000_global_entry_point_needed_p (void)
26699 /* Only needed for the ELFv2 ABI. */
26700 if (DEFAULT_ABI != ABI_ELFv2)
26703 /* With -msingle-pic-base, we assume the whole program shares the same
26704 TOC, so no global entry point prologues are needed anywhere. */
26705 if (TARGET_SINGLE_PIC_BASE)
26708 /* Ensure we have a global entry point for thunks. ??? We could
26709 avoid that if the target routine doesn't need a global entry point,
26710 but we do not know whether this is the case at this point. */
26711 if (cfun->is_thunk)
26714 /* For regular functions, rs6000_emit_prologue sets this flag if the
26715 routine ever uses the TOC pointer. */
26716 return cfun->machine->r2_setup_needed;
26719 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26721 rs6000_get_separate_components (void)
26723 rs6000_stack_t *info = rs6000_stack_info ();
26725 if (WORLD_SAVE_P (info))
26728 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26729 && !(info->savres_strategy & REST_MULTIPLE));
26731 /* Component 0 is the save/restore of LR (done via GPR0).
26732 Component 2 is the save of the TOC (GPR2).
26733 Components 13..31 are the save/restore of GPR13..GPR31.
26734 Components 46..63 are the save/restore of FPR14..FPR31. */
26736 cfun->machine->n_components = 64;
26738 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26739 bitmap_clear (components);
26741 int reg_size = TARGET_32BIT ? 4 : 8;
26742 int fp_reg_size = 8;
26744 /* The GPRs we need saved to the frame. */
26745 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26746 && (info->savres_strategy & REST_INLINE_GPRS))
26748 int offset = info->gp_save_offset;
26750 offset += info->total_size;
26752 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26754 if (IN_RANGE (offset, -0x8000, 0x7fff)
26755 && save_reg_p (regno))
26756 bitmap_set_bit (components, regno);
26758 offset += reg_size;
26762 /* Don't mess with the hard frame pointer. */
26763 if (frame_pointer_needed)
26764 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26766 /* Don't mess with the fixed TOC register. */
26767 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26768 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26769 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26770 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26772 /* The FPRs we need saved to the frame. */
26773 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26774 && (info->savres_strategy & REST_INLINE_FPRS))
26776 int offset = info->fp_save_offset;
26778 offset += info->total_size;
26780 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26782 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26783 bitmap_set_bit (components, regno);
26785 offset += fp_reg_size;
26789 /* Optimize LR save and restore if we can. This is component 0. Any
26790 out-of-line register save/restore routines need LR. */
26791 if (info->lr_save_p
26792 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26793 && (info->savres_strategy & SAVE_INLINE_GPRS)
26794 && (info->savres_strategy & REST_INLINE_GPRS)
26795 && (info->savres_strategy & SAVE_INLINE_FPRS)
26796 && (info->savres_strategy & REST_INLINE_FPRS)
26797 && (info->savres_strategy & SAVE_INLINE_VRS)
26798 && (info->savres_strategy & REST_INLINE_VRS))
26800 int offset = info->lr_save_offset;
26802 offset += info->total_size;
26803 if (IN_RANGE (offset, -0x8000, 0x7fff))
26804 bitmap_set_bit (components, 0);
26807 /* Optimize saving the TOC. This is component 2. */
26808 if (cfun->machine->save_toc_in_prologue)
26809 bitmap_set_bit (components, 2);
26814 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26816 rs6000_components_for_bb (basic_block bb)
26818 rs6000_stack_t *info = rs6000_stack_info ();
26820 bitmap in = DF_LIVE_IN (bb);
26821 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26822 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26824 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26825 bitmap_clear (components);
26827 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26830 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26831 if (bitmap_bit_p (in, regno)
26832 || bitmap_bit_p (gen, regno)
26833 || bitmap_bit_p (kill, regno))
26834 bitmap_set_bit (components, regno);
26837 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26838 if (bitmap_bit_p (in, regno)
26839 || bitmap_bit_p (gen, regno)
26840 || bitmap_bit_p (kill, regno))
26841 bitmap_set_bit (components, regno);
26843 /* The link register. */
26844 if (bitmap_bit_p (in, LR_REGNO)
26845 || bitmap_bit_p (gen, LR_REGNO)
26846 || bitmap_bit_p (kill, LR_REGNO))
26847 bitmap_set_bit (components, 0);
26849 /* The TOC save. */
26850 if (bitmap_bit_p (in, TOC_REGNUM)
26851 || bitmap_bit_p (gen, TOC_REGNUM)
26852 || bitmap_bit_p (kill, TOC_REGNUM))
26853 bitmap_set_bit (components, 2);
26858 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26860 rs6000_disqualify_components (sbitmap components, edge e,
26861 sbitmap edge_components, bool /*is_prologue*/)
26863 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26864 live where we want to place that code. */
26865 if (bitmap_bit_p (edge_components, 0)
26866 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26869 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26870 "on entry to bb %d\n", e->dest->index);
26871 bitmap_clear_bit (components, 0);
26875 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26877 rs6000_emit_prologue_components (sbitmap components)
26879 rs6000_stack_t *info = rs6000_stack_info ();
26880 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26881 ? HARD_FRAME_POINTER_REGNUM
26882 : STACK_POINTER_REGNUM);
26884 machine_mode reg_mode = Pmode;
26885 int reg_size = TARGET_32BIT ? 4 : 8;
26886 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26888 int fp_reg_size = 8;
26890 /* Prologue for LR. */
26891 if (bitmap_bit_p (components, 0))
26893 rtx reg = gen_rtx_REG (reg_mode, 0);
26894 rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
26895 RTX_FRAME_RELATED_P (insn) = 1;
26896 add_reg_note (insn, REG_CFA_REGISTER, NULL);
26898 int offset = info->lr_save_offset;
26900 offset += info->total_size;
26902 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26903 RTX_FRAME_RELATED_P (insn) = 1;
26904 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26905 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26906 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26909 /* Prologue for TOC. */
26910 if (bitmap_bit_p (components, 2))
26912 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26913 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26914 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26917 /* Prologue for the GPRs. */
26918 int offset = info->gp_save_offset;
26920 offset += info->total_size;
26922 for (int i = info->first_gp_reg_save; i < 32; i++)
26924 if (bitmap_bit_p (components, i))
26926 rtx reg = gen_rtx_REG (reg_mode, i);
26927 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26928 RTX_FRAME_RELATED_P (insn) = 1;
26929 rtx set = copy_rtx (single_set (insn));
26930 add_reg_note (insn, REG_CFA_OFFSET, set);
26933 offset += reg_size;
26936 /* Prologue for the FPRs. */
26937 offset = info->fp_save_offset;
26939 offset += info->total_size;
26941 for (int i = info->first_fp_reg_save; i < 64; i++)
26943 if (bitmap_bit_p (components, i))
26945 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26946 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26947 RTX_FRAME_RELATED_P (insn) = 1;
26948 rtx set = copy_rtx (single_set (insn));
26949 add_reg_note (insn, REG_CFA_OFFSET, set);
26952 offset += fp_reg_size;
26956 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26958 rs6000_emit_epilogue_components (sbitmap components)
26960 rs6000_stack_t *info = rs6000_stack_info ();
26961 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26962 ? HARD_FRAME_POINTER_REGNUM
26963 : STACK_POINTER_REGNUM);
26965 machine_mode reg_mode = Pmode;
26966 int reg_size = TARGET_32BIT ? 4 : 8;
26968 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26970 int fp_reg_size = 8;
26972 /* Epilogue for the FPRs. */
26973 int offset = info->fp_save_offset;
26975 offset += info->total_size;
26977 for (int i = info->first_fp_reg_save; i < 64; i++)
26979 if (bitmap_bit_p (components, i))
26981 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26982 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26983 RTX_FRAME_RELATED_P (insn) = 1;
26984 add_reg_note (insn, REG_CFA_RESTORE, reg);
26987 offset += fp_reg_size;
26990 /* Epilogue for the GPRs. */
26991 offset = info->gp_save_offset;
26993 offset += info->total_size;
26995 for (int i = info->first_gp_reg_save; i < 32; i++)
26997 if (bitmap_bit_p (components, i))
26999 rtx reg = gen_rtx_REG (reg_mode, i);
27000 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
27001 RTX_FRAME_RELATED_P (insn) = 1;
27002 add_reg_note (insn, REG_CFA_RESTORE, reg);
27005 offset += reg_size;
27008 /* Epilogue for LR. */
27009 if (bitmap_bit_p (components, 0))
27011 int offset = info->lr_save_offset;
27013 offset += info->total_size;
27015 rtx reg = gen_rtx_REG (reg_mode, 0);
27016 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
27018 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27019 insn = emit_move_insn (lr, reg);
27020 RTX_FRAME_RELATED_P (insn) = 1;
27021 add_reg_note (insn, REG_CFA_RESTORE, lr);
27025 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
27027 rs6000_set_handled_components (sbitmap components)
27029 rs6000_stack_t *info = rs6000_stack_info ();
27031 for (int i = info->first_gp_reg_save; i < 32; i++)
27032 if (bitmap_bit_p (components, i))
27033 cfun->machine->gpr_is_wrapped_separately[i] = true;
27035 for (int i = info->first_fp_reg_save; i < 64; i++)
27036 if (bitmap_bit_p (components, i))
27037 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
27039 if (bitmap_bit_p (components, 0))
27040 cfun->machine->lr_is_wrapped_separately = true;
27042 if (bitmap_bit_p (components, 2))
27043 cfun->machine->toc_is_wrapped_separately = true;
27046 /* VRSAVE is a bit vector representing which AltiVec registers
27047 are used. The OS uses this to determine which vector
27048 registers to save on a context switch. We need to save
27049 VRSAVE on the stack frame, add whatever AltiVec registers we
27050 used in this function, and do the corresponding magic in the
27053 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
27054 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27056 /* Get VRSAVE into a GPR. */
27057 rtx reg = gen_rtx_REG (SImode, save_regno);
27058 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
27060 emit_insn (gen_get_vrsave_internal (reg));
27062 emit_insn (gen_rtx_SET (reg, vrsave));
27065 int offset = info->vrsave_save_offset + frame_off;
27066 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
27068 /* Include the registers in the mask. */
27069 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
27071 emit_insn (generate_set_vrsave (reg, info, 0));
27074 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
27075 called, it left the arg pointer to the old stack in r29. Otherwise, the
27076 arg pointer is the top of the current frame. */
27078 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
27079 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27081 cfun->machine->split_stack_argp_used = true;
27085 rtx r12 = gen_rtx_REG (Pmode, 12);
27086 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27087 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
27088 emit_insn_before (set_r12, sp_adjust);
27090 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
27092 rtx r12 = gen_rtx_REG (Pmode, 12);
27093 if (frame_off == 0)
27094 emit_move_insn (r12, frame_reg_rtx);
27096 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
27101 rtx r12 = gen_rtx_REG (Pmode, 12);
27102 rtx r29 = gen_rtx_REG (Pmode, 29);
27103 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
27104 rtx not_more = gen_label_rtx ();
27107 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27108 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
27109 gen_rtx_LABEL_REF (VOIDmode, not_more),
27111 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27112 JUMP_LABEL (jump) = not_more;
27113 LABEL_NUSES (not_more) += 1;
27114 emit_move_insn (r12, r29);
27115 emit_label (not_more);
27119 /* Emit function prologue as insns. */
27122 rs6000_emit_prologue (void)
27124 rs6000_stack_t *info = rs6000_stack_info ();
27125 machine_mode reg_mode = Pmode;
27126 int reg_size = TARGET_32BIT ? 4 : 8;
27127 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
27129 int fp_reg_size = 8;
27130 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27131 rtx frame_reg_rtx = sp_reg_rtx;
27132 unsigned int cr_save_regno;
27133 rtx cr_save_rtx = NULL_RTX;
27136 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
27137 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
27138 && call_used_regs[STATIC_CHAIN_REGNUM]);
27139 int using_split_stack = (flag_split_stack
27140 && (lookup_attribute ("no_split_stack",
27141 DECL_ATTRIBUTES (cfun->decl))
27144 /* Offset to top of frame for frame_reg and sp respectively. */
27145 HOST_WIDE_INT frame_off = 0;
27146 HOST_WIDE_INT sp_off = 0;
27147 /* sp_adjust is the stack adjusting instruction, tracked so that the
27148 insn setting up the split-stack arg pointer can be emitted just
27149 prior to it, when r12 is not used here for other purposes. */
27150 rtx_insn *sp_adjust = 0;
27153 /* Track and check usage of r0, r11, r12. */
27154 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
27155 #define START_USE(R) do \
27157 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27158 reg_inuse |= 1 << (R); \
27160 #define END_USE(R) do \
27162 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27163 reg_inuse &= ~(1 << (R)); \
27165 #define NOT_INUSE(R) do \
27167 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27170 #define START_USE(R) do {} while (0)
27171 #define END_USE(R) do {} while (0)
27172 #define NOT_INUSE(R) do {} while (0)
27175 if (DEFAULT_ABI == ABI_ELFv2
27176 && !TARGET_SINGLE_PIC_BASE)
27178 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
27180 /* With -mminimal-toc we may generate an extra use of r2 below. */
27181 if (TARGET_TOC && TARGET_MINIMAL_TOC
27182 && !constant_pool_empty_p ())
27183 cfun->machine->r2_setup_needed = true;
27187 if (flag_stack_usage_info)
27188 current_function_static_stack_size = info->total_size;
27190 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
27192 HOST_WIDE_INT size = info->total_size;
27194 if (crtl->is_leaf && !cfun->calls_alloca)
27196 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
27197 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27198 size - get_stack_check_protect ());
27201 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
27204 if (TARGET_FIX_AND_CONTINUE)
27206 /* gdb on darwin arranges to forward a function from the old
27207 address by modifying the first 5 instructions of the function
27208 to branch to the overriding function. This is necessary to
27209 permit function pointers that point to the old function to
27210 actually forward to the new function. */
27211 emit_insn (gen_nop ());
27212 emit_insn (gen_nop ());
27213 emit_insn (gen_nop ());
27214 emit_insn (gen_nop ());
27215 emit_insn (gen_nop ());
27218 /* Handle world saves specially here. */
27219 if (WORLD_SAVE_P (info))
27226 /* save_world expects lr in r0. */
27227 reg0 = gen_rtx_REG (Pmode, 0);
27228 if (info->lr_save_p)
27230 insn = emit_move_insn (reg0,
27231 gen_rtx_REG (Pmode, LR_REGNO));
27232 RTX_FRAME_RELATED_P (insn) = 1;
27235 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27236 assumptions about the offsets of various bits of the stack
27238 gcc_assert (info->gp_save_offset == -220
27239 && info->fp_save_offset == -144
27240 && info->lr_save_offset == 8
27241 && info->cr_save_offset == 4
27244 && (!crtl->calls_eh_return
27245 || info->ehrd_offset == -432)
27246 && info->vrsave_save_offset == -224
27247 && info->altivec_save_offset == -416);
27249 treg = gen_rtx_REG (SImode, 11);
27250 emit_move_insn (treg, GEN_INT (-info->total_size));
27252 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27253 in R11. It also clobbers R12, so beware! */
27255 /* Preserve CR2 for save_world prologues */
27257 sz += 32 - info->first_gp_reg_save;
27258 sz += 64 - info->first_fp_reg_save;
27259 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
27260 p = rtvec_alloc (sz);
27262 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
27263 gen_rtx_REG (SImode,
27265 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
27266 gen_rtx_SYMBOL_REF (Pmode,
27268 /* We do floats first so that the instruction pattern matches
27270 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
27272 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
27274 info->first_fp_reg_save + i),
27276 info->fp_save_offset + frame_off + 8 * i);
27277 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27279 = gen_frame_store (gen_rtx_REG (V4SImode,
27280 info->first_altivec_reg_save + i),
27282 info->altivec_save_offset + frame_off + 16 * i);
27283 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27285 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27287 info->gp_save_offset + frame_off + reg_size * i);
27289 /* CR register traditionally saved as CR2. */
27291 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
27292 frame_reg_rtx, info->cr_save_offset + frame_off);
27293 /* Explain about use of R0. */
27294 if (info->lr_save_p)
27296 = gen_frame_store (reg0,
27297 frame_reg_rtx, info->lr_save_offset + frame_off);
27298 /* Explain what happens to the stack pointer. */
27300 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
27301 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
27304 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27305 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27306 treg, GEN_INT (-info->total_size));
27307 sp_off = frame_off = info->total_size;
27310 strategy = info->savres_strategy;
27312 /* For V.4, update stack before we do any saving and set back pointer. */
27313 if (! WORLD_SAVE_P (info)
27315 && (DEFAULT_ABI == ABI_V4
27316 || crtl->calls_eh_return))
27318 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
27319 || !(strategy & SAVE_INLINE_GPRS)
27320 || !(strategy & SAVE_INLINE_VRS));
27321 int ptr_regno = -1;
27322 rtx ptr_reg = NULL_RTX;
27325 if (info->total_size < 32767)
27326 frame_off = info->total_size;
27329 else if (info->cr_save_p
27331 || info->first_fp_reg_save < 64
27332 || info->first_gp_reg_save < 32
27333 || info->altivec_size != 0
27334 || info->vrsave_size != 0
27335 || crtl->calls_eh_return)
27339 /* The prologue won't be saving any regs so there is no need
27340 to set up a frame register to access any frame save area.
27341 We also won't be using frame_off anywhere below, but set
27342 the correct value anyway to protect against future
27343 changes to this function. */
27344 frame_off = info->total_size;
27346 if (ptr_regno != -1)
27348 /* Set up the frame offset to that needed by the first
27349 out-of-line save function. */
27350 START_USE (ptr_regno);
27351 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27352 frame_reg_rtx = ptr_reg;
27353 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
27354 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
27355 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
27356 ptr_off = info->gp_save_offset + info->gp_size;
27357 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
27358 ptr_off = info->altivec_save_offset + info->altivec_size;
27359 frame_off = -ptr_off;
27361 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27363 if (REGNO (frame_reg_rtx) == 12)
27365 sp_off = info->total_size;
27366 if (frame_reg_rtx != sp_reg_rtx)
27367 rs6000_emit_stack_tie (frame_reg_rtx, false);
27370 /* If we use the link register, get it into r0. */
27371 if (!WORLD_SAVE_P (info) && info->lr_save_p
27372 && !cfun->machine->lr_is_wrapped_separately)
27374 rtx addr, reg, mem;
27376 reg = gen_rtx_REG (Pmode, 0);
27378 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
27379 RTX_FRAME_RELATED_P (insn) = 1;
27381 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
27382 | SAVE_NOINLINE_FPRS_SAVES_LR)))
27384 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27385 GEN_INT (info->lr_save_offset + frame_off));
27386 mem = gen_rtx_MEM (Pmode, addr);
27387 /* This should not be of rs6000_sr_alias_set, because of
27388 __builtin_return_address. */
27390 insn = emit_move_insn (mem, reg);
27391 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27392 NULL_RTX, NULL_RTX);
27397 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27398 r12 will be needed by out-of-line gpr restore. */
27399 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27400 && !(strategy & (SAVE_INLINE_GPRS
27401 | SAVE_NOINLINE_GPRS_SAVES_LR))
27403 if (!WORLD_SAVE_P (info)
27405 && REGNO (frame_reg_rtx) != cr_save_regno
27406 && !(using_static_chain_p && cr_save_regno == 11)
27407 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27409 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27410 START_USE (cr_save_regno);
27411 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27414 /* Do any required saving of fpr's. If only one or two to save, do
27415 it ourselves. Otherwise, call function. */
27416 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27418 int offset = info->fp_save_offset + frame_off;
27419 for (int i = info->first_fp_reg_save; i < 64; i++)
27422 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27423 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27424 sp_off - frame_off);
27426 offset += fp_reg_size;
27429 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27431 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27432 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27433 unsigned ptr_regno = ptr_regno_for_savres (sel);
27434 rtx ptr_reg = frame_reg_rtx;
27436 if (REGNO (frame_reg_rtx) == ptr_regno)
27437 gcc_checking_assert (frame_off == 0);
27440 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27441 NOT_INUSE (ptr_regno);
27442 emit_insn (gen_add3_insn (ptr_reg,
27443 frame_reg_rtx, GEN_INT (frame_off)));
27445 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27446 info->fp_save_offset,
27447 info->lr_save_offset,
27449 rs6000_frame_related (insn, ptr_reg, sp_off,
27450 NULL_RTX, NULL_RTX);
27455 /* Save GPRs. This is done as a PARALLEL if we are using
27456 the store-multiple instructions. */
27457 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27459 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27460 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27461 unsigned ptr_regno = ptr_regno_for_savres (sel);
27462 rtx ptr_reg = frame_reg_rtx;
27463 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27464 int end_save = info->gp_save_offset + info->gp_size;
27467 if (ptr_regno == 12)
27470 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27472 /* Need to adjust r11 (r12) if we saved any FPRs. */
27473 if (end_save + frame_off != 0)
27475 rtx offset = GEN_INT (end_save + frame_off);
27478 frame_off = -end_save;
27480 NOT_INUSE (ptr_regno);
27481 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27483 else if (!ptr_set_up)
27485 NOT_INUSE (ptr_regno);
27486 emit_move_insn (ptr_reg, frame_reg_rtx);
27488 ptr_off = -end_save;
27489 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27490 info->gp_save_offset + ptr_off,
27491 info->lr_save_offset + ptr_off,
27493 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27494 NULL_RTX, NULL_RTX);
27498 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27502 p = rtvec_alloc (32 - info->first_gp_reg_save);
27503 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27505 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27507 info->gp_save_offset + frame_off + reg_size * i);
27508 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27509 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27510 NULL_RTX, NULL_RTX);
27512 else if (!WORLD_SAVE_P (info))
27514 int offset = info->gp_save_offset + frame_off;
27515 for (int i = info->first_gp_reg_save; i < 32; i++)
27518 && !cfun->machine->gpr_is_wrapped_separately[i])
27519 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27520 sp_off - frame_off);
27522 offset += reg_size;
27526 if (crtl->calls_eh_return)
27533 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27534 if (regno == INVALID_REGNUM)
27538 p = rtvec_alloc (i);
27542 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27543 if (regno == INVALID_REGNUM)
27547 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27549 info->ehrd_offset + sp_off + reg_size * (int) i);
27550 RTVEC_ELT (p, i) = set;
27551 RTX_FRAME_RELATED_P (set) = 1;
27554 insn = emit_insn (gen_blockage ());
27555 RTX_FRAME_RELATED_P (insn) = 1;
27556 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27559 /* In AIX ABI we need to make sure r2 is really saved. */
27560 if (TARGET_AIX && crtl->calls_eh_return)
27562 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27563 rtx join_insn, note;
27564 rtx_insn *save_insn;
27565 long toc_restore_insn;
27567 tmp_reg = gen_rtx_REG (Pmode, 11);
27568 tmp_reg_si = gen_rtx_REG (SImode, 11);
27569 if (using_static_chain_p)
27572 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27576 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27577 /* Peek at instruction to which this function returns. If it's
27578 restoring r2, then we know we've already saved r2. We can't
27579 unconditionally save r2 because the value we have will already
27580 be updated if we arrived at this function via a plt call or
27581 toc adjusting stub. */
27582 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27583 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27584 + RS6000_TOC_SAVE_SLOT);
27585 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27586 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27587 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27588 validate_condition_mode (EQ, CCUNSmode);
27589 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27590 emit_insn (gen_rtx_SET (compare_result,
27591 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27592 toc_save_done = gen_label_rtx ();
27593 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27594 gen_rtx_EQ (VOIDmode, compare_result,
27596 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27598 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27599 JUMP_LABEL (jump) = toc_save_done;
27600 LABEL_NUSES (toc_save_done) += 1;
27602 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27603 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27604 sp_off - frame_off);
27606 emit_label (toc_save_done);
27608 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27609 have a CFG that has different saves along different paths.
27610 Move the note to a dummy blockage insn, which describes that
27611 R2 is unconditionally saved after the label. */
27612 /* ??? An alternate representation might be a special insn pattern
27613 containing both the branch and the store. That might let the
27614 code that minimizes the number of DW_CFA_advance opcodes better
27615 freedom in placing the annotations. */
27616 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27618 remove_note (save_insn, note);
27620 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27621 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27622 RTX_FRAME_RELATED_P (save_insn) = 0;
27624 join_insn = emit_insn (gen_blockage ());
27625 REG_NOTES (join_insn) = note;
27626 RTX_FRAME_RELATED_P (join_insn) = 1;
27628 if (using_static_chain_p)
27630 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27637 /* Save CR if we use any that must be preserved. */
27638 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27640 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27641 GEN_INT (info->cr_save_offset + frame_off));
27642 rtx mem = gen_frame_mem (SImode, addr);
27644 /* If we didn't copy cr before, do so now using r0. */
27645 if (cr_save_rtx == NULL_RTX)
27648 cr_save_rtx = gen_rtx_REG (SImode, 0);
27649 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27652 /* Saving CR requires a two-instruction sequence: one instruction
27653 to move the CR to a general-purpose register, and a second
27654 instruction that stores the GPR to memory.
27656 We do not emit any DWARF CFI records for the first of these,
27657 because we cannot properly represent the fact that CR is saved in
27658 a register. One reason is that we cannot express that multiple
27659 CR fields are saved; another reason is that on 64-bit, the size
27660 of the CR register in DWARF (4 bytes) differs from the size of
27661 a general-purpose register.
27663 This means if any intervening instruction were to clobber one of
27664 the call-saved CR fields, we'd have incorrect CFI. To prevent
27665 this from happening, we mark the store to memory as a use of
27666 those CR fields, which prevents any such instruction from being
27667 scheduled in between the two instructions. */
27672 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27673 for (i = 0; i < 8; i++)
27674 if (save_reg_p (CR0_REGNO + i))
27675 crsave_v[n_crsave++]
27676 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27678 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27679 gen_rtvec_v (n_crsave, crsave_v)));
27680 END_USE (REGNO (cr_save_rtx));
27682 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27683 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27684 so we need to construct a frame expression manually. */
27685 RTX_FRAME_RELATED_P (insn) = 1;
27687 /* Update address to be stack-pointer relative, like
27688 rs6000_frame_related would do. */
27689 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27690 GEN_INT (info->cr_save_offset + sp_off));
27691 mem = gen_frame_mem (SImode, addr);
27693 if (DEFAULT_ABI == ABI_ELFv2)
27695 /* In the ELFv2 ABI we generate separate CFI records for each
27696 CR field that was actually saved. They all point to the
27697 same 32-bit stack slot. */
27701 for (i = 0; i < 8; i++)
27702 if (save_reg_p (CR0_REGNO + i))
27705 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27707 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27711 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27712 gen_rtx_PARALLEL (VOIDmode,
27713 gen_rtvec_v (n_crframe, crframe)));
27717 /* In other ABIs, by convention, we use a single CR regnum to
27718 represent the fact that all call-saved CR fields are saved.
27719 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27720 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27721 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27725 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27726 *separate* slots if the routine calls __builtin_eh_return, so
27727 that they can be independently restored by the unwinder. */
27728 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27730 int i, cr_off = info->ehcr_offset;
27733 /* ??? We might get better performance by using multiple mfocrf
27735 crsave = gen_rtx_REG (SImode, 0);
27736 emit_insn (gen_prologue_movesi_from_cr (crsave));
27738 for (i = 0; i < 8; i++)
27739 if (!call_used_regs[CR0_REGNO + i])
27741 rtvec p = rtvec_alloc (2);
27743 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27745 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27747 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27749 RTX_FRAME_RELATED_P (insn) = 1;
27750 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27751 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27752 sp_reg_rtx, cr_off + sp_off));
27754 cr_off += reg_size;
27758 /* If we are emitting stack probes, but allocate no stack, then
27759 just note that in the dump file. */
27760 if (flag_stack_clash_protection
27763 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27765 /* Update stack and set back pointer unless this is V.4,
27766 for which it was done previously. */
27767 if (!WORLD_SAVE_P (info) && info->push_p
27768 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27770 rtx ptr_reg = NULL;
27773 /* If saving altivec regs we need to be able to address all save
27774 locations using a 16-bit offset. */
27775 if ((strategy & SAVE_INLINE_VRS) == 0
27776 || (info->altivec_size != 0
27777 && (info->altivec_save_offset + info->altivec_size - 16
27778 + info->total_size - frame_off) > 32767)
27779 || (info->vrsave_size != 0
27780 && (info->vrsave_save_offset
27781 + info->total_size - frame_off) > 32767))
27783 int sel = SAVRES_SAVE | SAVRES_VR;
27784 unsigned ptr_regno = ptr_regno_for_savres (sel);
27786 if (using_static_chain_p
27787 && ptr_regno == STATIC_CHAIN_REGNUM)
27789 if (REGNO (frame_reg_rtx) != ptr_regno)
27790 START_USE (ptr_regno);
27791 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27792 frame_reg_rtx = ptr_reg;
27793 ptr_off = info->altivec_save_offset + info->altivec_size;
27794 frame_off = -ptr_off;
27796 else if (REGNO (frame_reg_rtx) == 1)
27797 frame_off = info->total_size;
27798 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27800 if (REGNO (frame_reg_rtx) == 12)
27802 sp_off = info->total_size;
27803 if (frame_reg_rtx != sp_reg_rtx)
27804 rs6000_emit_stack_tie (frame_reg_rtx, false);
27807 /* Set frame pointer, if needed. */
27808 if (frame_pointer_needed)
27810 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27812 RTX_FRAME_RELATED_P (insn) = 1;
27815 /* Save AltiVec registers if needed. Save here because the red zone does
27816 not always include AltiVec registers. */
27817 if (!WORLD_SAVE_P (info)
27818 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27820 int end_save = info->altivec_save_offset + info->altivec_size;
27822 /* Oddly, the vector save/restore functions point r0 at the end
27823 of the save area, then use r11 or r12 to load offsets for
27824 [reg+reg] addressing. */
27825 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27826 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27827 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27829 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27831 if (scratch_regno == 12)
27833 if (end_save + frame_off != 0)
27835 rtx offset = GEN_INT (end_save + frame_off);
27837 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27840 emit_move_insn (ptr_reg, frame_reg_rtx);
27842 ptr_off = -end_save;
27843 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27844 info->altivec_save_offset + ptr_off,
27845 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27846 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27847 NULL_RTX, NULL_RTX);
27848 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27850 /* The oddity mentioned above clobbered our frame reg. */
27851 emit_move_insn (frame_reg_rtx, ptr_reg);
27852 frame_off = ptr_off;
27855 else if (!WORLD_SAVE_P (info)
27856 && info->altivec_size != 0)
27860 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27861 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27863 rtx areg, savereg, mem;
27864 HOST_WIDE_INT offset;
27866 offset = (info->altivec_save_offset + frame_off
27867 + 16 * (i - info->first_altivec_reg_save));
27869 savereg = gen_rtx_REG (V4SImode, i);
27871 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27873 mem = gen_frame_mem (V4SImode,
27874 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27875 GEN_INT (offset)));
27876 insn = emit_insn (gen_rtx_SET (mem, savereg));
27882 areg = gen_rtx_REG (Pmode, 0);
27883 emit_move_insn (areg, GEN_INT (offset));
27885 /* AltiVec addressing mode is [reg+reg]. */
27886 mem = gen_frame_mem (V4SImode,
27887 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27889 /* Rather than emitting a generic move, force use of the stvx
27890 instruction, which we always want on ISA 2.07 (power8) systems.
27891 In particular we don't want xxpermdi/stxvd2x for little
27893 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27896 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27897 areg, GEN_INT (offset));
27901 /* VRSAVE is a bit vector representing which AltiVec registers
27902 are used. The OS uses this to determine which vector
27903 registers to save on a context switch. We need to save
27904 VRSAVE on the stack frame, add whatever AltiVec registers we
27905 used in this function, and do the corresponding magic in the
27908 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27910 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27911 be using r12 as frame_reg_rtx and r11 as the static chain
27912 pointer for nested functions. */
27913 int save_regno = 12;
27914 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27915 && !using_static_chain_p)
27917 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27920 if (using_static_chain_p)
27923 NOT_INUSE (save_regno);
27925 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27928 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27929 if (!TARGET_SINGLE_PIC_BASE
27930 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27931 && !constant_pool_empty_p ())
27932 || (DEFAULT_ABI == ABI_V4
27933 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27934 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27936 /* If emit_load_toc_table will use the link register, we need to save
27937 it. We use R12 for this purpose because emit_load_toc_table
27938 can use register 0. This allows us to use a plain 'blr' to return
27939 from the procedure more often. */
27940 int save_LR_around_toc_setup = (TARGET_ELF
27941 && DEFAULT_ABI == ABI_V4
27943 && ! info->lr_save_p
27944 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27945 if (save_LR_around_toc_setup)
27947 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27948 rtx tmp = gen_rtx_REG (Pmode, 12);
27951 insn = emit_move_insn (tmp, lr);
27952 RTX_FRAME_RELATED_P (insn) = 1;
27954 rs6000_emit_load_toc_table (TRUE);
27956 insn = emit_move_insn (lr, tmp);
27957 add_reg_note (insn, REG_CFA_RESTORE, lr);
27958 RTX_FRAME_RELATED_P (insn) = 1;
27961 rs6000_emit_load_toc_table (TRUE);
27965 if (!TARGET_SINGLE_PIC_BASE
27966 && DEFAULT_ABI == ABI_DARWIN
27967 && flag_pic && crtl->uses_pic_offset_table)
27969 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27970 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27972 /* Save and restore LR locally around this call (in R0). */
27973 if (!info->lr_save_p)
27974 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27976 emit_insn (gen_load_macho_picbase (src));
27978 emit_move_insn (gen_rtx_REG (Pmode,
27979 RS6000_PIC_OFFSET_TABLE_REGNUM),
27982 if (!info->lr_save_p)
27983 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27987 /* If we need to, save the TOC register after doing the stack setup.
27988 Do not emit eh frame info for this save. The unwinder wants info,
27989 conceptually attached to instructions in this function, about
27990 register values in the caller of this function. This R2 may have
27991 already been changed from the value in the caller.
27992 We don't attempt to write accurate DWARF EH frame info for R2
27993 because code emitted by gcc for a (non-pointer) function call
27994 doesn't save and restore R2. Instead, R2 is managed out-of-line
27995 by a linker generated plt call stub when the function resides in
27996 a shared library. This behavior is costly to describe in DWARF,
27997 both in terms of the size of DWARF info and the time taken in the
27998 unwinder to interpret it. R2 changes, apart from the
27999 calls_eh_return case earlier in this function, are handled by
28000 linux-unwind.h frob_update_context. */
28001 if (rs6000_save_toc_in_prologue_p ()
28002 && !cfun->machine->toc_is_wrapped_separately)
28004 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
28005 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
28008 /* Set up the arg pointer (r12) for -fsplit-stack code. */
28009 if (using_split_stack && split_stack_arg_pointer_used_p ())
28010 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
28013 /* Output .extern statements for the save/restore routines we use. */
28016 rs6000_output_savres_externs (FILE *file)
28018 rs6000_stack_t *info = rs6000_stack_info ();
28020 if (TARGET_DEBUG_STACK)
28021 debug_stack_info (info);
28023 /* Write .extern for any function we will call to save and restore
28025 if (info->first_fp_reg_save < 64
28030 int regno = info->first_fp_reg_save - 32;
28032 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
28034 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
28035 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
28036 name = rs6000_savres_routine_name (regno, sel);
28037 fprintf (file, "\t.extern %s\n", name);
28039 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
28041 bool lr = (info->savres_strategy
28042 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28043 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28044 name = rs6000_savres_routine_name (regno, sel);
28045 fprintf (file, "\t.extern %s\n", name);
28050 /* Write function prologue. */
28053 rs6000_output_function_prologue (FILE *file)
28055 if (!cfun->is_thunk)
28056 rs6000_output_savres_externs (file);
28058 /* ELFv2 ABI r2 setup code and local entry point. This must follow
28059 immediately after the global entry point label. */
28060 if (rs6000_global_entry_point_needed_p ())
28062 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28064 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
28066 if (TARGET_CMODEL != CMODEL_LARGE)
28068 /* In the small and medium code models, we assume the TOC is less
28069 2 GB away from the text section, so it can be computed via the
28070 following two-instruction sequence. */
28073 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28074 fprintf (file, "0:\taddis 2,12,.TOC.-");
28075 assemble_name (file, buf);
28076 fprintf (file, "@ha\n");
28077 fprintf (file, "\taddi 2,2,.TOC.-");
28078 assemble_name (file, buf);
28079 fprintf (file, "@l\n");
28083 /* In the large code model, we allow arbitrary offsets between the
28084 TOC and the text section, so we have to load the offset from
28085 memory. The data field is emitted directly before the global
28086 entry point in rs6000_elf_declare_function_name. */
28089 #ifdef HAVE_AS_ENTRY_MARKERS
28090 /* If supported by the linker, emit a marker relocation. If the
28091 total code size of the final executable or shared library
28092 happens to fit into 2 GB after all, the linker will replace
28093 this code sequence with the sequence for the small or medium
28095 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
28097 fprintf (file, "\tld 2,");
28098 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
28099 assemble_name (file, buf);
28100 fprintf (file, "-");
28101 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28102 assemble_name (file, buf);
28103 fprintf (file, "(12)\n");
28104 fprintf (file, "\tadd 2,2,12\n");
28107 fputs ("\t.localentry\t", file);
28108 assemble_name (file, name);
28109 fputs (",.-", file);
28110 assemble_name (file, name);
28111 fputs ("\n", file);
28114 /* Output -mprofile-kernel code. This needs to be done here instead of
28115 in output_function_profile since it must go after the ELFv2 ABI
28116 local entry point. */
28117 if (TARGET_PROFILE_KERNEL && crtl->profile)
28119 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
28120 gcc_assert (!TARGET_32BIT);
28122 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
28124 /* In the ELFv2 ABI we have no compiler stack word. It must be
28125 the resposibility of _mcount to preserve the static chain
28126 register if required. */
28127 if (DEFAULT_ABI != ABI_ELFv2
28128 && cfun->static_chain_decl != NULL)
28130 asm_fprintf (file, "\tstd %s,24(%s)\n",
28131 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28132 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28133 asm_fprintf (file, "\tld %s,24(%s)\n",
28134 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28137 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28140 rs6000_pic_labelno++;
28143 /* -mprofile-kernel code calls mcount before the function prolog,
28144 so a profiled leaf function should stay a leaf function. */
28146 rs6000_keep_leaf_when_profiled ()
28148 return TARGET_PROFILE_KERNEL;
28151 /* Non-zero if vmx regs are restored before the frame pop, zero if
28152 we restore after the pop when possible. */
28153 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28155 /* Restoring cr is a two step process: loading a reg from the frame
28156 save, then moving the reg to cr. For ABI_V4 we must let the
28157 unwinder know that the stack location is no longer valid at or
28158 before the stack deallocation, but we can't emit a cfa_restore for
28159 cr at the stack deallocation like we do for other registers.
28160 The trouble is that it is possible for the move to cr to be
28161 scheduled after the stack deallocation. So say exactly where cr
28162 is located on each of the two insns. */
28165 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
28167 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
28168 rtx reg = gen_rtx_REG (SImode, regno);
28169 rtx_insn *insn = emit_move_insn (reg, mem);
28171 if (!exit_func && DEFAULT_ABI == ABI_V4)
28173 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28174 rtx set = gen_rtx_SET (reg, cr);
28176 add_reg_note (insn, REG_CFA_REGISTER, set);
28177 RTX_FRAME_RELATED_P (insn) = 1;
28182 /* Reload CR from REG. */
28185 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
28190 if (using_mfcr_multiple)
28192 for (i = 0; i < 8; i++)
28193 if (save_reg_p (CR0_REGNO + i))
28195 gcc_assert (count);
28198 if (using_mfcr_multiple && count > 1)
28204 p = rtvec_alloc (count);
28207 for (i = 0; i < 8; i++)
28208 if (save_reg_p (CR0_REGNO + i))
28210 rtvec r = rtvec_alloc (2);
28211 RTVEC_ELT (r, 0) = reg;
28212 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
28213 RTVEC_ELT (p, ndx) =
28214 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
28215 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
28218 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28219 gcc_assert (ndx == count);
28221 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28222 CR field separately. */
28223 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28225 for (i = 0; i < 8; i++)
28226 if (save_reg_p (CR0_REGNO + i))
28227 add_reg_note (insn, REG_CFA_RESTORE,
28228 gen_rtx_REG (SImode, CR0_REGNO + i));
28230 RTX_FRAME_RELATED_P (insn) = 1;
28234 for (i = 0; i < 8; i++)
28235 if (save_reg_p (CR0_REGNO + i))
28237 rtx insn = emit_insn (gen_movsi_to_cr_one
28238 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28240 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28241 CR field separately, attached to the insn that in fact
28242 restores this particular CR field. */
28243 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28245 add_reg_note (insn, REG_CFA_RESTORE,
28246 gen_rtx_REG (SImode, CR0_REGNO + i));
28248 RTX_FRAME_RELATED_P (insn) = 1;
28252 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28253 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
28254 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
28256 rtx_insn *insn = get_last_insn ();
28257 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28259 add_reg_note (insn, REG_CFA_RESTORE, cr);
28260 RTX_FRAME_RELATED_P (insn) = 1;
28264 /* Like cr, the move to lr instruction can be scheduled after the
28265 stack deallocation, but unlike cr, its stack frame save is still
28266 valid. So we only need to emit the cfa_restore on the correct
28270 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
28272 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
28273 rtx reg = gen_rtx_REG (Pmode, regno);
28275 emit_move_insn (reg, mem);
28279 restore_saved_lr (int regno, bool exit_func)
28281 rtx reg = gen_rtx_REG (Pmode, regno);
28282 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
28283 rtx_insn *insn = emit_move_insn (lr, reg);
28285 if (!exit_func && flag_shrink_wrap)
28287 add_reg_note (insn, REG_CFA_RESTORE, lr);
28288 RTX_FRAME_RELATED_P (insn) = 1;
28293 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
28295 if (DEFAULT_ABI == ABI_ELFv2)
28298 for (i = 0; i < 8; i++)
28299 if (save_reg_p (CR0_REGNO + i))
28301 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
28302 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
28306 else if (info->cr_save_p)
28307 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28308 gen_rtx_REG (SImode, CR2_REGNO),
28311 if (info->lr_save_p)
28312 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28313 gen_rtx_REG (Pmode, LR_REGNO),
28315 return cfa_restores;
28318 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28319 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28320 below stack pointer not cloberred by signals. */
28323 offset_below_red_zone_p (HOST_WIDE_INT offset)
28325 return offset < (DEFAULT_ABI == ABI_V4
28327 : TARGET_32BIT ? -220 : -288);
28330 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28333 emit_cfa_restores (rtx cfa_restores)
28335 rtx_insn *insn = get_last_insn ();
28336 rtx *loc = ®_NOTES (insn);
28339 loc = &XEXP (*loc, 1);
28340 *loc = cfa_restores;
28341 RTX_FRAME_RELATED_P (insn) = 1;
28344 /* Emit function epilogue as insns. */
28347 rs6000_emit_epilogue (int sibcall)
28349 rs6000_stack_t *info;
28350 int restoring_GPRs_inline;
28351 int restoring_FPRs_inline;
28352 int using_load_multiple;
28353 int using_mtcr_multiple;
28354 int use_backchain_to_restore_sp;
28357 HOST_WIDE_INT frame_off = 0;
28358 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
28359 rtx frame_reg_rtx = sp_reg_rtx;
28360 rtx cfa_restores = NULL_RTX;
28362 rtx cr_save_reg = NULL_RTX;
28363 machine_mode reg_mode = Pmode;
28364 int reg_size = TARGET_32BIT ? 4 : 8;
28365 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
28367 int fp_reg_size = 8;
28370 unsigned ptr_regno;
28372 info = rs6000_stack_info ();
28374 strategy = info->savres_strategy;
28375 using_load_multiple = strategy & REST_MULTIPLE;
28376 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
28377 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
28378 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
28379 || rs6000_cpu == PROCESSOR_PPC603
28380 || rs6000_cpu == PROCESSOR_PPC750
28382 /* Restore via the backchain when we have a large frame, since this
28383 is more efficient than an addis, addi pair. The second condition
28384 here will not trigger at the moment; We don't actually need a
28385 frame pointer for alloca, but the generic parts of the compiler
28386 give us one anyway. */
28387 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
28388 ? info->lr_save_offset
28390 || (cfun->calls_alloca
28391 && !frame_pointer_needed));
28392 restore_lr = (info->lr_save_p
28393 && (restoring_FPRs_inline
28394 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28395 && (restoring_GPRs_inline
28396 || info->first_fp_reg_save < 64)
28397 && !cfun->machine->lr_is_wrapped_separately);
28400 if (WORLD_SAVE_P (info))
28404 const char *alloc_rname;
28407 /* eh_rest_world_r10 will return to the location saved in the LR
28408 stack slot (which is not likely to be our caller.)
28409 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28410 rest_world is similar, except any R10 parameter is ignored.
28411 The exception-handling stuff that was here in 2.95 is no
28412 longer necessary. */
28415 + 32 - info->first_gp_reg_save
28416 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28417 + 63 + 1 - info->first_fp_reg_save);
28419 strcpy (rname, ((crtl->calls_eh_return) ?
28420 "*eh_rest_world_r10" : "*rest_world"));
28421 alloc_rname = ggc_strdup (rname);
28424 RTVEC_ELT (p, j++) = ret_rtx;
28426 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
28427 /* The instruction pattern requires a clobber here;
28428 it is shared with the restVEC helper. */
28430 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
28433 /* CR register traditionally saved as CR2. */
28434 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28436 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28437 if (flag_shrink_wrap)
28439 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28440 gen_rtx_REG (Pmode, LR_REGNO),
28442 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28446 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28448 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28450 = gen_frame_load (reg,
28451 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28452 if (flag_shrink_wrap
28453 && save_reg_p (info->first_gp_reg_save + i))
28454 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28456 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28458 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28460 = gen_frame_load (reg,
28461 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28462 if (flag_shrink_wrap
28463 && save_reg_p (info->first_altivec_reg_save + i))
28464 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28466 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28468 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
28469 ? DFmode : SFmode),
28470 info->first_fp_reg_save + i);
28472 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28473 if (flag_shrink_wrap
28474 && save_reg_p (info->first_fp_reg_save + i))
28475 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28478 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
28480 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
28482 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
28484 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
28486 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28487 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28489 if (flag_shrink_wrap)
28491 REG_NOTES (insn) = cfa_restores;
28492 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28493 RTX_FRAME_RELATED_P (insn) = 1;
28498 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28500 frame_off = info->total_size;
28502 /* Restore AltiVec registers if we must do so before adjusting the
28504 if (info->altivec_size != 0
28505 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28506 || (DEFAULT_ABI != ABI_V4
28507 && offset_below_red_zone_p (info->altivec_save_offset))))
28510 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28512 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28513 if (use_backchain_to_restore_sp)
28515 int frame_regno = 11;
28517 if ((strategy & REST_INLINE_VRS) == 0)
28519 /* Of r11 and r12, select the one not clobbered by an
28520 out-of-line restore function for the frame register. */
28521 frame_regno = 11 + 12 - scratch_regno;
28523 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28524 emit_move_insn (frame_reg_rtx,
28525 gen_rtx_MEM (Pmode, sp_reg_rtx));
28528 else if (frame_pointer_needed)
28529 frame_reg_rtx = hard_frame_pointer_rtx;
28531 if ((strategy & REST_INLINE_VRS) == 0)
28533 int end_save = info->altivec_save_offset + info->altivec_size;
28535 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28536 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28538 if (end_save + frame_off != 0)
28540 rtx offset = GEN_INT (end_save + frame_off);
28542 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28545 emit_move_insn (ptr_reg, frame_reg_rtx);
28547 ptr_off = -end_save;
28548 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28549 info->altivec_save_offset + ptr_off,
28550 0, V4SImode, SAVRES_VR);
28554 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28555 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28557 rtx addr, areg, mem, insn;
28558 rtx reg = gen_rtx_REG (V4SImode, i);
28559 HOST_WIDE_INT offset
28560 = (info->altivec_save_offset + frame_off
28561 + 16 * (i - info->first_altivec_reg_save));
28563 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28565 mem = gen_frame_mem (V4SImode,
28566 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28567 GEN_INT (offset)));
28568 insn = gen_rtx_SET (reg, mem);
28572 areg = gen_rtx_REG (Pmode, 0);
28573 emit_move_insn (areg, GEN_INT (offset));
28575 /* AltiVec addressing mode is [reg+reg]. */
28576 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28577 mem = gen_frame_mem (V4SImode, addr);
28579 /* Rather than emitting a generic move, force use of the
28580 lvx instruction, which we always want. In particular we
28581 don't want lxvd2x/xxpermdi for little endian. */
28582 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28585 (void) emit_insn (insn);
28589 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28590 if (((strategy & REST_INLINE_VRS) == 0
28591 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28592 && (flag_shrink_wrap
28593 || (offset_below_red_zone_p
28594 (info->altivec_save_offset
28595 + 16 * (i - info->first_altivec_reg_save))))
28598 rtx reg = gen_rtx_REG (V4SImode, i);
28599 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28603 /* Restore VRSAVE if we must do so before adjusting the stack. */
28604 if (info->vrsave_size != 0
28605 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28606 || (DEFAULT_ABI != ABI_V4
28607 && offset_below_red_zone_p (info->vrsave_save_offset))))
28611 if (frame_reg_rtx == sp_reg_rtx)
28613 if (use_backchain_to_restore_sp)
28615 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28616 emit_move_insn (frame_reg_rtx,
28617 gen_rtx_MEM (Pmode, sp_reg_rtx));
28620 else if (frame_pointer_needed)
28621 frame_reg_rtx = hard_frame_pointer_rtx;
28624 reg = gen_rtx_REG (SImode, 12);
28625 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28626 info->vrsave_save_offset + frame_off));
28628 emit_insn (generate_set_vrsave (reg, info, 1));
28632 /* If we have a large stack frame, restore the old stack pointer
28633 using the backchain. */
28634 if (use_backchain_to_restore_sp)
28636 if (frame_reg_rtx == sp_reg_rtx)
28638 /* Under V.4, don't reset the stack pointer until after we're done
28639 loading the saved registers. */
28640 if (DEFAULT_ABI == ABI_V4)
28641 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28643 insn = emit_move_insn (frame_reg_rtx,
28644 gen_rtx_MEM (Pmode, sp_reg_rtx));
28647 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28648 && DEFAULT_ABI == ABI_V4)
28649 /* frame_reg_rtx has been set up by the altivec restore. */
28653 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28654 frame_reg_rtx = sp_reg_rtx;
28657 /* If we have a frame pointer, we can restore the old stack pointer
28659 else if (frame_pointer_needed)
28661 frame_reg_rtx = sp_reg_rtx;
28662 if (DEFAULT_ABI == ABI_V4)
28663 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28664 /* Prevent reordering memory accesses against stack pointer restore. */
28665 else if (cfun->calls_alloca
28666 || offset_below_red_zone_p (-info->total_size))
28667 rs6000_emit_stack_tie (frame_reg_rtx, true);
28669 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28670 GEN_INT (info->total_size)));
28673 else if (info->push_p
28674 && DEFAULT_ABI != ABI_V4
28675 && !crtl->calls_eh_return)
28677 /* Prevent reordering memory accesses against stack pointer restore. */
28678 if (cfun->calls_alloca
28679 || offset_below_red_zone_p (-info->total_size))
28680 rs6000_emit_stack_tie (frame_reg_rtx, false);
28681 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28682 GEN_INT (info->total_size)));
28685 if (insn && frame_reg_rtx == sp_reg_rtx)
28689 REG_NOTES (insn) = cfa_restores;
28690 cfa_restores = NULL_RTX;
28692 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28693 RTX_FRAME_RELATED_P (insn) = 1;
28696 /* Restore AltiVec registers if we have not done so already. */
28697 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28698 && info->altivec_size != 0
28699 && (DEFAULT_ABI == ABI_V4
28700 || !offset_below_red_zone_p (info->altivec_save_offset)))
28704 if ((strategy & REST_INLINE_VRS) == 0)
28706 int end_save = info->altivec_save_offset + info->altivec_size;
28708 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28709 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28710 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28712 if (end_save + frame_off != 0)
28714 rtx offset = GEN_INT (end_save + frame_off);
28716 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28719 emit_move_insn (ptr_reg, frame_reg_rtx);
28721 ptr_off = -end_save;
28722 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28723 info->altivec_save_offset + ptr_off,
28724 0, V4SImode, SAVRES_VR);
28725 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28727 /* Frame reg was clobbered by out-of-line save. Restore it
28728 from ptr_reg, and if we are calling out-of-line gpr or
28729 fpr restore set up the correct pointer and offset. */
28730 unsigned newptr_regno = 1;
28731 if (!restoring_GPRs_inline)
28733 bool lr = info->gp_save_offset + info->gp_size == 0;
28734 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28735 newptr_regno = ptr_regno_for_savres (sel);
28736 end_save = info->gp_save_offset + info->gp_size;
28738 else if (!restoring_FPRs_inline)
28740 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28741 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28742 newptr_regno = ptr_regno_for_savres (sel);
28743 end_save = info->fp_save_offset + info->fp_size;
28746 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28747 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28749 if (end_save + ptr_off != 0)
28751 rtx offset = GEN_INT (end_save + ptr_off);
28753 frame_off = -end_save;
28755 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28758 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28763 frame_off = ptr_off;
28764 emit_move_insn (frame_reg_rtx, ptr_reg);
28770 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28771 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28773 rtx addr, areg, mem, insn;
28774 rtx reg = gen_rtx_REG (V4SImode, i);
28775 HOST_WIDE_INT offset
28776 = (info->altivec_save_offset + frame_off
28777 + 16 * (i - info->first_altivec_reg_save));
28779 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28781 mem = gen_frame_mem (V4SImode,
28782 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28783 GEN_INT (offset)));
28784 insn = gen_rtx_SET (reg, mem);
28788 areg = gen_rtx_REG (Pmode, 0);
28789 emit_move_insn (areg, GEN_INT (offset));
28791 /* AltiVec addressing mode is [reg+reg]. */
28792 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28793 mem = gen_frame_mem (V4SImode, addr);
28795 /* Rather than emitting a generic move, force use of the
28796 lvx instruction, which we always want. In particular we
28797 don't want lxvd2x/xxpermdi for little endian. */
28798 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28801 (void) emit_insn (insn);
28805 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28806 if (((strategy & REST_INLINE_VRS) == 0
28807 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28808 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28811 rtx reg = gen_rtx_REG (V4SImode, i);
28812 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28816 /* Restore VRSAVE if we have not done so already. */
28817 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28818 && info->vrsave_size != 0
28819 && (DEFAULT_ABI == ABI_V4
28820 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28824 reg = gen_rtx_REG (SImode, 12);
28825 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28826 info->vrsave_save_offset + frame_off));
28828 emit_insn (generate_set_vrsave (reg, info, 1));
28831 /* If we exit by an out-of-line restore function on ABI_V4 then that
28832 function will deallocate the stack, so we don't need to worry
28833 about the unwinder restoring cr from an invalid stack frame
28835 exit_func = (!restoring_FPRs_inline
28836 || (!restoring_GPRs_inline
28837 && info->first_fp_reg_save == 64));
28839 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28840 *separate* slots if the routine calls __builtin_eh_return, so
28841 that they can be independently restored by the unwinder. */
28842 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28844 int i, cr_off = info->ehcr_offset;
28846 for (i = 0; i < 8; i++)
28847 if (!call_used_regs[CR0_REGNO + i])
28849 rtx reg = gen_rtx_REG (SImode, 0);
28850 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28851 cr_off + frame_off));
28853 insn = emit_insn (gen_movsi_to_cr_one
28854 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28856 if (!exit_func && flag_shrink_wrap)
28858 add_reg_note (insn, REG_CFA_RESTORE,
28859 gen_rtx_REG (SImode, CR0_REGNO + i));
28861 RTX_FRAME_RELATED_P (insn) = 1;
28864 cr_off += reg_size;
28868 /* Get the old lr if we saved it. If we are restoring registers
28869 out-of-line, then the out-of-line routines can do this for us. */
28870 if (restore_lr && restoring_GPRs_inline)
28871 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28873 /* Get the old cr if we saved it. */
28874 if (info->cr_save_p)
28876 unsigned cr_save_regno = 12;
28878 if (!restoring_GPRs_inline)
28880 /* Ensure we don't use the register used by the out-of-line
28881 gpr register restore below. */
28882 bool lr = info->gp_save_offset + info->gp_size == 0;
28883 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28884 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28886 if (gpr_ptr_regno == 12)
28887 cr_save_regno = 11;
28888 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28890 else if (REGNO (frame_reg_rtx) == 12)
28891 cr_save_regno = 11;
28893 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28894 info->cr_save_offset + frame_off,
28898 /* Set LR here to try to overlap restores below. */
28899 if (restore_lr && restoring_GPRs_inline)
28900 restore_saved_lr (0, exit_func);
28902 /* Load exception handler data registers, if needed. */
28903 if (crtl->calls_eh_return)
28905 unsigned int i, regno;
28909 rtx reg = gen_rtx_REG (reg_mode, 2);
28910 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28911 frame_off + RS6000_TOC_SAVE_SLOT));
28918 regno = EH_RETURN_DATA_REGNO (i);
28919 if (regno == INVALID_REGNUM)
28922 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28923 info->ehrd_offset + frame_off
28924 + reg_size * (int) i);
28926 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28930 /* Restore GPRs. This is done as a PARALLEL if we are using
28931 the load-multiple instructions. */
28932 if (!restoring_GPRs_inline)
28934 /* We are jumping to an out-of-line function. */
28936 int end_save = info->gp_save_offset + info->gp_size;
28937 bool can_use_exit = end_save == 0;
28938 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28941 /* Emit stack reset code if we need it. */
28942 ptr_regno = ptr_regno_for_savres (sel);
28943 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28945 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28946 else if (end_save + frame_off != 0)
28947 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28948 GEN_INT (end_save + frame_off)));
28949 else if (REGNO (frame_reg_rtx) != ptr_regno)
28950 emit_move_insn (ptr_reg, frame_reg_rtx);
28951 if (REGNO (frame_reg_rtx) == ptr_regno)
28952 frame_off = -end_save;
28954 if (can_use_exit && info->cr_save_p)
28955 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28957 ptr_off = -end_save;
28958 rs6000_emit_savres_rtx (info, ptr_reg,
28959 info->gp_save_offset + ptr_off,
28960 info->lr_save_offset + ptr_off,
28963 else if (using_load_multiple)
28966 p = rtvec_alloc (32 - info->first_gp_reg_save);
28967 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28969 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28971 info->gp_save_offset + frame_off + reg_size * i);
28972 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28976 int offset = info->gp_save_offset + frame_off;
28977 for (i = info->first_gp_reg_save; i < 32; i++)
28980 && !cfun->machine->gpr_is_wrapped_separately[i])
28982 rtx reg = gen_rtx_REG (reg_mode, i);
28983 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28986 offset += reg_size;
28990 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28992 /* If the frame pointer was used then we can't delay emitting
28993 a REG_CFA_DEF_CFA note. This must happen on the insn that
28994 restores the frame pointer, r31. We may have already emitted
28995 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28996 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28997 be harmless if emitted. */
28998 if (frame_pointer_needed)
29000 insn = get_last_insn ();
29001 add_reg_note (insn, REG_CFA_DEF_CFA,
29002 plus_constant (Pmode, frame_reg_rtx, frame_off));
29003 RTX_FRAME_RELATED_P (insn) = 1;
29006 /* Set up cfa_restores. We always need these when
29007 shrink-wrapping. If not shrink-wrapping then we only need
29008 the cfa_restore when the stack location is no longer valid.
29009 The cfa_restores must be emitted on or before the insn that
29010 invalidates the stack, and of course must not be emitted
29011 before the insn that actually does the restore. The latter
29012 is why it is a bad idea to emit the cfa_restores as a group
29013 on the last instruction here that actually does a restore:
29014 That insn may be reordered with respect to others doing
29016 if (flag_shrink_wrap
29017 && !restoring_GPRs_inline
29018 && info->first_fp_reg_save == 64)
29019 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29021 for (i = info->first_gp_reg_save; i < 32; i++)
29023 && !cfun->machine->gpr_is_wrapped_separately[i])
29025 rtx reg = gen_rtx_REG (reg_mode, i);
29026 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29030 if (!restoring_GPRs_inline
29031 && info->first_fp_reg_save == 64)
29033 /* We are jumping to an out-of-line function. */
29035 emit_cfa_restores (cfa_restores);
29039 if (restore_lr && !restoring_GPRs_inline)
29041 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
29042 restore_saved_lr (0, exit_func);
29045 /* Restore fpr's if we need to do it without calling a function. */
29046 if (restoring_FPRs_inline)
29048 int offset = info->fp_save_offset + frame_off;
29049 for (i = info->first_fp_reg_save; i < 64; i++)
29052 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
29054 rtx reg = gen_rtx_REG (fp_reg_mode, i);
29055 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
29056 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
29057 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
29061 offset += fp_reg_size;
29065 /* If we saved cr, restore it here. Just those that were used. */
29066 if (info->cr_save_p)
29067 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
29069 /* If this is V.4, unwind the stack pointer after all of the loads
29070 have been done, or set up r11 if we are restoring fp out of line. */
29072 if (!restoring_FPRs_inline)
29074 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29075 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
29076 ptr_regno = ptr_regno_for_savres (sel);
29079 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
29080 if (REGNO (frame_reg_rtx) == ptr_regno)
29083 if (insn && restoring_FPRs_inline)
29087 REG_NOTES (insn) = cfa_restores;
29088 cfa_restores = NULL_RTX;
29090 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
29091 RTX_FRAME_RELATED_P (insn) = 1;
29094 if (crtl->calls_eh_return)
29096 rtx sa = EH_RETURN_STACKADJ_RTX;
29097 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
29100 if (!sibcall && restoring_FPRs_inline)
29104 /* We can't hang the cfa_restores off a simple return,
29105 since the shrink-wrap code sometimes uses an existing
29106 return. This means there might be a path from
29107 pre-prologue code to this return, and dwarf2cfi code
29108 wants the eh_frame unwinder state to be the same on
29109 all paths to any point. So we need to emit the
29110 cfa_restores before the return. For -m64 we really
29111 don't need epilogue cfa_restores at all, except for
29112 this irritating dwarf2cfi with shrink-wrap
29113 requirement; The stack red-zone means eh_frame info
29114 from the prologue telling the unwinder to restore
29115 from the stack is perfectly good right to the end of
29117 emit_insn (gen_blockage ());
29118 emit_cfa_restores (cfa_restores);
29119 cfa_restores = NULL_RTX;
29122 emit_jump_insn (targetm.gen_simple_return ());
29125 if (!sibcall && !restoring_FPRs_inline)
29127 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29128 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
29130 RTVEC_ELT (p, elt++) = ret_rtx;
29132 RTVEC_ELT (p, elt++)
29133 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
29135 /* We have to restore more than two FP registers, so branch to the
29136 restore function. It will return to our caller. */
29141 if (flag_shrink_wrap)
29142 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29144 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
29145 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
29146 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
29147 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
29149 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
29151 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
29153 RTVEC_ELT (p, elt++)
29154 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
29155 if (flag_shrink_wrap
29156 && save_reg_p (info->first_fp_reg_save + i))
29157 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29160 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
29166 /* Ensure the cfa_restores are hung off an insn that won't
29167 be reordered above other restores. */
29168 emit_insn (gen_blockage ());
29170 emit_cfa_restores (cfa_restores);
29174 /* Write function epilogue. */
29177 rs6000_output_function_epilogue (FILE *file)
29180 macho_branch_islands ();
29183 rtx_insn *insn = get_last_insn ();
29184 rtx_insn *deleted_debug_label = NULL;
29186 /* Mach-O doesn't support labels at the end of objects, so if
29187 it looks like we might want one, take special action.
29189 First, collect any sequence of deleted debug labels. */
29192 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
29194 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29195 notes only, instead set their CODE_LABEL_NUMBER to -1,
29196 otherwise there would be code generation differences
29197 in between -g and -g0. */
29198 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29199 deleted_debug_label = insn;
29200 insn = PREV_INSN (insn);
29203 /* Second, if we have:
29206 then this needs to be detected, so skip past the barrier. */
29208 if (insn && BARRIER_P (insn))
29209 insn = PREV_INSN (insn);
29211 /* Up to now we've only seen notes or barriers. */
29216 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
29217 /* Trailing label: <barrier>. */
29218 fputs ("\tnop\n", file);
29221 /* Lastly, see if we have a completely empty function body. */
29222 while (insn && ! INSN_P (insn))
29223 insn = PREV_INSN (insn);
29224 /* If we don't find any insns, we've got an empty function body;
29225 I.e. completely empty - without a return or branch. This is
29226 taken as the case where a function body has been removed
29227 because it contains an inline __builtin_unreachable(). GCC
29228 states that reaching __builtin_unreachable() means UB so we're
29229 not obliged to do anything special; however, we want
29230 non-zero-sized function bodies. To meet this, and help the
29231 user out, let's trap the case. */
29233 fputs ("\ttrap\n", file);
29236 else if (deleted_debug_label)
29237 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
29238 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29239 CODE_LABEL_NUMBER (insn) = -1;
29243 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29246 We don't output a traceback table if -finhibit-size-directive was
29247 used. The documentation for -finhibit-size-directive reads
29248 ``don't output a @code{.size} assembler directive, or anything
29249 else that would cause trouble if the function is split in the
29250 middle, and the two halves are placed at locations far apart in
29251 memory.'' The traceback table has this property, since it
29252 includes the offset from the start of the function to the
29253 traceback table itself.
29255 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29256 different traceback table. */
29257 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29258 && ! flag_inhibit_size_directive
29259 && rs6000_traceback != traceback_none && !cfun->is_thunk)
29261 const char *fname = NULL;
29262 const char *language_string = lang_hooks.name;
29263 int fixed_parms = 0, float_parms = 0, parm_info = 0;
29265 int optional_tbtab;
29266 rs6000_stack_t *info = rs6000_stack_info ();
29268 if (rs6000_traceback == traceback_full)
29269 optional_tbtab = 1;
29270 else if (rs6000_traceback == traceback_part)
29271 optional_tbtab = 0;
29273 optional_tbtab = !optimize_size && !TARGET_ELF;
29275 if (optional_tbtab)
29277 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
29278 while (*fname == '.') /* V.4 encodes . in the name */
29281 /* Need label immediately before tbtab, so we can compute
29282 its offset from the function start. */
29283 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29284 ASM_OUTPUT_LABEL (file, fname);
29287 /* The .tbtab pseudo-op can only be used for the first eight
29288 expressions, since it can't handle the possibly variable
29289 length fields that follow. However, if you omit the optional
29290 fields, the assembler outputs zeros for all optional fields
29291 anyways, giving each variable length field is minimum length
29292 (as defined in sys/debug.h). Thus we can not use the .tbtab
29293 pseudo-op at all. */
29295 /* An all-zero word flags the start of the tbtab, for debuggers
29296 that have to find it by searching forward from the entry
29297 point or from the current pc. */
29298 fputs ("\t.long 0\n", file);
29300 /* Tbtab format type. Use format type 0. */
29301 fputs ("\t.byte 0,", file);
29303 /* Language type. Unfortunately, there does not seem to be any
29304 official way to discover the language being compiled, so we
29305 use language_string.
29306 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
29307 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29308 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
29309 either, so for now use 0. */
29311 || ! strcmp (language_string, "GNU GIMPLE")
29312 || ! strcmp (language_string, "GNU Go")
29313 || ! strcmp (language_string, "libgccjit"))
29315 else if (! strcmp (language_string, "GNU F77")
29316 || lang_GNU_Fortran ())
29318 else if (! strcmp (language_string, "GNU Pascal"))
29320 else if (! strcmp (language_string, "GNU Ada"))
29322 else if (lang_GNU_CXX ()
29323 || ! strcmp (language_string, "GNU Objective-C++"))
29325 else if (! strcmp (language_string, "GNU Java"))
29327 else if (! strcmp (language_string, "GNU Objective-C"))
29330 gcc_unreachable ();
29331 fprintf (file, "%d,", i);
29333 /* 8 single bit fields: global linkage (not set for C extern linkage,
29334 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29335 from start of procedure stored in tbtab, internal function, function
29336 has controlled storage, function has no toc, function uses fp,
29337 function logs/aborts fp operations. */
29338 /* Assume that fp operations are used if any fp reg must be saved. */
29339 fprintf (file, "%d,",
29340 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
29342 /* 6 bitfields: function is interrupt handler, name present in
29343 proc table, function calls alloca, on condition directives
29344 (controls stack walks, 3 bits), saves condition reg, saves
29346 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29347 set up as a frame pointer, even when there is no alloca call. */
29348 fprintf (file, "%d,",
29349 ((optional_tbtab << 6)
29350 | ((optional_tbtab & frame_pointer_needed) << 5)
29351 | (info->cr_save_p << 1)
29352 | (info->lr_save_p)));
29354 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29356 fprintf (file, "%d,",
29357 (info->push_p << 7) | (64 - info->first_fp_reg_save));
29359 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29360 fprintf (file, "%d,", (32 - first_reg_to_save ()));
29362 if (optional_tbtab)
29364 /* Compute the parameter info from the function decl argument
29367 int next_parm_info_bit = 31;
29369 for (decl = DECL_ARGUMENTS (current_function_decl);
29370 decl; decl = DECL_CHAIN (decl))
29372 rtx parameter = DECL_INCOMING_RTL (decl);
29373 machine_mode mode = GET_MODE (parameter);
29375 if (GET_CODE (parameter) == REG)
29377 if (SCALAR_FLOAT_MODE_P (mode))
29400 gcc_unreachable ();
29403 /* If only one bit will fit, don't or in this entry. */
29404 if (next_parm_info_bit > 0)
29405 parm_info |= (bits << (next_parm_info_bit - 1));
29406 next_parm_info_bit -= 2;
29410 fixed_parms += ((GET_MODE_SIZE (mode)
29411 + (UNITS_PER_WORD - 1))
29413 next_parm_info_bit -= 1;
29419 /* Number of fixed point parameters. */
29420 /* This is actually the number of words of fixed point parameters; thus
29421 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29422 fprintf (file, "%d,", fixed_parms);
29424 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29426 /* This is actually the number of fp registers that hold parameters;
29427 and thus the maximum value is 13. */
29428 /* Set parameters on stack bit if parameters are not in their original
29429 registers, regardless of whether they are on the stack? Xlc
29430 seems to set the bit when not optimizing. */
29431 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29433 if (optional_tbtab)
29435 /* Optional fields follow. Some are variable length. */
29437 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29438 float, 11 double float. */
29439 /* There is an entry for each parameter in a register, in the order
29440 that they occur in the parameter list. Any intervening arguments
29441 on the stack are ignored. If the list overflows a long (max
29442 possible length 34 bits) then completely leave off all elements
29444 /* Only emit this long if there was at least one parameter. */
29445 if (fixed_parms || float_parms)
29446 fprintf (file, "\t.long %d\n", parm_info);
29448 /* Offset from start of code to tb table. */
29449 fputs ("\t.long ", file);
29450 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29451 RS6000_OUTPUT_BASENAME (file, fname);
29453 rs6000_output_function_entry (file, fname);
29456 /* Interrupt handler mask. */
29457 /* Omit this long, since we never set the interrupt handler bit
29460 /* Number of CTL (controlled storage) anchors. */
29461 /* Omit this long, since the has_ctl bit is never set above. */
29463 /* Displacement into stack of each CTL anchor. */
29464 /* Omit this list of longs, because there are no CTL anchors. */
29466 /* Length of function name. */
29469 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29471 /* Function name. */
29472 assemble_string (fname, strlen (fname));
29474 /* Register for alloca automatic storage; this is always reg 31.
29475 Only emit this if the alloca bit was set above. */
29476 if (frame_pointer_needed)
29477 fputs ("\t.byte 31\n", file);
29479 fputs ("\t.align 2\n", file);
29483 /* Arrange to define .LCTOC1 label, if not already done. */
29487 if (!toc_initialized)
29489 switch_to_section (toc_section);
29490 switch_to_section (current_function_section ());
29495 /* -fsplit-stack support. */
29497 /* A SYMBOL_REF for __morestack. */
29498 static GTY(()) rtx morestack_ref;
29501 gen_add3_const (rtx rt, rtx ra, long c)
29504 return gen_adddi3 (rt, ra, GEN_INT (c));
29506 return gen_addsi3 (rt, ra, GEN_INT (c));
29509 /* Emit -fsplit-stack prologue, which goes before the regular function
29510 prologue (at local entry point in the case of ELFv2). */
29513 rs6000_expand_split_stack_prologue (void)
29515 rs6000_stack_t *info = rs6000_stack_info ();
29516 unsigned HOST_WIDE_INT allocate;
29517 long alloc_hi, alloc_lo;
29518 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29521 gcc_assert (flag_split_stack && reload_completed);
29526 if (global_regs[29])
29528 error ("%qs uses register r29", "-fsplit-stack");
29529 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29530 "conflicts with %qD", global_regs_decl[29]);
29533 allocate = info->total_size;
29534 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29536 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29539 if (morestack_ref == NULL_RTX)
29541 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29542 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29543 | SYMBOL_FLAG_FUNCTION);
29546 r0 = gen_rtx_REG (Pmode, 0);
29547 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29548 r12 = gen_rtx_REG (Pmode, 12);
29549 emit_insn (gen_load_split_stack_limit (r0));
29550 /* Always emit two insns here to calculate the requested stack,
29551 so that the linker can edit them when adjusting size for calling
29552 non-split-stack code. */
29553 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29554 alloc_lo = -allocate - alloc_hi;
29557 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29559 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29561 emit_insn (gen_nop ());
29565 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29566 emit_insn (gen_nop ());
29569 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29570 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29571 ok_label = gen_label_rtx ();
29572 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29573 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29574 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29576 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29577 JUMP_LABEL (insn) = ok_label;
29578 /* Mark the jump as very likely to be taken. */
29579 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29581 lr = gen_rtx_REG (Pmode, LR_REGNO);
29582 insn = emit_move_insn (r0, lr);
29583 RTX_FRAME_RELATED_P (insn) = 1;
29584 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29585 RTX_FRAME_RELATED_P (insn) = 1;
29587 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29588 const0_rtx, const0_rtx));
29589 call_fusage = NULL_RTX;
29590 use_reg (&call_fusage, r12);
29591 /* Say the call uses r0, even though it doesn't, to stop regrename
29592 from twiddling with the insns saving lr, trashing args for cfun.
29593 The insns restoring lr are similarly protected by making
29594 split_stack_return use r0. */
29595 use_reg (&call_fusage, r0);
29596 add_function_usage_to (insn, call_fusage);
29597 /* Indicate that this function can't jump to non-local gotos. */
29598 make_reg_eh_region_note_nothrow_nononlocal (insn);
29599 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29600 insn = emit_move_insn (lr, r0);
29601 add_reg_note (insn, REG_CFA_RESTORE, lr);
29602 RTX_FRAME_RELATED_P (insn) = 1;
29603 emit_insn (gen_split_stack_return ());
29605 emit_label (ok_label);
29606 LABEL_NUSES (ok_label) = 1;
29609 /* Return the internal arg pointer used for function incoming
29610 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29611 to copy it to a pseudo in order for it to be preserved over calls
29612 and suchlike. We'd really like to use a pseudo here for the
29613 internal arg pointer but data-flow analysis is not prepared to
29614 accept pseudos as live at the beginning of a function. */
29617 rs6000_internal_arg_pointer (void)
29619 if (flag_split_stack
29620 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29624 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29628 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29629 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29631 /* Put the pseudo initialization right after the note at the
29632 beginning of the function. */
29633 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29634 gen_rtx_REG (Pmode, 12));
29635 push_topmost_sequence ();
29636 emit_insn_after (pat, get_insns ());
29637 pop_topmost_sequence ();
29639 return plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29640 FIRST_PARM_OFFSET (current_function_decl));
29642 return virtual_incoming_args_rtx;
29645 /* We may have to tell the dataflow pass that the split stack prologue
29646 is initializing a register. */
29649 rs6000_live_on_entry (bitmap regs)
29651 if (flag_split_stack)
29652 bitmap_set_bit (regs, 12);
29655 /* Emit -fsplit-stack dynamic stack allocation space check. */
29658 rs6000_split_stack_space_check (rtx size, rtx label)
29660 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29661 rtx limit = gen_reg_rtx (Pmode);
29662 rtx requested = gen_reg_rtx (Pmode);
29663 rtx cmp = gen_reg_rtx (CCUNSmode);
29666 emit_insn (gen_load_split_stack_limit (limit));
29667 if (CONST_INT_P (size))
29668 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29671 size = force_reg (Pmode, size);
29672 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29674 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29675 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29676 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29677 gen_rtx_LABEL_REF (VOIDmode, label),
29679 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29680 JUMP_LABEL (jump) = label;
29683 /* A C compound statement that outputs the assembler code for a thunk
29684 function, used to implement C++ virtual function calls with
29685 multiple inheritance. The thunk acts as a wrapper around a virtual
29686 function, adjusting the implicit object parameter before handing
29687 control off to the real function.
29689 First, emit code to add the integer DELTA to the location that
29690 contains the incoming first argument. Assume that this argument
29691 contains a pointer, and is the one used to pass the `this' pointer
29692 in C++. This is the incoming argument *before* the function
29693 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29694 values of all other incoming arguments.
29696 After the addition, emit code to jump to FUNCTION, which is a
29697 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29698 not touch the return address. Hence returning from FUNCTION will
29699 return to whoever called the current `thunk'.
29701 The effect must be as if FUNCTION had been called directly with the
29702 adjusted first argument. This macro is responsible for emitting
29703 all of the code for a thunk function; output_function_prologue()
29704 and output_function_epilogue() are not invoked.
29706 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29707 been extracted from it.) It might possibly be useful on some
29708 targets, but probably not.
29710 If you do not define this macro, the target-independent code in the
29711 C++ frontend will generate a less efficient heavyweight thunk that
29712 calls FUNCTION instead of jumping to it. The generic approach does
29713 not support varargs. */
29716 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29717 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29720 rtx this_rtx, funexp;
29723 reload_completed = 1;
29724 epilogue_completed = 1;
29726 /* Mark the end of the (empty) prologue. */
29727 emit_note (NOTE_INSN_PROLOGUE_END);
29729 /* Find the "this" pointer. If the function returns a structure,
29730 the structure return pointer is in r3. */
29731 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29732 this_rtx = gen_rtx_REG (Pmode, 4);
29734 this_rtx = gen_rtx_REG (Pmode, 3);
29736 /* Apply the constant offset, if required. */
29738 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29740 /* Apply the offset from the vtable, if required. */
29743 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29744 rtx tmp = gen_rtx_REG (Pmode, 12);
29746 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29747 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29749 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29750 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29754 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29756 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29758 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29761 /* Generate a tail call to the target function. */
29762 if (!TREE_USED (function))
29764 assemble_external (function);
29765 TREE_USED (function) = 1;
29767 funexp = XEXP (DECL_RTL (function), 0);
29768 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29771 if (MACHOPIC_INDIRECT)
29772 funexp = machopic_indirect_call_target (funexp);
29775 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29776 generate sibcall RTL explicitly. */
29777 insn = emit_call_insn (
29778 gen_rtx_PARALLEL (VOIDmode,
29780 gen_rtx_CALL (VOIDmode,
29781 funexp, const0_rtx),
29782 gen_rtx_USE (VOIDmode, const0_rtx),
29783 simple_return_rtx)));
29784 SIBLING_CALL_P (insn) = 1;
29787 /* Run just enough of rest_of_compilation to get the insns emitted.
29788 There's not really enough bulk here to make other passes such as
29789 instruction scheduling worth while. Note that use_thunk calls
29790 assemble_start_function and assemble_end_function. */
29791 insn = get_insns ();
29792 shorten_branches (insn);
29793 final_start_function (insn, file, 1);
29794 final (insn, file, 1);
29795 final_end_function ();
29797 reload_completed = 0;
29798 epilogue_completed = 0;
29801 /* A quick summary of the various types of 'constant-pool tables'
29804 Target Flags Name One table per
29805 AIX (none) AIX TOC object file
29806 AIX -mfull-toc AIX TOC object file
29807 AIX -mminimal-toc AIX minimal TOC translation unit
29808 SVR4/EABI (none) SVR4 SDATA object file
29809 SVR4/EABI -fpic SVR4 pic object file
29810 SVR4/EABI -fPIC SVR4 PIC translation unit
29811 SVR4/EABI -mrelocatable EABI TOC function
29812 SVR4/EABI -maix AIX TOC object file
29813 SVR4/EABI -maix -mminimal-toc
29814 AIX minimal TOC translation unit
29816 Name Reg. Set by entries contains:
29817 made by addrs? fp? sum?
29819 AIX TOC 2 crt0 as Y option option
29820 AIX minimal TOC 30 prolog gcc Y Y option
29821 SVR4 SDATA 13 crt0 gcc N Y N
29822 SVR4 pic 30 prolog ld Y not yet N
29823 SVR4 PIC 30 prolog gcc Y option option
29824 EABI TOC 30 prolog gcc Y option option
29828 /* Hash functions for the hash table. */
29831 rs6000_hash_constant (rtx k)
29833 enum rtx_code code = GET_CODE (k);
29834 machine_mode mode = GET_MODE (k);
29835 unsigned result = (code << 3) ^ mode;
29836 const char *format;
29839 format = GET_RTX_FORMAT (code);
29840 flen = strlen (format);
29846 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29848 case CONST_WIDE_INT:
29851 flen = CONST_WIDE_INT_NUNITS (k);
29852 for (i = 0; i < flen; i++)
29853 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29858 if (mode != VOIDmode)
29859 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29871 for (; fidx < flen; fidx++)
29872 switch (format[fidx])
29877 const char *str = XSTR (k, fidx);
29878 len = strlen (str);
29879 result = result * 613 + len;
29880 for (i = 0; i < len; i++)
29881 result = result * 613 + (unsigned) str[i];
29886 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29890 result = result * 613 + (unsigned) XINT (k, fidx);
29893 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29894 result = result * 613 + (unsigned) XWINT (k, fidx);
29898 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29899 result = result * 613 + (unsigned) (XWINT (k, fidx)
29906 gcc_unreachable ();
29913 toc_hasher::hash (toc_hash_struct *thc)
29915 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29918 /* Compare H1 and H2 for equivalence. */
29921 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29926 if (h1->key_mode != h2->key_mode)
29929 return rtx_equal_p (r1, r2);
29932 /* These are the names given by the C++ front-end to vtables, and
29933 vtable-like objects. Ideally, this logic should not be here;
29934 instead, there should be some programmatic way of inquiring as
29935 to whether or not an object is a vtable. */
29937 #define VTABLE_NAME_P(NAME) \
29938 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29939 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29940 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29941 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29942 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29944 #ifdef NO_DOLLAR_IN_LABEL
29945 /* Return a GGC-allocated character string translating dollar signs in
29946 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29949 rs6000_xcoff_strip_dollar (const char *name)
29955 q = (const char *) strchr (name, '$');
29957 if (q == 0 || q == name)
29960 len = strlen (name);
29961 strip = XALLOCAVEC (char, len + 1);
29962 strcpy (strip, name);
29963 p = strip + (q - name);
29967 p = strchr (p + 1, '$');
29970 return ggc_alloc_string (strip, len);
29975 rs6000_output_symbol_ref (FILE *file, rtx x)
29977 const char *name = XSTR (x, 0);
29979 /* Currently C++ toc references to vtables can be emitted before it
29980 is decided whether the vtable is public or private. If this is
29981 the case, then the linker will eventually complain that there is
29982 a reference to an unknown section. Thus, for vtables only,
29983 we emit the TOC reference to reference the identifier and not the
29985 if (VTABLE_NAME_P (name))
29987 RS6000_OUTPUT_BASENAME (file, name);
29990 assemble_name (file, name);
29993 /* Output a TOC entry. We derive the entry name from what is being
29997 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
30000 const char *name = buf;
30002 HOST_WIDE_INT offset = 0;
30004 gcc_assert (!TARGET_NO_TOC);
30006 /* When the linker won't eliminate them, don't output duplicate
30007 TOC entries (this happens on AIX if there is any kind of TOC,
30008 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
30010 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
30012 struct toc_hash_struct *h;
30014 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
30015 time because GGC is not initialized at that point. */
30016 if (toc_hash_table == NULL)
30017 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
30019 h = ggc_alloc<toc_hash_struct> ();
30021 h->key_mode = mode;
30022 h->labelno = labelno;
30024 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
30025 if (*found == NULL)
30027 else /* This is indeed a duplicate.
30028 Set this label equal to that label. */
30030 fputs ("\t.set ", file);
30031 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30032 fprintf (file, "%d,", labelno);
30033 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30034 fprintf (file, "%d\n", ((*found)->labelno));
30037 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
30038 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
30039 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
30041 fputs ("\t.set ", file);
30042 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30043 fprintf (file, "%d,", labelno);
30044 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30045 fprintf (file, "%d\n", ((*found)->labelno));
30052 /* If we're going to put a double constant in the TOC, make sure it's
30053 aligned properly when strict alignment is on. */
30054 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
30055 && STRICT_ALIGNMENT
30056 && GET_MODE_BITSIZE (mode) >= 64
30057 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
30058 ASM_OUTPUT_ALIGN (file, 3);
30061 (*targetm.asm_out.internal_label) (file, "LC", labelno);
30063 /* Handle FP constants specially. Note that if we have a minimal
30064 TOC, things we put here aren't actually in the TOC, so we can allow
30066 if (GET_CODE (x) == CONST_DOUBLE &&
30067 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
30068 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
30072 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30073 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
30075 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30079 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30080 fputs (DOUBLE_INT_ASM_OP, file);
30082 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30083 k[0] & 0xffffffff, k[1] & 0xffffffff,
30084 k[2] & 0xffffffff, k[3] & 0xffffffff);
30085 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
30086 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30087 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
30088 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
30089 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
30094 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30095 fputs ("\t.long ", file);
30097 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30098 k[0] & 0xffffffff, k[1] & 0xffffffff,
30099 k[2] & 0xffffffff, k[3] & 0xffffffff);
30100 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
30101 k[0] & 0xffffffff, k[1] & 0xffffffff,
30102 k[2] & 0xffffffff, k[3] & 0xffffffff);
30106 else if (GET_CODE (x) == CONST_DOUBLE &&
30107 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
30111 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30112 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
30114 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30118 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30119 fputs (DOUBLE_INT_ASM_OP, file);
30121 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30122 k[0] & 0xffffffff, k[1] & 0xffffffff);
30123 fprintf (file, "0x%lx%08lx\n",
30124 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30125 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
30130 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30131 fputs ("\t.long ", file);
30133 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30134 k[0] & 0xffffffff, k[1] & 0xffffffff);
30135 fprintf (file, "0x%lx,0x%lx\n",
30136 k[0] & 0xffffffff, k[1] & 0xffffffff);
30140 else if (GET_CODE (x) == CONST_DOUBLE &&
30141 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
30145 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30146 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
30148 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
30152 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30153 fputs (DOUBLE_INT_ASM_OP, file);
30155 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30156 if (WORDS_BIG_ENDIAN)
30157 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
30159 fprintf (file, "0x%lx\n", l & 0xffffffff);
30164 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30165 fputs ("\t.long ", file);
30167 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30168 fprintf (file, "0x%lx\n", l & 0xffffffff);
30172 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
30174 unsigned HOST_WIDE_INT low;
30175 HOST_WIDE_INT high;
30177 low = INTVAL (x) & 0xffffffff;
30178 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
30180 /* TOC entries are always Pmode-sized, so when big-endian
30181 smaller integer constants in the TOC need to be padded.
30182 (This is still a win over putting the constants in
30183 a separate constant pool, because then we'd have
30184 to have both a TOC entry _and_ the actual constant.)
30186 For a 32-bit target, CONST_INT values are loaded and shifted
30187 entirely within `low' and can be stored in one TOC entry. */
30189 /* It would be easy to make this work, but it doesn't now. */
30190 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
30192 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
30195 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
30196 high = (HOST_WIDE_INT) low >> 32;
30202 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30203 fputs (DOUBLE_INT_ASM_OP, file);
30205 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30206 (long) high & 0xffffffff, (long) low & 0xffffffff);
30207 fprintf (file, "0x%lx%08lx\n",
30208 (long) high & 0xffffffff, (long) low & 0xffffffff);
30213 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
30215 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30216 fputs ("\t.long ", file);
30218 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30219 (long) high & 0xffffffff, (long) low & 0xffffffff);
30220 fprintf (file, "0x%lx,0x%lx\n",
30221 (long) high & 0xffffffff, (long) low & 0xffffffff);
30225 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30226 fputs ("\t.long ", file);
30228 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
30229 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
30235 if (GET_CODE (x) == CONST)
30237 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
30238 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
30240 base = XEXP (XEXP (x, 0), 0);
30241 offset = INTVAL (XEXP (XEXP (x, 0), 1));
30244 switch (GET_CODE (base))
30247 name = XSTR (base, 0);
30251 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
30252 CODE_LABEL_NUMBER (XEXP (base, 0)));
30256 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
30260 gcc_unreachable ();
30263 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30264 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
30267 fputs ("\t.tc ", file);
30268 RS6000_OUTPUT_BASENAME (file, name);
30271 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
30273 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
30275 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30276 after other TOC symbols, reducing overflow of small TOC access
30277 to [TC] symbols. */
30278 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
30279 ? "[TE]," : "[TC],", file);
30282 /* Currently C++ toc references to vtables can be emitted before it
30283 is decided whether the vtable is public or private. If this is
30284 the case, then the linker will eventually complain that there is
30285 a TOC reference to an unknown section. Thus, for vtables only,
30286 we emit the TOC reference to reference the symbol and not the
30288 if (VTABLE_NAME_P (name))
30290 RS6000_OUTPUT_BASENAME (file, name);
30292 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
30293 else if (offset > 0)
30294 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
30297 output_addr_const (file, x);
30300 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
30302 switch (SYMBOL_REF_TLS_MODEL (base))
30306 case TLS_MODEL_LOCAL_EXEC:
30307 fputs ("@le", file);
30309 case TLS_MODEL_INITIAL_EXEC:
30310 fputs ("@ie", file);
30312 /* Use global-dynamic for local-dynamic. */
30313 case TLS_MODEL_GLOBAL_DYNAMIC:
30314 case TLS_MODEL_LOCAL_DYNAMIC:
30316 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
30317 fputs ("\t.tc .", file);
30318 RS6000_OUTPUT_BASENAME (file, name);
30319 fputs ("[TC],", file);
30320 output_addr_const (file, x);
30321 fputs ("@m", file);
30324 gcc_unreachable ();
30332 /* Output an assembler pseudo-op to write an ASCII string of N characters
30333 starting at P to FILE.
30335 On the RS/6000, we have to do this using the .byte operation and
30336 write out special characters outside the quoted string.
30337 Also, the assembler is broken; very long strings are truncated,
30338 so we must artificially break them up early. */
30341 output_ascii (FILE *file, const char *p, int n)
30344 int i, count_string;
30345 const char *for_string = "\t.byte \"";
30346 const char *for_decimal = "\t.byte ";
30347 const char *to_close = NULL;
30350 for (i = 0; i < n; i++)
30353 if (c >= ' ' && c < 0177)
30356 fputs (for_string, file);
30359 /* Write two quotes to get one. */
30367 for_decimal = "\"\n\t.byte ";
30371 if (count_string >= 512)
30373 fputs (to_close, file);
30375 for_string = "\t.byte \"";
30376 for_decimal = "\t.byte ";
30384 fputs (for_decimal, file);
30385 fprintf (file, "%d", c);
30387 for_string = "\n\t.byte \"";
30388 for_decimal = ", ";
30394 /* Now close the string if we have written one. Then end the line. */
30396 fputs (to_close, file);
30399 /* Generate a unique section name for FILENAME for a section type
30400 represented by SECTION_DESC. Output goes into BUF.
30402 SECTION_DESC can be any string, as long as it is different for each
30403 possible section type.
30405 We name the section in the same manner as xlc. The name begins with an
30406 underscore followed by the filename (after stripping any leading directory
30407 names) with the last period replaced by the string SECTION_DESC. If
30408 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30412 rs6000_gen_section_name (char **buf, const char *filename,
30413 const char *section_desc)
30415 const char *q, *after_last_slash, *last_period = 0;
30419 after_last_slash = filename;
30420 for (q = filename; *q; q++)
30423 after_last_slash = q + 1;
30424 else if (*q == '.')
30428 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30429 *buf = (char *) xmalloc (len);
30434 for (q = after_last_slash; *q; q++)
30436 if (q == last_period)
30438 strcpy (p, section_desc);
30439 p += strlen (section_desc);
30443 else if (ISALNUM (*q))
30447 if (last_period == 0)
30448 strcpy (p, section_desc);
30453 /* Emit profile function. */
30456 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30458 /* Non-standard profiling for kernels, which just saves LR then calls
30459 _mcount without worrying about arg saves. The idea is to change
30460 the function prologue as little as possible as it isn't easy to
30461 account for arg save/restore code added just for _mcount. */
30462 if (TARGET_PROFILE_KERNEL)
30465 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30467 #ifndef NO_PROFILE_COUNTERS
30468 # define NO_PROFILE_COUNTERS 0
30470 if (NO_PROFILE_COUNTERS)
30471 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30472 LCT_NORMAL, VOIDmode);
30476 const char *label_name;
30479 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30480 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30481 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30483 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30484 LCT_NORMAL, VOIDmode, fun, Pmode);
30487 else if (DEFAULT_ABI == ABI_DARWIN)
30489 const char *mcount_name = RS6000_MCOUNT;
30490 int caller_addr_regno = LR_REGNO;
30492 /* Be conservative and always set this, at least for now. */
30493 crtl->uses_pic_offset_table = 1;
30496 /* For PIC code, set up a stub and collect the caller's address
30497 from r0, which is where the prologue puts it. */
30498 if (MACHOPIC_INDIRECT
30499 && crtl->uses_pic_offset_table)
30500 caller_addr_regno = 0;
30502 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30503 LCT_NORMAL, VOIDmode,
30504 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30508 /* Write function profiler code. */
30511 output_function_profiler (FILE *file, int labelno)
30515 switch (DEFAULT_ABI)
30518 gcc_unreachable ();
30523 warning (0, "no profiling of 64-bit code for this ABI");
30526 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30527 fprintf (file, "\tmflr %s\n", reg_names[0]);
30528 if (NO_PROFILE_COUNTERS)
30530 asm_fprintf (file, "\tstw %s,4(%s)\n",
30531 reg_names[0], reg_names[1]);
30533 else if (TARGET_SECURE_PLT && flag_pic)
30535 if (TARGET_LINK_STACK)
30538 get_ppc476_thunk_name (name);
30539 asm_fprintf (file, "\tbl %s\n", name);
30542 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30543 asm_fprintf (file, "\tstw %s,4(%s)\n",
30544 reg_names[0], reg_names[1]);
30545 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30546 asm_fprintf (file, "\taddis %s,%s,",
30547 reg_names[12], reg_names[12]);
30548 assemble_name (file, buf);
30549 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30550 assemble_name (file, buf);
30551 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30553 else if (flag_pic == 1)
30555 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30556 asm_fprintf (file, "\tstw %s,4(%s)\n",
30557 reg_names[0], reg_names[1]);
30558 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30559 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30560 assemble_name (file, buf);
30561 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30563 else if (flag_pic > 1)
30565 asm_fprintf (file, "\tstw %s,4(%s)\n",
30566 reg_names[0], reg_names[1]);
30567 /* Now, we need to get the address of the label. */
30568 if (TARGET_LINK_STACK)
30571 get_ppc476_thunk_name (name);
30572 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30573 assemble_name (file, buf);
30574 fputs ("-.\n1:", file);
30575 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30576 asm_fprintf (file, "\taddi %s,%s,4\n",
30577 reg_names[11], reg_names[11]);
30581 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30582 assemble_name (file, buf);
30583 fputs ("-.\n1:", file);
30584 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30586 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30587 reg_names[0], reg_names[11]);
30588 asm_fprintf (file, "\tadd %s,%s,%s\n",
30589 reg_names[0], reg_names[0], reg_names[11]);
30593 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30594 assemble_name (file, buf);
30595 fputs ("@ha\n", file);
30596 asm_fprintf (file, "\tstw %s,4(%s)\n",
30597 reg_names[0], reg_names[1]);
30598 asm_fprintf (file, "\tla %s,", reg_names[0]);
30599 assemble_name (file, buf);
30600 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30603 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30604 fprintf (file, "\tbl %s%s\n",
30605 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30611 /* Don't do anything, done in output_profile_hook (). */
30618 /* The following variable value is the last issued insn. */
30620 static rtx_insn *last_scheduled_insn;
30622 /* The following variable helps to balance issuing of load and
30623 store instructions */
30625 static int load_store_pendulum;
30627 /* The following variable helps pair divide insns during scheduling. */
30628 static int divide_cnt;
30629 /* The following variable helps pair and alternate vector and vector load
30630 insns during scheduling. */
30631 static int vec_pairing;
30634 /* Power4 load update and store update instructions are cracked into a
30635 load or store and an integer insn which are executed in the same cycle.
30636 Branches have their own dispatch slot which does not count against the
30637 GCC issue rate, but it changes the program flow so there are no other
30638 instructions to issue in this cycle. */
30641 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30643 last_scheduled_insn = insn;
30644 if (GET_CODE (PATTERN (insn)) == USE
30645 || GET_CODE (PATTERN (insn)) == CLOBBER)
30647 cached_can_issue_more = more;
30648 return cached_can_issue_more;
30651 if (insn_terminates_group_p (insn, current_group))
30653 cached_can_issue_more = 0;
30654 return cached_can_issue_more;
30657 /* If no reservation, but reach here */
30658 if (recog_memoized (insn) < 0)
30661 if (rs6000_sched_groups)
30663 if (is_microcoded_insn (insn))
30664 cached_can_issue_more = 0;
30665 else if (is_cracked_insn (insn))
30666 cached_can_issue_more = more > 2 ? more - 2 : 0;
30668 cached_can_issue_more = more - 1;
30670 return cached_can_issue_more;
30673 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
30676 cached_can_issue_more = more - 1;
30677 return cached_can_issue_more;
30681 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30683 int r = rs6000_variable_issue_1 (insn, more);
30685 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30689 /* Adjust the cost of a scheduling dependency. Return the new cost of
30690 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30693 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30696 enum attr_type attr_type;
30698 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30705 /* Data dependency; DEP_INSN writes a register that INSN reads
30706 some cycles later. */
30708 /* Separate a load from a narrower, dependent store. */
30709 if ((rs6000_sched_groups || rs6000_cpu_attr == CPU_POWER9)
30710 && GET_CODE (PATTERN (insn)) == SET
30711 && GET_CODE (PATTERN (dep_insn)) == SET
30712 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30713 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30714 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30715 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30718 attr_type = get_attr_type (insn);
30723 /* Tell the first scheduling pass about the latency between
30724 a mtctr and bctr (and mtlr and br/blr). The first
30725 scheduling pass will not know about this latency since
30726 the mtctr instruction, which has the latency associated
30727 to it, will be generated by reload. */
30730 /* Leave some extra cycles between a compare and its
30731 dependent branch, to inhibit expensive mispredicts. */
30732 if ((rs6000_cpu_attr == CPU_PPC603
30733 || rs6000_cpu_attr == CPU_PPC604
30734 || rs6000_cpu_attr == CPU_PPC604E
30735 || rs6000_cpu_attr == CPU_PPC620
30736 || rs6000_cpu_attr == CPU_PPC630
30737 || rs6000_cpu_attr == CPU_PPC750
30738 || rs6000_cpu_attr == CPU_PPC7400
30739 || rs6000_cpu_attr == CPU_PPC7450
30740 || rs6000_cpu_attr == CPU_PPCE5500
30741 || rs6000_cpu_attr == CPU_PPCE6500
30742 || rs6000_cpu_attr == CPU_POWER4
30743 || rs6000_cpu_attr == CPU_POWER5
30744 || rs6000_cpu_attr == CPU_POWER7
30745 || rs6000_cpu_attr == CPU_POWER8
30746 || rs6000_cpu_attr == CPU_POWER9
30747 || rs6000_cpu_attr == CPU_CELL)
30748 && recog_memoized (dep_insn)
30749 && (INSN_CODE (dep_insn) >= 0))
30751 switch (get_attr_type (dep_insn))
30754 case TYPE_FPCOMPARE:
30755 case TYPE_CR_LOGICAL:
30756 case TYPE_DELAYED_CR:
30760 if (get_attr_dot (dep_insn) == DOT_YES)
30765 if (get_attr_dot (dep_insn) == DOT_YES
30766 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30777 if ((rs6000_cpu == PROCESSOR_POWER6)
30778 && recog_memoized (dep_insn)
30779 && (INSN_CODE (dep_insn) >= 0))
30782 if (GET_CODE (PATTERN (insn)) != SET)
30783 /* If this happens, we have to extend this to schedule
30784 optimally. Return default for now. */
30787 /* Adjust the cost for the case where the value written
30788 by a fixed point operation is used as the address
30789 gen value on a store. */
30790 switch (get_attr_type (dep_insn))
30795 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30796 return get_attr_sign_extend (dep_insn)
30797 == SIGN_EXTEND_YES ? 6 : 4;
30802 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30803 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30813 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30821 if (get_attr_update (dep_insn) == UPDATE_YES
30822 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30828 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30834 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30835 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30845 if ((rs6000_cpu == PROCESSOR_POWER6)
30846 && recog_memoized (dep_insn)
30847 && (INSN_CODE (dep_insn) >= 0))
30850 /* Adjust the cost for the case where the value written
30851 by a fixed point instruction is used within the address
30852 gen portion of a subsequent load(u)(x) */
30853 switch (get_attr_type (dep_insn))
30858 if (set_to_load_agen (dep_insn, insn))
30859 return get_attr_sign_extend (dep_insn)
30860 == SIGN_EXTEND_YES ? 6 : 4;
30865 if (set_to_load_agen (dep_insn, insn))
30866 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30876 if (set_to_load_agen (dep_insn, insn))
30884 if (get_attr_update (dep_insn) == UPDATE_YES
30885 && set_to_load_agen (dep_insn, insn))
30891 if (set_to_load_agen (dep_insn, insn))
30897 if (set_to_load_agen (dep_insn, insn))
30898 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30908 if ((rs6000_cpu == PROCESSOR_POWER6)
30909 && get_attr_update (insn) == UPDATE_NO
30910 && recog_memoized (dep_insn)
30911 && (INSN_CODE (dep_insn) >= 0)
30912 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30919 /* Fall out to return default cost. */
30923 case REG_DEP_OUTPUT:
30924 /* Output dependency; DEP_INSN writes a register that INSN writes some
30926 if ((rs6000_cpu == PROCESSOR_POWER6)
30927 && recog_memoized (dep_insn)
30928 && (INSN_CODE (dep_insn) >= 0))
30930 attr_type = get_attr_type (insn);
30935 case TYPE_FPSIMPLE:
30936 if (get_attr_type (dep_insn) == TYPE_FP
30937 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30941 if (get_attr_update (insn) == UPDATE_NO
30942 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30949 /* Fall through, no cost for output dependency. */
30953 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30958 gcc_unreachable ();
30964 /* Debug version of rs6000_adjust_cost. */
30967 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30968 int cost, unsigned int dw)
30970 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30978 default: dep = "unknown depencency"; break;
30979 case REG_DEP_TRUE: dep = "data dependency"; break;
30980 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30981 case REG_DEP_ANTI: dep = "anti depencency"; break;
30985 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30986 "%s, insn:\n", ret, cost, dep);
30994 /* The function returns a true if INSN is microcoded.
30995 Return false otherwise. */
30998 is_microcoded_insn (rtx_insn *insn)
31000 if (!insn || !NONDEBUG_INSN_P (insn)
31001 || GET_CODE (PATTERN (insn)) == USE
31002 || GET_CODE (PATTERN (insn)) == CLOBBER)
31005 if (rs6000_cpu_attr == CPU_CELL)
31006 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
31008 if (rs6000_sched_groups
31009 && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
31011 enum attr_type type = get_attr_type (insn);
31012 if ((type == TYPE_LOAD
31013 && get_attr_update (insn) == UPDATE_YES
31014 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
31015 || ((type == TYPE_LOAD || type == TYPE_STORE)
31016 && get_attr_update (insn) == UPDATE_YES
31017 && get_attr_indexed (insn) == INDEXED_YES)
31018 || type == TYPE_MFCR)
31025 /* The function returns true if INSN is cracked into 2 instructions
31026 by the processor (and therefore occupies 2 issue slots). */
31029 is_cracked_insn (rtx_insn *insn)
31031 if (!insn || !NONDEBUG_INSN_P (insn)
31032 || GET_CODE (PATTERN (insn)) == USE
31033 || GET_CODE (PATTERN (insn)) == CLOBBER)
31036 if (rs6000_sched_groups
31037 && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
31039 enum attr_type type = get_attr_type (insn);
31040 if ((type == TYPE_LOAD
31041 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31042 && get_attr_update (insn) == UPDATE_NO)
31043 || (type == TYPE_LOAD
31044 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
31045 && get_attr_update (insn) == UPDATE_YES
31046 && get_attr_indexed (insn) == INDEXED_NO)
31047 || (type == TYPE_STORE
31048 && get_attr_update (insn) == UPDATE_YES
31049 && get_attr_indexed (insn) == INDEXED_NO)
31050 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
31051 && get_attr_update (insn) == UPDATE_YES)
31052 || type == TYPE_DELAYED_CR
31053 || (type == TYPE_EXTS
31054 && get_attr_dot (insn) == DOT_YES)
31055 || (type == TYPE_SHIFT
31056 && get_attr_dot (insn) == DOT_YES
31057 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
31058 || (type == TYPE_MUL
31059 && get_attr_dot (insn) == DOT_YES)
31060 || type == TYPE_DIV
31061 || (type == TYPE_INSERT
31062 && get_attr_size (insn) == SIZE_32))
31069 /* The function returns true if INSN can be issued only from
31070 the branch slot. */
31073 is_branch_slot_insn (rtx_insn *insn)
31075 if (!insn || !NONDEBUG_INSN_P (insn)
31076 || GET_CODE (PATTERN (insn)) == USE
31077 || GET_CODE (PATTERN (insn)) == CLOBBER)
31080 if (rs6000_sched_groups)
31082 enum attr_type type = get_attr_type (insn);
31083 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
31091 /* The function returns true if out_inst sets a value that is
31092 used in the address generation computation of in_insn */
31094 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
31096 rtx out_set, in_set;
31098 /* For performance reasons, only handle the simple case where
31099 both loads are a single_set. */
31100 out_set = single_set (out_insn);
31103 in_set = single_set (in_insn);
31105 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
31111 /* Try to determine base/offset/size parts of the given MEM.
31112 Return true if successful, false if all the values couldn't
31115 This function only looks for REG or REG+CONST address forms.
31116 REG+REG address form will return false. */
31119 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
31120 HOST_WIDE_INT *size)
31123 if MEM_SIZE_KNOWN_P (mem)
31124 *size = MEM_SIZE (mem);
31128 addr_rtx = (XEXP (mem, 0));
31129 if (GET_CODE (addr_rtx) == PRE_MODIFY)
31130 addr_rtx = XEXP (addr_rtx, 1);
31133 while (GET_CODE (addr_rtx) == PLUS
31134 && CONST_INT_P (XEXP (addr_rtx, 1)))
31136 *offset += INTVAL (XEXP (addr_rtx, 1));
31137 addr_rtx = XEXP (addr_rtx, 0);
31139 if (!REG_P (addr_rtx))
31146 /* The function returns true if the target storage location of
31147 mem1 is adjacent to the target storage location of mem2 */
31148 /* Return 1 if memory locations are adjacent. */
31151 adjacent_mem_locations (rtx mem1, rtx mem2)
31154 HOST_WIDE_INT off1, size1, off2, size2;
31156 if (get_memref_parts (mem1, ®1, &off1, &size1)
31157 && get_memref_parts (mem2, ®2, &off2, &size2))
31158 return ((REGNO (reg1) == REGNO (reg2))
31159 && ((off1 + size1 == off2)
31160 || (off2 + size2 == off1)));
31165 /* This function returns true if it can be determined that the two MEM
31166 locations overlap by at least 1 byte based on base reg/offset/size. */
31169 mem_locations_overlap (rtx mem1, rtx mem2)
31172 HOST_WIDE_INT off1, size1, off2, size2;
31174 if (get_memref_parts (mem1, ®1, &off1, &size1)
31175 && get_memref_parts (mem2, ®2, &off2, &size2))
31176 return ((REGNO (reg1) == REGNO (reg2))
31177 && (((off1 <= off2) && (off1 + size1 > off2))
31178 || ((off2 <= off1) && (off2 + size2 > off1))));
31183 /* A C statement (sans semicolon) to update the integer scheduling
31184 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31185 INSN earlier, reduce the priority to execute INSN later. Do not
31186 define this macro if you do not need to adjust the scheduling
31187 priorities of insns. */
31190 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
31192 rtx load_mem, str_mem;
31193 /* On machines (like the 750) which have asymmetric integer units,
31194 where one integer unit can do multiply and divides and the other
31195 can't, reduce the priority of multiply/divide so it is scheduled
31196 before other integer operations. */
31199 if (! INSN_P (insn))
31202 if (GET_CODE (PATTERN (insn)) == USE)
31205 switch (rs6000_cpu_attr) {
31207 switch (get_attr_type (insn))
31214 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
31215 priority, priority);
31216 if (priority >= 0 && priority < 0x01000000)
31223 if (insn_must_be_first_in_group (insn)
31224 && reload_completed
31225 && current_sched_info->sched_max_insns_priority
31226 && rs6000_sched_restricted_insns_priority)
31229 /* Prioritize insns that can be dispatched only in the first
31231 if (rs6000_sched_restricted_insns_priority == 1)
31232 /* Attach highest priority to insn. This means that in
31233 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31234 precede 'priority' (critical path) considerations. */
31235 return current_sched_info->sched_max_insns_priority;
31236 else if (rs6000_sched_restricted_insns_priority == 2)
31237 /* Increase priority of insn by a minimal amount. This means that in
31238 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31239 considerations precede dispatch-slot restriction considerations. */
31240 return (priority + 1);
31243 if (rs6000_cpu == PROCESSOR_POWER6
31244 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
31245 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
31246 /* Attach highest priority to insn if the scheduler has just issued two
31247 stores and this instruction is a load, or two loads and this instruction
31248 is a store. Power6 wants loads and stores scheduled alternately
31250 return current_sched_info->sched_max_insns_priority;
31255 /* Return true if the instruction is nonpipelined on the Cell. */
31257 is_nonpipeline_insn (rtx_insn *insn)
31259 enum attr_type type;
31260 if (!insn || !NONDEBUG_INSN_P (insn)
31261 || GET_CODE (PATTERN (insn)) == USE
31262 || GET_CODE (PATTERN (insn)) == CLOBBER)
31265 type = get_attr_type (insn);
31266 if (type == TYPE_MUL
31267 || type == TYPE_DIV
31268 || type == TYPE_SDIV
31269 || type == TYPE_DDIV
31270 || type == TYPE_SSQRT
31271 || type == TYPE_DSQRT
31272 || type == TYPE_MFCR
31273 || type == TYPE_MFCRF
31274 || type == TYPE_MFJMPR)
31282 /* Return how many instructions the machine can issue per cycle. */
31285 rs6000_issue_rate (void)
31287 /* Unless scheduling for register pressure, use issue rate of 1 for
31288 first scheduling pass to decrease degradation. */
31289 if (!reload_completed && !flag_sched_pressure)
31292 switch (rs6000_cpu_attr) {
31294 case CPU_PPC601: /* ? */
31304 case CPU_PPCE300C2:
31305 case CPU_PPCE300C3:
31306 case CPU_PPCE500MC:
31307 case CPU_PPCE500MC64:
31332 /* Return how many instructions to look ahead for better insn
31336 rs6000_use_sched_lookahead (void)
31338 switch (rs6000_cpu_attr)
31345 return (reload_completed ? 8 : 0);
31352 /* We are choosing insn from the ready queue. Return zero if INSN can be
31355 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
31357 if (ready_index == 0)
31360 if (rs6000_cpu_attr != CPU_CELL)
31363 gcc_assert (insn != NULL_RTX && INSN_P (insn));
31365 if (!reload_completed
31366 || is_nonpipeline_insn (insn)
31367 || is_microcoded_insn (insn))
31373 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31374 and return true. */
31377 find_mem_ref (rtx pat, rtx *mem_ref)
31382 /* stack_tie does not produce any real memory traffic. */
31383 if (tie_operand (pat, VOIDmode))
31386 if (GET_CODE (pat) == MEM)
31392 /* Recursively process the pattern. */
31393 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31395 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31399 if (find_mem_ref (XEXP (pat, i), mem_ref))
31402 else if (fmt[i] == 'E')
31403 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31405 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31413 /* Determine if PAT is a PATTERN of a load insn. */
31416 is_load_insn1 (rtx pat, rtx *load_mem)
31418 if (!pat || pat == NULL_RTX)
31421 if (GET_CODE (pat) == SET)
31422 return find_mem_ref (SET_SRC (pat), load_mem);
31424 if (GET_CODE (pat) == PARALLEL)
31428 for (i = 0; i < XVECLEN (pat, 0); i++)
31429 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31436 /* Determine if INSN loads from memory. */
31439 is_load_insn (rtx insn, rtx *load_mem)
31441 if (!insn || !INSN_P (insn))
31447 return is_load_insn1 (PATTERN (insn), load_mem);
31450 /* Determine if PAT is a PATTERN of a store insn. */
31453 is_store_insn1 (rtx pat, rtx *str_mem)
31455 if (!pat || pat == NULL_RTX)
31458 if (GET_CODE (pat) == SET)
31459 return find_mem_ref (SET_DEST (pat), str_mem);
31461 if (GET_CODE (pat) == PARALLEL)
31465 for (i = 0; i < XVECLEN (pat, 0); i++)
31466 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31473 /* Determine if INSN stores to memory. */
31476 is_store_insn (rtx insn, rtx *str_mem)
31478 if (!insn || !INSN_P (insn))
31481 return is_store_insn1 (PATTERN (insn), str_mem);
31484 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31487 is_power9_pairable_vec_type (enum attr_type type)
31491 case TYPE_VECSIMPLE:
31492 case TYPE_VECCOMPLEX:
31496 case TYPE_VECFLOAT:
31498 case TYPE_VECDOUBLE:
31506 /* Returns whether the dependence between INSN and NEXT is considered
31507 costly by the given target. */
31510 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31514 rtx load_mem, str_mem;
31516 /* If the flag is not enabled - no dependence is considered costly;
31517 allow all dependent insns in the same group.
31518 This is the most aggressive option. */
31519 if (rs6000_sched_costly_dep == no_dep_costly)
31522 /* If the flag is set to 1 - a dependence is always considered costly;
31523 do not allow dependent instructions in the same group.
31524 This is the most conservative option. */
31525 if (rs6000_sched_costly_dep == all_deps_costly)
31528 insn = DEP_PRO (dep);
31529 next = DEP_CON (dep);
31531 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31532 && is_load_insn (next, &load_mem)
31533 && is_store_insn (insn, &str_mem))
31534 /* Prevent load after store in the same group. */
31537 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31538 && is_load_insn (next, &load_mem)
31539 && is_store_insn (insn, &str_mem)
31540 && DEP_TYPE (dep) == REG_DEP_TRUE
31541 && mem_locations_overlap(str_mem, load_mem))
31542 /* Prevent load after store in the same group if it is a true
31546 /* The flag is set to X; dependences with latency >= X are considered costly,
31547 and will not be scheduled in the same group. */
31548 if (rs6000_sched_costly_dep <= max_dep_latency
31549 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31555 /* Return the next insn after INSN that is found before TAIL is reached,
31556 skipping any "non-active" insns - insns that will not actually occupy
31557 an issue slot. Return NULL_RTX if such an insn is not found. */
31560 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31562 if (insn == NULL_RTX || insn == tail)
31567 insn = NEXT_INSN (insn);
31568 if (insn == NULL_RTX || insn == tail)
31572 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31573 || (NONJUMP_INSN_P (insn)
31574 && GET_CODE (PATTERN (insn)) != USE
31575 && GET_CODE (PATTERN (insn)) != CLOBBER
31576 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31582 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31585 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31590 enum attr_type type, type2;
31592 type = get_attr_type (last_scheduled_insn);
31594 /* Try to issue fixed point divides back-to-back in pairs so they will be
31595 routed to separate execution units and execute in parallel. */
31596 if (type == TYPE_DIV && divide_cnt == 0)
31598 /* First divide has been scheduled. */
31601 /* Scan the ready list looking for another divide, if found move it
31602 to the end of the list so it is chosen next. */
31606 if (recog_memoized (ready[pos]) >= 0
31607 && get_attr_type (ready[pos]) == TYPE_DIV)
31610 for (i = pos; i < lastpos; i++)
31611 ready[i] = ready[i + 1];
31612 ready[lastpos] = tmp;
31620 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31623 /* The best dispatch throughput for vector and vector load insns can be
31624 achieved by interleaving a vector and vector load such that they'll
31625 dispatch to the same superslice. If this pairing cannot be achieved
31626 then it is best to pair vector insns together and vector load insns
31629 To aid in this pairing, vec_pairing maintains the current state with
31630 the following values:
31632 0 : Initial state, no vecload/vector pairing has been started.
31634 1 : A vecload or vector insn has been issued and a candidate for
31635 pairing has been found and moved to the end of the ready
31637 if (type == TYPE_VECLOAD)
31639 /* Issued a vecload. */
31640 if (vec_pairing == 0)
31642 int vecload_pos = -1;
31643 /* We issued a single vecload, look for a vector insn to pair it
31644 with. If one isn't found, try to pair another vecload. */
31648 if (recog_memoized (ready[pos]) >= 0)
31650 type2 = get_attr_type (ready[pos]);
31651 if (is_power9_pairable_vec_type (type2))
31653 /* Found a vector insn to pair with, move it to the
31654 end of the ready list so it is scheduled next. */
31656 for (i = pos; i < lastpos; i++)
31657 ready[i] = ready[i + 1];
31658 ready[lastpos] = tmp;
31660 return cached_can_issue_more;
31662 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31663 /* Remember position of first vecload seen. */
31668 if (vecload_pos >= 0)
31670 /* Didn't find a vector to pair with but did find a vecload,
31671 move it to the end of the ready list. */
31672 tmp = ready[vecload_pos];
31673 for (i = vecload_pos; i < lastpos; i++)
31674 ready[i] = ready[i + 1];
31675 ready[lastpos] = tmp;
31677 return cached_can_issue_more;
31681 else if (is_power9_pairable_vec_type (type))
31683 /* Issued a vector operation. */
31684 if (vec_pairing == 0)
31687 /* We issued a single vector insn, look for a vecload to pair it
31688 with. If one isn't found, try to pair another vector. */
31692 if (recog_memoized (ready[pos]) >= 0)
31694 type2 = get_attr_type (ready[pos]);
31695 if (type2 == TYPE_VECLOAD)
31697 /* Found a vecload insn to pair with, move it to the
31698 end of the ready list so it is scheduled next. */
31700 for (i = pos; i < lastpos; i++)
31701 ready[i] = ready[i + 1];
31702 ready[lastpos] = tmp;
31704 return cached_can_issue_more;
31706 else if (is_power9_pairable_vec_type (type2)
31708 /* Remember position of first vector insn seen. */
31715 /* Didn't find a vecload to pair with but did find a vector
31716 insn, move it to the end of the ready list. */
31717 tmp = ready[vec_pos];
31718 for (i = vec_pos; i < lastpos; i++)
31719 ready[i] = ready[i + 1];
31720 ready[lastpos] = tmp;
31722 return cached_can_issue_more;
31727 /* We've either finished a vec/vecload pair, couldn't find an insn to
31728 continue the current pair, or the last insn had nothing to do with
31729 with pairing. In any case, reset the state. */
31733 return cached_can_issue_more;
31736 /* We are about to begin issuing insns for this clock cycle. */
31739 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31740 rtx_insn **ready ATTRIBUTE_UNUSED,
31741 int *pn_ready ATTRIBUTE_UNUSED,
31742 int clock_var ATTRIBUTE_UNUSED)
31744 int n_ready = *pn_ready;
31747 fprintf (dump, "// rs6000_sched_reorder :\n");
31749 /* Reorder the ready list, if the second to last ready insn
31750 is a nonepipeline insn. */
31751 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
31753 if (is_nonpipeline_insn (ready[n_ready - 1])
31754 && (recog_memoized (ready[n_ready - 2]) > 0))
31755 /* Simply swap first two insns. */
31756 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31759 if (rs6000_cpu == PROCESSOR_POWER6)
31760 load_store_pendulum = 0;
31762 return rs6000_issue_rate ();
31765 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31768 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31769 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31772 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31774 /* For Power6, we need to handle some special cases to try and keep the
31775 store queue from overflowing and triggering expensive flushes.
31777 This code monitors how load and store instructions are being issued
31778 and skews the ready list one way or the other to increase the likelihood
31779 that a desired instruction is issued at the proper time.
31781 A couple of things are done. First, we maintain a "load_store_pendulum"
31782 to track the current state of load/store issue.
31784 - If the pendulum is at zero, then no loads or stores have been
31785 issued in the current cycle so we do nothing.
31787 - If the pendulum is 1, then a single load has been issued in this
31788 cycle and we attempt to locate another load in the ready list to
31791 - If the pendulum is -2, then two stores have already been
31792 issued in this cycle, so we increase the priority of the first load
31793 in the ready list to increase it's likelihood of being chosen first
31796 - If the pendulum is -1, then a single store has been issued in this
31797 cycle and we attempt to locate another store in the ready list to
31798 issue with it, preferring a store to an adjacent memory location to
31799 facilitate store pairing in the store queue.
31801 - If the pendulum is 2, then two loads have already been
31802 issued in this cycle, so we increase the priority of the first store
31803 in the ready list to increase it's likelihood of being chosen first
31806 - If the pendulum < -2 or > 2, then do nothing.
31808 Note: This code covers the most common scenarios. There exist non
31809 load/store instructions which make use of the LSU and which
31810 would need to be accounted for to strictly model the behavior
31811 of the machine. Those instructions are currently unaccounted
31812 for to help minimize compile time overhead of this code.
31814 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
31819 rtx load_mem, str_mem;
31821 if (is_store_insn (last_scheduled_insn, &str_mem))
31822 /* Issuing a store, swing the load_store_pendulum to the left */
31823 load_store_pendulum--;
31824 else if (is_load_insn (last_scheduled_insn, &load_mem))
31825 /* Issuing a load, swing the load_store_pendulum to the right */
31826 load_store_pendulum++;
31828 return cached_can_issue_more;
31830 /* If the pendulum is balanced, or there is only one instruction on
31831 the ready list, then all is well, so return. */
31832 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31833 return cached_can_issue_more;
31835 if (load_store_pendulum == 1)
31837 /* A load has been issued in this cycle. Scan the ready list
31838 for another load to issue with it */
31843 if (is_load_insn (ready[pos], &load_mem))
31845 /* Found a load. Move it to the head of the ready list,
31846 and adjust it's priority so that it is more likely to
31849 for (i=pos; i<*pn_ready-1; i++)
31850 ready[i] = ready[i + 1];
31851 ready[*pn_ready-1] = tmp;
31853 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31854 INSN_PRIORITY (tmp)++;
31860 else if (load_store_pendulum == -2)
31862 /* Two stores have been issued in this cycle. Increase the
31863 priority of the first load in the ready list to favor it for
31864 issuing in the next cycle. */
31869 if (is_load_insn (ready[pos], &load_mem)
31871 && INSN_PRIORITY_KNOWN (ready[pos]))
31873 INSN_PRIORITY (ready[pos])++;
31875 /* Adjust the pendulum to account for the fact that a load
31876 was found and increased in priority. This is to prevent
31877 increasing the priority of multiple loads */
31878 load_store_pendulum--;
31885 else if (load_store_pendulum == -1)
31887 /* A store has been issued in this cycle. Scan the ready list for
31888 another store to issue with it, preferring a store to an adjacent
31890 int first_store_pos = -1;
31896 if (is_store_insn (ready[pos], &str_mem))
31899 /* Maintain the index of the first store found on the
31901 if (first_store_pos == -1)
31902 first_store_pos = pos;
31904 if (is_store_insn (last_scheduled_insn, &str_mem2)
31905 && adjacent_mem_locations (str_mem, str_mem2))
31907 /* Found an adjacent store. Move it to the head of the
31908 ready list, and adjust it's priority so that it is
31909 more likely to stay there */
31911 for (i=pos; i<*pn_ready-1; i++)
31912 ready[i] = ready[i + 1];
31913 ready[*pn_ready-1] = tmp;
31915 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31916 INSN_PRIORITY (tmp)++;
31918 first_store_pos = -1;
31926 if (first_store_pos >= 0)
31928 /* An adjacent store wasn't found, but a non-adjacent store was,
31929 so move the non-adjacent store to the front of the ready
31930 list, and adjust its priority so that it is more likely to
31932 tmp = ready[first_store_pos];
31933 for (i=first_store_pos; i<*pn_ready-1; i++)
31934 ready[i] = ready[i + 1];
31935 ready[*pn_ready-1] = tmp;
31936 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31937 INSN_PRIORITY (tmp)++;
31940 else if (load_store_pendulum == 2)
31942 /* Two loads have been issued in this cycle. Increase the priority
31943 of the first store in the ready list to favor it for issuing in
31949 if (is_store_insn (ready[pos], &str_mem)
31951 && INSN_PRIORITY_KNOWN (ready[pos]))
31953 INSN_PRIORITY (ready[pos])++;
31955 /* Adjust the pendulum to account for the fact that a store
31956 was found and increased in priority. This is to prevent
31957 increasing the priority of multiple stores */
31958 load_store_pendulum++;
31967 /* Do Power9 dependent reordering if necessary. */
31968 if (rs6000_cpu == PROCESSOR_POWER9 && last_scheduled_insn
31969 && recog_memoized (last_scheduled_insn) >= 0)
31970 return power9_sched_reorder2 (ready, *pn_ready - 1);
31972 return cached_can_issue_more;
31975 /* Return whether the presence of INSN causes a dispatch group termination
31976 of group WHICH_GROUP.
31978 If WHICH_GROUP == current_group, this function will return true if INSN
31979 causes the termination of the current group (i.e, the dispatch group to
31980 which INSN belongs). This means that INSN will be the last insn in the
31981 group it belongs to.
31983 If WHICH_GROUP == previous_group, this function will return true if INSN
31984 causes the termination of the previous group (i.e, the dispatch group that
31985 precedes the group to which INSN belongs). This means that INSN will be
31986 the first insn in the group it belongs to). */
31989 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31996 first = insn_must_be_first_in_group (insn);
31997 last = insn_must_be_last_in_group (insn);
32002 if (which_group == current_group)
32004 else if (which_group == previous_group)
32012 insn_must_be_first_in_group (rtx_insn *insn)
32014 enum attr_type type;
32018 || DEBUG_INSN_P (insn)
32019 || GET_CODE (PATTERN (insn)) == USE
32020 || GET_CODE (PATTERN (insn)) == CLOBBER)
32023 switch (rs6000_cpu)
32025 case PROCESSOR_POWER5:
32026 if (is_cracked_insn (insn))
32029 case PROCESSOR_POWER4:
32030 if (is_microcoded_insn (insn))
32033 if (!rs6000_sched_groups)
32036 type = get_attr_type (insn);
32043 case TYPE_DELAYED_CR:
32044 case TYPE_CR_LOGICAL:
32057 case PROCESSOR_POWER6:
32058 type = get_attr_type (insn);
32067 case TYPE_FPCOMPARE:
32078 if (get_attr_dot (insn) == DOT_NO
32079 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32084 if (get_attr_size (insn) == SIZE_32)
32092 if (get_attr_update (insn) == UPDATE_YES)
32100 case PROCESSOR_POWER7:
32101 type = get_attr_type (insn);
32105 case TYPE_CR_LOGICAL:
32119 if (get_attr_dot (insn) == DOT_YES)
32124 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32125 || get_attr_update (insn) == UPDATE_YES)
32132 if (get_attr_update (insn) == UPDATE_YES)
32140 case PROCESSOR_POWER8:
32141 type = get_attr_type (insn);
32145 case TYPE_CR_LOGICAL:
32146 case TYPE_DELAYED_CR:
32154 case TYPE_VECSTORE:
32161 if (get_attr_dot (insn) == DOT_YES)
32166 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32167 || get_attr_update (insn) == UPDATE_YES)
32172 if (get_attr_update (insn) == UPDATE_YES
32173 && get_attr_indexed (insn) == INDEXED_YES)
32189 insn_must_be_last_in_group (rtx_insn *insn)
32191 enum attr_type type;
32195 || DEBUG_INSN_P (insn)
32196 || GET_CODE (PATTERN (insn)) == USE
32197 || GET_CODE (PATTERN (insn)) == CLOBBER)
32200 switch (rs6000_cpu) {
32201 case PROCESSOR_POWER4:
32202 case PROCESSOR_POWER5:
32203 if (is_microcoded_insn (insn))
32206 if (is_branch_slot_insn (insn))
32210 case PROCESSOR_POWER6:
32211 type = get_attr_type (insn);
32219 case TYPE_FPCOMPARE:
32230 if (get_attr_dot (insn) == DOT_NO
32231 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32236 if (get_attr_size (insn) == SIZE_32)
32244 case PROCESSOR_POWER7:
32245 type = get_attr_type (insn);
32255 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32256 && get_attr_update (insn) == UPDATE_YES)
32261 if (get_attr_update (insn) == UPDATE_YES
32262 && get_attr_indexed (insn) == INDEXED_YES)
32270 case PROCESSOR_POWER8:
32271 type = get_attr_type (insn);
32283 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32284 && get_attr_update (insn) == UPDATE_YES)
32289 if (get_attr_update (insn) == UPDATE_YES
32290 && get_attr_indexed (insn) == INDEXED_YES)
32305 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32306 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32309 is_costly_group (rtx *group_insns, rtx next_insn)
32312 int issue_rate = rs6000_issue_rate ();
32314 for (i = 0; i < issue_rate; i++)
32316 sd_iterator_def sd_it;
32318 rtx insn = group_insns[i];
32323 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
32325 rtx next = DEP_CON (dep);
32327 if (next == next_insn
32328 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
32336 /* Utility of the function redefine_groups.
32337 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32338 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32339 to keep it "far" (in a separate group) from GROUP_INSNS, following
32340 one of the following schemes, depending on the value of the flag
32341 -minsert_sched_nops = X:
32342 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32343 in order to force NEXT_INSN into a separate group.
32344 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32345 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32346 insertion (has a group just ended, how many vacant issue slots remain in the
32347 last group, and how many dispatch groups were encountered so far). */
32350 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
32351 rtx_insn *next_insn, bool *group_end, int can_issue_more,
32356 int issue_rate = rs6000_issue_rate ();
32357 bool end = *group_end;
32360 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
32361 return can_issue_more;
32363 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
32364 return can_issue_more;
32366 force = is_costly_group (group_insns, next_insn);
32368 return can_issue_more;
32370 if (sched_verbose > 6)
32371 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32372 *group_count ,can_issue_more);
32374 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32377 can_issue_more = 0;
32379 /* Since only a branch can be issued in the last issue_slot, it is
32380 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32381 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32382 in this case the last nop will start a new group and the branch
32383 will be forced to the new group. */
32384 if (can_issue_more && !is_branch_slot_insn (next_insn))
32387 /* Do we have a special group ending nop? */
32388 if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
32389 || rs6000_cpu_attr == CPU_POWER8)
32391 nop = gen_group_ending_nop ();
32392 emit_insn_before (nop, next_insn);
32393 can_issue_more = 0;
32396 while (can_issue_more > 0)
32399 emit_insn_before (nop, next_insn);
32407 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32409 int n_nops = rs6000_sched_insert_nops;
32411 /* Nops can't be issued from the branch slot, so the effective
32412 issue_rate for nops is 'issue_rate - 1'. */
32413 if (can_issue_more == 0)
32414 can_issue_more = issue_rate;
32416 if (can_issue_more == 0)
32418 can_issue_more = issue_rate - 1;
32421 for (i = 0; i < issue_rate; i++)
32423 group_insns[i] = 0;
32430 emit_insn_before (nop, next_insn);
32431 if (can_issue_more == issue_rate - 1) /* new group begins */
32434 if (can_issue_more == 0)
32436 can_issue_more = issue_rate - 1;
32439 for (i = 0; i < issue_rate; i++)
32441 group_insns[i] = 0;
32447 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32450 /* Is next_insn going to start a new group? */
32453 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32454 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32455 || (can_issue_more < issue_rate &&
32456 insn_terminates_group_p (next_insn, previous_group)));
32457 if (*group_end && end)
32460 if (sched_verbose > 6)
32461 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32462 *group_count, can_issue_more);
32463 return can_issue_more;
32466 return can_issue_more;
32469 /* This function tries to synch the dispatch groups that the compiler "sees"
32470 with the dispatch groups that the processor dispatcher is expected to
32471 form in practice. It tries to achieve this synchronization by forcing the
32472 estimated processor grouping on the compiler (as opposed to the function
32473 'pad_goups' which tries to force the scheduler's grouping on the processor).
32475 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32476 examines the (estimated) dispatch groups that will be formed by the processor
32477 dispatcher. It marks these group boundaries to reflect the estimated
32478 processor grouping, overriding the grouping that the scheduler had marked.
32479 Depending on the value of the flag '-minsert-sched-nops' this function can
32480 force certain insns into separate groups or force a certain distance between
32481 them by inserting nops, for example, if there exists a "costly dependence"
32484 The function estimates the group boundaries that the processor will form as
32485 follows: It keeps track of how many vacant issue slots are available after
32486 each insn. A subsequent insn will start a new group if one of the following
32488 - no more vacant issue slots remain in the current dispatch group.
32489 - only the last issue slot, which is the branch slot, is vacant, but the next
32490 insn is not a branch.
32491 - only the last 2 or less issue slots, including the branch slot, are vacant,
32492 which means that a cracked insn (which occupies two issue slots) can't be
32493 issued in this group.
32494 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32495 start a new group. */
32498 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32501 rtx_insn *insn, *next_insn;
32503 int can_issue_more;
32506 int group_count = 0;
32510 issue_rate = rs6000_issue_rate ();
32511 group_insns = XALLOCAVEC (rtx, issue_rate);
32512 for (i = 0; i < issue_rate; i++)
32514 group_insns[i] = 0;
32516 can_issue_more = issue_rate;
32518 insn = get_next_active_insn (prev_head_insn, tail);
32521 while (insn != NULL_RTX)
32523 slot = (issue_rate - can_issue_more);
32524 group_insns[slot] = insn;
32526 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32527 if (insn_terminates_group_p (insn, current_group))
32528 can_issue_more = 0;
32530 next_insn = get_next_active_insn (insn, tail);
32531 if (next_insn == NULL_RTX)
32532 return group_count + 1;
32534 /* Is next_insn going to start a new group? */
32536 = (can_issue_more == 0
32537 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32538 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32539 || (can_issue_more < issue_rate &&
32540 insn_terminates_group_p (next_insn, previous_group)));
32542 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32543 next_insn, &group_end, can_issue_more,
32549 can_issue_more = 0;
32550 for (i = 0; i < issue_rate; i++)
32552 group_insns[i] = 0;
32556 if (GET_MODE (next_insn) == TImode && can_issue_more)
32557 PUT_MODE (next_insn, VOIDmode);
32558 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32559 PUT_MODE (next_insn, TImode);
32562 if (can_issue_more == 0)
32563 can_issue_more = issue_rate;
32566 return group_count;
32569 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32570 dispatch group boundaries that the scheduler had marked. Pad with nops
32571 any dispatch groups which have vacant issue slots, in order to force the
32572 scheduler's grouping on the processor dispatcher. The function
32573 returns the number of dispatch groups found. */
32576 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32579 rtx_insn *insn, *next_insn;
32582 int can_issue_more;
32584 int group_count = 0;
32586 /* Initialize issue_rate. */
32587 issue_rate = rs6000_issue_rate ();
32588 can_issue_more = issue_rate;
32590 insn = get_next_active_insn (prev_head_insn, tail);
32591 next_insn = get_next_active_insn (insn, tail);
32593 while (insn != NULL_RTX)
32596 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32598 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32600 if (next_insn == NULL_RTX)
32605 /* If the scheduler had marked group termination at this location
32606 (between insn and next_insn), and neither insn nor next_insn will
32607 force group termination, pad the group with nops to force group
32610 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32611 && !insn_terminates_group_p (insn, current_group)
32612 && !insn_terminates_group_p (next_insn, previous_group))
32614 if (!is_branch_slot_insn (next_insn))
32617 while (can_issue_more)
32620 emit_insn_before (nop, next_insn);
32625 can_issue_more = issue_rate;
32630 next_insn = get_next_active_insn (insn, tail);
32633 return group_count;
32636 /* We're beginning a new block. Initialize data structures as necessary. */
32639 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32640 int sched_verbose ATTRIBUTE_UNUSED,
32641 int max_ready ATTRIBUTE_UNUSED)
32643 last_scheduled_insn = NULL;
32644 load_store_pendulum = 0;
32649 /* The following function is called at the end of scheduling BB.
32650 After reload, it inserts nops at insn group bundling. */
32653 rs6000_sched_finish (FILE *dump, int sched_verbose)
32658 fprintf (dump, "=== Finishing schedule.\n");
32660 if (reload_completed && rs6000_sched_groups)
32662 /* Do not run sched_finish hook when selective scheduling enabled. */
32663 if (sel_sched_p ())
32666 if (rs6000_sched_insert_nops == sched_finish_none)
32669 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32670 n_groups = pad_groups (dump, sched_verbose,
32671 current_sched_info->prev_head,
32672 current_sched_info->next_tail);
32674 n_groups = redefine_groups (dump, sched_verbose,
32675 current_sched_info->prev_head,
32676 current_sched_info->next_tail);
32678 if (sched_verbose >= 6)
32680 fprintf (dump, "ngroups = %d\n", n_groups);
32681 print_rtl (dump, current_sched_info->prev_head);
32682 fprintf (dump, "Done finish_sched\n");
32687 struct rs6000_sched_context
32689 short cached_can_issue_more;
32690 rtx_insn *last_scheduled_insn;
32691 int load_store_pendulum;
32696 typedef struct rs6000_sched_context rs6000_sched_context_def;
32697 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32699 /* Allocate store for new scheduling context. */
32701 rs6000_alloc_sched_context (void)
32703 return xmalloc (sizeof (rs6000_sched_context_def));
32706 /* If CLEAN_P is true then initializes _SC with clean data,
32707 and from the global context otherwise. */
32709 rs6000_init_sched_context (void *_sc, bool clean_p)
32711 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32715 sc->cached_can_issue_more = 0;
32716 sc->last_scheduled_insn = NULL;
32717 sc->load_store_pendulum = 0;
32718 sc->divide_cnt = 0;
32719 sc->vec_pairing = 0;
32723 sc->cached_can_issue_more = cached_can_issue_more;
32724 sc->last_scheduled_insn = last_scheduled_insn;
32725 sc->load_store_pendulum = load_store_pendulum;
32726 sc->divide_cnt = divide_cnt;
32727 sc->vec_pairing = vec_pairing;
32731 /* Sets the global scheduling context to the one pointed to by _SC. */
32733 rs6000_set_sched_context (void *_sc)
32735 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32737 gcc_assert (sc != NULL);
32739 cached_can_issue_more = sc->cached_can_issue_more;
32740 last_scheduled_insn = sc->last_scheduled_insn;
32741 load_store_pendulum = sc->load_store_pendulum;
32742 divide_cnt = sc->divide_cnt;
32743 vec_pairing = sc->vec_pairing;
32748 rs6000_free_sched_context (void *_sc)
32750 gcc_assert (_sc != NULL);
32756 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32758 switch (get_attr_type (insn))
32773 /* Length in units of the trampoline for entering a nested function. */
32776 rs6000_trampoline_size (void)
32780 switch (DEFAULT_ABI)
32783 gcc_unreachable ();
32786 ret = (TARGET_32BIT) ? 12 : 24;
32790 gcc_assert (!TARGET_32BIT);
32796 ret = (TARGET_32BIT) ? 40 : 48;
32803 /* Emit RTL insns to initialize the variable parts of a trampoline.
32804 FNADDR is an RTX for the address of the function's pure code.
32805 CXT is an RTX for the static chain value for the function. */
32808 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32810 int regsize = (TARGET_32BIT) ? 4 : 8;
32811 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32812 rtx ctx_reg = force_reg (Pmode, cxt);
32813 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32815 switch (DEFAULT_ABI)
32818 gcc_unreachable ();
32820 /* Under AIX, just build the 3 word function descriptor */
32823 rtx fnmem, fn_reg, toc_reg;
32825 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32826 error ("you cannot take the address of a nested function if you use "
32827 "the %qs option", "-mno-pointers-to-nested-functions");
32829 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32830 fn_reg = gen_reg_rtx (Pmode);
32831 toc_reg = gen_reg_rtx (Pmode);
32833 /* Macro to shorten the code expansions below. */
32834 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32836 m_tramp = replace_equiv_address (m_tramp, addr);
32838 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32839 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32840 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32841 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32842 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32848 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32852 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32853 LCT_NORMAL, VOIDmode,
32855 GEN_INT (rs6000_trampoline_size ()), SImode,
32863 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32864 identifier as an argument, so the front end shouldn't look it up. */
32867 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32869 return is_attribute_p ("altivec", attr_id);
32872 /* Handle the "altivec" attribute. The attribute may have
32873 arguments as follows:
32875 __attribute__((altivec(vector__)))
32876 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32877 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32879 and may appear more than once (e.g., 'vector bool char') in a
32880 given declaration. */
32883 rs6000_handle_altivec_attribute (tree *node,
32884 tree name ATTRIBUTE_UNUSED,
32886 int flags ATTRIBUTE_UNUSED,
32887 bool *no_add_attrs)
32889 tree type = *node, result = NULL_TREE;
32893 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32894 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32895 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32898 while (POINTER_TYPE_P (type)
32899 || TREE_CODE (type) == FUNCTION_TYPE
32900 || TREE_CODE (type) == METHOD_TYPE
32901 || TREE_CODE (type) == ARRAY_TYPE)
32902 type = TREE_TYPE (type);
32904 mode = TYPE_MODE (type);
32906 /* Check for invalid AltiVec type qualifiers. */
32907 if (type == long_double_type_node)
32908 error ("use of %<long double%> in AltiVec types is invalid");
32909 else if (type == boolean_type_node)
32910 error ("use of boolean types in AltiVec types is invalid");
32911 else if (TREE_CODE (type) == COMPLEX_TYPE)
32912 error ("use of %<complex%> in AltiVec types is invalid");
32913 else if (DECIMAL_FLOAT_MODE_P (mode))
32914 error ("use of decimal floating point types in AltiVec types is invalid");
32915 else if (!TARGET_VSX)
32917 if (type == long_unsigned_type_node || type == long_integer_type_node)
32920 error ("use of %<long%> in AltiVec types is invalid for "
32921 "64-bit code without %qs", "-mvsx");
32922 else if (rs6000_warn_altivec_long)
32923 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32926 else if (type == long_long_unsigned_type_node
32927 || type == long_long_integer_type_node)
32928 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32930 else if (type == double_type_node)
32931 error ("use of %<double%> in AltiVec types is invalid without %qs",
32935 switch (altivec_type)
32938 unsigned_p = TYPE_UNSIGNED (type);
32942 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32945 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32948 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32951 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32954 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32956 case E_SFmode: result = V4SF_type_node; break;
32957 case E_DFmode: result = V2DF_type_node; break;
32958 /* If the user says 'vector int bool', we may be handed the 'bool'
32959 attribute _before_ the 'vector' attribute, and so select the
32960 proper type in the 'b' case below. */
32961 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32962 case E_V2DImode: case E_V2DFmode:
32970 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32971 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32972 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32973 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32980 case E_V8HImode: result = pixel_V8HI_type_node;
32986 /* Propagate qualifiers attached to the element type
32987 onto the vector type. */
32988 if (result && result != type && TYPE_QUALS (type))
32989 result = build_qualified_type (result, TYPE_QUALS (type));
32991 *no_add_attrs = true; /* No need to hang on to the attribute. */
32994 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32999 /* AltiVec defines four built-in scalar types that serve as vector
33000 elements; we must teach the compiler how to mangle them. */
33002 static const char *
33003 rs6000_mangle_type (const_tree type)
33005 type = TYPE_MAIN_VARIANT (type);
33007 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
33008 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
33011 if (type == bool_char_type_node) return "U6__boolc";
33012 if (type == bool_short_type_node) return "U6__bools";
33013 if (type == pixel_type_node) return "u7__pixel";
33014 if (type == bool_int_type_node) return "U6__booli";
33015 if (type == bool_long_type_node) return "U6__booll";
33017 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
33018 "g" for IBM extended double, no matter whether it is long double (using
33019 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
33020 if (TARGET_FLOAT128_TYPE)
33022 if (type == ieee128_float_type_node)
33023 return "U10__float128";
33025 if (TARGET_LONG_DOUBLE_128)
33027 if (type == long_double_type_node)
33028 return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
33030 if (type == ibm128_float_type_node)
33035 /* Mangle IBM extended float long double as `g' (__float128) on
33036 powerpc*-linux where long-double-64 previously was the default. */
33037 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
33039 && TARGET_LONG_DOUBLE_128
33040 && !TARGET_IEEEQUAD)
33043 /* For all other types, use normal C++ mangling. */
33047 /* Handle a "longcall" or "shortcall" attribute; arguments as in
33048 struct attribute_spec.handler. */
33051 rs6000_handle_longcall_attribute (tree *node, tree name,
33052 tree args ATTRIBUTE_UNUSED,
33053 int flags ATTRIBUTE_UNUSED,
33054 bool *no_add_attrs)
33056 if (TREE_CODE (*node) != FUNCTION_TYPE
33057 && TREE_CODE (*node) != FIELD_DECL
33058 && TREE_CODE (*node) != TYPE_DECL)
33060 warning (OPT_Wattributes, "%qE attribute only applies to functions",
33062 *no_add_attrs = true;
33068 /* Set longcall attributes on all functions declared when
33069 rs6000_default_long_calls is true. */
33071 rs6000_set_default_type_attributes (tree type)
33073 if (rs6000_default_long_calls
33074 && (TREE_CODE (type) == FUNCTION_TYPE
33075 || TREE_CODE (type) == METHOD_TYPE))
33076 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
33078 TYPE_ATTRIBUTES (type));
33081 darwin_set_default_type_attributes (type);
33085 /* Return a reference suitable for calling a function with the
33086 longcall attribute. */
33089 rs6000_longcall_ref (rtx call_ref)
33091 const char *call_name;
33094 if (GET_CODE (call_ref) != SYMBOL_REF)
33097 /* System V adds '.' to the internal name, so skip them. */
33098 call_name = XSTR (call_ref, 0);
33099 if (*call_name == '.')
33101 while (*call_name == '.')
33104 node = get_identifier (call_name);
33105 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
33108 return force_reg (Pmode, call_ref);
33111 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
33112 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
33115 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
33116 struct attribute_spec.handler. */
33118 rs6000_handle_struct_attribute (tree *node, tree name,
33119 tree args ATTRIBUTE_UNUSED,
33120 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
33123 if (DECL_P (*node))
33125 if (TREE_CODE (*node) == TYPE_DECL)
33126 type = &TREE_TYPE (*node);
33131 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
33132 || TREE_CODE (*type) == UNION_TYPE)))
33134 warning (OPT_Wattributes, "%qE attribute ignored", name);
33135 *no_add_attrs = true;
33138 else if ((is_attribute_p ("ms_struct", name)
33139 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
33140 || ((is_attribute_p ("gcc_struct", name)
33141 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
33143 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
33145 *no_add_attrs = true;
33152 rs6000_ms_bitfield_layout_p (const_tree record_type)
33154 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
33155 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
33156 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
33159 #ifdef USING_ELFOS_H
33161 /* A get_unnamed_section callback, used for switching to toc_section. */
33164 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33166 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33167 && TARGET_MINIMAL_TOC)
33169 if (!toc_initialized)
33171 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33172 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33173 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
33174 fprintf (asm_out_file, "\t.tc ");
33175 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
33176 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33177 fprintf (asm_out_file, "\n");
33179 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33180 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33181 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33182 fprintf (asm_out_file, " = .+32768\n");
33183 toc_initialized = 1;
33186 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33188 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33190 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33191 if (!toc_initialized)
33193 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33194 toc_initialized = 1;
33199 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33200 if (!toc_initialized)
33202 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33203 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33204 fprintf (asm_out_file, " = .+32768\n");
33205 toc_initialized = 1;
33210 /* Implement TARGET_ASM_INIT_SECTIONS. */
33213 rs6000_elf_asm_init_sections (void)
33216 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
33219 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
33220 SDATA2_SECTION_ASM_OP);
33223 /* Implement TARGET_SELECT_RTX_SECTION. */
33226 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
33227 unsigned HOST_WIDE_INT align)
33229 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33230 return toc_section;
33232 return default_elf_select_rtx_section (mode, x, align);
33235 /* For a SYMBOL_REF, set generic flags and then perform some
33236 target-specific processing.
33238 When the AIX ABI is requested on a non-AIX system, replace the
33239 function name with the real name (with a leading .) rather than the
33240 function descriptor name. This saves a lot of overriding code to
33241 read the prefixes. */
33243 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
33245 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
33247 default_encode_section_info (decl, rtl, first);
33250 && TREE_CODE (decl) == FUNCTION_DECL
33252 && DEFAULT_ABI == ABI_AIX)
33254 rtx sym_ref = XEXP (rtl, 0);
33255 size_t len = strlen (XSTR (sym_ref, 0));
33256 char *str = XALLOCAVEC (char, len + 2);
33258 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
33259 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
33264 compare_section_name (const char *section, const char *templ)
33268 len = strlen (templ);
33269 return (strncmp (section, templ, len) == 0
33270 && (section[len] == 0 || section[len] == '.'));
33274 rs6000_elf_in_small_data_p (const_tree decl)
33276 if (rs6000_sdata == SDATA_NONE)
33279 /* We want to merge strings, so we never consider them small data. */
33280 if (TREE_CODE (decl) == STRING_CST)
33283 /* Functions are never in the small data area. */
33284 if (TREE_CODE (decl) == FUNCTION_DECL)
33287 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
33289 const char *section = DECL_SECTION_NAME (decl);
33290 if (compare_section_name (section, ".sdata")
33291 || compare_section_name (section, ".sdata2")
33292 || compare_section_name (section, ".gnu.linkonce.s")
33293 || compare_section_name (section, ".sbss")
33294 || compare_section_name (section, ".sbss2")
33295 || compare_section_name (section, ".gnu.linkonce.sb")
33296 || strcmp (section, ".PPC.EMB.sdata0") == 0
33297 || strcmp (section, ".PPC.EMB.sbss0") == 0)
33302 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
33305 && size <= g_switch_value
33306 /* If it's not public, and we're not going to reference it there,
33307 there's no need to put it in the small data section. */
33308 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
33315 #endif /* USING_ELFOS_H */
33317 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33320 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
33322 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
33325 /* Do not place thread-local symbols refs in the object blocks. */
33328 rs6000_use_blocks_for_decl_p (const_tree decl)
33330 return !DECL_THREAD_LOCAL_P (decl);
33333 /* Return a REG that occurs in ADDR with coefficient 1.
33334 ADDR can be effectively incremented by incrementing REG.
33336 r0 is special and we must not select it as an address
33337 register by this routine since our caller will try to
33338 increment the returned register via an "la" instruction. */
33341 find_addr_reg (rtx addr)
33343 while (GET_CODE (addr) == PLUS)
33345 if (GET_CODE (XEXP (addr, 0)) == REG
33346 && REGNO (XEXP (addr, 0)) != 0)
33347 addr = XEXP (addr, 0);
33348 else if (GET_CODE (XEXP (addr, 1)) == REG
33349 && REGNO (XEXP (addr, 1)) != 0)
33350 addr = XEXP (addr, 1);
33351 else if (CONSTANT_P (XEXP (addr, 0)))
33352 addr = XEXP (addr, 1);
33353 else if (CONSTANT_P (XEXP (addr, 1)))
33354 addr = XEXP (addr, 0);
33356 gcc_unreachable ();
33358 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
33363 rs6000_fatal_bad_address (rtx op)
33365 fatal_insn ("bad address", op);
33370 typedef struct branch_island_d {
33371 tree function_name;
33377 static vec<branch_island, va_gc> *branch_islands;
33379 /* Remember to generate a branch island for far calls to the given
33383 add_compiler_branch_island (tree label_name, tree function_name,
33386 branch_island bi = {function_name, label_name, line_number};
33387 vec_safe_push (branch_islands, bi);
33390 /* Generate far-jump branch islands for everything recorded in
33391 branch_islands. Invoked immediately after the last instruction of
33392 the epilogue has been emitted; the branch islands must be appended
33393 to, and contiguous with, the function body. Mach-O stubs are
33394 generated in machopic_output_stub(). */
33397 macho_branch_islands (void)
33401 while (!vec_safe_is_empty (branch_islands))
33403 branch_island *bi = &branch_islands->last ();
33404 const char *label = IDENTIFIER_POINTER (bi->label_name);
33405 const char *name = IDENTIFIER_POINTER (bi->function_name);
33406 char name_buf[512];
33407 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33408 if (name[0] == '*' || name[0] == '&')
33409 strcpy (name_buf, name+1);
33413 strcpy (name_buf+1, name);
33415 strcpy (tmp_buf, "\n");
33416 strcat (tmp_buf, label);
33417 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33418 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33419 dbxout_stabd (N_SLINE, bi->line_number);
33420 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33423 if (TARGET_LINK_STACK)
33426 get_ppc476_thunk_name (name);
33427 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33428 strcat (tmp_buf, name);
33429 strcat (tmp_buf, "\n");
33430 strcat (tmp_buf, label);
33431 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33435 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33436 strcat (tmp_buf, label);
33437 strcat (tmp_buf, "_pic\n");
33438 strcat (tmp_buf, label);
33439 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33442 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33443 strcat (tmp_buf, name_buf);
33444 strcat (tmp_buf, " - ");
33445 strcat (tmp_buf, label);
33446 strcat (tmp_buf, "_pic)\n");
33448 strcat (tmp_buf, "\tmtlr r0\n");
33450 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33451 strcat (tmp_buf, name_buf);
33452 strcat (tmp_buf, " - ");
33453 strcat (tmp_buf, label);
33454 strcat (tmp_buf, "_pic)\n");
33456 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33460 strcat (tmp_buf, ":\nlis r12,hi16(");
33461 strcat (tmp_buf, name_buf);
33462 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33463 strcat (tmp_buf, name_buf);
33464 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33466 output_asm_insn (tmp_buf, 0);
33467 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33468 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33469 dbxout_stabd (N_SLINE, bi->line_number);
33470 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33471 branch_islands->pop ();
33475 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33476 already there or not. */
33479 no_previous_def (tree function_name)
33484 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33485 if (function_name == bi->function_name)
33490 /* GET_PREV_LABEL gets the label name from the previous definition of
33494 get_prev_label (tree function_name)
33499 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33500 if (function_name == bi->function_name)
33501 return bi->label_name;
33505 /* INSN is either a function call or a millicode call. It may have an
33506 unconditional jump in its delay slot.
33508 CALL_DEST is the routine we are calling. */
33511 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
33512 int cookie_operand_number)
33514 static char buf[256];
33515 if (darwin_emit_branch_islands
33516 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
33517 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
33520 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
33522 if (no_previous_def (funname))
33524 rtx label_rtx = gen_label_rtx ();
33525 char *label_buf, temp_buf[256];
33526 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
33527 CODE_LABEL_NUMBER (label_rtx));
33528 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
33529 labelname = get_identifier (label_buf);
33530 add_compiler_branch_island (labelname, funname, insn_line (insn));
33533 labelname = get_prev_label (funname);
33535 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33536 instruction will reach 'foo', otherwise link as 'bl L42'".
33537 "L42" should be a 'branch island', that will do a far jump to
33538 'foo'. Branch islands are generated in
33539 macho_branch_islands(). */
33540 sprintf (buf, "jbsr %%z%d,%.246s",
33541 dest_operand_number, IDENTIFIER_POINTER (labelname));
33544 sprintf (buf, "bl %%z%d", dest_operand_number);
33548 /* Generate PIC and indirect symbol stubs. */
33551 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33553 unsigned int length;
33554 char *symbol_name, *lazy_ptr_name;
33555 char *local_label_0;
33556 static int label = 0;
33558 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33559 symb = (*targetm.strip_name_encoding) (symb);
33562 length = strlen (symb);
33563 symbol_name = XALLOCAVEC (char, length + 32);
33564 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33566 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33567 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33570 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33572 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33576 fprintf (file, "\t.align 5\n");
33578 fprintf (file, "%s:\n", stub);
33579 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33582 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33583 sprintf (local_label_0, "\"L%011d$spb\"", label);
33585 fprintf (file, "\tmflr r0\n");
33586 if (TARGET_LINK_STACK)
33589 get_ppc476_thunk_name (name);
33590 fprintf (file, "\tbl %s\n", name);
33591 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33595 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33596 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33598 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33599 lazy_ptr_name, local_label_0);
33600 fprintf (file, "\tmtlr r0\n");
33601 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33602 (TARGET_64BIT ? "ldu" : "lwzu"),
33603 lazy_ptr_name, local_label_0);
33604 fprintf (file, "\tmtctr r12\n");
33605 fprintf (file, "\tbctr\n");
33609 fprintf (file, "\t.align 4\n");
33611 fprintf (file, "%s:\n", stub);
33612 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33614 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33615 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33616 (TARGET_64BIT ? "ldu" : "lwzu"),
33618 fprintf (file, "\tmtctr r12\n");
33619 fprintf (file, "\tbctr\n");
33622 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33623 fprintf (file, "%s:\n", lazy_ptr_name);
33624 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33625 fprintf (file, "%sdyld_stub_binding_helper\n",
33626 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33629 /* Legitimize PIC addresses. If the address is already
33630 position-independent, we return ORIG. Newly generated
33631 position-independent addresses go into a reg. This is REG if non
33632 zero, otherwise we allocate register(s) as necessary. */
33634 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33637 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33642 if (reg == NULL && !reload_completed)
33643 reg = gen_reg_rtx (Pmode);
33645 if (GET_CODE (orig) == CONST)
33649 if (GET_CODE (XEXP (orig, 0)) == PLUS
33650 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33653 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33655 /* Use a different reg for the intermediate value, as
33656 it will be marked UNCHANGING. */
33657 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33658 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33661 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33664 if (GET_CODE (offset) == CONST_INT)
33666 if (SMALL_INT (offset))
33667 return plus_constant (Pmode, base, INTVAL (offset));
33668 else if (!reload_completed)
33669 offset = force_reg (Pmode, offset);
33672 rtx mem = force_const_mem (Pmode, orig);
33673 return machopic_legitimize_pic_address (mem, Pmode, reg);
33676 return gen_rtx_PLUS (Pmode, base, offset);
33679 /* Fall back on generic machopic code. */
33680 return machopic_legitimize_pic_address (orig, mode, reg);
33683 /* Output a .machine directive for the Darwin assembler, and call
33684 the generic start_file routine. */
33687 rs6000_darwin_file_start (void)
33689 static const struct
33693 HOST_WIDE_INT if_set;
33695 { "ppc64", "ppc64", MASK_64BIT },
33696 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33697 { "power4", "ppc970", 0 },
33698 { "G5", "ppc970", 0 },
33699 { "7450", "ppc7450", 0 },
33700 { "7400", "ppc7400", MASK_ALTIVEC },
33701 { "G4", "ppc7400", 0 },
33702 { "750", "ppc750", 0 },
33703 { "740", "ppc750", 0 },
33704 { "G3", "ppc750", 0 },
33705 { "604e", "ppc604e", 0 },
33706 { "604", "ppc604", 0 },
33707 { "603e", "ppc603", 0 },
33708 { "603", "ppc603", 0 },
33709 { "601", "ppc601", 0 },
33710 { NULL, "ppc", 0 } };
33711 const char *cpu_id = "";
33714 rs6000_file_start ();
33715 darwin_file_start ();
33717 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33719 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33720 cpu_id = rs6000_default_cpu;
33722 if (global_options_set.x_rs6000_cpu_index)
33723 cpu_id = processor_target_table[rs6000_cpu_index].name;
33725 /* Look through the mapping array. Pick the first name that either
33726 matches the argument, has a bit set in IF_SET that is also set
33727 in the target flags, or has a NULL name. */
33730 while (mapping[i].arg != NULL
33731 && strcmp (mapping[i].arg, cpu_id) != 0
33732 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33735 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33738 #endif /* TARGET_MACHO */
33742 rs6000_elf_reloc_rw_mask (void)
33746 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33752 /* Record an element in the table of global constructors. SYMBOL is
33753 a SYMBOL_REF of the function to be called; PRIORITY is a number
33754 between 0 and MAX_INIT_PRIORITY.
33756 This differs from default_named_section_asm_out_constructor in
33757 that we have special handling for -mrelocatable. */
33759 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33761 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33763 const char *section = ".ctors";
33766 if (priority != DEFAULT_INIT_PRIORITY)
33768 sprintf (buf, ".ctors.%.5u",
33769 /* Invert the numbering so the linker puts us in the proper
33770 order; constructors are run from right to left, and the
33771 linker sorts in increasing order. */
33772 MAX_INIT_PRIORITY - priority);
33776 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33777 assemble_align (POINTER_SIZE);
33779 if (DEFAULT_ABI == ABI_V4
33780 && (TARGET_RELOCATABLE || flag_pic > 1))
33782 fputs ("\t.long (", asm_out_file);
33783 output_addr_const (asm_out_file, symbol);
33784 fputs (")@fixup\n", asm_out_file);
33787 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33790 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33792 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33794 const char *section = ".dtors";
33797 if (priority != DEFAULT_INIT_PRIORITY)
33799 sprintf (buf, ".dtors.%.5u",
33800 /* Invert the numbering so the linker puts us in the proper
33801 order; constructors are run from right to left, and the
33802 linker sorts in increasing order. */
33803 MAX_INIT_PRIORITY - priority);
33807 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33808 assemble_align (POINTER_SIZE);
33810 if (DEFAULT_ABI == ABI_V4
33811 && (TARGET_RELOCATABLE || flag_pic > 1))
33813 fputs ("\t.long (", asm_out_file);
33814 output_addr_const (asm_out_file, symbol);
33815 fputs (")@fixup\n", asm_out_file);
33818 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33822 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33824 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33826 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33827 ASM_OUTPUT_LABEL (file, name);
33828 fputs (DOUBLE_INT_ASM_OP, file);
33829 rs6000_output_function_entry (file, name);
33830 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33833 fputs ("\t.size\t", file);
33834 assemble_name (file, name);
33835 fputs (",24\n\t.type\t.", file);
33836 assemble_name (file, name);
33837 fputs (",@function\n", file);
33838 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33840 fputs ("\t.globl\t.", file);
33841 assemble_name (file, name);
33846 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33847 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33848 rs6000_output_function_entry (file, name);
33849 fputs (":\n", file);
33854 if (DEFAULT_ABI == ABI_V4
33855 && (TARGET_RELOCATABLE || flag_pic > 1)
33856 && !TARGET_SECURE_PLT
33857 && (!constant_pool_empty_p () || crtl->profile)
33858 && (uses_toc = uses_TOC ()))
33863 switch_to_other_text_partition ();
33864 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33866 fprintf (file, "\t.long ");
33867 assemble_name (file, toc_label_name);
33870 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33871 assemble_name (file, buf);
33874 switch_to_other_text_partition ();
33877 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33878 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33880 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33884 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33886 fprintf (file, "\t.quad .TOC.-");
33887 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33888 assemble_name (file, buf);
33892 if (DEFAULT_ABI == ABI_AIX)
33894 const char *desc_name, *orig_name;
33896 orig_name = (*targetm.strip_name_encoding) (name);
33897 desc_name = orig_name;
33898 while (*desc_name == '.')
33901 if (TREE_PUBLIC (decl))
33902 fprintf (file, "\t.globl %s\n", desc_name);
33904 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33905 fprintf (file, "%s:\n", desc_name);
33906 fprintf (file, "\t.long %s\n", orig_name);
33907 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33908 fputs ("\t.long 0\n", file);
33909 fprintf (file, "\t.previous\n");
33911 ASM_OUTPUT_LABEL (file, name);
33914 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33916 rs6000_elf_file_end (void)
33918 #ifdef HAVE_AS_GNU_ATTRIBUTE
33919 /* ??? The value emitted depends on options active at file end.
33920 Assume anyone using #pragma or attributes that might change
33921 options knows what they are doing. */
33922 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33923 && rs6000_passes_float)
33929 else if (TARGET_SF_FPR)
33933 if (rs6000_passes_long_double)
33935 if (!TARGET_LONG_DOUBLE_128)
33937 else if (TARGET_IEEEQUAD)
33942 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33944 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33946 if (rs6000_passes_vector)
33947 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33948 (TARGET_ALTIVEC_ABI ? 2 : 1));
33949 if (rs6000_returns_struct)
33950 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33951 aix_struct_return ? 2 : 1);
33954 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33955 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33956 file_end_indicate_exec_stack ();
33959 if (flag_split_stack)
33960 file_end_indicate_split_stack ();
33964 /* We have expanded a CPU builtin, so we need to emit a reference to
33965 the special symbol that LIBC uses to declare it supports the
33966 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33967 switch_to_section (data_section);
33968 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33969 fprintf (asm_out_file, "\t%s %s\n",
33970 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33977 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33978 #define HAVE_XCOFF_DWARF_EXTRAS 0
33981 static enum unwind_info_type
33982 rs6000_xcoff_debug_unwind_info (void)
33988 rs6000_xcoff_asm_output_anchor (rtx symbol)
33992 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33993 SYMBOL_REF_BLOCK_OFFSET (symbol));
33994 fprintf (asm_out_file, "%s", SET_ASM_OP);
33995 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33996 fprintf (asm_out_file, ",");
33997 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33998 fprintf (asm_out_file, "\n");
34002 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
34004 fputs (GLOBAL_ASM_OP, stream);
34005 RS6000_OUTPUT_BASENAME (stream, name);
34006 putc ('\n', stream);
34009 /* A get_unnamed_decl callback, used for read-only sections. PTR
34010 points to the section string variable. */
34013 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
34015 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
34016 *(const char *const *) directive,
34017 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34020 /* Likewise for read-write sections. */
34023 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
34025 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
34026 *(const char *const *) directive,
34027 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34031 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
34033 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
34034 *(const char *const *) directive,
34035 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34038 /* A get_unnamed_section callback, used for switching to toc_section. */
34041 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
34043 if (TARGET_MINIMAL_TOC)
34045 /* toc_section is always selected at least once from
34046 rs6000_xcoff_file_start, so this is guaranteed to
34047 always be defined once and only once in each file. */
34048 if (!toc_initialized)
34050 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
34051 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
34052 toc_initialized = 1;
34054 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
34055 (TARGET_32BIT ? "" : ",3"));
34058 fputs ("\t.toc\n", asm_out_file);
34061 /* Implement TARGET_ASM_INIT_SECTIONS. */
34064 rs6000_xcoff_asm_init_sections (void)
34066 read_only_data_section
34067 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34068 &xcoff_read_only_section_name);
34070 private_data_section
34071 = get_unnamed_section (SECTION_WRITE,
34072 rs6000_xcoff_output_readwrite_section_asm_op,
34073 &xcoff_private_data_section_name);
34076 = get_unnamed_section (SECTION_TLS,
34077 rs6000_xcoff_output_tls_section_asm_op,
34078 &xcoff_tls_data_section_name);
34080 tls_private_data_section
34081 = get_unnamed_section (SECTION_TLS,
34082 rs6000_xcoff_output_tls_section_asm_op,
34083 &xcoff_private_data_section_name);
34085 read_only_private_data_section
34086 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34087 &xcoff_private_data_section_name);
34090 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
34092 readonly_data_section = read_only_data_section;
34096 rs6000_xcoff_reloc_rw_mask (void)
34102 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
34103 tree decl ATTRIBUTE_UNUSED)
34106 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
34108 if (flags & SECTION_EXCLUDE)
34110 else if (flags & SECTION_DEBUG)
34112 fprintf (asm_out_file, "\t.dwsect %s\n", name);
34115 else if (flags & SECTION_CODE)
34117 else if (flags & SECTION_TLS)
34119 else if (flags & SECTION_WRITE)
34124 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
34125 (flags & SECTION_CODE) ? "." : "",
34126 name, suffix[smclass], flags & SECTION_ENTSIZE);
34129 #define IN_NAMED_SECTION(DECL) \
34130 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
34131 && DECL_SECTION_NAME (DECL) != NULL)
34134 rs6000_xcoff_select_section (tree decl, int reloc,
34135 unsigned HOST_WIDE_INT align)
34137 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
34139 if (align > BIGGEST_ALIGNMENT)
34141 resolve_unique_section (decl, reloc, true);
34142 if (IN_NAMED_SECTION (decl))
34143 return get_named_section (decl, NULL, reloc);
34146 if (decl_readonly_section (decl, reloc))
34148 if (TREE_PUBLIC (decl))
34149 return read_only_data_section;
34151 return read_only_private_data_section;
34156 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34158 if (TREE_PUBLIC (decl))
34159 return tls_data_section;
34160 else if (bss_initializer_p (decl))
34162 /* Convert to COMMON to emit in BSS. */
34163 DECL_COMMON (decl) = 1;
34164 return tls_comm_section;
34167 return tls_private_data_section;
34171 if (TREE_PUBLIC (decl))
34172 return data_section;
34174 return private_data_section;
34179 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
34183 /* Use select_section for private data and uninitialized data with
34184 alignment <= BIGGEST_ALIGNMENT. */
34185 if (!TREE_PUBLIC (decl)
34186 || DECL_COMMON (decl)
34187 || (DECL_INITIAL (decl) == NULL_TREE
34188 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
34189 || DECL_INITIAL (decl) == error_mark_node
34190 || (flag_zero_initialized_in_bss
34191 && initializer_zerop (DECL_INITIAL (decl))))
34194 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
34195 name = (*targetm.strip_name_encoding) (name);
34196 set_decl_section_name (decl, name);
34199 /* Select section for constant in constant pool.
34201 On RS/6000, all constants are in the private read-only data area.
34202 However, if this is being placed in the TOC it must be output as a
34206 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
34207 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
34209 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
34210 return toc_section;
34212 return read_only_private_data_section;
34215 /* Remove any trailing [DS] or the like from the symbol name. */
34217 static const char *
34218 rs6000_xcoff_strip_name_encoding (const char *name)
34223 len = strlen (name);
34224 if (name[len - 1] == ']')
34225 return ggc_alloc_string (name, len - 4);
34230 /* Section attributes. AIX is always PIC. */
34232 static unsigned int
34233 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
34235 unsigned int align;
34236 unsigned int flags = default_section_type_flags (decl, name, reloc);
34238 /* Align to at least UNIT size. */
34239 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
34240 align = MIN_UNITS_PER_WORD;
34242 /* Increase alignment of large objects if not already stricter. */
34243 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
34244 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
34245 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
34247 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
34250 /* Output at beginning of assembler file.
34252 Initialize the section names for the RS/6000 at this point.
34254 Specify filename, including full path, to assembler.
34256 We want to go into the TOC section so at least one .toc will be emitted.
34257 Also, in order to output proper .bs/.es pairs, we need at least one static
34258 [RW] section emitted.
34260 Finally, declare mcount when profiling to make the assembler happy. */
34263 rs6000_xcoff_file_start (void)
34265 rs6000_gen_section_name (&xcoff_bss_section_name,
34266 main_input_filename, ".bss_");
34267 rs6000_gen_section_name (&xcoff_private_data_section_name,
34268 main_input_filename, ".rw_");
34269 rs6000_gen_section_name (&xcoff_read_only_section_name,
34270 main_input_filename, ".ro_");
34271 rs6000_gen_section_name (&xcoff_tls_data_section_name,
34272 main_input_filename, ".tls_");
34273 rs6000_gen_section_name (&xcoff_tbss_section_name,
34274 main_input_filename, ".tbss_[UL]");
34276 fputs ("\t.file\t", asm_out_file);
34277 output_quoted_string (asm_out_file, main_input_filename);
34278 fputc ('\n', asm_out_file);
34279 if (write_symbols != NO_DEBUG)
34280 switch_to_section (private_data_section);
34281 switch_to_section (toc_section);
34282 switch_to_section (text_section);
34284 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
34285 rs6000_file_start ();
34288 /* Output at end of assembler file.
34289 On the RS/6000, referencing data should automatically pull in text. */
34292 rs6000_xcoff_file_end (void)
34294 switch_to_section (text_section);
34295 fputs ("_section_.text:\n", asm_out_file);
34296 switch_to_section (data_section);
34297 fputs (TARGET_32BIT
34298 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34302 struct declare_alias_data
34305 bool function_descriptor;
34308 /* Declare alias N. A helper function for for_node_and_aliases. */
34311 rs6000_declare_alias (struct symtab_node *n, void *d)
34313 struct declare_alias_data *data = (struct declare_alias_data *)d;
34314 /* Main symbol is output specially, because varasm machinery does part of
34315 the job for us - we do not need to declare .globl/lglobs and such. */
34316 if (!n->alias || n->weakref)
34319 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
34322 /* Prevent assemble_alias from trying to use .set pseudo operation
34323 that does not behave as expected by the middle-end. */
34324 TREE_ASM_WRITTEN (n->decl) = true;
34326 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
34327 char *buffer = (char *) alloca (strlen (name) + 2);
34329 int dollar_inside = 0;
34331 strcpy (buffer, name);
34332 p = strchr (buffer, '$');
34336 p = strchr (p + 1, '$');
34338 if (TREE_PUBLIC (n->decl))
34340 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
34342 if (dollar_inside) {
34343 if (data->function_descriptor)
34344 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34345 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34347 if (data->function_descriptor)
34349 fputs ("\t.globl .", data->file);
34350 RS6000_OUTPUT_BASENAME (data->file, buffer);
34351 putc ('\n', data->file);
34353 fputs ("\t.globl ", data->file);
34354 RS6000_OUTPUT_BASENAME (data->file, buffer);
34355 putc ('\n', data->file);
34357 #ifdef ASM_WEAKEN_DECL
34358 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
34359 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
34366 if (data->function_descriptor)
34367 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34368 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34370 if (data->function_descriptor)
34372 fputs ("\t.lglobl .", data->file);
34373 RS6000_OUTPUT_BASENAME (data->file, buffer);
34374 putc ('\n', data->file);
34376 fputs ("\t.lglobl ", data->file);
34377 RS6000_OUTPUT_BASENAME (data->file, buffer);
34378 putc ('\n', data->file);
34380 if (data->function_descriptor)
34381 fputs (".", data->file);
34382 RS6000_OUTPUT_BASENAME (data->file, buffer);
34383 fputs (":\n", data->file);
34388 #ifdef HAVE_GAS_HIDDEN
34389 /* Helper function to calculate visibility of a DECL
34390 and return the value as a const string. */
34392 static const char *
34393 rs6000_xcoff_visibility (tree decl)
34395 static const char * const visibility_types[] = {
34396 "", ",protected", ",hidden", ",internal"
34399 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34401 if (TREE_CODE (decl) == FUNCTION_DECL
34402 && cgraph_node::get (decl)
34403 && cgraph_node::get (decl)->instrumentation_clone
34404 && cgraph_node::get (decl)->instrumented_version)
34405 vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
34407 return visibility_types[vis];
34412 /* This macro produces the initial definition of a function name.
34413 On the RS/6000, we need to place an extra '.' in the function name and
34414 output the function descriptor.
34415 Dollar signs are converted to underscores.
34417 The csect for the function will have already been created when
34418 text_section was selected. We do have to go back to that csect, however.
34420 The third and fourth parameters to the .function pseudo-op (16 and 044)
34421 are placeholders which no longer have any use.
34423 Because AIX assembler's .set command has unexpected semantics, we output
34424 all aliases as alternative labels in front of the definition. */
34427 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34429 char *buffer = (char *) alloca (strlen (name) + 1);
34431 int dollar_inside = 0;
34432 struct declare_alias_data data = {file, false};
34434 strcpy (buffer, name);
34435 p = strchr (buffer, '$');
34439 p = strchr (p + 1, '$');
34441 if (TREE_PUBLIC (decl))
34443 if (!RS6000_WEAK || !DECL_WEAK (decl))
34445 if (dollar_inside) {
34446 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34447 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34449 fputs ("\t.globl .", file);
34450 RS6000_OUTPUT_BASENAME (file, buffer);
34451 #ifdef HAVE_GAS_HIDDEN
34452 fputs (rs6000_xcoff_visibility (decl), file);
34459 if (dollar_inside) {
34460 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34461 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34463 fputs ("\t.lglobl .", file);
34464 RS6000_OUTPUT_BASENAME (file, buffer);
34467 fputs ("\t.csect ", file);
34468 RS6000_OUTPUT_BASENAME (file, buffer);
34469 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34470 RS6000_OUTPUT_BASENAME (file, buffer);
34471 fputs (":\n", file);
34472 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34474 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34475 RS6000_OUTPUT_BASENAME (file, buffer);
34476 fputs (", TOC[tc0], 0\n", file);
34478 switch_to_section (function_section (decl));
34480 RS6000_OUTPUT_BASENAME (file, buffer);
34481 fputs (":\n", file);
34482 data.function_descriptor = true;
34483 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34485 if (!DECL_IGNORED_P (decl))
34487 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34488 xcoffout_declare_function (file, decl, buffer);
34489 else if (write_symbols == DWARF2_DEBUG)
34491 name = (*targetm.strip_name_encoding) (name);
34492 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34499 /* Output assembly language to globalize a symbol from a DECL,
34500 possibly with visibility. */
34503 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34505 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34506 fputs (GLOBAL_ASM_OP, stream);
34507 RS6000_OUTPUT_BASENAME (stream, name);
34508 #ifdef HAVE_GAS_HIDDEN
34509 fputs (rs6000_xcoff_visibility (decl), stream);
34511 putc ('\n', stream);
34514 /* Output assembly language to define a symbol as COMMON from a DECL,
34515 possibly with visibility. */
34518 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34519 tree decl ATTRIBUTE_UNUSED,
34521 unsigned HOST_WIDE_INT size,
34522 unsigned HOST_WIDE_INT align)
34524 unsigned HOST_WIDE_INT align2 = 2;
34527 align2 = floor_log2 (align / BITS_PER_UNIT);
34531 fputs (COMMON_ASM_OP, stream);
34532 RS6000_OUTPUT_BASENAME (stream, name);
34535 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34538 #ifdef HAVE_GAS_HIDDEN
34540 fputs (rs6000_xcoff_visibility (decl), stream);
34542 putc ('\n', stream);
34545 /* This macro produces the initial definition of a object (variable) name.
34546 Because AIX assembler's .set command has unexpected semantics, we output
34547 all aliases as alternative labels in front of the definition. */
34550 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34552 struct declare_alias_data data = {file, false};
34553 RS6000_OUTPUT_BASENAME (file, name);
34554 fputs (":\n", file);
34555 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34559 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34562 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34564 fputs (integer_asm_op (size, FALSE), file);
34565 assemble_name (file, label);
34566 fputs ("-$", file);
34569 /* Output a symbol offset relative to the dbase for the current object.
34570 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34573 __gcc_unwind_dbase is embedded in all executables/libraries through
34574 libgcc/config/rs6000/crtdbase.S. */
34577 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34579 fputs (integer_asm_op (size, FALSE), file);
34580 assemble_name (file, label);
34581 fputs("-__gcc_unwind_dbase", file);
34586 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34590 const char *symname;
34592 default_encode_section_info (decl, rtl, first);
34594 /* Careful not to prod global register variables. */
34597 symbol = XEXP (rtl, 0);
34598 if (GET_CODE (symbol) != SYMBOL_REF)
34601 flags = SYMBOL_REF_FLAGS (symbol);
34603 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34604 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34606 SYMBOL_REF_FLAGS (symbol) = flags;
34608 /* Append mapping class to extern decls. */
34609 symname = XSTR (symbol, 0);
34610 if (decl /* sync condition with assemble_external () */
34611 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34612 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34613 || TREE_CODE (decl) == FUNCTION_DECL)
34614 && symname[strlen (symname) - 1] != ']')
34616 char *newname = (char *) alloca (strlen (symname) + 5);
34617 strcpy (newname, symname);
34618 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34619 ? "[DS]" : "[UA]"));
34620 XSTR (symbol, 0) = ggc_strdup (newname);
34623 #endif /* HAVE_AS_TLS */
34624 #endif /* TARGET_XCOFF */
34627 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34628 const char *name, const char *val)
34630 fputs ("\t.weak\t", stream);
34631 RS6000_OUTPUT_BASENAME (stream, name);
34632 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34633 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34636 fputs ("[DS]", stream);
34637 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34639 fputs (rs6000_xcoff_visibility (decl), stream);
34641 fputs ("\n\t.weak\t.", stream);
34642 RS6000_OUTPUT_BASENAME (stream, name);
34644 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34646 fputs (rs6000_xcoff_visibility (decl), stream);
34648 fputc ('\n', stream);
34651 #ifdef ASM_OUTPUT_DEF
34652 ASM_OUTPUT_DEF (stream, name, val);
34654 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34655 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34657 fputs ("\t.set\t.", stream);
34658 RS6000_OUTPUT_BASENAME (stream, name);
34659 fputs (",.", stream);
34660 RS6000_OUTPUT_BASENAME (stream, val);
34661 fputc ('\n', stream);
34667 /* Return true if INSN should not be copied. */
34670 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34672 return recog_memoized (insn) >= 0
34673 && get_attr_cannot_copy (insn);
34676 /* Compute a (partial) cost for rtx X. Return true if the complete
34677 cost has been computed, and false if subexpressions should be
34678 scanned. In either case, *TOTAL contains the cost result. */
34681 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34682 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34684 int code = GET_CODE (x);
34688 /* On the RS/6000, if it is valid in the insn, it is free. */
34690 if (((outer_code == SET
34691 || outer_code == PLUS
34692 || outer_code == MINUS)
34693 && (satisfies_constraint_I (x)
34694 || satisfies_constraint_L (x)))
34695 || (outer_code == AND
34696 && (satisfies_constraint_K (x)
34698 ? satisfies_constraint_L (x)
34699 : satisfies_constraint_J (x))))
34700 || ((outer_code == IOR || outer_code == XOR)
34701 && (satisfies_constraint_K (x)
34703 ? satisfies_constraint_L (x)
34704 : satisfies_constraint_J (x))))
34705 || outer_code == ASHIFT
34706 || outer_code == ASHIFTRT
34707 || outer_code == LSHIFTRT
34708 || outer_code == ROTATE
34709 || outer_code == ROTATERT
34710 || outer_code == ZERO_EXTRACT
34711 || (outer_code == MULT
34712 && satisfies_constraint_I (x))
34713 || ((outer_code == DIV || outer_code == UDIV
34714 || outer_code == MOD || outer_code == UMOD)
34715 && exact_log2 (INTVAL (x)) >= 0)
34716 || (outer_code == COMPARE
34717 && (satisfies_constraint_I (x)
34718 || satisfies_constraint_K (x)))
34719 || ((outer_code == EQ || outer_code == NE)
34720 && (satisfies_constraint_I (x)
34721 || satisfies_constraint_K (x)
34723 ? satisfies_constraint_L (x)
34724 : satisfies_constraint_J (x))))
34725 || (outer_code == GTU
34726 && satisfies_constraint_I (x))
34727 || (outer_code == LTU
34728 && satisfies_constraint_P (x)))
34733 else if ((outer_code == PLUS
34734 && reg_or_add_cint_operand (x, VOIDmode))
34735 || (outer_code == MINUS
34736 && reg_or_sub_cint_operand (x, VOIDmode))
34737 || ((outer_code == SET
34738 || outer_code == IOR
34739 || outer_code == XOR)
34741 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34743 *total = COSTS_N_INSNS (1);
34749 case CONST_WIDE_INT:
34753 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34757 /* When optimizing for size, MEM should be slightly more expensive
34758 than generating address, e.g., (plus (reg) (const)).
34759 L1 cache latency is about two instructions. */
34760 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34761 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34762 *total += COSTS_N_INSNS (100);
34771 if (FLOAT_MODE_P (mode))
34772 *total = rs6000_cost->fp;
34774 *total = COSTS_N_INSNS (1);
34778 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34779 && satisfies_constraint_I (XEXP (x, 1)))
34781 if (INTVAL (XEXP (x, 1)) >= -256
34782 && INTVAL (XEXP (x, 1)) <= 255)
34783 *total = rs6000_cost->mulsi_const9;
34785 *total = rs6000_cost->mulsi_const;
34787 else if (mode == SFmode)
34788 *total = rs6000_cost->fp;
34789 else if (FLOAT_MODE_P (mode))
34790 *total = rs6000_cost->dmul;
34791 else if (mode == DImode)
34792 *total = rs6000_cost->muldi;
34794 *total = rs6000_cost->mulsi;
34798 if (mode == SFmode)
34799 *total = rs6000_cost->fp;
34801 *total = rs6000_cost->dmul;
34806 if (FLOAT_MODE_P (mode))
34808 *total = mode == DFmode ? rs6000_cost->ddiv
34809 : rs6000_cost->sdiv;
34816 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34817 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34819 if (code == DIV || code == MOD)
34821 *total = COSTS_N_INSNS (2);
34824 *total = COSTS_N_INSNS (1);
34828 if (GET_MODE (XEXP (x, 1)) == DImode)
34829 *total = rs6000_cost->divdi;
34831 *total = rs6000_cost->divsi;
34833 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34834 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34835 *total += COSTS_N_INSNS (2);
34839 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34843 *total = COSTS_N_INSNS (4);
34847 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34851 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34855 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34858 *total = COSTS_N_INSNS (1);
34862 if (CONST_INT_P (XEXP (x, 1)))
34864 rtx left = XEXP (x, 0);
34865 rtx_code left_code = GET_CODE (left);
34867 /* rotate-and-mask: 1 insn. */
34868 if ((left_code == ROTATE
34869 || left_code == ASHIFT
34870 || left_code == LSHIFTRT)
34871 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34873 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34874 if (!CONST_INT_P (XEXP (left, 1)))
34875 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34876 *total += COSTS_N_INSNS (1);
34880 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34881 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34882 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34883 || (val & 0xffff) == val
34884 || (val & 0xffff0000) == val
34885 || ((val & 0xffff) == 0 && mode == SImode))
34887 *total = rtx_cost (left, mode, AND, 0, speed);
34888 *total += COSTS_N_INSNS (1);
34893 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34895 *total = rtx_cost (left, mode, AND, 0, speed);
34896 *total += COSTS_N_INSNS (2);
34901 *total = COSTS_N_INSNS (1);
34906 *total = COSTS_N_INSNS (1);
34912 *total = COSTS_N_INSNS (1);
34916 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34917 the sign extend and shift separately within the insn. */
34918 if (TARGET_EXTSWSLI && mode == DImode
34919 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34920 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34931 /* Handle mul_highpart. */
34932 if (outer_code == TRUNCATE
34933 && GET_CODE (XEXP (x, 0)) == MULT)
34935 if (mode == DImode)
34936 *total = rs6000_cost->muldi;
34938 *total = rs6000_cost->mulsi;
34941 else if (outer_code == AND)
34944 *total = COSTS_N_INSNS (1);
34949 if (GET_CODE (XEXP (x, 0)) == MEM)
34952 *total = COSTS_N_INSNS (1);
34958 if (!FLOAT_MODE_P (mode))
34960 *total = COSTS_N_INSNS (1);
34966 case UNSIGNED_FLOAT:
34969 case FLOAT_TRUNCATE:
34970 *total = rs6000_cost->fp;
34974 if (mode == DFmode)
34975 *total = rs6000_cost->sfdf_convert;
34977 *total = rs6000_cost->fp;
34981 switch (XINT (x, 1))
34984 *total = rs6000_cost->fp;
34996 *total = COSTS_N_INSNS (1);
34999 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
35001 *total = rs6000_cost->fp;
35010 /* Carry bit requires mode == Pmode.
35011 NEG or PLUS already counted so only add one. */
35013 && (outer_code == NEG || outer_code == PLUS))
35015 *total = COSTS_N_INSNS (1);
35018 if (outer_code == SET)
35020 if (XEXP (x, 1) == const0_rtx)
35022 if (TARGET_ISEL && !TARGET_MFCRF)
35023 *total = COSTS_N_INSNS (8);
35025 *total = COSTS_N_INSNS (2);
35030 *total = COSTS_N_INSNS (3);
35039 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
35041 if (TARGET_ISEL && !TARGET_MFCRF)
35042 *total = COSTS_N_INSNS (8);
35044 *total = COSTS_N_INSNS (2);
35048 if (outer_code == COMPARE)
35062 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
35065 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
35066 int opno, int *total, bool speed)
35068 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
35071 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
35072 "opno = %d, total = %d, speed = %s, x:\n",
35073 ret ? "complete" : "scan inner",
35074 GET_MODE_NAME (mode),
35075 GET_RTX_NAME (outer_code),
35078 speed ? "true" : "false");
35086 rs6000_insn_cost (rtx_insn *insn, bool speed)
35088 if (recog_memoized (insn) < 0)
35092 return get_attr_length (insn);
35094 int cost = get_attr_cost (insn);
35098 int n = get_attr_length (insn) / 4;
35099 enum attr_type type = get_attr_type (insn);
35106 cost = COSTS_N_INSNS (n + 1);
35110 switch (get_attr_size (insn))
35113 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
35116 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
35119 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
35122 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
35125 gcc_unreachable ();
35129 switch (get_attr_size (insn))
35132 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
35135 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
35138 gcc_unreachable ();
35143 cost = n * rs6000_cost->fp;
35146 cost = n * rs6000_cost->dmul;
35149 cost = n * rs6000_cost->sdiv;
35152 cost = n * rs6000_cost->ddiv;
35159 cost = COSTS_N_INSNS (n + 2);
35163 cost = COSTS_N_INSNS (n);
35169 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35172 rs6000_debug_address_cost (rtx x, machine_mode mode,
35173 addr_space_t as, bool speed)
35175 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
35177 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35178 ret, speed ? "true" : "false");
35185 /* A C expression returning the cost of moving data from a register of class
35186 CLASS1 to one of CLASS2. */
35189 rs6000_register_move_cost (machine_mode mode,
35190 reg_class_t from, reg_class_t to)
35194 if (TARGET_DEBUG_COST)
35197 /* Moves from/to GENERAL_REGS. */
35198 if (reg_classes_intersect_p (to, GENERAL_REGS)
35199 || reg_classes_intersect_p (from, GENERAL_REGS))
35201 reg_class_t rclass = from;
35203 if (! reg_classes_intersect_p (to, GENERAL_REGS))
35206 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
35207 ret = (rs6000_memory_move_cost (mode, rclass, false)
35208 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
35210 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35212 else if (rclass == CR_REGS)
35215 /* For those processors that have slow LR/CTR moves, make them more
35216 expensive than memory in order to bias spills to memory .*/
35217 else if ((rs6000_cpu == PROCESSOR_POWER6
35218 || rs6000_cpu == PROCESSOR_POWER7
35219 || rs6000_cpu == PROCESSOR_POWER8
35220 || rs6000_cpu == PROCESSOR_POWER9)
35221 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
35222 ret = 6 * hard_regno_nregs (0, mode);
35225 /* A move will cost one instruction per GPR moved. */
35226 ret = 2 * hard_regno_nregs (0, mode);
35229 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35230 else if (VECTOR_MEM_VSX_P (mode)
35231 && reg_classes_intersect_p (to, VSX_REGS)
35232 && reg_classes_intersect_p (from, VSX_REGS))
35233 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
35235 /* Moving between two similar registers is just one instruction. */
35236 else if (reg_classes_intersect_p (to, from))
35237 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
35239 /* Everything else has to go through GENERAL_REGS. */
35241 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
35242 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
35244 if (TARGET_DEBUG_COST)
35246 if (dbg_cost_ctrl == 1)
35248 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
35249 ret, GET_MODE_NAME (mode), reg_class_names[from],
35250 reg_class_names[to]);
35257 /* A C expressions returning the cost of moving data of MODE from a register to
35261 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
35262 bool in ATTRIBUTE_UNUSED)
35266 if (TARGET_DEBUG_COST)
35269 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
35270 ret = 4 * hard_regno_nregs (0, mode);
35271 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
35272 || reg_classes_intersect_p (rclass, VSX_REGS)))
35273 ret = 4 * hard_regno_nregs (32, mode);
35274 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
35275 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
35277 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
35279 if (TARGET_DEBUG_COST)
35281 if (dbg_cost_ctrl == 1)
35283 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35284 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
35291 /* Returns a code for a target-specific builtin that implements
35292 reciprocal of the function, or NULL_TREE if not available. */
35295 rs6000_builtin_reciprocal (tree fndecl)
35297 switch (DECL_FUNCTION_CODE (fndecl))
35299 case VSX_BUILTIN_XVSQRTDP:
35300 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
35303 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
35305 case VSX_BUILTIN_XVSQRTSP:
35306 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
35309 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
35316 /* Load up a constant. If the mode is a vector mode, splat the value across
35317 all of the vector elements. */
35320 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
35324 if (mode == SFmode || mode == DFmode)
35326 rtx d = const_double_from_real_value (dconst, mode);
35327 reg = force_reg (mode, d);
35329 else if (mode == V4SFmode)
35331 rtx d = const_double_from_real_value (dconst, SFmode);
35332 rtvec v = gen_rtvec (4, d, d, d, d);
35333 reg = gen_reg_rtx (mode);
35334 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35336 else if (mode == V2DFmode)
35338 rtx d = const_double_from_real_value (dconst, DFmode);
35339 rtvec v = gen_rtvec (2, d, d);
35340 reg = gen_reg_rtx (mode);
35341 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35344 gcc_unreachable ();
35349 /* Generate an FMA instruction. */
35352 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35354 machine_mode mode = GET_MODE (target);
35357 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35358 gcc_assert (dst != NULL);
35361 emit_move_insn (target, dst);
35364 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35367 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35369 machine_mode mode = GET_MODE (dst);
35372 /* This is a tad more complicated, since the fnma_optab is for
35373 a different expression: fma(-m1, m2, a), which is the same
35374 thing except in the case of signed zeros.
35376 Fortunately we know that if FMA is supported that FNMSUB is
35377 also supported in the ISA. Just expand it directly. */
35379 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35381 r = gen_rtx_NEG (mode, a);
35382 r = gen_rtx_FMA (mode, m1, m2, r);
35383 r = gen_rtx_NEG (mode, r);
35384 emit_insn (gen_rtx_SET (dst, r));
35387 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35388 add a reg_note saying that this was a division. Support both scalar and
35389 vector divide. Assumes no trapping math and finite arguments. */
35392 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35394 machine_mode mode = GET_MODE (dst);
35395 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35398 /* Low precision estimates guarantee 5 bits of accuracy. High
35399 precision estimates guarantee 14 bits of accuracy. SFmode
35400 requires 23 bits of accuracy. DFmode requires 52 bits of
35401 accuracy. Each pass at least doubles the accuracy, leading
35402 to the following. */
35403 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35404 if (mode == DFmode || mode == V2DFmode)
35407 enum insn_code code = optab_handler (smul_optab, mode);
35408 insn_gen_fn gen_mul = GEN_FCN (code);
35410 gcc_assert (code != CODE_FOR_nothing);
35412 one = rs6000_load_constant_and_splat (mode, dconst1);
35414 /* x0 = 1./d estimate */
35415 x0 = gen_reg_rtx (mode);
35416 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35419 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35422 /* e0 = 1. - d * x0 */
35423 e0 = gen_reg_rtx (mode);
35424 rs6000_emit_nmsub (e0, d, x0, one);
35426 /* x1 = x0 + e0 * x0 */
35427 x1 = gen_reg_rtx (mode);
35428 rs6000_emit_madd (x1, e0, x0, x0);
35430 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35431 ++i, xprev = xnext, eprev = enext) {
35433 /* enext = eprev * eprev */
35434 enext = gen_reg_rtx (mode);
35435 emit_insn (gen_mul (enext, eprev, eprev));
35437 /* xnext = xprev + enext * xprev */
35438 xnext = gen_reg_rtx (mode);
35439 rs6000_emit_madd (xnext, enext, xprev, xprev);
35445 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35447 /* u = n * xprev */
35448 u = gen_reg_rtx (mode);
35449 emit_insn (gen_mul (u, n, xprev));
35451 /* v = n - (d * u) */
35452 v = gen_reg_rtx (mode);
35453 rs6000_emit_nmsub (v, d, u, n);
35455 /* dst = (v * xprev) + u */
35456 rs6000_emit_madd (dst, v, xprev, u);
35459 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35462 /* Goldschmidt's Algorithm for single/double-precision floating point
35463 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35466 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35468 machine_mode mode = GET_MODE (src);
35469 rtx e = gen_reg_rtx (mode);
35470 rtx g = gen_reg_rtx (mode);
35471 rtx h = gen_reg_rtx (mode);
35473 /* Low precision estimates guarantee 5 bits of accuracy. High
35474 precision estimates guarantee 14 bits of accuracy. SFmode
35475 requires 23 bits of accuracy. DFmode requires 52 bits of
35476 accuracy. Each pass at least doubles the accuracy, leading
35477 to the following. */
35478 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35479 if (mode == DFmode || mode == V2DFmode)
35484 enum insn_code code = optab_handler (smul_optab, mode);
35485 insn_gen_fn gen_mul = GEN_FCN (code);
35487 gcc_assert (code != CODE_FOR_nothing);
35489 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35491 /* e = rsqrt estimate */
35492 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35495 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35498 rtx zero = force_reg (mode, CONST0_RTX (mode));
35500 if (mode == SFmode)
35502 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35505 emit_move_insn (e, target);
35509 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35510 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35514 /* g = sqrt estimate. */
35515 emit_insn (gen_mul (g, e, src));
35516 /* h = 1/(2*sqrt) estimate. */
35517 emit_insn (gen_mul (h, e, mhalf));
35523 rtx t = gen_reg_rtx (mode);
35524 rs6000_emit_nmsub (t, g, h, mhalf);
35525 /* Apply correction directly to 1/rsqrt estimate. */
35526 rs6000_emit_madd (dst, e, t, e);
35530 for (i = 0; i < passes; i++)
35532 rtx t1 = gen_reg_rtx (mode);
35533 rtx g1 = gen_reg_rtx (mode);
35534 rtx h1 = gen_reg_rtx (mode);
35536 rs6000_emit_nmsub (t1, g, h, mhalf);
35537 rs6000_emit_madd (g1, g, t1, g);
35538 rs6000_emit_madd (h1, h, t1, h);
35543 /* Multiply by 2 for 1/rsqrt. */
35544 emit_insn (gen_add3_insn (dst, h, h));
35549 rtx t = gen_reg_rtx (mode);
35550 rs6000_emit_nmsub (t, g, h, mhalf);
35551 rs6000_emit_madd (dst, g, t, g);
35557 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35558 (Power7) targets. DST is the target, and SRC is the argument operand. */
35561 rs6000_emit_popcount (rtx dst, rtx src)
35563 machine_mode mode = GET_MODE (dst);
35566 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35567 if (TARGET_POPCNTD)
35569 if (mode == SImode)
35570 emit_insn (gen_popcntdsi2 (dst, src));
35572 emit_insn (gen_popcntddi2 (dst, src));
35576 tmp1 = gen_reg_rtx (mode);
35578 if (mode == SImode)
35580 emit_insn (gen_popcntbsi2 (tmp1, src));
35581 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35583 tmp2 = force_reg (SImode, tmp2);
35584 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35588 emit_insn (gen_popcntbdi2 (tmp1, src));
35589 tmp2 = expand_mult (DImode, tmp1,
35590 GEN_INT ((HOST_WIDE_INT)
35591 0x01010101 << 32 | 0x01010101),
35593 tmp2 = force_reg (DImode, tmp2);
35594 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35599 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35600 target, and SRC is the argument operand. */
35603 rs6000_emit_parity (rtx dst, rtx src)
35605 machine_mode mode = GET_MODE (dst);
35608 tmp = gen_reg_rtx (mode);
35610 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35613 if (mode == SImode)
35615 emit_insn (gen_popcntbsi2 (tmp, src));
35616 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35620 emit_insn (gen_popcntbdi2 (tmp, src));
35621 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35626 if (mode == SImode)
35628 /* Is mult+shift >= shift+xor+shift+xor? */
35629 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35631 rtx tmp1, tmp2, tmp3, tmp4;
35633 tmp1 = gen_reg_rtx (SImode);
35634 emit_insn (gen_popcntbsi2 (tmp1, src));
35636 tmp2 = gen_reg_rtx (SImode);
35637 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35638 tmp3 = gen_reg_rtx (SImode);
35639 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35641 tmp4 = gen_reg_rtx (SImode);
35642 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35643 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35646 rs6000_emit_popcount (tmp, src);
35647 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35651 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35652 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35654 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35656 tmp1 = gen_reg_rtx (DImode);
35657 emit_insn (gen_popcntbdi2 (tmp1, src));
35659 tmp2 = gen_reg_rtx (DImode);
35660 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35661 tmp3 = gen_reg_rtx (DImode);
35662 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35664 tmp4 = gen_reg_rtx (DImode);
35665 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35666 tmp5 = gen_reg_rtx (DImode);
35667 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35669 tmp6 = gen_reg_rtx (DImode);
35670 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35671 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35674 rs6000_emit_popcount (tmp, src);
35675 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35679 /* Expand an Altivec constant permutation for little endian mode.
35680 There are two issues: First, the two input operands must be
35681 swapped so that together they form a double-wide array in LE
35682 order. Second, the vperm instruction has surprising behavior
35683 in LE mode: it interprets the elements of the source vectors
35684 in BE mode ("left to right") and interprets the elements of
35685 the destination vector in LE mode ("right to left"). To
35686 correct for this, we must subtract each element of the permute
35687 control vector from 31.
35689 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35690 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35691 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35692 serve as the permute control vector. Then, in BE mode,
35696 places the desired result in vr9. However, in LE mode the
35697 vector contents will be
35699 vr10 = 00000003 00000002 00000001 00000000
35700 vr11 = 00000007 00000006 00000005 00000004
35702 The result of the vperm using the same permute control vector is
35704 vr9 = 05000000 07000000 01000000 03000000
35706 That is, the leftmost 4 bytes of vr10 are interpreted as the
35707 source for the rightmost 4 bytes of vr9, and so on.
35709 If we change the permute control vector to
35711 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35719 vr9 = 00000006 00000004 00000002 00000000. */
35722 altivec_expand_vec_perm_const_le (rtx operands[4])
35726 rtx constv, unspec;
35727 rtx target = operands[0];
35728 rtx op0 = operands[1];
35729 rtx op1 = operands[2];
35730 rtx sel = operands[3];
35732 /* Unpack and adjust the constant selector. */
35733 for (i = 0; i < 16; ++i)
35735 rtx e = XVECEXP (sel, 0, i);
35736 unsigned int elt = 31 - (INTVAL (e) & 31);
35737 perm[i] = GEN_INT (elt);
35740 /* Expand to a permute, swapping the inputs and using the
35741 adjusted selector. */
35743 op0 = force_reg (V16QImode, op0);
35745 op1 = force_reg (V16QImode, op1);
35747 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35748 constv = force_reg (V16QImode, constv);
35749 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35751 if (!REG_P (target))
35753 rtx tmp = gen_reg_rtx (V16QImode);
35754 emit_move_insn (tmp, unspec);
35758 emit_move_insn (target, unspec);
35761 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35762 permute control vector. But here it's not a constant, so we must
35763 generate a vector NAND or NOR to do the adjustment. */
35766 altivec_expand_vec_perm_le (rtx operands[4])
35768 rtx notx, iorx, unspec;
35769 rtx target = operands[0];
35770 rtx op0 = operands[1];
35771 rtx op1 = operands[2];
35772 rtx sel = operands[3];
35774 rtx norreg = gen_reg_rtx (V16QImode);
35775 machine_mode mode = GET_MODE (target);
35777 /* Get everything in regs so the pattern matches. */
35779 op0 = force_reg (mode, op0);
35781 op1 = force_reg (mode, op1);
35783 sel = force_reg (V16QImode, sel);
35784 if (!REG_P (target))
35785 tmp = gen_reg_rtx (mode);
35787 if (TARGET_P9_VECTOR)
35789 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel),
35794 /* Invert the selector with a VNAND if available, else a VNOR.
35795 The VNAND is preferred for future fusion opportunities. */
35796 notx = gen_rtx_NOT (V16QImode, sel);
35797 iorx = (TARGET_P8_VECTOR
35798 ? gen_rtx_IOR (V16QImode, notx, notx)
35799 : gen_rtx_AND (V16QImode, notx, notx));
35800 emit_insn (gen_rtx_SET (norreg, iorx));
35802 /* Permute with operands reversed and adjusted selector. */
35803 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35807 /* Copy into target, possibly by way of a register. */
35808 if (!REG_P (target))
35810 emit_move_insn (tmp, unspec);
35814 emit_move_insn (target, unspec);
35817 /* Expand an Altivec constant permutation. Return true if we match
35818 an efficient implementation; false to fall back to VPERM. */
35821 altivec_expand_vec_perm_const (rtx operands[4])
35823 struct altivec_perm_insn {
35824 HOST_WIDE_INT mask;
35825 enum insn_code impl;
35826 unsigned char perm[16];
35828 static const struct altivec_perm_insn patterns[] = {
35829 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35830 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35831 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35832 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35833 { OPTION_MASK_ALTIVEC,
35834 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35835 : CODE_FOR_altivec_vmrglb_direct),
35836 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35837 { OPTION_MASK_ALTIVEC,
35838 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35839 : CODE_FOR_altivec_vmrglh_direct),
35840 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35841 { OPTION_MASK_ALTIVEC,
35842 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35843 : CODE_FOR_altivec_vmrglw_direct),
35844 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35845 { OPTION_MASK_ALTIVEC,
35846 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35847 : CODE_FOR_altivec_vmrghb_direct),
35848 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35849 { OPTION_MASK_ALTIVEC,
35850 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35851 : CODE_FOR_altivec_vmrghh_direct),
35852 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35853 { OPTION_MASK_ALTIVEC,
35854 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35855 : CODE_FOR_altivec_vmrghw_direct),
35856 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35857 { OPTION_MASK_P8_VECTOR,
35858 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35859 : CODE_FOR_p8_vmrgow_v4sf_direct),
35860 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35861 { OPTION_MASK_P8_VECTOR,
35862 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35863 : CODE_FOR_p8_vmrgew_v4sf_direct),
35864 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35867 unsigned int i, j, elt, which;
35868 unsigned char perm[16];
35869 rtx target, op0, op1, sel, x;
35872 target = operands[0];
35877 /* Unpack the constant selector. */
35878 for (i = which = 0; i < 16; ++i)
35880 rtx e = XVECEXP (sel, 0, i);
35881 elt = INTVAL (e) & 31;
35882 which |= (elt < 16 ? 1 : 2);
35886 /* Simplify the constant selector based on operands. */
35890 gcc_unreachable ();
35894 if (!rtx_equal_p (op0, op1))
35899 for (i = 0; i < 16; ++i)
35911 /* Look for splat patterns. */
35916 for (i = 0; i < 16; ++i)
35917 if (perm[i] != elt)
35921 if (!BYTES_BIG_ENDIAN)
35923 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35929 for (i = 0; i < 16; i += 2)
35930 if (perm[i] != elt || perm[i + 1] != elt + 1)
35934 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35935 x = gen_reg_rtx (V8HImode);
35936 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35938 emit_move_insn (target, gen_lowpart (V16QImode, x));
35945 for (i = 0; i < 16; i += 4)
35947 || perm[i + 1] != elt + 1
35948 || perm[i + 2] != elt + 2
35949 || perm[i + 3] != elt + 3)
35953 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35954 x = gen_reg_rtx (V4SImode);
35955 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35957 emit_move_insn (target, gen_lowpart (V16QImode, x));
35963 /* Look for merge and pack patterns. */
35964 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35968 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35971 elt = patterns[j].perm[0];
35972 if (perm[0] == elt)
35974 else if (perm[0] == elt + 16)
35978 for (i = 1; i < 16; ++i)
35980 elt = patterns[j].perm[i];
35982 elt = (elt >= 16 ? elt - 16 : elt + 16);
35983 else if (one_vec && elt >= 16)
35985 if (perm[i] != elt)
35990 enum insn_code icode = patterns[j].impl;
35991 machine_mode omode = insn_data[icode].operand[0].mode;
35992 machine_mode imode = insn_data[icode].operand[1].mode;
35994 /* For little-endian, don't use vpkuwum and vpkuhum if the
35995 underlying vector type is not V4SI and V8HI, respectively.
35996 For example, using vpkuwum with a V8HI picks up the even
35997 halfwords (BE numbering) when the even halfwords (LE
35998 numbering) are what we need. */
35999 if (!BYTES_BIG_ENDIAN
36000 && icode == CODE_FOR_altivec_vpkuwum_direct
36001 && ((GET_CODE (op0) == REG
36002 && GET_MODE (op0) != V4SImode)
36003 || (GET_CODE (op0) == SUBREG
36004 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
36006 if (!BYTES_BIG_ENDIAN
36007 && icode == CODE_FOR_altivec_vpkuhum_direct
36008 && ((GET_CODE (op0) == REG
36009 && GET_MODE (op0) != V8HImode)
36010 || (GET_CODE (op0) == SUBREG
36011 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
36014 /* For little-endian, the two input operands must be swapped
36015 (or swapped back) to ensure proper right-to-left numbering
36017 if (swapped ^ !BYTES_BIG_ENDIAN)
36018 std::swap (op0, op1);
36019 if (imode != V16QImode)
36021 op0 = gen_lowpart (imode, op0);
36022 op1 = gen_lowpart (imode, op1);
36024 if (omode == V16QImode)
36027 x = gen_reg_rtx (omode);
36028 emit_insn (GEN_FCN (icode) (x, op0, op1));
36029 if (omode != V16QImode)
36030 emit_move_insn (target, gen_lowpart (V16QImode, x));
36035 if (!BYTES_BIG_ENDIAN)
36037 altivec_expand_vec_perm_const_le (operands);
36044 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
36045 Return true if we match an efficient implementation. */
36048 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
36049 unsigned char perm0, unsigned char perm1)
36053 /* If both selectors come from the same operand, fold to single op. */
36054 if ((perm0 & 2) == (perm1 & 2))
36061 /* If both operands are equal, fold to simpler permutation. */
36062 if (rtx_equal_p (op0, op1))
36065 perm1 = (perm1 & 1) + 2;
36067 /* If the first selector comes from the second operand, swap. */
36068 else if (perm0 & 2)
36074 std::swap (op0, op1);
36076 /* If the second selector does not come from the second operand, fail. */
36077 else if ((perm1 & 2) == 0)
36081 if (target != NULL)
36083 machine_mode vmode, dmode;
36086 vmode = GET_MODE (target);
36087 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
36088 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
36089 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
36090 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
36091 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
36092 emit_insn (gen_rtx_SET (target, x));
36098 rs6000_expand_vec_perm_const (rtx operands[4])
36100 rtx target, op0, op1, sel;
36101 unsigned char perm0, perm1;
36103 target = operands[0];
36108 /* Unpack the constant selector. */
36109 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
36110 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
36112 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
36115 /* Test whether a constant permutation is supported. */
36118 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
36120 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
36121 if (TARGET_ALTIVEC)
36124 /* Check for ps_merge* or evmerge* insns. */
36125 if (TARGET_PAIRED_FLOAT && vmode == V2SFmode)
36127 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
36128 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
36129 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
36135 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
36138 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
36139 machine_mode vmode, unsigned nelt, rtx perm[])
36141 machine_mode imode;
36145 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
36146 imode = mode_for_int_vector (vmode).require ();
36148 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
36149 x = expand_vec_perm (vmode, op0, op1, x, target);
36151 emit_move_insn (target, x);
36154 /* Expand an extract even operation. */
36157 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
36159 machine_mode vmode = GET_MODE (target);
36160 unsigned i, nelt = GET_MODE_NUNITS (vmode);
36163 for (i = 0; i < nelt; i++)
36164 perm[i] = GEN_INT (i * 2);
36166 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
36169 /* Expand a vector interleave operation. */
36172 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
36174 machine_mode vmode = GET_MODE (target);
36175 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
36178 high = (highp ? 0 : nelt / 2);
36179 for (i = 0; i < nelt / 2; i++)
36181 perm[i * 2] = GEN_INT (i + high);
36182 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
36185 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
36188 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36190 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
36192 HOST_WIDE_INT hwi_scale (scale);
36193 REAL_VALUE_TYPE r_pow;
36194 rtvec v = rtvec_alloc (2);
36196 rtx scale_vec = gen_reg_rtx (V2DFmode);
36197 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
36198 elt = const_double_from_real_value (r_pow, DFmode);
36199 RTVEC_ELT (v, 0) = elt;
36200 RTVEC_ELT (v, 1) = elt;
36201 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
36202 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
36205 /* Return an RTX representing where to find the function value of a
36206 function returning MODE. */
36208 rs6000_complex_function_value (machine_mode mode)
36210 unsigned int regno;
36212 machine_mode inner = GET_MODE_INNER (mode);
36213 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
36215 if (TARGET_FLOAT128_TYPE
36217 || (mode == TCmode && TARGET_IEEEQUAD)))
36218 regno = ALTIVEC_ARG_RETURN;
36220 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36221 regno = FP_ARG_RETURN;
36225 regno = GP_ARG_RETURN;
36227 /* 32-bit is OK since it'll go in r3/r4. */
36228 if (TARGET_32BIT && inner_bytes >= 4)
36229 return gen_rtx_REG (mode, regno);
36232 if (inner_bytes >= 8)
36233 return gen_rtx_REG (mode, regno);
36235 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
36237 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
36238 GEN_INT (inner_bytes));
36239 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
36242 /* Return an rtx describing a return value of MODE as a PARALLEL
36243 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36244 stride REG_STRIDE. */
36247 rs6000_parallel_return (machine_mode mode,
36248 int n_elts, machine_mode elt_mode,
36249 unsigned int regno, unsigned int reg_stride)
36251 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
36254 for (i = 0; i < n_elts; i++)
36256 rtx r = gen_rtx_REG (elt_mode, regno);
36257 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
36258 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36259 regno += reg_stride;
36265 /* Target hook for TARGET_FUNCTION_VALUE.
36267 An integer value is in r3 and a floating-point value is in fp1,
36268 unless -msoft-float. */
36271 rs6000_function_value (const_tree valtype,
36272 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
36273 bool outgoing ATTRIBUTE_UNUSED)
36276 unsigned int regno;
36277 machine_mode elt_mode;
36280 /* Special handling for structs in darwin64. */
36282 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
36284 CUMULATIVE_ARGS valcum;
36288 valcum.fregno = FP_ARG_MIN_REG;
36289 valcum.vregno = ALTIVEC_ARG_MIN_REG;
36290 /* Do a trial code generation as if this were going to be passed as
36291 an argument; if any part goes in memory, we return NULL. */
36292 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
36295 /* Otherwise fall through to standard ABI rules. */
36298 mode = TYPE_MODE (valtype);
36300 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36301 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
36303 int first_reg, n_regs;
36305 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
36307 /* _Decimal128 must use even/odd register pairs. */
36308 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36309 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
36313 first_reg = ALTIVEC_ARG_RETURN;
36317 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
36320 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36321 if (TARGET_32BIT && TARGET_POWERPC64)
36330 int count = GET_MODE_SIZE (mode) / 4;
36331 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
36334 if ((INTEGRAL_TYPE_P (valtype)
36335 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
36336 || POINTER_TYPE_P (valtype))
36337 mode = TARGET_32BIT ? SImode : DImode;
36339 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36340 /* _Decimal128 must use an even/odd register pair. */
36341 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36342 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36343 && !FLOAT128_VECTOR_P (mode)
36344 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
36345 regno = FP_ARG_RETURN;
36346 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36347 && targetm.calls.split_complex_arg)
36348 return rs6000_complex_function_value (mode);
36349 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36350 return register is used in both cases, and we won't see V2DImode/V2DFmode
36351 for pure altivec, combine the two cases. */
36352 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36353 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36354 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36355 regno = ALTIVEC_ARG_RETURN;
36357 regno = GP_ARG_RETURN;
36359 return gen_rtx_REG (mode, regno);
36362 /* Define how to find the value returned by a library function
36363 assuming the value has mode MODE. */
36365 rs6000_libcall_value (machine_mode mode)
36367 unsigned int regno;
36369 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36370 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36371 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36373 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36374 /* _Decimal128 must use an even/odd register pair. */
36375 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36376 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
36377 && TARGET_HARD_FLOAT
36378 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
36379 regno = FP_ARG_RETURN;
36380 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36381 return register is used in both cases, and we won't see V2DImode/V2DFmode
36382 for pure altivec, combine the two cases. */
36383 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36384 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36385 regno = ALTIVEC_ARG_RETURN;
36386 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36387 return rs6000_complex_function_value (mode);
36389 regno = GP_ARG_RETURN;
36391 return gen_rtx_REG (mode, regno);
36394 /* Compute register pressure classes. We implement the target hook to avoid
36395 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
36396 lead to incorrect estimates of number of available registers and therefor
36397 increased register pressure/spill. */
36399 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36404 pressure_classes[n++] = GENERAL_REGS;
36406 pressure_classes[n++] = VSX_REGS;
36409 if (TARGET_ALTIVEC)
36410 pressure_classes[n++] = ALTIVEC_REGS;
36411 if (TARGET_HARD_FLOAT)
36412 pressure_classes[n++] = FLOAT_REGS;
36414 pressure_classes[n++] = CR_REGS;
36415 pressure_classes[n++] = SPECIAL_REGS;
36420 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36421 Frame pointer elimination is automatically handled.
36423 For the RS/6000, if frame pointer elimination is being done, we would like
36424 to convert ap into fp, not sp.
36426 We need r30 if -mminimal-toc was specified, and there are constant pool
36430 rs6000_can_eliminate (const int from, const int to)
36432 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36433 ? ! frame_pointer_needed
36434 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36435 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36436 || constant_pool_empty_p ()
36440 /* Define the offset between two registers, FROM to be eliminated and its
36441 replacement TO, at the start of a routine. */
36443 rs6000_initial_elimination_offset (int from, int to)
36445 rs6000_stack_t *info = rs6000_stack_info ();
36446 HOST_WIDE_INT offset;
36448 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36449 offset = info->push_p ? 0 : -info->total_size;
36450 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36452 offset = info->push_p ? 0 : -info->total_size;
36453 if (FRAME_GROWS_DOWNWARD)
36454 offset += info->fixed_size + info->vars_size + info->parm_size;
36456 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36457 offset = FRAME_GROWS_DOWNWARD
36458 ? info->fixed_size + info->vars_size + info->parm_size
36460 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36461 offset = info->total_size;
36462 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36463 offset = info->push_p ? info->total_size : 0;
36464 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36467 gcc_unreachable ();
36472 /* Fill in sizes of registers used by unwinder. */
36475 rs6000_init_dwarf_reg_sizes_extra (tree address)
36477 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36480 machine_mode mode = TYPE_MODE (char_type_node);
36481 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36482 rtx mem = gen_rtx_MEM (BLKmode, addr);
36483 rtx value = gen_int_mode (16, mode);
36485 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36486 The unwinder still needs to know the size of Altivec registers. */
36488 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36490 int column = DWARF_REG_TO_UNWIND_COLUMN
36491 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36492 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36494 emit_move_insn (adjust_address (mem, mode, offset), value);
36499 /* Map internal gcc register numbers to debug format register numbers.
36500 FORMAT specifies the type of debug register number to use:
36501 0 -- debug information, except for frame-related sections
36502 1 -- DWARF .debug_frame section
36503 2 -- DWARF .eh_frame section */
36506 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36508 /* Except for the above, we use the internal number for non-DWARF
36509 debug information, and also for .eh_frame. */
36510 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
36513 /* On some platforms, we use the standard DWARF register
36514 numbering for .debug_info and .debug_frame. */
36515 #ifdef RS6000_USE_DWARF_NUMBERING
36518 if (regno == LR_REGNO)
36520 if (regno == CTR_REGNO)
36522 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36523 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36524 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36525 to the DWARF reg for CR. */
36526 if (format == 1 && regno == CR2_REGNO)
36528 if (CR_REGNO_P (regno))
36529 return regno - CR0_REGNO + 86;
36530 if (regno == CA_REGNO)
36531 return 101; /* XER */
36532 if (ALTIVEC_REGNO_P (regno))
36533 return regno - FIRST_ALTIVEC_REGNO + 1124;
36534 if (regno == VRSAVE_REGNO)
36536 if (regno == VSCR_REGNO)
36542 /* target hook eh_return_filter_mode */
36543 static scalar_int_mode
36544 rs6000_eh_return_filter_mode (void)
36546 return TARGET_32BIT ? SImode : word_mode;
36549 /* Target hook for scalar_mode_supported_p. */
36551 rs6000_scalar_mode_supported_p (scalar_mode mode)
36553 /* -m32 does not support TImode. This is the default, from
36554 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36555 same ABI as for -m32. But default_scalar_mode_supported_p allows
36556 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36557 for -mpowerpc64. */
36558 if (TARGET_32BIT && mode == TImode)
36561 if (DECIMAL_FLOAT_MODE_P (mode))
36562 return default_decimal_float_supported_p ();
36563 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36566 return default_scalar_mode_supported_p (mode);
36569 /* Target hook for vector_mode_supported_p. */
36571 rs6000_vector_mode_supported_p (machine_mode mode)
36574 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
36577 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36578 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36580 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36587 /* Target hook for floatn_mode. */
36588 static opt_scalar_float_mode
36589 rs6000_floatn_mode (int n, bool extended)
36599 if (TARGET_FLOAT128_TYPE)
36600 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36602 return opt_scalar_float_mode ();
36605 return opt_scalar_float_mode ();
36608 /* Those are the only valid _FloatNx types. */
36609 gcc_unreachable ();
36623 if (TARGET_FLOAT128_TYPE)
36624 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36626 return opt_scalar_float_mode ();
36629 return opt_scalar_float_mode ();
36635 /* Target hook for c_mode_for_suffix. */
36636 static machine_mode
36637 rs6000_c_mode_for_suffix (char suffix)
36639 if (TARGET_FLOAT128_TYPE)
36641 if (suffix == 'q' || suffix == 'Q')
36642 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36644 /* At the moment, we are not defining a suffix for IBM extended double.
36645 If/when the default for -mabi=ieeelongdouble is changed, and we want
36646 to support __ibm128 constants in legacy library code, we may need to
36647 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36648 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36649 __float80 constants. */
36655 /* Target hook for invalid_arg_for_unprototyped_fn. */
36656 static const char *
36657 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36659 return (!rs6000_darwin64_abi
36661 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36662 && (funcdecl == NULL_TREE
36663 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36664 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36665 ? N_("AltiVec argument passed to unprototyped function")
36669 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36670 setup by using __stack_chk_fail_local hidden function instead of
36671 calling __stack_chk_fail directly. Otherwise it is better to call
36672 __stack_chk_fail directly. */
36674 static tree ATTRIBUTE_UNUSED
36675 rs6000_stack_protect_fail (void)
36677 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36678 ? default_hidden_stack_protect_fail ()
36679 : default_external_stack_protect_fail ();
36682 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36685 static unsigned HOST_WIDE_INT
36686 rs6000_asan_shadow_offset (void)
36688 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36692 /* Mask options that we want to support inside of attribute((target)) and
36693 #pragma GCC target operations. Note, we do not include things like
36694 64/32-bit, endianness, hard/soft floating point, etc. that would have
36695 different calling sequences. */
36697 struct rs6000_opt_mask {
36698 const char *name; /* option name */
36699 HOST_WIDE_INT mask; /* mask to set */
36700 bool invert; /* invert sense of mask */
36701 bool valid_target; /* option is a target option */
36704 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36706 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36707 { "cmpb", OPTION_MASK_CMPB, false, true },
36708 { "crypto", OPTION_MASK_CRYPTO, false, true },
36709 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36710 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36711 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36713 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36714 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36715 { "fprnd", OPTION_MASK_FPRND, false, true },
36716 { "hard-dfp", OPTION_MASK_DFP, false, true },
36717 { "htm", OPTION_MASK_HTM, false, true },
36718 { "isel", OPTION_MASK_ISEL, false, true },
36719 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36720 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36721 { "modulo", OPTION_MASK_MODULO, false, true },
36722 { "mulhw", OPTION_MASK_MULHW, false, true },
36723 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36724 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36725 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36726 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36727 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36728 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36729 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
36730 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36731 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36732 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36733 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36734 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36735 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36736 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36737 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36738 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36739 { "string", OPTION_MASK_STRING, false, true },
36740 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
36741 { "update", OPTION_MASK_NO_UPDATE, true , true },
36742 { "vsx", OPTION_MASK_VSX, false, true },
36743 #ifdef OPTION_MASK_64BIT
36745 { "aix64", OPTION_MASK_64BIT, false, false },
36746 { "aix32", OPTION_MASK_64BIT, true, false },
36748 { "64", OPTION_MASK_64BIT, false, false },
36749 { "32", OPTION_MASK_64BIT, true, false },
36752 #ifdef OPTION_MASK_EABI
36753 { "eabi", OPTION_MASK_EABI, false, false },
36755 #ifdef OPTION_MASK_LITTLE_ENDIAN
36756 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36757 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36759 #ifdef OPTION_MASK_RELOCATABLE
36760 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36762 #ifdef OPTION_MASK_STRICT_ALIGN
36763 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36765 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36766 { "string", OPTION_MASK_STRING, false, false },
36769 /* Builtin mask mapping for printing the flags. */
36770 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36772 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36773 { "vsx", RS6000_BTM_VSX, false, false },
36774 { "paired", RS6000_BTM_PAIRED, false, false },
36775 { "fre", RS6000_BTM_FRE, false, false },
36776 { "fres", RS6000_BTM_FRES, false, false },
36777 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36778 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36779 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36780 { "cell", RS6000_BTM_CELL, false, false },
36781 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36782 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36783 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36784 { "crypto", RS6000_BTM_CRYPTO, false, false },
36785 { "htm", RS6000_BTM_HTM, false, false },
36786 { "hard-dfp", RS6000_BTM_DFP, false, false },
36787 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36788 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36789 { "float128", RS6000_BTM_FLOAT128, false, false },
36790 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36793 /* Option variables that we want to support inside attribute((target)) and
36794 #pragma GCC target operations. */
36796 struct rs6000_opt_var {
36797 const char *name; /* option name */
36798 size_t global_offset; /* offset of the option in global_options. */
36799 size_t target_offset; /* offset of the option in target options. */
36802 static struct rs6000_opt_var const rs6000_opt_vars[] =
36805 offsetof (struct gcc_options, x_TARGET_FRIZ),
36806 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36807 { "avoid-indexed-addresses",
36808 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36809 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36811 offsetof (struct gcc_options, x_rs6000_paired_float),
36812 offsetof (struct cl_target_option, x_rs6000_paired_float), },
36814 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36815 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36816 { "optimize-swaps",
36817 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36818 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36819 { "allow-movmisalign",
36820 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36821 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36823 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36824 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36826 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36827 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36828 { "align-branch-targets",
36829 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36830 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36832 offsetof (struct gcc_options, x_tls_markers),
36833 offsetof (struct cl_target_option, x_tls_markers), },
36835 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36836 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36838 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36839 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36842 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36843 parsing. Return true if there were no errors. */
36846 rs6000_inner_target_options (tree args, bool attr_p)
36850 if (args == NULL_TREE)
36853 else if (TREE_CODE (args) == STRING_CST)
36855 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36858 while ((q = strtok (p, ",")) != NULL)
36860 bool error_p = false;
36861 bool not_valid_p = false;
36862 const char *cpu_opt = NULL;
36865 if (strncmp (q, "cpu=", 4) == 0)
36867 int cpu_index = rs6000_cpu_name_lookup (q+4);
36868 if (cpu_index >= 0)
36869 rs6000_cpu_index = cpu_index;
36876 else if (strncmp (q, "tune=", 5) == 0)
36878 int tune_index = rs6000_cpu_name_lookup (q+5);
36879 if (tune_index >= 0)
36880 rs6000_tune_index = tune_index;
36890 bool invert = false;
36894 if (strncmp (r, "no-", 3) == 0)
36900 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36901 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36903 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36905 if (!rs6000_opt_masks[i].valid_target)
36906 not_valid_p = true;
36910 rs6000_isa_flags_explicit |= mask;
36912 /* VSX needs altivec, so -mvsx automagically sets
36913 altivec and disables -mavoid-indexed-addresses. */
36916 if (mask == OPTION_MASK_VSX)
36918 mask |= OPTION_MASK_ALTIVEC;
36919 TARGET_AVOID_XFORM = 0;
36923 if (rs6000_opt_masks[i].invert)
36927 rs6000_isa_flags &= ~mask;
36929 rs6000_isa_flags |= mask;
36934 if (error_p && !not_valid_p)
36936 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36937 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36939 size_t j = rs6000_opt_vars[i].global_offset;
36940 *((int *) ((char *)&global_options + j)) = !invert;
36942 not_valid_p = false;
36950 const char *eprefix, *esuffix;
36955 eprefix = "__attribute__((__target__(";
36960 eprefix = "#pragma GCC target ";
36965 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36967 else if (not_valid_p)
36968 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36970 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36975 else if (TREE_CODE (args) == TREE_LIST)
36979 tree value = TREE_VALUE (args);
36982 bool ret2 = rs6000_inner_target_options (value, attr_p);
36986 args = TREE_CHAIN (args);
36988 while (args != NULL_TREE);
36993 error ("attribute %<target%> argument not a string");
37000 /* Print out the target options as a list for -mdebug=target. */
37003 rs6000_debug_target_options (tree args, const char *prefix)
37005 if (args == NULL_TREE)
37006 fprintf (stderr, "%s<NULL>", prefix);
37008 else if (TREE_CODE (args) == STRING_CST)
37010 char *p = ASTRDUP (TREE_STRING_POINTER (args));
37013 while ((q = strtok (p, ",")) != NULL)
37016 fprintf (stderr, "%s\"%s\"", prefix, q);
37021 else if (TREE_CODE (args) == TREE_LIST)
37025 tree value = TREE_VALUE (args);
37028 rs6000_debug_target_options (value, prefix);
37031 args = TREE_CHAIN (args);
37033 while (args != NULL_TREE);
37037 gcc_unreachable ();
37043 /* Hook to validate attribute((target("..."))). */
37046 rs6000_valid_attribute_p (tree fndecl,
37047 tree ARG_UNUSED (name),
37051 struct cl_target_option cur_target;
37054 tree new_target, new_optimize;
37055 tree func_optimize;
37057 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
37059 if (TARGET_DEBUG_TARGET)
37061 tree tname = DECL_NAME (fndecl);
37062 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
37064 fprintf (stderr, "function: %.*s\n",
37065 (int) IDENTIFIER_LENGTH (tname),
37066 IDENTIFIER_POINTER (tname));
37068 fprintf (stderr, "function: unknown\n");
37070 fprintf (stderr, "args:");
37071 rs6000_debug_target_options (args, " ");
37072 fprintf (stderr, "\n");
37075 fprintf (stderr, "flags: 0x%x\n", flags);
37077 fprintf (stderr, "--------------------\n");
37080 /* attribute((target("default"))) does nothing, beyond
37081 affecting multi-versioning. */
37082 if (TREE_VALUE (args)
37083 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
37084 && TREE_CHAIN (args) == NULL_TREE
37085 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
37088 old_optimize = build_optimization_node (&global_options);
37089 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
37091 /* If the function changed the optimization levels as well as setting target
37092 options, start with the optimizations specified. */
37093 if (func_optimize && func_optimize != old_optimize)
37094 cl_optimization_restore (&global_options,
37095 TREE_OPTIMIZATION (func_optimize));
37097 /* The target attributes may also change some optimization flags, so update
37098 the optimization options if necessary. */
37099 cl_target_option_save (&cur_target, &global_options);
37100 rs6000_cpu_index = rs6000_tune_index = -1;
37101 ret = rs6000_inner_target_options (args, true);
37103 /* Set up any additional state. */
37106 ret = rs6000_option_override_internal (false);
37107 new_target = build_target_option_node (&global_options);
37112 new_optimize = build_optimization_node (&global_options);
37119 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
37121 if (old_optimize != new_optimize)
37122 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
37125 cl_target_option_restore (&global_options, &cur_target);
37127 if (old_optimize != new_optimize)
37128 cl_optimization_restore (&global_options,
37129 TREE_OPTIMIZATION (old_optimize));
37135 /* Hook to validate the current #pragma GCC target and set the state, and
37136 update the macros based on what was changed. If ARGS is NULL, then
37137 POP_TARGET is used to reset the options. */
37140 rs6000_pragma_target_parse (tree args, tree pop_target)
37142 tree prev_tree = build_target_option_node (&global_options);
37144 struct cl_target_option *prev_opt, *cur_opt;
37145 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
37146 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
37148 if (TARGET_DEBUG_TARGET)
37150 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
37151 fprintf (stderr, "args:");
37152 rs6000_debug_target_options (args, " ");
37153 fprintf (stderr, "\n");
37157 fprintf (stderr, "pop_target:\n");
37158 debug_tree (pop_target);
37161 fprintf (stderr, "pop_target: <NULL>\n");
37163 fprintf (stderr, "--------------------\n");
37168 cur_tree = ((pop_target)
37170 : target_option_default_node);
37171 cl_target_option_restore (&global_options,
37172 TREE_TARGET_OPTION (cur_tree));
37176 rs6000_cpu_index = rs6000_tune_index = -1;
37177 if (!rs6000_inner_target_options (args, false)
37178 || !rs6000_option_override_internal (false)
37179 || (cur_tree = build_target_option_node (&global_options))
37182 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
37183 fprintf (stderr, "invalid pragma\n");
37189 target_option_current_node = cur_tree;
37190 rs6000_activate_target_options (target_option_current_node);
37192 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37193 change the macros that are defined. */
37194 if (rs6000_target_modify_macros_ptr)
37196 prev_opt = TREE_TARGET_OPTION (prev_tree);
37197 prev_bumask = prev_opt->x_rs6000_builtin_mask;
37198 prev_flags = prev_opt->x_rs6000_isa_flags;
37200 cur_opt = TREE_TARGET_OPTION (cur_tree);
37201 cur_flags = cur_opt->x_rs6000_isa_flags;
37202 cur_bumask = cur_opt->x_rs6000_builtin_mask;
37204 diff_bumask = (prev_bumask ^ cur_bumask);
37205 diff_flags = (prev_flags ^ cur_flags);
37207 if ((diff_flags != 0) || (diff_bumask != 0))
37209 /* Delete old macros. */
37210 rs6000_target_modify_macros_ptr (false,
37211 prev_flags & diff_flags,
37212 prev_bumask & diff_bumask);
37214 /* Define new macros. */
37215 rs6000_target_modify_macros_ptr (true,
37216 cur_flags & diff_flags,
37217 cur_bumask & diff_bumask);
37225 /* Remember the last target of rs6000_set_current_function. */
37226 static GTY(()) tree rs6000_previous_fndecl;
37228 /* Restore target's globals from NEW_TREE and invalidate the
37229 rs6000_previous_fndecl cache. */
37232 rs6000_activate_target_options (tree new_tree)
37234 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
37235 if (TREE_TARGET_GLOBALS (new_tree))
37236 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
37237 else if (new_tree == target_option_default_node)
37238 restore_target_globals (&default_target_globals);
37240 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
37241 rs6000_previous_fndecl = NULL_TREE;
37244 /* Establish appropriate back-end context for processing the function
37245 FNDECL. The argument might be NULL to indicate processing at top
37246 level, outside of any function scope. */
37248 rs6000_set_current_function (tree fndecl)
37250 if (TARGET_DEBUG_TARGET)
37252 fprintf (stderr, "\n==================== rs6000_set_current_function");
37255 fprintf (stderr, ", fndecl %s (%p)",
37256 (DECL_NAME (fndecl)
37257 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
37258 : "<unknown>"), (void *)fndecl);
37260 if (rs6000_previous_fndecl)
37261 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
37263 fprintf (stderr, "\n");
37266 /* Only change the context if the function changes. This hook is called
37267 several times in the course of compiling a function, and we don't want to
37268 slow things down too much or call target_reinit when it isn't safe. */
37269 if (fndecl == rs6000_previous_fndecl)
37273 if (rs6000_previous_fndecl == NULL_TREE)
37274 old_tree = target_option_current_node;
37275 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
37276 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
37278 old_tree = target_option_default_node;
37281 if (fndecl == NULL_TREE)
37283 if (old_tree != target_option_current_node)
37284 new_tree = target_option_current_node;
37286 new_tree = NULL_TREE;
37290 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37291 if (new_tree == NULL_TREE)
37292 new_tree = target_option_default_node;
37295 if (TARGET_DEBUG_TARGET)
37299 fprintf (stderr, "\nnew fndecl target specific options:\n");
37300 debug_tree (new_tree);
37305 fprintf (stderr, "\nold fndecl target specific options:\n");
37306 debug_tree (old_tree);
37309 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37310 fprintf (stderr, "--------------------\n");
37313 if (new_tree && old_tree != new_tree)
37314 rs6000_activate_target_options (new_tree);
37317 rs6000_previous_fndecl = fndecl;
37321 /* Save the current options */
37324 rs6000_function_specific_save (struct cl_target_option *ptr,
37325 struct gcc_options *opts)
37327 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37328 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37331 /* Restore the current options */
37334 rs6000_function_specific_restore (struct gcc_options *opts,
37335 struct cl_target_option *ptr)
37338 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37339 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37340 (void) rs6000_option_override_internal (false);
37343 /* Print the current options */
37346 rs6000_function_specific_print (FILE *file, int indent,
37347 struct cl_target_option *ptr)
37349 rs6000_print_isa_options (file, indent, "Isa options set",
37350 ptr->x_rs6000_isa_flags);
37352 rs6000_print_isa_options (file, indent, "Isa options explicit",
37353 ptr->x_rs6000_isa_flags_explicit);
37356 /* Helper function to print the current isa or misc options on a line. */
37359 rs6000_print_options_internal (FILE *file,
37361 const char *string,
37362 HOST_WIDE_INT flags,
37363 const char *prefix,
37364 const struct rs6000_opt_mask *opts,
37365 size_t num_elements)
37368 size_t start_column = 0;
37370 size_t max_column = 120;
37371 size_t prefix_len = strlen (prefix);
37372 size_t comma_len = 0;
37373 const char *comma = "";
37376 start_column += fprintf (file, "%*s", indent, "");
37380 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37384 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37386 /* Print the various mask options. */
37387 cur_column = start_column;
37388 for (i = 0; i < num_elements; i++)
37390 bool invert = opts[i].invert;
37391 const char *name = opts[i].name;
37392 const char *no_str = "";
37393 HOST_WIDE_INT mask = opts[i].mask;
37394 size_t len = comma_len + prefix_len + strlen (name);
37398 if ((flags & mask) == 0)
37401 len += sizeof ("no-") - 1;
37409 if ((flags & mask) != 0)
37412 len += sizeof ("no-") - 1;
37419 if (cur_column > max_column)
37421 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37422 cur_column = start_column + len;
37426 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37428 comma_len = sizeof (", ") - 1;
37431 fputs ("\n", file);
37434 /* Helper function to print the current isa options on a line. */
37437 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37438 HOST_WIDE_INT flags)
37440 rs6000_print_options_internal (file, indent, string, flags, "-m",
37441 &rs6000_opt_masks[0],
37442 ARRAY_SIZE (rs6000_opt_masks));
37446 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37447 HOST_WIDE_INT flags)
37449 rs6000_print_options_internal (file, indent, string, flags, "",
37450 &rs6000_builtin_mask_names[0],
37451 ARRAY_SIZE (rs6000_builtin_mask_names));
37454 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37455 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37456 -mupper-regs-df, etc.).
37458 If the user used -mno-power8-vector, we need to turn off all of the implicit
37459 ISA 2.07 and 3.0 options that relate to the vector unit.
37461 If the user used -mno-power9-vector, we need to turn off all of the implicit
37462 ISA 3.0 options that relate to the vector unit.
37464 This function does not handle explicit options such as the user specifying
37465 -mdirect-move. These are handled in rs6000_option_override_internal, and
37466 the appropriate error is given if needed.
37468 We return a mask of all of the implicit options that should not be enabled
37471 static HOST_WIDE_INT
37472 rs6000_disable_incompatible_switches (void)
37474 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37477 static const struct {
37478 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37479 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37480 const char *const name; /* name of the switch. */
37482 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37483 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37484 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37487 for (i = 0; i < ARRAY_SIZE (flags); i++)
37489 HOST_WIDE_INT no_flag = flags[i].no_flag;
37491 if ((rs6000_isa_flags & no_flag) == 0
37492 && (rs6000_isa_flags_explicit & no_flag) != 0)
37494 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37495 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37501 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37502 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37504 set_flags &= ~rs6000_opt_masks[j].mask;
37505 error ("%<-mno-%s%> turns off %<-m%s%>",
37507 rs6000_opt_masks[j].name);
37510 gcc_assert (!set_flags);
37513 rs6000_isa_flags &= ~dep_flags;
37514 ignore_masks |= no_flag | dep_flags;
37518 return ignore_masks;
37522 /* Helper function for printing the function name when debugging. */
37524 static const char *
37525 get_decl_name (tree fn)
37532 name = DECL_NAME (fn);
37534 return "<no-name>";
37536 return IDENTIFIER_POINTER (name);
37539 /* Return the clone id of the target we are compiling code for in a target
37540 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37541 the priority list for the target clones (ordered from lowest to
37545 rs6000_clone_priority (tree fndecl)
37547 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37548 HOST_WIDE_INT isa_masks;
37549 int ret = CLONE_DEFAULT;
37550 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37551 const char *attrs_str = NULL;
37553 attrs = TREE_VALUE (TREE_VALUE (attrs));
37554 attrs_str = TREE_STRING_POINTER (attrs);
37556 /* Return priority zero for default function. Return the ISA needed for the
37557 function if it is not the default. */
37558 if (strcmp (attrs_str, "default") != 0)
37560 if (fn_opts == NULL_TREE)
37561 fn_opts = target_option_default_node;
37563 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37564 isa_masks = rs6000_isa_flags;
37566 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37568 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37569 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37573 if (TARGET_DEBUG_TARGET)
37574 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37575 get_decl_name (fndecl), ret);
37580 /* This compares the priority of target features in function DECL1 and DECL2.
37581 It returns positive value if DECL1 is higher priority, negative value if
37582 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37583 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37586 rs6000_compare_version_priority (tree decl1, tree decl2)
37588 int priority1 = rs6000_clone_priority (decl1);
37589 int priority2 = rs6000_clone_priority (decl2);
37590 int ret = priority1 - priority2;
37592 if (TARGET_DEBUG_TARGET)
37593 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37594 get_decl_name (decl1), get_decl_name (decl2), ret);
37599 /* Make a dispatcher declaration for the multi-versioned function DECL.
37600 Calls to DECL function will be replaced with calls to the dispatcher
37601 by the front-end. Returns the decl of the dispatcher function. */
37604 rs6000_get_function_versions_dispatcher (void *decl)
37606 tree fn = (tree) decl;
37607 struct cgraph_node *node = NULL;
37608 struct cgraph_node *default_node = NULL;
37609 struct cgraph_function_version_info *node_v = NULL;
37610 struct cgraph_function_version_info *first_v = NULL;
37612 tree dispatch_decl = NULL;
37614 struct cgraph_function_version_info *default_version_info = NULL;
37615 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37617 if (TARGET_DEBUG_TARGET)
37618 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37619 get_decl_name (fn));
37621 node = cgraph_node::get (fn);
37622 gcc_assert (node != NULL);
37624 node_v = node->function_version ();
37625 gcc_assert (node_v != NULL);
37627 if (node_v->dispatcher_resolver != NULL)
37628 return node_v->dispatcher_resolver;
37630 /* Find the default version and make it the first node. */
37632 /* Go to the beginning of the chain. */
37633 while (first_v->prev != NULL)
37634 first_v = first_v->prev;
37636 default_version_info = first_v;
37637 while (default_version_info != NULL)
37639 const tree decl2 = default_version_info->this_node->decl;
37640 if (is_function_default_version (decl2))
37642 default_version_info = default_version_info->next;
37645 /* If there is no default node, just return NULL. */
37646 if (default_version_info == NULL)
37649 /* Make default info the first node. */
37650 if (first_v != default_version_info)
37652 default_version_info->prev->next = default_version_info->next;
37653 if (default_version_info->next)
37654 default_version_info->next->prev = default_version_info->prev;
37655 first_v->prev = default_version_info;
37656 default_version_info->next = first_v;
37657 default_version_info->prev = NULL;
37660 default_node = default_version_info->this_node;
37662 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37663 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37664 "target_clones attribute needs GLIBC (2.23 and newer) that "
37665 "exports hardware capability bits");
37668 if (targetm.has_ifunc_p ())
37670 struct cgraph_function_version_info *it_v = NULL;
37671 struct cgraph_node *dispatcher_node = NULL;
37672 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37674 /* Right now, the dispatching is done via ifunc. */
37675 dispatch_decl = make_dispatcher_decl (default_node->decl);
37677 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37678 gcc_assert (dispatcher_node != NULL);
37679 dispatcher_node->dispatcher_function = 1;
37680 dispatcher_version_info
37681 = dispatcher_node->insert_new_function_version ();
37682 dispatcher_version_info->next = default_version_info;
37683 dispatcher_node->definition = 1;
37685 /* Set the dispatcher for all the versions. */
37686 it_v = default_version_info;
37687 while (it_v != NULL)
37689 it_v->dispatcher_resolver = dispatch_decl;
37695 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37696 "multiversioning needs ifunc which is not supported "
37701 return dispatch_decl;
37704 /* Make the resolver function decl to dispatch the versions of a multi-
37705 versioned function, DEFAULT_DECL. Create an empty basic block in the
37706 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37710 make_resolver_func (const tree default_decl,
37711 const tree dispatch_decl,
37712 basic_block *empty_bb)
37714 /* Make the resolver function static. The resolver function returns
37716 tree decl_name = clone_function_name (default_decl, "resolver");
37717 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37718 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37719 tree decl = build_fn_decl (resolver_name, type);
37720 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37722 DECL_NAME (decl) = decl_name;
37723 TREE_USED (decl) = 1;
37724 DECL_ARTIFICIAL (decl) = 1;
37725 DECL_IGNORED_P (decl) = 0;
37726 TREE_PUBLIC (decl) = 0;
37727 DECL_UNINLINABLE (decl) = 1;
37729 /* Resolver is not external, body is generated. */
37730 DECL_EXTERNAL (decl) = 0;
37731 DECL_EXTERNAL (dispatch_decl) = 0;
37733 DECL_CONTEXT (decl) = NULL_TREE;
37734 DECL_INITIAL (decl) = make_node (BLOCK);
37735 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37737 /* Build result decl and add to function_decl. */
37738 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37739 DECL_ARTIFICIAL (t) = 1;
37740 DECL_IGNORED_P (t) = 1;
37741 DECL_RESULT (decl) = t;
37743 gimplify_function_tree (decl);
37744 push_cfun (DECL_STRUCT_FUNCTION (decl));
37745 *empty_bb = init_lowered_empty_function (decl, false,
37746 profile_count::uninitialized ());
37748 cgraph_node::add_new_function (decl, true);
37749 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37753 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37754 DECL_ATTRIBUTES (dispatch_decl)
37755 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37757 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37762 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37763 return a pointer to VERSION_DECL if we are running on a machine that
37764 supports the index CLONE_ISA hardware architecture bits. This function will
37765 be called during version dispatch to decide which function version to
37766 execute. It returns the basic block at the end, to which more conditions
37770 add_condition_to_bb (tree function_decl, tree version_decl,
37771 int clone_isa, basic_block new_bb)
37773 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37775 gcc_assert (new_bb != NULL);
37776 gimple_seq gseq = bb_seq (new_bb);
37779 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37780 build_fold_addr_expr (version_decl));
37781 tree result_var = create_tmp_var (ptr_type_node);
37782 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37783 gimple *return_stmt = gimple_build_return (result_var);
37785 if (clone_isa == CLONE_DEFAULT)
37787 gimple_seq_add_stmt (&gseq, convert_stmt);
37788 gimple_seq_add_stmt (&gseq, return_stmt);
37789 set_bb_seq (new_bb, gseq);
37790 gimple_set_bb (convert_stmt, new_bb);
37791 gimple_set_bb (return_stmt, new_bb);
37796 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37797 tree cond_var = create_tmp_var (bool_int_type_node);
37798 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37799 const char *arg_str = rs6000_clone_map[clone_isa].name;
37800 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37801 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37802 gimple_call_set_lhs (call_cond_stmt, cond_var);
37804 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37805 gimple_set_bb (call_cond_stmt, new_bb);
37806 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37808 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37809 NULL_TREE, NULL_TREE);
37810 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37811 gimple_set_bb (if_else_stmt, new_bb);
37812 gimple_seq_add_stmt (&gseq, if_else_stmt);
37814 gimple_seq_add_stmt (&gseq, convert_stmt);
37815 gimple_seq_add_stmt (&gseq, return_stmt);
37816 set_bb_seq (new_bb, gseq);
37818 basic_block bb1 = new_bb;
37819 edge e12 = split_block (bb1, if_else_stmt);
37820 basic_block bb2 = e12->dest;
37821 e12->flags &= ~EDGE_FALLTHRU;
37822 e12->flags |= EDGE_TRUE_VALUE;
37824 edge e23 = split_block (bb2, return_stmt);
37825 gimple_set_bb (convert_stmt, bb2);
37826 gimple_set_bb (return_stmt, bb2);
37828 basic_block bb3 = e23->dest;
37829 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37832 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37838 /* This function generates the dispatch function for multi-versioned functions.
37839 DISPATCH_DECL is the function which will contain the dispatch logic.
37840 FNDECLS are the function choices for dispatch, and is a tree chain.
37841 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37842 code is generated. */
37845 dispatch_function_versions (tree dispatch_decl,
37847 basic_block *empty_bb)
37851 vec<tree> *fndecls;
37852 tree clones[CLONE_MAX];
37854 if (TARGET_DEBUG_TARGET)
37855 fputs ("dispatch_function_versions, top\n", stderr);
37857 gcc_assert (dispatch_decl != NULL
37858 && fndecls_p != NULL
37859 && empty_bb != NULL);
37861 /* fndecls_p is actually a vector. */
37862 fndecls = static_cast<vec<tree> *> (fndecls_p);
37864 /* At least one more version other than the default. */
37865 gcc_assert (fndecls->length () >= 2);
37867 /* The first version in the vector is the default decl. */
37868 memset ((void *) clones, '\0', sizeof (clones));
37869 clones[CLONE_DEFAULT] = (*fndecls)[0];
37871 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37872 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37873 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37874 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37875 to insert the code here to do the call. */
37877 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37879 int priority = rs6000_clone_priority (ele);
37880 if (!clones[priority])
37881 clones[priority] = ele;
37884 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37887 if (TARGET_DEBUG_TARGET)
37888 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37889 ix, get_decl_name (clones[ix]));
37891 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37898 /* Generate the dispatching code body to dispatch multi-versioned function
37899 DECL. The target hook is called to process the "target" attributes and
37900 provide the code to dispatch the right function at run-time. NODE points
37901 to the dispatcher decl whose body will be created. */
37904 rs6000_generate_version_dispatcher_body (void *node_p)
37907 basic_block empty_bb;
37908 struct cgraph_node *node = (cgraph_node *) node_p;
37909 struct cgraph_function_version_info *ninfo = node->function_version ();
37911 if (ninfo->dispatcher_resolver)
37912 return ninfo->dispatcher_resolver;
37914 /* node is going to be an alias, so remove the finalized bit. */
37915 node->definition = false;
37917 /* The first version in the chain corresponds to the default version. */
37918 ninfo->dispatcher_resolver = resolver
37919 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37921 if (TARGET_DEBUG_TARGET)
37922 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37923 get_decl_name (resolver));
37925 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37926 auto_vec<tree, 2> fn_ver_vec;
37928 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37930 vinfo = vinfo->next)
37932 struct cgraph_node *version = vinfo->this_node;
37933 /* Check for virtual functions here again, as by this time it should
37934 have been determined if this function needs a vtable index or
37935 not. This happens for methods in derived classes that override
37936 virtual methods in base classes but are not explicitly marked as
37938 if (DECL_VINDEX (version->decl))
37939 sorry ("Virtual function multiversioning not supported");
37941 fn_ver_vec.safe_push (version->decl);
37944 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37945 cgraph_edge::rebuild_edges ();
37951 /* Hook to determine if one function can safely inline another. */
37954 rs6000_can_inline_p (tree caller, tree callee)
37957 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37958 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37960 /* If callee has no option attributes, then it is ok to inline. */
37964 /* If caller has no option attributes, but callee does then it is not ok to
37966 else if (!caller_tree)
37971 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37972 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37974 /* Callee's options should a subset of the caller's, i.e. a vsx function
37975 can inline an altivec function but a non-vsx function can't inline a
37977 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37978 == callee_opts->x_rs6000_isa_flags)
37982 if (TARGET_DEBUG_TARGET)
37983 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37984 get_decl_name (caller), get_decl_name (callee),
37985 (ret ? "can" : "cannot"));
37990 /* Allocate a stack temp and fixup the address so it meets the particular
37991 memory requirements (either offetable or REG+REG addressing). */
37994 rs6000_allocate_stack_temp (machine_mode mode,
37995 bool offsettable_p,
37998 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37999 rtx addr = XEXP (stack, 0);
38000 int strict_p = reload_completed;
38002 if (!legitimate_indirect_address_p (addr, strict_p))
38005 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
38006 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
38008 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
38009 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
38015 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
38016 to such a form to deal with memory reference instructions like STFIWX that
38017 only take reg+reg addressing. */
38020 rs6000_address_for_fpconvert (rtx x)
38024 gcc_assert (MEM_P (x));
38025 addr = XEXP (x, 0);
38026 if (! legitimate_indirect_address_p (addr, reload_completed)
38027 && ! legitimate_indexed_address_p (addr, reload_completed))
38029 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
38031 rtx reg = XEXP (addr, 0);
38032 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
38033 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
38034 gcc_assert (REG_P (reg));
38035 emit_insn (gen_add3_insn (reg, reg, size_rtx));
38038 else if (GET_CODE (addr) == PRE_MODIFY)
38040 rtx reg = XEXP (addr, 0);
38041 rtx expr = XEXP (addr, 1);
38042 gcc_assert (REG_P (reg));
38043 gcc_assert (GET_CODE (expr) == PLUS);
38044 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
38048 x = replace_equiv_address (x, copy_addr_to_reg (addr));
38054 /* Given a memory reference, if it is not in the form for altivec memory
38055 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
38056 convert to the altivec format. */
38059 rs6000_address_for_altivec (rtx x)
38061 gcc_assert (MEM_P (x));
38062 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
38064 rtx addr = XEXP (x, 0);
38066 if (!legitimate_indexed_address_p (addr, reload_completed)
38067 && !legitimate_indirect_address_p (addr, reload_completed))
38068 addr = copy_to_mode_reg (Pmode, addr);
38070 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
38071 x = change_address (x, GET_MODE (x), addr);
38077 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
38079 On the RS/6000, all integer constants are acceptable, most won't be valid
38080 for particular insns, though. Only easy FP constants are acceptable. */
38083 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
38085 if (TARGET_ELF && tls_referenced_p (x))
38088 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
38089 || GET_MODE (x) == VOIDmode
38090 || (TARGET_POWERPC64 && mode == DImode)
38091 || easy_fp_constant (x, mode)
38092 || easy_vector_constant (x, mode));
38096 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
38099 chain_already_loaded (rtx_insn *last)
38101 for (; last != NULL; last = PREV_INSN (last))
38103 if (NONJUMP_INSN_P (last))
38105 rtx patt = PATTERN (last);
38107 if (GET_CODE (patt) == SET)
38109 rtx lhs = XEXP (patt, 0);
38111 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
38119 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38122 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38124 const bool direct_call_p
38125 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
38126 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
38127 rtx toc_load = NULL_RTX;
38128 rtx toc_restore = NULL_RTX;
38130 rtx abi_reg = NULL_RTX;
38135 /* Handle longcall attributes. */
38136 if (INTVAL (cookie) & CALL_LONG)
38137 func_desc = rs6000_longcall_ref (func_desc);
38139 /* Handle indirect calls. */
38140 if (GET_CODE (func_desc) != SYMBOL_REF
38141 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
38143 /* Save the TOC into its reserved slot before the call,
38144 and prepare to restore it after the call. */
38145 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
38146 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
38147 rtx stack_toc_mem = gen_frame_mem (Pmode,
38148 gen_rtx_PLUS (Pmode, stack_ptr,
38149 stack_toc_offset));
38150 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
38151 gen_rtvec (1, stack_toc_offset),
38153 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
38155 /* Can we optimize saving the TOC in the prologue or
38156 do we need to do it at every call? */
38157 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
38158 cfun->machine->save_toc_in_prologue = true;
38161 MEM_VOLATILE_P (stack_toc_mem) = 1;
38162 emit_move_insn (stack_toc_mem, toc_reg);
38165 if (DEFAULT_ABI == ABI_ELFv2)
38167 /* A function pointer in the ELFv2 ABI is just a plain address, but
38168 the ABI requires it to be loaded into r12 before the call. */
38169 func_addr = gen_rtx_REG (Pmode, 12);
38170 emit_move_insn (func_addr, func_desc);
38171 abi_reg = func_addr;
38175 /* A function pointer under AIX is a pointer to a data area whose
38176 first word contains the actual address of the function, whose
38177 second word contains a pointer to its TOC, and whose third word
38178 contains a value to place in the static chain register (r11).
38179 Note that if we load the static chain, our "trampoline" need
38180 not have any executable code. */
38182 /* Load up address of the actual function. */
38183 func_desc = force_reg (Pmode, func_desc);
38184 func_addr = gen_reg_rtx (Pmode);
38185 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
38187 /* Prepare to load the TOC of the called function. Note that the
38188 TOC load must happen immediately before the actual call so
38189 that unwinding the TOC registers works correctly. See the
38190 comment in frob_update_context. */
38191 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
38192 rtx func_toc_mem = gen_rtx_MEM (Pmode,
38193 gen_rtx_PLUS (Pmode, func_desc,
38195 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
38197 /* If we have a static chain, load it up. But, if the call was
38198 originally direct, the 3rd word has not been written since no
38199 trampoline has been built, so we ought not to load it, lest we
38200 override a static chain value. */
38202 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38203 && !chain_already_loaded (get_current_sequence ()->next->last))
38205 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
38206 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
38207 rtx func_sc_mem = gen_rtx_MEM (Pmode,
38208 gen_rtx_PLUS (Pmode, func_desc,
38210 emit_move_insn (sc_reg, func_sc_mem);
38217 /* Direct calls use the TOC: for local calls, the callee will
38218 assume the TOC register is set; for non-local calls, the
38219 PLT stub needs the TOC register. */
38221 func_addr = func_desc;
38224 /* Create the call. */
38225 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
38226 if (value != NULL_RTX)
38227 call[0] = gen_rtx_SET (value, call[0]);
38231 call[n_call++] = toc_load;
38233 call[n_call++] = toc_restore;
38235 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
38237 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
38238 insn = emit_call_insn (insn);
38240 /* Mention all registers defined by the ABI to hold information
38241 as uses in CALL_INSN_FUNCTION_USAGE. */
38243 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38246 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38249 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38254 gcc_assert (INTVAL (cookie) == 0);
38256 /* Create the call. */
38257 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
38258 if (value != NULL_RTX)
38259 call[0] = gen_rtx_SET (value, call[0]);
38261 call[1] = simple_return_rtx;
38263 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
38264 insn = emit_call_insn (insn);
38266 /* Note use of the TOC register. */
38267 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
38270 /* Return whether we need to always update the saved TOC pointer when we update
38271 the stack pointer. */
38274 rs6000_save_toc_in_prologue_p (void)
38276 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38279 #ifdef HAVE_GAS_HIDDEN
38280 # define USE_HIDDEN_LINKONCE 1
38282 # define USE_HIDDEN_LINKONCE 0
38285 /* Fills in the label name that should be used for a 476 link stack thunk. */
38288 get_ppc476_thunk_name (char name[32])
38290 gcc_assert (TARGET_LINK_STACK);
38292 if (USE_HIDDEN_LINKONCE)
38293 sprintf (name, "__ppc476.get_thunk");
38295 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38298 /* This function emits the simple thunk routine that is used to preserve
38299 the link stack on the 476 cpu. */
38301 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38303 rs6000_code_end (void)
38308 if (!TARGET_LINK_STACK)
38311 get_ppc476_thunk_name (name);
38313 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38314 build_function_type_list (void_type_node, NULL_TREE));
38315 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38316 NULL_TREE, void_type_node);
38317 TREE_PUBLIC (decl) = 1;
38318 TREE_STATIC (decl) = 1;
38321 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38323 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38324 targetm.asm_out.unique_section (decl, 0);
38325 switch_to_section (get_named_section (decl, NULL, 0));
38326 DECL_WEAK (decl) = 1;
38327 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38328 targetm.asm_out.globalize_label (asm_out_file, name);
38329 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38330 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38335 switch_to_section (text_section);
38336 ASM_OUTPUT_LABEL (asm_out_file, name);
38339 DECL_INITIAL (decl) = make_node (BLOCK);
38340 current_function_decl = decl;
38341 allocate_struct_function (decl, false);
38342 init_function_start (decl);
38343 first_function_block_is_cold = false;
38344 /* Make sure unwind info is emitted for the thunk if needed. */
38345 final_start_function (emit_barrier (), asm_out_file, 1);
38347 fputs ("\tblr\n", asm_out_file);
38349 final_end_function ();
38350 init_insn_lengths ();
38351 free_after_compilation (cfun);
38353 current_function_decl = NULL;
38356 /* Add r30 to hard reg set if the prologue sets it up and it is not
38357 pic_offset_table_rtx. */
38360 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38362 if (!TARGET_SINGLE_PIC_BASE
38364 && TARGET_MINIMAL_TOC
38365 && !constant_pool_empty_p ())
38366 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38367 if (cfun->machine->split_stack_argp_used)
38368 add_to_hard_reg_set (&set->set, Pmode, 12);
38370 /* Make sure the hard reg set doesn't include r2, which was possibly added
38371 via PIC_OFFSET_TABLE_REGNUM. */
38373 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38377 /* Helper function for rs6000_split_logical to emit a logical instruction after
38378 spliting the operation to single GPR registers.
38380 DEST is the destination register.
38381 OP1 and OP2 are the input source registers.
38382 CODE is the base operation (AND, IOR, XOR, NOT).
38383 MODE is the machine mode.
38384 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38385 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38386 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38389 rs6000_split_logical_inner (rtx dest,
38392 enum rtx_code code,
38394 bool complement_final_p,
38395 bool complement_op1_p,
38396 bool complement_op2_p)
38400 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38401 if (op2 && GET_CODE (op2) == CONST_INT
38402 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38403 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38405 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38406 HOST_WIDE_INT value = INTVAL (op2) & mask;
38408 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38413 emit_insn (gen_rtx_SET (dest, const0_rtx));
38417 else if (value == mask)
38419 if (!rtx_equal_p (dest, op1))
38420 emit_insn (gen_rtx_SET (dest, op1));
38425 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38426 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38427 else if (code == IOR || code == XOR)
38431 if (!rtx_equal_p (dest, op1))
38432 emit_insn (gen_rtx_SET (dest, op1));
38438 if (code == AND && mode == SImode
38439 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38441 emit_insn (gen_andsi3 (dest, op1, op2));
38445 if (complement_op1_p)
38446 op1 = gen_rtx_NOT (mode, op1);
38448 if (complement_op2_p)
38449 op2 = gen_rtx_NOT (mode, op2);
38451 /* For canonical RTL, if only one arm is inverted it is the first. */
38452 if (!complement_op1_p && complement_op2_p)
38453 std::swap (op1, op2);
38455 bool_rtx = ((code == NOT)
38456 ? gen_rtx_NOT (mode, op1)
38457 : gen_rtx_fmt_ee (code, mode, op1, op2));
38459 if (complement_final_p)
38460 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38462 emit_insn (gen_rtx_SET (dest, bool_rtx));
38465 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38466 operations are split immediately during RTL generation to allow for more
38467 optimizations of the AND/IOR/XOR.
38469 OPERANDS is an array containing the destination and two input operands.
38470 CODE is the base operation (AND, IOR, XOR, NOT).
38471 MODE is the machine mode.
38472 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38473 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38474 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38475 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38476 formation of the AND instructions. */
38479 rs6000_split_logical_di (rtx operands[3],
38480 enum rtx_code code,
38481 bool complement_final_p,
38482 bool complement_op1_p,
38483 bool complement_op2_p)
38485 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38486 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38487 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38488 enum hi_lo { hi = 0, lo = 1 };
38489 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38492 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38493 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38494 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38495 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38498 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38501 if (GET_CODE (operands[2]) != CONST_INT)
38503 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38504 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38508 HOST_WIDE_INT value = INTVAL (operands[2]);
38509 HOST_WIDE_INT value_hi_lo[2];
38511 gcc_assert (!complement_final_p);
38512 gcc_assert (!complement_op1_p);
38513 gcc_assert (!complement_op2_p);
38515 value_hi_lo[hi] = value >> 32;
38516 value_hi_lo[lo] = value & lower_32bits;
38518 for (i = 0; i < 2; i++)
38520 HOST_WIDE_INT sub_value = value_hi_lo[i];
38522 if (sub_value & sign_bit)
38523 sub_value |= upper_32bits;
38525 op2_hi_lo[i] = GEN_INT (sub_value);
38527 /* If this is an AND instruction, check to see if we need to load
38528 the value in a register. */
38529 if (code == AND && sub_value != -1 && sub_value != 0
38530 && !and_operand (op2_hi_lo[i], SImode))
38531 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38536 for (i = 0; i < 2; i++)
38538 /* Split large IOR/XOR operations. */
38539 if ((code == IOR || code == XOR)
38540 && GET_CODE (op2_hi_lo[i]) == CONST_INT
38541 && !complement_final_p
38542 && !complement_op1_p
38543 && !complement_op2_p
38544 && !logical_const_operand (op2_hi_lo[i], SImode))
38546 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38547 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38548 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38549 rtx tmp = gen_reg_rtx (SImode);
38551 /* Make sure the constant is sign extended. */
38552 if ((hi_16bits & sign_bit) != 0)
38553 hi_16bits |= upper_32bits;
38555 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38556 code, SImode, false, false, false);
38558 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38559 code, SImode, false, false, false);
38562 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38563 code, SImode, complement_final_p,
38564 complement_op1_p, complement_op2_p);
38570 /* Split the insns that make up boolean operations operating on multiple GPR
38571 registers. The boolean MD patterns ensure that the inputs either are
38572 exactly the same as the output registers, or there is no overlap.
38574 OPERANDS is an array containing the destination and two input operands.
38575 CODE is the base operation (AND, IOR, XOR, NOT).
38576 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38577 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38578 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38581 rs6000_split_logical (rtx operands[3],
38582 enum rtx_code code,
38583 bool complement_final_p,
38584 bool complement_op1_p,
38585 bool complement_op2_p)
38587 machine_mode mode = GET_MODE (operands[0]);
38588 machine_mode sub_mode;
38590 int sub_size, regno0, regno1, nregs, i;
38592 /* If this is DImode, use the specialized version that can run before
38593 register allocation. */
38594 if (mode == DImode && !TARGET_POWERPC64)
38596 rs6000_split_logical_di (operands, code, complement_final_p,
38597 complement_op1_p, complement_op2_p);
38603 op2 = (code == NOT) ? NULL_RTX : operands[2];
38604 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38605 sub_size = GET_MODE_SIZE (sub_mode);
38606 regno0 = REGNO (op0);
38607 regno1 = REGNO (op1);
38609 gcc_assert (reload_completed);
38610 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38611 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38613 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38614 gcc_assert (nregs > 1);
38616 if (op2 && REG_P (op2))
38617 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38619 for (i = 0; i < nregs; i++)
38621 int offset = i * sub_size;
38622 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38623 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38624 rtx sub_op2 = ((code == NOT)
38626 : simplify_subreg (sub_mode, op2, mode, offset));
38628 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38629 complement_final_p, complement_op1_p,
38637 /* Return true if the peephole2 can combine a load involving a combination of
38638 an addis instruction and a load with an offset that can be fused together on
38642 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38643 rtx addis_value, /* addis value. */
38644 rtx target, /* target register that is loaded. */
38645 rtx mem) /* bottom part of the memory addr. */
38650 /* Validate arguments. */
38651 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38654 if (!base_reg_operand (target, GET_MODE (target)))
38657 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38660 /* Allow sign/zero extension. */
38661 if (GET_CODE (mem) == ZERO_EXTEND
38662 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38663 mem = XEXP (mem, 0);
38668 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38671 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38672 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38675 /* Validate that the register used to load the high value is either the
38676 register being loaded, or we can safely replace its use.
38678 This function is only called from the peephole2 pass and we assume that
38679 there are 2 instructions in the peephole (addis and load), so we want to
38680 check if the target register was not used in the memory address and the
38681 register to hold the addis result is dead after the peephole. */
38682 if (REGNO (addis_reg) != REGNO (target))
38684 if (reg_mentioned_p (target, mem))
38687 if (!peep2_reg_dead_p (2, addis_reg))
38690 /* If the target register being loaded is the stack pointer, we must
38691 avoid loading any other value into it, even temporarily. */
38692 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38696 base_reg = XEXP (addr, 0);
38697 return REGNO (addis_reg) == REGNO (base_reg);
38700 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38701 sequence. We adjust the addis register to use the target register. If the
38702 load sign extends, we adjust the code to do the zero extending load, and an
38703 explicit sign extension later since the fusion only covers zero extending
38707 operands[0] register set with addis (to be replaced with target)
38708 operands[1] value set via addis
38709 operands[2] target register being loaded
38710 operands[3] D-form memory reference using operands[0]. */
38713 expand_fusion_gpr_load (rtx *operands)
38715 rtx addis_value = operands[1];
38716 rtx target = operands[2];
38717 rtx orig_mem = operands[3];
38718 rtx new_addr, new_mem, orig_addr, offset;
38719 enum rtx_code plus_or_lo_sum;
38720 machine_mode target_mode = GET_MODE (target);
38721 machine_mode extend_mode = target_mode;
38722 machine_mode ptr_mode = Pmode;
38723 enum rtx_code extend = UNKNOWN;
38725 if (GET_CODE (orig_mem) == ZERO_EXTEND
38726 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38728 extend = GET_CODE (orig_mem);
38729 orig_mem = XEXP (orig_mem, 0);
38730 target_mode = GET_MODE (orig_mem);
38733 gcc_assert (MEM_P (orig_mem));
38735 orig_addr = XEXP (orig_mem, 0);
38736 plus_or_lo_sum = GET_CODE (orig_addr);
38737 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38739 offset = XEXP (orig_addr, 1);
38740 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38741 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38743 if (extend != UNKNOWN)
38744 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38746 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38747 UNSPEC_FUSION_GPR);
38748 emit_insn (gen_rtx_SET (target, new_mem));
38750 if (extend == SIGN_EXTEND)
38752 int sub_off = ((BYTES_BIG_ENDIAN)
38753 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38756 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38758 emit_insn (gen_rtx_SET (target,
38759 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38765 /* Emit the addis instruction that will be part of a fused instruction
38769 emit_fusion_addis (rtx target, rtx addis_value, const char *comment,
38770 const char *mode_name)
38773 char insn_template[80];
38774 const char *addis_str = NULL;
38775 const char *comment_str = ASM_COMMENT_START;
38777 if (*comment_str == ' ')
38780 /* Emit the addis instruction. */
38781 fuse_ops[0] = target;
38782 if (satisfies_constraint_L (addis_value))
38784 fuse_ops[1] = addis_value;
38785 addis_str = "lis %0,%v1";
38788 else if (GET_CODE (addis_value) == PLUS)
38790 rtx op0 = XEXP (addis_value, 0);
38791 rtx op1 = XEXP (addis_value, 1);
38793 if (REG_P (op0) && CONST_INT_P (op1)
38794 && satisfies_constraint_L (op1))
38798 addis_str = "addis %0,%1,%v2";
38802 else if (GET_CODE (addis_value) == HIGH)
38804 rtx value = XEXP (addis_value, 0);
38805 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38807 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38808 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38810 addis_str = "addis %0,%2,%1@toc@ha";
38812 else if (TARGET_XCOFF)
38813 addis_str = "addis %0,%1@u(%2)";
38816 gcc_unreachable ();
38819 else if (GET_CODE (value) == PLUS)
38821 rtx op0 = XEXP (value, 0);
38822 rtx op1 = XEXP (value, 1);
38824 if (GET_CODE (op0) == UNSPEC
38825 && XINT (op0, 1) == UNSPEC_TOCREL
38826 && CONST_INT_P (op1))
38828 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38829 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38832 addis_str = "addis %0,%2,%1+%3@toc@ha";
38834 else if (TARGET_XCOFF)
38835 addis_str = "addis %0,%1+%3@u(%2)";
38838 gcc_unreachable ();
38842 else if (satisfies_constraint_L (value))
38844 fuse_ops[1] = value;
38845 addis_str = "lis %0,%v1";
38848 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38850 fuse_ops[1] = value;
38851 addis_str = "lis %0,%1@ha";
38856 fatal_insn ("Could not generate addis value for fusion", addis_value);
38858 sprintf (insn_template, "%s\t\t%s %s, type %s", addis_str, comment_str,
38859 comment, mode_name);
38860 output_asm_insn (insn_template, fuse_ops);
38863 /* Emit a D-form load or store instruction that is the second instruction
38864 of a fusion sequence. */
38867 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
38868 const char *insn_str)
38871 char insn_template[80];
38873 fuse_ops[0] = load_store_reg;
38874 fuse_ops[1] = addis_reg;
38876 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38878 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38879 fuse_ops[2] = offset;
38880 output_asm_insn (insn_template, fuse_ops);
38883 else if (GET_CODE (offset) == UNSPEC
38884 && XINT (offset, 1) == UNSPEC_TOCREL)
38887 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38889 else if (TARGET_XCOFF)
38890 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38893 gcc_unreachable ();
38895 fuse_ops[2] = XVECEXP (offset, 0, 0);
38896 output_asm_insn (insn_template, fuse_ops);
38899 else if (GET_CODE (offset) == PLUS
38900 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38901 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38902 && CONST_INT_P (XEXP (offset, 1)))
38904 rtx tocrel_unspec = XEXP (offset, 0);
38906 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38908 else if (TARGET_XCOFF)
38909 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38912 gcc_unreachable ();
38914 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38915 fuse_ops[3] = XEXP (offset, 1);
38916 output_asm_insn (insn_template, fuse_ops);
38919 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38921 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38923 fuse_ops[2] = offset;
38924 output_asm_insn (insn_template, fuse_ops);
38928 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38933 /* Wrap a TOC address that can be fused to indicate that special fusion
38934 processing is needed. */
38937 fusion_wrap_memory_address (rtx old_mem)
38939 rtx old_addr = XEXP (old_mem, 0);
38940 rtvec v = gen_rtvec (1, old_addr);
38941 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38942 return replace_equiv_address_nv (old_mem, new_addr, false);
38945 /* Given an address, convert it into the addis and load offset parts. Addresses
38946 created during the peephole2 process look like:
38947 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38948 (unspec [(...)] UNSPEC_TOCREL))
38950 Addresses created via toc fusion look like:
38951 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38954 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38958 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38960 lo = XVECEXP (addr, 0, 0);
38961 hi = gen_rtx_HIGH (Pmode, lo);
38963 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38965 hi = XEXP (addr, 0);
38966 lo = XEXP (addr, 1);
38969 gcc_unreachable ();
38975 /* Return a string to fuse an addis instruction with a gpr load to the same
38976 register that we loaded up the addis instruction. The address that is used
38977 is the logical address that was formed during peephole2:
38978 (lo_sum (high) (low-part))
38980 Or the address is the TOC address that is wrapped before register allocation:
38981 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38983 The code is complicated, so we call output_asm_insn directly, and just
38987 emit_fusion_gpr_load (rtx target, rtx mem)
38992 const char *load_str = NULL;
38993 const char *mode_name = NULL;
38996 if (GET_CODE (mem) == ZERO_EXTEND)
38997 mem = XEXP (mem, 0);
38999 gcc_assert (REG_P (target) && MEM_P (mem));
39001 addr = XEXP (mem, 0);
39002 fusion_split_address (addr, &addis_value, &load_offset);
39004 /* Now emit the load instruction to the same register. */
39005 mode = GET_MODE (mem);
39009 mode_name = "char";
39014 mode_name = "short";
39020 mode_name = (mode == SFmode) ? "float" : "int";
39026 gcc_assert (TARGET_POWERPC64);
39027 mode_name = (mode == DFmode) ? "double" : "long";
39032 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
39035 /* Emit the addis instruction. */
39036 emit_fusion_addis (target, addis_value, "gpr load fusion", mode_name);
39038 /* Emit the D-form load instruction. */
39039 emit_fusion_load_store (target, target, load_offset, load_str);
39045 /* Return true if the peephole2 can combine a load/store involving a
39046 combination of an addis instruction and the memory operation. This was
39047 added to the ISA 3.0 (power9) hardware. */
39050 fusion_p9_p (rtx addis_reg, /* register set via addis. */
39051 rtx addis_value, /* addis value. */
39052 rtx dest, /* destination (memory or register). */
39053 rtx src) /* source (register or memory). */
39055 rtx addr, mem, offset;
39056 machine_mode mode = GET_MODE (src);
39058 /* Validate arguments. */
39059 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
39062 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
39065 /* Ignore extend operations that are part of the load. */
39066 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
39067 src = XEXP (src, 0);
39069 /* Test for memory<-register or register<-memory. */
39070 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
39078 else if (MEM_P (src))
39080 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
39089 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
39090 if (GET_CODE (addr) == PLUS)
39092 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39095 return satisfies_constraint_I (XEXP (addr, 1));
39098 else if (GET_CODE (addr) == LO_SUM)
39100 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39103 offset = XEXP (addr, 1);
39104 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
39105 return small_toc_ref (offset, GET_MODE (offset));
39107 else if (TARGET_ELF && !TARGET_POWERPC64)
39108 return CONSTANT_P (offset);
39114 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39118 operands[0] register set with addis
39119 operands[1] value set via addis
39120 operands[2] target register being loaded
39121 operands[3] D-form memory reference using operands[0].
39123 This is similar to the fusion introduced with power8, except it scales to
39124 both loads/stores and does not require the result register to be the same as
39125 the base register. At the moment, we only do this if register set with addis
39129 expand_fusion_p9_load (rtx *operands)
39131 rtx tmp_reg = operands[0];
39132 rtx addis_value = operands[1];
39133 rtx target = operands[2];
39134 rtx orig_mem = operands[3];
39135 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
39136 enum rtx_code plus_or_lo_sum;
39137 machine_mode target_mode = GET_MODE (target);
39138 machine_mode extend_mode = target_mode;
39139 machine_mode ptr_mode = Pmode;
39140 enum rtx_code extend = UNKNOWN;
39142 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
39144 extend = GET_CODE (orig_mem);
39145 orig_mem = XEXP (orig_mem, 0);
39146 target_mode = GET_MODE (orig_mem);
39149 gcc_assert (MEM_P (orig_mem));
39151 orig_addr = XEXP (orig_mem, 0);
39152 plus_or_lo_sum = GET_CODE (orig_addr);
39153 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39155 offset = XEXP (orig_addr, 1);
39156 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39157 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39159 if (extend != UNKNOWN)
39160 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
39162 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
39165 set = gen_rtx_SET (target, new_mem);
39166 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39167 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39173 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39177 operands[0] register set with addis
39178 operands[1] value set via addis
39179 operands[2] target D-form memory being stored to
39180 operands[3] register being stored
39182 This is similar to the fusion introduced with power8, except it scales to
39183 both loads/stores and does not require the result register to be the same as
39184 the base register. At the moment, we only do this if register set with addis
39188 expand_fusion_p9_store (rtx *operands)
39190 rtx tmp_reg = operands[0];
39191 rtx addis_value = operands[1];
39192 rtx orig_mem = operands[2];
39193 rtx src = operands[3];
39194 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
39195 enum rtx_code plus_or_lo_sum;
39196 machine_mode target_mode = GET_MODE (orig_mem);
39197 machine_mode ptr_mode = Pmode;
39199 gcc_assert (MEM_P (orig_mem));
39201 orig_addr = XEXP (orig_mem, 0);
39202 plus_or_lo_sum = GET_CODE (orig_addr);
39203 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39205 offset = XEXP (orig_addr, 1);
39206 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39207 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39209 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
39212 set = gen_rtx_SET (new_mem, new_src);
39213 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39214 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39220 /* Return a string to fuse an addis instruction with a load using extended
39221 fusion. The address that is used is the logical address that was formed
39222 during peephole2: (lo_sum (high) (low-part))
39224 The code is complicated, so we call output_asm_insn directly, and just
39228 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
39230 machine_mode mode = GET_MODE (reg);
39234 const char *load_string;
39237 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
39239 mem = XEXP (mem, 0);
39240 mode = GET_MODE (mem);
39243 if (GET_CODE (reg) == SUBREG)
39245 gcc_assert (SUBREG_BYTE (reg) == 0);
39246 reg = SUBREG_REG (reg);
39250 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
39253 if (FP_REGNO_P (r))
39255 if (mode == SFmode)
39256 load_string = "lfs";
39257 else if (mode == DFmode || mode == DImode)
39258 load_string = "lfd";
39260 gcc_unreachable ();
39262 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39264 if (mode == SFmode)
39265 load_string = "lxssp";
39266 else if (mode == DFmode || mode == DImode)
39267 load_string = "lxsd";
39269 gcc_unreachable ();
39271 else if (INT_REGNO_P (r))
39276 load_string = "lbz";
39279 load_string = "lhz";
39283 load_string = "lwz";
39287 if (!TARGET_POWERPC64)
39288 gcc_unreachable ();
39289 load_string = "ld";
39292 gcc_unreachable ();
39296 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
39299 fatal_insn ("emit_fusion_p9_load not MEM", mem);
39301 addr = XEXP (mem, 0);
39302 fusion_split_address (addr, &hi, &lo);
39304 /* Emit the addis instruction. */
39305 emit_fusion_addis (tmp_reg, hi, "power9 load fusion", GET_MODE_NAME (mode));
39307 /* Emit the D-form load instruction. */
39308 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
39313 /* Return a string to fuse an addis instruction with a store using extended
39314 fusion. The address that is used is the logical address that was formed
39315 during peephole2: (lo_sum (high) (low-part))
39317 The code is complicated, so we call output_asm_insn directly, and just
39321 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
39323 machine_mode mode = GET_MODE (reg);
39327 const char *store_string;
39330 if (GET_CODE (reg) == SUBREG)
39332 gcc_assert (SUBREG_BYTE (reg) == 0);
39333 reg = SUBREG_REG (reg);
39337 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
39340 if (FP_REGNO_P (r))
39342 if (mode == SFmode)
39343 store_string = "stfs";
39344 else if (mode == DFmode)
39345 store_string = "stfd";
39347 gcc_unreachable ();
39349 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39351 if (mode == SFmode)
39352 store_string = "stxssp";
39353 else if (mode == DFmode || mode == DImode)
39354 store_string = "stxsd";
39356 gcc_unreachable ();
39358 else if (INT_REGNO_P (r))
39363 store_string = "stb";
39366 store_string = "sth";
39370 store_string = "stw";
39374 if (!TARGET_POWERPC64)
39375 gcc_unreachable ();
39376 store_string = "std";
39379 gcc_unreachable ();
39383 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
39386 fatal_insn ("emit_fusion_p9_store not MEM", mem);
39388 addr = XEXP (mem, 0);
39389 fusion_split_address (addr, &hi, &lo);
39391 /* Emit the addis instruction. */
39392 emit_fusion_addis (tmp_reg, hi, "power9 store fusion", GET_MODE_NAME (mode));
39394 /* Emit the D-form load instruction. */
39395 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
39400 #ifdef RS6000_GLIBC_ATOMIC_FENV
39401 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39402 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39405 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39408 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39410 if (!TARGET_HARD_FLOAT)
39412 #ifdef RS6000_GLIBC_ATOMIC_FENV
39413 if (atomic_hold_decl == NULL_TREE)
39416 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39417 get_identifier ("__atomic_feholdexcept"),
39418 build_function_type_list (void_type_node,
39419 double_ptr_type_node,
39421 TREE_PUBLIC (atomic_hold_decl) = 1;
39422 DECL_EXTERNAL (atomic_hold_decl) = 1;
39425 if (atomic_clear_decl == NULL_TREE)
39428 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39429 get_identifier ("__atomic_feclearexcept"),
39430 build_function_type_list (void_type_node,
39432 TREE_PUBLIC (atomic_clear_decl) = 1;
39433 DECL_EXTERNAL (atomic_clear_decl) = 1;
39436 tree const_double = build_qualified_type (double_type_node,
39438 tree const_double_ptr = build_pointer_type (const_double);
39439 if (atomic_update_decl == NULL_TREE)
39442 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39443 get_identifier ("__atomic_feupdateenv"),
39444 build_function_type_list (void_type_node,
39447 TREE_PUBLIC (atomic_update_decl) = 1;
39448 DECL_EXTERNAL (atomic_update_decl) = 1;
39451 tree fenv_var = create_tmp_var_raw (double_type_node);
39452 TREE_ADDRESSABLE (fenv_var) = 1;
39453 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39455 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39456 *clear = build_call_expr (atomic_clear_decl, 0);
39457 *update = build_call_expr (atomic_update_decl, 1,
39458 fold_convert (const_double_ptr, fenv_addr));
39463 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39464 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39465 tree call_mffs = build_call_expr (mffs, 0);
39467 /* Generates the equivalent of feholdexcept (&fenv_var)
39469 *fenv_var = __builtin_mffs ();
39471 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39472 __builtin_mtfsf (0xff, fenv_hold); */
39474 /* Mask to clear everything except for the rounding modes and non-IEEE
39475 arithmetic flag. */
39476 const unsigned HOST_WIDE_INT hold_exception_mask =
39477 HOST_WIDE_INT_C (0xffffffff00000007);
39479 tree fenv_var = create_tmp_var_raw (double_type_node);
39481 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39483 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39484 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39485 build_int_cst (uint64_type_node,
39486 hold_exception_mask));
39488 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39491 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39492 build_int_cst (unsigned_type_node, 0xff),
39495 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39497 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39499 double fenv_clear = __builtin_mffs ();
39500 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39501 __builtin_mtfsf (0xff, fenv_clear); */
39503 /* Mask to clear everything except for the rounding modes and non-IEEE
39504 arithmetic flag. */
39505 const unsigned HOST_WIDE_INT clear_exception_mask =
39506 HOST_WIDE_INT_C (0xffffffff00000000);
39508 tree fenv_clear = create_tmp_var_raw (double_type_node);
39510 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39512 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39513 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39515 build_int_cst (uint64_type_node,
39516 clear_exception_mask));
39518 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39519 fenv_clear_llu_and);
39521 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39522 build_int_cst (unsigned_type_node, 0xff),
39525 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39527 /* Generates the equivalent of feupdateenv (&fenv_var)
39529 double old_fenv = __builtin_mffs ();
39530 double fenv_update;
39531 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39532 (*(uint64_t*)fenv_var 0x1ff80fff);
39533 __builtin_mtfsf (0xff, fenv_update); */
39535 const unsigned HOST_WIDE_INT update_exception_mask =
39536 HOST_WIDE_INT_C (0xffffffff1fffff00);
39537 const unsigned HOST_WIDE_INT new_exception_mask =
39538 HOST_WIDE_INT_C (0x1ff80fff);
39540 tree old_fenv = create_tmp_var_raw (double_type_node);
39541 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39543 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39544 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39545 build_int_cst (uint64_type_node,
39546 update_exception_mask));
39548 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39549 build_int_cst (uint64_type_node,
39550 new_exception_mask));
39552 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39553 old_llu_and, new_llu_and);
39555 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39558 tree update_mtfsf = build_call_expr (mtfsf, 2,
39559 build_int_cst (unsigned_type_node, 0xff),
39560 fenv_update_mtfsf);
39562 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39566 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39568 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39570 rtx_tmp0 = gen_reg_rtx (V2DImode);
39571 rtx_tmp1 = gen_reg_rtx (V2DImode);
39573 /* The destination of the vmrgew instruction layout is:
39574 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39575 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39576 vmrgew instruction will be correct. */
39577 if (VECTOR_ELT_ORDER_BIG)
39579 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39580 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39584 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39585 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39588 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39589 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39591 if (signed_convert)
39593 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39594 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39598 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39599 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39602 if (VECTOR_ELT_ORDER_BIG)
39603 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39605 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39609 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39612 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39614 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39615 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39617 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39618 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39620 rtx_tmp2 = gen_reg_rtx (V4SImode);
39621 rtx_tmp3 = gen_reg_rtx (V4SImode);
39623 if (signed_convert)
39625 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39626 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39630 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39631 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39634 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39637 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39640 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39641 optimization_type opt_type)
39646 return (opt_type == OPTIMIZE_FOR_SPEED
39647 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39654 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39656 static HOST_WIDE_INT
39657 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39659 if (TREE_CODE (exp) == STRING_CST
39660 && (STRICT_ALIGNMENT || !optimize_size))
39661 return MAX (align, BITS_PER_WORD);
39665 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39667 static HOST_WIDE_INT
39668 rs6000_starting_frame_offset (void)
39670 if (FRAME_GROWS_DOWNWARD)
39672 return RS6000_STARTING_FRAME_OFFSET;
39675 struct gcc_target targetm = TARGET_INITIALIZER;
39677 #include "gt-rs6000.h"