1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
108 /* Structure used to define the rs6000 stack */
109 typedef struct rs6000_stack {
110 int reload_completed; /* stack info won't change from here on */
111 int first_gp_reg_save; /* first callee saved GP register used */
112 int first_fp_reg_save; /* first callee saved FP register used */
113 int first_altivec_reg_save; /* first callee saved AltiVec register used */
114 int lr_save_p; /* true if the link reg needs to be saved */
115 int cr_save_p; /* true if the CR reg needs to be saved */
116 unsigned int vrsave_mask; /* mask of vec registers to save */
117 int push_p; /* true if we need to allocate stack space */
118 int calls_p; /* true if the function makes any calls */
119 int world_save_p; /* true if we're saving *everything*:
120 r13-r31, cr, f14-f31, vrsave, v20-v31 */
121 enum rs6000_abi abi; /* which ABI to use */
122 int gp_save_offset; /* offset to save GP regs from initial SP */
123 int fp_save_offset; /* offset to save FP regs from initial SP */
124 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
125 int lr_save_offset; /* offset to save LR from initial SP */
126 int cr_save_offset; /* offset to save CR from initial SP */
127 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
128 int varargs_save_offset; /* offset to save the varargs registers */
129 int ehrd_offset; /* offset to EH return data */
130 int ehcr_offset; /* offset to EH CR field data */
131 int reg_size; /* register size (4 or 8) */
132 HOST_WIDE_INT vars_size; /* variable save area size */
133 int parm_size; /* outgoing parameter size */
134 int save_size; /* save area size */
135 int fixed_size; /* fixed size of stack frame */
136 int gp_size; /* size of saved GP registers */
137 int fp_size; /* size of saved FP registers */
138 int altivec_size; /* size of saved AltiVec registers */
139 int cr_size; /* size to hold CR if not in fixed area */
140 int vrsave_size; /* size to hold VRSAVE */
141 int altivec_padding_size; /* size of altivec alignment padding */
142 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
146 /* A C structure for machine-specific, per-function data.
147 This is added to the cfun structure. */
148 typedef struct GTY(()) machine_function
150 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
151 int ra_needs_full_frame;
152 /* Flags if __builtin_return_address (0) was used. */
154 /* Cache lr_save_p after expansion of builtin_eh_return. */
156 /* Whether we need to save the TOC to the reserved stack location in the
157 function prologue. */
158 bool save_toc_in_prologue;
159 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
160 varargs save area. */
161 HOST_WIDE_INT varargs_save_offset;
162 /* Alternative internal arg pointer for -fsplit-stack. */
163 rtx split_stack_arg_pointer;
164 bool split_stack_argp_used;
165 /* Flag if r2 setup is needed with ELFv2 ABI. */
166 bool r2_setup_needed;
167 /* The number of components we use for separate shrink-wrapping. */
169 /* The components already handled by separate shrink-wrapping, which should
170 not be considered by the prologue and epilogue. */
171 bool gpr_is_wrapped_separately[32];
172 bool fpr_is_wrapped_separately[32];
173 bool lr_is_wrapped_separately;
174 bool toc_is_wrapped_separately;
177 /* Support targetm.vectorize.builtin_mask_for_load. */
178 static GTY(()) tree altivec_builtin_mask_for_load;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 static int rs6000_pic_labelno;
188 /* Counter for labels which are to be placed in .fixup. */
189 int fixuplabelno = 0;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
195 /* Specify the machine mode that pointers have. After generation of rtl, the
196 compiler makes no further distinction between pointers and any other objects
197 of this machine mode. */
198 scalar_int_mode rs6000_pmode;
200 /* Note whether IEEE 128-bit floating point was passed or returned, either as
201 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
202 floating point. We changed the default C++ mangling for these types and we
203 may want to generate a weak alias of the old mangling (U10__float128) to the
204 new mangling (u9__ieee128). */
205 static bool rs6000_passes_ieee128;
207 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
208 name used in current releases (i.e. u9__ieee128). */
209 static bool ieee128_mangling_gcc_8_1;
211 /* Width in bits of a pointer. */
212 unsigned rs6000_pointer_size;
214 #ifdef HAVE_AS_GNU_ATTRIBUTE
215 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
216 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
218 /* Flag whether floating point values have been passed/returned.
219 Note that this doesn't say whether fprs are used, since the
220 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
221 should be set for soft-float values passed in gprs and ieee128
222 values passed in vsx registers. */
223 static bool rs6000_passes_float;
224 static bool rs6000_passes_long_double;
225 /* Flag whether vector values have been passed/returned. */
226 static bool rs6000_passes_vector;
227 /* Flag whether small (<= 8 byte) structures have been returned. */
228 static bool rs6000_returns_struct;
231 /* Value is TRUE if register/mode pair is acceptable. */
232 static bool rs6000_hard_regno_mode_ok_p
233 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
235 /* Maximum number of registers needed for a given register class and mode. */
236 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
238 /* How many registers are needed for a given register and mode. */
239 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
241 /* Map register number to register class. */
242 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
244 static int dbg_cost_ctrl;
246 /* Built in types. */
247 tree rs6000_builtin_types[RS6000_BTI_MAX];
248 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
250 /* Flag to say the TOC is initialized */
251 int toc_initialized, need_toc_init;
252 char toc_label_name[10];
254 /* Cached value of rs6000_variable_issue. This is cached in
255 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
256 static short cached_can_issue_more;
258 static GTY(()) section *read_only_data_section;
259 static GTY(()) section *private_data_section;
260 static GTY(()) section *tls_data_section;
261 static GTY(()) section *tls_private_data_section;
262 static GTY(()) section *read_only_private_data_section;
263 static GTY(()) section *sdata2_section;
264 static GTY(()) section *toc_section;
266 struct builtin_description
268 const HOST_WIDE_INT mask;
269 const enum insn_code icode;
270 const char *const name;
271 const enum rs6000_builtins code;
274 /* Describe the vector unit used for modes. */
275 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
276 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
278 /* Register classes for various constraints that are based on the target
280 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
282 /* Describe the alignment of a vector. */
283 int rs6000_vector_align[NUM_MACHINE_MODES];
285 /* Map selected modes to types for builtins. */
286 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
288 /* What modes to automatically generate reciprocal divide estimate (fre) and
289 reciprocal sqrt (frsqrte) for. */
290 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
292 /* Masks to determine which reciprocal esitmate instructions to generate
294 enum rs6000_recip_mask {
295 RECIP_SF_DIV = 0x001, /* Use divide estimate */
296 RECIP_DF_DIV = 0x002,
297 RECIP_V4SF_DIV = 0x004,
298 RECIP_V2DF_DIV = 0x008,
300 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
301 RECIP_DF_RSQRT = 0x020,
302 RECIP_V4SF_RSQRT = 0x040,
303 RECIP_V2DF_RSQRT = 0x080,
305 /* Various combination of flags for -mrecip=xxx. */
307 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
308 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
309 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
311 RECIP_HIGH_PRECISION = RECIP_ALL,
313 /* On low precision machines like the power5, don't enable double precision
314 reciprocal square root estimate, since it isn't accurate enough. */
315 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
318 /* -mrecip options. */
321 const char *string; /* option name */
322 unsigned int mask; /* mask bits to set */
323 } recip_options[] = {
324 { "all", RECIP_ALL },
325 { "none", RECIP_NONE },
326 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
328 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
329 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
330 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
331 | RECIP_V2DF_RSQRT) },
332 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
333 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
336 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
342 { "power9", PPC_PLATFORM_POWER9 },
343 { "power8", PPC_PLATFORM_POWER8 },
344 { "power7", PPC_PLATFORM_POWER7 },
345 { "power6x", PPC_PLATFORM_POWER6X },
346 { "power6", PPC_PLATFORM_POWER6 },
347 { "power5+", PPC_PLATFORM_POWER5_PLUS },
348 { "power5", PPC_PLATFORM_POWER5 },
349 { "ppc970", PPC_PLATFORM_PPC970 },
350 { "power4", PPC_PLATFORM_POWER4 },
351 { "ppca2", PPC_PLATFORM_PPCA2 },
352 { "ppc476", PPC_PLATFORM_PPC476 },
353 { "ppc464", PPC_PLATFORM_PPC464 },
354 { "ppc440", PPC_PLATFORM_PPC440 },
355 { "ppc405", PPC_PLATFORM_PPC405 },
356 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
359 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
365 } cpu_supports_info[] = {
366 /* AT_HWCAP masks. */
367 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
368 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
369 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
370 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
371 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
372 { "booke", PPC_FEATURE_BOOKE, 0 },
373 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
374 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
375 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
376 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
377 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
378 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
379 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
380 { "notb", PPC_FEATURE_NO_TB, 0 },
381 { "pa6t", PPC_FEATURE_PA6T, 0 },
382 { "power4", PPC_FEATURE_POWER4, 0 },
383 { "power5", PPC_FEATURE_POWER5, 0 },
384 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
385 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
386 { "ppc32", PPC_FEATURE_32, 0 },
387 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
388 { "ppc64", PPC_FEATURE_64, 0 },
389 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
390 { "smt", PPC_FEATURE_SMT, 0 },
391 { "spe", PPC_FEATURE_HAS_SPE, 0 },
392 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
393 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
394 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
396 /* AT_HWCAP2 masks. */
397 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
398 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
399 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
400 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
401 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
402 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
403 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
404 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
405 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
406 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
407 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
408 { "darn", PPC_FEATURE2_DARN, 1 },
409 { "scv", PPC_FEATURE2_SCV, 1 }
412 /* On PowerPC, we have a limited number of target clones that we care about
413 which means we can use an array to hold the options, rather than having more
414 elaborate data structures to identify each possible variation. Order the
415 clones from the default to the highest ISA. */
417 CLONE_DEFAULT = 0, /* default clone. */
418 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
419 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
420 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
421 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
425 /* Map compiler ISA bits into HWCAP names. */
427 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
428 const char *name; /* name to use in __builtin_cpu_supports. */
431 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
432 { 0, "" }, /* Default options. */
433 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
434 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
435 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
436 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
440 /* Newer LIBCs explicitly export this symbol to declare that they provide
441 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
442 reference to this symbol whenever we expand a CPU builtin, so that
443 we never link against an old LIBC. */
444 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
446 /* True if we have expanded a CPU builtin. */
449 /* Pointer to function (in rs6000-c.c) that can define or undefine target
450 macros that have changed. Languages that don't support the preprocessor
451 don't link in rs6000-c.c, so we can't call it directly. */
452 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
454 /* Simplfy register classes into simpler classifications. We assume
455 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
456 check for standard register classes (gpr/floating/altivec/vsx) and
457 floating/vector classes (float/altivec/vsx). */
459 enum rs6000_reg_type {
470 /* Map register class to register type. */
471 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
473 /* First/last register type for the 'normal' register types (i.e. general
474 purpose, floating point, altivec, and VSX registers). */
475 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
477 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
480 /* Register classes we care about in secondary reload or go if legitimate
481 address. We only need to worry about GPR, FPR, and Altivec registers here,
482 along an ANY field that is the OR of the 3 register classes. */
484 enum rs6000_reload_reg_type {
485 RELOAD_REG_GPR, /* General purpose registers. */
486 RELOAD_REG_FPR, /* Traditional floating point regs. */
487 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
488 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
492 /* For setting up register classes, loop through the 3 register classes mapping
493 into real registers, and skip the ANY class, which is just an OR of the
495 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
496 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
498 /* Map reload register type to a register in the register class. */
499 struct reload_reg_map_type {
500 const char *name; /* Register class name. */
501 int reg; /* Register in the register class. */
504 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
505 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
506 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
507 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
508 { "Any", -1 }, /* RELOAD_REG_ANY. */
511 /* Mask bits for each register class, indexed per mode. Historically the
512 compiler has been more restrictive which types can do PRE_MODIFY instead of
513 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
514 typedef unsigned char addr_mask_type;
516 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
517 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
518 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
519 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
520 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
521 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
522 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
523 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
525 /* Register type masks based on the type, of valid addressing modes. */
526 struct rs6000_reg_addr {
527 enum insn_code reload_load; /* INSN to reload for loading. */
528 enum insn_code reload_store; /* INSN to reload for storing. */
529 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
530 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
531 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
532 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
533 /* INSNs for fusing addi with loads
534 or stores for each reg. class. */
535 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
536 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
537 /* INSNs for fusing addis with loads
538 or stores for each reg. class. */
539 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
540 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
541 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
542 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
543 bool fused_toc; /* Mode supports TOC fusion. */
546 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
548 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
550 mode_supports_pre_incdec_p (machine_mode mode)
552 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
556 /* Helper function to say whether a mode supports PRE_MODIFY. */
558 mode_supports_pre_modify_p (machine_mode mode)
560 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
564 /* Return true if we have D-form addressing in altivec registers. */
566 mode_supports_vmx_dform (machine_mode mode)
568 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
571 /* Return true if we have D-form addressing in VSX registers. This addressing
572 is more limited than normal d-form addressing in that the offset must be
573 aligned on a 16-byte boundary. */
575 mode_supports_dq_form (machine_mode mode)
577 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
581 /* Given that there exists at least one variable that is set (produced)
582 by OUT_INSN and read (consumed) by IN_INSN, return true iff
583 IN_INSN represents one or more memory store operations and none of
584 the variables set by OUT_INSN is used by IN_INSN as the address of a
585 store operation. If either IN_INSN or OUT_INSN does not represent
586 a "single" RTL SET expression (as loosely defined by the
587 implementation of the single_set function) or a PARALLEL with only
588 SETs, CLOBBERs, and USEs inside, this function returns false.
590 This rs6000-specific version of store_data_bypass_p checks for
591 certain conditions that result in assertion failures (and internal
592 compiler errors) in the generic store_data_bypass_p function and
593 returns false rather than calling store_data_bypass_p if one of the
594 problematic conditions is detected. */
597 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
604 in_set = single_set (in_insn);
607 if (MEM_P (SET_DEST (in_set)))
609 out_set = single_set (out_insn);
612 out_pat = PATTERN (out_insn);
613 if (GET_CODE (out_pat) == PARALLEL)
615 for (i = 0; i < XVECLEN (out_pat, 0); i++)
617 out_exp = XVECEXP (out_pat, 0, i);
618 if ((GET_CODE (out_exp) == CLOBBER)
619 || (GET_CODE (out_exp) == USE))
621 else if (GET_CODE (out_exp) != SET)
630 in_pat = PATTERN (in_insn);
631 if (GET_CODE (in_pat) != PARALLEL)
634 for (i = 0; i < XVECLEN (in_pat, 0); i++)
636 in_exp = XVECEXP (in_pat, 0, i);
637 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
639 else if (GET_CODE (in_exp) != SET)
642 if (MEM_P (SET_DEST (in_exp)))
644 out_set = single_set (out_insn);
647 out_pat = PATTERN (out_insn);
648 if (GET_CODE (out_pat) != PARALLEL)
650 for (j = 0; j < XVECLEN (out_pat, 0); j++)
652 out_exp = XVECEXP (out_pat, 0, j);
653 if ((GET_CODE (out_exp) == CLOBBER)
654 || (GET_CODE (out_exp) == USE))
656 else if (GET_CODE (out_exp) != SET)
663 return store_data_bypass_p (out_insn, in_insn);
667 /* Processor costs (relative to an add) */
669 const struct processor_costs *rs6000_cost;
671 /* Instruction size costs on 32bit processors. */
673 struct processor_costs size32_cost = {
674 COSTS_N_INSNS (1), /* mulsi */
675 COSTS_N_INSNS (1), /* mulsi_const */
676 COSTS_N_INSNS (1), /* mulsi_const9 */
677 COSTS_N_INSNS (1), /* muldi */
678 COSTS_N_INSNS (1), /* divsi */
679 COSTS_N_INSNS (1), /* divdi */
680 COSTS_N_INSNS (1), /* fp */
681 COSTS_N_INSNS (1), /* dmul */
682 COSTS_N_INSNS (1), /* sdiv */
683 COSTS_N_INSNS (1), /* ddiv */
684 32, /* cache line size */
688 0, /* SF->DF convert */
691 /* Instruction size costs on 64bit processors. */
693 struct processor_costs size64_cost = {
694 COSTS_N_INSNS (1), /* mulsi */
695 COSTS_N_INSNS (1), /* mulsi_const */
696 COSTS_N_INSNS (1), /* mulsi_const9 */
697 COSTS_N_INSNS (1), /* muldi */
698 COSTS_N_INSNS (1), /* divsi */
699 COSTS_N_INSNS (1), /* divdi */
700 COSTS_N_INSNS (1), /* fp */
701 COSTS_N_INSNS (1), /* dmul */
702 COSTS_N_INSNS (1), /* sdiv */
703 COSTS_N_INSNS (1), /* ddiv */
704 128, /* cache line size */
708 0, /* SF->DF convert */
711 /* Instruction costs on RS64A processors. */
713 struct processor_costs rs64a_cost = {
714 COSTS_N_INSNS (20), /* mulsi */
715 COSTS_N_INSNS (12), /* mulsi_const */
716 COSTS_N_INSNS (8), /* mulsi_const9 */
717 COSTS_N_INSNS (34), /* muldi */
718 COSTS_N_INSNS (65), /* divsi */
719 COSTS_N_INSNS (67), /* divdi */
720 COSTS_N_INSNS (4), /* fp */
721 COSTS_N_INSNS (4), /* dmul */
722 COSTS_N_INSNS (31), /* sdiv */
723 COSTS_N_INSNS (31), /* ddiv */
724 128, /* cache line size */
728 0, /* SF->DF convert */
731 /* Instruction costs on MPCCORE processors. */
733 struct processor_costs mpccore_cost = {
734 COSTS_N_INSNS (2), /* mulsi */
735 COSTS_N_INSNS (2), /* mulsi_const */
736 COSTS_N_INSNS (2), /* mulsi_const9 */
737 COSTS_N_INSNS (2), /* muldi */
738 COSTS_N_INSNS (6), /* divsi */
739 COSTS_N_INSNS (6), /* divdi */
740 COSTS_N_INSNS (4), /* fp */
741 COSTS_N_INSNS (5), /* dmul */
742 COSTS_N_INSNS (10), /* sdiv */
743 COSTS_N_INSNS (17), /* ddiv */
744 32, /* cache line size */
748 0, /* SF->DF convert */
751 /* Instruction costs on PPC403 processors. */
753 struct processor_costs ppc403_cost = {
754 COSTS_N_INSNS (4), /* mulsi */
755 COSTS_N_INSNS (4), /* mulsi_const */
756 COSTS_N_INSNS (4), /* mulsi_const9 */
757 COSTS_N_INSNS (4), /* muldi */
758 COSTS_N_INSNS (33), /* divsi */
759 COSTS_N_INSNS (33), /* divdi */
760 COSTS_N_INSNS (11), /* fp */
761 COSTS_N_INSNS (11), /* dmul */
762 COSTS_N_INSNS (11), /* sdiv */
763 COSTS_N_INSNS (11), /* ddiv */
764 32, /* cache line size */
768 0, /* SF->DF convert */
771 /* Instruction costs on PPC405 processors. */
773 struct processor_costs ppc405_cost = {
774 COSTS_N_INSNS (5), /* mulsi */
775 COSTS_N_INSNS (4), /* mulsi_const */
776 COSTS_N_INSNS (3), /* mulsi_const9 */
777 COSTS_N_INSNS (5), /* muldi */
778 COSTS_N_INSNS (35), /* divsi */
779 COSTS_N_INSNS (35), /* divdi */
780 COSTS_N_INSNS (11), /* fp */
781 COSTS_N_INSNS (11), /* dmul */
782 COSTS_N_INSNS (11), /* sdiv */
783 COSTS_N_INSNS (11), /* ddiv */
784 32, /* cache line size */
788 0, /* SF->DF convert */
791 /* Instruction costs on PPC440 processors. */
793 struct processor_costs ppc440_cost = {
794 COSTS_N_INSNS (3), /* mulsi */
795 COSTS_N_INSNS (2), /* mulsi_const */
796 COSTS_N_INSNS (2), /* mulsi_const9 */
797 COSTS_N_INSNS (3), /* muldi */
798 COSTS_N_INSNS (34), /* divsi */
799 COSTS_N_INSNS (34), /* divdi */
800 COSTS_N_INSNS (5), /* fp */
801 COSTS_N_INSNS (5), /* dmul */
802 COSTS_N_INSNS (19), /* sdiv */
803 COSTS_N_INSNS (33), /* ddiv */
804 32, /* cache line size */
808 0, /* SF->DF convert */
811 /* Instruction costs on PPC476 processors. */
813 struct processor_costs ppc476_cost = {
814 COSTS_N_INSNS (4), /* mulsi */
815 COSTS_N_INSNS (4), /* mulsi_const */
816 COSTS_N_INSNS (4), /* mulsi_const9 */
817 COSTS_N_INSNS (4), /* muldi */
818 COSTS_N_INSNS (11), /* divsi */
819 COSTS_N_INSNS (11), /* divdi */
820 COSTS_N_INSNS (6), /* fp */
821 COSTS_N_INSNS (6), /* dmul */
822 COSTS_N_INSNS (19), /* sdiv */
823 COSTS_N_INSNS (33), /* ddiv */
824 32, /* l1 cache line size */
828 0, /* SF->DF convert */
831 /* Instruction costs on PPC601 processors. */
833 struct processor_costs ppc601_cost = {
834 COSTS_N_INSNS (5), /* mulsi */
835 COSTS_N_INSNS (5), /* mulsi_const */
836 COSTS_N_INSNS (5), /* mulsi_const9 */
837 COSTS_N_INSNS (5), /* muldi */
838 COSTS_N_INSNS (36), /* divsi */
839 COSTS_N_INSNS (36), /* divdi */
840 COSTS_N_INSNS (4), /* fp */
841 COSTS_N_INSNS (5), /* dmul */
842 COSTS_N_INSNS (17), /* sdiv */
843 COSTS_N_INSNS (31), /* ddiv */
844 32, /* cache line size */
848 0, /* SF->DF convert */
851 /* Instruction costs on PPC603 processors. */
853 struct processor_costs ppc603_cost = {
854 COSTS_N_INSNS (5), /* mulsi */
855 COSTS_N_INSNS (3), /* mulsi_const */
856 COSTS_N_INSNS (2), /* mulsi_const9 */
857 COSTS_N_INSNS (5), /* muldi */
858 COSTS_N_INSNS (37), /* divsi */
859 COSTS_N_INSNS (37), /* divdi */
860 COSTS_N_INSNS (3), /* fp */
861 COSTS_N_INSNS (4), /* dmul */
862 COSTS_N_INSNS (18), /* sdiv */
863 COSTS_N_INSNS (33), /* ddiv */
864 32, /* cache line size */
868 0, /* SF->DF convert */
871 /* Instruction costs on PPC604 processors. */
873 struct processor_costs ppc604_cost = {
874 COSTS_N_INSNS (4), /* mulsi */
875 COSTS_N_INSNS (4), /* mulsi_const */
876 COSTS_N_INSNS (4), /* mulsi_const9 */
877 COSTS_N_INSNS (4), /* muldi */
878 COSTS_N_INSNS (20), /* divsi */
879 COSTS_N_INSNS (20), /* divdi */
880 COSTS_N_INSNS (3), /* fp */
881 COSTS_N_INSNS (3), /* dmul */
882 COSTS_N_INSNS (18), /* sdiv */
883 COSTS_N_INSNS (32), /* ddiv */
884 32, /* cache line size */
888 0, /* SF->DF convert */
891 /* Instruction costs on PPC604e processors. */
893 struct processor_costs ppc604e_cost = {
894 COSTS_N_INSNS (2), /* mulsi */
895 COSTS_N_INSNS (2), /* mulsi_const */
896 COSTS_N_INSNS (2), /* mulsi_const9 */
897 COSTS_N_INSNS (2), /* muldi */
898 COSTS_N_INSNS (20), /* divsi */
899 COSTS_N_INSNS (20), /* divdi */
900 COSTS_N_INSNS (3), /* fp */
901 COSTS_N_INSNS (3), /* dmul */
902 COSTS_N_INSNS (18), /* sdiv */
903 COSTS_N_INSNS (32), /* ddiv */
904 32, /* cache line size */
908 0, /* SF->DF convert */
911 /* Instruction costs on PPC620 processors. */
913 struct processor_costs ppc620_cost = {
914 COSTS_N_INSNS (5), /* mulsi */
915 COSTS_N_INSNS (4), /* mulsi_const */
916 COSTS_N_INSNS (3), /* mulsi_const9 */
917 COSTS_N_INSNS (7), /* muldi */
918 COSTS_N_INSNS (21), /* divsi */
919 COSTS_N_INSNS (37), /* divdi */
920 COSTS_N_INSNS (3), /* fp */
921 COSTS_N_INSNS (3), /* dmul */
922 COSTS_N_INSNS (18), /* sdiv */
923 COSTS_N_INSNS (32), /* ddiv */
924 128, /* cache line size */
928 0, /* SF->DF convert */
931 /* Instruction costs on PPC630 processors. */
933 struct processor_costs ppc630_cost = {
934 COSTS_N_INSNS (5), /* mulsi */
935 COSTS_N_INSNS (4), /* mulsi_const */
936 COSTS_N_INSNS (3), /* mulsi_const9 */
937 COSTS_N_INSNS (7), /* muldi */
938 COSTS_N_INSNS (21), /* divsi */
939 COSTS_N_INSNS (37), /* divdi */
940 COSTS_N_INSNS (3), /* fp */
941 COSTS_N_INSNS (3), /* dmul */
942 COSTS_N_INSNS (17), /* sdiv */
943 COSTS_N_INSNS (21), /* ddiv */
944 128, /* cache line size */
948 0, /* SF->DF convert */
951 /* Instruction costs on Cell processor. */
952 /* COSTS_N_INSNS (1) ~ one add. */
954 struct processor_costs ppccell_cost = {
955 COSTS_N_INSNS (9/2)+2, /* mulsi */
956 COSTS_N_INSNS (6/2), /* mulsi_const */
957 COSTS_N_INSNS (6/2), /* mulsi_const9 */
958 COSTS_N_INSNS (15/2)+2, /* muldi */
959 COSTS_N_INSNS (38/2), /* divsi */
960 COSTS_N_INSNS (70/2), /* divdi */
961 COSTS_N_INSNS (10/2), /* fp */
962 COSTS_N_INSNS (10/2), /* dmul */
963 COSTS_N_INSNS (74/2), /* sdiv */
964 COSTS_N_INSNS (74/2), /* ddiv */
965 128, /* cache line size */
969 0, /* SF->DF convert */
972 /* Instruction costs on PPC750 and PPC7400 processors. */
974 struct processor_costs ppc750_cost = {
975 COSTS_N_INSNS (5), /* mulsi */
976 COSTS_N_INSNS (3), /* mulsi_const */
977 COSTS_N_INSNS (2), /* mulsi_const9 */
978 COSTS_N_INSNS (5), /* muldi */
979 COSTS_N_INSNS (17), /* divsi */
980 COSTS_N_INSNS (17), /* divdi */
981 COSTS_N_INSNS (3), /* fp */
982 COSTS_N_INSNS (3), /* dmul */
983 COSTS_N_INSNS (17), /* sdiv */
984 COSTS_N_INSNS (31), /* ddiv */
985 32, /* cache line size */
989 0, /* SF->DF convert */
992 /* Instruction costs on PPC7450 processors. */
994 struct processor_costs ppc7450_cost = {
995 COSTS_N_INSNS (4), /* mulsi */
996 COSTS_N_INSNS (3), /* mulsi_const */
997 COSTS_N_INSNS (3), /* mulsi_const9 */
998 COSTS_N_INSNS (4), /* muldi */
999 COSTS_N_INSNS (23), /* divsi */
1000 COSTS_N_INSNS (23), /* divdi */
1001 COSTS_N_INSNS (5), /* fp */
1002 COSTS_N_INSNS (5), /* dmul */
1003 COSTS_N_INSNS (21), /* sdiv */
1004 COSTS_N_INSNS (35), /* ddiv */
1005 32, /* cache line size */
1007 1024, /* l2 cache */
1009 0, /* SF->DF convert */
1012 /* Instruction costs on PPC8540 processors. */
1014 struct processor_costs ppc8540_cost = {
1015 COSTS_N_INSNS (4), /* mulsi */
1016 COSTS_N_INSNS (4), /* mulsi_const */
1017 COSTS_N_INSNS (4), /* mulsi_const9 */
1018 COSTS_N_INSNS (4), /* muldi */
1019 COSTS_N_INSNS (19), /* divsi */
1020 COSTS_N_INSNS (19), /* divdi */
1021 COSTS_N_INSNS (4), /* fp */
1022 COSTS_N_INSNS (4), /* dmul */
1023 COSTS_N_INSNS (29), /* sdiv */
1024 COSTS_N_INSNS (29), /* ddiv */
1025 32, /* cache line size */
1028 1, /* prefetch streams /*/
1029 0, /* SF->DF convert */
1032 /* Instruction costs on E300C2 and E300C3 cores. */
1034 struct processor_costs ppce300c2c3_cost = {
1035 COSTS_N_INSNS (4), /* mulsi */
1036 COSTS_N_INSNS (4), /* mulsi_const */
1037 COSTS_N_INSNS (4), /* mulsi_const9 */
1038 COSTS_N_INSNS (4), /* muldi */
1039 COSTS_N_INSNS (19), /* divsi */
1040 COSTS_N_INSNS (19), /* divdi */
1041 COSTS_N_INSNS (3), /* fp */
1042 COSTS_N_INSNS (4), /* dmul */
1043 COSTS_N_INSNS (18), /* sdiv */
1044 COSTS_N_INSNS (33), /* ddiv */
1048 1, /* prefetch streams /*/
1049 0, /* SF->DF convert */
1052 /* Instruction costs on PPCE500MC processors. */
1054 struct processor_costs ppce500mc_cost = {
1055 COSTS_N_INSNS (4), /* mulsi */
1056 COSTS_N_INSNS (4), /* mulsi_const */
1057 COSTS_N_INSNS (4), /* mulsi_const9 */
1058 COSTS_N_INSNS (4), /* muldi */
1059 COSTS_N_INSNS (14), /* divsi */
1060 COSTS_N_INSNS (14), /* divdi */
1061 COSTS_N_INSNS (8), /* fp */
1062 COSTS_N_INSNS (10), /* dmul */
1063 COSTS_N_INSNS (36), /* sdiv */
1064 COSTS_N_INSNS (66), /* ddiv */
1065 64, /* cache line size */
1068 1, /* prefetch streams /*/
1069 0, /* SF->DF convert */
1072 /* Instruction costs on PPCE500MC64 processors. */
1074 struct processor_costs ppce500mc64_cost = {
1075 COSTS_N_INSNS (4), /* mulsi */
1076 COSTS_N_INSNS (4), /* mulsi_const */
1077 COSTS_N_INSNS (4), /* mulsi_const9 */
1078 COSTS_N_INSNS (4), /* muldi */
1079 COSTS_N_INSNS (14), /* divsi */
1080 COSTS_N_INSNS (14), /* divdi */
1081 COSTS_N_INSNS (4), /* fp */
1082 COSTS_N_INSNS (10), /* dmul */
1083 COSTS_N_INSNS (36), /* sdiv */
1084 COSTS_N_INSNS (66), /* ddiv */
1085 64, /* cache line size */
1088 1, /* prefetch streams /*/
1089 0, /* SF->DF convert */
1092 /* Instruction costs on PPCE5500 processors. */
1094 struct processor_costs ppce5500_cost = {
1095 COSTS_N_INSNS (5), /* mulsi */
1096 COSTS_N_INSNS (5), /* mulsi_const */
1097 COSTS_N_INSNS (4), /* mulsi_const9 */
1098 COSTS_N_INSNS (5), /* muldi */
1099 COSTS_N_INSNS (14), /* divsi */
1100 COSTS_N_INSNS (14), /* divdi */
1101 COSTS_N_INSNS (7), /* fp */
1102 COSTS_N_INSNS (10), /* dmul */
1103 COSTS_N_INSNS (36), /* sdiv */
1104 COSTS_N_INSNS (66), /* ddiv */
1105 64, /* cache line size */
1108 1, /* prefetch streams /*/
1109 0, /* SF->DF convert */
1112 /* Instruction costs on PPCE6500 processors. */
1114 struct processor_costs ppce6500_cost = {
1115 COSTS_N_INSNS (5), /* mulsi */
1116 COSTS_N_INSNS (5), /* mulsi_const */
1117 COSTS_N_INSNS (4), /* mulsi_const9 */
1118 COSTS_N_INSNS (5), /* muldi */
1119 COSTS_N_INSNS (14), /* divsi */
1120 COSTS_N_INSNS (14), /* divdi */
1121 COSTS_N_INSNS (7), /* fp */
1122 COSTS_N_INSNS (10), /* dmul */
1123 COSTS_N_INSNS (36), /* sdiv */
1124 COSTS_N_INSNS (66), /* ddiv */
1125 64, /* cache line size */
1128 1, /* prefetch streams /*/
1129 0, /* SF->DF convert */
1132 /* Instruction costs on AppliedMicro Titan processors. */
1134 struct processor_costs titan_cost = {
1135 COSTS_N_INSNS (5), /* mulsi */
1136 COSTS_N_INSNS (5), /* mulsi_const */
1137 COSTS_N_INSNS (5), /* mulsi_const9 */
1138 COSTS_N_INSNS (5), /* muldi */
1139 COSTS_N_INSNS (18), /* divsi */
1140 COSTS_N_INSNS (18), /* divdi */
1141 COSTS_N_INSNS (10), /* fp */
1142 COSTS_N_INSNS (10), /* dmul */
1143 COSTS_N_INSNS (46), /* sdiv */
1144 COSTS_N_INSNS (72), /* ddiv */
1145 32, /* cache line size */
1148 1, /* prefetch streams /*/
1149 0, /* SF->DF convert */
1152 /* Instruction costs on POWER4 and POWER5 processors. */
1154 struct processor_costs power4_cost = {
1155 COSTS_N_INSNS (3), /* mulsi */
1156 COSTS_N_INSNS (2), /* mulsi_const */
1157 COSTS_N_INSNS (2), /* mulsi_const9 */
1158 COSTS_N_INSNS (4), /* muldi */
1159 COSTS_N_INSNS (18), /* divsi */
1160 COSTS_N_INSNS (34), /* divdi */
1161 COSTS_N_INSNS (3), /* fp */
1162 COSTS_N_INSNS (3), /* dmul */
1163 COSTS_N_INSNS (17), /* sdiv */
1164 COSTS_N_INSNS (17), /* ddiv */
1165 128, /* cache line size */
1167 1024, /* l2 cache */
1168 8, /* prefetch streams /*/
1169 0, /* SF->DF convert */
1172 /* Instruction costs on POWER6 processors. */
1174 struct processor_costs power6_cost = {
1175 COSTS_N_INSNS (8), /* mulsi */
1176 COSTS_N_INSNS (8), /* mulsi_const */
1177 COSTS_N_INSNS (8), /* mulsi_const9 */
1178 COSTS_N_INSNS (8), /* muldi */
1179 COSTS_N_INSNS (22), /* divsi */
1180 COSTS_N_INSNS (28), /* divdi */
1181 COSTS_N_INSNS (3), /* fp */
1182 COSTS_N_INSNS (3), /* dmul */
1183 COSTS_N_INSNS (13), /* sdiv */
1184 COSTS_N_INSNS (16), /* ddiv */
1185 128, /* cache line size */
1187 2048, /* l2 cache */
1188 16, /* prefetch streams */
1189 0, /* SF->DF convert */
1192 /* Instruction costs on POWER7 processors. */
1194 struct processor_costs power7_cost = {
1195 COSTS_N_INSNS (2), /* mulsi */
1196 COSTS_N_INSNS (2), /* mulsi_const */
1197 COSTS_N_INSNS (2), /* mulsi_const9 */
1198 COSTS_N_INSNS (2), /* muldi */
1199 COSTS_N_INSNS (18), /* divsi */
1200 COSTS_N_INSNS (34), /* divdi */
1201 COSTS_N_INSNS (3), /* fp */
1202 COSTS_N_INSNS (3), /* dmul */
1203 COSTS_N_INSNS (13), /* sdiv */
1204 COSTS_N_INSNS (16), /* ddiv */
1205 128, /* cache line size */
1208 12, /* prefetch streams */
1209 COSTS_N_INSNS (3), /* SF->DF convert */
1212 /* Instruction costs on POWER8 processors. */
1214 struct processor_costs power8_cost = {
1215 COSTS_N_INSNS (3), /* mulsi */
1216 COSTS_N_INSNS (3), /* mulsi_const */
1217 COSTS_N_INSNS (3), /* mulsi_const9 */
1218 COSTS_N_INSNS (3), /* muldi */
1219 COSTS_N_INSNS (19), /* divsi */
1220 COSTS_N_INSNS (35), /* divdi */
1221 COSTS_N_INSNS (3), /* fp */
1222 COSTS_N_INSNS (3), /* dmul */
1223 COSTS_N_INSNS (14), /* sdiv */
1224 COSTS_N_INSNS (17), /* ddiv */
1225 128, /* cache line size */
1228 12, /* prefetch streams */
1229 COSTS_N_INSNS (3), /* SF->DF convert */
1232 /* Instruction costs on POWER9 processors. */
1234 struct processor_costs power9_cost = {
1235 COSTS_N_INSNS (3), /* mulsi */
1236 COSTS_N_INSNS (3), /* mulsi_const */
1237 COSTS_N_INSNS (3), /* mulsi_const9 */
1238 COSTS_N_INSNS (3), /* muldi */
1239 COSTS_N_INSNS (8), /* divsi */
1240 COSTS_N_INSNS (12), /* divdi */
1241 COSTS_N_INSNS (3), /* fp */
1242 COSTS_N_INSNS (3), /* dmul */
1243 COSTS_N_INSNS (13), /* sdiv */
1244 COSTS_N_INSNS (18), /* ddiv */
1245 128, /* cache line size */
1248 8, /* prefetch streams */
1249 COSTS_N_INSNS (3), /* SF->DF convert */
1252 /* Instruction costs on POWER A2 processors. */
1254 struct processor_costs ppca2_cost = {
1255 COSTS_N_INSNS (16), /* mulsi */
1256 COSTS_N_INSNS (16), /* mulsi_const */
1257 COSTS_N_INSNS (16), /* mulsi_const9 */
1258 COSTS_N_INSNS (16), /* muldi */
1259 COSTS_N_INSNS (22), /* divsi */
1260 COSTS_N_INSNS (28), /* divdi */
1261 COSTS_N_INSNS (3), /* fp */
1262 COSTS_N_INSNS (3), /* dmul */
1263 COSTS_N_INSNS (59), /* sdiv */
1264 COSTS_N_INSNS (72), /* ddiv */
1267 2048, /* l2 cache */
1268 16, /* prefetch streams */
1269 0, /* SF->DF convert */
1273 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1274 #undef RS6000_BUILTIN_0
1275 #undef RS6000_BUILTIN_1
1276 #undef RS6000_BUILTIN_2
1277 #undef RS6000_BUILTIN_3
1278 #undef RS6000_BUILTIN_A
1279 #undef RS6000_BUILTIN_D
1280 #undef RS6000_BUILTIN_H
1281 #undef RS6000_BUILTIN_P
1282 #undef RS6000_BUILTIN_X
1284 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1306 { NAME, ICODE, MASK, ATTR },
1308 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1309 { NAME, ICODE, MASK, ATTR },
1311 struct rs6000_builtin_info_type {
1313 const enum insn_code icode;
1314 const HOST_WIDE_INT mask;
1315 const unsigned attr;
1318 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1320 #include "rs6000-builtin.def"
1323 #undef RS6000_BUILTIN_0
1324 #undef RS6000_BUILTIN_1
1325 #undef RS6000_BUILTIN_2
1326 #undef RS6000_BUILTIN_3
1327 #undef RS6000_BUILTIN_A
1328 #undef RS6000_BUILTIN_D
1329 #undef RS6000_BUILTIN_H
1330 #undef RS6000_BUILTIN_P
1331 #undef RS6000_BUILTIN_X
1333 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1334 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1337 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1338 static struct machine_function * rs6000_init_machine_status (void);
1339 static int rs6000_ra_ever_killed (void);
1340 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1341 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1342 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1343 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1344 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1345 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1346 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1347 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1349 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1351 static bool is_microcoded_insn (rtx_insn *);
1352 static bool is_nonpipeline_insn (rtx_insn *);
1353 static bool is_cracked_insn (rtx_insn *);
1354 static bool is_load_insn (rtx, rtx *);
1355 static bool is_store_insn (rtx, rtx *);
1356 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1357 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1358 static bool insn_must_be_first_in_group (rtx_insn *);
1359 static bool insn_must_be_last_in_group (rtx_insn *);
1360 static void altivec_init_builtins (void);
1361 static tree builtin_function_type (machine_mode, machine_mode,
1362 machine_mode, machine_mode,
1363 enum rs6000_builtins, const char *name);
1364 static void rs6000_common_init_builtins (void);
1365 static void htm_init_builtins (void);
1366 static rs6000_stack_t *rs6000_stack_info (void);
1367 static void is_altivec_return_reg (rtx, void *);
1368 int easy_vector_constant (rtx, machine_mode);
1369 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1370 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1371 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1374 static void macho_branch_islands (void);
1376 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1378 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1380 static bool rs6000_mode_dependent_address (const_rtx);
1381 static bool rs6000_debug_mode_dependent_address (const_rtx);
1382 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1383 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1385 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1388 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1389 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1391 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1394 static bool rs6000_debug_can_change_mode_class (machine_mode,
1397 static bool rs6000_save_toc_in_prologue_p (void);
1398 static rtx rs6000_internal_arg_pointer (void);
1400 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1402 = rs6000_legitimize_reload_address;
1404 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1405 = rs6000_mode_dependent_address;
1407 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1409 = rs6000_secondary_reload_class;
1411 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1412 = rs6000_preferred_reload_class;
1414 const int INSN_NOT_AVAILABLE = -1;
1416 static void rs6000_print_isa_options (FILE *, int, const char *,
1418 static void rs6000_print_builtin_options (FILE *, int, const char *,
1420 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1422 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1423 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1424 enum rs6000_reg_type,
1426 secondary_reload_info *,
1428 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1429 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1430 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1432 /* Hash table stuff for keeping track of TOC entries. */
1434 struct GTY((for_user)) toc_hash_struct
1436 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1437 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1439 machine_mode key_mode;
1443 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1445 static hashval_t hash (toc_hash_struct *);
1446 static bool equal (toc_hash_struct *, toc_hash_struct *);
1449 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1451 /* Hash table to keep track of the argument types for builtin functions. */
1453 struct GTY((for_user)) builtin_hash_struct
1456 machine_mode mode[4]; /* return value + 3 arguments. */
1457 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1460 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1462 static hashval_t hash (builtin_hash_struct *);
1463 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1466 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1469 /* Default register names. */
1470 char rs6000_reg_names[][8] =
1472 "0", "1", "2", "3", "4", "5", "6", "7",
1473 "8", "9", "10", "11", "12", "13", "14", "15",
1474 "16", "17", "18", "19", "20", "21", "22", "23",
1475 "24", "25", "26", "27", "28", "29", "30", "31",
1476 "0", "1", "2", "3", "4", "5", "6", "7",
1477 "8", "9", "10", "11", "12", "13", "14", "15",
1478 "16", "17", "18", "19", "20", "21", "22", "23",
1479 "24", "25", "26", "27", "28", "29", "30", "31",
1480 "mq", "lr", "ctr","ap",
1481 "0", "1", "2", "3", "4", "5", "6", "7",
1483 /* AltiVec registers. */
1484 "0", "1", "2", "3", "4", "5", "6", "7",
1485 "8", "9", "10", "11", "12", "13", "14", "15",
1486 "16", "17", "18", "19", "20", "21", "22", "23",
1487 "24", "25", "26", "27", "28", "29", "30", "31",
1489 /* Soft frame pointer. */
1491 /* HTM SPR registers. */
1492 "tfhar", "tfiar", "texasr"
1495 #ifdef TARGET_REGNAMES
1496 static const char alt_reg_names[][8] =
1498 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1499 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1500 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1501 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1502 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1503 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1504 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1505 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1506 "mq", "lr", "ctr", "ap",
1507 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1509 /* AltiVec registers. */
1510 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1511 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1512 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1513 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1515 /* Soft frame pointer. */
1517 /* HTM SPR registers. */
1518 "tfhar", "tfiar", "texasr"
1522 /* Table of valid machine attributes. */
1524 static const struct attribute_spec rs6000_attribute_table[] =
1526 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1527 affects_type_identity, handler, exclude } */
1528 { "altivec", 1, 1, false, true, false, false,
1529 rs6000_handle_altivec_attribute, NULL },
1530 { "longcall", 0, 0, false, true, true, false,
1531 rs6000_handle_longcall_attribute, NULL },
1532 { "shortcall", 0, 0, false, true, true, false,
1533 rs6000_handle_longcall_attribute, NULL },
1534 { "ms_struct", 0, 0, false, false, false, false,
1535 rs6000_handle_struct_attribute, NULL },
1536 { "gcc_struct", 0, 0, false, false, false, false,
1537 rs6000_handle_struct_attribute, NULL },
1538 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1539 SUBTARGET_ATTRIBUTE_TABLE,
1541 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1544 #ifndef TARGET_PROFILE_KERNEL
1545 #define TARGET_PROFILE_KERNEL 0
1548 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1549 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1551 /* Initialize the GCC target structure. */
1552 #undef TARGET_ATTRIBUTE_TABLE
1553 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1554 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1555 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1556 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1557 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1559 #undef TARGET_ASM_ALIGNED_DI_OP
1560 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1562 /* Default unaligned ops are only provided for ELF. Find the ops needed
1563 for non-ELF systems. */
1564 #ifndef OBJECT_FORMAT_ELF
1566 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1568 #undef TARGET_ASM_UNALIGNED_HI_OP
1569 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1570 #undef TARGET_ASM_UNALIGNED_SI_OP
1571 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1572 #undef TARGET_ASM_UNALIGNED_DI_OP
1573 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1576 #undef TARGET_ASM_UNALIGNED_HI_OP
1577 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1578 #undef TARGET_ASM_UNALIGNED_SI_OP
1579 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1580 #undef TARGET_ASM_UNALIGNED_DI_OP
1581 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1582 #undef TARGET_ASM_ALIGNED_DI_OP
1583 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1587 /* This hook deals with fixups for relocatable code and DI-mode objects
1589 #undef TARGET_ASM_INTEGER
1590 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1592 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1593 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1594 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1597 #undef TARGET_SET_UP_BY_PROLOGUE
1598 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1600 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1601 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1602 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1603 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1604 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1605 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1606 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1607 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1608 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1609 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1610 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1611 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1613 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1614 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1616 #undef TARGET_INTERNAL_ARG_POINTER
1617 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1619 #undef TARGET_HAVE_TLS
1620 #define TARGET_HAVE_TLS HAVE_AS_TLS
1622 #undef TARGET_CANNOT_FORCE_CONST_MEM
1623 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1625 #undef TARGET_DELEGITIMIZE_ADDRESS
1626 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1628 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1629 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1631 #undef TARGET_LEGITIMATE_COMBINED_INSN
1632 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1634 #undef TARGET_ASM_FUNCTION_PROLOGUE
1635 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1636 #undef TARGET_ASM_FUNCTION_EPILOGUE
1637 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1639 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1640 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1642 #undef TARGET_LEGITIMIZE_ADDRESS
1643 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1645 #undef TARGET_SCHED_VARIABLE_ISSUE
1646 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1648 #undef TARGET_SCHED_ISSUE_RATE
1649 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1650 #undef TARGET_SCHED_ADJUST_COST
1651 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1652 #undef TARGET_SCHED_ADJUST_PRIORITY
1653 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1654 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1655 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1656 #undef TARGET_SCHED_INIT
1657 #define TARGET_SCHED_INIT rs6000_sched_init
1658 #undef TARGET_SCHED_FINISH
1659 #define TARGET_SCHED_FINISH rs6000_sched_finish
1660 #undef TARGET_SCHED_REORDER
1661 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1662 #undef TARGET_SCHED_REORDER2
1663 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1665 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1666 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1668 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1669 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1671 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1672 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1673 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1674 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1675 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1676 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1677 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1678 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1680 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1681 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1683 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1684 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1685 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1686 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1687 rs6000_builtin_support_vector_misalignment
1688 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1689 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1690 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1691 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1692 rs6000_builtin_vectorization_cost
1693 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1694 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1695 rs6000_preferred_simd_mode
1696 #undef TARGET_VECTORIZE_INIT_COST
1697 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1698 #undef TARGET_VECTORIZE_ADD_STMT_COST
1699 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1700 #undef TARGET_VECTORIZE_FINISH_COST
1701 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1702 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1703 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1705 #undef TARGET_INIT_BUILTINS
1706 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1707 #undef TARGET_BUILTIN_DECL
1708 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1710 #undef TARGET_FOLD_BUILTIN
1711 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1712 #undef TARGET_GIMPLE_FOLD_BUILTIN
1713 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1715 #undef TARGET_EXPAND_BUILTIN
1716 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1718 #undef TARGET_MANGLE_TYPE
1719 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1721 #undef TARGET_INIT_LIBFUNCS
1722 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1725 #undef TARGET_BINDS_LOCAL_P
1726 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1729 #undef TARGET_MS_BITFIELD_LAYOUT_P
1730 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1732 #undef TARGET_ASM_OUTPUT_MI_THUNK
1733 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1735 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1736 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1738 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1739 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1741 #undef TARGET_REGISTER_MOVE_COST
1742 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1743 #undef TARGET_MEMORY_MOVE_COST
1744 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1745 #undef TARGET_CANNOT_COPY_INSN_P
1746 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1747 #undef TARGET_RTX_COSTS
1748 #define TARGET_RTX_COSTS rs6000_rtx_costs
1749 #undef TARGET_ADDRESS_COST
1750 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1751 #undef TARGET_INSN_COST
1752 #define TARGET_INSN_COST rs6000_insn_cost
1754 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1755 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1757 #undef TARGET_PROMOTE_FUNCTION_MODE
1758 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1760 #undef TARGET_RETURN_IN_MEMORY
1761 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1763 #undef TARGET_RETURN_IN_MSB
1764 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1766 #undef TARGET_SETUP_INCOMING_VARARGS
1767 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1769 /* Always strict argument naming on rs6000. */
1770 #undef TARGET_STRICT_ARGUMENT_NAMING
1771 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1772 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1773 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1774 #undef TARGET_SPLIT_COMPLEX_ARG
1775 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1776 #undef TARGET_MUST_PASS_IN_STACK
1777 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1778 #undef TARGET_PASS_BY_REFERENCE
1779 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1780 #undef TARGET_ARG_PARTIAL_BYTES
1781 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1782 #undef TARGET_FUNCTION_ARG_ADVANCE
1783 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1784 #undef TARGET_FUNCTION_ARG
1785 #define TARGET_FUNCTION_ARG rs6000_function_arg
1786 #undef TARGET_FUNCTION_ARG_PADDING
1787 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1788 #undef TARGET_FUNCTION_ARG_BOUNDARY
1789 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1791 #undef TARGET_BUILD_BUILTIN_VA_LIST
1792 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1794 #undef TARGET_EXPAND_BUILTIN_VA_START
1795 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1797 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1798 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1800 #undef TARGET_EH_RETURN_FILTER_MODE
1801 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1803 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1804 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1806 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1807 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1809 #undef TARGET_FLOATN_MODE
1810 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1812 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1813 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1815 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1816 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1818 #undef TARGET_MD_ASM_ADJUST
1819 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1821 #undef TARGET_OPTION_OVERRIDE
1822 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1824 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1825 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1826 rs6000_builtin_vectorized_function
1828 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1829 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1830 rs6000_builtin_md_vectorized_function
1832 #undef TARGET_STACK_PROTECT_GUARD
1833 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1836 #undef TARGET_STACK_PROTECT_FAIL
1837 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1841 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1842 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1845 /* Use a 32-bit anchor range. This leads to sequences like:
1847 addis tmp,anchor,high
1850 where tmp itself acts as an anchor, and can be shared between
1851 accesses to the same 64k page. */
1852 #undef TARGET_MIN_ANCHOR_OFFSET
1853 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1854 #undef TARGET_MAX_ANCHOR_OFFSET
1855 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1856 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1857 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1858 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1859 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1861 #undef TARGET_BUILTIN_RECIPROCAL
1862 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1864 #undef TARGET_SECONDARY_RELOAD
1865 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1866 #undef TARGET_SECONDARY_MEMORY_NEEDED
1867 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1868 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1869 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1871 #undef TARGET_LEGITIMATE_ADDRESS_P
1872 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1874 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1875 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1877 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1878 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1880 #undef TARGET_CAN_ELIMINATE
1881 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1883 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1884 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1886 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1887 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1889 #undef TARGET_TRAMPOLINE_INIT
1890 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1892 #undef TARGET_FUNCTION_VALUE
1893 #define TARGET_FUNCTION_VALUE rs6000_function_value
1895 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1896 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1898 #undef TARGET_OPTION_SAVE
1899 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1901 #undef TARGET_OPTION_RESTORE
1902 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1904 #undef TARGET_OPTION_PRINT
1905 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1907 #undef TARGET_CAN_INLINE_P
1908 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1910 #undef TARGET_SET_CURRENT_FUNCTION
1911 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1913 #undef TARGET_LEGITIMATE_CONSTANT_P
1914 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1916 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1917 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1919 #undef TARGET_CAN_USE_DOLOOP_P
1920 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1922 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1923 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1925 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1926 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1927 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1928 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1929 #undef TARGET_UNWIND_WORD_MODE
1930 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1932 #undef TARGET_OFFLOAD_OPTIONS
1933 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1935 #undef TARGET_C_MODE_FOR_SUFFIX
1936 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1938 #undef TARGET_INVALID_BINARY_OP
1939 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1941 #undef TARGET_OPTAB_SUPPORTED_P
1942 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1944 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1945 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1947 #undef TARGET_COMPARE_VERSION_PRIORITY
1948 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1950 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1951 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1952 rs6000_generate_version_dispatcher_body
1954 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1955 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1956 rs6000_get_function_versions_dispatcher
1958 #undef TARGET_OPTION_FUNCTION_VERSIONS
1959 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1961 #undef TARGET_HARD_REGNO_NREGS
1962 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1963 #undef TARGET_HARD_REGNO_MODE_OK
1964 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1966 #undef TARGET_MODES_TIEABLE_P
1967 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1969 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1970 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1971 rs6000_hard_regno_call_part_clobbered
1973 #undef TARGET_SLOW_UNALIGNED_ACCESS
1974 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1976 #undef TARGET_CAN_CHANGE_MODE_CLASS
1977 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1979 #undef TARGET_CONSTANT_ALIGNMENT
1980 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1982 #undef TARGET_STARTING_FRAME_OFFSET
1983 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1985 #if TARGET_ELF && RS6000_WEAK
1986 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1987 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1991 /* Processor table. */
1994 const char *const name; /* Canonical processor name. */
1995 const enum processor_type processor; /* Processor type enum value. */
1996 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1999 static struct rs6000_ptt const processor_target_table[] =
2001 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2002 #include "rs6000-cpus.def"
2006 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2010 rs6000_cpu_name_lookup (const char *name)
2016 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2017 if (! strcmp (name, processor_target_table[i].name))
2025 /* Return number of consecutive hard regs needed starting at reg REGNO
2026 to hold something of mode MODE.
2027 This is ordinarily the length in words of a value of mode MODE
2028 but can be less for certain modes in special long registers.
2030 POWER and PowerPC GPRs hold 32 bits worth;
2031 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2034 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2036 unsigned HOST_WIDE_INT reg_size;
2038 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2039 128-bit floating point that can go in vector registers, which has VSX
2040 memory addressing. */
2041 if (FP_REGNO_P (regno))
2042 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2043 ? UNITS_PER_VSX_WORD
2044 : UNITS_PER_FP_WORD);
2046 else if (ALTIVEC_REGNO_P (regno))
2047 reg_size = UNITS_PER_ALTIVEC_WORD;
2050 reg_size = UNITS_PER_WORD;
2052 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2055 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2058 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2060 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2062 if (COMPLEX_MODE_P (mode))
2063 mode = GET_MODE_INNER (mode);
2065 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2066 register combinations, and use PTImode where we need to deal with quad
2067 word memory operations. Don't allow quad words in the argument or frame
2068 pointer registers, just registers 0..31. */
2069 if (mode == PTImode)
2070 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2071 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2072 && ((regno & 1) == 0));
2074 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2075 implementations. Don't allow an item to be split between a FP register
2076 and an Altivec register. Allow TImode in all VSX registers if the user
2078 if (TARGET_VSX && VSX_REGNO_P (regno)
2079 && (VECTOR_MEM_VSX_P (mode)
2080 || FLOAT128_VECTOR_P (mode)
2081 || reg_addr[mode].scalar_in_vmx_p
2083 || (TARGET_VADDUQM && mode == V1TImode)))
2085 if (FP_REGNO_P (regno))
2086 return FP_REGNO_P (last_regno);
2088 if (ALTIVEC_REGNO_P (regno))
2090 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2093 return ALTIVEC_REGNO_P (last_regno);
2097 /* The GPRs can hold any mode, but values bigger than one register
2098 cannot go past R31. */
2099 if (INT_REGNO_P (regno))
2100 return INT_REGNO_P (last_regno);
2102 /* The float registers (except for VSX vector modes) can only hold floating
2103 modes and DImode. */
2104 if (FP_REGNO_P (regno))
2106 if (FLOAT128_VECTOR_P (mode))
2109 if (SCALAR_FLOAT_MODE_P (mode)
2110 && (mode != TDmode || (regno % 2) == 0)
2111 && FP_REGNO_P (last_regno))
2114 if (GET_MODE_CLASS (mode) == MODE_INT)
2116 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2119 if (TARGET_P8_VECTOR && (mode == SImode))
2122 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2129 /* The CR register can only hold CC modes. */
2130 if (CR_REGNO_P (regno))
2131 return GET_MODE_CLASS (mode) == MODE_CC;
2133 if (CA_REGNO_P (regno))
2134 return mode == Pmode || mode == SImode;
2136 /* AltiVec only in AldyVec registers. */
2137 if (ALTIVEC_REGNO_P (regno))
2138 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2139 || mode == V1TImode);
2141 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2142 and it must be able to fit within the register set. */
2144 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2147 /* Implement TARGET_HARD_REGNO_NREGS. */
2150 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2152 return rs6000_hard_regno_nregs[mode][regno];
2155 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2158 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2160 return rs6000_hard_regno_mode_ok_p[mode][regno];
2163 /* Implement TARGET_MODES_TIEABLE_P.
2165 PTImode cannot tie with other modes because PTImode is restricted to even
2166 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2169 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2170 128-bit floating point on VSX systems ties with other vectors. */
2173 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2175 if (mode1 == PTImode)
2176 return mode2 == PTImode;
2177 if (mode2 == PTImode)
2180 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2181 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2182 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2185 if (SCALAR_FLOAT_MODE_P (mode1))
2186 return SCALAR_FLOAT_MODE_P (mode2);
2187 if (SCALAR_FLOAT_MODE_P (mode2))
2190 if (GET_MODE_CLASS (mode1) == MODE_CC)
2191 return GET_MODE_CLASS (mode2) == MODE_CC;
2192 if (GET_MODE_CLASS (mode2) == MODE_CC)
2198 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2201 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2205 && GET_MODE_SIZE (mode) > 4
2206 && INT_REGNO_P (regno))
2210 && FP_REGNO_P (regno)
2211 && GET_MODE_SIZE (mode) > 8
2212 && !FLOAT128_2REG_P (mode))
2218 /* Print interesting facts about registers. */
2220 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2224 for (r = first_regno; r <= last_regno; ++r)
2226 const char *comma = "";
2229 if (first_regno == last_regno)
2230 fprintf (stderr, "%s:\t", reg_name);
2232 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2235 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2236 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2240 fprintf (stderr, ",\n\t");
2245 if (rs6000_hard_regno_nregs[m][r] > 1)
2246 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2247 rs6000_hard_regno_nregs[m][r]);
2249 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2254 if (call_used_regs[r])
2258 fprintf (stderr, ",\n\t");
2263 len += fprintf (stderr, "%s%s", comma, "call-used");
2271 fprintf (stderr, ",\n\t");
2276 len += fprintf (stderr, "%s%s", comma, "fixed");
2282 fprintf (stderr, ",\n\t");
2286 len += fprintf (stderr, "%sreg-class = %s", comma,
2287 reg_class_names[(int)rs6000_regno_regclass[r]]);
2292 fprintf (stderr, ",\n\t");
2296 fprintf (stderr, "%sregno = %d\n", comma, r);
2301 rs6000_debug_vector_unit (enum rs6000_vector v)
2307 case VECTOR_NONE: ret = "none"; break;
2308 case VECTOR_ALTIVEC: ret = "altivec"; break;
2309 case VECTOR_VSX: ret = "vsx"; break;
2310 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2311 case VECTOR_OTHER: ret = "other"; break;
2312 default: ret = "unknown"; break;
2318 /* Inner function printing just the address mask for a particular reload
2320 DEBUG_FUNCTION char *
2321 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2326 if ((mask & RELOAD_REG_VALID) != 0)
2328 else if (keep_spaces)
2331 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2333 else if (keep_spaces)
2336 if ((mask & RELOAD_REG_INDEXED) != 0)
2338 else if (keep_spaces)
2341 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2343 else if ((mask & RELOAD_REG_OFFSET) != 0)
2345 else if (keep_spaces)
2348 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2350 else if (keep_spaces)
2353 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2355 else if (keep_spaces)
2358 if ((mask & RELOAD_REG_AND_M16) != 0)
2360 else if (keep_spaces)
2368 /* Print the address masks in a human readble fashion. */
2370 rs6000_debug_print_mode (ssize_t m)
2376 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2377 for (rc = 0; rc < N_RELOAD_REG; rc++)
2378 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2379 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2381 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2382 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2383 fprintf (stderr, " Reload=%c%c",
2384 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2385 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2387 spaces += sizeof (" Reload=sl") - 1;
2389 if (reg_addr[m].scalar_in_vmx_p)
2391 fprintf (stderr, "%*s Upper=y", spaces, "");
2395 spaces += sizeof (" Upper=y") - 1;
2397 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2398 || reg_addr[m].fused_toc);
2401 for (rc = 0; rc < N_RELOAD_REG; rc++)
2403 if (rc != RELOAD_REG_ANY)
2405 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2406 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2407 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2408 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2411 fuse_extra_p = true;
2420 fprintf (stderr, "%*s Fuse:", spaces, "");
2423 for (rc = 0; rc < N_RELOAD_REG; rc++)
2425 if (rc != RELOAD_REG_ANY)
2429 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2431 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2436 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2438 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2443 if (load == '-' && store == '-')
2447 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2448 reload_reg_map[rc].name[0], load, store);
2454 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2456 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2460 spaces += sizeof (" P8gpr") - 1;
2462 if (reg_addr[m].fused_toc)
2464 fprintf (stderr, "%*sToc", (spaces + 1), "");
2468 spaces += sizeof (" Toc") - 1;
2471 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2473 if (rs6000_vector_unit[m] != VECTOR_NONE
2474 || rs6000_vector_mem[m] != VECTOR_NONE)
2476 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2478 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2479 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2482 fputs ("\n", stderr);
2485 #define DEBUG_FMT_ID "%-32s= "
2486 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2487 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2488 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2490 /* Print various interesting information with -mdebug=reg. */
2492 rs6000_debug_reg_global (void)
2494 static const char *const tf[2] = { "false", "true" };
2495 const char *nl = (const char *)0;
2498 char costly_num[20];
2500 char flags_buffer[40];
2501 const char *costly_str;
2502 const char *nop_str;
2503 const char *trace_str;
2504 const char *abi_str;
2505 const char *cmodel_str;
2506 struct cl_target_option cl_opts;
2508 /* Modes we want tieable information on. */
2509 static const machine_mode print_tieable_modes[] = {
2543 /* Virtual regs we are interested in. */
2544 const static struct {
2545 int regno; /* register number. */
2546 const char *name; /* register name. */
2547 } virtual_regs[] = {
2548 { STACK_POINTER_REGNUM, "stack pointer:" },
2549 { TOC_REGNUM, "toc: " },
2550 { STATIC_CHAIN_REGNUM, "static chain: " },
2551 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2552 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2553 { ARG_POINTER_REGNUM, "arg pointer: " },
2554 { FRAME_POINTER_REGNUM, "frame pointer:" },
2555 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2556 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2557 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2558 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2559 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2560 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2561 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2562 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2563 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2566 fputs ("\nHard register information:\n", stderr);
2567 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2568 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2569 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2572 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2573 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2574 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2575 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2576 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2577 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2579 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2580 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2581 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2585 "d reg_class = %s\n"
2586 "f reg_class = %s\n"
2587 "v reg_class = %s\n"
2588 "wa reg_class = %s\n"
2589 "wb reg_class = %s\n"
2590 "wd reg_class = %s\n"
2591 "we reg_class = %s\n"
2592 "wf reg_class = %s\n"
2593 "wg reg_class = %s\n"
2594 "wh reg_class = %s\n"
2595 "wi reg_class = %s\n"
2596 "wj reg_class = %s\n"
2597 "wk reg_class = %s\n"
2598 "wl reg_class = %s\n"
2599 "wm reg_class = %s\n"
2600 "wo reg_class = %s\n"
2601 "wp reg_class = %s\n"
2602 "wq reg_class = %s\n"
2603 "wr reg_class = %s\n"
2604 "ws reg_class = %s\n"
2605 "wt reg_class = %s\n"
2606 "wu reg_class = %s\n"
2607 "wv reg_class = %s\n"
2608 "ww reg_class = %s\n"
2609 "wx reg_class = %s\n"
2610 "wy reg_class = %s\n"
2611 "wz reg_class = %s\n"
2612 "wA reg_class = %s\n"
2613 "wH reg_class = %s\n"
2614 "wI reg_class = %s\n"
2615 "wJ reg_class = %s\n"
2616 "wK reg_class = %s\n"
2618 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2619 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2620 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2621 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2622 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2652 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2653 rs6000_debug_print_mode (m);
2655 fputs ("\n", stderr);
2657 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2659 machine_mode mode1 = print_tieable_modes[m1];
2660 bool first_time = true;
2662 nl = (const char *)0;
2663 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2665 machine_mode mode2 = print_tieable_modes[m2];
2666 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2670 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2675 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2680 fputs ("\n", stderr);
2686 if (rs6000_recip_control)
2688 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2690 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2691 if (rs6000_recip_bits[m])
2694 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2696 (RS6000_RECIP_AUTO_RE_P (m)
2698 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2699 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2701 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2704 fputs ("\n", stderr);
2707 if (rs6000_cpu_index >= 0)
2709 const char *name = processor_target_table[rs6000_cpu_index].name;
2711 = processor_target_table[rs6000_cpu_index].target_enable;
2713 sprintf (flags_buffer, "-mcpu=%s flags", name);
2714 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2717 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2719 if (rs6000_tune_index >= 0)
2721 const char *name = processor_target_table[rs6000_tune_index].name;
2723 = processor_target_table[rs6000_tune_index].target_enable;
2725 sprintf (flags_buffer, "-mtune=%s flags", name);
2726 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2729 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2731 cl_target_option_save (&cl_opts, &global_options);
2732 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2735 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2736 rs6000_isa_flags_explicit);
2738 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2739 rs6000_builtin_mask);
2741 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2743 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2744 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2746 switch (rs6000_sched_costly_dep)
2748 case max_dep_latency:
2749 costly_str = "max_dep_latency";
2753 costly_str = "no_dep_costly";
2756 case all_deps_costly:
2757 costly_str = "all_deps_costly";
2760 case true_store_to_load_dep_costly:
2761 costly_str = "true_store_to_load_dep_costly";
2764 case store_to_load_dep_costly:
2765 costly_str = "store_to_load_dep_costly";
2769 costly_str = costly_num;
2770 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2774 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2776 switch (rs6000_sched_insert_nops)
2778 case sched_finish_regroup_exact:
2779 nop_str = "sched_finish_regroup_exact";
2782 case sched_finish_pad_groups:
2783 nop_str = "sched_finish_pad_groups";
2786 case sched_finish_none:
2787 nop_str = "sched_finish_none";
2792 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2796 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2798 switch (rs6000_sdata)
2805 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2809 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2813 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2818 switch (rs6000_traceback)
2820 case traceback_default: trace_str = "default"; break;
2821 case traceback_none: trace_str = "none"; break;
2822 case traceback_part: trace_str = "part"; break;
2823 case traceback_full: trace_str = "full"; break;
2824 default: trace_str = "unknown"; break;
2827 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2829 switch (rs6000_current_cmodel)
2831 case CMODEL_SMALL: cmodel_str = "small"; break;
2832 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2833 case CMODEL_LARGE: cmodel_str = "large"; break;
2834 default: cmodel_str = "unknown"; break;
2837 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2839 switch (rs6000_current_abi)
2841 case ABI_NONE: abi_str = "none"; break;
2842 case ABI_AIX: abi_str = "aix"; break;
2843 case ABI_ELFv2: abi_str = "ELFv2"; break;
2844 case ABI_V4: abi_str = "V4"; break;
2845 case ABI_DARWIN: abi_str = "darwin"; break;
2846 default: abi_str = "unknown"; break;
2849 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2851 if (rs6000_altivec_abi)
2852 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2854 if (rs6000_darwin64_abi)
2855 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2857 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2858 (TARGET_SOFT_FLOAT ? "true" : "false"));
2860 if (TARGET_LINK_STACK)
2861 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2863 if (TARGET_P8_FUSION)
2867 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2868 if (TARGET_TOC_FUSION)
2869 strcat (options, ", toc");
2871 if (TARGET_P8_FUSION_SIGN)
2872 strcat (options, ", sign");
2874 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2877 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2878 TARGET_SECURE_PLT ? "secure" : "bss");
2879 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2880 aix_struct_return ? "aix" : "sysv");
2881 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2882 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2883 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2884 tf[!!rs6000_align_branch_targets]);
2885 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2886 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2887 rs6000_long_double_type_size);
2888 if (rs6000_long_double_type_size == 128)
2890 fprintf (stderr, DEBUG_FMT_S, "long double type",
2891 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2892 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2893 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2895 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2896 (int)rs6000_sched_restricted_insns_priority);
2897 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2899 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2900 (int)RS6000_BUILTIN_COUNT);
2902 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2903 (int)TARGET_FLOAT128_ENABLE_TYPE);
2906 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2907 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2909 if (TARGET_DIRECT_MOVE_128)
2910 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2911 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2915 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2916 legitimate address support to figure out the appropriate addressing to
2920 rs6000_setup_reg_addr_masks (void)
2922 ssize_t rc, reg, m, nregs;
2923 addr_mask_type any_addr_mask, addr_mask;
2925 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2927 machine_mode m2 = (machine_mode) m;
2928 bool complex_p = false;
2929 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2932 if (COMPLEX_MODE_P (m2))
2935 m2 = GET_MODE_INNER (m2);
2938 msize = GET_MODE_SIZE (m2);
2940 /* SDmode is special in that we want to access it only via REG+REG
2941 addressing on power7 and above, since we want to use the LFIWZX and
2942 STFIWZX instructions to load it. */
2943 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2946 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2949 reg = reload_reg_map[rc].reg;
2951 /* Can mode values go in the GPR/FPR/Altivec registers? */
2952 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2954 bool small_int_vsx_p = (small_int_p
2955 && (rc == RELOAD_REG_FPR
2956 || rc == RELOAD_REG_VMX));
2958 nregs = rs6000_hard_regno_nregs[m][reg];
2959 addr_mask |= RELOAD_REG_VALID;
2961 /* Indicate if the mode takes more than 1 physical register. If
2962 it takes a single register, indicate it can do REG+REG
2963 addressing. Small integers in VSX registers can only do
2964 REG+REG addressing. */
2965 if (small_int_vsx_p)
2966 addr_mask |= RELOAD_REG_INDEXED;
2967 else if (nregs > 1 || m == BLKmode || complex_p)
2968 addr_mask |= RELOAD_REG_MULTIPLE;
2970 addr_mask |= RELOAD_REG_INDEXED;
2972 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2973 addressing. If we allow scalars into Altivec registers,
2974 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2976 For VSX systems, we don't allow update addressing for
2977 DFmode/SFmode if those registers can go in both the
2978 traditional floating point registers and Altivec registers.
2979 The load/store instructions for the Altivec registers do not
2980 have update forms. If we allowed update addressing, it seems
2981 to break IV-OPT code using floating point if the index type is
2982 int instead of long (PR target/81550 and target/84042). */
2985 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2987 && !VECTOR_MODE_P (m2)
2988 && !FLOAT128_VECTOR_P (m2)
2990 && (m != E_DFmode || !TARGET_VSX)
2991 && (m != E_SFmode || !TARGET_P8_VECTOR)
2992 && !small_int_vsx_p)
2994 addr_mask |= RELOAD_REG_PRE_INCDEC;
2996 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2997 we don't allow PRE_MODIFY for some multi-register
3002 addr_mask |= RELOAD_REG_PRE_MODIFY;
3006 if (TARGET_POWERPC64)
3007 addr_mask |= RELOAD_REG_PRE_MODIFY;
3012 if (TARGET_HARD_FLOAT)
3013 addr_mask |= RELOAD_REG_PRE_MODIFY;
3019 /* GPR and FPR registers can do REG+OFFSET addressing, except
3020 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3021 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3022 if ((addr_mask != 0) && !indexed_only_p
3024 && (rc == RELOAD_REG_GPR
3025 || ((msize == 8 || m2 == SFmode)
3026 && (rc == RELOAD_REG_FPR
3027 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3028 addr_mask |= RELOAD_REG_OFFSET;
3030 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3031 instructions are enabled. The offset for 128-bit VSX registers is
3032 only 12-bits. While GPRs can handle the full offset range, VSX
3033 registers can only handle the restricted range. */
3034 else if ((addr_mask != 0) && !indexed_only_p
3035 && msize == 16 && TARGET_P9_VECTOR
3036 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3037 || (m2 == TImode && TARGET_VSX)))
3039 addr_mask |= RELOAD_REG_OFFSET;
3040 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3041 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3044 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3045 addressing on 128-bit types. */
3046 if (rc == RELOAD_REG_VMX && msize == 16
3047 && (addr_mask & RELOAD_REG_VALID) != 0)
3048 addr_mask |= RELOAD_REG_AND_M16;
3050 reg_addr[m].addr_mask[rc] = addr_mask;
3051 any_addr_mask |= addr_mask;
3054 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3059 /* Initialize the various global tables that are based on register size. */
3061 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3067 /* Precalculate REGNO_REG_CLASS. */
3068 rs6000_regno_regclass[0] = GENERAL_REGS;
3069 for (r = 1; r < 32; ++r)
3070 rs6000_regno_regclass[r] = BASE_REGS;
3072 for (r = 32; r < 64; ++r)
3073 rs6000_regno_regclass[r] = FLOAT_REGS;
3075 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3076 rs6000_regno_regclass[r] = NO_REGS;
3078 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3079 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3081 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3082 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3083 rs6000_regno_regclass[r] = CR_REGS;
3085 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3086 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3087 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3088 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3089 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3090 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3091 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3092 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3093 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3094 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3096 /* Precalculate register class to simpler reload register class. We don't
3097 need all of the register classes that are combinations of different
3098 classes, just the simple ones that have constraint letters. */
3099 for (c = 0; c < N_REG_CLASSES; c++)
3100 reg_class_to_reg_type[c] = NO_REG_TYPE;
3102 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3103 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3104 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3105 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3106 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3107 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3108 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3109 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3110 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3111 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3115 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3116 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3120 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3121 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3124 /* Precalculate the valid memory formats as well as the vector information,
3125 this must be set up before the rs6000_hard_regno_nregs_internal calls
3127 gcc_assert ((int)VECTOR_NONE == 0);
3128 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3129 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3131 gcc_assert ((int)CODE_FOR_nothing == 0);
3132 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3134 gcc_assert ((int)NO_REGS == 0);
3135 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3137 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3138 believes it can use native alignment or still uses 128-bit alignment. */
3139 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3150 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3151 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3152 if (TARGET_FLOAT128_TYPE)
3154 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3155 rs6000_vector_align[KFmode] = 128;
3157 if (FLOAT128_IEEE_P (TFmode))
3159 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3160 rs6000_vector_align[TFmode] = 128;
3164 /* V2DF mode, VSX only. */
3167 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3168 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3169 rs6000_vector_align[V2DFmode] = align64;
3172 /* V4SF mode, either VSX or Altivec. */
3175 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3176 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3177 rs6000_vector_align[V4SFmode] = align32;
3179 else if (TARGET_ALTIVEC)
3181 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3182 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3183 rs6000_vector_align[V4SFmode] = align32;
3186 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3190 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3191 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3192 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3193 rs6000_vector_align[V4SImode] = align32;
3194 rs6000_vector_align[V8HImode] = align32;
3195 rs6000_vector_align[V16QImode] = align32;
3199 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3200 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3201 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3205 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3206 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3207 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3211 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3212 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3215 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3216 rs6000_vector_unit[V2DImode]
3217 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3218 rs6000_vector_align[V2DImode] = align64;
3220 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3221 rs6000_vector_unit[V1TImode]
3222 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3223 rs6000_vector_align[V1TImode] = 128;
3226 /* DFmode, see if we want to use the VSX unit. Memory is handled
3227 differently, so don't set rs6000_vector_mem. */
3230 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3231 rs6000_vector_align[DFmode] = 64;
3234 /* SFmode, see if we want to use the VSX unit. */
3235 if (TARGET_P8_VECTOR)
3237 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3238 rs6000_vector_align[SFmode] = 32;
3241 /* Allow TImode in VSX register and set the VSX memory macros. */
3244 rs6000_vector_mem[TImode] = VECTOR_VSX;
3245 rs6000_vector_align[TImode] = align64;
3248 /* Register class constraints for the constraints that depend on compile
3249 switches. When the VSX code was added, different constraints were added
3250 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3251 of the VSX registers are used. The register classes for scalar floating
3252 point types is set, based on whether we allow that type into the upper
3253 (Altivec) registers. GCC has register classes to target the Altivec
3254 registers for load/store operations, to select using a VSX memory
3255 operation instead of the traditional floating point operation. The
3258 d - Register class to use with traditional DFmode instructions.
3259 f - Register class to use with traditional SFmode instructions.
3260 v - Altivec register.
3261 wa - Any VSX register.
3262 wc - Reserved to represent individual CR bits (used in LLVM).
3263 wd - Preferred register class for V2DFmode.
3264 wf - Preferred register class for V4SFmode.
3265 wg - Float register for power6x move insns.
3266 wh - FP register for direct move instructions.
3267 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3268 wj - FP or VSX register to hold 64-bit integers for direct moves.
3269 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3270 wl - Float register if we can do 32-bit signed int loads.
3271 wm - VSX register for ISA 2.07 direct move operations.
3272 wn - always NO_REGS.
3273 wr - GPR if 64-bit mode is permitted.
3274 ws - Register class to do ISA 2.06 DF operations.
3275 wt - VSX register for TImode in VSX registers.
3276 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3277 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3278 ww - Register class to do SF conversions in with VSX operations.
3279 wx - Float register if we can do 32-bit int stores.
3280 wy - Register class to do ISA 2.07 SF operations.
3281 wz - Float register if we can do 32-bit unsigned int loads.
3282 wH - Altivec register if SImode is allowed in VSX registers.
3283 wI - VSX register if SImode is allowed in VSX registers.
3284 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3285 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3287 if (TARGET_HARD_FLOAT)
3289 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3290 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3295 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3296 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3297 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3298 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3299 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3300 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3301 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3304 /* Add conditional constraints based on various options, to allow us to
3305 collapse multiple insn patterns. */
3307 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3309 if (TARGET_MFPGPR) /* DFmode */
3310 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3313 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3315 if (TARGET_DIRECT_MOVE)
3317 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3318 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3319 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3320 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3321 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3322 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3325 if (TARGET_POWERPC64)
3327 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3328 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3331 if (TARGET_P8_VECTOR) /* SFmode */
3333 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3334 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3335 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3337 else if (TARGET_VSX)
3338 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3341 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3344 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3346 if (TARGET_FLOAT128_TYPE)
3348 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3349 if (FLOAT128_IEEE_P (TFmode))
3350 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3353 if (TARGET_P9_VECTOR)
3355 /* Support for new D-form instructions. */
3356 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3358 /* Support for ISA 3.0 (power9) vectors. */
3359 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3362 /* Support for new direct moves (ISA 3.0 + 64bit). */
3363 if (TARGET_DIRECT_MOVE_128)
3364 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3366 /* Support small integers in VSX registers. */
3367 if (TARGET_P8_VECTOR)
3369 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3370 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3371 if (TARGET_P9_VECTOR)
3373 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3374 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3378 /* Set up the reload helper and direct move functions. */
3379 if (TARGET_VSX || TARGET_ALTIVEC)
3383 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3384 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3385 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3386 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3387 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3388 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3389 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3390 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3391 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3392 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3393 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3394 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3395 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3396 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3397 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3398 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3399 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3400 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3401 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3402 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3404 if (FLOAT128_VECTOR_P (KFmode))
3406 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3407 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3410 if (FLOAT128_VECTOR_P (TFmode))
3412 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3413 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3416 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3418 if (TARGET_NO_SDMODE_STACK)
3420 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3421 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3426 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3427 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3430 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3432 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3433 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3434 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3435 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3436 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3437 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3438 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3439 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3440 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3442 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3443 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3444 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3445 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3446 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3447 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3448 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3449 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3450 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3452 if (FLOAT128_VECTOR_P (KFmode))
3454 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3455 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3458 if (FLOAT128_VECTOR_P (TFmode))
3460 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3461 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3467 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3468 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3469 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3470 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3471 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3472 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3473 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3474 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3475 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3476 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3477 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3478 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3479 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3480 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3481 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3482 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3483 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3484 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3485 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3486 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3488 if (FLOAT128_VECTOR_P (KFmode))
3490 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3491 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3494 if (FLOAT128_IEEE_P (TFmode))
3496 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3497 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3500 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3502 if (TARGET_NO_SDMODE_STACK)
3504 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3505 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3510 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3511 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3514 if (TARGET_DIRECT_MOVE)
3516 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3517 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3518 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3522 reg_addr[DFmode].scalar_in_vmx_p = true;
3523 reg_addr[DImode].scalar_in_vmx_p = true;
3525 if (TARGET_P8_VECTOR)
3527 reg_addr[SFmode].scalar_in_vmx_p = true;
3528 reg_addr[SImode].scalar_in_vmx_p = true;
3530 if (TARGET_P9_VECTOR)
3532 reg_addr[HImode].scalar_in_vmx_p = true;
3533 reg_addr[QImode].scalar_in_vmx_p = true;
3538 /* Setup the fusion operations. */
3539 if (TARGET_P8_FUSION)
3541 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3542 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3543 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3545 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3548 if (TARGET_P9_FUSION)
3551 enum machine_mode mode; /* mode of the fused type. */
3552 enum machine_mode pmode; /* pointer mode. */
3553 enum rs6000_reload_reg_type rtype; /* register type. */
3554 enum insn_code load; /* load insn. */
3555 enum insn_code store; /* store insn. */
3558 static const struct fuse_insns addis_insns[] = {
3559 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3560 CODE_FOR_fusion_vsx_di_sf_load,
3561 CODE_FOR_fusion_vsx_di_sf_store },
3563 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3564 CODE_FOR_fusion_vsx_si_sf_load,
3565 CODE_FOR_fusion_vsx_si_sf_store },
3567 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3568 CODE_FOR_fusion_vsx_di_df_load,
3569 CODE_FOR_fusion_vsx_di_df_store },
3571 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3572 CODE_FOR_fusion_vsx_si_df_load,
3573 CODE_FOR_fusion_vsx_si_df_store },
3575 { E_DImode, E_DImode, RELOAD_REG_FPR,
3576 CODE_FOR_fusion_vsx_di_di_load,
3577 CODE_FOR_fusion_vsx_di_di_store },
3579 { E_DImode, E_SImode, RELOAD_REG_FPR,
3580 CODE_FOR_fusion_vsx_si_di_load,
3581 CODE_FOR_fusion_vsx_si_di_store },
3583 { E_QImode, E_DImode, RELOAD_REG_GPR,
3584 CODE_FOR_fusion_gpr_di_qi_load,
3585 CODE_FOR_fusion_gpr_di_qi_store },
3587 { E_QImode, E_SImode, RELOAD_REG_GPR,
3588 CODE_FOR_fusion_gpr_si_qi_load,
3589 CODE_FOR_fusion_gpr_si_qi_store },
3591 { E_HImode, E_DImode, RELOAD_REG_GPR,
3592 CODE_FOR_fusion_gpr_di_hi_load,
3593 CODE_FOR_fusion_gpr_di_hi_store },
3595 { E_HImode, E_SImode, RELOAD_REG_GPR,
3596 CODE_FOR_fusion_gpr_si_hi_load,
3597 CODE_FOR_fusion_gpr_si_hi_store },
3599 { E_SImode, E_DImode, RELOAD_REG_GPR,
3600 CODE_FOR_fusion_gpr_di_si_load,
3601 CODE_FOR_fusion_gpr_di_si_store },
3603 { E_SImode, E_SImode, RELOAD_REG_GPR,
3604 CODE_FOR_fusion_gpr_si_si_load,
3605 CODE_FOR_fusion_gpr_si_si_store },
3607 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3608 CODE_FOR_fusion_gpr_di_sf_load,
3609 CODE_FOR_fusion_gpr_di_sf_store },
3611 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3612 CODE_FOR_fusion_gpr_si_sf_load,
3613 CODE_FOR_fusion_gpr_si_sf_store },
3615 { E_DImode, E_DImode, RELOAD_REG_GPR,
3616 CODE_FOR_fusion_gpr_di_di_load,
3617 CODE_FOR_fusion_gpr_di_di_store },
3619 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3620 CODE_FOR_fusion_gpr_di_df_load,
3621 CODE_FOR_fusion_gpr_di_df_store },
3624 machine_mode cur_pmode = Pmode;
3627 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3629 machine_mode xmode = addis_insns[i].mode;
3630 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3632 if (addis_insns[i].pmode != cur_pmode)
3635 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3638 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3639 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3641 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3643 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3644 = addis_insns[i].load;
3645 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3646 = addis_insns[i].store;
3651 /* Note which types we support fusing TOC setup plus memory insn. We only do
3652 fused TOCs for medium/large code models. */
3653 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3654 && (TARGET_CMODEL != CMODEL_SMALL))
3656 reg_addr[QImode].fused_toc = true;
3657 reg_addr[HImode].fused_toc = true;
3658 reg_addr[SImode].fused_toc = true;
3659 reg_addr[DImode].fused_toc = true;
3660 if (TARGET_HARD_FLOAT)
3662 reg_addr[SFmode].fused_toc = true;
3663 reg_addr[DFmode].fused_toc = true;
3667 /* Precalculate HARD_REGNO_NREGS. */
3668 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3669 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3670 rs6000_hard_regno_nregs[m][r]
3671 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3673 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3674 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3675 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3676 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3677 rs6000_hard_regno_mode_ok_p[m][r] = true;
3679 /* Precalculate CLASS_MAX_NREGS sizes. */
3680 for (c = 0; c < LIM_REG_CLASSES; ++c)
3684 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3685 reg_size = UNITS_PER_VSX_WORD;
3687 else if (c == ALTIVEC_REGS)
3688 reg_size = UNITS_PER_ALTIVEC_WORD;
3690 else if (c == FLOAT_REGS)
3691 reg_size = UNITS_PER_FP_WORD;
3694 reg_size = UNITS_PER_WORD;
3696 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3698 machine_mode m2 = (machine_mode)m;
3699 int reg_size2 = reg_size;
3701 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3703 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3704 reg_size2 = UNITS_PER_FP_WORD;
3706 rs6000_class_max_nregs[m][c]
3707 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3711 /* Calculate which modes to automatically generate code to use a the
3712 reciprocal divide and square root instructions. In the future, possibly
3713 automatically generate the instructions even if the user did not specify
3714 -mrecip. The older machines double precision reciprocal sqrt estimate is
3715 not accurate enough. */
3716 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3718 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3720 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3721 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3722 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3723 if (VECTOR_UNIT_VSX_P (V2DFmode))
3724 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3726 if (TARGET_FRSQRTES)
3727 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3729 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3730 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3731 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3732 if (VECTOR_UNIT_VSX_P (V2DFmode))
3733 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3735 if (rs6000_recip_control)
3737 if (!flag_finite_math_only)
3738 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3740 if (flag_trapping_math)
3741 warning (0, "%qs requires %qs or %qs", "-mrecip",
3742 "-fno-trapping-math", "-ffast-math");
3743 if (!flag_reciprocal_math)
3744 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3746 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3748 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3749 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3750 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3752 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3753 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3754 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3756 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3757 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3758 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3760 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3761 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3762 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3764 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3765 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3766 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3768 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3769 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3770 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3772 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3773 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3774 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3776 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3777 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3778 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3782 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3783 legitimate address support to figure out the appropriate addressing to
3785 rs6000_setup_reg_addr_masks ();
3787 if (global_init_p || TARGET_DEBUG_TARGET)
3789 if (TARGET_DEBUG_REG)
3790 rs6000_debug_reg_global ();
3792 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3794 "SImode variable mult cost = %d\n"
3795 "SImode constant mult cost = %d\n"
3796 "SImode short constant mult cost = %d\n"
3797 "DImode multipliciation cost = %d\n"
3798 "SImode division cost = %d\n"
3799 "DImode division cost = %d\n"
3800 "Simple fp operation cost = %d\n"
3801 "DFmode multiplication cost = %d\n"
3802 "SFmode division cost = %d\n"
3803 "DFmode division cost = %d\n"
3804 "cache line size = %d\n"
3805 "l1 cache size = %d\n"
3806 "l2 cache size = %d\n"
3807 "simultaneous prefetches = %d\n"
3810 rs6000_cost->mulsi_const,
3811 rs6000_cost->mulsi_const9,
3819 rs6000_cost->cache_line_size,
3820 rs6000_cost->l1_cache_size,
3821 rs6000_cost->l2_cache_size,
3822 rs6000_cost->simultaneous_prefetches);
3827 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3830 darwin_rs6000_override_options (void)
3832 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3834 rs6000_altivec_abi = 1;
3835 TARGET_ALTIVEC_VRSAVE = 1;
3836 rs6000_current_abi = ABI_DARWIN;
3838 if (DEFAULT_ABI == ABI_DARWIN
3840 darwin_one_byte_bool = 1;
3842 if (TARGET_64BIT && ! TARGET_POWERPC64)
3844 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3845 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3849 rs6000_default_long_calls = 1;
3850 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3853 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3855 if (!flag_mkernel && !flag_apple_kext
3857 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3858 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3860 /* Unless the user (not the configurer) has explicitly overridden
3861 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3862 G4 unless targeting the kernel. */
3865 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3866 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3867 && ! global_options_set.x_rs6000_cpu_index)
3869 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3874 /* If not otherwise specified by a target, make 'long double' equivalent to
3877 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3878 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3881 /* Return the builtin mask of the various options used that could affect which
3882 builtins were used. In the past we used target_flags, but we've run out of
3883 bits, and some options are no longer in target_flags. */
3886 rs6000_builtin_mask_calculate (void)
3888 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3889 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3890 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3891 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3892 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3893 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3894 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3895 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3896 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3897 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3898 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3899 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3900 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3901 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3902 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3903 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3904 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3905 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3906 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3907 | ((TARGET_LONG_DOUBLE_128
3908 && TARGET_HARD_FLOAT
3909 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3910 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3911 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3914 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3915 to clobber the XER[CA] bit because clobbering that bit without telling
3916 the compiler worked just fine with versions of GCC before GCC 5, and
3917 breaking a lot of older code in ways that are hard to track down is
3918 not such a great idea. */
3921 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3922 vec<const char *> &/*constraints*/,
3923 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3925 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3926 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3930 /* Override command line options.
3932 Combine build-specific configuration information with options
3933 specified on the command line to set various state variables which
3934 influence code generation, optimization, and expansion of built-in
3935 functions. Assure that command-line configuration preferences are
3936 compatible with each other and with the build configuration; issue
3937 warnings while adjusting configuration or error messages while
3938 rejecting configuration.
3940 Upon entry to this function:
3942 This function is called once at the beginning of
3943 compilation, and then again at the start and end of compiling
3944 each section of code that has a different configuration, as
3945 indicated, for example, by adding the
3947 __attribute__((__target__("cpu=power9")))
3949 qualifier to a function definition or, for example, by bracketing
3952 #pragma GCC target("altivec")
3956 #pragma GCC reset_options
3958 directives. Parameter global_init_p is true for the initial
3959 invocation, which initializes global variables, and false for all
3960 subsequent invocations.
3963 Various global state information is assumed to be valid. This
3964 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3965 default CPU specified at build configure time, TARGET_DEFAULT,
3966 representing the default set of option flags for the default
3967 target, and global_options_set.x_rs6000_isa_flags, representing
3968 which options were requested on the command line.
3970 Upon return from this function:
3972 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3973 was set by name on the command line. Additionally, if certain
3974 attributes are automatically enabled or disabled by this function
3975 in order to assure compatibility between options and
3976 configuration, the flags associated with those attributes are
3977 also set. By setting these "explicit bits", we avoid the risk
3978 that other code might accidentally overwrite these particular
3979 attributes with "default values".
3981 The various bits of rs6000_isa_flags are set to indicate the
3982 target options that have been selected for the most current
3983 compilation efforts. This has the effect of also turning on the
3984 associated TARGET_XXX values since these are macros which are
3985 generally defined to test the corresponding bit of the
3986 rs6000_isa_flags variable.
3988 The variable rs6000_builtin_mask is set to represent the target
3989 options for the most current compilation efforts, consistent with
3990 the current contents of rs6000_isa_flags. This variable controls
3991 expansion of built-in functions.
3993 Various other global variables and fields of global structures
3994 (over 50 in all) are initialized to reflect the desired options
3995 for the most current compilation efforts. */
3998 rs6000_option_override_internal (bool global_init_p)
4002 HOST_WIDE_INT set_masks;
4003 HOST_WIDE_INT ignore_masks;
4006 struct cl_target_option *main_target_opt
4007 = ((global_init_p || target_option_default_node == NULL)
4008 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4010 /* Print defaults. */
4011 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4012 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4014 /* Remember the explicit arguments. */
4016 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4018 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4019 library functions, so warn about it. The flag may be useful for
4020 performance studies from time to time though, so don't disable it
4022 if (global_options_set.x_rs6000_alignment_flags
4023 && rs6000_alignment_flags == MASK_ALIGN_POWER
4024 && DEFAULT_ABI == ABI_DARWIN
4026 warning (0, "%qs is not supported for 64-bit Darwin;"
4027 " it is incompatible with the installed C and C++ libraries",
4030 /* Numerous experiment shows that IRA based loop pressure
4031 calculation works better for RTL loop invariant motion on targets
4032 with enough (>= 32) registers. It is an expensive optimization.
4033 So it is on only for peak performance. */
4034 if (optimize >= 3 && global_init_p
4035 && !global_options_set.x_flag_ira_loop_pressure)
4036 flag_ira_loop_pressure = 1;
4038 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4039 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4040 options were already specified. */
4041 if (flag_sanitize & SANITIZE_USER_ADDRESS
4042 && !global_options_set.x_flag_asynchronous_unwind_tables)
4043 flag_asynchronous_unwind_tables = 1;
4045 /* Set the pointer size. */
4048 rs6000_pmode = DImode;
4049 rs6000_pointer_size = 64;
4053 rs6000_pmode = SImode;
4054 rs6000_pointer_size = 32;
4057 /* Some OSs don't support saving the high part of 64-bit registers on context
4058 switch. Other OSs don't support saving Altivec registers. On those OSs,
4059 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4060 if the user wants either, the user must explicitly specify them and we
4061 won't interfere with the user's specification. */
4063 set_masks = POWERPC_MASKS;
4064 #ifdef OS_MISSING_POWERPC64
4065 if (OS_MISSING_POWERPC64)
4066 set_masks &= ~OPTION_MASK_POWERPC64;
4068 #ifdef OS_MISSING_ALTIVEC
4069 if (OS_MISSING_ALTIVEC)
4070 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4071 | OTHER_VSX_VECTOR_MASKS);
4074 /* Don't override by the processor default if given explicitly. */
4075 set_masks &= ~rs6000_isa_flags_explicit;
4077 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4078 the cpu in a target attribute or pragma, but did not specify a tuning
4079 option, use the cpu for the tuning option rather than the option specified
4080 with -mtune on the command line. Process a '--with-cpu' configuration
4081 request as an implicit --cpu. */
4082 if (rs6000_cpu_index >= 0)
4083 cpu_index = rs6000_cpu_index;
4084 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4085 cpu_index = main_target_opt->x_rs6000_cpu_index;
4086 else if (OPTION_TARGET_CPU_DEFAULT)
4087 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4091 const char *unavailable_cpu = NULL;
4092 switch (processor_target_table[cpu_index].processor)
4094 #ifndef HAVE_AS_POWER9
4095 case PROCESSOR_POWER9:
4096 unavailable_cpu = "power9";
4099 #ifndef HAVE_AS_POWER8
4100 case PROCESSOR_POWER8:
4101 unavailable_cpu = "power8";
4104 #ifndef HAVE_AS_POPCNTD
4105 case PROCESSOR_POWER7:
4106 unavailable_cpu = "power7";
4110 case PROCESSOR_POWER6:
4111 unavailable_cpu = "power6";
4114 #ifndef HAVE_AS_POPCNTB
4115 case PROCESSOR_POWER5:
4116 unavailable_cpu = "power5";
4122 if (unavailable_cpu)
4125 warning (0, "will not generate %qs instructions because "
4126 "assembler lacks %qs support", unavailable_cpu,
4131 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4132 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4133 with those from the cpu, except for options that were explicitly set. If
4134 we don't have a cpu, do not override the target bits set in
4138 rs6000_cpu_index = cpu_index;
4139 rs6000_isa_flags &= ~set_masks;
4140 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4145 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4146 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4147 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4148 to using rs6000_isa_flags, we need to do the initialization here.
4150 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4151 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4152 HOST_WIDE_INT flags;
4154 flags = TARGET_DEFAULT;
4157 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4158 const char *default_cpu = (!TARGET_POWERPC64
4163 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4164 flags = processor_target_table[default_cpu_index].target_enable;
4166 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4169 if (rs6000_tune_index >= 0)
4170 tune_index = rs6000_tune_index;
4171 else if (cpu_index >= 0)
4172 rs6000_tune_index = tune_index = cpu_index;
4176 enum processor_type tune_proc
4177 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4180 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4181 if (processor_target_table[i].processor == tune_proc)
4189 rs6000_cpu = processor_target_table[cpu_index].processor;
4191 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4193 gcc_assert (tune_index >= 0);
4194 rs6000_tune = processor_target_table[tune_index].processor;
4196 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4197 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4198 || rs6000_cpu == PROCESSOR_PPCE5500)
4201 error ("AltiVec not supported in this target");
4204 /* If we are optimizing big endian systems for space, use the load/store
4205 multiple instructions. */
4206 if (BYTES_BIG_ENDIAN && optimize_size)
4207 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
4209 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
4210 because the hardware doesn't support the instructions used in little
4211 endian mode, and causes an alignment trap. The 750 does not cause an
4212 alignment trap (except when the target is unaligned). */
4214 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
4216 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4217 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4218 warning (0, "%qs is not supported on little endian systems",
4222 /* If little-endian, default to -mstrict-align on older processors.
4223 Testing for htm matches power8 and later. */
4224 if (!BYTES_BIG_ENDIAN
4225 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4226 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4228 if (!rs6000_fold_gimple)
4230 "gimple folding of rs6000 builtins has been disabled.\n");
4232 /* Add some warnings for VSX. */
4235 const char *msg = NULL;
4236 if (!TARGET_HARD_FLOAT)
4238 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4239 msg = N_("-mvsx requires hardware floating point");
4242 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4243 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4246 else if (TARGET_AVOID_XFORM > 0)
4247 msg = N_("-mvsx needs indexed addressing");
4248 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4249 & OPTION_MASK_ALTIVEC))
4251 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4252 msg = N_("-mvsx and -mno-altivec are incompatible");
4254 msg = N_("-mno-altivec disables vsx");
4260 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4261 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4265 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4266 the -mcpu setting to enable options that conflict. */
4267 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4268 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4269 | OPTION_MASK_ALTIVEC
4270 | OPTION_MASK_VSX)) != 0)
4271 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4272 | OPTION_MASK_DIRECT_MOVE)
4273 & ~rs6000_isa_flags_explicit);
4275 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4276 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4278 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4279 off all of the options that depend on those flags. */
4280 ignore_masks = rs6000_disable_incompatible_switches ();
4282 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4283 unless the user explicitly used the -mno-<option> to disable the code. */
4284 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4285 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4286 else if (TARGET_P9_MINMAX)
4290 if (cpu_index == PROCESSOR_POWER9)
4292 /* legacy behavior: allow -mcpu=power9 with certain
4293 capabilities explicitly disabled. */
4294 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4297 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4298 "for <xxx> less than power9", "-mcpu");
4300 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4301 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4302 & rs6000_isa_flags_explicit))
4303 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4304 were explicitly cleared. */
4305 error ("%qs incompatible with explicitly disabled options",
4308 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4310 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4311 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4312 else if (TARGET_VSX)
4313 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4314 else if (TARGET_POPCNTD)
4315 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4316 else if (TARGET_DFP)
4317 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4318 else if (TARGET_CMPB)
4319 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4320 else if (TARGET_FPRND)
4321 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4322 else if (TARGET_POPCNTB)
4323 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4324 else if (TARGET_ALTIVEC)
4325 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4327 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4329 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4330 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4331 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4334 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4336 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4337 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4338 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4341 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4343 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4344 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4345 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4348 if (TARGET_P8_VECTOR && !TARGET_VSX)
4350 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4351 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4352 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4353 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4355 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4356 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4357 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4361 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4363 rs6000_isa_flags |= OPTION_MASK_VSX;
4364 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4368 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4370 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4371 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4372 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4375 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4376 silently turn off quad memory mode. */
4377 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4379 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4380 warning (0, N_("-mquad-memory requires 64-bit mode"));
4382 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4383 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4385 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4386 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4389 /* Non-atomic quad memory load/store are disabled for little endian, since
4390 the words are reversed, but atomic operations can still be done by
4391 swapping the words. */
4392 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4394 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4395 warning (0, N_("-mquad-memory is not available in little endian "
4398 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4401 /* Assume if the user asked for normal quad memory instructions, they want
4402 the atomic versions as well, unless they explicity told us not to use quad
4403 word atomic instructions. */
4404 if (TARGET_QUAD_MEMORY
4405 && !TARGET_QUAD_MEMORY_ATOMIC
4406 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4407 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4409 /* If we can shrink-wrap the TOC register save separately, then use
4410 -msave-toc-indirect unless explicitly disabled. */
4411 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4412 && flag_shrink_wrap_separate
4413 && optimize_function_for_speed_p (cfun))
4414 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4416 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4417 generating power8 instructions. */
4418 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4419 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4420 & OPTION_MASK_P8_FUSION);
4422 /* Setting additional fusion flags turns on base fusion. */
4423 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4425 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4427 if (TARGET_P8_FUSION_SIGN)
4428 error ("%qs requires %qs", "-mpower8-fusion-sign",
4431 if (TARGET_TOC_FUSION)
4432 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4434 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4437 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4440 /* Power9 fusion is a superset over power8 fusion. */
4441 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4443 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4445 /* We prefer to not mention undocumented options in
4446 error messages. However, if users have managed to select
4447 power9-fusion without selecting power8-fusion, they
4448 already know about undocumented flags. */
4449 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4450 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4453 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4456 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4457 generating power9 instructions. */
4458 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4459 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4460 & OPTION_MASK_P9_FUSION);
4462 /* Power8 does not fuse sign extended loads with the addis. If we are
4463 optimizing at high levels for speed, convert a sign extended load into a
4464 zero extending load, and an explicit sign extension. */
4465 if (TARGET_P8_FUSION
4466 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4467 && optimize_function_for_speed_p (cfun)
4469 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4471 /* TOC fusion requires 64-bit and medium/large code model. */
4472 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4474 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4475 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4476 warning (0, N_("-mtoc-fusion requires 64-bit"));
4479 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4481 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4482 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4483 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4486 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4488 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4489 && (TARGET_CMODEL != CMODEL_SMALL)
4490 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4491 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4493 /* ISA 3.0 vector instructions include ISA 2.07. */
4494 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4496 /* We prefer to not mention undocumented options in
4497 error messages. However, if users have managed to select
4498 power9-vector without selecting power8-vector, they
4499 already know about undocumented flags. */
4500 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4501 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4502 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4503 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4505 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4506 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4507 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4511 /* OPTION_MASK_P9_VECTOR is explicit and
4512 OPTION_MASK_P8_VECTOR is not explicit. */
4513 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4514 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4518 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4519 support. If we only have ISA 2.06 support, and the user did not specify
4520 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4521 but we don't enable the full vectorization support */
4522 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4523 TARGET_ALLOW_MOVMISALIGN = 1;
4525 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4527 if (TARGET_ALLOW_MOVMISALIGN > 0
4528 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4529 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4531 TARGET_ALLOW_MOVMISALIGN = 0;
4534 /* Determine when unaligned vector accesses are permitted, and when
4535 they are preferred over masked Altivec loads. Note that if
4536 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4537 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4539 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4543 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4544 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4546 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4549 else if (!TARGET_ALLOW_MOVMISALIGN)
4551 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4552 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4553 "-mallow-movmisalign");
4555 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4559 /* Set long double size before the IEEE 128-bit tests. */
4560 if (!global_options_set.x_rs6000_long_double_type_size)
4562 if (main_target_opt != NULL
4563 && (main_target_opt->x_rs6000_long_double_type_size
4564 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4565 error ("target attribute or pragma changes long double size");
4567 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4570 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4571 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4572 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4573 those systems will not pick up this default. Warn if the user changes the
4574 default unless either the user used the -Wno-psabi option, or the compiler
4575 was built to enable multilibs to switch between the two long double
4577 if (!global_options_set.x_rs6000_ieeequad)
4578 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4580 else if (!TARGET_IEEEQUAD_MULTILIB
4581 && rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT
4582 && TARGET_LONG_DOUBLE_128)
4584 static bool warned_change_long_double;
4585 if (!warned_change_long_double)
4587 warned_change_long_double = true;
4588 if (TARGET_IEEEQUAD)
4589 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4591 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4595 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4596 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4597 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4598 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4599 the keyword as well as the type. */
4600 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4602 /* IEEE 128-bit floating point requires VSX support. */
4603 if (TARGET_FLOAT128_KEYWORD)
4607 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4608 error ("%qs requires VSX support", "-mfloat128");
4610 TARGET_FLOAT128_TYPE = 0;
4611 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4612 | OPTION_MASK_FLOAT128_HW);
4614 else if (!TARGET_FLOAT128_TYPE)
4616 TARGET_FLOAT128_TYPE = 1;
4617 warning (0, "The -mfloat128 option may not be fully supported");
4621 /* Enable the __float128 keyword under Linux by default. */
4622 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4623 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4624 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4626 /* If we have are supporting the float128 type and full ISA 3.0 support,
4627 enable -mfloat128-hardware by default. However, don't enable the
4628 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4629 because sometimes the compiler wants to put things in an integer
4630 container, and if we don't have __int128 support, it is impossible. */
4631 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4632 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4633 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4634 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4636 if (TARGET_FLOAT128_HW
4637 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4639 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4640 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4642 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4645 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4647 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4648 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4650 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4653 /* Print the options after updating the defaults. */
4654 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4655 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4657 /* E500mc does "better" if we inline more aggressively. Respect the
4658 user's opinion, though. */
4659 if (rs6000_block_move_inline_limit == 0
4660 && (rs6000_tune == PROCESSOR_PPCE500MC
4661 || rs6000_tune == PROCESSOR_PPCE500MC64
4662 || rs6000_tune == PROCESSOR_PPCE5500
4663 || rs6000_tune == PROCESSOR_PPCE6500))
4664 rs6000_block_move_inline_limit = 128;
4666 /* store_one_arg depends on expand_block_move to handle at least the
4667 size of reg_parm_stack_space. */
4668 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4669 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4673 /* If the appropriate debug option is enabled, replace the target hooks
4674 with debug versions that call the real version and then prints
4675 debugging information. */
4676 if (TARGET_DEBUG_COST)
4678 targetm.rtx_costs = rs6000_debug_rtx_costs;
4679 targetm.address_cost = rs6000_debug_address_cost;
4680 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4683 if (TARGET_DEBUG_ADDR)
4685 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4686 targetm.legitimize_address = rs6000_debug_legitimize_address;
4687 rs6000_secondary_reload_class_ptr
4688 = rs6000_debug_secondary_reload_class;
4689 targetm.secondary_memory_needed
4690 = rs6000_debug_secondary_memory_needed;
4691 targetm.can_change_mode_class
4692 = rs6000_debug_can_change_mode_class;
4693 rs6000_preferred_reload_class_ptr
4694 = rs6000_debug_preferred_reload_class;
4695 rs6000_legitimize_reload_address_ptr
4696 = rs6000_debug_legitimize_reload_address;
4697 rs6000_mode_dependent_address_ptr
4698 = rs6000_debug_mode_dependent_address;
4701 if (rs6000_veclibabi_name)
4703 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4704 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4707 error ("unknown vectorization library ABI type (%qs) for "
4708 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4714 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4715 target attribute or pragma which automatically enables both options,
4716 unless the altivec ABI was set. This is set by default for 64-bit, but
4718 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4720 TARGET_FLOAT128_TYPE = 0;
4721 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4722 | OPTION_MASK_FLOAT128_KEYWORD)
4723 & ~rs6000_isa_flags_explicit);
4726 /* Enable Altivec ABI for AIX -maltivec. */
4727 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4729 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4730 error ("target attribute or pragma changes AltiVec ABI");
4732 rs6000_altivec_abi = 1;
4735 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4736 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4737 be explicitly overridden in either case. */
4740 if (!global_options_set.x_rs6000_altivec_abi
4741 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4743 if (main_target_opt != NULL &&
4744 !main_target_opt->x_rs6000_altivec_abi)
4745 error ("target attribute or pragma changes AltiVec ABI");
4747 rs6000_altivec_abi = 1;
4751 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4752 So far, the only darwin64 targets are also MACH-O. */
4754 && DEFAULT_ABI == ABI_DARWIN
4757 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4758 error ("target attribute or pragma changes darwin64 ABI");
4761 rs6000_darwin64_abi = 1;
4762 /* Default to natural alignment, for better performance. */
4763 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4767 /* Place FP constants in the constant pool instead of TOC
4768 if section anchors enabled. */
4769 if (flag_section_anchors
4770 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4771 TARGET_NO_FP_IN_TOC = 1;
4773 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4774 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4776 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4777 SUBTARGET_OVERRIDE_OPTIONS;
4779 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4780 SUBSUBTARGET_OVERRIDE_OPTIONS;
4782 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4783 SUB3TARGET_OVERRIDE_OPTIONS;
4786 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4787 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4789 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4790 && rs6000_tune != PROCESSOR_POWER5
4791 && rs6000_tune != PROCESSOR_POWER6
4792 && rs6000_tune != PROCESSOR_POWER7
4793 && rs6000_tune != PROCESSOR_POWER8
4794 && rs6000_tune != PROCESSOR_POWER9
4795 && rs6000_tune != PROCESSOR_PPCA2
4796 && rs6000_tune != PROCESSOR_CELL
4797 && rs6000_tune != PROCESSOR_PPC476);
4798 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4799 || rs6000_tune == PROCESSOR_POWER5
4800 || rs6000_tune == PROCESSOR_POWER7
4801 || rs6000_tune == PROCESSOR_POWER8);
4802 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4803 || rs6000_tune == PROCESSOR_POWER5
4804 || rs6000_tune == PROCESSOR_POWER6
4805 || rs6000_tune == PROCESSOR_POWER7
4806 || rs6000_tune == PROCESSOR_POWER8
4807 || rs6000_tune == PROCESSOR_POWER9
4808 || rs6000_tune == PROCESSOR_PPCE500MC
4809 || rs6000_tune == PROCESSOR_PPCE500MC64
4810 || rs6000_tune == PROCESSOR_PPCE5500
4811 || rs6000_tune == PROCESSOR_PPCE6500);
4813 /* Allow debug switches to override the above settings. These are set to -1
4814 in rs6000.opt to indicate the user hasn't directly set the switch. */
4815 if (TARGET_ALWAYS_HINT >= 0)
4816 rs6000_always_hint = TARGET_ALWAYS_HINT;
4818 if (TARGET_SCHED_GROUPS >= 0)
4819 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4821 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4822 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4824 rs6000_sched_restricted_insns_priority
4825 = (rs6000_sched_groups ? 1 : 0);
4827 /* Handle -msched-costly-dep option. */
4828 rs6000_sched_costly_dep
4829 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4831 if (rs6000_sched_costly_dep_str)
4833 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4834 rs6000_sched_costly_dep = no_dep_costly;
4835 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4836 rs6000_sched_costly_dep = all_deps_costly;
4837 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4838 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4839 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4840 rs6000_sched_costly_dep = store_to_load_dep_costly;
4842 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4843 atoi (rs6000_sched_costly_dep_str));
4846 /* Handle -minsert-sched-nops option. */
4847 rs6000_sched_insert_nops
4848 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4850 if (rs6000_sched_insert_nops_str)
4852 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4853 rs6000_sched_insert_nops = sched_finish_none;
4854 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4855 rs6000_sched_insert_nops = sched_finish_pad_groups;
4856 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4857 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4859 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4860 atoi (rs6000_sched_insert_nops_str));
4863 /* Handle stack protector */
4864 if (!global_options_set.x_rs6000_stack_protector_guard)
4865 #ifdef TARGET_THREAD_SSP_OFFSET
4866 rs6000_stack_protector_guard = SSP_TLS;
4868 rs6000_stack_protector_guard = SSP_GLOBAL;
4871 #ifdef TARGET_THREAD_SSP_OFFSET
4872 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4873 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4876 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4879 const char *str = rs6000_stack_protector_guard_offset_str;
4882 long offset = strtol (str, &endp, 0);
4883 if (!*str || *endp || errno)
4884 error ("%qs is not a valid number in %qs", str,
4885 "-mstack-protector-guard-offset=");
4887 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4888 || (TARGET_64BIT && (offset & 3)))
4889 error ("%qs is not a valid offset in %qs", str,
4890 "-mstack-protector-guard-offset=");
4892 rs6000_stack_protector_guard_offset = offset;
4895 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4897 const char *str = rs6000_stack_protector_guard_reg_str;
4898 int reg = decode_reg_name (str);
4900 if (!IN_RANGE (reg, 1, 31))
4901 error ("%qs is not a valid base register in %qs", str,
4902 "-mstack-protector-guard-reg=");
4904 rs6000_stack_protector_guard_reg = reg;
4907 if (rs6000_stack_protector_guard == SSP_TLS
4908 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4909 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4913 #ifdef TARGET_REGNAMES
4914 /* If the user desires alternate register names, copy in the
4915 alternate names now. */
4916 if (TARGET_REGNAMES)
4917 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4920 /* Set aix_struct_return last, after the ABI is determined.
4921 If -maix-struct-return or -msvr4-struct-return was explicitly
4922 used, don't override with the ABI default. */
4923 if (!global_options_set.x_aix_struct_return)
4924 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4927 /* IBM XL compiler defaults to unsigned bitfields. */
4928 if (TARGET_XL_COMPAT)
4929 flag_signed_bitfields = 0;
4932 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4933 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4935 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4937 /* We can only guarantee the availability of DI pseudo-ops when
4938 assembling for 64-bit targets. */
4941 targetm.asm_out.aligned_op.di = NULL;
4942 targetm.asm_out.unaligned_op.di = NULL;
4946 /* Set branch target alignment, if not optimizing for size. */
4949 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4950 aligned 8byte to avoid misprediction by the branch predictor. */
4951 if (rs6000_tune == PROCESSOR_TITAN
4952 || rs6000_tune == PROCESSOR_CELL)
4954 if (align_functions <= 0)
4955 align_functions = 8;
4956 if (align_jumps <= 0)
4958 if (align_loops <= 0)
4961 if (rs6000_align_branch_targets)
4963 if (align_functions <= 0)
4964 align_functions = 16;
4965 if (align_jumps <= 0)
4967 if (align_loops <= 0)
4969 can_override_loop_align = 1;
4973 if (align_jumps_max_skip <= 0)
4974 align_jumps_max_skip = 15;
4975 if (align_loops_max_skip <= 0)
4976 align_loops_max_skip = 15;
4979 /* Arrange to save and restore machine status around nested functions. */
4980 init_machine_status = rs6000_init_machine_status;
4982 /* We should always be splitting complex arguments, but we can't break
4983 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4984 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4985 targetm.calls.split_complex_arg = NULL;
4987 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4988 if (DEFAULT_ABI == ABI_AIX)
4989 targetm.calls.custom_function_descriptors = 0;
4992 /* Initialize rs6000_cost with the appropriate target costs. */
4994 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4996 switch (rs6000_tune)
4998 case PROCESSOR_RS64A:
4999 rs6000_cost = &rs64a_cost;
5002 case PROCESSOR_MPCCORE:
5003 rs6000_cost = &mpccore_cost;
5006 case PROCESSOR_PPC403:
5007 rs6000_cost = &ppc403_cost;
5010 case PROCESSOR_PPC405:
5011 rs6000_cost = &ppc405_cost;
5014 case PROCESSOR_PPC440:
5015 rs6000_cost = &ppc440_cost;
5018 case PROCESSOR_PPC476:
5019 rs6000_cost = &ppc476_cost;
5022 case PROCESSOR_PPC601:
5023 rs6000_cost = &ppc601_cost;
5026 case PROCESSOR_PPC603:
5027 rs6000_cost = &ppc603_cost;
5030 case PROCESSOR_PPC604:
5031 rs6000_cost = &ppc604_cost;
5034 case PROCESSOR_PPC604e:
5035 rs6000_cost = &ppc604e_cost;
5038 case PROCESSOR_PPC620:
5039 rs6000_cost = &ppc620_cost;
5042 case PROCESSOR_PPC630:
5043 rs6000_cost = &ppc630_cost;
5046 case PROCESSOR_CELL:
5047 rs6000_cost = &ppccell_cost;
5050 case PROCESSOR_PPC750:
5051 case PROCESSOR_PPC7400:
5052 rs6000_cost = &ppc750_cost;
5055 case PROCESSOR_PPC7450:
5056 rs6000_cost = &ppc7450_cost;
5059 case PROCESSOR_PPC8540:
5060 case PROCESSOR_PPC8548:
5061 rs6000_cost = &ppc8540_cost;
5064 case PROCESSOR_PPCE300C2:
5065 case PROCESSOR_PPCE300C3:
5066 rs6000_cost = &ppce300c2c3_cost;
5069 case PROCESSOR_PPCE500MC:
5070 rs6000_cost = &ppce500mc_cost;
5073 case PROCESSOR_PPCE500MC64:
5074 rs6000_cost = &ppce500mc64_cost;
5077 case PROCESSOR_PPCE5500:
5078 rs6000_cost = &ppce5500_cost;
5081 case PROCESSOR_PPCE6500:
5082 rs6000_cost = &ppce6500_cost;
5085 case PROCESSOR_TITAN:
5086 rs6000_cost = &titan_cost;
5089 case PROCESSOR_POWER4:
5090 case PROCESSOR_POWER5:
5091 rs6000_cost = &power4_cost;
5094 case PROCESSOR_POWER6:
5095 rs6000_cost = &power6_cost;
5098 case PROCESSOR_POWER7:
5099 rs6000_cost = &power7_cost;
5102 case PROCESSOR_POWER8:
5103 rs6000_cost = &power8_cost;
5106 case PROCESSOR_POWER9:
5107 rs6000_cost = &power9_cost;
5110 case PROCESSOR_PPCA2:
5111 rs6000_cost = &ppca2_cost;
5120 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5121 rs6000_cost->simultaneous_prefetches,
5122 global_options.x_param_values,
5123 global_options_set.x_param_values);
5124 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5125 global_options.x_param_values,
5126 global_options_set.x_param_values);
5127 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5128 rs6000_cost->cache_line_size,
5129 global_options.x_param_values,
5130 global_options_set.x_param_values);
5131 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5132 global_options.x_param_values,
5133 global_options_set.x_param_values);
5135 /* Increase loop peeling limits based on performance analysis. */
5136 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5137 global_options.x_param_values,
5138 global_options_set.x_param_values);
5139 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5140 global_options.x_param_values,
5141 global_options_set.x_param_values);
5143 /* Use the 'model' -fsched-pressure algorithm by default. */
5144 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5145 SCHED_PRESSURE_MODEL,
5146 global_options.x_param_values,
5147 global_options_set.x_param_values);
5149 /* If using typedef char *va_list, signal that
5150 __builtin_va_start (&ap, 0) can be optimized to
5151 ap = __builtin_next_arg (0). */
5152 if (DEFAULT_ABI != ABI_V4)
5153 targetm.expand_builtin_va_start = NULL;
5156 /* If not explicitly specified via option, decide whether to generate indexed
5157 load/store instructions. A value of -1 indicates that the
5158 initial value of this variable has not been overwritten. During
5159 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5160 if (TARGET_AVOID_XFORM == -1)
5161 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5162 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5163 need indexed accesses and the type used is the scalar type of the element
5164 being loaded or stored. */
5165 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5166 && !TARGET_ALTIVEC);
5168 /* Set the -mrecip options. */
5169 if (rs6000_recip_name)
5171 char *p = ASTRDUP (rs6000_recip_name);
5173 unsigned int mask, i;
5176 while ((q = strtok (p, ",")) != NULL)
5187 if (!strcmp (q, "default"))
5188 mask = ((TARGET_RECIP_PRECISION)
5189 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5192 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5193 if (!strcmp (q, recip_options[i].string))
5195 mask = recip_options[i].mask;
5199 if (i == ARRAY_SIZE (recip_options))
5201 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5209 rs6000_recip_control &= ~mask;
5211 rs6000_recip_control |= mask;
5215 /* Set the builtin mask of the various options used that could affect which
5216 builtins were used. In the past we used target_flags, but we've run out
5217 of bits, and some options are no longer in target_flags. */
5218 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5219 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5220 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5221 rs6000_builtin_mask);
5223 /* Initialize all of the registers. */
5224 rs6000_init_hard_regno_mode_ok (global_init_p);
5226 /* Save the initial options in case the user does function specific options */
5228 target_option_default_node = target_option_current_node
5229 = build_target_option_node (&global_options);
5231 /* If not explicitly specified via option, decide whether to generate the
5232 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5233 if (TARGET_LINK_STACK == -1)
5234 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5236 /* Deprecate use of -mno-speculate-indirect-jumps. */
5237 if (!rs6000_speculate_indirect_jumps)
5238 warning (0, "%qs is deprecated and not recommended in any circumstances",
5239 "-mno-speculate-indirect-jumps");
5244 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5245 define the target cpu type. */
5248 rs6000_option_override (void)
5250 (void) rs6000_option_override_internal (true);
5254 /* Implement targetm.vectorize.builtin_mask_for_load. */
5256 rs6000_builtin_mask_for_load (void)
5258 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5259 if ((TARGET_ALTIVEC && !TARGET_VSX)
5260 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5261 return altivec_builtin_mask_for_load;
5266 /* Implement LOOP_ALIGN. */
5268 rs6000_loop_align (rtx label)
5273 /* Don't override loop alignment if -falign-loops was specified. */
5274 if (!can_override_loop_align)
5275 return align_loops_log;
5277 bb = BLOCK_FOR_INSN (label);
5278 ninsns = num_loop_insns(bb->loop_father);
5280 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5281 if (ninsns > 4 && ninsns <= 8
5282 && (rs6000_tune == PROCESSOR_POWER4
5283 || rs6000_tune == PROCESSOR_POWER5
5284 || rs6000_tune == PROCESSOR_POWER6
5285 || rs6000_tune == PROCESSOR_POWER7
5286 || rs6000_tune == PROCESSOR_POWER8))
5289 return align_loops_log;
5292 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5294 rs6000_loop_align_max_skip (rtx_insn *label)
5296 return (1 << rs6000_loop_align (label)) - 1;
5299 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5300 after applying N number of iterations. This routine does not determine
5301 how may iterations are required to reach desired alignment. */
5304 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5311 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5314 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5324 /* Assuming that all other types are naturally aligned. CHECKME! */
5329 /* Return true if the vector misalignment factor is supported by the
5332 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5339 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5342 /* Return if movmisalign pattern is not supported for this mode. */
5343 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5346 if (misalignment == -1)
5348 /* Misalignment factor is unknown at compile time but we know
5349 it's word aligned. */
5350 if (rs6000_vector_alignment_reachable (type, is_packed))
5352 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5354 if (element_size == 64 || element_size == 32)
5361 /* VSX supports word-aligned vector. */
5362 if (misalignment % 4 == 0)
5368 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5370 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5371 tree vectype, int misalign)
5376 switch (type_of_cost)
5386 case cond_branch_not_taken:
5395 case vec_promote_demote:
5401 case cond_branch_taken:
5404 case unaligned_load:
5405 case vector_gather_load:
5406 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5409 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5411 elements = TYPE_VECTOR_SUBPARTS (vectype);
5413 /* Double word aligned. */
5421 /* Double word aligned. */
5425 /* Unknown misalignment. */
5438 /* Misaligned loads are not supported. */
5443 case unaligned_store:
5444 case vector_scatter_store:
5445 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5448 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5450 elements = TYPE_VECTOR_SUBPARTS (vectype);
5452 /* Double word aligned. */
5460 /* Double word aligned. */
5464 /* Unknown misalignment. */
5477 /* Misaligned stores are not supported. */
5483 /* This is a rough approximation assuming non-constant elements
5484 constructed into a vector via element insertion. FIXME:
5485 vec_construct is not granular enough for uniformly good
5486 decisions. If the initialization is a splat, this is
5487 cheaper than we estimate. Improve this someday. */
5488 elem_type = TREE_TYPE (vectype);
5489 /* 32-bit vectors loaded into registers are stored as double
5490 precision, so we need 2 permutes, 2 converts, and 1 merge
5491 to construct a vector of short floats from them. */
5492 if (SCALAR_FLOAT_TYPE_P (elem_type)
5493 && TYPE_PRECISION (elem_type) == 32)
5495 /* On POWER9, integer vector types are built up in GPRs and then
5496 use a direct move (2 cycles). For POWER8 this is even worse,
5497 as we need two direct moves and a merge, and the direct moves
5499 else if (INTEGRAL_TYPE_P (elem_type))
5501 if (TARGET_P9_VECTOR)
5502 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5504 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5507 /* V2DFmode doesn't need a direct move. */
5515 /* Implement targetm.vectorize.preferred_simd_mode. */
5518 rs6000_preferred_simd_mode (scalar_mode mode)
5527 if (TARGET_ALTIVEC || TARGET_VSX)
5547 typedef struct _rs6000_cost_data
5549 struct loop *loop_info;
5553 /* Test for likely overcommitment of vector hardware resources. If a
5554 loop iteration is relatively large, and too large a percentage of
5555 instructions in the loop are vectorized, the cost model may not
5556 adequately reflect delays from unavailable vector resources.
5557 Penalize the loop body cost for this case. */
5560 rs6000_density_test (rs6000_cost_data *data)
5562 const int DENSITY_PCT_THRESHOLD = 85;
5563 const int DENSITY_SIZE_THRESHOLD = 70;
5564 const int DENSITY_PENALTY = 10;
5565 struct loop *loop = data->loop_info;
5566 basic_block *bbs = get_loop_body (loop);
5567 int nbbs = loop->num_nodes;
5568 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5571 for (i = 0; i < nbbs; i++)
5573 basic_block bb = bbs[i];
5574 gimple_stmt_iterator gsi;
5576 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5578 gimple *stmt = gsi_stmt (gsi);
5579 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5581 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5582 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5588 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5590 if (density_pct > DENSITY_PCT_THRESHOLD
5591 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5593 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5594 if (dump_enabled_p ())
5595 dump_printf_loc (MSG_NOTE, vect_location,
5596 "density %d%%, cost %d exceeds threshold, penalizing "
5597 "loop body cost by %d%%", density_pct,
5598 vec_cost + not_vec_cost, DENSITY_PENALTY);
5602 /* Implement targetm.vectorize.init_cost. */
5604 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5605 instruction is needed by the vectorization. */
5606 static bool rs6000_vect_nonmem;
5609 rs6000_init_cost (struct loop *loop_info)
5611 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5612 data->loop_info = loop_info;
5613 data->cost[vect_prologue] = 0;
5614 data->cost[vect_body] = 0;
5615 data->cost[vect_epilogue] = 0;
5616 rs6000_vect_nonmem = false;
5620 /* Implement targetm.vectorize.add_stmt_cost. */
5623 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5624 struct _stmt_vec_info *stmt_info, int misalign,
5625 enum vect_cost_model_location where)
5627 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5628 unsigned retval = 0;
5630 if (flag_vect_cost_model)
5632 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5633 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5635 /* Statements in an inner loop relative to the loop being
5636 vectorized are weighted more heavily. The value here is
5637 arbitrary and could potentially be improved with analysis. */
5638 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5639 count *= 50; /* FIXME. */
5641 retval = (unsigned) (count * stmt_cost);
5642 cost_data->cost[where] += retval;
5644 /* Check whether we're doing something other than just a copy loop.
5645 Not all such loops may be profitably vectorized; see
5646 rs6000_finish_cost. */
5647 if ((kind == vec_to_scalar || kind == vec_perm
5648 || kind == vec_promote_demote || kind == vec_construct
5649 || kind == scalar_to_vec)
5650 || (where == vect_body && kind == vector_stmt))
5651 rs6000_vect_nonmem = true;
5657 /* Implement targetm.vectorize.finish_cost. */
5660 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5661 unsigned *body_cost, unsigned *epilogue_cost)
5663 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5665 if (cost_data->loop_info)
5666 rs6000_density_test (cost_data);
5668 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5669 that require versioning for any reason. The vectorization is at
5670 best a wash inside the loop, and the versioning checks make
5671 profitability highly unlikely and potentially quite harmful. */
5672 if (cost_data->loop_info)
5674 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5675 if (!rs6000_vect_nonmem
5676 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5677 && LOOP_REQUIRES_VERSIONING (vec_info))
5678 cost_data->cost[vect_body] += 10000;
5681 *prologue_cost = cost_data->cost[vect_prologue];
5682 *body_cost = cost_data->cost[vect_body];
5683 *epilogue_cost = cost_data->cost[vect_epilogue];
5686 /* Implement targetm.vectorize.destroy_cost_data. */
5689 rs6000_destroy_cost_data (void *data)
5694 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5695 library with vectorized intrinsics. */
5698 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5702 const char *suffix = NULL;
5703 tree fntype, new_fndecl, bdecl = NULL_TREE;
5706 machine_mode el_mode, in_mode;
5709 /* Libmass is suitable for unsafe math only as it does not correctly support
5710 parts of IEEE with the required precision such as denormals. Only support
5711 it if we have VSX to use the simd d2 or f4 functions.
5712 XXX: Add variable length support. */
5713 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5716 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5717 n = TYPE_VECTOR_SUBPARTS (type_out);
5718 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5719 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5720 if (el_mode != in_mode
5756 if (el_mode == DFmode && n == 2)
5758 bdecl = mathfn_built_in (double_type_node, fn);
5759 suffix = "d2"; /* pow -> powd2 */
5761 else if (el_mode == SFmode && n == 4)
5763 bdecl = mathfn_built_in (float_type_node, fn);
5764 suffix = "4"; /* powf -> powf4 */
5776 gcc_assert (suffix != NULL);
5777 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5781 strcpy (name, bname + sizeof ("__builtin_") - 1);
5782 strcat (name, suffix);
5785 fntype = build_function_type_list (type_out, type_in, NULL);
5786 else if (n_args == 2)
5787 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5791 /* Build a function declaration for the vectorized function. */
5792 new_fndecl = build_decl (BUILTINS_LOCATION,
5793 FUNCTION_DECL, get_identifier (name), fntype);
5794 TREE_PUBLIC (new_fndecl) = 1;
5795 DECL_EXTERNAL (new_fndecl) = 1;
5796 DECL_IS_NOVOPS (new_fndecl) = 1;
5797 TREE_READONLY (new_fndecl) = 1;
5802 /* Returns a function decl for a vectorized version of the builtin function
5803 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5804 if it is not available. */
5807 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5810 machine_mode in_mode, out_mode;
5813 if (TARGET_DEBUG_BUILTIN)
5814 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5815 combined_fn_name (combined_fn (fn)),
5816 GET_MODE_NAME (TYPE_MODE (type_out)),
5817 GET_MODE_NAME (TYPE_MODE (type_in)));
5819 if (TREE_CODE (type_out) != VECTOR_TYPE
5820 || TREE_CODE (type_in) != VECTOR_TYPE)
5823 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5824 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5825 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5826 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5831 if (VECTOR_UNIT_VSX_P (V2DFmode)
5832 && out_mode == DFmode && out_n == 2
5833 && in_mode == DFmode && in_n == 2)
5834 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5835 if (VECTOR_UNIT_VSX_P (V4SFmode)
5836 && out_mode == SFmode && out_n == 4
5837 && in_mode == SFmode && in_n == 4)
5838 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5839 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5840 && out_mode == SFmode && out_n == 4
5841 && in_mode == SFmode && in_n == 4)
5842 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5845 if (VECTOR_UNIT_VSX_P (V2DFmode)
5846 && out_mode == DFmode && out_n == 2
5847 && in_mode == DFmode && in_n == 2)
5848 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5849 if (VECTOR_UNIT_VSX_P (V4SFmode)
5850 && out_mode == SFmode && out_n == 4
5851 && in_mode == SFmode && in_n == 4)
5852 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5853 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5854 && out_mode == SFmode && out_n == 4
5855 && in_mode == SFmode && in_n == 4)
5856 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5859 if (VECTOR_UNIT_VSX_P (V2DFmode)
5860 && out_mode == DFmode && out_n == 2
5861 && in_mode == DFmode && in_n == 2)
5862 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5863 if (VECTOR_UNIT_VSX_P (V4SFmode)
5864 && out_mode == SFmode && out_n == 4
5865 && in_mode == SFmode && in_n == 4)
5866 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5867 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5868 && out_mode == SFmode && out_n == 4
5869 && in_mode == SFmode && in_n == 4)
5870 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5873 if (VECTOR_UNIT_VSX_P (V2DFmode)
5874 && out_mode == DFmode && out_n == 2
5875 && in_mode == DFmode && in_n == 2)
5876 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5877 if (VECTOR_UNIT_VSX_P (V4SFmode)
5878 && out_mode == SFmode && out_n == 4
5879 && in_mode == SFmode && in_n == 4)
5880 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5881 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5882 && out_mode == SFmode && out_n == 4
5883 && in_mode == SFmode && in_n == 4)
5884 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5887 if (VECTOR_UNIT_VSX_P (V2DFmode)
5888 && out_mode == DFmode && out_n == 2
5889 && in_mode == DFmode && in_n == 2)
5890 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5891 if (VECTOR_UNIT_VSX_P (V4SFmode)
5892 && out_mode == SFmode && out_n == 4
5893 && in_mode == SFmode && in_n == 4)
5894 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5895 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5896 && out_mode == SFmode && out_n == 4
5897 && in_mode == SFmode && in_n == 4)
5898 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5901 if (VECTOR_UNIT_VSX_P (V2DFmode)
5902 && flag_unsafe_math_optimizations
5903 && out_mode == DFmode && out_n == 2
5904 && in_mode == DFmode && in_n == 2)
5905 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5906 if (VECTOR_UNIT_VSX_P (V4SFmode)
5907 && flag_unsafe_math_optimizations
5908 && out_mode == SFmode && out_n == 4
5909 && in_mode == SFmode && in_n == 4)
5910 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5913 if (VECTOR_UNIT_VSX_P (V2DFmode)
5914 && !flag_trapping_math
5915 && out_mode == DFmode && out_n == 2
5916 && in_mode == DFmode && in_n == 2)
5917 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5918 if (VECTOR_UNIT_VSX_P (V4SFmode)
5919 && !flag_trapping_math
5920 && out_mode == SFmode && out_n == 4
5921 && in_mode == SFmode && in_n == 4)
5922 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5928 /* Generate calls to libmass if appropriate. */
5929 if (rs6000_veclib_handler)
5930 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5935 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5938 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5941 machine_mode in_mode, out_mode;
5944 if (TARGET_DEBUG_BUILTIN)
5945 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5946 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5947 GET_MODE_NAME (TYPE_MODE (type_out)),
5948 GET_MODE_NAME (TYPE_MODE (type_in)));
5950 if (TREE_CODE (type_out) != VECTOR_TYPE
5951 || TREE_CODE (type_in) != VECTOR_TYPE)
5954 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5955 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5956 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5957 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5959 enum rs6000_builtins fn
5960 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5963 case RS6000_BUILTIN_RSQRTF:
5964 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5965 && out_mode == SFmode && out_n == 4
5966 && in_mode == SFmode && in_n == 4)
5967 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5969 case RS6000_BUILTIN_RSQRT:
5970 if (VECTOR_UNIT_VSX_P (V2DFmode)
5971 && out_mode == DFmode && out_n == 2
5972 && in_mode == DFmode && in_n == 2)
5973 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5975 case RS6000_BUILTIN_RECIPF:
5976 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5977 && out_mode == SFmode && out_n == 4
5978 && in_mode == SFmode && in_n == 4)
5979 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5981 case RS6000_BUILTIN_RECIP:
5982 if (VECTOR_UNIT_VSX_P (V2DFmode)
5983 && out_mode == DFmode && out_n == 2
5984 && in_mode == DFmode && in_n == 2)
5985 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5993 /* Default CPU string for rs6000*_file_start functions. */
5994 static const char *rs6000_default_cpu;
5996 /* Do anything needed at the start of the asm file. */
5999 rs6000_file_start (void)
6002 const char *start = buffer;
6003 FILE *file = asm_out_file;
6005 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6007 default_file_start ();
6009 if (flag_verbose_asm)
6011 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6013 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6015 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6019 if (global_options_set.x_rs6000_cpu_index)
6021 fprintf (file, "%s -mcpu=%s", start,
6022 processor_target_table[rs6000_cpu_index].name);
6026 if (global_options_set.x_rs6000_tune_index)
6028 fprintf (file, "%s -mtune=%s", start,
6029 processor_target_table[rs6000_tune_index].name);
6033 if (PPC405_ERRATUM77)
6035 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6039 #ifdef USING_ELFOS_H
6040 switch (rs6000_sdata)
6042 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6043 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6044 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6045 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6048 if (rs6000_sdata && g_switch_value)
6050 fprintf (file, "%s -G %d", start,
6060 #ifdef USING_ELFOS_H
6061 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6062 && !global_options_set.x_rs6000_cpu_index)
6064 fputs ("\t.machine ", asm_out_file);
6065 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6066 fputs ("power9\n", asm_out_file);
6067 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6068 fputs ("power8\n", asm_out_file);
6069 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6070 fputs ("power7\n", asm_out_file);
6071 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6072 fputs ("power6\n", asm_out_file);
6073 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6074 fputs ("power5\n", asm_out_file);
6075 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6076 fputs ("power4\n", asm_out_file);
6077 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6078 fputs ("ppc64\n", asm_out_file);
6080 fputs ("ppc\n", asm_out_file);
6084 if (DEFAULT_ABI == ABI_ELFv2)
6085 fprintf (file, "\t.abiversion 2\n");
6089 /* Return nonzero if this function is known to have a null epilogue. */
6092 direct_return (void)
6094 if (reload_completed)
6096 rs6000_stack_t *info = rs6000_stack_info ();
6098 if (info->first_gp_reg_save == 32
6099 && info->first_fp_reg_save == 64
6100 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6101 && ! info->lr_save_p
6102 && ! info->cr_save_p
6103 && info->vrsave_size == 0
6111 /* Return the number of instructions it takes to form a constant in an
6112 integer register. */
6115 num_insns_constant_wide (HOST_WIDE_INT value)
6117 /* signed constant loadable with addi */
6118 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6121 /* constant loadable with addis */
6122 else if ((value & 0xffff) == 0
6123 && (value >> 31 == -1 || value >> 31 == 0))
6126 else if (TARGET_POWERPC64)
6128 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6129 HOST_WIDE_INT high = value >> 31;
6131 if (high == 0 || high == -1)
6137 return num_insns_constant_wide (high) + 1;
6139 return num_insns_constant_wide (low) + 1;
6141 return (num_insns_constant_wide (high)
6142 + num_insns_constant_wide (low) + 1);
6150 num_insns_constant (rtx op, machine_mode mode)
6152 HOST_WIDE_INT low, high;
6154 switch (GET_CODE (op))
6157 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6158 && rs6000_is_valid_and_mask (op, mode))
6161 return num_insns_constant_wide (INTVAL (op));
6163 case CONST_WIDE_INT:
6166 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6167 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6168 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6173 if (mode == SFmode || mode == SDmode)
6177 if (DECIMAL_FLOAT_MODE_P (mode))
6178 REAL_VALUE_TO_TARGET_DECIMAL32
6179 (*CONST_DOUBLE_REAL_VALUE (op), l);
6181 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6182 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6186 if (DECIMAL_FLOAT_MODE_P (mode))
6187 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6189 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6190 high = l[WORDS_BIG_ENDIAN == 0];
6191 low = l[WORDS_BIG_ENDIAN != 0];
6194 return (num_insns_constant_wide (low)
6195 + num_insns_constant_wide (high));
6198 if ((high == 0 && low >= 0)
6199 || (high == -1 && low < 0))
6200 return num_insns_constant_wide (low);
6202 else if (rs6000_is_valid_and_mask (op, mode))
6206 return num_insns_constant_wide (high) + 1;
6209 return (num_insns_constant_wide (high)
6210 + num_insns_constant_wide (low) + 1);
6218 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6219 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6220 corresponding element of the vector, but for V4SFmode, the
6221 corresponding "float" is interpreted as an SImode integer. */
6224 const_vector_elt_as_int (rtx op, unsigned int elt)
6228 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6229 gcc_assert (GET_MODE (op) != V2DImode
6230 && GET_MODE (op) != V2DFmode);
6232 tmp = CONST_VECTOR_ELT (op, elt);
6233 if (GET_MODE (op) == V4SFmode)
6234 tmp = gen_lowpart (SImode, tmp);
6235 return INTVAL (tmp);
6238 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6239 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6240 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6241 all items are set to the same value and contain COPIES replicas of the
6242 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6243 operand and the others are set to the value of the operand's msb. */
6246 vspltis_constant (rtx op, unsigned step, unsigned copies)
6248 machine_mode mode = GET_MODE (op);
6249 machine_mode inner = GET_MODE_INNER (mode);
6257 HOST_WIDE_INT splat_val;
6258 HOST_WIDE_INT msb_val;
6260 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6263 nunits = GET_MODE_NUNITS (mode);
6264 bitsize = GET_MODE_BITSIZE (inner);
6265 mask = GET_MODE_MASK (inner);
6267 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6269 msb_val = val >= 0 ? 0 : -1;
6271 /* Construct the value to be splatted, if possible. If not, return 0. */
6272 for (i = 2; i <= copies; i *= 2)
6274 HOST_WIDE_INT small_val;
6276 small_val = splat_val >> bitsize;
6278 if (splat_val != ((HOST_WIDE_INT)
6279 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6280 | (small_val & mask)))
6282 splat_val = small_val;
6285 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6286 if (EASY_VECTOR_15 (splat_val))
6289 /* Also check if we can splat, and then add the result to itself. Do so if
6290 the value is positive, of if the splat instruction is using OP's mode;
6291 for splat_val < 0, the splat and the add should use the same mode. */
6292 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6293 && (splat_val >= 0 || (step == 1 && copies == 1)))
6296 /* Also check if are loading up the most significant bit which can be done by
6297 loading up -1 and shifting the value left by -1. */
6298 else if (EASY_VECTOR_MSB (splat_val, inner))
6304 /* Check if VAL is present in every STEP-th element, and the
6305 other elements are filled with its most significant bit. */
6306 for (i = 1; i < nunits; ++i)
6308 HOST_WIDE_INT desired_val;
6309 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6310 if ((i & (step - 1)) == 0)
6313 desired_val = msb_val;
6315 if (desired_val != const_vector_elt_as_int (op, elt))
6322 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6323 instruction, filling in the bottom elements with 0 or -1.
6325 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6326 for the number of zeroes to shift in, or negative for the number of 0xff
6329 OP is a CONST_VECTOR. */
6332 vspltis_shifted (rtx op)
6334 machine_mode mode = GET_MODE (op);
6335 machine_mode inner = GET_MODE_INNER (mode);
6343 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6346 /* We need to create pseudo registers to do the shift, so don't recognize
6347 shift vector constants after reload. */
6348 if (!can_create_pseudo_p ())
6351 nunits = GET_MODE_NUNITS (mode);
6352 mask = GET_MODE_MASK (inner);
6354 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6356 /* Check if the value can really be the operand of a vspltis[bhw]. */
6357 if (EASY_VECTOR_15 (val))
6360 /* Also check if we are loading up the most significant bit which can be done
6361 by loading up -1 and shifting the value left by -1. */
6362 else if (EASY_VECTOR_MSB (val, inner))
6368 /* Check if VAL is present in every STEP-th element until we find elements
6369 that are 0 or all 1 bits. */
6370 for (i = 1; i < nunits; ++i)
6372 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6373 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6375 /* If the value isn't the splat value, check for the remaining elements
6381 for (j = i+1; j < nunits; ++j)
6383 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6384 if (const_vector_elt_as_int (op, elt2) != 0)
6388 return (nunits - i) * GET_MODE_SIZE (inner);
6391 else if ((elt_val & mask) == mask)
6393 for (j = i+1; j < nunits; ++j)
6395 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6396 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6400 return -((nunits - i) * GET_MODE_SIZE (inner));
6408 /* If all elements are equal, we don't need to do VLSDOI. */
6413 /* Return true if OP is of the given MODE and can be synthesized
6414 with a vspltisb, vspltish or vspltisw. */
6417 easy_altivec_constant (rtx op, machine_mode mode)
6419 unsigned step, copies;
6421 if (mode == VOIDmode)
6422 mode = GET_MODE (op);
6423 else if (mode != GET_MODE (op))
6426 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6428 if (mode == V2DFmode)
6429 return zero_constant (op, mode);
6431 else if (mode == V2DImode)
6433 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6434 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6437 if (zero_constant (op, mode))
6440 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6441 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6447 /* V1TImode is a special container for TImode. Ignore for now. */
6448 else if (mode == V1TImode)
6451 /* Start with a vspltisw. */
6452 step = GET_MODE_NUNITS (mode) / 4;
6455 if (vspltis_constant (op, step, copies))
6458 /* Then try with a vspltish. */
6464 if (vspltis_constant (op, step, copies))
6467 /* And finally a vspltisb. */
6473 if (vspltis_constant (op, step, copies))
6476 if (vspltis_shifted (op) != 0)
6482 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6483 result is OP. Abort if it is not possible. */
6486 gen_easy_altivec_constant (rtx op)
6488 machine_mode mode = GET_MODE (op);
6489 int nunits = GET_MODE_NUNITS (mode);
6490 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6491 unsigned step = nunits / 4;
6492 unsigned copies = 1;
6494 /* Start with a vspltisw. */
6495 if (vspltis_constant (op, step, copies))
6496 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6498 /* Then try with a vspltish. */
6504 if (vspltis_constant (op, step, copies))
6505 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6507 /* And finally a vspltisb. */
6513 if (vspltis_constant (op, step, copies))
6514 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6519 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6520 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6522 Return the number of instructions needed (1 or 2) into the address pointed
6525 Return the constant that is being split via CONSTANT_PTR. */
6528 xxspltib_constant_p (rtx op,
6533 size_t nunits = GET_MODE_NUNITS (mode);
6535 HOST_WIDE_INT value;
6538 /* Set the returned values to out of bound values. */
6539 *num_insns_ptr = -1;
6540 *constant_ptr = 256;
6542 if (!TARGET_P9_VECTOR)
6545 if (mode == VOIDmode)
6546 mode = GET_MODE (op);
6548 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6551 /* Handle (vec_duplicate <constant>). */
6552 if (GET_CODE (op) == VEC_DUPLICATE)
6554 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6555 && mode != V2DImode)
6558 element = XEXP (op, 0);
6559 if (!CONST_INT_P (element))
6562 value = INTVAL (element);
6563 if (!IN_RANGE (value, -128, 127))
6567 /* Handle (const_vector [...]). */
6568 else if (GET_CODE (op) == CONST_VECTOR)
6570 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6571 && mode != V2DImode)
6574 element = CONST_VECTOR_ELT (op, 0);
6575 if (!CONST_INT_P (element))
6578 value = INTVAL (element);
6579 if (!IN_RANGE (value, -128, 127))
6582 for (i = 1; i < nunits; i++)
6584 element = CONST_VECTOR_ELT (op, i);
6585 if (!CONST_INT_P (element))
6588 if (value != INTVAL (element))
6593 /* Handle integer constants being loaded into the upper part of the VSX
6594 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6595 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6596 else if (CONST_INT_P (op))
6598 if (!SCALAR_INT_MODE_P (mode))
6601 value = INTVAL (op);
6602 if (!IN_RANGE (value, -128, 127))
6605 if (!IN_RANGE (value, -1, 0))
6607 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6610 if (EASY_VECTOR_15 (value))
6618 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6619 sign extend. Special case 0/-1 to allow getting any VSX register instead
6620 of an Altivec register. */
6621 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6622 && EASY_VECTOR_15 (value))
6625 /* Return # of instructions and the constant byte for XXSPLTIB. */
6626 if (mode == V16QImode)
6629 else if (IN_RANGE (value, -1, 0))
6635 *constant_ptr = (int) value;
6640 output_vec_const_move (rtx *operands)
6648 mode = GET_MODE (dest);
6652 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6653 int xxspltib_value = 256;
6656 if (zero_constant (vec, mode))
6658 if (TARGET_P9_VECTOR)
6659 return "xxspltib %x0,0";
6661 else if (dest_vmx_p)
6662 return "vspltisw %0,0";
6665 return "xxlxor %x0,%x0,%x0";
6668 if (all_ones_constant (vec, mode))
6670 if (TARGET_P9_VECTOR)
6671 return "xxspltib %x0,255";
6673 else if (dest_vmx_p)
6674 return "vspltisw %0,-1";
6676 else if (TARGET_P8_VECTOR)
6677 return "xxlorc %x0,%x0,%x0";
6683 if (TARGET_P9_VECTOR
6684 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6688 operands[2] = GEN_INT (xxspltib_value & 0xff);
6689 return "xxspltib %x0,%2";
6700 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6701 if (zero_constant (vec, mode))
6702 return "vspltisw %0,0";
6704 if (all_ones_constant (vec, mode))
6705 return "vspltisw %0,-1";
6707 /* Do we need to construct a value using VSLDOI? */
6708 shift = vspltis_shifted (vec);
6712 splat_vec = gen_easy_altivec_constant (vec);
6713 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6714 operands[1] = XEXP (splat_vec, 0);
6715 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6718 switch (GET_MODE (splat_vec))
6721 return "vspltisw %0,%1";
6724 return "vspltish %0,%1";
6727 return "vspltisb %0,%1";
6737 /* Initialize vector TARGET to VALS. */
6740 rs6000_expand_vector_init (rtx target, rtx vals)
6742 machine_mode mode = GET_MODE (target);
6743 machine_mode inner_mode = GET_MODE_INNER (mode);
6744 int n_elts = GET_MODE_NUNITS (mode);
6745 int n_var = 0, one_var = -1;
6746 bool all_same = true, all_const_zero = true;
6750 for (i = 0; i < n_elts; ++i)
6752 x = XVECEXP (vals, 0, i);
6753 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6754 ++n_var, one_var = i;
6755 else if (x != CONST0_RTX (inner_mode))
6756 all_const_zero = false;
6758 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6764 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6765 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6766 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6768 /* Zero register. */
6769 emit_move_insn (target, CONST0_RTX (mode));
6772 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6774 /* Splat immediate. */
6775 emit_insn (gen_rtx_SET (target, const_vec));
6780 /* Load from constant pool. */
6781 emit_move_insn (target, const_vec);
6786 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6787 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6791 size_t num_elements = all_same ? 1 : 2;
6792 for (i = 0; i < num_elements; i++)
6794 op[i] = XVECEXP (vals, 0, i);
6795 /* Just in case there is a SUBREG with a smaller mode, do a
6797 if (GET_MODE (op[i]) != inner_mode)
6799 rtx tmp = gen_reg_rtx (inner_mode);
6800 convert_move (tmp, op[i], 0);
6803 /* Allow load with splat double word. */
6804 else if (MEM_P (op[i]))
6807 op[i] = force_reg (inner_mode, op[i]);
6809 else if (!REG_P (op[i]))
6810 op[i] = force_reg (inner_mode, op[i]);
6815 if (mode == V2DFmode)
6816 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6818 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6822 if (mode == V2DFmode)
6823 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6825 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6830 /* Special case initializing vector int if we are on 64-bit systems with
6831 direct move or we have the ISA 3.0 instructions. */
6832 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6833 && TARGET_DIRECT_MOVE_64BIT)
6837 rtx element0 = XVECEXP (vals, 0, 0);
6838 if (MEM_P (element0))
6839 element0 = rs6000_address_for_fpconvert (element0);
6841 element0 = force_reg (SImode, element0);
6843 if (TARGET_P9_VECTOR)
6844 emit_insn (gen_vsx_splat_v4si (target, element0));
6847 rtx tmp = gen_reg_rtx (DImode);
6848 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6849 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6858 for (i = 0; i < 4; i++)
6860 elements[i] = XVECEXP (vals, 0, i);
6861 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
6862 elements[i] = copy_to_mode_reg (SImode, elements[i]);
6865 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6866 elements[2], elements[3]));
6871 /* With single precision floating point on VSX, know that internally single
6872 precision is actually represented as a double, and either make 2 V2DF
6873 vectors, and convert these vectors to single precision, or do one
6874 conversion, and splat the result to the other elements. */
6875 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6879 rtx element0 = XVECEXP (vals, 0, 0);
6881 if (TARGET_P9_VECTOR)
6883 if (MEM_P (element0))
6884 element0 = rs6000_address_for_fpconvert (element0);
6886 emit_insn (gen_vsx_splat_v4sf (target, element0));
6891 rtx freg = gen_reg_rtx (V4SFmode);
6892 rtx sreg = force_reg (SFmode, element0);
6893 rtx cvt = (TARGET_XSCVDPSPN
6894 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6895 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6898 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6904 rtx dbl_even = gen_reg_rtx (V2DFmode);
6905 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6906 rtx flt_even = gen_reg_rtx (V4SFmode);
6907 rtx flt_odd = gen_reg_rtx (V4SFmode);
6908 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6909 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6910 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6911 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6913 /* Use VMRGEW if we can instead of doing a permute. */
6914 if (TARGET_P8_VECTOR)
6916 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6917 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6918 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6919 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6920 if (BYTES_BIG_ENDIAN)
6921 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6923 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6927 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6928 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6929 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6930 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6931 rs6000_expand_extract_even (target, flt_even, flt_odd);
6937 /* Special case initializing vector short/char that are splats if we are on
6938 64-bit systems with direct move. */
6939 if (all_same && TARGET_DIRECT_MOVE_64BIT
6940 && (mode == V16QImode || mode == V8HImode))
6942 rtx op0 = XVECEXP (vals, 0, 0);
6943 rtx di_tmp = gen_reg_rtx (DImode);
6946 op0 = force_reg (GET_MODE_INNER (mode), op0);
6948 if (mode == V16QImode)
6950 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6951 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6955 if (mode == V8HImode)
6957 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6958 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6963 /* Store value to stack temp. Load vector element. Splat. However, splat
6964 of 64-bit items is not supported on Altivec. */
6965 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6967 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6968 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6969 XVECEXP (vals, 0, 0));
6970 x = gen_rtx_UNSPEC (VOIDmode,
6971 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6972 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6974 gen_rtx_SET (target, mem),
6976 x = gen_rtx_VEC_SELECT (inner_mode, target,
6977 gen_rtx_PARALLEL (VOIDmode,
6978 gen_rtvec (1, const0_rtx)));
6979 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6983 /* One field is non-constant. Load constant then overwrite
6987 rtx copy = copy_rtx (vals);
6989 /* Load constant part of vector, substitute neighboring value for
6991 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6992 rs6000_expand_vector_init (target, copy);
6994 /* Insert variable. */
6995 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6999 /* Construct the vector in memory one field at a time
7000 and load the whole vector. */
7001 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7002 for (i = 0; i < n_elts; i++)
7003 emit_move_insn (adjust_address_nv (mem, inner_mode,
7004 i * GET_MODE_SIZE (inner_mode)),
7005 XVECEXP (vals, 0, i));
7006 emit_move_insn (target, mem);
7009 /* Set field ELT of TARGET to VAL. */
7012 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7014 machine_mode mode = GET_MODE (target);
7015 machine_mode inner_mode = GET_MODE_INNER (mode);
7016 rtx reg = gen_reg_rtx (mode);
7018 int width = GET_MODE_SIZE (inner_mode);
7021 val = force_reg (GET_MODE (val), val);
7023 if (VECTOR_MEM_VSX_P (mode))
7025 rtx insn = NULL_RTX;
7026 rtx elt_rtx = GEN_INT (elt);
7028 if (mode == V2DFmode)
7029 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7031 else if (mode == V2DImode)
7032 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7034 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7036 if (mode == V4SImode)
7037 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7038 else if (mode == V8HImode)
7039 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7040 else if (mode == V16QImode)
7041 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7042 else if (mode == V4SFmode)
7043 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7053 /* Simplify setting single element vectors like V1TImode. */
7054 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7056 emit_move_insn (target, gen_lowpart (mode, val));
7060 /* Load single variable value. */
7061 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7062 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7063 x = gen_rtx_UNSPEC (VOIDmode,
7064 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7065 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7067 gen_rtx_SET (reg, mem),
7070 /* Linear sequence. */
7071 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7072 for (i = 0; i < 16; ++i)
7073 XVECEXP (mask, 0, i) = GEN_INT (i);
7075 /* Set permute mask to insert element into target. */
7076 for (i = 0; i < width; ++i)
7077 XVECEXP (mask, 0, elt*width + i)
7078 = GEN_INT (i + 0x10);
7079 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7081 if (BYTES_BIG_ENDIAN)
7082 x = gen_rtx_UNSPEC (mode,
7083 gen_rtvec (3, target, reg,
7084 force_reg (V16QImode, x)),
7088 if (TARGET_P9_VECTOR)
7089 x = gen_rtx_UNSPEC (mode,
7090 gen_rtvec (3, reg, target,
7091 force_reg (V16QImode, x)),
7095 /* Invert selector. We prefer to generate VNAND on P8 so
7096 that future fusion opportunities can kick in, but must
7097 generate VNOR elsewhere. */
7098 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7099 rtx iorx = (TARGET_P8_VECTOR
7100 ? gen_rtx_IOR (V16QImode, notx, notx)
7101 : gen_rtx_AND (V16QImode, notx, notx));
7102 rtx tmp = gen_reg_rtx (V16QImode);
7103 emit_insn (gen_rtx_SET (tmp, iorx));
7105 /* Permute with operands reversed and adjusted selector. */
7106 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7111 emit_insn (gen_rtx_SET (target, x));
7114 /* Extract field ELT from VEC into TARGET. */
7117 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7119 machine_mode mode = GET_MODE (vec);
7120 machine_mode inner_mode = GET_MODE_INNER (mode);
7123 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7130 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7131 emit_move_insn (target, gen_lowpart (TImode, vec));
7134 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7137 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7140 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7143 if (TARGET_DIRECT_MOVE_64BIT)
7145 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7151 if (TARGET_DIRECT_MOVE_64BIT)
7153 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7159 if (TARGET_DIRECT_MOVE_64BIT)
7161 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7167 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7168 && TARGET_DIRECT_MOVE_64BIT)
7170 if (GET_MODE (elt) != DImode)
7172 rtx tmp = gen_reg_rtx (DImode);
7173 convert_move (tmp, elt, 0);
7176 else if (!REG_P (elt))
7177 elt = force_reg (DImode, elt);
7182 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7186 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7190 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7194 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7198 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7202 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7210 gcc_assert (CONST_INT_P (elt));
7212 /* Allocate mode-sized buffer. */
7213 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7215 emit_move_insn (mem, vec);
7217 /* Add offset to field within buffer matching vector element. */
7218 mem = adjust_address_nv (mem, inner_mode,
7219 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7221 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7224 /* Helper function to return the register number of a RTX. */
7226 regno_or_subregno (rtx op)
7230 else if (SUBREG_P (op))
7231 return subreg_regno (op);
7236 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7237 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7238 temporary (BASE_TMP) to fixup the address. Return the new memory address
7239 that is valid for reads or writes to a given register (SCALAR_REG). */
7242 rs6000_adjust_vec_address (rtx scalar_reg,
7246 machine_mode scalar_mode)
7248 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7249 rtx addr = XEXP (mem, 0);
7254 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7255 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7257 /* Calculate what we need to add to the address to get the element
7259 if (CONST_INT_P (element))
7260 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7263 int byte_shift = exact_log2 (scalar_size);
7264 gcc_assert (byte_shift >= 0);
7266 if (byte_shift == 0)
7267 element_offset = element;
7271 if (TARGET_POWERPC64)
7272 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7274 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7276 element_offset = base_tmp;
7280 /* Create the new address pointing to the element within the vector. If we
7281 are adding 0, we don't have to change the address. */
7282 if (element_offset == const0_rtx)
7285 /* A simple indirect address can be converted into a reg + offset
7287 else if (REG_P (addr) || SUBREG_P (addr))
7288 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7290 /* Optimize D-FORM addresses with constant offset with a constant element, to
7291 include the element offset in the address directly. */
7292 else if (GET_CODE (addr) == PLUS)
7294 rtx op0 = XEXP (addr, 0);
7295 rtx op1 = XEXP (addr, 1);
7298 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7299 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7301 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7302 rtx offset_rtx = GEN_INT (offset);
7304 if (IN_RANGE (offset, -32768, 32767)
7305 && (scalar_size < 8 || (offset & 0x3) == 0))
7306 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7309 emit_move_insn (base_tmp, offset_rtx);
7310 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7315 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7316 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7318 /* Note, ADDI requires the register being added to be a base
7319 register. If the register was R0, load it up into the temporary
7322 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7324 insn = gen_add3_insn (base_tmp, op1, element_offset);
7325 gcc_assert (insn != NULL_RTX);
7330 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7332 insn = gen_add3_insn (base_tmp, element_offset, op1);
7333 gcc_assert (insn != NULL_RTX);
7339 emit_move_insn (base_tmp, op1);
7340 emit_insn (gen_add2_insn (base_tmp, element_offset));
7343 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7349 emit_move_insn (base_tmp, addr);
7350 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7353 /* If we have a PLUS, we need to see whether the particular register class
7354 allows for D-FORM or X-FORM addressing. */
7355 if (GET_CODE (new_addr) == PLUS)
7357 rtx op1 = XEXP (new_addr, 1);
7358 addr_mask_type addr_mask;
7359 int scalar_regno = regno_or_subregno (scalar_reg);
7361 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7362 if (INT_REGNO_P (scalar_regno))
7363 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7365 else if (FP_REGNO_P (scalar_regno))
7366 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7368 else if (ALTIVEC_REGNO_P (scalar_regno))
7369 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7374 if (REG_P (op1) || SUBREG_P (op1))
7375 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7377 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7380 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7381 valid_addr_p = true;
7384 valid_addr_p = false;
7388 emit_move_insn (base_tmp, new_addr);
7389 new_addr = base_tmp;
7392 return change_address (mem, scalar_mode, new_addr);
7395 /* Split a variable vec_extract operation into the component instructions. */
7398 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7401 machine_mode mode = GET_MODE (src);
7402 machine_mode scalar_mode = GET_MODE (dest);
7403 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7404 int byte_shift = exact_log2 (scalar_size);
7406 gcc_assert (byte_shift >= 0);
7408 /* If we are given a memory address, optimize to load just the element. We
7409 don't have to adjust the vector element number on little endian
7413 gcc_assert (REG_P (tmp_gpr));
7414 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7415 tmp_gpr, scalar_mode));
7419 else if (REG_P (src) || SUBREG_P (src))
7421 int bit_shift = byte_shift + 3;
7423 int dest_regno = regno_or_subregno (dest);
7424 int src_regno = regno_or_subregno (src);
7425 int element_regno = regno_or_subregno (element);
7427 gcc_assert (REG_P (tmp_gpr));
7429 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7430 a general purpose register. */
7431 if (TARGET_P9_VECTOR
7432 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7433 && INT_REGNO_P (dest_regno)
7434 && ALTIVEC_REGNO_P (src_regno)
7435 && INT_REGNO_P (element_regno))
7437 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7438 rtx element_si = gen_rtx_REG (SImode, element_regno);
7440 if (mode == V16QImode)
7441 emit_insn (BYTES_BIG_ENDIAN
7442 ? gen_vextublx (dest_si, element_si, src)
7443 : gen_vextubrx (dest_si, element_si, src));
7445 else if (mode == V8HImode)
7447 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7448 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7449 emit_insn (BYTES_BIG_ENDIAN
7450 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7451 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7457 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7458 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7459 emit_insn (BYTES_BIG_ENDIAN
7460 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7461 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7468 gcc_assert (REG_P (tmp_altivec));
7470 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7471 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7472 will shift the element into the upper position (adding 3 to convert a
7473 byte shift into a bit shift). */
7474 if (scalar_size == 8)
7476 if (!BYTES_BIG_ENDIAN)
7478 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7484 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7486 emit_insn (gen_rtx_SET (tmp_gpr,
7487 gen_rtx_AND (DImode,
7488 gen_rtx_ASHIFT (DImode,
7495 if (!BYTES_BIG_ENDIAN)
7497 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7499 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7500 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7506 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7509 /* Get the value into the lower byte of the Altivec register where VSLO
7511 if (TARGET_P9_VECTOR)
7512 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7513 else if (can_create_pseudo_p ())
7514 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7517 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7518 emit_move_insn (tmp_di, tmp_gpr);
7519 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7522 /* Do the VSLO to get the value into the final location. */
7526 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7530 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7535 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7536 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7537 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7538 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7541 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7549 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7550 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7551 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7552 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7554 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7555 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7556 GEN_INT (64 - (8 * scalar_size))));
7570 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7571 two SImode values. */
7574 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7576 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7578 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7580 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7581 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7583 emit_move_insn (dest, GEN_INT (const1 | const2));
7587 /* Put si1 into upper 32-bits of dest. */
7588 if (CONST_INT_P (si1))
7589 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7592 /* Generate RLDIC. */
7593 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7594 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7595 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7596 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7597 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7598 emit_insn (gen_rtx_SET (dest, and_rtx));
7601 /* Put si2 into the temporary. */
7602 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7603 if (CONST_INT_P (si2))
7604 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7606 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7608 /* Combine the two parts. */
7609 emit_insn (gen_iordi3 (dest, dest, tmp));
7613 /* Split a V4SI initialization. */
7616 rs6000_split_v4si_init (rtx operands[])
7618 rtx dest = operands[0];
7620 /* Destination is a GPR, build up the two DImode parts in place. */
7621 if (REG_P (dest) || SUBREG_P (dest))
7623 int d_regno = regno_or_subregno (dest);
7624 rtx scalar1 = operands[1];
7625 rtx scalar2 = operands[2];
7626 rtx scalar3 = operands[3];
7627 rtx scalar4 = operands[4];
7628 rtx tmp1 = operands[5];
7629 rtx tmp2 = operands[6];
7631 /* Even though we only need one temporary (plus the destination, which
7632 has an early clobber constraint, try to use two temporaries, one for
7633 each double word created. That way the 2nd insn scheduling pass can
7634 rearrange things so the two parts are done in parallel. */
7635 if (BYTES_BIG_ENDIAN)
7637 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7638 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7639 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7640 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7644 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7645 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7646 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7647 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7656 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7657 selects whether the alignment is abi mandated, optional, or
7658 both abi and optional alignment. */
7661 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7663 if (how != align_opt)
7665 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7669 if (how != align_abi)
7671 if (TREE_CODE (type) == ARRAY_TYPE
7672 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7674 if (align < BITS_PER_WORD)
7675 align = BITS_PER_WORD;
7682 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7683 instructions simply ignore the low bits; VSX memory instructions
7684 are aligned to 4 or 8 bytes. */
7687 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7689 return (STRICT_ALIGNMENT
7690 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7691 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7692 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7693 && (int) align < VECTOR_ALIGN (mode)))));
7696 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7699 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7701 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7703 if (computed != 128)
7706 if (!warned && warn_psabi)
7709 inform (input_location,
7710 "the layout of aggregates containing vectors with"
7711 " %d-byte alignment has changed in GCC 5",
7712 computed / BITS_PER_UNIT);
7715 /* In current GCC there is no special case. */
7722 /* AIX increases natural record alignment to doubleword if the first
7723 field is an FP double while the FP fields remain word aligned. */
7726 rs6000_special_round_type_align (tree type, unsigned int computed,
7727 unsigned int specified)
7729 unsigned int align = MAX (computed, specified);
7730 tree field = TYPE_FIELDS (type);
7732 /* Skip all non field decls */
7733 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7734 field = DECL_CHAIN (field);
7736 if (field != NULL && field != type)
7738 type = TREE_TYPE (field);
7739 while (TREE_CODE (type) == ARRAY_TYPE)
7740 type = TREE_TYPE (type);
7742 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7743 align = MAX (align, 64);
7749 /* Darwin increases record alignment to the natural alignment of
7753 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7754 unsigned int specified)
7756 unsigned int align = MAX (computed, specified);
7758 if (TYPE_PACKED (type))
7761 /* Find the first field, looking down into aggregates. */
7763 tree field = TYPE_FIELDS (type);
7764 /* Skip all non field decls */
7765 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7766 field = DECL_CHAIN (field);
7769 /* A packed field does not contribute any extra alignment. */
7770 if (DECL_PACKED (field))
7772 type = TREE_TYPE (field);
7773 while (TREE_CODE (type) == ARRAY_TYPE)
7774 type = TREE_TYPE (type);
7775 } while (AGGREGATE_TYPE_P (type));
7777 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7778 align = MAX (align, TYPE_ALIGN (type));
7783 /* Return 1 for an operand in small memory on V.4/eabi. */
7786 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7787 machine_mode mode ATTRIBUTE_UNUSED)
7792 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7795 if (DEFAULT_ABI != ABI_V4)
7798 if (GET_CODE (op) == SYMBOL_REF)
7801 else if (GET_CODE (op) != CONST
7802 || GET_CODE (XEXP (op, 0)) != PLUS
7803 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
7804 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7809 rtx sum = XEXP (op, 0);
7810 HOST_WIDE_INT summand;
7812 /* We have to be careful here, because it is the referenced address
7813 that must be 32k from _SDA_BASE_, not just the symbol. */
7814 summand = INTVAL (XEXP (sum, 1));
7815 if (summand < 0 || summand > g_switch_value)
7818 sym_ref = XEXP (sum, 0);
7821 return SYMBOL_REF_SMALL_P (sym_ref);
7827 /* Return true if either operand is a general purpose register. */
7830 gpr_or_gpr_p (rtx op0, rtx op1)
7832 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7833 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7836 /* Return true if this is a move direct operation between GPR registers and
7837 floating point/VSX registers. */
7840 direct_move_p (rtx op0, rtx op1)
7844 if (!REG_P (op0) || !REG_P (op1))
7847 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7850 regno0 = REGNO (op0);
7851 regno1 = REGNO (op1);
7852 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
7855 if (INT_REGNO_P (regno0))
7856 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7858 else if (INT_REGNO_P (regno1))
7860 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7863 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7870 /* Return true if the OFFSET is valid for the quad address instructions that
7871 use d-form (register + offset) addressing. */
7874 quad_address_offset_p (HOST_WIDE_INT offset)
7876 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7879 /* Return true if the ADDR is an acceptable address for a quad memory
7880 operation of mode MODE (either LQ/STQ for general purpose registers, or
7881 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7882 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7883 3.0 LXV/STXV instruction. */
7886 quad_address_p (rtx addr, machine_mode mode, bool strict)
7890 if (GET_MODE_SIZE (mode) != 16)
7893 if (legitimate_indirect_address_p (addr, strict))
7896 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7899 if (GET_CODE (addr) != PLUS)
7902 op0 = XEXP (addr, 0);
7903 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7906 op1 = XEXP (addr, 1);
7907 if (!CONST_INT_P (op1))
7910 return quad_address_offset_p (INTVAL (op1));
7913 /* Return true if this is a load or store quad operation. This function does
7914 not handle the atomic quad memory instructions. */
7917 quad_load_store_p (rtx op0, rtx op1)
7921 if (!TARGET_QUAD_MEMORY)
7924 else if (REG_P (op0) && MEM_P (op1))
7925 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7926 && quad_memory_operand (op1, GET_MODE (op1))
7927 && !reg_overlap_mentioned_p (op0, op1));
7929 else if (MEM_P (op0) && REG_P (op1))
7930 ret = (quad_memory_operand (op0, GET_MODE (op0))
7931 && quad_int_reg_operand (op1, GET_MODE (op1)));
7936 if (TARGET_DEBUG_ADDR)
7938 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7939 ret ? "true" : "false");
7940 debug_rtx (gen_rtx_SET (op0, op1));
7946 /* Given an address, return a constant offset term if one exists. */
7949 address_offset (rtx op)
7951 if (GET_CODE (op) == PRE_INC
7952 || GET_CODE (op) == PRE_DEC)
7954 else if (GET_CODE (op) == PRE_MODIFY
7955 || GET_CODE (op) == LO_SUM)
7958 if (GET_CODE (op) == CONST)
7961 if (GET_CODE (op) == PLUS)
7964 if (CONST_INT_P (op))
7970 /* Return true if the MEM operand is a memory operand suitable for use
7971 with a (full width, possibly multiple) gpr load/store. On
7972 powerpc64 this means the offset must be divisible by 4.
7973 Implements 'Y' constraint.
7975 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7976 a constraint function we know the operand has satisfied a suitable
7977 memory predicate. Also accept some odd rtl generated by reload
7978 (see rs6000_legitimize_reload_address for various forms). It is
7979 important that reload rtl be accepted by appropriate constraints
7980 but not by the operand predicate.
7982 Offsetting a lo_sum should not be allowed, except where we know by
7983 alignment that a 32k boundary is not crossed, but see the ???
7984 comment in rs6000_legitimize_reload_address. Note that by
7985 "offsetting" here we mean a further offset to access parts of the
7986 MEM. It's fine to have a lo_sum where the inner address is offset
7987 from a sym, since the same sym+offset will appear in the high part
7988 of the address calculation. */
7991 mem_operand_gpr (rtx op, machine_mode mode)
7993 unsigned HOST_WIDE_INT offset;
7995 rtx addr = XEXP (op, 0);
7997 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7998 if (!rs6000_offsettable_memref_p (op, mode, false))
8001 op = address_offset (addr);
8005 offset = INTVAL (op);
8006 if (TARGET_POWERPC64 && (offset & 3) != 0)
8009 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8013 if (GET_CODE (addr) == LO_SUM)
8014 /* For lo_sum addresses, we must allow any offset except one that
8015 causes a wrap, so test only the low 16 bits. */
8016 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8018 return offset + 0x8000 < 0x10000u - extra;
8021 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8022 enforce an offset divisible by 4 even for 32-bit. */
8025 mem_operand_ds_form (rtx op, machine_mode mode)
8027 unsigned HOST_WIDE_INT offset;
8029 rtx addr = XEXP (op, 0);
8031 if (!offsettable_address_p (false, mode, addr))
8034 op = address_offset (addr);
8038 offset = INTVAL (op);
8039 if ((offset & 3) != 0)
8042 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8046 if (GET_CODE (addr) == LO_SUM)
8047 /* For lo_sum addresses, we must allow any offset except one that
8048 causes a wrap, so test only the low 16 bits. */
8049 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8051 return offset + 0x8000 < 0x10000u - extra;
8054 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8057 reg_offset_addressing_ok_p (machine_mode mode)
8071 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8072 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8073 a vector mode, if we want to use the VSX registers to move it around,
8074 we need to restrict ourselves to reg+reg addressing. Similarly for
8075 IEEE 128-bit floating point that is passed in a single vector
8077 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8078 return mode_supports_dq_form (mode);
8082 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8083 addressing for the LFIWZX and STFIWX instructions. */
8084 if (TARGET_NO_SDMODE_STACK)
8096 virtual_stack_registers_memory_p (rtx op)
8100 if (GET_CODE (op) == REG)
8101 regnum = REGNO (op);
8103 else if (GET_CODE (op) == PLUS
8104 && GET_CODE (XEXP (op, 0)) == REG
8105 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8106 regnum = REGNO (XEXP (op, 0));
8111 return (regnum >= FIRST_VIRTUAL_REGISTER
8112 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8115 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8116 is known to not straddle a 32k boundary. This function is used
8117 to determine whether -mcmodel=medium code can use TOC pointer
8118 relative addressing for OP. This means the alignment of the TOC
8119 pointer must also be taken into account, and unfortunately that is
8122 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8123 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8127 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8131 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8133 if (GET_CODE (op) != SYMBOL_REF)
8136 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8138 if (mode_supports_dq_form (mode))
8141 dsize = GET_MODE_SIZE (mode);
8142 decl = SYMBOL_REF_DECL (op);
8148 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8149 replacing memory addresses with an anchor plus offset. We
8150 could find the decl by rummaging around in the block->objects
8151 VEC for the given offset but that seems like too much work. */
8152 dalign = BITS_PER_UNIT;
8153 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8154 && SYMBOL_REF_ANCHOR_P (op)
8155 && SYMBOL_REF_BLOCK (op) != NULL)
8157 struct object_block *block = SYMBOL_REF_BLOCK (op);
8159 dalign = block->alignment;
8160 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8162 else if (CONSTANT_POOL_ADDRESS_P (op))
8164 /* It would be nice to have get_pool_align().. */
8165 machine_mode cmode = get_pool_mode (op);
8167 dalign = GET_MODE_ALIGNMENT (cmode);
8170 else if (DECL_P (decl))
8172 dalign = DECL_ALIGN (decl);
8176 /* Allow BLKmode when the entire object is known to not
8177 cross a 32k boundary. */
8178 if (!DECL_SIZE_UNIT (decl))
8181 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8184 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8188 dalign /= BITS_PER_UNIT;
8189 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8190 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8191 return dalign >= dsize;
8197 /* Find how many bits of the alignment we know for this access. */
8198 dalign /= BITS_PER_UNIT;
8199 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8200 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8202 lsb = offset & -offset;
8206 return dalign >= dsize;
8210 constant_pool_expr_p (rtx op)
8214 split_const (op, &base, &offset);
8215 return (GET_CODE (base) == SYMBOL_REF
8216 && CONSTANT_POOL_ADDRESS_P (base)
8217 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8220 /* These are only used to pass through from print_operand/print_operand_address
8221 to rs6000_output_addr_const_extra over the intervening function
8222 output_addr_const which is not target code. */
8223 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8225 /* Return true if OP is a toc pointer relative address (the output
8226 of create_TOC_reference). If STRICT, do not match non-split
8227 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8228 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8229 TOCREL_OFFSET_RET respectively. */
8232 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8233 const_rtx *tocrel_offset_ret)
8238 if (TARGET_CMODEL != CMODEL_SMALL)
8240 /* When strict ensure we have everything tidy. */
8242 && !(GET_CODE (op) == LO_SUM
8243 && REG_P (XEXP (op, 0))
8244 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8247 /* When not strict, allow non-split TOC addresses and also allow
8248 (lo_sum (high ..)) TOC addresses created during reload. */
8249 if (GET_CODE (op) == LO_SUM)
8253 const_rtx tocrel_base = op;
8254 const_rtx tocrel_offset = const0_rtx;
8256 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8258 tocrel_base = XEXP (op, 0);
8259 tocrel_offset = XEXP (op, 1);
8262 if (tocrel_base_ret)
8263 *tocrel_base_ret = tocrel_base;
8264 if (tocrel_offset_ret)
8265 *tocrel_offset_ret = tocrel_offset;
8267 return (GET_CODE (tocrel_base) == UNSPEC
8268 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8271 /* Return true if X is a constant pool address, and also for cmodel=medium
8272 if X is a toc-relative address known to be offsettable within MODE. */
8275 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8278 const_rtx tocrel_base, tocrel_offset;
8279 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8280 && (TARGET_CMODEL != CMODEL_MEDIUM
8281 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8283 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8284 INTVAL (tocrel_offset), mode)));
8288 legitimate_small_data_p (machine_mode mode, rtx x)
8290 return (DEFAULT_ABI == ABI_V4
8291 && !flag_pic && !TARGET_TOC
8292 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8293 && small_data_operand (x, mode));
8297 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8298 bool strict, bool worst_case)
8300 unsigned HOST_WIDE_INT offset;
8303 if (GET_CODE (x) != PLUS)
8305 if (!REG_P (XEXP (x, 0)))
8307 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8309 if (mode_supports_dq_form (mode))
8310 return quad_address_p (x, mode, strict);
8311 if (!reg_offset_addressing_ok_p (mode))
8312 return virtual_stack_registers_memory_p (x);
8313 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8315 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8318 offset = INTVAL (XEXP (x, 1));
8325 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8327 if (VECTOR_MEM_VSX_P (mode))
8332 if (!TARGET_POWERPC64)
8334 else if (offset & 3)
8347 if (!TARGET_POWERPC64)
8349 else if (offset & 3)
8358 return offset < 0x10000 - extra;
8362 legitimate_indexed_address_p (rtx x, int strict)
8366 if (GET_CODE (x) != PLUS)
8372 return (REG_P (op0) && REG_P (op1)
8373 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8374 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8375 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8376 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8380 avoiding_indexed_address_p (machine_mode mode)
8382 /* Avoid indexed addressing for modes that have non-indexed
8383 load/store instruction forms. */
8384 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8388 legitimate_indirect_address_p (rtx x, int strict)
8390 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8394 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8396 if (!TARGET_MACHO || !flag_pic
8397 || mode != SImode || GET_CODE (x) != MEM)
8401 if (GET_CODE (x) != LO_SUM)
8403 if (GET_CODE (XEXP (x, 0)) != REG)
8405 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8409 return CONSTANT_P (x);
8413 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8415 if (GET_CODE (x) != LO_SUM)
8417 if (GET_CODE (XEXP (x, 0)) != REG)
8419 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8421 /* quad word addresses are restricted, and we can't use LO_SUM. */
8422 if (mode_supports_dq_form (mode))
8426 if (TARGET_ELF || TARGET_MACHO)
8430 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8432 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8433 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8434 recognizes some LO_SUM addresses as valid although this
8435 function says opposite. In most cases, LRA through different
8436 transformations can generate correct code for address reloads.
8437 It can not manage only some LO_SUM cases. So we need to add
8438 code analogous to one in rs6000_legitimize_reload_address for
8439 LOW_SUM here saying that some addresses are still valid. */
8440 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8441 && small_toc_ref (x, VOIDmode));
8442 if (TARGET_TOC && ! large_toc_ok)
8444 if (GET_MODE_NUNITS (mode) != 1)
8446 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8447 && !(/* ??? Assume floating point reg based on mode? */
8448 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8451 return CONSTANT_P (x) || large_toc_ok;
8458 /* Try machine-dependent ways of modifying an illegitimate address
8459 to be legitimate. If we find one, return the new, valid address.
8460 This is used from only one place: `memory_address' in explow.c.
8462 OLDX is the address as it was before break_out_memory_refs was
8463 called. In some cases it is useful to look at this to decide what
8466 It is always safe for this function to do nothing. It exists to
8467 recognize opportunities to optimize the output.
8469 On RS/6000, first check for the sum of a register with a constant
8470 integer that is out of range. If so, generate code to add the
8471 constant with the low-order 16 bits masked to the register and force
8472 this result into another register (this can be done with `cau').
8473 Then generate an address of REG+(CONST&0xffff), allowing for the
8474 possibility of bit 16 being a one.
8476 Then check for the sum of a register and something not constant, try to
8477 load the other things into a register and return the sum. */
8480 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8485 if (!reg_offset_addressing_ok_p (mode)
8486 || mode_supports_dq_form (mode))
8488 if (virtual_stack_registers_memory_p (x))
8491 /* In theory we should not be seeing addresses of the form reg+0,
8492 but just in case it is generated, optimize it away. */
8493 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8494 return force_reg (Pmode, XEXP (x, 0));
8496 /* For TImode with load/store quad, restrict addresses to just a single
8497 pointer, so it works with both GPRs and VSX registers. */
8498 /* Make sure both operands are registers. */
8499 else if (GET_CODE (x) == PLUS
8500 && (mode != TImode || !TARGET_VSX))
8501 return gen_rtx_PLUS (Pmode,
8502 force_reg (Pmode, XEXP (x, 0)),
8503 force_reg (Pmode, XEXP (x, 1)));
8505 return force_reg (Pmode, x);
8507 if (GET_CODE (x) == SYMBOL_REF)
8509 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8511 return rs6000_legitimize_tls_address (x, model);
8523 /* As in legitimate_offset_address_p we do not assume
8524 worst-case. The mode here is just a hint as to the registers
8525 used. A TImode is usually in gprs, but may actually be in
8526 fprs. Leave worst-case scenario for reload to handle via
8527 insn constraints. PTImode is only GPRs. */
8534 if (GET_CODE (x) == PLUS
8535 && GET_CODE (XEXP (x, 0)) == REG
8536 && GET_CODE (XEXP (x, 1)) == CONST_INT
8537 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8538 >= 0x10000 - extra))
8540 HOST_WIDE_INT high_int, low_int;
8542 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8543 if (low_int >= 0x8000 - extra)
8545 high_int = INTVAL (XEXP (x, 1)) - low_int;
8546 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8547 GEN_INT (high_int)), 0);
8548 return plus_constant (Pmode, sum, low_int);
8550 else if (GET_CODE (x) == PLUS
8551 && GET_CODE (XEXP (x, 0)) == REG
8552 && GET_CODE (XEXP (x, 1)) != CONST_INT
8553 && GET_MODE_NUNITS (mode) == 1
8554 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8555 || (/* ??? Assume floating point reg based on mode? */
8556 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8557 && !avoiding_indexed_address_p (mode))
8559 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8560 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8562 else if ((TARGET_ELF
8564 || !MACHO_DYNAMIC_NO_PIC_P
8570 && GET_CODE (x) != CONST_INT
8571 && GET_CODE (x) != CONST_WIDE_INT
8572 && GET_CODE (x) != CONST_DOUBLE
8574 && GET_MODE_NUNITS (mode) == 1
8575 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8576 || (/* ??? Assume floating point reg based on mode? */
8577 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8579 rtx reg = gen_reg_rtx (Pmode);
8581 emit_insn (gen_elf_high (reg, x));
8583 emit_insn (gen_macho_high (reg, x));
8584 return gen_rtx_LO_SUM (Pmode, reg, x);
8587 && GET_CODE (x) == SYMBOL_REF
8588 && constant_pool_expr_p (x)
8589 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8590 return create_TOC_reference (x, NULL_RTX);
8595 /* Debug version of rs6000_legitimize_address. */
8597 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8603 ret = rs6000_legitimize_address (x, oldx, mode);
8604 insns = get_insns ();
8610 "\nrs6000_legitimize_address: mode %s, old code %s, "
8611 "new code %s, modified\n",
8612 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8613 GET_RTX_NAME (GET_CODE (ret)));
8615 fprintf (stderr, "Original address:\n");
8618 fprintf (stderr, "oldx:\n");
8621 fprintf (stderr, "New address:\n");
8626 fprintf (stderr, "Insns added:\n");
8627 debug_rtx_list (insns, 20);
8633 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8634 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8645 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8646 We need to emit DTP-relative relocations. */
8648 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8650 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8655 fputs ("\t.long\t", file);
8658 fputs (DOUBLE_INT_ASM_OP, file);
8663 output_addr_const (file, x);
8665 fputs ("@dtprel+0x8000", file);
8666 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8668 switch (SYMBOL_REF_TLS_MODEL (x))
8672 case TLS_MODEL_LOCAL_EXEC:
8673 fputs ("@le", file);
8675 case TLS_MODEL_INITIAL_EXEC:
8676 fputs ("@ie", file);
8678 case TLS_MODEL_GLOBAL_DYNAMIC:
8679 case TLS_MODEL_LOCAL_DYNAMIC:
8688 /* Return true if X is a symbol that refers to real (rather than emulated)
8692 rs6000_real_tls_symbol_ref_p (rtx x)
8694 return (GET_CODE (x) == SYMBOL_REF
8695 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8698 /* In the name of slightly smaller debug output, and to cater to
8699 general assembler lossage, recognize various UNSPEC sequences
8700 and turn them back into a direct symbol reference. */
8703 rs6000_delegitimize_address (rtx orig_x)
8707 orig_x = delegitimize_mem_from_attrs (orig_x);
8713 if (TARGET_CMODEL != CMODEL_SMALL
8714 && GET_CODE (y) == LO_SUM)
8718 if (GET_CODE (y) == PLUS
8719 && GET_MODE (y) == Pmode
8720 && CONST_INT_P (XEXP (y, 1)))
8722 offset = XEXP (y, 1);
8726 if (GET_CODE (y) == UNSPEC
8727 && XINT (y, 1) == UNSPEC_TOCREL)
8729 y = XVECEXP (y, 0, 0);
8732 /* Do not associate thread-local symbols with the original
8733 constant pool symbol. */
8735 && GET_CODE (y) == SYMBOL_REF
8736 && CONSTANT_POOL_ADDRESS_P (y)
8737 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8741 if (offset != NULL_RTX)
8742 y = gen_rtx_PLUS (Pmode, y, offset);
8743 if (!MEM_P (orig_x))
8746 return replace_equiv_address_nv (orig_x, y);
8750 && GET_CODE (orig_x) == LO_SUM
8751 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8753 y = XEXP (XEXP (orig_x, 1), 0);
8754 if (GET_CODE (y) == UNSPEC
8755 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8756 return XVECEXP (y, 0, 0);
8762 /* Return true if X shouldn't be emitted into the debug info.
8763 The linker doesn't like .toc section references from
8764 .debug_* sections, so reject .toc section symbols. */
8767 rs6000_const_not_ok_for_debug_p (rtx x)
8769 if (GET_CODE (x) == UNSPEC)
8771 if (GET_CODE (x) == SYMBOL_REF
8772 && CONSTANT_POOL_ADDRESS_P (x))
8774 rtx c = get_pool_constant (x);
8775 machine_mode cmode = get_pool_mode (x);
8776 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8784 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8787 rs6000_legitimate_combined_insn (rtx_insn *insn)
8789 int icode = INSN_CODE (insn);
8791 /* Reject creating doloop insns. Combine should not be allowed
8792 to create these for a number of reasons:
8793 1) In a nested loop, if combine creates one of these in an
8794 outer loop and the register allocator happens to allocate ctr
8795 to the outer loop insn, then the inner loop can't use ctr.
8796 Inner loops ought to be more highly optimized.
8797 2) Combine often wants to create one of these from what was
8798 originally a three insn sequence, first combining the three
8799 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8800 allocated ctr, the splitter takes use back to the three insn
8801 sequence. It's better to stop combine at the two insn
8803 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8804 insns, the register allocator sometimes uses floating point
8805 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8806 jump insn and output reloads are not implemented for jumps,
8807 the ctrsi/ctrdi splitters need to handle all possible cases.
8808 That's a pain, and it gets to be seriously difficult when a
8809 splitter that runs after reload needs memory to transfer from
8810 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8811 for the difficult case. It's better to not create problems
8812 in the first place. */
8813 if (icode != CODE_FOR_nothing
8814 && (icode == CODE_FOR_bdz_si
8815 || icode == CODE_FOR_bdz_di
8816 || icode == CODE_FOR_bdnz_si
8817 || icode == CODE_FOR_bdnz_di
8818 || icode == CODE_FOR_bdztf_si
8819 || icode == CODE_FOR_bdztf_di
8820 || icode == CODE_FOR_bdnztf_si
8821 || icode == CODE_FOR_bdnztf_di))
8827 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8829 static GTY(()) rtx rs6000_tls_symbol;
8831 rs6000_tls_get_addr (void)
8833 if (!rs6000_tls_symbol)
8834 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8836 return rs6000_tls_symbol;
8839 /* Construct the SYMBOL_REF for TLS GOT references. */
8841 static GTY(()) rtx rs6000_got_symbol;
8843 rs6000_got_sym (void)
8845 if (!rs6000_got_symbol)
8847 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8848 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8849 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8852 return rs6000_got_symbol;
8855 /* AIX Thread-Local Address support. */
8858 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8860 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8864 name = XSTR (addr, 0);
8865 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8866 or the symbol will be in TLS private data section. */
8867 if (name[strlen (name) - 1] != ']'
8868 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8869 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8871 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8872 strcpy (tlsname, name);
8874 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8875 tlsaddr = copy_rtx (addr);
8876 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8881 /* Place addr into TOC constant pool. */
8882 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8884 /* Output the TOC entry and create the MEM referencing the value. */
8885 if (constant_pool_expr_p (XEXP (sym, 0))
8886 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8888 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8889 mem = gen_const_mem (Pmode, tocref);
8890 set_mem_alias_set (mem, get_TOC_alias_set ());
8895 /* Use global-dynamic for local-dynamic. */
8896 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8897 || model == TLS_MODEL_LOCAL_DYNAMIC)
8899 /* Create new TOC reference for @m symbol. */
8900 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8901 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8902 strcpy (tlsname, "*LCM");
8903 strcat (tlsname, name + 3);
8904 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8905 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8906 tocref = create_TOC_reference (modaddr, NULL_RTX);
8907 rtx modmem = gen_const_mem (Pmode, tocref);
8908 set_mem_alias_set (modmem, get_TOC_alias_set ());
8910 rtx modreg = gen_reg_rtx (Pmode);
8911 emit_insn (gen_rtx_SET (modreg, modmem));
8913 tmpreg = gen_reg_rtx (Pmode);
8914 emit_insn (gen_rtx_SET (tmpreg, mem));
8916 dest = gen_reg_rtx (Pmode);
8918 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8920 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8923 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8924 else if (TARGET_32BIT)
8926 tlsreg = gen_reg_rtx (SImode);
8927 emit_insn (gen_tls_get_tpointer (tlsreg));
8930 tlsreg = gen_rtx_REG (DImode, 13);
8932 /* Load the TOC value into temporary register. */
8933 tmpreg = gen_reg_rtx (Pmode);
8934 emit_insn (gen_rtx_SET (tmpreg, mem));
8935 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8936 gen_rtx_MINUS (Pmode, addr, tlsreg));
8938 /* Add TOC symbol value to TLS pointer. */
8939 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8944 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8945 this (thread-local) address. */
8948 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8953 return rs6000_legitimize_tls_address_aix (addr, model);
8955 dest = gen_reg_rtx (Pmode);
8956 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8962 tlsreg = gen_rtx_REG (Pmode, 13);
8963 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8967 tlsreg = gen_rtx_REG (Pmode, 2);
8968 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8972 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8976 tmp = gen_reg_rtx (Pmode);
8979 tlsreg = gen_rtx_REG (Pmode, 13);
8980 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8984 tlsreg = gen_rtx_REG (Pmode, 2);
8985 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8989 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8991 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8996 rtx r3, got, tga, tmp1, tmp2, call_insn;
8998 /* We currently use relocations like @got@tlsgd for tls, which
8999 means the linker will handle allocation of tls entries, placing
9000 them in the .got section. So use a pointer to the .got section,
9001 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9002 or to secondary GOT sections used by 32-bit -fPIC. */
9004 got = gen_rtx_REG (Pmode, 2);
9008 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9011 rtx gsym = rs6000_got_sym ();
9012 got = gen_reg_rtx (Pmode);
9014 rs6000_emit_move (got, gsym, Pmode);
9019 tmp1 = gen_reg_rtx (Pmode);
9020 tmp2 = gen_reg_rtx (Pmode);
9021 mem = gen_const_mem (Pmode, tmp1);
9022 lab = gen_label_rtx ();
9023 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9024 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9025 if (TARGET_LINK_STACK)
9026 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9027 emit_move_insn (tmp2, mem);
9028 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9029 set_unique_reg_note (last, REG_EQUAL, gsym);
9034 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9036 tga = rs6000_tls_get_addr ();
9037 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9040 r3 = gen_rtx_REG (Pmode, 3);
9041 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9044 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9046 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9048 else if (DEFAULT_ABI == ABI_V4)
9049 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9052 call_insn = last_call_insn ();
9053 PATTERN (call_insn) = insn;
9054 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9055 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9056 pic_offset_table_rtx);
9058 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9060 tga = rs6000_tls_get_addr ();
9061 tmp1 = gen_reg_rtx (Pmode);
9062 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9065 r3 = gen_rtx_REG (Pmode, 3);
9066 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9069 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9071 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9073 else if (DEFAULT_ABI == ABI_V4)
9074 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9077 call_insn = last_call_insn ();
9078 PATTERN (call_insn) = insn;
9079 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9080 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9081 pic_offset_table_rtx);
9083 if (rs6000_tls_size == 16)
9086 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9088 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9090 else if (rs6000_tls_size == 32)
9092 tmp2 = gen_reg_rtx (Pmode);
9094 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9096 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9099 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9101 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9105 tmp2 = gen_reg_rtx (Pmode);
9107 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9109 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9111 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9117 /* IE, or 64-bit offset LE. */
9118 tmp2 = gen_reg_rtx (Pmode);
9120 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9122 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9125 insn = gen_tls_tls_64 (dest, tmp2, addr);
9127 insn = gen_tls_tls_32 (dest, tmp2, addr);
9135 /* Only create the global variable for the stack protect guard if we are using
9136 the global flavor of that guard. */
9138 rs6000_init_stack_protect_guard (void)
9140 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9141 return default_stack_protect_guard ();
9146 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9149 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9151 if (GET_CODE (x) == HIGH
9152 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9155 /* A TLS symbol in the TOC cannot contain a sum. */
9156 if (GET_CODE (x) == CONST
9157 && GET_CODE (XEXP (x, 0)) == PLUS
9158 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9159 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9162 /* Do not place an ELF TLS symbol in the constant pool. */
9163 return TARGET_ELF && tls_referenced_p (x);
9166 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9167 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9168 can be addressed relative to the toc pointer. */
9171 use_toc_relative_ref (rtx sym, machine_mode mode)
9173 return ((constant_pool_expr_p (sym)
9174 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9175 get_pool_mode (sym)))
9176 || (TARGET_CMODEL == CMODEL_MEDIUM
9177 && SYMBOL_REF_LOCAL_P (sym)
9178 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9181 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9182 replace the input X, or the original X if no replacement is called for.
9183 The output parameter *WIN is 1 if the calling macro should goto WIN,
9186 For RS/6000, we wish to handle large displacements off a base
9187 register by splitting the addend across an addiu/addis and the mem insn.
9188 This cuts number of extra insns needed from 3 to 1.
9190 On Darwin, we use this to generate code for floating point constants.
9191 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9192 The Darwin code is inside #if TARGET_MACHO because only then are the
9193 machopic_* functions defined. */
9195 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9196 int opnum, int type,
9197 int ind_levels ATTRIBUTE_UNUSED, int *win)
9199 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9200 bool quad_offset_p = mode_supports_dq_form (mode);
9202 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9203 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9206 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9207 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9208 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9209 && TARGET_P9_VECTOR)
9210 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9211 && TARGET_P9_VECTOR)))
9212 reg_offset_p = false;
9214 /* We must recognize output that we have already generated ourselves. */
9215 if (GET_CODE (x) == PLUS
9216 && GET_CODE (XEXP (x, 0)) == PLUS
9217 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9218 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9219 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9221 if (TARGET_DEBUG_ADDR)
9223 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9226 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9227 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9228 opnum, (enum reload_type) type);
9233 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9234 if (GET_CODE (x) == LO_SUM
9235 && GET_CODE (XEXP (x, 0)) == HIGH)
9237 if (TARGET_DEBUG_ADDR)
9239 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9242 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9243 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9244 opnum, (enum reload_type) type);
9250 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9251 && GET_CODE (x) == LO_SUM
9252 && GET_CODE (XEXP (x, 0)) == PLUS
9253 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9254 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9255 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9256 && machopic_operand_p (XEXP (x, 1)))
9258 /* Result of previous invocation of this function on Darwin
9259 floating point constant. */
9260 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9261 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9262 opnum, (enum reload_type) type);
9268 if (TARGET_CMODEL != CMODEL_SMALL
9271 && small_toc_ref (x, VOIDmode))
9273 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9274 x = gen_rtx_LO_SUM (Pmode, hi, x);
9275 if (TARGET_DEBUG_ADDR)
9277 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9280 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9281 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9282 opnum, (enum reload_type) type);
9287 if (GET_CODE (x) == PLUS
9288 && REG_P (XEXP (x, 0))
9289 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9290 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9291 && CONST_INT_P (XEXP (x, 1))
9293 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9295 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9296 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9298 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9300 /* Check for 32-bit overflow or quad addresses with one of the
9301 four least significant bits set. */
9302 if (high + low != val
9303 || (quad_offset_p && (low & 0xf)))
9309 /* Reload the high part into a base reg; leave the low part
9310 in the mem directly. */
9312 x = gen_rtx_PLUS (GET_MODE (x),
9313 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9317 if (TARGET_DEBUG_ADDR)
9319 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9322 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9323 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9324 opnum, (enum reload_type) type);
9329 if (GET_CODE (x) == SYMBOL_REF
9332 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9334 && DEFAULT_ABI == ABI_DARWIN
9335 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9336 && machopic_symbol_defined_p (x)
9338 && DEFAULT_ABI == ABI_V4
9341 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9342 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9344 ??? Assume floating point reg based on mode? This assumption is
9345 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9346 where reload ends up doing a DFmode load of a constant from
9347 mem using two gprs. Unfortunately, at this point reload
9348 hasn't yet selected regs so poking around in reload data
9349 won't help and even if we could figure out the regs reliably,
9350 we'd still want to allow this transformation when the mem is
9351 naturally aligned. Since we say the address is good here, we
9352 can't disable offsets from LO_SUMs in mem_operand_gpr.
9353 FIXME: Allow offset from lo_sum for other modes too, when
9354 mem is sufficiently aligned.
9356 Also disallow this if the type can go in VMX/Altivec registers, since
9357 those registers do not have d-form (reg+offset) address modes. */
9358 && !reg_addr[mode].scalar_in_vmx_p
9363 && (mode != TImode || !TARGET_VSX)
9365 && (mode != DImode || TARGET_POWERPC64)
9366 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9367 || TARGET_HARD_FLOAT))
9372 rtx offset = machopic_gen_offset (x);
9373 x = gen_rtx_LO_SUM (GET_MODE (x),
9374 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9375 gen_rtx_HIGH (Pmode, offset)), offset);
9379 x = gen_rtx_LO_SUM (GET_MODE (x),
9380 gen_rtx_HIGH (Pmode, x), x);
9382 if (TARGET_DEBUG_ADDR)
9384 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9387 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9388 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9389 opnum, (enum reload_type) type);
9394 /* Reload an offset address wrapped by an AND that represents the
9395 masking of the lower bits. Strip the outer AND and let reload
9396 convert the offset address into an indirect address. For VSX,
9397 force reload to create the address with an AND in a separate
9398 register, because we can't guarantee an altivec register will
9400 if (VECTOR_MEM_ALTIVEC_P (mode)
9401 && GET_CODE (x) == AND
9402 && GET_CODE (XEXP (x, 0)) == PLUS
9403 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9404 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9405 && GET_CODE (XEXP (x, 1)) == CONST_INT
9406 && INTVAL (XEXP (x, 1)) == -16)
9416 && GET_CODE (x) == SYMBOL_REF
9417 && use_toc_relative_ref (x, mode))
9419 x = create_TOC_reference (x, NULL_RTX);
9420 if (TARGET_CMODEL != CMODEL_SMALL)
9422 if (TARGET_DEBUG_ADDR)
9424 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9427 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9428 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9429 opnum, (enum reload_type) type);
9438 /* Debug version of rs6000_legitimize_reload_address. */
9440 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9441 int opnum, int type,
9442 int ind_levels, int *win)
9444 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9447 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9448 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9449 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9453 fprintf (stderr, "Same address returned\n");
9455 fprintf (stderr, "NULL returned\n");
9458 fprintf (stderr, "New address:\n");
9465 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9466 that is a valid memory address for an instruction.
9467 The MODE argument is the machine mode for the MEM expression
9468 that wants to use this address.
9470 On the RS/6000, there are four valid address: a SYMBOL_REF that
9471 refers to a constant pool entry of an address (or the sum of it
9472 plus a constant), a short (16-bit signed) constant plus a register,
9473 the sum of two registers, or a register indirect, possibly with an
9474 auto-increment. For DFmode, DDmode and DImode with a constant plus
9475 register, we must ensure that both words are addressable or PowerPC64
9476 with offset word aligned.
9478 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9479 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9480 because adjacent memory cells are accessed by adding word-sized offsets
9481 during assembly output. */
9483 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9485 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9486 bool quad_offset_p = mode_supports_dq_form (mode);
9488 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9489 if (VECTOR_MEM_ALTIVEC_P (mode)
9490 && GET_CODE (x) == AND
9491 && GET_CODE (XEXP (x, 1)) == CONST_INT
9492 && INTVAL (XEXP (x, 1)) == -16)
9495 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9497 if (legitimate_indirect_address_p (x, reg_ok_strict))
9500 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9501 && mode_supports_pre_incdec_p (mode)
9502 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9504 /* Handle restricted vector d-form offsets in ISA 3.0. */
9507 if (quad_address_p (x, mode, reg_ok_strict))
9510 else if (virtual_stack_registers_memory_p (x))
9513 else if (reg_offset_p)
9515 if (legitimate_small_data_p (mode, x))
9517 if (legitimate_constant_pool_address_p (x, mode,
9518 reg_ok_strict || lra_in_progress))
9520 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9521 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9525 /* For TImode, if we have TImode in VSX registers, only allow register
9526 indirect addresses. This will allow the values to go in either GPRs
9527 or VSX registers without reloading. The vector types would tend to
9528 go into VSX registers, so we allow REG+REG, while TImode seems
9529 somewhat split, in that some uses are GPR based, and some VSX based. */
9530 /* FIXME: We could loosen this by changing the following to
9531 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9532 but currently we cannot allow REG+REG addressing for TImode. See
9533 PR72827 for complete details on how this ends up hoodwinking DSE. */
9534 if (mode == TImode && TARGET_VSX)
9536 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9539 && GET_CODE (x) == PLUS
9540 && GET_CODE (XEXP (x, 0)) == REG
9541 && (XEXP (x, 0) == virtual_stack_vars_rtx
9542 || XEXP (x, 0) == arg_pointer_rtx)
9543 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9545 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9547 if (!FLOAT128_2REG_P (mode)
9548 && (TARGET_HARD_FLOAT
9550 || (mode != DFmode && mode != DDmode))
9551 && (TARGET_POWERPC64 || mode != DImode)
9552 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9554 && !avoiding_indexed_address_p (mode)
9555 && legitimate_indexed_address_p (x, reg_ok_strict))
9557 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9558 && mode_supports_pre_modify_p (mode)
9559 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9560 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9561 reg_ok_strict, false)
9562 || (!avoiding_indexed_address_p (mode)
9563 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9564 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9566 if (reg_offset_p && !quad_offset_p
9567 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9572 /* Debug version of rs6000_legitimate_address_p. */
9574 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9577 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9579 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9580 "strict = %d, reload = %s, code = %s\n",
9581 ret ? "true" : "false",
9582 GET_MODE_NAME (mode),
9584 (reload_completed ? "after" : "before"),
9585 GET_RTX_NAME (GET_CODE (x)));
9591 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9594 rs6000_mode_dependent_address_p (const_rtx addr,
9595 addr_space_t as ATTRIBUTE_UNUSED)
9597 return rs6000_mode_dependent_address_ptr (addr);
9600 /* Go to LABEL if ADDR (a legitimate address expression)
9601 has an effect that depends on the machine mode it is used for.
9603 On the RS/6000 this is true of all integral offsets (since AltiVec
9604 and VSX modes don't allow them) or is a pre-increment or decrement.
9606 ??? Except that due to conceptual problems in offsettable_address_p
9607 we can't really report the problems of integral offsets. So leave
9608 this assuming that the adjustable offset must be valid for the
9609 sub-words of a TFmode operand, which is what we had before. */
9612 rs6000_mode_dependent_address (const_rtx addr)
9614 switch (GET_CODE (addr))
9617 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9618 is considered a legitimate address before reload, so there
9619 are no offset restrictions in that case. Note that this
9620 condition is safe in strict mode because any address involving
9621 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9622 been rejected as illegitimate. */
9623 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9624 && XEXP (addr, 0) != arg_pointer_rtx
9625 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9627 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9628 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9633 /* Anything in the constant pool is sufficiently aligned that
9634 all bytes have the same high part address. */
9635 return !legitimate_constant_pool_address_p (addr, QImode, false);
9637 /* Auto-increment cases are now treated generically in recog.c. */
9639 return TARGET_UPDATE;
9641 /* AND is only allowed in Altivec loads. */
9652 /* Debug version of rs6000_mode_dependent_address. */
9654 rs6000_debug_mode_dependent_address (const_rtx addr)
9656 bool ret = rs6000_mode_dependent_address (addr);
9658 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9659 ret ? "true" : "false");
9665 /* Implement FIND_BASE_TERM. */
9668 rs6000_find_base_term (rtx op)
9673 if (GET_CODE (base) == CONST)
9674 base = XEXP (base, 0);
9675 if (GET_CODE (base) == PLUS)
9676 base = XEXP (base, 0);
9677 if (GET_CODE (base) == UNSPEC)
9678 switch (XINT (base, 1))
9681 case UNSPEC_MACHOPIC_OFFSET:
9682 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9683 for aliasing purposes. */
9684 return XVECEXP (base, 0, 0);
9690 /* More elaborate version of recog's offsettable_memref_p predicate
9691 that works around the ??? note of rs6000_mode_dependent_address.
9692 In particular it accepts
9694 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9696 in 32-bit mode, that the recog predicate rejects. */
9699 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9706 /* First mimic offsettable_memref_p. */
9707 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9710 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9711 the latter predicate knows nothing about the mode of the memory
9712 reference and, therefore, assumes that it is the largest supported
9713 mode (TFmode). As a consequence, legitimate offsettable memory
9714 references are rejected. rs6000_legitimate_offset_address_p contains
9715 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9716 at least with a little bit of help here given that we know the
9717 actual registers used. */
9718 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9719 || GET_MODE_SIZE (reg_mode) == 4);
9720 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9721 strict, worst_case);
9724 /* Determine the reassociation width to be used in reassociate_bb.
9725 This takes into account how many parallel operations we
9726 can actually do of a given type, and also the latency.
9730 vect add/sub/mul 2/cycle
9731 fp add/sub/mul 2/cycle
9736 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9739 switch (rs6000_tune)
9741 case PROCESSOR_POWER8:
9742 case PROCESSOR_POWER9:
9743 if (DECIMAL_FLOAT_MODE_P (mode))
9745 if (VECTOR_MODE_P (mode))
9747 if (INTEGRAL_MODE_P (mode))
9749 if (FLOAT_MODE_P (mode))
9758 /* Change register usage conditional on target flags. */
9760 rs6000_conditional_register_usage (void)
9764 if (TARGET_DEBUG_TARGET)
9765 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9767 /* Set MQ register fixed (already call_used) so that it will not be
9771 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9773 fixed_regs[13] = call_used_regs[13]
9774 = call_really_used_regs[13] = 1;
9776 /* Conditionally disable FPRs. */
9777 if (TARGET_SOFT_FLOAT)
9778 for (i = 32; i < 64; i++)
9779 fixed_regs[i] = call_used_regs[i]
9780 = call_really_used_regs[i] = 1;
9782 /* The TOC register is not killed across calls in a way that is
9783 visible to the compiler. */
9784 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9785 call_really_used_regs[2] = 0;
9787 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9788 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9790 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9791 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9792 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9793 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9795 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9796 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9797 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9798 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9800 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9801 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9802 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9804 if (!TARGET_ALTIVEC && !TARGET_VSX)
9806 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9807 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9808 call_really_used_regs[VRSAVE_REGNO] = 1;
9811 if (TARGET_ALTIVEC || TARGET_VSX)
9812 global_regs[VSCR_REGNO] = 1;
9814 if (TARGET_ALTIVEC_ABI)
9816 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9817 call_used_regs[i] = call_really_used_regs[i] = 1;
9819 /* AIX reserves VR20:31 in non-extended ABI mode. */
9821 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9822 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9827 /* Output insns to set DEST equal to the constant SOURCE as a series of
9828 lis, ori and shl instructions and return TRUE. */
9831 rs6000_emit_set_const (rtx dest, rtx source)
9833 machine_mode mode = GET_MODE (dest);
9838 gcc_checking_assert (CONST_INT_P (source));
9839 c = INTVAL (source);
9844 emit_insn (gen_rtx_SET (dest, source));
9848 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9850 emit_insn (gen_rtx_SET (copy_rtx (temp),
9851 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9852 emit_insn (gen_rtx_SET (dest,
9853 gen_rtx_IOR (SImode, copy_rtx (temp),
9854 GEN_INT (c & 0xffff))));
9858 if (!TARGET_POWERPC64)
9862 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9864 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9866 emit_move_insn (hi, GEN_INT (c >> 32));
9867 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9868 emit_move_insn (lo, GEN_INT (c));
9871 rs6000_emit_set_long_const (dest, c);
9878 insn = get_last_insn ();
9879 set = single_set (insn);
9880 if (! CONSTANT_P (SET_SRC (set)))
9881 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9886 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9887 Output insns to set DEST equal to the constant C as a series of
9888 lis, ori and shl instructions. */
9891 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9894 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9904 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9905 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9906 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9908 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9909 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9911 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9913 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9914 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9916 emit_move_insn (dest,
9917 gen_rtx_IOR (DImode, copy_rtx (temp),
9920 else if (ud3 == 0 && ud4 == 0)
9922 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9924 gcc_assert (ud2 & 0x8000);
9925 emit_move_insn (copy_rtx (temp),
9926 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9928 emit_move_insn (copy_rtx (temp),
9929 gen_rtx_IOR (DImode, copy_rtx (temp),
9931 emit_move_insn (dest,
9932 gen_rtx_ZERO_EXTEND (DImode,
9933 gen_lowpart (SImode,
9936 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9937 || (ud4 == 0 && ! (ud3 & 0x8000)))
9939 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9941 emit_move_insn (copy_rtx (temp),
9942 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9944 emit_move_insn (copy_rtx (temp),
9945 gen_rtx_IOR (DImode, copy_rtx (temp),
9947 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9948 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9951 emit_move_insn (dest,
9952 gen_rtx_IOR (DImode, copy_rtx (temp),
9957 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9959 emit_move_insn (copy_rtx (temp),
9960 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9962 emit_move_insn (copy_rtx (temp),
9963 gen_rtx_IOR (DImode, copy_rtx (temp),
9966 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9967 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9970 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9971 gen_rtx_IOR (DImode, copy_rtx (temp),
9972 GEN_INT (ud2 << 16)));
9974 emit_move_insn (dest,
9975 gen_rtx_IOR (DImode, copy_rtx (temp),
9980 /* Helper for the following. Get rid of [r+r] memory refs
9981 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9984 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9986 if (GET_CODE (operands[0]) == MEM
9987 && GET_CODE (XEXP (operands[0], 0)) != REG
9988 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9989 GET_MODE (operands[0]), false))
9991 = replace_equiv_address (operands[0],
9992 copy_addr_to_reg (XEXP (operands[0], 0)));
9994 if (GET_CODE (operands[1]) == MEM
9995 && GET_CODE (XEXP (operands[1], 0)) != REG
9996 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9997 GET_MODE (operands[1]), false))
9999 = replace_equiv_address (operands[1],
10000 copy_addr_to_reg (XEXP (operands[1], 0)));
10003 /* Generate a vector of constants to permute MODE for a little-endian
10004 storage operation by swapping the two halves of a vector. */
10006 rs6000_const_vec (machine_mode mode)
10034 v = rtvec_alloc (subparts);
10036 for (i = 0; i < subparts / 2; ++i)
10037 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10038 for (i = subparts / 2; i < subparts; ++i)
10039 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10044 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10045 store operation. */
10047 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10049 /* Scalar permutations are easier to express in integer modes rather than
10050 floating-point modes, so cast them here. We use V1TImode instead
10051 of TImode to ensure that the values don't go through GPRs. */
10052 if (FLOAT128_VECTOR_P (mode))
10054 dest = gen_lowpart (V1TImode, dest);
10055 source = gen_lowpart (V1TImode, source);
10059 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10061 if (mode == TImode || mode == V1TImode)
10062 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10066 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10067 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10071 /* Emit a little-endian load from vector memory location SOURCE to VSX
10072 register DEST in mode MODE. The load is done with two permuting
10073 insn's that represent an lxvd2x and xxpermdi. */
10075 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10077 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10079 if (mode == TImode || mode == V1TImode)
10082 dest = gen_lowpart (V2DImode, dest);
10083 source = adjust_address (source, V2DImode, 0);
10086 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10087 rs6000_emit_le_vsx_permute (tmp, source, mode);
10088 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10091 /* Emit a little-endian store to vector memory location DEST from VSX
10092 register SOURCE in mode MODE. The store is done with two permuting
10093 insn's that represent an xxpermdi and an stxvd2x. */
10095 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10097 /* This should never be called during or after LRA, because it does
10098 not re-permute the source register. It is intended only for use
10100 gcc_assert (!lra_in_progress && !reload_completed);
10102 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10104 if (mode == TImode || mode == V1TImode)
10107 dest = adjust_address (dest, V2DImode, 0);
10108 source = gen_lowpart (V2DImode, source);
10111 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10112 rs6000_emit_le_vsx_permute (tmp, source, mode);
10113 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10116 /* Emit a sequence representing a little-endian VSX load or store,
10117 moving data from SOURCE to DEST in mode MODE. This is done
10118 separately from rs6000_emit_move to ensure it is called only
10119 during expand. LE VSX loads and stores introduced later are
10120 handled with a split. The expand-time RTL generation allows
10121 us to optimize away redundant pairs of register-permutes. */
10123 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10125 gcc_assert (!BYTES_BIG_ENDIAN
10126 && VECTOR_MEM_VSX_P (mode)
10127 && !TARGET_P9_VECTOR
10128 && !gpr_or_gpr_p (dest, source)
10129 && (MEM_P (source) ^ MEM_P (dest)));
10131 if (MEM_P (source))
10133 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10134 rs6000_emit_le_vsx_load (dest, source, mode);
10138 if (!REG_P (source))
10139 source = force_reg (mode, source);
10140 rs6000_emit_le_vsx_store (dest, source, mode);
10144 /* Return whether a SFmode or SImode move can be done without converting one
10145 mode to another. This arrises when we have:
10147 (SUBREG:SF (REG:SI ...))
10148 (SUBREG:SI (REG:SF ...))
10150 and one of the values is in a floating point/vector register, where SFmode
10151 scalars are stored in DFmode format. */
10154 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10156 if (TARGET_ALLOW_SF_SUBREG)
10159 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10162 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10165 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10166 if (SUBREG_P (dest))
10168 rtx dest_subreg = SUBREG_REG (dest);
10169 rtx src_subreg = SUBREG_REG (src);
10170 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10177 /* Helper function to change moves with:
10179 (SUBREG:SF (REG:SI)) and
10180 (SUBREG:SI (REG:SF))
10182 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10183 values are stored as DFmode values in the VSX registers. We need to convert
10184 the bits before we can use a direct move or operate on the bits in the
10185 vector register as an integer type.
10187 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10190 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10192 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10193 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10194 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10196 rtx inner_source = SUBREG_REG (source);
10197 machine_mode inner_mode = GET_MODE (inner_source);
10199 if (mode == SImode && inner_mode == SFmode)
10201 emit_insn (gen_movsi_from_sf (dest, inner_source));
10205 if (mode == SFmode && inner_mode == SImode)
10207 emit_insn (gen_movsf_from_si (dest, inner_source));
10215 /* Emit a move from SOURCE to DEST in mode MODE. */
10217 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10220 operands[0] = dest;
10221 operands[1] = source;
10223 if (TARGET_DEBUG_ADDR)
10226 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10227 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10228 GET_MODE_NAME (mode),
10231 can_create_pseudo_p ());
10233 fprintf (stderr, "source:\n");
10234 debug_rtx (source);
10237 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10238 if (CONST_WIDE_INT_P (operands[1])
10239 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10241 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10242 gcc_unreachable ();
10245 #ifdef HAVE_AS_GNU_ATTRIBUTE
10246 /* If we use a long double type, set the flags in .gnu_attribute that say
10247 what the long double type is. This is to allow the linker's warning
10248 message for the wrong long double to be useful, even if the function does
10249 not do a call (for example, doing a 128-bit add on power9 if the long
10250 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
10251 used if they aren't the default long dobule type. */
10252 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
10254 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
10255 rs6000_passes_float = rs6000_passes_long_double = true;
10257 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
10258 rs6000_passes_float = rs6000_passes_long_double = true;
10262 /* See if we need to special case SImode/SFmode SUBREG moves. */
10263 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10264 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10267 /* Check if GCC is setting up a block move that will end up using FP
10268 registers as temporaries. We must make sure this is acceptable. */
10269 if (GET_CODE (operands[0]) == MEM
10270 && GET_CODE (operands[1]) == MEM
10272 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10273 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10274 && ! (rs6000_slow_unaligned_access (SImode,
10275 (MEM_ALIGN (operands[0]) > 32
10276 ? 32 : MEM_ALIGN (operands[0])))
10277 || rs6000_slow_unaligned_access (SImode,
10278 (MEM_ALIGN (operands[1]) > 32
10279 ? 32 : MEM_ALIGN (operands[1]))))
10280 && ! MEM_VOLATILE_P (operands [0])
10281 && ! MEM_VOLATILE_P (operands [1]))
10283 emit_move_insn (adjust_address (operands[0], SImode, 0),
10284 adjust_address (operands[1], SImode, 0));
10285 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10286 adjust_address (copy_rtx (operands[1]), SImode, 4));
10290 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10291 && !gpc_reg_operand (operands[1], mode))
10292 operands[1] = force_reg (mode, operands[1]);
10294 /* Recognize the case where operand[1] is a reference to thread-local
10295 data and load its address to a register. */
10296 if (tls_referenced_p (operands[1]))
10298 enum tls_model model;
10299 rtx tmp = operands[1];
10302 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10304 addend = XEXP (XEXP (tmp, 0), 1);
10305 tmp = XEXP (XEXP (tmp, 0), 0);
10308 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10309 model = SYMBOL_REF_TLS_MODEL (tmp);
10310 gcc_assert (model != 0);
10312 tmp = rs6000_legitimize_tls_address (tmp, model);
10315 tmp = gen_rtx_PLUS (mode, tmp, addend);
10316 tmp = force_operand (tmp, operands[0]);
10321 /* 128-bit constant floating-point values on Darwin should really be loaded
10322 as two parts. However, this premature splitting is a problem when DFmode
10323 values can go into Altivec registers. */
10324 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10325 && GET_CODE (operands[1]) == CONST_DOUBLE)
10327 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10328 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10330 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10331 GET_MODE_SIZE (DFmode)),
10332 simplify_gen_subreg (DFmode, operands[1], mode,
10333 GET_MODE_SIZE (DFmode)),
10338 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10339 p1:SD) if p1 is not of floating point class and p0 is spilled as
10340 we can have no analogous movsd_store for this. */
10341 if (lra_in_progress && mode == DDmode
10342 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10343 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10344 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10345 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10348 int regno = REGNO (SUBREG_REG (operands[1]));
10350 if (regno >= FIRST_PSEUDO_REGISTER)
10352 cl = reg_preferred_class (regno);
10353 regno = reg_renumber[regno];
10355 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10357 if (regno >= 0 && ! FP_REGNO_P (regno))
10360 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10361 operands[1] = SUBREG_REG (operands[1]);
10364 if (lra_in_progress
10366 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10367 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10368 && (REG_P (operands[1])
10369 || (GET_CODE (operands[1]) == SUBREG
10370 && REG_P (SUBREG_REG (operands[1])))))
10372 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10373 ? SUBREG_REG (operands[1]) : operands[1]);
10376 if (regno >= FIRST_PSEUDO_REGISTER)
10378 cl = reg_preferred_class (regno);
10379 gcc_assert (cl != NO_REGS);
10380 regno = reg_renumber[regno];
10382 regno = ira_class_hard_regs[cl][0];
10384 if (FP_REGNO_P (regno))
10386 if (GET_MODE (operands[0]) != DDmode)
10387 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10388 emit_insn (gen_movsd_store (operands[0], operands[1]));
10390 else if (INT_REGNO_P (regno))
10391 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10396 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10397 p:DD)) if p0 is not of floating point class and p1 is spilled as
10398 we can have no analogous movsd_load for this. */
10399 if (lra_in_progress && mode == DDmode
10400 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10401 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10402 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10403 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10406 int regno = REGNO (SUBREG_REG (operands[0]));
10408 if (regno >= FIRST_PSEUDO_REGISTER)
10410 cl = reg_preferred_class (regno);
10411 regno = reg_renumber[regno];
10413 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10415 if (regno >= 0 && ! FP_REGNO_P (regno))
10418 operands[0] = SUBREG_REG (operands[0]);
10419 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10422 if (lra_in_progress
10424 && (REG_P (operands[0])
10425 || (GET_CODE (operands[0]) == SUBREG
10426 && REG_P (SUBREG_REG (operands[0]))))
10427 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10428 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10430 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10431 ? SUBREG_REG (operands[0]) : operands[0]);
10434 if (regno >= FIRST_PSEUDO_REGISTER)
10436 cl = reg_preferred_class (regno);
10437 gcc_assert (cl != NO_REGS);
10438 regno = reg_renumber[regno];
10440 regno = ira_class_hard_regs[cl][0];
10442 if (FP_REGNO_P (regno))
10444 if (GET_MODE (operands[1]) != DDmode)
10445 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10446 emit_insn (gen_movsd_load (operands[0], operands[1]));
10448 else if (INT_REGNO_P (regno))
10449 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10455 /* FIXME: In the long term, this switch statement should go away
10456 and be replaced by a sequence of tests based on things like
10462 if (CONSTANT_P (operands[1])
10463 && GET_CODE (operands[1]) != CONST_INT)
10464 operands[1] = force_const_mem (mode, operands[1]);
10471 if (FLOAT128_2REG_P (mode))
10472 rs6000_eliminate_indexed_memrefs (operands);
10479 if (CONSTANT_P (operands[1])
10480 && ! easy_fp_constant (operands[1], mode))
10481 operands[1] = force_const_mem (mode, operands[1]);
10491 if (CONSTANT_P (operands[1])
10492 && !easy_vector_constant (operands[1], mode))
10493 operands[1] = force_const_mem (mode, operands[1]);
10498 /* Use default pattern for address of ELF small data */
10501 && DEFAULT_ABI == ABI_V4
10502 && (GET_CODE (operands[1]) == SYMBOL_REF
10503 || GET_CODE (operands[1]) == CONST)
10504 && small_data_operand (operands[1], mode))
10506 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10510 if (DEFAULT_ABI == ABI_V4
10511 && mode == Pmode && mode == SImode
10512 && flag_pic == 1 && got_operand (operands[1], mode))
10514 emit_insn (gen_movsi_got (operands[0], operands[1]));
10518 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10522 && CONSTANT_P (operands[1])
10523 && GET_CODE (operands[1]) != HIGH
10524 && GET_CODE (operands[1]) != CONST_INT)
10526 rtx target = (!can_create_pseudo_p ()
10528 : gen_reg_rtx (mode));
10530 /* If this is a function address on -mcall-aixdesc,
10531 convert it to the address of the descriptor. */
10532 if (DEFAULT_ABI == ABI_AIX
10533 && GET_CODE (operands[1]) == SYMBOL_REF
10534 && XSTR (operands[1], 0)[0] == '.')
10536 const char *name = XSTR (operands[1], 0);
10538 while (*name == '.')
10540 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10541 CONSTANT_POOL_ADDRESS_P (new_ref)
10542 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10543 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10544 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10545 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10546 operands[1] = new_ref;
10549 if (DEFAULT_ABI == ABI_DARWIN)
10552 if (MACHO_DYNAMIC_NO_PIC_P)
10554 /* Take care of any required data indirection. */
10555 operands[1] = rs6000_machopic_legitimize_pic_address (
10556 operands[1], mode, operands[0]);
10557 if (operands[0] != operands[1])
10558 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10562 emit_insn (gen_macho_high (target, operands[1]));
10563 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10567 emit_insn (gen_elf_high (target, operands[1]));
10568 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10572 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10573 and we have put it in the TOC, we just need to make a TOC-relative
10574 reference to it. */
10576 && GET_CODE (operands[1]) == SYMBOL_REF
10577 && use_toc_relative_ref (operands[1], mode))
10578 operands[1] = create_TOC_reference (operands[1], operands[0]);
10579 else if (mode == Pmode
10580 && CONSTANT_P (operands[1])
10581 && GET_CODE (operands[1]) != HIGH
10582 && ((GET_CODE (operands[1]) != CONST_INT
10583 && ! easy_fp_constant (operands[1], mode))
10584 || (GET_CODE (operands[1]) == CONST_INT
10585 && (num_insns_constant (operands[1], mode)
10586 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10587 || (GET_CODE (operands[0]) == REG
10588 && FP_REGNO_P (REGNO (operands[0]))))
10589 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10590 && (TARGET_CMODEL == CMODEL_SMALL
10591 || can_create_pseudo_p ()
10592 || (REG_P (operands[0])
10593 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10597 /* Darwin uses a special PIC legitimizer. */
10598 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10601 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10603 if (operands[0] != operands[1])
10604 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10609 /* If we are to limit the number of things we put in the TOC and
10610 this is a symbol plus a constant we can add in one insn,
10611 just put the symbol in the TOC and add the constant. */
10612 if (GET_CODE (operands[1]) == CONST
10613 && TARGET_NO_SUM_IN_TOC
10614 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10615 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10616 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10617 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10618 && ! side_effects_p (operands[0]))
10621 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10622 rtx other = XEXP (XEXP (operands[1], 0), 1);
10624 sym = force_reg (mode, sym);
10625 emit_insn (gen_add3_insn (operands[0], sym, other));
10629 operands[1] = force_const_mem (mode, operands[1]);
10632 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10633 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10635 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10637 operands[1] = gen_const_mem (mode, tocref);
10638 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10644 if (!VECTOR_MEM_VSX_P (TImode))
10645 rs6000_eliminate_indexed_memrefs (operands);
10649 rs6000_eliminate_indexed_memrefs (operands);
10653 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10656 /* Above, we may have called force_const_mem which may have returned
10657 an invalid address. If we can, fix this up; otherwise, reload will
10658 have to deal with it. */
10659 if (GET_CODE (operands[1]) == MEM)
10660 operands[1] = validize_mem (operands[1]);
10662 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10665 /* Nonzero if we can use a floating-point register to pass this arg. */
10666 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10667 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10668 && (CUM)->fregno <= FP_ARG_MAX_REG \
10669 && TARGET_HARD_FLOAT)
10671 /* Nonzero if we can use an AltiVec register to pass this arg. */
10672 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10673 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10674 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10675 && TARGET_ALTIVEC_ABI \
10678 /* Walk down the type tree of TYPE counting consecutive base elements.
10679 If *MODEP is VOIDmode, then set it to the first valid floating point
10680 or vector type. If a non-floating point or vector type is found, or
10681 if a floating point or vector type that doesn't match a non-VOIDmode
10682 *MODEP is found, then return -1, otherwise return the count in the
10686 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10689 HOST_WIDE_INT size;
10691 switch (TREE_CODE (type))
10694 mode = TYPE_MODE (type);
10695 if (!SCALAR_FLOAT_MODE_P (mode))
10698 if (*modep == VOIDmode)
10701 if (*modep == mode)
10707 mode = TYPE_MODE (TREE_TYPE (type));
10708 if (!SCALAR_FLOAT_MODE_P (mode))
10711 if (*modep == VOIDmode)
10714 if (*modep == mode)
10720 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10723 /* Use V4SImode as representative of all 128-bit vector types. */
10724 size = int_size_in_bytes (type);
10734 if (*modep == VOIDmode)
10737 /* Vector modes are considered to be opaque: two vectors are
10738 equivalent for the purposes of being homogeneous aggregates
10739 if they are the same size. */
10740 if (*modep == mode)
10748 tree index = TYPE_DOMAIN (type);
10750 /* Can't handle incomplete types nor sizes that are not
10752 if (!COMPLETE_TYPE_P (type)
10753 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10756 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10759 || !TYPE_MAX_VALUE (index)
10760 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10761 || !TYPE_MIN_VALUE (index)
10762 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10766 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10767 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10769 /* There must be no padding. */
10770 if (wi::to_wide (TYPE_SIZE (type))
10771 != count * GET_MODE_BITSIZE (*modep))
10783 /* Can't handle incomplete types nor sizes that are not
10785 if (!COMPLETE_TYPE_P (type)
10786 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10789 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10791 if (TREE_CODE (field) != FIELD_DECL)
10794 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10797 count += sub_count;
10800 /* There must be no padding. */
10801 if (wi::to_wide (TYPE_SIZE (type))
10802 != count * GET_MODE_BITSIZE (*modep))
10809 case QUAL_UNION_TYPE:
10811 /* These aren't very interesting except in a degenerate case. */
10816 /* Can't handle incomplete types nor sizes that are not
10818 if (!COMPLETE_TYPE_P (type)
10819 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10822 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10824 if (TREE_CODE (field) != FIELD_DECL)
10827 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10830 count = count > sub_count ? count : sub_count;
10833 /* There must be no padding. */
10834 if (wi::to_wide (TYPE_SIZE (type))
10835 != count * GET_MODE_BITSIZE (*modep))
10848 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10849 float or vector aggregate that shall be passed in FP/vector registers
10850 according to the ELFv2 ABI, return the homogeneous element mode in
10851 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10853 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10856 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10857 machine_mode *elt_mode,
10860 /* Note that we do not accept complex types at the top level as
10861 homogeneous aggregates; these types are handled via the
10862 targetm.calls.split_complex_arg mechanism. Complex types
10863 can be elements of homogeneous aggregates, however. */
10864 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10865 && AGGREGATE_TYPE_P (type))
10867 machine_mode field_mode = VOIDmode;
10868 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10870 if (field_count > 0)
10872 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
10873 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
10875 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10876 up to AGGR_ARG_NUM_REG registers. */
10877 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
10880 *elt_mode = field_mode;
10882 *n_elts = field_count;
10895 /* Return a nonzero value to say to return the function value in
10896 memory, just as large structures are always returned. TYPE will be
10897 the data type of the value, and FNTYPE will be the type of the
10898 function doing the returning, or @code{NULL} for libcalls.
10900 The AIX ABI for the RS/6000 specifies that all structures are
10901 returned in memory. The Darwin ABI does the same.
10903 For the Darwin 64 Bit ABI, a function result can be returned in
10904 registers or in memory, depending on the size of the return data
10905 type. If it is returned in registers, the value occupies the same
10906 registers as it would if it were the first and only function
10907 argument. Otherwise, the function places its result in memory at
10908 the location pointed to by GPR3.
10910 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10911 but a draft put them in memory, and GCC used to implement the draft
10912 instead of the final standard. Therefore, aix_struct_return
10913 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10914 compatibility can change DRAFT_V4_STRUCT_RET to override the
10915 default, and -m switches get the final word. See
10916 rs6000_option_override_internal for more details.
10918 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10919 long double support is enabled. These values are returned in memory.
10921 int_size_in_bytes returns -1 for variable size objects, which go in
10922 memory always. The cast to unsigned makes -1 > 8. */
10925 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10927 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10929 && rs6000_darwin64_abi
10930 && TREE_CODE (type) == RECORD_TYPE
10931 && int_size_in_bytes (type) > 0)
10933 CUMULATIVE_ARGS valcum;
10937 valcum.fregno = FP_ARG_MIN_REG;
10938 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10939 /* Do a trial code generation as if this were going to be passed
10940 as an argument; if any part goes in memory, we return NULL. */
10941 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10944 /* Otherwise fall through to more conventional ABI rules. */
10947 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10948 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10952 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10953 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10954 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10957 if (AGGREGATE_TYPE_P (type)
10958 && (aix_struct_return
10959 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10962 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10963 modes only exist for GCC vector types if -maltivec. */
10964 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10965 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10968 /* Return synthetic vectors in memory. */
10969 if (TREE_CODE (type) == VECTOR_TYPE
10970 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10972 static bool warned_for_return_big_vectors = false;
10973 if (!warned_for_return_big_vectors)
10975 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10976 "non-standard ABI extension with no compatibility "
10978 warned_for_return_big_vectors = true;
10983 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10984 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10990 /* Specify whether values returned in registers should be at the most
10991 significant end of a register. We want aggregates returned by
10992 value to match the way aggregates are passed to functions. */
10995 rs6000_return_in_msb (const_tree valtype)
10997 return (DEFAULT_ABI == ABI_ELFv2
10998 && BYTES_BIG_ENDIAN
10999 && AGGREGATE_TYPE_P (valtype)
11000 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11004 #ifdef HAVE_AS_GNU_ATTRIBUTE
11005 /* Return TRUE if a call to function FNDECL may be one that
11006 potentially affects the function calling ABI of the object file. */
11009 call_ABI_of_interest (tree fndecl)
11011 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11013 struct cgraph_node *c_node;
11015 /* Libcalls are always interesting. */
11016 if (fndecl == NULL_TREE)
11019 /* Any call to an external function is interesting. */
11020 if (DECL_EXTERNAL (fndecl))
11023 /* Interesting functions that we are emitting in this object file. */
11024 c_node = cgraph_node::get (fndecl);
11025 c_node = c_node->ultimate_alias_target ();
11026 return !c_node->only_called_directly_p ();
11032 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11033 for a call to a function whose data type is FNTYPE.
11034 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11036 For incoming args we set the number of arguments in the prototype large
11037 so we never return a PARALLEL. */
11040 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11041 rtx libname ATTRIBUTE_UNUSED, int incoming,
11042 int libcall, int n_named_args,
11043 tree fndecl ATTRIBUTE_UNUSED,
11044 machine_mode return_mode ATTRIBUTE_UNUSED)
11046 static CUMULATIVE_ARGS zero_cumulative;
11048 *cum = zero_cumulative;
11050 cum->fregno = FP_ARG_MIN_REG;
11051 cum->vregno = ALTIVEC_ARG_MIN_REG;
11052 cum->prototype = (fntype && prototype_p (fntype));
11053 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11054 ? CALL_LIBCALL : CALL_NORMAL);
11055 cum->sysv_gregno = GP_ARG_MIN_REG;
11056 cum->stdarg = stdarg_p (fntype);
11057 cum->libcall = libcall;
11059 cum->nargs_prototype = 0;
11060 if (incoming || cum->prototype)
11061 cum->nargs_prototype = n_named_args;
11063 /* Check for a longcall attribute. */
11064 if ((!fntype && rs6000_default_long_calls)
11066 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11067 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11068 cum->call_cookie |= CALL_LONG;
11070 if (TARGET_DEBUG_ARG)
11072 fprintf (stderr, "\ninit_cumulative_args:");
11075 tree ret_type = TREE_TYPE (fntype);
11076 fprintf (stderr, " ret code = %s,",
11077 get_tree_code_name (TREE_CODE (ret_type)));
11080 if (cum->call_cookie & CALL_LONG)
11081 fprintf (stderr, " longcall,");
11083 fprintf (stderr, " proto = %d, nargs = %d\n",
11084 cum->prototype, cum->nargs_prototype);
11087 #ifdef HAVE_AS_GNU_ATTRIBUTE
11088 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11090 cum->escapes = call_ABI_of_interest (fndecl);
11097 return_type = TREE_TYPE (fntype);
11098 return_mode = TYPE_MODE (return_type);
11101 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11103 if (return_type != NULL)
11105 if (TREE_CODE (return_type) == RECORD_TYPE
11106 && TYPE_TRANSPARENT_AGGR (return_type))
11108 return_type = TREE_TYPE (first_field (return_type));
11109 return_mode = TYPE_MODE (return_type);
11111 if (AGGREGATE_TYPE_P (return_type)
11112 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11114 rs6000_returns_struct = true;
11116 if (SCALAR_FLOAT_MODE_P (return_mode))
11118 rs6000_passes_float = true;
11119 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11120 && (FLOAT128_IBM_P (return_mode)
11121 || FLOAT128_IEEE_P (return_mode)
11122 || (return_type != NULL
11123 && (TYPE_MAIN_VARIANT (return_type)
11124 == long_double_type_node))))
11125 rs6000_passes_long_double = true;
11127 /* Note if we passed or return a IEEE 128-bit type. We changed
11128 the mangling for these types, and we may need to make an alias
11129 with the old mangling. */
11130 if (FLOAT128_IEEE_P (return_mode))
11131 rs6000_passes_ieee128 = true;
11133 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
11134 rs6000_passes_vector = true;
11141 && TARGET_ALTIVEC_ABI
11142 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11144 error ("cannot return value in vector register because"
11145 " altivec instructions are disabled, use %qs"
11146 " to enable them", "-maltivec");
11150 /* The mode the ABI uses for a word. This is not the same as word_mode
11151 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11153 static scalar_int_mode
11154 rs6000_abi_word_mode (void)
11156 return TARGET_32BIT ? SImode : DImode;
11159 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11161 rs6000_offload_options (void)
11164 return xstrdup ("-foffload-abi=lp64");
11166 return xstrdup ("-foffload-abi=ilp32");
11169 /* On rs6000, function arguments are promoted, as are function return
11172 static machine_mode
11173 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11175 int *punsignedp ATTRIBUTE_UNUSED,
11178 PROMOTE_MODE (mode, *punsignedp, type);
11183 /* Return true if TYPE must be passed on the stack and not in registers. */
11186 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11188 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11189 return must_pass_in_stack_var_size (mode, type);
11191 return must_pass_in_stack_var_size_or_pad (mode, type);
11195 is_complex_IBM_long_double (machine_mode mode)
11197 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
11200 /* Whether ABI_V4 passes MODE args to a function in floating point
11204 abi_v4_pass_in_fpr (machine_mode mode, bool named)
11206 if (!TARGET_HARD_FLOAT)
11208 if (mode == DFmode)
11210 if (mode == SFmode && named)
11212 /* ABI_V4 passes complex IBM long double in 8 gprs.
11213 Stupid, but we can't change the ABI now. */
11214 if (is_complex_IBM_long_double (mode))
11216 if (FLOAT128_2REG_P (mode))
11218 if (DECIMAL_FLOAT_MODE_P (mode))
11223 /* Implement TARGET_FUNCTION_ARG_PADDING.
11225 For the AIX ABI structs are always stored left shifted in their
11228 static pad_direction
11229 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11231 #ifndef AGGREGATE_PADDING_FIXED
11232 #define AGGREGATE_PADDING_FIXED 0
11234 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11235 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11238 if (!AGGREGATE_PADDING_FIXED)
11240 /* GCC used to pass structures of the same size as integer types as
11241 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11242 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11243 passed padded downward, except that -mstrict-align further
11244 muddied the water in that multi-component structures of 2 and 4
11245 bytes in size were passed padded upward.
11247 The following arranges for best compatibility with previous
11248 versions of gcc, but removes the -mstrict-align dependency. */
11249 if (BYTES_BIG_ENDIAN)
11251 HOST_WIDE_INT size = 0;
11253 if (mode == BLKmode)
11255 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11256 size = int_size_in_bytes (type);
11259 size = GET_MODE_SIZE (mode);
11261 if (size == 1 || size == 2 || size == 4)
11262 return PAD_DOWNWARD;
11267 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11269 if (type != 0 && AGGREGATE_TYPE_P (type))
11273 /* Fall back to the default. */
11274 return default_function_arg_padding (mode, type);
11277 /* If defined, a C expression that gives the alignment boundary, in bits,
11278 of an argument with the specified mode and type. If it is not defined,
11279 PARM_BOUNDARY is used for all arguments.
11281 V.4 wants long longs and doubles to be double word aligned. Just
11282 testing the mode size is a boneheaded way to do this as it means
11283 that other types such as complex int are also double word aligned.
11284 However, we're stuck with this because changing the ABI might break
11285 existing library interfaces.
11287 Quadword align Altivec/VSX vectors.
11288 Quadword align large synthetic vector types. */
11290 static unsigned int
11291 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11293 machine_mode elt_mode;
11296 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11298 if (DEFAULT_ABI == ABI_V4
11299 && (GET_MODE_SIZE (mode) == 8
11300 || (TARGET_HARD_FLOAT
11301 && !is_complex_IBM_long_double (mode)
11302 && FLOAT128_2REG_P (mode))))
11304 else if (FLOAT128_VECTOR_P (mode))
11306 else if (type && TREE_CODE (type) == VECTOR_TYPE
11307 && int_size_in_bytes (type) >= 8
11308 && int_size_in_bytes (type) < 16)
11310 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11311 || (type && TREE_CODE (type) == VECTOR_TYPE
11312 && int_size_in_bytes (type) >= 16))
11315 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11316 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11317 -mcompat-align-parm is used. */
11318 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11319 || DEFAULT_ABI == ABI_ELFv2)
11320 && type && TYPE_ALIGN (type) > 64)
11322 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11323 or homogeneous float/vector aggregates here. We already handled
11324 vector aggregates above, but still need to check for float here. */
11325 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11326 && !SCALAR_FLOAT_MODE_P (elt_mode));
11328 /* We used to check for BLKmode instead of the above aggregate type
11329 check. Warn when this results in any difference to the ABI. */
11330 if (aggregate_p != (mode == BLKmode))
11332 static bool warned;
11333 if (!warned && warn_psabi)
11336 inform (input_location,
11337 "the ABI of passing aggregates with %d-byte alignment"
11338 " has changed in GCC 5",
11339 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11347 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11348 implement the "aggregate type" check as a BLKmode check here; this
11349 means certain aggregate types are in fact not aligned. */
11350 if (TARGET_MACHO && rs6000_darwin64_abi
11352 && type && TYPE_ALIGN (type) > 64)
11355 return PARM_BOUNDARY;
11358 /* The offset in words to the start of the parameter save area. */
11360 static unsigned int
11361 rs6000_parm_offset (void)
11363 return (DEFAULT_ABI == ABI_V4 ? 2
11364 : DEFAULT_ABI == ABI_ELFv2 ? 4
11368 /* For a function parm of MODE and TYPE, return the starting word in
11369 the parameter area. NWORDS of the parameter area are already used. */
11371 static unsigned int
11372 rs6000_parm_start (machine_mode mode, const_tree type,
11373 unsigned int nwords)
11375 unsigned int align;
11377 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11378 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11381 /* Compute the size (in words) of a function argument. */
11383 static unsigned long
11384 rs6000_arg_size (machine_mode mode, const_tree type)
11386 unsigned long size;
11388 if (mode != BLKmode)
11389 size = GET_MODE_SIZE (mode);
11391 size = int_size_in_bytes (type);
11394 return (size + 3) >> 2;
11396 return (size + 7) >> 3;
11399 /* Use this to flush pending int fields. */
11402 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11403 HOST_WIDE_INT bitpos, int final)
11405 unsigned int startbit, endbit;
11406 int intregs, intoffset;
11408 /* Handle the situations where a float is taking up the first half
11409 of the GPR, and the other half is empty (typically due to
11410 alignment restrictions). We can detect this by a 8-byte-aligned
11411 int field, or by seeing that this is the final flush for this
11412 argument. Count the word and continue on. */
11413 if (cum->floats_in_gpr == 1
11414 && (cum->intoffset % 64 == 0
11415 || (cum->intoffset == -1 && final)))
11418 cum->floats_in_gpr = 0;
11421 if (cum->intoffset == -1)
11424 intoffset = cum->intoffset;
11425 cum->intoffset = -1;
11426 cum->floats_in_gpr = 0;
11428 if (intoffset % BITS_PER_WORD != 0)
11430 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11431 if (!int_mode_for_size (bits, 0).exists ())
11433 /* We couldn't find an appropriate mode, which happens,
11434 e.g., in packed structs when there are 3 bytes to load.
11435 Back intoffset back to the beginning of the word in this
11437 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11441 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11442 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11443 intregs = (endbit - startbit) / BITS_PER_WORD;
11444 cum->words += intregs;
11445 /* words should be unsigned. */
11446 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11448 int pad = (endbit/BITS_PER_WORD) - cum->words;
11453 /* The darwin64 ABI calls for us to recurse down through structs,
11454 looking for elements passed in registers. Unfortunately, we have
11455 to track int register count here also because of misalignments
11456 in powerpc alignment mode. */
11459 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11461 HOST_WIDE_INT startbitpos)
11465 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11466 if (TREE_CODE (f) == FIELD_DECL)
11468 HOST_WIDE_INT bitpos = startbitpos;
11469 tree ftype = TREE_TYPE (f);
11471 if (ftype == error_mark_node)
11473 mode = TYPE_MODE (ftype);
11475 if (DECL_SIZE (f) != 0
11476 && tree_fits_uhwi_p (bit_position (f)))
11477 bitpos += int_bit_position (f);
11479 /* ??? FIXME: else assume zero offset. */
11481 if (TREE_CODE (ftype) == RECORD_TYPE)
11482 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11483 else if (USE_FP_FOR_ARG_P (cum, mode))
11485 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11486 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11487 cum->fregno += n_fpregs;
11488 /* Single-precision floats present a special problem for
11489 us, because they are smaller than an 8-byte GPR, and so
11490 the structure-packing rules combined with the standard
11491 varargs behavior mean that we want to pack float/float
11492 and float/int combinations into a single register's
11493 space. This is complicated by the arg advance flushing,
11494 which works on arbitrarily large groups of int-type
11496 if (mode == SFmode)
11498 if (cum->floats_in_gpr == 1)
11500 /* Two floats in a word; count the word and reset
11501 the float count. */
11503 cum->floats_in_gpr = 0;
11505 else if (bitpos % 64 == 0)
11507 /* A float at the beginning of an 8-byte word;
11508 count it and put off adjusting cum->words until
11509 we see if a arg advance flush is going to do it
11511 cum->floats_in_gpr++;
11515 /* The float is at the end of a word, preceded
11516 by integer fields, so the arg advance flush
11517 just above has already set cum->words and
11518 everything is taken care of. */
11522 cum->words += n_fpregs;
11524 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11526 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11530 else if (cum->intoffset == -1)
11531 cum->intoffset = bitpos;
11535 /* Check for an item that needs to be considered specially under the darwin 64
11536 bit ABI. These are record types where the mode is BLK or the structure is
11537 8 bytes in size. */
11539 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11541 return rs6000_darwin64_abi
11542 && ((mode == BLKmode
11543 && TREE_CODE (type) == RECORD_TYPE
11544 && int_size_in_bytes (type) > 0)
11545 || (type && TREE_CODE (type) == RECORD_TYPE
11546 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11549 /* Update the data in CUM to advance over an argument
11550 of mode MODE and data type TYPE.
11551 (TYPE is null for libcalls where that information may not be available.)
11553 Note that for args passed by reference, function_arg will be called
11554 with MODE and TYPE set to that of the pointer to the arg, not the arg
11558 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11559 const_tree type, bool named, int depth)
11561 machine_mode elt_mode;
11564 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11566 /* Only tick off an argument if we're not recursing. */
11568 cum->nargs_prototype--;
11570 #ifdef HAVE_AS_GNU_ATTRIBUTE
11571 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11574 if (SCALAR_FLOAT_MODE_P (mode))
11576 rs6000_passes_float = true;
11577 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11578 && (FLOAT128_IBM_P (mode)
11579 || FLOAT128_IEEE_P (mode)
11581 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11582 rs6000_passes_long_double = true;
11584 /* Note if we passed or return a IEEE 128-bit type. We changed the
11585 mangling for these types, and we may need to make an alias with
11586 the old mangling. */
11587 if (FLOAT128_IEEE_P (mode))
11588 rs6000_passes_ieee128 = true;
11590 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11591 rs6000_passes_vector = true;
11595 if (TARGET_ALTIVEC_ABI
11596 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11597 || (type && TREE_CODE (type) == VECTOR_TYPE
11598 && int_size_in_bytes (type) == 16)))
11600 bool stack = false;
11602 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11604 cum->vregno += n_elts;
11606 if (!TARGET_ALTIVEC)
11607 error ("cannot pass argument in vector register because"
11608 " altivec instructions are disabled, use %qs"
11609 " to enable them", "-maltivec");
11611 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11612 even if it is going to be passed in a vector register.
11613 Darwin does the same for variable-argument functions. */
11614 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11616 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11626 /* Vector parameters must be 16-byte aligned. In 32-bit
11627 mode this means we need to take into account the offset
11628 to the parameter save area. In 64-bit mode, they just
11629 have to start on an even word, since the parameter save
11630 area is 16-byte aligned. */
11632 align = -(rs6000_parm_offset () + cum->words) & 3;
11634 align = cum->words & 1;
11635 cum->words += align + rs6000_arg_size (mode, type);
11637 if (TARGET_DEBUG_ARG)
11639 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11640 cum->words, align);
11641 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11642 cum->nargs_prototype, cum->prototype,
11643 GET_MODE_NAME (mode));
11647 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11649 int size = int_size_in_bytes (type);
11650 /* Variable sized types have size == -1 and are
11651 treated as if consisting entirely of ints.
11652 Pad to 16 byte boundary if needed. */
11653 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11654 && (cum->words % 2) != 0)
11656 /* For varargs, we can just go up by the size of the struct. */
11658 cum->words += (size + 7) / 8;
11661 /* It is tempting to say int register count just goes up by
11662 sizeof(type)/8, but this is wrong in a case such as
11663 { int; double; int; } [powerpc alignment]. We have to
11664 grovel through the fields for these too. */
11665 cum->intoffset = 0;
11666 cum->floats_in_gpr = 0;
11667 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11668 rs6000_darwin64_record_arg_advance_flush (cum,
11669 size * BITS_PER_UNIT, 1);
11671 if (TARGET_DEBUG_ARG)
11673 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11674 cum->words, TYPE_ALIGN (type), size);
11676 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11677 cum->nargs_prototype, cum->prototype,
11678 GET_MODE_NAME (mode));
11681 else if (DEFAULT_ABI == ABI_V4)
11683 if (abi_v4_pass_in_fpr (mode, named))
11685 /* _Decimal128 must use an even/odd register pair. This assumes
11686 that the register number is odd when fregno is odd. */
11687 if (mode == TDmode && (cum->fregno % 2) == 1)
11690 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11691 <= FP_ARG_V4_MAX_REG)
11692 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11695 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11696 if (mode == DFmode || FLOAT128_IBM_P (mode)
11697 || mode == DDmode || mode == TDmode)
11698 cum->words += cum->words & 1;
11699 cum->words += rs6000_arg_size (mode, type);
11704 int n_words = rs6000_arg_size (mode, type);
11705 int gregno = cum->sysv_gregno;
11707 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11708 As does any other 2 word item such as complex int due to a
11709 historical mistake. */
11711 gregno += (1 - gregno) & 1;
11713 /* Multi-reg args are not split between registers and stack. */
11714 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11716 /* Long long is aligned on the stack. So are other 2 word
11717 items such as complex int due to a historical mistake. */
11719 cum->words += cum->words & 1;
11720 cum->words += n_words;
11723 /* Note: continuing to accumulate gregno past when we've started
11724 spilling to the stack indicates the fact that we've started
11725 spilling to the stack to expand_builtin_saveregs. */
11726 cum->sysv_gregno = gregno + n_words;
11729 if (TARGET_DEBUG_ARG)
11731 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11732 cum->words, cum->fregno);
11733 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11734 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11735 fprintf (stderr, "mode = %4s, named = %d\n",
11736 GET_MODE_NAME (mode), named);
11741 int n_words = rs6000_arg_size (mode, type);
11742 int start_words = cum->words;
11743 int align_words = rs6000_parm_start (mode, type, start_words);
11745 cum->words = align_words + n_words;
11747 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11749 /* _Decimal128 must be passed in an even/odd float register pair.
11750 This assumes that the register number is odd when fregno is
11752 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11754 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11757 if (TARGET_DEBUG_ARG)
11759 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11760 cum->words, cum->fregno);
11761 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11762 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11763 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11764 named, align_words - start_words, depth);
11770 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11771 const_tree type, bool named)
11773 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11777 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11778 structure between cum->intoffset and bitpos to integer registers. */
11781 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11782 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11785 unsigned int regno;
11786 unsigned int startbit, endbit;
11787 int this_regno, intregs, intoffset;
11790 if (cum->intoffset == -1)
11793 intoffset = cum->intoffset;
11794 cum->intoffset = -1;
11796 /* If this is the trailing part of a word, try to only load that
11797 much into the register. Otherwise load the whole register. Note
11798 that in the latter case we may pick up unwanted bits. It's not a
11799 problem at the moment but may wish to revisit. */
11801 if (intoffset % BITS_PER_WORD != 0)
11803 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11804 if (!int_mode_for_size (bits, 0).exists (&mode))
11806 /* We couldn't find an appropriate mode, which happens,
11807 e.g., in packed structs when there are 3 bytes to load.
11808 Back intoffset back to the beginning of the word in this
11810 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11817 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11818 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11819 intregs = (endbit - startbit) / BITS_PER_WORD;
11820 this_regno = cum->words + intoffset / BITS_PER_WORD;
11822 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11823 cum->use_stack = 1;
11825 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11829 intoffset /= BITS_PER_UNIT;
11832 regno = GP_ARG_MIN_REG + this_regno;
11833 reg = gen_rtx_REG (mode, regno);
11835 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11838 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11842 while (intregs > 0);
11845 /* Recursive workhorse for the following. */
11848 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11849 HOST_WIDE_INT startbitpos, rtx rvec[],
11854 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11855 if (TREE_CODE (f) == FIELD_DECL)
11857 HOST_WIDE_INT bitpos = startbitpos;
11858 tree ftype = TREE_TYPE (f);
11860 if (ftype == error_mark_node)
11862 mode = TYPE_MODE (ftype);
11864 if (DECL_SIZE (f) != 0
11865 && tree_fits_uhwi_p (bit_position (f)))
11866 bitpos += int_bit_position (f);
11868 /* ??? FIXME: else assume zero offset. */
11870 if (TREE_CODE (ftype) == RECORD_TYPE)
11871 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11872 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11874 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11878 case E_SCmode: mode = SFmode; break;
11879 case E_DCmode: mode = DFmode; break;
11880 case E_TCmode: mode = TFmode; break;
11884 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11885 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11887 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11888 && (mode == TFmode || mode == TDmode));
11889 /* Long double or _Decimal128 split over regs and memory. */
11890 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11894 = gen_rtx_EXPR_LIST (VOIDmode,
11895 gen_rtx_REG (mode, cum->fregno++),
11896 GEN_INT (bitpos / BITS_PER_UNIT));
11897 if (FLOAT128_2REG_P (mode))
11900 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11902 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11904 = gen_rtx_EXPR_LIST (VOIDmode,
11905 gen_rtx_REG (mode, cum->vregno++),
11906 GEN_INT (bitpos / BITS_PER_UNIT));
11908 else if (cum->intoffset == -1)
11909 cum->intoffset = bitpos;
11913 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11914 the register(s) to be used for each field and subfield of a struct
11915 being passed by value, along with the offset of where the
11916 register's value may be found in the block. FP fields go in FP
11917 register, vector fields go in vector registers, and everything
11918 else goes in int registers, packed as in memory.
11920 This code is also used for function return values. RETVAL indicates
11921 whether this is the case.
11923 Much of this is taken from the SPARC V9 port, which has a similar
11924 calling convention. */
11927 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11928 bool named, bool retval)
11930 rtx rvec[FIRST_PSEUDO_REGISTER];
11931 int k = 1, kbase = 1;
11932 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11933 /* This is a copy; modifications are not visible to our caller. */
11934 CUMULATIVE_ARGS copy_cum = *orig_cum;
11935 CUMULATIVE_ARGS *cum = ©_cum;
11937 /* Pad to 16 byte boundary if needed. */
11938 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11939 && (cum->words % 2) != 0)
11942 cum->intoffset = 0;
11943 cum->use_stack = 0;
11944 cum->named = named;
11946 /* Put entries into rvec[] for individual FP and vector fields, and
11947 for the chunks of memory that go in int regs. Note we start at
11948 element 1; 0 is reserved for an indication of using memory, and
11949 may or may not be filled in below. */
11950 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11951 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11953 /* If any part of the struct went on the stack put all of it there.
11954 This hack is because the generic code for
11955 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11956 parts of the struct are not at the beginning. */
11957 if (cum->use_stack)
11960 return NULL_RTX; /* doesn't go in registers at all */
11962 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11964 if (k > 1 || cum->use_stack)
11965 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11970 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11973 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11978 rtx rvec[GP_ARG_NUM_REG + 1];
11980 if (align_words >= GP_ARG_NUM_REG)
11983 n_units = rs6000_arg_size (mode, type);
11985 /* Optimize the simple case where the arg fits in one gpr, except in
11986 the case of BLKmode due to assign_parms assuming that registers are
11987 BITS_PER_WORD wide. */
11989 || (n_units == 1 && mode != BLKmode))
11990 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11993 if (align_words + n_units > GP_ARG_NUM_REG)
11994 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11995 using a magic NULL_RTX component.
11996 This is not strictly correct. Only some of the arg belongs in
11997 memory, not all of it. However, the normal scheme using
11998 function_arg_partial_nregs can result in unusual subregs, eg.
11999 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12000 store the whole arg to memory is often more efficient than code
12001 to store pieces, and we know that space is available in the right
12002 place for the whole arg. */
12003 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12008 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12009 rtx off = GEN_INT (i++ * 4);
12010 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12012 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12014 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12017 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12018 but must also be copied into the parameter save area starting at
12019 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12020 to the GPRs and/or memory. Return the number of elements used. */
12023 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12024 int align_words, rtx *rvec)
12028 if (align_words < GP_ARG_NUM_REG)
12030 int n_words = rs6000_arg_size (mode, type);
12032 if (align_words + n_words > GP_ARG_NUM_REG
12034 || (TARGET_32BIT && TARGET_POWERPC64))
12036 /* If this is partially on the stack, then we only
12037 include the portion actually in registers here. */
12038 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12041 if (align_words + n_words > GP_ARG_NUM_REG)
12043 /* Not all of the arg fits in gprs. Say that it goes in memory
12044 too, using a magic NULL_RTX component. Also see comment in
12045 rs6000_mixed_function_arg for why the normal
12046 function_arg_partial_nregs scheme doesn't work in this case. */
12047 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12052 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12053 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12054 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12056 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12060 /* The whole arg fits in gprs. */
12061 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12062 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12067 /* It's entirely in memory. */
12068 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12074 /* RVEC is a vector of K components of an argument of mode MODE.
12075 Construct the final function_arg return value from it. */
12078 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12080 gcc_assert (k >= 1);
12082 /* Avoid returning a PARALLEL in the trivial cases. */
12085 if (XEXP (rvec[0], 0) == NULL_RTX)
12088 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12089 return XEXP (rvec[0], 0);
12092 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12095 /* Determine where to put an argument to a function.
12096 Value is zero to push the argument on the stack,
12097 or a hard register in which to store the argument.
12099 MODE is the argument's machine mode.
12100 TYPE is the data type of the argument (as a tree).
12101 This is null for libcalls where that information may
12103 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12104 the preceding args and about the function being called. It is
12105 not modified in this routine.
12106 NAMED is nonzero if this argument is a named parameter
12107 (otherwise it is an extra parameter matching an ellipsis).
12109 On RS/6000 the first eight words of non-FP are normally in registers
12110 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12111 Under V.4, the first 8 FP args are in registers.
12113 If this is floating-point and no prototype is specified, we use
12114 both an FP and integer register (or possibly FP reg and stack). Library
12115 functions (when CALL_LIBCALL is set) always have the proper types for args,
12116 so we can pass the FP value just in one register. emit_library_function
12117 doesn't support PARALLEL anyway.
12119 Note that for args passed by reference, function_arg will be called
12120 with MODE and TYPE set to that of the pointer to the arg, not the arg
12124 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12125 const_tree type, bool named)
12127 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12128 enum rs6000_abi abi = DEFAULT_ABI;
12129 machine_mode elt_mode;
12132 /* Return a marker to indicate whether CR1 needs to set or clear the
12133 bit that V.4 uses to say fp args were passed in registers.
12134 Assume that we don't need the marker for software floating point,
12135 or compiler generated library calls. */
12136 if (mode == VOIDmode)
12139 && (cum->call_cookie & CALL_LIBCALL) == 0
12141 || (cum->nargs_prototype < 0
12142 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12143 && TARGET_HARD_FLOAT)
12144 return GEN_INT (cum->call_cookie
12145 | ((cum->fregno == FP_ARG_MIN_REG)
12146 ? CALL_V4_SET_FP_ARGS
12147 : CALL_V4_CLEAR_FP_ARGS));
12149 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12152 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12154 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12156 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12157 if (rslt != NULL_RTX)
12159 /* Else fall through to usual handling. */
12162 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12164 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12168 /* Do we also need to pass this argument in the parameter save area?
12169 Library support functions for IEEE 128-bit are assumed to not need the
12170 value passed both in GPRs and in vector registers. */
12171 if (TARGET_64BIT && !cum->prototype
12172 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12174 int align_words = ROUND_UP (cum->words, 2);
12175 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12178 /* Describe where this argument goes in the vector registers. */
12179 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12181 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12182 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12183 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12186 return rs6000_finish_function_arg (mode, rvec, k);
12188 else if (TARGET_ALTIVEC_ABI
12189 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12190 || (type && TREE_CODE (type) == VECTOR_TYPE
12191 && int_size_in_bytes (type) == 16)))
12193 if (named || abi == ABI_V4)
12197 /* Vector parameters to varargs functions under AIX or Darwin
12198 get passed in memory and possibly also in GPRs. */
12199 int align, align_words, n_words;
12200 machine_mode part_mode;
12202 /* Vector parameters must be 16-byte aligned. In 32-bit
12203 mode this means we need to take into account the offset
12204 to the parameter save area. In 64-bit mode, they just
12205 have to start on an even word, since the parameter save
12206 area is 16-byte aligned. */
12208 align = -(rs6000_parm_offset () + cum->words) & 3;
12210 align = cum->words & 1;
12211 align_words = cum->words + align;
12213 /* Out of registers? Memory, then. */
12214 if (align_words >= GP_ARG_NUM_REG)
12217 if (TARGET_32BIT && TARGET_POWERPC64)
12218 return rs6000_mixed_function_arg (mode, type, align_words);
12220 /* The vector value goes in GPRs. Only the part of the
12221 value in GPRs is reported here. */
12223 n_words = rs6000_arg_size (mode, type);
12224 if (align_words + n_words > GP_ARG_NUM_REG)
12225 /* Fortunately, there are only two possibilities, the value
12226 is either wholly in GPRs or half in GPRs and half not. */
12227 part_mode = DImode;
12229 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12233 else if (abi == ABI_V4)
12235 if (abi_v4_pass_in_fpr (mode, named))
12237 /* _Decimal128 must use an even/odd register pair. This assumes
12238 that the register number is odd when fregno is odd. */
12239 if (mode == TDmode && (cum->fregno % 2) == 1)
12242 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12243 <= FP_ARG_V4_MAX_REG)
12244 return gen_rtx_REG (mode, cum->fregno);
12250 int n_words = rs6000_arg_size (mode, type);
12251 int gregno = cum->sysv_gregno;
12253 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12254 As does any other 2 word item such as complex int due to a
12255 historical mistake. */
12257 gregno += (1 - gregno) & 1;
12259 /* Multi-reg args are not split between registers and stack. */
12260 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12263 if (TARGET_32BIT && TARGET_POWERPC64)
12264 return rs6000_mixed_function_arg (mode, type,
12265 gregno - GP_ARG_MIN_REG);
12266 return gen_rtx_REG (mode, gregno);
12271 int align_words = rs6000_parm_start (mode, type, cum->words);
12273 /* _Decimal128 must be passed in an even/odd float register pair.
12274 This assumes that the register number is odd when fregno is odd. */
12275 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12278 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12280 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12283 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12286 /* Do we also need to pass this argument in the parameter
12288 if (type && (cum->nargs_prototype <= 0
12289 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12290 && TARGET_XL_COMPAT
12291 && align_words >= GP_ARG_NUM_REG)))
12292 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12294 /* Describe where this argument goes in the fprs. */
12295 for (i = 0; i < n_elts
12296 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12298 /* Check if the argument is split over registers and memory.
12299 This can only ever happen for long double or _Decimal128;
12300 complex types are handled via split_complex_arg. */
12301 machine_mode fmode = elt_mode;
12302 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12304 gcc_assert (FLOAT128_2REG_P (fmode));
12305 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12308 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12309 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12310 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12313 /* If there were not enough FPRs to hold the argument, the rest
12314 usually goes into memory. However, if the current position
12315 is still within the register parameter area, a portion may
12316 actually have to go into GPRs.
12318 Note that it may happen that the portion of the argument
12319 passed in the first "half" of the first GPR was already
12320 passed in the last FPR as well.
12322 For unnamed arguments, we already set up GPRs to cover the
12323 whole argument in rs6000_psave_function_arg, so there is
12324 nothing further to do at this point. */
12325 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12326 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12327 && cum->nargs_prototype > 0)
12329 static bool warned;
12331 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12332 int n_words = rs6000_arg_size (mode, type);
12334 align_words += fpr_words;
12335 n_words -= fpr_words;
12339 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12340 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12341 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12343 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12345 if (!warned && warn_psabi)
12348 inform (input_location,
12349 "the ABI of passing homogeneous float aggregates"
12350 " has changed in GCC 5");
12354 return rs6000_finish_function_arg (mode, rvec, k);
12356 else if (align_words < GP_ARG_NUM_REG)
12358 if (TARGET_32BIT && TARGET_POWERPC64)
12359 return rs6000_mixed_function_arg (mode, type, align_words);
12361 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12368 /* For an arg passed partly in registers and partly in memory, this is
12369 the number of bytes passed in registers. For args passed entirely in
12370 registers or entirely in memory, zero. When an arg is described by a
12371 PARALLEL, perhaps using more than one register type, this function
12372 returns the number of bytes used by the first element of the PARALLEL. */
12375 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12376 tree type, bool named)
12378 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12379 bool passed_in_gprs = true;
12382 machine_mode elt_mode;
12385 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12387 if (DEFAULT_ABI == ABI_V4)
12390 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12392 /* If we are passing this arg in the fixed parameter save area (gprs or
12393 memory) as well as VRs, we do not use the partial bytes mechanism;
12394 instead, rs6000_function_arg will return a PARALLEL including a memory
12395 element as necessary. Library support functions for IEEE 128-bit are
12396 assumed to not need the value passed both in GPRs and in vector
12398 if (TARGET_64BIT && !cum->prototype
12399 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12402 /* Otherwise, we pass in VRs only. Check for partial copies. */
12403 passed_in_gprs = false;
12404 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12405 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12408 /* In this complicated case we just disable the partial_nregs code. */
12409 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12412 align_words = rs6000_parm_start (mode, type, cum->words);
12414 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12416 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12418 /* If we are passing this arg in the fixed parameter save area
12419 (gprs or memory) as well as FPRs, we do not use the partial
12420 bytes mechanism; instead, rs6000_function_arg will return a
12421 PARALLEL including a memory element as necessary. */
12423 && (cum->nargs_prototype <= 0
12424 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12425 && TARGET_XL_COMPAT
12426 && align_words >= GP_ARG_NUM_REG)))
12429 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12430 passed_in_gprs = false;
12431 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12433 /* Compute number of bytes / words passed in FPRs. If there
12434 is still space available in the register parameter area
12435 *after* that amount, a part of the argument will be passed
12436 in GPRs. In that case, the total amount passed in any
12437 registers is equal to the amount that would have been passed
12438 in GPRs if everything were passed there, so we fall back to
12439 the GPR code below to compute the appropriate value. */
12440 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12441 * MIN (8, GET_MODE_SIZE (elt_mode)));
12442 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12444 if (align_words + fpr_words < GP_ARG_NUM_REG)
12445 passed_in_gprs = true;
12452 && align_words < GP_ARG_NUM_REG
12453 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12454 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12456 if (ret != 0 && TARGET_DEBUG_ARG)
12457 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12462 /* A C expression that indicates when an argument must be passed by
12463 reference. If nonzero for an argument, a copy of that argument is
12464 made in memory and a pointer to the argument is passed instead of
12465 the argument itself. The pointer is passed in whatever way is
12466 appropriate for passing a pointer to that type.
12468 Under V.4, aggregates and long double are passed by reference.
12470 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12471 reference unless the AltiVec vector extension ABI is in force.
12473 As an extension to all ABIs, variable sized types are passed by
12477 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12478 machine_mode mode, const_tree type,
12479 bool named ATTRIBUTE_UNUSED)
12484 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12485 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12487 if (TARGET_DEBUG_ARG)
12488 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12492 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12494 if (TARGET_DEBUG_ARG)
12495 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12499 if (int_size_in_bytes (type) < 0)
12501 if (TARGET_DEBUG_ARG)
12502 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12506 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12507 modes only exist for GCC vector types if -maltivec. */
12508 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12510 if (TARGET_DEBUG_ARG)
12511 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12515 /* Pass synthetic vectors in memory. */
12516 if (TREE_CODE (type) == VECTOR_TYPE
12517 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12519 static bool warned_for_pass_big_vectors = false;
12520 if (TARGET_DEBUG_ARG)
12521 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12522 if (!warned_for_pass_big_vectors)
12524 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12525 "non-standard ABI extension with no compatibility "
12527 warned_for_pass_big_vectors = true;
12535 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12536 already processes. Return true if the parameter must be passed
12537 (fully or partially) on the stack. */
12540 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12546 /* Catch errors. */
12547 if (type == NULL || type == error_mark_node)
12550 /* Handle types with no storage requirement. */
12551 if (TYPE_MODE (type) == VOIDmode)
12554 /* Handle complex types. */
12555 if (TREE_CODE (type) == COMPLEX_TYPE)
12556 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12557 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12559 /* Handle transparent aggregates. */
12560 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12561 && TYPE_TRANSPARENT_AGGR (type))
12562 type = TREE_TYPE (first_field (type));
12564 /* See if this arg was passed by invisible reference. */
12565 if (pass_by_reference (get_cumulative_args (args_so_far),
12566 TYPE_MODE (type), type, true))
12567 type = build_pointer_type (type);
12569 /* Find mode as it is passed by the ABI. */
12570 unsignedp = TYPE_UNSIGNED (type);
12571 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12573 /* If we must pass in stack, we need a stack. */
12574 if (rs6000_must_pass_in_stack (mode, type))
12577 /* If there is no incoming register, we need a stack. */
12578 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12579 if (entry_parm == NULL)
12582 /* Likewise if we need to pass both in registers and on the stack. */
12583 if (GET_CODE (entry_parm) == PARALLEL
12584 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12587 /* Also true if we're partially in registers and partially not. */
12588 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12591 /* Update info on where next arg arrives in registers. */
12592 rs6000_function_arg_advance (args_so_far, mode, type, true);
12596 /* Return true if FUN has no prototype, has a variable argument
12597 list, or passes any parameter in memory. */
12600 rs6000_function_parms_need_stack (tree fun, bool incoming)
12602 tree fntype, result;
12603 CUMULATIVE_ARGS args_so_far_v;
12604 cumulative_args_t args_so_far;
12607 /* Must be a libcall, all of which only use reg parms. */
12612 fntype = TREE_TYPE (fun);
12614 /* Varargs functions need the parameter save area. */
12615 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12618 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12619 args_so_far = pack_cumulative_args (&args_so_far_v);
12621 /* When incoming, we will have been passed the function decl.
12622 It is necessary to use the decl to handle K&R style functions,
12623 where TYPE_ARG_TYPES may not be available. */
12626 gcc_assert (DECL_P (fun));
12627 result = DECL_RESULT (fun);
12630 result = TREE_TYPE (fntype);
12632 if (result && aggregate_value_p (result, fntype))
12634 if (!TYPE_P (result))
12635 result = TREE_TYPE (result);
12636 result = build_pointer_type (result);
12637 rs6000_parm_needs_stack (args_so_far, result);
12644 for (parm = DECL_ARGUMENTS (fun);
12645 parm && parm != void_list_node;
12646 parm = TREE_CHAIN (parm))
12647 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12652 function_args_iterator args_iter;
12655 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12656 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12663 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12664 usually a constant depending on the ABI. However, in the ELFv2 ABI
12665 the register parameter area is optional when calling a function that
12666 has a prototype is scope, has no variable argument list, and passes
12667 all parameters in registers. */
12670 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12672 int reg_parm_stack_space;
12674 switch (DEFAULT_ABI)
12677 reg_parm_stack_space = 0;
12682 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12686 /* ??? Recomputing this every time is a bit expensive. Is there
12687 a place to cache this information? */
12688 if (rs6000_function_parms_need_stack (fun, incoming))
12689 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12691 reg_parm_stack_space = 0;
12695 return reg_parm_stack_space;
12699 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12702 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12707 for (i = 0; i < nregs; i++)
12709 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12710 if (reload_completed)
12712 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12715 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12716 i * GET_MODE_SIZE (reg_mode));
12719 tem = replace_equiv_address (tem, XEXP (tem, 0));
12723 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12727 /* Perform any needed actions needed for a function that is receiving a
12728 variable number of arguments.
12732 MODE and TYPE are the mode and type of the current parameter.
12734 PRETEND_SIZE is a variable that should be set to the amount of stack
12735 that must be pushed by the prolog to pretend that our caller pushed
12738 Normally, this macro will push all remaining incoming registers on the
12739 stack and set PRETEND_SIZE to the length of the registers pushed. */
12742 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12743 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12746 CUMULATIVE_ARGS next_cum;
12747 int reg_size = TARGET_32BIT ? 4 : 8;
12748 rtx save_area = NULL_RTX, mem;
12749 int first_reg_offset;
12750 alias_set_type set;
12752 /* Skip the last named argument. */
12753 next_cum = *get_cumulative_args (cum);
12754 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12756 if (DEFAULT_ABI == ABI_V4)
12758 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12762 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12763 HOST_WIDE_INT offset = 0;
12765 /* Try to optimize the size of the varargs save area.
12766 The ABI requires that ap.reg_save_area is doubleword
12767 aligned, but we don't need to allocate space for all
12768 the bytes, only those to which we actually will save
12770 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12771 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12772 if (TARGET_HARD_FLOAT
12773 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12774 && cfun->va_list_fpr_size)
12777 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12778 * UNITS_PER_FP_WORD;
12779 if (cfun->va_list_fpr_size
12780 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12781 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12783 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12784 * UNITS_PER_FP_WORD;
12788 offset = -((first_reg_offset * reg_size) & ~7);
12789 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12791 gpr_reg_num = cfun->va_list_gpr_size;
12792 if (reg_size == 4 && (first_reg_offset & 1))
12795 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12798 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12799 * UNITS_PER_FP_WORD
12800 - (int) (GP_ARG_NUM_REG * reg_size);
12802 if (gpr_size + fpr_size)
12805 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12806 gcc_assert (GET_CODE (reg_save_area) == MEM);
12807 reg_save_area = XEXP (reg_save_area, 0);
12808 if (GET_CODE (reg_save_area) == PLUS)
12810 gcc_assert (XEXP (reg_save_area, 0)
12811 == virtual_stack_vars_rtx);
12812 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
12813 offset += INTVAL (XEXP (reg_save_area, 1));
12816 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12819 cfun->machine->varargs_save_offset = offset;
12820 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12825 first_reg_offset = next_cum.words;
12826 save_area = crtl->args.internal_arg_pointer;
12828 if (targetm.calls.must_pass_in_stack (mode, type))
12829 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12832 set = get_varargs_alias_set ();
12833 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12834 && cfun->va_list_gpr_size)
12836 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12838 if (va_list_gpr_counter_field)
12839 /* V4 va_list_gpr_size counts number of registers needed. */
12840 n_gpr = cfun->va_list_gpr_size;
12842 /* char * va_list instead counts number of bytes needed. */
12843 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12848 mem = gen_rtx_MEM (BLKmode,
12849 plus_constant (Pmode, save_area,
12850 first_reg_offset * reg_size));
12851 MEM_NOTRAP_P (mem) = 1;
12852 set_mem_alias_set (mem, set);
12853 set_mem_align (mem, BITS_PER_WORD);
12855 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12859 /* Save FP registers if needed. */
12860 if (DEFAULT_ABI == ABI_V4
12861 && TARGET_HARD_FLOAT
12863 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12864 && cfun->va_list_fpr_size)
12866 int fregno = next_cum.fregno, nregs;
12867 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12868 rtx lab = gen_label_rtx ();
12869 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12870 * UNITS_PER_FP_WORD);
12873 (gen_rtx_SET (pc_rtx,
12874 gen_rtx_IF_THEN_ELSE (VOIDmode,
12875 gen_rtx_NE (VOIDmode, cr1,
12877 gen_rtx_LABEL_REF (VOIDmode, lab),
12881 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12882 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12884 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12885 plus_constant (Pmode, save_area, off));
12886 MEM_NOTRAP_P (mem) = 1;
12887 set_mem_alias_set (mem, set);
12888 set_mem_align (mem, GET_MODE_ALIGNMENT (
12889 TARGET_HARD_FLOAT ? DFmode : SFmode));
12890 emit_move_insn (mem, gen_rtx_REG (
12891 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12898 /* Create the va_list data type. */
12901 rs6000_build_builtin_va_list (void)
12903 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12905 /* For AIX, prefer 'char *' because that's what the system
12906 header files like. */
12907 if (DEFAULT_ABI != ABI_V4)
12908 return build_pointer_type (char_type_node);
12910 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12911 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12912 get_identifier ("__va_list_tag"), record);
12914 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12915 unsigned_char_type_node);
12916 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12917 unsigned_char_type_node);
12918 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12919 every user file. */
12920 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12921 get_identifier ("reserved"), short_unsigned_type_node);
12922 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12923 get_identifier ("overflow_arg_area"),
12925 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12926 get_identifier ("reg_save_area"),
12929 va_list_gpr_counter_field = f_gpr;
12930 va_list_fpr_counter_field = f_fpr;
12932 DECL_FIELD_CONTEXT (f_gpr) = record;
12933 DECL_FIELD_CONTEXT (f_fpr) = record;
12934 DECL_FIELD_CONTEXT (f_res) = record;
12935 DECL_FIELD_CONTEXT (f_ovf) = record;
12936 DECL_FIELD_CONTEXT (f_sav) = record;
12938 TYPE_STUB_DECL (record) = type_decl;
12939 TYPE_NAME (record) = type_decl;
12940 TYPE_FIELDS (record) = f_gpr;
12941 DECL_CHAIN (f_gpr) = f_fpr;
12942 DECL_CHAIN (f_fpr) = f_res;
12943 DECL_CHAIN (f_res) = f_ovf;
12944 DECL_CHAIN (f_ovf) = f_sav;
12946 layout_type (record);
12948 /* The correct type is an array type of one element. */
12949 return build_array_type (record, build_index_type (size_zero_node));
12952 /* Implement va_start. */
12955 rs6000_va_start (tree valist, rtx nextarg)
12957 HOST_WIDE_INT words, n_gpr, n_fpr;
12958 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12959 tree gpr, fpr, ovf, sav, t;
12961 /* Only SVR4 needs something special. */
12962 if (DEFAULT_ABI != ABI_V4)
12964 std_expand_builtin_va_start (valist, nextarg);
12968 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12969 f_fpr = DECL_CHAIN (f_gpr);
12970 f_res = DECL_CHAIN (f_fpr);
12971 f_ovf = DECL_CHAIN (f_res);
12972 f_sav = DECL_CHAIN (f_ovf);
12974 valist = build_simple_mem_ref (valist);
12975 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12976 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12978 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12980 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12983 /* Count number of gp and fp argument registers used. */
12984 words = crtl->args.info.words;
12985 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12987 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12990 if (TARGET_DEBUG_ARG)
12991 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12992 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12993 words, n_gpr, n_fpr);
12995 if (cfun->va_list_gpr_size)
12997 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12998 build_int_cst (NULL_TREE, n_gpr));
12999 TREE_SIDE_EFFECTS (t) = 1;
13000 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13003 if (cfun->va_list_fpr_size)
13005 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13006 build_int_cst (NULL_TREE, n_fpr));
13007 TREE_SIDE_EFFECTS (t) = 1;
13008 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13010 #ifdef HAVE_AS_GNU_ATTRIBUTE
13011 if (call_ABI_of_interest (cfun->decl))
13012 rs6000_passes_float = true;
13016 /* Find the overflow area. */
13017 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13019 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13020 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13021 TREE_SIDE_EFFECTS (t) = 1;
13022 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13024 /* If there were no va_arg invocations, don't set up the register
13026 if (!cfun->va_list_gpr_size
13027 && !cfun->va_list_fpr_size
13028 && n_gpr < GP_ARG_NUM_REG
13029 && n_fpr < FP_ARG_V4_MAX_REG)
13032 /* Find the register save area. */
13033 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13034 if (cfun->machine->varargs_save_offset)
13035 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13036 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13037 TREE_SIDE_EFFECTS (t) = 1;
13038 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13041 /* Implement va_arg. */
13044 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13045 gimple_seq *post_p)
13047 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13048 tree gpr, fpr, ovf, sav, reg, t, u;
13049 int size, rsize, n_reg, sav_ofs, sav_scale;
13050 tree lab_false, lab_over, addr;
13052 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13056 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13058 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13059 return build_va_arg_indirect_ref (t);
13062 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13063 earlier version of gcc, with the property that it always applied alignment
13064 adjustments to the va-args (even for zero-sized types). The cheapest way
13065 to deal with this is to replicate the effect of the part of
13066 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13068 We don't need to check for pass-by-reference because of the test above.
13069 We can return a simplifed answer, since we know there's no offset to add. */
13072 && rs6000_darwin64_abi)
13073 || DEFAULT_ABI == ABI_ELFv2
13074 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13075 && integer_zerop (TYPE_SIZE (type)))
13077 unsigned HOST_WIDE_INT align, boundary;
13078 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13079 align = PARM_BOUNDARY / BITS_PER_UNIT;
13080 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13081 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13082 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13083 boundary /= BITS_PER_UNIT;
13084 if (boundary > align)
13087 /* This updates arg ptr by the amount that would be necessary
13088 to align the zero-sized (but not zero-alignment) item. */
13089 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13090 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13091 gimplify_and_add (t, pre_p);
13093 t = fold_convert (sizetype, valist_tmp);
13094 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13095 fold_convert (TREE_TYPE (valist),
13096 fold_build2 (BIT_AND_EXPR, sizetype, t,
13097 size_int (-boundary))));
13098 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13099 gimplify_and_add (t, pre_p);
13101 /* Since it is zero-sized there's no increment for the item itself. */
13102 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13103 return build_va_arg_indirect_ref (valist_tmp);
13106 if (DEFAULT_ABI != ABI_V4)
13108 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13110 tree elem_type = TREE_TYPE (type);
13111 machine_mode elem_mode = TYPE_MODE (elem_type);
13112 int elem_size = GET_MODE_SIZE (elem_mode);
13114 if (elem_size < UNITS_PER_WORD)
13116 tree real_part, imag_part;
13117 gimple_seq post = NULL;
13119 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13121 /* Copy the value into a temporary, lest the formal temporary
13122 be reused out from under us. */
13123 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13124 gimple_seq_add_seq (pre_p, post);
13126 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13129 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13133 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13136 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13137 f_fpr = DECL_CHAIN (f_gpr);
13138 f_res = DECL_CHAIN (f_fpr);
13139 f_ovf = DECL_CHAIN (f_res);
13140 f_sav = DECL_CHAIN (f_ovf);
13142 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13143 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13145 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13147 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13150 size = int_size_in_bytes (type);
13151 rsize = (size + 3) / 4;
13152 int pad = 4 * rsize - size;
13155 machine_mode mode = TYPE_MODE (type);
13156 if (abi_v4_pass_in_fpr (mode, false))
13158 /* FP args go in FP registers, if present. */
13160 n_reg = (size + 7) / 8;
13161 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
13162 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
13163 if (mode != SFmode && mode != SDmode)
13168 /* Otherwise into GP registers. */
13177 /* Pull the value out of the saved registers.... */
13180 addr = create_tmp_var (ptr_type_node, "addr");
13182 /* AltiVec vectors never go in registers when -mabi=altivec. */
13183 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13187 lab_false = create_artificial_label (input_location);
13188 lab_over = create_artificial_label (input_location);
13190 /* Long long is aligned in the registers. As are any other 2 gpr
13191 item such as complex int due to a historical mistake. */
13193 if (n_reg == 2 && reg == gpr)
13196 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13197 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13198 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13199 unshare_expr (reg), u);
13201 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13202 reg number is 0 for f1, so we want to make it odd. */
13203 else if (reg == fpr && mode == TDmode)
13205 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13206 build_int_cst (TREE_TYPE (reg), 1));
13207 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13210 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13211 t = build2 (GE_EXPR, boolean_type_node, u, t);
13212 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13213 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13214 gimplify_and_add (t, pre_p);
13218 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13220 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13221 build_int_cst (TREE_TYPE (reg), n_reg));
13222 u = fold_convert (sizetype, u);
13223 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13224 t = fold_build_pointer_plus (t, u);
13226 /* _Decimal32 varargs are located in the second word of the 64-bit
13227 FP register for 32-bit binaries. */
13228 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13229 t = fold_build_pointer_plus_hwi (t, size);
13231 /* Args are passed right-aligned. */
13232 if (BYTES_BIG_ENDIAN)
13233 t = fold_build_pointer_plus_hwi (t, pad);
13235 gimplify_assign (addr, t, pre_p);
13237 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13239 stmt = gimple_build_label (lab_false);
13240 gimple_seq_add_stmt (pre_p, stmt);
13242 if ((n_reg == 2 && !regalign) || n_reg > 2)
13244 /* Ensure that we don't find any more args in regs.
13245 Alignment has taken care of for special cases. */
13246 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13250 /* ... otherwise out of the overflow area. */
13252 /* Care for on-stack alignment if needed. */
13256 t = fold_build_pointer_plus_hwi (t, align - 1);
13257 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13258 build_int_cst (TREE_TYPE (t), -align));
13261 /* Args are passed right-aligned. */
13262 if (BYTES_BIG_ENDIAN)
13263 t = fold_build_pointer_plus_hwi (t, pad);
13265 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13267 gimplify_assign (unshare_expr (addr), t, pre_p);
13269 t = fold_build_pointer_plus_hwi (t, size);
13270 gimplify_assign (unshare_expr (ovf), t, pre_p);
13274 stmt = gimple_build_label (lab_over);
13275 gimple_seq_add_stmt (pre_p, stmt);
13278 if (STRICT_ALIGNMENT
13279 && (TYPE_ALIGN (type)
13280 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13282 /* The value (of type complex double, for example) may not be
13283 aligned in memory in the saved registers, so copy via a
13284 temporary. (This is the same code as used for SPARC.) */
13285 tree tmp = create_tmp_var (type, "va_arg_tmp");
13286 tree dest_addr = build_fold_addr_expr (tmp);
13288 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13289 3, dest_addr, addr, size_int (rsize * 4));
13290 TREE_ADDRESSABLE (tmp) = 1;
13292 gimplify_and_add (copy, pre_p);
13296 addr = fold_convert (ptrtype, addr);
13297 return build_va_arg_indirect_ref (addr);
13303 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13306 unsigned classify = rs6000_builtin_info[(int)code].attr;
13307 const char *attr_string = "";
13309 gcc_assert (name != NULL);
13310 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13312 if (rs6000_builtin_decls[(int)code])
13313 fatal_error (input_location,
13314 "internal error: builtin function %qs already processed",
13317 rs6000_builtin_decls[(int)code] = t =
13318 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13320 /* Set any special attributes. */
13321 if ((classify & RS6000_BTC_CONST) != 0)
13323 /* const function, function only depends on the inputs. */
13324 TREE_READONLY (t) = 1;
13325 TREE_NOTHROW (t) = 1;
13326 attr_string = ", const";
13328 else if ((classify & RS6000_BTC_PURE) != 0)
13330 /* pure function, function can read global memory, but does not set any
13332 DECL_PURE_P (t) = 1;
13333 TREE_NOTHROW (t) = 1;
13334 attr_string = ", pure";
13336 else if ((classify & RS6000_BTC_FP) != 0)
13338 /* Function is a math function. If rounding mode is on, then treat the
13339 function as not reading global memory, but it can have arbitrary side
13340 effects. If it is off, then assume the function is a const function.
13341 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13342 builtin-attribute.def that is used for the math functions. */
13343 TREE_NOTHROW (t) = 1;
13344 if (flag_rounding_math)
13346 DECL_PURE_P (t) = 1;
13347 DECL_IS_NOVOPS (t) = 1;
13348 attr_string = ", fp, pure";
13352 TREE_READONLY (t) = 1;
13353 attr_string = ", fp, const";
13356 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13357 gcc_unreachable ();
13359 if (TARGET_DEBUG_BUILTIN)
13360 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13361 (int)code, name, attr_string);
13364 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13366 #undef RS6000_BUILTIN_0
13367 #undef RS6000_BUILTIN_1
13368 #undef RS6000_BUILTIN_2
13369 #undef RS6000_BUILTIN_3
13370 #undef RS6000_BUILTIN_A
13371 #undef RS6000_BUILTIN_D
13372 #undef RS6000_BUILTIN_H
13373 #undef RS6000_BUILTIN_P
13374 #undef RS6000_BUILTIN_X
13376 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13377 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13378 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13379 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13380 { MASK, ICODE, NAME, ENUM },
13382 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13383 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13384 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13385 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13386 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13388 static const struct builtin_description bdesc_3arg[] =
13390 #include "rs6000-builtin.def"
13393 /* DST operations: void foo (void *, const int, const char). */
13395 #undef RS6000_BUILTIN_0
13396 #undef RS6000_BUILTIN_1
13397 #undef RS6000_BUILTIN_2
13398 #undef RS6000_BUILTIN_3
13399 #undef RS6000_BUILTIN_A
13400 #undef RS6000_BUILTIN_D
13401 #undef RS6000_BUILTIN_H
13402 #undef RS6000_BUILTIN_P
13403 #undef RS6000_BUILTIN_X
13405 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13406 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13407 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13408 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13409 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13410 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13411 { MASK, ICODE, NAME, ENUM },
13413 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13414 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13415 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13417 static const struct builtin_description bdesc_dst[] =
13419 #include "rs6000-builtin.def"
13422 /* Simple binary operations: VECc = foo (VECa, VECb). */
13424 #undef RS6000_BUILTIN_0
13425 #undef RS6000_BUILTIN_1
13426 #undef RS6000_BUILTIN_2
13427 #undef RS6000_BUILTIN_3
13428 #undef RS6000_BUILTIN_A
13429 #undef RS6000_BUILTIN_D
13430 #undef RS6000_BUILTIN_H
13431 #undef RS6000_BUILTIN_P
13432 #undef RS6000_BUILTIN_X
13434 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13435 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13436 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13437 { MASK, ICODE, NAME, ENUM },
13439 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13440 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13441 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13442 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13443 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13444 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13446 static const struct builtin_description bdesc_2arg[] =
13448 #include "rs6000-builtin.def"
13451 #undef RS6000_BUILTIN_0
13452 #undef RS6000_BUILTIN_1
13453 #undef RS6000_BUILTIN_2
13454 #undef RS6000_BUILTIN_3
13455 #undef RS6000_BUILTIN_A
13456 #undef RS6000_BUILTIN_D
13457 #undef RS6000_BUILTIN_H
13458 #undef RS6000_BUILTIN_P
13459 #undef RS6000_BUILTIN_X
13461 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13462 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13463 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13464 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13465 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13466 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13467 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13468 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13469 { MASK, ICODE, NAME, ENUM },
13471 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13473 /* AltiVec predicates. */
13475 static const struct builtin_description bdesc_altivec_preds[] =
13477 #include "rs6000-builtin.def"
13480 /* ABS* operations. */
13482 #undef RS6000_BUILTIN_0
13483 #undef RS6000_BUILTIN_1
13484 #undef RS6000_BUILTIN_2
13485 #undef RS6000_BUILTIN_3
13486 #undef RS6000_BUILTIN_A
13487 #undef RS6000_BUILTIN_D
13488 #undef RS6000_BUILTIN_H
13489 #undef RS6000_BUILTIN_P
13490 #undef RS6000_BUILTIN_X
13492 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13493 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13494 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13495 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13496 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13497 { MASK, ICODE, NAME, ENUM },
13499 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13500 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13501 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13502 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13504 static const struct builtin_description bdesc_abs[] =
13506 #include "rs6000-builtin.def"
13509 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13512 #undef RS6000_BUILTIN_0
13513 #undef RS6000_BUILTIN_1
13514 #undef RS6000_BUILTIN_2
13515 #undef RS6000_BUILTIN_3
13516 #undef RS6000_BUILTIN_A
13517 #undef RS6000_BUILTIN_D
13518 #undef RS6000_BUILTIN_H
13519 #undef RS6000_BUILTIN_P
13520 #undef RS6000_BUILTIN_X
13522 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13523 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13524 { MASK, ICODE, NAME, ENUM },
13526 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13527 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13528 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13529 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13530 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13531 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13532 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13534 static const struct builtin_description bdesc_1arg[] =
13536 #include "rs6000-builtin.def"
13539 /* Simple no-argument operations: result = __builtin_darn_32 () */
13541 #undef RS6000_BUILTIN_0
13542 #undef RS6000_BUILTIN_1
13543 #undef RS6000_BUILTIN_2
13544 #undef RS6000_BUILTIN_3
13545 #undef RS6000_BUILTIN_A
13546 #undef RS6000_BUILTIN_D
13547 #undef RS6000_BUILTIN_H
13548 #undef RS6000_BUILTIN_P
13549 #undef RS6000_BUILTIN_X
13551 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13552 { MASK, ICODE, NAME, ENUM },
13554 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13555 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13556 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13557 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13558 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13559 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13560 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13561 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13563 static const struct builtin_description bdesc_0arg[] =
13565 #include "rs6000-builtin.def"
13568 /* HTM builtins. */
13569 #undef RS6000_BUILTIN_0
13570 #undef RS6000_BUILTIN_1
13571 #undef RS6000_BUILTIN_2
13572 #undef RS6000_BUILTIN_3
13573 #undef RS6000_BUILTIN_A
13574 #undef RS6000_BUILTIN_D
13575 #undef RS6000_BUILTIN_H
13576 #undef RS6000_BUILTIN_P
13577 #undef RS6000_BUILTIN_X
13579 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13580 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13581 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13582 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13583 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13584 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13585 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13586 { MASK, ICODE, NAME, ENUM },
13588 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13589 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13591 static const struct builtin_description bdesc_htm[] =
13593 #include "rs6000-builtin.def"
13596 #undef RS6000_BUILTIN_0
13597 #undef RS6000_BUILTIN_1
13598 #undef RS6000_BUILTIN_2
13599 #undef RS6000_BUILTIN_3
13600 #undef RS6000_BUILTIN_A
13601 #undef RS6000_BUILTIN_D
13602 #undef RS6000_BUILTIN_H
13603 #undef RS6000_BUILTIN_P
13605 /* Return true if a builtin function is overloaded. */
13607 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13609 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13613 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13615 return rs6000_builtin_info[(int)fncode].name;
13618 /* Expand an expression EXP that calls a builtin without arguments. */
13620 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13623 machine_mode tmode = insn_data[icode].operand[0].mode;
13625 if (icode == CODE_FOR_nothing)
13626 /* Builtin not supported on this processor. */
13630 || GET_MODE (target) != tmode
13631 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13632 target = gen_reg_rtx (tmode);
13634 pat = GEN_FCN (icode) (target);
13644 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13647 tree arg0 = CALL_EXPR_ARG (exp, 0);
13648 tree arg1 = CALL_EXPR_ARG (exp, 1);
13649 rtx op0 = expand_normal (arg0);
13650 rtx op1 = expand_normal (arg1);
13651 machine_mode mode0 = insn_data[icode].operand[0].mode;
13652 machine_mode mode1 = insn_data[icode].operand[1].mode;
13654 if (icode == CODE_FOR_nothing)
13655 /* Builtin not supported on this processor. */
13658 /* If we got invalid arguments bail out before generating bad rtl. */
13659 if (arg0 == error_mark_node || arg1 == error_mark_node)
13662 if (GET_CODE (op0) != CONST_INT
13663 || INTVAL (op0) > 255
13664 || INTVAL (op0) < 0)
13666 error ("argument 1 must be an 8-bit field value");
13670 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13671 op0 = copy_to_mode_reg (mode0, op0);
13673 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13674 op1 = copy_to_mode_reg (mode1, op1);
13676 pat = GEN_FCN (icode) (op0, op1);
13685 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13688 tree arg0 = CALL_EXPR_ARG (exp, 0);
13689 rtx op0 = expand_normal (arg0);
13690 machine_mode tmode = insn_data[icode].operand[0].mode;
13691 machine_mode mode0 = insn_data[icode].operand[1].mode;
13693 if (icode == CODE_FOR_nothing)
13694 /* Builtin not supported on this processor. */
13697 /* If we got invalid arguments bail out before generating bad rtl. */
13698 if (arg0 == error_mark_node)
13701 if (icode == CODE_FOR_altivec_vspltisb
13702 || icode == CODE_FOR_altivec_vspltish
13703 || icode == CODE_FOR_altivec_vspltisw)
13705 /* Only allow 5-bit *signed* literals. */
13706 if (GET_CODE (op0) != CONST_INT
13707 || INTVAL (op0) > 15
13708 || INTVAL (op0) < -16)
13710 error ("argument 1 must be a 5-bit signed literal");
13711 return CONST0_RTX (tmode);
13716 || GET_MODE (target) != tmode
13717 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13718 target = gen_reg_rtx (tmode);
13720 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13721 op0 = copy_to_mode_reg (mode0, op0);
13723 pat = GEN_FCN (icode) (target, op0);
13732 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13734 rtx pat, scratch1, scratch2;
13735 tree arg0 = CALL_EXPR_ARG (exp, 0);
13736 rtx op0 = expand_normal (arg0);
13737 machine_mode tmode = insn_data[icode].operand[0].mode;
13738 machine_mode mode0 = insn_data[icode].operand[1].mode;
13740 /* If we have invalid arguments, bail out before generating bad rtl. */
13741 if (arg0 == error_mark_node)
13745 || GET_MODE (target) != tmode
13746 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13747 target = gen_reg_rtx (tmode);
13749 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13750 op0 = copy_to_mode_reg (mode0, op0);
13752 scratch1 = gen_reg_rtx (mode0);
13753 scratch2 = gen_reg_rtx (mode0);
13755 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13764 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13767 tree arg0 = CALL_EXPR_ARG (exp, 0);
13768 tree arg1 = CALL_EXPR_ARG (exp, 1);
13769 rtx op0 = expand_normal (arg0);
13770 rtx op1 = expand_normal (arg1);
13771 machine_mode tmode = insn_data[icode].operand[0].mode;
13772 machine_mode mode0 = insn_data[icode].operand[1].mode;
13773 machine_mode mode1 = insn_data[icode].operand[2].mode;
13775 if (icode == CODE_FOR_nothing)
13776 /* Builtin not supported on this processor. */
13779 /* If we got invalid arguments bail out before generating bad rtl. */
13780 if (arg0 == error_mark_node || arg1 == error_mark_node)
13783 if (icode == CODE_FOR_altivec_vcfux
13784 || icode == CODE_FOR_altivec_vcfsx
13785 || icode == CODE_FOR_altivec_vctsxs
13786 || icode == CODE_FOR_altivec_vctuxs
13787 || icode == CODE_FOR_altivec_vspltb
13788 || icode == CODE_FOR_altivec_vsplth
13789 || icode == CODE_FOR_altivec_vspltw)
13791 /* Only allow 5-bit unsigned literals. */
13793 if (TREE_CODE (arg1) != INTEGER_CST
13794 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13796 error ("argument 2 must be a 5-bit unsigned literal");
13797 return CONST0_RTX (tmode);
13800 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13801 || icode == CODE_FOR_dfptstsfi_lt_dd
13802 || icode == CODE_FOR_dfptstsfi_gt_dd
13803 || icode == CODE_FOR_dfptstsfi_unordered_dd
13804 || icode == CODE_FOR_dfptstsfi_eq_td
13805 || icode == CODE_FOR_dfptstsfi_lt_td
13806 || icode == CODE_FOR_dfptstsfi_gt_td
13807 || icode == CODE_FOR_dfptstsfi_unordered_td)
13809 /* Only allow 6-bit unsigned literals. */
13811 if (TREE_CODE (arg0) != INTEGER_CST
13812 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13814 error ("argument 1 must be a 6-bit unsigned literal");
13815 return CONST0_RTX (tmode);
13818 else if (icode == CODE_FOR_xststdcqp_kf
13819 || icode == CODE_FOR_xststdcqp_tf
13820 || icode == CODE_FOR_xststdcdp
13821 || icode == CODE_FOR_xststdcsp
13822 || icode == CODE_FOR_xvtstdcdp
13823 || icode == CODE_FOR_xvtstdcsp)
13825 /* Only allow 7-bit unsigned literals. */
13827 if (TREE_CODE (arg1) != INTEGER_CST
13828 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13830 error ("argument 2 must be a 7-bit unsigned literal");
13831 return CONST0_RTX (tmode);
13834 else if (icode == CODE_FOR_unpackv1ti
13835 || icode == CODE_FOR_unpackkf
13836 || icode == CODE_FOR_unpacktf
13837 || icode == CODE_FOR_unpackif
13838 || icode == CODE_FOR_unpacktd)
13840 /* Only allow 1-bit unsigned literals. */
13842 if (TREE_CODE (arg1) != INTEGER_CST
13843 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13845 error ("argument 2 must be a 1-bit unsigned literal");
13846 return CONST0_RTX (tmode);
13851 || GET_MODE (target) != tmode
13852 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13853 target = gen_reg_rtx (tmode);
13855 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13856 op0 = copy_to_mode_reg (mode0, op0);
13857 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13858 op1 = copy_to_mode_reg (mode1, op1);
13860 pat = GEN_FCN (icode) (target, op0, op1);
13869 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13872 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13873 tree arg0 = CALL_EXPR_ARG (exp, 1);
13874 tree arg1 = CALL_EXPR_ARG (exp, 2);
13875 rtx op0 = expand_normal (arg0);
13876 rtx op1 = expand_normal (arg1);
13877 machine_mode tmode = SImode;
13878 machine_mode mode0 = insn_data[icode].operand[1].mode;
13879 machine_mode mode1 = insn_data[icode].operand[2].mode;
13882 if (TREE_CODE (cr6_form) != INTEGER_CST)
13884 error ("argument 1 of %qs must be a constant",
13885 "__builtin_altivec_predicate");
13889 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13891 gcc_assert (mode0 == mode1);
13893 /* If we have invalid arguments, bail out before generating bad rtl. */
13894 if (arg0 == error_mark_node || arg1 == error_mark_node)
13898 || GET_MODE (target) != tmode
13899 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13900 target = gen_reg_rtx (tmode);
13902 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13903 op0 = copy_to_mode_reg (mode0, op0);
13904 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13905 op1 = copy_to_mode_reg (mode1, op1);
13907 /* Note that for many of the relevant operations (e.g. cmpne or
13908 cmpeq) with float or double operands, it makes more sense for the
13909 mode of the allocated scratch register to select a vector of
13910 integer. But the choice to copy the mode of operand 0 was made
13911 long ago and there are no plans to change it. */
13912 scratch = gen_reg_rtx (mode0);
13914 pat = GEN_FCN (icode) (scratch, op0, op1);
13919 /* The vec_any* and vec_all* predicates use the same opcodes for two
13920 different operations, but the bits in CR6 will be different
13921 depending on what information we want. So we have to play tricks
13922 with CR6 to get the right bits out.
13924 If you think this is disgusting, look at the specs for the
13925 AltiVec predicates. */
13927 switch (cr6_form_int)
13930 emit_insn (gen_cr6_test_for_zero (target));
13933 emit_insn (gen_cr6_test_for_zero_reverse (target));
13936 emit_insn (gen_cr6_test_for_lt (target));
13939 emit_insn (gen_cr6_test_for_lt_reverse (target));
13942 error ("argument 1 of %qs is out of range",
13943 "__builtin_altivec_predicate");
13951 swap_endian_selector_for_mode (machine_mode mode)
13953 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13954 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13955 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13956 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13958 unsigned int *swaparray, i;
13978 gcc_unreachable ();
13981 for (i = 0; i < 16; ++i)
13982 perm[i] = GEN_INT (swaparray[i]);
13984 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13985 gen_rtvec_v (16, perm)));
13989 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13992 tree arg0 = CALL_EXPR_ARG (exp, 0);
13993 tree arg1 = CALL_EXPR_ARG (exp, 1);
13994 machine_mode tmode = insn_data[icode].operand[0].mode;
13995 machine_mode mode0 = Pmode;
13996 machine_mode mode1 = Pmode;
13997 rtx op0 = expand_normal (arg0);
13998 rtx op1 = expand_normal (arg1);
14000 if (icode == CODE_FOR_nothing)
14001 /* Builtin not supported on this processor. */
14004 /* If we got invalid arguments bail out before generating bad rtl. */
14005 if (arg0 == error_mark_node || arg1 == error_mark_node)
14009 || GET_MODE (target) != tmode
14010 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14011 target = gen_reg_rtx (tmode);
14013 op1 = copy_to_mode_reg (mode1, op1);
14015 /* For LVX, express the RTL accurately by ANDing the address with -16.
14016 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14017 so the raw address is fine. */
14018 if (icode == CODE_FOR_altivec_lvx_v1ti
14019 || icode == CODE_FOR_altivec_lvx_v2df
14020 || icode == CODE_FOR_altivec_lvx_v2di
14021 || icode == CODE_FOR_altivec_lvx_v4sf
14022 || icode == CODE_FOR_altivec_lvx_v4si
14023 || icode == CODE_FOR_altivec_lvx_v8hi
14024 || icode == CODE_FOR_altivec_lvx_v16qi)
14027 if (op0 == const0_rtx)
14031 op0 = copy_to_mode_reg (mode0, op0);
14032 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14034 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14035 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14037 emit_insn (gen_rtx_SET (target, addr));
14041 if (op0 == const0_rtx)
14042 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14045 op0 = copy_to_mode_reg (mode0, op0);
14046 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14047 gen_rtx_PLUS (Pmode, op1, op0));
14050 pat = GEN_FCN (icode) (target, addr);
14060 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14063 tree arg0 = CALL_EXPR_ARG (exp, 0);
14064 tree arg1 = CALL_EXPR_ARG (exp, 1);
14065 tree arg2 = CALL_EXPR_ARG (exp, 2);
14066 rtx op0 = expand_normal (arg0);
14067 rtx op1 = expand_normal (arg1);
14068 rtx op2 = expand_normal (arg2);
14069 machine_mode mode0 = insn_data[icode].operand[0].mode;
14070 machine_mode mode1 = insn_data[icode].operand[1].mode;
14071 machine_mode mode2 = insn_data[icode].operand[2].mode;
14073 if (icode == CODE_FOR_nothing)
14074 /* Builtin not supported on this processor. */
14077 /* If we got invalid arguments bail out before generating bad rtl. */
14078 if (arg0 == error_mark_node
14079 || arg1 == error_mark_node
14080 || arg2 == error_mark_node)
14083 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14084 op0 = copy_to_mode_reg (mode0, op0);
14085 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14086 op1 = copy_to_mode_reg (mode1, op1);
14087 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14088 op2 = copy_to_mode_reg (mode2, op2);
14090 pat = GEN_FCN (icode) (op0, op1, op2);
14098 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14100 tree arg0 = CALL_EXPR_ARG (exp, 0);
14101 tree arg1 = CALL_EXPR_ARG (exp, 1);
14102 tree arg2 = CALL_EXPR_ARG (exp, 2);
14103 rtx op0 = expand_normal (arg0);
14104 rtx op1 = expand_normal (arg1);
14105 rtx op2 = expand_normal (arg2);
14106 rtx pat, addr, rawaddr;
14107 machine_mode tmode = insn_data[icode].operand[0].mode;
14108 machine_mode smode = insn_data[icode].operand[1].mode;
14109 machine_mode mode1 = Pmode;
14110 machine_mode mode2 = Pmode;
14112 /* Invalid arguments. Bail before doing anything stoopid! */
14113 if (arg0 == error_mark_node
14114 || arg1 == error_mark_node
14115 || arg2 == error_mark_node)
14118 op2 = copy_to_mode_reg (mode2, op2);
14120 /* For STVX, express the RTL accurately by ANDing the address with -16.
14121 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14122 so the raw address is fine. */
14123 if (icode == CODE_FOR_altivec_stvx_v2df
14124 || icode == CODE_FOR_altivec_stvx_v2di
14125 || icode == CODE_FOR_altivec_stvx_v4sf
14126 || icode == CODE_FOR_altivec_stvx_v4si
14127 || icode == CODE_FOR_altivec_stvx_v8hi
14128 || icode == CODE_FOR_altivec_stvx_v16qi)
14130 if (op1 == const0_rtx)
14134 op1 = copy_to_mode_reg (mode1, op1);
14135 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14138 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14139 addr = gen_rtx_MEM (tmode, addr);
14141 op0 = copy_to_mode_reg (tmode, op0);
14143 emit_insn (gen_rtx_SET (addr, op0));
14147 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14148 op0 = copy_to_mode_reg (smode, op0);
14150 if (op1 == const0_rtx)
14151 addr = gen_rtx_MEM (tmode, op2);
14154 op1 = copy_to_mode_reg (mode1, op1);
14155 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14158 pat = GEN_FCN (icode) (addr, op0);
14166 /* Return the appropriate SPR number associated with the given builtin. */
14167 static inline HOST_WIDE_INT
14168 htm_spr_num (enum rs6000_builtins code)
14170 if (code == HTM_BUILTIN_GET_TFHAR
14171 || code == HTM_BUILTIN_SET_TFHAR)
14173 else if (code == HTM_BUILTIN_GET_TFIAR
14174 || code == HTM_BUILTIN_SET_TFIAR)
14176 else if (code == HTM_BUILTIN_GET_TEXASR
14177 || code == HTM_BUILTIN_SET_TEXASR)
14179 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14180 || code == HTM_BUILTIN_SET_TEXASRU);
14181 return TEXASRU_SPR;
14184 /* Return the appropriate SPR regno associated with the given builtin. */
14185 static inline HOST_WIDE_INT
14186 htm_spr_regno (enum rs6000_builtins code)
14188 if (code == HTM_BUILTIN_GET_TFHAR
14189 || code == HTM_BUILTIN_SET_TFHAR)
14190 return TFHAR_REGNO;
14191 else if (code == HTM_BUILTIN_GET_TFIAR
14192 || code == HTM_BUILTIN_SET_TFIAR)
14193 return TFIAR_REGNO;
14194 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14195 || code == HTM_BUILTIN_SET_TEXASR
14196 || code == HTM_BUILTIN_GET_TEXASRU
14197 || code == HTM_BUILTIN_SET_TEXASRU);
14198 return TEXASR_REGNO;
14201 /* Return the correct ICODE value depending on whether we are
14202 setting or reading the HTM SPRs. */
14203 static inline enum insn_code
14204 rs6000_htm_spr_icode (bool nonvoid)
14207 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14209 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14212 /* Expand the HTM builtin in EXP and store the result in TARGET.
14213 Store true in *EXPANDEDP if we found a builtin to expand. */
14215 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14217 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14218 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14219 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14220 const struct builtin_description *d;
14225 if (!TARGET_POWERPC64
14226 && (fcode == HTM_BUILTIN_TABORTDC
14227 || fcode == HTM_BUILTIN_TABORTDCI))
14229 size_t uns_fcode = (size_t)fcode;
14230 const char *name = rs6000_builtin_info[uns_fcode].name;
14231 error ("builtin %qs is only valid in 64-bit mode", name);
14235 /* Expand the HTM builtins. */
14237 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14238 if (d->code == fcode)
14240 rtx op[MAX_HTM_OPERANDS], pat;
14243 call_expr_arg_iterator iter;
14244 unsigned attr = rs6000_builtin_info[fcode].attr;
14245 enum insn_code icode = d->icode;
14246 const struct insn_operand_data *insn_op;
14247 bool uses_spr = (attr & RS6000_BTC_SPR);
14251 icode = rs6000_htm_spr_icode (nonvoid);
14252 insn_op = &insn_data[icode].operand[0];
14256 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14258 || GET_MODE (target) != tmode
14259 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14260 target = gen_reg_rtx (tmode);
14262 op[nopnds++] = target;
14265 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14267 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14270 insn_op = &insn_data[icode].operand[nopnds];
14272 op[nopnds] = expand_normal (arg);
14274 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14276 if (!strcmp (insn_op->constraint, "n"))
14278 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14279 if (!CONST_INT_P (op[nopnds]))
14280 error ("argument %d must be an unsigned literal", arg_num);
14282 error ("argument %d is an unsigned literal that is "
14283 "out of range", arg_num);
14286 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14292 /* Handle the builtins for extended mnemonics. These accept
14293 no arguments, but map to builtins that take arguments. */
14296 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14297 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14298 op[nopnds++] = GEN_INT (1);
14300 attr |= RS6000_BTC_UNARY;
14302 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14303 op[nopnds++] = GEN_INT (0);
14305 attr |= RS6000_BTC_UNARY;
14311 /* If this builtin accesses SPRs, then pass in the appropriate
14312 SPR number and SPR regno as the last two operands. */
14315 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14316 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14317 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14319 /* If this builtin accesses a CR, then pass in a scratch
14320 CR as the last operand. */
14321 else if (attr & RS6000_BTC_CR)
14322 { cr = gen_reg_rtx (CCmode);
14328 int expected_nopnds = 0;
14329 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14330 expected_nopnds = 1;
14331 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14332 expected_nopnds = 2;
14333 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14334 expected_nopnds = 3;
14335 if (!(attr & RS6000_BTC_VOID))
14336 expected_nopnds += 1;
14338 expected_nopnds += 2;
14340 gcc_assert (nopnds == expected_nopnds
14341 && nopnds <= MAX_HTM_OPERANDS);
14347 pat = GEN_FCN (icode) (op[0]);
14350 pat = GEN_FCN (icode) (op[0], op[1]);
14353 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14356 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14359 gcc_unreachable ();
14365 if (attr & RS6000_BTC_CR)
14367 if (fcode == HTM_BUILTIN_TBEGIN)
14369 /* Emit code to set TARGET to true or false depending on
14370 whether the tbegin. instruction successfully or failed
14371 to start a transaction. We do this by placing the 1's
14372 complement of CR's EQ bit into TARGET. */
14373 rtx scratch = gen_reg_rtx (SImode);
14374 emit_insn (gen_rtx_SET (scratch,
14375 gen_rtx_EQ (SImode, cr,
14377 emit_insn (gen_rtx_SET (target,
14378 gen_rtx_XOR (SImode, scratch,
14383 /* Emit code to copy the 4-bit condition register field
14384 CR into the least significant end of register TARGET. */
14385 rtx scratch1 = gen_reg_rtx (SImode);
14386 rtx scratch2 = gen_reg_rtx (SImode);
14387 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14388 emit_insn (gen_movcc (subreg, cr));
14389 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14390 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14399 *expandedp = false;
14403 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14406 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14409 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14410 if (fcode == RS6000_BUILTIN_CPU_INIT)
14413 if (target == 0 || GET_MODE (target) != SImode)
14414 target = gen_reg_rtx (SImode);
14416 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14417 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14418 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14419 to a STRING_CST. */
14420 if (TREE_CODE (arg) == ARRAY_REF
14421 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14422 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14423 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14424 arg = TREE_OPERAND (arg, 0);
14426 if (TREE_CODE (arg) != STRING_CST)
14428 error ("builtin %qs only accepts a string argument",
14429 rs6000_builtin_info[(size_t) fcode].name);
14433 if (fcode == RS6000_BUILTIN_CPU_IS)
14435 const char *cpu = TREE_STRING_POINTER (arg);
14436 rtx cpuid = NULL_RTX;
14437 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14438 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14440 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14441 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14444 if (cpuid == NULL_RTX)
14446 /* Invalid CPU argument. */
14447 error ("cpu %qs is an invalid argument to builtin %qs",
14448 cpu, rs6000_builtin_info[(size_t) fcode].name);
14452 rtx platform = gen_reg_rtx (SImode);
14453 rtx tcbmem = gen_const_mem (SImode,
14454 gen_rtx_PLUS (Pmode,
14455 gen_rtx_REG (Pmode, TLS_REGNUM),
14456 GEN_INT (TCB_PLATFORM_OFFSET)));
14457 emit_move_insn (platform, tcbmem);
14458 emit_insn (gen_eqsi3 (target, platform, cpuid));
14460 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14462 const char *hwcap = TREE_STRING_POINTER (arg);
14463 rtx mask = NULL_RTX;
14465 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14466 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14468 mask = GEN_INT (cpu_supports_info[i].mask);
14469 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14472 if (mask == NULL_RTX)
14474 /* Invalid HWCAP argument. */
14475 error ("%s %qs is an invalid argument to builtin %qs",
14476 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14480 rtx tcb_hwcap = gen_reg_rtx (SImode);
14481 rtx tcbmem = gen_const_mem (SImode,
14482 gen_rtx_PLUS (Pmode,
14483 gen_rtx_REG (Pmode, TLS_REGNUM),
14484 GEN_INT (hwcap_offset)));
14485 emit_move_insn (tcb_hwcap, tcbmem);
14486 rtx scratch1 = gen_reg_rtx (SImode);
14487 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14488 rtx scratch2 = gen_reg_rtx (SImode);
14489 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14490 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14493 gcc_unreachable ();
14495 /* Record that we have expanded a CPU builtin, so that we can later
14496 emit a reference to the special symbol exported by LIBC to ensure we
14497 do not link against an old LIBC that doesn't support this feature. */
14498 cpu_builtin_p = true;
14501 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14502 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14504 /* For old LIBCs, always return FALSE. */
14505 emit_move_insn (target, GEN_INT (0));
14506 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14512 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14515 tree arg0 = CALL_EXPR_ARG (exp, 0);
14516 tree arg1 = CALL_EXPR_ARG (exp, 1);
14517 tree arg2 = CALL_EXPR_ARG (exp, 2);
14518 rtx op0 = expand_normal (arg0);
14519 rtx op1 = expand_normal (arg1);
14520 rtx op2 = expand_normal (arg2);
14521 machine_mode tmode = insn_data[icode].operand[0].mode;
14522 machine_mode mode0 = insn_data[icode].operand[1].mode;
14523 machine_mode mode1 = insn_data[icode].operand[2].mode;
14524 machine_mode mode2 = insn_data[icode].operand[3].mode;
14526 if (icode == CODE_FOR_nothing)
14527 /* Builtin not supported on this processor. */
14530 /* If we got invalid arguments bail out before generating bad rtl. */
14531 if (arg0 == error_mark_node
14532 || arg1 == error_mark_node
14533 || arg2 == error_mark_node)
14536 /* Check and prepare argument depending on the instruction code.
14538 Note that a switch statement instead of the sequence of tests
14539 would be incorrect as many of the CODE_FOR values could be
14540 CODE_FOR_nothing and that would yield multiple alternatives
14541 with identical values. We'd never reach here at runtime in
14543 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14544 || icode == CODE_FOR_altivec_vsldoi_v2df
14545 || icode == CODE_FOR_altivec_vsldoi_v4si
14546 || icode == CODE_FOR_altivec_vsldoi_v8hi
14547 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14549 /* Only allow 4-bit unsigned literals. */
14551 if (TREE_CODE (arg2) != INTEGER_CST
14552 || TREE_INT_CST_LOW (arg2) & ~0xf)
14554 error ("argument 3 must be a 4-bit unsigned literal");
14555 return CONST0_RTX (tmode);
14558 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14559 || icode == CODE_FOR_vsx_xxpermdi_v2di
14560 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14561 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14562 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14563 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14564 || icode == CODE_FOR_vsx_xxpermdi_v4si
14565 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14566 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14567 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14568 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14569 || icode == CODE_FOR_vsx_xxsldwi_v4si
14570 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14571 || icode == CODE_FOR_vsx_xxsldwi_v2di
14572 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14574 /* Only allow 2-bit unsigned literals. */
14576 if (TREE_CODE (arg2) != INTEGER_CST
14577 || TREE_INT_CST_LOW (arg2) & ~0x3)
14579 error ("argument 3 must be a 2-bit unsigned literal");
14580 return CONST0_RTX (tmode);
14583 else if (icode == CODE_FOR_vsx_set_v2df
14584 || icode == CODE_FOR_vsx_set_v2di
14585 || icode == CODE_FOR_bcdadd
14586 || icode == CODE_FOR_bcdadd_lt
14587 || icode == CODE_FOR_bcdadd_eq
14588 || icode == CODE_FOR_bcdadd_gt
14589 || icode == CODE_FOR_bcdsub
14590 || icode == CODE_FOR_bcdsub_lt
14591 || icode == CODE_FOR_bcdsub_eq
14592 || icode == CODE_FOR_bcdsub_gt)
14594 /* Only allow 1-bit unsigned literals. */
14596 if (TREE_CODE (arg2) != INTEGER_CST
14597 || TREE_INT_CST_LOW (arg2) & ~0x1)
14599 error ("argument 3 must be a 1-bit unsigned literal");
14600 return CONST0_RTX (tmode);
14603 else if (icode == CODE_FOR_dfp_ddedpd_dd
14604 || icode == CODE_FOR_dfp_ddedpd_td)
14606 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14608 if (TREE_CODE (arg0) != INTEGER_CST
14609 || TREE_INT_CST_LOW (arg2) & ~0x3)
14611 error ("argument 1 must be 0 or 2");
14612 return CONST0_RTX (tmode);
14615 else if (icode == CODE_FOR_dfp_denbcd_dd
14616 || icode == CODE_FOR_dfp_denbcd_td)
14618 /* Only allow 1-bit unsigned literals. */
14620 if (TREE_CODE (arg0) != INTEGER_CST
14621 || TREE_INT_CST_LOW (arg0) & ~0x1)
14623 error ("argument 1 must be a 1-bit unsigned literal");
14624 return CONST0_RTX (tmode);
14627 else if (icode == CODE_FOR_dfp_dscli_dd
14628 || icode == CODE_FOR_dfp_dscli_td
14629 || icode == CODE_FOR_dfp_dscri_dd
14630 || icode == CODE_FOR_dfp_dscri_td)
14632 /* Only allow 6-bit unsigned literals. */
14634 if (TREE_CODE (arg1) != INTEGER_CST
14635 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14637 error ("argument 2 must be a 6-bit unsigned literal");
14638 return CONST0_RTX (tmode);
14641 else if (icode == CODE_FOR_crypto_vshasigmaw
14642 || icode == CODE_FOR_crypto_vshasigmad)
14644 /* Check whether the 2nd and 3rd arguments are integer constants and in
14645 range and prepare arguments. */
14647 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14649 error ("argument 2 must be 0 or 1");
14650 return CONST0_RTX (tmode);
14654 if (TREE_CODE (arg2) != INTEGER_CST
14655 || wi::geu_p (wi::to_wide (arg2), 16))
14657 error ("argument 3 must be in the range 0..15");
14658 return CONST0_RTX (tmode);
14663 || GET_MODE (target) != tmode
14664 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14665 target = gen_reg_rtx (tmode);
14667 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14668 op0 = copy_to_mode_reg (mode0, op0);
14669 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14670 op1 = copy_to_mode_reg (mode1, op1);
14671 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14672 op2 = copy_to_mode_reg (mode2, op2);
14674 pat = GEN_FCN (icode) (target, op0, op1, op2);
14683 /* Expand the dst builtins. */
14685 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14688 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14689 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14690 tree arg0, arg1, arg2;
14691 machine_mode mode0, mode1;
14692 rtx pat, op0, op1, op2;
14693 const struct builtin_description *d;
14696 *expandedp = false;
14698 /* Handle DST variants. */
14700 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14701 if (d->code == fcode)
14703 arg0 = CALL_EXPR_ARG (exp, 0);
14704 arg1 = CALL_EXPR_ARG (exp, 1);
14705 arg2 = CALL_EXPR_ARG (exp, 2);
14706 op0 = expand_normal (arg0);
14707 op1 = expand_normal (arg1);
14708 op2 = expand_normal (arg2);
14709 mode0 = insn_data[d->icode].operand[0].mode;
14710 mode1 = insn_data[d->icode].operand[1].mode;
14712 /* Invalid arguments, bail out before generating bad rtl. */
14713 if (arg0 == error_mark_node
14714 || arg1 == error_mark_node
14715 || arg2 == error_mark_node)
14720 if (TREE_CODE (arg2) != INTEGER_CST
14721 || TREE_INT_CST_LOW (arg2) & ~0x3)
14723 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14727 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14728 op0 = copy_to_mode_reg (Pmode, op0);
14729 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14730 op1 = copy_to_mode_reg (mode1, op1);
14732 pat = GEN_FCN (d->icode) (op0, op1, op2);
14742 /* Expand vec_init builtin. */
14744 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14746 machine_mode tmode = TYPE_MODE (type);
14747 machine_mode inner_mode = GET_MODE_INNER (tmode);
14748 int i, n_elt = GET_MODE_NUNITS (tmode);
14750 gcc_assert (VECTOR_MODE_P (tmode));
14751 gcc_assert (n_elt == call_expr_nargs (exp));
14753 if (!target || !register_operand (target, tmode))
14754 target = gen_reg_rtx (tmode);
14756 /* If we have a vector compromised of a single element, such as V1TImode, do
14757 the initialization directly. */
14758 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14760 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14761 emit_move_insn (target, gen_lowpart (tmode, x));
14765 rtvec v = rtvec_alloc (n_elt);
14767 for (i = 0; i < n_elt; ++i)
14769 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14770 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14773 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14779 /* Return the integer constant in ARG. Constrain it to be in the range
14780 of the subparts of VEC_TYPE; issue an error if not. */
14783 get_element_number (tree vec_type, tree arg)
14785 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14787 if (!tree_fits_uhwi_p (arg)
14788 || (elt = tree_to_uhwi (arg), elt > max))
14790 error ("selector must be an integer constant in the range 0..%wi", max);
14797 /* Expand vec_set builtin. */
14799 altivec_expand_vec_set_builtin (tree exp)
14801 machine_mode tmode, mode1;
14802 tree arg0, arg1, arg2;
14806 arg0 = CALL_EXPR_ARG (exp, 0);
14807 arg1 = CALL_EXPR_ARG (exp, 1);
14808 arg2 = CALL_EXPR_ARG (exp, 2);
14810 tmode = TYPE_MODE (TREE_TYPE (arg0));
14811 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14812 gcc_assert (VECTOR_MODE_P (tmode));
14814 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14815 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14816 elt = get_element_number (TREE_TYPE (arg0), arg2);
14818 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14819 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14821 op0 = force_reg (tmode, op0);
14822 op1 = force_reg (mode1, op1);
14824 rs6000_expand_vector_set (op0, op1, elt);
14829 /* Expand vec_ext builtin. */
14831 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14833 machine_mode tmode, mode0;
14838 arg0 = CALL_EXPR_ARG (exp, 0);
14839 arg1 = CALL_EXPR_ARG (exp, 1);
14841 op0 = expand_normal (arg0);
14842 op1 = expand_normal (arg1);
14844 /* Call get_element_number to validate arg1 if it is a constant. */
14845 if (TREE_CODE (arg1) == INTEGER_CST)
14846 (void) get_element_number (TREE_TYPE (arg0), arg1);
14848 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14849 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14850 gcc_assert (VECTOR_MODE_P (mode0));
14852 op0 = force_reg (mode0, op0);
14854 if (optimize || !target || !register_operand (target, tmode))
14855 target = gen_reg_rtx (tmode);
14857 rs6000_expand_vector_extract (target, op0, op1);
14862 /* Expand the builtin in EXP and store the result in TARGET. Store
14863 true in *EXPANDEDP if we found a builtin to expand. */
14865 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14867 const struct builtin_description *d;
14869 enum insn_code icode;
14870 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14871 tree arg0, arg1, arg2;
14873 machine_mode tmode, mode0;
14874 enum rs6000_builtins fcode
14875 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14877 if (rs6000_overloaded_builtin_p (fcode))
14880 error ("unresolved overload for Altivec builtin %qF", fndecl);
14882 /* Given it is invalid, just generate a normal call. */
14883 return expand_call (exp, target, false);
14886 target = altivec_expand_dst_builtin (exp, target, expandedp);
14894 case ALTIVEC_BUILTIN_STVX_V2DF:
14895 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14896 case ALTIVEC_BUILTIN_STVX_V2DI:
14897 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14898 case ALTIVEC_BUILTIN_STVX_V4SF:
14899 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14900 case ALTIVEC_BUILTIN_STVX:
14901 case ALTIVEC_BUILTIN_STVX_V4SI:
14902 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14903 case ALTIVEC_BUILTIN_STVX_V8HI:
14904 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14905 case ALTIVEC_BUILTIN_STVX_V16QI:
14906 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14907 case ALTIVEC_BUILTIN_STVEBX:
14908 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14909 case ALTIVEC_BUILTIN_STVEHX:
14910 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14911 case ALTIVEC_BUILTIN_STVEWX:
14912 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14913 case ALTIVEC_BUILTIN_STVXL_V2DF:
14914 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14915 case ALTIVEC_BUILTIN_STVXL_V2DI:
14916 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14917 case ALTIVEC_BUILTIN_STVXL_V4SF:
14918 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14919 case ALTIVEC_BUILTIN_STVXL:
14920 case ALTIVEC_BUILTIN_STVXL_V4SI:
14921 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14922 case ALTIVEC_BUILTIN_STVXL_V8HI:
14923 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14924 case ALTIVEC_BUILTIN_STVXL_V16QI:
14925 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14927 case ALTIVEC_BUILTIN_STVLX:
14928 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14929 case ALTIVEC_BUILTIN_STVLXL:
14930 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14931 case ALTIVEC_BUILTIN_STVRX:
14932 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14933 case ALTIVEC_BUILTIN_STVRXL:
14934 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14936 case P9V_BUILTIN_STXVL:
14937 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14939 case P9V_BUILTIN_XST_LEN_R:
14940 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14942 case VSX_BUILTIN_STXVD2X_V1TI:
14943 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14944 case VSX_BUILTIN_STXVD2X_V2DF:
14945 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14946 case VSX_BUILTIN_STXVD2X_V2DI:
14947 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14948 case VSX_BUILTIN_STXVW4X_V4SF:
14949 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14950 case VSX_BUILTIN_STXVW4X_V4SI:
14951 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14952 case VSX_BUILTIN_STXVW4X_V8HI:
14953 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14954 case VSX_BUILTIN_STXVW4X_V16QI:
14955 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14957 /* For the following on big endian, it's ok to use any appropriate
14958 unaligned-supporting store, so use a generic expander. For
14959 little-endian, the exact element-reversing instruction must
14961 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14963 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14964 : CODE_FOR_vsx_st_elemrev_v1ti);
14965 return altivec_expand_stv_builtin (code, exp);
14967 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14969 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14970 : CODE_FOR_vsx_st_elemrev_v2df);
14971 return altivec_expand_stv_builtin (code, exp);
14973 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14975 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14976 : CODE_FOR_vsx_st_elemrev_v2di);
14977 return altivec_expand_stv_builtin (code, exp);
14979 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14981 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14982 : CODE_FOR_vsx_st_elemrev_v4sf);
14983 return altivec_expand_stv_builtin (code, exp);
14985 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14987 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14988 : CODE_FOR_vsx_st_elemrev_v4si);
14989 return altivec_expand_stv_builtin (code, exp);
14991 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14993 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14994 : CODE_FOR_vsx_st_elemrev_v8hi);
14995 return altivec_expand_stv_builtin (code, exp);
14997 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14999 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15000 : CODE_FOR_vsx_st_elemrev_v16qi);
15001 return altivec_expand_stv_builtin (code, exp);
15004 case ALTIVEC_BUILTIN_MFVSCR:
15005 icode = CODE_FOR_altivec_mfvscr;
15006 tmode = insn_data[icode].operand[0].mode;
15009 || GET_MODE (target) != tmode
15010 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15011 target = gen_reg_rtx (tmode);
15013 pat = GEN_FCN (icode) (target);
15019 case ALTIVEC_BUILTIN_MTVSCR:
15020 icode = CODE_FOR_altivec_mtvscr;
15021 arg0 = CALL_EXPR_ARG (exp, 0);
15022 op0 = expand_normal (arg0);
15023 mode0 = insn_data[icode].operand[0].mode;
15025 /* If we got invalid arguments bail out before generating bad rtl. */
15026 if (arg0 == error_mark_node)
15029 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15030 op0 = copy_to_mode_reg (mode0, op0);
15032 pat = GEN_FCN (icode) (op0);
15037 case ALTIVEC_BUILTIN_DSSALL:
15038 emit_insn (gen_altivec_dssall ());
15041 case ALTIVEC_BUILTIN_DSS:
15042 icode = CODE_FOR_altivec_dss;
15043 arg0 = CALL_EXPR_ARG (exp, 0);
15045 op0 = expand_normal (arg0);
15046 mode0 = insn_data[icode].operand[0].mode;
15048 /* If we got invalid arguments bail out before generating bad rtl. */
15049 if (arg0 == error_mark_node)
15052 if (TREE_CODE (arg0) != INTEGER_CST
15053 || TREE_INT_CST_LOW (arg0) & ~0x3)
15055 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15059 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15060 op0 = copy_to_mode_reg (mode0, op0);
15062 emit_insn (gen_altivec_dss (op0));
15065 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15066 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15067 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15068 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15069 case VSX_BUILTIN_VEC_INIT_V2DF:
15070 case VSX_BUILTIN_VEC_INIT_V2DI:
15071 case VSX_BUILTIN_VEC_INIT_V1TI:
15072 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15074 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15075 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15076 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15077 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15078 case VSX_BUILTIN_VEC_SET_V2DF:
15079 case VSX_BUILTIN_VEC_SET_V2DI:
15080 case VSX_BUILTIN_VEC_SET_V1TI:
15081 return altivec_expand_vec_set_builtin (exp);
15083 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15084 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15085 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15086 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15087 case VSX_BUILTIN_VEC_EXT_V2DF:
15088 case VSX_BUILTIN_VEC_EXT_V2DI:
15089 case VSX_BUILTIN_VEC_EXT_V1TI:
15090 return altivec_expand_vec_ext_builtin (exp, target);
15092 case P9V_BUILTIN_VEC_EXTRACT4B:
15093 arg1 = CALL_EXPR_ARG (exp, 1);
15096 /* Generate a normal call if it is invalid. */
15097 if (arg1 == error_mark_node)
15098 return expand_call (exp, target, false);
15100 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15102 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15103 return expand_call (exp, target, false);
15107 case P9V_BUILTIN_VEC_INSERT4B:
15108 arg2 = CALL_EXPR_ARG (exp, 2);
15111 /* Generate a normal call if it is invalid. */
15112 if (arg2 == error_mark_node)
15113 return expand_call (exp, target, false);
15115 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15117 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15118 return expand_call (exp, target, false);
15124 /* Fall through. */
15127 /* Expand abs* operations. */
15129 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15130 if (d->code == fcode)
15131 return altivec_expand_abs_builtin (d->icode, exp, target);
15133 /* Expand the AltiVec predicates. */
15134 d = bdesc_altivec_preds;
15135 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15136 if (d->code == fcode)
15137 return altivec_expand_predicate_builtin (d->icode, exp, target);
15139 /* LV* are funky. We initialized them differently. */
15142 case ALTIVEC_BUILTIN_LVSL:
15143 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15144 exp, target, false);
15145 case ALTIVEC_BUILTIN_LVSR:
15146 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15147 exp, target, false);
15148 case ALTIVEC_BUILTIN_LVEBX:
15149 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15150 exp, target, false);
15151 case ALTIVEC_BUILTIN_LVEHX:
15152 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15153 exp, target, false);
15154 case ALTIVEC_BUILTIN_LVEWX:
15155 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15156 exp, target, false);
15157 case ALTIVEC_BUILTIN_LVXL_V2DF:
15158 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15159 exp, target, false);
15160 case ALTIVEC_BUILTIN_LVXL_V2DI:
15161 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15162 exp, target, false);
15163 case ALTIVEC_BUILTIN_LVXL_V4SF:
15164 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15165 exp, target, false);
15166 case ALTIVEC_BUILTIN_LVXL:
15167 case ALTIVEC_BUILTIN_LVXL_V4SI:
15168 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15169 exp, target, false);
15170 case ALTIVEC_BUILTIN_LVXL_V8HI:
15171 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15172 exp, target, false);
15173 case ALTIVEC_BUILTIN_LVXL_V16QI:
15174 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15175 exp, target, false);
15176 case ALTIVEC_BUILTIN_LVX_V1TI:
15177 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
15178 exp, target, false);
15179 case ALTIVEC_BUILTIN_LVX_V2DF:
15180 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
15181 exp, target, false);
15182 case ALTIVEC_BUILTIN_LVX_V2DI:
15183 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
15184 exp, target, false);
15185 case ALTIVEC_BUILTIN_LVX_V4SF:
15186 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
15187 exp, target, false);
15188 case ALTIVEC_BUILTIN_LVX:
15189 case ALTIVEC_BUILTIN_LVX_V4SI:
15190 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
15191 exp, target, false);
15192 case ALTIVEC_BUILTIN_LVX_V8HI:
15193 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
15194 exp, target, false);
15195 case ALTIVEC_BUILTIN_LVX_V16QI:
15196 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
15197 exp, target, false);
15198 case ALTIVEC_BUILTIN_LVLX:
15199 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15200 exp, target, true);
15201 case ALTIVEC_BUILTIN_LVLXL:
15202 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15203 exp, target, true);
15204 case ALTIVEC_BUILTIN_LVRX:
15205 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15206 exp, target, true);
15207 case ALTIVEC_BUILTIN_LVRXL:
15208 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15209 exp, target, true);
15210 case VSX_BUILTIN_LXVD2X_V1TI:
15211 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15212 exp, target, false);
15213 case VSX_BUILTIN_LXVD2X_V2DF:
15214 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15215 exp, target, false);
15216 case VSX_BUILTIN_LXVD2X_V2DI:
15217 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15218 exp, target, false);
15219 case VSX_BUILTIN_LXVW4X_V4SF:
15220 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15221 exp, target, false);
15222 case VSX_BUILTIN_LXVW4X_V4SI:
15223 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15224 exp, target, false);
15225 case VSX_BUILTIN_LXVW4X_V8HI:
15226 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15227 exp, target, false);
15228 case VSX_BUILTIN_LXVW4X_V16QI:
15229 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15230 exp, target, false);
15231 /* For the following on big endian, it's ok to use any appropriate
15232 unaligned-supporting load, so use a generic expander. For
15233 little-endian, the exact element-reversing instruction must
15235 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15237 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15238 : CODE_FOR_vsx_ld_elemrev_v2df);
15239 return altivec_expand_lv_builtin (code, exp, target, false);
15241 case VSX_BUILTIN_LD_ELEMREV_V1TI:
15243 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
15244 : CODE_FOR_vsx_ld_elemrev_v1ti);
15245 return altivec_expand_lv_builtin (code, exp, target, false);
15247 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15249 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15250 : CODE_FOR_vsx_ld_elemrev_v2di);
15251 return altivec_expand_lv_builtin (code, exp, target, false);
15253 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15255 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15256 : CODE_FOR_vsx_ld_elemrev_v4sf);
15257 return altivec_expand_lv_builtin (code, exp, target, false);
15259 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15261 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15262 : CODE_FOR_vsx_ld_elemrev_v4si);
15263 return altivec_expand_lv_builtin (code, exp, target, false);
15265 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15267 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15268 : CODE_FOR_vsx_ld_elemrev_v8hi);
15269 return altivec_expand_lv_builtin (code, exp, target, false);
15271 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15273 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15274 : CODE_FOR_vsx_ld_elemrev_v16qi);
15275 return altivec_expand_lv_builtin (code, exp, target, false);
15280 /* Fall through. */
15283 *expandedp = false;
15287 /* Check whether a builtin function is supported in this target
15290 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
15292 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
15293 if ((fnmask & rs6000_builtin_mask) != fnmask)
15299 /* Raise an error message for a builtin function that is called without the
15300 appropriate target options being set. */
15303 rs6000_invalid_builtin (enum rs6000_builtins fncode)
15305 size_t uns_fncode = (size_t) fncode;
15306 const char *name = rs6000_builtin_info[uns_fncode].name;
15307 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
15309 gcc_assert (name != NULL);
15310 if ((fnmask & RS6000_BTM_CELL) != 0)
15311 error ("builtin function %qs is only valid for the cell processor", name);
15312 else if ((fnmask & RS6000_BTM_VSX) != 0)
15313 error ("builtin function %qs requires the %qs option", name, "-mvsx");
15314 else if ((fnmask & RS6000_BTM_HTM) != 0)
15315 error ("builtin function %qs requires the %qs option", name, "-mhtm");
15316 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
15317 error ("builtin function %qs requires the %qs option", name, "-maltivec");
15318 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15319 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15320 error ("builtin function %qs requires the %qs and %qs options",
15321 name, "-mhard-dfp", "-mpower8-vector");
15322 else if ((fnmask & RS6000_BTM_DFP) != 0)
15323 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
15324 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
15325 error ("builtin function %qs requires the %qs option", name,
15326 "-mpower8-vector");
15327 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15328 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15329 error ("builtin function %qs requires the %qs and %qs options",
15330 name, "-mcpu=power9", "-m64");
15331 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
15332 error ("builtin function %qs requires the %qs option", name,
15334 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15335 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15336 error ("builtin function %qs requires the %qs and %qs options",
15337 name, "-mcpu=power9", "-m64");
15338 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
15339 error ("builtin function %qs requires the %qs option", name,
15341 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
15343 if (!TARGET_HARD_FLOAT)
15344 error ("builtin function %qs requires the %qs option", name,
15347 error ("builtin function %qs requires the %qs option", name,
15348 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
15350 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
15351 error ("builtin function %qs requires the %qs option", name,
15353 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
15354 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15356 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
15357 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
15358 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15359 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15360 error ("builtin function %qs requires the %qs (or newer), and "
15361 "%qs or %qs options",
15362 name, "-mcpu=power7", "-m64", "-mpowerpc64");
15364 error ("builtin function %qs is not supported with the current options",
15368 /* Target hook for early folding of built-ins, shamelessly stolen
15372 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
15373 int n_args ATTRIBUTE_UNUSED,
15374 tree *args ATTRIBUTE_UNUSED,
15375 bool ignore ATTRIBUTE_UNUSED)
15377 #ifdef SUBTARGET_FOLD_BUILTIN
15378 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
15384 /* Helper function to sort out which built-ins may be valid without having
15387 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
15391 case ALTIVEC_BUILTIN_STVX_V16QI:
15392 case ALTIVEC_BUILTIN_STVX_V8HI:
15393 case ALTIVEC_BUILTIN_STVX_V4SI:
15394 case ALTIVEC_BUILTIN_STVX_V4SF:
15395 case ALTIVEC_BUILTIN_STVX_V2DI:
15396 case ALTIVEC_BUILTIN_STVX_V2DF:
15403 /* Helper function to handle the gimple folding of a vector compare
15404 operation. This sets up true/false vectors, and uses the
15405 VEC_COND_EXPR operation.
15406 CODE indicates which comparison is to be made. (EQ, GT, ...).
15407 TYPE indicates the type of the result. */
15409 fold_build_vec_cmp (tree_code code, tree type,
15410 tree arg0, tree arg1)
15412 tree cmp_type = build_same_sized_truth_vector_type (type);
15413 tree zero_vec = build_zero_cst (type);
15414 tree minus_one_vec = build_minus_one_cst (type);
15415 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
15416 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
15419 /* Helper function to handle the in-between steps for the
15420 vector compare built-ins. */
15422 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
15424 tree arg0 = gimple_call_arg (stmt, 0);
15425 tree arg1 = gimple_call_arg (stmt, 1);
15426 tree lhs = gimple_call_lhs (stmt);
15427 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
15428 gimple *g = gimple_build_assign (lhs, cmp);
15429 gimple_set_location (g, gimple_location (stmt));
15430 gsi_replace (gsi, g, true);
15433 /* Helper function to handle the vector merge[hl] built-ins. The
15434 implementation difference between h and l versions for this code are in
15435 the values used when building of the permute vector for high word versus
15436 low word merge. The variance is keyed off the use_high parameter. */
15438 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15440 tree arg0 = gimple_call_arg (stmt, 0);
15441 tree arg1 = gimple_call_arg (stmt, 1);
15442 tree lhs = gimple_call_lhs (stmt);
15443 tree lhs_type = TREE_TYPE (lhs);
15444 tree lhs_type_type = TREE_TYPE (lhs_type);
15445 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15446 int midpoint = n_elts / 2;
15452 tree_vector_builder elts (lhs_type, VECTOR_CST_NELTS (arg0), 1);
15454 for (int i = 0; i < midpoint; i++)
15456 elts.safe_push (build_int_cst (lhs_type_type, offset + i));
15457 elts.safe_push (build_int_cst (lhs_type_type, offset + n_elts + i));
15460 tree permute = elts.build ();
15462 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15463 gimple_set_location (g, gimple_location (stmt));
15464 gsi_replace (gsi, g, true);
15467 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15468 a constant, use rs6000_fold_builtin.) */
15471 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15473 gimple *stmt = gsi_stmt (*gsi);
15474 tree fndecl = gimple_call_fndecl (stmt);
15475 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15476 enum rs6000_builtins fn_code
15477 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15478 tree arg0, arg1, lhs, temp;
15481 size_t uns_fncode = (size_t) fn_code;
15482 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15483 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15484 const char *fn_name2 = (icode != CODE_FOR_nothing)
15485 ? get_insn_name ((int) icode)
15488 if (TARGET_DEBUG_BUILTIN)
15489 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15490 fn_code, fn_name1, fn_name2);
15492 if (!rs6000_fold_gimple)
15495 /* Prevent gimple folding for code that does not have a LHS, unless it is
15496 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15497 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15500 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15501 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15502 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15508 /* Flavors of vec_add. We deliberately don't expand
15509 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15510 TImode, resulting in much poorer code generation. */
15511 case ALTIVEC_BUILTIN_VADDUBM:
15512 case ALTIVEC_BUILTIN_VADDUHM:
15513 case ALTIVEC_BUILTIN_VADDUWM:
15514 case P8V_BUILTIN_VADDUDM:
15515 case ALTIVEC_BUILTIN_VADDFP:
15516 case VSX_BUILTIN_XVADDDP:
15517 arg0 = gimple_call_arg (stmt, 0);
15518 arg1 = gimple_call_arg (stmt, 1);
15519 lhs = gimple_call_lhs (stmt);
15520 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
15521 gimple_set_location (g, gimple_location (stmt));
15522 gsi_replace (gsi, g, true);
15524 /* Flavors of vec_sub. We deliberately don't expand
15525 P8V_BUILTIN_VSUBUQM. */
15526 case ALTIVEC_BUILTIN_VSUBUBM:
15527 case ALTIVEC_BUILTIN_VSUBUHM:
15528 case ALTIVEC_BUILTIN_VSUBUWM:
15529 case P8V_BUILTIN_VSUBUDM:
15530 case ALTIVEC_BUILTIN_VSUBFP:
15531 case VSX_BUILTIN_XVSUBDP:
15532 arg0 = gimple_call_arg (stmt, 0);
15533 arg1 = gimple_call_arg (stmt, 1);
15534 lhs = gimple_call_lhs (stmt);
15535 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
15536 gimple_set_location (g, gimple_location (stmt));
15537 gsi_replace (gsi, g, true);
15539 case VSX_BUILTIN_XVMULSP:
15540 case VSX_BUILTIN_XVMULDP:
15541 arg0 = gimple_call_arg (stmt, 0);
15542 arg1 = gimple_call_arg (stmt, 1);
15543 lhs = gimple_call_lhs (stmt);
15544 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15545 gimple_set_location (g, gimple_location (stmt));
15546 gsi_replace (gsi, g, true);
15548 /* Even element flavors of vec_mul (signed). */
15549 case ALTIVEC_BUILTIN_VMULESB:
15550 case ALTIVEC_BUILTIN_VMULESH:
15551 case P8V_BUILTIN_VMULESW:
15552 /* Even element flavors of vec_mul (unsigned). */
15553 case ALTIVEC_BUILTIN_VMULEUB:
15554 case ALTIVEC_BUILTIN_VMULEUH:
15555 case P8V_BUILTIN_VMULEUW:
15556 arg0 = gimple_call_arg (stmt, 0);
15557 arg1 = gimple_call_arg (stmt, 1);
15558 lhs = gimple_call_lhs (stmt);
15559 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15560 gimple_set_location (g, gimple_location (stmt));
15561 gsi_replace (gsi, g, true);
15563 /* Odd element flavors of vec_mul (signed). */
15564 case ALTIVEC_BUILTIN_VMULOSB:
15565 case ALTIVEC_BUILTIN_VMULOSH:
15566 case P8V_BUILTIN_VMULOSW:
15567 /* Odd element flavors of vec_mul (unsigned). */
15568 case ALTIVEC_BUILTIN_VMULOUB:
15569 case ALTIVEC_BUILTIN_VMULOUH:
15570 case P8V_BUILTIN_VMULOUW:
15571 arg0 = gimple_call_arg (stmt, 0);
15572 arg1 = gimple_call_arg (stmt, 1);
15573 lhs = gimple_call_lhs (stmt);
15574 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15575 gimple_set_location (g, gimple_location (stmt));
15576 gsi_replace (gsi, g, true);
15578 /* Flavors of vec_div (Integer). */
15579 case VSX_BUILTIN_DIV_V2DI:
15580 case VSX_BUILTIN_UDIV_V2DI:
15581 arg0 = gimple_call_arg (stmt, 0);
15582 arg1 = gimple_call_arg (stmt, 1);
15583 lhs = gimple_call_lhs (stmt);
15584 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15585 gimple_set_location (g, gimple_location (stmt));
15586 gsi_replace (gsi, g, true);
15588 /* Flavors of vec_div (Float). */
15589 case VSX_BUILTIN_XVDIVSP:
15590 case VSX_BUILTIN_XVDIVDP:
15591 arg0 = gimple_call_arg (stmt, 0);
15592 arg1 = gimple_call_arg (stmt, 1);
15593 lhs = gimple_call_lhs (stmt);
15594 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15595 gimple_set_location (g, gimple_location (stmt));
15596 gsi_replace (gsi, g, true);
15598 /* Flavors of vec_and. */
15599 case ALTIVEC_BUILTIN_VAND:
15600 arg0 = gimple_call_arg (stmt, 0);
15601 arg1 = gimple_call_arg (stmt, 1);
15602 lhs = gimple_call_lhs (stmt);
15603 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15604 gimple_set_location (g, gimple_location (stmt));
15605 gsi_replace (gsi, g, true);
15607 /* Flavors of vec_andc. */
15608 case ALTIVEC_BUILTIN_VANDC:
15609 arg0 = gimple_call_arg (stmt, 0);
15610 arg1 = gimple_call_arg (stmt, 1);
15611 lhs = gimple_call_lhs (stmt);
15612 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15613 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15614 gimple_set_location (g, gimple_location (stmt));
15615 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15616 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15617 gimple_set_location (g, gimple_location (stmt));
15618 gsi_replace (gsi, g, true);
15620 /* Flavors of vec_nand. */
15621 case P8V_BUILTIN_VEC_NAND:
15622 case P8V_BUILTIN_NAND_V16QI:
15623 case P8V_BUILTIN_NAND_V8HI:
15624 case P8V_BUILTIN_NAND_V4SI:
15625 case P8V_BUILTIN_NAND_V4SF:
15626 case P8V_BUILTIN_NAND_V2DF:
15627 case P8V_BUILTIN_NAND_V2DI:
15628 arg0 = gimple_call_arg (stmt, 0);
15629 arg1 = gimple_call_arg (stmt, 1);
15630 lhs = gimple_call_lhs (stmt);
15631 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15632 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15633 gimple_set_location (g, gimple_location (stmt));
15634 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15635 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15636 gimple_set_location (g, gimple_location (stmt));
15637 gsi_replace (gsi, g, true);
15639 /* Flavors of vec_or. */
15640 case ALTIVEC_BUILTIN_VOR:
15641 arg0 = gimple_call_arg (stmt, 0);
15642 arg1 = gimple_call_arg (stmt, 1);
15643 lhs = gimple_call_lhs (stmt);
15644 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15645 gimple_set_location (g, gimple_location (stmt));
15646 gsi_replace (gsi, g, true);
15648 /* flavors of vec_orc. */
15649 case P8V_BUILTIN_ORC_V16QI:
15650 case P8V_BUILTIN_ORC_V8HI:
15651 case P8V_BUILTIN_ORC_V4SI:
15652 case P8V_BUILTIN_ORC_V4SF:
15653 case P8V_BUILTIN_ORC_V2DF:
15654 case P8V_BUILTIN_ORC_V2DI:
15655 arg0 = gimple_call_arg (stmt, 0);
15656 arg1 = gimple_call_arg (stmt, 1);
15657 lhs = gimple_call_lhs (stmt);
15658 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15659 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15660 gimple_set_location (g, gimple_location (stmt));
15661 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15662 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15663 gimple_set_location (g, gimple_location (stmt));
15664 gsi_replace (gsi, g, true);
15666 /* Flavors of vec_xor. */
15667 case ALTIVEC_BUILTIN_VXOR:
15668 arg0 = gimple_call_arg (stmt, 0);
15669 arg1 = gimple_call_arg (stmt, 1);
15670 lhs = gimple_call_lhs (stmt);
15671 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15672 gimple_set_location (g, gimple_location (stmt));
15673 gsi_replace (gsi, g, true);
15675 /* Flavors of vec_nor. */
15676 case ALTIVEC_BUILTIN_VNOR:
15677 arg0 = gimple_call_arg (stmt, 0);
15678 arg1 = gimple_call_arg (stmt, 1);
15679 lhs = gimple_call_lhs (stmt);
15680 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15681 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15682 gimple_set_location (g, gimple_location (stmt));
15683 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15684 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15685 gimple_set_location (g, gimple_location (stmt));
15686 gsi_replace (gsi, g, true);
15688 /* flavors of vec_abs. */
15689 case ALTIVEC_BUILTIN_ABS_V16QI:
15690 case ALTIVEC_BUILTIN_ABS_V8HI:
15691 case ALTIVEC_BUILTIN_ABS_V4SI:
15692 case ALTIVEC_BUILTIN_ABS_V4SF:
15693 case P8V_BUILTIN_ABS_V2DI:
15694 case VSX_BUILTIN_XVABSDP:
15695 arg0 = gimple_call_arg (stmt, 0);
15696 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15697 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15699 lhs = gimple_call_lhs (stmt);
15700 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15701 gimple_set_location (g, gimple_location (stmt));
15702 gsi_replace (gsi, g, true);
15704 /* flavors of vec_min. */
15705 case VSX_BUILTIN_XVMINDP:
15706 case P8V_BUILTIN_VMINSD:
15707 case P8V_BUILTIN_VMINUD:
15708 case ALTIVEC_BUILTIN_VMINSB:
15709 case ALTIVEC_BUILTIN_VMINSH:
15710 case ALTIVEC_BUILTIN_VMINSW:
15711 case ALTIVEC_BUILTIN_VMINUB:
15712 case ALTIVEC_BUILTIN_VMINUH:
15713 case ALTIVEC_BUILTIN_VMINUW:
15714 case ALTIVEC_BUILTIN_VMINFP:
15715 arg0 = gimple_call_arg (stmt, 0);
15716 arg1 = gimple_call_arg (stmt, 1);
15717 lhs = gimple_call_lhs (stmt);
15718 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15719 gimple_set_location (g, gimple_location (stmt));
15720 gsi_replace (gsi, g, true);
15722 /* flavors of vec_max. */
15723 case VSX_BUILTIN_XVMAXDP:
15724 case P8V_BUILTIN_VMAXSD:
15725 case P8V_BUILTIN_VMAXUD:
15726 case ALTIVEC_BUILTIN_VMAXSB:
15727 case ALTIVEC_BUILTIN_VMAXSH:
15728 case ALTIVEC_BUILTIN_VMAXSW:
15729 case ALTIVEC_BUILTIN_VMAXUB:
15730 case ALTIVEC_BUILTIN_VMAXUH:
15731 case ALTIVEC_BUILTIN_VMAXUW:
15732 case ALTIVEC_BUILTIN_VMAXFP:
15733 arg0 = gimple_call_arg (stmt, 0);
15734 arg1 = gimple_call_arg (stmt, 1);
15735 lhs = gimple_call_lhs (stmt);
15736 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15737 gimple_set_location (g, gimple_location (stmt));
15738 gsi_replace (gsi, g, true);
15740 /* Flavors of vec_eqv. */
15741 case P8V_BUILTIN_EQV_V16QI:
15742 case P8V_BUILTIN_EQV_V8HI:
15743 case P8V_BUILTIN_EQV_V4SI:
15744 case P8V_BUILTIN_EQV_V4SF:
15745 case P8V_BUILTIN_EQV_V2DF:
15746 case P8V_BUILTIN_EQV_V2DI:
15747 arg0 = gimple_call_arg (stmt, 0);
15748 arg1 = gimple_call_arg (stmt, 1);
15749 lhs = gimple_call_lhs (stmt);
15750 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15751 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15752 gimple_set_location (g, gimple_location (stmt));
15753 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15754 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15755 gimple_set_location (g, gimple_location (stmt));
15756 gsi_replace (gsi, g, true);
15758 /* Flavors of vec_rotate_left. */
15759 case ALTIVEC_BUILTIN_VRLB:
15760 case ALTIVEC_BUILTIN_VRLH:
15761 case ALTIVEC_BUILTIN_VRLW:
15762 case P8V_BUILTIN_VRLD:
15763 arg0 = gimple_call_arg (stmt, 0);
15764 arg1 = gimple_call_arg (stmt, 1);
15765 lhs = gimple_call_lhs (stmt);
15766 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15767 gimple_set_location (g, gimple_location (stmt));
15768 gsi_replace (gsi, g, true);
15770 /* Flavors of vector shift right algebraic.
15771 vec_sra{b,h,w} -> vsra{b,h,w}. */
15772 case ALTIVEC_BUILTIN_VSRAB:
15773 case ALTIVEC_BUILTIN_VSRAH:
15774 case ALTIVEC_BUILTIN_VSRAW:
15775 case P8V_BUILTIN_VSRAD:
15776 arg0 = gimple_call_arg (stmt, 0);
15777 arg1 = gimple_call_arg (stmt, 1);
15778 lhs = gimple_call_lhs (stmt);
15779 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
15780 gimple_set_location (g, gimple_location (stmt));
15781 gsi_replace (gsi, g, true);
15783 /* Flavors of vector shift left.
15784 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15785 case ALTIVEC_BUILTIN_VSLB:
15786 case ALTIVEC_BUILTIN_VSLH:
15787 case ALTIVEC_BUILTIN_VSLW:
15788 case P8V_BUILTIN_VSLD:
15789 arg0 = gimple_call_arg (stmt, 0);
15790 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15791 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15793 arg1 = gimple_call_arg (stmt, 1);
15794 lhs = gimple_call_lhs (stmt);
15795 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
15796 gimple_set_location (g, gimple_location (stmt));
15797 gsi_replace (gsi, g, true);
15799 /* Flavors of vector shift right. */
15800 case ALTIVEC_BUILTIN_VSRB:
15801 case ALTIVEC_BUILTIN_VSRH:
15802 case ALTIVEC_BUILTIN_VSRW:
15803 case P8V_BUILTIN_VSRD:
15805 arg0 = gimple_call_arg (stmt, 0);
15806 arg1 = gimple_call_arg (stmt, 1);
15807 lhs = gimple_call_lhs (stmt);
15808 gimple_seq stmts = NULL;
15809 /* Convert arg0 to unsigned. */
15811 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15812 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15814 = gimple_build (&stmts, RSHIFT_EXPR,
15815 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
15816 /* Convert result back to the lhs type. */
15817 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15818 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15819 update_call_from_tree (gsi, res);
15822 /* Vector loads. */
15823 case ALTIVEC_BUILTIN_LVX_V16QI:
15824 case ALTIVEC_BUILTIN_LVX_V8HI:
15825 case ALTIVEC_BUILTIN_LVX_V4SI:
15826 case ALTIVEC_BUILTIN_LVX_V4SF:
15827 case ALTIVEC_BUILTIN_LVX_V2DI:
15828 case ALTIVEC_BUILTIN_LVX_V2DF:
15829 case ALTIVEC_BUILTIN_LVX_V1TI:
15831 arg0 = gimple_call_arg (stmt, 0); // offset
15832 arg1 = gimple_call_arg (stmt, 1); // address
15833 lhs = gimple_call_lhs (stmt);
15834 location_t loc = gimple_location (stmt);
15835 /* Since arg1 may be cast to a different type, just use ptr_type_node
15836 here instead of trying to enforce TBAA on pointer types. */
15837 tree arg1_type = ptr_type_node;
15838 tree lhs_type = TREE_TYPE (lhs);
15839 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15840 the tree using the value from arg0. The resulting type will match
15841 the type of arg1. */
15842 gimple_seq stmts = NULL;
15843 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15844 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15845 arg1_type, arg1, temp_offset);
15846 /* Mask off any lower bits from the address. */
15847 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15848 arg1_type, temp_addr,
15849 build_int_cst (arg1_type, -16));
15850 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15851 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15852 take an offset, but since we've already incorporated the offset
15853 above, here we just pass in a zero. */
15855 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15856 build_int_cst (arg1_type, 0)));
15857 gimple_set_location (g, loc);
15858 gsi_replace (gsi, g, true);
15861 /* Vector stores. */
15862 case ALTIVEC_BUILTIN_STVX_V16QI:
15863 case ALTIVEC_BUILTIN_STVX_V8HI:
15864 case ALTIVEC_BUILTIN_STVX_V4SI:
15865 case ALTIVEC_BUILTIN_STVX_V4SF:
15866 case ALTIVEC_BUILTIN_STVX_V2DI:
15867 case ALTIVEC_BUILTIN_STVX_V2DF:
15869 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15870 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15871 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15872 location_t loc = gimple_location (stmt);
15873 tree arg0_type = TREE_TYPE (arg0);
15874 /* Use ptr_type_node (no TBAA) for the arg2_type.
15875 FIXME: (Richard) "A proper fix would be to transition this type as
15876 seen from the frontend to GIMPLE, for example in a similar way we
15877 do for MEM_REFs by piggy-backing that on an extra argument, a
15878 constant zero pointer of the alias pointer type to use (which would
15879 also serve as a type indicator of the store itself). I'd use a
15880 target specific internal function for this (not sure if we can have
15881 those target specific, but I guess if it's folded away then that's
15882 fine) and get away with the overload set." */
15883 tree arg2_type = ptr_type_node;
15884 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15885 the tree using the value from arg0. The resulting type will match
15886 the type of arg2. */
15887 gimple_seq stmts = NULL;
15888 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15889 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15890 arg2_type, arg2, temp_offset);
15891 /* Mask off any lower bits from the address. */
15892 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15893 arg2_type, temp_addr,
15894 build_int_cst (arg2_type, -16));
15895 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15896 /* The desired gimple result should be similar to:
15897 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15899 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15900 build_int_cst (arg2_type, 0)), arg0);
15901 gimple_set_location (g, loc);
15902 gsi_replace (gsi, g, true);
15906 /* Vector Fused multiply-add (fma). */
15907 case ALTIVEC_BUILTIN_VMADDFP:
15908 case VSX_BUILTIN_XVMADDDP:
15909 case ALTIVEC_BUILTIN_VMLADDUHM:
15911 arg0 = gimple_call_arg (stmt, 0);
15912 arg1 = gimple_call_arg (stmt, 1);
15913 tree arg2 = gimple_call_arg (stmt, 2);
15914 lhs = gimple_call_lhs (stmt);
15915 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15916 gimple_call_set_lhs (g, lhs);
15917 gimple_call_set_nothrow (g, true);
15918 gimple_set_location (g, gimple_location (stmt));
15919 gsi_replace (gsi, g, true);
15923 /* Vector compares; EQ, NE, GE, GT, LE. */
15924 case ALTIVEC_BUILTIN_VCMPEQUB:
15925 case ALTIVEC_BUILTIN_VCMPEQUH:
15926 case ALTIVEC_BUILTIN_VCMPEQUW:
15927 case P8V_BUILTIN_VCMPEQUD:
15928 fold_compare_helper (gsi, EQ_EXPR, stmt);
15931 case P9V_BUILTIN_CMPNEB:
15932 case P9V_BUILTIN_CMPNEH:
15933 case P9V_BUILTIN_CMPNEW:
15934 fold_compare_helper (gsi, NE_EXPR, stmt);
15937 case VSX_BUILTIN_CMPGE_16QI:
15938 case VSX_BUILTIN_CMPGE_U16QI:
15939 case VSX_BUILTIN_CMPGE_8HI:
15940 case VSX_BUILTIN_CMPGE_U8HI:
15941 case VSX_BUILTIN_CMPGE_4SI:
15942 case VSX_BUILTIN_CMPGE_U4SI:
15943 case VSX_BUILTIN_CMPGE_2DI:
15944 case VSX_BUILTIN_CMPGE_U2DI:
15945 fold_compare_helper (gsi, GE_EXPR, stmt);
15948 case ALTIVEC_BUILTIN_VCMPGTSB:
15949 case ALTIVEC_BUILTIN_VCMPGTUB:
15950 case ALTIVEC_BUILTIN_VCMPGTSH:
15951 case ALTIVEC_BUILTIN_VCMPGTUH:
15952 case ALTIVEC_BUILTIN_VCMPGTSW:
15953 case ALTIVEC_BUILTIN_VCMPGTUW:
15954 case P8V_BUILTIN_VCMPGTUD:
15955 case P8V_BUILTIN_VCMPGTSD:
15956 fold_compare_helper (gsi, GT_EXPR, stmt);
15959 case VSX_BUILTIN_CMPLE_16QI:
15960 case VSX_BUILTIN_CMPLE_U16QI:
15961 case VSX_BUILTIN_CMPLE_8HI:
15962 case VSX_BUILTIN_CMPLE_U8HI:
15963 case VSX_BUILTIN_CMPLE_4SI:
15964 case VSX_BUILTIN_CMPLE_U4SI:
15965 case VSX_BUILTIN_CMPLE_2DI:
15966 case VSX_BUILTIN_CMPLE_U2DI:
15967 fold_compare_helper (gsi, LE_EXPR, stmt);
15970 /* flavors of vec_splat_[us]{8,16,32}. */
15971 case ALTIVEC_BUILTIN_VSPLTISB:
15972 case ALTIVEC_BUILTIN_VSPLTISH:
15973 case ALTIVEC_BUILTIN_VSPLTISW:
15977 if (fn_code == ALTIVEC_BUILTIN_VSPLTISB)
15979 else if (fn_code == ALTIVEC_BUILTIN_VSPLTISH)
15984 arg0 = gimple_call_arg (stmt, 0);
15985 lhs = gimple_call_lhs (stmt);
15987 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15988 5-bit signed constant in range -16 to +15. */
15989 if (TREE_CODE (arg0) != INTEGER_CST
15990 || !IN_RANGE (sext_hwi(TREE_INT_CST_LOW (arg0), size),
15993 gimple_seq stmts = NULL;
15994 location_t loc = gimple_location (stmt);
15995 tree splat_value = gimple_convert (&stmts, loc,
15996 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15997 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15998 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15999 g = gimple_build_assign (lhs, splat_tree);
16000 gimple_set_location (g, gimple_location (stmt));
16001 gsi_replace (gsi, g, true);
16005 /* vec_mergel (integrals). */
16006 case ALTIVEC_BUILTIN_VMRGLH:
16007 case ALTIVEC_BUILTIN_VMRGLW:
16008 case VSX_BUILTIN_XXMRGLW_4SI:
16009 case ALTIVEC_BUILTIN_VMRGLB:
16010 case VSX_BUILTIN_VEC_MERGEL_V2DI:
16011 fold_mergehl_helper (gsi, stmt, 1);
16013 /* vec_mergeh (integrals). */
16014 case ALTIVEC_BUILTIN_VMRGHH:
16015 case ALTIVEC_BUILTIN_VMRGHW:
16016 case VSX_BUILTIN_XXMRGHW_4SI:
16017 case ALTIVEC_BUILTIN_VMRGHB:
16018 case VSX_BUILTIN_VEC_MERGEH_V2DI:
16019 fold_mergehl_helper (gsi, stmt, 0);
16022 if (TARGET_DEBUG_BUILTIN)
16023 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16024 fn_code, fn_name1, fn_name2);
16031 /* Expand an expression EXP that calls a built-in function,
16032 with result going to TARGET if that's convenient
16033 (and in mode MODE if that's convenient).
16034 SUBTARGET may be used as the target for computing one of EXP's operands.
16035 IGNORE is nonzero if the value is to be ignored. */
16038 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16039 machine_mode mode ATTRIBUTE_UNUSED,
16040 int ignore ATTRIBUTE_UNUSED)
16042 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16043 enum rs6000_builtins fcode
16044 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16045 size_t uns_fcode = (size_t)fcode;
16046 const struct builtin_description *d;
16050 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16051 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16052 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16054 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16055 floating point type, depending on whether long double is the IBM extended
16056 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16057 we only define one variant of the built-in function, and switch the code
16058 when defining it, rather than defining two built-ins and using the
16059 overload table in rs6000-c.c to switch between the two. If we don't have
16060 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16061 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16062 #ifdef HAVE_AS_POWER9
16063 if (FLOAT128_IEEE_P (TFmode))
16069 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16070 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16071 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16072 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16073 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16074 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16075 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16076 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16077 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16078 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16079 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16080 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16081 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16085 if (TARGET_DEBUG_BUILTIN)
16087 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16088 const char *name2 = (icode != CODE_FOR_nothing)
16089 ? get_insn_name ((int) icode)
16093 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16095 default: name3 = "unknown"; break;
16096 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16097 case RS6000_BTC_UNARY: name3 = "unary"; break;
16098 case RS6000_BTC_BINARY: name3 = "binary"; break;
16099 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16100 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16101 case RS6000_BTC_ABS: name3 = "abs"; break;
16102 case RS6000_BTC_DST: name3 = "dst"; break;
16107 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16108 (name1) ? name1 : "---", fcode,
16109 (name2) ? name2 : "---", (int) icode,
16111 func_valid_p ? "" : ", not valid");
16116 rs6000_invalid_builtin (fcode);
16118 /* Given it is invalid, just generate a normal call. */
16119 return expand_call (exp, target, ignore);
16124 case RS6000_BUILTIN_RECIP:
16125 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16127 case RS6000_BUILTIN_RECIPF:
16128 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16130 case RS6000_BUILTIN_RSQRTF:
16131 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16133 case RS6000_BUILTIN_RSQRT:
16134 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16136 case POWER7_BUILTIN_BPERMD:
16137 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16138 ? CODE_FOR_bpermd_di
16139 : CODE_FOR_bpermd_si), exp, target);
16141 case RS6000_BUILTIN_GET_TB:
16142 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16145 case RS6000_BUILTIN_MFTB:
16146 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16147 ? CODE_FOR_rs6000_mftb_di
16148 : CODE_FOR_rs6000_mftb_si),
16151 case RS6000_BUILTIN_MFFS:
16152 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16154 case RS6000_BUILTIN_MTFSF:
16155 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16157 case RS6000_BUILTIN_CPU_INIT:
16158 case RS6000_BUILTIN_CPU_IS:
16159 case RS6000_BUILTIN_CPU_SUPPORTS:
16160 return cpu_expand_builtin (fcode, exp, target);
16162 case MISC_BUILTIN_SPEC_BARRIER:
16164 emit_insn (gen_rs6000_speculation_barrier ());
16168 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16169 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16171 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16172 : (int) CODE_FOR_altivec_lvsl_direct);
16173 machine_mode tmode = insn_data[icode2].operand[0].mode;
16174 machine_mode mode = insn_data[icode2].operand[1].mode;
16178 gcc_assert (TARGET_ALTIVEC);
16180 arg = CALL_EXPR_ARG (exp, 0);
16181 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16182 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16183 addr = memory_address (mode, op);
16184 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16188 /* For the load case need to negate the address. */
16189 op = gen_reg_rtx (GET_MODE (addr));
16190 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16192 op = gen_rtx_MEM (mode, op);
16195 || GET_MODE (target) != tmode
16196 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16197 target = gen_reg_rtx (tmode);
16199 pat = GEN_FCN (icode2) (target, op);
16207 case ALTIVEC_BUILTIN_VCFUX:
16208 case ALTIVEC_BUILTIN_VCFSX:
16209 case ALTIVEC_BUILTIN_VCTUXS:
16210 case ALTIVEC_BUILTIN_VCTSXS:
16211 /* FIXME: There's got to be a nicer way to handle this case than
16212 constructing a new CALL_EXPR. */
16213 if (call_expr_nargs (exp) == 1)
16215 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16216 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16220 /* For the pack and unpack int128 routines, fix up the builtin so it
16221 uses the correct IBM128 type. */
16222 case MISC_BUILTIN_PACK_IF:
16223 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16225 icode = CODE_FOR_packtf;
16226 fcode = MISC_BUILTIN_PACK_TF;
16227 uns_fcode = (size_t)fcode;
16231 case MISC_BUILTIN_UNPACK_IF:
16232 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16234 icode = CODE_FOR_unpacktf;
16235 fcode = MISC_BUILTIN_UNPACK_TF;
16236 uns_fcode = (size_t)fcode;
16244 if (TARGET_ALTIVEC)
16246 ret = altivec_expand_builtin (exp, target, &success);
16253 ret = htm_expand_builtin (exp, target, &success);
16259 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16260 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16261 gcc_assert (attr == RS6000_BTC_UNARY
16262 || attr == RS6000_BTC_BINARY
16263 || attr == RS6000_BTC_TERNARY
16264 || attr == RS6000_BTC_SPECIAL);
16266 /* Handle simple unary operations. */
16268 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16269 if (d->code == fcode)
16270 return rs6000_expand_unop_builtin (icode, exp, target);
16272 /* Handle simple binary operations. */
16274 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16275 if (d->code == fcode)
16276 return rs6000_expand_binop_builtin (icode, exp, target);
16278 /* Handle simple ternary operations. */
16280 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16281 if (d->code == fcode)
16282 return rs6000_expand_ternop_builtin (icode, exp, target);
16284 /* Handle simple no-argument operations. */
16286 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16287 if (d->code == fcode)
16288 return rs6000_expand_zeroop_builtin (icode, target);
16290 gcc_unreachable ();
16293 /* Create a builtin vector type with a name. Taking care not to give
16294 the canonical type a name. */
16297 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16299 tree result = build_vector_type (elt_type, num_elts);
16301 /* Copy so we don't give the canonical type a name. */
16302 result = build_variant_type_copy (result);
16304 add_builtin_type (name, result);
16310 rs6000_init_builtins (void)
16316 if (TARGET_DEBUG_BUILTIN)
16317 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16318 (TARGET_ALTIVEC) ? ", altivec" : "",
16319 (TARGET_VSX) ? ", vsx" : "");
16321 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16322 : "__vector long long",
16323 intDI_type_node, 2);
16324 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16325 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16326 intSI_type_node, 4);
16327 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16328 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16329 intHI_type_node, 8);
16330 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16331 intQI_type_node, 16);
16333 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16334 unsigned_intQI_type_node, 16);
16335 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16336 unsigned_intHI_type_node, 8);
16337 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16338 unsigned_intSI_type_node, 4);
16339 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16340 ? "__vector unsigned long"
16341 : "__vector unsigned long long",
16342 unsigned_intDI_type_node, 2);
16344 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16346 const_str_type_node
16347 = build_pointer_type (build_qualified_type (char_type_node,
16350 /* We use V1TI mode as a special container to hold __int128_t items that
16351 must live in VSX registers. */
16352 if (intTI_type_node)
16354 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16355 intTI_type_node, 1);
16356 unsigned_V1TI_type_node
16357 = rs6000_vector_type ("__vector unsigned __int128",
16358 unsigned_intTI_type_node, 1);
16361 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16362 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16363 'vector unsigned short'. */
16365 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16366 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16367 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16368 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16369 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16371 long_integer_type_internal_node = long_integer_type_node;
16372 long_unsigned_type_internal_node = long_unsigned_type_node;
16373 long_long_integer_type_internal_node = long_long_integer_type_node;
16374 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16375 intQI_type_internal_node = intQI_type_node;
16376 uintQI_type_internal_node = unsigned_intQI_type_node;
16377 intHI_type_internal_node = intHI_type_node;
16378 uintHI_type_internal_node = unsigned_intHI_type_node;
16379 intSI_type_internal_node = intSI_type_node;
16380 uintSI_type_internal_node = unsigned_intSI_type_node;
16381 intDI_type_internal_node = intDI_type_node;
16382 uintDI_type_internal_node = unsigned_intDI_type_node;
16383 intTI_type_internal_node = intTI_type_node;
16384 uintTI_type_internal_node = unsigned_intTI_type_node;
16385 float_type_internal_node = float_type_node;
16386 double_type_internal_node = double_type_node;
16387 long_double_type_internal_node = long_double_type_node;
16388 dfloat64_type_internal_node = dfloat64_type_node;
16389 dfloat128_type_internal_node = dfloat128_type_node;
16390 void_type_internal_node = void_type_node;
16392 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16393 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16394 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16395 format that uses a pair of doubles, depending on the switches and
16398 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16399 floating point, we need make sure the type is non-zero or else self-test
16400 fails during bootstrap.
16402 Always create __ibm128 as a separate type, even if the current long double
16403 format is IBM extended double.
16405 For IEEE 128-bit floating point, always create the type __ieee128. If the
16406 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16408 if (TARGET_FLOAT128_TYPE)
16410 if (TARGET_IEEEQUAD || !TARGET_LONG_DOUBLE_128)
16412 ibm128_float_type_node = make_node (REAL_TYPE);
16413 TYPE_PRECISION (ibm128_float_type_node) = 128;
16414 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16415 layout_type (ibm128_float_type_node);
16418 ibm128_float_type_node = long_double_type_node;
16420 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16423 ieee128_float_type_node
16424 = TARGET_IEEEQUAD ? long_double_type_node : float128_type_node;
16425 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16430 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16432 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16434 builtin_mode_to_type[QImode][0] = integer_type_node;
16435 builtin_mode_to_type[HImode][0] = integer_type_node;
16436 builtin_mode_to_type[SImode][0] = intSI_type_node;
16437 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16438 builtin_mode_to_type[DImode][0] = intDI_type_node;
16439 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16440 builtin_mode_to_type[TImode][0] = intTI_type_node;
16441 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16442 builtin_mode_to_type[SFmode][0] = float_type_node;
16443 builtin_mode_to_type[DFmode][0] = double_type_node;
16444 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16445 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16446 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16447 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16448 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16449 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16450 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16451 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16452 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16453 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16454 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16455 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16456 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16457 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16458 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16459 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16460 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16462 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16463 TYPE_NAME (bool_char_type_node) = tdecl;
16465 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16466 TYPE_NAME (bool_short_type_node) = tdecl;
16468 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16469 TYPE_NAME (bool_int_type_node) = tdecl;
16471 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16472 TYPE_NAME (pixel_type_node) = tdecl;
16474 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16475 bool_char_type_node, 16);
16476 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16477 bool_short_type_node, 8);
16478 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16479 bool_int_type_node, 4);
16480 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16481 ? "__vector __bool long"
16482 : "__vector __bool long long",
16483 bool_long_long_type_node, 2);
16484 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16485 pixel_type_node, 8);
16487 /* Create Altivec and VSX builtins on machines with at least the
16488 general purpose extensions (970 and newer) to allow the use of
16489 the target attribute. */
16490 if (TARGET_EXTRA_BUILTINS)
16491 altivec_init_builtins ();
16493 htm_init_builtins ();
16495 if (TARGET_EXTRA_BUILTINS)
16496 rs6000_common_init_builtins ();
16498 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16499 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16500 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16502 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16503 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16504 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16506 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16507 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16508 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16510 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16511 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16512 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16514 mode = (TARGET_64BIT) ? DImode : SImode;
16515 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16516 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16517 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16519 ftype = build_function_type_list (unsigned_intDI_type_node,
16521 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16524 ftype = build_function_type_list (unsigned_intDI_type_node,
16527 ftype = build_function_type_list (unsigned_intSI_type_node,
16529 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16531 ftype = build_function_type_list (double_type_node, NULL_TREE);
16532 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16534 ftype = build_function_type_list (void_type_node,
16535 intSI_type_node, double_type_node,
16537 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16539 ftype = build_function_type_list (void_type_node, NULL_TREE);
16540 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16541 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16542 MISC_BUILTIN_SPEC_BARRIER);
16544 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16546 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16547 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16549 /* AIX libm provides clog as __clog. */
16550 if (TARGET_XCOFF &&
16551 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16552 set_user_assembler_name (tdecl, "__clog");
16554 #ifdef SUBTARGET_INIT_BUILTINS
16555 SUBTARGET_INIT_BUILTINS;
16559 /* Returns the rs6000 builtin decl for CODE. */
16562 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16564 HOST_WIDE_INT fnmask;
16566 if (code >= RS6000_BUILTIN_COUNT)
16567 return error_mark_node;
16569 fnmask = rs6000_builtin_info[code].mask;
16570 if ((fnmask & rs6000_builtin_mask) != fnmask)
16572 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16573 return error_mark_node;
16576 return rs6000_builtin_decls[code];
16580 altivec_init_builtins (void)
16582 const struct builtin_description *d;
16586 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16588 tree pvoid_type_node = build_pointer_type (void_type_node);
16590 tree pcvoid_type_node
16591 = build_pointer_type (build_qualified_type (void_type_node,
16594 tree int_ftype_opaque
16595 = build_function_type_list (integer_type_node,
16596 opaque_V4SI_type_node, NULL_TREE);
16597 tree opaque_ftype_opaque
16598 = build_function_type_list (integer_type_node, NULL_TREE);
16599 tree opaque_ftype_opaque_int
16600 = build_function_type_list (opaque_V4SI_type_node,
16601 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16602 tree opaque_ftype_opaque_opaque_int
16603 = build_function_type_list (opaque_V4SI_type_node,
16604 opaque_V4SI_type_node, opaque_V4SI_type_node,
16605 integer_type_node, NULL_TREE);
16606 tree opaque_ftype_opaque_opaque_opaque
16607 = build_function_type_list (opaque_V4SI_type_node,
16608 opaque_V4SI_type_node, opaque_V4SI_type_node,
16609 opaque_V4SI_type_node, NULL_TREE);
16610 tree opaque_ftype_opaque_opaque
16611 = build_function_type_list (opaque_V4SI_type_node,
16612 opaque_V4SI_type_node, opaque_V4SI_type_node,
16614 tree int_ftype_int_opaque_opaque
16615 = build_function_type_list (integer_type_node,
16616 integer_type_node, opaque_V4SI_type_node,
16617 opaque_V4SI_type_node, NULL_TREE);
16618 tree int_ftype_int_v4si_v4si
16619 = build_function_type_list (integer_type_node,
16620 integer_type_node, V4SI_type_node,
16621 V4SI_type_node, NULL_TREE);
16622 tree int_ftype_int_v2di_v2di
16623 = build_function_type_list (integer_type_node,
16624 integer_type_node, V2DI_type_node,
16625 V2DI_type_node, NULL_TREE);
16626 tree void_ftype_v4si
16627 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16628 tree v8hi_ftype_void
16629 = build_function_type_list (V8HI_type_node, NULL_TREE);
16630 tree void_ftype_void
16631 = build_function_type_list (void_type_node, NULL_TREE);
16632 tree void_ftype_int
16633 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16635 tree opaque_ftype_long_pcvoid
16636 = build_function_type_list (opaque_V4SI_type_node,
16637 long_integer_type_node, pcvoid_type_node,
16639 tree v16qi_ftype_long_pcvoid
16640 = build_function_type_list (V16QI_type_node,
16641 long_integer_type_node, pcvoid_type_node,
16643 tree v8hi_ftype_long_pcvoid
16644 = build_function_type_list (V8HI_type_node,
16645 long_integer_type_node, pcvoid_type_node,
16647 tree v4si_ftype_long_pcvoid
16648 = build_function_type_list (V4SI_type_node,
16649 long_integer_type_node, pcvoid_type_node,
16651 tree v4sf_ftype_long_pcvoid
16652 = build_function_type_list (V4SF_type_node,
16653 long_integer_type_node, pcvoid_type_node,
16655 tree v2df_ftype_long_pcvoid
16656 = build_function_type_list (V2DF_type_node,
16657 long_integer_type_node, pcvoid_type_node,
16659 tree v2di_ftype_long_pcvoid
16660 = build_function_type_list (V2DI_type_node,
16661 long_integer_type_node, pcvoid_type_node,
16663 tree v1ti_ftype_long_pcvoid
16664 = build_function_type_list (V1TI_type_node,
16665 long_integer_type_node, pcvoid_type_node,
16668 tree void_ftype_opaque_long_pvoid
16669 = build_function_type_list (void_type_node,
16670 opaque_V4SI_type_node, long_integer_type_node,
16671 pvoid_type_node, NULL_TREE);
16672 tree void_ftype_v4si_long_pvoid
16673 = build_function_type_list (void_type_node,
16674 V4SI_type_node, long_integer_type_node,
16675 pvoid_type_node, NULL_TREE);
16676 tree void_ftype_v16qi_long_pvoid
16677 = build_function_type_list (void_type_node,
16678 V16QI_type_node, long_integer_type_node,
16679 pvoid_type_node, NULL_TREE);
16681 tree void_ftype_v16qi_pvoid_long
16682 = build_function_type_list (void_type_node,
16683 V16QI_type_node, pvoid_type_node,
16684 long_integer_type_node, NULL_TREE);
16686 tree void_ftype_v8hi_long_pvoid
16687 = build_function_type_list (void_type_node,
16688 V8HI_type_node, long_integer_type_node,
16689 pvoid_type_node, NULL_TREE);
16690 tree void_ftype_v4sf_long_pvoid
16691 = build_function_type_list (void_type_node,
16692 V4SF_type_node, long_integer_type_node,
16693 pvoid_type_node, NULL_TREE);
16694 tree void_ftype_v2df_long_pvoid
16695 = build_function_type_list (void_type_node,
16696 V2DF_type_node, long_integer_type_node,
16697 pvoid_type_node, NULL_TREE);
16698 tree void_ftype_v1ti_long_pvoid
16699 = build_function_type_list (void_type_node,
16700 V1TI_type_node, long_integer_type_node,
16701 pvoid_type_node, NULL_TREE);
16702 tree void_ftype_v2di_long_pvoid
16703 = build_function_type_list (void_type_node,
16704 V2DI_type_node, long_integer_type_node,
16705 pvoid_type_node, NULL_TREE);
16706 tree int_ftype_int_v8hi_v8hi
16707 = build_function_type_list (integer_type_node,
16708 integer_type_node, V8HI_type_node,
16709 V8HI_type_node, NULL_TREE);
16710 tree int_ftype_int_v16qi_v16qi
16711 = build_function_type_list (integer_type_node,
16712 integer_type_node, V16QI_type_node,
16713 V16QI_type_node, NULL_TREE);
16714 tree int_ftype_int_v4sf_v4sf
16715 = build_function_type_list (integer_type_node,
16716 integer_type_node, V4SF_type_node,
16717 V4SF_type_node, NULL_TREE);
16718 tree int_ftype_int_v2df_v2df
16719 = build_function_type_list (integer_type_node,
16720 integer_type_node, V2DF_type_node,
16721 V2DF_type_node, NULL_TREE);
16722 tree v2di_ftype_v2di
16723 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16724 tree v4si_ftype_v4si
16725 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16726 tree v8hi_ftype_v8hi
16727 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16728 tree v16qi_ftype_v16qi
16729 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16730 tree v4sf_ftype_v4sf
16731 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16732 tree v2df_ftype_v2df
16733 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16734 tree void_ftype_pcvoid_int_int
16735 = build_function_type_list (void_type_node,
16736 pcvoid_type_node, integer_type_node,
16737 integer_type_node, NULL_TREE);
16739 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16740 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16741 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16742 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16743 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16744 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16745 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16746 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16747 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16748 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16749 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16750 ALTIVEC_BUILTIN_LVXL_V2DF);
16751 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16752 ALTIVEC_BUILTIN_LVXL_V2DI);
16753 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16754 ALTIVEC_BUILTIN_LVXL_V4SF);
16755 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16756 ALTIVEC_BUILTIN_LVXL_V4SI);
16757 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16758 ALTIVEC_BUILTIN_LVXL_V8HI);
16759 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16760 ALTIVEC_BUILTIN_LVXL_V16QI);
16761 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16762 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16763 ALTIVEC_BUILTIN_LVX_V1TI);
16764 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16765 ALTIVEC_BUILTIN_LVX_V2DF);
16766 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16767 ALTIVEC_BUILTIN_LVX_V2DI);
16768 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16769 ALTIVEC_BUILTIN_LVX_V4SF);
16770 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16771 ALTIVEC_BUILTIN_LVX_V4SI);
16772 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16773 ALTIVEC_BUILTIN_LVX_V8HI);
16774 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16775 ALTIVEC_BUILTIN_LVX_V16QI);
16776 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16777 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16778 ALTIVEC_BUILTIN_STVX_V2DF);
16779 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16780 ALTIVEC_BUILTIN_STVX_V2DI);
16781 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16782 ALTIVEC_BUILTIN_STVX_V4SF);
16783 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16784 ALTIVEC_BUILTIN_STVX_V4SI);
16785 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16786 ALTIVEC_BUILTIN_STVX_V8HI);
16787 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16788 ALTIVEC_BUILTIN_STVX_V16QI);
16789 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16790 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16791 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16792 ALTIVEC_BUILTIN_STVXL_V2DF);
16793 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16794 ALTIVEC_BUILTIN_STVXL_V2DI);
16795 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16796 ALTIVEC_BUILTIN_STVXL_V4SF);
16797 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16798 ALTIVEC_BUILTIN_STVXL_V4SI);
16799 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16800 ALTIVEC_BUILTIN_STVXL_V8HI);
16801 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16802 ALTIVEC_BUILTIN_STVXL_V16QI);
16803 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16804 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16805 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16806 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16807 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16808 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16809 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16810 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16811 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16812 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16813 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16814 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16815 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16816 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16817 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16818 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16820 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16821 VSX_BUILTIN_LXVD2X_V2DF);
16822 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16823 VSX_BUILTIN_LXVD2X_V2DI);
16824 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16825 VSX_BUILTIN_LXVW4X_V4SF);
16826 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16827 VSX_BUILTIN_LXVW4X_V4SI);
16828 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16829 VSX_BUILTIN_LXVW4X_V8HI);
16830 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16831 VSX_BUILTIN_LXVW4X_V16QI);
16832 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16833 VSX_BUILTIN_STXVD2X_V2DF);
16834 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16835 VSX_BUILTIN_STXVD2X_V2DI);
16836 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16837 VSX_BUILTIN_STXVW4X_V4SF);
16838 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16839 VSX_BUILTIN_STXVW4X_V4SI);
16840 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16841 VSX_BUILTIN_STXVW4X_V8HI);
16842 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16843 VSX_BUILTIN_STXVW4X_V16QI);
16845 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16846 VSX_BUILTIN_LD_ELEMREV_V2DF);
16847 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16848 VSX_BUILTIN_LD_ELEMREV_V2DI);
16849 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16850 VSX_BUILTIN_LD_ELEMREV_V4SF);
16851 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16852 VSX_BUILTIN_LD_ELEMREV_V4SI);
16853 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16854 VSX_BUILTIN_LD_ELEMREV_V8HI);
16855 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16856 VSX_BUILTIN_LD_ELEMREV_V16QI);
16857 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16858 VSX_BUILTIN_ST_ELEMREV_V2DF);
16859 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16860 VSX_BUILTIN_ST_ELEMREV_V1TI);
16861 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16862 VSX_BUILTIN_ST_ELEMREV_V2DI);
16863 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16864 VSX_BUILTIN_ST_ELEMREV_V4SF);
16865 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16866 VSX_BUILTIN_ST_ELEMREV_V4SI);
16867 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16868 VSX_BUILTIN_ST_ELEMREV_V8HI);
16869 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16870 VSX_BUILTIN_ST_ELEMREV_V16QI);
16872 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16873 VSX_BUILTIN_VEC_LD);
16874 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16875 VSX_BUILTIN_VEC_ST);
16876 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16877 VSX_BUILTIN_VEC_XL);
16878 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16879 VSX_BUILTIN_VEC_XL_BE);
16880 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16881 VSX_BUILTIN_VEC_XST);
16882 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16883 VSX_BUILTIN_VEC_XST_BE);
16885 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16886 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16887 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16889 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16890 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16891 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16892 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16893 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16894 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16895 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16896 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16897 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16898 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16899 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16900 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16902 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16903 ALTIVEC_BUILTIN_VEC_ADDE);
16904 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16905 ALTIVEC_BUILTIN_VEC_ADDEC);
16906 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16907 ALTIVEC_BUILTIN_VEC_CMPNE);
16908 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16909 ALTIVEC_BUILTIN_VEC_MUL);
16910 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16911 ALTIVEC_BUILTIN_VEC_SUBE);
16912 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16913 ALTIVEC_BUILTIN_VEC_SUBEC);
16915 /* Cell builtins. */
16916 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16917 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16918 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16919 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16921 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16922 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16923 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16924 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16926 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16927 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16928 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16929 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16931 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16932 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16933 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16934 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16936 if (TARGET_P9_VECTOR)
16938 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16939 P9V_BUILTIN_STXVL);
16940 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16941 P9V_BUILTIN_XST_LEN_R);
16944 /* Add the DST variants. */
16946 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16948 HOST_WIDE_INT mask = d->mask;
16950 /* It is expected that these dst built-in functions may have
16951 d->icode equal to CODE_FOR_nothing. */
16952 if ((mask & builtin_mask) != mask)
16954 if (TARGET_DEBUG_BUILTIN)
16955 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16959 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16962 /* Initialize the predicates. */
16963 d = bdesc_altivec_preds;
16964 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16966 machine_mode mode1;
16968 HOST_WIDE_INT mask = d->mask;
16970 if ((mask & builtin_mask) != mask)
16972 if (TARGET_DEBUG_BUILTIN)
16973 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16978 if (rs6000_overloaded_builtin_p (d->code))
16982 /* Cannot define builtin if the instruction is disabled. */
16983 gcc_assert (d->icode != CODE_FOR_nothing);
16984 mode1 = insn_data[d->icode].operand[1].mode;
16990 type = int_ftype_int_opaque_opaque;
16993 type = int_ftype_int_v2di_v2di;
16996 type = int_ftype_int_v4si_v4si;
16999 type = int_ftype_int_v8hi_v8hi;
17002 type = int_ftype_int_v16qi_v16qi;
17005 type = int_ftype_int_v4sf_v4sf;
17008 type = int_ftype_int_v2df_v2df;
17011 gcc_unreachable ();
17014 def_builtin (d->name, type, d->code);
17017 /* Initialize the abs* operators. */
17019 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17021 machine_mode mode0;
17023 HOST_WIDE_INT mask = d->mask;
17025 if ((mask & builtin_mask) != mask)
17027 if (TARGET_DEBUG_BUILTIN)
17028 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17033 /* Cannot define builtin if the instruction is disabled. */
17034 gcc_assert (d->icode != CODE_FOR_nothing);
17035 mode0 = insn_data[d->icode].operand[0].mode;
17040 type = v2di_ftype_v2di;
17043 type = v4si_ftype_v4si;
17046 type = v8hi_ftype_v8hi;
17049 type = v16qi_ftype_v16qi;
17052 type = v4sf_ftype_v4sf;
17055 type = v2df_ftype_v2df;
17058 gcc_unreachable ();
17061 def_builtin (d->name, type, d->code);
17064 /* Initialize target builtin that implements
17065 targetm.vectorize.builtin_mask_for_load. */
17067 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17068 v16qi_ftype_long_pcvoid,
17069 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17070 BUILT_IN_MD, NULL, NULL_TREE);
17071 TREE_READONLY (decl) = 1;
17072 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17073 altivec_builtin_mask_for_load = decl;
17075 /* Access to the vec_init patterns. */
17076 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17077 integer_type_node, integer_type_node,
17078 integer_type_node, NULL_TREE);
17079 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17081 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17082 short_integer_type_node,
17083 short_integer_type_node,
17084 short_integer_type_node,
17085 short_integer_type_node,
17086 short_integer_type_node,
17087 short_integer_type_node,
17088 short_integer_type_node, NULL_TREE);
17089 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17091 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17092 char_type_node, char_type_node,
17093 char_type_node, char_type_node,
17094 char_type_node, char_type_node,
17095 char_type_node, char_type_node,
17096 char_type_node, char_type_node,
17097 char_type_node, char_type_node,
17098 char_type_node, char_type_node,
17099 char_type_node, NULL_TREE);
17100 def_builtin ("__builtin_vec_init_v16qi", ftype,
17101 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17103 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17104 float_type_node, float_type_node,
17105 float_type_node, NULL_TREE);
17106 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17108 /* VSX builtins. */
17109 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17110 double_type_node, NULL_TREE);
17111 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17113 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17114 intDI_type_node, NULL_TREE);
17115 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17117 /* Access to the vec_set patterns. */
17118 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17120 integer_type_node, NULL_TREE);
17121 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17123 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17125 integer_type_node, NULL_TREE);
17126 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17128 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17130 integer_type_node, NULL_TREE);
17131 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17133 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17135 integer_type_node, NULL_TREE);
17136 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17138 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17140 integer_type_node, NULL_TREE);
17141 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17143 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17145 integer_type_node, NULL_TREE);
17146 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17148 /* Access to the vec_extract patterns. */
17149 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17150 integer_type_node, NULL_TREE);
17151 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17153 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17154 integer_type_node, NULL_TREE);
17155 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17157 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17158 integer_type_node, NULL_TREE);
17159 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17161 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17162 integer_type_node, NULL_TREE);
17163 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17165 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17166 integer_type_node, NULL_TREE);
17167 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17169 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17170 integer_type_node, NULL_TREE);
17171 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17174 if (V1TI_type_node)
17176 tree v1ti_ftype_long_pcvoid
17177 = build_function_type_list (V1TI_type_node,
17178 long_integer_type_node, pcvoid_type_node,
17180 tree void_ftype_v1ti_long_pvoid
17181 = build_function_type_list (void_type_node,
17182 V1TI_type_node, long_integer_type_node,
17183 pvoid_type_node, NULL_TREE);
17184 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17185 VSX_BUILTIN_LD_ELEMREV_V1TI);
17186 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17187 VSX_BUILTIN_LXVD2X_V1TI);
17188 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17189 VSX_BUILTIN_STXVD2X_V1TI);
17190 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17191 NULL_TREE, NULL_TREE);
17192 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17193 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17195 integer_type_node, NULL_TREE);
17196 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17197 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17198 integer_type_node, NULL_TREE);
17199 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17205 htm_init_builtins (void)
17207 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17208 const struct builtin_description *d;
17212 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17214 tree op[MAX_HTM_OPERANDS], type;
17215 HOST_WIDE_INT mask = d->mask;
17216 unsigned attr = rs6000_builtin_info[d->code].attr;
17217 bool void_func = (attr & RS6000_BTC_VOID);
17218 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17220 tree gpr_type_node;
17224 /* It is expected that these htm built-in functions may have
17225 d->icode equal to CODE_FOR_nothing. */
17227 if (TARGET_32BIT && TARGET_POWERPC64)
17228 gpr_type_node = long_long_unsigned_type_node;
17230 gpr_type_node = long_unsigned_type_node;
17232 if (attr & RS6000_BTC_SPR)
17234 rettype = gpr_type_node;
17235 argtype = gpr_type_node;
17237 else if (d->code == HTM_BUILTIN_TABORTDC
17238 || d->code == HTM_BUILTIN_TABORTDCI)
17240 rettype = unsigned_type_node;
17241 argtype = gpr_type_node;
17245 rettype = unsigned_type_node;
17246 argtype = unsigned_type_node;
17249 if ((mask & builtin_mask) != mask)
17251 if (TARGET_DEBUG_BUILTIN)
17252 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17258 if (TARGET_DEBUG_BUILTIN)
17259 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17260 (long unsigned) i);
17264 op[nopnds++] = (void_func) ? void_type_node : rettype;
17266 if (attr_args == RS6000_BTC_UNARY)
17267 op[nopnds++] = argtype;
17268 else if (attr_args == RS6000_BTC_BINARY)
17270 op[nopnds++] = argtype;
17271 op[nopnds++] = argtype;
17273 else if (attr_args == RS6000_BTC_TERNARY)
17275 op[nopnds++] = argtype;
17276 op[nopnds++] = argtype;
17277 op[nopnds++] = argtype;
17283 type = build_function_type_list (op[0], NULL_TREE);
17286 type = build_function_type_list (op[0], op[1], NULL_TREE);
17289 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17292 type = build_function_type_list (op[0], op[1], op[2], op[3],
17296 gcc_unreachable ();
17299 def_builtin (d->name, type, d->code);
17303 /* Hash function for builtin functions with up to 3 arguments and a return
17306 builtin_hasher::hash (builtin_hash_struct *bh)
17311 for (i = 0; i < 4; i++)
17313 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17314 ret = (ret * 2) + bh->uns_p[i];
17320 /* Compare builtin hash entries H1 and H2 for equivalence. */
17322 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17324 return ((p1->mode[0] == p2->mode[0])
17325 && (p1->mode[1] == p2->mode[1])
17326 && (p1->mode[2] == p2->mode[2])
17327 && (p1->mode[3] == p2->mode[3])
17328 && (p1->uns_p[0] == p2->uns_p[0])
17329 && (p1->uns_p[1] == p2->uns_p[1])
17330 && (p1->uns_p[2] == p2->uns_p[2])
17331 && (p1->uns_p[3] == p2->uns_p[3]));
17334 /* Map types for builtin functions with an explicit return type and up to 3
17335 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17336 of the argument. */
17338 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17339 machine_mode mode_arg1, machine_mode mode_arg2,
17340 enum rs6000_builtins builtin, const char *name)
17342 struct builtin_hash_struct h;
17343 struct builtin_hash_struct *h2;
17346 tree ret_type = NULL_TREE;
17347 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17349 /* Create builtin_hash_table. */
17350 if (builtin_hash_table == NULL)
17351 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17353 h.type = NULL_TREE;
17354 h.mode[0] = mode_ret;
17355 h.mode[1] = mode_arg0;
17356 h.mode[2] = mode_arg1;
17357 h.mode[3] = mode_arg2;
17363 /* If the builtin is a type that produces unsigned results or takes unsigned
17364 arguments, and it is returned as a decl for the vectorizer (such as
17365 widening multiplies, permute), make sure the arguments and return value
17366 are type correct. */
17369 /* unsigned 1 argument functions. */
17370 case CRYPTO_BUILTIN_VSBOX:
17371 case P8V_BUILTIN_VGBBD:
17372 case MISC_BUILTIN_CDTBCD:
17373 case MISC_BUILTIN_CBCDTD:
17378 /* unsigned 2 argument functions. */
17379 case ALTIVEC_BUILTIN_VMULEUB:
17380 case ALTIVEC_BUILTIN_VMULEUH:
17381 case P8V_BUILTIN_VMULEUW:
17382 case ALTIVEC_BUILTIN_VMULOUB:
17383 case ALTIVEC_BUILTIN_VMULOUH:
17384 case P8V_BUILTIN_VMULOUW:
17385 case CRYPTO_BUILTIN_VCIPHER:
17386 case CRYPTO_BUILTIN_VCIPHERLAST:
17387 case CRYPTO_BUILTIN_VNCIPHER:
17388 case CRYPTO_BUILTIN_VNCIPHERLAST:
17389 case CRYPTO_BUILTIN_VPMSUMB:
17390 case CRYPTO_BUILTIN_VPMSUMH:
17391 case CRYPTO_BUILTIN_VPMSUMW:
17392 case CRYPTO_BUILTIN_VPMSUMD:
17393 case CRYPTO_BUILTIN_VPMSUM:
17394 case MISC_BUILTIN_ADDG6S:
17395 case MISC_BUILTIN_DIVWEU:
17396 case MISC_BUILTIN_DIVDEU:
17397 case VSX_BUILTIN_UDIV_V2DI:
17398 case ALTIVEC_BUILTIN_VMAXUB:
17399 case ALTIVEC_BUILTIN_VMINUB:
17400 case ALTIVEC_BUILTIN_VMAXUH:
17401 case ALTIVEC_BUILTIN_VMINUH:
17402 case ALTIVEC_BUILTIN_VMAXUW:
17403 case ALTIVEC_BUILTIN_VMINUW:
17404 case P8V_BUILTIN_VMAXUD:
17405 case P8V_BUILTIN_VMINUD:
17411 /* unsigned 3 argument functions. */
17412 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17413 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17414 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17415 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17416 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17417 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17418 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17419 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17420 case VSX_BUILTIN_VPERM_16QI_UNS:
17421 case VSX_BUILTIN_VPERM_8HI_UNS:
17422 case VSX_BUILTIN_VPERM_4SI_UNS:
17423 case VSX_BUILTIN_VPERM_2DI_UNS:
17424 case VSX_BUILTIN_XXSEL_16QI_UNS:
17425 case VSX_BUILTIN_XXSEL_8HI_UNS:
17426 case VSX_BUILTIN_XXSEL_4SI_UNS:
17427 case VSX_BUILTIN_XXSEL_2DI_UNS:
17428 case CRYPTO_BUILTIN_VPERMXOR:
17429 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17430 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17431 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17432 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17433 case CRYPTO_BUILTIN_VSHASIGMAW:
17434 case CRYPTO_BUILTIN_VSHASIGMAD:
17435 case CRYPTO_BUILTIN_VSHASIGMA:
17442 /* signed permute functions with unsigned char mask. */
17443 case ALTIVEC_BUILTIN_VPERM_16QI:
17444 case ALTIVEC_BUILTIN_VPERM_8HI:
17445 case ALTIVEC_BUILTIN_VPERM_4SI:
17446 case ALTIVEC_BUILTIN_VPERM_4SF:
17447 case ALTIVEC_BUILTIN_VPERM_2DI:
17448 case ALTIVEC_BUILTIN_VPERM_2DF:
17449 case VSX_BUILTIN_VPERM_16QI:
17450 case VSX_BUILTIN_VPERM_8HI:
17451 case VSX_BUILTIN_VPERM_4SI:
17452 case VSX_BUILTIN_VPERM_4SF:
17453 case VSX_BUILTIN_VPERM_2DI:
17454 case VSX_BUILTIN_VPERM_2DF:
17458 /* unsigned args, signed return. */
17459 case VSX_BUILTIN_XVCVUXDSP:
17460 case VSX_BUILTIN_XVCVUXDDP_UNS:
17461 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17465 /* signed args, unsigned return. */
17466 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17467 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17468 case MISC_BUILTIN_UNPACK_TD:
17469 case MISC_BUILTIN_UNPACK_V1TI:
17473 /* unsigned arguments, bool return (compares). */
17474 case ALTIVEC_BUILTIN_VCMPEQUB:
17475 case ALTIVEC_BUILTIN_VCMPEQUH:
17476 case ALTIVEC_BUILTIN_VCMPEQUW:
17477 case P8V_BUILTIN_VCMPEQUD:
17478 case VSX_BUILTIN_CMPGE_U16QI:
17479 case VSX_BUILTIN_CMPGE_U8HI:
17480 case VSX_BUILTIN_CMPGE_U4SI:
17481 case VSX_BUILTIN_CMPGE_U2DI:
17482 case ALTIVEC_BUILTIN_VCMPGTUB:
17483 case ALTIVEC_BUILTIN_VCMPGTUH:
17484 case ALTIVEC_BUILTIN_VCMPGTUW:
17485 case P8V_BUILTIN_VCMPGTUD:
17490 /* unsigned arguments for 128-bit pack instructions. */
17491 case MISC_BUILTIN_PACK_TD:
17492 case MISC_BUILTIN_PACK_V1TI:
17497 /* unsigned second arguments (vector shift right). */
17498 case ALTIVEC_BUILTIN_VSRB:
17499 case ALTIVEC_BUILTIN_VSRH:
17500 case ALTIVEC_BUILTIN_VSRW:
17501 case P8V_BUILTIN_VSRD:
17509 /* Figure out how many args are present. */
17510 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17513 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17514 if (!ret_type && h.uns_p[0])
17515 ret_type = builtin_mode_to_type[h.mode[0]][0];
17518 fatal_error (input_location,
17519 "internal error: builtin function %qs had an unexpected "
17520 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17522 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17523 arg_type[i] = NULL_TREE;
17525 for (i = 0; i < num_args; i++)
17527 int m = (int) h.mode[i+1];
17528 int uns_p = h.uns_p[i+1];
17530 arg_type[i] = builtin_mode_to_type[m][uns_p];
17531 if (!arg_type[i] && uns_p)
17532 arg_type[i] = builtin_mode_to_type[m][0];
17535 fatal_error (input_location,
17536 "internal error: builtin function %qs, argument %d "
17537 "had unexpected argument type %qs", name, i,
17538 GET_MODE_NAME (m));
17541 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17542 if (*found == NULL)
17544 h2 = ggc_alloc<builtin_hash_struct> ();
17548 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17549 arg_type[2], NULL_TREE);
17552 return (*found)->type;
17556 rs6000_common_init_builtins (void)
17558 const struct builtin_description *d;
17561 tree opaque_ftype_opaque = NULL_TREE;
17562 tree opaque_ftype_opaque_opaque = NULL_TREE;
17563 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17564 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17566 /* Create Altivec and VSX builtins on machines with at least the
17567 general purpose extensions (970 and newer) to allow the use of
17568 the target attribute. */
17570 if (TARGET_EXTRA_BUILTINS)
17571 builtin_mask |= RS6000_BTM_COMMON;
17573 /* Add the ternary operators. */
17575 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17578 HOST_WIDE_INT mask = d->mask;
17580 if ((mask & builtin_mask) != mask)
17582 if (TARGET_DEBUG_BUILTIN)
17583 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17587 if (rs6000_overloaded_builtin_p (d->code))
17589 if (! (type = opaque_ftype_opaque_opaque_opaque))
17590 type = opaque_ftype_opaque_opaque_opaque
17591 = build_function_type_list (opaque_V4SI_type_node,
17592 opaque_V4SI_type_node,
17593 opaque_V4SI_type_node,
17594 opaque_V4SI_type_node,
17599 enum insn_code icode = d->icode;
17602 if (TARGET_DEBUG_BUILTIN)
17603 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17609 if (icode == CODE_FOR_nothing)
17611 if (TARGET_DEBUG_BUILTIN)
17612 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17618 type = builtin_function_type (insn_data[icode].operand[0].mode,
17619 insn_data[icode].operand[1].mode,
17620 insn_data[icode].operand[2].mode,
17621 insn_data[icode].operand[3].mode,
17625 def_builtin (d->name, type, d->code);
17628 /* Add the binary operators. */
17630 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17632 machine_mode mode0, mode1, mode2;
17634 HOST_WIDE_INT mask = d->mask;
17636 if ((mask & builtin_mask) != mask)
17638 if (TARGET_DEBUG_BUILTIN)
17639 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17643 if (rs6000_overloaded_builtin_p (d->code))
17645 if (! (type = opaque_ftype_opaque_opaque))
17646 type = opaque_ftype_opaque_opaque
17647 = build_function_type_list (opaque_V4SI_type_node,
17648 opaque_V4SI_type_node,
17649 opaque_V4SI_type_node,
17654 enum insn_code icode = d->icode;
17657 if (TARGET_DEBUG_BUILTIN)
17658 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17664 if (icode == CODE_FOR_nothing)
17666 if (TARGET_DEBUG_BUILTIN)
17667 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17673 mode0 = insn_data[icode].operand[0].mode;
17674 mode1 = insn_data[icode].operand[1].mode;
17675 mode2 = insn_data[icode].operand[2].mode;
17677 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17681 def_builtin (d->name, type, d->code);
17684 /* Add the simple unary operators. */
17686 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17688 machine_mode mode0, mode1;
17690 HOST_WIDE_INT mask = d->mask;
17692 if ((mask & builtin_mask) != mask)
17694 if (TARGET_DEBUG_BUILTIN)
17695 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17699 if (rs6000_overloaded_builtin_p (d->code))
17701 if (! (type = opaque_ftype_opaque))
17702 type = opaque_ftype_opaque
17703 = build_function_type_list (opaque_V4SI_type_node,
17704 opaque_V4SI_type_node,
17709 enum insn_code icode = d->icode;
17712 if (TARGET_DEBUG_BUILTIN)
17713 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17719 if (icode == CODE_FOR_nothing)
17721 if (TARGET_DEBUG_BUILTIN)
17722 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17728 mode0 = insn_data[icode].operand[0].mode;
17729 mode1 = insn_data[icode].operand[1].mode;
17731 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17735 def_builtin (d->name, type, d->code);
17738 /* Add the simple no-argument operators. */
17740 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17742 machine_mode mode0;
17744 HOST_WIDE_INT mask = d->mask;
17746 if ((mask & builtin_mask) != mask)
17748 if (TARGET_DEBUG_BUILTIN)
17749 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17752 if (rs6000_overloaded_builtin_p (d->code))
17754 if (!opaque_ftype_opaque)
17755 opaque_ftype_opaque
17756 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17757 type = opaque_ftype_opaque;
17761 enum insn_code icode = d->icode;
17764 if (TARGET_DEBUG_BUILTIN)
17765 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17766 (long unsigned) i);
17769 if (icode == CODE_FOR_nothing)
17771 if (TARGET_DEBUG_BUILTIN)
17773 "rs6000_builtin, skip no-argument %s (no code)\n",
17777 mode0 = insn_data[icode].operand[0].mode;
17778 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17781 def_builtin (d->name, type, d->code);
17785 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17787 init_float128_ibm (machine_mode mode)
17789 if (!TARGET_XL_COMPAT)
17791 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17792 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17793 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17794 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17796 if (!TARGET_HARD_FLOAT)
17798 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17799 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17800 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17801 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17802 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17803 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17804 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17805 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17807 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17808 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17809 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17810 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17811 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17812 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17813 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17814 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17819 set_optab_libfunc (add_optab, mode, "_xlqadd");
17820 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17821 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17822 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17825 /* Add various conversions for IFmode to use the traditional TFmode
17827 if (mode == IFmode)
17829 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
17830 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
17831 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
17832 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
17833 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
17834 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
17836 if (TARGET_POWERPC64)
17838 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17839 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17840 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17841 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17846 /* Create a decl for either complex long double multiply or complex long double
17847 divide when long double is IEEE 128-bit floating point. We can't use
17848 __multc3 and __divtc3 because the original long double using IBM extended
17849 double used those names. The complex multiply/divide functions are encoded
17850 as builtin functions with a complex result and 4 scalar inputs. */
17853 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17855 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17858 set_builtin_decl (fncode, fndecl, true);
17860 if (TARGET_DEBUG_BUILTIN)
17861 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17866 /* Set up IEEE 128-bit floating point routines. Use different names if the
17867 arguments can be passed in a vector register. The historical PowerPC
17868 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17869 continue to use that if we aren't using vector registers to pass IEEE
17870 128-bit floating point. */
17873 init_float128_ieee (machine_mode mode)
17875 if (FLOAT128_VECTOR_P (mode))
17877 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. */
17878 if (mode == TFmode && TARGET_IEEEQUAD)
17880 built_in_function fncode_mul =
17881 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17882 - MIN_MODE_COMPLEX_FLOAT);
17883 built_in_function fncode_div =
17884 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17885 - MIN_MODE_COMPLEX_FLOAT);
17887 tree fntype = build_function_type_list (complex_long_double_type_node,
17888 long_double_type_node,
17889 long_double_type_node,
17890 long_double_type_node,
17891 long_double_type_node,
17894 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17895 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17898 set_optab_libfunc (add_optab, mode, "__addkf3");
17899 set_optab_libfunc (sub_optab, mode, "__subkf3");
17900 set_optab_libfunc (neg_optab, mode, "__negkf2");
17901 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17902 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17903 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17904 set_optab_libfunc (abs_optab, mode, "__abskf2");
17905 set_optab_libfunc (powi_optab, mode, "__powikf2");
17907 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17908 set_optab_libfunc (ne_optab, mode, "__nekf2");
17909 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17910 set_optab_libfunc (ge_optab, mode, "__gekf2");
17911 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17912 set_optab_libfunc (le_optab, mode, "__lekf2");
17913 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17915 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17916 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17917 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17918 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17920 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17921 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17922 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17924 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17925 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17926 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17928 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
17929 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
17930 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
17931 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
17932 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
17933 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
17935 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17936 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17937 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17938 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17940 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17941 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17942 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17943 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17945 if (TARGET_POWERPC64)
17947 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17948 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17949 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17950 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17956 set_optab_libfunc (add_optab, mode, "_q_add");
17957 set_optab_libfunc (sub_optab, mode, "_q_sub");
17958 set_optab_libfunc (neg_optab, mode, "_q_neg");
17959 set_optab_libfunc (smul_optab, mode, "_q_mul");
17960 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17961 if (TARGET_PPC_GPOPT)
17962 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17964 set_optab_libfunc (eq_optab, mode, "_q_feq");
17965 set_optab_libfunc (ne_optab, mode, "_q_fne");
17966 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17967 set_optab_libfunc (ge_optab, mode, "_q_fge");
17968 set_optab_libfunc (lt_optab, mode, "_q_flt");
17969 set_optab_libfunc (le_optab, mode, "_q_fle");
17971 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17972 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17973 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17974 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17975 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17976 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17977 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17978 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17983 rs6000_init_libfuncs (void)
17985 /* __float128 support. */
17986 if (TARGET_FLOAT128_TYPE)
17988 init_float128_ibm (IFmode);
17989 init_float128_ieee (KFmode);
17992 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17993 if (TARGET_LONG_DOUBLE_128)
17995 if (!TARGET_IEEEQUAD)
17996 init_float128_ibm (TFmode);
17998 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18000 init_float128_ieee (TFmode);
18004 /* Emit a potentially record-form instruction, setting DST from SRC.
18005 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18006 signed comparison of DST with zero. If DOT is 1, the generated RTL
18007 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18008 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18009 a separate COMPARE. */
18012 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18016 emit_move_insn (dst, src);
18020 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18022 emit_move_insn (dst, src);
18023 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18027 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18030 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18031 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18035 rtx set = gen_rtx_SET (dst, src);
18036 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18041 /* A validation routine: say whether CODE, a condition code, and MODE
18042 match. The other alternatives either don't make sense or should
18043 never be generated. */
18046 validate_condition_mode (enum rtx_code code, machine_mode mode)
18048 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18049 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18050 && GET_MODE_CLASS (mode) == MODE_CC);
18052 /* These don't make sense. */
18053 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18054 || mode != CCUNSmode);
18056 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18057 || mode == CCUNSmode);
18059 gcc_assert (mode == CCFPmode
18060 || (code != ORDERED && code != UNORDERED
18061 && code != UNEQ && code != LTGT
18062 && code != UNGT && code != UNLT
18063 && code != UNGE && code != UNLE));
18065 /* These should never be generated except for
18066 flag_finite_math_only. */
18067 gcc_assert (mode != CCFPmode
18068 || flag_finite_math_only
18069 || (code != LE && code != GE
18070 && code != UNEQ && code != LTGT
18071 && code != UNGT && code != UNLT));
18073 /* These are invalid; the information is not there. */
18074 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18078 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18079 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18080 not zero, store there the bit offset (counted from the right) where
18081 the single stretch of 1 bits begins; and similarly for B, the bit
18082 offset where it ends. */
18085 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18087 unsigned HOST_WIDE_INT val = INTVAL (mask);
18088 unsigned HOST_WIDE_INT bit;
18090 int n = GET_MODE_PRECISION (mode);
18092 if (mode != DImode && mode != SImode)
18095 if (INTVAL (mask) >= 0)
18098 ne = exact_log2 (bit);
18099 nb = exact_log2 (val + bit);
18101 else if (val + 1 == 0)
18110 nb = exact_log2 (bit);
18111 ne = exact_log2 (val + bit);
18116 ne = exact_log2 (bit);
18117 if (val + bit == 0)
18125 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18136 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18137 or rldicr instruction, to implement an AND with it in mode MODE. */
18140 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18144 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18147 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18149 if (mode == DImode)
18150 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18152 /* For SImode, rlwinm can do everything. */
18153 if (mode == SImode)
18154 return (nb < 32 && ne < 32);
18159 /* Return the instruction template for an AND with mask in mode MODE, with
18160 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18163 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18167 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18168 gcc_unreachable ();
18170 if (mode == DImode && ne == 0)
18172 operands[3] = GEN_INT (63 - nb);
18174 return "rldicl. %0,%1,0,%3";
18175 return "rldicl %0,%1,0,%3";
18178 if (mode == DImode && nb == 63)
18180 operands[3] = GEN_INT (63 - ne);
18182 return "rldicr. %0,%1,0,%3";
18183 return "rldicr %0,%1,0,%3";
18186 if (nb < 32 && ne < 32)
18188 operands[3] = GEN_INT (31 - nb);
18189 operands[4] = GEN_INT (31 - ne);
18191 return "rlwinm. %0,%1,0,%3,%4";
18192 return "rlwinm %0,%1,0,%3,%4";
18195 gcc_unreachable ();
18198 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18199 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18200 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18203 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18207 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18210 int n = GET_MODE_PRECISION (mode);
18213 if (CONST_INT_P (XEXP (shift, 1)))
18215 sh = INTVAL (XEXP (shift, 1));
18216 if (sh < 0 || sh >= n)
18220 rtx_code code = GET_CODE (shift);
18222 /* Convert any shift by 0 to a rotate, to simplify below code. */
18226 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18227 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18229 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18235 /* DImode rotates need rld*. */
18236 if (mode == DImode && code == ROTATE)
18237 return (nb == 63 || ne == 0 || ne == sh);
18239 /* SImode rotates need rlw*. */
18240 if (mode == SImode && code == ROTATE)
18241 return (nb < 32 && ne < 32 && sh < 32);
18243 /* Wrap-around masks are only okay for rotates. */
18247 /* Variable shifts are only okay for rotates. */
18251 /* Don't allow ASHIFT if the mask is wrong for that. */
18252 if (code == ASHIFT && ne < sh)
18255 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18256 if the mask is wrong for that. */
18257 if (nb < 32 && ne < 32 && sh < 32
18258 && !(code == LSHIFTRT && nb >= 32 - sh))
18261 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18262 if the mask is wrong for that. */
18263 if (code == LSHIFTRT)
18265 if (nb == 63 || ne == 0 || ne == sh)
18266 return !(code == LSHIFTRT && nb >= sh);
18271 /* Return the instruction template for a shift with mask in mode MODE, with
18272 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18275 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18279 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18280 gcc_unreachable ();
18282 if (mode == DImode && ne == 0)
18284 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18285 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18286 operands[3] = GEN_INT (63 - nb);
18288 return "rld%I2cl. %0,%1,%2,%3";
18289 return "rld%I2cl %0,%1,%2,%3";
18292 if (mode == DImode && nb == 63)
18294 operands[3] = GEN_INT (63 - ne);
18296 return "rld%I2cr. %0,%1,%2,%3";
18297 return "rld%I2cr %0,%1,%2,%3";
18301 && GET_CODE (operands[4]) != LSHIFTRT
18302 && CONST_INT_P (operands[2])
18303 && ne == INTVAL (operands[2]))
18305 operands[3] = GEN_INT (63 - nb);
18307 return "rld%I2c. %0,%1,%2,%3";
18308 return "rld%I2c %0,%1,%2,%3";
18311 if (nb < 32 && ne < 32)
18313 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18314 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18315 operands[3] = GEN_INT (31 - nb);
18316 operands[4] = GEN_INT (31 - ne);
18317 /* This insn can also be a 64-bit rotate with mask that really makes
18318 it just a shift right (with mask); the %h below are to adjust for
18319 that situation (shift count is >= 32 in that case). */
18321 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18322 return "rlw%I2nm %0,%1,%h2,%3,%4";
18325 gcc_unreachable ();
18328 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18329 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18330 ASHIFT, or LSHIFTRT) in mode MODE. */
18333 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18337 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18340 int n = GET_MODE_PRECISION (mode);
18342 int sh = INTVAL (XEXP (shift, 1));
18343 if (sh < 0 || sh >= n)
18346 rtx_code code = GET_CODE (shift);
18348 /* Convert any shift by 0 to a rotate, to simplify below code. */
18352 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18353 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18355 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18361 /* DImode rotates need rldimi. */
18362 if (mode == DImode && code == ROTATE)
18365 /* SImode rotates need rlwimi. */
18366 if (mode == SImode && code == ROTATE)
18367 return (nb < 32 && ne < 32 && sh < 32);
18369 /* Wrap-around masks are only okay for rotates. */
18373 /* Don't allow ASHIFT if the mask is wrong for that. */
18374 if (code == ASHIFT && ne < sh)
18377 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18378 if the mask is wrong for that. */
18379 if (nb < 32 && ne < 32 && sh < 32
18380 && !(code == LSHIFTRT && nb >= 32 - sh))
18383 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18384 if the mask is wrong for that. */
18385 if (code == LSHIFTRT)
18388 return !(code == LSHIFTRT && nb >= sh);
18393 /* Return the instruction template for an insert with mask in mode MODE, with
18394 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18397 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18401 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18402 gcc_unreachable ();
18404 /* Prefer rldimi because rlwimi is cracked. */
18405 if (TARGET_POWERPC64
18406 && (!dot || mode == DImode)
18407 && GET_CODE (operands[4]) != LSHIFTRT
18408 && ne == INTVAL (operands[2]))
18410 operands[3] = GEN_INT (63 - nb);
18412 return "rldimi. %0,%1,%2,%3";
18413 return "rldimi %0,%1,%2,%3";
18416 if (nb < 32 && ne < 32)
18418 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18419 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18420 operands[3] = GEN_INT (31 - nb);
18421 operands[4] = GEN_INT (31 - ne);
18423 return "rlwimi. %0,%1,%2,%3,%4";
18424 return "rlwimi %0,%1,%2,%3,%4";
18427 gcc_unreachable ();
18430 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18431 using two machine instructions. */
18434 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18436 /* There are two kinds of AND we can handle with two insns:
18437 1) those we can do with two rl* insn;
18440 We do not handle that last case yet. */
18442 /* If there is just one stretch of ones, we can do it. */
18443 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18446 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18447 one insn, we can do the whole thing with two. */
18448 unsigned HOST_WIDE_INT val = INTVAL (c);
18449 unsigned HOST_WIDE_INT bit1 = val & -val;
18450 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18451 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18452 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18453 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18456 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18457 If EXPAND is true, split rotate-and-mask instructions we generate to
18458 their constituent parts as well (this is used during expand); if DOT
18459 is 1, make the last insn a record-form instruction clobbering the
18460 destination GPR and setting the CC reg (from operands[3]); if 2, set
18461 that GPR as well as the CC reg. */
18464 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18466 gcc_assert (!(expand && dot));
18468 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18470 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18471 shift right. This generates better code than doing the masks without
18472 shifts, or shifting first right and then left. */
18474 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18476 gcc_assert (mode == DImode);
18478 int shift = 63 - nb;
18481 rtx tmp1 = gen_reg_rtx (DImode);
18482 rtx tmp2 = gen_reg_rtx (DImode);
18483 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18484 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18485 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18489 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18490 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18491 emit_move_insn (operands[0], tmp);
18492 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18493 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18498 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18499 that does the rest. */
18500 unsigned HOST_WIDE_INT bit1 = val & -val;
18501 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18502 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18503 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18505 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18506 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18508 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18510 /* Two "no-rotate"-and-mask instructions, for SImode. */
18511 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18513 gcc_assert (mode == SImode);
18515 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18516 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18517 emit_move_insn (reg, tmp);
18518 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18519 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18523 gcc_assert (mode == DImode);
18525 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18526 insns; we have to do the first in SImode, because it wraps. */
18527 if (mask2 <= 0xffffffff
18528 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18530 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18531 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18533 rtx reg_low = gen_lowpart (SImode, reg);
18534 emit_move_insn (reg_low, tmp);
18535 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18536 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18540 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18541 at the top end), rotate back and clear the other hole. */
18542 int right = exact_log2 (bit3);
18543 int left = 64 - right;
18545 /* Rotate the mask too. */
18546 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18550 rtx tmp1 = gen_reg_rtx (DImode);
18551 rtx tmp2 = gen_reg_rtx (DImode);
18552 rtx tmp3 = gen_reg_rtx (DImode);
18553 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18554 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18555 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18556 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18560 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18561 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18562 emit_move_insn (operands[0], tmp);
18563 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18564 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18565 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18569 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18570 for lfq and stfq insns iff the registers are hard registers. */
18573 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18575 /* We might have been passed a SUBREG. */
18576 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
18579 /* We might have been passed non floating point registers. */
18580 if (!FP_REGNO_P (REGNO (reg1))
18581 || !FP_REGNO_P (REGNO (reg2)))
18584 return (REGNO (reg1) == REGNO (reg2) - 1);
18587 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18588 addr1 and addr2 must be in consecutive memory locations
18589 (addr2 == addr1 + 8). */
18592 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18595 unsigned int reg1, reg2;
18596 int offset1, offset2;
18598 /* The mems cannot be volatile. */
18599 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18602 addr1 = XEXP (mem1, 0);
18603 addr2 = XEXP (mem2, 0);
18605 /* Extract an offset (if used) from the first addr. */
18606 if (GET_CODE (addr1) == PLUS)
18608 /* If not a REG, return zero. */
18609 if (GET_CODE (XEXP (addr1, 0)) != REG)
18613 reg1 = REGNO (XEXP (addr1, 0));
18614 /* The offset must be constant! */
18615 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
18617 offset1 = INTVAL (XEXP (addr1, 1));
18620 else if (GET_CODE (addr1) != REG)
18624 reg1 = REGNO (addr1);
18625 /* This was a simple (mem (reg)) expression. Offset is 0. */
18629 /* And now for the second addr. */
18630 if (GET_CODE (addr2) == PLUS)
18632 /* If not a REG, return zero. */
18633 if (GET_CODE (XEXP (addr2, 0)) != REG)
18637 reg2 = REGNO (XEXP (addr2, 0));
18638 /* The offset must be constant. */
18639 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
18641 offset2 = INTVAL (XEXP (addr2, 1));
18644 else if (GET_CODE (addr2) != REG)
18648 reg2 = REGNO (addr2);
18649 /* This was a simple (mem (reg)) expression. Offset is 0. */
18653 /* Both of these must have the same base register. */
18657 /* The offset for the second addr must be 8 more than the first addr. */
18658 if (offset2 != offset1 + 8)
18661 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18666 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18667 need to use DDmode, in all other cases we can use the same mode. */
18668 static machine_mode
18669 rs6000_secondary_memory_needed_mode (machine_mode mode)
18671 if (lra_in_progress && mode == SDmode)
18676 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18677 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18678 only work on the traditional altivec registers, note if an altivec register
18681 static enum rs6000_reg_type
18682 register_to_reg_type (rtx reg, bool *is_altivec)
18684 HOST_WIDE_INT regno;
18685 enum reg_class rclass;
18687 if (GET_CODE (reg) == SUBREG)
18688 reg = SUBREG_REG (reg);
18691 return NO_REG_TYPE;
18693 regno = REGNO (reg);
18694 if (regno >= FIRST_PSEUDO_REGISTER)
18696 if (!lra_in_progress && !reload_completed)
18697 return PSEUDO_REG_TYPE;
18699 regno = true_regnum (reg);
18700 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
18701 return PSEUDO_REG_TYPE;
18704 gcc_assert (regno >= 0);
18706 if (is_altivec && ALTIVEC_REGNO_P (regno))
18707 *is_altivec = true;
18709 rclass = rs6000_regno_regclass[regno];
18710 return reg_class_to_reg_type[(int)rclass];
18713 /* Helper function to return the cost of adding a TOC entry address. */
18716 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18720 if (TARGET_CMODEL != CMODEL_SMALL)
18721 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18724 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18729 /* Helper function for rs6000_secondary_reload to determine whether the memory
18730 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18731 needs reloading. Return negative if the memory is not handled by the memory
18732 helper functions and to try a different reload method, 0 if no additional
18733 instructions are need, and positive to give the extra cost for the
18737 rs6000_secondary_reload_memory (rtx addr,
18738 enum reg_class rclass,
18741 int extra_cost = 0;
18742 rtx reg, and_arg, plus_arg0, plus_arg1;
18743 addr_mask_type addr_mask;
18744 const char *type = NULL;
18745 const char *fail_msg = NULL;
18747 if (GPR_REG_CLASS_P (rclass))
18748 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18750 else if (rclass == FLOAT_REGS)
18751 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18753 else if (rclass == ALTIVEC_REGS)
18754 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18756 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18757 else if (rclass == VSX_REGS)
18758 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18759 & ~RELOAD_REG_AND_M16);
18761 /* If the register allocator hasn't made up its mind yet on the register
18762 class to use, settle on defaults to use. */
18763 else if (rclass == NO_REGS)
18765 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18766 & ~RELOAD_REG_AND_M16);
18768 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18769 addr_mask &= ~(RELOAD_REG_INDEXED
18770 | RELOAD_REG_PRE_INCDEC
18771 | RELOAD_REG_PRE_MODIFY);
18777 /* If the register isn't valid in this register class, just return now. */
18778 if ((addr_mask & RELOAD_REG_VALID) == 0)
18780 if (TARGET_DEBUG_ADDR)
18783 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18784 "not valid in class\n",
18785 GET_MODE_NAME (mode), reg_class_names[rclass]);
18792 switch (GET_CODE (addr))
18794 /* Does the register class supports auto update forms for this mode? We
18795 don't need a scratch register, since the powerpc only supports
18796 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18799 reg = XEXP (addr, 0);
18800 if (!base_reg_operand (addr, GET_MODE (reg)))
18802 fail_msg = "no base register #1";
18806 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18814 reg = XEXP (addr, 0);
18815 plus_arg1 = XEXP (addr, 1);
18816 if (!base_reg_operand (reg, GET_MODE (reg))
18817 || GET_CODE (plus_arg1) != PLUS
18818 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18820 fail_msg = "bad PRE_MODIFY";
18824 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18831 /* Do we need to simulate AND -16 to clear the bottom address bits used
18832 in VMX load/stores? Only allow the AND for vector sizes. */
18834 and_arg = XEXP (addr, 0);
18835 if (GET_MODE_SIZE (mode) != 16
18836 || GET_CODE (XEXP (addr, 1)) != CONST_INT
18837 || INTVAL (XEXP (addr, 1)) != -16)
18839 fail_msg = "bad Altivec AND #1";
18843 if (rclass != ALTIVEC_REGS)
18845 if (legitimate_indirect_address_p (and_arg, false))
18848 else if (legitimate_indexed_address_p (and_arg, false))
18853 fail_msg = "bad Altivec AND #2";
18861 /* If this is an indirect address, make sure it is a base register. */
18864 if (!legitimate_indirect_address_p (addr, false))
18871 /* If this is an indexed address, make sure the register class can handle
18872 indexed addresses for this mode. */
18874 plus_arg0 = XEXP (addr, 0);
18875 plus_arg1 = XEXP (addr, 1);
18877 /* (plus (plus (reg) (constant)) (constant)) is generated during
18878 push_reload processing, so handle it now. */
18879 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18881 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18888 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18889 push_reload processing, so handle it now. */
18890 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18892 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18895 type = "indexed #2";
18899 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18901 fail_msg = "no base register #2";
18905 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18907 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18908 || !legitimate_indexed_address_p (addr, false))
18915 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18916 && CONST_INT_P (plus_arg1))
18918 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18921 type = "vector d-form offset";
18925 /* Make sure the register class can handle offset addresses. */
18926 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18928 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18931 type = "offset #2";
18937 fail_msg = "bad PLUS";
18944 /* Quad offsets are restricted and can't handle normal addresses. */
18945 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18948 type = "vector d-form lo_sum";
18951 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18953 fail_msg = "bad LO_SUM";
18957 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18964 /* Static addresses need to create a TOC entry. */
18968 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18971 type = "vector d-form lo_sum #2";
18977 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18981 /* TOC references look like offsetable memory. */
18983 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18985 fail_msg = "bad UNSPEC";
18989 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18992 type = "vector d-form lo_sum #3";
18995 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18998 type = "toc reference";
19004 fail_msg = "bad address";
19009 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19011 if (extra_cost < 0)
19013 "rs6000_secondary_reload_memory error: mode = %s, "
19014 "class = %s, addr_mask = '%s', %s\n",
19015 GET_MODE_NAME (mode),
19016 reg_class_names[rclass],
19017 rs6000_debug_addr_mask (addr_mask, false),
19018 (fail_msg != NULL) ? fail_msg : "<bad address>");
19022 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19023 "addr_mask = '%s', extra cost = %d, %s\n",
19024 GET_MODE_NAME (mode),
19025 reg_class_names[rclass],
19026 rs6000_debug_addr_mask (addr_mask, false),
19028 (type) ? type : "<none>");
19036 /* Helper function for rs6000_secondary_reload to return true if a move to a
19037 different register classe is really a simple move. */
19040 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19041 enum rs6000_reg_type from_type,
19044 int size = GET_MODE_SIZE (mode);
19046 /* Add support for various direct moves available. In this function, we only
19047 look at cases where we don't need any extra registers, and one or more
19048 simple move insns are issued. Originally small integers are not allowed
19049 in FPR/VSX registers. Single precision binary floating is not a simple
19050 move because we need to convert to the single precision memory layout.
19051 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19052 need special direct move handling, which we do not support yet. */
19053 if (TARGET_DIRECT_MOVE
19054 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19055 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19057 if (TARGET_POWERPC64)
19059 /* ISA 2.07: MTVSRD or MVFVSRD. */
19063 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19064 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19068 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19069 if (TARGET_P8_VECTOR)
19071 if (mode == SImode)
19074 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19078 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19079 if (mode == SDmode)
19083 /* Power6+: MFTGPR or MFFGPR. */
19084 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19085 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19086 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19089 /* Move to/from SPR. */
19090 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19091 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19092 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19098 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19099 special direct moves that involve allocating an extra register, return the
19100 insn code of the helper function if there is such a function or
19101 CODE_FOR_nothing if not. */
19104 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19105 enum rs6000_reg_type from_type,
19107 secondary_reload_info *sri,
19111 enum insn_code icode = CODE_FOR_nothing;
19113 int size = GET_MODE_SIZE (mode);
19115 if (TARGET_POWERPC64 && size == 16)
19117 /* Handle moving 128-bit values from GPRs to VSX point registers on
19118 ISA 2.07 (power8, power9) when running in 64-bit mode using
19119 XXPERMDI to glue the two 64-bit values back together. */
19120 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19122 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19123 icode = reg_addr[mode].reload_vsx_gpr;
19126 /* Handle moving 128-bit values from VSX point registers to GPRs on
19127 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19128 bottom 64-bit value. */
19129 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19131 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19132 icode = reg_addr[mode].reload_gpr_vsx;
19136 else if (TARGET_POWERPC64 && mode == SFmode)
19138 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19140 cost = 3; /* xscvdpspn, mfvsrd, and. */
19141 icode = reg_addr[mode].reload_gpr_vsx;
19144 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19146 cost = 2; /* mtvsrz, xscvspdpn. */
19147 icode = reg_addr[mode].reload_vsx_gpr;
19151 else if (!TARGET_POWERPC64 && size == 8)
19153 /* Handle moving 64-bit values from GPRs to floating point registers on
19154 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19155 32-bit values back together. Altivec register classes must be handled
19156 specially since a different instruction is used, and the secondary
19157 reload support requires a single instruction class in the scratch
19158 register constraint. However, right now TFmode is not allowed in
19159 Altivec registers, so the pattern will never match. */
19160 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19162 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19163 icode = reg_addr[mode].reload_fpr_gpr;
19167 if (icode != CODE_FOR_nothing)
19172 sri->icode = icode;
19173 sri->extra_cost = cost;
19180 /* Return whether a move between two register classes can be done either
19181 directly (simple move) or via a pattern that uses a single extra temporary
19182 (using ISA 2.07's direct move in this case. */
19185 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19186 enum rs6000_reg_type from_type,
19188 secondary_reload_info *sri,
19191 /* Fall back to load/store reloads if either type is not a register. */
19192 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19195 /* If we haven't allocated registers yet, assume the move can be done for the
19196 standard register types. */
19197 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19198 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19199 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19202 /* Moves to the same set of registers is a simple move for non-specialized
19204 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19207 /* Check whether a simple move can be done directly. */
19208 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19212 sri->icode = CODE_FOR_nothing;
19213 sri->extra_cost = 0;
19218 /* Now check if we can do it in a few steps. */
19219 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19223 /* Inform reload about cases where moving X with a mode MODE to a register in
19224 RCLASS requires an extra scratch or immediate register. Return the class
19225 needed for the immediate register.
19227 For VSX and Altivec, we may need a register to convert sp+offset into
19230 For misaligned 64-bit gpr loads and stores we need a register to
19231 convert an offset address to indirect. */
19234 rs6000_secondary_reload (bool in_p,
19236 reg_class_t rclass_i,
19238 secondary_reload_info *sri)
19240 enum reg_class rclass = (enum reg_class) rclass_i;
19241 reg_class_t ret = ALL_REGS;
19242 enum insn_code icode;
19243 bool default_p = false;
19244 bool done_p = false;
19246 /* Allow subreg of memory before/during reload. */
19247 bool memory_p = (MEM_P (x)
19248 || (!reload_completed && GET_CODE (x) == SUBREG
19249 && MEM_P (SUBREG_REG (x))));
19251 sri->icode = CODE_FOR_nothing;
19252 sri->t_icode = CODE_FOR_nothing;
19253 sri->extra_cost = 0;
19255 ? reg_addr[mode].reload_load
19256 : reg_addr[mode].reload_store);
19258 if (REG_P (x) || register_operand (x, mode))
19260 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19261 bool altivec_p = (rclass == ALTIVEC_REGS);
19262 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19265 std::swap (to_type, from_type);
19267 /* Can we do a direct move of some sort? */
19268 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19271 icode = (enum insn_code)sri->icode;
19278 /* Make sure 0.0 is not reloaded or forced into memory. */
19279 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19286 /* If this is a scalar floating point value and we want to load it into the
19287 traditional Altivec registers, do it via a move via a traditional floating
19288 point register, unless we have D-form addressing. Also make sure that
19289 non-zero constants use a FPR. */
19290 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19291 && !mode_supports_vmx_dform (mode)
19292 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19293 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
19300 /* Handle reload of load/stores if we have reload helper functions. */
19301 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19303 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19306 if (extra_cost >= 0)
19310 if (extra_cost > 0)
19312 sri->extra_cost = extra_cost;
19313 sri->icode = icode;
19318 /* Handle unaligned loads and stores of integer registers. */
19319 if (!done_p && TARGET_POWERPC64
19320 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19322 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19324 rtx addr = XEXP (x, 0);
19325 rtx off = address_offset (addr);
19327 if (off != NULL_RTX)
19329 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19330 unsigned HOST_WIDE_INT offset = INTVAL (off);
19332 /* We need a secondary reload when our legitimate_address_p
19333 says the address is good (as otherwise the entire address
19334 will be reloaded), and the offset is not a multiple of
19335 four or we have an address wrap. Address wrap will only
19336 occur for LO_SUMs since legitimate_offset_address_p
19337 rejects addresses for 16-byte mems that will wrap. */
19338 if (GET_CODE (addr) == LO_SUM
19339 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19340 && ((offset & 3) != 0
19341 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19342 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19343 && (offset & 3) != 0))
19345 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19347 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19348 : CODE_FOR_reload_di_load);
19350 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19351 : CODE_FOR_reload_di_store);
19352 sri->extra_cost = 2;
19363 if (!done_p && !TARGET_POWERPC64
19364 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19366 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19368 rtx addr = XEXP (x, 0);
19369 rtx off = address_offset (addr);
19371 if (off != NULL_RTX)
19373 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19374 unsigned HOST_WIDE_INT offset = INTVAL (off);
19376 /* We need a secondary reload when our legitimate_address_p
19377 says the address is good (as otherwise the entire address
19378 will be reloaded), and we have a wrap.
19380 legitimate_lo_sum_address_p allows LO_SUM addresses to
19381 have any offset so test for wrap in the low 16 bits.
19383 legitimate_offset_address_p checks for the range
19384 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19385 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19386 [0x7ff4,0x7fff] respectively, so test for the
19387 intersection of these ranges, [0x7ffc,0x7fff] and
19388 [0x7ff4,0x7ff7] respectively.
19390 Note that the address we see here may have been
19391 manipulated by legitimize_reload_address. */
19392 if (GET_CODE (addr) == LO_SUM
19393 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19394 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19397 sri->icode = CODE_FOR_reload_si_load;
19399 sri->icode = CODE_FOR_reload_si_store;
19400 sri->extra_cost = 2;
19415 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19417 gcc_assert (ret != ALL_REGS);
19419 if (TARGET_DEBUG_ADDR)
19422 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19424 reg_class_names[ret],
19425 in_p ? "true" : "false",
19426 reg_class_names[rclass],
19427 GET_MODE_NAME (mode));
19429 if (reload_completed)
19430 fputs (", after reload", stderr);
19433 fputs (", done_p not set", stderr);
19436 fputs (", default secondary reload", stderr);
19438 if (sri->icode != CODE_FOR_nothing)
19439 fprintf (stderr, ", reload func = %s, extra cost = %d",
19440 insn_data[sri->icode].name, sri->extra_cost);
19442 else if (sri->extra_cost > 0)
19443 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19445 fputs ("\n", stderr);
19452 /* Better tracing for rs6000_secondary_reload_inner. */
19455 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19460 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19462 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19463 store_p ? "store" : "load");
19466 set = gen_rtx_SET (mem, reg);
19468 set = gen_rtx_SET (reg, mem);
19470 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19471 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19474 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19475 ATTRIBUTE_NORETURN;
19478 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19481 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19482 gcc_unreachable ();
19485 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19486 reload helper functions. These were identified in
19487 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19488 reload, it calls the insns:
19489 reload_<RELOAD:mode>_<P:mptrsize>_store
19490 reload_<RELOAD:mode>_<P:mptrsize>_load
19492 which in turn calls this function, to do whatever is necessary to create
19493 valid addresses. */
19496 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19498 int regno = true_regnum (reg);
19499 machine_mode mode = GET_MODE (reg);
19500 addr_mask_type addr_mask;
19503 rtx op_reg, op0, op1;
19508 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
19509 || !base_reg_operand (scratch, GET_MODE (scratch)))
19510 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19512 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19513 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19515 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19516 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19518 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19519 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19522 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19524 /* Make sure the mode is valid in this register class. */
19525 if ((addr_mask & RELOAD_REG_VALID) == 0)
19526 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19528 if (TARGET_DEBUG_ADDR)
19529 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19531 new_addr = addr = XEXP (mem, 0);
19532 switch (GET_CODE (addr))
19534 /* Does the register class support auto update forms for this mode? If
19535 not, do the update now. We don't need a scratch register, since the
19536 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19539 op_reg = XEXP (addr, 0);
19540 if (!base_reg_operand (op_reg, Pmode))
19541 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19543 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19545 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
19551 op0 = XEXP (addr, 0);
19552 op1 = XEXP (addr, 1);
19553 if (!base_reg_operand (op0, Pmode)
19554 || GET_CODE (op1) != PLUS
19555 || !rtx_equal_p (op0, XEXP (op1, 0)))
19556 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19558 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19560 emit_insn (gen_rtx_SET (op0, op1));
19565 /* Do we need to simulate AND -16 to clear the bottom address bits used
19566 in VMX load/stores? */
19568 op0 = XEXP (addr, 0);
19569 op1 = XEXP (addr, 1);
19570 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19572 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
19575 else if (GET_CODE (op1) == PLUS)
19577 emit_insn (gen_rtx_SET (scratch, op1));
19582 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19584 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19585 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19586 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19587 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19588 new_addr = scratch;
19592 /* If this is an indirect address, make sure it is a base register. */
19595 if (!base_reg_operand (addr, GET_MODE (addr)))
19597 emit_insn (gen_rtx_SET (scratch, addr));
19598 new_addr = scratch;
19602 /* If this is an indexed address, make sure the register class can handle
19603 indexed addresses for this mode. */
19605 op0 = XEXP (addr, 0);
19606 op1 = XEXP (addr, 1);
19607 if (!base_reg_operand (op0, Pmode))
19608 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19610 else if (int_reg_operand (op1, Pmode))
19612 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19614 emit_insn (gen_rtx_SET (scratch, addr));
19615 new_addr = scratch;
19619 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19621 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19622 || !quad_address_p (addr, mode, false))
19624 emit_insn (gen_rtx_SET (scratch, addr));
19625 new_addr = scratch;
19629 /* Make sure the register class can handle offset addresses. */
19630 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19632 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19634 emit_insn (gen_rtx_SET (scratch, addr));
19635 new_addr = scratch;
19640 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19645 op0 = XEXP (addr, 0);
19646 op1 = XEXP (addr, 1);
19647 if (!base_reg_operand (op0, Pmode))
19648 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19650 else if (int_reg_operand (op1, Pmode))
19652 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19654 emit_insn (gen_rtx_SET (scratch, addr));
19655 new_addr = scratch;
19659 /* Quad offsets are restricted and can't handle normal addresses. */
19660 else if (mode_supports_dq_form (mode))
19662 emit_insn (gen_rtx_SET (scratch, addr));
19663 new_addr = scratch;
19666 /* Make sure the register class can handle offset addresses. */
19667 else if (legitimate_lo_sum_address_p (mode, addr, false))
19669 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19671 emit_insn (gen_rtx_SET (scratch, addr));
19672 new_addr = scratch;
19677 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19684 rs6000_emit_move (scratch, addr, Pmode);
19685 new_addr = scratch;
19689 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19692 /* Adjust the address if it changed. */
19693 if (addr != new_addr)
19695 mem = replace_equiv_address_nv (mem, new_addr);
19696 if (TARGET_DEBUG_ADDR)
19697 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19700 /* Now create the move. */
19702 emit_insn (gen_rtx_SET (mem, reg));
19704 emit_insn (gen_rtx_SET (reg, mem));
19709 /* Convert reloads involving 64-bit gprs and misaligned offset
19710 addressing, or multiple 32-bit gprs and offsets that are too large,
19711 to use indirect addressing. */
19714 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19716 int regno = true_regnum (reg);
19717 enum reg_class rclass;
19719 rtx scratch_or_premodify = scratch;
19721 if (TARGET_DEBUG_ADDR)
19723 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19724 store_p ? "store" : "load");
19725 fprintf (stderr, "reg:\n");
19727 fprintf (stderr, "mem:\n");
19729 fprintf (stderr, "scratch:\n");
19730 debug_rtx (scratch);
19733 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
19734 gcc_assert (GET_CODE (mem) == MEM);
19735 rclass = REGNO_REG_CLASS (regno);
19736 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19737 addr = XEXP (mem, 0);
19739 if (GET_CODE (addr) == PRE_MODIFY)
19741 gcc_assert (REG_P (XEXP (addr, 0))
19742 && GET_CODE (XEXP (addr, 1)) == PLUS
19743 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19744 scratch_or_premodify = XEXP (addr, 0);
19745 if (!HARD_REGISTER_P (scratch_or_premodify))
19746 /* If we have a pseudo here then reload will have arranged
19747 to have it replaced, but only in the original insn.
19748 Use the replacement here too. */
19749 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
19751 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
19752 expressions from the original insn, without unsharing them.
19753 Any RTL that points into the original insn will of course
19754 have register replacements applied. That is why we don't
19755 need to look for replacements under the PLUS. */
19756 addr = XEXP (addr, 1);
19758 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19760 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19762 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19764 /* Now create the move. */
19766 emit_insn (gen_rtx_SET (mem, reg));
19768 emit_insn (gen_rtx_SET (reg, mem));
19773 /* Given an rtx X being reloaded into a reg required to be
19774 in class CLASS, return the class of reg to actually use.
19775 In general this is just CLASS; but on some machines
19776 in some cases it is preferable to use a more restrictive class.
19778 On the RS/6000, we have to return NO_REGS when we want to reload a
19779 floating-point CONST_DOUBLE to force it to be copied to memory.
19781 We also don't want to reload integer values into floating-point
19782 registers if we can at all help it. In fact, this can
19783 cause reload to die, if it tries to generate a reload of CTR
19784 into a FP register and discovers it doesn't have the memory location
19787 ??? Would it be a good idea to have reload do the converse, that is
19788 try to reload floating modes into FP registers if possible?
19791 static enum reg_class
19792 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19794 machine_mode mode = GET_MODE (x);
19795 bool is_constant = CONSTANT_P (x);
19797 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19798 reload class for it. */
19799 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19800 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19803 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19804 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19807 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19808 the reloading of address expressions using PLUS into floating point
19810 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19814 /* Zero is always allowed in all VSX registers. */
19815 if (x == CONST0_RTX (mode))
19818 /* If this is a vector constant that can be formed with a few Altivec
19819 instructions, we want altivec registers. */
19820 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19821 return ALTIVEC_REGS;
19823 /* If this is an integer constant that can easily be loaded into
19824 vector registers, allow it. */
19825 if (CONST_INT_P (x))
19827 HOST_WIDE_INT value = INTVAL (x);
19829 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19830 2.06 can generate it in the Altivec registers with
19834 if (TARGET_P8_VECTOR)
19836 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19837 return ALTIVEC_REGS;
19842 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19843 a sign extend in the Altivec registers. */
19844 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19845 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19846 return ALTIVEC_REGS;
19849 /* Force constant to memory. */
19853 /* D-form addressing can easily reload the value. */
19854 if (mode_supports_vmx_dform (mode)
19855 || mode_supports_dq_form (mode))
19858 /* If this is a scalar floating point value and we don't have D-form
19859 addressing, prefer the traditional floating point registers so that we
19860 can use D-form (register+offset) addressing. */
19861 if (rclass == VSX_REGS
19862 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19865 /* Prefer the Altivec registers if Altivec is handling the vector
19866 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19868 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19869 || mode == V1TImode)
19870 return ALTIVEC_REGS;
19875 if (is_constant || GET_CODE (x) == PLUS)
19877 if (reg_class_subset_p (GENERAL_REGS, rclass))
19878 return GENERAL_REGS;
19879 if (reg_class_subset_p (BASE_REGS, rclass))
19884 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
19885 return GENERAL_REGS;
19890 /* Debug version of rs6000_preferred_reload_class. */
19891 static enum reg_class
19892 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19894 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19897 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19899 reg_class_names[ret], reg_class_names[rclass],
19900 GET_MODE_NAME (GET_MODE (x)));
19906 /* If we are copying between FP or AltiVec registers and anything else, we need
19907 a memory location. The exception is when we are targeting ppc64 and the
19908 move to/from fpr to gpr instructions are available. Also, under VSX, you
19909 can copy vector registers from the FP register set to the Altivec register
19910 set and vice versa. */
19913 rs6000_secondary_memory_needed (machine_mode mode,
19914 reg_class_t from_class,
19915 reg_class_t to_class)
19917 enum rs6000_reg_type from_type, to_type;
19918 bool altivec_p = ((from_class == ALTIVEC_REGS)
19919 || (to_class == ALTIVEC_REGS));
19921 /* If a simple/direct move is available, we don't need secondary memory */
19922 from_type = reg_class_to_reg_type[(int)from_class];
19923 to_type = reg_class_to_reg_type[(int)to_class];
19925 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19926 (secondary_reload_info *)0, altivec_p))
19929 /* If we have a floating point or vector register class, we need to use
19930 memory to transfer the data. */
19931 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19937 /* Debug version of rs6000_secondary_memory_needed. */
19939 rs6000_debug_secondary_memory_needed (machine_mode mode,
19940 reg_class_t from_class,
19941 reg_class_t to_class)
19943 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19946 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19947 "to_class = %s, mode = %s\n",
19948 ret ? "true" : "false",
19949 reg_class_names[from_class],
19950 reg_class_names[to_class],
19951 GET_MODE_NAME (mode));
19956 /* Return the register class of a scratch register needed to copy IN into
19957 or out of a register in RCLASS in MODE. If it can be done directly,
19958 NO_REGS is returned. */
19960 static enum reg_class
19961 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19966 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19968 && MACHOPIC_INDIRECT
19972 /* We cannot copy a symbolic operand directly into anything
19973 other than BASE_REGS for TARGET_ELF. So indicate that a
19974 register from BASE_REGS is needed as an intermediate
19977 On Darwin, pic addresses require a load from memory, which
19978 needs a base register. */
19979 if (rclass != BASE_REGS
19980 && (GET_CODE (in) == SYMBOL_REF
19981 || GET_CODE (in) == HIGH
19982 || GET_CODE (in) == LABEL_REF
19983 || GET_CODE (in) == CONST))
19987 if (GET_CODE (in) == REG)
19989 regno = REGNO (in);
19990 if (regno >= FIRST_PSEUDO_REGISTER)
19992 regno = true_regnum (in);
19993 if (regno >= FIRST_PSEUDO_REGISTER)
19997 else if (GET_CODE (in) == SUBREG)
19999 regno = true_regnum (in);
20000 if (regno >= FIRST_PSEUDO_REGISTER)
20006 /* If we have VSX register moves, prefer moving scalar values between
20007 Altivec registers and GPR by going via an FPR (and then via memory)
20008 instead of reloading the secondary memory address for Altivec moves. */
20010 && GET_MODE_SIZE (mode) < 16
20011 && !mode_supports_vmx_dform (mode)
20012 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20013 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20014 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20015 && (regno >= 0 && INT_REGNO_P (regno)))))
20018 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20020 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20021 || (regno >= 0 && INT_REGNO_P (regno)))
20024 /* Constants, memory, and VSX registers can go into VSX registers (both the
20025 traditional floating point and the altivec registers). */
20026 if (rclass == VSX_REGS
20027 && (regno == -1 || VSX_REGNO_P (regno)))
20030 /* Constants, memory, and FP registers can go into FP registers. */
20031 if ((regno == -1 || FP_REGNO_P (regno))
20032 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20033 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20035 /* Memory, and AltiVec registers can go into AltiVec registers. */
20036 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20037 && rclass == ALTIVEC_REGS)
20040 /* We can copy among the CR registers. */
20041 if ((rclass == CR_REGS || rclass == CR0_REGS)
20042 && regno >= 0 && CR_REGNO_P (regno))
20045 /* Otherwise, we need GENERAL_REGS. */
20046 return GENERAL_REGS;
20049 /* Debug version of rs6000_secondary_reload_class. */
20050 static enum reg_class
20051 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20052 machine_mode mode, rtx in)
20054 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20056 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20057 "mode = %s, input rtx:\n",
20058 reg_class_names[ret], reg_class_names[rclass],
20059 GET_MODE_NAME (mode));
20065 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20068 rs6000_can_change_mode_class (machine_mode from,
20070 reg_class_t rclass)
20072 unsigned from_size = GET_MODE_SIZE (from);
20073 unsigned to_size = GET_MODE_SIZE (to);
20075 if (from_size != to_size)
20077 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20079 if (reg_classes_intersect_p (xclass, rclass))
20081 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20082 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20083 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20084 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20086 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20087 single register under VSX because the scalar part of the register
20088 is in the upper 64-bits, and not the lower 64-bits. Types like
20089 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20090 IEEE floating point can't overlap, and neither can small
20093 if (to_float128_vector_p && from_float128_vector_p)
20096 else if (to_float128_vector_p || from_float128_vector_p)
20099 /* TDmode in floating-mode registers must always go into a register
20100 pair with the most significant word in the even-numbered register
20101 to match ISA requirements. In little-endian mode, this does not
20102 match subreg numbering, so we cannot allow subregs. */
20103 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20106 if (from_size < 8 || to_size < 8)
20109 if (from_size == 8 && (8 * to_nregs) != to_size)
20112 if (to_size == 8 && (8 * from_nregs) != from_size)
20121 /* Since the VSX register set includes traditional floating point registers
20122 and altivec registers, just check for the size being different instead of
20123 trying to check whether the modes are vector modes. Otherwise it won't
20124 allow say DF and DI to change classes. For types like TFmode and TDmode
20125 that take 2 64-bit registers, rather than a single 128-bit register, don't
20126 allow subregs of those types to other 128 bit types. */
20127 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20129 unsigned num_regs = (from_size + 15) / 16;
20130 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20131 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20134 return (from_size == 8 || from_size == 16);
20137 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20138 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20144 /* Debug version of rs6000_can_change_mode_class. */
20146 rs6000_debug_can_change_mode_class (machine_mode from,
20148 reg_class_t rclass)
20150 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20153 "rs6000_can_change_mode_class, return %s, from = %s, "
20154 "to = %s, rclass = %s\n",
20155 ret ? "true" : "false",
20156 GET_MODE_NAME (from), GET_MODE_NAME (to),
20157 reg_class_names[rclass]);
20162 /* Return a string to do a move operation of 128 bits of data. */
20165 rs6000_output_move_128bit (rtx operands[])
20167 rtx dest = operands[0];
20168 rtx src = operands[1];
20169 machine_mode mode = GET_MODE (dest);
20172 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20173 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20177 dest_regno = REGNO (dest);
20178 dest_gpr_p = INT_REGNO_P (dest_regno);
20179 dest_fp_p = FP_REGNO_P (dest_regno);
20180 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20181 dest_vsx_p = dest_fp_p | dest_vmx_p;
20186 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20191 src_regno = REGNO (src);
20192 src_gpr_p = INT_REGNO_P (src_regno);
20193 src_fp_p = FP_REGNO_P (src_regno);
20194 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20195 src_vsx_p = src_fp_p | src_vmx_p;
20200 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20203 /* Register moves. */
20204 if (dest_regno >= 0 && src_regno >= 0)
20211 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20212 return (WORDS_BIG_ENDIAN
20213 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20214 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20216 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20220 else if (TARGET_VSX && dest_vsx_p)
20223 return "xxlor %x0,%x1,%x1";
20225 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20226 return (WORDS_BIG_ENDIAN
20227 ? "mtvsrdd %x0,%1,%L1"
20228 : "mtvsrdd %x0,%L1,%1");
20230 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20234 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20235 return "vor %0,%1,%1";
20237 else if (dest_fp_p && src_fp_p)
20242 else if (dest_regno >= 0 && MEM_P (src))
20246 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20252 else if (TARGET_ALTIVEC && dest_vmx_p
20253 && altivec_indexed_or_indirect_operand (src, mode))
20254 return "lvx %0,%y1";
20256 else if (TARGET_VSX && dest_vsx_p)
20258 if (mode_supports_dq_form (mode)
20259 && quad_address_p (XEXP (src, 0), mode, true))
20260 return "lxv %x0,%1";
20262 else if (TARGET_P9_VECTOR)
20263 return "lxvx %x0,%y1";
20265 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20266 return "lxvw4x %x0,%y1";
20269 return "lxvd2x %x0,%y1";
20272 else if (TARGET_ALTIVEC && dest_vmx_p)
20273 return "lvx %0,%y1";
20275 else if (dest_fp_p)
20280 else if (src_regno >= 0 && MEM_P (dest))
20284 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20285 return "stq %1,%0";
20290 else if (TARGET_ALTIVEC && src_vmx_p
20291 && altivec_indexed_or_indirect_operand (dest, mode))
20292 return "stvx %1,%y0";
20294 else if (TARGET_VSX && src_vsx_p)
20296 if (mode_supports_dq_form (mode)
20297 && quad_address_p (XEXP (dest, 0), mode, true))
20298 return "stxv %x1,%0";
20300 else if (TARGET_P9_VECTOR)
20301 return "stxvx %x1,%y0";
20303 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20304 return "stxvw4x %x1,%y0";
20307 return "stxvd2x %x1,%y0";
20310 else if (TARGET_ALTIVEC && src_vmx_p)
20311 return "stvx %1,%y0";
20318 else if (dest_regno >= 0
20319 && (GET_CODE (src) == CONST_INT
20320 || GET_CODE (src) == CONST_WIDE_INT
20321 || GET_CODE (src) == CONST_DOUBLE
20322 || GET_CODE (src) == CONST_VECTOR))
20327 else if ((dest_vmx_p && TARGET_ALTIVEC)
20328 || (dest_vsx_p && TARGET_VSX))
20329 return output_vec_const_move (operands);
20332 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20335 /* Validate a 128-bit move. */
20337 rs6000_move_128bit_ok_p (rtx operands[])
20339 machine_mode mode = GET_MODE (operands[0]);
20340 return (gpc_reg_operand (operands[0], mode)
20341 || gpc_reg_operand (operands[1], mode));
20344 /* Return true if a 128-bit move needs to be split. */
20346 rs6000_split_128bit_ok_p (rtx operands[])
20348 if (!reload_completed)
20351 if (!gpr_or_gpr_p (operands[0], operands[1]))
20354 if (quad_load_store_p (operands[0], operands[1]))
20361 /* Given a comparison operation, return the bit number in CCR to test. We
20362 know this is a valid comparison.
20364 SCC_P is 1 if this is for an scc. That means that %D will have been
20365 used instead of %C, so the bits will be in different places.
20367 Return -1 if OP isn't a valid comparison for some reason. */
20370 ccr_bit (rtx op, int scc_p)
20372 enum rtx_code code = GET_CODE (op);
20373 machine_mode cc_mode;
20378 if (!COMPARISON_P (op))
20381 reg = XEXP (op, 0);
20383 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
20385 cc_mode = GET_MODE (reg);
20386 cc_regnum = REGNO (reg);
20387 base_bit = 4 * (cc_regnum - CR0_REGNO);
20389 validate_condition_mode (code, cc_mode);
20391 /* When generating a sCOND operation, only positive conditions are
20394 || code == EQ || code == GT || code == LT || code == UNORDERED
20395 || code == GTU || code == LTU);
20400 return scc_p ? base_bit + 3 : base_bit + 2;
20402 return base_bit + 2;
20403 case GT: case GTU: case UNLE:
20404 return base_bit + 1;
20405 case LT: case LTU: case UNGE:
20407 case ORDERED: case UNORDERED:
20408 return base_bit + 3;
20411 /* If scc, we will have done a cror to put the bit in the
20412 unordered position. So test that bit. For integer, this is ! LT
20413 unless this is an scc insn. */
20414 return scc_p ? base_bit + 3 : base_bit;
20417 return scc_p ? base_bit + 3 : base_bit + 1;
20420 gcc_unreachable ();
20424 /* Return the GOT register. */
20427 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20429 /* The second flow pass currently (June 1999) can't update
20430 regs_ever_live without disturbing other parts of the compiler, so
20431 update it here to make the prolog/epilogue code happy. */
20432 if (!can_create_pseudo_p ()
20433 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20434 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20436 crtl->uses_pic_offset_table = 1;
20438 return pic_offset_table_rtx;
20441 static rs6000_stack_t stack_info;
20443 /* Function to init struct machine_function.
20444 This will be called, via a pointer variable,
20445 from push_function_context. */
20447 static struct machine_function *
20448 rs6000_init_machine_status (void)
20450 stack_info.reload_completed = 0;
20451 return ggc_cleared_alloc<machine_function> ();
20454 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
20456 /* Write out a function code label. */
20459 rs6000_output_function_entry (FILE *file, const char *fname)
20461 if (fname[0] != '.')
20463 switch (DEFAULT_ABI)
20466 gcc_unreachable ();
20472 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20482 RS6000_OUTPUT_BASENAME (file, fname);
20485 /* Print an operand. Recognize special options, documented below. */
20488 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20489 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20491 #define SMALL_DATA_RELOC "sda21"
20492 #define SMALL_DATA_REG 0
20496 print_operand (FILE *file, rtx x, int code)
20499 unsigned HOST_WIDE_INT uval;
20503 /* %a is output_address. */
20505 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20509 /* Like 'J' but get to the GT bit only. */
20510 gcc_assert (REG_P (x));
20512 /* Bit 1 is GT bit. */
20513 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20515 /* Add one for shift count in rlinm for scc. */
20516 fprintf (file, "%d", i + 1);
20520 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20523 output_operand_lossage ("invalid %%e value");
20528 if ((uval & 0xffff) == 0 && uval != 0)
20533 /* X is a CR register. Print the number of the EQ bit of the CR */
20534 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20535 output_operand_lossage ("invalid %%E value");
20537 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20541 /* X is a CR register. Print the shift count needed to move it
20542 to the high-order four bits. */
20543 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20544 output_operand_lossage ("invalid %%f value");
20546 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20550 /* Similar, but print the count for the rotate in the opposite
20552 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20553 output_operand_lossage ("invalid %%F value");
20555 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20559 /* X is a constant integer. If it is negative, print "m",
20560 otherwise print "z". This is to make an aze or ame insn. */
20561 if (GET_CODE (x) != CONST_INT)
20562 output_operand_lossage ("invalid %%G value");
20563 else if (INTVAL (x) >= 0)
20570 /* If constant, output low-order five bits. Otherwise, write
20573 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20575 print_operand (file, x, 0);
20579 /* If constant, output low-order six bits. Otherwise, write
20582 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20584 print_operand (file, x, 0);
20588 /* Print `i' if this is a constant, else nothing. */
20594 /* Write the bit number in CCR for jump. */
20595 i = ccr_bit (x, 0);
20597 output_operand_lossage ("invalid %%j code");
20599 fprintf (file, "%d", i);
20603 /* Similar, but add one for shift count in rlinm for scc and pass
20604 scc flag to `ccr_bit'. */
20605 i = ccr_bit (x, 1);
20607 output_operand_lossage ("invalid %%J code");
20609 /* If we want bit 31, write a shift count of zero, not 32. */
20610 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20614 /* X must be a constant. Write the 1's complement of the
20617 output_operand_lossage ("invalid %%k value");
20619 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20623 /* X must be a symbolic constant on ELF. Write an
20624 expression suitable for an 'addi' that adds in the low 16
20625 bits of the MEM. */
20626 if (GET_CODE (x) == CONST)
20628 if (GET_CODE (XEXP (x, 0)) != PLUS
20629 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
20630 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20631 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
20632 output_operand_lossage ("invalid %%K value");
20634 print_operand_address (file, x);
20635 fputs ("@l", file);
20638 /* %l is output_asm_label. */
20641 /* Write second word of DImode or DFmode reference. Works on register
20642 or non-indexed memory only. */
20644 fputs (reg_names[REGNO (x) + 1], file);
20645 else if (MEM_P (x))
20647 machine_mode mode = GET_MODE (x);
20648 /* Handle possible auto-increment. Since it is pre-increment and
20649 we have already done it, we can just use an offset of word. */
20650 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20651 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20652 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20654 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20655 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20658 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20662 if (small_data_operand (x, GET_MODE (x)))
20663 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20664 reg_names[SMALL_DATA_REG]);
20668 case 'N': /* Unused */
20669 /* Write the number of elements in the vector times 4. */
20670 if (GET_CODE (x) != PARALLEL)
20671 output_operand_lossage ("invalid %%N value");
20673 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20676 case 'O': /* Unused */
20677 /* Similar, but subtract 1 first. */
20678 if (GET_CODE (x) != PARALLEL)
20679 output_operand_lossage ("invalid %%O value");
20681 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20685 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20688 || (i = exact_log2 (INTVAL (x))) < 0)
20689 output_operand_lossage ("invalid %%p value");
20691 fprintf (file, "%d", i);
20695 /* The operand must be an indirect memory reference. The result
20696 is the register name. */
20697 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
20698 || REGNO (XEXP (x, 0)) >= 32)
20699 output_operand_lossage ("invalid %%P value");
20701 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20705 /* This outputs the logical code corresponding to a boolean
20706 expression. The expression may have one or both operands
20707 negated (if one, only the first one). For condition register
20708 logical operations, it will also treat the negated
20709 CR codes as NOTs, but not handle NOTs of them. */
20711 const char *const *t = 0;
20713 enum rtx_code code = GET_CODE (x);
20714 static const char * const tbl[3][3] = {
20715 { "and", "andc", "nor" },
20716 { "or", "orc", "nand" },
20717 { "xor", "eqv", "xor" } };
20721 else if (code == IOR)
20723 else if (code == XOR)
20726 output_operand_lossage ("invalid %%q value");
20728 if (GET_CODE (XEXP (x, 0)) != NOT)
20732 if (GET_CODE (XEXP (x, 1)) == NOT)
20743 if (! TARGET_MFCRF)
20749 /* X is a CR register. Print the mask for `mtcrf'. */
20750 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20751 output_operand_lossage ("invalid %%R value");
20753 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20757 /* Low 5 bits of 32 - value */
20759 output_operand_lossage ("invalid %%s value");
20761 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20765 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20766 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
20768 /* Bit 3 is OV bit. */
20769 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20771 /* If we want bit 31, write a shift count of zero, not 32. */
20772 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20776 /* Print the symbolic name of a branch target register. */
20777 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
20778 && REGNO (x) != CTR_REGNO))
20779 output_operand_lossage ("invalid %%T value");
20780 else if (REGNO (x) == LR_REGNO)
20781 fputs ("lr", file);
20783 fputs ("ctr", file);
20787 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20788 for use in unsigned operand. */
20791 output_operand_lossage ("invalid %%u value");
20796 if ((uval & 0xffff) == 0)
20799 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20803 /* High-order 16 bits of constant for use in signed operand. */
20805 output_operand_lossage ("invalid %%v value");
20807 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20808 (INTVAL (x) >> 16) & 0xffff);
20812 /* Print `u' if this has an auto-increment or auto-decrement. */
20814 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20815 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20816 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20821 /* Print the trap code for this operand. */
20822 switch (GET_CODE (x))
20825 fputs ("eq", file); /* 4 */
20828 fputs ("ne", file); /* 24 */
20831 fputs ("lt", file); /* 16 */
20834 fputs ("le", file); /* 20 */
20837 fputs ("gt", file); /* 8 */
20840 fputs ("ge", file); /* 12 */
20843 fputs ("llt", file); /* 2 */
20846 fputs ("lle", file); /* 6 */
20849 fputs ("lgt", file); /* 1 */
20852 fputs ("lge", file); /* 5 */
20855 gcc_unreachable ();
20860 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20863 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20864 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20866 print_operand (file, x, 0);
20870 /* X is a FPR or Altivec register used in a VSX context. */
20871 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
20872 output_operand_lossage ("invalid %%x value");
20875 int reg = REGNO (x);
20876 int vsx_reg = (FP_REGNO_P (reg)
20878 : reg - FIRST_ALTIVEC_REGNO + 32);
20880 #ifdef TARGET_REGNAMES
20881 if (TARGET_REGNAMES)
20882 fprintf (file, "%%vs%d", vsx_reg);
20885 fprintf (file, "%d", vsx_reg);
20891 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20892 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20893 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20898 /* Like 'L', for third word of TImode/PTImode */
20900 fputs (reg_names[REGNO (x) + 2], file);
20901 else if (MEM_P (x))
20903 machine_mode mode = GET_MODE (x);
20904 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20905 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20906 output_address (mode, plus_constant (Pmode,
20907 XEXP (XEXP (x, 0), 0), 8));
20908 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20909 output_address (mode, plus_constant (Pmode,
20910 XEXP (XEXP (x, 0), 0), 8));
20912 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20913 if (small_data_operand (x, GET_MODE (x)))
20914 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20915 reg_names[SMALL_DATA_REG]);
20920 /* X is a SYMBOL_REF. Write out the name preceded by a
20921 period and without any trailing data in brackets. Used for function
20922 names. If we are configured for System V (or the embedded ABI) on
20923 the PowerPC, do not emit the period, since those systems do not use
20924 TOCs and the like. */
20925 gcc_assert (GET_CODE (x) == SYMBOL_REF);
20927 /* For macho, check to see if we need a stub. */
20930 const char *name = XSTR (x, 0);
20932 if (darwin_emit_branch_islands
20933 && MACHOPIC_INDIRECT
20934 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20935 name = machopic_indirection_name (x, /*stub_p=*/true);
20937 assemble_name (file, name);
20939 else if (!DOT_SYMBOLS)
20940 assemble_name (file, XSTR (x, 0));
20942 rs6000_output_function_entry (file, XSTR (x, 0));
20946 /* Like 'L', for last word of TImode/PTImode. */
20948 fputs (reg_names[REGNO (x) + 3], file);
20949 else if (MEM_P (x))
20951 machine_mode mode = GET_MODE (x);
20952 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20953 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20954 output_address (mode, plus_constant (Pmode,
20955 XEXP (XEXP (x, 0), 0), 12));
20956 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20957 output_address (mode, plus_constant (Pmode,
20958 XEXP (XEXP (x, 0), 0), 12));
20960 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20961 if (small_data_operand (x, GET_MODE (x)))
20962 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20963 reg_names[SMALL_DATA_REG]);
20967 /* Print AltiVec memory operand. */
20972 gcc_assert (MEM_P (x));
20976 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20977 && GET_CODE (tmp) == AND
20978 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
20979 && INTVAL (XEXP (tmp, 1)) == -16)
20980 tmp = XEXP (tmp, 0);
20981 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20982 && GET_CODE (tmp) == PRE_MODIFY)
20983 tmp = XEXP (tmp, 1);
20985 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
20988 if (GET_CODE (tmp) != PLUS
20989 || !REG_P (XEXP (tmp, 0))
20990 || !REG_P (XEXP (tmp, 1)))
20992 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20996 if (REGNO (XEXP (tmp, 0)) == 0)
20997 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
20998 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21000 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21001 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21008 fprintf (file, "%s", reg_names[REGNO (x)]);
21009 else if (MEM_P (x))
21011 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21012 know the width from the mode. */
21013 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21014 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21015 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21016 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21017 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21018 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21019 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21020 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21022 output_address (GET_MODE (x), XEXP (x, 0));
21026 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21027 /* This hack along with a corresponding hack in
21028 rs6000_output_addr_const_extra arranges to output addends
21029 where the assembler expects to find them. eg.
21030 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21031 without this hack would be output as "x@toc+4". We
21033 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21035 output_addr_const (file, x);
21040 if (const char *name = get_some_local_dynamic_name ())
21041 assemble_name (file, name);
21043 output_operand_lossage ("'%%&' used without any "
21044 "local dynamic TLS references");
21048 output_operand_lossage ("invalid %%xn code");
21052 /* Print the address of an operand. */
21055 print_operand_address (FILE *file, rtx x)
21058 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21059 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21060 || GET_CODE (x) == LABEL_REF)
21062 output_addr_const (file, x);
21063 if (small_data_operand (x, GET_MODE (x)))
21064 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21065 reg_names[SMALL_DATA_REG]);
21067 gcc_assert (!TARGET_TOC);
21069 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21070 && REG_P (XEXP (x, 1)))
21072 if (REGNO (XEXP (x, 0)) == 0)
21073 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21074 reg_names[ REGNO (XEXP (x, 0)) ]);
21076 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21077 reg_names[ REGNO (XEXP (x, 1)) ]);
21079 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21080 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21081 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21082 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21084 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21085 && CONSTANT_P (XEXP (x, 1)))
21087 fprintf (file, "lo16(");
21088 output_addr_const (file, XEXP (x, 1));
21089 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21093 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21094 && CONSTANT_P (XEXP (x, 1)))
21096 output_addr_const (file, XEXP (x, 1));
21097 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21100 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21102 /* This hack along with a corresponding hack in
21103 rs6000_output_addr_const_extra arranges to output addends
21104 where the assembler expects to find them. eg.
21106 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21107 without this hack would be output as "x@toc+8@l(9)". We
21108 want "x+8@toc@l(9)". */
21109 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21110 if (GET_CODE (x) == LO_SUM)
21111 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21113 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21116 gcc_unreachable ();
21119 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21122 rs6000_output_addr_const_extra (FILE *file, rtx x)
21124 if (GET_CODE (x) == UNSPEC)
21125 switch (XINT (x, 1))
21127 case UNSPEC_TOCREL:
21128 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21129 && REG_P (XVECEXP (x, 0, 1))
21130 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21131 output_addr_const (file, XVECEXP (x, 0, 0));
21132 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21134 if (INTVAL (tocrel_offset_oac) >= 0)
21135 fprintf (file, "+");
21136 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21138 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21141 assemble_name (file, toc_label_name);
21144 else if (TARGET_ELF)
21145 fputs ("@toc", file);
21149 case UNSPEC_MACHOPIC_OFFSET:
21150 output_addr_const (file, XVECEXP (x, 0, 0));
21152 machopic_output_function_base_name (file);
21159 /* Target hook for assembling integer objects. The PowerPC version has
21160 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21161 is defined. It also needs to handle DI-mode objects on 64-bit
21165 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21167 #ifdef RELOCATABLE_NEEDS_FIXUP
21168 /* Special handling for SI values. */
21169 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21171 static int recurse = 0;
21173 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21174 the .fixup section. Since the TOC section is already relocated, we
21175 don't need to mark it here. We used to skip the text section, but it
21176 should never be valid for relocated addresses to be placed in the text
21178 if (DEFAULT_ABI == ABI_V4
21179 && (TARGET_RELOCATABLE || flag_pic > 1)
21180 && in_section != toc_section
21182 && !CONST_SCALAR_INT_P (x)
21188 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21190 ASM_OUTPUT_LABEL (asm_out_file, buf);
21191 fprintf (asm_out_file, "\t.long\t(");
21192 output_addr_const (asm_out_file, x);
21193 fprintf (asm_out_file, ")@fixup\n");
21194 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21195 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21196 fprintf (asm_out_file, "\t.long\t");
21197 assemble_name (asm_out_file, buf);
21198 fprintf (asm_out_file, "\n\t.previous\n");
21202 /* Remove initial .'s to turn a -mcall-aixdesc function
21203 address into the address of the descriptor, not the function
21205 else if (GET_CODE (x) == SYMBOL_REF
21206 && XSTR (x, 0)[0] == '.'
21207 && DEFAULT_ABI == ABI_AIX)
21209 const char *name = XSTR (x, 0);
21210 while (*name == '.')
21213 fprintf (asm_out_file, "\t.long\t%s\n", name);
21217 #endif /* RELOCATABLE_NEEDS_FIXUP */
21218 return default_assemble_integer (x, size, aligned_p);
21221 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21222 /* Emit an assembler directive to set symbol visibility for DECL to
21223 VISIBILITY_TYPE. */
21226 rs6000_assemble_visibility (tree decl, int vis)
21231 /* Functions need to have their entry point symbol visibility set as
21232 well as their descriptor symbol visibility. */
21233 if (DEFAULT_ABI == ABI_AIX
21235 && TREE_CODE (decl) == FUNCTION_DECL)
21237 static const char * const visibility_types[] = {
21238 NULL, "protected", "hidden", "internal"
21241 const char *name, *type;
21243 name = ((* targetm.strip_name_encoding)
21244 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21245 type = visibility_types[vis];
21247 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21248 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21251 default_assemble_visibility (decl, vis);
21256 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21258 /* Reversal of FP compares takes care -- an ordered compare
21259 becomes an unordered compare and vice versa. */
21260 if (mode == CCFPmode
21261 && (!flag_finite_math_only
21262 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21263 || code == UNEQ || code == LTGT))
21264 return reverse_condition_maybe_unordered (code);
21266 return reverse_condition (code);
21269 /* Generate a compare for CODE. Return a brand-new rtx that
21270 represents the result of the compare. */
21273 rs6000_generate_compare (rtx cmp, machine_mode mode)
21275 machine_mode comp_mode;
21276 rtx compare_result;
21277 enum rtx_code code = GET_CODE (cmp);
21278 rtx op0 = XEXP (cmp, 0);
21279 rtx op1 = XEXP (cmp, 1);
21281 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21282 comp_mode = CCmode;
21283 else if (FLOAT_MODE_P (mode))
21284 comp_mode = CCFPmode;
21285 else if (code == GTU || code == LTU
21286 || code == GEU || code == LEU)
21287 comp_mode = CCUNSmode;
21288 else if ((code == EQ || code == NE)
21289 && unsigned_reg_p (op0)
21290 && (unsigned_reg_p (op1)
21291 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21292 /* These are unsigned values, perhaps there will be a later
21293 ordering compare that can be shared with this one. */
21294 comp_mode = CCUNSmode;
21296 comp_mode = CCmode;
21298 /* If we have an unsigned compare, make sure we don't have a signed value as
21300 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
21301 && INTVAL (op1) < 0)
21303 op0 = copy_rtx_if_shared (op0);
21304 op1 = force_reg (GET_MODE (op0), op1);
21305 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21308 /* First, the compare. */
21309 compare_result = gen_reg_rtx (comp_mode);
21311 /* IEEE 128-bit support in VSX registers when we do not have hardware
21313 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21315 rtx libfunc = NULL_RTX;
21316 bool check_nan = false;
21323 libfunc = optab_libfunc (eq_optab, mode);
21328 libfunc = optab_libfunc (ge_optab, mode);
21333 libfunc = optab_libfunc (le_optab, mode);
21338 libfunc = optab_libfunc (unord_optab, mode);
21339 code = (code == UNORDERED) ? NE : EQ;
21345 libfunc = optab_libfunc (ge_optab, mode);
21346 code = (code == UNGE) ? GE : GT;
21352 libfunc = optab_libfunc (le_optab, mode);
21353 code = (code == UNLE) ? LE : LT;
21359 libfunc = optab_libfunc (eq_optab, mode);
21360 code = (code = UNEQ) ? EQ : NE;
21364 gcc_unreachable ();
21367 gcc_assert (libfunc);
21370 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21371 SImode, op0, mode, op1, mode);
21373 /* The library signals an exception for signalling NaNs, so we need to
21374 handle isgreater, etc. by first checking isordered. */
21377 rtx ne_rtx, normal_dest, unord_dest;
21378 rtx unord_func = optab_libfunc (unord_optab, mode);
21379 rtx join_label = gen_label_rtx ();
21380 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21381 rtx unord_cmp = gen_reg_rtx (comp_mode);
21384 /* Test for either value being a NaN. */
21385 gcc_assert (unord_func);
21386 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21387 SImode, op0, mode, op1, mode);
21389 /* Set value (0) if either value is a NaN, and jump to the join
21391 dest = gen_reg_rtx (SImode);
21392 emit_move_insn (dest, const1_rtx);
21393 emit_insn (gen_rtx_SET (unord_cmp,
21394 gen_rtx_COMPARE (comp_mode, unord_dest,
21397 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21398 emit_jump_insn (gen_rtx_SET (pc_rtx,
21399 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21403 /* Do the normal comparison, knowing that the values are not
21405 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21406 SImode, op0, mode, op1, mode);
21408 emit_insn (gen_cstoresi4 (dest,
21409 gen_rtx_fmt_ee (code, SImode, normal_dest,
21411 normal_dest, const0_rtx));
21413 /* Join NaN and non-Nan paths. Compare dest against 0. */
21414 emit_label (join_label);
21418 emit_insn (gen_rtx_SET (compare_result,
21419 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21424 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21425 CLOBBERs to match cmptf_internal2 pattern. */
21426 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21427 && FLOAT128_IBM_P (GET_MODE (op0))
21428 && TARGET_HARD_FLOAT)
21429 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21431 gen_rtx_SET (compare_result,
21432 gen_rtx_COMPARE (comp_mode, op0, op1)),
21433 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21434 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21435 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21436 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21437 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21438 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21439 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21440 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21441 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21442 else if (GET_CODE (op1) == UNSPEC
21443 && XINT (op1, 1) == UNSPEC_SP_TEST)
21445 rtx op1b = XVECEXP (op1, 0, 0);
21446 comp_mode = CCEQmode;
21447 compare_result = gen_reg_rtx (CCEQmode);
21449 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21451 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21454 emit_insn (gen_rtx_SET (compare_result,
21455 gen_rtx_COMPARE (comp_mode, op0, op1)));
21458 /* Some kinds of FP comparisons need an OR operation;
21459 under flag_finite_math_only we don't bother. */
21460 if (FLOAT_MODE_P (mode)
21461 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21462 && !flag_finite_math_only
21463 && (code == LE || code == GE
21464 || code == UNEQ || code == LTGT
21465 || code == UNGT || code == UNLT))
21467 enum rtx_code or1, or2;
21468 rtx or1_rtx, or2_rtx, compare2_rtx;
21469 rtx or_result = gen_reg_rtx (CCEQmode);
21473 case LE: or1 = LT; or2 = EQ; break;
21474 case GE: or1 = GT; or2 = EQ; break;
21475 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21476 case LTGT: or1 = LT; or2 = GT; break;
21477 case UNGT: or1 = UNORDERED; or2 = GT; break;
21478 case UNLT: or1 = UNORDERED; or2 = LT; break;
21479 default: gcc_unreachable ();
21481 validate_condition_mode (or1, comp_mode);
21482 validate_condition_mode (or2, comp_mode);
21483 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21484 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21485 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21486 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21488 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21490 compare_result = or_result;
21494 validate_condition_mode (code, GET_MODE (compare_result));
21496 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21500 /* Return the diagnostic message string if the binary operation OP is
21501 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21504 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21508 machine_mode mode1 = TYPE_MODE (type1);
21509 machine_mode mode2 = TYPE_MODE (type2);
21511 /* For complex modes, use the inner type. */
21512 if (COMPLEX_MODE_P (mode1))
21513 mode1 = GET_MODE_INNER (mode1);
21515 if (COMPLEX_MODE_P (mode2))
21516 mode2 = GET_MODE_INNER (mode2);
21518 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21519 double to intermix unless -mfloat128-convert. */
21520 if (mode1 == mode2)
21523 if (!TARGET_FLOAT128_CVT)
21525 if ((mode1 == KFmode && mode2 == IFmode)
21526 || (mode1 == IFmode && mode2 == KFmode))
21527 return N_("__float128 and __ibm128 cannot be used in the same "
21530 if (TARGET_IEEEQUAD
21531 && ((mode1 == IFmode && mode2 == TFmode)
21532 || (mode1 == TFmode && mode2 == IFmode)))
21533 return N_("__ibm128 and long double cannot be used in the same "
21536 if (!TARGET_IEEEQUAD
21537 && ((mode1 == KFmode && mode2 == TFmode)
21538 || (mode1 == TFmode && mode2 == KFmode)))
21539 return N_("__float128 and long double cannot be used in the same "
21547 /* Expand floating point conversion to/from __float128 and __ibm128. */
21550 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21552 machine_mode dest_mode = GET_MODE (dest);
21553 machine_mode src_mode = GET_MODE (src);
21554 convert_optab cvt = unknown_optab;
21555 bool do_move = false;
21556 rtx libfunc = NULL_RTX;
21558 typedef rtx (*rtx_2func_t) (rtx, rtx);
21559 rtx_2func_t hw_convert = (rtx_2func_t)0;
21563 rtx_2func_t from_df;
21564 rtx_2func_t from_sf;
21565 rtx_2func_t from_si_sign;
21566 rtx_2func_t from_si_uns;
21567 rtx_2func_t from_di_sign;
21568 rtx_2func_t from_di_uns;
21571 rtx_2func_t to_si_sign;
21572 rtx_2func_t to_si_uns;
21573 rtx_2func_t to_di_sign;
21574 rtx_2func_t to_di_uns;
21575 } hw_conversions[2] = {
21576 /* convertions to/from KFmode */
21578 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21579 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21580 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21581 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21582 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21583 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21584 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21585 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21586 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21587 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21588 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21589 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21592 /* convertions to/from TFmode */
21594 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21595 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21596 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21597 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21598 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21599 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21600 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21601 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21602 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21603 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21604 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21605 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21609 if (dest_mode == src_mode)
21610 gcc_unreachable ();
21612 /* Eliminate memory operations. */
21614 src = force_reg (src_mode, src);
21618 rtx tmp = gen_reg_rtx (dest_mode);
21619 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21620 rs6000_emit_move (dest, tmp, dest_mode);
21624 /* Convert to IEEE 128-bit floating point. */
21625 if (FLOAT128_IEEE_P (dest_mode))
21627 if (dest_mode == KFmode)
21629 else if (dest_mode == TFmode)
21632 gcc_unreachable ();
21638 hw_convert = hw_conversions[kf_or_tf].from_df;
21643 hw_convert = hw_conversions[kf_or_tf].from_sf;
21649 if (FLOAT128_IBM_P (src_mode))
21658 cvt = ufloat_optab;
21659 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21663 cvt = sfloat_optab;
21664 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21671 cvt = ufloat_optab;
21672 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21676 cvt = sfloat_optab;
21677 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21682 gcc_unreachable ();
21686 /* Convert from IEEE 128-bit floating point. */
21687 else if (FLOAT128_IEEE_P (src_mode))
21689 if (src_mode == KFmode)
21691 else if (src_mode == TFmode)
21694 gcc_unreachable ();
21700 hw_convert = hw_conversions[kf_or_tf].to_df;
21705 hw_convert = hw_conversions[kf_or_tf].to_sf;
21711 if (FLOAT128_IBM_P (dest_mode))
21721 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
21726 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
21734 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
21739 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
21744 gcc_unreachable ();
21748 /* Both IBM format. */
21749 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
21753 gcc_unreachable ();
21755 /* Handle conversion between TFmode/KFmode/IFmode. */
21757 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
21759 /* Handle conversion if we have hardware support. */
21760 else if (TARGET_FLOAT128_HW && hw_convert)
21761 emit_insn ((hw_convert) (dest, src));
21763 /* Call an external function to do the conversion. */
21764 else if (cvt != unknown_optab)
21766 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
21767 gcc_assert (libfunc != NULL_RTX);
21769 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
21772 gcc_assert (dest2 != NULL_RTX);
21773 if (!rtx_equal_p (dest, dest2))
21774 emit_move_insn (dest, dest2);
21778 gcc_unreachable ();
21784 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
21785 can be used as that dest register. Return the dest register. */
21788 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
21790 if (op2 == const0_rtx)
21793 if (GET_CODE (scratch) == SCRATCH)
21794 scratch = gen_reg_rtx (mode);
21796 if (logical_operand (op2, mode))
21797 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
21799 emit_insn (gen_rtx_SET (scratch,
21800 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
21806 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
21809 machine_mode op_mode;
21810 enum rtx_code cond_code;
21811 rtx result = operands[0];
21813 condition_rtx = rs6000_generate_compare (operands[1], mode);
21814 cond_code = GET_CODE (condition_rtx);
21816 if (cond_code == NE
21817 || cond_code == GE || cond_code == LE
21818 || cond_code == GEU || cond_code == LEU
21819 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
21821 rtx not_result = gen_reg_rtx (CCEQmode);
21822 rtx not_op, rev_cond_rtx;
21823 machine_mode cc_mode;
21825 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
21827 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
21828 SImode, XEXP (condition_rtx, 0), const0_rtx);
21829 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
21830 emit_insn (gen_rtx_SET (not_result, not_op));
21831 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
21834 op_mode = GET_MODE (XEXP (operands[1], 0));
21835 if (op_mode == VOIDmode)
21836 op_mode = GET_MODE (XEXP (operands[1], 1));
21838 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
21840 PUT_MODE (condition_rtx, DImode);
21841 convert_move (result, condition_rtx, 0);
21845 PUT_MODE (condition_rtx, SImode);
21846 emit_insn (gen_rtx_SET (result, condition_rtx));
21850 /* Emit a branch of kind CODE to location LOC. */
21853 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
21855 rtx condition_rtx, loc_ref;
21857 condition_rtx = rs6000_generate_compare (operands[0], mode);
21858 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
21859 emit_jump_insn (gen_rtx_SET (pc_rtx,
21860 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
21861 loc_ref, pc_rtx)));
21864 /* Return the string to output a conditional branch to LABEL, which is
21865 the operand template of the label, or NULL if the branch is really a
21866 conditional return.
21868 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
21869 condition code register and its mode specifies what kind of
21870 comparison we made.
21872 REVERSED is nonzero if we should reverse the sense of the comparison.
21874 INSN is the insn. */
21877 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
21879 static char string[64];
21880 enum rtx_code code = GET_CODE (op);
21881 rtx cc_reg = XEXP (op, 0);
21882 machine_mode mode = GET_MODE (cc_reg);
21883 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
21884 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
21885 int really_reversed = reversed ^ need_longbranch;
21891 validate_condition_mode (code, mode);
21893 /* Work out which way this really branches. We could use
21894 reverse_condition_maybe_unordered here always but this
21895 makes the resulting assembler clearer. */
21896 if (really_reversed)
21898 /* Reversal of FP compares takes care -- an ordered compare
21899 becomes an unordered compare and vice versa. */
21900 if (mode == CCFPmode)
21901 code = reverse_condition_maybe_unordered (code);
21903 code = reverse_condition (code);
21908 /* Not all of these are actually distinct opcodes, but
21909 we distinguish them for clarity of the resulting assembler. */
21910 case NE: case LTGT:
21911 ccode = "ne"; break;
21912 case EQ: case UNEQ:
21913 ccode = "eq"; break;
21915 ccode = "ge"; break;
21916 case GT: case GTU: case UNGT:
21917 ccode = "gt"; break;
21919 ccode = "le"; break;
21920 case LT: case LTU: case UNLT:
21921 ccode = "lt"; break;
21922 case UNORDERED: ccode = "un"; break;
21923 case ORDERED: ccode = "nu"; break;
21924 case UNGE: ccode = "nl"; break;
21925 case UNLE: ccode = "ng"; break;
21927 gcc_unreachable ();
21930 /* Maybe we have a guess as to how likely the branch is. */
21932 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
21933 if (note != NULL_RTX)
21935 /* PROB is the difference from 50%. */
21936 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
21937 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
21939 /* Only hint for highly probable/improbable branches on newer cpus when
21940 we have real profile data, as static prediction overrides processor
21941 dynamic prediction. For older cpus we may as well always hint, but
21942 assume not taken for branches that are very close to 50% as a
21943 mispredicted taken branch is more expensive than a
21944 mispredicted not-taken branch. */
21945 if (rs6000_always_hint
21946 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
21947 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
21948 && br_prob_note_reliable_p (note)))
21950 if (abs (prob) > REG_BR_PROB_BASE / 20
21951 && ((prob > 0) ^ need_longbranch))
21959 s += sprintf (s, "b%slr%s ", ccode, pred);
21961 s += sprintf (s, "b%s%s ", ccode, pred);
21963 /* We need to escape any '%' characters in the reg_names string.
21964 Assume they'd only be the first character.... */
21965 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
21967 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
21971 /* If the branch distance was too far, we may have to use an
21972 unconditional branch to go the distance. */
21973 if (need_longbranch)
21974 s += sprintf (s, ",$+8\n\tb %s", label);
21976 s += sprintf (s, ",%s", label);
21982 /* Return insn for VSX or Altivec comparisons. */
21985 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
21988 machine_mode mode = GET_MODE (op0);
21996 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22007 mask = gen_reg_rtx (mode);
22008 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22015 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22016 DMODE is expected destination mode. This is a recursive function. */
22019 rs6000_emit_vector_compare (enum rtx_code rcode,
22021 machine_mode dmode)
22024 bool swap_operands = false;
22025 bool try_again = false;
22027 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22028 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22030 /* See if the comparison works as is. */
22031 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22039 swap_operands = true;
22044 swap_operands = true;
22052 /* Invert condition and try again.
22053 e.g., A != B becomes ~(A==B). */
22055 enum rtx_code rev_code;
22056 enum insn_code nor_code;
22059 rev_code = reverse_condition_maybe_unordered (rcode);
22060 if (rev_code == UNKNOWN)
22063 nor_code = optab_handler (one_cmpl_optab, dmode);
22064 if (nor_code == CODE_FOR_nothing)
22067 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22071 mask = gen_reg_rtx (dmode);
22072 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22080 /* Try GT/GTU/LT/LTU OR EQ */
22083 enum insn_code ior_code;
22084 enum rtx_code new_code;
22105 gcc_unreachable ();
22108 ior_code = optab_handler (ior_optab, dmode);
22109 if (ior_code == CODE_FOR_nothing)
22112 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22116 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22120 mask = gen_reg_rtx (dmode);
22121 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22132 std::swap (op0, op1);
22134 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22139 /* You only get two chances. */
22143 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22144 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22145 operands for the relation operation COND. */
22148 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22149 rtx cond, rtx cc_op0, rtx cc_op1)
22151 machine_mode dest_mode = GET_MODE (dest);
22152 machine_mode mask_mode = GET_MODE (cc_op0);
22153 enum rtx_code rcode = GET_CODE (cond);
22154 machine_mode cc_mode = CCmode;
22157 bool invert_move = false;
22159 if (VECTOR_UNIT_NONE_P (dest_mode))
22162 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22163 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22167 /* Swap operands if we can, and fall back to doing the operation as
22168 specified, and doing a NOR to invert the test. */
22174 /* Invert condition and try again.
22175 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22176 invert_move = true;
22177 rcode = reverse_condition_maybe_unordered (rcode);
22178 if (rcode == UNKNOWN)
22184 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22186 /* Invert condition to avoid compound test. */
22187 invert_move = true;
22188 rcode = reverse_condition (rcode);
22196 /* Mark unsigned tests with CCUNSmode. */
22197 cc_mode = CCUNSmode;
22199 /* Invert condition to avoid compound test if necessary. */
22200 if (rcode == GEU || rcode == LEU)
22202 invert_move = true;
22203 rcode = reverse_condition (rcode);
22211 /* Get the vector mask for the given relational operations. */
22212 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22218 std::swap (op_true, op_false);
22220 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22221 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22222 && (GET_CODE (op_true) == CONST_VECTOR
22223 || GET_CODE (op_false) == CONST_VECTOR))
22225 rtx constant_0 = CONST0_RTX (dest_mode);
22226 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22228 if (op_true == constant_m1 && op_false == constant_0)
22230 emit_move_insn (dest, mask);
22234 else if (op_true == constant_0 && op_false == constant_m1)
22236 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22240 /* If we can't use the vector comparison directly, perhaps we can use
22241 the mask for the true or false fields, instead of loading up a
22243 if (op_true == constant_m1)
22246 if (op_false == constant_0)
22250 if (!REG_P (op_true) && !SUBREG_P (op_true))
22251 op_true = force_reg (dest_mode, op_true);
22253 if (!REG_P (op_false) && !SUBREG_P (op_false))
22254 op_false = force_reg (dest_mode, op_false);
22256 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22257 CONST0_RTX (dest_mode));
22258 emit_insn (gen_rtx_SET (dest,
22259 gen_rtx_IF_THEN_ELSE (dest_mode,
22266 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22267 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22268 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22269 hardware has no such operation. */
22272 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22274 enum rtx_code code = GET_CODE (op);
22275 rtx op0 = XEXP (op, 0);
22276 rtx op1 = XEXP (op, 1);
22277 machine_mode compare_mode = GET_MODE (op0);
22278 machine_mode result_mode = GET_MODE (dest);
22279 bool max_p = false;
22281 if (result_mode != compare_mode)
22284 if (code == GE || code == GT)
22286 else if (code == LE || code == LT)
22291 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22294 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22300 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22304 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22305 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22306 operands of the last comparison is nonzero/true, FALSE_COND if it is
22307 zero/false. Return 0 if the hardware has no such operation. */
22310 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22312 enum rtx_code code = GET_CODE (op);
22313 rtx op0 = XEXP (op, 0);
22314 rtx op1 = XEXP (op, 1);
22315 machine_mode result_mode = GET_MODE (dest);
22320 if (!can_create_pseudo_p ())
22333 code = swap_condition (code);
22334 std::swap (op0, op1);
22341 /* Generate: [(parallel [(set (dest)
22342 (if_then_else (op (cmp1) (cmp2))
22345 (clobber (scratch))])]. */
22347 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22348 cmove_rtx = gen_rtx_SET (dest,
22349 gen_rtx_IF_THEN_ELSE (result_mode,
22354 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22355 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22356 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22361 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22362 operands of the last comparison is nonzero/true, FALSE_COND if it
22363 is zero/false. Return 0 if the hardware has no such operation. */
22366 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22368 enum rtx_code code = GET_CODE (op);
22369 rtx op0 = XEXP (op, 0);
22370 rtx op1 = XEXP (op, 1);
22371 machine_mode compare_mode = GET_MODE (op0);
22372 machine_mode result_mode = GET_MODE (dest);
22374 bool is_against_zero;
22376 /* These modes should always match. */
22377 if (GET_MODE (op1) != compare_mode
22378 /* In the isel case however, we can use a compare immediate, so
22379 op1 may be a small constant. */
22380 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22382 if (GET_MODE (true_cond) != result_mode)
22384 if (GET_MODE (false_cond) != result_mode)
22387 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22388 if (TARGET_P9_MINMAX
22389 && (compare_mode == SFmode || compare_mode == DFmode)
22390 && (result_mode == SFmode || result_mode == DFmode))
22392 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22395 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22399 /* Don't allow using floating point comparisons for integer results for
22401 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22404 /* First, work out if the hardware can do this at all, or
22405 if it's too slow.... */
22406 if (!FLOAT_MODE_P (compare_mode))
22409 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22413 is_against_zero = op1 == CONST0_RTX (compare_mode);
22415 /* A floating-point subtract might overflow, underflow, or produce
22416 an inexact result, thus changing the floating-point flags, so it
22417 can't be generated if we care about that. It's safe if one side
22418 of the construct is zero, since then no subtract will be
22420 if (SCALAR_FLOAT_MODE_P (compare_mode)
22421 && flag_trapping_math && ! is_against_zero)
22424 /* Eliminate half of the comparisons by switching operands, this
22425 makes the remaining code simpler. */
22426 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22427 || code == LTGT || code == LT || code == UNLE)
22429 code = reverse_condition_maybe_unordered (code);
22431 true_cond = false_cond;
22435 /* UNEQ and LTGT take four instructions for a comparison with zero,
22436 it'll probably be faster to use a branch here too. */
22437 if (code == UNEQ && HONOR_NANS (compare_mode))
22440 /* We're going to try to implement comparisons by performing
22441 a subtract, then comparing against zero. Unfortunately,
22442 Inf - Inf is NaN which is not zero, and so if we don't
22443 know that the operand is finite and the comparison
22444 would treat EQ different to UNORDERED, we can't do it. */
22445 if (HONOR_INFINITIES (compare_mode)
22446 && code != GT && code != UNGE
22447 && (GET_CODE (op1) != CONST_DOUBLE
22448 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22449 /* Constructs of the form (a OP b ? a : b) are safe. */
22450 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22451 || (! rtx_equal_p (op0, true_cond)
22452 && ! rtx_equal_p (op1, true_cond))))
22455 /* At this point we know we can use fsel. */
22457 /* Reduce the comparison to a comparison against zero. */
22458 if (! is_against_zero)
22460 temp = gen_reg_rtx (compare_mode);
22461 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22463 op1 = CONST0_RTX (compare_mode);
22466 /* If we don't care about NaNs we can reduce some of the comparisons
22467 down to faster ones. */
22468 if (! HONOR_NANS (compare_mode))
22474 true_cond = false_cond;
22487 /* Now, reduce everything down to a GE. */
22494 temp = gen_reg_rtx (compare_mode);
22495 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22500 temp = gen_reg_rtx (compare_mode);
22501 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22506 temp = gen_reg_rtx (compare_mode);
22507 emit_insn (gen_rtx_SET (temp,
22508 gen_rtx_NEG (compare_mode,
22509 gen_rtx_ABS (compare_mode, op0))));
22514 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22515 temp = gen_reg_rtx (result_mode);
22516 emit_insn (gen_rtx_SET (temp,
22517 gen_rtx_IF_THEN_ELSE (result_mode,
22518 gen_rtx_GE (VOIDmode,
22520 true_cond, false_cond)));
22521 false_cond = true_cond;
22524 temp = gen_reg_rtx (compare_mode);
22525 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22530 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22531 temp = gen_reg_rtx (result_mode);
22532 emit_insn (gen_rtx_SET (temp,
22533 gen_rtx_IF_THEN_ELSE (result_mode,
22534 gen_rtx_GE (VOIDmode,
22536 true_cond, false_cond)));
22537 true_cond = false_cond;
22540 temp = gen_reg_rtx (compare_mode);
22541 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22546 gcc_unreachable ();
22549 emit_insn (gen_rtx_SET (dest,
22550 gen_rtx_IF_THEN_ELSE (result_mode,
22551 gen_rtx_GE (VOIDmode,
22553 true_cond, false_cond)));
22557 /* Same as above, but for ints (isel). */
22560 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22562 rtx condition_rtx, cr;
22563 machine_mode mode = GET_MODE (dest);
22564 enum rtx_code cond_code;
22565 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22568 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22571 /* We still have to do the compare, because isel doesn't do a
22572 compare, it just looks at the CRx bits set by a previous compare
22574 condition_rtx = rs6000_generate_compare (op, mode);
22575 cond_code = GET_CODE (condition_rtx);
22576 cr = XEXP (condition_rtx, 0);
22577 signedp = GET_MODE (cr) == CCmode;
22579 isel_func = (mode == SImode
22580 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22581 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22585 case LT: case GT: case LTU: case GTU: case EQ:
22586 /* isel handles these directly. */
22590 /* We need to swap the sense of the comparison. */
22592 std::swap (false_cond, true_cond);
22593 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22598 false_cond = force_reg (mode, false_cond);
22599 if (true_cond != const0_rtx)
22600 true_cond = force_reg (mode, true_cond);
22602 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22608 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22610 machine_mode mode = GET_MODE (op0);
22614 /* VSX/altivec have direct min/max insns. */
22615 if ((code == SMAX || code == SMIN)
22616 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22617 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22619 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22623 if (code == SMAX || code == SMIN)
22628 if (code == SMAX || code == UMAX)
22629 target = emit_conditional_move (dest, c, op0, op1, mode,
22630 op0, op1, mode, 0);
22632 target = emit_conditional_move (dest, c, op0, op1, mode,
22633 op1, op0, mode, 0);
22634 gcc_assert (target);
22635 if (target != dest)
22636 emit_move_insn (dest, target);
22639 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22640 COND is true. Mark the jump as unlikely to be taken. */
22643 emit_unlikely_jump (rtx cond, rtx label)
22645 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22646 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22647 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22650 /* A subroutine of the atomic operation splitters. Emit a load-locked
22651 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22652 the zero_extend operation. */
22655 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22657 rtx (*fn) (rtx, rtx) = NULL;
22662 fn = gen_load_lockedqi;
22665 fn = gen_load_lockedhi;
22668 if (GET_MODE (mem) == QImode)
22669 fn = gen_load_lockedqi_si;
22670 else if (GET_MODE (mem) == HImode)
22671 fn = gen_load_lockedhi_si;
22673 fn = gen_load_lockedsi;
22676 fn = gen_load_lockeddi;
22679 fn = gen_load_lockedti;
22682 gcc_unreachable ();
22684 emit_insn (fn (reg, mem));
22687 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22688 instruction in MODE. */
22691 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
22693 rtx (*fn) (rtx, rtx, rtx) = NULL;
22698 fn = gen_store_conditionalqi;
22701 fn = gen_store_conditionalhi;
22704 fn = gen_store_conditionalsi;
22707 fn = gen_store_conditionaldi;
22710 fn = gen_store_conditionalti;
22713 gcc_unreachable ();
22716 /* Emit sync before stwcx. to address PPC405 Erratum. */
22717 if (PPC405_ERRATUM77)
22718 emit_insn (gen_hwsync ());
22720 emit_insn (fn (res, mem, val));
22723 /* Expand barriers before and after a load_locked/store_cond sequence. */
22726 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
22728 rtx addr = XEXP (mem, 0);
22730 if (!legitimate_indirect_address_p (addr, reload_completed)
22731 && !legitimate_indexed_address_p (addr, reload_completed))
22733 addr = force_reg (Pmode, addr);
22734 mem = replace_equiv_address_nv (mem, addr);
22739 case MEMMODEL_RELAXED:
22740 case MEMMODEL_CONSUME:
22741 case MEMMODEL_ACQUIRE:
22743 case MEMMODEL_RELEASE:
22744 case MEMMODEL_ACQ_REL:
22745 emit_insn (gen_lwsync ());
22747 case MEMMODEL_SEQ_CST:
22748 emit_insn (gen_hwsync ());
22751 gcc_unreachable ();
22757 rs6000_post_atomic_barrier (enum memmodel model)
22761 case MEMMODEL_RELAXED:
22762 case MEMMODEL_CONSUME:
22763 case MEMMODEL_RELEASE:
22765 case MEMMODEL_ACQUIRE:
22766 case MEMMODEL_ACQ_REL:
22767 case MEMMODEL_SEQ_CST:
22768 emit_insn (gen_isync ());
22771 gcc_unreachable ();
22775 /* A subroutine of the various atomic expanders. For sub-word operations,
22776 we must adjust things to operate on SImode. Given the original MEM,
22777 return a new aligned memory. Also build and return the quantities by
22778 which to shift and mask. */
22781 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
22783 rtx addr, align, shift, mask, mem;
22784 HOST_WIDE_INT shift_mask;
22785 machine_mode mode = GET_MODE (orig_mem);
22787 /* For smaller modes, we have to implement this via SImode. */
22788 shift_mask = (mode == QImode ? 0x18 : 0x10);
22790 addr = XEXP (orig_mem, 0);
22791 addr = force_reg (GET_MODE (addr), addr);
22793 /* Aligned memory containing subword. Generate a new memory. We
22794 do not want any of the existing MEM_ATTR data, as we're now
22795 accessing memory outside the original object. */
22796 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
22797 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22798 mem = gen_rtx_MEM (SImode, align);
22799 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
22800 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
22801 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
22803 /* Shift amount for subword relative to aligned word. */
22804 shift = gen_reg_rtx (SImode);
22805 addr = gen_lowpart (SImode, addr);
22806 rtx tmp = gen_reg_rtx (SImode);
22807 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
22808 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
22809 if (BYTES_BIG_ENDIAN)
22810 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
22811 shift, 1, OPTAB_LIB_WIDEN);
22814 /* Mask for insertion. */
22815 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
22816 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
22822 /* A subroutine of the various atomic expanders. For sub-word operands,
22823 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
22826 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
22830 x = gen_reg_rtx (SImode);
22831 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
22832 gen_rtx_NOT (SImode, mask),
22835 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
22840 /* A subroutine of the various atomic expanders. For sub-word operands,
22841 extract WIDE to NARROW via SHIFT. */
22844 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
22846 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
22847 wide, 1, OPTAB_LIB_WIDEN);
22848 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
22851 /* Expand an atomic compare and swap operation. */
22854 rs6000_expand_atomic_compare_and_swap (rtx operands[])
22856 rtx boolval, retval, mem, oldval, newval, cond;
22857 rtx label1, label2, x, mask, shift;
22858 machine_mode mode, orig_mode;
22859 enum memmodel mod_s, mod_f;
22862 boolval = operands[0];
22863 retval = operands[1];
22865 oldval = operands[3];
22866 newval = operands[4];
22867 is_weak = (INTVAL (operands[5]) != 0);
22868 mod_s = memmodel_base (INTVAL (operands[6]));
22869 mod_f = memmodel_base (INTVAL (operands[7]));
22870 orig_mode = mode = GET_MODE (mem);
22872 mask = shift = NULL_RTX;
22873 if (mode == QImode || mode == HImode)
22875 /* Before power8, we didn't have access to lbarx/lharx, so generate a
22876 lwarx and shift/mask operations. With power8, we need to do the
22877 comparison in SImode, but the store is still done in QI/HImode. */
22878 oldval = convert_modes (SImode, mode, oldval, 1);
22880 if (!TARGET_SYNC_HI_QI)
22882 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
22884 /* Shift and mask OLDVAL into position with the word. */
22885 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
22886 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22888 /* Shift and mask NEWVAL into position within the word. */
22889 newval = convert_modes (SImode, mode, newval, 1);
22890 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
22891 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22894 /* Prepare to adjust the return value. */
22895 retval = gen_reg_rtx (SImode);
22898 else if (reg_overlap_mentioned_p (retval, oldval))
22899 oldval = copy_to_reg (oldval);
22901 if (mode != TImode && !reg_or_short_operand (oldval, mode))
22902 oldval = copy_to_mode_reg (mode, oldval);
22904 if (reg_overlap_mentioned_p (retval, newval))
22905 newval = copy_to_reg (newval);
22907 mem = rs6000_pre_atomic_barrier (mem, mod_s);
22912 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
22913 emit_label (XEXP (label1, 0));
22915 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
22917 emit_load_locked (mode, retval, mem);
22921 x = expand_simple_binop (SImode, AND, retval, mask,
22922 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22924 cond = gen_reg_rtx (CCmode);
22925 /* If we have TImode, synthesize a comparison. */
22926 if (mode != TImode)
22927 x = gen_rtx_COMPARE (CCmode, x, oldval);
22930 rtx xor1_result = gen_reg_rtx (DImode);
22931 rtx xor2_result = gen_reg_rtx (DImode);
22932 rtx or_result = gen_reg_rtx (DImode);
22933 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
22934 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
22935 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
22936 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
22938 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
22939 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
22940 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
22941 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
22944 emit_insn (gen_rtx_SET (cond, x));
22946 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
22947 emit_unlikely_jump (x, label2);
22951 x = rs6000_mask_atomic_subword (retval, newval, mask);
22953 emit_store_conditional (orig_mode, cond, mem, x);
22957 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
22958 emit_unlikely_jump (x, label1);
22961 if (!is_mm_relaxed (mod_f))
22962 emit_label (XEXP (label2, 0));
22964 rs6000_post_atomic_barrier (mod_s);
22966 if (is_mm_relaxed (mod_f))
22967 emit_label (XEXP (label2, 0));
22970 rs6000_finish_atomic_subword (operands[1], retval, shift);
22971 else if (mode != GET_MODE (operands[1]))
22972 convert_move (operands[1], retval, 1);
22974 /* In all cases, CR0 contains EQ on success, and NE on failure. */
22975 x = gen_rtx_EQ (SImode, cond, const0_rtx);
22976 emit_insn (gen_rtx_SET (boolval, x));
22979 /* Expand an atomic exchange operation. */
22982 rs6000_expand_atomic_exchange (rtx operands[])
22984 rtx retval, mem, val, cond;
22986 enum memmodel model;
22987 rtx label, x, mask, shift;
22989 retval = operands[0];
22992 model = memmodel_base (INTVAL (operands[3]));
22993 mode = GET_MODE (mem);
22995 mask = shift = NULL_RTX;
22996 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
22998 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23000 /* Shift and mask VAL into position with the word. */
23001 val = convert_modes (SImode, mode, val, 1);
23002 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23003 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23005 /* Prepare to adjust the return value. */
23006 retval = gen_reg_rtx (SImode);
23010 mem = rs6000_pre_atomic_barrier (mem, model);
23012 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23013 emit_label (XEXP (label, 0));
23015 emit_load_locked (mode, retval, mem);
23019 x = rs6000_mask_atomic_subword (retval, val, mask);
23021 cond = gen_reg_rtx (CCmode);
23022 emit_store_conditional (mode, cond, mem, x);
23024 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23025 emit_unlikely_jump (x, label);
23027 rs6000_post_atomic_barrier (model);
23030 rs6000_finish_atomic_subword (operands[0], retval, shift);
23033 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23034 to perform. MEM is the memory on which to operate. VAL is the second
23035 operand of the binary operator. BEFORE and AFTER are optional locations to
23036 return the value of MEM either before of after the operation. MODEL_RTX
23037 is a CONST_INT containing the memory model to use. */
23040 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23041 rtx orig_before, rtx orig_after, rtx model_rtx)
23043 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23044 machine_mode mode = GET_MODE (mem);
23045 machine_mode store_mode = mode;
23046 rtx label, x, cond, mask, shift;
23047 rtx before = orig_before, after = orig_after;
23049 mask = shift = NULL_RTX;
23050 /* On power8, we want to use SImode for the operation. On previous systems,
23051 use the operation in a subword and shift/mask to get the proper byte or
23053 if (mode == QImode || mode == HImode)
23055 if (TARGET_SYNC_HI_QI)
23057 val = convert_modes (SImode, mode, val, 1);
23059 /* Prepare to adjust the return value. */
23060 before = gen_reg_rtx (SImode);
23062 after = gen_reg_rtx (SImode);
23067 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23069 /* Shift and mask VAL into position with the word. */
23070 val = convert_modes (SImode, mode, val, 1);
23071 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23072 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23078 /* We've already zero-extended VAL. That is sufficient to
23079 make certain that it does not affect other bits. */
23084 /* If we make certain that all of the other bits in VAL are
23085 set, that will be sufficient to not affect other bits. */
23086 x = gen_rtx_NOT (SImode, mask);
23087 x = gen_rtx_IOR (SImode, x, val);
23088 emit_insn (gen_rtx_SET (val, x));
23095 /* These will all affect bits outside the field and need
23096 adjustment via MASK within the loop. */
23100 gcc_unreachable ();
23103 /* Prepare to adjust the return value. */
23104 before = gen_reg_rtx (SImode);
23106 after = gen_reg_rtx (SImode);
23107 store_mode = mode = SImode;
23111 mem = rs6000_pre_atomic_barrier (mem, model);
23113 label = gen_label_rtx ();
23114 emit_label (label);
23115 label = gen_rtx_LABEL_REF (VOIDmode, label);
23117 if (before == NULL_RTX)
23118 before = gen_reg_rtx (mode);
23120 emit_load_locked (mode, before, mem);
23124 x = expand_simple_binop (mode, AND, before, val,
23125 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23126 after = expand_simple_unop (mode, NOT, x, after, 1);
23130 after = expand_simple_binop (mode, code, before, val,
23131 after, 1, OPTAB_LIB_WIDEN);
23137 x = expand_simple_binop (SImode, AND, after, mask,
23138 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23139 x = rs6000_mask_atomic_subword (before, x, mask);
23141 else if (store_mode != mode)
23142 x = convert_modes (store_mode, mode, x, 1);
23144 cond = gen_reg_rtx (CCmode);
23145 emit_store_conditional (store_mode, cond, mem, x);
23147 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23148 emit_unlikely_jump (x, label);
23150 rs6000_post_atomic_barrier (model);
23154 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23155 then do the calcuations in a SImode register. */
23157 rs6000_finish_atomic_subword (orig_before, before, shift);
23159 rs6000_finish_atomic_subword (orig_after, after, shift);
23161 else if (store_mode != mode)
23163 /* QImode/HImode on machines with lbarx/lharx where we do the native
23164 operation and then do the calcuations in a SImode register. */
23166 convert_move (orig_before, before, 1);
23168 convert_move (orig_after, after, 1);
23170 else if (orig_after && after != orig_after)
23171 emit_move_insn (orig_after, after);
23174 /* Emit instructions to move SRC to DST. Called by splitters for
23175 multi-register moves. It will emit at most one instruction for
23176 each register that is accessed; that is, it won't emit li/lis pairs
23177 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23181 rs6000_split_multireg_move (rtx dst, rtx src)
23183 /* The register number of the first register being moved. */
23185 /* The mode that is to be moved. */
23187 /* The mode that the move is being done in, and its size. */
23188 machine_mode reg_mode;
23190 /* The number of registers that will be moved. */
23193 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23194 mode = GET_MODE (dst);
23195 nregs = hard_regno_nregs (reg, mode);
23196 if (FP_REGNO_P (reg))
23197 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23198 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23199 else if (ALTIVEC_REGNO_P (reg))
23200 reg_mode = V16QImode;
23202 reg_mode = word_mode;
23203 reg_mode_size = GET_MODE_SIZE (reg_mode);
23205 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23207 /* TDmode residing in FP registers is special, since the ISA requires that
23208 the lower-numbered word of a register pair is always the most significant
23209 word, even in little-endian mode. This does not match the usual subreg
23210 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23211 the appropriate constituent registers "by hand" in little-endian mode.
23213 Note we do not need to check for destructive overlap here since TDmode
23214 can only reside in even/odd register pairs. */
23215 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23220 for (i = 0; i < nregs; i++)
23222 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23223 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23225 p_src = simplify_gen_subreg (reg_mode, src, mode,
23226 i * reg_mode_size);
23228 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23229 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23231 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23232 i * reg_mode_size);
23234 emit_insn (gen_rtx_SET (p_dst, p_src));
23240 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23242 /* Move register range backwards, if we might have destructive
23245 for (i = nregs - 1; i >= 0; i--)
23246 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23247 i * reg_mode_size),
23248 simplify_gen_subreg (reg_mode, src, mode,
23249 i * reg_mode_size)));
23255 bool used_update = false;
23256 rtx restore_basereg = NULL_RTX;
23258 if (MEM_P (src) && INT_REGNO_P (reg))
23262 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23263 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23266 breg = XEXP (XEXP (src, 0), 0);
23267 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23268 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23269 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23270 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23271 src = replace_equiv_address (src, breg);
23273 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23275 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23277 rtx basereg = XEXP (XEXP (src, 0), 0);
23280 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23281 emit_insn (gen_rtx_SET (ndst,
23282 gen_rtx_MEM (reg_mode,
23284 used_update = true;
23287 emit_insn (gen_rtx_SET (basereg,
23288 XEXP (XEXP (src, 0), 1)));
23289 src = replace_equiv_address (src, basereg);
23293 rtx basereg = gen_rtx_REG (Pmode, reg);
23294 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23295 src = replace_equiv_address (src, basereg);
23299 breg = XEXP (src, 0);
23300 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23301 breg = XEXP (breg, 0);
23303 /* If the base register we are using to address memory is
23304 also a destination reg, then change that register last. */
23306 && REGNO (breg) >= REGNO (dst)
23307 && REGNO (breg) < REGNO (dst) + nregs)
23308 j = REGNO (breg) - REGNO (dst);
23310 else if (MEM_P (dst) && INT_REGNO_P (reg))
23314 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23315 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23318 breg = XEXP (XEXP (dst, 0), 0);
23319 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23320 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23321 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23323 /* We have to update the breg before doing the store.
23324 Use store with update, if available. */
23328 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23329 emit_insn (TARGET_32BIT
23330 ? (TARGET_POWERPC64
23331 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23332 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
23333 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23334 used_update = true;
23337 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23338 dst = replace_equiv_address (dst, breg);
23340 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23341 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23343 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23345 rtx basereg = XEXP (XEXP (dst, 0), 0);
23348 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23349 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23352 used_update = true;
23355 emit_insn (gen_rtx_SET (basereg,
23356 XEXP (XEXP (dst, 0), 1)));
23357 dst = replace_equiv_address (dst, basereg);
23361 rtx basereg = XEXP (XEXP (dst, 0), 0);
23362 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23363 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23365 && REG_P (offsetreg)
23366 && REGNO (basereg) != REGNO (offsetreg));
23367 if (REGNO (basereg) == 0)
23369 rtx tmp = offsetreg;
23370 offsetreg = basereg;
23373 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23374 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23375 dst = replace_equiv_address (dst, basereg);
23378 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23379 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23382 for (i = 0; i < nregs; i++)
23384 /* Calculate index to next subword. */
23389 /* If compiler already emitted move of first word by
23390 store with update, no need to do anything. */
23391 if (j == 0 && used_update)
23394 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23395 j * reg_mode_size),
23396 simplify_gen_subreg (reg_mode, src, mode,
23397 j * reg_mode_size)));
23399 if (restore_basereg != NULL_RTX)
23400 emit_insn (restore_basereg);
23405 /* This page contains routines that are used to determine what the
23406 function prologue and epilogue code will do and write them out. */
23408 /* Determine whether the REG is really used. */
23411 save_reg_p (int reg)
23413 /* We need to mark the PIC offset register live for the same conditions
23414 as it is set up, or otherwise it won't be saved before we clobber it. */
23416 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23418 /* When calling eh_return, we must return true for all the cases
23419 where conditional_register_usage marks the PIC offset reg
23421 if (TARGET_TOC && TARGET_MINIMAL_TOC
23422 && (crtl->calls_eh_return
23423 || df_regs_ever_live_p (reg)
23424 || !constant_pool_empty_p ()))
23427 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
23432 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23435 /* Return the first fixed-point register that is required to be
23436 saved. 32 if none. */
23439 first_reg_to_save (void)
23443 /* Find lowest numbered live register. */
23444 for (first_reg = 13; first_reg <= 31; first_reg++)
23445 if (save_reg_p (first_reg))
23450 && crtl->uses_pic_offset_table
23451 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
23452 return RS6000_PIC_OFFSET_TABLE_REGNUM;
23458 /* Similar, for FP regs. */
23461 first_fp_reg_to_save (void)
23465 /* Find lowest numbered live register. */
23466 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23467 if (save_reg_p (first_reg))
23473 /* Similar, for AltiVec regs. */
23476 first_altivec_reg_to_save (void)
23480 /* Stack frame remains as is unless we are in AltiVec ABI. */
23481 if (! TARGET_ALTIVEC_ABI)
23482 return LAST_ALTIVEC_REGNO + 1;
23484 /* On Darwin, the unwind routines are compiled without
23485 TARGET_ALTIVEC, and use save_world to save/restore the
23486 altivec registers when necessary. */
23487 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23488 && ! TARGET_ALTIVEC)
23489 return FIRST_ALTIVEC_REGNO + 20;
23491 /* Find lowest numbered live register. */
23492 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23493 if (save_reg_p (i))
23499 /* Return a 32-bit mask of the AltiVec registers we need to set in
23500 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23501 the 32-bit word is 0. */
23503 static unsigned int
23504 compute_vrsave_mask (void)
23506 unsigned int i, mask = 0;
23508 /* On Darwin, the unwind routines are compiled without
23509 TARGET_ALTIVEC, and use save_world to save/restore the
23510 call-saved altivec registers when necessary. */
23511 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23512 && ! TARGET_ALTIVEC)
23515 /* First, find out if we use _any_ altivec registers. */
23516 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23517 if (df_regs_ever_live_p (i))
23518 mask |= ALTIVEC_REG_BIT (i);
23523 /* Next, remove the argument registers from the set. These must
23524 be in the VRSAVE mask set by the caller, so we don't need to add
23525 them in again. More importantly, the mask we compute here is
23526 used to generate CLOBBERs in the set_vrsave insn, and we do not
23527 wish the argument registers to die. */
23528 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23529 mask &= ~ALTIVEC_REG_BIT (i);
23531 /* Similarly, remove the return value from the set. */
23534 diddle_return_value (is_altivec_return_reg, &yes);
23536 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23542 /* For a very restricted set of circumstances, we can cut down the
23543 size of prologues/epilogues by calling our own save/restore-the-world
23547 compute_save_world_info (rs6000_stack_t *info)
23549 info->world_save_p = 1;
23551 = (WORLD_SAVE_P (info)
23552 && DEFAULT_ABI == ABI_DARWIN
23553 && !cfun->has_nonlocal_label
23554 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23555 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23556 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23557 && info->cr_save_p);
23559 /* This will not work in conjunction with sibcalls. Make sure there
23560 are none. (This check is expensive, but seldom executed.) */
23561 if (WORLD_SAVE_P (info))
23564 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23565 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23567 info->world_save_p = 0;
23572 if (WORLD_SAVE_P (info))
23574 /* Even if we're not touching VRsave, make sure there's room on the
23575 stack for it, if it looks like we're calling SAVE_WORLD, which
23576 will attempt to save it. */
23577 info->vrsave_size = 4;
23579 /* If we are going to save the world, we need to save the link register too. */
23580 info->lr_save_p = 1;
23582 /* "Save" the VRsave register too if we're saving the world. */
23583 if (info->vrsave_mask == 0)
23584 info->vrsave_mask = compute_vrsave_mask ();
23586 /* Because the Darwin register save/restore routines only handle
23587 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23589 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23590 && (info->first_altivec_reg_save
23591 >= FIRST_SAVED_ALTIVEC_REGNO));
23599 is_altivec_return_reg (rtx reg, void *xyes)
23601 bool *yes = (bool *) xyes;
23602 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23607 /* Return whether REG is a global user reg or has been specifed by
23608 -ffixed-REG. We should not restore these, and so cannot use
23609 lmw or out-of-line restore functions if there are any. We also
23610 can't save them (well, emit frame notes for them), because frame
23611 unwinding during exception handling will restore saved registers. */
23614 fixed_reg_p (int reg)
23616 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23617 backend sets it, overriding anything the user might have given. */
23618 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23619 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23620 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23621 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23624 return fixed_regs[reg];
23627 /* Determine the strategy for savings/restoring registers. */
23630 SAVE_MULTIPLE = 0x1,
23631 SAVE_INLINE_GPRS = 0x2,
23632 SAVE_INLINE_FPRS = 0x4,
23633 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23634 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23635 SAVE_INLINE_VRS = 0x20,
23636 REST_MULTIPLE = 0x100,
23637 REST_INLINE_GPRS = 0x200,
23638 REST_INLINE_FPRS = 0x400,
23639 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23640 REST_INLINE_VRS = 0x1000
23644 rs6000_savres_strategy (rs6000_stack_t *info,
23645 bool using_static_chain_p)
23649 /* Select between in-line and out-of-line save and restore of regs.
23650 First, all the obvious cases where we don't use out-of-line. */
23651 if (crtl->calls_eh_return
23652 || cfun->machine->ra_need_lr)
23653 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23654 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23655 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23657 if (info->first_gp_reg_save == 32)
23658 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23660 if (info->first_fp_reg_save == 64)
23661 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23663 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23664 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23666 /* Define cutoff for using out-of-line functions to save registers. */
23667 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23669 if (!optimize_size)
23671 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23672 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23673 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23677 /* Prefer out-of-line restore if it will exit. */
23678 if (info->first_fp_reg_save > 61)
23679 strategy |= SAVE_INLINE_FPRS;
23680 if (info->first_gp_reg_save > 29)
23682 if (info->first_fp_reg_save == 64)
23683 strategy |= SAVE_INLINE_GPRS;
23685 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23687 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
23688 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23691 else if (DEFAULT_ABI == ABI_DARWIN)
23693 if (info->first_fp_reg_save > 60)
23694 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23695 if (info->first_gp_reg_save > 29)
23696 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23697 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23701 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
23702 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
23703 || info->first_fp_reg_save > 61)
23704 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23705 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23706 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23709 /* Don't bother to try to save things out-of-line if r11 is occupied
23710 by the static chain. It would require too much fiddling and the
23711 static chain is rarely used anyway. FPRs are saved w.r.t the stack
23712 pointer on Darwin, and AIX uses r1 or r12. */
23713 if (using_static_chain_p
23714 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
23715 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
23717 | SAVE_INLINE_VRS);
23719 /* Don't ever restore fixed regs. That means we can't use the
23720 out-of-line register restore functions if a fixed reg is in the
23721 range of regs restored. */
23722 if (!(strategy & REST_INLINE_FPRS))
23723 for (int i = info->first_fp_reg_save; i < 64; i++)
23726 strategy |= REST_INLINE_FPRS;
23730 /* We can only use the out-of-line routines to restore fprs if we've
23731 saved all the registers from first_fp_reg_save in the prologue.
23732 Otherwise, we risk loading garbage. Of course, if we have saved
23733 out-of-line then we know we haven't skipped any fprs. */
23734 if ((strategy & SAVE_INLINE_FPRS)
23735 && !(strategy & REST_INLINE_FPRS))
23736 for (int i = info->first_fp_reg_save; i < 64; i++)
23737 if (!save_reg_p (i))
23739 strategy |= REST_INLINE_FPRS;
23743 /* Similarly, for altivec regs. */
23744 if (!(strategy & REST_INLINE_VRS))
23745 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23748 strategy |= REST_INLINE_VRS;
23752 if ((strategy & SAVE_INLINE_VRS)
23753 && !(strategy & REST_INLINE_VRS))
23754 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23755 if (!save_reg_p (i))
23757 strategy |= REST_INLINE_VRS;
23761 /* info->lr_save_p isn't yet set if the only reason lr needs to be
23762 saved is an out-of-line save or restore. Set up the value for
23763 the next test (excluding out-of-line gprs). */
23764 bool lr_save_p = (info->lr_save_p
23765 || !(strategy & SAVE_INLINE_FPRS)
23766 || !(strategy & SAVE_INLINE_VRS)
23767 || !(strategy & REST_INLINE_FPRS)
23768 || !(strategy & REST_INLINE_VRS));
23770 if (TARGET_MULTIPLE
23771 && !TARGET_POWERPC64
23772 && info->first_gp_reg_save < 31
23773 && !(flag_shrink_wrap
23774 && flag_shrink_wrap_separate
23775 && optimize_function_for_speed_p (cfun)))
23778 for (int i = info->first_gp_reg_save; i < 32; i++)
23779 if (save_reg_p (i))
23783 /* Don't use store multiple if only one reg needs to be
23784 saved. This can occur for example when the ABI_V4 pic reg
23785 (r30) needs to be saved to make calls, but r31 is not
23787 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23790 /* Prefer store multiple for saves over out-of-line
23791 routines, since the store-multiple instruction will
23792 always be smaller. */
23793 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
23795 /* The situation is more complicated with load multiple.
23796 We'd prefer to use the out-of-line routines for restores,
23797 since the "exit" out-of-line routines can handle the
23798 restore of LR and the frame teardown. However if doesn't
23799 make sense to use the out-of-line routine if that is the
23800 only reason we'd need to save LR, and we can't use the
23801 "exit" out-of-line gpr restore if we have saved some
23802 fprs; In those cases it is advantageous to use load
23803 multiple when available. */
23804 if (info->first_fp_reg_save != 64 || !lr_save_p)
23805 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
23809 /* Using the "exit" out-of-line routine does not improve code size
23810 if using it would require lr to be saved and if only saving one
23812 else if (!lr_save_p && info->first_gp_reg_save > 29)
23813 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23815 /* Don't ever restore fixed regs. */
23816 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23817 for (int i = info->first_gp_reg_save; i < 32; i++)
23818 if (fixed_reg_p (i))
23820 strategy |= REST_INLINE_GPRS;
23821 strategy &= ~REST_MULTIPLE;
23825 /* We can only use load multiple or the out-of-line routines to
23826 restore gprs if we've saved all the registers from
23827 first_gp_reg_save. Otherwise, we risk loading garbage.
23828 Of course, if we have saved out-of-line or used stmw then we know
23829 we haven't skipped any gprs. */
23830 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
23831 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23832 for (int i = info->first_gp_reg_save; i < 32; i++)
23833 if (!save_reg_p (i))
23835 strategy |= REST_INLINE_GPRS;
23836 strategy &= ~REST_MULTIPLE;
23840 if (TARGET_ELF && TARGET_64BIT)
23842 if (!(strategy & SAVE_INLINE_FPRS))
23843 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
23844 else if (!(strategy & SAVE_INLINE_GPRS)
23845 && info->first_fp_reg_save == 64)
23846 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
23848 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
23849 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
23851 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
23852 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
23857 /* Calculate the stack information for the current function. This is
23858 complicated by having two separate calling sequences, the AIX calling
23859 sequence and the V.4 calling sequence.
23861 AIX (and Darwin/Mac OS X) stack frames look like:
23863 SP----> +---------------------------------------+
23864 | back chain to caller | 0 0
23865 +---------------------------------------+
23866 | saved CR | 4 8 (8-11)
23867 +---------------------------------------+
23869 +---------------------------------------+
23870 | reserved for compilers | 12 24
23871 +---------------------------------------+
23872 | reserved for binders | 16 32
23873 +---------------------------------------+
23874 | saved TOC pointer | 20 40
23875 +---------------------------------------+
23876 | Parameter save area (+padding*) (P) | 24 48
23877 +---------------------------------------+
23878 | Alloca space (A) | 24+P etc.
23879 +---------------------------------------+
23880 | Local variable space (L) | 24+P+A
23881 +---------------------------------------+
23882 | Float/int conversion temporary (X) | 24+P+A+L
23883 +---------------------------------------+
23884 | Save area for AltiVec registers (W) | 24+P+A+L+X
23885 +---------------------------------------+
23886 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
23887 +---------------------------------------+
23888 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
23889 +---------------------------------------+
23890 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
23891 +---------------------------------------+
23892 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
23893 +---------------------------------------+
23894 old SP->| back chain to caller's caller |
23895 +---------------------------------------+
23897 * If the alloca area is present, the parameter save area is
23898 padded so that the former starts 16-byte aligned.
23900 The required alignment for AIX configurations is two words (i.e., 8
23903 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
23905 SP----> +---------------------------------------+
23906 | Back chain to caller | 0
23907 +---------------------------------------+
23908 | Save area for CR | 8
23909 +---------------------------------------+
23911 +---------------------------------------+
23912 | Saved TOC pointer | 24
23913 +---------------------------------------+
23914 | Parameter save area (+padding*) (P) | 32
23915 +---------------------------------------+
23916 | Alloca space (A) | 32+P
23917 +---------------------------------------+
23918 | Local variable space (L) | 32+P+A
23919 +---------------------------------------+
23920 | Save area for AltiVec registers (W) | 32+P+A+L
23921 +---------------------------------------+
23922 | AltiVec alignment padding (Y) | 32+P+A+L+W
23923 +---------------------------------------+
23924 | Save area for GP registers (G) | 32+P+A+L+W+Y
23925 +---------------------------------------+
23926 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
23927 +---------------------------------------+
23928 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
23929 +---------------------------------------+
23931 * If the alloca area is present, the parameter save area is
23932 padded so that the former starts 16-byte aligned.
23934 V.4 stack frames look like:
23936 SP----> +---------------------------------------+
23937 | back chain to caller | 0
23938 +---------------------------------------+
23939 | caller's saved LR | 4
23940 +---------------------------------------+
23941 | Parameter save area (+padding*) (P) | 8
23942 +---------------------------------------+
23943 | Alloca space (A) | 8+P
23944 +---------------------------------------+
23945 | Varargs save area (V) | 8+P+A
23946 +---------------------------------------+
23947 | Local variable space (L) | 8+P+A+V
23948 +---------------------------------------+
23949 | Float/int conversion temporary (X) | 8+P+A+V+L
23950 +---------------------------------------+
23951 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
23952 +---------------------------------------+
23953 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
23954 +---------------------------------------+
23955 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
23956 +---------------------------------------+
23957 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
23958 +---------------------------------------+
23959 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
23960 +---------------------------------------+
23961 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
23962 +---------------------------------------+
23963 old SP->| back chain to caller's caller |
23964 +---------------------------------------+
23966 * If the alloca area is present and the required alignment is
23967 16 bytes, the parameter save area is padded so that the
23968 alloca area starts 16-byte aligned.
23970 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
23971 given. (But note below and in sysv4.h that we require only 8 and
23972 may round up the size of our stack frame anyways. The historical
23973 reason is early versions of powerpc-linux which didn't properly
23974 align the stack at program startup. A happy side-effect is that
23975 -mno-eabi libraries can be used with -meabi programs.)
23977 The EABI configuration defaults to the V.4 layout. However,
23978 the stack alignment requirements may differ. If -mno-eabi is not
23979 given, the required stack alignment is 8 bytes; if -mno-eabi is
23980 given, the required alignment is 16 bytes. (But see V.4 comment
23983 #ifndef ABI_STACK_BOUNDARY
23984 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
23987 static rs6000_stack_t *
23988 rs6000_stack_info (void)
23990 /* We should never be called for thunks, we are not set up for that. */
23991 gcc_assert (!cfun->is_thunk);
23993 rs6000_stack_t *info = &stack_info;
23994 int reg_size = TARGET_32BIT ? 4 : 8;
23999 HOST_WIDE_INT non_fixed_size;
24000 bool using_static_chain_p;
24002 if (reload_completed && info->reload_completed)
24005 memset (info, 0, sizeof (*info));
24006 info->reload_completed = reload_completed;
24008 /* Select which calling sequence. */
24009 info->abi = DEFAULT_ABI;
24011 /* Calculate which registers need to be saved & save area size. */
24012 info->first_gp_reg_save = first_reg_to_save ();
24013 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24014 even if it currently looks like we won't. Reload may need it to
24015 get at a constant; if so, it will have already created a constant
24016 pool entry for it. */
24017 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24018 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24019 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24020 && crtl->uses_const_pool
24021 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24022 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24024 first_gp = info->first_gp_reg_save;
24026 info->gp_size = reg_size * (32 - first_gp);
24028 info->first_fp_reg_save = first_fp_reg_to_save ();
24029 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24031 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24032 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24033 - info->first_altivec_reg_save);
24035 /* Does this function call anything? */
24036 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24038 /* Determine if we need to save the condition code registers. */
24039 if (save_reg_p (CR2_REGNO)
24040 || save_reg_p (CR3_REGNO)
24041 || save_reg_p (CR4_REGNO))
24043 info->cr_save_p = 1;
24044 if (DEFAULT_ABI == ABI_V4)
24045 info->cr_size = reg_size;
24048 /* If the current function calls __builtin_eh_return, then we need
24049 to allocate stack space for registers that will hold data for
24050 the exception handler. */
24051 if (crtl->calls_eh_return)
24054 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24057 ehrd_size = i * UNITS_PER_WORD;
24062 /* In the ELFv2 ABI, we also need to allocate space for separate
24063 CR field save areas if the function calls __builtin_eh_return. */
24064 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24066 /* This hard-codes that we have three call-saved CR fields. */
24067 ehcr_size = 3 * reg_size;
24068 /* We do *not* use the regular CR save mechanism. */
24069 info->cr_save_p = 0;
24074 /* Determine various sizes. */
24075 info->reg_size = reg_size;
24076 info->fixed_size = RS6000_SAVE_AREA;
24077 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24078 if (cfun->calls_alloca)
24080 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24081 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24083 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24084 TARGET_ALTIVEC ? 16 : 8);
24085 if (FRAME_GROWS_DOWNWARD)
24087 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24088 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24089 - (info->fixed_size + info->vars_size + info->parm_size);
24091 if (TARGET_ALTIVEC_ABI)
24092 info->vrsave_mask = compute_vrsave_mask ();
24094 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24095 info->vrsave_size = 4;
24097 compute_save_world_info (info);
24099 /* Calculate the offsets. */
24100 switch (DEFAULT_ABI)
24104 gcc_unreachable ();
24109 info->fp_save_offset = -info->fp_size;
24110 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24112 if (TARGET_ALTIVEC_ABI)
24114 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24116 /* Align stack so vector save area is on a quadword boundary.
24117 The padding goes above the vectors. */
24118 if (info->altivec_size != 0)
24119 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24121 info->altivec_save_offset = info->vrsave_save_offset
24122 - info->altivec_padding_size
24123 - info->altivec_size;
24124 gcc_assert (info->altivec_size == 0
24125 || info->altivec_save_offset % 16 == 0);
24127 /* Adjust for AltiVec case. */
24128 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24131 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24133 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24134 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24135 info->lr_save_offset = 2*reg_size;
24139 info->fp_save_offset = -info->fp_size;
24140 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24141 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24143 if (TARGET_ALTIVEC_ABI)
24145 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24147 /* Align stack so vector save area is on a quadword boundary. */
24148 if (info->altivec_size != 0)
24149 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24151 info->altivec_save_offset = info->vrsave_save_offset
24152 - info->altivec_padding_size
24153 - info->altivec_size;
24155 /* Adjust for AltiVec case. */
24156 info->ehrd_offset = info->altivec_save_offset;
24159 info->ehrd_offset = info->cr_save_offset;
24161 info->ehrd_offset -= ehrd_size;
24162 info->lr_save_offset = reg_size;
24165 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24166 info->save_size = RS6000_ALIGN (info->fp_size
24168 + info->altivec_size
24169 + info->altivec_padding_size
24173 + info->vrsave_size,
24176 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24178 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24179 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24181 /* Determine if we need to save the link register. */
24183 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24185 && !TARGET_PROFILE_KERNEL)
24186 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24187 #ifdef TARGET_RELOCATABLE
24188 || (DEFAULT_ABI == ABI_V4
24189 && (TARGET_RELOCATABLE || flag_pic > 1)
24190 && !constant_pool_empty_p ())
24192 || rs6000_ra_ever_killed ())
24193 info->lr_save_p = 1;
24195 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24196 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24197 && call_used_regs[STATIC_CHAIN_REGNUM]);
24198 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24200 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24201 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24202 || !(info->savres_strategy & SAVE_INLINE_VRS)
24203 || !(info->savres_strategy & REST_INLINE_GPRS)
24204 || !(info->savres_strategy & REST_INLINE_FPRS)
24205 || !(info->savres_strategy & REST_INLINE_VRS))
24206 info->lr_save_p = 1;
24208 if (info->lr_save_p)
24209 df_set_regs_ever_live (LR_REGNO, true);
24211 /* Determine if we need to allocate any stack frame:
24213 For AIX we need to push the stack if a frame pointer is needed
24214 (because the stack might be dynamically adjusted), if we are
24215 debugging, if we make calls, or if the sum of fp_save, gp_save,
24216 and local variables are more than the space needed to save all
24217 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24218 + 18*8 = 288 (GPR13 reserved).
24220 For V.4 we don't have the stack cushion that AIX uses, but assume
24221 that the debugger can handle stackless frames. */
24226 else if (DEFAULT_ABI == ABI_V4)
24227 info->push_p = non_fixed_size != 0;
24229 else if (frame_pointer_needed)
24232 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24236 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24242 debug_stack_info (rs6000_stack_t *info)
24244 const char *abi_string;
24247 info = rs6000_stack_info ();
24249 fprintf (stderr, "\nStack information for function %s:\n",
24250 ((current_function_decl && DECL_NAME (current_function_decl))
24251 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24256 default: abi_string = "Unknown"; break;
24257 case ABI_NONE: abi_string = "NONE"; break;
24258 case ABI_AIX: abi_string = "AIX"; break;
24259 case ABI_ELFv2: abi_string = "ELFv2"; break;
24260 case ABI_DARWIN: abi_string = "Darwin"; break;
24261 case ABI_V4: abi_string = "V.4"; break;
24264 fprintf (stderr, "\tABI = %5s\n", abi_string);
24266 if (TARGET_ALTIVEC_ABI)
24267 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24269 if (info->first_gp_reg_save != 32)
24270 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24272 if (info->first_fp_reg_save != 64)
24273 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24275 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24276 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24277 info->first_altivec_reg_save);
24279 if (info->lr_save_p)
24280 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24282 if (info->cr_save_p)
24283 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24285 if (info->vrsave_mask)
24286 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24289 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24292 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24295 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24298 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24300 if (info->altivec_size)
24301 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24302 info->altivec_save_offset);
24304 if (info->vrsave_size)
24305 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24306 info->vrsave_save_offset);
24308 if (info->lr_save_p)
24309 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24311 if (info->cr_save_p)
24312 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24314 if (info->varargs_save_offset)
24315 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24317 if (info->total_size)
24318 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24321 if (info->vars_size)
24322 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24325 if (info->parm_size)
24326 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24328 if (info->fixed_size)
24329 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24332 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24335 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24337 if (info->altivec_size)
24338 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24340 if (info->vrsave_size)
24341 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24343 if (info->altivec_padding_size)
24344 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24345 info->altivec_padding_size);
24348 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24350 if (info->save_size)
24351 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24353 if (info->reg_size != 4)
24354 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24356 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24358 fprintf (stderr, "\n");
24362 rs6000_return_addr (int count, rtx frame)
24364 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24365 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24367 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24369 cfun->machine->ra_needs_full_frame = 1;
24372 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24373 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24374 frame = stack_pointer_rtx;
24375 rtx prev_frame_addr = memory_address (Pmode, frame);
24376 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24377 rtx lr_save_off = plus_constant (Pmode,
24378 prev_frame, RETURN_ADDRESS_OFFSET);
24379 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24380 return gen_rtx_MEM (Pmode, lr_save_addr);
24383 cfun->machine->ra_need_lr = 1;
24384 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24387 /* Say whether a function is a candidate for sibcall handling or not. */
24390 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24395 fntype = TREE_TYPE (decl);
24397 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24399 /* We can't do it if the called function has more vector parameters
24400 than the current function; there's nowhere to put the VRsave code. */
24401 if (TARGET_ALTIVEC_ABI
24402 && TARGET_ALTIVEC_VRSAVE
24403 && !(decl && decl == current_function_decl))
24405 function_args_iterator args_iter;
24409 /* Functions with vector parameters are required to have a
24410 prototype, so the argument type info must be available
24412 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24413 if (TREE_CODE (type) == VECTOR_TYPE
24414 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24417 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24418 if (TREE_CODE (type) == VECTOR_TYPE
24419 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24426 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24427 functions, because the callee may have a different TOC pointer to
24428 the caller and there's no way to ensure we restore the TOC when
24429 we return. With the secure-plt SYSV ABI we can't make non-local
24430 calls when -fpic/PIC because the plt call stubs use r30. */
24431 if (DEFAULT_ABI == ABI_DARWIN
24432 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24434 && !DECL_EXTERNAL (decl)
24435 && !DECL_WEAK (decl)
24436 && (*targetm.binds_local_p) (decl))
24437 || (DEFAULT_ABI == ABI_V4
24438 && (!TARGET_SECURE_PLT
24441 && (*targetm.binds_local_p) (decl)))))
24443 tree attr_list = TYPE_ATTRIBUTES (fntype);
24445 if (!lookup_attribute ("longcall", attr_list)
24446 || lookup_attribute ("shortcall", attr_list))
24454 rs6000_ra_ever_killed (void)
24460 if (cfun->is_thunk)
24463 if (cfun->machine->lr_save_state)
24464 return cfun->machine->lr_save_state - 1;
24466 /* regs_ever_live has LR marked as used if any sibcalls are present,
24467 but this should not force saving and restoring in the
24468 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24469 clobbers LR, so that is inappropriate. */
24471 /* Also, the prologue can generate a store into LR that
24472 doesn't really count, like this:
24475 bcl to set PIC register
24479 When we're called from the epilogue, we need to avoid counting
24480 this as a store. */
24482 push_topmost_sequence ();
24483 top = get_insns ();
24484 pop_topmost_sequence ();
24485 reg = gen_rtx_REG (Pmode, LR_REGNO);
24487 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24493 if (!SIBLING_CALL_P (insn))
24496 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24498 else if (set_of (reg, insn) != NULL_RTX
24499 && !prologue_epilogue_contains (insn))
24506 /* Emit instructions needed to load the TOC register.
24507 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24508 a constant pool; or for SVR4 -fpic. */
24511 rs6000_emit_load_toc_table (int fromprolog)
24514 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24516 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24519 rtx lab, tmp1, tmp2, got;
24521 lab = gen_label_rtx ();
24522 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24523 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24526 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24530 got = rs6000_got_sym ();
24531 tmp1 = tmp2 = dest;
24534 tmp1 = gen_reg_rtx (Pmode);
24535 tmp2 = gen_reg_rtx (Pmode);
24537 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24538 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24539 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24540 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24542 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24544 emit_insn (gen_load_toc_v4_pic_si ());
24545 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24547 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24550 rtx temp0 = (fromprolog
24551 ? gen_rtx_REG (Pmode, 0)
24552 : gen_reg_rtx (Pmode));
24558 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24559 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24561 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24562 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24564 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24565 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24566 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24572 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24574 lab = gen_label_rtx ();
24575 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24576 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24577 if (TARGET_LINK_STACK)
24578 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24579 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24581 emit_insn (gen_addsi3 (dest, temp0, dest));
24583 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24585 /* This is for AIX code running in non-PIC ELF32. */
24586 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24589 emit_insn (gen_elf_high (dest, realsym));
24590 emit_insn (gen_elf_low (dest, dest, realsym));
24594 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24597 emit_insn (gen_load_toc_aix_si (dest));
24599 emit_insn (gen_load_toc_aix_di (dest));
24603 /* Emit instructions to restore the link register after determining where
24604 its value has been stored. */
24607 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24609 rs6000_stack_t *info = rs6000_stack_info ();
24612 operands[0] = source;
24613 operands[1] = scratch;
24615 if (info->lr_save_p)
24617 rtx frame_rtx = stack_pointer_rtx;
24618 HOST_WIDE_INT sp_offset = 0;
24621 if (frame_pointer_needed
24622 || cfun->calls_alloca
24623 || info->total_size > 32767)
24625 tmp = gen_frame_mem (Pmode, frame_rtx);
24626 emit_move_insn (operands[1], tmp);
24627 frame_rtx = operands[1];
24629 else if (info->push_p)
24630 sp_offset = info->total_size;
24632 tmp = plus_constant (Pmode, frame_rtx,
24633 info->lr_save_offset + sp_offset);
24634 tmp = gen_frame_mem (Pmode, tmp);
24635 emit_move_insn (tmp, operands[0]);
24638 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24640 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24641 state of lr_save_p so any change from here on would be a bug. In
24642 particular, stop rs6000_ra_ever_killed from considering the SET
24643 of lr we may have added just above. */
24644 cfun->machine->lr_save_state = info->lr_save_p + 1;
24647 static GTY(()) alias_set_type set = -1;
24650 get_TOC_alias_set (void)
24653 set = new_alias_set ();
24657 /* This returns nonzero if the current function uses the TOC. This is
24658 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24659 is generated by the ABI_V4 load_toc_* patterns.
24660 Return 2 instead of 1 if the load_toc_* pattern is in the function
24661 partition that doesn't start the function. */
24669 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24673 rtx pat = PATTERN (insn);
24676 if (GET_CODE (pat) == PARALLEL)
24677 for (i = 0; i < XVECLEN (pat, 0); i++)
24679 rtx sub = XVECEXP (pat, 0, i);
24680 if (GET_CODE (sub) == USE)
24682 sub = XEXP (sub, 0);
24683 if (GET_CODE (sub) == UNSPEC
24684 && XINT (sub, 1) == UNSPEC_TOC)
24689 else if (crtl->has_bb_partition
24691 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
24699 create_TOC_reference (rtx symbol, rtx largetoc_reg)
24701 rtx tocrel, tocreg, hi;
24703 if (TARGET_DEBUG_ADDR)
24705 if (GET_CODE (symbol) == SYMBOL_REF)
24706 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
24710 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
24711 GET_RTX_NAME (GET_CODE (symbol)));
24712 debug_rtx (symbol);
24716 if (!can_create_pseudo_p ())
24717 df_set_regs_ever_live (TOC_REGISTER, true);
24719 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
24720 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
24721 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
24724 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
24725 if (largetoc_reg != NULL)
24727 emit_move_insn (largetoc_reg, hi);
24730 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
24733 /* Issue assembly directives that create a reference to the given DWARF
24734 FRAME_TABLE_LABEL from the current function section. */
24736 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
24738 fprintf (asm_out_file, "\t.ref %s\n",
24739 (* targetm.strip_name_encoding) (frame_table_label));
24742 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
24743 and the change to the stack pointer. */
24746 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
24753 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
24754 if (hard_frame_needed)
24755 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
24756 if (!(REGNO (fp) == STACK_POINTER_REGNUM
24757 || (hard_frame_needed
24758 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
24761 p = rtvec_alloc (i);
24764 rtx mem = gen_frame_mem (BLKmode, regs[i]);
24765 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
24768 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
24771 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
24772 and set the appropriate attributes for the generated insn. Return the
24773 first insn which adjusts the stack pointer or the last insn before
24774 the stack adjustment loop.
24776 SIZE_INT is used to create the CFI note for the allocation.
24778 SIZE_RTX is an rtx containing the size of the adjustment. Note that
24779 since stacks grow to lower addresses its runtime value is -SIZE_INT.
24781 ORIG_SP contains the backchain value that must be stored at *sp. */
24784 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
24788 rtx size_rtx = GEN_INT (-size_int);
24789 if (size_int > 32767)
24791 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
24792 /* Need a note here so that try_split doesn't get confused. */
24793 if (get_last_insn () == NULL_RTX)
24794 emit_note (NOTE_INSN_DELETED);
24795 insn = emit_move_insn (tmp_reg, size_rtx);
24796 try_split (PATTERN (insn), insn, 0);
24797 size_rtx = tmp_reg;
24800 if (Pmode == SImode)
24801 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
24806 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
24810 rtx par = PATTERN (insn);
24811 gcc_assert (GET_CODE (par) == PARALLEL);
24812 rtx set = XVECEXP (par, 0, 0);
24813 gcc_assert (GET_CODE (set) == SET);
24814 rtx mem = SET_DEST (set);
24815 gcc_assert (MEM_P (mem));
24816 MEM_NOTRAP_P (mem) = 1;
24817 set_mem_alias_set (mem, get_frame_alias_set ());
24819 RTX_FRAME_RELATED_P (insn) = 1;
24820 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
24821 gen_rtx_SET (stack_pointer_rtx,
24822 gen_rtx_PLUS (Pmode,
24824 GEN_INT (-size_int))));
24826 /* Emit a blockage to ensure the allocation/probing insns are
24827 not optimized, combined, removed, etc. Add REG_STACK_CHECK
24828 note for similar reasons. */
24829 if (flag_stack_clash_protection)
24831 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
24832 emit_insn (gen_blockage ());
24838 static HOST_WIDE_INT
24839 get_stack_clash_protection_probe_interval (void)
24841 return (HOST_WIDE_INT_1U
24842 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
24845 static HOST_WIDE_INT
24846 get_stack_clash_protection_guard_size (void)
24848 return (HOST_WIDE_INT_1U
24849 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
24852 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
24853 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
24855 COPY_REG, if non-null, should contain a copy of the original
24856 stack pointer at exit from this function.
24858 This is subtly different than the Ada probing in that it tries hard to
24859 prevent attacks that jump the stack guard. Thus it is never allowed to
24860 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
24861 space without a suitable probe. */
24863 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
24866 rtx orig_sp = copy_reg;
24868 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
24870 /* Round the size down to a multiple of PROBE_INTERVAL. */
24871 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
24873 /* If explicitly requested,
24874 or the rounded size is not the same as the original size
24875 or the the rounded size is greater than a page,
24876 then we will need a copy of the original stack pointer. */
24877 if (rounded_size != orig_size
24878 || rounded_size > probe_interval
24881 /* If the caller did not request a copy of the incoming stack
24882 pointer, then we use r0 to hold the copy. */
24884 orig_sp = gen_rtx_REG (Pmode, 0);
24885 emit_move_insn (orig_sp, stack_pointer_rtx);
24888 /* There's three cases here.
24890 One is a single probe which is the most common and most efficiently
24891 implemented as it does not have to have a copy of the original
24892 stack pointer if there are no residuals.
24894 Second is unrolled allocation/probes which we use if there's just
24895 a few of them. It needs to save the original stack pointer into a
24896 temporary for use as a source register in the allocation/probe.
24898 Last is a loop. This is the most uncommon case and least efficient. */
24899 rtx_insn *retval = NULL;
24900 if (rounded_size == probe_interval)
24902 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
24904 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
24906 else if (rounded_size <= 8 * probe_interval)
24908 /* The ABI requires using the store with update insns to allocate
24909 space and store the backchain into the stack
24911 So we save the current stack pointer into a temporary, then
24912 emit the store-with-update insns to store the saved stack pointer
24913 into the right location in each new page. */
24914 for (int i = 0; i < rounded_size; i += probe_interval)
24917 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
24919 /* Save the first stack adjustment in RETVAL. */
24924 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
24928 /* Compute the ending address. */
24930 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
24931 rtx rs = GEN_INT (-rounded_size);
24933 if (add_operand (rs, Pmode))
24934 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
24937 emit_move_insn (end_addr, GEN_INT (-rounded_size));
24938 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
24939 stack_pointer_rtx));
24940 /* Describe the effect of INSN to the CFI engine. */
24941 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
24942 gen_rtx_SET (end_addr,
24943 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
24946 RTX_FRAME_RELATED_P (insn) = 1;
24948 /* Emit the loop. */
24950 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
24951 stack_pointer_rtx, orig_sp,
24954 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
24955 stack_pointer_rtx, orig_sp,
24957 RTX_FRAME_RELATED_P (retval) = 1;
24958 /* Describe the effect of INSN to the CFI engine. */
24959 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
24960 gen_rtx_SET (stack_pointer_rtx, end_addr));
24962 /* Emit a blockage to ensure the allocation/probing insns are
24963 not optimized, combined, removed, etc. Other cases handle this
24964 within their call to rs6000_emit_allocate_stack_1. */
24965 emit_insn (gen_blockage ());
24967 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
24970 if (orig_size != rounded_size)
24972 /* Allocate (and implicitly probe) any residual space. */
24973 HOST_WIDE_INT residual = orig_size - rounded_size;
24975 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
24977 /* If the residual was the only allocation, then we can return the
24978 allocating insn. */
24986 /* Emit the correct code for allocating stack space, as insns.
24987 If COPY_REG, make sure a copy of the old frame is left there.
24988 The generated code may use hard register 0 as a temporary. */
24991 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
24994 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
24995 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
24996 rtx todec = gen_int_mode (-size, Pmode);
24998 if (INTVAL (todec) != -size)
25000 warning (0, "stack frame too large");
25001 emit_insn (gen_trap ());
25005 if (crtl->limit_stack)
25007 if (REG_P (stack_limit_rtx)
25008 && REGNO (stack_limit_rtx) > 1
25009 && REGNO (stack_limit_rtx) <= 31)
25012 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25015 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25017 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25019 && DEFAULT_ABI == ABI_V4
25022 rtx toload = gen_rtx_CONST (VOIDmode,
25023 gen_rtx_PLUS (Pmode,
25027 emit_insn (gen_elf_high (tmp_reg, toload));
25028 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25029 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25033 warning (0, "stack limit expression is not supported");
25036 if (flag_stack_clash_protection)
25038 if (size < get_stack_clash_protection_guard_size ())
25039 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25042 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25045 /* If we asked for a copy with an offset, then we still need add in
25047 if (copy_reg && copy_off)
25048 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25056 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25058 emit_move_insn (copy_reg, stack_reg);
25061 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25062 it now and set the alias set/attributes. The above gen_*_update
25063 calls will generate a PARALLEL with the MEM set being the first
25065 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25069 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25071 #if PROBE_INTERVAL > 32768
25072 #error Cannot use indexed addressing mode for stack probing
25075 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25076 inclusive. These are offsets from the current stack pointer. */
25079 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25081 /* See if we have a constant small number of probes to generate. If so,
25082 that's the easy case. */
25083 if (first + size <= 32768)
25087 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25088 it exceeds SIZE. If only one probe is needed, this will not
25089 generate any code. Then probe at FIRST + SIZE. */
25090 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25091 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25094 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25098 /* Otherwise, do the same as above, but in a loop. Note that we must be
25099 extra careful with variables wrapping around because we might be at
25100 the very top (or the very bottom) of the address space and we have
25101 to be able to handle this case properly; in particular, we use an
25102 equality test for the loop condition. */
25105 HOST_WIDE_INT rounded_size;
25106 rtx r12 = gen_rtx_REG (Pmode, 12);
25107 rtx r0 = gen_rtx_REG (Pmode, 0);
25109 /* Sanity check for the addressing mode we're going to use. */
25110 gcc_assert (first <= 32768);
25112 /* Step 1: round SIZE to the previous multiple of the interval. */
25114 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25117 /* Step 2: compute initial and final value of the loop counter. */
25119 /* TEST_ADDR = SP + FIRST. */
25120 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25123 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25124 if (rounded_size > 32768)
25126 emit_move_insn (r0, GEN_INT (-rounded_size));
25127 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25130 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25134 /* Step 3: the loop
25138 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25141 while (TEST_ADDR != LAST_ADDR)
25143 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25144 until it is equal to ROUNDED_SIZE. */
25147 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25149 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25152 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25153 that SIZE is equal to ROUNDED_SIZE. */
25155 if (size != rounded_size)
25156 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25160 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25161 addresses, not offsets. */
25163 static const char *
25164 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25166 static int labelno = 0;
25170 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25173 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25175 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25177 xops[1] = GEN_INT (-PROBE_INTERVAL);
25178 output_asm_insn ("addi %0,%0,%1", xops);
25180 /* Probe at TEST_ADDR. */
25181 xops[1] = gen_rtx_REG (Pmode, 0);
25182 output_asm_insn ("stw %1,0(%0)", xops);
25184 /* Test if TEST_ADDR == LAST_ADDR. */
25187 output_asm_insn ("cmpd 0,%0,%1", xops);
25189 output_asm_insn ("cmpw 0,%0,%1", xops);
25192 fputs ("\tbne 0,", asm_out_file);
25193 assemble_name_raw (asm_out_file, loop_lab);
25194 fputc ('\n', asm_out_file);
25199 /* This function is called when rs6000_frame_related is processing
25200 SETs within a PARALLEL, and returns whether the REGNO save ought to
25201 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25202 for out-of-line register save functions, store multiple, and the
25203 Darwin world_save. They may contain registers that don't really
25207 interesting_frame_related_regno (unsigned int regno)
25209 /* Saves apparently of r0 are actually saving LR. It doesn't make
25210 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25211 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25212 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25213 as frame related. */
25216 /* If we see CR2 then we are here on a Darwin world save. Saves of
25217 CR2 signify the whole CR is being saved. This is a long-standing
25218 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25219 that CR needs to be saved. */
25220 if (regno == CR2_REGNO)
25222 /* Omit frame info for any user-defined global regs. If frame info
25223 is supplied for them, frame unwinding will restore a user reg.
25224 Also omit frame info for any reg we don't need to save, as that
25225 bloats frame info and can cause problems with shrink wrapping.
25226 Since global regs won't be seen as needing to be saved, both of
25227 these conditions are covered by save_reg_p. */
25228 return save_reg_p (regno);
25231 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25232 addresses, not offsets.
25234 REG2 contains the backchain that must be stored into *sp at each allocation.
25236 This is subtly different than the Ada probing above in that it tries hard
25237 to prevent attacks that jump the stack guard. Thus, it is never allowed
25238 to allocate more than PROBE_INTERVAL bytes of stack space without a
25241 static const char *
25242 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25244 static int labelno = 0;
25248 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25250 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25252 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25254 /* This allocates and probes. */
25257 xops[2] = GEN_INT (-probe_interval);
25259 output_asm_insn ("stdu %1,%2(%0)", xops);
25261 output_asm_insn ("stwu %1,%2(%0)", xops);
25263 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25267 output_asm_insn ("cmpd 0,%0,%1", xops);
25269 output_asm_insn ("cmpw 0,%0,%1", xops);
25271 fputs ("\tbne 0,", asm_out_file);
25272 assemble_name_raw (asm_out_file, loop_lab);
25273 fputc ('\n', asm_out_file);
25278 /* Wrapper around the output_probe_stack_range routines. */
25280 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25282 if (flag_stack_clash_protection)
25283 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25285 return output_probe_stack_range_1 (reg1, reg3);
25288 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25289 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25290 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25291 deduce these equivalences by itself so it wasn't necessary to hold
25292 its hand so much. Don't be tempted to always supply d2_f_d_e with
25293 the actual cfa register, ie. r31 when we are using a hard frame
25294 pointer. That fails when saving regs off r1, and sched moves the
25295 r31 setup past the reg saves. */
25298 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25299 rtx reg2, rtx repl2)
25303 if (REGNO (reg) == STACK_POINTER_REGNUM)
25305 gcc_checking_assert (val == 0);
25309 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25312 rtx pat = PATTERN (insn);
25313 if (!repl && !reg2)
25315 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25316 if (GET_CODE (pat) == PARALLEL)
25317 for (int i = 0; i < XVECLEN (pat, 0); i++)
25318 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25320 rtx set = XVECEXP (pat, 0, i);
25322 if (!REG_P (SET_SRC (set))
25323 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25324 RTX_FRAME_RELATED_P (set) = 1;
25326 RTX_FRAME_RELATED_P (insn) = 1;
25330 /* We expect that 'pat' is either a SET or a PARALLEL containing
25331 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25332 are important so they all have to be marked RTX_FRAME_RELATED_P.
25333 Call simplify_replace_rtx on the SETs rather than the whole insn
25334 so as to leave the other stuff alone (for example USE of r12). */
25336 set_used_flags (pat);
25337 if (GET_CODE (pat) == SET)
25340 pat = simplify_replace_rtx (pat, reg, repl);
25342 pat = simplify_replace_rtx (pat, reg2, repl2);
25344 else if (GET_CODE (pat) == PARALLEL)
25346 pat = shallow_copy_rtx (pat);
25347 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25349 for (int i = 0; i < XVECLEN (pat, 0); i++)
25350 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25352 rtx set = XVECEXP (pat, 0, i);
25355 set = simplify_replace_rtx (set, reg, repl);
25357 set = simplify_replace_rtx (set, reg2, repl2);
25358 XVECEXP (pat, 0, i) = set;
25360 if (!REG_P (SET_SRC (set))
25361 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25362 RTX_FRAME_RELATED_P (set) = 1;
25366 gcc_unreachable ();
25368 RTX_FRAME_RELATED_P (insn) = 1;
25369 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25374 /* Returns an insn that has a vrsave set operation with the
25375 appropriate CLOBBERs. */
25378 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25381 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25382 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25385 = gen_rtx_SET (vrsave,
25386 gen_rtx_UNSPEC_VOLATILE (SImode,
25387 gen_rtvec (2, reg, vrsave),
25388 UNSPECV_SET_VRSAVE));
25392 /* We need to clobber the registers in the mask so the scheduler
25393 does not move sets to VRSAVE before sets of AltiVec registers.
25395 However, if the function receives nonlocal gotos, reload will set
25396 all call saved registers live. We will end up with:
25398 (set (reg 999) (mem))
25399 (parallel [ (set (reg vrsave) (unspec blah))
25400 (clobber (reg 999))])
25402 The clobber will cause the store into reg 999 to be dead, and
25403 flow will attempt to delete an epilogue insn. In this case, we
25404 need an unspec use/set of the register. */
25406 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25407 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25409 if (!epiloguep || call_used_regs [i])
25410 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
25411 gen_rtx_REG (V4SImode, i));
25414 rtx reg = gen_rtx_REG (V4SImode, i);
25417 = gen_rtx_SET (reg,
25418 gen_rtx_UNSPEC (V4SImode,
25419 gen_rtvec (1, reg), 27));
25423 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25425 for (i = 0; i < nclobs; ++i)
25426 XVECEXP (insn, 0, i) = clobs[i];
25432 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25436 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25437 mem = gen_frame_mem (GET_MODE (reg), addr);
25438 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25442 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25444 return gen_frame_set (reg, frame_reg, offset, false);
25448 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25450 return gen_frame_set (reg, frame_reg, offset, true);
25453 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25454 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25457 emit_frame_save (rtx frame_reg, machine_mode mode,
25458 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25462 /* Some cases that need register indexed addressing. */
25463 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25464 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25466 reg = gen_rtx_REG (mode, regno);
25467 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25468 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25469 NULL_RTX, NULL_RTX);
25472 /* Emit an offset memory reference suitable for a frame store, while
25473 converting to a valid addressing mode. */
25476 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25478 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25481 #ifndef TARGET_FIX_AND_CONTINUE
25482 #define TARGET_FIX_AND_CONTINUE 0
25485 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25486 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25487 #define LAST_SAVRES_REGISTER 31
25488 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25499 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25501 /* Temporary holding space for an out-of-line register save/restore
25503 static char savres_routine_name[30];
25505 /* Return the name for an out-of-line register save/restore routine.
25506 We are saving/restoring GPRs if GPR is true. */
25509 rs6000_savres_routine_name (int regno, int sel)
25511 const char *prefix = "";
25512 const char *suffix = "";
25514 /* Different targets are supposed to define
25515 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25516 routine name could be defined with:
25518 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25520 This is a nice idea in practice, but in reality, things are
25521 complicated in several ways:
25523 - ELF targets have save/restore routines for GPRs.
25525 - PPC64 ELF targets have routines for save/restore of GPRs that
25526 differ in what they do with the link register, so having a set
25527 prefix doesn't work. (We only use one of the save routines at
25528 the moment, though.)
25530 - PPC32 elf targets have "exit" versions of the restore routines
25531 that restore the link register and can save some extra space.
25532 These require an extra suffix. (There are also "tail" versions
25533 of the restore routines and "GOT" versions of the save routines,
25534 but we don't generate those at present. Same problems apply,
25537 We deal with all this by synthesizing our own prefix/suffix and
25538 using that for the simple sprintf call shown above. */
25539 if (DEFAULT_ABI == ABI_V4)
25544 if ((sel & SAVRES_REG) == SAVRES_GPR)
25545 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25546 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25547 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25548 else if ((sel & SAVRES_REG) == SAVRES_VR)
25549 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25553 if ((sel & SAVRES_LR))
25556 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25558 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25559 /* No out-of-line save/restore routines for GPRs on AIX. */
25560 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25564 if ((sel & SAVRES_REG) == SAVRES_GPR)
25565 prefix = ((sel & SAVRES_SAVE)
25566 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25567 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25568 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25570 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25571 if ((sel & SAVRES_LR))
25572 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25576 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25577 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25580 else if ((sel & SAVRES_REG) == SAVRES_VR)
25581 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25586 if (DEFAULT_ABI == ABI_DARWIN)
25588 /* The Darwin approach is (slightly) different, in order to be
25589 compatible with code generated by the system toolchain. There is a
25590 single symbol for the start of save sequence, and the code here
25591 embeds an offset into that code on the basis of the first register
25593 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25594 if ((sel & SAVRES_REG) == SAVRES_GPR)
25595 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25596 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25597 (regno - 13) * 4, prefix, regno);
25598 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25599 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25600 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25601 else if ((sel & SAVRES_REG) == SAVRES_VR)
25602 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25603 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25608 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25610 return savres_routine_name;
25613 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25614 We are saving/restoring GPRs if GPR is true. */
25617 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25619 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25620 ? info->first_gp_reg_save
25621 : (sel & SAVRES_REG) == SAVRES_FPR
25622 ? info->first_fp_reg_save - 32
25623 : (sel & SAVRES_REG) == SAVRES_VR
25624 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25629 /* Don't generate bogus routine names. */
25630 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25631 && regno <= LAST_SAVRES_REGISTER
25632 && select >= 0 && select <= 12);
25634 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25640 name = rs6000_savres_routine_name (regno, sel);
25642 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25643 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25644 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25650 /* Emit a sequence of insns, including a stack tie if needed, for
25651 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25652 reset the stack pointer, but move the base of the frame into
25653 reg UPDT_REGNO for use by out-of-line register restore routines. */
25656 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25657 unsigned updt_regno)
25659 /* If there is nothing to do, don't do anything. */
25660 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25663 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25665 /* This blockage is needed so that sched doesn't decide to move
25666 the sp change before the register restores. */
25667 if (DEFAULT_ABI == ABI_V4)
25668 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25669 GEN_INT (frame_off)));
25671 /* If we are restoring registers out-of-line, we will be using the
25672 "exit" variants of the restore routines, which will reset the
25673 stack for us. But we do need to point updt_reg into the
25674 right place for those routines. */
25675 if (frame_off != 0)
25676 return emit_insn (gen_add3_insn (updt_reg_rtx,
25677 frame_reg_rtx, GEN_INT (frame_off)));
25679 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
25684 /* Return the register number used as a pointer by out-of-line
25685 save/restore functions. */
25687 static inline unsigned
25688 ptr_regno_for_savres (int sel)
25690 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25691 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
25692 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
25695 /* Construct a parallel rtx describing the effect of a call to an
25696 out-of-line register save/restore routine, and emit the insn
25697 or jump_insn as appropriate. */
25700 rs6000_emit_savres_rtx (rs6000_stack_t *info,
25701 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
25702 machine_mode reg_mode, int sel)
25705 int offset, start_reg, end_reg, n_regs, use_reg;
25706 int reg_size = GET_MODE_SIZE (reg_mode);
25713 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25714 ? info->first_gp_reg_save
25715 : (sel & SAVRES_REG) == SAVRES_FPR
25716 ? info->first_fp_reg_save
25717 : (sel & SAVRES_REG) == SAVRES_VR
25718 ? info->first_altivec_reg_save
25720 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25722 : (sel & SAVRES_REG) == SAVRES_FPR
25724 : (sel & SAVRES_REG) == SAVRES_VR
25725 ? LAST_ALTIVEC_REGNO + 1
25727 n_regs = end_reg - start_reg;
25728 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
25729 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
25732 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25733 RTVEC_ELT (p, offset++) = ret_rtx;
25735 RTVEC_ELT (p, offset++)
25736 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
25738 sym = rs6000_savres_routine_sym (info, sel);
25739 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
25741 use_reg = ptr_regno_for_savres (sel);
25742 if ((sel & SAVRES_REG) == SAVRES_VR)
25744 /* Vector regs are saved/restored using [reg+reg] addressing. */
25745 RTVEC_ELT (p, offset++)
25746 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25747 RTVEC_ELT (p, offset++)
25748 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
25751 RTVEC_ELT (p, offset++)
25752 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25754 for (i = 0; i < end_reg - start_reg; i++)
25755 RTVEC_ELT (p, i + offset)
25756 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
25757 frame_reg_rtx, save_area_offset + reg_size * i,
25758 (sel & SAVRES_SAVE) != 0);
25760 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25761 RTVEC_ELT (p, i + offset)
25762 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
25764 par = gen_rtx_PARALLEL (VOIDmode, p);
25766 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25768 insn = emit_jump_insn (par);
25769 JUMP_LABEL (insn) = ret_rtx;
25772 insn = emit_insn (par);
25776 /* Emit prologue code to store CR fields that need to be saved into REG. This
25777 function should only be called when moving the non-volatile CRs to REG, it
25778 is not a general purpose routine to move the entire set of CRs to REG.
25779 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
25783 rs6000_emit_prologue_move_from_cr (rtx reg)
25785 /* Only the ELFv2 ABI allows storing only selected fields. */
25786 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
25788 int i, cr_reg[8], count = 0;
25790 /* Collect CR fields that must be saved. */
25791 for (i = 0; i < 8; i++)
25792 if (save_reg_p (CR0_REGNO + i))
25793 cr_reg[count++] = i;
25795 /* If it's just a single one, use mfcrf. */
25798 rtvec p = rtvec_alloc (1);
25799 rtvec r = rtvec_alloc (2);
25800 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
25801 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
25803 = gen_rtx_SET (reg,
25804 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
25806 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
25810 /* ??? It might be better to handle count == 2 / 3 cases here
25811 as well, using logical operations to combine the values. */
25814 emit_insn (gen_prologue_movesi_from_cr (reg));
25817 /* Return whether the split-stack arg pointer (r12) is used. */
25820 split_stack_arg_pointer_used_p (void)
25822 /* If the pseudo holding the arg pointer is no longer a pseudo,
25823 then the arg pointer is used. */
25824 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
25825 && (!REG_P (cfun->machine->split_stack_arg_pointer)
25826 || (REGNO (cfun->machine->split_stack_arg_pointer)
25827 < FIRST_PSEUDO_REGISTER)))
25830 /* Unfortunately we also need to do some code scanning, since
25831 r12 may have been substituted for the pseudo. */
25833 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
25834 FOR_BB_INSNS (bb, insn)
25835 if (NONDEBUG_INSN_P (insn))
25837 /* A call destroys r12. */
25842 FOR_EACH_INSN_USE (use, insn)
25844 rtx x = DF_REF_REG (use);
25845 if (REG_P (x) && REGNO (x) == 12)
25849 FOR_EACH_INSN_DEF (def, insn)
25851 rtx x = DF_REF_REG (def);
25852 if (REG_P (x) && REGNO (x) == 12)
25856 return bitmap_bit_p (DF_LR_OUT (bb), 12);
25859 /* Return whether we need to emit an ELFv2 global entry point prologue. */
25862 rs6000_global_entry_point_needed_p (void)
25864 /* Only needed for the ELFv2 ABI. */
25865 if (DEFAULT_ABI != ABI_ELFv2)
25868 /* With -msingle-pic-base, we assume the whole program shares the same
25869 TOC, so no global entry point prologues are needed anywhere. */
25870 if (TARGET_SINGLE_PIC_BASE)
25873 /* Ensure we have a global entry point for thunks. ??? We could
25874 avoid that if the target routine doesn't need a global entry point,
25875 but we do not know whether this is the case at this point. */
25876 if (cfun->is_thunk)
25879 /* For regular functions, rs6000_emit_prologue sets this flag if the
25880 routine ever uses the TOC pointer. */
25881 return cfun->machine->r2_setup_needed;
25884 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
25886 rs6000_get_separate_components (void)
25888 rs6000_stack_t *info = rs6000_stack_info ();
25890 if (WORLD_SAVE_P (info))
25893 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
25894 && !(info->savres_strategy & REST_MULTIPLE));
25896 /* Component 0 is the save/restore of LR (done via GPR0).
25897 Component 2 is the save of the TOC (GPR2).
25898 Components 13..31 are the save/restore of GPR13..GPR31.
25899 Components 46..63 are the save/restore of FPR14..FPR31. */
25901 cfun->machine->n_components = 64;
25903 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
25904 bitmap_clear (components);
25906 int reg_size = TARGET_32BIT ? 4 : 8;
25907 int fp_reg_size = 8;
25909 /* The GPRs we need saved to the frame. */
25910 if ((info->savres_strategy & SAVE_INLINE_GPRS)
25911 && (info->savres_strategy & REST_INLINE_GPRS))
25913 int offset = info->gp_save_offset;
25915 offset += info->total_size;
25917 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
25919 if (IN_RANGE (offset, -0x8000, 0x7fff)
25920 && save_reg_p (regno))
25921 bitmap_set_bit (components, regno);
25923 offset += reg_size;
25927 /* Don't mess with the hard frame pointer. */
25928 if (frame_pointer_needed)
25929 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
25931 /* Don't mess with the fixed TOC register. */
25932 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
25933 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
25934 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
25935 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
25937 /* The FPRs we need saved to the frame. */
25938 if ((info->savres_strategy & SAVE_INLINE_FPRS)
25939 && (info->savres_strategy & REST_INLINE_FPRS))
25941 int offset = info->fp_save_offset;
25943 offset += info->total_size;
25945 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
25947 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
25948 bitmap_set_bit (components, regno);
25950 offset += fp_reg_size;
25954 /* Optimize LR save and restore if we can. This is component 0. Any
25955 out-of-line register save/restore routines need LR. */
25956 if (info->lr_save_p
25957 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
25958 && (info->savres_strategy & SAVE_INLINE_GPRS)
25959 && (info->savres_strategy & REST_INLINE_GPRS)
25960 && (info->savres_strategy & SAVE_INLINE_FPRS)
25961 && (info->savres_strategy & REST_INLINE_FPRS)
25962 && (info->savres_strategy & SAVE_INLINE_VRS)
25963 && (info->savres_strategy & REST_INLINE_VRS))
25965 int offset = info->lr_save_offset;
25967 offset += info->total_size;
25968 if (IN_RANGE (offset, -0x8000, 0x7fff))
25969 bitmap_set_bit (components, 0);
25972 /* Optimize saving the TOC. This is component 2. */
25973 if (cfun->machine->save_toc_in_prologue)
25974 bitmap_set_bit (components, 2);
25979 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
25981 rs6000_components_for_bb (basic_block bb)
25983 rs6000_stack_t *info = rs6000_stack_info ();
25985 bitmap in = DF_LIVE_IN (bb);
25986 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
25987 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
25989 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
25990 bitmap_clear (components);
25992 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
25995 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
25996 if (bitmap_bit_p (in, regno)
25997 || bitmap_bit_p (gen, regno)
25998 || bitmap_bit_p (kill, regno))
25999 bitmap_set_bit (components, regno);
26002 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26003 if (bitmap_bit_p (in, regno)
26004 || bitmap_bit_p (gen, regno)
26005 || bitmap_bit_p (kill, regno))
26006 bitmap_set_bit (components, regno);
26008 /* The link register. */
26009 if (bitmap_bit_p (in, LR_REGNO)
26010 || bitmap_bit_p (gen, LR_REGNO)
26011 || bitmap_bit_p (kill, LR_REGNO))
26012 bitmap_set_bit (components, 0);
26014 /* The TOC save. */
26015 if (bitmap_bit_p (in, TOC_REGNUM)
26016 || bitmap_bit_p (gen, TOC_REGNUM)
26017 || bitmap_bit_p (kill, TOC_REGNUM))
26018 bitmap_set_bit (components, 2);
26023 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26025 rs6000_disqualify_components (sbitmap components, edge e,
26026 sbitmap edge_components, bool /*is_prologue*/)
26028 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26029 live where we want to place that code. */
26030 if (bitmap_bit_p (edge_components, 0)
26031 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26034 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26035 "on entry to bb %d\n", e->dest->index);
26036 bitmap_clear_bit (components, 0);
26040 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26042 rs6000_emit_prologue_components (sbitmap components)
26044 rs6000_stack_t *info = rs6000_stack_info ();
26045 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26046 ? HARD_FRAME_POINTER_REGNUM
26047 : STACK_POINTER_REGNUM);
26049 machine_mode reg_mode = Pmode;
26050 int reg_size = TARGET_32BIT ? 4 : 8;
26051 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26052 int fp_reg_size = 8;
26054 /* Prologue for LR. */
26055 if (bitmap_bit_p (components, 0))
26057 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26058 rtx reg = gen_rtx_REG (reg_mode, 0);
26059 rtx_insn *insn = emit_move_insn (reg, lr);
26060 RTX_FRAME_RELATED_P (insn) = 1;
26061 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26063 int offset = info->lr_save_offset;
26065 offset += info->total_size;
26067 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26068 RTX_FRAME_RELATED_P (insn) = 1;
26069 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26070 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26073 /* Prologue for TOC. */
26074 if (bitmap_bit_p (components, 2))
26076 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26077 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26078 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26081 /* Prologue for the GPRs. */
26082 int offset = info->gp_save_offset;
26084 offset += info->total_size;
26086 for (int i = info->first_gp_reg_save; i < 32; i++)
26088 if (bitmap_bit_p (components, i))
26090 rtx reg = gen_rtx_REG (reg_mode, i);
26091 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26092 RTX_FRAME_RELATED_P (insn) = 1;
26093 rtx set = copy_rtx (single_set (insn));
26094 add_reg_note (insn, REG_CFA_OFFSET, set);
26097 offset += reg_size;
26100 /* Prologue for the FPRs. */
26101 offset = info->fp_save_offset;
26103 offset += info->total_size;
26105 for (int i = info->first_fp_reg_save; i < 64; i++)
26107 if (bitmap_bit_p (components, i))
26109 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26110 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26111 RTX_FRAME_RELATED_P (insn) = 1;
26112 rtx set = copy_rtx (single_set (insn));
26113 add_reg_note (insn, REG_CFA_OFFSET, set);
26116 offset += fp_reg_size;
26120 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26122 rs6000_emit_epilogue_components (sbitmap components)
26124 rs6000_stack_t *info = rs6000_stack_info ();
26125 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26126 ? HARD_FRAME_POINTER_REGNUM
26127 : STACK_POINTER_REGNUM);
26129 machine_mode reg_mode = Pmode;
26130 int reg_size = TARGET_32BIT ? 4 : 8;
26132 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26133 int fp_reg_size = 8;
26135 /* Epilogue for the FPRs. */
26136 int offset = info->fp_save_offset;
26138 offset += info->total_size;
26140 for (int i = info->first_fp_reg_save; i < 64; i++)
26142 if (bitmap_bit_p (components, i))
26144 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26145 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26146 RTX_FRAME_RELATED_P (insn) = 1;
26147 add_reg_note (insn, REG_CFA_RESTORE, reg);
26150 offset += fp_reg_size;
26153 /* Epilogue for the GPRs. */
26154 offset = info->gp_save_offset;
26156 offset += info->total_size;
26158 for (int i = info->first_gp_reg_save; i < 32; i++)
26160 if (bitmap_bit_p (components, i))
26162 rtx reg = gen_rtx_REG (reg_mode, i);
26163 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26164 RTX_FRAME_RELATED_P (insn) = 1;
26165 add_reg_note (insn, REG_CFA_RESTORE, reg);
26168 offset += reg_size;
26171 /* Epilogue for LR. */
26172 if (bitmap_bit_p (components, 0))
26174 int offset = info->lr_save_offset;
26176 offset += info->total_size;
26178 rtx reg = gen_rtx_REG (reg_mode, 0);
26179 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26181 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26182 insn = emit_move_insn (lr, reg);
26183 RTX_FRAME_RELATED_P (insn) = 1;
26184 add_reg_note (insn, REG_CFA_RESTORE, lr);
26188 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26190 rs6000_set_handled_components (sbitmap components)
26192 rs6000_stack_t *info = rs6000_stack_info ();
26194 for (int i = info->first_gp_reg_save; i < 32; i++)
26195 if (bitmap_bit_p (components, i))
26196 cfun->machine->gpr_is_wrapped_separately[i] = true;
26198 for (int i = info->first_fp_reg_save; i < 64; i++)
26199 if (bitmap_bit_p (components, i))
26200 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26202 if (bitmap_bit_p (components, 0))
26203 cfun->machine->lr_is_wrapped_separately = true;
26205 if (bitmap_bit_p (components, 2))
26206 cfun->machine->toc_is_wrapped_separately = true;
26209 /* VRSAVE is a bit vector representing which AltiVec registers
26210 are used. The OS uses this to determine which vector
26211 registers to save on a context switch. We need to save
26212 VRSAVE on the stack frame, add whatever AltiVec registers we
26213 used in this function, and do the corresponding magic in the
26216 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26217 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26219 /* Get VRSAVE into a GPR. */
26220 rtx reg = gen_rtx_REG (SImode, save_regno);
26221 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26223 emit_insn (gen_get_vrsave_internal (reg));
26225 emit_insn (gen_rtx_SET (reg, vrsave));
26228 int offset = info->vrsave_save_offset + frame_off;
26229 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26231 /* Include the registers in the mask. */
26232 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26234 emit_insn (generate_set_vrsave (reg, info, 0));
26237 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26238 called, it left the arg pointer to the old stack in r29. Otherwise, the
26239 arg pointer is the top of the current frame. */
26241 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26242 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26244 cfun->machine->split_stack_argp_used = true;
26248 rtx r12 = gen_rtx_REG (Pmode, 12);
26249 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26250 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26251 emit_insn_before (set_r12, sp_adjust);
26253 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26255 rtx r12 = gen_rtx_REG (Pmode, 12);
26256 if (frame_off == 0)
26257 emit_move_insn (r12, frame_reg_rtx);
26259 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26264 rtx r12 = gen_rtx_REG (Pmode, 12);
26265 rtx r29 = gen_rtx_REG (Pmode, 29);
26266 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26267 rtx not_more = gen_label_rtx ();
26270 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26271 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26272 gen_rtx_LABEL_REF (VOIDmode, not_more),
26274 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26275 JUMP_LABEL (jump) = not_more;
26276 LABEL_NUSES (not_more) += 1;
26277 emit_move_insn (r12, r29);
26278 emit_label (not_more);
26282 /* Emit function prologue as insns. */
26285 rs6000_emit_prologue (void)
26287 rs6000_stack_t *info = rs6000_stack_info ();
26288 machine_mode reg_mode = Pmode;
26289 int reg_size = TARGET_32BIT ? 4 : 8;
26290 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26291 int fp_reg_size = 8;
26292 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26293 rtx frame_reg_rtx = sp_reg_rtx;
26294 unsigned int cr_save_regno;
26295 rtx cr_save_rtx = NULL_RTX;
26298 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26299 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26300 && call_used_regs[STATIC_CHAIN_REGNUM]);
26301 int using_split_stack = (flag_split_stack
26302 && (lookup_attribute ("no_split_stack",
26303 DECL_ATTRIBUTES (cfun->decl))
26306 /* Offset to top of frame for frame_reg and sp respectively. */
26307 HOST_WIDE_INT frame_off = 0;
26308 HOST_WIDE_INT sp_off = 0;
26309 /* sp_adjust is the stack adjusting instruction, tracked so that the
26310 insn setting up the split-stack arg pointer can be emitted just
26311 prior to it, when r12 is not used here for other purposes. */
26312 rtx_insn *sp_adjust = 0;
26315 /* Track and check usage of r0, r11, r12. */
26316 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26317 #define START_USE(R) do \
26319 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26320 reg_inuse |= 1 << (R); \
26322 #define END_USE(R) do \
26324 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26325 reg_inuse &= ~(1 << (R)); \
26327 #define NOT_INUSE(R) do \
26329 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26332 #define START_USE(R) do {} while (0)
26333 #define END_USE(R) do {} while (0)
26334 #define NOT_INUSE(R) do {} while (0)
26337 if (DEFAULT_ABI == ABI_ELFv2
26338 && !TARGET_SINGLE_PIC_BASE)
26340 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26342 /* With -mminimal-toc we may generate an extra use of r2 below. */
26343 if (TARGET_TOC && TARGET_MINIMAL_TOC
26344 && !constant_pool_empty_p ())
26345 cfun->machine->r2_setup_needed = true;
26349 if (flag_stack_usage_info)
26350 current_function_static_stack_size = info->total_size;
26352 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26354 HOST_WIDE_INT size = info->total_size;
26356 if (crtl->is_leaf && !cfun->calls_alloca)
26358 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26359 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26360 size - get_stack_check_protect ());
26363 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26366 if (TARGET_FIX_AND_CONTINUE)
26368 /* gdb on darwin arranges to forward a function from the old
26369 address by modifying the first 5 instructions of the function
26370 to branch to the overriding function. This is necessary to
26371 permit function pointers that point to the old function to
26372 actually forward to the new function. */
26373 emit_insn (gen_nop ());
26374 emit_insn (gen_nop ());
26375 emit_insn (gen_nop ());
26376 emit_insn (gen_nop ());
26377 emit_insn (gen_nop ());
26380 /* Handle world saves specially here. */
26381 if (WORLD_SAVE_P (info))
26388 /* save_world expects lr in r0. */
26389 reg0 = gen_rtx_REG (Pmode, 0);
26390 if (info->lr_save_p)
26392 insn = emit_move_insn (reg0,
26393 gen_rtx_REG (Pmode, LR_REGNO));
26394 RTX_FRAME_RELATED_P (insn) = 1;
26397 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26398 assumptions about the offsets of various bits of the stack
26400 gcc_assert (info->gp_save_offset == -220
26401 && info->fp_save_offset == -144
26402 && info->lr_save_offset == 8
26403 && info->cr_save_offset == 4
26406 && (!crtl->calls_eh_return
26407 || info->ehrd_offset == -432)
26408 && info->vrsave_save_offset == -224
26409 && info->altivec_save_offset == -416);
26411 treg = gen_rtx_REG (SImode, 11);
26412 emit_move_insn (treg, GEN_INT (-info->total_size));
26414 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26415 in R11. It also clobbers R12, so beware! */
26417 /* Preserve CR2 for save_world prologues */
26419 sz += 32 - info->first_gp_reg_save;
26420 sz += 64 - info->first_fp_reg_save;
26421 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26422 p = rtvec_alloc (sz);
26424 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
26425 gen_rtx_REG (SImode,
26427 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26428 gen_rtx_SYMBOL_REF (Pmode,
26430 /* We do floats first so that the instruction pattern matches
26432 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26434 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26435 info->first_fp_reg_save + i),
26437 info->fp_save_offset + frame_off + 8 * i);
26438 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26440 = gen_frame_store (gen_rtx_REG (V4SImode,
26441 info->first_altivec_reg_save + i),
26443 info->altivec_save_offset + frame_off + 16 * i);
26444 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26446 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26448 info->gp_save_offset + frame_off + reg_size * i);
26450 /* CR register traditionally saved as CR2. */
26452 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26453 frame_reg_rtx, info->cr_save_offset + frame_off);
26454 /* Explain about use of R0. */
26455 if (info->lr_save_p)
26457 = gen_frame_store (reg0,
26458 frame_reg_rtx, info->lr_save_offset + frame_off);
26459 /* Explain what happens to the stack pointer. */
26461 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26462 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26465 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26466 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26467 treg, GEN_INT (-info->total_size));
26468 sp_off = frame_off = info->total_size;
26471 strategy = info->savres_strategy;
26473 /* For V.4, update stack before we do any saving and set back pointer. */
26474 if (! WORLD_SAVE_P (info)
26476 && (DEFAULT_ABI == ABI_V4
26477 || crtl->calls_eh_return))
26479 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26480 || !(strategy & SAVE_INLINE_GPRS)
26481 || !(strategy & SAVE_INLINE_VRS));
26482 int ptr_regno = -1;
26483 rtx ptr_reg = NULL_RTX;
26486 if (info->total_size < 32767)
26487 frame_off = info->total_size;
26490 else if (info->cr_save_p
26492 || info->first_fp_reg_save < 64
26493 || info->first_gp_reg_save < 32
26494 || info->altivec_size != 0
26495 || info->vrsave_size != 0
26496 || crtl->calls_eh_return)
26500 /* The prologue won't be saving any regs so there is no need
26501 to set up a frame register to access any frame save area.
26502 We also won't be using frame_off anywhere below, but set
26503 the correct value anyway to protect against future
26504 changes to this function. */
26505 frame_off = info->total_size;
26507 if (ptr_regno != -1)
26509 /* Set up the frame offset to that needed by the first
26510 out-of-line save function. */
26511 START_USE (ptr_regno);
26512 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26513 frame_reg_rtx = ptr_reg;
26514 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26515 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26516 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26517 ptr_off = info->gp_save_offset + info->gp_size;
26518 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26519 ptr_off = info->altivec_save_offset + info->altivec_size;
26520 frame_off = -ptr_off;
26522 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26524 if (REGNO (frame_reg_rtx) == 12)
26526 sp_off = info->total_size;
26527 if (frame_reg_rtx != sp_reg_rtx)
26528 rs6000_emit_stack_tie (frame_reg_rtx, false);
26531 /* If we use the link register, get it into r0. */
26532 if (!WORLD_SAVE_P (info) && info->lr_save_p
26533 && !cfun->machine->lr_is_wrapped_separately)
26535 rtx addr, reg, mem;
26537 reg = gen_rtx_REG (Pmode, 0);
26539 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26540 RTX_FRAME_RELATED_P (insn) = 1;
26542 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26543 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26545 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26546 GEN_INT (info->lr_save_offset + frame_off));
26547 mem = gen_rtx_MEM (Pmode, addr);
26548 /* This should not be of rs6000_sr_alias_set, because of
26549 __builtin_return_address. */
26551 insn = emit_move_insn (mem, reg);
26552 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26553 NULL_RTX, NULL_RTX);
26558 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26559 r12 will be needed by out-of-line gpr restore. */
26560 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26561 && !(strategy & (SAVE_INLINE_GPRS
26562 | SAVE_NOINLINE_GPRS_SAVES_LR))
26564 if (!WORLD_SAVE_P (info)
26566 && REGNO (frame_reg_rtx) != cr_save_regno
26567 && !(using_static_chain_p && cr_save_regno == 11)
26568 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26570 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26571 START_USE (cr_save_regno);
26572 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26575 /* Do any required saving of fpr's. If only one or two to save, do
26576 it ourselves. Otherwise, call function. */
26577 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26579 int offset = info->fp_save_offset + frame_off;
26580 for (int i = info->first_fp_reg_save; i < 64; i++)
26583 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26584 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26585 sp_off - frame_off);
26587 offset += fp_reg_size;
26590 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26592 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26593 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26594 unsigned ptr_regno = ptr_regno_for_savres (sel);
26595 rtx ptr_reg = frame_reg_rtx;
26597 if (REGNO (frame_reg_rtx) == ptr_regno)
26598 gcc_checking_assert (frame_off == 0);
26601 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26602 NOT_INUSE (ptr_regno);
26603 emit_insn (gen_add3_insn (ptr_reg,
26604 frame_reg_rtx, GEN_INT (frame_off)));
26606 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26607 info->fp_save_offset,
26608 info->lr_save_offset,
26610 rs6000_frame_related (insn, ptr_reg, sp_off,
26611 NULL_RTX, NULL_RTX);
26616 /* Save GPRs. This is done as a PARALLEL if we are using
26617 the store-multiple instructions. */
26618 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26620 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26621 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26622 unsigned ptr_regno = ptr_regno_for_savres (sel);
26623 rtx ptr_reg = frame_reg_rtx;
26624 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26625 int end_save = info->gp_save_offset + info->gp_size;
26628 if (ptr_regno == 12)
26631 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26633 /* Need to adjust r11 (r12) if we saved any FPRs. */
26634 if (end_save + frame_off != 0)
26636 rtx offset = GEN_INT (end_save + frame_off);
26639 frame_off = -end_save;
26641 NOT_INUSE (ptr_regno);
26642 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26644 else if (!ptr_set_up)
26646 NOT_INUSE (ptr_regno);
26647 emit_move_insn (ptr_reg, frame_reg_rtx);
26649 ptr_off = -end_save;
26650 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26651 info->gp_save_offset + ptr_off,
26652 info->lr_save_offset + ptr_off,
26654 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26655 NULL_RTX, NULL_RTX);
26659 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26663 p = rtvec_alloc (32 - info->first_gp_reg_save);
26664 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26666 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26668 info->gp_save_offset + frame_off + reg_size * i);
26669 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26670 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26671 NULL_RTX, NULL_RTX);
26673 else if (!WORLD_SAVE_P (info))
26675 int offset = info->gp_save_offset + frame_off;
26676 for (int i = info->first_gp_reg_save; i < 32; i++)
26679 && !cfun->machine->gpr_is_wrapped_separately[i])
26680 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26681 sp_off - frame_off);
26683 offset += reg_size;
26687 if (crtl->calls_eh_return)
26694 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26695 if (regno == INVALID_REGNUM)
26699 p = rtvec_alloc (i);
26703 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26704 if (regno == INVALID_REGNUM)
26708 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
26710 info->ehrd_offset + sp_off + reg_size * (int) i);
26711 RTVEC_ELT (p, i) = set;
26712 RTX_FRAME_RELATED_P (set) = 1;
26715 insn = emit_insn (gen_blockage ());
26716 RTX_FRAME_RELATED_P (insn) = 1;
26717 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
26720 /* In AIX ABI we need to make sure r2 is really saved. */
26721 if (TARGET_AIX && crtl->calls_eh_return)
26723 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
26724 rtx join_insn, note;
26725 rtx_insn *save_insn;
26726 long toc_restore_insn;
26728 tmp_reg = gen_rtx_REG (Pmode, 11);
26729 tmp_reg_si = gen_rtx_REG (SImode, 11);
26730 if (using_static_chain_p)
26733 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
26737 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
26738 /* Peek at instruction to which this function returns. If it's
26739 restoring r2, then we know we've already saved r2. We can't
26740 unconditionally save r2 because the value we have will already
26741 be updated if we arrived at this function via a plt call or
26742 toc adjusting stub. */
26743 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
26744 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
26745 + RS6000_TOC_SAVE_SLOT);
26746 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
26747 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
26748 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
26749 validate_condition_mode (EQ, CCUNSmode);
26750 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
26751 emit_insn (gen_rtx_SET (compare_result,
26752 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
26753 toc_save_done = gen_label_rtx ();
26754 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26755 gen_rtx_EQ (VOIDmode, compare_result,
26757 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
26759 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26760 JUMP_LABEL (jump) = toc_save_done;
26761 LABEL_NUSES (toc_save_done) += 1;
26763 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
26764 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
26765 sp_off - frame_off);
26767 emit_label (toc_save_done);
26769 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
26770 have a CFG that has different saves along different paths.
26771 Move the note to a dummy blockage insn, which describes that
26772 R2 is unconditionally saved after the label. */
26773 /* ??? An alternate representation might be a special insn pattern
26774 containing both the branch and the store. That might let the
26775 code that minimizes the number of DW_CFA_advance opcodes better
26776 freedom in placing the annotations. */
26777 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
26779 remove_note (save_insn, note);
26781 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
26782 copy_rtx (PATTERN (save_insn)), NULL_RTX);
26783 RTX_FRAME_RELATED_P (save_insn) = 0;
26785 join_insn = emit_insn (gen_blockage ());
26786 REG_NOTES (join_insn) = note;
26787 RTX_FRAME_RELATED_P (join_insn) = 1;
26789 if (using_static_chain_p)
26791 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
26798 /* Save CR if we use any that must be preserved. */
26799 if (!WORLD_SAVE_P (info) && info->cr_save_p)
26801 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26802 GEN_INT (info->cr_save_offset + frame_off));
26803 rtx mem = gen_frame_mem (SImode, addr);
26805 /* If we didn't copy cr before, do so now using r0. */
26806 if (cr_save_rtx == NULL_RTX)
26809 cr_save_rtx = gen_rtx_REG (SImode, 0);
26810 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26813 /* Saving CR requires a two-instruction sequence: one instruction
26814 to move the CR to a general-purpose register, and a second
26815 instruction that stores the GPR to memory.
26817 We do not emit any DWARF CFI records for the first of these,
26818 because we cannot properly represent the fact that CR is saved in
26819 a register. One reason is that we cannot express that multiple
26820 CR fields are saved; another reason is that on 64-bit, the size
26821 of the CR register in DWARF (4 bytes) differs from the size of
26822 a general-purpose register.
26824 This means if any intervening instruction were to clobber one of
26825 the call-saved CR fields, we'd have incorrect CFI. To prevent
26826 this from happening, we mark the store to memory as a use of
26827 those CR fields, which prevents any such instruction from being
26828 scheduled in between the two instructions. */
26833 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
26834 for (i = 0; i < 8; i++)
26835 if (save_reg_p (CR0_REGNO + i))
26836 crsave_v[n_crsave++]
26837 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
26839 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
26840 gen_rtvec_v (n_crsave, crsave_v)));
26841 END_USE (REGNO (cr_save_rtx));
26843 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
26844 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
26845 so we need to construct a frame expression manually. */
26846 RTX_FRAME_RELATED_P (insn) = 1;
26848 /* Update address to be stack-pointer relative, like
26849 rs6000_frame_related would do. */
26850 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26851 GEN_INT (info->cr_save_offset + sp_off));
26852 mem = gen_frame_mem (SImode, addr);
26854 if (DEFAULT_ABI == ABI_ELFv2)
26856 /* In the ELFv2 ABI we generate separate CFI records for each
26857 CR field that was actually saved. They all point to the
26858 same 32-bit stack slot. */
26862 for (i = 0; i < 8; i++)
26863 if (save_reg_p (CR0_REGNO + i))
26866 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
26868 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
26872 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
26873 gen_rtx_PARALLEL (VOIDmode,
26874 gen_rtvec_v (n_crframe, crframe)));
26878 /* In other ABIs, by convention, we use a single CR regnum to
26879 represent the fact that all call-saved CR fields are saved.
26880 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
26881 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
26882 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
26886 /* In the ELFv2 ABI we need to save all call-saved CR fields into
26887 *separate* slots if the routine calls __builtin_eh_return, so
26888 that they can be independently restored by the unwinder. */
26889 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
26891 int i, cr_off = info->ehcr_offset;
26894 /* ??? We might get better performance by using multiple mfocrf
26896 crsave = gen_rtx_REG (SImode, 0);
26897 emit_insn (gen_prologue_movesi_from_cr (crsave));
26899 for (i = 0; i < 8; i++)
26900 if (!call_used_regs[CR0_REGNO + i])
26902 rtvec p = rtvec_alloc (2);
26904 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
26906 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
26908 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26910 RTX_FRAME_RELATED_P (insn) = 1;
26911 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
26912 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
26913 sp_reg_rtx, cr_off + sp_off));
26915 cr_off += reg_size;
26919 /* If we are emitting stack probes, but allocate no stack, then
26920 just note that in the dump file. */
26921 if (flag_stack_clash_protection
26924 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
26926 /* Update stack and set back pointer unless this is V.4,
26927 for which it was done previously. */
26928 if (!WORLD_SAVE_P (info) && info->push_p
26929 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
26931 rtx ptr_reg = NULL;
26934 /* If saving altivec regs we need to be able to address all save
26935 locations using a 16-bit offset. */
26936 if ((strategy & SAVE_INLINE_VRS) == 0
26937 || (info->altivec_size != 0
26938 && (info->altivec_save_offset + info->altivec_size - 16
26939 + info->total_size - frame_off) > 32767)
26940 || (info->vrsave_size != 0
26941 && (info->vrsave_save_offset
26942 + info->total_size - frame_off) > 32767))
26944 int sel = SAVRES_SAVE | SAVRES_VR;
26945 unsigned ptr_regno = ptr_regno_for_savres (sel);
26947 if (using_static_chain_p
26948 && ptr_regno == STATIC_CHAIN_REGNUM)
26950 if (REGNO (frame_reg_rtx) != ptr_regno)
26951 START_USE (ptr_regno);
26952 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26953 frame_reg_rtx = ptr_reg;
26954 ptr_off = info->altivec_save_offset + info->altivec_size;
26955 frame_off = -ptr_off;
26957 else if (REGNO (frame_reg_rtx) == 1)
26958 frame_off = info->total_size;
26959 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26961 if (REGNO (frame_reg_rtx) == 12)
26963 sp_off = info->total_size;
26964 if (frame_reg_rtx != sp_reg_rtx)
26965 rs6000_emit_stack_tie (frame_reg_rtx, false);
26968 /* Set frame pointer, if needed. */
26969 if (frame_pointer_needed)
26971 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
26973 RTX_FRAME_RELATED_P (insn) = 1;
26976 /* Save AltiVec registers if needed. Save here because the red zone does
26977 not always include AltiVec registers. */
26978 if (!WORLD_SAVE_P (info)
26979 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
26981 int end_save = info->altivec_save_offset + info->altivec_size;
26983 /* Oddly, the vector save/restore functions point r0 at the end
26984 of the save area, then use r11 or r12 to load offsets for
26985 [reg+reg] addressing. */
26986 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
26987 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
26988 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
26990 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
26992 if (scratch_regno == 12)
26994 if (end_save + frame_off != 0)
26996 rtx offset = GEN_INT (end_save + frame_off);
26998 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27001 emit_move_insn (ptr_reg, frame_reg_rtx);
27003 ptr_off = -end_save;
27004 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27005 info->altivec_save_offset + ptr_off,
27006 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27007 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27008 NULL_RTX, NULL_RTX);
27009 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27011 /* The oddity mentioned above clobbered our frame reg. */
27012 emit_move_insn (frame_reg_rtx, ptr_reg);
27013 frame_off = ptr_off;
27016 else if (!WORLD_SAVE_P (info)
27017 && info->altivec_size != 0)
27021 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27022 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27024 rtx areg, savereg, mem;
27025 HOST_WIDE_INT offset;
27027 offset = (info->altivec_save_offset + frame_off
27028 + 16 * (i - info->first_altivec_reg_save));
27030 savereg = gen_rtx_REG (V4SImode, i);
27032 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27034 mem = gen_frame_mem (V4SImode,
27035 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27036 GEN_INT (offset)));
27037 insn = emit_insn (gen_rtx_SET (mem, savereg));
27043 areg = gen_rtx_REG (Pmode, 0);
27044 emit_move_insn (areg, GEN_INT (offset));
27046 /* AltiVec addressing mode is [reg+reg]. */
27047 mem = gen_frame_mem (V4SImode,
27048 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27050 /* Rather than emitting a generic move, force use of the stvx
27051 instruction, which we always want on ISA 2.07 (power8) systems.
27052 In particular we don't want xxpermdi/stxvd2x for little
27054 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27057 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27058 areg, GEN_INT (offset));
27062 /* VRSAVE is a bit vector representing which AltiVec registers
27063 are used. The OS uses this to determine which vector
27064 registers to save on a context switch. We need to save
27065 VRSAVE on the stack frame, add whatever AltiVec registers we
27066 used in this function, and do the corresponding magic in the
27069 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27071 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27072 be using r12 as frame_reg_rtx and r11 as the static chain
27073 pointer for nested functions. */
27074 int save_regno = 12;
27075 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27076 && !using_static_chain_p)
27078 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27081 if (using_static_chain_p)
27084 NOT_INUSE (save_regno);
27086 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27089 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27090 if (!TARGET_SINGLE_PIC_BASE
27091 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27092 && !constant_pool_empty_p ())
27093 || (DEFAULT_ABI == ABI_V4
27094 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27095 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27097 /* If emit_load_toc_table will use the link register, we need to save
27098 it. We use R12 for this purpose because emit_load_toc_table
27099 can use register 0. This allows us to use a plain 'blr' to return
27100 from the procedure more often. */
27101 int save_LR_around_toc_setup = (TARGET_ELF
27102 && DEFAULT_ABI == ABI_V4
27104 && ! info->lr_save_p
27105 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27106 if (save_LR_around_toc_setup)
27108 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27109 rtx tmp = gen_rtx_REG (Pmode, 12);
27112 insn = emit_move_insn (tmp, lr);
27113 RTX_FRAME_RELATED_P (insn) = 1;
27115 rs6000_emit_load_toc_table (TRUE);
27117 insn = emit_move_insn (lr, tmp);
27118 add_reg_note (insn, REG_CFA_RESTORE, lr);
27119 RTX_FRAME_RELATED_P (insn) = 1;
27122 rs6000_emit_load_toc_table (TRUE);
27126 if (!TARGET_SINGLE_PIC_BASE
27127 && DEFAULT_ABI == ABI_DARWIN
27128 && flag_pic && crtl->uses_pic_offset_table)
27130 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27131 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27133 /* Save and restore LR locally around this call (in R0). */
27134 if (!info->lr_save_p)
27135 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27137 emit_insn (gen_load_macho_picbase (src));
27139 emit_move_insn (gen_rtx_REG (Pmode,
27140 RS6000_PIC_OFFSET_TABLE_REGNUM),
27143 if (!info->lr_save_p)
27144 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27148 /* If we need to, save the TOC register after doing the stack setup.
27149 Do not emit eh frame info for this save. The unwinder wants info,
27150 conceptually attached to instructions in this function, about
27151 register values in the caller of this function. This R2 may have
27152 already been changed from the value in the caller.
27153 We don't attempt to write accurate DWARF EH frame info for R2
27154 because code emitted by gcc for a (non-pointer) function call
27155 doesn't save and restore R2. Instead, R2 is managed out-of-line
27156 by a linker generated plt call stub when the function resides in
27157 a shared library. This behavior is costly to describe in DWARF,
27158 both in terms of the size of DWARF info and the time taken in the
27159 unwinder to interpret it. R2 changes, apart from the
27160 calls_eh_return case earlier in this function, are handled by
27161 linux-unwind.h frob_update_context. */
27162 if (rs6000_save_toc_in_prologue_p ()
27163 && !cfun->machine->toc_is_wrapped_separately)
27165 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27166 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27169 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27170 if (using_split_stack && split_stack_arg_pointer_used_p ())
27171 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27174 /* Output .extern statements for the save/restore routines we use. */
27177 rs6000_output_savres_externs (FILE *file)
27179 rs6000_stack_t *info = rs6000_stack_info ();
27181 if (TARGET_DEBUG_STACK)
27182 debug_stack_info (info);
27184 /* Write .extern for any function we will call to save and restore
27186 if (info->first_fp_reg_save < 64
27191 int regno = info->first_fp_reg_save - 32;
27193 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27195 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27196 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27197 name = rs6000_savres_routine_name (regno, sel);
27198 fprintf (file, "\t.extern %s\n", name);
27200 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27202 bool lr = (info->savres_strategy
27203 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27204 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27205 name = rs6000_savres_routine_name (regno, sel);
27206 fprintf (file, "\t.extern %s\n", name);
27211 /* Write function prologue. */
27214 rs6000_output_function_prologue (FILE *file)
27216 if (!cfun->is_thunk)
27217 rs6000_output_savres_externs (file);
27219 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27220 immediately after the global entry point label. */
27221 if (rs6000_global_entry_point_needed_p ())
27223 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27225 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27227 if (TARGET_CMODEL != CMODEL_LARGE)
27229 /* In the small and medium code models, we assume the TOC is less
27230 2 GB away from the text section, so it can be computed via the
27231 following two-instruction sequence. */
27234 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27235 fprintf (file, "0:\taddis 2,12,.TOC.-");
27236 assemble_name (file, buf);
27237 fprintf (file, "@ha\n");
27238 fprintf (file, "\taddi 2,2,.TOC.-");
27239 assemble_name (file, buf);
27240 fprintf (file, "@l\n");
27244 /* In the large code model, we allow arbitrary offsets between the
27245 TOC and the text section, so we have to load the offset from
27246 memory. The data field is emitted directly before the global
27247 entry point in rs6000_elf_declare_function_name. */
27250 #ifdef HAVE_AS_ENTRY_MARKERS
27251 /* If supported by the linker, emit a marker relocation. If the
27252 total code size of the final executable or shared library
27253 happens to fit into 2 GB after all, the linker will replace
27254 this code sequence with the sequence for the small or medium
27256 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27258 fprintf (file, "\tld 2,");
27259 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27260 assemble_name (file, buf);
27261 fprintf (file, "-");
27262 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27263 assemble_name (file, buf);
27264 fprintf (file, "(12)\n");
27265 fprintf (file, "\tadd 2,2,12\n");
27268 fputs ("\t.localentry\t", file);
27269 assemble_name (file, name);
27270 fputs (",.-", file);
27271 assemble_name (file, name);
27272 fputs ("\n", file);
27275 /* Output -mprofile-kernel code. This needs to be done here instead of
27276 in output_function_profile since it must go after the ELFv2 ABI
27277 local entry point. */
27278 if (TARGET_PROFILE_KERNEL && crtl->profile)
27280 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27281 gcc_assert (!TARGET_32BIT);
27283 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27285 /* In the ELFv2 ABI we have no compiler stack word. It must be
27286 the resposibility of _mcount to preserve the static chain
27287 register if required. */
27288 if (DEFAULT_ABI != ABI_ELFv2
27289 && cfun->static_chain_decl != NULL)
27291 asm_fprintf (file, "\tstd %s,24(%s)\n",
27292 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27293 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27294 asm_fprintf (file, "\tld %s,24(%s)\n",
27295 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27298 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27301 rs6000_pic_labelno++;
27304 /* -mprofile-kernel code calls mcount before the function prolog,
27305 so a profiled leaf function should stay a leaf function. */
27307 rs6000_keep_leaf_when_profiled ()
27309 return TARGET_PROFILE_KERNEL;
27312 /* Non-zero if vmx regs are restored before the frame pop, zero if
27313 we restore after the pop when possible. */
27314 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27316 /* Restoring cr is a two step process: loading a reg from the frame
27317 save, then moving the reg to cr. For ABI_V4 we must let the
27318 unwinder know that the stack location is no longer valid at or
27319 before the stack deallocation, but we can't emit a cfa_restore for
27320 cr at the stack deallocation like we do for other registers.
27321 The trouble is that it is possible for the move to cr to be
27322 scheduled after the stack deallocation. So say exactly where cr
27323 is located on each of the two insns. */
27326 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27328 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27329 rtx reg = gen_rtx_REG (SImode, regno);
27330 rtx_insn *insn = emit_move_insn (reg, mem);
27332 if (!exit_func && DEFAULT_ABI == ABI_V4)
27334 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27335 rtx set = gen_rtx_SET (reg, cr);
27337 add_reg_note (insn, REG_CFA_REGISTER, set);
27338 RTX_FRAME_RELATED_P (insn) = 1;
27343 /* Reload CR from REG. */
27346 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
27351 if (using_mfcr_multiple)
27353 for (i = 0; i < 8; i++)
27354 if (save_reg_p (CR0_REGNO + i))
27356 gcc_assert (count);
27359 if (using_mfcr_multiple && count > 1)
27365 p = rtvec_alloc (count);
27368 for (i = 0; i < 8; i++)
27369 if (save_reg_p (CR0_REGNO + i))
27371 rtvec r = rtvec_alloc (2);
27372 RTVEC_ELT (r, 0) = reg;
27373 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27374 RTVEC_ELT (p, ndx) =
27375 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27376 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27379 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27380 gcc_assert (ndx == count);
27382 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27383 CR field separately. */
27384 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27386 for (i = 0; i < 8; i++)
27387 if (save_reg_p (CR0_REGNO + i))
27388 add_reg_note (insn, REG_CFA_RESTORE,
27389 gen_rtx_REG (SImode, CR0_REGNO + i));
27391 RTX_FRAME_RELATED_P (insn) = 1;
27395 for (i = 0; i < 8; i++)
27396 if (save_reg_p (CR0_REGNO + i))
27398 rtx insn = emit_insn (gen_movsi_to_cr_one
27399 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27401 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27402 CR field separately, attached to the insn that in fact
27403 restores this particular CR field. */
27404 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27406 add_reg_note (insn, REG_CFA_RESTORE,
27407 gen_rtx_REG (SImode, CR0_REGNO + i));
27409 RTX_FRAME_RELATED_P (insn) = 1;
27413 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27414 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27415 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27417 rtx_insn *insn = get_last_insn ();
27418 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27420 add_reg_note (insn, REG_CFA_RESTORE, cr);
27421 RTX_FRAME_RELATED_P (insn) = 1;
27425 /* Like cr, the move to lr instruction can be scheduled after the
27426 stack deallocation, but unlike cr, its stack frame save is still
27427 valid. So we only need to emit the cfa_restore on the correct
27431 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27433 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27434 rtx reg = gen_rtx_REG (Pmode, regno);
27436 emit_move_insn (reg, mem);
27440 restore_saved_lr (int regno, bool exit_func)
27442 rtx reg = gen_rtx_REG (Pmode, regno);
27443 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27444 rtx_insn *insn = emit_move_insn (lr, reg);
27446 if (!exit_func && flag_shrink_wrap)
27448 add_reg_note (insn, REG_CFA_RESTORE, lr);
27449 RTX_FRAME_RELATED_P (insn) = 1;
27454 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27456 if (DEFAULT_ABI == ABI_ELFv2)
27459 for (i = 0; i < 8; i++)
27460 if (save_reg_p (CR0_REGNO + i))
27462 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27463 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27467 else if (info->cr_save_p)
27468 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27469 gen_rtx_REG (SImode, CR2_REGNO),
27472 if (info->lr_save_p)
27473 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27474 gen_rtx_REG (Pmode, LR_REGNO),
27476 return cfa_restores;
27479 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27480 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27481 below stack pointer not cloberred by signals. */
27484 offset_below_red_zone_p (HOST_WIDE_INT offset)
27486 return offset < (DEFAULT_ABI == ABI_V4
27488 : TARGET_32BIT ? -220 : -288);
27491 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27494 emit_cfa_restores (rtx cfa_restores)
27496 rtx_insn *insn = get_last_insn ();
27497 rtx *loc = ®_NOTES (insn);
27500 loc = &XEXP (*loc, 1);
27501 *loc = cfa_restores;
27502 RTX_FRAME_RELATED_P (insn) = 1;
27505 /* Emit function epilogue as insns. */
27508 rs6000_emit_epilogue (int sibcall)
27510 rs6000_stack_t *info;
27511 int restoring_GPRs_inline;
27512 int restoring_FPRs_inline;
27513 int using_load_multiple;
27514 int using_mtcr_multiple;
27515 int use_backchain_to_restore_sp;
27518 HOST_WIDE_INT frame_off = 0;
27519 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27520 rtx frame_reg_rtx = sp_reg_rtx;
27521 rtx cfa_restores = NULL_RTX;
27523 rtx cr_save_reg = NULL_RTX;
27524 machine_mode reg_mode = Pmode;
27525 int reg_size = TARGET_32BIT ? 4 : 8;
27526 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27527 int fp_reg_size = 8;
27530 unsigned ptr_regno;
27532 info = rs6000_stack_info ();
27534 strategy = info->savres_strategy;
27535 using_load_multiple = strategy & REST_MULTIPLE;
27536 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
27537 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
27538 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27539 || rs6000_tune == PROCESSOR_PPC603
27540 || rs6000_tune == PROCESSOR_PPC750
27542 /* Restore via the backchain when we have a large frame, since this
27543 is more efficient than an addis, addi pair. The second condition
27544 here will not trigger at the moment; We don't actually need a
27545 frame pointer for alloca, but the generic parts of the compiler
27546 give us one anyway. */
27547 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
27548 ? info->lr_save_offset
27550 || (cfun->calls_alloca
27551 && !frame_pointer_needed));
27552 restore_lr = (info->lr_save_p
27553 && (restoring_FPRs_inline
27554 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27555 && (restoring_GPRs_inline
27556 || info->first_fp_reg_save < 64)
27557 && !cfun->machine->lr_is_wrapped_separately);
27560 if (WORLD_SAVE_P (info))
27564 const char *alloc_rname;
27567 /* eh_rest_world_r10 will return to the location saved in the LR
27568 stack slot (which is not likely to be our caller.)
27569 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27570 rest_world is similar, except any R10 parameter is ignored.
27571 The exception-handling stuff that was here in 2.95 is no
27572 longer necessary. */
27575 + 32 - info->first_gp_reg_save
27576 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27577 + 63 + 1 - info->first_fp_reg_save);
27579 strcpy (rname, ((crtl->calls_eh_return) ?
27580 "*eh_rest_world_r10" : "*rest_world"));
27581 alloc_rname = ggc_strdup (rname);
27584 RTVEC_ELT (p, j++) = ret_rtx;
27586 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
27587 /* The instruction pattern requires a clobber here;
27588 it is shared with the restVEC helper. */
27590 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
27593 /* CR register traditionally saved as CR2. */
27594 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27596 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27597 if (flag_shrink_wrap)
27599 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27600 gen_rtx_REG (Pmode, LR_REGNO),
27602 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27606 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27608 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27610 = gen_frame_load (reg,
27611 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27612 if (flag_shrink_wrap
27613 && save_reg_p (info->first_gp_reg_save + i))
27614 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27616 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27618 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27620 = gen_frame_load (reg,
27621 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27622 if (flag_shrink_wrap
27623 && save_reg_p (info->first_altivec_reg_save + i))
27624 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27626 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27628 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27629 info->first_fp_reg_save + i);
27631 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27632 if (flag_shrink_wrap
27633 && save_reg_p (info->first_fp_reg_save + i))
27634 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27637 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
27639 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
27641 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
27643 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
27645 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27646 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27648 if (flag_shrink_wrap)
27650 REG_NOTES (insn) = cfa_restores;
27651 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27652 RTX_FRAME_RELATED_P (insn) = 1;
27657 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27659 frame_off = info->total_size;
27661 /* Restore AltiVec registers if we must do so before adjusting the
27663 if (info->altivec_size != 0
27664 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27665 || (DEFAULT_ABI != ABI_V4
27666 && offset_below_red_zone_p (info->altivec_save_offset))))
27669 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27671 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27672 if (use_backchain_to_restore_sp)
27674 int frame_regno = 11;
27676 if ((strategy & REST_INLINE_VRS) == 0)
27678 /* Of r11 and r12, select the one not clobbered by an
27679 out-of-line restore function for the frame register. */
27680 frame_regno = 11 + 12 - scratch_regno;
27682 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
27683 emit_move_insn (frame_reg_rtx,
27684 gen_rtx_MEM (Pmode, sp_reg_rtx));
27687 else if (frame_pointer_needed)
27688 frame_reg_rtx = hard_frame_pointer_rtx;
27690 if ((strategy & REST_INLINE_VRS) == 0)
27692 int end_save = info->altivec_save_offset + info->altivec_size;
27694 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27695 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27697 if (end_save + frame_off != 0)
27699 rtx offset = GEN_INT (end_save + frame_off);
27701 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27704 emit_move_insn (ptr_reg, frame_reg_rtx);
27706 ptr_off = -end_save;
27707 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27708 info->altivec_save_offset + ptr_off,
27709 0, V4SImode, SAVRES_VR);
27713 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27714 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27716 rtx addr, areg, mem, insn;
27717 rtx reg = gen_rtx_REG (V4SImode, i);
27718 HOST_WIDE_INT offset
27719 = (info->altivec_save_offset + frame_off
27720 + 16 * (i - info->first_altivec_reg_save));
27722 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27724 mem = gen_frame_mem (V4SImode,
27725 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27726 GEN_INT (offset)));
27727 insn = gen_rtx_SET (reg, mem);
27731 areg = gen_rtx_REG (Pmode, 0);
27732 emit_move_insn (areg, GEN_INT (offset));
27734 /* AltiVec addressing mode is [reg+reg]. */
27735 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
27736 mem = gen_frame_mem (V4SImode, addr);
27738 /* Rather than emitting a generic move, force use of the
27739 lvx instruction, which we always want. In particular we
27740 don't want lxvd2x/xxpermdi for little endian. */
27741 insn = gen_altivec_lvx_v4si_internal (reg, mem);
27744 (void) emit_insn (insn);
27748 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27749 if (((strategy & REST_INLINE_VRS) == 0
27750 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
27751 && (flag_shrink_wrap
27752 || (offset_below_red_zone_p
27753 (info->altivec_save_offset
27754 + 16 * (i - info->first_altivec_reg_save))))
27757 rtx reg = gen_rtx_REG (V4SImode, i);
27758 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27762 /* Restore VRSAVE if we must do so before adjusting the stack. */
27763 if (info->vrsave_size != 0
27764 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27765 || (DEFAULT_ABI != ABI_V4
27766 && offset_below_red_zone_p (info->vrsave_save_offset))))
27770 if (frame_reg_rtx == sp_reg_rtx)
27772 if (use_backchain_to_restore_sp)
27774 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27775 emit_move_insn (frame_reg_rtx,
27776 gen_rtx_MEM (Pmode, sp_reg_rtx));
27779 else if (frame_pointer_needed)
27780 frame_reg_rtx = hard_frame_pointer_rtx;
27783 reg = gen_rtx_REG (SImode, 12);
27784 emit_insn (gen_frame_load (reg, frame_reg_rtx,
27785 info->vrsave_save_offset + frame_off));
27787 emit_insn (generate_set_vrsave (reg, info, 1));
27791 /* If we have a large stack frame, restore the old stack pointer
27792 using the backchain. */
27793 if (use_backchain_to_restore_sp)
27795 if (frame_reg_rtx == sp_reg_rtx)
27797 /* Under V.4, don't reset the stack pointer until after we're done
27798 loading the saved registers. */
27799 if (DEFAULT_ABI == ABI_V4)
27800 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27802 insn = emit_move_insn (frame_reg_rtx,
27803 gen_rtx_MEM (Pmode, sp_reg_rtx));
27806 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27807 && DEFAULT_ABI == ABI_V4)
27808 /* frame_reg_rtx has been set up by the altivec restore. */
27812 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
27813 frame_reg_rtx = sp_reg_rtx;
27816 /* If we have a frame pointer, we can restore the old stack pointer
27818 else if (frame_pointer_needed)
27820 frame_reg_rtx = sp_reg_rtx;
27821 if (DEFAULT_ABI == ABI_V4)
27822 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27823 /* Prevent reordering memory accesses against stack pointer restore. */
27824 else if (cfun->calls_alloca
27825 || offset_below_red_zone_p (-info->total_size))
27826 rs6000_emit_stack_tie (frame_reg_rtx, true);
27828 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
27829 GEN_INT (info->total_size)));
27832 else if (info->push_p
27833 && DEFAULT_ABI != ABI_V4
27834 && !crtl->calls_eh_return)
27836 /* Prevent reordering memory accesses against stack pointer restore. */
27837 if (cfun->calls_alloca
27838 || offset_below_red_zone_p (-info->total_size))
27839 rs6000_emit_stack_tie (frame_reg_rtx, false);
27840 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
27841 GEN_INT (info->total_size)));
27844 if (insn && frame_reg_rtx == sp_reg_rtx)
27848 REG_NOTES (insn) = cfa_restores;
27849 cfa_restores = NULL_RTX;
27851 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27852 RTX_FRAME_RELATED_P (insn) = 1;
27855 /* Restore AltiVec registers if we have not done so already. */
27856 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27857 && info->altivec_size != 0
27858 && (DEFAULT_ABI == ABI_V4
27859 || !offset_below_red_zone_p (info->altivec_save_offset)))
27863 if ((strategy & REST_INLINE_VRS) == 0)
27865 int end_save = info->altivec_save_offset + info->altivec_size;
27867 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27868 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27869 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27871 if (end_save + frame_off != 0)
27873 rtx offset = GEN_INT (end_save + frame_off);
27875 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27878 emit_move_insn (ptr_reg, frame_reg_rtx);
27880 ptr_off = -end_save;
27881 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27882 info->altivec_save_offset + ptr_off,
27883 0, V4SImode, SAVRES_VR);
27884 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27886 /* Frame reg was clobbered by out-of-line save. Restore it
27887 from ptr_reg, and if we are calling out-of-line gpr or
27888 fpr restore set up the correct pointer and offset. */
27889 unsigned newptr_regno = 1;
27890 if (!restoring_GPRs_inline)
27892 bool lr = info->gp_save_offset + info->gp_size == 0;
27893 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
27894 newptr_regno = ptr_regno_for_savres (sel);
27895 end_save = info->gp_save_offset + info->gp_size;
27897 else if (!restoring_FPRs_inline)
27899 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
27900 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27901 newptr_regno = ptr_regno_for_savres (sel);
27902 end_save = info->fp_save_offset + info->fp_size;
27905 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
27906 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
27908 if (end_save + ptr_off != 0)
27910 rtx offset = GEN_INT (end_save + ptr_off);
27912 frame_off = -end_save;
27914 emit_insn (gen_addsi3_carry (frame_reg_rtx,
27917 emit_insn (gen_adddi3_carry (frame_reg_rtx,
27922 frame_off = ptr_off;
27923 emit_move_insn (frame_reg_rtx, ptr_reg);
27929 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27930 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27932 rtx addr, areg, mem, insn;
27933 rtx reg = gen_rtx_REG (V4SImode, i);
27934 HOST_WIDE_INT offset
27935 = (info->altivec_save_offset + frame_off
27936 + 16 * (i - info->first_altivec_reg_save));
27938 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27940 mem = gen_frame_mem (V4SImode,
27941 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27942 GEN_INT (offset)));
27943 insn = gen_rtx_SET (reg, mem);
27947 areg = gen_rtx_REG (Pmode, 0);
27948 emit_move_insn (areg, GEN_INT (offset));
27950 /* AltiVec addressing mode is [reg+reg]. */
27951 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
27952 mem = gen_frame_mem (V4SImode, addr);
27954 /* Rather than emitting a generic move, force use of the
27955 lvx instruction, which we always want. In particular we
27956 don't want lxvd2x/xxpermdi for little endian. */
27957 insn = gen_altivec_lvx_v4si_internal (reg, mem);
27960 (void) emit_insn (insn);
27964 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27965 if (((strategy & REST_INLINE_VRS) == 0
27966 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
27967 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
27970 rtx reg = gen_rtx_REG (V4SImode, i);
27971 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27975 /* Restore VRSAVE if we have not done so already. */
27976 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27977 && info->vrsave_size != 0
27978 && (DEFAULT_ABI == ABI_V4
27979 || !offset_below_red_zone_p (info->vrsave_save_offset)))
27983 reg = gen_rtx_REG (SImode, 12);
27984 emit_insn (gen_frame_load (reg, frame_reg_rtx,
27985 info->vrsave_save_offset + frame_off));
27987 emit_insn (generate_set_vrsave (reg, info, 1));
27990 /* If we exit by an out-of-line restore function on ABI_V4 then that
27991 function will deallocate the stack, so we don't need to worry
27992 about the unwinder restoring cr from an invalid stack frame
27994 exit_func = (!restoring_FPRs_inline
27995 || (!restoring_GPRs_inline
27996 && info->first_fp_reg_save == 64));
27998 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
27999 *separate* slots if the routine calls __builtin_eh_return, so
28000 that they can be independently restored by the unwinder. */
28001 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28003 int i, cr_off = info->ehcr_offset;
28005 for (i = 0; i < 8; i++)
28006 if (!call_used_regs[CR0_REGNO + i])
28008 rtx reg = gen_rtx_REG (SImode, 0);
28009 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28010 cr_off + frame_off));
28012 insn = emit_insn (gen_movsi_to_cr_one
28013 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28015 if (!exit_func && flag_shrink_wrap)
28017 add_reg_note (insn, REG_CFA_RESTORE,
28018 gen_rtx_REG (SImode, CR0_REGNO + i));
28020 RTX_FRAME_RELATED_P (insn) = 1;
28023 cr_off += reg_size;
28027 /* Get the old lr if we saved it. If we are restoring registers
28028 out-of-line, then the out-of-line routines can do this for us. */
28029 if (restore_lr && restoring_GPRs_inline)
28030 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28032 /* Get the old cr if we saved it. */
28033 if (info->cr_save_p)
28035 unsigned cr_save_regno = 12;
28037 if (!restoring_GPRs_inline)
28039 /* Ensure we don't use the register used by the out-of-line
28040 gpr register restore below. */
28041 bool lr = info->gp_save_offset + info->gp_size == 0;
28042 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28043 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28045 if (gpr_ptr_regno == 12)
28046 cr_save_regno = 11;
28047 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28049 else if (REGNO (frame_reg_rtx) == 12)
28050 cr_save_regno = 11;
28052 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28053 info->cr_save_offset + frame_off,
28057 /* Set LR here to try to overlap restores below. */
28058 if (restore_lr && restoring_GPRs_inline)
28059 restore_saved_lr (0, exit_func);
28061 /* Load exception handler data registers, if needed. */
28062 if (crtl->calls_eh_return)
28064 unsigned int i, regno;
28068 rtx reg = gen_rtx_REG (reg_mode, 2);
28069 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28070 frame_off + RS6000_TOC_SAVE_SLOT));
28077 regno = EH_RETURN_DATA_REGNO (i);
28078 if (regno == INVALID_REGNUM)
28081 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28082 info->ehrd_offset + frame_off
28083 + reg_size * (int) i);
28085 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28089 /* Restore GPRs. This is done as a PARALLEL if we are using
28090 the load-multiple instructions. */
28091 if (!restoring_GPRs_inline)
28093 /* We are jumping to an out-of-line function. */
28095 int end_save = info->gp_save_offset + info->gp_size;
28096 bool can_use_exit = end_save == 0;
28097 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28100 /* Emit stack reset code if we need it. */
28101 ptr_regno = ptr_regno_for_savres (sel);
28102 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28104 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28105 else if (end_save + frame_off != 0)
28106 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28107 GEN_INT (end_save + frame_off)));
28108 else if (REGNO (frame_reg_rtx) != ptr_regno)
28109 emit_move_insn (ptr_reg, frame_reg_rtx);
28110 if (REGNO (frame_reg_rtx) == ptr_regno)
28111 frame_off = -end_save;
28113 if (can_use_exit && info->cr_save_p)
28114 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28116 ptr_off = -end_save;
28117 rs6000_emit_savres_rtx (info, ptr_reg,
28118 info->gp_save_offset + ptr_off,
28119 info->lr_save_offset + ptr_off,
28122 else if (using_load_multiple)
28125 p = rtvec_alloc (32 - info->first_gp_reg_save);
28126 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28128 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28130 info->gp_save_offset + frame_off + reg_size * i);
28131 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28135 int offset = info->gp_save_offset + frame_off;
28136 for (i = info->first_gp_reg_save; i < 32; i++)
28139 && !cfun->machine->gpr_is_wrapped_separately[i])
28141 rtx reg = gen_rtx_REG (reg_mode, i);
28142 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28145 offset += reg_size;
28149 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28151 /* If the frame pointer was used then we can't delay emitting
28152 a REG_CFA_DEF_CFA note. This must happen on the insn that
28153 restores the frame pointer, r31. We may have already emitted
28154 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28155 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28156 be harmless if emitted. */
28157 if (frame_pointer_needed)
28159 insn = get_last_insn ();
28160 add_reg_note (insn, REG_CFA_DEF_CFA,
28161 plus_constant (Pmode, frame_reg_rtx, frame_off));
28162 RTX_FRAME_RELATED_P (insn) = 1;
28165 /* Set up cfa_restores. We always need these when
28166 shrink-wrapping. If not shrink-wrapping then we only need
28167 the cfa_restore when the stack location is no longer valid.
28168 The cfa_restores must be emitted on or before the insn that
28169 invalidates the stack, and of course must not be emitted
28170 before the insn that actually does the restore. The latter
28171 is why it is a bad idea to emit the cfa_restores as a group
28172 on the last instruction here that actually does a restore:
28173 That insn may be reordered with respect to others doing
28175 if (flag_shrink_wrap
28176 && !restoring_GPRs_inline
28177 && info->first_fp_reg_save == 64)
28178 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28180 for (i = info->first_gp_reg_save; i < 32; i++)
28182 && !cfun->machine->gpr_is_wrapped_separately[i])
28184 rtx reg = gen_rtx_REG (reg_mode, i);
28185 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28189 if (!restoring_GPRs_inline
28190 && info->first_fp_reg_save == 64)
28192 /* We are jumping to an out-of-line function. */
28194 emit_cfa_restores (cfa_restores);
28198 if (restore_lr && !restoring_GPRs_inline)
28200 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28201 restore_saved_lr (0, exit_func);
28204 /* Restore fpr's if we need to do it without calling a function. */
28205 if (restoring_FPRs_inline)
28207 int offset = info->fp_save_offset + frame_off;
28208 for (i = info->first_fp_reg_save; i < 64; i++)
28211 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28213 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28214 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28215 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28216 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28220 offset += fp_reg_size;
28224 /* If we saved cr, restore it here. Just those that were used. */
28225 if (info->cr_save_p)
28226 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28228 /* If this is V.4, unwind the stack pointer after all of the loads
28229 have been done, or set up r11 if we are restoring fp out of line. */
28231 if (!restoring_FPRs_inline)
28233 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28234 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28235 ptr_regno = ptr_regno_for_savres (sel);
28238 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28239 if (REGNO (frame_reg_rtx) == ptr_regno)
28242 if (insn && restoring_FPRs_inline)
28246 REG_NOTES (insn) = cfa_restores;
28247 cfa_restores = NULL_RTX;
28249 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28250 RTX_FRAME_RELATED_P (insn) = 1;
28253 if (crtl->calls_eh_return)
28255 rtx sa = EH_RETURN_STACKADJ_RTX;
28256 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28259 if (!sibcall && restoring_FPRs_inline)
28263 /* We can't hang the cfa_restores off a simple return,
28264 since the shrink-wrap code sometimes uses an existing
28265 return. This means there might be a path from
28266 pre-prologue code to this return, and dwarf2cfi code
28267 wants the eh_frame unwinder state to be the same on
28268 all paths to any point. So we need to emit the
28269 cfa_restores before the return. For -m64 we really
28270 don't need epilogue cfa_restores at all, except for
28271 this irritating dwarf2cfi with shrink-wrap
28272 requirement; The stack red-zone means eh_frame info
28273 from the prologue telling the unwinder to restore
28274 from the stack is perfectly good right to the end of
28276 emit_insn (gen_blockage ());
28277 emit_cfa_restores (cfa_restores);
28278 cfa_restores = NULL_RTX;
28281 emit_jump_insn (targetm.gen_simple_return ());
28284 if (!sibcall && !restoring_FPRs_inline)
28286 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28287 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28289 RTVEC_ELT (p, elt++) = ret_rtx;
28291 RTVEC_ELT (p, elt++)
28292 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
28294 /* We have to restore more than two FP registers, so branch to the
28295 restore function. It will return to our caller. */
28300 if (flag_shrink_wrap)
28301 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28303 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28304 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28305 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28306 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28308 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28310 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28312 RTVEC_ELT (p, elt++)
28313 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28314 if (flag_shrink_wrap
28315 && save_reg_p (info->first_fp_reg_save + i))
28316 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28319 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28325 /* Ensure the cfa_restores are hung off an insn that won't
28326 be reordered above other restores. */
28327 emit_insn (gen_blockage ());
28329 emit_cfa_restores (cfa_restores);
28333 /* Write function epilogue. */
28336 rs6000_output_function_epilogue (FILE *file)
28339 macho_branch_islands ();
28342 rtx_insn *insn = get_last_insn ();
28343 rtx_insn *deleted_debug_label = NULL;
28345 /* Mach-O doesn't support labels at the end of objects, so if
28346 it looks like we might want one, take special action.
28348 First, collect any sequence of deleted debug labels. */
28351 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28353 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28354 notes only, instead set their CODE_LABEL_NUMBER to -1,
28355 otherwise there would be code generation differences
28356 in between -g and -g0. */
28357 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28358 deleted_debug_label = insn;
28359 insn = PREV_INSN (insn);
28362 /* Second, if we have:
28365 then this needs to be detected, so skip past the barrier. */
28367 if (insn && BARRIER_P (insn))
28368 insn = PREV_INSN (insn);
28370 /* Up to now we've only seen notes or barriers. */
28375 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28376 /* Trailing label: <barrier>. */
28377 fputs ("\tnop\n", file);
28380 /* Lastly, see if we have a completely empty function body. */
28381 while (insn && ! INSN_P (insn))
28382 insn = PREV_INSN (insn);
28383 /* If we don't find any insns, we've got an empty function body;
28384 I.e. completely empty - without a return or branch. This is
28385 taken as the case where a function body has been removed
28386 because it contains an inline __builtin_unreachable(). GCC
28387 states that reaching __builtin_unreachable() means UB so we're
28388 not obliged to do anything special; however, we want
28389 non-zero-sized function bodies. To meet this, and help the
28390 user out, let's trap the case. */
28392 fputs ("\ttrap\n", file);
28395 else if (deleted_debug_label)
28396 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28397 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28398 CODE_LABEL_NUMBER (insn) = -1;
28402 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28405 We don't output a traceback table if -finhibit-size-directive was
28406 used. The documentation for -finhibit-size-directive reads
28407 ``don't output a @code{.size} assembler directive, or anything
28408 else that would cause trouble if the function is split in the
28409 middle, and the two halves are placed at locations far apart in
28410 memory.'' The traceback table has this property, since it
28411 includes the offset from the start of the function to the
28412 traceback table itself.
28414 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28415 different traceback table. */
28416 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28417 && ! flag_inhibit_size_directive
28418 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28420 const char *fname = NULL;
28421 const char *language_string = lang_hooks.name;
28422 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28424 int optional_tbtab;
28425 rs6000_stack_t *info = rs6000_stack_info ();
28427 if (rs6000_traceback == traceback_full)
28428 optional_tbtab = 1;
28429 else if (rs6000_traceback == traceback_part)
28430 optional_tbtab = 0;
28432 optional_tbtab = !optimize_size && !TARGET_ELF;
28434 if (optional_tbtab)
28436 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28437 while (*fname == '.') /* V.4 encodes . in the name */
28440 /* Need label immediately before tbtab, so we can compute
28441 its offset from the function start. */
28442 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28443 ASM_OUTPUT_LABEL (file, fname);
28446 /* The .tbtab pseudo-op can only be used for the first eight
28447 expressions, since it can't handle the possibly variable
28448 length fields that follow. However, if you omit the optional
28449 fields, the assembler outputs zeros for all optional fields
28450 anyways, giving each variable length field is minimum length
28451 (as defined in sys/debug.h). Thus we can not use the .tbtab
28452 pseudo-op at all. */
28454 /* An all-zero word flags the start of the tbtab, for debuggers
28455 that have to find it by searching forward from the entry
28456 point or from the current pc. */
28457 fputs ("\t.long 0\n", file);
28459 /* Tbtab format type. Use format type 0. */
28460 fputs ("\t.byte 0,", file);
28462 /* Language type. Unfortunately, there does not seem to be any
28463 official way to discover the language being compiled, so we
28464 use language_string.
28465 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
28466 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28467 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
28468 either, so for now use 0. */
28470 || ! strcmp (language_string, "GNU GIMPLE")
28471 || ! strcmp (language_string, "GNU Go")
28472 || ! strcmp (language_string, "libgccjit"))
28474 else if (! strcmp (language_string, "GNU F77")
28475 || lang_GNU_Fortran ())
28477 else if (! strcmp (language_string, "GNU Pascal"))
28479 else if (! strcmp (language_string, "GNU Ada"))
28481 else if (lang_GNU_CXX ()
28482 || ! strcmp (language_string, "GNU Objective-C++"))
28484 else if (! strcmp (language_string, "GNU Java"))
28486 else if (! strcmp (language_string, "GNU Objective-C"))
28489 gcc_unreachable ();
28490 fprintf (file, "%d,", i);
28492 /* 8 single bit fields: global linkage (not set for C extern linkage,
28493 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28494 from start of procedure stored in tbtab, internal function, function
28495 has controlled storage, function has no toc, function uses fp,
28496 function logs/aborts fp operations. */
28497 /* Assume that fp operations are used if any fp reg must be saved. */
28498 fprintf (file, "%d,",
28499 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28501 /* 6 bitfields: function is interrupt handler, name present in
28502 proc table, function calls alloca, on condition directives
28503 (controls stack walks, 3 bits), saves condition reg, saves
28505 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28506 set up as a frame pointer, even when there is no alloca call. */
28507 fprintf (file, "%d,",
28508 ((optional_tbtab << 6)
28509 | ((optional_tbtab & frame_pointer_needed) << 5)
28510 | (info->cr_save_p << 1)
28511 | (info->lr_save_p)));
28513 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28515 fprintf (file, "%d,",
28516 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28518 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28519 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28521 if (optional_tbtab)
28523 /* Compute the parameter info from the function decl argument
28526 int next_parm_info_bit = 31;
28528 for (decl = DECL_ARGUMENTS (current_function_decl);
28529 decl; decl = DECL_CHAIN (decl))
28531 rtx parameter = DECL_INCOMING_RTL (decl);
28532 machine_mode mode = GET_MODE (parameter);
28534 if (GET_CODE (parameter) == REG)
28536 if (SCALAR_FLOAT_MODE_P (mode))
28559 gcc_unreachable ();
28562 /* If only one bit will fit, don't or in this entry. */
28563 if (next_parm_info_bit > 0)
28564 parm_info |= (bits << (next_parm_info_bit - 1));
28565 next_parm_info_bit -= 2;
28569 fixed_parms += ((GET_MODE_SIZE (mode)
28570 + (UNITS_PER_WORD - 1))
28572 next_parm_info_bit -= 1;
28578 /* Number of fixed point parameters. */
28579 /* This is actually the number of words of fixed point parameters; thus
28580 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28581 fprintf (file, "%d,", fixed_parms);
28583 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28585 /* This is actually the number of fp registers that hold parameters;
28586 and thus the maximum value is 13. */
28587 /* Set parameters on stack bit if parameters are not in their original
28588 registers, regardless of whether they are on the stack? Xlc
28589 seems to set the bit when not optimizing. */
28590 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28592 if (optional_tbtab)
28594 /* Optional fields follow. Some are variable length. */
28596 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28597 float, 11 double float. */
28598 /* There is an entry for each parameter in a register, in the order
28599 that they occur in the parameter list. Any intervening arguments
28600 on the stack are ignored. If the list overflows a long (max
28601 possible length 34 bits) then completely leave off all elements
28603 /* Only emit this long if there was at least one parameter. */
28604 if (fixed_parms || float_parms)
28605 fprintf (file, "\t.long %d\n", parm_info);
28607 /* Offset from start of code to tb table. */
28608 fputs ("\t.long ", file);
28609 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28610 RS6000_OUTPUT_BASENAME (file, fname);
28612 rs6000_output_function_entry (file, fname);
28615 /* Interrupt handler mask. */
28616 /* Omit this long, since we never set the interrupt handler bit
28619 /* Number of CTL (controlled storage) anchors. */
28620 /* Omit this long, since the has_ctl bit is never set above. */
28622 /* Displacement into stack of each CTL anchor. */
28623 /* Omit this list of longs, because there are no CTL anchors. */
28625 /* Length of function name. */
28628 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28630 /* Function name. */
28631 assemble_string (fname, strlen (fname));
28633 /* Register for alloca automatic storage; this is always reg 31.
28634 Only emit this if the alloca bit was set above. */
28635 if (frame_pointer_needed)
28636 fputs ("\t.byte 31\n", file);
28638 fputs ("\t.align 2\n", file);
28642 /* Arrange to define .LCTOC1 label, if not already done. */
28646 if (!toc_initialized)
28648 switch_to_section (toc_section);
28649 switch_to_section (current_function_section ());
28654 /* -fsplit-stack support. */
28656 /* A SYMBOL_REF for __morestack. */
28657 static GTY(()) rtx morestack_ref;
28660 gen_add3_const (rtx rt, rtx ra, long c)
28663 return gen_adddi3 (rt, ra, GEN_INT (c));
28665 return gen_addsi3 (rt, ra, GEN_INT (c));
28668 /* Emit -fsplit-stack prologue, which goes before the regular function
28669 prologue (at local entry point in the case of ELFv2). */
28672 rs6000_expand_split_stack_prologue (void)
28674 rs6000_stack_t *info = rs6000_stack_info ();
28675 unsigned HOST_WIDE_INT allocate;
28676 long alloc_hi, alloc_lo;
28677 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28680 gcc_assert (flag_split_stack && reload_completed);
28685 if (global_regs[29])
28687 error ("%qs uses register r29", "-fsplit-stack");
28688 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
28689 "conflicts with %qD", global_regs_decl[29]);
28692 allocate = info->total_size;
28693 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
28695 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
28698 if (morestack_ref == NULL_RTX)
28700 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
28701 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
28702 | SYMBOL_FLAG_FUNCTION);
28705 r0 = gen_rtx_REG (Pmode, 0);
28706 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28707 r12 = gen_rtx_REG (Pmode, 12);
28708 emit_insn (gen_load_split_stack_limit (r0));
28709 /* Always emit two insns here to calculate the requested stack,
28710 so that the linker can edit them when adjusting size for calling
28711 non-split-stack code. */
28712 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
28713 alloc_lo = -allocate - alloc_hi;
28716 emit_insn (gen_add3_const (r12, r1, alloc_hi));
28718 emit_insn (gen_add3_const (r12, r12, alloc_lo));
28720 emit_insn (gen_nop ());
28724 emit_insn (gen_add3_const (r12, r1, alloc_lo));
28725 emit_insn (gen_nop ());
28728 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
28729 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
28730 ok_label = gen_label_rtx ();
28731 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28732 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
28733 gen_rtx_LABEL_REF (VOIDmode, ok_label),
28735 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28736 JUMP_LABEL (insn) = ok_label;
28737 /* Mark the jump as very likely to be taken. */
28738 add_reg_br_prob_note (insn, profile_probability::very_likely ());
28740 lr = gen_rtx_REG (Pmode, LR_REGNO);
28741 insn = emit_move_insn (r0, lr);
28742 RTX_FRAME_RELATED_P (insn) = 1;
28743 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
28744 RTX_FRAME_RELATED_P (insn) = 1;
28746 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
28747 const0_rtx, const0_rtx));
28748 call_fusage = NULL_RTX;
28749 use_reg (&call_fusage, r12);
28750 /* Say the call uses r0, even though it doesn't, to stop regrename
28751 from twiddling with the insns saving lr, trashing args for cfun.
28752 The insns restoring lr are similarly protected by making
28753 split_stack_return use r0. */
28754 use_reg (&call_fusage, r0);
28755 add_function_usage_to (insn, call_fusage);
28756 /* Indicate that this function can't jump to non-local gotos. */
28757 make_reg_eh_region_note_nothrow_nononlocal (insn);
28758 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
28759 insn = emit_move_insn (lr, r0);
28760 add_reg_note (insn, REG_CFA_RESTORE, lr);
28761 RTX_FRAME_RELATED_P (insn) = 1;
28762 emit_insn (gen_split_stack_return ());
28764 emit_label (ok_label);
28765 LABEL_NUSES (ok_label) = 1;
28768 /* Return the internal arg pointer used for function incoming
28769 arguments. When -fsplit-stack, the arg pointer is r12 so we need
28770 to copy it to a pseudo in order for it to be preserved over calls
28771 and suchlike. We'd really like to use a pseudo here for the
28772 internal arg pointer but data-flow analysis is not prepared to
28773 accept pseudos as live at the beginning of a function. */
28776 rs6000_internal_arg_pointer (void)
28778 if (flag_split_stack
28779 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
28783 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
28787 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
28788 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
28790 /* Put the pseudo initialization right after the note at the
28791 beginning of the function. */
28792 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
28793 gen_rtx_REG (Pmode, 12));
28794 push_topmost_sequence ();
28795 emit_insn_after (pat, get_insns ());
28796 pop_topmost_sequence ();
28798 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
28799 FIRST_PARM_OFFSET (current_function_decl));
28800 return copy_to_reg (ret);
28802 return virtual_incoming_args_rtx;
28805 /* We may have to tell the dataflow pass that the split stack prologue
28806 is initializing a register. */
28809 rs6000_live_on_entry (bitmap regs)
28811 if (flag_split_stack)
28812 bitmap_set_bit (regs, 12);
28815 /* Emit -fsplit-stack dynamic stack allocation space check. */
28818 rs6000_split_stack_space_check (rtx size, rtx label)
28820 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28821 rtx limit = gen_reg_rtx (Pmode);
28822 rtx requested = gen_reg_rtx (Pmode);
28823 rtx cmp = gen_reg_rtx (CCUNSmode);
28826 emit_insn (gen_load_split_stack_limit (limit));
28827 if (CONST_INT_P (size))
28828 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
28831 size = force_reg (Pmode, size);
28832 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
28834 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
28835 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28836 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
28837 gen_rtx_LABEL_REF (VOIDmode, label),
28839 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28840 JUMP_LABEL (jump) = label;
28843 /* A C compound statement that outputs the assembler code for a thunk
28844 function, used to implement C++ virtual function calls with
28845 multiple inheritance. The thunk acts as a wrapper around a virtual
28846 function, adjusting the implicit object parameter before handing
28847 control off to the real function.
28849 First, emit code to add the integer DELTA to the location that
28850 contains the incoming first argument. Assume that this argument
28851 contains a pointer, and is the one used to pass the `this' pointer
28852 in C++. This is the incoming argument *before* the function
28853 prologue, e.g. `%o0' on a sparc. The addition must preserve the
28854 values of all other incoming arguments.
28856 After the addition, emit code to jump to FUNCTION, which is a
28857 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
28858 not touch the return address. Hence returning from FUNCTION will
28859 return to whoever called the current `thunk'.
28861 The effect must be as if FUNCTION had been called directly with the
28862 adjusted first argument. This macro is responsible for emitting
28863 all of the code for a thunk function; output_function_prologue()
28864 and output_function_epilogue() are not invoked.
28866 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
28867 been extracted from it.) It might possibly be useful on some
28868 targets, but probably not.
28870 If you do not define this macro, the target-independent code in the
28871 C++ frontend will generate a less efficient heavyweight thunk that
28872 calls FUNCTION instead of jumping to it. The generic approach does
28873 not support varargs. */
28876 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
28877 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
28880 rtx this_rtx, funexp;
28883 reload_completed = 1;
28884 epilogue_completed = 1;
28886 /* Mark the end of the (empty) prologue. */
28887 emit_note (NOTE_INSN_PROLOGUE_END);
28889 /* Find the "this" pointer. If the function returns a structure,
28890 the structure return pointer is in r3. */
28891 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
28892 this_rtx = gen_rtx_REG (Pmode, 4);
28894 this_rtx = gen_rtx_REG (Pmode, 3);
28896 /* Apply the constant offset, if required. */
28898 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
28900 /* Apply the offset from the vtable, if required. */
28903 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
28904 rtx tmp = gen_rtx_REG (Pmode, 12);
28906 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
28907 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
28909 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
28910 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
28914 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
28916 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
28918 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
28921 /* Generate a tail call to the target function. */
28922 if (!TREE_USED (function))
28924 assemble_external (function);
28925 TREE_USED (function) = 1;
28927 funexp = XEXP (DECL_RTL (function), 0);
28928 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
28931 if (MACHOPIC_INDIRECT)
28932 funexp = machopic_indirect_call_target (funexp);
28935 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
28936 generate sibcall RTL explicitly. */
28937 insn = emit_call_insn (
28938 gen_rtx_PARALLEL (VOIDmode,
28940 gen_rtx_CALL (VOIDmode,
28941 funexp, const0_rtx),
28942 gen_rtx_USE (VOIDmode, const0_rtx),
28943 simple_return_rtx)));
28944 SIBLING_CALL_P (insn) = 1;
28947 /* Run just enough of rest_of_compilation to get the insns emitted.
28948 There's not really enough bulk here to make other passes such as
28949 instruction scheduling worth while. Note that use_thunk calls
28950 assemble_start_function and assemble_end_function. */
28951 insn = get_insns ();
28952 shorten_branches (insn);
28953 final_start_function (insn, file, 1);
28954 final (insn, file, 1);
28955 final_end_function ();
28957 reload_completed = 0;
28958 epilogue_completed = 0;
28961 /* A quick summary of the various types of 'constant-pool tables'
28964 Target Flags Name One table per
28965 AIX (none) AIX TOC object file
28966 AIX -mfull-toc AIX TOC object file
28967 AIX -mminimal-toc AIX minimal TOC translation unit
28968 SVR4/EABI (none) SVR4 SDATA object file
28969 SVR4/EABI -fpic SVR4 pic object file
28970 SVR4/EABI -fPIC SVR4 PIC translation unit
28971 SVR4/EABI -mrelocatable EABI TOC function
28972 SVR4/EABI -maix AIX TOC object file
28973 SVR4/EABI -maix -mminimal-toc
28974 AIX minimal TOC translation unit
28976 Name Reg. Set by entries contains:
28977 made by addrs? fp? sum?
28979 AIX TOC 2 crt0 as Y option option
28980 AIX minimal TOC 30 prolog gcc Y Y option
28981 SVR4 SDATA 13 crt0 gcc N Y N
28982 SVR4 pic 30 prolog ld Y not yet N
28983 SVR4 PIC 30 prolog gcc Y option option
28984 EABI TOC 30 prolog gcc Y option option
28988 /* Hash functions for the hash table. */
28991 rs6000_hash_constant (rtx k)
28993 enum rtx_code code = GET_CODE (k);
28994 machine_mode mode = GET_MODE (k);
28995 unsigned result = (code << 3) ^ mode;
28996 const char *format;
28999 format = GET_RTX_FORMAT (code);
29000 flen = strlen (format);
29006 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29008 case CONST_WIDE_INT:
29011 flen = CONST_WIDE_INT_NUNITS (k);
29012 for (i = 0; i < flen; i++)
29013 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29018 if (mode != VOIDmode)
29019 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29031 for (; fidx < flen; fidx++)
29032 switch (format[fidx])
29037 const char *str = XSTR (k, fidx);
29038 len = strlen (str);
29039 result = result * 613 + len;
29040 for (i = 0; i < len; i++)
29041 result = result * 613 + (unsigned) str[i];
29046 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29050 result = result * 613 + (unsigned) XINT (k, fidx);
29053 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29054 result = result * 613 + (unsigned) XWINT (k, fidx);
29058 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29059 result = result * 613 + (unsigned) (XWINT (k, fidx)
29066 gcc_unreachable ();
29073 toc_hasher::hash (toc_hash_struct *thc)
29075 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29078 /* Compare H1 and H2 for equivalence. */
29081 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29086 if (h1->key_mode != h2->key_mode)
29089 return rtx_equal_p (r1, r2);
29092 /* These are the names given by the C++ front-end to vtables, and
29093 vtable-like objects. Ideally, this logic should not be here;
29094 instead, there should be some programmatic way of inquiring as
29095 to whether or not an object is a vtable. */
29097 #define VTABLE_NAME_P(NAME) \
29098 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29099 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29100 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29101 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29102 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29104 #ifdef NO_DOLLAR_IN_LABEL
29105 /* Return a GGC-allocated character string translating dollar signs in
29106 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29109 rs6000_xcoff_strip_dollar (const char *name)
29115 q = (const char *) strchr (name, '$');
29117 if (q == 0 || q == name)
29120 len = strlen (name);
29121 strip = XALLOCAVEC (char, len + 1);
29122 strcpy (strip, name);
29123 p = strip + (q - name);
29127 p = strchr (p + 1, '$');
29130 return ggc_alloc_string (strip, len);
29135 rs6000_output_symbol_ref (FILE *file, rtx x)
29137 const char *name = XSTR (x, 0);
29139 /* Currently C++ toc references to vtables can be emitted before it
29140 is decided whether the vtable is public or private. If this is
29141 the case, then the linker will eventually complain that there is
29142 a reference to an unknown section. Thus, for vtables only,
29143 we emit the TOC reference to reference the identifier and not the
29145 if (VTABLE_NAME_P (name))
29147 RS6000_OUTPUT_BASENAME (file, name);
29150 assemble_name (file, name);
29153 /* Output a TOC entry. We derive the entry name from what is being
29157 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29160 const char *name = buf;
29162 HOST_WIDE_INT offset = 0;
29164 gcc_assert (!TARGET_NO_TOC);
29166 /* When the linker won't eliminate them, don't output duplicate
29167 TOC entries (this happens on AIX if there is any kind of TOC,
29168 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29170 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29172 struct toc_hash_struct *h;
29174 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29175 time because GGC is not initialized at that point. */
29176 if (toc_hash_table == NULL)
29177 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29179 h = ggc_alloc<toc_hash_struct> ();
29181 h->key_mode = mode;
29182 h->labelno = labelno;
29184 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29185 if (*found == NULL)
29187 else /* This is indeed a duplicate.
29188 Set this label equal to that label. */
29190 fputs ("\t.set ", file);
29191 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29192 fprintf (file, "%d,", labelno);
29193 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29194 fprintf (file, "%d\n", ((*found)->labelno));
29197 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
29198 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29199 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29201 fputs ("\t.set ", file);
29202 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29203 fprintf (file, "%d,", labelno);
29204 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29205 fprintf (file, "%d\n", ((*found)->labelno));
29212 /* If we're going to put a double constant in the TOC, make sure it's
29213 aligned properly when strict alignment is on. */
29214 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29215 && STRICT_ALIGNMENT
29216 && GET_MODE_BITSIZE (mode) >= 64
29217 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29218 ASM_OUTPUT_ALIGN (file, 3);
29221 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29223 /* Handle FP constants specially. Note that if we have a minimal
29224 TOC, things we put here aren't actually in the TOC, so we can allow
29226 if (GET_CODE (x) == CONST_DOUBLE &&
29227 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29228 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29232 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29233 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29235 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29239 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29240 fputs (DOUBLE_INT_ASM_OP, file);
29242 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29243 k[0] & 0xffffffff, k[1] & 0xffffffff,
29244 k[2] & 0xffffffff, k[3] & 0xffffffff);
29245 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29246 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29247 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29248 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29249 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29254 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29255 fputs ("\t.long ", file);
29257 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29258 k[0] & 0xffffffff, k[1] & 0xffffffff,
29259 k[2] & 0xffffffff, k[3] & 0xffffffff);
29260 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29261 k[0] & 0xffffffff, k[1] & 0xffffffff,
29262 k[2] & 0xffffffff, k[3] & 0xffffffff);
29266 else if (GET_CODE (x) == CONST_DOUBLE &&
29267 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29271 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29272 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29274 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29278 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29279 fputs (DOUBLE_INT_ASM_OP, file);
29281 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29282 k[0] & 0xffffffff, k[1] & 0xffffffff);
29283 fprintf (file, "0x%lx%08lx\n",
29284 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29285 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29290 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29291 fputs ("\t.long ", file);
29293 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29294 k[0] & 0xffffffff, k[1] & 0xffffffff);
29295 fprintf (file, "0x%lx,0x%lx\n",
29296 k[0] & 0xffffffff, k[1] & 0xffffffff);
29300 else if (GET_CODE (x) == CONST_DOUBLE &&
29301 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29305 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29306 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29308 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29312 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29313 fputs (DOUBLE_INT_ASM_OP, file);
29315 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29316 if (WORDS_BIG_ENDIAN)
29317 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29319 fprintf (file, "0x%lx\n", l & 0xffffffff);
29324 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29325 fputs ("\t.long ", file);
29327 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29328 fprintf (file, "0x%lx\n", l & 0xffffffff);
29332 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
29334 unsigned HOST_WIDE_INT low;
29335 HOST_WIDE_INT high;
29337 low = INTVAL (x) & 0xffffffff;
29338 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29340 /* TOC entries are always Pmode-sized, so when big-endian
29341 smaller integer constants in the TOC need to be padded.
29342 (This is still a win over putting the constants in
29343 a separate constant pool, because then we'd have
29344 to have both a TOC entry _and_ the actual constant.)
29346 For a 32-bit target, CONST_INT values are loaded and shifted
29347 entirely within `low' and can be stored in one TOC entry. */
29349 /* It would be easy to make this work, but it doesn't now. */
29350 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29352 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29355 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29356 high = (HOST_WIDE_INT) low >> 32;
29362 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29363 fputs (DOUBLE_INT_ASM_OP, file);
29365 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29366 (long) high & 0xffffffff, (long) low & 0xffffffff);
29367 fprintf (file, "0x%lx%08lx\n",
29368 (long) high & 0xffffffff, (long) low & 0xffffffff);
29373 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29375 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29376 fputs ("\t.long ", file);
29378 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29379 (long) high & 0xffffffff, (long) low & 0xffffffff);
29380 fprintf (file, "0x%lx,0x%lx\n",
29381 (long) high & 0xffffffff, (long) low & 0xffffffff);
29385 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29386 fputs ("\t.long ", file);
29388 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29389 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29395 if (GET_CODE (x) == CONST)
29397 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29398 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
29400 base = XEXP (XEXP (x, 0), 0);
29401 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29404 switch (GET_CODE (base))
29407 name = XSTR (base, 0);
29411 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29412 CODE_LABEL_NUMBER (XEXP (base, 0)));
29416 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29420 gcc_unreachable ();
29423 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29424 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29427 fputs ("\t.tc ", file);
29428 RS6000_OUTPUT_BASENAME (file, name);
29431 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29433 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29435 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29436 after other TOC symbols, reducing overflow of small TOC access
29437 to [TC] symbols. */
29438 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29439 ? "[TE]," : "[TC],", file);
29442 /* Currently C++ toc references to vtables can be emitted before it
29443 is decided whether the vtable is public or private. If this is
29444 the case, then the linker will eventually complain that there is
29445 a TOC reference to an unknown section. Thus, for vtables only,
29446 we emit the TOC reference to reference the symbol and not the
29448 if (VTABLE_NAME_P (name))
29450 RS6000_OUTPUT_BASENAME (file, name);
29452 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29453 else if (offset > 0)
29454 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29457 output_addr_const (file, x);
29460 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
29462 switch (SYMBOL_REF_TLS_MODEL (base))
29466 case TLS_MODEL_LOCAL_EXEC:
29467 fputs ("@le", file);
29469 case TLS_MODEL_INITIAL_EXEC:
29470 fputs ("@ie", file);
29472 /* Use global-dynamic for local-dynamic. */
29473 case TLS_MODEL_GLOBAL_DYNAMIC:
29474 case TLS_MODEL_LOCAL_DYNAMIC:
29476 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29477 fputs ("\t.tc .", file);
29478 RS6000_OUTPUT_BASENAME (file, name);
29479 fputs ("[TC],", file);
29480 output_addr_const (file, x);
29481 fputs ("@m", file);
29484 gcc_unreachable ();
29492 /* Output an assembler pseudo-op to write an ASCII string of N characters
29493 starting at P to FILE.
29495 On the RS/6000, we have to do this using the .byte operation and
29496 write out special characters outside the quoted string.
29497 Also, the assembler is broken; very long strings are truncated,
29498 so we must artificially break them up early. */
29501 output_ascii (FILE *file, const char *p, int n)
29504 int i, count_string;
29505 const char *for_string = "\t.byte \"";
29506 const char *for_decimal = "\t.byte ";
29507 const char *to_close = NULL;
29510 for (i = 0; i < n; i++)
29513 if (c >= ' ' && c < 0177)
29516 fputs (for_string, file);
29519 /* Write two quotes to get one. */
29527 for_decimal = "\"\n\t.byte ";
29531 if (count_string >= 512)
29533 fputs (to_close, file);
29535 for_string = "\t.byte \"";
29536 for_decimal = "\t.byte ";
29544 fputs (for_decimal, file);
29545 fprintf (file, "%d", c);
29547 for_string = "\n\t.byte \"";
29548 for_decimal = ", ";
29554 /* Now close the string if we have written one. Then end the line. */
29556 fputs (to_close, file);
29559 /* Generate a unique section name for FILENAME for a section type
29560 represented by SECTION_DESC. Output goes into BUF.
29562 SECTION_DESC can be any string, as long as it is different for each
29563 possible section type.
29565 We name the section in the same manner as xlc. The name begins with an
29566 underscore followed by the filename (after stripping any leading directory
29567 names) with the last period replaced by the string SECTION_DESC. If
29568 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29572 rs6000_gen_section_name (char **buf, const char *filename,
29573 const char *section_desc)
29575 const char *q, *after_last_slash, *last_period = 0;
29579 after_last_slash = filename;
29580 for (q = filename; *q; q++)
29583 after_last_slash = q + 1;
29584 else if (*q == '.')
29588 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29589 *buf = (char *) xmalloc (len);
29594 for (q = after_last_slash; *q; q++)
29596 if (q == last_period)
29598 strcpy (p, section_desc);
29599 p += strlen (section_desc);
29603 else if (ISALNUM (*q))
29607 if (last_period == 0)
29608 strcpy (p, section_desc);
29613 /* Emit profile function. */
29616 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29618 /* Non-standard profiling for kernels, which just saves LR then calls
29619 _mcount without worrying about arg saves. The idea is to change
29620 the function prologue as little as possible as it isn't easy to
29621 account for arg save/restore code added just for _mcount. */
29622 if (TARGET_PROFILE_KERNEL)
29625 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29627 #ifndef NO_PROFILE_COUNTERS
29628 # define NO_PROFILE_COUNTERS 0
29630 if (NO_PROFILE_COUNTERS)
29631 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29632 LCT_NORMAL, VOIDmode);
29636 const char *label_name;
29639 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29640 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29641 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29643 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29644 LCT_NORMAL, VOIDmode, fun, Pmode);
29647 else if (DEFAULT_ABI == ABI_DARWIN)
29649 const char *mcount_name = RS6000_MCOUNT;
29650 int caller_addr_regno = LR_REGNO;
29652 /* Be conservative and always set this, at least for now. */
29653 crtl->uses_pic_offset_table = 1;
29656 /* For PIC code, set up a stub and collect the caller's address
29657 from r0, which is where the prologue puts it. */
29658 if (MACHOPIC_INDIRECT
29659 && crtl->uses_pic_offset_table)
29660 caller_addr_regno = 0;
29662 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29663 LCT_NORMAL, VOIDmode,
29664 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29668 /* Write function profiler code. */
29671 output_function_profiler (FILE *file, int labelno)
29675 switch (DEFAULT_ABI)
29678 gcc_unreachable ();
29683 warning (0, "no profiling of 64-bit code for this ABI");
29686 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29687 fprintf (file, "\tmflr %s\n", reg_names[0]);
29688 if (NO_PROFILE_COUNTERS)
29690 asm_fprintf (file, "\tstw %s,4(%s)\n",
29691 reg_names[0], reg_names[1]);
29693 else if (TARGET_SECURE_PLT && flag_pic)
29695 if (TARGET_LINK_STACK)
29698 get_ppc476_thunk_name (name);
29699 asm_fprintf (file, "\tbl %s\n", name);
29702 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
29703 asm_fprintf (file, "\tstw %s,4(%s)\n",
29704 reg_names[0], reg_names[1]);
29705 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29706 asm_fprintf (file, "\taddis %s,%s,",
29707 reg_names[12], reg_names[12]);
29708 assemble_name (file, buf);
29709 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
29710 assemble_name (file, buf);
29711 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
29713 else if (flag_pic == 1)
29715 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
29716 asm_fprintf (file, "\tstw %s,4(%s)\n",
29717 reg_names[0], reg_names[1]);
29718 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29719 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
29720 assemble_name (file, buf);
29721 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
29723 else if (flag_pic > 1)
29725 asm_fprintf (file, "\tstw %s,4(%s)\n",
29726 reg_names[0], reg_names[1]);
29727 /* Now, we need to get the address of the label. */
29728 if (TARGET_LINK_STACK)
29731 get_ppc476_thunk_name (name);
29732 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
29733 assemble_name (file, buf);
29734 fputs ("-.\n1:", file);
29735 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29736 asm_fprintf (file, "\taddi %s,%s,4\n",
29737 reg_names[11], reg_names[11]);
29741 fputs ("\tbcl 20,31,1f\n\t.long ", file);
29742 assemble_name (file, buf);
29743 fputs ("-.\n1:", file);
29744 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29746 asm_fprintf (file, "\tlwz %s,0(%s)\n",
29747 reg_names[0], reg_names[11]);
29748 asm_fprintf (file, "\tadd %s,%s,%s\n",
29749 reg_names[0], reg_names[0], reg_names[11]);
29753 asm_fprintf (file, "\tlis %s,", reg_names[12]);
29754 assemble_name (file, buf);
29755 fputs ("@ha\n", file);
29756 asm_fprintf (file, "\tstw %s,4(%s)\n",
29757 reg_names[0], reg_names[1]);
29758 asm_fprintf (file, "\tla %s,", reg_names[0]);
29759 assemble_name (file, buf);
29760 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
29763 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
29764 fprintf (file, "\tbl %s%s\n",
29765 RS6000_MCOUNT, flag_pic ? "@plt" : "");
29771 /* Don't do anything, done in output_profile_hook (). */
29778 /* The following variable value is the last issued insn. */
29780 static rtx_insn *last_scheduled_insn;
29782 /* The following variable helps to balance issuing of load and
29783 store instructions */
29785 static int load_store_pendulum;
29787 /* The following variable helps pair divide insns during scheduling. */
29788 static int divide_cnt;
29789 /* The following variable helps pair and alternate vector and vector load
29790 insns during scheduling. */
29791 static int vec_pairing;
29794 /* Power4 load update and store update instructions are cracked into a
29795 load or store and an integer insn which are executed in the same cycle.
29796 Branches have their own dispatch slot which does not count against the
29797 GCC issue rate, but it changes the program flow so there are no other
29798 instructions to issue in this cycle. */
29801 rs6000_variable_issue_1 (rtx_insn *insn, int more)
29803 last_scheduled_insn = insn;
29804 if (GET_CODE (PATTERN (insn)) == USE
29805 || GET_CODE (PATTERN (insn)) == CLOBBER)
29807 cached_can_issue_more = more;
29808 return cached_can_issue_more;
29811 if (insn_terminates_group_p (insn, current_group))
29813 cached_can_issue_more = 0;
29814 return cached_can_issue_more;
29817 /* If no reservation, but reach here */
29818 if (recog_memoized (insn) < 0)
29821 if (rs6000_sched_groups)
29823 if (is_microcoded_insn (insn))
29824 cached_can_issue_more = 0;
29825 else if (is_cracked_insn (insn))
29826 cached_can_issue_more = more > 2 ? more - 2 : 0;
29828 cached_can_issue_more = more - 1;
29830 return cached_can_issue_more;
29833 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
29836 cached_can_issue_more = more - 1;
29837 return cached_can_issue_more;
29841 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
29843 int r = rs6000_variable_issue_1 (insn, more);
29845 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
29849 /* Adjust the cost of a scheduling dependency. Return the new cost of
29850 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
29853 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
29856 enum attr_type attr_type;
29858 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
29865 /* Data dependency; DEP_INSN writes a register that INSN reads
29866 some cycles later. */
29868 /* Separate a load from a narrower, dependent store. */
29869 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
29870 && GET_CODE (PATTERN (insn)) == SET
29871 && GET_CODE (PATTERN (dep_insn)) == SET
29872 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
29873 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
29874 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
29875 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
29878 attr_type = get_attr_type (insn);
29883 /* Tell the first scheduling pass about the latency between
29884 a mtctr and bctr (and mtlr and br/blr). The first
29885 scheduling pass will not know about this latency since
29886 the mtctr instruction, which has the latency associated
29887 to it, will be generated by reload. */
29890 /* Leave some extra cycles between a compare and its
29891 dependent branch, to inhibit expensive mispredicts. */
29892 if ((rs6000_tune == PROCESSOR_PPC603
29893 || rs6000_tune == PROCESSOR_PPC604
29894 || rs6000_tune == PROCESSOR_PPC604e
29895 || rs6000_tune == PROCESSOR_PPC620
29896 || rs6000_tune == PROCESSOR_PPC630
29897 || rs6000_tune == PROCESSOR_PPC750
29898 || rs6000_tune == PROCESSOR_PPC7400
29899 || rs6000_tune == PROCESSOR_PPC7450
29900 || rs6000_tune == PROCESSOR_PPCE5500
29901 || rs6000_tune == PROCESSOR_PPCE6500
29902 || rs6000_tune == PROCESSOR_POWER4
29903 || rs6000_tune == PROCESSOR_POWER5
29904 || rs6000_tune == PROCESSOR_POWER7
29905 || rs6000_tune == PROCESSOR_POWER8
29906 || rs6000_tune == PROCESSOR_POWER9
29907 || rs6000_tune == PROCESSOR_CELL)
29908 && recog_memoized (dep_insn)
29909 && (INSN_CODE (dep_insn) >= 0))
29911 switch (get_attr_type (dep_insn))
29914 case TYPE_FPCOMPARE:
29915 case TYPE_CR_LOGICAL:
29919 if (get_attr_dot (dep_insn) == DOT_YES)
29924 if (get_attr_dot (dep_insn) == DOT_YES
29925 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
29936 if ((rs6000_tune == PROCESSOR_POWER6)
29937 && recog_memoized (dep_insn)
29938 && (INSN_CODE (dep_insn) >= 0))
29941 if (GET_CODE (PATTERN (insn)) != SET)
29942 /* If this happens, we have to extend this to schedule
29943 optimally. Return default for now. */
29946 /* Adjust the cost for the case where the value written
29947 by a fixed point operation is used as the address
29948 gen value on a store. */
29949 switch (get_attr_type (dep_insn))
29954 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29955 return get_attr_sign_extend (dep_insn)
29956 == SIGN_EXTEND_YES ? 6 : 4;
29961 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29962 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
29972 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29980 if (get_attr_update (dep_insn) == UPDATE_YES
29981 && ! rs6000_store_data_bypass_p (dep_insn, insn))
29987 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29993 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29994 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30004 if ((rs6000_tune == PROCESSOR_POWER6)
30005 && recog_memoized (dep_insn)
30006 && (INSN_CODE (dep_insn) >= 0))
30009 /* Adjust the cost for the case where the value written
30010 by a fixed point instruction is used within the address
30011 gen portion of a subsequent load(u)(x) */
30012 switch (get_attr_type (dep_insn))
30017 if (set_to_load_agen (dep_insn, insn))
30018 return get_attr_sign_extend (dep_insn)
30019 == SIGN_EXTEND_YES ? 6 : 4;
30024 if (set_to_load_agen (dep_insn, insn))
30025 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30035 if (set_to_load_agen (dep_insn, insn))
30043 if (get_attr_update (dep_insn) == UPDATE_YES
30044 && set_to_load_agen (dep_insn, insn))
30050 if (set_to_load_agen (dep_insn, insn))
30056 if (set_to_load_agen (dep_insn, insn))
30057 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30067 if ((rs6000_tune == PROCESSOR_POWER6)
30068 && get_attr_update (insn) == UPDATE_NO
30069 && recog_memoized (dep_insn)
30070 && (INSN_CODE (dep_insn) >= 0)
30071 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30078 /* Fall out to return default cost. */
30082 case REG_DEP_OUTPUT:
30083 /* Output dependency; DEP_INSN writes a register that INSN writes some
30085 if ((rs6000_tune == PROCESSOR_POWER6)
30086 && recog_memoized (dep_insn)
30087 && (INSN_CODE (dep_insn) >= 0))
30089 attr_type = get_attr_type (insn);
30094 case TYPE_FPSIMPLE:
30095 if (get_attr_type (dep_insn) == TYPE_FP
30096 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30100 if (get_attr_update (insn) == UPDATE_NO
30101 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30108 /* Fall through, no cost for output dependency. */
30112 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30117 gcc_unreachable ();
30123 /* Debug version of rs6000_adjust_cost. */
30126 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30127 int cost, unsigned int dw)
30129 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30137 default: dep = "unknown depencency"; break;
30138 case REG_DEP_TRUE: dep = "data dependency"; break;
30139 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30140 case REG_DEP_ANTI: dep = "anti depencency"; break;
30144 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30145 "%s, insn:\n", ret, cost, dep);
30153 /* The function returns a true if INSN is microcoded.
30154 Return false otherwise. */
30157 is_microcoded_insn (rtx_insn *insn)
30159 if (!insn || !NONDEBUG_INSN_P (insn)
30160 || GET_CODE (PATTERN (insn)) == USE
30161 || GET_CODE (PATTERN (insn)) == CLOBBER)
30164 if (rs6000_tune == PROCESSOR_CELL)
30165 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30167 if (rs6000_sched_groups
30168 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30170 enum attr_type type = get_attr_type (insn);
30171 if ((type == TYPE_LOAD
30172 && get_attr_update (insn) == UPDATE_YES
30173 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30174 || ((type == TYPE_LOAD || type == TYPE_STORE)
30175 && get_attr_update (insn) == UPDATE_YES
30176 && get_attr_indexed (insn) == INDEXED_YES)
30177 || type == TYPE_MFCR)
30184 /* The function returns true if INSN is cracked into 2 instructions
30185 by the processor (and therefore occupies 2 issue slots). */
30188 is_cracked_insn (rtx_insn *insn)
30190 if (!insn || !NONDEBUG_INSN_P (insn)
30191 || GET_CODE (PATTERN (insn)) == USE
30192 || GET_CODE (PATTERN (insn)) == CLOBBER)
30195 if (rs6000_sched_groups
30196 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30198 enum attr_type type = get_attr_type (insn);
30199 if ((type == TYPE_LOAD
30200 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30201 && get_attr_update (insn) == UPDATE_NO)
30202 || (type == TYPE_LOAD
30203 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30204 && get_attr_update (insn) == UPDATE_YES
30205 && get_attr_indexed (insn) == INDEXED_NO)
30206 || (type == TYPE_STORE
30207 && get_attr_update (insn) == UPDATE_YES
30208 && get_attr_indexed (insn) == INDEXED_NO)
30209 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30210 && get_attr_update (insn) == UPDATE_YES)
30211 || (type == TYPE_CR_LOGICAL
30212 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30213 || (type == TYPE_EXTS
30214 && get_attr_dot (insn) == DOT_YES)
30215 || (type == TYPE_SHIFT
30216 && get_attr_dot (insn) == DOT_YES
30217 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30218 || (type == TYPE_MUL
30219 && get_attr_dot (insn) == DOT_YES)
30220 || type == TYPE_DIV
30221 || (type == TYPE_INSERT
30222 && get_attr_size (insn) == SIZE_32))
30229 /* The function returns true if INSN can be issued only from
30230 the branch slot. */
30233 is_branch_slot_insn (rtx_insn *insn)
30235 if (!insn || !NONDEBUG_INSN_P (insn)
30236 || GET_CODE (PATTERN (insn)) == USE
30237 || GET_CODE (PATTERN (insn)) == CLOBBER)
30240 if (rs6000_sched_groups)
30242 enum attr_type type = get_attr_type (insn);
30243 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30251 /* The function returns true if out_inst sets a value that is
30252 used in the address generation computation of in_insn */
30254 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30256 rtx out_set, in_set;
30258 /* For performance reasons, only handle the simple case where
30259 both loads are a single_set. */
30260 out_set = single_set (out_insn);
30263 in_set = single_set (in_insn);
30265 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30271 /* Try to determine base/offset/size parts of the given MEM.
30272 Return true if successful, false if all the values couldn't
30275 This function only looks for REG or REG+CONST address forms.
30276 REG+REG address form will return false. */
30279 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30280 HOST_WIDE_INT *size)
30283 if MEM_SIZE_KNOWN_P (mem)
30284 *size = MEM_SIZE (mem);
30288 addr_rtx = (XEXP (mem, 0));
30289 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30290 addr_rtx = XEXP (addr_rtx, 1);
30293 while (GET_CODE (addr_rtx) == PLUS
30294 && CONST_INT_P (XEXP (addr_rtx, 1)))
30296 *offset += INTVAL (XEXP (addr_rtx, 1));
30297 addr_rtx = XEXP (addr_rtx, 0);
30299 if (!REG_P (addr_rtx))
30306 /* The function returns true if the target storage location of
30307 mem1 is adjacent to the target storage location of mem2 */
30308 /* Return 1 if memory locations are adjacent. */
30311 adjacent_mem_locations (rtx mem1, rtx mem2)
30314 HOST_WIDE_INT off1, size1, off2, size2;
30316 if (get_memref_parts (mem1, ®1, &off1, &size1)
30317 && get_memref_parts (mem2, ®2, &off2, &size2))
30318 return ((REGNO (reg1) == REGNO (reg2))
30319 && ((off1 + size1 == off2)
30320 || (off2 + size2 == off1)));
30325 /* This function returns true if it can be determined that the two MEM
30326 locations overlap by at least 1 byte based on base reg/offset/size. */
30329 mem_locations_overlap (rtx mem1, rtx mem2)
30332 HOST_WIDE_INT off1, size1, off2, size2;
30334 if (get_memref_parts (mem1, ®1, &off1, &size1)
30335 && get_memref_parts (mem2, ®2, &off2, &size2))
30336 return ((REGNO (reg1) == REGNO (reg2))
30337 && (((off1 <= off2) && (off1 + size1 > off2))
30338 || ((off2 <= off1) && (off2 + size2 > off1))));
30343 /* A C statement (sans semicolon) to update the integer scheduling
30344 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30345 INSN earlier, reduce the priority to execute INSN later. Do not
30346 define this macro if you do not need to adjust the scheduling
30347 priorities of insns. */
30350 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30352 rtx load_mem, str_mem;
30353 /* On machines (like the 750) which have asymmetric integer units,
30354 where one integer unit can do multiply and divides and the other
30355 can't, reduce the priority of multiply/divide so it is scheduled
30356 before other integer operations. */
30359 if (! INSN_P (insn))
30362 if (GET_CODE (PATTERN (insn)) == USE)
30365 switch (rs6000_tune) {
30366 case PROCESSOR_PPC750:
30367 switch (get_attr_type (insn))
30374 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30375 priority, priority);
30376 if (priority >= 0 && priority < 0x01000000)
30383 if (insn_must_be_first_in_group (insn)
30384 && reload_completed
30385 && current_sched_info->sched_max_insns_priority
30386 && rs6000_sched_restricted_insns_priority)
30389 /* Prioritize insns that can be dispatched only in the first
30391 if (rs6000_sched_restricted_insns_priority == 1)
30392 /* Attach highest priority to insn. This means that in
30393 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30394 precede 'priority' (critical path) considerations. */
30395 return current_sched_info->sched_max_insns_priority;
30396 else if (rs6000_sched_restricted_insns_priority == 2)
30397 /* Increase priority of insn by a minimal amount. This means that in
30398 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30399 considerations precede dispatch-slot restriction considerations. */
30400 return (priority + 1);
30403 if (rs6000_tune == PROCESSOR_POWER6
30404 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30405 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30406 /* Attach highest priority to insn if the scheduler has just issued two
30407 stores and this instruction is a load, or two loads and this instruction
30408 is a store. Power6 wants loads and stores scheduled alternately
30410 return current_sched_info->sched_max_insns_priority;
30415 /* Return true if the instruction is nonpipelined on the Cell. */
30417 is_nonpipeline_insn (rtx_insn *insn)
30419 enum attr_type type;
30420 if (!insn || !NONDEBUG_INSN_P (insn)
30421 || GET_CODE (PATTERN (insn)) == USE
30422 || GET_CODE (PATTERN (insn)) == CLOBBER)
30425 type = get_attr_type (insn);
30426 if (type == TYPE_MUL
30427 || type == TYPE_DIV
30428 || type == TYPE_SDIV
30429 || type == TYPE_DDIV
30430 || type == TYPE_SSQRT
30431 || type == TYPE_DSQRT
30432 || type == TYPE_MFCR
30433 || type == TYPE_MFCRF
30434 || type == TYPE_MFJMPR)
30442 /* Return how many instructions the machine can issue per cycle. */
30445 rs6000_issue_rate (void)
30447 /* Unless scheduling for register pressure, use issue rate of 1 for
30448 first scheduling pass to decrease degradation. */
30449 if (!reload_completed && !flag_sched_pressure)
30452 switch (rs6000_tune) {
30453 case PROCESSOR_RS64A:
30454 case PROCESSOR_PPC601: /* ? */
30455 case PROCESSOR_PPC7450:
30457 case PROCESSOR_PPC440:
30458 case PROCESSOR_PPC603:
30459 case PROCESSOR_PPC750:
30460 case PROCESSOR_PPC7400:
30461 case PROCESSOR_PPC8540:
30462 case PROCESSOR_PPC8548:
30463 case PROCESSOR_CELL:
30464 case PROCESSOR_PPCE300C2:
30465 case PROCESSOR_PPCE300C3:
30466 case PROCESSOR_PPCE500MC:
30467 case PROCESSOR_PPCE500MC64:
30468 case PROCESSOR_PPCE5500:
30469 case PROCESSOR_PPCE6500:
30470 case PROCESSOR_TITAN:
30472 case PROCESSOR_PPC476:
30473 case PROCESSOR_PPC604:
30474 case PROCESSOR_PPC604e:
30475 case PROCESSOR_PPC620:
30476 case PROCESSOR_PPC630:
30478 case PROCESSOR_POWER4:
30479 case PROCESSOR_POWER5:
30480 case PROCESSOR_POWER6:
30481 case PROCESSOR_POWER7:
30483 case PROCESSOR_POWER8:
30485 case PROCESSOR_POWER9:
30492 /* Return how many instructions to look ahead for better insn
30496 rs6000_use_sched_lookahead (void)
30498 switch (rs6000_tune)
30500 case PROCESSOR_PPC8540:
30501 case PROCESSOR_PPC8548:
30504 case PROCESSOR_CELL:
30505 return (reload_completed ? 8 : 0);
30512 /* We are choosing insn from the ready queue. Return zero if INSN can be
30515 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30517 if (ready_index == 0)
30520 if (rs6000_tune != PROCESSOR_CELL)
30523 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30525 if (!reload_completed
30526 || is_nonpipeline_insn (insn)
30527 || is_microcoded_insn (insn))
30533 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30534 and return true. */
30537 find_mem_ref (rtx pat, rtx *mem_ref)
30542 /* stack_tie does not produce any real memory traffic. */
30543 if (tie_operand (pat, VOIDmode))
30546 if (GET_CODE (pat) == MEM)
30552 /* Recursively process the pattern. */
30553 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30555 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30559 if (find_mem_ref (XEXP (pat, i), mem_ref))
30562 else if (fmt[i] == 'E')
30563 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30565 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30573 /* Determine if PAT is a PATTERN of a load insn. */
30576 is_load_insn1 (rtx pat, rtx *load_mem)
30578 if (!pat || pat == NULL_RTX)
30581 if (GET_CODE (pat) == SET)
30582 return find_mem_ref (SET_SRC (pat), load_mem);
30584 if (GET_CODE (pat) == PARALLEL)
30588 for (i = 0; i < XVECLEN (pat, 0); i++)
30589 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30596 /* Determine if INSN loads from memory. */
30599 is_load_insn (rtx insn, rtx *load_mem)
30601 if (!insn || !INSN_P (insn))
30607 return is_load_insn1 (PATTERN (insn), load_mem);
30610 /* Determine if PAT is a PATTERN of a store insn. */
30613 is_store_insn1 (rtx pat, rtx *str_mem)
30615 if (!pat || pat == NULL_RTX)
30618 if (GET_CODE (pat) == SET)
30619 return find_mem_ref (SET_DEST (pat), str_mem);
30621 if (GET_CODE (pat) == PARALLEL)
30625 for (i = 0; i < XVECLEN (pat, 0); i++)
30626 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30633 /* Determine if INSN stores to memory. */
30636 is_store_insn (rtx insn, rtx *str_mem)
30638 if (!insn || !INSN_P (insn))
30641 return is_store_insn1 (PATTERN (insn), str_mem);
30644 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30647 is_power9_pairable_vec_type (enum attr_type type)
30651 case TYPE_VECSIMPLE:
30652 case TYPE_VECCOMPLEX:
30656 case TYPE_VECFLOAT:
30658 case TYPE_VECDOUBLE:
30666 /* Returns whether the dependence between INSN and NEXT is considered
30667 costly by the given target. */
30670 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30674 rtx load_mem, str_mem;
30676 /* If the flag is not enabled - no dependence is considered costly;
30677 allow all dependent insns in the same group.
30678 This is the most aggressive option. */
30679 if (rs6000_sched_costly_dep == no_dep_costly)
30682 /* If the flag is set to 1 - a dependence is always considered costly;
30683 do not allow dependent instructions in the same group.
30684 This is the most conservative option. */
30685 if (rs6000_sched_costly_dep == all_deps_costly)
30688 insn = DEP_PRO (dep);
30689 next = DEP_CON (dep);
30691 if (rs6000_sched_costly_dep == store_to_load_dep_costly
30692 && is_load_insn (next, &load_mem)
30693 && is_store_insn (insn, &str_mem))
30694 /* Prevent load after store in the same group. */
30697 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
30698 && is_load_insn (next, &load_mem)
30699 && is_store_insn (insn, &str_mem)
30700 && DEP_TYPE (dep) == REG_DEP_TRUE
30701 && mem_locations_overlap(str_mem, load_mem))
30702 /* Prevent load after store in the same group if it is a true
30706 /* The flag is set to X; dependences with latency >= X are considered costly,
30707 and will not be scheduled in the same group. */
30708 if (rs6000_sched_costly_dep <= max_dep_latency
30709 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
30715 /* Return the next insn after INSN that is found before TAIL is reached,
30716 skipping any "non-active" insns - insns that will not actually occupy
30717 an issue slot. Return NULL_RTX if such an insn is not found. */
30720 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
30722 if (insn == NULL_RTX || insn == tail)
30727 insn = NEXT_INSN (insn);
30728 if (insn == NULL_RTX || insn == tail)
30732 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
30733 || (NONJUMP_INSN_P (insn)
30734 && GET_CODE (PATTERN (insn)) != USE
30735 && GET_CODE (PATTERN (insn)) != CLOBBER
30736 && INSN_CODE (insn) != CODE_FOR_stack_tie))
30742 /* Do Power9 specific sched_reorder2 reordering of ready list. */
30745 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
30750 enum attr_type type, type2;
30752 type = get_attr_type (last_scheduled_insn);
30754 /* Try to issue fixed point divides back-to-back in pairs so they will be
30755 routed to separate execution units and execute in parallel. */
30756 if (type == TYPE_DIV && divide_cnt == 0)
30758 /* First divide has been scheduled. */
30761 /* Scan the ready list looking for another divide, if found move it
30762 to the end of the list so it is chosen next. */
30766 if (recog_memoized (ready[pos]) >= 0
30767 && get_attr_type (ready[pos]) == TYPE_DIV)
30770 for (i = pos; i < lastpos; i++)
30771 ready[i] = ready[i + 1];
30772 ready[lastpos] = tmp;
30780 /* Last insn was the 2nd divide or not a divide, reset the counter. */
30783 /* The best dispatch throughput for vector and vector load insns can be
30784 achieved by interleaving a vector and vector load such that they'll
30785 dispatch to the same superslice. If this pairing cannot be achieved
30786 then it is best to pair vector insns together and vector load insns
30789 To aid in this pairing, vec_pairing maintains the current state with
30790 the following values:
30792 0 : Initial state, no vecload/vector pairing has been started.
30794 1 : A vecload or vector insn has been issued and a candidate for
30795 pairing has been found and moved to the end of the ready
30797 if (type == TYPE_VECLOAD)
30799 /* Issued a vecload. */
30800 if (vec_pairing == 0)
30802 int vecload_pos = -1;
30803 /* We issued a single vecload, look for a vector insn to pair it
30804 with. If one isn't found, try to pair another vecload. */
30808 if (recog_memoized (ready[pos]) >= 0)
30810 type2 = get_attr_type (ready[pos]);
30811 if (is_power9_pairable_vec_type (type2))
30813 /* Found a vector insn to pair with, move it to the
30814 end of the ready list so it is scheduled next. */
30816 for (i = pos; i < lastpos; i++)
30817 ready[i] = ready[i + 1];
30818 ready[lastpos] = tmp;
30820 return cached_can_issue_more;
30822 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
30823 /* Remember position of first vecload seen. */
30828 if (vecload_pos >= 0)
30830 /* Didn't find a vector to pair with but did find a vecload,
30831 move it to the end of the ready list. */
30832 tmp = ready[vecload_pos];
30833 for (i = vecload_pos; i < lastpos; i++)
30834 ready[i] = ready[i + 1];
30835 ready[lastpos] = tmp;
30837 return cached_can_issue_more;
30841 else if (is_power9_pairable_vec_type (type))
30843 /* Issued a vector operation. */
30844 if (vec_pairing == 0)
30847 /* We issued a single vector insn, look for a vecload to pair it
30848 with. If one isn't found, try to pair another vector. */
30852 if (recog_memoized (ready[pos]) >= 0)
30854 type2 = get_attr_type (ready[pos]);
30855 if (type2 == TYPE_VECLOAD)
30857 /* Found a vecload insn to pair with, move it to the
30858 end of the ready list so it is scheduled next. */
30860 for (i = pos; i < lastpos; i++)
30861 ready[i] = ready[i + 1];
30862 ready[lastpos] = tmp;
30864 return cached_can_issue_more;
30866 else if (is_power9_pairable_vec_type (type2)
30868 /* Remember position of first vector insn seen. */
30875 /* Didn't find a vecload to pair with but did find a vector
30876 insn, move it to the end of the ready list. */
30877 tmp = ready[vec_pos];
30878 for (i = vec_pos; i < lastpos; i++)
30879 ready[i] = ready[i + 1];
30880 ready[lastpos] = tmp;
30882 return cached_can_issue_more;
30887 /* We've either finished a vec/vecload pair, couldn't find an insn to
30888 continue the current pair, or the last insn had nothing to do with
30889 with pairing. In any case, reset the state. */
30893 return cached_can_issue_more;
30896 /* We are about to begin issuing insns for this clock cycle. */
30899 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
30900 rtx_insn **ready ATTRIBUTE_UNUSED,
30901 int *pn_ready ATTRIBUTE_UNUSED,
30902 int clock_var ATTRIBUTE_UNUSED)
30904 int n_ready = *pn_ready;
30907 fprintf (dump, "// rs6000_sched_reorder :\n");
30909 /* Reorder the ready list, if the second to last ready insn
30910 is a nonepipeline insn. */
30911 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
30913 if (is_nonpipeline_insn (ready[n_ready - 1])
30914 && (recog_memoized (ready[n_ready - 2]) > 0))
30915 /* Simply swap first two insns. */
30916 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
30919 if (rs6000_tune == PROCESSOR_POWER6)
30920 load_store_pendulum = 0;
30922 return rs6000_issue_rate ();
30925 /* Like rs6000_sched_reorder, but called after issuing each insn. */
30928 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
30929 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
30932 fprintf (dump, "// rs6000_sched_reorder2 :\n");
30934 /* For Power6, we need to handle some special cases to try and keep the
30935 store queue from overflowing and triggering expensive flushes.
30937 This code monitors how load and store instructions are being issued
30938 and skews the ready list one way or the other to increase the likelihood
30939 that a desired instruction is issued at the proper time.
30941 A couple of things are done. First, we maintain a "load_store_pendulum"
30942 to track the current state of load/store issue.
30944 - If the pendulum is at zero, then no loads or stores have been
30945 issued in the current cycle so we do nothing.
30947 - If the pendulum is 1, then a single load has been issued in this
30948 cycle and we attempt to locate another load in the ready list to
30951 - If the pendulum is -2, then two stores have already been
30952 issued in this cycle, so we increase the priority of the first load
30953 in the ready list to increase it's likelihood of being chosen first
30956 - If the pendulum is -1, then a single store has been issued in this
30957 cycle and we attempt to locate another store in the ready list to
30958 issue with it, preferring a store to an adjacent memory location to
30959 facilitate store pairing in the store queue.
30961 - If the pendulum is 2, then two loads have already been
30962 issued in this cycle, so we increase the priority of the first store
30963 in the ready list to increase it's likelihood of being chosen first
30966 - If the pendulum < -2 or > 2, then do nothing.
30968 Note: This code covers the most common scenarios. There exist non
30969 load/store instructions which make use of the LSU and which
30970 would need to be accounted for to strictly model the behavior
30971 of the machine. Those instructions are currently unaccounted
30972 for to help minimize compile time overhead of this code.
30974 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
30979 rtx load_mem, str_mem;
30981 if (is_store_insn (last_scheduled_insn, &str_mem))
30982 /* Issuing a store, swing the load_store_pendulum to the left */
30983 load_store_pendulum--;
30984 else if (is_load_insn (last_scheduled_insn, &load_mem))
30985 /* Issuing a load, swing the load_store_pendulum to the right */
30986 load_store_pendulum++;
30988 return cached_can_issue_more;
30990 /* If the pendulum is balanced, or there is only one instruction on
30991 the ready list, then all is well, so return. */
30992 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
30993 return cached_can_issue_more;
30995 if (load_store_pendulum == 1)
30997 /* A load has been issued in this cycle. Scan the ready list
30998 for another load to issue with it */
31003 if (is_load_insn (ready[pos], &load_mem))
31005 /* Found a load. Move it to the head of the ready list,
31006 and adjust it's priority so that it is more likely to
31009 for (i=pos; i<*pn_ready-1; i++)
31010 ready[i] = ready[i + 1];
31011 ready[*pn_ready-1] = tmp;
31013 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31014 INSN_PRIORITY (tmp)++;
31020 else if (load_store_pendulum == -2)
31022 /* Two stores have been issued in this cycle. Increase the
31023 priority of the first load in the ready list to favor it for
31024 issuing in the next cycle. */
31029 if (is_load_insn (ready[pos], &load_mem)
31031 && INSN_PRIORITY_KNOWN (ready[pos]))
31033 INSN_PRIORITY (ready[pos])++;
31035 /* Adjust the pendulum to account for the fact that a load
31036 was found and increased in priority. This is to prevent
31037 increasing the priority of multiple loads */
31038 load_store_pendulum--;
31045 else if (load_store_pendulum == -1)
31047 /* A store has been issued in this cycle. Scan the ready list for
31048 another store to issue with it, preferring a store to an adjacent
31050 int first_store_pos = -1;
31056 if (is_store_insn (ready[pos], &str_mem))
31059 /* Maintain the index of the first store found on the
31061 if (first_store_pos == -1)
31062 first_store_pos = pos;
31064 if (is_store_insn (last_scheduled_insn, &str_mem2)
31065 && adjacent_mem_locations (str_mem, str_mem2))
31067 /* Found an adjacent store. Move it to the head of the
31068 ready list, and adjust it's priority so that it is
31069 more likely to stay there */
31071 for (i=pos; i<*pn_ready-1; i++)
31072 ready[i] = ready[i + 1];
31073 ready[*pn_ready-1] = tmp;
31075 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31076 INSN_PRIORITY (tmp)++;
31078 first_store_pos = -1;
31086 if (first_store_pos >= 0)
31088 /* An adjacent store wasn't found, but a non-adjacent store was,
31089 so move the non-adjacent store to the front of the ready
31090 list, and adjust its priority so that it is more likely to
31092 tmp = ready[first_store_pos];
31093 for (i=first_store_pos; i<*pn_ready-1; i++)
31094 ready[i] = ready[i + 1];
31095 ready[*pn_ready-1] = tmp;
31096 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31097 INSN_PRIORITY (tmp)++;
31100 else if (load_store_pendulum == 2)
31102 /* Two loads have been issued in this cycle. Increase the priority
31103 of the first store in the ready list to favor it for issuing in
31109 if (is_store_insn (ready[pos], &str_mem)
31111 && INSN_PRIORITY_KNOWN (ready[pos]))
31113 INSN_PRIORITY (ready[pos])++;
31115 /* Adjust the pendulum to account for the fact that a store
31116 was found and increased in priority. This is to prevent
31117 increasing the priority of multiple stores */
31118 load_store_pendulum++;
31127 /* Do Power9 dependent reordering if necessary. */
31128 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31129 && recog_memoized (last_scheduled_insn) >= 0)
31130 return power9_sched_reorder2 (ready, *pn_ready - 1);
31132 return cached_can_issue_more;
31135 /* Return whether the presence of INSN causes a dispatch group termination
31136 of group WHICH_GROUP.
31138 If WHICH_GROUP == current_group, this function will return true if INSN
31139 causes the termination of the current group (i.e, the dispatch group to
31140 which INSN belongs). This means that INSN will be the last insn in the
31141 group it belongs to.
31143 If WHICH_GROUP == previous_group, this function will return true if INSN
31144 causes the termination of the previous group (i.e, the dispatch group that
31145 precedes the group to which INSN belongs). This means that INSN will be
31146 the first insn in the group it belongs to). */
31149 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31156 first = insn_must_be_first_in_group (insn);
31157 last = insn_must_be_last_in_group (insn);
31162 if (which_group == current_group)
31164 else if (which_group == previous_group)
31172 insn_must_be_first_in_group (rtx_insn *insn)
31174 enum attr_type type;
31178 || DEBUG_INSN_P (insn)
31179 || GET_CODE (PATTERN (insn)) == USE
31180 || GET_CODE (PATTERN (insn)) == CLOBBER)
31183 switch (rs6000_tune)
31185 case PROCESSOR_POWER5:
31186 if (is_cracked_insn (insn))
31189 case PROCESSOR_POWER4:
31190 if (is_microcoded_insn (insn))
31193 if (!rs6000_sched_groups)
31196 type = get_attr_type (insn);
31203 case TYPE_CR_LOGICAL:
31216 case PROCESSOR_POWER6:
31217 type = get_attr_type (insn);
31226 case TYPE_FPCOMPARE:
31237 if (get_attr_dot (insn) == DOT_NO
31238 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31243 if (get_attr_size (insn) == SIZE_32)
31251 if (get_attr_update (insn) == UPDATE_YES)
31259 case PROCESSOR_POWER7:
31260 type = get_attr_type (insn);
31264 case TYPE_CR_LOGICAL:
31278 if (get_attr_dot (insn) == DOT_YES)
31283 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31284 || get_attr_update (insn) == UPDATE_YES)
31291 if (get_attr_update (insn) == UPDATE_YES)
31299 case PROCESSOR_POWER8:
31300 type = get_attr_type (insn);
31304 case TYPE_CR_LOGICAL:
31312 case TYPE_VECSTORE:
31319 if (get_attr_dot (insn) == DOT_YES)
31324 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31325 || get_attr_update (insn) == UPDATE_YES)
31330 if (get_attr_update (insn) == UPDATE_YES
31331 && get_attr_indexed (insn) == INDEXED_YES)
31347 insn_must_be_last_in_group (rtx_insn *insn)
31349 enum attr_type type;
31353 || DEBUG_INSN_P (insn)
31354 || GET_CODE (PATTERN (insn)) == USE
31355 || GET_CODE (PATTERN (insn)) == CLOBBER)
31358 switch (rs6000_tune) {
31359 case PROCESSOR_POWER4:
31360 case PROCESSOR_POWER5:
31361 if (is_microcoded_insn (insn))
31364 if (is_branch_slot_insn (insn))
31368 case PROCESSOR_POWER6:
31369 type = get_attr_type (insn);
31377 case TYPE_FPCOMPARE:
31388 if (get_attr_dot (insn) == DOT_NO
31389 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31394 if (get_attr_size (insn) == SIZE_32)
31402 case PROCESSOR_POWER7:
31403 type = get_attr_type (insn);
31413 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31414 && get_attr_update (insn) == UPDATE_YES)
31419 if (get_attr_update (insn) == UPDATE_YES
31420 && get_attr_indexed (insn) == INDEXED_YES)
31428 case PROCESSOR_POWER8:
31429 type = get_attr_type (insn);
31441 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31442 && get_attr_update (insn) == UPDATE_YES)
31447 if (get_attr_update (insn) == UPDATE_YES
31448 && get_attr_indexed (insn) == INDEXED_YES)
31463 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31464 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31467 is_costly_group (rtx *group_insns, rtx next_insn)
31470 int issue_rate = rs6000_issue_rate ();
31472 for (i = 0; i < issue_rate; i++)
31474 sd_iterator_def sd_it;
31476 rtx insn = group_insns[i];
31481 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31483 rtx next = DEP_CON (dep);
31485 if (next == next_insn
31486 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31494 /* Utility of the function redefine_groups.
31495 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31496 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31497 to keep it "far" (in a separate group) from GROUP_INSNS, following
31498 one of the following schemes, depending on the value of the flag
31499 -minsert_sched_nops = X:
31500 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31501 in order to force NEXT_INSN into a separate group.
31502 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31503 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31504 insertion (has a group just ended, how many vacant issue slots remain in the
31505 last group, and how many dispatch groups were encountered so far). */
31508 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31509 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31514 int issue_rate = rs6000_issue_rate ();
31515 bool end = *group_end;
31518 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31519 return can_issue_more;
31521 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31522 return can_issue_more;
31524 force = is_costly_group (group_insns, next_insn);
31526 return can_issue_more;
31528 if (sched_verbose > 6)
31529 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31530 *group_count ,can_issue_more);
31532 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31535 can_issue_more = 0;
31537 /* Since only a branch can be issued in the last issue_slot, it is
31538 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31539 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31540 in this case the last nop will start a new group and the branch
31541 will be forced to the new group. */
31542 if (can_issue_more && !is_branch_slot_insn (next_insn))
31545 /* Do we have a special group ending nop? */
31546 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31547 || rs6000_tune == PROCESSOR_POWER8)
31549 nop = gen_group_ending_nop ();
31550 emit_insn_before (nop, next_insn);
31551 can_issue_more = 0;
31554 while (can_issue_more > 0)
31557 emit_insn_before (nop, next_insn);
31565 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31567 int n_nops = rs6000_sched_insert_nops;
31569 /* Nops can't be issued from the branch slot, so the effective
31570 issue_rate for nops is 'issue_rate - 1'. */
31571 if (can_issue_more == 0)
31572 can_issue_more = issue_rate;
31574 if (can_issue_more == 0)
31576 can_issue_more = issue_rate - 1;
31579 for (i = 0; i < issue_rate; i++)
31581 group_insns[i] = 0;
31588 emit_insn_before (nop, next_insn);
31589 if (can_issue_more == issue_rate - 1) /* new group begins */
31592 if (can_issue_more == 0)
31594 can_issue_more = issue_rate - 1;
31597 for (i = 0; i < issue_rate; i++)
31599 group_insns[i] = 0;
31605 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31608 /* Is next_insn going to start a new group? */
31611 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31612 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31613 || (can_issue_more < issue_rate &&
31614 insn_terminates_group_p (next_insn, previous_group)));
31615 if (*group_end && end)
31618 if (sched_verbose > 6)
31619 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31620 *group_count, can_issue_more);
31621 return can_issue_more;
31624 return can_issue_more;
31627 /* This function tries to synch the dispatch groups that the compiler "sees"
31628 with the dispatch groups that the processor dispatcher is expected to
31629 form in practice. It tries to achieve this synchronization by forcing the
31630 estimated processor grouping on the compiler (as opposed to the function
31631 'pad_goups' which tries to force the scheduler's grouping on the processor).
31633 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31634 examines the (estimated) dispatch groups that will be formed by the processor
31635 dispatcher. It marks these group boundaries to reflect the estimated
31636 processor grouping, overriding the grouping that the scheduler had marked.
31637 Depending on the value of the flag '-minsert-sched-nops' this function can
31638 force certain insns into separate groups or force a certain distance between
31639 them by inserting nops, for example, if there exists a "costly dependence"
31642 The function estimates the group boundaries that the processor will form as
31643 follows: It keeps track of how many vacant issue slots are available after
31644 each insn. A subsequent insn will start a new group if one of the following
31646 - no more vacant issue slots remain in the current dispatch group.
31647 - only the last issue slot, which is the branch slot, is vacant, but the next
31648 insn is not a branch.
31649 - only the last 2 or less issue slots, including the branch slot, are vacant,
31650 which means that a cracked insn (which occupies two issue slots) can't be
31651 issued in this group.
31652 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31653 start a new group. */
31656 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31659 rtx_insn *insn, *next_insn;
31661 int can_issue_more;
31664 int group_count = 0;
31668 issue_rate = rs6000_issue_rate ();
31669 group_insns = XALLOCAVEC (rtx, issue_rate);
31670 for (i = 0; i < issue_rate; i++)
31672 group_insns[i] = 0;
31674 can_issue_more = issue_rate;
31676 insn = get_next_active_insn (prev_head_insn, tail);
31679 while (insn != NULL_RTX)
31681 slot = (issue_rate - can_issue_more);
31682 group_insns[slot] = insn;
31684 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31685 if (insn_terminates_group_p (insn, current_group))
31686 can_issue_more = 0;
31688 next_insn = get_next_active_insn (insn, tail);
31689 if (next_insn == NULL_RTX)
31690 return group_count + 1;
31692 /* Is next_insn going to start a new group? */
31694 = (can_issue_more == 0
31695 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31696 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31697 || (can_issue_more < issue_rate &&
31698 insn_terminates_group_p (next_insn, previous_group)));
31700 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
31701 next_insn, &group_end, can_issue_more,
31707 can_issue_more = 0;
31708 for (i = 0; i < issue_rate; i++)
31710 group_insns[i] = 0;
31714 if (GET_MODE (next_insn) == TImode && can_issue_more)
31715 PUT_MODE (next_insn, VOIDmode);
31716 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
31717 PUT_MODE (next_insn, TImode);
31720 if (can_issue_more == 0)
31721 can_issue_more = issue_rate;
31724 return group_count;
31727 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
31728 dispatch group boundaries that the scheduler had marked. Pad with nops
31729 any dispatch groups which have vacant issue slots, in order to force the
31730 scheduler's grouping on the processor dispatcher. The function
31731 returns the number of dispatch groups found. */
31734 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31737 rtx_insn *insn, *next_insn;
31740 int can_issue_more;
31742 int group_count = 0;
31744 /* Initialize issue_rate. */
31745 issue_rate = rs6000_issue_rate ();
31746 can_issue_more = issue_rate;
31748 insn = get_next_active_insn (prev_head_insn, tail);
31749 next_insn = get_next_active_insn (insn, tail);
31751 while (insn != NULL_RTX)
31754 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31756 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
31758 if (next_insn == NULL_RTX)
31763 /* If the scheduler had marked group termination at this location
31764 (between insn and next_insn), and neither insn nor next_insn will
31765 force group termination, pad the group with nops to force group
31768 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
31769 && !insn_terminates_group_p (insn, current_group)
31770 && !insn_terminates_group_p (next_insn, previous_group))
31772 if (!is_branch_slot_insn (next_insn))
31775 while (can_issue_more)
31778 emit_insn_before (nop, next_insn);
31783 can_issue_more = issue_rate;
31788 next_insn = get_next_active_insn (insn, tail);
31791 return group_count;
31794 /* We're beginning a new block. Initialize data structures as necessary. */
31797 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
31798 int sched_verbose ATTRIBUTE_UNUSED,
31799 int max_ready ATTRIBUTE_UNUSED)
31801 last_scheduled_insn = NULL;
31802 load_store_pendulum = 0;
31807 /* The following function is called at the end of scheduling BB.
31808 After reload, it inserts nops at insn group bundling. */
31811 rs6000_sched_finish (FILE *dump, int sched_verbose)
31816 fprintf (dump, "=== Finishing schedule.\n");
31818 if (reload_completed && rs6000_sched_groups)
31820 /* Do not run sched_finish hook when selective scheduling enabled. */
31821 if (sel_sched_p ())
31824 if (rs6000_sched_insert_nops == sched_finish_none)
31827 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
31828 n_groups = pad_groups (dump, sched_verbose,
31829 current_sched_info->prev_head,
31830 current_sched_info->next_tail);
31832 n_groups = redefine_groups (dump, sched_verbose,
31833 current_sched_info->prev_head,
31834 current_sched_info->next_tail);
31836 if (sched_verbose >= 6)
31838 fprintf (dump, "ngroups = %d\n", n_groups);
31839 print_rtl (dump, current_sched_info->prev_head);
31840 fprintf (dump, "Done finish_sched\n");
31845 struct rs6000_sched_context
31847 short cached_can_issue_more;
31848 rtx_insn *last_scheduled_insn;
31849 int load_store_pendulum;
31854 typedef struct rs6000_sched_context rs6000_sched_context_def;
31855 typedef rs6000_sched_context_def *rs6000_sched_context_t;
31857 /* Allocate store for new scheduling context. */
31859 rs6000_alloc_sched_context (void)
31861 return xmalloc (sizeof (rs6000_sched_context_def));
31864 /* If CLEAN_P is true then initializes _SC with clean data,
31865 and from the global context otherwise. */
31867 rs6000_init_sched_context (void *_sc, bool clean_p)
31869 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
31873 sc->cached_can_issue_more = 0;
31874 sc->last_scheduled_insn = NULL;
31875 sc->load_store_pendulum = 0;
31876 sc->divide_cnt = 0;
31877 sc->vec_pairing = 0;
31881 sc->cached_can_issue_more = cached_can_issue_more;
31882 sc->last_scheduled_insn = last_scheduled_insn;
31883 sc->load_store_pendulum = load_store_pendulum;
31884 sc->divide_cnt = divide_cnt;
31885 sc->vec_pairing = vec_pairing;
31889 /* Sets the global scheduling context to the one pointed to by _SC. */
31891 rs6000_set_sched_context (void *_sc)
31893 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
31895 gcc_assert (sc != NULL);
31897 cached_can_issue_more = sc->cached_can_issue_more;
31898 last_scheduled_insn = sc->last_scheduled_insn;
31899 load_store_pendulum = sc->load_store_pendulum;
31900 divide_cnt = sc->divide_cnt;
31901 vec_pairing = sc->vec_pairing;
31906 rs6000_free_sched_context (void *_sc)
31908 gcc_assert (_sc != NULL);
31914 rs6000_sched_can_speculate_insn (rtx_insn *insn)
31916 switch (get_attr_type (insn))
31931 /* Length in units of the trampoline for entering a nested function. */
31934 rs6000_trampoline_size (void)
31938 switch (DEFAULT_ABI)
31941 gcc_unreachable ();
31944 ret = (TARGET_32BIT) ? 12 : 24;
31948 gcc_assert (!TARGET_32BIT);
31954 ret = (TARGET_32BIT) ? 40 : 48;
31961 /* Emit RTL insns to initialize the variable parts of a trampoline.
31962 FNADDR is an RTX for the address of the function's pure code.
31963 CXT is an RTX for the static chain value for the function. */
31966 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
31968 int regsize = (TARGET_32BIT) ? 4 : 8;
31969 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
31970 rtx ctx_reg = force_reg (Pmode, cxt);
31971 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
31973 switch (DEFAULT_ABI)
31976 gcc_unreachable ();
31978 /* Under AIX, just build the 3 word function descriptor */
31981 rtx fnmem, fn_reg, toc_reg;
31983 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
31984 error ("you cannot take the address of a nested function if you use "
31985 "the %qs option", "-mno-pointers-to-nested-functions");
31987 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
31988 fn_reg = gen_reg_rtx (Pmode);
31989 toc_reg = gen_reg_rtx (Pmode);
31991 /* Macro to shorten the code expansions below. */
31992 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
31994 m_tramp = replace_equiv_address (m_tramp, addr);
31996 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
31997 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
31998 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
31999 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32000 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32006 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32010 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32011 LCT_NORMAL, VOIDmode,
32013 GEN_INT (rs6000_trampoline_size ()), SImode,
32021 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32022 identifier as an argument, so the front end shouldn't look it up. */
32025 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32027 return is_attribute_p ("altivec", attr_id);
32030 /* Handle the "altivec" attribute. The attribute may have
32031 arguments as follows:
32033 __attribute__((altivec(vector__)))
32034 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32035 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32037 and may appear more than once (e.g., 'vector bool char') in a
32038 given declaration. */
32041 rs6000_handle_altivec_attribute (tree *node,
32042 tree name ATTRIBUTE_UNUSED,
32044 int flags ATTRIBUTE_UNUSED,
32045 bool *no_add_attrs)
32047 tree type = *node, result = NULL_TREE;
32051 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32052 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32053 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32056 while (POINTER_TYPE_P (type)
32057 || TREE_CODE (type) == FUNCTION_TYPE
32058 || TREE_CODE (type) == METHOD_TYPE
32059 || TREE_CODE (type) == ARRAY_TYPE)
32060 type = TREE_TYPE (type);
32062 mode = TYPE_MODE (type);
32064 /* Check for invalid AltiVec type qualifiers. */
32065 if (type == long_double_type_node)
32066 error ("use of %<long double%> in AltiVec types is invalid");
32067 else if (type == boolean_type_node)
32068 error ("use of boolean types in AltiVec types is invalid");
32069 else if (TREE_CODE (type) == COMPLEX_TYPE)
32070 error ("use of %<complex%> in AltiVec types is invalid");
32071 else if (DECIMAL_FLOAT_MODE_P (mode))
32072 error ("use of decimal floating point types in AltiVec types is invalid");
32073 else if (!TARGET_VSX)
32075 if (type == long_unsigned_type_node || type == long_integer_type_node)
32078 error ("use of %<long%> in AltiVec types is invalid for "
32079 "64-bit code without %qs", "-mvsx");
32080 else if (rs6000_warn_altivec_long)
32081 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32084 else if (type == long_long_unsigned_type_node
32085 || type == long_long_integer_type_node)
32086 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32088 else if (type == double_type_node)
32089 error ("use of %<double%> in AltiVec types is invalid without %qs",
32093 switch (altivec_type)
32096 unsigned_p = TYPE_UNSIGNED (type);
32100 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32103 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32106 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32109 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32112 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32114 case E_SFmode: result = V4SF_type_node; break;
32115 case E_DFmode: result = V2DF_type_node; break;
32116 /* If the user says 'vector int bool', we may be handed the 'bool'
32117 attribute _before_ the 'vector' attribute, and so select the
32118 proper type in the 'b' case below. */
32119 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32120 case E_V2DImode: case E_V2DFmode:
32128 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32129 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32130 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32131 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32138 case E_V8HImode: result = pixel_V8HI_type_node;
32144 /* Propagate qualifiers attached to the element type
32145 onto the vector type. */
32146 if (result && result != type && TYPE_QUALS (type))
32147 result = build_qualified_type (result, TYPE_QUALS (type));
32149 *no_add_attrs = true; /* No need to hang on to the attribute. */
32152 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32157 /* AltiVec defines five built-in scalar types that serve as vector
32158 elements; we must teach the compiler how to mangle them. The 128-bit
32159 floating point mangling is target-specific as well. */
32161 static const char *
32162 rs6000_mangle_type (const_tree type)
32164 type = TYPE_MAIN_VARIANT (type);
32166 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32167 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32170 if (type == bool_char_type_node) return "U6__boolc";
32171 if (type == bool_short_type_node) return "U6__bools";
32172 if (type == pixel_type_node) return "u7__pixel";
32173 if (type == bool_int_type_node) return "U6__booli";
32174 if (type == bool_long_long_type_node) return "U6__boolx";
32176 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32178 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32179 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32181 /* For all other types, use the default mangling. */
32185 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32186 struct attribute_spec.handler. */
32189 rs6000_handle_longcall_attribute (tree *node, tree name,
32190 tree args ATTRIBUTE_UNUSED,
32191 int flags ATTRIBUTE_UNUSED,
32192 bool *no_add_attrs)
32194 if (TREE_CODE (*node) != FUNCTION_TYPE
32195 && TREE_CODE (*node) != FIELD_DECL
32196 && TREE_CODE (*node) != TYPE_DECL)
32198 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32200 *no_add_attrs = true;
32206 /* Set longcall attributes on all functions declared when
32207 rs6000_default_long_calls is true. */
32209 rs6000_set_default_type_attributes (tree type)
32211 if (rs6000_default_long_calls
32212 && (TREE_CODE (type) == FUNCTION_TYPE
32213 || TREE_CODE (type) == METHOD_TYPE))
32214 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32216 TYPE_ATTRIBUTES (type));
32219 darwin_set_default_type_attributes (type);
32223 /* Return a reference suitable for calling a function with the
32224 longcall attribute. */
32227 rs6000_longcall_ref (rtx call_ref)
32229 const char *call_name;
32232 if (GET_CODE (call_ref) != SYMBOL_REF)
32235 /* System V adds '.' to the internal name, so skip them. */
32236 call_name = XSTR (call_ref, 0);
32237 if (*call_name == '.')
32239 while (*call_name == '.')
32242 node = get_identifier (call_name);
32243 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32246 return force_reg (Pmode, call_ref);
32249 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32250 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32253 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32254 struct attribute_spec.handler. */
32256 rs6000_handle_struct_attribute (tree *node, tree name,
32257 tree args ATTRIBUTE_UNUSED,
32258 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32261 if (DECL_P (*node))
32263 if (TREE_CODE (*node) == TYPE_DECL)
32264 type = &TREE_TYPE (*node);
32269 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32270 || TREE_CODE (*type) == UNION_TYPE)))
32272 warning (OPT_Wattributes, "%qE attribute ignored", name);
32273 *no_add_attrs = true;
32276 else if ((is_attribute_p ("ms_struct", name)
32277 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32278 || ((is_attribute_p ("gcc_struct", name)
32279 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32281 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32283 *no_add_attrs = true;
32290 rs6000_ms_bitfield_layout_p (const_tree record_type)
32292 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32293 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32294 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32297 #ifdef USING_ELFOS_H
32299 /* A get_unnamed_section callback, used for switching to toc_section. */
32302 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32304 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32305 && TARGET_MINIMAL_TOC)
32307 if (!toc_initialized)
32309 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32310 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32311 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32312 fprintf (asm_out_file, "\t.tc ");
32313 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32314 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32315 fprintf (asm_out_file, "\n");
32317 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32318 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32319 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32320 fprintf (asm_out_file, " = .+32768\n");
32321 toc_initialized = 1;
32324 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32326 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32328 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32329 if (!toc_initialized)
32331 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32332 toc_initialized = 1;
32337 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32338 if (!toc_initialized)
32340 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32341 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32342 fprintf (asm_out_file, " = .+32768\n");
32343 toc_initialized = 1;
32348 /* Implement TARGET_ASM_INIT_SECTIONS. */
32351 rs6000_elf_asm_init_sections (void)
32354 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32357 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32358 SDATA2_SECTION_ASM_OP);
32361 /* Implement TARGET_SELECT_RTX_SECTION. */
32364 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32365 unsigned HOST_WIDE_INT align)
32367 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32368 return toc_section;
32370 return default_elf_select_rtx_section (mode, x, align);
32373 /* For a SYMBOL_REF, set generic flags and then perform some
32374 target-specific processing.
32376 When the AIX ABI is requested on a non-AIX system, replace the
32377 function name with the real name (with a leading .) rather than the
32378 function descriptor name. This saves a lot of overriding code to
32379 read the prefixes. */
32381 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32383 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32385 default_encode_section_info (decl, rtl, first);
32388 && TREE_CODE (decl) == FUNCTION_DECL
32390 && DEFAULT_ABI == ABI_AIX)
32392 rtx sym_ref = XEXP (rtl, 0);
32393 size_t len = strlen (XSTR (sym_ref, 0));
32394 char *str = XALLOCAVEC (char, len + 2);
32396 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32397 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32402 compare_section_name (const char *section, const char *templ)
32406 len = strlen (templ);
32407 return (strncmp (section, templ, len) == 0
32408 && (section[len] == 0 || section[len] == '.'));
32412 rs6000_elf_in_small_data_p (const_tree decl)
32414 if (rs6000_sdata == SDATA_NONE)
32417 /* We want to merge strings, so we never consider them small data. */
32418 if (TREE_CODE (decl) == STRING_CST)
32421 /* Functions are never in the small data area. */
32422 if (TREE_CODE (decl) == FUNCTION_DECL)
32425 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32427 const char *section = DECL_SECTION_NAME (decl);
32428 if (compare_section_name (section, ".sdata")
32429 || compare_section_name (section, ".sdata2")
32430 || compare_section_name (section, ".gnu.linkonce.s")
32431 || compare_section_name (section, ".sbss")
32432 || compare_section_name (section, ".sbss2")
32433 || compare_section_name (section, ".gnu.linkonce.sb")
32434 || strcmp (section, ".PPC.EMB.sdata0") == 0
32435 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32440 /* If we are told not to put readonly data in sdata, then don't. */
32441 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32442 && !rs6000_readonly_in_sdata)
32445 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32448 && size <= g_switch_value
32449 /* If it's not public, and we're not going to reference it there,
32450 there's no need to put it in the small data section. */
32451 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32458 #endif /* USING_ELFOS_H */
32460 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32463 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32465 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32468 /* Do not place thread-local symbols refs in the object blocks. */
32471 rs6000_use_blocks_for_decl_p (const_tree decl)
32473 return !DECL_THREAD_LOCAL_P (decl);
32476 /* Return a REG that occurs in ADDR with coefficient 1.
32477 ADDR can be effectively incremented by incrementing REG.
32479 r0 is special and we must not select it as an address
32480 register by this routine since our caller will try to
32481 increment the returned register via an "la" instruction. */
32484 find_addr_reg (rtx addr)
32486 while (GET_CODE (addr) == PLUS)
32488 if (GET_CODE (XEXP (addr, 0)) == REG
32489 && REGNO (XEXP (addr, 0)) != 0)
32490 addr = XEXP (addr, 0);
32491 else if (GET_CODE (XEXP (addr, 1)) == REG
32492 && REGNO (XEXP (addr, 1)) != 0)
32493 addr = XEXP (addr, 1);
32494 else if (CONSTANT_P (XEXP (addr, 0)))
32495 addr = XEXP (addr, 1);
32496 else if (CONSTANT_P (XEXP (addr, 1)))
32497 addr = XEXP (addr, 0);
32499 gcc_unreachable ();
32501 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
32506 rs6000_fatal_bad_address (rtx op)
32508 fatal_insn ("bad address", op);
32513 typedef struct branch_island_d {
32514 tree function_name;
32520 static vec<branch_island, va_gc> *branch_islands;
32522 /* Remember to generate a branch island for far calls to the given
32526 add_compiler_branch_island (tree label_name, tree function_name,
32529 branch_island bi = {function_name, label_name, line_number};
32530 vec_safe_push (branch_islands, bi);
32533 /* Generate far-jump branch islands for everything recorded in
32534 branch_islands. Invoked immediately after the last instruction of
32535 the epilogue has been emitted; the branch islands must be appended
32536 to, and contiguous with, the function body. Mach-O stubs are
32537 generated in machopic_output_stub(). */
32540 macho_branch_islands (void)
32544 while (!vec_safe_is_empty (branch_islands))
32546 branch_island *bi = &branch_islands->last ();
32547 const char *label = IDENTIFIER_POINTER (bi->label_name);
32548 const char *name = IDENTIFIER_POINTER (bi->function_name);
32549 char name_buf[512];
32550 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32551 if (name[0] == '*' || name[0] == '&')
32552 strcpy (name_buf, name+1);
32556 strcpy (name_buf+1, name);
32558 strcpy (tmp_buf, "\n");
32559 strcat (tmp_buf, label);
32560 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32561 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32562 dbxout_stabd (N_SLINE, bi->line_number);
32563 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32566 if (TARGET_LINK_STACK)
32569 get_ppc476_thunk_name (name);
32570 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32571 strcat (tmp_buf, name);
32572 strcat (tmp_buf, "\n");
32573 strcat (tmp_buf, label);
32574 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32578 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32579 strcat (tmp_buf, label);
32580 strcat (tmp_buf, "_pic\n");
32581 strcat (tmp_buf, label);
32582 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32585 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32586 strcat (tmp_buf, name_buf);
32587 strcat (tmp_buf, " - ");
32588 strcat (tmp_buf, label);
32589 strcat (tmp_buf, "_pic)\n");
32591 strcat (tmp_buf, "\tmtlr r0\n");
32593 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32594 strcat (tmp_buf, name_buf);
32595 strcat (tmp_buf, " - ");
32596 strcat (tmp_buf, label);
32597 strcat (tmp_buf, "_pic)\n");
32599 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32603 strcat (tmp_buf, ":\nlis r12,hi16(");
32604 strcat (tmp_buf, name_buf);
32605 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32606 strcat (tmp_buf, name_buf);
32607 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32609 output_asm_insn (tmp_buf, 0);
32610 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32611 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32612 dbxout_stabd (N_SLINE, bi->line_number);
32613 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32614 branch_islands->pop ();
32618 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32619 already there or not. */
32622 no_previous_def (tree function_name)
32627 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32628 if (function_name == bi->function_name)
32633 /* GET_PREV_LABEL gets the label name from the previous definition of
32637 get_prev_label (tree function_name)
32642 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32643 if (function_name == bi->function_name)
32644 return bi->label_name;
32648 /* INSN is either a function call or a millicode call. It may have an
32649 unconditional jump in its delay slot.
32651 CALL_DEST is the routine we are calling. */
32654 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
32655 int cookie_operand_number)
32657 static char buf[256];
32658 if (darwin_emit_branch_islands
32659 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
32660 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
32663 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
32665 if (no_previous_def (funname))
32667 rtx label_rtx = gen_label_rtx ();
32668 char *label_buf, temp_buf[256];
32669 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
32670 CODE_LABEL_NUMBER (label_rtx));
32671 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
32672 labelname = get_identifier (label_buf);
32673 add_compiler_branch_island (labelname, funname, insn_line (insn));
32676 labelname = get_prev_label (funname);
32678 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
32679 instruction will reach 'foo', otherwise link as 'bl L42'".
32680 "L42" should be a 'branch island', that will do a far jump to
32681 'foo'. Branch islands are generated in
32682 macho_branch_islands(). */
32683 sprintf (buf, "jbsr %%z%d,%.246s",
32684 dest_operand_number, IDENTIFIER_POINTER (labelname));
32687 sprintf (buf, "bl %%z%d", dest_operand_number);
32691 /* Generate PIC and indirect symbol stubs. */
32694 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32696 unsigned int length;
32697 char *symbol_name, *lazy_ptr_name;
32698 char *local_label_0;
32699 static int label = 0;
32701 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32702 symb = (*targetm.strip_name_encoding) (symb);
32705 length = strlen (symb);
32706 symbol_name = XALLOCAVEC (char, length + 32);
32707 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
32709 lazy_ptr_name = XALLOCAVEC (char, length + 32);
32710 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
32713 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
32715 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
32719 fprintf (file, "\t.align 5\n");
32721 fprintf (file, "%s:\n", stub);
32722 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32725 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
32726 sprintf (local_label_0, "\"L%011d$spb\"", label);
32728 fprintf (file, "\tmflr r0\n");
32729 if (TARGET_LINK_STACK)
32732 get_ppc476_thunk_name (name);
32733 fprintf (file, "\tbl %s\n", name);
32734 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32738 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
32739 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32741 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
32742 lazy_ptr_name, local_label_0);
32743 fprintf (file, "\tmtlr r0\n");
32744 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
32745 (TARGET_64BIT ? "ldu" : "lwzu"),
32746 lazy_ptr_name, local_label_0);
32747 fprintf (file, "\tmtctr r12\n");
32748 fprintf (file, "\tbctr\n");
32752 fprintf (file, "\t.align 4\n");
32754 fprintf (file, "%s:\n", stub);
32755 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32757 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
32758 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
32759 (TARGET_64BIT ? "ldu" : "lwzu"),
32761 fprintf (file, "\tmtctr r12\n");
32762 fprintf (file, "\tbctr\n");
32765 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
32766 fprintf (file, "%s:\n", lazy_ptr_name);
32767 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32768 fprintf (file, "%sdyld_stub_binding_helper\n",
32769 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
32772 /* Legitimize PIC addresses. If the address is already
32773 position-independent, we return ORIG. Newly generated
32774 position-independent addresses go into a reg. This is REG if non
32775 zero, otherwise we allocate register(s) as necessary. */
32777 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
32780 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
32785 if (reg == NULL && !reload_completed)
32786 reg = gen_reg_rtx (Pmode);
32788 if (GET_CODE (orig) == CONST)
32792 if (GET_CODE (XEXP (orig, 0)) == PLUS
32793 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
32796 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
32798 /* Use a different reg for the intermediate value, as
32799 it will be marked UNCHANGING. */
32800 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
32801 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
32804 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
32807 if (GET_CODE (offset) == CONST_INT)
32809 if (SMALL_INT (offset))
32810 return plus_constant (Pmode, base, INTVAL (offset));
32811 else if (!reload_completed)
32812 offset = force_reg (Pmode, offset);
32815 rtx mem = force_const_mem (Pmode, orig);
32816 return machopic_legitimize_pic_address (mem, Pmode, reg);
32819 return gen_rtx_PLUS (Pmode, base, offset);
32822 /* Fall back on generic machopic code. */
32823 return machopic_legitimize_pic_address (orig, mode, reg);
32826 /* Output a .machine directive for the Darwin assembler, and call
32827 the generic start_file routine. */
32830 rs6000_darwin_file_start (void)
32832 static const struct
32836 HOST_WIDE_INT if_set;
32838 { "ppc64", "ppc64", MASK_64BIT },
32839 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
32840 { "power4", "ppc970", 0 },
32841 { "G5", "ppc970", 0 },
32842 { "7450", "ppc7450", 0 },
32843 { "7400", "ppc7400", MASK_ALTIVEC },
32844 { "G4", "ppc7400", 0 },
32845 { "750", "ppc750", 0 },
32846 { "740", "ppc750", 0 },
32847 { "G3", "ppc750", 0 },
32848 { "604e", "ppc604e", 0 },
32849 { "604", "ppc604", 0 },
32850 { "603e", "ppc603", 0 },
32851 { "603", "ppc603", 0 },
32852 { "601", "ppc601", 0 },
32853 { NULL, "ppc", 0 } };
32854 const char *cpu_id = "";
32857 rs6000_file_start ();
32858 darwin_file_start ();
32860 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
32862 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
32863 cpu_id = rs6000_default_cpu;
32865 if (global_options_set.x_rs6000_cpu_index)
32866 cpu_id = processor_target_table[rs6000_cpu_index].name;
32868 /* Look through the mapping array. Pick the first name that either
32869 matches the argument, has a bit set in IF_SET that is also set
32870 in the target flags, or has a NULL name. */
32873 while (mapping[i].arg != NULL
32874 && strcmp (mapping[i].arg, cpu_id) != 0
32875 && (mapping[i].if_set & rs6000_isa_flags) == 0)
32878 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
32881 #endif /* TARGET_MACHO */
32885 rs6000_elf_reloc_rw_mask (void)
32889 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32895 /* Record an element in the table of global constructors. SYMBOL is
32896 a SYMBOL_REF of the function to be called; PRIORITY is a number
32897 between 0 and MAX_INIT_PRIORITY.
32899 This differs from default_named_section_asm_out_constructor in
32900 that we have special handling for -mrelocatable. */
32902 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
32904 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
32906 const char *section = ".ctors";
32909 if (priority != DEFAULT_INIT_PRIORITY)
32911 sprintf (buf, ".ctors.%.5u",
32912 /* Invert the numbering so the linker puts us in the proper
32913 order; constructors are run from right to left, and the
32914 linker sorts in increasing order. */
32915 MAX_INIT_PRIORITY - priority);
32919 switch_to_section (get_section (section, SECTION_WRITE, NULL));
32920 assemble_align (POINTER_SIZE);
32922 if (DEFAULT_ABI == ABI_V4
32923 && (TARGET_RELOCATABLE || flag_pic > 1))
32925 fputs ("\t.long (", asm_out_file);
32926 output_addr_const (asm_out_file, symbol);
32927 fputs (")@fixup\n", asm_out_file);
32930 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
32933 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
32935 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
32937 const char *section = ".dtors";
32940 if (priority != DEFAULT_INIT_PRIORITY)
32942 sprintf (buf, ".dtors.%.5u",
32943 /* Invert the numbering so the linker puts us in the proper
32944 order; constructors are run from right to left, and the
32945 linker sorts in increasing order. */
32946 MAX_INIT_PRIORITY - priority);
32950 switch_to_section (get_section (section, SECTION_WRITE, NULL));
32951 assemble_align (POINTER_SIZE);
32953 if (DEFAULT_ABI == ABI_V4
32954 && (TARGET_RELOCATABLE || flag_pic > 1))
32956 fputs ("\t.long (", asm_out_file);
32957 output_addr_const (asm_out_file, symbol);
32958 fputs (")@fixup\n", asm_out_file);
32961 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
32965 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
32967 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
32969 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
32970 ASM_OUTPUT_LABEL (file, name);
32971 fputs (DOUBLE_INT_ASM_OP, file);
32972 rs6000_output_function_entry (file, name);
32973 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
32976 fputs ("\t.size\t", file);
32977 assemble_name (file, name);
32978 fputs (",24\n\t.type\t.", file);
32979 assemble_name (file, name);
32980 fputs (",@function\n", file);
32981 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
32983 fputs ("\t.globl\t.", file);
32984 assemble_name (file, name);
32989 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
32990 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
32991 rs6000_output_function_entry (file, name);
32992 fputs (":\n", file);
32997 if (DEFAULT_ABI == ABI_V4
32998 && (TARGET_RELOCATABLE || flag_pic > 1)
32999 && !TARGET_SECURE_PLT
33000 && (!constant_pool_empty_p () || crtl->profile)
33001 && (uses_toc = uses_TOC ()))
33006 switch_to_other_text_partition ();
33007 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33009 fprintf (file, "\t.long ");
33010 assemble_name (file, toc_label_name);
33013 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33014 assemble_name (file, buf);
33017 switch_to_other_text_partition ();
33020 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33021 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33023 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33027 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33029 fprintf (file, "\t.quad .TOC.-");
33030 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33031 assemble_name (file, buf);
33035 if (DEFAULT_ABI == ABI_AIX)
33037 const char *desc_name, *orig_name;
33039 orig_name = (*targetm.strip_name_encoding) (name);
33040 desc_name = orig_name;
33041 while (*desc_name == '.')
33044 if (TREE_PUBLIC (decl))
33045 fprintf (file, "\t.globl %s\n", desc_name);
33047 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33048 fprintf (file, "%s:\n", desc_name);
33049 fprintf (file, "\t.long %s\n", orig_name);
33050 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33051 fputs ("\t.long 0\n", file);
33052 fprintf (file, "\t.previous\n");
33054 ASM_OUTPUT_LABEL (file, name);
33057 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33059 rs6000_elf_file_end (void)
33061 #ifdef HAVE_AS_GNU_ATTRIBUTE
33062 /* ??? The value emitted depends on options active at file end.
33063 Assume anyone using #pragma or attributes that might change
33064 options knows what they are doing. */
33065 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33066 && rs6000_passes_float)
33070 if (TARGET_HARD_FLOAT)
33074 if (rs6000_passes_long_double)
33076 if (!TARGET_LONG_DOUBLE_128)
33078 else if (TARGET_IEEEQUAD)
33083 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33085 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33087 if (rs6000_passes_vector)
33088 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33089 (TARGET_ALTIVEC_ABI ? 2 : 1));
33090 if (rs6000_returns_struct)
33091 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33092 aix_struct_return ? 2 : 1);
33095 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33096 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33097 file_end_indicate_exec_stack ();
33100 if (flag_split_stack)
33101 file_end_indicate_split_stack ();
33105 /* We have expanded a CPU builtin, so we need to emit a reference to
33106 the special symbol that LIBC uses to declare it supports the
33107 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33108 switch_to_section (data_section);
33109 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33110 fprintf (asm_out_file, "\t%s %s\n",
33111 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33118 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33119 #define HAVE_XCOFF_DWARF_EXTRAS 0
33122 static enum unwind_info_type
33123 rs6000_xcoff_debug_unwind_info (void)
33129 rs6000_xcoff_asm_output_anchor (rtx symbol)
33133 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33134 SYMBOL_REF_BLOCK_OFFSET (symbol));
33135 fprintf (asm_out_file, "%s", SET_ASM_OP);
33136 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33137 fprintf (asm_out_file, ",");
33138 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33139 fprintf (asm_out_file, "\n");
33143 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33145 fputs (GLOBAL_ASM_OP, stream);
33146 RS6000_OUTPUT_BASENAME (stream, name);
33147 putc ('\n', stream);
33150 /* A get_unnamed_decl callback, used for read-only sections. PTR
33151 points to the section string variable. */
33154 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33156 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33157 *(const char *const *) directive,
33158 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33161 /* Likewise for read-write sections. */
33164 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33166 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33167 *(const char *const *) directive,
33168 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33172 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33174 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33175 *(const char *const *) directive,
33176 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33179 /* A get_unnamed_section callback, used for switching to toc_section. */
33182 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33184 if (TARGET_MINIMAL_TOC)
33186 /* toc_section is always selected at least once from
33187 rs6000_xcoff_file_start, so this is guaranteed to
33188 always be defined once and only once in each file. */
33189 if (!toc_initialized)
33191 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33192 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33193 toc_initialized = 1;
33195 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33196 (TARGET_32BIT ? "" : ",3"));
33199 fputs ("\t.toc\n", asm_out_file);
33202 /* Implement TARGET_ASM_INIT_SECTIONS. */
33205 rs6000_xcoff_asm_init_sections (void)
33207 read_only_data_section
33208 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33209 &xcoff_read_only_section_name);
33211 private_data_section
33212 = get_unnamed_section (SECTION_WRITE,
33213 rs6000_xcoff_output_readwrite_section_asm_op,
33214 &xcoff_private_data_section_name);
33217 = get_unnamed_section (SECTION_TLS,
33218 rs6000_xcoff_output_tls_section_asm_op,
33219 &xcoff_tls_data_section_name);
33221 tls_private_data_section
33222 = get_unnamed_section (SECTION_TLS,
33223 rs6000_xcoff_output_tls_section_asm_op,
33224 &xcoff_private_data_section_name);
33226 read_only_private_data_section
33227 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33228 &xcoff_private_data_section_name);
33231 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33233 readonly_data_section = read_only_data_section;
33237 rs6000_xcoff_reloc_rw_mask (void)
33243 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33244 tree decl ATTRIBUTE_UNUSED)
33247 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33249 if (flags & SECTION_EXCLUDE)
33251 else if (flags & SECTION_DEBUG)
33253 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33256 else if (flags & SECTION_CODE)
33258 else if (flags & SECTION_TLS)
33260 else if (flags & SECTION_WRITE)
33265 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33266 (flags & SECTION_CODE) ? "." : "",
33267 name, suffix[smclass], flags & SECTION_ENTSIZE);
33270 #define IN_NAMED_SECTION(DECL) \
33271 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33272 && DECL_SECTION_NAME (DECL) != NULL)
33275 rs6000_xcoff_select_section (tree decl, int reloc,
33276 unsigned HOST_WIDE_INT align)
33278 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33280 if (align > BIGGEST_ALIGNMENT)
33282 resolve_unique_section (decl, reloc, true);
33283 if (IN_NAMED_SECTION (decl))
33284 return get_named_section (decl, NULL, reloc);
33287 if (decl_readonly_section (decl, reloc))
33289 if (TREE_PUBLIC (decl))
33290 return read_only_data_section;
33292 return read_only_private_data_section;
33297 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33299 if (TREE_PUBLIC (decl))
33300 return tls_data_section;
33301 else if (bss_initializer_p (decl))
33303 /* Convert to COMMON to emit in BSS. */
33304 DECL_COMMON (decl) = 1;
33305 return tls_comm_section;
33308 return tls_private_data_section;
33312 if (TREE_PUBLIC (decl))
33313 return data_section;
33315 return private_data_section;
33320 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33324 /* Use select_section for private data and uninitialized data with
33325 alignment <= BIGGEST_ALIGNMENT. */
33326 if (!TREE_PUBLIC (decl)
33327 || DECL_COMMON (decl)
33328 || (DECL_INITIAL (decl) == NULL_TREE
33329 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33330 || DECL_INITIAL (decl) == error_mark_node
33331 || (flag_zero_initialized_in_bss
33332 && initializer_zerop (DECL_INITIAL (decl))))
33335 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33336 name = (*targetm.strip_name_encoding) (name);
33337 set_decl_section_name (decl, name);
33340 /* Select section for constant in constant pool.
33342 On RS/6000, all constants are in the private read-only data area.
33343 However, if this is being placed in the TOC it must be output as a
33347 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33348 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33350 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33351 return toc_section;
33353 return read_only_private_data_section;
33356 /* Remove any trailing [DS] or the like from the symbol name. */
33358 static const char *
33359 rs6000_xcoff_strip_name_encoding (const char *name)
33364 len = strlen (name);
33365 if (name[len - 1] == ']')
33366 return ggc_alloc_string (name, len - 4);
33371 /* Section attributes. AIX is always PIC. */
33373 static unsigned int
33374 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33376 unsigned int align;
33377 unsigned int flags = default_section_type_flags (decl, name, reloc);
33379 /* Align to at least UNIT size. */
33380 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33381 align = MIN_UNITS_PER_WORD;
33383 /* Increase alignment of large objects if not already stricter. */
33384 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33385 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33386 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33388 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33391 /* Output at beginning of assembler file.
33393 Initialize the section names for the RS/6000 at this point.
33395 Specify filename, including full path, to assembler.
33397 We want to go into the TOC section so at least one .toc will be emitted.
33398 Also, in order to output proper .bs/.es pairs, we need at least one static
33399 [RW] section emitted.
33401 Finally, declare mcount when profiling to make the assembler happy. */
33404 rs6000_xcoff_file_start (void)
33406 rs6000_gen_section_name (&xcoff_bss_section_name,
33407 main_input_filename, ".bss_");
33408 rs6000_gen_section_name (&xcoff_private_data_section_name,
33409 main_input_filename, ".rw_");
33410 rs6000_gen_section_name (&xcoff_read_only_section_name,
33411 main_input_filename, ".ro_");
33412 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33413 main_input_filename, ".tls_");
33414 rs6000_gen_section_name (&xcoff_tbss_section_name,
33415 main_input_filename, ".tbss_[UL]");
33417 fputs ("\t.file\t", asm_out_file);
33418 output_quoted_string (asm_out_file, main_input_filename);
33419 fputc ('\n', asm_out_file);
33420 if (write_symbols != NO_DEBUG)
33421 switch_to_section (private_data_section);
33422 switch_to_section (toc_section);
33423 switch_to_section (text_section);
33425 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33426 rs6000_file_start ();
33429 /* Output at end of assembler file.
33430 On the RS/6000, referencing data should automatically pull in text. */
33433 rs6000_xcoff_file_end (void)
33435 switch_to_section (text_section);
33436 fputs ("_section_.text:\n", asm_out_file);
33437 switch_to_section (data_section);
33438 fputs (TARGET_32BIT
33439 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33443 struct declare_alias_data
33446 bool function_descriptor;
33449 /* Declare alias N. A helper function for for_node_and_aliases. */
33452 rs6000_declare_alias (struct symtab_node *n, void *d)
33454 struct declare_alias_data *data = (struct declare_alias_data *)d;
33455 /* Main symbol is output specially, because varasm machinery does part of
33456 the job for us - we do not need to declare .globl/lglobs and such. */
33457 if (!n->alias || n->weakref)
33460 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33463 /* Prevent assemble_alias from trying to use .set pseudo operation
33464 that does not behave as expected by the middle-end. */
33465 TREE_ASM_WRITTEN (n->decl) = true;
33467 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33468 char *buffer = (char *) alloca (strlen (name) + 2);
33470 int dollar_inside = 0;
33472 strcpy (buffer, name);
33473 p = strchr (buffer, '$');
33477 p = strchr (p + 1, '$');
33479 if (TREE_PUBLIC (n->decl))
33481 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33483 if (dollar_inside) {
33484 if (data->function_descriptor)
33485 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33486 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33488 if (data->function_descriptor)
33490 fputs ("\t.globl .", data->file);
33491 RS6000_OUTPUT_BASENAME (data->file, buffer);
33492 putc ('\n', data->file);
33494 fputs ("\t.globl ", data->file);
33495 RS6000_OUTPUT_BASENAME (data->file, buffer);
33496 putc ('\n', data->file);
33498 #ifdef ASM_WEAKEN_DECL
33499 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33500 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33507 if (data->function_descriptor)
33508 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33509 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33511 if (data->function_descriptor)
33513 fputs ("\t.lglobl .", data->file);
33514 RS6000_OUTPUT_BASENAME (data->file, buffer);
33515 putc ('\n', data->file);
33517 fputs ("\t.lglobl ", data->file);
33518 RS6000_OUTPUT_BASENAME (data->file, buffer);
33519 putc ('\n', data->file);
33521 if (data->function_descriptor)
33522 fputs (".", data->file);
33523 RS6000_OUTPUT_BASENAME (data->file, buffer);
33524 fputs (":\n", data->file);
33529 #ifdef HAVE_GAS_HIDDEN
33530 /* Helper function to calculate visibility of a DECL
33531 and return the value as a const string. */
33533 static const char *
33534 rs6000_xcoff_visibility (tree decl)
33536 static const char * const visibility_types[] = {
33537 "", ",protected", ",hidden", ",internal"
33540 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33541 return visibility_types[vis];
33546 /* This macro produces the initial definition of a function name.
33547 On the RS/6000, we need to place an extra '.' in the function name and
33548 output the function descriptor.
33549 Dollar signs are converted to underscores.
33551 The csect for the function will have already been created when
33552 text_section was selected. We do have to go back to that csect, however.
33554 The third and fourth parameters to the .function pseudo-op (16 and 044)
33555 are placeholders which no longer have any use.
33557 Because AIX assembler's .set command has unexpected semantics, we output
33558 all aliases as alternative labels in front of the definition. */
33561 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33563 char *buffer = (char *) alloca (strlen (name) + 1);
33565 int dollar_inside = 0;
33566 struct declare_alias_data data = {file, false};
33568 strcpy (buffer, name);
33569 p = strchr (buffer, '$');
33573 p = strchr (p + 1, '$');
33575 if (TREE_PUBLIC (decl))
33577 if (!RS6000_WEAK || !DECL_WEAK (decl))
33579 if (dollar_inside) {
33580 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33581 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33583 fputs ("\t.globl .", file);
33584 RS6000_OUTPUT_BASENAME (file, buffer);
33585 #ifdef HAVE_GAS_HIDDEN
33586 fputs (rs6000_xcoff_visibility (decl), file);
33593 if (dollar_inside) {
33594 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33595 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33597 fputs ("\t.lglobl .", file);
33598 RS6000_OUTPUT_BASENAME (file, buffer);
33601 fputs ("\t.csect ", file);
33602 RS6000_OUTPUT_BASENAME (file, buffer);
33603 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33604 RS6000_OUTPUT_BASENAME (file, buffer);
33605 fputs (":\n", file);
33606 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33608 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33609 RS6000_OUTPUT_BASENAME (file, buffer);
33610 fputs (", TOC[tc0], 0\n", file);
33612 switch_to_section (function_section (decl));
33614 RS6000_OUTPUT_BASENAME (file, buffer);
33615 fputs (":\n", file);
33616 data.function_descriptor = true;
33617 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33619 if (!DECL_IGNORED_P (decl))
33621 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33622 xcoffout_declare_function (file, decl, buffer);
33623 else if (write_symbols == DWARF2_DEBUG)
33625 name = (*targetm.strip_name_encoding) (name);
33626 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33633 /* Output assembly language to globalize a symbol from a DECL,
33634 possibly with visibility. */
33637 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33639 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33640 fputs (GLOBAL_ASM_OP, stream);
33641 RS6000_OUTPUT_BASENAME (stream, name);
33642 #ifdef HAVE_GAS_HIDDEN
33643 fputs (rs6000_xcoff_visibility (decl), stream);
33645 putc ('\n', stream);
33648 /* Output assembly language to define a symbol as COMMON from a DECL,
33649 possibly with visibility. */
33652 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33653 tree decl ATTRIBUTE_UNUSED,
33655 unsigned HOST_WIDE_INT size,
33656 unsigned HOST_WIDE_INT align)
33658 unsigned HOST_WIDE_INT align2 = 2;
33661 align2 = floor_log2 (align / BITS_PER_UNIT);
33665 fputs (COMMON_ASM_OP, stream);
33666 RS6000_OUTPUT_BASENAME (stream, name);
33669 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33672 #ifdef HAVE_GAS_HIDDEN
33674 fputs (rs6000_xcoff_visibility (decl), stream);
33676 putc ('\n', stream);
33679 /* This macro produces the initial definition of a object (variable) name.
33680 Because AIX assembler's .set command has unexpected semantics, we output
33681 all aliases as alternative labels in front of the definition. */
33684 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33686 struct declare_alias_data data = {file, false};
33687 RS6000_OUTPUT_BASENAME (file, name);
33688 fputs (":\n", file);
33689 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33693 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33696 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33698 fputs (integer_asm_op (size, FALSE), file);
33699 assemble_name (file, label);
33700 fputs ("-$", file);
33703 /* Output a symbol offset relative to the dbase for the current object.
33704 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
33707 __gcc_unwind_dbase is embedded in all executables/libraries through
33708 libgcc/config/rs6000/crtdbase.S. */
33711 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
33713 fputs (integer_asm_op (size, FALSE), file);
33714 assemble_name (file, label);
33715 fputs("-__gcc_unwind_dbase", file);
33720 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
33724 const char *symname;
33726 default_encode_section_info (decl, rtl, first);
33728 /* Careful not to prod global register variables. */
33731 symbol = XEXP (rtl, 0);
33732 if (GET_CODE (symbol) != SYMBOL_REF)
33735 flags = SYMBOL_REF_FLAGS (symbol);
33737 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33738 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
33740 SYMBOL_REF_FLAGS (symbol) = flags;
33742 /* Append mapping class to extern decls. */
33743 symname = XSTR (symbol, 0);
33744 if (decl /* sync condition with assemble_external () */
33745 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
33746 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
33747 || TREE_CODE (decl) == FUNCTION_DECL)
33748 && symname[strlen (symname) - 1] != ']')
33750 char *newname = (char *) alloca (strlen (symname) + 5);
33751 strcpy (newname, symname);
33752 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
33753 ? "[DS]" : "[UA]"));
33754 XSTR (symbol, 0) = ggc_strdup (newname);
33757 #endif /* HAVE_AS_TLS */
33758 #endif /* TARGET_XCOFF */
33761 rs6000_asm_weaken_decl (FILE *stream, tree decl,
33762 const char *name, const char *val)
33764 fputs ("\t.weak\t", stream);
33765 RS6000_OUTPUT_BASENAME (stream, name);
33766 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33767 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33770 fputs ("[DS]", stream);
33771 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33773 fputs (rs6000_xcoff_visibility (decl), stream);
33775 fputs ("\n\t.weak\t.", stream);
33776 RS6000_OUTPUT_BASENAME (stream, name);
33778 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33780 fputs (rs6000_xcoff_visibility (decl), stream);
33782 fputc ('\n', stream);
33785 #ifdef ASM_OUTPUT_DEF
33786 ASM_OUTPUT_DEF (stream, name, val);
33788 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33789 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33791 fputs ("\t.set\t.", stream);
33792 RS6000_OUTPUT_BASENAME (stream, name);
33793 fputs (",.", stream);
33794 RS6000_OUTPUT_BASENAME (stream, val);
33795 fputc ('\n', stream);
33801 /* Return true if INSN should not be copied. */
33804 rs6000_cannot_copy_insn_p (rtx_insn *insn)
33806 return recog_memoized (insn) >= 0
33807 && get_attr_cannot_copy (insn);
33810 /* Compute a (partial) cost for rtx X. Return true if the complete
33811 cost has been computed, and false if subexpressions should be
33812 scanned. In either case, *TOTAL contains the cost result. */
33815 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
33816 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
33818 int code = GET_CODE (x);
33822 /* On the RS/6000, if it is valid in the insn, it is free. */
33824 if (((outer_code == SET
33825 || outer_code == PLUS
33826 || outer_code == MINUS)
33827 && (satisfies_constraint_I (x)
33828 || satisfies_constraint_L (x)))
33829 || (outer_code == AND
33830 && (satisfies_constraint_K (x)
33832 ? satisfies_constraint_L (x)
33833 : satisfies_constraint_J (x))))
33834 || ((outer_code == IOR || outer_code == XOR)
33835 && (satisfies_constraint_K (x)
33837 ? satisfies_constraint_L (x)
33838 : satisfies_constraint_J (x))))
33839 || outer_code == ASHIFT
33840 || outer_code == ASHIFTRT
33841 || outer_code == LSHIFTRT
33842 || outer_code == ROTATE
33843 || outer_code == ROTATERT
33844 || outer_code == ZERO_EXTRACT
33845 || (outer_code == MULT
33846 && satisfies_constraint_I (x))
33847 || ((outer_code == DIV || outer_code == UDIV
33848 || outer_code == MOD || outer_code == UMOD)
33849 && exact_log2 (INTVAL (x)) >= 0)
33850 || (outer_code == COMPARE
33851 && (satisfies_constraint_I (x)
33852 || satisfies_constraint_K (x)))
33853 || ((outer_code == EQ || outer_code == NE)
33854 && (satisfies_constraint_I (x)
33855 || satisfies_constraint_K (x)
33857 ? satisfies_constraint_L (x)
33858 : satisfies_constraint_J (x))))
33859 || (outer_code == GTU
33860 && satisfies_constraint_I (x))
33861 || (outer_code == LTU
33862 && satisfies_constraint_P (x)))
33867 else if ((outer_code == PLUS
33868 && reg_or_add_cint_operand (x, VOIDmode))
33869 || (outer_code == MINUS
33870 && reg_or_sub_cint_operand (x, VOIDmode))
33871 || ((outer_code == SET
33872 || outer_code == IOR
33873 || outer_code == XOR)
33875 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
33877 *total = COSTS_N_INSNS (1);
33883 case CONST_WIDE_INT:
33887 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
33891 /* When optimizing for size, MEM should be slightly more expensive
33892 than generating address, e.g., (plus (reg) (const)).
33893 L1 cache latency is about two instructions. */
33894 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
33895 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
33896 *total += COSTS_N_INSNS (100);
33905 if (FLOAT_MODE_P (mode))
33906 *total = rs6000_cost->fp;
33908 *total = COSTS_N_INSNS (1);
33912 if (GET_CODE (XEXP (x, 1)) == CONST_INT
33913 && satisfies_constraint_I (XEXP (x, 1)))
33915 if (INTVAL (XEXP (x, 1)) >= -256
33916 && INTVAL (XEXP (x, 1)) <= 255)
33917 *total = rs6000_cost->mulsi_const9;
33919 *total = rs6000_cost->mulsi_const;
33921 else if (mode == SFmode)
33922 *total = rs6000_cost->fp;
33923 else if (FLOAT_MODE_P (mode))
33924 *total = rs6000_cost->dmul;
33925 else if (mode == DImode)
33926 *total = rs6000_cost->muldi;
33928 *total = rs6000_cost->mulsi;
33932 if (mode == SFmode)
33933 *total = rs6000_cost->fp;
33935 *total = rs6000_cost->dmul;
33940 if (FLOAT_MODE_P (mode))
33942 *total = mode == DFmode ? rs6000_cost->ddiv
33943 : rs6000_cost->sdiv;
33950 if (GET_CODE (XEXP (x, 1)) == CONST_INT
33951 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
33953 if (code == DIV || code == MOD)
33955 *total = COSTS_N_INSNS (2);
33958 *total = COSTS_N_INSNS (1);
33962 if (GET_MODE (XEXP (x, 1)) == DImode)
33963 *total = rs6000_cost->divdi;
33965 *total = rs6000_cost->divsi;
33967 /* Add in shift and subtract for MOD unless we have a mod instruction. */
33968 if (!TARGET_MODULO && (code == MOD || code == UMOD))
33969 *total += COSTS_N_INSNS (2);
33973 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
33977 *total = COSTS_N_INSNS (4);
33981 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
33985 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
33989 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
33992 *total = COSTS_N_INSNS (1);
33996 if (CONST_INT_P (XEXP (x, 1)))
33998 rtx left = XEXP (x, 0);
33999 rtx_code left_code = GET_CODE (left);
34001 /* rotate-and-mask: 1 insn. */
34002 if ((left_code == ROTATE
34003 || left_code == ASHIFT
34004 || left_code == LSHIFTRT)
34005 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34007 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34008 if (!CONST_INT_P (XEXP (left, 1)))
34009 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34010 *total += COSTS_N_INSNS (1);
34014 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34015 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34016 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34017 || (val & 0xffff) == val
34018 || (val & 0xffff0000) == val
34019 || ((val & 0xffff) == 0 && mode == SImode))
34021 *total = rtx_cost (left, mode, AND, 0, speed);
34022 *total += COSTS_N_INSNS (1);
34027 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34029 *total = rtx_cost (left, mode, AND, 0, speed);
34030 *total += COSTS_N_INSNS (2);
34035 *total = COSTS_N_INSNS (1);
34040 *total = COSTS_N_INSNS (1);
34046 *total = COSTS_N_INSNS (1);
34050 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34051 the sign extend and shift separately within the insn. */
34052 if (TARGET_EXTSWSLI && mode == DImode
34053 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34054 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34065 /* Handle mul_highpart. */
34066 if (outer_code == TRUNCATE
34067 && GET_CODE (XEXP (x, 0)) == MULT)
34069 if (mode == DImode)
34070 *total = rs6000_cost->muldi;
34072 *total = rs6000_cost->mulsi;
34075 else if (outer_code == AND)
34078 *total = COSTS_N_INSNS (1);
34083 if (GET_CODE (XEXP (x, 0)) == MEM)
34086 *total = COSTS_N_INSNS (1);
34092 if (!FLOAT_MODE_P (mode))
34094 *total = COSTS_N_INSNS (1);
34100 case UNSIGNED_FLOAT:
34103 case FLOAT_TRUNCATE:
34104 *total = rs6000_cost->fp;
34108 if (mode == DFmode)
34109 *total = rs6000_cost->sfdf_convert;
34111 *total = rs6000_cost->fp;
34115 switch (XINT (x, 1))
34118 *total = rs6000_cost->fp;
34130 *total = COSTS_N_INSNS (1);
34133 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34135 *total = rs6000_cost->fp;
34144 /* Carry bit requires mode == Pmode.
34145 NEG or PLUS already counted so only add one. */
34147 && (outer_code == NEG || outer_code == PLUS))
34149 *total = COSTS_N_INSNS (1);
34157 if (outer_code == SET)
34159 if (XEXP (x, 1) == const0_rtx)
34161 *total = COSTS_N_INSNS (2);
34166 *total = COSTS_N_INSNS (3);
34171 if (outer_code == COMPARE)
34185 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34188 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34189 int opno, int *total, bool speed)
34191 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34194 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34195 "opno = %d, total = %d, speed = %s, x:\n",
34196 ret ? "complete" : "scan inner",
34197 GET_MODE_NAME (mode),
34198 GET_RTX_NAME (outer_code),
34201 speed ? "true" : "false");
34209 rs6000_insn_cost (rtx_insn *insn, bool speed)
34211 if (recog_memoized (insn) < 0)
34215 return get_attr_length (insn);
34217 int cost = get_attr_cost (insn);
34221 int n = get_attr_length (insn) / 4;
34222 enum attr_type type = get_attr_type (insn);
34229 cost = COSTS_N_INSNS (n + 1);
34233 switch (get_attr_size (insn))
34236 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34239 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34242 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34245 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34248 gcc_unreachable ();
34252 switch (get_attr_size (insn))
34255 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34258 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34261 gcc_unreachable ();
34266 cost = n * rs6000_cost->fp;
34269 cost = n * rs6000_cost->dmul;
34272 cost = n * rs6000_cost->sdiv;
34275 cost = n * rs6000_cost->ddiv;
34282 cost = COSTS_N_INSNS (n + 2);
34286 cost = COSTS_N_INSNS (n);
34292 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34295 rs6000_debug_address_cost (rtx x, machine_mode mode,
34296 addr_space_t as, bool speed)
34298 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34300 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34301 ret, speed ? "true" : "false");
34308 /* A C expression returning the cost of moving data from a register of class
34309 CLASS1 to one of CLASS2. */
34312 rs6000_register_move_cost (machine_mode mode,
34313 reg_class_t from, reg_class_t to)
34317 if (TARGET_DEBUG_COST)
34320 /* Moves from/to GENERAL_REGS. */
34321 if (reg_classes_intersect_p (to, GENERAL_REGS)
34322 || reg_classes_intersect_p (from, GENERAL_REGS))
34324 reg_class_t rclass = from;
34326 if (! reg_classes_intersect_p (to, GENERAL_REGS))
34329 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34330 ret = (rs6000_memory_move_cost (mode, rclass, false)
34331 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34333 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34335 else if (rclass == CR_REGS)
34338 /* For those processors that have slow LR/CTR moves, make them more
34339 expensive than memory in order to bias spills to memory .*/
34340 else if ((rs6000_tune == PROCESSOR_POWER6
34341 || rs6000_tune == PROCESSOR_POWER7
34342 || rs6000_tune == PROCESSOR_POWER8
34343 || rs6000_tune == PROCESSOR_POWER9)
34344 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
34345 ret = 6 * hard_regno_nregs (0, mode);
34348 /* A move will cost one instruction per GPR moved. */
34349 ret = 2 * hard_regno_nregs (0, mode);
34352 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34353 else if (VECTOR_MEM_VSX_P (mode)
34354 && reg_classes_intersect_p (to, VSX_REGS)
34355 && reg_classes_intersect_p (from, VSX_REGS))
34356 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
34358 /* Moving between two similar registers is just one instruction. */
34359 else if (reg_classes_intersect_p (to, from))
34360 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
34362 /* Everything else has to go through GENERAL_REGS. */
34364 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34365 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34367 if (TARGET_DEBUG_COST)
34369 if (dbg_cost_ctrl == 1)
34371 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34372 ret, GET_MODE_NAME (mode), reg_class_names[from],
34373 reg_class_names[to]);
34380 /* A C expressions returning the cost of moving data of MODE from a register to
34384 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34385 bool in ATTRIBUTE_UNUSED)
34389 if (TARGET_DEBUG_COST)
34392 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34393 ret = 4 * hard_regno_nregs (0, mode);
34394 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34395 || reg_classes_intersect_p (rclass, VSX_REGS)))
34396 ret = 4 * hard_regno_nregs (32, mode);
34397 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34398 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34400 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34402 if (TARGET_DEBUG_COST)
34404 if (dbg_cost_ctrl == 1)
34406 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34407 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34414 /* Returns a code for a target-specific builtin that implements
34415 reciprocal of the function, or NULL_TREE if not available. */
34418 rs6000_builtin_reciprocal (tree fndecl)
34420 switch (DECL_FUNCTION_CODE (fndecl))
34422 case VSX_BUILTIN_XVSQRTDP:
34423 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34426 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34428 case VSX_BUILTIN_XVSQRTSP:
34429 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34432 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34439 /* Load up a constant. If the mode is a vector mode, splat the value across
34440 all of the vector elements. */
34443 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34447 if (mode == SFmode || mode == DFmode)
34449 rtx d = const_double_from_real_value (dconst, mode);
34450 reg = force_reg (mode, d);
34452 else if (mode == V4SFmode)
34454 rtx d = const_double_from_real_value (dconst, SFmode);
34455 rtvec v = gen_rtvec (4, d, d, d, d);
34456 reg = gen_reg_rtx (mode);
34457 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34459 else if (mode == V2DFmode)
34461 rtx d = const_double_from_real_value (dconst, DFmode);
34462 rtvec v = gen_rtvec (2, d, d);
34463 reg = gen_reg_rtx (mode);
34464 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34467 gcc_unreachable ();
34472 /* Generate an FMA instruction. */
34475 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34477 machine_mode mode = GET_MODE (target);
34480 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34481 gcc_assert (dst != NULL);
34484 emit_move_insn (target, dst);
34487 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34490 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34492 machine_mode mode = GET_MODE (dst);
34495 /* This is a tad more complicated, since the fnma_optab is for
34496 a different expression: fma(-m1, m2, a), which is the same
34497 thing except in the case of signed zeros.
34499 Fortunately we know that if FMA is supported that FNMSUB is
34500 also supported in the ISA. Just expand it directly. */
34502 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34504 r = gen_rtx_NEG (mode, a);
34505 r = gen_rtx_FMA (mode, m1, m2, r);
34506 r = gen_rtx_NEG (mode, r);
34507 emit_insn (gen_rtx_SET (dst, r));
34510 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34511 add a reg_note saying that this was a division. Support both scalar and
34512 vector divide. Assumes no trapping math and finite arguments. */
34515 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34517 machine_mode mode = GET_MODE (dst);
34518 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34521 /* Low precision estimates guarantee 5 bits of accuracy. High
34522 precision estimates guarantee 14 bits of accuracy. SFmode
34523 requires 23 bits of accuracy. DFmode requires 52 bits of
34524 accuracy. Each pass at least doubles the accuracy, leading
34525 to the following. */
34526 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34527 if (mode == DFmode || mode == V2DFmode)
34530 enum insn_code code = optab_handler (smul_optab, mode);
34531 insn_gen_fn gen_mul = GEN_FCN (code);
34533 gcc_assert (code != CODE_FOR_nothing);
34535 one = rs6000_load_constant_and_splat (mode, dconst1);
34537 /* x0 = 1./d estimate */
34538 x0 = gen_reg_rtx (mode);
34539 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34542 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34545 /* e0 = 1. - d * x0 */
34546 e0 = gen_reg_rtx (mode);
34547 rs6000_emit_nmsub (e0, d, x0, one);
34549 /* x1 = x0 + e0 * x0 */
34550 x1 = gen_reg_rtx (mode);
34551 rs6000_emit_madd (x1, e0, x0, x0);
34553 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34554 ++i, xprev = xnext, eprev = enext) {
34556 /* enext = eprev * eprev */
34557 enext = gen_reg_rtx (mode);
34558 emit_insn (gen_mul (enext, eprev, eprev));
34560 /* xnext = xprev + enext * xprev */
34561 xnext = gen_reg_rtx (mode);
34562 rs6000_emit_madd (xnext, enext, xprev, xprev);
34568 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34570 /* u = n * xprev */
34571 u = gen_reg_rtx (mode);
34572 emit_insn (gen_mul (u, n, xprev));
34574 /* v = n - (d * u) */
34575 v = gen_reg_rtx (mode);
34576 rs6000_emit_nmsub (v, d, u, n);
34578 /* dst = (v * xprev) + u */
34579 rs6000_emit_madd (dst, v, xprev, u);
34582 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34585 /* Goldschmidt's Algorithm for single/double-precision floating point
34586 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34589 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34591 machine_mode mode = GET_MODE (src);
34592 rtx e = gen_reg_rtx (mode);
34593 rtx g = gen_reg_rtx (mode);
34594 rtx h = gen_reg_rtx (mode);
34596 /* Low precision estimates guarantee 5 bits of accuracy. High
34597 precision estimates guarantee 14 bits of accuracy. SFmode
34598 requires 23 bits of accuracy. DFmode requires 52 bits of
34599 accuracy. Each pass at least doubles the accuracy, leading
34600 to the following. */
34601 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34602 if (mode == DFmode || mode == V2DFmode)
34607 enum insn_code code = optab_handler (smul_optab, mode);
34608 insn_gen_fn gen_mul = GEN_FCN (code);
34610 gcc_assert (code != CODE_FOR_nothing);
34612 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
34614 /* e = rsqrt estimate */
34615 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
34618 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34621 rtx zero = force_reg (mode, CONST0_RTX (mode));
34623 if (mode == SFmode)
34625 rtx target = emit_conditional_move (e, GT, src, zero, mode,
34628 emit_move_insn (e, target);
34632 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
34633 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
34637 /* g = sqrt estimate. */
34638 emit_insn (gen_mul (g, e, src));
34639 /* h = 1/(2*sqrt) estimate. */
34640 emit_insn (gen_mul (h, e, mhalf));
34646 rtx t = gen_reg_rtx (mode);
34647 rs6000_emit_nmsub (t, g, h, mhalf);
34648 /* Apply correction directly to 1/rsqrt estimate. */
34649 rs6000_emit_madd (dst, e, t, e);
34653 for (i = 0; i < passes; i++)
34655 rtx t1 = gen_reg_rtx (mode);
34656 rtx g1 = gen_reg_rtx (mode);
34657 rtx h1 = gen_reg_rtx (mode);
34659 rs6000_emit_nmsub (t1, g, h, mhalf);
34660 rs6000_emit_madd (g1, g, t1, g);
34661 rs6000_emit_madd (h1, h, t1, h);
34666 /* Multiply by 2 for 1/rsqrt. */
34667 emit_insn (gen_add3_insn (dst, h, h));
34672 rtx t = gen_reg_rtx (mode);
34673 rs6000_emit_nmsub (t, g, h, mhalf);
34674 rs6000_emit_madd (dst, g, t, g);
34680 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
34681 (Power7) targets. DST is the target, and SRC is the argument operand. */
34684 rs6000_emit_popcount (rtx dst, rtx src)
34686 machine_mode mode = GET_MODE (dst);
34689 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
34690 if (TARGET_POPCNTD)
34692 if (mode == SImode)
34693 emit_insn (gen_popcntdsi2 (dst, src));
34695 emit_insn (gen_popcntddi2 (dst, src));
34699 tmp1 = gen_reg_rtx (mode);
34701 if (mode == SImode)
34703 emit_insn (gen_popcntbsi2 (tmp1, src));
34704 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
34706 tmp2 = force_reg (SImode, tmp2);
34707 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
34711 emit_insn (gen_popcntbdi2 (tmp1, src));
34712 tmp2 = expand_mult (DImode, tmp1,
34713 GEN_INT ((HOST_WIDE_INT)
34714 0x01010101 << 32 | 0x01010101),
34716 tmp2 = force_reg (DImode, tmp2);
34717 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
34722 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
34723 target, and SRC is the argument operand. */
34726 rs6000_emit_parity (rtx dst, rtx src)
34728 machine_mode mode = GET_MODE (dst);
34731 tmp = gen_reg_rtx (mode);
34733 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
34736 if (mode == SImode)
34738 emit_insn (gen_popcntbsi2 (tmp, src));
34739 emit_insn (gen_paritysi2_cmpb (dst, tmp));
34743 emit_insn (gen_popcntbdi2 (tmp, src));
34744 emit_insn (gen_paritydi2_cmpb (dst, tmp));
34749 if (mode == SImode)
34751 /* Is mult+shift >= shift+xor+shift+xor? */
34752 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
34754 rtx tmp1, tmp2, tmp3, tmp4;
34756 tmp1 = gen_reg_rtx (SImode);
34757 emit_insn (gen_popcntbsi2 (tmp1, src));
34759 tmp2 = gen_reg_rtx (SImode);
34760 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
34761 tmp3 = gen_reg_rtx (SImode);
34762 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
34764 tmp4 = gen_reg_rtx (SImode);
34765 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
34766 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
34769 rs6000_emit_popcount (tmp, src);
34770 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
34774 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
34775 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
34777 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
34779 tmp1 = gen_reg_rtx (DImode);
34780 emit_insn (gen_popcntbdi2 (tmp1, src));
34782 tmp2 = gen_reg_rtx (DImode);
34783 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
34784 tmp3 = gen_reg_rtx (DImode);
34785 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
34787 tmp4 = gen_reg_rtx (DImode);
34788 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
34789 tmp5 = gen_reg_rtx (DImode);
34790 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
34792 tmp6 = gen_reg_rtx (DImode);
34793 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
34794 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
34797 rs6000_emit_popcount (tmp, src);
34798 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
34802 /* Expand an Altivec constant permutation for little endian mode.
34803 OP0 and OP1 are the input vectors and TARGET is the output vector.
34804 SEL specifies the constant permutation vector.
34806 There are two issues: First, the two input operands must be
34807 swapped so that together they form a double-wide array in LE
34808 order. Second, the vperm instruction has surprising behavior
34809 in LE mode: it interprets the elements of the source vectors
34810 in BE mode ("left to right") and interprets the elements of
34811 the destination vector in LE mode ("right to left"). To
34812 correct for this, we must subtract each element of the permute
34813 control vector from 31.
34815 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
34816 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
34817 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
34818 serve as the permute control vector. Then, in BE mode,
34822 places the desired result in vr9. However, in LE mode the
34823 vector contents will be
34825 vr10 = 00000003 00000002 00000001 00000000
34826 vr11 = 00000007 00000006 00000005 00000004
34828 The result of the vperm using the same permute control vector is
34830 vr9 = 05000000 07000000 01000000 03000000
34832 That is, the leftmost 4 bytes of vr10 are interpreted as the
34833 source for the rightmost 4 bytes of vr9, and so on.
34835 If we change the permute control vector to
34837 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
34845 vr9 = 00000006 00000004 00000002 00000000. */
34848 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
34849 const vec_perm_indices &sel)
34853 rtx constv, unspec;
34855 /* Unpack and adjust the constant selector. */
34856 for (i = 0; i < 16; ++i)
34858 unsigned int elt = 31 - (sel[i] & 31);
34859 perm[i] = GEN_INT (elt);
34862 /* Expand to a permute, swapping the inputs and using the
34863 adjusted selector. */
34865 op0 = force_reg (V16QImode, op0);
34867 op1 = force_reg (V16QImode, op1);
34869 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
34870 constv = force_reg (V16QImode, constv);
34871 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
34873 if (!REG_P (target))
34875 rtx tmp = gen_reg_rtx (V16QImode);
34876 emit_move_insn (tmp, unspec);
34880 emit_move_insn (target, unspec);
34883 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
34884 permute control vector. But here it's not a constant, so we must
34885 generate a vector NAND or NOR to do the adjustment. */
34888 altivec_expand_vec_perm_le (rtx operands[4])
34890 rtx notx, iorx, unspec;
34891 rtx target = operands[0];
34892 rtx op0 = operands[1];
34893 rtx op1 = operands[2];
34894 rtx sel = operands[3];
34896 rtx norreg = gen_reg_rtx (V16QImode);
34897 machine_mode mode = GET_MODE (target);
34899 /* Get everything in regs so the pattern matches. */
34901 op0 = force_reg (mode, op0);
34903 op1 = force_reg (mode, op1);
34905 sel = force_reg (V16QImode, sel);
34906 if (!REG_P (target))
34907 tmp = gen_reg_rtx (mode);
34909 if (TARGET_P9_VECTOR)
34911 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
34916 /* Invert the selector with a VNAND if available, else a VNOR.
34917 The VNAND is preferred for future fusion opportunities. */
34918 notx = gen_rtx_NOT (V16QImode, sel);
34919 iorx = (TARGET_P8_VECTOR
34920 ? gen_rtx_IOR (V16QImode, notx, notx)
34921 : gen_rtx_AND (V16QImode, notx, notx));
34922 emit_insn (gen_rtx_SET (norreg, iorx));
34924 /* Permute with operands reversed and adjusted selector. */
34925 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
34929 /* Copy into target, possibly by way of a register. */
34930 if (!REG_P (target))
34932 emit_move_insn (tmp, unspec);
34936 emit_move_insn (target, unspec);
34939 /* Expand an Altivec constant permutation. Return true if we match
34940 an efficient implementation; false to fall back to VPERM.
34942 OP0 and OP1 are the input vectors and TARGET is the output vector.
34943 SEL specifies the constant permutation vector. */
34946 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
34947 const vec_perm_indices &sel)
34949 struct altivec_perm_insn {
34950 HOST_WIDE_INT mask;
34951 enum insn_code impl;
34952 unsigned char perm[16];
34954 static const struct altivec_perm_insn patterns[] = {
34955 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
34956 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
34957 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
34958 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
34959 { OPTION_MASK_ALTIVEC,
34960 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
34961 : CODE_FOR_altivec_vmrglb_direct),
34962 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
34963 { OPTION_MASK_ALTIVEC,
34964 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
34965 : CODE_FOR_altivec_vmrglh_direct),
34966 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
34967 { OPTION_MASK_ALTIVEC,
34968 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
34969 : CODE_FOR_altivec_vmrglw_direct),
34970 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
34971 { OPTION_MASK_ALTIVEC,
34972 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
34973 : CODE_FOR_altivec_vmrghb_direct),
34974 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
34975 { OPTION_MASK_ALTIVEC,
34976 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
34977 : CODE_FOR_altivec_vmrghh_direct),
34978 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
34979 { OPTION_MASK_ALTIVEC,
34980 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
34981 : CODE_FOR_altivec_vmrghw_direct),
34982 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
34983 { OPTION_MASK_P8_VECTOR,
34984 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
34985 : CODE_FOR_p8_vmrgow_v4sf_direct),
34986 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
34987 { OPTION_MASK_P8_VECTOR,
34988 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
34989 : CODE_FOR_p8_vmrgew_v4sf_direct),
34990 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
34993 unsigned int i, j, elt, which;
34994 unsigned char perm[16];
34998 /* Unpack the constant selector. */
34999 for (i = which = 0; i < 16; ++i)
35002 which |= (elt < 16 ? 1 : 2);
35006 /* Simplify the constant selector based on operands. */
35010 gcc_unreachable ();
35014 if (!rtx_equal_p (op0, op1))
35019 for (i = 0; i < 16; ++i)
35031 /* Look for splat patterns. */
35036 for (i = 0; i < 16; ++i)
35037 if (perm[i] != elt)
35041 if (!BYTES_BIG_ENDIAN)
35043 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35049 for (i = 0; i < 16; i += 2)
35050 if (perm[i] != elt || perm[i + 1] != elt + 1)
35054 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35055 x = gen_reg_rtx (V8HImode);
35056 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35058 emit_move_insn (target, gen_lowpart (V16QImode, x));
35065 for (i = 0; i < 16; i += 4)
35067 || perm[i + 1] != elt + 1
35068 || perm[i + 2] != elt + 2
35069 || perm[i + 3] != elt + 3)
35073 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35074 x = gen_reg_rtx (V4SImode);
35075 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35077 emit_move_insn (target, gen_lowpart (V16QImode, x));
35083 /* Look for merge and pack patterns. */
35084 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35088 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35091 elt = patterns[j].perm[0];
35092 if (perm[0] == elt)
35094 else if (perm[0] == elt + 16)
35098 for (i = 1; i < 16; ++i)
35100 elt = patterns[j].perm[i];
35102 elt = (elt >= 16 ? elt - 16 : elt + 16);
35103 else if (one_vec && elt >= 16)
35105 if (perm[i] != elt)
35110 enum insn_code icode = patterns[j].impl;
35111 machine_mode omode = insn_data[icode].operand[0].mode;
35112 machine_mode imode = insn_data[icode].operand[1].mode;
35114 /* For little-endian, don't use vpkuwum and vpkuhum if the
35115 underlying vector type is not V4SI and V8HI, respectively.
35116 For example, using vpkuwum with a V8HI picks up the even
35117 halfwords (BE numbering) when the even halfwords (LE
35118 numbering) are what we need. */
35119 if (!BYTES_BIG_ENDIAN
35120 && icode == CODE_FOR_altivec_vpkuwum_direct
35121 && ((GET_CODE (op0) == REG
35122 && GET_MODE (op0) != V4SImode)
35123 || (GET_CODE (op0) == SUBREG
35124 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35126 if (!BYTES_BIG_ENDIAN
35127 && icode == CODE_FOR_altivec_vpkuhum_direct
35128 && ((GET_CODE (op0) == REG
35129 && GET_MODE (op0) != V8HImode)
35130 || (GET_CODE (op0) == SUBREG
35131 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35134 /* For little-endian, the two input operands must be swapped
35135 (or swapped back) to ensure proper right-to-left numbering
35137 if (swapped ^ !BYTES_BIG_ENDIAN)
35138 std::swap (op0, op1);
35139 if (imode != V16QImode)
35141 op0 = gen_lowpart (imode, op0);
35142 op1 = gen_lowpart (imode, op1);
35144 if (omode == V16QImode)
35147 x = gen_reg_rtx (omode);
35148 emit_insn (GEN_FCN (icode) (x, op0, op1));
35149 if (omode != V16QImode)
35150 emit_move_insn (target, gen_lowpart (V16QImode, x));
35155 if (!BYTES_BIG_ENDIAN)
35157 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35164 /* Expand a VSX Permute Doubleword constant permutation.
35165 Return true if we match an efficient implementation. */
35168 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35169 unsigned char perm0, unsigned char perm1)
35173 /* If both selectors come from the same operand, fold to single op. */
35174 if ((perm0 & 2) == (perm1 & 2))
35181 /* If both operands are equal, fold to simpler permutation. */
35182 if (rtx_equal_p (op0, op1))
35185 perm1 = (perm1 & 1) + 2;
35187 /* If the first selector comes from the second operand, swap. */
35188 else if (perm0 & 2)
35194 std::swap (op0, op1);
35196 /* If the second selector does not come from the second operand, fail. */
35197 else if ((perm1 & 2) == 0)
35201 if (target != NULL)
35203 machine_mode vmode, dmode;
35206 vmode = GET_MODE (target);
35207 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35208 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35209 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35210 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35211 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35212 emit_insn (gen_rtx_SET (target, x));
35217 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35220 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35221 rtx op1, const vec_perm_indices &sel)
35223 bool testing_p = !target;
35225 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35226 if (TARGET_ALTIVEC && testing_p)
35229 /* Check for ps_merge* or xxpermdi insns. */
35230 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35234 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35235 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35237 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35241 if (TARGET_ALTIVEC)
35243 /* Force the target-independent code to lower to V16QImode. */
35244 if (vmode != V16QImode)
35246 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35253 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35254 OP0 and OP1 are the input vectors and TARGET is the output vector.
35255 PERM specifies the constant permutation vector. */
35258 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35259 machine_mode vmode, const vec_perm_builder &perm)
35261 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35263 emit_move_insn (target, x);
35266 /* Expand an extract even operation. */
35269 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35271 machine_mode vmode = GET_MODE (target);
35272 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35273 vec_perm_builder perm (nelt, nelt, 1);
35275 for (i = 0; i < nelt; i++)
35276 perm.quick_push (i * 2);
35278 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35281 /* Expand a vector interleave operation. */
35284 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35286 machine_mode vmode = GET_MODE (target);
35287 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35288 vec_perm_builder perm (nelt, nelt, 1);
35290 high = (highp ? 0 : nelt / 2);
35291 for (i = 0; i < nelt / 2; i++)
35293 perm.quick_push (i + high);
35294 perm.quick_push (i + nelt + high);
35297 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35300 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35302 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35304 HOST_WIDE_INT hwi_scale (scale);
35305 REAL_VALUE_TYPE r_pow;
35306 rtvec v = rtvec_alloc (2);
35308 rtx scale_vec = gen_reg_rtx (V2DFmode);
35309 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35310 elt = const_double_from_real_value (r_pow, DFmode);
35311 RTVEC_ELT (v, 0) = elt;
35312 RTVEC_ELT (v, 1) = elt;
35313 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35314 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35317 /* Return an RTX representing where to find the function value of a
35318 function returning MODE. */
35320 rs6000_complex_function_value (machine_mode mode)
35322 unsigned int regno;
35324 machine_mode inner = GET_MODE_INNER (mode);
35325 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35327 if (TARGET_FLOAT128_TYPE
35329 || (mode == TCmode && TARGET_IEEEQUAD)))
35330 regno = ALTIVEC_ARG_RETURN;
35332 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35333 regno = FP_ARG_RETURN;
35337 regno = GP_ARG_RETURN;
35339 /* 32-bit is OK since it'll go in r3/r4. */
35340 if (TARGET_32BIT && inner_bytes >= 4)
35341 return gen_rtx_REG (mode, regno);
35344 if (inner_bytes >= 8)
35345 return gen_rtx_REG (mode, regno);
35347 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35349 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35350 GEN_INT (inner_bytes));
35351 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35354 /* Return an rtx describing a return value of MODE as a PARALLEL
35355 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35356 stride REG_STRIDE. */
35359 rs6000_parallel_return (machine_mode mode,
35360 int n_elts, machine_mode elt_mode,
35361 unsigned int regno, unsigned int reg_stride)
35363 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35366 for (i = 0; i < n_elts; i++)
35368 rtx r = gen_rtx_REG (elt_mode, regno);
35369 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35370 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35371 regno += reg_stride;
35377 /* Target hook for TARGET_FUNCTION_VALUE.
35379 An integer value is in r3 and a floating-point value is in fp1,
35380 unless -msoft-float. */
35383 rs6000_function_value (const_tree valtype,
35384 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35385 bool outgoing ATTRIBUTE_UNUSED)
35388 unsigned int regno;
35389 machine_mode elt_mode;
35392 /* Special handling for structs in darwin64. */
35394 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35396 CUMULATIVE_ARGS valcum;
35400 valcum.fregno = FP_ARG_MIN_REG;
35401 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35402 /* Do a trial code generation as if this were going to be passed as
35403 an argument; if any part goes in memory, we return NULL. */
35404 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35407 /* Otherwise fall through to standard ABI rules. */
35410 mode = TYPE_MODE (valtype);
35412 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35413 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35415 int first_reg, n_regs;
35417 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35419 /* _Decimal128 must use even/odd register pairs. */
35420 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35421 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35425 first_reg = ALTIVEC_ARG_RETURN;
35429 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35432 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35433 if (TARGET_32BIT && TARGET_POWERPC64)
35442 int count = GET_MODE_SIZE (mode) / 4;
35443 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35446 if ((INTEGRAL_TYPE_P (valtype)
35447 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35448 || POINTER_TYPE_P (valtype))
35449 mode = TARGET_32BIT ? SImode : DImode;
35451 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35452 /* _Decimal128 must use an even/odd register pair. */
35453 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35454 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35455 && !FLOAT128_VECTOR_P (mode))
35456 regno = FP_ARG_RETURN;
35457 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35458 && targetm.calls.split_complex_arg)
35459 return rs6000_complex_function_value (mode);
35460 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35461 return register is used in both cases, and we won't see V2DImode/V2DFmode
35462 for pure altivec, combine the two cases. */
35463 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35464 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35465 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35466 regno = ALTIVEC_ARG_RETURN;
35468 regno = GP_ARG_RETURN;
35470 return gen_rtx_REG (mode, regno);
35473 /* Define how to find the value returned by a library function
35474 assuming the value has mode MODE. */
35476 rs6000_libcall_value (machine_mode mode)
35478 unsigned int regno;
35480 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35481 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35482 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35484 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35485 /* _Decimal128 must use an even/odd register pair. */
35486 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35487 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35488 regno = FP_ARG_RETURN;
35489 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35490 return register is used in both cases, and we won't see V2DImode/V2DFmode
35491 for pure altivec, combine the two cases. */
35492 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35493 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35494 regno = ALTIVEC_ARG_RETURN;
35495 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35496 return rs6000_complex_function_value (mode);
35498 regno = GP_ARG_RETURN;
35500 return gen_rtx_REG (mode, regno);
35503 /* Compute register pressure classes. We implement the target hook to avoid
35504 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35505 lead to incorrect estimates of number of available registers and therefor
35506 increased register pressure/spill. */
35508 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35513 pressure_classes[n++] = GENERAL_REGS;
35515 pressure_classes[n++] = VSX_REGS;
35518 if (TARGET_ALTIVEC)
35519 pressure_classes[n++] = ALTIVEC_REGS;
35520 if (TARGET_HARD_FLOAT)
35521 pressure_classes[n++] = FLOAT_REGS;
35523 pressure_classes[n++] = CR_REGS;
35524 pressure_classes[n++] = SPECIAL_REGS;
35529 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35530 Frame pointer elimination is automatically handled.
35532 For the RS/6000, if frame pointer elimination is being done, we would like
35533 to convert ap into fp, not sp.
35535 We need r30 if -mminimal-toc was specified, and there are constant pool
35539 rs6000_can_eliminate (const int from, const int to)
35541 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35542 ? ! frame_pointer_needed
35543 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35544 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35545 || constant_pool_empty_p ()
35549 /* Define the offset between two registers, FROM to be eliminated and its
35550 replacement TO, at the start of a routine. */
35552 rs6000_initial_elimination_offset (int from, int to)
35554 rs6000_stack_t *info = rs6000_stack_info ();
35555 HOST_WIDE_INT offset;
35557 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35558 offset = info->push_p ? 0 : -info->total_size;
35559 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35561 offset = info->push_p ? 0 : -info->total_size;
35562 if (FRAME_GROWS_DOWNWARD)
35563 offset += info->fixed_size + info->vars_size + info->parm_size;
35565 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35566 offset = FRAME_GROWS_DOWNWARD
35567 ? info->fixed_size + info->vars_size + info->parm_size
35569 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35570 offset = info->total_size;
35571 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35572 offset = info->push_p ? info->total_size : 0;
35573 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35576 gcc_unreachable ();
35581 /* Fill in sizes of registers used by unwinder. */
35584 rs6000_init_dwarf_reg_sizes_extra (tree address)
35586 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35589 machine_mode mode = TYPE_MODE (char_type_node);
35590 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35591 rtx mem = gen_rtx_MEM (BLKmode, addr);
35592 rtx value = gen_int_mode (16, mode);
35594 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35595 The unwinder still needs to know the size of Altivec registers. */
35597 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35599 int column = DWARF_REG_TO_UNWIND_COLUMN
35600 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35601 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35603 emit_move_insn (adjust_address (mem, mode, offset), value);
35608 /* Map internal gcc register numbers to debug format register numbers.
35609 FORMAT specifies the type of debug register number to use:
35610 0 -- debug information, except for frame-related sections
35611 1 -- DWARF .debug_frame section
35612 2 -- DWARF .eh_frame section */
35615 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
35617 /* Except for the above, we use the internal number for non-DWARF
35618 debug information, and also for .eh_frame. */
35619 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
35622 /* On some platforms, we use the standard DWARF register
35623 numbering for .debug_info and .debug_frame. */
35624 #ifdef RS6000_USE_DWARF_NUMBERING
35627 if (regno == LR_REGNO)
35629 if (regno == CTR_REGNO)
35631 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
35632 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
35633 The actual code emitted saves the whole of CR, so we map CR2_REGNO
35634 to the DWARF reg for CR. */
35635 if (format == 1 && regno == CR2_REGNO)
35637 if (CR_REGNO_P (regno))
35638 return regno - CR0_REGNO + 86;
35639 if (regno == CA_REGNO)
35640 return 101; /* XER */
35641 if (ALTIVEC_REGNO_P (regno))
35642 return regno - FIRST_ALTIVEC_REGNO + 1124;
35643 if (regno == VRSAVE_REGNO)
35645 if (regno == VSCR_REGNO)
35651 /* target hook eh_return_filter_mode */
35652 static scalar_int_mode
35653 rs6000_eh_return_filter_mode (void)
35655 return TARGET_32BIT ? SImode : word_mode;
35658 /* Target hook for scalar_mode_supported_p. */
35660 rs6000_scalar_mode_supported_p (scalar_mode mode)
35662 /* -m32 does not support TImode. This is the default, from
35663 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
35664 same ABI as for -m32. But default_scalar_mode_supported_p allows
35665 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
35666 for -mpowerpc64. */
35667 if (TARGET_32BIT && mode == TImode)
35670 if (DECIMAL_FLOAT_MODE_P (mode))
35671 return default_decimal_float_supported_p ();
35672 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
35675 return default_scalar_mode_supported_p (mode);
35678 /* Target hook for vector_mode_supported_p. */
35680 rs6000_vector_mode_supported_p (machine_mode mode)
35682 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
35683 128-bit, the compiler might try to widen IEEE 128-bit to IBM
35685 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
35692 /* Target hook for floatn_mode. */
35693 static opt_scalar_float_mode
35694 rs6000_floatn_mode (int n, bool extended)
35704 if (TARGET_FLOAT128_TYPE)
35705 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35707 return opt_scalar_float_mode ();
35710 return opt_scalar_float_mode ();
35713 /* Those are the only valid _FloatNx types. */
35714 gcc_unreachable ();
35728 if (TARGET_FLOAT128_TYPE)
35729 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35731 return opt_scalar_float_mode ();
35734 return opt_scalar_float_mode ();
35740 /* Target hook for c_mode_for_suffix. */
35741 static machine_mode
35742 rs6000_c_mode_for_suffix (char suffix)
35744 if (TARGET_FLOAT128_TYPE)
35746 if (suffix == 'q' || suffix == 'Q')
35747 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35749 /* At the moment, we are not defining a suffix for IBM extended double.
35750 If/when the default for -mabi=ieeelongdouble is changed, and we want
35751 to support __ibm128 constants in legacy library code, we may need to
35752 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
35753 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
35754 __float80 constants. */
35760 /* Target hook for invalid_arg_for_unprototyped_fn. */
35761 static const char *
35762 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
35764 return (!rs6000_darwin64_abi
35766 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
35767 && (funcdecl == NULL_TREE
35768 || (TREE_CODE (funcdecl) == FUNCTION_DECL
35769 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
35770 ? N_("AltiVec argument passed to unprototyped function")
35774 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
35775 setup by using __stack_chk_fail_local hidden function instead of
35776 calling __stack_chk_fail directly. Otherwise it is better to call
35777 __stack_chk_fail directly. */
35779 static tree ATTRIBUTE_UNUSED
35780 rs6000_stack_protect_fail (void)
35782 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
35783 ? default_hidden_stack_protect_fail ()
35784 : default_external_stack_protect_fail ();
35787 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
35790 static unsigned HOST_WIDE_INT
35791 rs6000_asan_shadow_offset (void)
35793 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
35797 /* Mask options that we want to support inside of attribute((target)) and
35798 #pragma GCC target operations. Note, we do not include things like
35799 64/32-bit, endianness, hard/soft floating point, etc. that would have
35800 different calling sequences. */
35802 struct rs6000_opt_mask {
35803 const char *name; /* option name */
35804 HOST_WIDE_INT mask; /* mask to set */
35805 bool invert; /* invert sense of mask */
35806 bool valid_target; /* option is a target option */
35809 static struct rs6000_opt_mask const rs6000_opt_masks[] =
35811 { "altivec", OPTION_MASK_ALTIVEC, false, true },
35812 { "cmpb", OPTION_MASK_CMPB, false, true },
35813 { "crypto", OPTION_MASK_CRYPTO, false, true },
35814 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
35815 { "dlmzb", OPTION_MASK_DLMZB, false, true },
35816 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
35818 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
35819 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
35820 { "fprnd", OPTION_MASK_FPRND, false, true },
35821 { "hard-dfp", OPTION_MASK_DFP, false, true },
35822 { "htm", OPTION_MASK_HTM, false, true },
35823 { "isel", OPTION_MASK_ISEL, false, true },
35824 { "mfcrf", OPTION_MASK_MFCRF, false, true },
35825 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
35826 { "modulo", OPTION_MASK_MODULO, false, true },
35827 { "mulhw", OPTION_MASK_MULHW, false, true },
35828 { "multiple", OPTION_MASK_MULTIPLE, false, true },
35829 { "popcntb", OPTION_MASK_POPCNTB, false, true },
35830 { "popcntd", OPTION_MASK_POPCNTD, false, true },
35831 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
35832 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
35833 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
35834 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
35835 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
35836 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
35837 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
35838 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
35839 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
35840 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
35841 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
35842 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
35843 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
35844 { "string", 0, false, true },
35845 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
35846 { "update", OPTION_MASK_NO_UPDATE, true , true },
35847 { "vsx", OPTION_MASK_VSX, false, true },
35848 #ifdef OPTION_MASK_64BIT
35850 { "aix64", OPTION_MASK_64BIT, false, false },
35851 { "aix32", OPTION_MASK_64BIT, true, false },
35853 { "64", OPTION_MASK_64BIT, false, false },
35854 { "32", OPTION_MASK_64BIT, true, false },
35857 #ifdef OPTION_MASK_EABI
35858 { "eabi", OPTION_MASK_EABI, false, false },
35860 #ifdef OPTION_MASK_LITTLE_ENDIAN
35861 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
35862 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
35864 #ifdef OPTION_MASK_RELOCATABLE
35865 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
35867 #ifdef OPTION_MASK_STRICT_ALIGN
35868 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
35870 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
35871 { "string", 0, false, false },
35874 /* Builtin mask mapping for printing the flags. */
35875 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
35877 { "altivec", RS6000_BTM_ALTIVEC, false, false },
35878 { "vsx", RS6000_BTM_VSX, false, false },
35879 { "fre", RS6000_BTM_FRE, false, false },
35880 { "fres", RS6000_BTM_FRES, false, false },
35881 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
35882 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
35883 { "popcntd", RS6000_BTM_POPCNTD, false, false },
35884 { "cell", RS6000_BTM_CELL, false, false },
35885 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
35886 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
35887 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
35888 { "crypto", RS6000_BTM_CRYPTO, false, false },
35889 { "htm", RS6000_BTM_HTM, false, false },
35890 { "hard-dfp", RS6000_BTM_DFP, false, false },
35891 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
35892 { "long-double-128", RS6000_BTM_LDBL128, false, false },
35893 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
35894 { "float128", RS6000_BTM_FLOAT128, false, false },
35895 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
35898 /* Option variables that we want to support inside attribute((target)) and
35899 #pragma GCC target operations. */
35901 struct rs6000_opt_var {
35902 const char *name; /* option name */
35903 size_t global_offset; /* offset of the option in global_options. */
35904 size_t target_offset; /* offset of the option in target options. */
35907 static struct rs6000_opt_var const rs6000_opt_vars[] =
35910 offsetof (struct gcc_options, x_TARGET_FRIZ),
35911 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
35912 { "avoid-indexed-addresses",
35913 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
35914 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
35916 offsetof (struct gcc_options, x_rs6000_default_long_calls),
35917 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
35918 { "optimize-swaps",
35919 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
35920 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
35921 { "allow-movmisalign",
35922 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
35923 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
35925 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
35926 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
35928 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
35929 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
35930 { "align-branch-targets",
35931 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
35932 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
35934 offsetof (struct gcc_options, x_tls_markers),
35935 offsetof (struct cl_target_option, x_tls_markers), },
35937 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
35938 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
35940 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
35941 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
35942 { "speculate-indirect-jumps",
35943 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
35944 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
35947 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
35948 parsing. Return true if there were no errors. */
35951 rs6000_inner_target_options (tree args, bool attr_p)
35955 if (args == NULL_TREE)
35958 else if (TREE_CODE (args) == STRING_CST)
35960 char *p = ASTRDUP (TREE_STRING_POINTER (args));
35963 while ((q = strtok (p, ",")) != NULL)
35965 bool error_p = false;
35966 bool not_valid_p = false;
35967 const char *cpu_opt = NULL;
35970 if (strncmp (q, "cpu=", 4) == 0)
35972 int cpu_index = rs6000_cpu_name_lookup (q+4);
35973 if (cpu_index >= 0)
35974 rs6000_cpu_index = cpu_index;
35981 else if (strncmp (q, "tune=", 5) == 0)
35983 int tune_index = rs6000_cpu_name_lookup (q+5);
35984 if (tune_index >= 0)
35985 rs6000_tune_index = tune_index;
35995 bool invert = false;
35999 if (strncmp (r, "no-", 3) == 0)
36005 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36006 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36008 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36010 if (!rs6000_opt_masks[i].valid_target)
36011 not_valid_p = true;
36015 rs6000_isa_flags_explicit |= mask;
36017 /* VSX needs altivec, so -mvsx automagically sets
36018 altivec and disables -mavoid-indexed-addresses. */
36021 if (mask == OPTION_MASK_VSX)
36023 mask |= OPTION_MASK_ALTIVEC;
36024 TARGET_AVOID_XFORM = 0;
36028 if (rs6000_opt_masks[i].invert)
36032 rs6000_isa_flags &= ~mask;
36034 rs6000_isa_flags |= mask;
36039 if (error_p && !not_valid_p)
36041 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36042 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36044 size_t j = rs6000_opt_vars[i].global_offset;
36045 *((int *) ((char *)&global_options + j)) = !invert;
36047 not_valid_p = false;
36055 const char *eprefix, *esuffix;
36060 eprefix = "__attribute__((__target__(";
36065 eprefix = "#pragma GCC target ";
36070 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36072 else if (not_valid_p)
36073 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36075 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36080 else if (TREE_CODE (args) == TREE_LIST)
36084 tree value = TREE_VALUE (args);
36087 bool ret2 = rs6000_inner_target_options (value, attr_p);
36091 args = TREE_CHAIN (args);
36093 while (args != NULL_TREE);
36098 error ("attribute %<target%> argument not a string");
36105 /* Print out the target options as a list for -mdebug=target. */
36108 rs6000_debug_target_options (tree args, const char *prefix)
36110 if (args == NULL_TREE)
36111 fprintf (stderr, "%s<NULL>", prefix);
36113 else if (TREE_CODE (args) == STRING_CST)
36115 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36118 while ((q = strtok (p, ",")) != NULL)
36121 fprintf (stderr, "%s\"%s\"", prefix, q);
36126 else if (TREE_CODE (args) == TREE_LIST)
36130 tree value = TREE_VALUE (args);
36133 rs6000_debug_target_options (value, prefix);
36136 args = TREE_CHAIN (args);
36138 while (args != NULL_TREE);
36142 gcc_unreachable ();
36148 /* Hook to validate attribute((target("..."))). */
36151 rs6000_valid_attribute_p (tree fndecl,
36152 tree ARG_UNUSED (name),
36156 struct cl_target_option cur_target;
36159 tree new_target, new_optimize;
36160 tree func_optimize;
36162 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36164 if (TARGET_DEBUG_TARGET)
36166 tree tname = DECL_NAME (fndecl);
36167 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36169 fprintf (stderr, "function: %.*s\n",
36170 (int) IDENTIFIER_LENGTH (tname),
36171 IDENTIFIER_POINTER (tname));
36173 fprintf (stderr, "function: unknown\n");
36175 fprintf (stderr, "args:");
36176 rs6000_debug_target_options (args, " ");
36177 fprintf (stderr, "\n");
36180 fprintf (stderr, "flags: 0x%x\n", flags);
36182 fprintf (stderr, "--------------------\n");
36185 /* attribute((target("default"))) does nothing, beyond
36186 affecting multi-versioning. */
36187 if (TREE_VALUE (args)
36188 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36189 && TREE_CHAIN (args) == NULL_TREE
36190 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36193 old_optimize = build_optimization_node (&global_options);
36194 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36196 /* If the function changed the optimization levels as well as setting target
36197 options, start with the optimizations specified. */
36198 if (func_optimize && func_optimize != old_optimize)
36199 cl_optimization_restore (&global_options,
36200 TREE_OPTIMIZATION (func_optimize));
36202 /* The target attributes may also change some optimization flags, so update
36203 the optimization options if necessary. */
36204 cl_target_option_save (&cur_target, &global_options);
36205 rs6000_cpu_index = rs6000_tune_index = -1;
36206 ret = rs6000_inner_target_options (args, true);
36208 /* Set up any additional state. */
36211 ret = rs6000_option_override_internal (false);
36212 new_target = build_target_option_node (&global_options);
36217 new_optimize = build_optimization_node (&global_options);
36224 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36226 if (old_optimize != new_optimize)
36227 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36230 cl_target_option_restore (&global_options, &cur_target);
36232 if (old_optimize != new_optimize)
36233 cl_optimization_restore (&global_options,
36234 TREE_OPTIMIZATION (old_optimize));
36240 /* Hook to validate the current #pragma GCC target and set the state, and
36241 update the macros based on what was changed. If ARGS is NULL, then
36242 POP_TARGET is used to reset the options. */
36245 rs6000_pragma_target_parse (tree args, tree pop_target)
36247 tree prev_tree = build_target_option_node (&global_options);
36249 struct cl_target_option *prev_opt, *cur_opt;
36250 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36251 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36253 if (TARGET_DEBUG_TARGET)
36255 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36256 fprintf (stderr, "args:");
36257 rs6000_debug_target_options (args, " ");
36258 fprintf (stderr, "\n");
36262 fprintf (stderr, "pop_target:\n");
36263 debug_tree (pop_target);
36266 fprintf (stderr, "pop_target: <NULL>\n");
36268 fprintf (stderr, "--------------------\n");
36273 cur_tree = ((pop_target)
36275 : target_option_default_node);
36276 cl_target_option_restore (&global_options,
36277 TREE_TARGET_OPTION (cur_tree));
36281 rs6000_cpu_index = rs6000_tune_index = -1;
36282 if (!rs6000_inner_target_options (args, false)
36283 || !rs6000_option_override_internal (false)
36284 || (cur_tree = build_target_option_node (&global_options))
36287 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36288 fprintf (stderr, "invalid pragma\n");
36294 target_option_current_node = cur_tree;
36295 rs6000_activate_target_options (target_option_current_node);
36297 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36298 change the macros that are defined. */
36299 if (rs6000_target_modify_macros_ptr)
36301 prev_opt = TREE_TARGET_OPTION (prev_tree);
36302 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36303 prev_flags = prev_opt->x_rs6000_isa_flags;
36305 cur_opt = TREE_TARGET_OPTION (cur_tree);
36306 cur_flags = cur_opt->x_rs6000_isa_flags;
36307 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36309 diff_bumask = (prev_bumask ^ cur_bumask);
36310 diff_flags = (prev_flags ^ cur_flags);
36312 if ((diff_flags != 0) || (diff_bumask != 0))
36314 /* Delete old macros. */
36315 rs6000_target_modify_macros_ptr (false,
36316 prev_flags & diff_flags,
36317 prev_bumask & diff_bumask);
36319 /* Define new macros. */
36320 rs6000_target_modify_macros_ptr (true,
36321 cur_flags & diff_flags,
36322 cur_bumask & diff_bumask);
36330 /* Remember the last target of rs6000_set_current_function. */
36331 static GTY(()) tree rs6000_previous_fndecl;
36333 /* Restore target's globals from NEW_TREE and invalidate the
36334 rs6000_previous_fndecl cache. */
36337 rs6000_activate_target_options (tree new_tree)
36339 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36340 if (TREE_TARGET_GLOBALS (new_tree))
36341 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36342 else if (new_tree == target_option_default_node)
36343 restore_target_globals (&default_target_globals);
36345 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36346 rs6000_previous_fndecl = NULL_TREE;
36349 /* Establish appropriate back-end context for processing the function
36350 FNDECL. The argument might be NULL to indicate processing at top
36351 level, outside of any function scope. */
36353 rs6000_set_current_function (tree fndecl)
36355 if (TARGET_DEBUG_TARGET)
36357 fprintf (stderr, "\n==================== rs6000_set_current_function");
36360 fprintf (stderr, ", fndecl %s (%p)",
36361 (DECL_NAME (fndecl)
36362 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36363 : "<unknown>"), (void *)fndecl);
36365 if (rs6000_previous_fndecl)
36366 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36368 fprintf (stderr, "\n");
36371 /* Only change the context if the function changes. This hook is called
36372 several times in the course of compiling a function, and we don't want to
36373 slow things down too much or call target_reinit when it isn't safe. */
36374 if (fndecl == rs6000_previous_fndecl)
36378 if (rs6000_previous_fndecl == NULL_TREE)
36379 old_tree = target_option_current_node;
36380 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36381 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36383 old_tree = target_option_default_node;
36386 if (fndecl == NULL_TREE)
36388 if (old_tree != target_option_current_node)
36389 new_tree = target_option_current_node;
36391 new_tree = NULL_TREE;
36395 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36396 if (new_tree == NULL_TREE)
36397 new_tree = target_option_default_node;
36400 if (TARGET_DEBUG_TARGET)
36404 fprintf (stderr, "\nnew fndecl target specific options:\n");
36405 debug_tree (new_tree);
36410 fprintf (stderr, "\nold fndecl target specific options:\n");
36411 debug_tree (old_tree);
36414 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36415 fprintf (stderr, "--------------------\n");
36418 if (new_tree && old_tree != new_tree)
36419 rs6000_activate_target_options (new_tree);
36422 rs6000_previous_fndecl = fndecl;
36426 /* Save the current options */
36429 rs6000_function_specific_save (struct cl_target_option *ptr,
36430 struct gcc_options *opts)
36432 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36433 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36436 /* Restore the current options */
36439 rs6000_function_specific_restore (struct gcc_options *opts,
36440 struct cl_target_option *ptr)
36443 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36444 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36445 (void) rs6000_option_override_internal (false);
36448 /* Print the current options */
36451 rs6000_function_specific_print (FILE *file, int indent,
36452 struct cl_target_option *ptr)
36454 rs6000_print_isa_options (file, indent, "Isa options set",
36455 ptr->x_rs6000_isa_flags);
36457 rs6000_print_isa_options (file, indent, "Isa options explicit",
36458 ptr->x_rs6000_isa_flags_explicit);
36461 /* Helper function to print the current isa or misc options on a line. */
36464 rs6000_print_options_internal (FILE *file,
36466 const char *string,
36467 HOST_WIDE_INT flags,
36468 const char *prefix,
36469 const struct rs6000_opt_mask *opts,
36470 size_t num_elements)
36473 size_t start_column = 0;
36475 size_t max_column = 120;
36476 size_t prefix_len = strlen (prefix);
36477 size_t comma_len = 0;
36478 const char *comma = "";
36481 start_column += fprintf (file, "%*s", indent, "");
36485 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36489 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36491 /* Print the various mask options. */
36492 cur_column = start_column;
36493 for (i = 0; i < num_elements; i++)
36495 bool invert = opts[i].invert;
36496 const char *name = opts[i].name;
36497 const char *no_str = "";
36498 HOST_WIDE_INT mask = opts[i].mask;
36499 size_t len = comma_len + prefix_len + strlen (name);
36503 if ((flags & mask) == 0)
36506 len += sizeof ("no-") - 1;
36514 if ((flags & mask) != 0)
36517 len += sizeof ("no-") - 1;
36524 if (cur_column > max_column)
36526 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36527 cur_column = start_column + len;
36531 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36533 comma_len = sizeof (", ") - 1;
36536 fputs ("\n", file);
36539 /* Helper function to print the current isa options on a line. */
36542 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36543 HOST_WIDE_INT flags)
36545 rs6000_print_options_internal (file, indent, string, flags, "-m",
36546 &rs6000_opt_masks[0],
36547 ARRAY_SIZE (rs6000_opt_masks));
36551 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36552 HOST_WIDE_INT flags)
36554 rs6000_print_options_internal (file, indent, string, flags, "",
36555 &rs6000_builtin_mask_names[0],
36556 ARRAY_SIZE (rs6000_builtin_mask_names));
36559 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36560 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36561 -mupper-regs-df, etc.).
36563 If the user used -mno-power8-vector, we need to turn off all of the implicit
36564 ISA 2.07 and 3.0 options that relate to the vector unit.
36566 If the user used -mno-power9-vector, we need to turn off all of the implicit
36567 ISA 3.0 options that relate to the vector unit.
36569 This function does not handle explicit options such as the user specifying
36570 -mdirect-move. These are handled in rs6000_option_override_internal, and
36571 the appropriate error is given if needed.
36573 We return a mask of all of the implicit options that should not be enabled
36576 static HOST_WIDE_INT
36577 rs6000_disable_incompatible_switches (void)
36579 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
36582 static const struct {
36583 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
36584 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
36585 const char *const name; /* name of the switch. */
36587 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
36588 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
36589 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
36592 for (i = 0; i < ARRAY_SIZE (flags); i++)
36594 HOST_WIDE_INT no_flag = flags[i].no_flag;
36596 if ((rs6000_isa_flags & no_flag) == 0
36597 && (rs6000_isa_flags_explicit & no_flag) != 0)
36599 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
36600 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
36606 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
36607 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
36609 set_flags &= ~rs6000_opt_masks[j].mask;
36610 error ("%<-mno-%s%> turns off %<-m%s%>",
36612 rs6000_opt_masks[j].name);
36615 gcc_assert (!set_flags);
36618 rs6000_isa_flags &= ~dep_flags;
36619 ignore_masks |= no_flag | dep_flags;
36623 return ignore_masks;
36627 /* Helper function for printing the function name when debugging. */
36629 static const char *
36630 get_decl_name (tree fn)
36637 name = DECL_NAME (fn);
36639 return "<no-name>";
36641 return IDENTIFIER_POINTER (name);
36644 /* Return the clone id of the target we are compiling code for in a target
36645 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
36646 the priority list for the target clones (ordered from lowest to
36650 rs6000_clone_priority (tree fndecl)
36652 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36653 HOST_WIDE_INT isa_masks;
36654 int ret = CLONE_DEFAULT;
36655 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
36656 const char *attrs_str = NULL;
36658 attrs = TREE_VALUE (TREE_VALUE (attrs));
36659 attrs_str = TREE_STRING_POINTER (attrs);
36661 /* Return priority zero for default function. Return the ISA needed for the
36662 function if it is not the default. */
36663 if (strcmp (attrs_str, "default") != 0)
36665 if (fn_opts == NULL_TREE)
36666 fn_opts = target_option_default_node;
36668 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
36669 isa_masks = rs6000_isa_flags;
36671 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
36673 for (ret = CLONE_MAX - 1; ret != 0; ret--)
36674 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
36678 if (TARGET_DEBUG_TARGET)
36679 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
36680 get_decl_name (fndecl), ret);
36685 /* This compares the priority of target features in function DECL1 and DECL2.
36686 It returns positive value if DECL1 is higher priority, negative value if
36687 DECL2 is higher priority and 0 if they are the same. Note, priorities are
36688 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
36691 rs6000_compare_version_priority (tree decl1, tree decl2)
36693 int priority1 = rs6000_clone_priority (decl1);
36694 int priority2 = rs6000_clone_priority (decl2);
36695 int ret = priority1 - priority2;
36697 if (TARGET_DEBUG_TARGET)
36698 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
36699 get_decl_name (decl1), get_decl_name (decl2), ret);
36704 /* Make a dispatcher declaration for the multi-versioned function DECL.
36705 Calls to DECL function will be replaced with calls to the dispatcher
36706 by the front-end. Returns the decl of the dispatcher function. */
36709 rs6000_get_function_versions_dispatcher (void *decl)
36711 tree fn = (tree) decl;
36712 struct cgraph_node *node = NULL;
36713 struct cgraph_node *default_node = NULL;
36714 struct cgraph_function_version_info *node_v = NULL;
36715 struct cgraph_function_version_info *first_v = NULL;
36717 tree dispatch_decl = NULL;
36719 struct cgraph_function_version_info *default_version_info = NULL;
36720 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
36722 if (TARGET_DEBUG_TARGET)
36723 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
36724 get_decl_name (fn));
36726 node = cgraph_node::get (fn);
36727 gcc_assert (node != NULL);
36729 node_v = node->function_version ();
36730 gcc_assert (node_v != NULL);
36732 if (node_v->dispatcher_resolver != NULL)
36733 return node_v->dispatcher_resolver;
36735 /* Find the default version and make it the first node. */
36737 /* Go to the beginning of the chain. */
36738 while (first_v->prev != NULL)
36739 first_v = first_v->prev;
36741 default_version_info = first_v;
36742 while (default_version_info != NULL)
36744 const tree decl2 = default_version_info->this_node->decl;
36745 if (is_function_default_version (decl2))
36747 default_version_info = default_version_info->next;
36750 /* If there is no default node, just return NULL. */
36751 if (default_version_info == NULL)
36754 /* Make default info the first node. */
36755 if (first_v != default_version_info)
36757 default_version_info->prev->next = default_version_info->next;
36758 if (default_version_info->next)
36759 default_version_info->next->prev = default_version_info->prev;
36760 first_v->prev = default_version_info;
36761 default_version_info->next = first_v;
36762 default_version_info->prev = NULL;
36765 default_node = default_version_info->this_node;
36767 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
36768 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36769 "target_clones attribute needs GLIBC (2.23 and newer) that "
36770 "exports hardware capability bits");
36773 if (targetm.has_ifunc_p ())
36775 struct cgraph_function_version_info *it_v = NULL;
36776 struct cgraph_node *dispatcher_node = NULL;
36777 struct cgraph_function_version_info *dispatcher_version_info = NULL;
36779 /* Right now, the dispatching is done via ifunc. */
36780 dispatch_decl = make_dispatcher_decl (default_node->decl);
36782 dispatcher_node = cgraph_node::get_create (dispatch_decl);
36783 gcc_assert (dispatcher_node != NULL);
36784 dispatcher_node->dispatcher_function = 1;
36785 dispatcher_version_info
36786 = dispatcher_node->insert_new_function_version ();
36787 dispatcher_version_info->next = default_version_info;
36788 dispatcher_node->definition = 1;
36790 /* Set the dispatcher for all the versions. */
36791 it_v = default_version_info;
36792 while (it_v != NULL)
36794 it_v->dispatcher_resolver = dispatch_decl;
36800 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36801 "multiversioning needs ifunc which is not supported "
36806 return dispatch_decl;
36809 /* Make the resolver function decl to dispatch the versions of a multi-
36810 versioned function, DEFAULT_DECL. Create an empty basic block in the
36811 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
36815 make_resolver_func (const tree default_decl,
36816 const tree dispatch_decl,
36817 basic_block *empty_bb)
36819 /* Make the resolver function static. The resolver function returns
36821 tree decl_name = clone_function_name (default_decl, "resolver");
36822 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
36823 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
36824 tree decl = build_fn_decl (resolver_name, type);
36825 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
36827 DECL_NAME (decl) = decl_name;
36828 TREE_USED (decl) = 1;
36829 DECL_ARTIFICIAL (decl) = 1;
36830 DECL_IGNORED_P (decl) = 0;
36831 TREE_PUBLIC (decl) = 0;
36832 DECL_UNINLINABLE (decl) = 1;
36834 /* Resolver is not external, body is generated. */
36835 DECL_EXTERNAL (decl) = 0;
36836 DECL_EXTERNAL (dispatch_decl) = 0;
36838 DECL_CONTEXT (decl) = NULL_TREE;
36839 DECL_INITIAL (decl) = make_node (BLOCK);
36840 DECL_STATIC_CONSTRUCTOR (decl) = 0;
36842 /* Build result decl and add to function_decl. */
36843 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
36844 DECL_ARTIFICIAL (t) = 1;
36845 DECL_IGNORED_P (t) = 1;
36846 DECL_RESULT (decl) = t;
36848 gimplify_function_tree (decl);
36849 push_cfun (DECL_STRUCT_FUNCTION (decl));
36850 *empty_bb = init_lowered_empty_function (decl, false,
36851 profile_count::uninitialized ());
36853 cgraph_node::add_new_function (decl, true);
36854 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
36858 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
36859 DECL_ATTRIBUTES (dispatch_decl)
36860 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
36862 cgraph_node::create_same_body_alias (dispatch_decl, decl);
36867 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
36868 return a pointer to VERSION_DECL if we are running on a machine that
36869 supports the index CLONE_ISA hardware architecture bits. This function will
36870 be called during version dispatch to decide which function version to
36871 execute. It returns the basic block at the end, to which more conditions
36875 add_condition_to_bb (tree function_decl, tree version_decl,
36876 int clone_isa, basic_block new_bb)
36878 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
36880 gcc_assert (new_bb != NULL);
36881 gimple_seq gseq = bb_seq (new_bb);
36884 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
36885 build_fold_addr_expr (version_decl));
36886 tree result_var = create_tmp_var (ptr_type_node);
36887 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
36888 gimple *return_stmt = gimple_build_return (result_var);
36890 if (clone_isa == CLONE_DEFAULT)
36892 gimple_seq_add_stmt (&gseq, convert_stmt);
36893 gimple_seq_add_stmt (&gseq, return_stmt);
36894 set_bb_seq (new_bb, gseq);
36895 gimple_set_bb (convert_stmt, new_bb);
36896 gimple_set_bb (return_stmt, new_bb);
36901 tree bool_zero = build_int_cst (bool_int_type_node, 0);
36902 tree cond_var = create_tmp_var (bool_int_type_node);
36903 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
36904 const char *arg_str = rs6000_clone_map[clone_isa].name;
36905 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
36906 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
36907 gimple_call_set_lhs (call_cond_stmt, cond_var);
36909 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
36910 gimple_set_bb (call_cond_stmt, new_bb);
36911 gimple_seq_add_stmt (&gseq, call_cond_stmt);
36913 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
36914 NULL_TREE, NULL_TREE);
36915 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
36916 gimple_set_bb (if_else_stmt, new_bb);
36917 gimple_seq_add_stmt (&gseq, if_else_stmt);
36919 gimple_seq_add_stmt (&gseq, convert_stmt);
36920 gimple_seq_add_stmt (&gseq, return_stmt);
36921 set_bb_seq (new_bb, gseq);
36923 basic_block bb1 = new_bb;
36924 edge e12 = split_block (bb1, if_else_stmt);
36925 basic_block bb2 = e12->dest;
36926 e12->flags &= ~EDGE_FALLTHRU;
36927 e12->flags |= EDGE_TRUE_VALUE;
36929 edge e23 = split_block (bb2, return_stmt);
36930 gimple_set_bb (convert_stmt, bb2);
36931 gimple_set_bb (return_stmt, bb2);
36933 basic_block bb3 = e23->dest;
36934 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
36937 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
36943 /* This function generates the dispatch function for multi-versioned functions.
36944 DISPATCH_DECL is the function which will contain the dispatch logic.
36945 FNDECLS are the function choices for dispatch, and is a tree chain.
36946 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
36947 code is generated. */
36950 dispatch_function_versions (tree dispatch_decl,
36952 basic_block *empty_bb)
36956 vec<tree> *fndecls;
36957 tree clones[CLONE_MAX];
36959 if (TARGET_DEBUG_TARGET)
36960 fputs ("dispatch_function_versions, top\n", stderr);
36962 gcc_assert (dispatch_decl != NULL
36963 && fndecls_p != NULL
36964 && empty_bb != NULL);
36966 /* fndecls_p is actually a vector. */
36967 fndecls = static_cast<vec<tree> *> (fndecls_p);
36969 /* At least one more version other than the default. */
36970 gcc_assert (fndecls->length () >= 2);
36972 /* The first version in the vector is the default decl. */
36973 memset ((void *) clones, '\0', sizeof (clones));
36974 clones[CLONE_DEFAULT] = (*fndecls)[0];
36976 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
36977 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
36978 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
36979 recent glibc. If we ever need to call __builtin_cpu_init, we would need
36980 to insert the code here to do the call. */
36982 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
36984 int priority = rs6000_clone_priority (ele);
36985 if (!clones[priority])
36986 clones[priority] = ele;
36989 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
36992 if (TARGET_DEBUG_TARGET)
36993 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
36994 ix, get_decl_name (clones[ix]));
36996 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37003 /* Generate the dispatching code body to dispatch multi-versioned function
37004 DECL. The target hook is called to process the "target" attributes and
37005 provide the code to dispatch the right function at run-time. NODE points
37006 to the dispatcher decl whose body will be created. */
37009 rs6000_generate_version_dispatcher_body (void *node_p)
37012 basic_block empty_bb;
37013 struct cgraph_node *node = (cgraph_node *) node_p;
37014 struct cgraph_function_version_info *ninfo = node->function_version ();
37016 if (ninfo->dispatcher_resolver)
37017 return ninfo->dispatcher_resolver;
37019 /* node is going to be an alias, so remove the finalized bit. */
37020 node->definition = false;
37022 /* The first version in the chain corresponds to the default version. */
37023 ninfo->dispatcher_resolver = resolver
37024 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37026 if (TARGET_DEBUG_TARGET)
37027 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37028 get_decl_name (resolver));
37030 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37031 auto_vec<tree, 2> fn_ver_vec;
37033 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37035 vinfo = vinfo->next)
37037 struct cgraph_node *version = vinfo->this_node;
37038 /* Check for virtual functions here again, as by this time it should
37039 have been determined if this function needs a vtable index or
37040 not. This happens for methods in derived classes that override
37041 virtual methods in base classes but are not explicitly marked as
37043 if (DECL_VINDEX (version->decl))
37044 sorry ("Virtual function multiversioning not supported");
37046 fn_ver_vec.safe_push (version->decl);
37049 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37050 cgraph_edge::rebuild_edges ();
37056 /* Hook to determine if one function can safely inline another. */
37059 rs6000_can_inline_p (tree caller, tree callee)
37062 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37063 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37065 /* If callee has no option attributes, then it is ok to inline. */
37069 /* If caller has no option attributes, but callee does then it is not ok to
37071 else if (!caller_tree)
37076 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37077 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37079 /* Callee's options should a subset of the caller's, i.e. a vsx function
37080 can inline an altivec function but a non-vsx function can't inline a
37082 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37083 == callee_opts->x_rs6000_isa_flags)
37087 if (TARGET_DEBUG_TARGET)
37088 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37089 get_decl_name (caller), get_decl_name (callee),
37090 (ret ? "can" : "cannot"));
37095 /* Allocate a stack temp and fixup the address so it meets the particular
37096 memory requirements (either offetable or REG+REG addressing). */
37099 rs6000_allocate_stack_temp (machine_mode mode,
37100 bool offsettable_p,
37103 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37104 rtx addr = XEXP (stack, 0);
37105 int strict_p = reload_completed;
37107 if (!legitimate_indirect_address_p (addr, strict_p))
37110 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37111 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37113 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37114 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37120 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37121 to such a form to deal with memory reference instructions like STFIWX that
37122 only take reg+reg addressing. */
37125 rs6000_address_for_fpconvert (rtx x)
37129 gcc_assert (MEM_P (x));
37130 addr = XEXP (x, 0);
37131 if (can_create_pseudo_p ()
37132 && ! legitimate_indirect_address_p (addr, reload_completed)
37133 && ! legitimate_indexed_address_p (addr, reload_completed))
37135 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37137 rtx reg = XEXP (addr, 0);
37138 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37139 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37140 gcc_assert (REG_P (reg));
37141 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37144 else if (GET_CODE (addr) == PRE_MODIFY)
37146 rtx reg = XEXP (addr, 0);
37147 rtx expr = XEXP (addr, 1);
37148 gcc_assert (REG_P (reg));
37149 gcc_assert (GET_CODE (expr) == PLUS);
37150 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37154 x = replace_equiv_address (x, copy_addr_to_reg (addr));
37160 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37162 On the RS/6000, all integer constants are acceptable, most won't be valid
37163 for particular insns, though. Only easy FP constants are acceptable. */
37166 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37168 if (TARGET_ELF && tls_referenced_p (x))
37171 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
37172 || GET_MODE (x) == VOIDmode
37173 || (TARGET_POWERPC64 && mode == DImode)
37174 || easy_fp_constant (x, mode)
37175 || easy_vector_constant (x, mode));
37179 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37182 chain_already_loaded (rtx_insn *last)
37184 for (; last != NULL; last = PREV_INSN (last))
37186 if (NONJUMP_INSN_P (last))
37188 rtx patt = PATTERN (last);
37190 if (GET_CODE (patt) == SET)
37192 rtx lhs = XEXP (patt, 0);
37194 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37202 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37205 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37207 const bool direct_call_p
37208 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
37209 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37210 rtx toc_load = NULL_RTX;
37211 rtx toc_restore = NULL_RTX;
37213 rtx abi_reg = NULL_RTX;
37218 /* Handle longcall attributes. */
37219 if (INTVAL (cookie) & CALL_LONG)
37220 func_desc = rs6000_longcall_ref (func_desc);
37222 /* Handle indirect calls. */
37223 if (GET_CODE (func_desc) != SYMBOL_REF
37224 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
37226 /* Save the TOC into its reserved slot before the call,
37227 and prepare to restore it after the call. */
37228 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37229 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37230 rtx stack_toc_mem = gen_frame_mem (Pmode,
37231 gen_rtx_PLUS (Pmode, stack_ptr,
37232 stack_toc_offset));
37233 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37234 gen_rtvec (1, stack_toc_offset),
37236 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37238 /* Can we optimize saving the TOC in the prologue or
37239 do we need to do it at every call? */
37240 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37241 cfun->machine->save_toc_in_prologue = true;
37244 MEM_VOLATILE_P (stack_toc_mem) = 1;
37245 emit_move_insn (stack_toc_mem, toc_reg);
37248 if (DEFAULT_ABI == ABI_ELFv2)
37250 /* A function pointer in the ELFv2 ABI is just a plain address, but
37251 the ABI requires it to be loaded into r12 before the call. */
37252 func_addr = gen_rtx_REG (Pmode, 12);
37253 emit_move_insn (func_addr, func_desc);
37254 abi_reg = func_addr;
37258 /* A function pointer under AIX is a pointer to a data area whose
37259 first word contains the actual address of the function, whose
37260 second word contains a pointer to its TOC, and whose third word
37261 contains a value to place in the static chain register (r11).
37262 Note that if we load the static chain, our "trampoline" need
37263 not have any executable code. */
37265 /* Load up address of the actual function. */
37266 func_desc = force_reg (Pmode, func_desc);
37267 func_addr = gen_reg_rtx (Pmode);
37268 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
37270 /* Prepare to load the TOC of the called function. Note that the
37271 TOC load must happen immediately before the actual call so
37272 that unwinding the TOC registers works correctly. See the
37273 comment in frob_update_context. */
37274 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37275 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37276 gen_rtx_PLUS (Pmode, func_desc,
37278 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37280 /* If we have a static chain, load it up. But, if the call was
37281 originally direct, the 3rd word has not been written since no
37282 trampoline has been built, so we ought not to load it, lest we
37283 override a static chain value. */
37285 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37286 && !chain_already_loaded (get_current_sequence ()->next->last))
37288 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37289 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37290 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37291 gen_rtx_PLUS (Pmode, func_desc,
37293 emit_move_insn (sc_reg, func_sc_mem);
37300 /* Direct calls use the TOC: for local calls, the callee will
37301 assume the TOC register is set; for non-local calls, the
37302 PLT stub needs the TOC register. */
37304 func_addr = func_desc;
37307 /* Create the call. */
37308 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
37309 if (value != NULL_RTX)
37310 call[0] = gen_rtx_SET (value, call[0]);
37314 call[n_call++] = toc_load;
37316 call[n_call++] = toc_restore;
37318 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
37320 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37321 insn = emit_call_insn (insn);
37323 /* Mention all registers defined by the ABI to hold information
37324 as uses in CALL_INSN_FUNCTION_USAGE. */
37326 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37329 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37332 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37337 gcc_assert (INTVAL (cookie) == 0);
37339 /* Create the call. */
37340 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
37341 if (value != NULL_RTX)
37342 call[0] = gen_rtx_SET (value, call[0]);
37344 call[1] = simple_return_rtx;
37346 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37347 insn = emit_call_insn (insn);
37349 /* Note use of the TOC register. */
37350 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37353 /* Return whether we need to always update the saved TOC pointer when we update
37354 the stack pointer. */
37357 rs6000_save_toc_in_prologue_p (void)
37359 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
37362 #ifdef HAVE_GAS_HIDDEN
37363 # define USE_HIDDEN_LINKONCE 1
37365 # define USE_HIDDEN_LINKONCE 0
37368 /* Fills in the label name that should be used for a 476 link stack thunk. */
37371 get_ppc476_thunk_name (char name[32])
37373 gcc_assert (TARGET_LINK_STACK);
37375 if (USE_HIDDEN_LINKONCE)
37376 sprintf (name, "__ppc476.get_thunk");
37378 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
37381 /* This function emits the simple thunk routine that is used to preserve
37382 the link stack on the 476 cpu. */
37384 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
37386 rs6000_code_end (void)
37391 if (!TARGET_LINK_STACK)
37394 get_ppc476_thunk_name (name);
37396 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
37397 build_function_type_list (void_type_node, NULL_TREE));
37398 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
37399 NULL_TREE, void_type_node);
37400 TREE_PUBLIC (decl) = 1;
37401 TREE_STATIC (decl) = 1;
37404 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
37406 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
37407 targetm.asm_out.unique_section (decl, 0);
37408 switch_to_section (get_named_section (decl, NULL, 0));
37409 DECL_WEAK (decl) = 1;
37410 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
37411 targetm.asm_out.globalize_label (asm_out_file, name);
37412 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
37413 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
37418 switch_to_section (text_section);
37419 ASM_OUTPUT_LABEL (asm_out_file, name);
37422 DECL_INITIAL (decl) = make_node (BLOCK);
37423 current_function_decl = decl;
37424 allocate_struct_function (decl, false);
37425 init_function_start (decl);
37426 first_function_block_is_cold = false;
37427 /* Make sure unwind info is emitted for the thunk if needed. */
37428 final_start_function (emit_barrier (), asm_out_file, 1);
37430 fputs ("\tblr\n", asm_out_file);
37432 final_end_function ();
37433 init_insn_lengths ();
37434 free_after_compilation (cfun);
37436 current_function_decl = NULL;
37439 /* Add r30 to hard reg set if the prologue sets it up and it is not
37440 pic_offset_table_rtx. */
37443 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
37445 if (!TARGET_SINGLE_PIC_BASE
37447 && TARGET_MINIMAL_TOC
37448 && !constant_pool_empty_p ())
37449 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
37450 if (cfun->machine->split_stack_argp_used)
37451 add_to_hard_reg_set (&set->set, Pmode, 12);
37453 /* Make sure the hard reg set doesn't include r2, which was possibly added
37454 via PIC_OFFSET_TABLE_REGNUM. */
37456 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
37460 /* Helper function for rs6000_split_logical to emit a logical instruction after
37461 spliting the operation to single GPR registers.
37463 DEST is the destination register.
37464 OP1 and OP2 are the input source registers.
37465 CODE is the base operation (AND, IOR, XOR, NOT).
37466 MODE is the machine mode.
37467 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37468 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37469 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37472 rs6000_split_logical_inner (rtx dest,
37475 enum rtx_code code,
37477 bool complement_final_p,
37478 bool complement_op1_p,
37479 bool complement_op2_p)
37483 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
37484 if (op2 && GET_CODE (op2) == CONST_INT
37485 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
37486 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37488 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
37489 HOST_WIDE_INT value = INTVAL (op2) & mask;
37491 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
37496 emit_insn (gen_rtx_SET (dest, const0_rtx));
37500 else if (value == mask)
37502 if (!rtx_equal_p (dest, op1))
37503 emit_insn (gen_rtx_SET (dest, op1));
37508 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
37509 into separate ORI/ORIS or XORI/XORIS instrucitons. */
37510 else if (code == IOR || code == XOR)
37514 if (!rtx_equal_p (dest, op1))
37515 emit_insn (gen_rtx_SET (dest, op1));
37521 if (code == AND && mode == SImode
37522 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37524 emit_insn (gen_andsi3 (dest, op1, op2));
37528 if (complement_op1_p)
37529 op1 = gen_rtx_NOT (mode, op1);
37531 if (complement_op2_p)
37532 op2 = gen_rtx_NOT (mode, op2);
37534 /* For canonical RTL, if only one arm is inverted it is the first. */
37535 if (!complement_op1_p && complement_op2_p)
37536 std::swap (op1, op2);
37538 bool_rtx = ((code == NOT)
37539 ? gen_rtx_NOT (mode, op1)
37540 : gen_rtx_fmt_ee (code, mode, op1, op2));
37542 if (complement_final_p)
37543 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
37545 emit_insn (gen_rtx_SET (dest, bool_rtx));
37548 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
37549 operations are split immediately during RTL generation to allow for more
37550 optimizations of the AND/IOR/XOR.
37552 OPERANDS is an array containing the destination and two input operands.
37553 CODE is the base operation (AND, IOR, XOR, NOT).
37554 MODE is the machine mode.
37555 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37556 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37557 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
37558 CLOBBER_REG is either NULL or a scratch register of type CC to allow
37559 formation of the AND instructions. */
37562 rs6000_split_logical_di (rtx operands[3],
37563 enum rtx_code code,
37564 bool complement_final_p,
37565 bool complement_op1_p,
37566 bool complement_op2_p)
37568 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
37569 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
37570 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
37571 enum hi_lo { hi = 0, lo = 1 };
37572 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
37575 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
37576 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
37577 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
37578 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
37581 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
37584 if (GET_CODE (operands[2]) != CONST_INT)
37586 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
37587 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
37591 HOST_WIDE_INT value = INTVAL (operands[2]);
37592 HOST_WIDE_INT value_hi_lo[2];
37594 gcc_assert (!complement_final_p);
37595 gcc_assert (!complement_op1_p);
37596 gcc_assert (!complement_op2_p);
37598 value_hi_lo[hi] = value >> 32;
37599 value_hi_lo[lo] = value & lower_32bits;
37601 for (i = 0; i < 2; i++)
37603 HOST_WIDE_INT sub_value = value_hi_lo[i];
37605 if (sub_value & sign_bit)
37606 sub_value |= upper_32bits;
37608 op2_hi_lo[i] = GEN_INT (sub_value);
37610 /* If this is an AND instruction, check to see if we need to load
37611 the value in a register. */
37612 if (code == AND && sub_value != -1 && sub_value != 0
37613 && !and_operand (op2_hi_lo[i], SImode))
37614 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
37619 for (i = 0; i < 2; i++)
37621 /* Split large IOR/XOR operations. */
37622 if ((code == IOR || code == XOR)
37623 && GET_CODE (op2_hi_lo[i]) == CONST_INT
37624 && !complement_final_p
37625 && !complement_op1_p
37626 && !complement_op2_p
37627 && !logical_const_operand (op2_hi_lo[i], SImode))
37629 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
37630 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
37631 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
37632 rtx tmp = gen_reg_rtx (SImode);
37634 /* Make sure the constant is sign extended. */
37635 if ((hi_16bits & sign_bit) != 0)
37636 hi_16bits |= upper_32bits;
37638 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
37639 code, SImode, false, false, false);
37641 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
37642 code, SImode, false, false, false);
37645 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
37646 code, SImode, complement_final_p,
37647 complement_op1_p, complement_op2_p);
37653 /* Split the insns that make up boolean operations operating on multiple GPR
37654 registers. The boolean MD patterns ensure that the inputs either are
37655 exactly the same as the output registers, or there is no overlap.
37657 OPERANDS is an array containing the destination and two input operands.
37658 CODE is the base operation (AND, IOR, XOR, NOT).
37659 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37660 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37661 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37664 rs6000_split_logical (rtx operands[3],
37665 enum rtx_code code,
37666 bool complement_final_p,
37667 bool complement_op1_p,
37668 bool complement_op2_p)
37670 machine_mode mode = GET_MODE (operands[0]);
37671 machine_mode sub_mode;
37673 int sub_size, regno0, regno1, nregs, i;
37675 /* If this is DImode, use the specialized version that can run before
37676 register allocation. */
37677 if (mode == DImode && !TARGET_POWERPC64)
37679 rs6000_split_logical_di (operands, code, complement_final_p,
37680 complement_op1_p, complement_op2_p);
37686 op2 = (code == NOT) ? NULL_RTX : operands[2];
37687 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
37688 sub_size = GET_MODE_SIZE (sub_mode);
37689 regno0 = REGNO (op0);
37690 regno1 = REGNO (op1);
37692 gcc_assert (reload_completed);
37693 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37694 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37696 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
37697 gcc_assert (nregs > 1);
37699 if (op2 && REG_P (op2))
37700 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
37702 for (i = 0; i < nregs; i++)
37704 int offset = i * sub_size;
37705 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
37706 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
37707 rtx sub_op2 = ((code == NOT)
37709 : simplify_subreg (sub_mode, op2, mode, offset));
37711 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
37712 complement_final_p, complement_op1_p,
37720 /* Return true if the peephole2 can combine a load involving a combination of
37721 an addis instruction and a load with an offset that can be fused together on
37725 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
37726 rtx addis_value, /* addis value. */
37727 rtx target, /* target register that is loaded. */
37728 rtx mem) /* bottom part of the memory addr. */
37733 /* Validate arguments. */
37734 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
37737 if (!base_reg_operand (target, GET_MODE (target)))
37740 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
37743 /* Allow sign/zero extension. */
37744 if (GET_CODE (mem) == ZERO_EXTEND
37745 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
37746 mem = XEXP (mem, 0);
37751 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
37754 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
37755 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
37758 /* Validate that the register used to load the high value is either the
37759 register being loaded, or we can safely replace its use.
37761 This function is only called from the peephole2 pass and we assume that
37762 there are 2 instructions in the peephole (addis and load), so we want to
37763 check if the target register was not used in the memory address and the
37764 register to hold the addis result is dead after the peephole. */
37765 if (REGNO (addis_reg) != REGNO (target))
37767 if (reg_mentioned_p (target, mem))
37770 if (!peep2_reg_dead_p (2, addis_reg))
37773 /* If the target register being loaded is the stack pointer, we must
37774 avoid loading any other value into it, even temporarily. */
37775 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
37779 base_reg = XEXP (addr, 0);
37780 return REGNO (addis_reg) == REGNO (base_reg);
37783 /* During the peephole2 pass, adjust and expand the insns for a load fusion
37784 sequence. We adjust the addis register to use the target register. If the
37785 load sign extends, we adjust the code to do the zero extending load, and an
37786 explicit sign extension later since the fusion only covers zero extending
37790 operands[0] register set with addis (to be replaced with target)
37791 operands[1] value set via addis
37792 operands[2] target register being loaded
37793 operands[3] D-form memory reference using operands[0]. */
37796 expand_fusion_gpr_load (rtx *operands)
37798 rtx addis_value = operands[1];
37799 rtx target = operands[2];
37800 rtx orig_mem = operands[3];
37801 rtx new_addr, new_mem, orig_addr, offset;
37802 enum rtx_code plus_or_lo_sum;
37803 machine_mode target_mode = GET_MODE (target);
37804 machine_mode extend_mode = target_mode;
37805 machine_mode ptr_mode = Pmode;
37806 enum rtx_code extend = UNKNOWN;
37808 if (GET_CODE (orig_mem) == ZERO_EXTEND
37809 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
37811 extend = GET_CODE (orig_mem);
37812 orig_mem = XEXP (orig_mem, 0);
37813 target_mode = GET_MODE (orig_mem);
37816 gcc_assert (MEM_P (orig_mem));
37818 orig_addr = XEXP (orig_mem, 0);
37819 plus_or_lo_sum = GET_CODE (orig_addr);
37820 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
37822 offset = XEXP (orig_addr, 1);
37823 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
37824 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
37826 if (extend != UNKNOWN)
37827 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
37829 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
37830 UNSPEC_FUSION_GPR);
37831 emit_insn (gen_rtx_SET (target, new_mem));
37833 if (extend == SIGN_EXTEND)
37835 int sub_off = ((BYTES_BIG_ENDIAN)
37836 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
37839 = simplify_subreg (target_mode, target, extend_mode, sub_off);
37841 emit_insn (gen_rtx_SET (target,
37842 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
37848 /* Emit the addis instruction that will be part of a fused instruction
37852 emit_fusion_addis (rtx target, rtx addis_value)
37855 const char *addis_str = NULL;
37857 /* Emit the addis instruction. */
37858 fuse_ops[0] = target;
37859 if (satisfies_constraint_L (addis_value))
37861 fuse_ops[1] = addis_value;
37862 addis_str = "lis %0,%v1";
37865 else if (GET_CODE (addis_value) == PLUS)
37867 rtx op0 = XEXP (addis_value, 0);
37868 rtx op1 = XEXP (addis_value, 1);
37870 if (REG_P (op0) && CONST_INT_P (op1)
37871 && satisfies_constraint_L (op1))
37875 addis_str = "addis %0,%1,%v2";
37879 else if (GET_CODE (addis_value) == HIGH)
37881 rtx value = XEXP (addis_value, 0);
37882 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
37884 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
37885 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
37887 addis_str = "addis %0,%2,%1@toc@ha";
37889 else if (TARGET_XCOFF)
37890 addis_str = "addis %0,%1@u(%2)";
37893 gcc_unreachable ();
37896 else if (GET_CODE (value) == PLUS)
37898 rtx op0 = XEXP (value, 0);
37899 rtx op1 = XEXP (value, 1);
37901 if (GET_CODE (op0) == UNSPEC
37902 && XINT (op0, 1) == UNSPEC_TOCREL
37903 && CONST_INT_P (op1))
37905 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
37906 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
37909 addis_str = "addis %0,%2,%1+%3@toc@ha";
37911 else if (TARGET_XCOFF)
37912 addis_str = "addis %0,%1+%3@u(%2)";
37915 gcc_unreachable ();
37919 else if (satisfies_constraint_L (value))
37921 fuse_ops[1] = value;
37922 addis_str = "lis %0,%v1";
37925 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
37927 fuse_ops[1] = value;
37928 addis_str = "lis %0,%1@ha";
37933 fatal_insn ("Could not generate addis value for fusion", addis_value);
37935 output_asm_insn (addis_str, fuse_ops);
37938 /* Emit a D-form load or store instruction that is the second instruction
37939 of a fusion sequence. */
37942 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
37943 const char *insn_str)
37946 char insn_template[80];
37948 fuse_ops[0] = load_store_reg;
37949 fuse_ops[1] = addis_reg;
37951 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
37953 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
37954 fuse_ops[2] = offset;
37955 output_asm_insn (insn_template, fuse_ops);
37958 else if (GET_CODE (offset) == UNSPEC
37959 && XINT (offset, 1) == UNSPEC_TOCREL)
37962 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
37964 else if (TARGET_XCOFF)
37965 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
37968 gcc_unreachable ();
37970 fuse_ops[2] = XVECEXP (offset, 0, 0);
37971 output_asm_insn (insn_template, fuse_ops);
37974 else if (GET_CODE (offset) == PLUS
37975 && GET_CODE (XEXP (offset, 0)) == UNSPEC
37976 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
37977 && CONST_INT_P (XEXP (offset, 1)))
37979 rtx tocrel_unspec = XEXP (offset, 0);
37981 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
37983 else if (TARGET_XCOFF)
37984 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
37987 gcc_unreachable ();
37989 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
37990 fuse_ops[3] = XEXP (offset, 1);
37991 output_asm_insn (insn_template, fuse_ops);
37994 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
37996 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
37998 fuse_ops[2] = offset;
37999 output_asm_insn (insn_template, fuse_ops);
38003 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38008 /* Wrap a TOC address that can be fused to indicate that special fusion
38009 processing is needed. */
38012 fusion_wrap_memory_address (rtx old_mem)
38014 rtx old_addr = XEXP (old_mem, 0);
38015 rtvec v = gen_rtvec (1, old_addr);
38016 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38017 return replace_equiv_address_nv (old_mem, new_addr, false);
38020 /* Given an address, convert it into the addis and load offset parts. Addresses
38021 created during the peephole2 process look like:
38022 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38023 (unspec [(...)] UNSPEC_TOCREL))
38025 Addresses created via toc fusion look like:
38026 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38029 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38033 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38035 lo = XVECEXP (addr, 0, 0);
38036 hi = gen_rtx_HIGH (Pmode, lo);
38038 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38040 hi = XEXP (addr, 0);
38041 lo = XEXP (addr, 1);
38044 gcc_unreachable ();
38050 /* Return a string to fuse an addis instruction with a gpr load to the same
38051 register that we loaded up the addis instruction. The address that is used
38052 is the logical address that was formed during peephole2:
38053 (lo_sum (high) (low-part))
38055 Or the address is the TOC address that is wrapped before register allocation:
38056 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38058 The code is complicated, so we call output_asm_insn directly, and just
38062 emit_fusion_gpr_load (rtx target, rtx mem)
38067 const char *load_str = NULL;
38070 if (GET_CODE (mem) == ZERO_EXTEND)
38071 mem = XEXP (mem, 0);
38073 gcc_assert (REG_P (target) && MEM_P (mem));
38075 addr = XEXP (mem, 0);
38076 fusion_split_address (addr, &addis_value, &load_offset);
38078 /* Now emit the load instruction to the same register. */
38079 mode = GET_MODE (mem);
38097 gcc_assert (TARGET_POWERPC64);
38102 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38105 /* Emit the addis instruction. */
38106 emit_fusion_addis (target, addis_value);
38108 /* Emit the D-form load instruction. */
38109 emit_fusion_load_store (target, target, load_offset, load_str);
38115 /* Return true if the peephole2 can combine a load/store involving a
38116 combination of an addis instruction and the memory operation. This was
38117 added to the ISA 3.0 (power9) hardware. */
38120 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38121 rtx addis_value, /* addis value. */
38122 rtx dest, /* destination (memory or register). */
38123 rtx src) /* source (register or memory). */
38125 rtx addr, mem, offset;
38126 machine_mode mode = GET_MODE (src);
38128 /* Validate arguments. */
38129 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38132 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38135 /* Ignore extend operations that are part of the load. */
38136 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
38137 src = XEXP (src, 0);
38139 /* Test for memory<-register or register<-memory. */
38140 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
38148 else if (MEM_P (src))
38150 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
38159 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38160 if (GET_CODE (addr) == PLUS)
38162 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38165 return satisfies_constraint_I (XEXP (addr, 1));
38168 else if (GET_CODE (addr) == LO_SUM)
38170 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38173 offset = XEXP (addr, 1);
38174 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
38175 return small_toc_ref (offset, GET_MODE (offset));
38177 else if (TARGET_ELF && !TARGET_POWERPC64)
38178 return CONSTANT_P (offset);
38184 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38188 operands[0] register set with addis
38189 operands[1] value set via addis
38190 operands[2] target register being loaded
38191 operands[3] D-form memory reference using operands[0].
38193 This is similar to the fusion introduced with power8, except it scales to
38194 both loads/stores and does not require the result register to be the same as
38195 the base register. At the moment, we only do this if register set with addis
38199 expand_fusion_p9_load (rtx *operands)
38201 rtx tmp_reg = operands[0];
38202 rtx addis_value = operands[1];
38203 rtx target = operands[2];
38204 rtx orig_mem = operands[3];
38205 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
38206 enum rtx_code plus_or_lo_sum;
38207 machine_mode target_mode = GET_MODE (target);
38208 machine_mode extend_mode = target_mode;
38209 machine_mode ptr_mode = Pmode;
38210 enum rtx_code extend = UNKNOWN;
38212 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
38214 extend = GET_CODE (orig_mem);
38215 orig_mem = XEXP (orig_mem, 0);
38216 target_mode = GET_MODE (orig_mem);
38219 gcc_assert (MEM_P (orig_mem));
38221 orig_addr = XEXP (orig_mem, 0);
38222 plus_or_lo_sum = GET_CODE (orig_addr);
38223 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38225 offset = XEXP (orig_addr, 1);
38226 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38227 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38229 if (extend != UNKNOWN)
38230 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
38232 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38235 set = gen_rtx_SET (target, new_mem);
38236 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
38237 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
38243 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38247 operands[0] register set with addis
38248 operands[1] value set via addis
38249 operands[2] target D-form memory being stored to
38250 operands[3] register being stored
38252 This is similar to the fusion introduced with power8, except it scales to
38253 both loads/stores and does not require the result register to be the same as
38254 the base register. At the moment, we only do this if register set with addis
38258 expand_fusion_p9_store (rtx *operands)
38260 rtx tmp_reg = operands[0];
38261 rtx addis_value = operands[1];
38262 rtx orig_mem = operands[2];
38263 rtx src = operands[3];
38264 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
38265 enum rtx_code plus_or_lo_sum;
38266 machine_mode target_mode = GET_MODE (orig_mem);
38267 machine_mode ptr_mode = Pmode;
38269 gcc_assert (MEM_P (orig_mem));
38271 orig_addr = XEXP (orig_mem, 0);
38272 plus_or_lo_sum = GET_CODE (orig_addr);
38273 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38275 offset = XEXP (orig_addr, 1);
38276 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38277 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38279 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
38282 set = gen_rtx_SET (new_mem, new_src);
38283 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
38284 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
38290 /* Return a string to fuse an addis instruction with a load using extended
38291 fusion. The address that is used is the logical address that was formed
38292 during peephole2: (lo_sum (high) (low-part))
38294 The code is complicated, so we call output_asm_insn directly, and just
38298 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
38300 machine_mode mode = GET_MODE (reg);
38304 const char *load_string;
38307 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
38309 mem = XEXP (mem, 0);
38310 mode = GET_MODE (mem);
38313 if (GET_CODE (reg) == SUBREG)
38315 gcc_assert (SUBREG_BYTE (reg) == 0);
38316 reg = SUBREG_REG (reg);
38320 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
38323 if (FP_REGNO_P (r))
38325 if (mode == SFmode)
38326 load_string = "lfs";
38327 else if (mode == DFmode || mode == DImode)
38328 load_string = "lfd";
38330 gcc_unreachable ();
38332 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
38334 if (mode == SFmode)
38335 load_string = "lxssp";
38336 else if (mode == DFmode || mode == DImode)
38337 load_string = "lxsd";
38339 gcc_unreachable ();
38341 else if (INT_REGNO_P (r))
38346 load_string = "lbz";
38349 load_string = "lhz";
38353 load_string = "lwz";
38357 if (!TARGET_POWERPC64)
38358 gcc_unreachable ();
38359 load_string = "ld";
38362 gcc_unreachable ();
38366 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
38369 fatal_insn ("emit_fusion_p9_load not MEM", mem);
38371 addr = XEXP (mem, 0);
38372 fusion_split_address (addr, &hi, &lo);
38374 /* Emit the addis instruction. */
38375 emit_fusion_addis (tmp_reg, hi);
38377 /* Emit the D-form load instruction. */
38378 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
38383 /* Return a string to fuse an addis instruction with a store using extended
38384 fusion. The address that is used is the logical address that was formed
38385 during peephole2: (lo_sum (high) (low-part))
38387 The code is complicated, so we call output_asm_insn directly, and just
38391 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
38393 machine_mode mode = GET_MODE (reg);
38397 const char *store_string;
38400 if (GET_CODE (reg) == SUBREG)
38402 gcc_assert (SUBREG_BYTE (reg) == 0);
38403 reg = SUBREG_REG (reg);
38407 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
38410 if (FP_REGNO_P (r))
38412 if (mode == SFmode)
38413 store_string = "stfs";
38414 else if (mode == DFmode)
38415 store_string = "stfd";
38417 gcc_unreachable ();
38419 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
38421 if (mode == SFmode)
38422 store_string = "stxssp";
38423 else if (mode == DFmode || mode == DImode)
38424 store_string = "stxsd";
38426 gcc_unreachable ();
38428 else if (INT_REGNO_P (r))
38433 store_string = "stb";
38436 store_string = "sth";
38440 store_string = "stw";
38444 if (!TARGET_POWERPC64)
38445 gcc_unreachable ();
38446 store_string = "std";
38449 gcc_unreachable ();
38453 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
38456 fatal_insn ("emit_fusion_p9_store not MEM", mem);
38458 addr = XEXP (mem, 0);
38459 fusion_split_address (addr, &hi, &lo);
38461 /* Emit the addis instruction. */
38462 emit_fusion_addis (tmp_reg, hi);
38464 /* Emit the D-form load instruction. */
38465 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
38470 #ifdef RS6000_GLIBC_ATOMIC_FENV
38471 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38472 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38475 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38478 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38480 if (!TARGET_HARD_FLOAT)
38482 #ifdef RS6000_GLIBC_ATOMIC_FENV
38483 if (atomic_hold_decl == NULL_TREE)
38486 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38487 get_identifier ("__atomic_feholdexcept"),
38488 build_function_type_list (void_type_node,
38489 double_ptr_type_node,
38491 TREE_PUBLIC (atomic_hold_decl) = 1;
38492 DECL_EXTERNAL (atomic_hold_decl) = 1;
38495 if (atomic_clear_decl == NULL_TREE)
38498 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38499 get_identifier ("__atomic_feclearexcept"),
38500 build_function_type_list (void_type_node,
38502 TREE_PUBLIC (atomic_clear_decl) = 1;
38503 DECL_EXTERNAL (atomic_clear_decl) = 1;
38506 tree const_double = build_qualified_type (double_type_node,
38508 tree const_double_ptr = build_pointer_type (const_double);
38509 if (atomic_update_decl == NULL_TREE)
38512 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38513 get_identifier ("__atomic_feupdateenv"),
38514 build_function_type_list (void_type_node,
38517 TREE_PUBLIC (atomic_update_decl) = 1;
38518 DECL_EXTERNAL (atomic_update_decl) = 1;
38521 tree fenv_var = create_tmp_var_raw (double_type_node);
38522 TREE_ADDRESSABLE (fenv_var) = 1;
38523 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38525 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38526 *clear = build_call_expr (atomic_clear_decl, 0);
38527 *update = build_call_expr (atomic_update_decl, 1,
38528 fold_convert (const_double_ptr, fenv_addr));
38533 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38534 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38535 tree call_mffs = build_call_expr (mffs, 0);
38537 /* Generates the equivalent of feholdexcept (&fenv_var)
38539 *fenv_var = __builtin_mffs ();
38541 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38542 __builtin_mtfsf (0xff, fenv_hold); */
38544 /* Mask to clear everything except for the rounding modes and non-IEEE
38545 arithmetic flag. */
38546 const unsigned HOST_WIDE_INT hold_exception_mask =
38547 HOST_WIDE_INT_C (0xffffffff00000007);
38549 tree fenv_var = create_tmp_var_raw (double_type_node);
38551 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38553 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38554 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38555 build_int_cst (uint64_type_node,
38556 hold_exception_mask));
38558 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38561 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38562 build_int_cst (unsigned_type_node, 0xff),
38565 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38567 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38569 double fenv_clear = __builtin_mffs ();
38570 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38571 __builtin_mtfsf (0xff, fenv_clear); */
38573 /* Mask to clear everything except for the rounding modes and non-IEEE
38574 arithmetic flag. */
38575 const unsigned HOST_WIDE_INT clear_exception_mask =
38576 HOST_WIDE_INT_C (0xffffffff00000000);
38578 tree fenv_clear = create_tmp_var_raw (double_type_node);
38580 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38582 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38583 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38585 build_int_cst (uint64_type_node,
38586 clear_exception_mask));
38588 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38589 fenv_clear_llu_and);
38591 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38592 build_int_cst (unsigned_type_node, 0xff),
38595 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38597 /* Generates the equivalent of feupdateenv (&fenv_var)
38599 double old_fenv = __builtin_mffs ();
38600 double fenv_update;
38601 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38602 (*(uint64_t*)fenv_var 0x1ff80fff);
38603 __builtin_mtfsf (0xff, fenv_update); */
38605 const unsigned HOST_WIDE_INT update_exception_mask =
38606 HOST_WIDE_INT_C (0xffffffff1fffff00);
38607 const unsigned HOST_WIDE_INT new_exception_mask =
38608 HOST_WIDE_INT_C (0x1ff80fff);
38610 tree old_fenv = create_tmp_var_raw (double_type_node);
38611 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38613 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38614 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38615 build_int_cst (uint64_type_node,
38616 update_exception_mask));
38618 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38619 build_int_cst (uint64_type_node,
38620 new_exception_mask));
38622 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38623 old_llu_and, new_llu_and);
38625 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38628 tree update_mtfsf = build_call_expr (mtfsf, 2,
38629 build_int_cst (unsigned_type_node, 0xff),
38630 fenv_update_mtfsf);
38632 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
38636 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
38638 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38640 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38641 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38643 /* The destination of the vmrgew instruction layout is:
38644 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38645 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38646 vmrgew instruction will be correct. */
38647 if (BYTES_BIG_ENDIAN)
38649 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
38651 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
38656 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
38657 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
38660 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38661 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38663 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
38664 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
38666 if (BYTES_BIG_ENDIAN)
38667 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38669 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38673 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
38675 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38677 rtx_tmp0 = gen_reg_rtx (V2DImode);
38678 rtx_tmp1 = gen_reg_rtx (V2DImode);
38680 /* The destination of the vmrgew instruction layout is:
38681 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38682 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38683 vmrgew instruction will be correct. */
38684 if (BYTES_BIG_ENDIAN)
38686 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
38687 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
38691 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
38692 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
38695 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38696 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38698 if (signed_convert)
38700 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
38701 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
38705 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
38706 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
38709 if (BYTES_BIG_ENDIAN)
38710 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38712 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38716 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
38719 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38721 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38722 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38724 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
38725 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
38727 rtx_tmp2 = gen_reg_rtx (V4SImode);
38728 rtx_tmp3 = gen_reg_rtx (V4SImode);
38730 if (signed_convert)
38732 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
38733 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
38737 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
38738 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
38741 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
38744 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
38747 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
38748 optimization_type opt_type)
38753 return (opt_type == OPTIMIZE_FOR_SPEED
38754 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
38761 /* Implement TARGET_CONSTANT_ALIGNMENT. */
38763 static HOST_WIDE_INT
38764 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
38766 if (TREE_CODE (exp) == STRING_CST
38767 && (STRICT_ALIGNMENT || !optimize_size))
38768 return MAX (align, BITS_PER_WORD);
38772 /* Implement TARGET_STARTING_FRAME_OFFSET. */
38774 static HOST_WIDE_INT
38775 rs6000_starting_frame_offset (void)
38777 if (FRAME_GROWS_DOWNWARD)
38779 return RS6000_STARTING_FRAME_OFFSET;
38783 /* Create an alias for a mangled name where we have changed the mangling (in
38784 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
38785 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
38787 #if TARGET_ELF && RS6000_WEAK
38789 rs6000_globalize_decl_name (FILE * stream, tree decl)
38791 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
38793 targetm.asm_out.globalize_label (stream, name);
38795 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
38797 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
38798 const char *old_name;
38800 ieee128_mangling_gcc_8_1 = true;
38801 lang_hooks.set_decl_assembler_name (decl);
38802 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
38803 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
38804 ieee128_mangling_gcc_8_1 = false;
38806 if (strcmp (name, old_name) != 0)
38808 fprintf (stream, "\t.weak %s\n", old_name);
38809 fprintf (stream, "\t.set %s,%s\n", old_name, name);
38816 struct gcc_target targetm = TARGET_INITIALIZER;
38818 #include "gt-rs6000.h"