1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "langhooks.h"
56 #include "sched-int.h"
58 #include "tree-flow.h"
61 #include "tm-constrs.h"
64 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
67 #include "gstab.h" /* for N_SLINE */
70 #ifndef TARGET_NO_PROTOTYPE
71 #define TARGET_NO_PROTOTYPE 0
74 #define min(A,B) ((A) < (B) ? (A) : (B))
75 #define max(A,B) ((A) > (B) ? (A) : (B))
77 /* Structure used to define the rs6000 stack */
78 typedef struct rs6000_stack {
79 int reload_completed; /* stack info won't change from here on */
80 int first_gp_reg_save; /* first callee saved GP register used */
81 int first_fp_reg_save; /* first callee saved FP register used */
82 int first_altivec_reg_save; /* first callee saved AltiVec register used */
83 int lr_save_p; /* true if the link reg needs to be saved */
84 int cr_save_p; /* true if the CR reg needs to be saved */
85 unsigned int vrsave_mask; /* mask of vec registers to save */
86 int push_p; /* true if we need to allocate stack space */
87 int calls_p; /* true if the function makes any calls */
88 int world_save_p; /* true if we're saving *everything*:
89 r13-r31, cr, f14-f31, vrsave, v20-v31 */
90 enum rs6000_abi abi; /* which ABI to use */
91 int gp_save_offset; /* offset to save GP regs from initial SP */
92 int fp_save_offset; /* offset to save FP regs from initial SP */
93 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
94 int lr_save_offset; /* offset to save LR from initial SP */
95 int cr_save_offset; /* offset to save CR from initial SP */
96 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
97 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
98 int varargs_save_offset; /* offset to save the varargs registers */
99 int ehrd_offset; /* offset to EH return data */
100 int reg_size; /* register size (4 or 8) */
101 HOST_WIDE_INT vars_size; /* variable save area size */
102 int parm_size; /* outgoing parameter size */
103 int save_size; /* save area size */
104 int fixed_size; /* fixed size of stack frame */
105 int gp_size; /* size of saved GP registers */
106 int fp_size; /* size of saved FP registers */
107 int altivec_size; /* size of saved AltiVec registers */
108 int cr_size; /* size to hold CR if not in save_size */
109 int vrsave_size; /* size to hold VRSAVE if not in save_size */
110 int altivec_padding_size; /* size of altivec alignment padding if
112 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
113 int spe_padding_size;
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
119 /* A C structure for machine-specific, per-function data.
120 This is added to the cfun structure. */
121 typedef struct GTY(()) machine_function
123 /* Some local-dynamic symbol. */
124 const char *some_ld_name;
125 /* Whether the instruction chain has been scanned already. */
126 int insn_chain_scanned_p;
127 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
128 int ra_needs_full_frame;
129 /* Flags if __builtin_return_address (0) was used. */
131 /* Cache lr_save_p after expansion of builtin_eh_return. */
133 /* Whether we need to save the TOC to the reserved stack location in the
134 function prologue. */
135 bool save_toc_in_prologue;
136 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
137 varargs save area. */
138 HOST_WIDE_INT varargs_save_offset;
139 /* Temporary stack slot to use for SDmode copies. This slot is
140 64-bits wide and is allocated early enough so that the offset
141 does not overflow the 16-bit load/store offset field. */
142 rtx sdmode_stack_slot;
145 /* Support targetm.vectorize.builtin_mask_for_load. */
146 static GTY(()) tree altivec_builtin_mask_for_load;
148 /* Set to nonzero once AIX common-mode calls have been defined. */
149 static GTY(()) int common_mode_defined;
151 /* Label number of label created for -mrelocatable, to call to so we can
152 get the address of the GOT section */
153 static int rs6000_pic_labelno;
156 /* Counter for labels which are to be placed in .fixup. */
157 int fixuplabelno = 0;
160 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
163 /* Specify the machine mode that pointers have. After generation of rtl, the
164 compiler makes no further distinction between pointers and any other objects
165 of this machine mode. The type is unsigned since not all things that
166 include rs6000.h also include machmode.h. */
167 unsigned rs6000_pmode;
169 /* Width in bits of a pointer. */
170 unsigned rs6000_pointer_size;
172 #ifdef HAVE_AS_GNU_ATTRIBUTE
173 /* Flag whether floating point values have been passed/returned. */
174 static bool rs6000_passes_float;
175 /* Flag whether vector values have been passed/returned. */
176 static bool rs6000_passes_vector;
177 /* Flag whether small (<= 8 byte) structures have been returned. */
178 static bool rs6000_returns_struct;
181 /* Value is TRUE if register/mode pair is acceptable. */
182 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
184 /* Maximum number of registers needed for a given register class and mode. */
185 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
187 /* How many registers are needed for a given register and mode. */
188 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
190 /* Map register number to register class. */
191 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
193 /* Reload functions based on the type and the vector unit. */
194 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
196 static int dbg_cost_ctrl;
198 /* Built in types. */
199 tree rs6000_builtin_types[RS6000_BTI_MAX];
200 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
202 /* Flag to say the TOC is initialized */
204 char toc_label_name[10];
206 /* Cached value of rs6000_variable_issue. This is cached in
207 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
208 static short cached_can_issue_more;
210 static GTY(()) section *read_only_data_section;
211 static GTY(()) section *private_data_section;
212 static GTY(()) section *read_only_private_data_section;
213 static GTY(()) section *sdata2_section;
214 static GTY(()) section *toc_section;
216 struct builtin_description
218 const unsigned int mask;
219 const enum insn_code icode;
220 const char *const name;
221 const enum rs6000_builtins code;
224 /* Describe the vector unit used for modes. */
225 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
226 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
228 /* Register classes for various constraints that are based on the target
230 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
232 /* Describe the alignment of a vector. */
233 int rs6000_vector_align[NUM_MACHINE_MODES];
235 /* Map selected modes to types for builtins. */
236 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
238 /* What modes to automatically generate reciprocal divide estimate (fre) and
239 reciprocal sqrt (frsqrte) for. */
240 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
242 /* Masks to determine which reciprocal esitmate instructions to generate
244 enum rs6000_recip_mask {
245 RECIP_SF_DIV = 0x001, /* Use divide estimate */
246 RECIP_DF_DIV = 0x002,
247 RECIP_V4SF_DIV = 0x004,
248 RECIP_V2DF_DIV = 0x008,
250 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
251 RECIP_DF_RSQRT = 0x020,
252 RECIP_V4SF_RSQRT = 0x040,
253 RECIP_V2DF_RSQRT = 0x080,
255 /* Various combination of flags for -mrecip=xxx. */
257 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
258 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
259 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
261 RECIP_HIGH_PRECISION = RECIP_ALL,
263 /* On low precision machines like the power5, don't enable double precision
264 reciprocal square root estimate, since it isn't accurate enough. */
265 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
268 /* -mrecip options. */
271 const char *string; /* option name */
272 unsigned int mask; /* mask bits to set */
273 } recip_options[] = {
274 { "all", RECIP_ALL },
275 { "none", RECIP_NONE },
276 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
278 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
279 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
280 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
281 | RECIP_V2DF_RSQRT) },
282 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
283 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
286 /* 2 argument gen function typedef. */
287 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
289 /* Pointer to function (in rs6000-c.c) that can define or undefine target
290 macros that have changed. Languages that don't support the preprocessor
291 don't link in rs6000-c.c, so we can't call it directly. */
292 void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
295 /* Target cpu costs. */
297 struct processor_costs {
298 const int mulsi; /* cost of SImode multiplication. */
299 const int mulsi_const; /* cost of SImode multiplication by constant. */
300 const int mulsi_const9; /* cost of SImode mult by short constant. */
301 const int muldi; /* cost of DImode multiplication. */
302 const int divsi; /* cost of SImode division. */
303 const int divdi; /* cost of DImode division. */
304 const int fp; /* cost of simple SFmode and DFmode insns. */
305 const int dmul; /* cost of DFmode multiplication (and fmadd). */
306 const int sdiv; /* cost of SFmode division (fdivs). */
307 const int ddiv; /* cost of DFmode division (fdiv). */
308 const int cache_line_size; /* cache line size in bytes. */
309 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
310 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
311 const int simultaneous_prefetches; /* number of parallel prefetch
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
338 /* Instruction size costs on 64bit processors. */
340 struct processor_costs size64_cost = {
341 COSTS_N_INSNS (1), /* mulsi */
342 COSTS_N_INSNS (1), /* mulsi_const */
343 COSTS_N_INSNS (1), /* mulsi_const9 */
344 COSTS_N_INSNS (1), /* muldi */
345 COSTS_N_INSNS (1), /* divsi */
346 COSTS_N_INSNS (1), /* divdi */
347 COSTS_N_INSNS (1), /* fp */
348 COSTS_N_INSNS (1), /* dmul */
349 COSTS_N_INSNS (1), /* sdiv */
350 COSTS_N_INSNS (1), /* ddiv */
357 /* Instruction costs on RIOS1 processors. */
359 struct processor_costs rios1_cost = {
360 COSTS_N_INSNS (5), /* mulsi */
361 COSTS_N_INSNS (4), /* mulsi_const */
362 COSTS_N_INSNS (3), /* mulsi_const9 */
363 COSTS_N_INSNS (5), /* muldi */
364 COSTS_N_INSNS (19), /* divsi */
365 COSTS_N_INSNS (19), /* divdi */
366 COSTS_N_INSNS (2), /* fp */
367 COSTS_N_INSNS (2), /* dmul */
368 COSTS_N_INSNS (19), /* sdiv */
369 COSTS_N_INSNS (19), /* ddiv */
370 128, /* cache line size */
376 /* Instruction costs on RIOS2 processors. */
378 struct processor_costs rios2_cost = {
379 COSTS_N_INSNS (2), /* mulsi */
380 COSTS_N_INSNS (2), /* mulsi_const */
381 COSTS_N_INSNS (2), /* mulsi_const9 */
382 COSTS_N_INSNS (2), /* muldi */
383 COSTS_N_INSNS (13), /* divsi */
384 COSTS_N_INSNS (13), /* divdi */
385 COSTS_N_INSNS (2), /* fp */
386 COSTS_N_INSNS (2), /* dmul */
387 COSTS_N_INSNS (17), /* sdiv */
388 COSTS_N_INSNS (17), /* ddiv */
389 256, /* cache line size */
395 /* Instruction costs on RS64A processors. */
397 struct processor_costs rs64a_cost = {
398 COSTS_N_INSNS (20), /* mulsi */
399 COSTS_N_INSNS (12), /* mulsi_const */
400 COSTS_N_INSNS (8), /* mulsi_const9 */
401 COSTS_N_INSNS (34), /* muldi */
402 COSTS_N_INSNS (65), /* divsi */
403 COSTS_N_INSNS (67), /* divdi */
404 COSTS_N_INSNS (4), /* fp */
405 COSTS_N_INSNS (4), /* dmul */
406 COSTS_N_INSNS (31), /* sdiv */
407 COSTS_N_INSNS (31), /* ddiv */
408 128, /* cache line size */
414 /* Instruction costs on MPCCORE processors. */
416 struct processor_costs mpccore_cost = {
417 COSTS_N_INSNS (2), /* mulsi */
418 COSTS_N_INSNS (2), /* mulsi_const */
419 COSTS_N_INSNS (2), /* mulsi_const9 */
420 COSTS_N_INSNS (2), /* muldi */
421 COSTS_N_INSNS (6), /* divsi */
422 COSTS_N_INSNS (6), /* divdi */
423 COSTS_N_INSNS (4), /* fp */
424 COSTS_N_INSNS (5), /* dmul */
425 COSTS_N_INSNS (10), /* sdiv */
426 COSTS_N_INSNS (17), /* ddiv */
427 32, /* cache line size */
433 /* Instruction costs on PPC403 processors. */
435 struct processor_costs ppc403_cost = {
436 COSTS_N_INSNS (4), /* mulsi */
437 COSTS_N_INSNS (4), /* mulsi_const */
438 COSTS_N_INSNS (4), /* mulsi_const9 */
439 COSTS_N_INSNS (4), /* muldi */
440 COSTS_N_INSNS (33), /* divsi */
441 COSTS_N_INSNS (33), /* divdi */
442 COSTS_N_INSNS (11), /* fp */
443 COSTS_N_INSNS (11), /* dmul */
444 COSTS_N_INSNS (11), /* sdiv */
445 COSTS_N_INSNS (11), /* ddiv */
446 32, /* cache line size */
452 /* Instruction costs on PPC405 processors. */
454 struct processor_costs ppc405_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (4), /* mulsi_const */
457 COSTS_N_INSNS (3), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (35), /* divsi */
460 COSTS_N_INSNS (35), /* divdi */
461 COSTS_N_INSNS (11), /* fp */
462 COSTS_N_INSNS (11), /* dmul */
463 COSTS_N_INSNS (11), /* sdiv */
464 COSTS_N_INSNS (11), /* ddiv */
465 32, /* cache line size */
471 /* Instruction costs on PPC440 processors. */
473 struct processor_costs ppc440_cost = {
474 COSTS_N_INSNS (3), /* mulsi */
475 COSTS_N_INSNS (2), /* mulsi_const */
476 COSTS_N_INSNS (2), /* mulsi_const9 */
477 COSTS_N_INSNS (3), /* muldi */
478 COSTS_N_INSNS (34), /* divsi */
479 COSTS_N_INSNS (34), /* divdi */
480 COSTS_N_INSNS (5), /* fp */
481 COSTS_N_INSNS (5), /* dmul */
482 COSTS_N_INSNS (19), /* sdiv */
483 COSTS_N_INSNS (33), /* ddiv */
484 32, /* cache line size */
490 /* Instruction costs on PPC476 processors. */
492 struct processor_costs ppc476_cost = {
493 COSTS_N_INSNS (4), /* mulsi */
494 COSTS_N_INSNS (4), /* mulsi_const */
495 COSTS_N_INSNS (4), /* mulsi_const9 */
496 COSTS_N_INSNS (4), /* muldi */
497 COSTS_N_INSNS (11), /* divsi */
498 COSTS_N_INSNS (11), /* divdi */
499 COSTS_N_INSNS (6), /* fp */
500 COSTS_N_INSNS (6), /* dmul */
501 COSTS_N_INSNS (19), /* sdiv */
502 COSTS_N_INSNS (33), /* ddiv */
503 32, /* l1 cache line size */
509 /* Instruction costs on PPC601 processors. */
511 struct processor_costs ppc601_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (5), /* mulsi_const */
514 COSTS_N_INSNS (5), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (36), /* divsi */
517 COSTS_N_INSNS (36), /* divdi */
518 COSTS_N_INSNS (4), /* fp */
519 COSTS_N_INSNS (5), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
522 32, /* cache line size */
528 /* Instruction costs on PPC603 processors. */
530 struct processor_costs ppc603_cost = {
531 COSTS_N_INSNS (5), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (2), /* mulsi_const9 */
534 COSTS_N_INSNS (5), /* muldi */
535 COSTS_N_INSNS (37), /* divsi */
536 COSTS_N_INSNS (37), /* divdi */
537 COSTS_N_INSNS (3), /* fp */
538 COSTS_N_INSNS (4), /* dmul */
539 COSTS_N_INSNS (18), /* sdiv */
540 COSTS_N_INSNS (33), /* ddiv */
541 32, /* cache line size */
547 /* Instruction costs on PPC604 processors. */
549 struct processor_costs ppc604_cost = {
550 COSTS_N_INSNS (4), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (4), /* mulsi_const9 */
553 COSTS_N_INSNS (4), /* muldi */
554 COSTS_N_INSNS (20), /* divsi */
555 COSTS_N_INSNS (20), /* divdi */
556 COSTS_N_INSNS (3), /* fp */
557 COSTS_N_INSNS (3), /* dmul */
558 COSTS_N_INSNS (18), /* sdiv */
559 COSTS_N_INSNS (32), /* ddiv */
560 32, /* cache line size */
566 /* Instruction costs on PPC604e processors. */
568 struct processor_costs ppc604e_cost = {
569 COSTS_N_INSNS (2), /* mulsi */
570 COSTS_N_INSNS (2), /* mulsi_const */
571 COSTS_N_INSNS (2), /* mulsi_const9 */
572 COSTS_N_INSNS (2), /* muldi */
573 COSTS_N_INSNS (20), /* divsi */
574 COSTS_N_INSNS (20), /* divdi */
575 COSTS_N_INSNS (3), /* fp */
576 COSTS_N_INSNS (3), /* dmul */
577 COSTS_N_INSNS (18), /* sdiv */
578 COSTS_N_INSNS (32), /* ddiv */
579 32, /* cache line size */
585 /* Instruction costs on PPC620 processors. */
587 struct processor_costs ppc620_cost = {
588 COSTS_N_INSNS (5), /* mulsi */
589 COSTS_N_INSNS (4), /* mulsi_const */
590 COSTS_N_INSNS (3), /* mulsi_const9 */
591 COSTS_N_INSNS (7), /* muldi */
592 COSTS_N_INSNS (21), /* divsi */
593 COSTS_N_INSNS (37), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (18), /* sdiv */
597 COSTS_N_INSNS (32), /* ddiv */
598 128, /* cache line size */
604 /* Instruction costs on PPC630 processors. */
606 struct processor_costs ppc630_cost = {
607 COSTS_N_INSNS (5), /* mulsi */
608 COSTS_N_INSNS (4), /* mulsi_const */
609 COSTS_N_INSNS (3), /* mulsi_const9 */
610 COSTS_N_INSNS (7), /* muldi */
611 COSTS_N_INSNS (21), /* divsi */
612 COSTS_N_INSNS (37), /* divdi */
613 COSTS_N_INSNS (3), /* fp */
614 COSTS_N_INSNS (3), /* dmul */
615 COSTS_N_INSNS (17), /* sdiv */
616 COSTS_N_INSNS (21), /* ddiv */
617 128, /* cache line size */
623 /* Instruction costs on Cell processor. */
624 /* COSTS_N_INSNS (1) ~ one add. */
626 struct processor_costs ppccell_cost = {
627 COSTS_N_INSNS (9/2)+2, /* mulsi */
628 COSTS_N_INSNS (6/2), /* mulsi_const */
629 COSTS_N_INSNS (6/2), /* mulsi_const9 */
630 COSTS_N_INSNS (15/2)+2, /* muldi */
631 COSTS_N_INSNS (38/2), /* divsi */
632 COSTS_N_INSNS (70/2), /* divdi */
633 COSTS_N_INSNS (10/2), /* fp */
634 COSTS_N_INSNS (10/2), /* dmul */
635 COSTS_N_INSNS (74/2), /* sdiv */
636 COSTS_N_INSNS (74/2), /* ddiv */
637 128, /* cache line size */
643 /* Instruction costs on PPC750 and PPC7400 processors. */
645 struct processor_costs ppc750_cost = {
646 COSTS_N_INSNS (5), /* mulsi */
647 COSTS_N_INSNS (3), /* mulsi_const */
648 COSTS_N_INSNS (2), /* mulsi_const9 */
649 COSTS_N_INSNS (5), /* muldi */
650 COSTS_N_INSNS (17), /* divsi */
651 COSTS_N_INSNS (17), /* divdi */
652 COSTS_N_INSNS (3), /* fp */
653 COSTS_N_INSNS (3), /* dmul */
654 COSTS_N_INSNS (17), /* sdiv */
655 COSTS_N_INSNS (31), /* ddiv */
656 32, /* cache line size */
662 /* Instruction costs on PPC7450 processors. */
664 struct processor_costs ppc7450_cost = {
665 COSTS_N_INSNS (4), /* mulsi */
666 COSTS_N_INSNS (3), /* mulsi_const */
667 COSTS_N_INSNS (3), /* mulsi_const9 */
668 COSTS_N_INSNS (4), /* muldi */
669 COSTS_N_INSNS (23), /* divsi */
670 COSTS_N_INSNS (23), /* divdi */
671 COSTS_N_INSNS (5), /* fp */
672 COSTS_N_INSNS (5), /* dmul */
673 COSTS_N_INSNS (21), /* sdiv */
674 COSTS_N_INSNS (35), /* ddiv */
675 32, /* cache line size */
681 /* Instruction costs on PPC8540 processors. */
683 struct processor_costs ppc8540_cost = {
684 COSTS_N_INSNS (4), /* mulsi */
685 COSTS_N_INSNS (4), /* mulsi_const */
686 COSTS_N_INSNS (4), /* mulsi_const9 */
687 COSTS_N_INSNS (4), /* muldi */
688 COSTS_N_INSNS (19), /* divsi */
689 COSTS_N_INSNS (19), /* divdi */
690 COSTS_N_INSNS (4), /* fp */
691 COSTS_N_INSNS (4), /* dmul */
692 COSTS_N_INSNS (29), /* sdiv */
693 COSTS_N_INSNS (29), /* ddiv */
694 32, /* cache line size */
697 1, /* prefetch streams /*/
700 /* Instruction costs on E300C2 and E300C3 cores. */
702 struct processor_costs ppce300c2c3_cost = {
703 COSTS_N_INSNS (4), /* mulsi */
704 COSTS_N_INSNS (4), /* mulsi_const */
705 COSTS_N_INSNS (4), /* mulsi_const9 */
706 COSTS_N_INSNS (4), /* muldi */
707 COSTS_N_INSNS (19), /* divsi */
708 COSTS_N_INSNS (19), /* divdi */
709 COSTS_N_INSNS (3), /* fp */
710 COSTS_N_INSNS (4), /* dmul */
711 COSTS_N_INSNS (18), /* sdiv */
712 COSTS_N_INSNS (33), /* ddiv */
716 1, /* prefetch streams /*/
719 /* Instruction costs on PPCE500MC processors. */
721 struct processor_costs ppce500mc_cost = {
722 COSTS_N_INSNS (4), /* mulsi */
723 COSTS_N_INSNS (4), /* mulsi_const */
724 COSTS_N_INSNS (4), /* mulsi_const9 */
725 COSTS_N_INSNS (4), /* muldi */
726 COSTS_N_INSNS (14), /* divsi */
727 COSTS_N_INSNS (14), /* divdi */
728 COSTS_N_INSNS (8), /* fp */
729 COSTS_N_INSNS (10), /* dmul */
730 COSTS_N_INSNS (36), /* sdiv */
731 COSTS_N_INSNS (66), /* ddiv */
732 64, /* cache line size */
735 1, /* prefetch streams /*/
738 /* Instruction costs on PPCE500MC64 processors. */
740 struct processor_costs ppce500mc64_cost = {
741 COSTS_N_INSNS (4), /* mulsi */
742 COSTS_N_INSNS (4), /* mulsi_const */
743 COSTS_N_INSNS (4), /* mulsi_const9 */
744 COSTS_N_INSNS (4), /* muldi */
745 COSTS_N_INSNS (14), /* divsi */
746 COSTS_N_INSNS (14), /* divdi */
747 COSTS_N_INSNS (4), /* fp */
748 COSTS_N_INSNS (10), /* dmul */
749 COSTS_N_INSNS (36), /* sdiv */
750 COSTS_N_INSNS (66), /* ddiv */
751 64, /* cache line size */
754 1, /* prefetch streams /*/
757 /* Instruction costs on PPCE5500 processors. */
759 struct processor_costs ppce5500_cost = {
760 COSTS_N_INSNS (5), /* mulsi */
761 COSTS_N_INSNS (5), /* mulsi_const */
762 COSTS_N_INSNS (4), /* mulsi_const9 */
763 COSTS_N_INSNS (5), /* muldi */
764 COSTS_N_INSNS (14), /* divsi */
765 COSTS_N_INSNS (14), /* divdi */
766 COSTS_N_INSNS (7), /* fp */
767 COSTS_N_INSNS (10), /* dmul */
768 COSTS_N_INSNS (36), /* sdiv */
769 COSTS_N_INSNS (66), /* ddiv */
770 64, /* cache line size */
773 1, /* prefetch streams /*/
776 /* Instruction costs on PPCE6500 processors. */
778 struct processor_costs ppce6500_cost = {
779 COSTS_N_INSNS (5), /* mulsi */
780 COSTS_N_INSNS (5), /* mulsi_const */
781 COSTS_N_INSNS (4), /* mulsi_const9 */
782 COSTS_N_INSNS (5), /* muldi */
783 COSTS_N_INSNS (14), /* divsi */
784 COSTS_N_INSNS (14), /* divdi */
785 COSTS_N_INSNS (7), /* fp */
786 COSTS_N_INSNS (10), /* dmul */
787 COSTS_N_INSNS (36), /* sdiv */
788 COSTS_N_INSNS (66), /* ddiv */
789 64, /* cache line size */
792 1, /* prefetch streams /*/
795 /* Instruction costs on AppliedMicro Titan processors. */
797 struct processor_costs titan_cost = {
798 COSTS_N_INSNS (5), /* mulsi */
799 COSTS_N_INSNS (5), /* mulsi_const */
800 COSTS_N_INSNS (5), /* mulsi_const9 */
801 COSTS_N_INSNS (5), /* muldi */
802 COSTS_N_INSNS (18), /* divsi */
803 COSTS_N_INSNS (18), /* divdi */
804 COSTS_N_INSNS (10), /* fp */
805 COSTS_N_INSNS (10), /* dmul */
806 COSTS_N_INSNS (46), /* sdiv */
807 COSTS_N_INSNS (72), /* ddiv */
808 32, /* cache line size */
811 1, /* prefetch streams /*/
814 /* Instruction costs on POWER4 and POWER5 processors. */
816 struct processor_costs power4_cost = {
817 COSTS_N_INSNS (3), /* mulsi */
818 COSTS_N_INSNS (2), /* mulsi_const */
819 COSTS_N_INSNS (2), /* mulsi_const9 */
820 COSTS_N_INSNS (4), /* muldi */
821 COSTS_N_INSNS (18), /* divsi */
822 COSTS_N_INSNS (34), /* divdi */
823 COSTS_N_INSNS (3), /* fp */
824 COSTS_N_INSNS (3), /* dmul */
825 COSTS_N_INSNS (17), /* sdiv */
826 COSTS_N_INSNS (17), /* ddiv */
827 128, /* cache line size */
830 8, /* prefetch streams /*/
833 /* Instruction costs on POWER6 processors. */
835 struct processor_costs power6_cost = {
836 COSTS_N_INSNS (8), /* mulsi */
837 COSTS_N_INSNS (8), /* mulsi_const */
838 COSTS_N_INSNS (8), /* mulsi_const9 */
839 COSTS_N_INSNS (8), /* muldi */
840 COSTS_N_INSNS (22), /* divsi */
841 COSTS_N_INSNS (28), /* divdi */
842 COSTS_N_INSNS (3), /* fp */
843 COSTS_N_INSNS (3), /* dmul */
844 COSTS_N_INSNS (13), /* sdiv */
845 COSTS_N_INSNS (16), /* ddiv */
846 128, /* cache line size */
849 16, /* prefetch streams */
852 /* Instruction costs on POWER7 processors. */
854 struct processor_costs power7_cost = {
855 COSTS_N_INSNS (2), /* mulsi */
856 COSTS_N_INSNS (2), /* mulsi_const */
857 COSTS_N_INSNS (2), /* mulsi_const9 */
858 COSTS_N_INSNS (2), /* muldi */
859 COSTS_N_INSNS (18), /* divsi */
860 COSTS_N_INSNS (34), /* divdi */
861 COSTS_N_INSNS (3), /* fp */
862 COSTS_N_INSNS (3), /* dmul */
863 COSTS_N_INSNS (13), /* sdiv */
864 COSTS_N_INSNS (16), /* ddiv */
865 128, /* cache line size */
868 12, /* prefetch streams */
871 /* Instruction costs on POWER A2 processors. */
873 struct processor_costs ppca2_cost = {
874 COSTS_N_INSNS (16), /* mulsi */
875 COSTS_N_INSNS (16), /* mulsi_const */
876 COSTS_N_INSNS (16), /* mulsi_const9 */
877 COSTS_N_INSNS (16), /* muldi */
878 COSTS_N_INSNS (22), /* divsi */
879 COSTS_N_INSNS (28), /* divdi */
880 COSTS_N_INSNS (3), /* fp */
881 COSTS_N_INSNS (3), /* dmul */
882 COSTS_N_INSNS (59), /* sdiv */
883 COSTS_N_INSNS (72), /* ddiv */
887 16, /* prefetch streams */
891 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
892 #undef RS6000_BUILTIN_1
893 #undef RS6000_BUILTIN_2
894 #undef RS6000_BUILTIN_3
895 #undef RS6000_BUILTIN_A
896 #undef RS6000_BUILTIN_D
897 #undef RS6000_BUILTIN_E
898 #undef RS6000_BUILTIN_P
899 #undef RS6000_BUILTIN_Q
900 #undef RS6000_BUILTIN_S
901 #undef RS6000_BUILTIN_X
903 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
904 { NAME, ICODE, MASK, ATTR },
906 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
907 { NAME, ICODE, MASK, ATTR },
909 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
910 { NAME, ICODE, MASK, ATTR },
912 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
913 { NAME, ICODE, MASK, ATTR },
915 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
916 { NAME, ICODE, MASK, ATTR },
918 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
919 { NAME, ICODE, MASK, ATTR },
921 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
922 { NAME, ICODE, MASK, ATTR },
924 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
925 { NAME, ICODE, MASK, ATTR },
927 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
928 { NAME, ICODE, MASK, ATTR },
930 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
931 { NAME, ICODE, MASK, ATTR },
933 struct rs6000_builtin_info_type {
935 const enum insn_code icode;
940 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
942 #include "rs6000-builtin.def"
945 #undef RS6000_BUILTIN_1
946 #undef RS6000_BUILTIN_2
947 #undef RS6000_BUILTIN_3
948 #undef RS6000_BUILTIN_A
949 #undef RS6000_BUILTIN_D
950 #undef RS6000_BUILTIN_E
951 #undef RS6000_BUILTIN_P
952 #undef RS6000_BUILTIN_Q
953 #undef RS6000_BUILTIN_S
954 #undef RS6000_BUILTIN_X
956 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
957 static tree (*rs6000_veclib_handler) (tree, tree, tree);
960 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
961 static bool spe_func_has_64bit_regs_p (void);
962 static struct machine_function * rs6000_init_machine_status (void);
963 static int rs6000_ra_ever_killed (void);
964 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
965 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
966 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
967 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
968 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
969 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
970 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
971 static int rs6000_debug_address_cost (rtx, bool);
972 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
973 static bool is_microcoded_insn (rtx);
974 static bool is_nonpipeline_insn (rtx);
975 static bool is_cracked_insn (rtx);
976 static bool is_load_insn (rtx, rtx *);
977 static bool is_store_insn (rtx, rtx *);
978 static bool set_to_load_agen (rtx,rtx);
979 static bool insn_terminates_group_p (rtx , enum group_termination);
980 static bool insn_must_be_first_in_group (rtx);
981 static bool insn_must_be_last_in_group (rtx);
982 static void altivec_init_builtins (void);
983 static tree builtin_function_type (enum machine_mode, enum machine_mode,
984 enum machine_mode, enum machine_mode,
985 enum rs6000_builtins, const char *name);
986 static void rs6000_common_init_builtins (void);
987 static void paired_init_builtins (void);
988 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
989 static void spe_init_builtins (void);
990 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
991 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
992 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
993 static rs6000_stack_t *rs6000_stack_info (void);
994 static void is_altivec_return_reg (rtx, void *);
995 int easy_vector_constant (rtx, enum machine_mode);
996 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
997 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
998 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
999 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
1000 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1003 static void macho_branch_islands (void);
1005 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
1007 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
1009 static bool rs6000_mode_dependent_address (const_rtx);
1010 static bool rs6000_debug_mode_dependent_address (const_rtx);
1011 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1012 enum machine_mode, rtx);
1013 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1016 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1017 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1019 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
1021 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
1024 static bool rs6000_cannot_change_mode_class (enum machine_mode,
1027 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
1030 static bool rs6000_save_toc_in_prologue_p (void);
1032 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
1034 = rs6000_legitimize_reload_address;
1036 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1037 = rs6000_mode_dependent_address;
1039 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1040 enum machine_mode, rtx)
1041 = rs6000_secondary_reload_class;
1043 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1044 = rs6000_preferred_reload_class;
1046 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1048 = rs6000_secondary_memory_needed;
1050 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1053 = rs6000_cannot_change_mode_class;
1055 const int INSN_NOT_AVAILABLE = -1;
1057 /* Hash table stuff for keeping track of TOC entries. */
1059 struct GTY(()) toc_hash_struct
1061 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1062 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1064 enum machine_mode key_mode;
1068 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1070 /* Hash table to keep track of the argument types for builtin functions. */
1072 struct GTY(()) builtin_hash_struct
1075 enum machine_mode mode[4]; /* return value + 3 arguments. */
1076 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1079 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1082 /* Default register names. */
1083 char rs6000_reg_names[][8] =
1085 "0", "1", "2", "3", "4", "5", "6", "7",
1086 "8", "9", "10", "11", "12", "13", "14", "15",
1087 "16", "17", "18", "19", "20", "21", "22", "23",
1088 "24", "25", "26", "27", "28", "29", "30", "31",
1089 "0", "1", "2", "3", "4", "5", "6", "7",
1090 "8", "9", "10", "11", "12", "13", "14", "15",
1091 "16", "17", "18", "19", "20", "21", "22", "23",
1092 "24", "25", "26", "27", "28", "29", "30", "31",
1093 "mq", "lr", "ctr","ap",
1094 "0", "1", "2", "3", "4", "5", "6", "7",
1096 /* AltiVec registers. */
1097 "0", "1", "2", "3", "4", "5", "6", "7",
1098 "8", "9", "10", "11", "12", "13", "14", "15",
1099 "16", "17", "18", "19", "20", "21", "22", "23",
1100 "24", "25", "26", "27", "28", "29", "30", "31",
1102 /* SPE registers. */
1103 "spe_acc", "spefscr",
1104 /* Soft frame pointer. */
1108 #ifdef TARGET_REGNAMES
1109 static const char alt_reg_names[][8] =
1111 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1112 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1113 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1114 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1115 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1116 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1117 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1118 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1119 "mq", "lr", "ctr", "ap",
1120 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1122 /* AltiVec registers. */
1123 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1124 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1125 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1126 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1128 /* SPE registers. */
1129 "spe_acc", "spefscr",
1130 /* Soft frame pointer. */
1135 /* Table of valid machine attributes. */
1137 static const struct attribute_spec rs6000_attribute_table[] =
1139 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1140 affects_type_identity } */
1141 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1143 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1145 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1147 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1149 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1151 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1152 SUBTARGET_ATTRIBUTE_TABLE,
1154 { NULL, 0, 0, false, false, false, NULL, false }
1157 #ifndef MASK_STRICT_ALIGN
1158 #define MASK_STRICT_ALIGN 0
1160 #ifndef TARGET_PROFILE_KERNEL
1161 #define TARGET_PROFILE_KERNEL 0
1164 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1165 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1167 /* Initialize the GCC target structure. */
1168 #undef TARGET_ATTRIBUTE_TABLE
1169 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1170 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1171 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1172 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1173 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1175 #undef TARGET_ASM_ALIGNED_DI_OP
1176 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1178 /* Default unaligned ops are only provided for ELF. Find the ops needed
1179 for non-ELF systems. */
1180 #ifndef OBJECT_FORMAT_ELF
1182 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1184 #undef TARGET_ASM_UNALIGNED_HI_OP
1185 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1186 #undef TARGET_ASM_UNALIGNED_SI_OP
1187 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1188 #undef TARGET_ASM_UNALIGNED_DI_OP
1189 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1192 #undef TARGET_ASM_UNALIGNED_HI_OP
1193 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1194 #undef TARGET_ASM_UNALIGNED_SI_OP
1195 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1196 #undef TARGET_ASM_UNALIGNED_DI_OP
1197 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1198 #undef TARGET_ASM_ALIGNED_DI_OP
1199 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1203 /* This hook deals with fixups for relocatable code and DI-mode objects
1205 #undef TARGET_ASM_INTEGER
1206 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1208 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1209 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1210 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1213 #undef TARGET_SET_UP_BY_PROLOGUE
1214 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1216 #undef TARGET_HAVE_TLS
1217 #define TARGET_HAVE_TLS HAVE_AS_TLS
1219 #undef TARGET_CANNOT_FORCE_CONST_MEM
1220 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1222 #undef TARGET_DELEGITIMIZE_ADDRESS
1223 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1225 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1226 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1228 #undef TARGET_ASM_FUNCTION_PROLOGUE
1229 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1230 #undef TARGET_ASM_FUNCTION_EPILOGUE
1231 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1233 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1234 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1236 #undef TARGET_LEGITIMIZE_ADDRESS
1237 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1239 #undef TARGET_SCHED_VARIABLE_ISSUE
1240 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1242 #undef TARGET_SCHED_ISSUE_RATE
1243 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1244 #undef TARGET_SCHED_ADJUST_COST
1245 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1246 #undef TARGET_SCHED_ADJUST_PRIORITY
1247 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1248 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1249 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1250 #undef TARGET_SCHED_INIT
1251 #define TARGET_SCHED_INIT rs6000_sched_init
1252 #undef TARGET_SCHED_FINISH
1253 #define TARGET_SCHED_FINISH rs6000_sched_finish
1254 #undef TARGET_SCHED_REORDER
1255 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1256 #undef TARGET_SCHED_REORDER2
1257 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1259 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1260 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1262 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1263 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1265 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1266 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1267 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1268 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1269 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1270 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1271 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1272 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1274 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1275 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1276 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1277 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1278 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1279 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1280 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1281 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1282 rs6000_builtin_support_vector_misalignment
1283 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1284 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1285 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1286 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1287 rs6000_builtin_vectorization_cost
1288 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1289 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1290 rs6000_preferred_simd_mode
1292 #undef TARGET_INIT_BUILTINS
1293 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1294 #undef TARGET_BUILTIN_DECL
1295 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1297 #undef TARGET_EXPAND_BUILTIN
1298 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1300 #undef TARGET_MANGLE_TYPE
1301 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1303 #undef TARGET_INIT_LIBFUNCS
1304 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1307 #undef TARGET_BINDS_LOCAL_P
1308 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1311 #undef TARGET_MS_BITFIELD_LAYOUT_P
1312 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1314 #undef TARGET_ASM_OUTPUT_MI_THUNK
1315 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1317 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1318 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1320 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1321 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1323 #undef TARGET_INVALID_WITHIN_DOLOOP
1324 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1326 #undef TARGET_REGISTER_MOVE_COST
1327 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1328 #undef TARGET_MEMORY_MOVE_COST
1329 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1330 #undef TARGET_RTX_COSTS
1331 #define TARGET_RTX_COSTS rs6000_rtx_costs
1332 #undef TARGET_ADDRESS_COST
1333 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1335 #undef TARGET_DWARF_REGISTER_SPAN
1336 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1338 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1339 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1341 /* On rs6000, function arguments are promoted, as are function return
1343 #undef TARGET_PROMOTE_FUNCTION_MODE
1344 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1346 #undef TARGET_RETURN_IN_MEMORY
1347 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1349 #undef TARGET_SETUP_INCOMING_VARARGS
1350 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1352 /* Always strict argument naming on rs6000. */
1353 #undef TARGET_STRICT_ARGUMENT_NAMING
1354 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1355 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1356 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1357 #undef TARGET_SPLIT_COMPLEX_ARG
1358 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1359 #undef TARGET_MUST_PASS_IN_STACK
1360 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1361 #undef TARGET_PASS_BY_REFERENCE
1362 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1363 #undef TARGET_ARG_PARTIAL_BYTES
1364 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1365 #undef TARGET_FUNCTION_ARG_ADVANCE
1366 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1367 #undef TARGET_FUNCTION_ARG
1368 #define TARGET_FUNCTION_ARG rs6000_function_arg
1369 #undef TARGET_FUNCTION_ARG_BOUNDARY
1370 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1372 #undef TARGET_BUILD_BUILTIN_VA_LIST
1373 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1375 #undef TARGET_EXPAND_BUILTIN_VA_START
1376 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1378 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1379 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1381 #undef TARGET_EH_RETURN_FILTER_MODE
1382 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1384 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1385 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1387 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1388 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1390 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1391 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1393 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1394 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1396 #undef TARGET_OPTION_OVERRIDE
1397 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1399 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1400 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1401 rs6000_builtin_vectorized_function
1404 #undef TARGET_STACK_PROTECT_FAIL
1405 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1408 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1409 The PowerPC architecture requires only weak consistency among
1410 processors--that is, memory accesses between processors need not be
1411 sequentially consistent and memory accesses among processors can occur
1412 in any order. The ability to order memory accesses weakly provides
1413 opportunities for more efficient use of the system bus. Unless a
1414 dependency exists, the 604e allows read operations to precede store
1416 #undef TARGET_RELAXED_ORDERING
1417 #define TARGET_RELAXED_ORDERING true
1420 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1421 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1424 /* Use a 32-bit anchor range. This leads to sequences like:
1426 addis tmp,anchor,high
1429 where tmp itself acts as an anchor, and can be shared between
1430 accesses to the same 64k page. */
1431 #undef TARGET_MIN_ANCHOR_OFFSET
1432 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1433 #undef TARGET_MAX_ANCHOR_OFFSET
1434 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1435 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1436 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1438 #undef TARGET_BUILTIN_RECIPROCAL
1439 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1441 #undef TARGET_EXPAND_TO_RTL_HOOK
1442 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1444 #undef TARGET_INSTANTIATE_DECLS
1445 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1447 #undef TARGET_SECONDARY_RELOAD
1448 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1450 #undef TARGET_LEGITIMATE_ADDRESS_P
1451 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1453 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1454 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1456 #undef TARGET_CAN_ELIMINATE
1457 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1459 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1460 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1462 #undef TARGET_TRAMPOLINE_INIT
1463 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1465 #undef TARGET_FUNCTION_VALUE
1466 #define TARGET_FUNCTION_VALUE rs6000_function_value
1468 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1469 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1471 #undef TARGET_OPTION_SAVE
1472 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1474 #undef TARGET_OPTION_RESTORE
1475 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1477 #undef TARGET_OPTION_PRINT
1478 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1480 #undef TARGET_CAN_INLINE_P
1481 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1483 #undef TARGET_SET_CURRENT_FUNCTION
1484 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1486 #undef TARGET_LEGITIMATE_CONSTANT_P
1487 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1489 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1490 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1493 /* Simplifications for entries below. */
1496 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1497 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1500 /* Some OSs don't support saving the high part of 64-bit registers on context
1501 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1502 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1503 either, the user must explicitly specify them and we won't interfere with
1504 the user's specification. */
1507 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1508 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1509 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1510 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1511 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
1512 | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
1513 | MASK_RECIP_PRECISION)
1516 /* Masks for instructions set at various powerpc ISAs. */
1518 ISA_2_1_MASKS = MASK_MFCRF,
1519 ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
1520 ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
1522 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1523 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1524 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1525 server and embedded. */
1526 ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
1527 | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
1528 ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
1530 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1531 altivec is a win so enable it. */
1532 ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
1533 ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
1539 const char *const name; /* Canonical processor name. */
1540 const enum processor_type processor; /* Processor type enum value. */
1541 const int target_enable; /* Target flags to enable. */
1544 static struct rs6000_ptt const processor_target_table[] =
1546 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1547 #include "rs6000-cpus.def"
1551 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1555 rs6000_cpu_name_lookup (const char *name)
1561 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1562 if (! strcmp (name, processor_target_table[i].name))
1570 /* Return number of consecutive hard regs needed starting at reg REGNO
1571 to hold something of mode MODE.
1572 This is ordinarily the length in words of a value of mode MODE
1573 but can be less for certain modes in special long registers.
1575 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1576 scalar instructions. The upper 32 bits are only available to the
1579 POWER and PowerPC GPRs hold 32 bits worth;
1580 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1583 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1585 unsigned HOST_WIDE_INT reg_size;
1587 if (FP_REGNO_P (regno))
1588 reg_size = (VECTOR_MEM_VSX_P (mode)
1589 ? UNITS_PER_VSX_WORD
1590 : UNITS_PER_FP_WORD);
1592 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1593 reg_size = UNITS_PER_SPE_WORD;
1595 else if (ALTIVEC_REGNO_P (regno))
1596 reg_size = UNITS_PER_ALTIVEC_WORD;
1598 /* The value returned for SCmode in the E500 double case is 2 for
1599 ABI compatibility; storing an SCmode value in a single register
1600 would require function_arg and rs6000_spe_function_arg to handle
1601 SCmode so as to pass the value correctly in a pair of
1603 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1604 && !DECIMAL_FLOAT_MODE_P (mode))
1605 reg_size = UNITS_PER_FP_WORD;
1608 reg_size = UNITS_PER_WORD;
1610 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1613 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1616 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1618 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1620 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1621 implementations. Don't allow an item to be split between a FP register
1622 and an Altivec register. */
1623 if (VECTOR_MEM_VSX_P (mode))
1625 if (FP_REGNO_P (regno))
1626 return FP_REGNO_P (last_regno);
1628 if (ALTIVEC_REGNO_P (regno))
1629 return ALTIVEC_REGNO_P (last_regno);
1632 /* The GPRs can hold any mode, but values bigger than one register
1633 cannot go past R31. */
1634 if (INT_REGNO_P (regno))
1635 return INT_REGNO_P (last_regno);
1637 /* The float registers (except for VSX vector modes) can only hold floating
1638 modes and DImode. This excludes the 32-bit decimal float mode for
1640 if (FP_REGNO_P (regno))
1642 if (SCALAR_FLOAT_MODE_P (mode)
1643 && (mode != TDmode || (regno % 2) == 0)
1644 && FP_REGNO_P (last_regno))
1647 if (GET_MODE_CLASS (mode) == MODE_INT
1648 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1651 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1652 && PAIRED_VECTOR_MODE (mode))
1658 /* The CR register can only hold CC modes. */
1659 if (CR_REGNO_P (regno))
1660 return GET_MODE_CLASS (mode) == MODE_CC;
1662 if (CA_REGNO_P (regno))
1663 return mode == BImode;
1665 /* AltiVec only in AldyVec registers. */
1666 if (ALTIVEC_REGNO_P (regno))
1667 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1669 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1670 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1673 /* We cannot put TImode anywhere except general register and it must be able
1674 to fit within the register set. In the future, allow TImode in the
1675 Altivec or VSX registers. */
1677 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1680 /* Print interesting facts about registers. */
1682 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1686 for (r = first_regno; r <= last_regno; ++r)
1688 const char *comma = "";
1691 if (first_regno == last_regno)
1692 fprintf (stderr, "%s:\t", reg_name);
1694 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1697 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1698 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1702 fprintf (stderr, ",\n\t");
1707 if (rs6000_hard_regno_nregs[m][r] > 1)
1708 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1709 rs6000_hard_regno_nregs[m][r]);
1711 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1716 if (call_used_regs[r])
1720 fprintf (stderr, ",\n\t");
1725 len += fprintf (stderr, "%s%s", comma, "call-used");
1733 fprintf (stderr, ",\n\t");
1738 len += fprintf (stderr, "%s%s", comma, "fixed");
1744 fprintf (stderr, ",\n\t");
1748 fprintf (stderr, "%sregno = %d\n", comma, r);
1752 #define DEBUG_FMT_D "%-32s= %d\n"
1753 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1754 #define DEBUG_FMT_S "%-32s= %s\n"
1756 /* Print various interesting information with -mdebug=reg. */
1758 rs6000_debug_reg_global (void)
1760 static const char *const tf[2] = { "false", "true" };
1761 const char *nl = (const char *)0;
1763 char costly_num[20];
1765 const char *costly_str;
1766 const char *nop_str;
1767 const char *trace_str;
1768 const char *abi_str;
1769 const char *cmodel_str;
1771 /* Map enum rs6000_vector to string. */
1772 static const char *rs6000_debug_vector_unit[] = {
1781 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1782 LAST_VIRTUAL_REGISTER);
1783 rs6000_debug_reg_print (0, 31, "gr");
1784 rs6000_debug_reg_print (32, 63, "fp");
1785 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1788 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1789 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1790 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1791 rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
1792 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1793 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1794 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1795 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1796 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1800 "d reg_class = %s\n"
1801 "f reg_class = %s\n"
1802 "v reg_class = %s\n"
1803 "wa reg_class = %s\n"
1804 "wd reg_class = %s\n"
1805 "wf reg_class = %s\n"
1806 "ws reg_class = %s\n\n",
1807 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1808 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1809 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1810 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1811 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1812 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1813 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1815 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1816 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1819 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1821 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1822 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
1828 if (rs6000_recip_control)
1830 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
1832 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1833 if (rs6000_recip_bits[m])
1836 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1838 (RS6000_RECIP_AUTO_RE_P (m)
1840 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
1841 (RS6000_RECIP_AUTO_RSQRTE_P (m)
1843 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
1846 fputs ("\n", stderr);
1849 if (rs6000_cpu_index >= 0)
1850 fprintf (stderr, DEBUG_FMT_S, "cpu",
1851 processor_target_table[rs6000_cpu_index].name);
1853 if (rs6000_tune_index >= 0)
1854 fprintf (stderr, DEBUG_FMT_S, "tune",
1855 processor_target_table[rs6000_tune_index].name);
1857 switch (rs6000_sched_costly_dep)
1859 case max_dep_latency:
1860 costly_str = "max_dep_latency";
1864 costly_str = "no_dep_costly";
1867 case all_deps_costly:
1868 costly_str = "all_deps_costly";
1871 case true_store_to_load_dep_costly:
1872 costly_str = "true_store_to_load_dep_costly";
1875 case store_to_load_dep_costly:
1876 costly_str = "store_to_load_dep_costly";
1880 costly_str = costly_num;
1881 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
1885 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
1887 switch (rs6000_sched_insert_nops)
1889 case sched_finish_regroup_exact:
1890 nop_str = "sched_finish_regroup_exact";
1893 case sched_finish_pad_groups:
1894 nop_str = "sched_finish_pad_groups";
1897 case sched_finish_none:
1898 nop_str = "sched_finish_none";
1903 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
1907 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
1909 switch (rs6000_sdata)
1916 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
1920 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
1924 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
1929 switch (rs6000_traceback)
1931 case traceback_default: trace_str = "default"; break;
1932 case traceback_none: trace_str = "none"; break;
1933 case traceback_part: trace_str = "part"; break;
1934 case traceback_full: trace_str = "full"; break;
1935 default: trace_str = "unknown"; break;
1938 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
1940 switch (rs6000_current_cmodel)
1942 case CMODEL_SMALL: cmodel_str = "small"; break;
1943 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
1944 case CMODEL_LARGE: cmodel_str = "large"; break;
1945 default: cmodel_str = "unknown"; break;
1948 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
1950 switch (rs6000_current_abi)
1952 case ABI_NONE: abi_str = "none"; break;
1953 case ABI_AIX: abi_str = "aix"; break;
1954 case ABI_V4: abi_str = "V4"; break;
1955 case ABI_DARWIN: abi_str = "darwin"; break;
1956 default: abi_str = "unknown"; break;
1959 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
1961 if (rs6000_altivec_abi)
1962 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
1965 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
1967 if (rs6000_darwin64_abi)
1968 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
1970 if (rs6000_float_gprs)
1971 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
1973 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
1974 fprintf (stderr, DEBUG_FMT_S, "align_branch",
1975 tf[!!rs6000_align_branch_targets]);
1976 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
1977 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
1978 rs6000_long_double_type_size);
1979 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
1980 (int)rs6000_sched_restricted_insns_priority);
1981 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
1983 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
1984 (int)RS6000_BUILTIN_COUNT);
1985 fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
1988 /* Initialize the various global tables that are based on register size. */
1990 rs6000_init_hard_regno_mode_ok (bool global_init_p)
1996 /* Precalculate REGNO_REG_CLASS. */
1997 rs6000_regno_regclass[0] = GENERAL_REGS;
1998 for (r = 1; r < 32; ++r)
1999 rs6000_regno_regclass[r] = BASE_REGS;
2001 for (r = 32; r < 64; ++r)
2002 rs6000_regno_regclass[r] = FLOAT_REGS;
2004 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2005 rs6000_regno_regclass[r] = NO_REGS;
2007 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2008 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2010 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2011 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2012 rs6000_regno_regclass[r] = CR_REGS;
2014 rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
2015 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2016 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2017 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
2018 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2019 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2020 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
2021 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
2022 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2023 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2025 /* Precalculate vector information, this must be set up before the
2026 rs6000_hard_regno_nregs_internal below. */
2027 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2029 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2030 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2031 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2034 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2035 rs6000_constraints[c] = NO_REGS;
2037 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2038 believes it can use native alignment or still uses 128-bit alignment. */
2039 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2050 /* V2DF mode, VSX only. */
2053 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2054 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2055 rs6000_vector_align[V2DFmode] = align64;
2058 /* V4SF mode, either VSX or Altivec. */
2061 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2062 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2063 rs6000_vector_align[V4SFmode] = align32;
2065 else if (TARGET_ALTIVEC)
2067 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2068 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2069 rs6000_vector_align[V4SFmode] = align32;
2072 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2076 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2077 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2078 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2079 rs6000_vector_align[V4SImode] = align32;
2080 rs6000_vector_align[V8HImode] = align32;
2081 rs6000_vector_align[V16QImode] = align32;
2085 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2086 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2087 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2091 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2092 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2093 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2097 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2098 Altivec doesn't have 64-bit support. */
2101 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2102 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2103 rs6000_vector_align[V2DImode] = align64;
2106 /* DFmode, see if we want to use the VSX unit. */
2107 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2109 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2110 rs6000_vector_mem[DFmode]
2111 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2112 rs6000_vector_align[DFmode] = align64;
2115 /* TODO add SPE and paired floating point vector support. */
2117 /* Register class constraints for the constraints that depend on compile
2119 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2120 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2122 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2123 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2127 /* At present, we just use VSX_REGS, but we have different constraints
2128 based on the use, in case we want to fine tune the default register
2129 class used. wa = any VSX register, wf = register class to use for
2130 V4SF, wd = register class to use for V2DF, and ws = register classs to
2131 use for DF scalars. */
2132 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2133 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2134 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2135 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2141 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2143 /* Set up the reload helper functions. */
2144 if (TARGET_VSX || TARGET_ALTIVEC)
2148 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2149 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2150 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2151 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2152 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2153 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2154 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2155 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2156 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2157 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2158 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2159 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2160 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2162 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
2163 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
2168 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2169 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2170 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2171 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2172 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2173 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2174 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2175 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2176 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2177 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2178 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2179 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2180 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2182 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
2183 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
2188 /* Precalculate HARD_REGNO_NREGS. */
2189 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2190 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2191 rs6000_hard_regno_nregs[m][r]
2192 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2194 /* Precalculate HARD_REGNO_MODE_OK. */
2195 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2196 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2197 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2198 rs6000_hard_regno_mode_ok_p[m][r] = true;
2200 /* Precalculate CLASS_MAX_NREGS sizes. */
2201 for (c = 0; c < LIM_REG_CLASSES; ++c)
2205 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2206 reg_size = UNITS_PER_VSX_WORD;
2208 else if (c == ALTIVEC_REGS)
2209 reg_size = UNITS_PER_ALTIVEC_WORD;
2211 else if (c == FLOAT_REGS)
2212 reg_size = UNITS_PER_FP_WORD;
2215 reg_size = UNITS_PER_WORD;
2217 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2218 rs6000_class_max_nregs[m][c]
2219 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2222 if (TARGET_E500_DOUBLE)
2223 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2225 /* Calculate which modes to automatically generate code to use a the
2226 reciprocal divide and square root instructions. In the future, possibly
2227 automatically generate the instructions even if the user did not specify
2228 -mrecip. The older machines double precision reciprocal sqrt estimate is
2229 not accurate enough. */
2230 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2232 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2234 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2235 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2236 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2237 if (VECTOR_UNIT_VSX_P (V2DFmode))
2238 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2240 if (TARGET_FRSQRTES)
2241 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2243 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2244 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2245 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2246 if (VECTOR_UNIT_VSX_P (V2DFmode))
2247 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2249 if (rs6000_recip_control)
2251 if (!flag_finite_math_only)
2252 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2253 if (flag_trapping_math)
2254 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2255 if (!flag_reciprocal_math)
2256 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2257 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2259 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2260 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2261 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2263 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2264 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2265 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2267 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2268 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2269 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2271 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2272 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2273 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2275 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2276 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2277 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2279 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2280 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2281 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2283 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2284 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2285 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2287 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2288 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2289 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2293 if (global_init_p || TARGET_DEBUG_TARGET)
2295 if (TARGET_DEBUG_REG)
2296 rs6000_debug_reg_global ();
2298 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2300 "SImode variable mult cost = %d\n"
2301 "SImode constant mult cost = %d\n"
2302 "SImode short constant mult cost = %d\n"
2303 "DImode multipliciation cost = %d\n"
2304 "SImode division cost = %d\n"
2305 "DImode division cost = %d\n"
2306 "Simple fp operation cost = %d\n"
2307 "DFmode multiplication cost = %d\n"
2308 "SFmode division cost = %d\n"
2309 "DFmode division cost = %d\n"
2310 "cache line size = %d\n"
2311 "l1 cache size = %d\n"
2312 "l2 cache size = %d\n"
2313 "simultaneous prefetches = %d\n"
2316 rs6000_cost->mulsi_const,
2317 rs6000_cost->mulsi_const9,
2325 rs6000_cost->cache_line_size,
2326 rs6000_cost->l1_cache_size,
2327 rs6000_cost->l2_cache_size,
2328 rs6000_cost->simultaneous_prefetches);
2333 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2336 darwin_rs6000_override_options (void)
2338 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2340 rs6000_altivec_abi = 1;
2341 TARGET_ALTIVEC_VRSAVE = 1;
2342 rs6000_current_abi = ABI_DARWIN;
2344 if (DEFAULT_ABI == ABI_DARWIN
2346 darwin_one_byte_bool = 1;
2348 if (TARGET_64BIT && ! TARGET_POWERPC64)
2350 target_flags |= MASK_POWERPC64;
2351 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2355 rs6000_default_long_calls = 1;
2356 target_flags |= MASK_SOFT_FLOAT;
2359 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2361 if (!flag_mkernel && !flag_apple_kext
2363 && ! (target_flags_explicit & MASK_ALTIVEC))
2364 target_flags |= MASK_ALTIVEC;
2366 /* Unless the user (not the configurer) has explicitly overridden
2367 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2368 G4 unless targeting the kernel. */
2371 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2372 && ! (target_flags_explicit & MASK_ALTIVEC)
2373 && ! global_options_set.x_rs6000_cpu_index)
2375 target_flags |= MASK_ALTIVEC;
2380 /* If not otherwise specified by a target, make 'long double' equivalent to
2383 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2384 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2387 /* Return the builtin mask of the various options used that could affect which
2388 builtins were used. In the past we used target_flags, but we've run out of
2389 bits, and some options like SPE and PAIRED are no longer in
2393 rs6000_builtin_mask_calculate (void)
2395 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2396 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2397 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2398 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2399 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2400 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2401 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2402 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2403 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2404 | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0)
2405 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2408 /* Override command line options. Mostly we process the processor type and
2409 sometimes adjust other TARGET_ options. */
2412 rs6000_option_override_internal (bool global_init_p)
2415 bool have_cpu = false;
2417 /* The default cpu requested at configure time, if any. */
2418 const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
2423 struct cl_target_option *main_target_opt
2424 = ((global_init_p || target_option_default_node == NULL)
2425 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2427 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2428 library functions, so warn about it. The flag may be useful for
2429 performance studies from time to time though, so don't disable it
2431 if (global_options_set.x_rs6000_alignment_flags
2432 && rs6000_alignment_flags == MASK_ALIGN_POWER
2433 && DEFAULT_ABI == ABI_DARWIN
2435 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2436 " it is incompatible with the installed C and C++ libraries");
2438 /* Numerous experiment shows that IRA based loop pressure
2439 calculation works better for RTL loop invariant motion on targets
2440 with enough (>= 32) registers. It is an expensive optimization.
2441 So it is on only for peak performance. */
2442 if (optimize >= 3 && global_init_p)
2443 flag_ira_loop_pressure = 1;
2445 /* Set the pointer size. */
2448 rs6000_pmode = (int)DImode;
2449 rs6000_pointer_size = 64;
2453 rs6000_pmode = (int)SImode;
2454 rs6000_pointer_size = 32;
2457 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
2458 #ifdef OS_MISSING_POWERPC64
2459 if (OS_MISSING_POWERPC64)
2460 set_masks &= ~MASK_POWERPC64;
2462 #ifdef OS_MISSING_ALTIVEC
2463 if (OS_MISSING_ALTIVEC)
2464 set_masks &= ~MASK_ALTIVEC;
2467 /* Don't override by the processor default if given explicitly. */
2468 set_masks &= ~target_flags_explicit;
2470 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2471 the cpu in a target attribute or pragma, but did not specify a tuning
2472 option, use the cpu for the tuning option rather than the option specified
2473 with -mtune on the command line. Process a '--with-cpu' configuration
2474 request as an implicit --cpu. */
2475 if (rs6000_cpu_index >= 0)
2477 cpu_index = rs6000_cpu_index;
2480 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
2482 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2487 const char *default_cpu =
2488 (implicit_cpu ? implicit_cpu
2489 : (TARGET_POWERPC64 ? "powerpc64" : "powerpc"));
2491 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2492 have_cpu = implicit_cpu != 0;
2495 gcc_assert (cpu_index >= 0);
2497 target_flags &= ~set_masks;
2498 target_flags |= (processor_target_table[cpu_index].target_enable
2501 if (rs6000_tune_index >= 0)
2502 tune_index = rs6000_tune_index;
2504 rs6000_tune_index = tune_index = cpu_index;
2508 enum processor_type tune_proc
2509 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
2512 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2513 if (processor_target_table[i].processor == tune_proc)
2515 rs6000_tune_index = tune_index = i;
2520 gcc_assert (tune_index >= 0);
2521 rs6000_cpu = processor_target_table[tune_index].processor;
2523 /* Pick defaults for SPE related control flags. Do this early to make sure
2524 that the TARGET_ macros are representative ASAP. */
2526 int spe_capable_cpu =
2527 (rs6000_cpu == PROCESSOR_PPC8540
2528 || rs6000_cpu == PROCESSOR_PPC8548);
2530 if (!global_options_set.x_rs6000_spe_abi)
2531 rs6000_spe_abi = spe_capable_cpu;
2533 if (!global_options_set.x_rs6000_spe)
2534 rs6000_spe = spe_capable_cpu;
2536 if (!global_options_set.x_rs6000_float_gprs)
2538 (rs6000_cpu == PROCESSOR_PPC8540 ? 1
2539 : rs6000_cpu == PROCESSOR_PPC8548 ? 2
2543 if (global_options_set.x_rs6000_spe_abi
2546 error ("not configured for SPE ABI");
2548 if (global_options_set.x_rs6000_spe
2551 error ("not configured for SPE instruction set");
2553 if (main_target_opt != NULL
2554 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2555 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2556 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2557 error ("target attribute or pragma changes SPE ABI");
2559 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2560 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
2561 || rs6000_cpu == PROCESSOR_PPCE5500)
2564 error ("AltiVec not supported in this target");
2566 error ("SPE not supported in this target");
2568 if (rs6000_cpu == PROCESSOR_PPCE6500)
2571 error ("SPE not supported in this target");
2574 /* Disable Cell microcode if we are optimizing for the Cell
2575 and not optimizing for size. */
2576 if (rs6000_gen_cell_microcode == -1)
2577 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2580 /* If we are optimizing big endian systems for space and it's OK to
2581 use instructions that would be microcoded on the Cell, use the
2582 load/store multiple and string instructions. */
2583 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2584 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
2586 /* Don't allow -mmultiple or -mstring on little endian systems
2587 unless the cpu is a 750, because the hardware doesn't support the
2588 instructions used in little endian mode, and causes an alignment
2589 trap. The 750 does not cause an alignment trap (except when the
2590 target is unaligned). */
2592 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2594 if (TARGET_MULTIPLE)
2596 target_flags &= ~MASK_MULTIPLE;
2597 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
2598 warning (0, "-mmultiple is not supported on little endian systems");
2603 target_flags &= ~MASK_STRING;
2604 if ((target_flags_explicit & MASK_STRING) != 0)
2605 warning (0, "-mstring is not supported on little endian systems");
2609 /* Add some warnings for VSX. */
2612 const char *msg = NULL;
2613 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2614 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2616 if (target_flags_explicit & MASK_VSX)
2617 msg = N_("-mvsx requires hardware floating point");
2619 target_flags &= ~ MASK_VSX;
2621 else if (TARGET_PAIRED_FLOAT)
2622 msg = N_("-mvsx and -mpaired are incompatible");
2623 /* The hardware will allow VSX and little endian, but until we make sure
2624 things like vector select, etc. work don't allow VSX on little endian
2625 systems at this point. */
2626 else if (!BYTES_BIG_ENDIAN)
2627 msg = N_("-mvsx used with little endian code");
2628 else if (TARGET_AVOID_XFORM > 0)
2629 msg = N_("-mvsx needs indexed addressing");
2630 else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
2632 if (target_flags_explicit & MASK_VSX)
2633 msg = N_("-mvsx and -mno-altivec are incompatible");
2635 msg = N_("-mno-altivec disables vsx");
2641 target_flags &= ~ MASK_VSX;
2642 target_flags_explicit |= MASK_VSX;
2646 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2647 unless the user explicitly used the -mno-<option> to disable the code. */
2649 target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
2650 else if (TARGET_POPCNTD)
2651 target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
2652 else if (TARGET_DFP)
2653 target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
2654 else if (TARGET_CMPB)
2655 target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
2656 else if (TARGET_FPRND)
2657 target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
2658 else if (TARGET_POPCNTB)
2659 target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
2660 else if (TARGET_ALTIVEC)
2661 target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
2663 /* E500mc does "better" if we inline more aggressively. Respect the
2664 user's opinion, though. */
2665 if (rs6000_block_move_inline_limit == 0
2666 && (rs6000_cpu == PROCESSOR_PPCE500MC
2667 || rs6000_cpu == PROCESSOR_PPCE500MC64
2668 || rs6000_cpu == PROCESSOR_PPCE5500
2669 || rs6000_cpu == PROCESSOR_PPCE6500))
2670 rs6000_block_move_inline_limit = 128;
2672 /* store_one_arg depends on expand_block_move to handle at least the
2673 size of reg_parm_stack_space. */
2674 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2675 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2679 /* If the appropriate debug option is enabled, replace the target hooks
2680 with debug versions that call the real version and then prints
2681 debugging information. */
2682 if (TARGET_DEBUG_COST)
2684 targetm.rtx_costs = rs6000_debug_rtx_costs;
2685 targetm.address_cost = rs6000_debug_address_cost;
2686 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2689 if (TARGET_DEBUG_ADDR)
2691 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2692 targetm.legitimize_address = rs6000_debug_legitimize_address;
2693 rs6000_secondary_reload_class_ptr
2694 = rs6000_debug_secondary_reload_class;
2695 rs6000_secondary_memory_needed_ptr
2696 = rs6000_debug_secondary_memory_needed;
2697 rs6000_cannot_change_mode_class_ptr
2698 = rs6000_debug_cannot_change_mode_class;
2699 rs6000_preferred_reload_class_ptr
2700 = rs6000_debug_preferred_reload_class;
2701 rs6000_legitimize_reload_address_ptr
2702 = rs6000_debug_legitimize_reload_address;
2703 rs6000_mode_dependent_address_ptr
2704 = rs6000_debug_mode_dependent_address;
2707 if (rs6000_veclibabi_name)
2709 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2710 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2713 error ("unknown vectorization library ABI type (%s) for "
2714 "-mveclibabi= switch", rs6000_veclibabi_name);
2720 if (!global_options_set.x_rs6000_long_double_type_size)
2722 if (main_target_opt != NULL
2723 && (main_target_opt->x_rs6000_long_double_type_size
2724 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2725 error ("target attribute or pragma changes long double size");
2727 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2730 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2731 if (!global_options_set.x_rs6000_ieeequad)
2732 rs6000_ieeequad = 1;
2735 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2736 target attribute or pragma which automatically enables both options,
2737 unless the altivec ABI was set. This is set by default for 64-bit, but
2739 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2740 target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
2742 /* Enable Altivec ABI for AIX -maltivec. */
2743 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2745 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2746 error ("target attribute or pragma changes AltiVec ABI");
2748 rs6000_altivec_abi = 1;
2751 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2752 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2753 be explicitly overridden in either case. */
2756 if (!global_options_set.x_rs6000_altivec_abi
2757 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2759 if (main_target_opt != NULL &&
2760 !main_target_opt->x_rs6000_altivec_abi)
2761 error ("target attribute or pragma changes AltiVec ABI");
2763 rs6000_altivec_abi = 1;
2766 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2767 if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE)
2768 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
2771 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2772 So far, the only darwin64 targets are also MACH-O. */
2774 && DEFAULT_ABI == ABI_DARWIN
2777 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2778 error ("target attribute or pragma changes darwin64 ABI");
2781 rs6000_darwin64_abi = 1;
2782 /* Default to natural alignment, for better performance. */
2783 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2787 /* Place FP constants in the constant pool instead of TOC
2788 if section anchors enabled. */
2789 if (flag_section_anchors)
2790 TARGET_NO_FP_IN_TOC = 1;
2792 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2793 SUBTARGET_OVERRIDE_OPTIONS;
2795 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2796 SUBSUBTARGET_OVERRIDE_OPTIONS;
2798 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2799 SUB3TARGET_OVERRIDE_OPTIONS;
2802 /* For the E500 family of cores, reset the single/double FP flags to let us
2803 check that they remain constant across attributes or pragmas. Also,
2804 clear a possible request for string instructions, not supported and which
2805 we might have silently queried above for -Os.
2807 For other families, clear ISEL in case it was set implicitly.
2812 case PROCESSOR_PPC8540:
2813 case PROCESSOR_PPC8548:
2814 case PROCESSOR_PPCE500MC:
2815 case PROCESSOR_PPCE500MC64:
2816 case PROCESSOR_PPCE5500:
2817 case PROCESSOR_PPCE6500:
2819 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
2820 rs6000_double_float = TARGET_E500_DOUBLE;
2822 target_flags &= ~MASK_STRING;
2828 if (have_cpu && !(target_flags_explicit & MASK_ISEL))
2829 target_flags &= ~MASK_ISEL;
2834 if (main_target_opt)
2836 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
2837 error ("target attribute or pragma changes single precision floating "
2839 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
2840 error ("target attribute or pragma changes double precision floating "
2844 /* Detect invalid option combinations with E500. */
2847 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2848 && rs6000_cpu != PROCESSOR_POWER5
2849 && rs6000_cpu != PROCESSOR_POWER6
2850 && rs6000_cpu != PROCESSOR_POWER7
2851 && rs6000_cpu != PROCESSOR_PPCA2
2852 && rs6000_cpu != PROCESSOR_CELL
2853 && rs6000_cpu != PROCESSOR_PPC476);
2854 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2855 || rs6000_cpu == PROCESSOR_POWER5
2856 || rs6000_cpu == PROCESSOR_POWER7);
2857 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2858 || rs6000_cpu == PROCESSOR_POWER5
2859 || rs6000_cpu == PROCESSOR_POWER6
2860 || rs6000_cpu == PROCESSOR_POWER7
2861 || rs6000_cpu == PROCESSOR_PPCE500MC
2862 || rs6000_cpu == PROCESSOR_PPCE500MC64
2863 || rs6000_cpu == PROCESSOR_PPCE5500
2864 || rs6000_cpu == PROCESSOR_PPCE6500);
2866 /* Allow debug switches to override the above settings. These are set to -1
2867 in rs6000.opt to indicate the user hasn't directly set the switch. */
2868 if (TARGET_ALWAYS_HINT >= 0)
2869 rs6000_always_hint = TARGET_ALWAYS_HINT;
2871 if (TARGET_SCHED_GROUPS >= 0)
2872 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2874 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2875 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2877 rs6000_sched_restricted_insns_priority
2878 = (rs6000_sched_groups ? 1 : 0);
2880 /* Handle -msched-costly-dep option. */
2881 rs6000_sched_costly_dep
2882 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
2884 if (rs6000_sched_costly_dep_str)
2886 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2887 rs6000_sched_costly_dep = no_dep_costly;
2888 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2889 rs6000_sched_costly_dep = all_deps_costly;
2890 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2891 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2892 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2893 rs6000_sched_costly_dep = store_to_load_dep_costly;
2895 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2896 atoi (rs6000_sched_costly_dep_str));
2899 /* Handle -minsert-sched-nops option. */
2900 rs6000_sched_insert_nops
2901 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2903 if (rs6000_sched_insert_nops_str)
2905 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2906 rs6000_sched_insert_nops = sched_finish_none;
2907 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
2908 rs6000_sched_insert_nops = sched_finish_pad_groups;
2909 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
2910 rs6000_sched_insert_nops = sched_finish_regroup_exact;
2912 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
2913 atoi (rs6000_sched_insert_nops_str));
2918 #ifdef TARGET_REGNAMES
2919 /* If the user desires alternate register names, copy in the
2920 alternate names now. */
2921 if (TARGET_REGNAMES)
2922 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
2925 /* Set aix_struct_return last, after the ABI is determined.
2926 If -maix-struct-return or -msvr4-struct-return was explicitly
2927 used, don't override with the ABI default. */
2928 if (!global_options_set.x_aix_struct_return)
2929 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
2932 /* IBM XL compiler defaults to unsigned bitfields. */
2933 if (TARGET_XL_COMPAT)
2934 flag_signed_bitfields = 0;
2937 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
2938 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
2941 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
2943 /* We can only guarantee the availability of DI pseudo-ops when
2944 assembling for 64-bit targets. */
2947 targetm.asm_out.aligned_op.di = NULL;
2948 targetm.asm_out.unaligned_op.di = NULL;
2952 /* Set branch target alignment, if not optimizing for size. */
2955 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
2956 aligned 8byte to avoid misprediction by the branch predictor. */
2957 if (rs6000_cpu == PROCESSOR_TITAN
2958 || rs6000_cpu == PROCESSOR_CELL)
2960 if (align_functions <= 0)
2961 align_functions = 8;
2962 if (align_jumps <= 0)
2964 if (align_loops <= 0)
2967 if (rs6000_align_branch_targets)
2969 if (align_functions <= 0)
2970 align_functions = 16;
2971 if (align_jumps <= 0)
2973 if (align_loops <= 0)
2975 can_override_loop_align = 1;
2979 if (align_jumps_max_skip <= 0)
2980 align_jumps_max_skip = 15;
2981 if (align_loops_max_skip <= 0)
2982 align_loops_max_skip = 15;
2985 /* Arrange to save and restore machine status around nested functions. */
2986 init_machine_status = rs6000_init_machine_status;
2988 /* We should always be splitting complex arguments, but we can't break
2989 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
2990 if (DEFAULT_ABI != ABI_AIX)
2991 targetm.calls.split_complex_arg = NULL;
2994 /* Initialize rs6000_cost with the appropriate target costs. */
2996 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3000 case PROCESSOR_RIOS1:
3001 rs6000_cost = &rios1_cost;
3004 case PROCESSOR_RIOS2:
3005 rs6000_cost = &rios2_cost;
3008 case PROCESSOR_RS64A:
3009 rs6000_cost = &rs64a_cost;
3012 case PROCESSOR_MPCCORE:
3013 rs6000_cost = &mpccore_cost;
3016 case PROCESSOR_PPC403:
3017 rs6000_cost = &ppc403_cost;
3020 case PROCESSOR_PPC405:
3021 rs6000_cost = &ppc405_cost;
3024 case PROCESSOR_PPC440:
3025 rs6000_cost = &ppc440_cost;
3028 case PROCESSOR_PPC476:
3029 rs6000_cost = &ppc476_cost;
3032 case PROCESSOR_PPC601:
3033 rs6000_cost = &ppc601_cost;
3036 case PROCESSOR_PPC603:
3037 rs6000_cost = &ppc603_cost;
3040 case PROCESSOR_PPC604:
3041 rs6000_cost = &ppc604_cost;
3044 case PROCESSOR_PPC604e:
3045 rs6000_cost = &ppc604e_cost;
3048 case PROCESSOR_PPC620:
3049 rs6000_cost = &ppc620_cost;
3052 case PROCESSOR_PPC630:
3053 rs6000_cost = &ppc630_cost;
3056 case PROCESSOR_CELL:
3057 rs6000_cost = &ppccell_cost;
3060 case PROCESSOR_PPC750:
3061 case PROCESSOR_PPC7400:
3062 rs6000_cost = &ppc750_cost;
3065 case PROCESSOR_PPC7450:
3066 rs6000_cost = &ppc7450_cost;
3069 case PROCESSOR_PPC8540:
3070 case PROCESSOR_PPC8548:
3071 rs6000_cost = &ppc8540_cost;
3074 case PROCESSOR_PPCE300C2:
3075 case PROCESSOR_PPCE300C3:
3076 rs6000_cost = &ppce300c2c3_cost;
3079 case PROCESSOR_PPCE500MC:
3080 rs6000_cost = &ppce500mc_cost;
3083 case PROCESSOR_PPCE500MC64:
3084 rs6000_cost = &ppce500mc64_cost;
3087 case PROCESSOR_PPCE5500:
3088 rs6000_cost = &ppce5500_cost;
3091 case PROCESSOR_PPCE6500:
3092 rs6000_cost = &ppce6500_cost;
3095 case PROCESSOR_TITAN:
3096 rs6000_cost = &titan_cost;
3099 case PROCESSOR_POWER4:
3100 case PROCESSOR_POWER5:
3101 rs6000_cost = &power4_cost;
3104 case PROCESSOR_POWER6:
3105 rs6000_cost = &power6_cost;
3108 case PROCESSOR_POWER7:
3109 rs6000_cost = &power7_cost;
3112 case PROCESSOR_PPCA2:
3113 rs6000_cost = &ppca2_cost;
3122 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3123 rs6000_cost->simultaneous_prefetches,
3124 global_options.x_param_values,
3125 global_options_set.x_param_values);
3126 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3127 global_options.x_param_values,
3128 global_options_set.x_param_values);
3129 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3130 rs6000_cost->cache_line_size,
3131 global_options.x_param_values,
3132 global_options_set.x_param_values);
3133 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3134 global_options.x_param_values,
3135 global_options_set.x_param_values);
3137 /* If using typedef char *va_list, signal that
3138 __builtin_va_start (&ap, 0) can be optimized to
3139 ap = __builtin_next_arg (0). */
3140 if (DEFAULT_ABI != ABI_V4)
3141 targetm.expand_builtin_va_start = NULL;
3144 /* Set up single/double float flags.
3145 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3146 then set both flags. */
3147 if (TARGET_HARD_FLOAT && TARGET_FPRS
3148 && rs6000_single_float == 0 && rs6000_double_float == 0)
3149 rs6000_single_float = rs6000_double_float = 1;
3151 /* If not explicitly specified via option, decide whether to generate indexed
3152 load/store instructions. */
3153 if (TARGET_AVOID_XFORM == -1)
3154 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3155 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3156 need indexed accesses and the type used is the scalar type of the element
3157 being loaded or stored. */
3158 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3159 && !TARGET_ALTIVEC);
3161 /* Set the -mrecip options. */
3162 if (rs6000_recip_name)
3164 char *p = ASTRDUP (rs6000_recip_name);
3166 unsigned int mask, i;
3169 while ((q = strtok (p, ",")) != NULL)
3180 if (!strcmp (q, "default"))
3181 mask = ((TARGET_RECIP_PRECISION)
3182 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3185 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3186 if (!strcmp (q, recip_options[i].string))
3188 mask = recip_options[i].mask;
3192 if (i == ARRAY_SIZE (recip_options))
3194 error ("unknown option for -mrecip=%s", q);
3202 rs6000_recip_control &= ~mask;
3204 rs6000_recip_control |= mask;
3208 /* Set the builtin mask of the various options used that could affect which
3209 builtins were used. In the past we used target_flags, but we've run out
3210 of bits, and some options like SPE and PAIRED are no longer in
3212 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3213 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3214 fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
3215 (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
3216 (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "",
3217 (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "",
3218 (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : "");
3220 /* Initialize all of the registers. */
3221 rs6000_init_hard_regno_mode_ok (global_init_p);
3223 /* Save the initial options in case the user does function specific options */
3225 target_option_default_node = target_option_current_node
3226 = build_target_option_node ();
3228 /* If not explicitly specified via option, decide whether to generate the
3229 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3230 if (TARGET_LINK_STACK == -1)
3231 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3236 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3237 define the target cpu type. */
3240 rs6000_option_override (void)
3242 (void) rs6000_option_override_internal (true);
3246 /* Implement targetm.vectorize.builtin_mask_for_load. */
3248 rs6000_builtin_mask_for_load (void)
3250 if (TARGET_ALTIVEC || TARGET_VSX)
3251 return altivec_builtin_mask_for_load;
3256 /* Implement LOOP_ALIGN. */
3258 rs6000_loop_align (rtx label)
3263 /* Don't override loop alignment if -falign-loops was specified. */
3264 if (!can_override_loop_align)
3265 return align_loops_log;
3267 bb = BLOCK_FOR_INSN (label);
3268 ninsns = num_loop_insns(bb->loop_father);
3270 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3271 if (ninsns > 4 && ninsns <= 8
3272 && (rs6000_cpu == PROCESSOR_POWER4
3273 || rs6000_cpu == PROCESSOR_POWER5
3274 || rs6000_cpu == PROCESSOR_POWER6
3275 || rs6000_cpu == PROCESSOR_POWER7))
3278 return align_loops_log;
3281 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3283 rs6000_loop_align_max_skip (rtx label)
3285 return (1 << rs6000_loop_align (label)) - 1;
3288 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3290 rs6000_builtin_mul_widen_even (tree type)
3292 if (!TARGET_ALTIVEC)
3295 switch (TYPE_MODE (type))
3298 return TYPE_UNSIGNED (type)
3299 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
3300 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
3303 return TYPE_UNSIGNED (type)
3304 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
3305 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
3311 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3313 rs6000_builtin_mul_widen_odd (tree type)
3315 if (!TARGET_ALTIVEC)
3318 switch (TYPE_MODE (type))
3321 return TYPE_UNSIGNED (type)
3322 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
3323 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
3326 return TYPE_UNSIGNED (type)
3327 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
3328 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
3335 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3336 after applying N number of iterations. This routine does not determine
3337 how may iterations are required to reach desired alignment. */
3340 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3347 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3350 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3360 /* Assuming that all other types are naturally aligned. CHECKME! */
3365 /* Return true if the vector misalignment factor is supported by the
3368 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3375 /* Return if movmisalign pattern is not supported for this mode. */
3376 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3379 if (misalignment == -1)
3381 /* Misalignment factor is unknown at compile time but we know
3382 it's word aligned. */
3383 if (rs6000_vector_alignment_reachable (type, is_packed))
3385 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3387 if (element_size == 64 || element_size == 32)
3394 /* VSX supports word-aligned vector. */
3395 if (misalignment % 4 == 0)
3401 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3403 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3404 tree vectype, int misalign)
3409 switch (type_of_cost)
3419 case cond_branch_not_taken:
3428 case vec_promote_demote:
3434 case cond_branch_taken:
3437 case unaligned_load:
3438 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3440 elements = TYPE_VECTOR_SUBPARTS (vectype);
3442 /* Double word aligned. */
3450 /* Double word aligned. */
3454 /* Unknown misalignment. */
3467 /* Misaligned loads are not supported. */
3472 case unaligned_store:
3473 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3475 elements = TYPE_VECTOR_SUBPARTS (vectype);
3477 /* Double word aligned. */
3485 /* Double word aligned. */
3489 /* Unknown misalignment. */
3502 /* Misaligned stores are not supported. */
3508 elements = TYPE_VECTOR_SUBPARTS (vectype);
3509 elem_type = TREE_TYPE (vectype);
3510 /* 32-bit vectors loaded into registers are stored as double
3511 precision, so we need n/2 converts in addition to the usual
3512 n/2 merges to construct a vector of short floats from them. */
3513 if (SCALAR_FLOAT_TYPE_P (elem_type)
3514 && TYPE_PRECISION (elem_type) == 32)
3515 return elements + 1;
3517 return elements / 2 + 1;
3524 /* Implement targetm.vectorize.preferred_simd_mode. */
3526 static enum machine_mode
3527 rs6000_preferred_simd_mode (enum machine_mode mode)
3536 if (TARGET_ALTIVEC || TARGET_VSX)
3560 if (TARGET_PAIRED_FLOAT
3566 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3567 library with vectorized intrinsics. */
3570 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3573 const char *suffix = NULL;
3574 tree fntype, new_fndecl, bdecl = NULL_TREE;
3577 enum machine_mode el_mode, in_mode;
3580 /* Libmass is suitable for unsafe math only as it does not correctly support
3581 parts of IEEE with the required precision such as denormals. Only support
3582 it if we have VSX to use the simd d2 or f4 functions.
3583 XXX: Add variable length support. */
3584 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3587 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3588 n = TYPE_VECTOR_SUBPARTS (type_out);
3589 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3590 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3591 if (el_mode != in_mode
3595 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3597 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3600 case BUILT_IN_ATAN2:
3601 case BUILT_IN_HYPOT:
3607 case BUILT_IN_ACOSH:
3609 case BUILT_IN_ASINH:
3611 case BUILT_IN_ATANH:
3619 case BUILT_IN_EXPM1:
3620 case BUILT_IN_LGAMMA:
3621 case BUILT_IN_LOG10:
3622 case BUILT_IN_LOG1P:
3630 bdecl = builtin_decl_implicit (fn);
3631 suffix = "d2"; /* pow -> powd2 */
3632 if (el_mode != DFmode
3637 case BUILT_IN_ATAN2F:
3638 case BUILT_IN_HYPOTF:
3643 case BUILT_IN_ACOSF:
3644 case BUILT_IN_ACOSHF:
3645 case BUILT_IN_ASINF:
3646 case BUILT_IN_ASINHF:
3647 case BUILT_IN_ATANF:
3648 case BUILT_IN_ATANHF:
3649 case BUILT_IN_CBRTF:
3651 case BUILT_IN_COSHF:
3653 case BUILT_IN_ERFCF:
3654 case BUILT_IN_EXP2F:
3656 case BUILT_IN_EXPM1F:
3657 case BUILT_IN_LGAMMAF:
3658 case BUILT_IN_LOG10F:
3659 case BUILT_IN_LOG1PF:
3660 case BUILT_IN_LOG2F:
3663 case BUILT_IN_SINHF:
3664 case BUILT_IN_SQRTF:
3666 case BUILT_IN_TANHF:
3667 bdecl = builtin_decl_implicit (fn);
3668 suffix = "4"; /* powf -> powf4 */
3669 if (el_mode != SFmode
3681 gcc_assert (suffix != NULL);
3682 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3683 strcpy (name, bname + sizeof ("__builtin_") - 1);
3684 strcat (name, suffix);
3687 fntype = build_function_type_list (type_out, type_in, NULL);
3688 else if (n_args == 2)
3689 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3693 /* Build a function declaration for the vectorized function. */
3694 new_fndecl = build_decl (BUILTINS_LOCATION,
3695 FUNCTION_DECL, get_identifier (name), fntype);
3696 TREE_PUBLIC (new_fndecl) = 1;
3697 DECL_EXTERNAL (new_fndecl) = 1;
3698 DECL_IS_NOVOPS (new_fndecl) = 1;
3699 TREE_READONLY (new_fndecl) = 1;
3704 /* Returns a function decl for a vectorized version of the builtin function
3705 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3706 if it is not available. */
3709 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3712 enum machine_mode in_mode, out_mode;
3715 if (TARGET_DEBUG_BUILTIN)
3716 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3717 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3718 GET_MODE_NAME (TYPE_MODE (type_out)),
3719 GET_MODE_NAME (TYPE_MODE (type_in)));
3721 if (TREE_CODE (type_out) != VECTOR_TYPE
3722 || TREE_CODE (type_in) != VECTOR_TYPE
3723 || !TARGET_VECTORIZE_BUILTINS)
3726 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3727 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3728 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3729 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3731 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3733 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3736 case BUILT_IN_COPYSIGN:
3737 if (VECTOR_UNIT_VSX_P (V2DFmode)
3738 && out_mode == DFmode && out_n == 2
3739 && in_mode == DFmode && in_n == 2)
3740 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3742 case BUILT_IN_COPYSIGNF:
3743 if (out_mode != SFmode || out_n != 4
3744 || in_mode != SFmode || in_n != 4)
3746 if (VECTOR_UNIT_VSX_P (V4SFmode))
3747 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3748 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3749 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3752 if (VECTOR_UNIT_VSX_P (V2DFmode)
3753 && out_mode == DFmode && out_n == 2
3754 && in_mode == DFmode && in_n == 2)
3755 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3757 case BUILT_IN_SQRTF:
3758 if (VECTOR_UNIT_VSX_P (V4SFmode)
3759 && out_mode == SFmode && out_n == 4
3760 && in_mode == SFmode && in_n == 4)
3761 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3764 if (VECTOR_UNIT_VSX_P (V2DFmode)
3765 && out_mode == DFmode && out_n == 2
3766 && in_mode == DFmode && in_n == 2)
3767 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3769 case BUILT_IN_CEILF:
3770 if (out_mode != SFmode || out_n != 4
3771 || in_mode != SFmode || in_n != 4)
3773 if (VECTOR_UNIT_VSX_P (V4SFmode))
3774 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3775 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3776 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3778 case BUILT_IN_FLOOR:
3779 if (VECTOR_UNIT_VSX_P (V2DFmode)
3780 && out_mode == DFmode && out_n == 2
3781 && in_mode == DFmode && in_n == 2)
3782 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3784 case BUILT_IN_FLOORF:
3785 if (out_mode != SFmode || out_n != 4
3786 || in_mode != SFmode || in_n != 4)
3788 if (VECTOR_UNIT_VSX_P (V4SFmode))
3789 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3790 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3791 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3794 if (VECTOR_UNIT_VSX_P (V2DFmode)
3795 && out_mode == DFmode && out_n == 2
3796 && in_mode == DFmode && in_n == 2)
3797 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3800 if (VECTOR_UNIT_VSX_P (V4SFmode)
3801 && out_mode == SFmode && out_n == 4
3802 && in_mode == SFmode && in_n == 4)
3803 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3804 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3805 && out_mode == SFmode && out_n == 4
3806 && in_mode == SFmode && in_n == 4)
3807 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3809 case BUILT_IN_TRUNC:
3810 if (VECTOR_UNIT_VSX_P (V2DFmode)
3811 && out_mode == DFmode && out_n == 2
3812 && in_mode == DFmode && in_n == 2)
3813 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3815 case BUILT_IN_TRUNCF:
3816 if (out_mode != SFmode || out_n != 4
3817 || in_mode != SFmode || in_n != 4)
3819 if (VECTOR_UNIT_VSX_P (V4SFmode))
3820 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3821 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3822 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3824 case BUILT_IN_NEARBYINT:
3825 if (VECTOR_UNIT_VSX_P (V2DFmode)
3826 && flag_unsafe_math_optimizations
3827 && out_mode == DFmode && out_n == 2
3828 && in_mode == DFmode && in_n == 2)
3829 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3831 case BUILT_IN_NEARBYINTF:
3832 if (VECTOR_UNIT_VSX_P (V4SFmode)
3833 && flag_unsafe_math_optimizations
3834 && out_mode == SFmode && out_n == 4
3835 && in_mode == SFmode && in_n == 4)
3836 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3839 if (VECTOR_UNIT_VSX_P (V2DFmode)
3840 && !flag_trapping_math
3841 && out_mode == DFmode && out_n == 2
3842 && in_mode == DFmode && in_n == 2)
3843 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3845 case BUILT_IN_RINTF:
3846 if (VECTOR_UNIT_VSX_P (V4SFmode)
3847 && !flag_trapping_math
3848 && out_mode == SFmode && out_n == 4
3849 && in_mode == SFmode && in_n == 4)
3850 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3857 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3859 enum rs6000_builtins fn
3860 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3863 case RS6000_BUILTIN_RSQRTF:
3864 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3865 && out_mode == SFmode && out_n == 4
3866 && in_mode == SFmode && in_n == 4)
3867 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3869 case RS6000_BUILTIN_RSQRT:
3870 if (VECTOR_UNIT_VSX_P (V2DFmode)
3871 && out_mode == DFmode && out_n == 2
3872 && in_mode == DFmode && in_n == 2)
3873 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3875 case RS6000_BUILTIN_RECIPF:
3876 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3877 && out_mode == SFmode && out_n == 4
3878 && in_mode == SFmode && in_n == 4)
3879 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3881 case RS6000_BUILTIN_RECIP:
3882 if (VECTOR_UNIT_VSX_P (V2DFmode)
3883 && out_mode == DFmode && out_n == 2
3884 && in_mode == DFmode && in_n == 2)
3885 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3892 /* Generate calls to libmass if appropriate. */
3893 if (rs6000_veclib_handler)
3894 return rs6000_veclib_handler (fndecl, type_out, type_in);
3899 /* Default CPU string for rs6000*_file_start functions. */
3900 static const char *rs6000_default_cpu;
3902 /* Do anything needed at the start of the asm file. */
3905 rs6000_file_start (void)
3908 const char *start = buffer;
3909 FILE *file = asm_out_file;
3911 rs6000_default_cpu = TARGET_CPU_DEFAULT;
3913 default_file_start ();
3915 if (flag_verbose_asm)
3917 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
3919 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
3921 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
3925 if (global_options_set.x_rs6000_cpu_index)
3927 fprintf (file, "%s -mcpu=%s", start,
3928 processor_target_table[rs6000_cpu_index].name);
3932 if (global_options_set.x_rs6000_tune_index)
3934 fprintf (file, "%s -mtune=%s", start,
3935 processor_target_table[rs6000_tune_index].name);
3939 if (PPC405_ERRATUM77)
3941 fprintf (file, "%s PPC405CR_ERRATUM77", start);
3945 #ifdef USING_ELFOS_H
3946 switch (rs6000_sdata)
3948 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
3949 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
3950 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
3951 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
3954 if (rs6000_sdata && g_switch_value)
3956 fprintf (file, "%s -G %d", start,
3966 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
3968 switch_to_section (toc_section);
3969 switch_to_section (text_section);
3974 /* Return nonzero if this function is known to have a null epilogue. */
3977 direct_return (void)
3979 if (reload_completed)
3981 rs6000_stack_t *info = rs6000_stack_info ();
3983 if (info->first_gp_reg_save == 32
3984 && info->first_fp_reg_save == 64
3985 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
3986 && ! info->lr_save_p
3987 && ! info->cr_save_p
3988 && info->vrsave_mask == 0
3996 /* Return the number of instructions it takes to form a constant in an
3997 integer register. */
4000 num_insns_constant_wide (HOST_WIDE_INT value)
4002 /* signed constant loadable with {cal|addi} */
4003 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4006 /* constant loadable with {cau|addis} */
4007 else if ((value & 0xffff) == 0
4008 && (value >> 31 == -1 || value >> 31 == 0))
4011 #if HOST_BITS_PER_WIDE_INT == 64
4012 else if (TARGET_POWERPC64)
4014 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4015 HOST_WIDE_INT high = value >> 31;
4017 if (high == 0 || high == -1)
4023 return num_insns_constant_wide (high) + 1;
4025 return num_insns_constant_wide (low) + 1;
4027 return (num_insns_constant_wide (high)
4028 + num_insns_constant_wide (low) + 1);
4037 num_insns_constant (rtx op, enum machine_mode mode)
4039 HOST_WIDE_INT low, high;
4041 switch (GET_CODE (op))
4044 #if HOST_BITS_PER_WIDE_INT == 64
4045 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4046 && mask64_operand (op, mode))
4050 return num_insns_constant_wide (INTVAL (op));
4053 if (mode == SFmode || mode == SDmode)
4058 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4059 if (DECIMAL_FLOAT_MODE_P (mode))
4060 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4062 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4063 return num_insns_constant_wide ((HOST_WIDE_INT) l);
4066 if (mode == VOIDmode || mode == DImode)
4068 high = CONST_DOUBLE_HIGH (op);
4069 low = CONST_DOUBLE_LOW (op);
4076 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4077 if (DECIMAL_FLOAT_MODE_P (mode))
4078 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4080 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4081 high = l[WORDS_BIG_ENDIAN == 0];
4082 low = l[WORDS_BIG_ENDIAN != 0];
4086 return (num_insns_constant_wide (low)
4087 + num_insns_constant_wide (high));
4090 if ((high == 0 && low >= 0)
4091 || (high == -1 && low < 0))
4092 return num_insns_constant_wide (low);
4094 else if (mask64_operand (op, mode))
4098 return num_insns_constant_wide (high) + 1;
4101 return (num_insns_constant_wide (high)
4102 + num_insns_constant_wide (low) + 1);
4110 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4111 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4112 corresponding element of the vector, but for V4SFmode and V2SFmode,
4113 the corresponding "float" is interpreted as an SImode integer. */
4116 const_vector_elt_as_int (rtx op, unsigned int elt)
4120 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4121 gcc_assert (GET_MODE (op) != V2DImode
4122 && GET_MODE (op) != V2DFmode);
4124 tmp = CONST_VECTOR_ELT (op, elt);
4125 if (GET_MODE (op) == V4SFmode
4126 || GET_MODE (op) == V2SFmode)
4127 tmp = gen_lowpart (SImode, tmp);
4128 return INTVAL (tmp);
4131 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4132 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4133 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4134 all items are set to the same value and contain COPIES replicas of the
4135 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4136 operand and the others are set to the value of the operand's msb. */
4139 vspltis_constant (rtx op, unsigned step, unsigned copies)
4141 enum machine_mode mode = GET_MODE (op);
4142 enum machine_mode inner = GET_MODE_INNER (mode);
4150 HOST_WIDE_INT splat_val;
4151 HOST_WIDE_INT msb_val;
4153 if (mode == V2DImode || mode == V2DFmode)
4156 nunits = GET_MODE_NUNITS (mode);
4157 bitsize = GET_MODE_BITSIZE (inner);
4158 mask = GET_MODE_MASK (inner);
4160 val = const_vector_elt_as_int (op, nunits - 1);
4162 msb_val = val > 0 ? 0 : -1;
4164 /* Construct the value to be splatted, if possible. If not, return 0. */
4165 for (i = 2; i <= copies; i *= 2)
4167 HOST_WIDE_INT small_val;
4169 small_val = splat_val >> bitsize;
4171 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4173 splat_val = small_val;
4176 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4177 if (EASY_VECTOR_15 (splat_val))
4180 /* Also check if we can splat, and then add the result to itself. Do so if
4181 the value is positive, of if the splat instruction is using OP's mode;
4182 for splat_val < 0, the splat and the add should use the same mode. */
4183 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4184 && (splat_val >= 0 || (step == 1 && copies == 1)))
4187 /* Also check if are loading up the most significant bit which can be done by
4188 loading up -1 and shifting the value left by -1. */
4189 else if (EASY_VECTOR_MSB (splat_val, inner))
4195 /* Check if VAL is present in every STEP-th element, and the
4196 other elements are filled with its most significant bit. */
4197 for (i = 0; i < nunits - 1; ++i)
4199 HOST_WIDE_INT desired_val;
4200 if (((i + 1) & (step - 1)) == 0)
4203 desired_val = msb_val;
4205 if (desired_val != const_vector_elt_as_int (op, i))
4213 /* Return true if OP is of the given MODE and can be synthesized
4214 with a vspltisb, vspltish or vspltisw. */
4217 easy_altivec_constant (rtx op, enum machine_mode mode)
4219 unsigned step, copies;
4221 if (mode == VOIDmode)
4222 mode = GET_MODE (op);
4223 else if (mode != GET_MODE (op))
4226 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4228 if (mode == V2DFmode)
4229 return zero_constant (op, mode);
4231 if (mode == V2DImode)
4233 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4235 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4236 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4239 if (zero_constant (op, mode))
4242 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4243 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4249 /* Start with a vspltisw. */
4250 step = GET_MODE_NUNITS (mode) / 4;
4253 if (vspltis_constant (op, step, copies))
4256 /* Then try with a vspltish. */
4262 if (vspltis_constant (op, step, copies))
4265 /* And finally a vspltisb. */
4271 if (vspltis_constant (op, step, copies))
4277 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4278 result is OP. Abort if it is not possible. */
4281 gen_easy_altivec_constant (rtx op)
4283 enum machine_mode mode = GET_MODE (op);
4284 int nunits = GET_MODE_NUNITS (mode);
4285 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4286 unsigned step = nunits / 4;
4287 unsigned copies = 1;
4289 /* Start with a vspltisw. */
4290 if (vspltis_constant (op, step, copies))
4291 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4293 /* Then try with a vspltish. */
4299 if (vspltis_constant (op, step, copies))
4300 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4302 /* And finally a vspltisb. */
4308 if (vspltis_constant (op, step, copies))
4309 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4315 output_vec_const_move (rtx *operands)
4318 enum machine_mode mode;
4323 mode = GET_MODE (dest);
4327 if (zero_constant (vec, mode))
4328 return "xxlxor %x0,%x0,%x0";
4330 if (mode == V2DImode
4331 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4332 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4333 return "vspltisw %0,-1";
4339 if (zero_constant (vec, mode))
4340 return "vxor %0,%0,%0";
4342 splat_vec = gen_easy_altivec_constant (vec);
4343 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4344 operands[1] = XEXP (splat_vec, 0);
4345 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4348 switch (GET_MODE (splat_vec))
4351 return "vspltisw %0,%1";
4354 return "vspltish %0,%1";
4357 return "vspltisb %0,%1";
4364 gcc_assert (TARGET_SPE);
4366 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4367 pattern of V1DI, V4HI, and V2SF.
4369 FIXME: We should probably return # and add post reload
4370 splitters for these, but this way is so easy ;-). */
4371 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4372 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4373 operands[1] = CONST_VECTOR_ELT (vec, 0);
4374 operands[2] = CONST_VECTOR_ELT (vec, 1);
4376 return "li %0,%1\n\tevmergelo %0,%0,%0";
4378 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4381 /* Initialize TARGET of vector PAIRED to VALS. */
4384 paired_expand_vector_init (rtx target, rtx vals)
4386 enum machine_mode mode = GET_MODE (target);
4387 int n_elts = GET_MODE_NUNITS (mode);
4389 rtx x, new_rtx, tmp, constant_op, op1, op2;
4392 for (i = 0; i < n_elts; ++i)
4394 x = XVECEXP (vals, 0, i);
4395 if (!(CONST_INT_P (x)
4396 || GET_CODE (x) == CONST_DOUBLE
4397 || GET_CODE (x) == CONST_FIXED))
4402 /* Load from constant pool. */
4403 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4409 /* The vector is initialized only with non-constants. */
4410 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4411 XVECEXP (vals, 0, 1));
4413 emit_move_insn (target, new_rtx);
4417 /* One field is non-constant and the other one is a constant. Load the
4418 constant from the constant pool and use ps_merge instruction to
4419 construct the whole vector. */
4420 op1 = XVECEXP (vals, 0, 0);
4421 op2 = XVECEXP (vals, 0, 1);
4423 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4425 tmp = gen_reg_rtx (GET_MODE (constant_op));
4426 emit_move_insn (tmp, constant_op);
4428 if (CONSTANT_P (op1))
4429 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4431 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4433 emit_move_insn (target, new_rtx);
4437 paired_expand_vector_move (rtx operands[])
4439 rtx op0 = operands[0], op1 = operands[1];
4441 emit_move_insn (op0, op1);
4444 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4445 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4446 operands for the relation operation COND. This is a recursive
4450 paired_emit_vector_compare (enum rtx_code rcode,
4451 rtx dest, rtx op0, rtx op1,
4452 rtx cc_op0, rtx cc_op1)
4454 rtx tmp = gen_reg_rtx (V2SFmode);
4457 gcc_assert (TARGET_PAIRED_FLOAT);
4458 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4464 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4468 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4469 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4473 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4476 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4479 tmp1 = gen_reg_rtx (V2SFmode);
4480 max = gen_reg_rtx (V2SFmode);
4481 min = gen_reg_rtx (V2SFmode);
4482 gen_reg_rtx (V2SFmode);
4484 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4485 emit_insn (gen_selv2sf4
4486 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4487 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4488 emit_insn (gen_selv2sf4
4489 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4490 emit_insn (gen_subv2sf3 (tmp1, min, max));
4491 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4494 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4497 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4500 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4503 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4506 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4515 /* Emit vector conditional expression.
4516 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4517 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4520 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4521 rtx cond, rtx cc_op0, rtx cc_op1)
4523 enum rtx_code rcode = GET_CODE (cond);
4525 if (!TARGET_PAIRED_FLOAT)
4528 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4533 /* Initialize vector TARGET to VALS. */
4536 rs6000_expand_vector_init (rtx target, rtx vals)
4538 enum machine_mode mode = GET_MODE (target);
4539 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4540 int n_elts = GET_MODE_NUNITS (mode);
4541 int n_var = 0, one_var = -1;
4542 bool all_same = true, all_const_zero = true;
4546 for (i = 0; i < n_elts; ++i)
4548 x = XVECEXP (vals, 0, i);
4549 if (!(CONST_INT_P (x)
4550 || GET_CODE (x) == CONST_DOUBLE
4551 || GET_CODE (x) == CONST_FIXED))
4552 ++n_var, one_var = i;
4553 else if (x != CONST0_RTX (inner_mode))
4554 all_const_zero = false;
4556 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4562 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4563 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4564 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4566 /* Zero register. */
4567 emit_insn (gen_rtx_SET (VOIDmode, target,
4568 gen_rtx_XOR (mode, target, target)));
4571 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4573 /* Splat immediate. */
4574 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4579 /* Load from constant pool. */
4580 emit_move_insn (target, const_vec);
4585 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4586 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4588 rtx op0 = XVECEXP (vals, 0, 0);
4589 rtx op1 = XVECEXP (vals, 0, 1);
4592 if (!MEM_P (op0) && !REG_P (op0))
4593 op0 = force_reg (inner_mode, op0);
4594 if (mode == V2DFmode)
4595 emit_insn (gen_vsx_splat_v2df (target, op0));
4597 emit_insn (gen_vsx_splat_v2di (target, op0));
4601 op0 = force_reg (inner_mode, op0);
4602 op1 = force_reg (inner_mode, op1);
4603 if (mode == V2DFmode)
4604 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4606 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4611 /* With single precision floating point on VSX, know that internally single
4612 precision is actually represented as a double, and either make 2 V2DF
4613 vectors, and convert these vectors to single precision, or do one
4614 conversion, and splat the result to the other elements. */
4615 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4619 rtx freg = gen_reg_rtx (V4SFmode);
4620 rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
4622 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4623 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4627 rtx dbl_even = gen_reg_rtx (V2DFmode);
4628 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4629 rtx flt_even = gen_reg_rtx (V4SFmode);
4630 rtx flt_odd = gen_reg_rtx (V4SFmode);
4631 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
4632 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
4633 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
4634 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
4636 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
4637 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
4638 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4639 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4640 rs6000_expand_extract_even (target, flt_even, flt_odd);
4645 /* Store value to stack temp. Load vector element. Splat. However, splat
4646 of 64-bit items is not supported on Altivec. */
4647 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4649 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4650 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4651 XVECEXP (vals, 0, 0));
4652 x = gen_rtx_UNSPEC (VOIDmode,
4653 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4654 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4656 gen_rtx_SET (VOIDmode,
4659 x = gen_rtx_VEC_SELECT (inner_mode, target,
4660 gen_rtx_PARALLEL (VOIDmode,
4661 gen_rtvec (1, const0_rtx)));
4662 emit_insn (gen_rtx_SET (VOIDmode, target,
4663 gen_rtx_VEC_DUPLICATE (mode, x)));
4667 /* One field is non-constant. Load constant then overwrite
4671 rtx copy = copy_rtx (vals);
4673 /* Load constant part of vector, substitute neighboring value for
4675 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4676 rs6000_expand_vector_init (target, copy);
4678 /* Insert variable. */
4679 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4683 /* Construct the vector in memory one field at a time
4684 and load the whole vector. */
4685 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4686 for (i = 0; i < n_elts; i++)
4687 emit_move_insn (adjust_address_nv (mem, inner_mode,
4688 i * GET_MODE_SIZE (inner_mode)),
4689 XVECEXP (vals, 0, i));
4690 emit_move_insn (target, mem);
4693 /* Set field ELT of TARGET to VAL. */
4696 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4698 enum machine_mode mode = GET_MODE (target);
4699 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4700 rtx reg = gen_reg_rtx (mode);
4702 int width = GET_MODE_SIZE (inner_mode);
4705 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4707 rtx (*set_func) (rtx, rtx, rtx, rtx)
4708 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4709 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4713 /* Load single variable value. */
4714 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4715 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4716 x = gen_rtx_UNSPEC (VOIDmode,
4717 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4718 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4720 gen_rtx_SET (VOIDmode,
4724 /* Linear sequence. */
4725 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4726 for (i = 0; i < 16; ++i)
4727 XVECEXP (mask, 0, i) = GEN_INT (i);
4729 /* Set permute mask to insert element into target. */
4730 for (i = 0; i < width; ++i)
4731 XVECEXP (mask, 0, elt*width + i)
4732 = GEN_INT (i + 0x10);
4733 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4734 x = gen_rtx_UNSPEC (mode,
4735 gen_rtvec (3, target, reg,
4736 force_reg (V16QImode, x)),
4738 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4741 /* Extract field ELT from VEC into TARGET. */
4744 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4746 enum machine_mode mode = GET_MODE (vec);
4747 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4750 if (VECTOR_MEM_VSX_P (mode))
4757 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4760 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4763 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4768 /* Allocate mode-sized buffer. */
4769 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4771 emit_move_insn (mem, vec);
4773 /* Add offset to field within buffer matching vector element. */
4774 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4776 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4779 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4780 implement ANDing by the mask IN. */
4782 build_mask64_2_operands (rtx in, rtx *out)
4784 #if HOST_BITS_PER_WIDE_INT >= 64
4785 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4788 gcc_assert (GET_CODE (in) == CONST_INT);
4793 /* Assume c initially something like 0x00fff000000fffff. The idea
4794 is to rotate the word so that the middle ^^^^^^ group of zeros
4795 is at the MS end and can be cleared with an rldicl mask. We then
4796 rotate back and clear off the MS ^^ group of zeros with a
4798 c = ~c; /* c == 0xff000ffffff00000 */
4799 lsb = c & -c; /* lsb == 0x0000000000100000 */
4800 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4801 c = ~c; /* c == 0x00fff000000fffff */
4802 c &= -lsb; /* c == 0x00fff00000000000 */
4803 lsb = c & -c; /* lsb == 0x0000100000000000 */
4804 c = ~c; /* c == 0xff000fffffffffff */
4805 c &= -lsb; /* c == 0xff00000000000000 */
4807 while ((lsb >>= 1) != 0)
4808 shift++; /* shift == 44 on exit from loop */
4809 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4810 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4811 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4815 /* Assume c initially something like 0xff000f0000000000. The idea
4816 is to rotate the word so that the ^^^ middle group of zeros
4817 is at the LS end and can be cleared with an rldicr mask. We then
4818 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4820 lsb = c & -c; /* lsb == 0x0000010000000000 */
4821 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4822 c = ~c; /* c == 0x00fff0ffffffffff */
4823 c &= -lsb; /* c == 0x00fff00000000000 */
4824 lsb = c & -c; /* lsb == 0x0000100000000000 */
4825 c = ~c; /* c == 0xff000fffffffffff */
4826 c &= -lsb; /* c == 0xff00000000000000 */
4828 while ((lsb >>= 1) != 0)
4829 shift++; /* shift == 44 on exit from loop */
4830 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4831 m1 >>= shift; /* m1 == 0x0000000000000fff */
4832 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4835 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4836 masks will be all 1's. We are guaranteed more than one transition. */
4837 out[0] = GEN_INT (64 - shift);
4838 out[1] = GEN_INT (m1);
4839 out[2] = GEN_INT (shift);
4840 out[3] = GEN_INT (m2);
4848 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4851 invalid_e500_subreg (rtx op, enum machine_mode mode)
4853 if (TARGET_E500_DOUBLE)
4855 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4856 subreg:TI and reg:TF. Decimal float modes are like integer
4857 modes (only low part of each register used) for this
4859 if (GET_CODE (op) == SUBREG
4860 && (mode == SImode || mode == DImode || mode == TImode
4861 || mode == DDmode || mode == TDmode)
4862 && REG_P (SUBREG_REG (op))
4863 && (GET_MODE (SUBREG_REG (op)) == DFmode
4864 || GET_MODE (SUBREG_REG (op)) == TFmode))
4867 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4869 if (GET_CODE (op) == SUBREG
4870 && (mode == DFmode || mode == TFmode)
4871 && REG_P (SUBREG_REG (op))
4872 && (GET_MODE (SUBREG_REG (op)) == DImode
4873 || GET_MODE (SUBREG_REG (op)) == TImode
4874 || GET_MODE (SUBREG_REG (op)) == DDmode
4875 || GET_MODE (SUBREG_REG (op)) == TDmode))
4880 && GET_CODE (op) == SUBREG
4882 && REG_P (SUBREG_REG (op))
4883 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4889 /* AIX increases natural record alignment to doubleword if the first
4890 field is an FP double while the FP fields remain word aligned. */
4893 rs6000_special_round_type_align (tree type, unsigned int computed,
4894 unsigned int specified)
4896 unsigned int align = MAX (computed, specified);
4897 tree field = TYPE_FIELDS (type);
4899 /* Skip all non field decls */
4900 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4901 field = DECL_CHAIN (field);
4903 if (field != NULL && field != type)
4905 type = TREE_TYPE (field);
4906 while (TREE_CODE (type) == ARRAY_TYPE)
4907 type = TREE_TYPE (type);
4909 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4910 align = MAX (align, 64);
4916 /* Darwin increases record alignment to the natural alignment of
4920 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
4921 unsigned int specified)
4923 unsigned int align = MAX (computed, specified);
4925 if (TYPE_PACKED (type))
4928 /* Find the first field, looking down into aggregates. */
4930 tree field = TYPE_FIELDS (type);
4931 /* Skip all non field decls */
4932 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4933 field = DECL_CHAIN (field);
4936 /* A packed field does not contribute any extra alignment. */
4937 if (DECL_PACKED (field))
4939 type = TREE_TYPE (field);
4940 while (TREE_CODE (type) == ARRAY_TYPE)
4941 type = TREE_TYPE (type);
4942 } while (AGGREGATE_TYPE_P (type));
4944 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
4945 align = MAX (align, TYPE_ALIGN (type));
4950 /* Return 1 for an operand in small memory on V.4/eabi. */
4953 small_data_operand (rtx op ATTRIBUTE_UNUSED,
4954 enum machine_mode mode ATTRIBUTE_UNUSED)
4959 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
4962 if (DEFAULT_ABI != ABI_V4)
4965 /* Vector and float memory instructions have a limited offset on the
4966 SPE, so using a vector or float variable directly as an operand is
4969 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
4972 if (GET_CODE (op) == SYMBOL_REF)
4975 else if (GET_CODE (op) != CONST
4976 || GET_CODE (XEXP (op, 0)) != PLUS
4977 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
4978 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
4983 rtx sum = XEXP (op, 0);
4984 HOST_WIDE_INT summand;
4986 /* We have to be careful here, because it is the referenced address
4987 that must be 32k from _SDA_BASE_, not just the symbol. */
4988 summand = INTVAL (XEXP (sum, 1));
4989 if (summand < 0 || summand > g_switch_value)
4992 sym_ref = XEXP (sum, 0);
4995 return SYMBOL_REF_SMALL_P (sym_ref);
5001 /* Return true if either operand is a general purpose register. */
5004 gpr_or_gpr_p (rtx op0, rtx op1)
5006 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5007 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5011 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5014 reg_offset_addressing_ok_p (enum machine_mode mode)
5024 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5025 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5033 /* Paired vector modes. Only reg+reg addressing is valid. */
5034 if (TARGET_PAIRED_FLOAT)
5046 virtual_stack_registers_memory_p (rtx op)
5050 if (GET_CODE (op) == REG)
5051 regnum = REGNO (op);
5053 else if (GET_CODE (op) == PLUS
5054 && GET_CODE (XEXP (op, 0)) == REG
5055 && GET_CODE (XEXP (op, 1)) == CONST_INT)
5056 regnum = REGNO (XEXP (op, 0));
5061 return (regnum >= FIRST_VIRTUAL_REGISTER
5062 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5065 /* Return true if memory accesses to OP are known to never straddle
5069 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5070 enum machine_mode mode)
5073 unsigned HOST_WIDE_INT dsize, dalign;
5075 if (GET_CODE (op) != SYMBOL_REF)
5078 decl = SYMBOL_REF_DECL (op);
5081 if (GET_MODE_SIZE (mode) == 0)
5084 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5085 replacing memory addresses with an anchor plus offset. We
5086 could find the decl by rummaging around in the block->objects
5087 VEC for the given offset but that seems like too much work. */
5089 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5090 && SYMBOL_REF_ANCHOR_P (op)
5091 && SYMBOL_REF_BLOCK (op) != NULL)
5093 struct object_block *block = SYMBOL_REF_BLOCK (op);
5094 HOST_WIDE_INT lsb, mask;
5096 /* Given the alignment of the block.. */
5097 dalign = block->alignment;
5098 mask = dalign / BITS_PER_UNIT - 1;
5100 /* ..and the combined offset of the anchor and any offset
5101 to this block object.. */
5102 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5103 lsb = offset & -offset;
5105 /* ..find how many bits of the alignment we know for the
5110 return dalign >= GET_MODE_SIZE (mode);
5115 if (TREE_CODE (decl) == FUNCTION_DECL)
5118 if (!DECL_SIZE_UNIT (decl))
5121 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5124 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5128 dalign = DECL_ALIGN_UNIT (decl);
5129 return dalign >= dsize;
5132 type = TREE_TYPE (decl);
5134 if (TREE_CODE (decl) == STRING_CST)
5135 dsize = TREE_STRING_LENGTH (decl);
5136 else if (TYPE_SIZE_UNIT (type)
5137 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5138 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5144 dalign = TYPE_ALIGN (type);
5145 if (CONSTANT_CLASS_P (decl))
5146 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5148 dalign = DATA_ALIGNMENT (decl, dalign);
5149 dalign /= BITS_PER_UNIT;
5150 return dalign >= dsize;
5154 constant_pool_expr_p (rtx op)
5158 split_const (op, &base, &offset);
5159 return (GET_CODE (base) == SYMBOL_REF
5160 && CONSTANT_POOL_ADDRESS_P (base)
5161 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5164 static const_rtx tocrel_base, tocrel_offset;
5166 /* Return true if OP is a toc pointer relative address (the output
5167 of create_TOC_reference). If STRICT, do not match high part or
5168 non-split -mcmodel=large/medium toc pointer relative addresses. */
5171 toc_relative_expr_p (const_rtx op, bool strict)
5176 if (TARGET_CMODEL != CMODEL_SMALL)
5178 /* Only match the low part. */
5179 if (GET_CODE (op) == LO_SUM
5180 && REG_P (XEXP (op, 0))
5181 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict))
5188 tocrel_offset = const0_rtx;
5189 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
5191 tocrel_base = XEXP (op, 0);
5192 tocrel_offset = XEXP (op, 1);
5195 return (GET_CODE (tocrel_base) == UNSPEC
5196 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5199 /* Return true if X is a constant pool address, and also for cmodel=medium
5200 if X is a toc-relative address known to be offsettable within MODE. */
5203 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5206 return (toc_relative_expr_p (x, strict)
5207 && (TARGET_CMODEL != CMODEL_MEDIUM
5208 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5210 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5211 INTVAL (tocrel_offset), mode)));
5215 legitimate_small_data_p (enum machine_mode mode, rtx x)
5217 return (DEFAULT_ABI == ABI_V4
5218 && !flag_pic && !TARGET_TOC
5219 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5220 && small_data_operand (x, mode));
5223 /* SPE offset addressing is limited to 5-bits worth of double words. */
5224 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5227 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
5229 unsigned HOST_WIDE_INT offset, extra;
5231 if (GET_CODE (x) != PLUS)
5233 if (GET_CODE (XEXP (x, 0)) != REG)
5235 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5237 if (!reg_offset_addressing_ok_p (mode))
5238 return virtual_stack_registers_memory_p (x);
5239 if (legitimate_constant_pool_address_p (x, mode, strict))
5241 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5244 offset = INTVAL (XEXP (x, 1));
5252 /* SPE vector modes. */
5253 return SPE_CONST_OFFSET_OK (offset);
5256 if (TARGET_E500_DOUBLE)
5257 return SPE_CONST_OFFSET_OK (offset);
5259 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5261 if (VECTOR_MEM_VSX_P (DFmode))
5266 /* On e500v2, we may have:
5268 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5270 Which gets addressed with evldd instructions. */
5271 if (TARGET_E500_DOUBLE)
5272 return SPE_CONST_OFFSET_OK (offset);
5274 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
5276 else if (offset & 3)
5281 if (TARGET_E500_DOUBLE)
5282 return (SPE_CONST_OFFSET_OK (offset)
5283 && SPE_CONST_OFFSET_OK (offset + 8));
5287 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
5289 else if (offset & 3)
5300 return offset < 0x10000 - extra;
5304 legitimate_indexed_address_p (rtx x, int strict)
5308 if (GET_CODE (x) != PLUS)
5314 /* Recognize the rtl generated by reload which we know will later be
5315 replaced with proper base and index regs. */
5317 && reload_in_progress
5318 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5322 return (REG_P (op0) && REG_P (op1)
5323 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5324 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5325 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5326 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5330 avoiding_indexed_address_p (enum machine_mode mode)
5332 /* Avoid indexed addressing for modes that have non-indexed
5333 load/store instruction forms. */
5334 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5338 legitimate_indirect_address_p (rtx x, int strict)
5340 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5344 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5346 if (!TARGET_MACHO || !flag_pic
5347 || mode != SImode || GET_CODE (x) != MEM)
5351 if (GET_CODE (x) != LO_SUM)
5353 if (GET_CODE (XEXP (x, 0)) != REG)
5355 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5359 return CONSTANT_P (x);
5363 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5365 if (GET_CODE (x) != LO_SUM)
5367 if (GET_CODE (XEXP (x, 0)) != REG)
5369 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5371 /* Restrict addressing for DI because of our SUBREG hackery. */
5372 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5373 || mode == DDmode || mode == TDmode
5378 if (TARGET_ELF || TARGET_MACHO)
5380 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5384 if (GET_MODE_NUNITS (mode) != 1)
5386 if (GET_MODE_BITSIZE (mode) > 64
5387 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
5388 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5389 && (mode == DFmode || mode == DDmode))))
5392 return CONSTANT_P (x);
5399 /* Try machine-dependent ways of modifying an illegitimate address
5400 to be legitimate. If we find one, return the new, valid address.
5401 This is used from only one place: `memory_address' in explow.c.
5403 OLDX is the address as it was before break_out_memory_refs was
5404 called. In some cases it is useful to look at this to decide what
5407 It is always safe for this function to do nothing. It exists to
5408 recognize opportunities to optimize the output.
5410 On RS/6000, first check for the sum of a register with a constant
5411 integer that is out of range. If so, generate code to add the
5412 constant with the low-order 16 bits masked to the register and force
5413 this result into another register (this can be done with `cau').
5414 Then generate an address of REG+(CONST&0xffff), allowing for the
5415 possibility of bit 16 being a one.
5417 Then check for the sum of a register and something not constant, try to
5418 load the other things into a register and return the sum. */
5421 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5422 enum machine_mode mode)
5424 unsigned int extra = 0;
5426 if (!reg_offset_addressing_ok_p (mode))
5428 if (virtual_stack_registers_memory_p (x))
5431 /* In theory we should not be seeing addresses of the form reg+0,
5432 but just in case it is generated, optimize it away. */
5433 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5434 return force_reg (Pmode, XEXP (x, 0));
5436 /* Make sure both operands are registers. */
5437 else if (GET_CODE (x) == PLUS)
5438 return gen_rtx_PLUS (Pmode,
5439 force_reg (Pmode, XEXP (x, 0)),
5440 force_reg (Pmode, XEXP (x, 1)));
5442 return force_reg (Pmode, x);
5444 if (GET_CODE (x) == SYMBOL_REF)
5446 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5448 return rs6000_legitimize_tls_address (x, model);
5458 if (!TARGET_POWERPC64)
5466 extra = TARGET_POWERPC64 ? 8 : 12;
5472 if (GET_CODE (x) == PLUS
5473 && GET_CODE (XEXP (x, 0)) == REG
5474 && GET_CODE (XEXP (x, 1)) == CONST_INT
5475 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5477 && !((TARGET_POWERPC64
5478 && (mode == DImode || mode == TImode)
5479 && (INTVAL (XEXP (x, 1)) & 3) != 0)
5480 || SPE_VECTOR_MODE (mode)
5481 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5482 || mode == DImode || mode == DDmode
5483 || mode == TDmode))))
5485 HOST_WIDE_INT high_int, low_int;
5487 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5488 if (low_int >= 0x8000 - extra)
5490 high_int = INTVAL (XEXP (x, 1)) - low_int;
5491 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5492 GEN_INT (high_int)), 0);
5493 return plus_constant (Pmode, sum, low_int);
5495 else if (GET_CODE (x) == PLUS
5496 && GET_CODE (XEXP (x, 0)) == REG
5497 && GET_CODE (XEXP (x, 1)) != CONST_INT
5498 && GET_MODE_NUNITS (mode) == 1
5499 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5501 || ((mode != DImode && mode != DFmode && mode != DDmode)
5502 || (TARGET_E500_DOUBLE && mode != DDmode)))
5503 && (TARGET_POWERPC64 || mode != DImode)
5504 && !avoiding_indexed_address_p (mode)
5509 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5510 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5512 else if (SPE_VECTOR_MODE (mode)
5513 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5514 || mode == DDmode || mode == TDmode
5515 || mode == DImode)))
5519 /* We accept [reg + reg] and [reg + OFFSET]. */
5521 if (GET_CODE (x) == PLUS)
5523 rtx op1 = XEXP (x, 0);
5524 rtx op2 = XEXP (x, 1);
5527 op1 = force_reg (Pmode, op1);
5529 if (GET_CODE (op2) != REG
5530 && (GET_CODE (op2) != CONST_INT
5531 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5532 || (GET_MODE_SIZE (mode) > 8
5533 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5534 op2 = force_reg (Pmode, op2);
5536 /* We can't always do [reg + reg] for these, because [reg +
5537 reg + offset] is not a legitimate addressing mode. */
5538 y = gen_rtx_PLUS (Pmode, op1, op2);
5540 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5541 return force_reg (Pmode, y);
5546 return force_reg (Pmode, x);
5552 && GET_CODE (x) != CONST_INT
5553 && GET_CODE (x) != CONST_DOUBLE
5555 && GET_MODE_NUNITS (mode) == 1
5556 && (GET_MODE_BITSIZE (mode) <= 32
5557 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5558 && (mode == DFmode || mode == DDmode))))
5560 rtx reg = gen_reg_rtx (Pmode);
5561 emit_insn (gen_elf_high (reg, x));
5562 return gen_rtx_LO_SUM (Pmode, reg, x);
5564 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
5567 && ! MACHO_DYNAMIC_NO_PIC_P
5569 && GET_CODE (x) != CONST_INT
5570 && GET_CODE (x) != CONST_DOUBLE
5572 && GET_MODE_NUNITS (mode) == 1
5573 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5574 || (mode != DFmode && mode != DDmode))
5578 rtx reg = gen_reg_rtx (Pmode);
5579 emit_insn (gen_macho_high (reg, x));
5580 return gen_rtx_LO_SUM (Pmode, reg, x);
5583 && GET_CODE (x) == SYMBOL_REF
5584 && constant_pool_expr_p (x)
5585 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5586 return create_TOC_reference (x, NULL_RTX);
5591 /* Debug version of rs6000_legitimize_address. */
5593 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5599 ret = rs6000_legitimize_address (x, oldx, mode);
5600 insns = get_insns ();
5606 "\nrs6000_legitimize_address: mode %s, old code %s, "
5607 "new code %s, modified\n",
5608 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5609 GET_RTX_NAME (GET_CODE (ret)));
5611 fprintf (stderr, "Original address:\n");
5614 fprintf (stderr, "oldx:\n");
5617 fprintf (stderr, "New address:\n");
5622 fprintf (stderr, "Insns added:\n");
5623 debug_rtx_list (insns, 20);
5629 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5630 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5641 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5642 We need to emit DTP-relative relocations. */
5644 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5646 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5651 fputs ("\t.long\t", file);
5654 fputs (DOUBLE_INT_ASM_OP, file);
5659 output_addr_const (file, x);
5660 fputs ("@dtprel+0x8000", file);
5663 /* In the name of slightly smaller debug output, and to cater to
5664 general assembler lossage, recognize various UNSPEC sequences
5665 and turn them back into a direct symbol reference. */
5668 rs6000_delegitimize_address (rtx orig_x)
5672 orig_x = delegitimize_mem_from_attrs (orig_x);
5678 if (TARGET_CMODEL != CMODEL_SMALL
5679 && GET_CODE (y) == LO_SUM)
5683 if (GET_CODE (y) == PLUS
5684 && GET_MODE (y) == Pmode
5685 && CONST_INT_P (XEXP (y, 1)))
5687 offset = XEXP (y, 1);
5691 if (GET_CODE (y) == UNSPEC
5692 && XINT (y, 1) == UNSPEC_TOCREL)
5694 #ifdef ENABLE_CHECKING
5695 if (REG_P (XVECEXP (y, 0, 1))
5696 && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
5700 else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
5702 /* Weirdness alert. df_note_compute can replace r2 with a
5703 debug_expr when this unspec is in a debug_insn.
5704 Seen in gcc.dg/pr51957-1.c */
5712 y = XVECEXP (y, 0, 0);
5713 if (offset != NULL_RTX)
5714 y = gen_rtx_PLUS (Pmode, y, offset);
5715 if (!MEM_P (orig_x))
5718 return replace_equiv_address_nv (orig_x, y);
5722 && GET_CODE (orig_x) == LO_SUM
5723 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5725 y = XEXP (XEXP (orig_x, 1), 0);
5726 if (GET_CODE (y) == UNSPEC
5727 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5728 return XVECEXP (y, 0, 0);
5734 /* Return true if X shouldn't be emitted into the debug info.
5735 The linker doesn't like .toc section references from
5736 .debug_* sections, so reject .toc section symbols. */
5739 rs6000_const_not_ok_for_debug_p (rtx x)
5741 if (GET_CODE (x) == SYMBOL_REF
5742 && CONSTANT_POOL_ADDRESS_P (x))
5744 rtx c = get_pool_constant (x);
5745 enum machine_mode cmode = get_pool_mode (x);
5746 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
5753 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5755 static GTY(()) rtx rs6000_tls_symbol;
5757 rs6000_tls_get_addr (void)
5759 if (!rs6000_tls_symbol)
5760 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5762 return rs6000_tls_symbol;
5765 /* Construct the SYMBOL_REF for TLS GOT references. */
5767 static GTY(()) rtx rs6000_got_symbol;
5769 rs6000_got_sym (void)
5771 if (!rs6000_got_symbol)
5773 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5774 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5775 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5778 return rs6000_got_symbol;
5781 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5782 this (thread-local) address. */
5785 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5789 dest = gen_reg_rtx (Pmode);
5790 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5796 tlsreg = gen_rtx_REG (Pmode, 13);
5797 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5801 tlsreg = gen_rtx_REG (Pmode, 2);
5802 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5806 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5810 tmp = gen_reg_rtx (Pmode);
5813 tlsreg = gen_rtx_REG (Pmode, 13);
5814 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5818 tlsreg = gen_rtx_REG (Pmode, 2);
5819 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
5823 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
5825 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
5830 rtx r3, got, tga, tmp1, tmp2, call_insn;
5832 /* We currently use relocations like @got@tlsgd for tls, which
5833 means the linker will handle allocation of tls entries, placing
5834 them in the .got section. So use a pointer to the .got section,
5835 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5836 or to secondary GOT sections used by 32-bit -fPIC. */
5838 got = gen_rtx_REG (Pmode, 2);
5842 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
5845 rtx gsym = rs6000_got_sym ();
5846 got = gen_reg_rtx (Pmode);
5848 rs6000_emit_move (got, gsym, Pmode);
5853 tmp1 = gen_reg_rtx (Pmode);
5854 tmp2 = gen_reg_rtx (Pmode);
5855 mem = gen_const_mem (Pmode, tmp1);
5856 lab = gen_label_rtx ();
5857 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
5858 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
5859 if (TARGET_LINK_STACK)
5860 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
5861 emit_move_insn (tmp2, mem);
5862 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
5863 set_unique_reg_note (last, REG_EQUAL, gsym);
5868 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
5870 tga = rs6000_tls_get_addr ();
5871 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
5872 1, const0_rtx, Pmode);
5874 r3 = gen_rtx_REG (Pmode, 3);
5875 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5876 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
5877 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5878 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
5879 else if (DEFAULT_ABI == ABI_V4)
5880 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
5883 call_insn = last_call_insn ();
5884 PATTERN (call_insn) = insn;
5885 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5886 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5887 pic_offset_table_rtx);
5889 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
5891 tga = rs6000_tls_get_addr ();
5892 tmp1 = gen_reg_rtx (Pmode);
5893 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
5894 1, const0_rtx, Pmode);
5896 r3 = gen_rtx_REG (Pmode, 3);
5897 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5898 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
5899 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5900 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
5901 else if (DEFAULT_ABI == ABI_V4)
5902 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
5905 call_insn = last_call_insn ();
5906 PATTERN (call_insn) = insn;
5907 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5908 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5909 pic_offset_table_rtx);
5911 if (rs6000_tls_size == 16)
5914 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
5916 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
5918 else if (rs6000_tls_size == 32)
5920 tmp2 = gen_reg_rtx (Pmode);
5922 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
5924 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
5927 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
5929 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
5933 tmp2 = gen_reg_rtx (Pmode);
5935 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
5937 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
5939 insn = gen_rtx_SET (Pmode, dest,
5940 gen_rtx_PLUS (Pmode, tmp2, tmp1));
5946 /* IE, or 64-bit offset LE. */
5947 tmp2 = gen_reg_rtx (Pmode);
5949 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
5951 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
5954 insn = gen_tls_tls_64 (dest, tmp2, addr);
5956 insn = gen_tls_tls_32 (dest, tmp2, addr);
5964 /* Return 1 if X contains a thread-local symbol. */
5967 rs6000_tls_referenced_p (rtx x)
5969 if (! TARGET_HAVE_TLS)
5972 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
5975 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
5978 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5980 if (GET_CODE (x) == HIGH
5981 && GET_CODE (XEXP (x, 0)) == UNSPEC)
5984 return rs6000_tls_referenced_p (x);
5987 /* Return 1 if *X is a thread-local symbol. This is the same as
5988 rs6000_tls_symbol_ref except for the type of the unused argument. */
5991 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
5993 return RS6000_SYMBOL_REF_TLS_P (*x);
5996 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
5997 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
5998 can be addressed relative to the toc pointer. */
6001 use_toc_relative_ref (rtx sym)
6003 return ((constant_pool_expr_p (sym)
6004 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
6005 get_pool_mode (sym)))
6006 || (TARGET_CMODEL == CMODEL_MEDIUM
6007 && !CONSTANT_POOL_ADDRESS_P (sym)
6008 && SYMBOL_REF_LOCAL_P (sym)));
6011 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6012 replace the input X, or the original X if no replacement is called for.
6013 The output parameter *WIN is 1 if the calling macro should goto WIN,
6016 For RS/6000, we wish to handle large displacements off a base
6017 register by splitting the addend across an addiu/addis and the mem insn.
6018 This cuts number of extra insns needed from 3 to 1.
6020 On Darwin, we use this to generate code for floating point constants.
6021 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6022 The Darwin code is inside #if TARGET_MACHO because only then are the
6023 machopic_* functions defined. */
6025 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6026 int opnum, int type,
6027 int ind_levels ATTRIBUTE_UNUSED, int *win)
6029 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6031 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6032 DFmode/DImode MEM. */
6035 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6036 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6037 reg_offset_p = false;
6039 /* We must recognize output that we have already generated ourselves. */
6040 if (GET_CODE (x) == PLUS
6041 && GET_CODE (XEXP (x, 0)) == PLUS
6042 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6043 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6044 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6046 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6047 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6048 opnum, (enum reload_type) type);
6053 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6054 if (GET_CODE (x) == LO_SUM
6055 && GET_CODE (XEXP (x, 0)) == HIGH)
6057 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6058 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6059 opnum, (enum reload_type) type);
6065 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6066 && GET_CODE (x) == LO_SUM
6067 && GET_CODE (XEXP (x, 0)) == PLUS
6068 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6069 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6070 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6071 && machopic_operand_p (XEXP (x, 1)))
6073 /* Result of previous invocation of this function on Darwin
6074 floating point constant. */
6075 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6076 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6077 opnum, (enum reload_type) type);
6083 if (TARGET_CMODEL != CMODEL_SMALL
6085 && small_toc_ref (x, VOIDmode))
6087 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
6088 x = gen_rtx_LO_SUM (Pmode, hi, x);
6089 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6090 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6091 opnum, (enum reload_type) type);
6096 /* Force ld/std non-word aligned offset into base register by wrapping
6098 if (GET_CODE (x) == PLUS
6099 && GET_CODE (XEXP (x, 0)) == REG
6100 && REGNO (XEXP (x, 0)) < 32
6101 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6102 && GET_CODE (XEXP (x, 1)) == CONST_INT
6104 && (INTVAL (XEXP (x, 1)) & 3) != 0
6105 && VECTOR_MEM_NONE_P (mode)
6106 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
6107 && TARGET_POWERPC64)
6109 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
6110 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6111 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6112 opnum, (enum reload_type) type);
6117 if (GET_CODE (x) == PLUS
6118 && GET_CODE (XEXP (x, 0)) == REG
6119 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6120 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6121 && GET_CODE (XEXP (x, 1)) == CONST_INT
6123 && !SPE_VECTOR_MODE (mode)
6124 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6125 || mode == DDmode || mode == TDmode
6127 && VECTOR_MEM_NONE_P (mode))
6129 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6130 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6132 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6134 /* Check for 32-bit overflow. */
6135 if (high + low != val)
6141 /* Reload the high part into a base reg; leave the low part
6142 in the mem directly. */
6144 x = gen_rtx_PLUS (GET_MODE (x),
6145 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6149 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6150 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6151 opnum, (enum reload_type) type);
6156 if (GET_CODE (x) == SYMBOL_REF
6158 && VECTOR_MEM_NONE_P (mode)
6159 && !SPE_VECTOR_MODE (mode)
6161 && DEFAULT_ABI == ABI_DARWIN
6162 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6163 && machopic_symbol_defined_p (x)
6165 && DEFAULT_ABI == ABI_V4
6168 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6169 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6173 && (mode != DImode || TARGET_POWERPC64)
6174 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6175 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6180 rtx offset = machopic_gen_offset (x);
6181 x = gen_rtx_LO_SUM (GET_MODE (x),
6182 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6183 gen_rtx_HIGH (Pmode, offset)), offset);
6187 x = gen_rtx_LO_SUM (GET_MODE (x),
6188 gen_rtx_HIGH (Pmode, x), x);
6190 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6191 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6192 opnum, (enum reload_type) type);
6197 /* Reload an offset address wrapped by an AND that represents the
6198 masking of the lower bits. Strip the outer AND and let reload
6199 convert the offset address into an indirect address. For VSX,
6200 force reload to create the address with an AND in a separate
6201 register, because we can't guarantee an altivec register will
6203 if (VECTOR_MEM_ALTIVEC_P (mode)
6204 && GET_CODE (x) == AND
6205 && GET_CODE (XEXP (x, 0)) == PLUS
6206 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6207 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6208 && GET_CODE (XEXP (x, 1)) == CONST_INT
6209 && INTVAL (XEXP (x, 1)) == -16)
6218 && GET_CODE (x) == SYMBOL_REF
6219 && use_toc_relative_ref (x))
6221 x = create_TOC_reference (x, NULL_RTX);
6222 if (TARGET_CMODEL != CMODEL_SMALL)
6223 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6224 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6225 opnum, (enum reload_type) type);
6233 /* Debug version of rs6000_legitimize_reload_address. */
6235 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6236 int opnum, int type,
6237 int ind_levels, int *win)
6239 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6242 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6243 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6244 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6248 fprintf (stderr, "Same address returned\n");
6250 fprintf (stderr, "NULL returned\n");
6253 fprintf (stderr, "New address:\n");
6260 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6261 that is a valid memory address for an instruction.
6262 The MODE argument is the machine mode for the MEM expression
6263 that wants to use this address.
6265 On the RS/6000, there are four valid address: a SYMBOL_REF that
6266 refers to a constant pool entry of an address (or the sum of it
6267 plus a constant), a short (16-bit signed) constant plus a register,
6268 the sum of two registers, or a register indirect, possibly with an
6269 auto-increment. For DFmode, DDmode and DImode with a constant plus
6270 register, we must ensure that both words are addressable or PowerPC64
6271 with offset word aligned.
6273 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6274 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6275 because adjacent memory cells are accessed by adding word-sized offsets
6276 during assembly output. */
6278 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6280 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6282 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6283 if (VECTOR_MEM_ALTIVEC_P (mode)
6284 && GET_CODE (x) == AND
6285 && GET_CODE (XEXP (x, 1)) == CONST_INT
6286 && INTVAL (XEXP (x, 1)) == -16)
6289 if (RS6000_SYMBOL_REF_TLS_P (x))
6291 if (legitimate_indirect_address_p (x, reg_ok_strict))
6293 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6294 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6295 && !SPE_VECTOR_MODE (mode)
6298 /* Restrict addressing for DI because of our SUBREG hackery. */
6299 && !(TARGET_E500_DOUBLE
6300 && (mode == DFmode || mode == DDmode || mode == DImode))
6302 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6304 if (virtual_stack_registers_memory_p (x))
6306 if (reg_offset_p && legitimate_small_data_p (mode, x))
6309 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6311 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6314 && GET_CODE (x) == PLUS
6315 && GET_CODE (XEXP (x, 0)) == REG
6316 && (XEXP (x, 0) == virtual_stack_vars_rtx
6317 || XEXP (x, 0) == arg_pointer_rtx)
6318 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6320 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
6325 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6327 || (mode != DFmode && mode != DDmode)
6328 || (TARGET_E500_DOUBLE && mode != DDmode))
6329 && (TARGET_POWERPC64 || mode != DImode)
6330 && !avoiding_indexed_address_p (mode)
6331 && legitimate_indexed_address_p (x, reg_ok_strict))
6333 if (GET_CODE (x) == PRE_MODIFY
6337 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6339 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6340 && (TARGET_POWERPC64 || mode != DImode)
6341 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6342 && !SPE_VECTOR_MODE (mode)
6343 /* Restrict addressing for DI because of our SUBREG hackery. */
6344 && !(TARGET_E500_DOUBLE
6345 && (mode == DFmode || mode == DDmode || mode == DImode))
6347 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6348 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
6349 || (!avoiding_indexed_address_p (mode)
6350 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6351 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6353 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6358 /* Debug version of rs6000_legitimate_address_p. */
6360 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6363 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6365 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6366 "strict = %d, code = %s\n",
6367 ret ? "true" : "false",
6368 GET_MODE_NAME (mode),
6370 GET_RTX_NAME (GET_CODE (x)));
6376 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6379 rs6000_mode_dependent_address_p (const_rtx addr)
6381 return rs6000_mode_dependent_address_ptr (addr);
6384 /* Go to LABEL if ADDR (a legitimate address expression)
6385 has an effect that depends on the machine mode it is used for.
6387 On the RS/6000 this is true of all integral offsets (since AltiVec
6388 and VSX modes don't allow them) or is a pre-increment or decrement.
6390 ??? Except that due to conceptual problems in offsettable_address_p
6391 we can't really report the problems of integral offsets. So leave
6392 this assuming that the adjustable offset must be valid for the
6393 sub-words of a TFmode operand, which is what we had before. */
6396 rs6000_mode_dependent_address (const_rtx addr)
6398 switch (GET_CODE (addr))
6401 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6402 is considered a legitimate address before reload, so there
6403 are no offset restrictions in that case. Note that this
6404 condition is safe in strict mode because any address involving
6405 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6406 been rejected as illegitimate. */
6407 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6408 && XEXP (addr, 0) != arg_pointer_rtx
6409 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6411 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6412 return val + 12 + 0x8000 >= 0x10000;
6417 /* Anything in the constant pool is sufficiently aligned that
6418 all bytes have the same high part address. */
6419 return !legitimate_constant_pool_address_p (addr, QImode, false);
6421 /* Auto-increment cases are now treated generically in recog.c. */
6423 return TARGET_UPDATE;
6425 /* AND is only allowed in Altivec loads. */
6436 /* Debug version of rs6000_mode_dependent_address. */
6438 rs6000_debug_mode_dependent_address (const_rtx addr)
6440 bool ret = rs6000_mode_dependent_address (addr);
6442 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6443 ret ? "true" : "false");
6449 /* Implement FIND_BASE_TERM. */
6452 rs6000_find_base_term (rtx op)
6457 if (GET_CODE (base) == CONST)
6458 base = XEXP (base, 0);
6459 if (GET_CODE (base) == PLUS)
6460 base = XEXP (base, 0);
6461 if (GET_CODE (base) == UNSPEC)
6462 switch (XINT (base, 1))
6465 case UNSPEC_MACHOPIC_OFFSET:
6466 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6467 for aliasing purposes. */
6468 return XVECEXP (base, 0, 0);
6474 /* More elaborate version of recog's offsettable_memref_p predicate
6475 that works around the ??? note of rs6000_mode_dependent_address.
6476 In particular it accepts
6478 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6480 in 32-bit mode, that the recog predicate rejects. */
6483 rs6000_offsettable_memref_p (rtx op)
6488 /* First mimic offsettable_memref_p. */
6489 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
6492 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6493 the latter predicate knows nothing about the mode of the memory
6494 reference and, therefore, assumes that it is the largest supported
6495 mode (TFmode). As a consequence, legitimate offsettable memory
6496 references are rejected. rs6000_legitimate_offset_address_p contains
6497 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6498 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
6501 /* Change register usage conditional on target flags. */
6503 rs6000_conditional_register_usage (void)
6507 if (TARGET_DEBUG_TARGET)
6508 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6510 /* Set MQ register fixed (already call_used) if not POWER
6511 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6516 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6518 fixed_regs[13] = call_used_regs[13]
6519 = call_really_used_regs[13] = 1;
6521 /* Conditionally disable FPRs. */
6522 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6523 for (i = 32; i < 64; i++)
6524 fixed_regs[i] = call_used_regs[i]
6525 = call_really_used_regs[i] = 1;
6527 /* The TOC register is not killed across calls in a way that is
6528 visible to the compiler. */
6529 if (DEFAULT_ABI == ABI_AIX)
6530 call_really_used_regs[2] = 0;
6532 if (DEFAULT_ABI == ABI_V4
6533 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6535 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6537 if (DEFAULT_ABI == ABI_V4
6538 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6540 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6541 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6542 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6544 if (DEFAULT_ABI == ABI_DARWIN
6545 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6546 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6547 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6548 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6550 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6551 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6552 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6556 global_regs[SPEFSCR_REGNO] = 1;
6557 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6558 registers in prologues and epilogues. We no longer use r14
6559 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6560 pool for link-compatibility with older versions of GCC. Once
6561 "old" code has died out, we can return r14 to the allocation
6564 = call_used_regs[14]
6565 = call_really_used_regs[14] = 1;
6568 if (!TARGET_ALTIVEC && !TARGET_VSX)
6570 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6571 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6572 call_really_used_regs[VRSAVE_REGNO] = 1;
6575 if (TARGET_ALTIVEC || TARGET_VSX)
6576 global_regs[VSCR_REGNO] = 1;
6578 if (TARGET_ALTIVEC_ABI)
6580 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6581 call_used_regs[i] = call_really_used_regs[i] = 1;
6583 /* AIX reserves VR20:31 in non-extended ABI mode. */
6585 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6586 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6590 /* Try to output insns to set TARGET equal to the constant C if it can
6591 be done in less than N insns. Do all computations in MODE.
6592 Returns the place where the output has been placed if it can be
6593 done and the insns have been emitted. If it would take more than N
6594 insns, zero is returned and no insns and emitted. */
6597 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6598 rtx source, int n ATTRIBUTE_UNUSED)
6600 rtx result, insn, set;
6601 HOST_WIDE_INT c0, c1;
6608 dest = gen_reg_rtx (mode);
6609 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6613 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6615 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6616 GEN_INT (INTVAL (source)
6617 & (~ (HOST_WIDE_INT) 0xffff))));
6618 emit_insn (gen_rtx_SET (VOIDmode, dest,
6619 gen_rtx_IOR (SImode, copy_rtx (result),
6620 GEN_INT (INTVAL (source) & 0xffff))));
6625 switch (GET_CODE (source))
6628 c0 = INTVAL (source);
6633 #if HOST_BITS_PER_WIDE_INT >= 64
6634 c0 = CONST_DOUBLE_LOW (source);
6637 c0 = CONST_DOUBLE_LOW (source);
6638 c1 = CONST_DOUBLE_HIGH (source);
6646 result = rs6000_emit_set_long_const (dest, c0, c1);
6653 insn = get_last_insn ();
6654 set = single_set (insn);
6655 if (! CONSTANT_P (SET_SRC (set)))
6656 set_unique_reg_note (insn, REG_EQUAL, source);
6661 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6662 fall back to a straight forward decomposition. We do this to avoid
6663 exponential run times encountered when looking for longer sequences
6664 with rs6000_emit_set_const. */
6666 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6668 if (!TARGET_POWERPC64)
6670 rtx operand1, operand2;
6672 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6674 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6676 emit_move_insn (operand1, GEN_INT (c1));
6677 emit_move_insn (operand2, GEN_INT (c2));
6681 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6684 ud2 = (c1 & 0xffff0000) >> 16;
6685 #if HOST_BITS_PER_WIDE_INT >= 64
6689 ud4 = (c2 & 0xffff0000) >> 16;
6691 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6692 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6695 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6697 emit_move_insn (dest, GEN_INT (ud1));
6700 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6701 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6704 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6707 emit_move_insn (dest, GEN_INT (ud2 << 16));
6709 emit_move_insn (copy_rtx (dest),
6710 gen_rtx_IOR (DImode, copy_rtx (dest),
6713 else if (ud3 == 0 && ud4 == 0)
6715 gcc_assert (ud2 & 0x8000);
6716 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6719 emit_move_insn (copy_rtx (dest),
6720 gen_rtx_IOR (DImode, copy_rtx (dest),
6722 emit_move_insn (copy_rtx (dest),
6723 gen_rtx_ZERO_EXTEND (DImode,
6724 gen_lowpart (SImode,
6727 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6728 || (ud4 == 0 && ! (ud3 & 0x8000)))
6731 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6734 emit_move_insn (dest, GEN_INT (ud3 << 16));
6737 emit_move_insn (copy_rtx (dest),
6738 gen_rtx_IOR (DImode, copy_rtx (dest),
6740 emit_move_insn (copy_rtx (dest),
6741 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6744 emit_move_insn (copy_rtx (dest),
6745 gen_rtx_IOR (DImode, copy_rtx (dest),
6751 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6754 emit_move_insn (dest, GEN_INT (ud4 << 16));
6757 emit_move_insn (copy_rtx (dest),
6758 gen_rtx_IOR (DImode, copy_rtx (dest),
6761 emit_move_insn (copy_rtx (dest),
6762 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6765 emit_move_insn (copy_rtx (dest),
6766 gen_rtx_IOR (DImode, copy_rtx (dest),
6767 GEN_INT (ud2 << 16)));
6769 emit_move_insn (copy_rtx (dest),
6770 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6776 /* Helper for the following. Get rid of [r+r] memory refs
6777 in cases where it won't work (TImode, TFmode, TDmode). */
6780 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6782 if (reload_in_progress)
6785 if (GET_CODE (operands[0]) == MEM
6786 && GET_CODE (XEXP (operands[0], 0)) != REG
6787 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6788 GET_MODE (operands[0]), false))
6790 = replace_equiv_address (operands[0],
6791 copy_addr_to_reg (XEXP (operands[0], 0)));
6793 if (GET_CODE (operands[1]) == MEM
6794 && GET_CODE (XEXP (operands[1], 0)) != REG
6795 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6796 GET_MODE (operands[1]), false))
6798 = replace_equiv_address (operands[1],
6799 copy_addr_to_reg (XEXP (operands[1], 0)));
6802 /* Emit a move from SOURCE to DEST in mode MODE. */
6804 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6808 operands[1] = source;
6810 if (TARGET_DEBUG_ADDR)
6813 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6814 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6815 GET_MODE_NAME (mode),
6818 can_create_pseudo_p ());
6820 fprintf (stderr, "source:\n");
6824 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6825 if (GET_CODE (operands[1]) == CONST_DOUBLE
6826 && ! FLOAT_MODE_P (mode)
6827 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6829 /* FIXME. This should never happen. */
6830 /* Since it seems that it does, do the safe thing and convert
6832 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
6834 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
6835 || FLOAT_MODE_P (mode)
6836 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
6837 || CONST_DOUBLE_LOW (operands[1]) < 0)
6838 && (CONST_DOUBLE_HIGH (operands[1]) != -1
6839 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
6841 /* Check if GCC is setting up a block move that will end up using FP
6842 registers as temporaries. We must make sure this is acceptable. */
6843 if (GET_CODE (operands[0]) == MEM
6844 && GET_CODE (operands[1]) == MEM
6846 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
6847 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
6848 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
6849 ? 32 : MEM_ALIGN (operands[0])))
6850 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
6852 : MEM_ALIGN (operands[1]))))
6853 && ! MEM_VOLATILE_P (operands [0])
6854 && ! MEM_VOLATILE_P (operands [1]))
6856 emit_move_insn (adjust_address (operands[0], SImode, 0),
6857 adjust_address (operands[1], SImode, 0));
6858 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
6859 adjust_address (copy_rtx (operands[1]), SImode, 4));
6863 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
6864 && !gpc_reg_operand (operands[1], mode))
6865 operands[1] = force_reg (mode, operands[1]);
6867 if (mode == SFmode && ! TARGET_POWERPC
6868 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6869 && GET_CODE (operands[0]) == MEM)
6873 if (reload_in_progress || reload_completed)
6874 regnum = true_regnum (operands[1]);
6875 else if (GET_CODE (operands[1]) == REG)
6876 regnum = REGNO (operands[1]);
6880 /* If operands[1] is a register, on POWER it may have
6881 double-precision data in it, so truncate it to single
6883 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
6886 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
6887 : gen_reg_rtx (mode));
6888 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6889 operands[1] = newreg;
6893 /* Recognize the case where operand[1] is a reference to thread-local
6894 data and load its address to a register. */
6895 if (rs6000_tls_referenced_p (operands[1]))
6897 enum tls_model model;
6898 rtx tmp = operands[1];
6901 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
6903 addend = XEXP (XEXP (tmp, 0), 1);
6904 tmp = XEXP (XEXP (tmp, 0), 0);
6907 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
6908 model = SYMBOL_REF_TLS_MODEL (tmp);
6909 gcc_assert (model != 0);
6911 tmp = rs6000_legitimize_tls_address (tmp, model);
6914 tmp = gen_rtx_PLUS (mode, tmp, addend);
6915 tmp = force_operand (tmp, operands[0]);
6920 /* Handle the case where reload calls us with an invalid address. */
6921 if (reload_in_progress && mode == Pmode
6922 && (! general_operand (operands[1], mode)
6923 || ! nonimmediate_operand (operands[0], mode)))
6926 /* 128-bit constant floating-point values on Darwin should really be
6927 loaded as two parts. */
6928 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6929 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
6931 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
6932 simplify_gen_subreg (DFmode, operands[1], mode, 0),
6934 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
6935 GET_MODE_SIZE (DFmode)),
6936 simplify_gen_subreg (DFmode, operands[1], mode,
6937 GET_MODE_SIZE (DFmode)),
6942 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
6943 cfun->machine->sdmode_stack_slot =
6944 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
6946 if (reload_in_progress
6948 && MEM_P (operands[0])
6949 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
6950 && REG_P (operands[1]))
6952 if (FP_REGNO_P (REGNO (operands[1])))
6954 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
6955 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6956 emit_insn (gen_movsd_store (mem, operands[1]));
6958 else if (INT_REGNO_P (REGNO (operands[1])))
6960 rtx mem = adjust_address_nv (operands[0], mode, 4);
6961 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6962 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
6968 if (reload_in_progress
6970 && REG_P (operands[0])
6971 && MEM_P (operands[1])
6972 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
6974 if (FP_REGNO_P (REGNO (operands[0])))
6976 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
6977 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6978 emit_insn (gen_movsd_load (operands[0], mem));
6980 else if (INT_REGNO_P (REGNO (operands[0])))
6982 rtx mem = adjust_address_nv (operands[1], mode, 4);
6983 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6984 emit_insn (gen_movsd_hardfloat (operands[0], mem));
6991 /* FIXME: In the long term, this switch statement should go away
6992 and be replaced by a sequence of tests based on things like
6998 if (CONSTANT_P (operands[1])
6999 && GET_CODE (operands[1]) != CONST_INT)
7000 operands[1] = force_const_mem (mode, operands[1]);
7005 rs6000_eliminate_indexed_memrefs (operands);
7012 if (CONSTANT_P (operands[1])
7013 && ! easy_fp_constant (operands[1], mode))
7014 operands[1] = force_const_mem (mode, operands[1]);
7027 if (CONSTANT_P (operands[1])
7028 && !easy_vector_constant (operands[1], mode))
7029 operands[1] = force_const_mem (mode, operands[1]);
7034 /* Use default pattern for address of ELF small data */
7037 && DEFAULT_ABI == ABI_V4
7038 && (GET_CODE (operands[1]) == SYMBOL_REF
7039 || GET_CODE (operands[1]) == CONST)
7040 && small_data_operand (operands[1], mode))
7042 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7046 if (DEFAULT_ABI == ABI_V4
7047 && mode == Pmode && mode == SImode
7048 && flag_pic == 1 && got_operand (operands[1], mode))
7050 emit_insn (gen_movsi_got (operands[0], operands[1]));
7054 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7058 && CONSTANT_P (operands[1])
7059 && GET_CODE (operands[1]) != HIGH
7060 && GET_CODE (operands[1]) != CONST_INT)
7062 rtx target = (!can_create_pseudo_p ()
7064 : gen_reg_rtx (mode));
7066 /* If this is a function address on -mcall-aixdesc,
7067 convert it to the address of the descriptor. */
7068 if (DEFAULT_ABI == ABI_AIX
7069 && GET_CODE (operands[1]) == SYMBOL_REF
7070 && XSTR (operands[1], 0)[0] == '.')
7072 const char *name = XSTR (operands[1], 0);
7074 while (*name == '.')
7076 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7077 CONSTANT_POOL_ADDRESS_P (new_ref)
7078 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7079 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7080 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7081 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7082 operands[1] = new_ref;
7085 if (DEFAULT_ABI == ABI_DARWIN)
7088 if (MACHO_DYNAMIC_NO_PIC_P)
7090 /* Take care of any required data indirection. */
7091 operands[1] = rs6000_machopic_legitimize_pic_address (
7092 operands[1], mode, operands[0]);
7093 if (operands[0] != operands[1])
7094 emit_insn (gen_rtx_SET (VOIDmode,
7095 operands[0], operands[1]));
7099 emit_insn (gen_macho_high (target, operands[1]));
7100 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7104 emit_insn (gen_elf_high (target, operands[1]));
7105 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7109 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7110 and we have put it in the TOC, we just need to make a TOC-relative
7113 && GET_CODE (operands[1]) == SYMBOL_REF
7114 && use_toc_relative_ref (operands[1]))
7115 operands[1] = create_TOC_reference (operands[1], operands[0]);
7116 else if (mode == Pmode
7117 && CONSTANT_P (operands[1])
7118 && GET_CODE (operands[1]) != HIGH
7119 && ((GET_CODE (operands[1]) != CONST_INT
7120 && ! easy_fp_constant (operands[1], mode))
7121 || (GET_CODE (operands[1]) == CONST_INT
7122 && (num_insns_constant (operands[1], mode)
7123 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7124 || (GET_CODE (operands[0]) == REG
7125 && FP_REGNO_P (REGNO (operands[0]))))
7126 && !toc_relative_expr_p (operands[1], false)
7127 && (TARGET_CMODEL == CMODEL_SMALL
7128 || can_create_pseudo_p ()
7129 || (REG_P (operands[0])
7130 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7134 /* Darwin uses a special PIC legitimizer. */
7135 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7138 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7140 if (operands[0] != operands[1])
7141 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7146 /* If we are to limit the number of things we put in the TOC and
7147 this is a symbol plus a constant we can add in one insn,
7148 just put the symbol in the TOC and add the constant. Don't do
7149 this if reload is in progress. */
7150 if (GET_CODE (operands[1]) == CONST
7151 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7152 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7153 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7154 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7155 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7156 && ! side_effects_p (operands[0]))
7159 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7160 rtx other = XEXP (XEXP (operands[1], 0), 1);
7162 sym = force_reg (mode, sym);
7163 emit_insn (gen_add3_insn (operands[0], sym, other));
7167 operands[1] = force_const_mem (mode, operands[1]);
7170 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7171 && constant_pool_expr_p (XEXP (operands[1], 0))
7172 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7173 get_pool_constant (XEXP (operands[1], 0)),
7174 get_pool_mode (XEXP (operands[1], 0))))
7176 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
7178 operands[1] = gen_const_mem (mode, tocref);
7179 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7185 rs6000_eliminate_indexed_memrefs (operands);
7189 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7191 gen_rtx_SET (VOIDmode,
7192 operands[0], operands[1]),
7193 gen_rtx_CLOBBER (VOIDmode,
7194 gen_rtx_SCRATCH (SImode)))));
7200 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7203 /* Above, we may have called force_const_mem which may have returned
7204 an invalid address. If we can, fix this up; otherwise, reload will
7205 have to deal with it. */
7206 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7207 operands[1] = validize_mem (operands[1]);
7210 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7213 /* Nonzero if we can use a floating-point register to pass this arg. */
7214 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7215 (SCALAR_FLOAT_MODE_P (MODE) \
7216 && (CUM)->fregno <= FP_ARG_MAX_REG \
7217 && TARGET_HARD_FLOAT && TARGET_FPRS)
7219 /* Nonzero if we can use an AltiVec register to pass this arg. */
7220 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7221 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7222 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7223 && TARGET_ALTIVEC_ABI \
7226 /* Return a nonzero value to say to return the function value in
7227 memory, just as large structures are always returned. TYPE will be
7228 the data type of the value, and FNTYPE will be the type of the
7229 function doing the returning, or @code{NULL} for libcalls.
7231 The AIX ABI for the RS/6000 specifies that all structures are
7232 returned in memory. The Darwin ABI does the same.
7234 For the Darwin 64 Bit ABI, a function result can be returned in
7235 registers or in memory, depending on the size of the return data
7236 type. If it is returned in registers, the value occupies the same
7237 registers as it would if it were the first and only function
7238 argument. Otherwise, the function places its result in memory at
7239 the location pointed to by GPR3.
7241 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7242 but a draft put them in memory, and GCC used to implement the draft
7243 instead of the final standard. Therefore, aix_struct_return
7244 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7245 compatibility can change DRAFT_V4_STRUCT_RET to override the
7246 default, and -m switches get the final word. See
7247 rs6000_option_override_internal for more details.
7249 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7250 long double support is enabled. These values are returned in memory.
7252 int_size_in_bytes returns -1 for variable size objects, which go in
7253 memory always. The cast to unsigned makes -1 > 8. */
7256 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7258 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7260 && rs6000_darwin64_abi
7261 && TREE_CODE (type) == RECORD_TYPE
7262 && int_size_in_bytes (type) > 0)
7264 CUMULATIVE_ARGS valcum;
7268 valcum.fregno = FP_ARG_MIN_REG;
7269 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7270 /* Do a trial code generation as if this were going to be passed
7271 as an argument; if any part goes in memory, we return NULL. */
7272 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7275 /* Otherwise fall through to more conventional ABI rules. */
7278 if (AGGREGATE_TYPE_P (type)
7279 && (aix_struct_return
7280 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7283 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7284 modes only exist for GCC vector types if -maltivec. */
7285 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7286 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7289 /* Return synthetic vectors in memory. */
7290 if (TREE_CODE (type) == VECTOR_TYPE
7291 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7293 static bool warned_for_return_big_vectors = false;
7294 if (!warned_for_return_big_vectors)
7296 warning (0, "GCC vector returned by reference: "
7297 "non-standard ABI extension with no compatibility guarantee");
7298 warned_for_return_big_vectors = true;
7303 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7309 #ifdef HAVE_AS_GNU_ATTRIBUTE
7310 /* Return TRUE if a call to function FNDECL may be one that
7311 potentially affects the function calling ABI of the object file. */
7314 call_ABI_of_interest (tree fndecl)
7316 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7318 struct cgraph_node *c_node;
7320 /* Libcalls are always interesting. */
7321 if (fndecl == NULL_TREE)
7324 /* Any call to an external function is interesting. */
7325 if (DECL_EXTERNAL (fndecl))
7328 /* Interesting functions that we are emitting in this object file. */
7329 c_node = cgraph_get_node (fndecl);
7330 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7331 return !cgraph_only_called_directly_p (c_node);
7337 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7338 for a call to a function whose data type is FNTYPE.
7339 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7341 For incoming args we set the number of arguments in the prototype large
7342 so we never return a PARALLEL. */
7345 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7346 rtx libname ATTRIBUTE_UNUSED, int incoming,
7347 int libcall, int n_named_args,
7348 tree fndecl ATTRIBUTE_UNUSED,
7349 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7351 static CUMULATIVE_ARGS zero_cumulative;
7353 *cum = zero_cumulative;
7355 cum->fregno = FP_ARG_MIN_REG;
7356 cum->vregno = ALTIVEC_ARG_MIN_REG;
7357 cum->prototype = (fntype && prototype_p (fntype));
7358 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7359 ? CALL_LIBCALL : CALL_NORMAL);
7360 cum->sysv_gregno = GP_ARG_MIN_REG;
7361 cum->stdarg = stdarg_p (fntype);
7363 cum->nargs_prototype = 0;
7364 if (incoming || cum->prototype)
7365 cum->nargs_prototype = n_named_args;
7367 /* Check for a longcall attribute. */
7368 if ((!fntype && rs6000_default_long_calls)
7370 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7371 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7372 cum->call_cookie |= CALL_LONG;
7374 if (TARGET_DEBUG_ARG)
7376 fprintf (stderr, "\ninit_cumulative_args:");
7379 tree ret_type = TREE_TYPE (fntype);
7380 fprintf (stderr, " ret code = %s,",
7381 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7384 if (cum->call_cookie & CALL_LONG)
7385 fprintf (stderr, " longcall,");
7387 fprintf (stderr, " proto = %d, nargs = %d\n",
7388 cum->prototype, cum->nargs_prototype);
7391 #ifdef HAVE_AS_GNU_ATTRIBUTE
7392 if (DEFAULT_ABI == ABI_V4)
7394 cum->escapes = call_ABI_of_interest (fndecl);
7401 return_type = TREE_TYPE (fntype);
7402 return_mode = TYPE_MODE (return_type);
7405 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7407 if (return_type != NULL)
7409 if (TREE_CODE (return_type) == RECORD_TYPE
7410 && TYPE_TRANSPARENT_AGGR (return_type))
7412 return_type = TREE_TYPE (first_field (return_type));
7413 return_mode = TYPE_MODE (return_type);
7415 if (AGGREGATE_TYPE_P (return_type)
7416 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7418 rs6000_returns_struct = true;
7420 if (SCALAR_FLOAT_MODE_P (return_mode))
7421 rs6000_passes_float = true;
7422 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7423 || SPE_VECTOR_MODE (return_mode))
7424 rs6000_passes_vector = true;
7431 && TARGET_ALTIVEC_ABI
7432 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7434 error ("cannot return value in vector register because"
7435 " altivec instructions are disabled, use -maltivec"
7440 /* Return true if TYPE must be passed on the stack and not in registers. */
7443 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7445 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7446 return must_pass_in_stack_var_size (mode, type);
7448 return must_pass_in_stack_var_size_or_pad (mode, type);
7451 /* If defined, a C expression which determines whether, and in which
7452 direction, to pad out an argument with extra space. The value
7453 should be of type `enum direction': either `upward' to pad above
7454 the argument, `downward' to pad below, or `none' to inhibit
7457 For the AIX ABI structs are always stored left shifted in their
7461 function_arg_padding (enum machine_mode mode, const_tree type)
7463 #ifndef AGGREGATE_PADDING_FIXED
7464 #define AGGREGATE_PADDING_FIXED 0
7466 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7467 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7470 if (!AGGREGATE_PADDING_FIXED)
7472 /* GCC used to pass structures of the same size as integer types as
7473 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7474 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7475 passed padded downward, except that -mstrict-align further
7476 muddied the water in that multi-component structures of 2 and 4
7477 bytes in size were passed padded upward.
7479 The following arranges for best compatibility with previous
7480 versions of gcc, but removes the -mstrict-align dependency. */
7481 if (BYTES_BIG_ENDIAN)
7483 HOST_WIDE_INT size = 0;
7485 if (mode == BLKmode)
7487 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7488 size = int_size_in_bytes (type);
7491 size = GET_MODE_SIZE (mode);
7493 if (size == 1 || size == 2 || size == 4)
7499 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7501 if (type != 0 && AGGREGATE_TYPE_P (type))
7505 /* Fall back to the default. */
7506 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7509 /* If defined, a C expression that gives the alignment boundary, in bits,
7510 of an argument with the specified mode and type. If it is not defined,
7511 PARM_BOUNDARY is used for all arguments.
7513 V.4 wants long longs and doubles to be double word aligned. Just
7514 testing the mode size is a boneheaded way to do this as it means
7515 that other types such as complex int are also double word aligned.
7516 However, we're stuck with this because changing the ABI might break
7517 existing library interfaces.
7519 Doubleword align SPE vectors.
7520 Quadword align Altivec/VSX vectors.
7521 Quadword align large synthetic vector types. */
7524 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7526 if (DEFAULT_ABI == ABI_V4
7527 && (GET_MODE_SIZE (mode) == 8
7528 || (TARGET_HARD_FLOAT
7530 && (mode == TFmode || mode == TDmode))))
7532 else if (SPE_VECTOR_MODE (mode)
7533 || (type && TREE_CODE (type) == VECTOR_TYPE
7534 && int_size_in_bytes (type) >= 8
7535 && int_size_in_bytes (type) < 16))
7537 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7538 || (type && TREE_CODE (type) == VECTOR_TYPE
7539 && int_size_in_bytes (type) >= 16))
7541 else if (TARGET_MACHO
7542 && rs6000_darwin64_abi
7544 && type && TYPE_ALIGN (type) > 64)
7547 return PARM_BOUNDARY;
7550 /* For a function parm of MODE and TYPE, return the starting word in
7551 the parameter area. NWORDS of the parameter area are already used. */
7554 rs6000_parm_start (enum machine_mode mode, const_tree type,
7555 unsigned int nwords)
7558 unsigned int parm_offset;
7560 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7561 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7562 return nwords + (-(parm_offset + nwords) & align);
7565 /* Compute the size (in words) of a function argument. */
7567 static unsigned long
7568 rs6000_arg_size (enum machine_mode mode, const_tree type)
7572 if (mode != BLKmode)
7573 size = GET_MODE_SIZE (mode);
7575 size = int_size_in_bytes (type);
7578 return (size + 3) >> 2;
7580 return (size + 7) >> 3;
7583 /* Use this to flush pending int fields. */
7586 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7587 HOST_WIDE_INT bitpos, int final)
7589 unsigned int startbit, endbit;
7590 int intregs, intoffset;
7591 enum machine_mode mode;
7593 /* Handle the situations where a float is taking up the first half
7594 of the GPR, and the other half is empty (typically due to
7595 alignment restrictions). We can detect this by a 8-byte-aligned
7596 int field, or by seeing that this is the final flush for this
7597 argument. Count the word and continue on. */
7598 if (cum->floats_in_gpr == 1
7599 && (cum->intoffset % 64 == 0
7600 || (cum->intoffset == -1 && final)))
7603 cum->floats_in_gpr = 0;
7606 if (cum->intoffset == -1)
7609 intoffset = cum->intoffset;
7610 cum->intoffset = -1;
7611 cum->floats_in_gpr = 0;
7613 if (intoffset % BITS_PER_WORD != 0)
7615 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7617 if (mode == BLKmode)
7619 /* We couldn't find an appropriate mode, which happens,
7620 e.g., in packed structs when there are 3 bytes to load.
7621 Back intoffset back to the beginning of the word in this
7623 intoffset = intoffset & -BITS_PER_WORD;
7627 startbit = intoffset & -BITS_PER_WORD;
7628 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7629 intregs = (endbit - startbit) / BITS_PER_WORD;
7630 cum->words += intregs;
7631 /* words should be unsigned. */
7632 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7634 int pad = (endbit/BITS_PER_WORD) - cum->words;
7639 /* The darwin64 ABI calls for us to recurse down through structs,
7640 looking for elements passed in registers. Unfortunately, we have
7641 to track int register count here also because of misalignments
7642 in powerpc alignment mode. */
7645 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7647 HOST_WIDE_INT startbitpos)
7651 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7652 if (TREE_CODE (f) == FIELD_DECL)
7654 HOST_WIDE_INT bitpos = startbitpos;
7655 tree ftype = TREE_TYPE (f);
7656 enum machine_mode mode;
7657 if (ftype == error_mark_node)
7659 mode = TYPE_MODE (ftype);
7661 if (DECL_SIZE (f) != 0
7662 && host_integerp (bit_position (f), 1))
7663 bitpos += int_bit_position (f);
7665 /* ??? FIXME: else assume zero offset. */
7667 if (TREE_CODE (ftype) == RECORD_TYPE)
7668 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7669 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7671 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7672 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7673 cum->fregno += n_fpregs;
7674 /* Single-precision floats present a special problem for
7675 us, because they are smaller than an 8-byte GPR, and so
7676 the structure-packing rules combined with the standard
7677 varargs behavior mean that we want to pack float/float
7678 and float/int combinations into a single register's
7679 space. This is complicated by the arg advance flushing,
7680 which works on arbitrarily large groups of int-type
7684 if (cum->floats_in_gpr == 1)
7686 /* Two floats in a word; count the word and reset
7689 cum->floats_in_gpr = 0;
7691 else if (bitpos % 64 == 0)
7693 /* A float at the beginning of an 8-byte word;
7694 count it and put off adjusting cum->words until
7695 we see if a arg advance flush is going to do it
7697 cum->floats_in_gpr++;
7701 /* The float is at the end of a word, preceded
7702 by integer fields, so the arg advance flush
7703 just above has already set cum->words and
7704 everything is taken care of. */
7708 cum->words += n_fpregs;
7710 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7712 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7716 else if (cum->intoffset == -1)
7717 cum->intoffset = bitpos;
7721 /* Check for an item that needs to be considered specially under the darwin 64
7722 bit ABI. These are record types where the mode is BLK or the structure is
7725 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7727 return rs6000_darwin64_abi
7728 && ((mode == BLKmode
7729 && TREE_CODE (type) == RECORD_TYPE
7730 && int_size_in_bytes (type) > 0)
7731 || (type && TREE_CODE (type) == RECORD_TYPE
7732 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7735 /* Update the data in CUM to advance over an argument
7736 of mode MODE and data type TYPE.
7737 (TYPE is null for libcalls where that information may not be available.)
7739 Note that for args passed by reference, function_arg will be called
7740 with MODE and TYPE set to that of the pointer to the arg, not the arg
7744 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7745 const_tree type, bool named, int depth)
7747 /* Only tick off an argument if we're not recursing. */
7749 cum->nargs_prototype--;
7751 #ifdef HAVE_AS_GNU_ATTRIBUTE
7752 if (DEFAULT_ABI == ABI_V4
7755 if (SCALAR_FLOAT_MODE_P (mode))
7756 rs6000_passes_float = true;
7757 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7758 rs6000_passes_vector = true;
7759 else if (SPE_VECTOR_MODE (mode)
7761 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7762 rs6000_passes_vector = true;
7766 if (TARGET_ALTIVEC_ABI
7767 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7768 || (type && TREE_CODE (type) == VECTOR_TYPE
7769 && int_size_in_bytes (type) == 16)))
7773 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7776 if (!TARGET_ALTIVEC)
7777 error ("cannot pass argument in vector register because"
7778 " altivec instructions are disabled, use -maltivec"
7781 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7782 even if it is going to be passed in a vector register.
7783 Darwin does the same for variable-argument functions. */
7784 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7785 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7795 /* Vector parameters must be 16-byte aligned. This places
7796 them at 2 mod 4 in terms of words in 32-bit mode, since
7797 the parameter save area starts at offset 24 from the
7798 stack. In 64-bit mode, they just have to start on an
7799 even word, since the parameter save area is 16-byte
7800 aligned. Space for GPRs is reserved even if the argument
7801 will be passed in memory. */
7803 align = (2 - cum->words) & 3;
7805 align = cum->words & 1;
7806 cum->words += align + rs6000_arg_size (mode, type);
7808 if (TARGET_DEBUG_ARG)
7810 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7812 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7813 cum->nargs_prototype, cum->prototype,
7814 GET_MODE_NAME (mode));
7818 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7820 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7823 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7825 int size = int_size_in_bytes (type);
7826 /* Variable sized types have size == -1 and are
7827 treated as if consisting entirely of ints.
7828 Pad to 16 byte boundary if needed. */
7829 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7830 && (cum->words % 2) != 0)
7832 /* For varargs, we can just go up by the size of the struct. */
7834 cum->words += (size + 7) / 8;
7837 /* It is tempting to say int register count just goes up by
7838 sizeof(type)/8, but this is wrong in a case such as
7839 { int; double; int; } [powerpc alignment]. We have to
7840 grovel through the fields for these too. */
7842 cum->floats_in_gpr = 0;
7843 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7844 rs6000_darwin64_record_arg_advance_flush (cum,
7845 size * BITS_PER_UNIT, 1);
7847 if (TARGET_DEBUG_ARG)
7849 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7850 cum->words, TYPE_ALIGN (type), size);
7852 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7853 cum->nargs_prototype, cum->prototype,
7854 GET_MODE_NAME (mode));
7857 else if (DEFAULT_ABI == ABI_V4)
7859 if (TARGET_HARD_FLOAT && TARGET_FPRS
7860 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
7861 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
7862 || (mode == TFmode && !TARGET_IEEEQUAD)
7863 || mode == SDmode || mode == DDmode || mode == TDmode))
7865 /* _Decimal128 must use an even/odd register pair. This assumes
7866 that the register number is odd when fregno is odd. */
7867 if (mode == TDmode && (cum->fregno % 2) == 1)
7870 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
7871 <= FP_ARG_V4_MAX_REG)
7872 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7875 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7876 if (mode == DFmode || mode == TFmode
7877 || mode == DDmode || mode == TDmode)
7878 cum->words += cum->words & 1;
7879 cum->words += rs6000_arg_size (mode, type);
7884 int n_words = rs6000_arg_size (mode, type);
7885 int gregno = cum->sysv_gregno;
7887 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
7888 (r7,r8) or (r9,r10). As does any other 2 word item such
7889 as complex int due to a historical mistake. */
7891 gregno += (1 - gregno) & 1;
7893 /* Multi-reg args are not split between registers and stack. */
7894 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7896 /* Long long and SPE vectors are aligned on the stack.
7897 So are other 2 word items such as complex int due to
7898 a historical mistake. */
7900 cum->words += cum->words & 1;
7901 cum->words += n_words;
7904 /* Note: continuing to accumulate gregno past when we've started
7905 spilling to the stack indicates the fact that we've started
7906 spilling to the stack to expand_builtin_saveregs. */
7907 cum->sysv_gregno = gregno + n_words;
7910 if (TARGET_DEBUG_ARG)
7912 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7913 cum->words, cum->fregno);
7914 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7915 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7916 fprintf (stderr, "mode = %4s, named = %d\n",
7917 GET_MODE_NAME (mode), named);
7922 int n_words = rs6000_arg_size (mode, type);
7923 int start_words = cum->words;
7924 int align_words = rs6000_parm_start (mode, type, start_words);
7926 cum->words = align_words + n_words;
7928 if (SCALAR_FLOAT_MODE_P (mode)
7929 && TARGET_HARD_FLOAT && TARGET_FPRS)
7931 /* _Decimal128 must be passed in an even/odd float register pair.
7932 This assumes that the register number is odd when fregno is
7934 if (mode == TDmode && (cum->fregno % 2) == 1)
7936 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7939 if (TARGET_DEBUG_ARG)
7941 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7942 cum->words, cum->fregno);
7943 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
7944 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
7945 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
7946 named, align_words - start_words, depth);
7952 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
7953 const_tree type, bool named)
7955 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
7960 spe_build_register_parallel (enum machine_mode mode, int gregno)
7967 r1 = gen_rtx_REG (DImode, gregno);
7968 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7969 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
7973 r1 = gen_rtx_REG (DImode, gregno);
7974 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7975 r3 = gen_rtx_REG (DImode, gregno + 2);
7976 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
7977 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
7980 r1 = gen_rtx_REG (DImode, gregno);
7981 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7982 r3 = gen_rtx_REG (DImode, gregno + 2);
7983 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
7984 r5 = gen_rtx_REG (DImode, gregno + 4);
7985 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
7986 r7 = gen_rtx_REG (DImode, gregno + 6);
7987 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
7988 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
7995 /* Determine where to put a SIMD argument on the SPE. */
7997 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8000 int gregno = cum->sysv_gregno;
8002 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8003 are passed and returned in a pair of GPRs for ABI compatibility. */
8004 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8005 || mode == DCmode || mode == TCmode))
8007 int n_words = rs6000_arg_size (mode, type);
8009 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8011 gregno += (1 - gregno) & 1;
8013 /* Multi-reg args are not split between registers and stack. */
8014 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8017 return spe_build_register_parallel (mode, gregno);
8021 int n_words = rs6000_arg_size (mode, type);
8023 /* SPE vectors are put in odd registers. */
8024 if (n_words == 2 && (gregno & 1) == 0)
8027 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8030 enum machine_mode m = SImode;
8032 r1 = gen_rtx_REG (m, gregno);
8033 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8034 r2 = gen_rtx_REG (m, gregno + 1);
8035 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8036 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8043 if (gregno <= GP_ARG_MAX_REG)
8044 return gen_rtx_REG (mode, gregno);
8050 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8051 structure between cum->intoffset and bitpos to integer registers. */
8054 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8055 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8057 enum machine_mode mode;
8059 unsigned int startbit, endbit;
8060 int this_regno, intregs, intoffset;
8063 if (cum->intoffset == -1)
8066 intoffset = cum->intoffset;
8067 cum->intoffset = -1;
8069 /* If this is the trailing part of a word, try to only load that
8070 much into the register. Otherwise load the whole register. Note
8071 that in the latter case we may pick up unwanted bits. It's not a
8072 problem at the moment but may wish to revisit. */
8074 if (intoffset % BITS_PER_WORD != 0)
8076 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8078 if (mode == BLKmode)
8080 /* We couldn't find an appropriate mode, which happens,
8081 e.g., in packed structs when there are 3 bytes to load.
8082 Back intoffset back to the beginning of the word in this
8084 intoffset = intoffset & -BITS_PER_WORD;
8091 startbit = intoffset & -BITS_PER_WORD;
8092 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8093 intregs = (endbit - startbit) / BITS_PER_WORD;
8094 this_regno = cum->words + intoffset / BITS_PER_WORD;
8096 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8099 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8103 intoffset /= BITS_PER_UNIT;
8106 regno = GP_ARG_MIN_REG + this_regno;
8107 reg = gen_rtx_REG (mode, regno);
8109 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8112 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8116 while (intregs > 0);
8119 /* Recursive workhorse for the following. */
8122 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8123 HOST_WIDE_INT startbitpos, rtx rvec[],
8128 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8129 if (TREE_CODE (f) == FIELD_DECL)
8131 HOST_WIDE_INT bitpos = startbitpos;
8132 tree ftype = TREE_TYPE (f);
8133 enum machine_mode mode;
8134 if (ftype == error_mark_node)
8136 mode = TYPE_MODE (ftype);
8138 if (DECL_SIZE (f) != 0
8139 && host_integerp (bit_position (f), 1))
8140 bitpos += int_bit_position (f);
8142 /* ??? FIXME: else assume zero offset. */
8144 if (TREE_CODE (ftype) == RECORD_TYPE)
8145 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8146 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8148 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8152 case SCmode: mode = SFmode; break;
8153 case DCmode: mode = DFmode; break;
8154 case TCmode: mode = TFmode; break;
8158 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8159 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8161 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8162 && (mode == TFmode || mode == TDmode));
8163 /* Long double or _Decimal128 split over regs and memory. */
8164 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8168 = gen_rtx_EXPR_LIST (VOIDmode,
8169 gen_rtx_REG (mode, cum->fregno++),
8170 GEN_INT (bitpos / BITS_PER_UNIT));
8171 if (mode == TFmode || mode == TDmode)
8174 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8176 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8178 = gen_rtx_EXPR_LIST (VOIDmode,
8179 gen_rtx_REG (mode, cum->vregno++),
8180 GEN_INT (bitpos / BITS_PER_UNIT));
8182 else if (cum->intoffset == -1)
8183 cum->intoffset = bitpos;
8187 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8188 the register(s) to be used for each field and subfield of a struct
8189 being passed by value, along with the offset of where the
8190 register's value may be found in the block. FP fields go in FP
8191 register, vector fields go in vector registers, and everything
8192 else goes in int registers, packed as in memory.
8194 This code is also used for function return values. RETVAL indicates
8195 whether this is the case.
8197 Much of this is taken from the SPARC V9 port, which has a similar
8198 calling convention. */
8201 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8202 bool named, bool retval)
8204 rtx rvec[FIRST_PSEUDO_REGISTER];
8205 int k = 1, kbase = 1;
8206 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8207 /* This is a copy; modifications are not visible to our caller. */
8208 CUMULATIVE_ARGS copy_cum = *orig_cum;
8209 CUMULATIVE_ARGS *cum = ©_cum;
8211 /* Pad to 16 byte boundary if needed. */
8212 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8213 && (cum->words % 2) != 0)
8220 /* Put entries into rvec[] for individual FP and vector fields, and
8221 for the chunks of memory that go in int regs. Note we start at
8222 element 1; 0 is reserved for an indication of using memory, and
8223 may or may not be filled in below. */
8224 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8225 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8227 /* If any part of the struct went on the stack put all of it there.
8228 This hack is because the generic code for
8229 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8230 parts of the struct are not at the beginning. */
8234 return NULL_RTX; /* doesn't go in registers at all */
8236 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8238 if (k > 1 || cum->use_stack)
8239 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8244 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8247 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8252 rtx rvec[GP_ARG_NUM_REG + 1];
8254 if (align_words >= GP_ARG_NUM_REG)
8257 n_units = rs6000_arg_size (mode, type);
8259 /* Optimize the simple case where the arg fits in one gpr, except in
8260 the case of BLKmode due to assign_parms assuming that registers are
8261 BITS_PER_WORD wide. */
8263 || (n_units == 1 && mode != BLKmode))
8264 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8267 if (align_words + n_units > GP_ARG_NUM_REG)
8268 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8269 using a magic NULL_RTX component.
8270 This is not strictly correct. Only some of the arg belongs in
8271 memory, not all of it. However, the normal scheme using
8272 function_arg_partial_nregs can result in unusual subregs, eg.
8273 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8274 store the whole arg to memory is often more efficient than code
8275 to store pieces, and we know that space is available in the right
8276 place for the whole arg. */
8277 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8282 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8283 rtx off = GEN_INT (i++ * 4);
8284 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8286 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8288 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8291 /* Determine where to put an argument to a function.
8292 Value is zero to push the argument on the stack,
8293 or a hard register in which to store the argument.
8295 MODE is the argument's machine mode.
8296 TYPE is the data type of the argument (as a tree).
8297 This is null for libcalls where that information may
8299 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8300 the preceding args and about the function being called. It is
8301 not modified in this routine.
8302 NAMED is nonzero if this argument is a named parameter
8303 (otherwise it is an extra parameter matching an ellipsis).
8305 On RS/6000 the first eight words of non-FP are normally in registers
8306 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8307 Under V.4, the first 8 FP args are in registers.
8309 If this is floating-point and no prototype is specified, we use
8310 both an FP and integer register (or possibly FP reg and stack). Library
8311 functions (when CALL_LIBCALL is set) always have the proper types for args,
8312 so we can pass the FP value just in one register. emit_library_function
8313 doesn't support PARALLEL anyway.
8315 Note that for args passed by reference, function_arg will be called
8316 with MODE and TYPE set to that of the pointer to the arg, not the arg
8320 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8321 const_tree type, bool named)
8323 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8324 enum rs6000_abi abi = DEFAULT_ABI;
8326 /* Return a marker to indicate whether CR1 needs to set or clear the
8327 bit that V.4 uses to say fp args were passed in registers.
8328 Assume that we don't need the marker for software floating point,
8329 or compiler generated library calls. */
8330 if (mode == VOIDmode)
8333 && (cum->call_cookie & CALL_LIBCALL) == 0
8335 || (cum->nargs_prototype < 0
8336 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8338 /* For the SPE, we need to crxor CR6 always. */
8340 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8341 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8342 return GEN_INT (cum->call_cookie
8343 | ((cum->fregno == FP_ARG_MIN_REG)
8344 ? CALL_V4_SET_FP_ARGS
8345 : CALL_V4_CLEAR_FP_ARGS));
8348 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8351 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8353 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8354 if (rslt != NULL_RTX)
8356 /* Else fall through to usual handling. */
8359 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8360 if (TARGET_64BIT && ! cum->prototype)
8362 /* Vector parameters get passed in vector register
8363 and also in GPRs or memory, in absence of prototype. */
8366 align_words = (cum->words + 1) & ~1;
8368 if (align_words >= GP_ARG_NUM_REG)
8374 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8376 return gen_rtx_PARALLEL (mode,
8378 gen_rtx_EXPR_LIST (VOIDmode,
8380 gen_rtx_EXPR_LIST (VOIDmode,
8381 gen_rtx_REG (mode, cum->vregno),
8385 return gen_rtx_REG (mode, cum->vregno);
8386 else if (TARGET_ALTIVEC_ABI
8387 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8388 || (type && TREE_CODE (type) == VECTOR_TYPE
8389 && int_size_in_bytes (type) == 16)))
8391 if (named || abi == ABI_V4)
8395 /* Vector parameters to varargs functions under AIX or Darwin
8396 get passed in memory and possibly also in GPRs. */
8397 int align, align_words, n_words;
8398 enum machine_mode part_mode;
8400 /* Vector parameters must be 16-byte aligned. This places them at
8401 2 mod 4 in terms of words in 32-bit mode, since the parameter
8402 save area starts at offset 24 from the stack. In 64-bit mode,
8403 they just have to start on an even word, since the parameter
8404 save area is 16-byte aligned. */
8406 align = (2 - cum->words) & 3;
8408 align = cum->words & 1;
8409 align_words = cum->words + align;
8411 /* Out of registers? Memory, then. */
8412 if (align_words >= GP_ARG_NUM_REG)
8415 if (TARGET_32BIT && TARGET_POWERPC64)
8416 return rs6000_mixed_function_arg (mode, type, align_words);
8418 /* The vector value goes in GPRs. Only the part of the
8419 value in GPRs is reported here. */
8421 n_words = rs6000_arg_size (mode, type);
8422 if (align_words + n_words > GP_ARG_NUM_REG)
8423 /* Fortunately, there are only two possibilities, the value
8424 is either wholly in GPRs or half in GPRs and half not. */
8427 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8430 else if (TARGET_SPE_ABI && TARGET_SPE
8431 && (SPE_VECTOR_MODE (mode)
8432 || (TARGET_E500_DOUBLE && (mode == DFmode
8435 || mode == TCmode))))
8436 return rs6000_spe_function_arg (cum, mode, type);
8438 else if (abi == ABI_V4)
8440 if (TARGET_HARD_FLOAT && TARGET_FPRS
8441 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8442 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8443 || (mode == TFmode && !TARGET_IEEEQUAD)
8444 || mode == SDmode || mode == DDmode || mode == TDmode))
8446 /* _Decimal128 must use an even/odd register pair. This assumes
8447 that the register number is odd when fregno is odd. */
8448 if (mode == TDmode && (cum->fregno % 2) == 1)
8451 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8452 <= FP_ARG_V4_MAX_REG)
8453 return gen_rtx_REG (mode, cum->fregno);
8459 int n_words = rs6000_arg_size (mode, type);
8460 int gregno = cum->sysv_gregno;
8462 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8463 (r7,r8) or (r9,r10). As does any other 2 word item such
8464 as complex int due to a historical mistake. */
8466 gregno += (1 - gregno) & 1;
8468 /* Multi-reg args are not split between registers and stack. */
8469 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8472 if (TARGET_32BIT && TARGET_POWERPC64)
8473 return rs6000_mixed_function_arg (mode, type,
8474 gregno - GP_ARG_MIN_REG);
8475 return gen_rtx_REG (mode, gregno);
8480 int align_words = rs6000_parm_start (mode, type, cum->words);
8482 /* _Decimal128 must be passed in an even/odd float register pair.
8483 This assumes that the register number is odd when fregno is odd. */
8484 if (mode == TDmode && (cum->fregno % 2) == 1)
8487 if (USE_FP_FOR_ARG_P (cum, mode, type))
8489 rtx rvec[GP_ARG_NUM_REG + 1];
8493 enum machine_mode fmode = mode;
8494 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8496 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8498 /* Currently, we only ever need one reg here because complex
8499 doubles are split. */
8500 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8501 && (fmode == TFmode || fmode == TDmode));
8503 /* Long double or _Decimal128 split over regs and memory. */
8504 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8507 /* Do we also need to pass this arg in the parameter save
8510 && (cum->nargs_prototype <= 0
8511 || (DEFAULT_ABI == ABI_AIX
8513 && align_words >= GP_ARG_NUM_REG)));
8515 if (!needs_psave && mode == fmode)
8516 return gen_rtx_REG (fmode, cum->fregno);
8521 /* Describe the part that goes in gprs or the stack.
8522 This piece must come first, before the fprs. */
8523 if (align_words < GP_ARG_NUM_REG)
8525 unsigned long n_words = rs6000_arg_size (mode, type);
8527 if (align_words + n_words > GP_ARG_NUM_REG
8528 || (TARGET_32BIT && TARGET_POWERPC64))
8530 /* If this is partially on the stack, then we only
8531 include the portion actually in registers here. */
8532 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8535 if (align_words + n_words > GP_ARG_NUM_REG)
8536 /* Not all of the arg fits in gprs. Say that it
8537 goes in memory too, using a magic NULL_RTX
8538 component. Also see comment in
8539 rs6000_mixed_function_arg for why the normal
8540 function_arg_partial_nregs scheme doesn't work
8542 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8546 r = gen_rtx_REG (rmode,
8547 GP_ARG_MIN_REG + align_words);
8548 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8549 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8551 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8555 /* The whole arg fits in gprs. */
8556 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8557 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8561 /* It's entirely in memory. */
8562 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8565 /* Describe where this piece goes in the fprs. */
8566 r = gen_rtx_REG (fmode, cum->fregno);
8567 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8569 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8571 else if (align_words < GP_ARG_NUM_REG)
8573 if (TARGET_32BIT && TARGET_POWERPC64)
8574 return rs6000_mixed_function_arg (mode, type, align_words);
8576 if (mode == BLKmode)
8579 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8586 /* For an arg passed partly in registers and partly in memory, this is
8587 the number of bytes passed in registers. For args passed entirely in
8588 registers or entirely in memory, zero. When an arg is described by a
8589 PARALLEL, perhaps using more than one register type, this function
8590 returns the number of bytes used by the first element of the PARALLEL. */
8593 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8594 tree type, bool named)
8596 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8600 if (DEFAULT_ABI == ABI_V4)
8603 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8604 && cum->nargs_prototype >= 0)
8607 /* In this complicated case we just disable the partial_nregs code. */
8608 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8611 align_words = rs6000_parm_start (mode, type, cum->words);
8613 if (USE_FP_FOR_ARG_P (cum, mode, type))
8615 /* If we are passing this arg in the fixed parameter save area
8616 (gprs or memory) as well as fprs, then this function should
8617 return the number of partial bytes passed in the parameter
8618 save area rather than partial bytes passed in fprs. */
8620 && (cum->nargs_prototype <= 0
8621 || (DEFAULT_ABI == ABI_AIX
8623 && align_words >= GP_ARG_NUM_REG)))
8625 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8626 > FP_ARG_MAX_REG + 1)
8627 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8628 else if (cum->nargs_prototype >= 0)
8632 if (align_words < GP_ARG_NUM_REG
8633 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8634 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8636 if (ret != 0 && TARGET_DEBUG_ARG)
8637 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8642 /* A C expression that indicates when an argument must be passed by
8643 reference. If nonzero for an argument, a copy of that argument is
8644 made in memory and a pointer to the argument is passed instead of
8645 the argument itself. The pointer is passed in whatever way is
8646 appropriate for passing a pointer to that type.
8648 Under V.4, aggregates and long double are passed by reference.
8650 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8651 reference unless the AltiVec vector extension ABI is in force.
8653 As an extension to all ABIs, variable sized types are passed by
8657 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8658 enum machine_mode mode, const_tree type,
8659 bool named ATTRIBUTE_UNUSED)
8661 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8663 if (TARGET_DEBUG_ARG)
8664 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8671 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8673 if (TARGET_DEBUG_ARG)
8674 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8678 if (int_size_in_bytes (type) < 0)
8680 if (TARGET_DEBUG_ARG)
8681 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8685 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8686 modes only exist for GCC vector types if -maltivec. */
8687 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8689 if (TARGET_DEBUG_ARG)
8690 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8694 /* Pass synthetic vectors in memory. */
8695 if (TREE_CODE (type) == VECTOR_TYPE
8696 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8698 static bool warned_for_pass_big_vectors = false;
8699 if (TARGET_DEBUG_ARG)
8700 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8701 if (!warned_for_pass_big_vectors)
8703 warning (0, "GCC vector passed by reference: "
8704 "non-standard ABI extension with no compatibility guarantee");
8705 warned_for_pass_big_vectors = true;
8714 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8717 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8722 for (i = 0; i < nregs; i++)
8724 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8725 if (reload_completed)
8727 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8730 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8731 i * GET_MODE_SIZE (reg_mode));
8734 tem = replace_equiv_address (tem, XEXP (tem, 0));
8738 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8742 /* Perform any needed actions needed for a function that is receiving a
8743 variable number of arguments.
8747 MODE and TYPE are the mode and type of the current parameter.
8749 PRETEND_SIZE is a variable that should be set to the amount of stack
8750 that must be pushed by the prolog to pretend that our caller pushed
8753 Normally, this macro will push all remaining incoming registers on the
8754 stack and set PRETEND_SIZE to the length of the registers pushed. */
8757 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8758 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8761 CUMULATIVE_ARGS next_cum;
8762 int reg_size = TARGET_32BIT ? 4 : 8;
8763 rtx save_area = NULL_RTX, mem;
8764 int first_reg_offset;
8767 /* Skip the last named argument. */
8768 next_cum = *get_cumulative_args (cum);
8769 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8771 if (DEFAULT_ABI == ABI_V4)
8773 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8777 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8778 HOST_WIDE_INT offset = 0;
8780 /* Try to optimize the size of the varargs save area.
8781 The ABI requires that ap.reg_save_area is doubleword
8782 aligned, but we don't need to allocate space for all
8783 the bytes, only those to which we actually will save
8785 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8786 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8787 if (TARGET_HARD_FLOAT && TARGET_FPRS
8788 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8789 && cfun->va_list_fpr_size)
8792 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8793 * UNITS_PER_FP_WORD;
8794 if (cfun->va_list_fpr_size
8795 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8796 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8798 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8799 * UNITS_PER_FP_WORD;
8803 offset = -((first_reg_offset * reg_size) & ~7);
8804 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8806 gpr_reg_num = cfun->va_list_gpr_size;
8807 if (reg_size == 4 && (first_reg_offset & 1))
8810 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8813 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8815 - (int) (GP_ARG_NUM_REG * reg_size);
8817 if (gpr_size + fpr_size)
8820 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8821 gcc_assert (GET_CODE (reg_save_area) == MEM);
8822 reg_save_area = XEXP (reg_save_area, 0);
8823 if (GET_CODE (reg_save_area) == PLUS)
8825 gcc_assert (XEXP (reg_save_area, 0)
8826 == virtual_stack_vars_rtx);
8827 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
8828 offset += INTVAL (XEXP (reg_save_area, 1));
8831 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8834 cfun->machine->varargs_save_offset = offset;
8835 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
8840 first_reg_offset = next_cum.words;
8841 save_area = virtual_incoming_args_rtx;
8843 if (targetm.calls.must_pass_in_stack (mode, type))
8844 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
8847 set = get_varargs_alias_set ();
8848 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8849 && cfun->va_list_gpr_size)
8851 int nregs = GP_ARG_NUM_REG - first_reg_offset;
8853 if (va_list_gpr_counter_field)
8855 /* V4 va_list_gpr_size counts number of registers needed. */
8856 if (nregs > cfun->va_list_gpr_size)
8857 nregs = cfun->va_list_gpr_size;
8861 /* char * va_list instead counts number of bytes needed. */
8862 if (nregs > cfun->va_list_gpr_size / reg_size)
8863 nregs = cfun->va_list_gpr_size / reg_size;
8866 mem = gen_rtx_MEM (BLKmode,
8867 plus_constant (Pmode, save_area,
8868 first_reg_offset * reg_size));
8869 MEM_NOTRAP_P (mem) = 1;
8870 set_mem_alias_set (mem, set);
8871 set_mem_align (mem, BITS_PER_WORD);
8873 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8877 /* Save FP registers if needed. */
8878 if (DEFAULT_ABI == ABI_V4
8879 && TARGET_HARD_FLOAT && TARGET_FPRS
8881 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8882 && cfun->va_list_fpr_size)
8884 int fregno = next_cum.fregno, nregs;
8885 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8886 rtx lab = gen_label_rtx ();
8887 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8888 * UNITS_PER_FP_WORD);
8891 (gen_rtx_SET (VOIDmode,
8893 gen_rtx_IF_THEN_ELSE (VOIDmode,
8894 gen_rtx_NE (VOIDmode, cr1,
8896 gen_rtx_LABEL_REF (VOIDmode, lab),
8900 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8901 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8903 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8905 plus_constant (Pmode, save_area, off));
8906 MEM_NOTRAP_P (mem) = 1;
8907 set_mem_alias_set (mem, set);
8908 set_mem_align (mem, GET_MODE_ALIGNMENT (
8909 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8910 ? DFmode : SFmode));
8911 emit_move_insn (mem, gen_rtx_REG (
8912 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8913 ? DFmode : SFmode, fregno));
8920 /* Create the va_list data type. */
8923 rs6000_build_builtin_va_list (void)
8925 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8927 /* For AIX, prefer 'char *' because that's what the system
8928 header files like. */
8929 if (DEFAULT_ABI != ABI_V4)
8930 return build_pointer_type (char_type_node);
8932 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
8933 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
8934 get_identifier ("__va_list_tag"), record);
8936 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
8937 unsigned_char_type_node);
8938 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
8939 unsigned_char_type_node);
8940 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
8942 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8943 get_identifier ("reserved"), short_unsigned_type_node);
8944 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8945 get_identifier ("overflow_arg_area"),
8947 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8948 get_identifier ("reg_save_area"),
8951 va_list_gpr_counter_field = f_gpr;
8952 va_list_fpr_counter_field = f_fpr;
8954 DECL_FIELD_CONTEXT (f_gpr) = record;
8955 DECL_FIELD_CONTEXT (f_fpr) = record;
8956 DECL_FIELD_CONTEXT (f_res) = record;
8957 DECL_FIELD_CONTEXT (f_ovf) = record;
8958 DECL_FIELD_CONTEXT (f_sav) = record;
8960 TYPE_STUB_DECL (record) = type_decl;
8961 TYPE_NAME (record) = type_decl;
8962 TYPE_FIELDS (record) = f_gpr;
8963 DECL_CHAIN (f_gpr) = f_fpr;
8964 DECL_CHAIN (f_fpr) = f_res;
8965 DECL_CHAIN (f_res) = f_ovf;
8966 DECL_CHAIN (f_ovf) = f_sav;
8968 layout_type (record);
8970 /* The correct type is an array type of one element. */
8971 return build_array_type (record, build_index_type (size_zero_node));
8974 /* Implement va_start. */
8977 rs6000_va_start (tree valist, rtx nextarg)
8979 HOST_WIDE_INT words, n_gpr, n_fpr;
8980 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8981 tree gpr, fpr, ovf, sav, t;
8983 /* Only SVR4 needs something special. */
8984 if (DEFAULT_ABI != ABI_V4)
8986 std_expand_builtin_va_start (valist, nextarg);
8990 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8991 f_fpr = DECL_CHAIN (f_gpr);
8992 f_res = DECL_CHAIN (f_fpr);
8993 f_ovf = DECL_CHAIN (f_res);
8994 f_sav = DECL_CHAIN (f_ovf);
8996 valist = build_simple_mem_ref (valist);
8997 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8998 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9000 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9002 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9005 /* Count number of gp and fp argument registers used. */
9006 words = crtl->args.info.words;
9007 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9009 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9012 if (TARGET_DEBUG_ARG)
9013 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
9014 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
9015 words, n_gpr, n_fpr);
9017 if (cfun->va_list_gpr_size)
9019 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9020 build_int_cst (NULL_TREE, n_gpr));
9021 TREE_SIDE_EFFECTS (t) = 1;
9022 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9025 if (cfun->va_list_fpr_size)
9027 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9028 build_int_cst (NULL_TREE, n_fpr));
9029 TREE_SIDE_EFFECTS (t) = 1;
9030 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9032 #ifdef HAVE_AS_GNU_ATTRIBUTE
9033 if (call_ABI_of_interest (cfun->decl))
9034 rs6000_passes_float = true;
9038 /* Find the overflow area. */
9039 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9041 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9042 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9043 TREE_SIDE_EFFECTS (t) = 1;
9044 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9046 /* If there were no va_arg invocations, don't set up the register
9048 if (!cfun->va_list_gpr_size
9049 && !cfun->va_list_fpr_size
9050 && n_gpr < GP_ARG_NUM_REG
9051 && n_fpr < FP_ARG_V4_MAX_REG)
9054 /* Find the register save area. */
9055 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9056 if (cfun->machine->varargs_save_offset)
9057 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9058 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9059 TREE_SIDE_EFFECTS (t) = 1;
9060 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9063 /* Implement va_arg. */
9066 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9069 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9070 tree gpr, fpr, ovf, sav, reg, t, u;
9071 int size, rsize, n_reg, sav_ofs, sav_scale;
9072 tree lab_false, lab_over, addr;
9074 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9078 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9080 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9081 return build_va_arg_indirect_ref (t);
9084 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9085 earlier version of gcc, with the property that it always applied alignment
9086 adjustments to the va-args (even for zero-sized types). The cheapest way
9087 to deal with this is to replicate the effect of the part of
9088 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9090 We don't need to check for pass-by-reference because of the test above.
9091 We can return a simplifed answer, since we know there's no offset to add. */
9094 && rs6000_darwin64_abi
9095 && integer_zerop (TYPE_SIZE (type)))
9097 unsigned HOST_WIDE_INT align, boundary;
9098 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9099 align = PARM_BOUNDARY / BITS_PER_UNIT;
9100 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9101 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9102 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9103 boundary /= BITS_PER_UNIT;
9104 if (boundary > align)
9107 /* This updates arg ptr by the amount that would be necessary
9108 to align the zero-sized (but not zero-alignment) item. */
9109 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9110 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9111 gimplify_and_add (t, pre_p);
9113 t = fold_convert (sizetype, valist_tmp);
9114 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9115 fold_convert (TREE_TYPE (valist),
9116 fold_build2 (BIT_AND_EXPR, sizetype, t,
9117 size_int (-boundary))));
9118 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9119 gimplify_and_add (t, pre_p);
9121 /* Since it is zero-sized there's no increment for the item itself. */
9122 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9123 return build_va_arg_indirect_ref (valist_tmp);
9126 if (DEFAULT_ABI != ABI_V4)
9128 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9130 tree elem_type = TREE_TYPE (type);
9131 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9132 int elem_size = GET_MODE_SIZE (elem_mode);
9134 if (elem_size < UNITS_PER_WORD)
9136 tree real_part, imag_part;
9137 gimple_seq post = NULL;
9139 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9141 /* Copy the value into a temporary, lest the formal temporary
9142 be reused out from under us. */
9143 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9144 gimple_seq_add_seq (pre_p, post);
9146 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9149 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9153 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9156 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9157 f_fpr = DECL_CHAIN (f_gpr);
9158 f_res = DECL_CHAIN (f_fpr);
9159 f_ovf = DECL_CHAIN (f_res);
9160 f_sav = DECL_CHAIN (f_ovf);
9162 valist = build_va_arg_indirect_ref (valist);
9163 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9164 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9166 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9168 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9171 size = int_size_in_bytes (type);
9172 rsize = (size + 3) / 4;
9175 if (TARGET_HARD_FLOAT && TARGET_FPRS
9176 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9177 || (TARGET_DOUBLE_FLOAT
9178 && (TYPE_MODE (type) == DFmode
9179 || TYPE_MODE (type) == TFmode
9180 || TYPE_MODE (type) == SDmode
9181 || TYPE_MODE (type) == DDmode
9182 || TYPE_MODE (type) == TDmode))))
9184 /* FP args go in FP registers, if present. */
9186 n_reg = (size + 7) / 8;
9187 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9188 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9189 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9194 /* Otherwise into GP registers. */
9203 /* Pull the value out of the saved registers.... */
9206 addr = create_tmp_var (ptr_type_node, "addr");
9208 /* AltiVec vectors never go in registers when -mabi=altivec. */
9209 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9213 lab_false = create_artificial_label (input_location);
9214 lab_over = create_artificial_label (input_location);
9216 /* Long long and SPE vectors are aligned in the registers.
9217 As are any other 2 gpr item such as complex int due to a
9218 historical mistake. */
9220 if (n_reg == 2 && reg == gpr)
9223 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9224 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9225 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9226 unshare_expr (reg), u);
9228 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9229 reg number is 0 for f1, so we want to make it odd. */
9230 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9232 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9233 build_int_cst (TREE_TYPE (reg), 1));
9234 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9237 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9238 t = build2 (GE_EXPR, boolean_type_node, u, t);
9239 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9240 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9241 gimplify_and_add (t, pre_p);
9245 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9247 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9248 build_int_cst (TREE_TYPE (reg), n_reg));
9249 u = fold_convert (sizetype, u);
9250 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9251 t = fold_build_pointer_plus (t, u);
9253 /* _Decimal32 varargs are located in the second word of the 64-bit
9254 FP register for 32-bit binaries. */
9255 if (!TARGET_POWERPC64
9256 && TARGET_HARD_FLOAT && TARGET_FPRS
9257 && TYPE_MODE (type) == SDmode)
9258 t = fold_build_pointer_plus_hwi (t, size);
9260 gimplify_assign (addr, t, pre_p);
9262 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9264 stmt = gimple_build_label (lab_false);
9265 gimple_seq_add_stmt (pre_p, stmt);
9267 if ((n_reg == 2 && !regalign) || n_reg > 2)
9269 /* Ensure that we don't find any more args in regs.
9270 Alignment has taken care of for special cases. */
9271 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9275 /* ... otherwise out of the overflow area. */
9277 /* Care for on-stack alignment if needed. */
9281 t = fold_build_pointer_plus_hwi (t, align - 1);
9282 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9283 build_int_cst (TREE_TYPE (t), -align));
9285 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9287 gimplify_assign (unshare_expr (addr), t, pre_p);
9289 t = fold_build_pointer_plus_hwi (t, size);
9290 gimplify_assign (unshare_expr (ovf), t, pre_p);
9294 stmt = gimple_build_label (lab_over);
9295 gimple_seq_add_stmt (pre_p, stmt);
9298 if (STRICT_ALIGNMENT
9299 && (TYPE_ALIGN (type)
9300 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9302 /* The value (of type complex double, for example) may not be
9303 aligned in memory in the saved registers, so copy via a
9304 temporary. (This is the same code as used for SPARC.) */
9305 tree tmp = create_tmp_var (type, "va_arg_tmp");
9306 tree dest_addr = build_fold_addr_expr (tmp);
9308 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9309 3, dest_addr, addr, size_int (rsize * 4));
9311 gimplify_and_add (copy, pre_p);
9315 addr = fold_convert (ptrtype, addr);
9316 return build_va_arg_indirect_ref (addr);
9322 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9325 unsigned classify = rs6000_builtin_info[(int)code].attr;
9326 const char *attr_string = "";
9328 gcc_assert (name != NULL);
9329 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9331 if (rs6000_builtin_decls[(int)code])
9332 fatal_error ("internal error: builtin function %s already processed", name);
9334 rs6000_builtin_decls[(int)code] = t =
9335 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9337 /* Set any special attributes. */
9338 if ((classify & RS6000_BTC_CONST) != 0)
9340 /* const function, function only depends on the inputs. */
9341 TREE_READONLY (t) = 1;
9342 TREE_NOTHROW (t) = 1;
9343 attr_string = ", pure";
9345 else if ((classify & RS6000_BTC_PURE) != 0)
9347 /* pure function, function can read global memory, but does not set any
9349 DECL_PURE_P (t) = 1;
9350 TREE_NOTHROW (t) = 1;
9351 attr_string = ", const";
9353 else if ((classify & RS6000_BTC_FP) != 0)
9355 /* Function is a math function. If rounding mode is on, then treat the
9356 function as not reading global memory, but it can have arbitrary side
9357 effects. If it is off, then assume the function is a const function.
9358 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9359 builtin-attribute.def that is used for the math functions. */
9360 TREE_NOTHROW (t) = 1;
9361 if (flag_rounding_math)
9363 DECL_PURE_P (t) = 1;
9364 DECL_IS_NOVOPS (t) = 1;
9365 attr_string = ", fp, pure";
9369 TREE_READONLY (t) = 1;
9370 attr_string = ", fp, const";
9373 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9376 if (TARGET_DEBUG_BUILTIN)
9377 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9378 (int)code, name, attr_string);
9381 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9383 #undef RS6000_BUILTIN_1
9384 #undef RS6000_BUILTIN_2
9385 #undef RS6000_BUILTIN_3
9386 #undef RS6000_BUILTIN_A
9387 #undef RS6000_BUILTIN_D
9388 #undef RS6000_BUILTIN_E
9389 #undef RS6000_BUILTIN_P
9390 #undef RS6000_BUILTIN_Q
9391 #undef RS6000_BUILTIN_S
9392 #undef RS6000_BUILTIN_X
9394 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9395 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9396 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9397 { MASK, ICODE, NAME, ENUM },
9399 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9400 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9401 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9402 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9403 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9404 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9405 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9407 static const struct builtin_description bdesc_3arg[] =
9409 #include "rs6000-builtin.def"
9412 /* DST operations: void foo (void *, const int, const char). */
9414 #undef RS6000_BUILTIN_1
9415 #undef RS6000_BUILTIN_2
9416 #undef RS6000_BUILTIN_3
9417 #undef RS6000_BUILTIN_A
9418 #undef RS6000_BUILTIN_D
9419 #undef RS6000_BUILTIN_E
9420 #undef RS6000_BUILTIN_P
9421 #undef RS6000_BUILTIN_Q
9422 #undef RS6000_BUILTIN_S
9423 #undef RS6000_BUILTIN_X
9425 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9426 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9427 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9428 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9429 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9430 { MASK, ICODE, NAME, ENUM },
9432 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9433 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9434 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9435 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9436 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9438 static const struct builtin_description bdesc_dst[] =
9440 #include "rs6000-builtin.def"
9443 /* Simple binary operations: VECc = foo (VECa, VECb). */
9445 #undef RS6000_BUILTIN_1
9446 #undef RS6000_BUILTIN_2
9447 #undef RS6000_BUILTIN_3
9448 #undef RS6000_BUILTIN_A
9449 #undef RS6000_BUILTIN_D
9450 #undef RS6000_BUILTIN_E
9451 #undef RS6000_BUILTIN_P
9452 #undef RS6000_BUILTIN_Q
9453 #undef RS6000_BUILTIN_S
9454 #undef RS6000_BUILTIN_X
9456 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9457 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9458 { MASK, ICODE, NAME, ENUM },
9460 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9461 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9462 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9463 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9464 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9465 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9466 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9467 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9469 static const struct builtin_description bdesc_2arg[] =
9471 #include "rs6000-builtin.def"
9474 #undef RS6000_BUILTIN_1
9475 #undef RS6000_BUILTIN_2
9476 #undef RS6000_BUILTIN_3
9477 #undef RS6000_BUILTIN_A
9478 #undef RS6000_BUILTIN_D
9479 #undef RS6000_BUILTIN_E
9480 #undef RS6000_BUILTIN_P
9481 #undef RS6000_BUILTIN_Q
9482 #undef RS6000_BUILTIN_S
9483 #undef RS6000_BUILTIN_X
9485 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9486 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9487 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9488 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9489 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9490 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9491 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9492 { MASK, ICODE, NAME, ENUM },
9494 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9495 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9496 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9498 /* AltiVec predicates. */
9500 static const struct builtin_description bdesc_altivec_preds[] =
9502 #include "rs6000-builtin.def"
9505 /* SPE predicates. */
9506 #undef RS6000_BUILTIN_1
9507 #undef RS6000_BUILTIN_2
9508 #undef RS6000_BUILTIN_3
9509 #undef RS6000_BUILTIN_A
9510 #undef RS6000_BUILTIN_D
9511 #undef RS6000_BUILTIN_E
9512 #undef RS6000_BUILTIN_P
9513 #undef RS6000_BUILTIN_Q
9514 #undef RS6000_BUILTIN_S
9515 #undef RS6000_BUILTIN_X
9517 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9518 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9519 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9520 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9521 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9522 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9523 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9524 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9525 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9526 { MASK, ICODE, NAME, ENUM },
9528 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9530 static const struct builtin_description bdesc_spe_predicates[] =
9532 #include "rs6000-builtin.def"
9535 /* SPE evsel predicates. */
9536 #undef RS6000_BUILTIN_1
9537 #undef RS6000_BUILTIN_2
9538 #undef RS6000_BUILTIN_3
9539 #undef RS6000_BUILTIN_A
9540 #undef RS6000_BUILTIN_D
9541 #undef RS6000_BUILTIN_E
9542 #undef RS6000_BUILTIN_P
9543 #undef RS6000_BUILTIN_Q
9544 #undef RS6000_BUILTIN_S
9545 #undef RS6000_BUILTIN_X
9547 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9548 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9549 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9550 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9551 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9552 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9553 { MASK, ICODE, NAME, ENUM },
9555 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9556 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9557 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9558 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9560 static const struct builtin_description bdesc_spe_evsel[] =
9562 #include "rs6000-builtin.def"
9565 /* PAIRED predicates. */
9566 #undef RS6000_BUILTIN_1
9567 #undef RS6000_BUILTIN_2
9568 #undef RS6000_BUILTIN_3
9569 #undef RS6000_BUILTIN_A
9570 #undef RS6000_BUILTIN_D
9571 #undef RS6000_BUILTIN_E
9572 #undef RS6000_BUILTIN_P
9573 #undef RS6000_BUILTIN_Q
9574 #undef RS6000_BUILTIN_S
9575 #undef RS6000_BUILTIN_X
9577 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9578 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9579 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9580 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9581 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9582 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9583 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9584 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9585 { MASK, ICODE, NAME, ENUM },
9587 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9588 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9590 static const struct builtin_description bdesc_paired_preds[] =
9592 #include "rs6000-builtin.def"
9595 /* ABS* operations. */
9597 #undef RS6000_BUILTIN_1
9598 #undef RS6000_BUILTIN_2
9599 #undef RS6000_BUILTIN_3
9600 #undef RS6000_BUILTIN_A
9601 #undef RS6000_BUILTIN_D
9602 #undef RS6000_BUILTIN_E
9603 #undef RS6000_BUILTIN_P
9604 #undef RS6000_BUILTIN_Q
9605 #undef RS6000_BUILTIN_S
9606 #undef RS6000_BUILTIN_X
9608 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9609 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9610 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9611 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9612 { MASK, ICODE, NAME, ENUM },
9614 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9615 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9616 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9617 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9618 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9619 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9621 static const struct builtin_description bdesc_abs[] =
9623 #include "rs6000-builtin.def"
9626 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9629 #undef RS6000_BUILTIN_1
9630 #undef RS6000_BUILTIN_2
9631 #undef RS6000_BUILTIN_3
9632 #undef RS6000_BUILTIN_A
9633 #undef RS6000_BUILTIN_E
9634 #undef RS6000_BUILTIN_D
9635 #undef RS6000_BUILTIN_P
9636 #undef RS6000_BUILTIN_Q
9637 #undef RS6000_BUILTIN_S
9638 #undef RS6000_BUILTIN_X
9640 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9641 { MASK, ICODE, NAME, ENUM },
9643 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9644 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9645 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9646 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9647 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9648 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9649 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9650 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9651 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9653 static const struct builtin_description bdesc_1arg[] =
9655 #include "rs6000-builtin.def"
9658 #undef RS6000_BUILTIN_1
9659 #undef RS6000_BUILTIN_2
9660 #undef RS6000_BUILTIN_3
9661 #undef RS6000_BUILTIN_A
9662 #undef RS6000_BUILTIN_D
9663 #undef RS6000_BUILTIN_E
9664 #undef RS6000_BUILTIN_P
9665 #undef RS6000_BUILTIN_Q
9666 #undef RS6000_BUILTIN_S
9667 #undef RS6000_BUILTIN_X
9669 /* Return true if a builtin function is overloaded. */
9671 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9673 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9678 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9681 tree arg0 = CALL_EXPR_ARG (exp, 0);
9682 rtx op0 = expand_normal (arg0);
9683 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9684 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9686 if (icode == CODE_FOR_nothing)
9687 /* Builtin not supported on this processor. */
9690 /* If we got invalid arguments bail out before generating bad rtl. */
9691 if (arg0 == error_mark_node)
9694 if (icode == CODE_FOR_altivec_vspltisb
9695 || icode == CODE_FOR_altivec_vspltish
9696 || icode == CODE_FOR_altivec_vspltisw
9697 || icode == CODE_FOR_spe_evsplatfi
9698 || icode == CODE_FOR_spe_evsplati)
9700 /* Only allow 5-bit *signed* literals. */
9701 if (GET_CODE (op0) != CONST_INT
9702 || INTVAL (op0) > 15
9703 || INTVAL (op0) < -16)
9705 error ("argument 1 must be a 5-bit signed literal");
9711 || GET_MODE (target) != tmode
9712 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9713 target = gen_reg_rtx (tmode);
9715 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9716 op0 = copy_to_mode_reg (mode0, op0);
9718 pat = GEN_FCN (icode) (target, op0);
9727 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9729 rtx pat, scratch1, scratch2;
9730 tree arg0 = CALL_EXPR_ARG (exp, 0);
9731 rtx op0 = expand_normal (arg0);
9732 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9733 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9735 /* If we have invalid arguments, bail out before generating bad rtl. */
9736 if (arg0 == error_mark_node)
9740 || GET_MODE (target) != tmode
9741 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9742 target = gen_reg_rtx (tmode);
9744 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9745 op0 = copy_to_mode_reg (mode0, op0);
9747 scratch1 = gen_reg_rtx (mode0);
9748 scratch2 = gen_reg_rtx (mode0);
9750 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9759 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9762 tree arg0 = CALL_EXPR_ARG (exp, 0);
9763 tree arg1 = CALL_EXPR_ARG (exp, 1);
9764 rtx op0 = expand_normal (arg0);
9765 rtx op1 = expand_normal (arg1);
9766 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9767 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9768 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9770 if (icode == CODE_FOR_nothing)
9771 /* Builtin not supported on this processor. */
9774 /* If we got invalid arguments bail out before generating bad rtl. */
9775 if (arg0 == error_mark_node || arg1 == error_mark_node)
9778 if (icode == CODE_FOR_altivec_vcfux
9779 || icode == CODE_FOR_altivec_vcfsx
9780 || icode == CODE_FOR_altivec_vctsxs
9781 || icode == CODE_FOR_altivec_vctuxs
9782 || icode == CODE_FOR_altivec_vspltb
9783 || icode == CODE_FOR_altivec_vsplth
9784 || icode == CODE_FOR_altivec_vspltw
9785 || icode == CODE_FOR_spe_evaddiw
9786 || icode == CODE_FOR_spe_evldd
9787 || icode == CODE_FOR_spe_evldh
9788 || icode == CODE_FOR_spe_evldw
9789 || icode == CODE_FOR_spe_evlhhesplat
9790 || icode == CODE_FOR_spe_evlhhossplat
9791 || icode == CODE_FOR_spe_evlhhousplat
9792 || icode == CODE_FOR_spe_evlwhe
9793 || icode == CODE_FOR_spe_evlwhos
9794 || icode == CODE_FOR_spe_evlwhou
9795 || icode == CODE_FOR_spe_evlwhsplat
9796 || icode == CODE_FOR_spe_evlwwsplat
9797 || icode == CODE_FOR_spe_evrlwi
9798 || icode == CODE_FOR_spe_evslwi
9799 || icode == CODE_FOR_spe_evsrwis
9800 || icode == CODE_FOR_spe_evsubifw
9801 || icode == CODE_FOR_spe_evsrwiu)
9803 /* Only allow 5-bit unsigned literals. */
9805 if (TREE_CODE (arg1) != INTEGER_CST
9806 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9808 error ("argument 2 must be a 5-bit unsigned literal");
9814 || GET_MODE (target) != tmode
9815 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9816 target = gen_reg_rtx (tmode);
9818 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9819 op0 = copy_to_mode_reg (mode0, op0);
9820 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9821 op1 = copy_to_mode_reg (mode1, op1);
9823 pat = GEN_FCN (icode) (target, op0, op1);
9832 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9835 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9836 tree arg0 = CALL_EXPR_ARG (exp, 1);
9837 tree arg1 = CALL_EXPR_ARG (exp, 2);
9838 rtx op0 = expand_normal (arg0);
9839 rtx op1 = expand_normal (arg1);
9840 enum machine_mode tmode = SImode;
9841 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9842 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9845 if (TREE_CODE (cr6_form) != INTEGER_CST)
9847 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9851 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9853 gcc_assert (mode0 == mode1);
9855 /* If we have invalid arguments, bail out before generating bad rtl. */
9856 if (arg0 == error_mark_node || arg1 == error_mark_node)
9860 || GET_MODE (target) != tmode
9861 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9862 target = gen_reg_rtx (tmode);
9864 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9865 op0 = copy_to_mode_reg (mode0, op0);
9866 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9867 op1 = copy_to_mode_reg (mode1, op1);
9869 scratch = gen_reg_rtx (mode0);
9871 pat = GEN_FCN (icode) (scratch, op0, op1);
9876 /* The vec_any* and vec_all* predicates use the same opcodes for two
9877 different operations, but the bits in CR6 will be different
9878 depending on what information we want. So we have to play tricks
9879 with CR6 to get the right bits out.
9881 If you think this is disgusting, look at the specs for the
9882 AltiVec predicates. */
9884 switch (cr6_form_int)
9887 emit_insn (gen_cr6_test_for_zero (target));
9890 emit_insn (gen_cr6_test_for_zero_reverse (target));
9893 emit_insn (gen_cr6_test_for_lt (target));
9896 emit_insn (gen_cr6_test_for_lt_reverse (target));
9899 error ("argument 1 of __builtin_altivec_predicate is out of range");
9907 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
9910 tree arg0 = CALL_EXPR_ARG (exp, 0);
9911 tree arg1 = CALL_EXPR_ARG (exp, 1);
9912 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9913 enum machine_mode mode0 = Pmode;
9914 enum machine_mode mode1 = Pmode;
9915 rtx op0 = expand_normal (arg0);
9916 rtx op1 = expand_normal (arg1);
9918 if (icode == CODE_FOR_nothing)
9919 /* Builtin not supported on this processor. */
9922 /* If we got invalid arguments bail out before generating bad rtl. */
9923 if (arg0 == error_mark_node || arg1 == error_mark_node)
9927 || GET_MODE (target) != tmode
9928 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9929 target = gen_reg_rtx (tmode);
9931 op1 = copy_to_mode_reg (mode1, op1);
9933 if (op0 == const0_rtx)
9935 addr = gen_rtx_MEM (tmode, op1);
9939 op0 = copy_to_mode_reg (mode0, op0);
9940 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
9943 pat = GEN_FCN (icode) (target, addr);
9953 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9956 tree arg0 = CALL_EXPR_ARG (exp, 0);
9957 tree arg1 = CALL_EXPR_ARG (exp, 1);
9958 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9959 enum machine_mode mode0 = Pmode;
9960 enum machine_mode mode1 = Pmode;
9961 rtx op0 = expand_normal (arg0);
9962 rtx op1 = expand_normal (arg1);
9964 if (icode == CODE_FOR_nothing)
9965 /* Builtin not supported on this processor. */
9968 /* If we got invalid arguments bail out before generating bad rtl. */
9969 if (arg0 == error_mark_node || arg1 == error_mark_node)
9973 || GET_MODE (target) != tmode
9974 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9975 target = gen_reg_rtx (tmode);
9977 op1 = copy_to_mode_reg (mode1, op1);
9979 if (op0 == const0_rtx)
9981 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9985 op0 = copy_to_mode_reg (mode0, op0);
9986 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
9989 pat = GEN_FCN (icode) (target, addr);
9999 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10001 tree arg0 = CALL_EXPR_ARG (exp, 0);
10002 tree arg1 = CALL_EXPR_ARG (exp, 1);
10003 tree arg2 = CALL_EXPR_ARG (exp, 2);
10004 rtx op0 = expand_normal (arg0);
10005 rtx op1 = expand_normal (arg1);
10006 rtx op2 = expand_normal (arg2);
10008 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10009 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10010 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10012 /* Invalid arguments. Bail before doing anything stoopid! */
10013 if (arg0 == error_mark_node
10014 || arg1 == error_mark_node
10015 || arg2 == error_mark_node)
10018 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10019 op0 = copy_to_mode_reg (mode2, op0);
10020 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10021 op1 = copy_to_mode_reg (mode0, op1);
10022 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10023 op2 = copy_to_mode_reg (mode1, op2);
10025 pat = GEN_FCN (icode) (op1, op2, op0);
10032 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10034 tree arg0 = CALL_EXPR_ARG (exp, 0);
10035 tree arg1 = CALL_EXPR_ARG (exp, 1);
10036 tree arg2 = CALL_EXPR_ARG (exp, 2);
10037 rtx op0 = expand_normal (arg0);
10038 rtx op1 = expand_normal (arg1);
10039 rtx op2 = expand_normal (arg2);
10041 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10042 enum machine_mode mode1 = Pmode;
10043 enum machine_mode mode2 = Pmode;
10045 /* Invalid arguments. Bail before doing anything stoopid! */
10046 if (arg0 == error_mark_node
10047 || arg1 == error_mark_node
10048 || arg2 == error_mark_node)
10051 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10052 op0 = copy_to_mode_reg (tmode, op0);
10054 op2 = copy_to_mode_reg (mode2, op2);
10056 if (op1 == const0_rtx)
10058 addr = gen_rtx_MEM (tmode, op2);
10062 op1 = copy_to_mode_reg (mode1, op1);
10063 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10066 pat = GEN_FCN (icode) (addr, op0);
10073 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10075 tree arg0 = CALL_EXPR_ARG (exp, 0);
10076 tree arg1 = CALL_EXPR_ARG (exp, 1);
10077 tree arg2 = CALL_EXPR_ARG (exp, 2);
10078 rtx op0 = expand_normal (arg0);
10079 rtx op1 = expand_normal (arg1);
10080 rtx op2 = expand_normal (arg2);
10082 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10083 enum machine_mode smode = insn_data[icode].operand[1].mode;
10084 enum machine_mode mode1 = Pmode;
10085 enum machine_mode mode2 = Pmode;
10087 /* Invalid arguments. Bail before doing anything stoopid! */
10088 if (arg0 == error_mark_node
10089 || arg1 == error_mark_node
10090 || arg2 == error_mark_node)
10093 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10094 op0 = copy_to_mode_reg (smode, op0);
10096 op2 = copy_to_mode_reg (mode2, op2);
10098 if (op1 == const0_rtx)
10100 addr = gen_rtx_MEM (tmode, op2);
10104 op1 = copy_to_mode_reg (mode1, op1);
10105 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10108 pat = GEN_FCN (icode) (addr, op0);
10115 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10118 tree arg0 = CALL_EXPR_ARG (exp, 0);
10119 tree arg1 = CALL_EXPR_ARG (exp, 1);
10120 tree arg2 = CALL_EXPR_ARG (exp, 2);
10121 rtx op0 = expand_normal (arg0);
10122 rtx op1 = expand_normal (arg1);
10123 rtx op2 = expand_normal (arg2);
10124 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10125 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10126 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10127 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10129 if (icode == CODE_FOR_nothing)
10130 /* Builtin not supported on this processor. */
10133 /* If we got invalid arguments bail out before generating bad rtl. */
10134 if (arg0 == error_mark_node
10135 || arg1 == error_mark_node
10136 || arg2 == error_mark_node)
10139 /* Check and prepare argument depending on the instruction code.
10141 Note that a switch statement instead of the sequence of tests
10142 would be incorrect as many of the CODE_FOR values could be
10143 CODE_FOR_nothing and that would yield multiple alternatives
10144 with identical values. We'd never reach here at runtime in
10146 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10147 || icode == CODE_FOR_altivec_vsldoi_v4si
10148 || icode == CODE_FOR_altivec_vsldoi_v8hi
10149 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10151 /* Only allow 4-bit unsigned literals. */
10153 if (TREE_CODE (arg2) != INTEGER_CST
10154 || TREE_INT_CST_LOW (arg2) & ~0xf)
10156 error ("argument 3 must be a 4-bit unsigned literal");
10160 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10161 || icode == CODE_FOR_vsx_xxpermdi_v2di
10162 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10163 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10164 || icode == CODE_FOR_vsx_xxsldwi_v4si
10165 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10166 || icode == CODE_FOR_vsx_xxsldwi_v2di
10167 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10169 /* Only allow 2-bit unsigned literals. */
10171 if (TREE_CODE (arg2) != INTEGER_CST
10172 || TREE_INT_CST_LOW (arg2) & ~0x3)
10174 error ("argument 3 must be a 2-bit unsigned literal");
10178 else if (icode == CODE_FOR_vsx_set_v2df
10179 || icode == CODE_FOR_vsx_set_v2di)
10181 /* Only allow 1-bit unsigned literals. */
10183 if (TREE_CODE (arg2) != INTEGER_CST
10184 || TREE_INT_CST_LOW (arg2) & ~0x1)
10186 error ("argument 3 must be a 1-bit unsigned literal");
10192 || GET_MODE (target) != tmode
10193 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10194 target = gen_reg_rtx (tmode);
10196 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10197 op0 = copy_to_mode_reg (mode0, op0);
10198 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10199 op1 = copy_to_mode_reg (mode1, op1);
10200 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10201 op2 = copy_to_mode_reg (mode2, op2);
10203 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10204 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10206 pat = GEN_FCN (icode) (target, op0, op1, op2);
10214 /* Expand the lvx builtins. */
10216 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10218 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10219 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10221 enum machine_mode tmode, mode0;
10223 enum insn_code icode;
10227 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10228 icode = CODE_FOR_vector_altivec_load_v16qi;
10230 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10231 icode = CODE_FOR_vector_altivec_load_v8hi;
10233 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10234 icode = CODE_FOR_vector_altivec_load_v4si;
10236 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10237 icode = CODE_FOR_vector_altivec_load_v4sf;
10239 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10240 icode = CODE_FOR_vector_altivec_load_v2df;
10242 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10243 icode = CODE_FOR_vector_altivec_load_v2di;
10246 *expandedp = false;
10252 arg0 = CALL_EXPR_ARG (exp, 0);
10253 op0 = expand_normal (arg0);
10254 tmode = insn_data[icode].operand[0].mode;
10255 mode0 = insn_data[icode].operand[1].mode;
10258 || GET_MODE (target) != tmode
10259 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10260 target = gen_reg_rtx (tmode);
10262 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10263 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10265 pat = GEN_FCN (icode) (target, op0);
10272 /* Expand the stvx builtins. */
10274 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10277 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10278 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10280 enum machine_mode mode0, mode1;
10282 enum insn_code icode;
10286 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10287 icode = CODE_FOR_vector_altivec_store_v16qi;
10289 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10290 icode = CODE_FOR_vector_altivec_store_v8hi;
10292 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10293 icode = CODE_FOR_vector_altivec_store_v4si;
10295 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10296 icode = CODE_FOR_vector_altivec_store_v4sf;
10298 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10299 icode = CODE_FOR_vector_altivec_store_v2df;
10301 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10302 icode = CODE_FOR_vector_altivec_store_v2di;
10305 *expandedp = false;
10309 arg0 = CALL_EXPR_ARG (exp, 0);
10310 arg1 = CALL_EXPR_ARG (exp, 1);
10311 op0 = expand_normal (arg0);
10312 op1 = expand_normal (arg1);
10313 mode0 = insn_data[icode].operand[0].mode;
10314 mode1 = insn_data[icode].operand[1].mode;
10316 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10317 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10318 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10319 op1 = copy_to_mode_reg (mode1, op1);
10321 pat = GEN_FCN (icode) (op0, op1);
10329 /* Expand the dst builtins. */
10331 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10334 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10335 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10336 tree arg0, arg1, arg2;
10337 enum machine_mode mode0, mode1;
10338 rtx pat, op0, op1, op2;
10339 const struct builtin_description *d;
10342 *expandedp = false;
10344 /* Handle DST variants. */
10346 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10347 if (d->code == fcode)
10349 arg0 = CALL_EXPR_ARG (exp, 0);
10350 arg1 = CALL_EXPR_ARG (exp, 1);
10351 arg2 = CALL_EXPR_ARG (exp, 2);
10352 op0 = expand_normal (arg0);
10353 op1 = expand_normal (arg1);
10354 op2 = expand_normal (arg2);
10355 mode0 = insn_data[d->icode].operand[0].mode;
10356 mode1 = insn_data[d->icode].operand[1].mode;
10358 /* Invalid arguments, bail out before generating bad rtl. */
10359 if (arg0 == error_mark_node
10360 || arg1 == error_mark_node
10361 || arg2 == error_mark_node)
10366 if (TREE_CODE (arg2) != INTEGER_CST
10367 || TREE_INT_CST_LOW (arg2) & ~0x3)
10369 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10373 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10374 op0 = copy_to_mode_reg (Pmode, op0);
10375 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10376 op1 = copy_to_mode_reg (mode1, op1);
10378 pat = GEN_FCN (d->icode) (op0, op1, op2);
10388 /* Expand vec_init builtin. */
10390 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10392 enum machine_mode tmode = TYPE_MODE (type);
10393 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10394 int i, n_elt = GET_MODE_NUNITS (tmode);
10395 rtvec v = rtvec_alloc (n_elt);
10397 gcc_assert (VECTOR_MODE_P (tmode));
10398 gcc_assert (n_elt == call_expr_nargs (exp));
10400 for (i = 0; i < n_elt; ++i)
10402 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10403 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10406 if (!target || !register_operand (target, tmode))
10407 target = gen_reg_rtx (tmode);
10409 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10413 /* Return the integer constant in ARG. Constrain it to be in the range
10414 of the subparts of VEC_TYPE; issue an error if not. */
10417 get_element_number (tree vec_type, tree arg)
10419 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10421 if (!host_integerp (arg, 1)
10422 || (elt = tree_low_cst (arg, 1), elt > max))
10424 error ("selector must be an integer constant in the range 0..%wi", max);
10431 /* Expand vec_set builtin. */
10433 altivec_expand_vec_set_builtin (tree exp)
10435 enum machine_mode tmode, mode1;
10436 tree arg0, arg1, arg2;
10440 arg0 = CALL_EXPR_ARG (exp, 0);
10441 arg1 = CALL_EXPR_ARG (exp, 1);
10442 arg2 = CALL_EXPR_ARG (exp, 2);
10444 tmode = TYPE_MODE (TREE_TYPE (arg0));
10445 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10446 gcc_assert (VECTOR_MODE_P (tmode));
10448 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10449 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10450 elt = get_element_number (TREE_TYPE (arg0), arg2);
10452 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10453 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10455 op0 = force_reg (tmode, op0);
10456 op1 = force_reg (mode1, op1);
10458 rs6000_expand_vector_set (op0, op1, elt);
10463 /* Expand vec_ext builtin. */
10465 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10467 enum machine_mode tmode, mode0;
10472 arg0 = CALL_EXPR_ARG (exp, 0);
10473 arg1 = CALL_EXPR_ARG (exp, 1);
10475 op0 = expand_normal (arg0);
10476 elt = get_element_number (TREE_TYPE (arg0), arg1);
10478 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10479 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10480 gcc_assert (VECTOR_MODE_P (mode0));
10482 op0 = force_reg (mode0, op0);
10484 if (optimize || !target || !register_operand (target, tmode))
10485 target = gen_reg_rtx (tmode);
10487 rs6000_expand_vector_extract (target, op0, elt);
10492 /* Expand the builtin in EXP and store the result in TARGET. Store
10493 true in *EXPANDEDP if we found a builtin to expand. */
10495 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10497 const struct builtin_description *d;
10499 enum insn_code icode;
10500 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10503 enum machine_mode tmode, mode0;
10504 enum rs6000_builtins fcode
10505 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10507 if (rs6000_overloaded_builtin_p (fcode))
10510 error ("unresolved overload for Altivec builtin %qF", fndecl);
10512 /* Given it is invalid, just generate a normal call. */
10513 return expand_call (exp, target, false);
10516 target = altivec_expand_ld_builtin (exp, target, expandedp);
10520 target = altivec_expand_st_builtin (exp, target, expandedp);
10524 target = altivec_expand_dst_builtin (exp, target, expandedp);
10532 case ALTIVEC_BUILTIN_STVX:
10533 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10534 case ALTIVEC_BUILTIN_STVEBX:
10535 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10536 case ALTIVEC_BUILTIN_STVEHX:
10537 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10538 case ALTIVEC_BUILTIN_STVEWX:
10539 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10540 case ALTIVEC_BUILTIN_STVXL:
10541 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10543 case ALTIVEC_BUILTIN_STVLX:
10544 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10545 case ALTIVEC_BUILTIN_STVLXL:
10546 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10547 case ALTIVEC_BUILTIN_STVRX:
10548 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10549 case ALTIVEC_BUILTIN_STVRXL:
10550 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10552 case VSX_BUILTIN_STXVD2X_V2DF:
10553 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10554 case VSX_BUILTIN_STXVD2X_V2DI:
10555 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10556 case VSX_BUILTIN_STXVW4X_V4SF:
10557 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10558 case VSX_BUILTIN_STXVW4X_V4SI:
10559 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10560 case VSX_BUILTIN_STXVW4X_V8HI:
10561 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10562 case VSX_BUILTIN_STXVW4X_V16QI:
10563 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10565 case ALTIVEC_BUILTIN_MFVSCR:
10566 icode = CODE_FOR_altivec_mfvscr;
10567 tmode = insn_data[icode].operand[0].mode;
10570 || GET_MODE (target) != tmode
10571 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10572 target = gen_reg_rtx (tmode);
10574 pat = GEN_FCN (icode) (target);
10580 case ALTIVEC_BUILTIN_MTVSCR:
10581 icode = CODE_FOR_altivec_mtvscr;
10582 arg0 = CALL_EXPR_ARG (exp, 0);
10583 op0 = expand_normal (arg0);
10584 mode0 = insn_data[icode].operand[0].mode;
10586 /* If we got invalid arguments bail out before generating bad rtl. */
10587 if (arg0 == error_mark_node)
10590 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10591 op0 = copy_to_mode_reg (mode0, op0);
10593 pat = GEN_FCN (icode) (op0);
10598 case ALTIVEC_BUILTIN_DSSALL:
10599 emit_insn (gen_altivec_dssall ());
10602 case ALTIVEC_BUILTIN_DSS:
10603 icode = CODE_FOR_altivec_dss;
10604 arg0 = CALL_EXPR_ARG (exp, 0);
10606 op0 = expand_normal (arg0);
10607 mode0 = insn_data[icode].operand[0].mode;
10609 /* If we got invalid arguments bail out before generating bad rtl. */
10610 if (arg0 == error_mark_node)
10613 if (TREE_CODE (arg0) != INTEGER_CST
10614 || TREE_INT_CST_LOW (arg0) & ~0x3)
10616 error ("argument to dss must be a 2-bit unsigned literal");
10620 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10621 op0 = copy_to_mode_reg (mode0, op0);
10623 emit_insn (gen_altivec_dss (op0));
10626 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10627 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10628 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10629 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10630 case VSX_BUILTIN_VEC_INIT_V2DF:
10631 case VSX_BUILTIN_VEC_INIT_V2DI:
10632 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10634 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10635 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10636 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10637 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10638 case VSX_BUILTIN_VEC_SET_V2DF:
10639 case VSX_BUILTIN_VEC_SET_V2DI:
10640 return altivec_expand_vec_set_builtin (exp);
10642 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10643 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10644 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10645 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10646 case VSX_BUILTIN_VEC_EXT_V2DF:
10647 case VSX_BUILTIN_VEC_EXT_V2DI:
10648 return altivec_expand_vec_ext_builtin (exp, target);
10652 /* Fall through. */
10655 /* Expand abs* operations. */
10657 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10658 if (d->code == fcode)
10659 return altivec_expand_abs_builtin (d->icode, exp, target);
10661 /* Expand the AltiVec predicates. */
10662 d = bdesc_altivec_preds;
10663 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10664 if (d->code == fcode)
10665 return altivec_expand_predicate_builtin (d->icode, exp, target);
10667 /* LV* are funky. We initialized them differently. */
10670 case ALTIVEC_BUILTIN_LVSL:
10671 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10672 exp, target, false);
10673 case ALTIVEC_BUILTIN_LVSR:
10674 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10675 exp, target, false);
10676 case ALTIVEC_BUILTIN_LVEBX:
10677 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10678 exp, target, false);
10679 case ALTIVEC_BUILTIN_LVEHX:
10680 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10681 exp, target, false);
10682 case ALTIVEC_BUILTIN_LVEWX:
10683 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10684 exp, target, false);
10685 case ALTIVEC_BUILTIN_LVXL:
10686 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10687 exp, target, false);
10688 case ALTIVEC_BUILTIN_LVX:
10689 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10690 exp, target, false);
10691 case ALTIVEC_BUILTIN_LVLX:
10692 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10693 exp, target, true);
10694 case ALTIVEC_BUILTIN_LVLXL:
10695 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10696 exp, target, true);
10697 case ALTIVEC_BUILTIN_LVRX:
10698 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10699 exp, target, true);
10700 case ALTIVEC_BUILTIN_LVRXL:
10701 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10702 exp, target, true);
10703 case VSX_BUILTIN_LXVD2X_V2DF:
10704 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10705 exp, target, false);
10706 case VSX_BUILTIN_LXVD2X_V2DI:
10707 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10708 exp, target, false);
10709 case VSX_BUILTIN_LXVW4X_V4SF:
10710 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10711 exp, target, false);
10712 case VSX_BUILTIN_LXVW4X_V4SI:
10713 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10714 exp, target, false);
10715 case VSX_BUILTIN_LXVW4X_V8HI:
10716 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10717 exp, target, false);
10718 case VSX_BUILTIN_LXVW4X_V16QI:
10719 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10720 exp, target, false);
10724 /* Fall through. */
10727 *expandedp = false;
10731 /* Expand the builtin in EXP and store the result in TARGET. Store
10732 true in *EXPANDEDP if we found a builtin to expand. */
10734 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10736 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10737 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10738 const struct builtin_description *d;
10745 case PAIRED_BUILTIN_STX:
10746 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10747 case PAIRED_BUILTIN_LX:
10748 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10751 /* Fall through. */
10754 /* Expand the paired predicates. */
10755 d = bdesc_paired_preds;
10756 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10757 if (d->code == fcode)
10758 return paired_expand_predicate_builtin (d->icode, exp, target);
10760 *expandedp = false;
10764 /* Binops that need to be initialized manually, but can be expanded
10765 automagically by rs6000_expand_binop_builtin. */
10766 static const struct builtin_description bdesc_2arg_spe[] =
10768 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10769 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10770 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10771 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10772 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10773 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10774 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10775 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10776 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10777 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10778 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10779 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10780 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10781 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10782 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10783 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10784 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10785 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10786 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10787 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10788 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10789 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10792 /* Expand the builtin in EXP and store the result in TARGET. Store
10793 true in *EXPANDEDP if we found a builtin to expand.
10795 This expands the SPE builtins that are not simple unary and binary
10798 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
10800 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10802 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10803 enum insn_code icode;
10804 enum machine_mode tmode, mode0;
10806 const struct builtin_description *d;
10811 /* Syntax check for a 5-bit unsigned immediate. */
10814 case SPE_BUILTIN_EVSTDD:
10815 case SPE_BUILTIN_EVSTDH:
10816 case SPE_BUILTIN_EVSTDW:
10817 case SPE_BUILTIN_EVSTWHE:
10818 case SPE_BUILTIN_EVSTWHO:
10819 case SPE_BUILTIN_EVSTWWE:
10820 case SPE_BUILTIN_EVSTWWO:
10821 arg1 = CALL_EXPR_ARG (exp, 2);
10822 if (TREE_CODE (arg1) != INTEGER_CST
10823 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10825 error ("argument 2 must be a 5-bit unsigned literal");
10833 /* The evsplat*i instructions are not quite generic. */
10836 case SPE_BUILTIN_EVSPLATFI:
10837 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
10839 case SPE_BUILTIN_EVSPLATI:
10840 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
10846 d = bdesc_2arg_spe;
10847 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
10848 if (d->code == fcode)
10849 return rs6000_expand_binop_builtin (d->icode, exp, target);
10851 d = bdesc_spe_predicates;
10852 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
10853 if (d->code == fcode)
10854 return spe_expand_predicate_builtin (d->icode, exp, target);
10856 d = bdesc_spe_evsel;
10857 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
10858 if (d->code == fcode)
10859 return spe_expand_evsel_builtin (d->icode, exp, target);
10863 case SPE_BUILTIN_EVSTDDX:
10864 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
10865 case SPE_BUILTIN_EVSTDHX:
10866 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
10867 case SPE_BUILTIN_EVSTDWX:
10868 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
10869 case SPE_BUILTIN_EVSTWHEX:
10870 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
10871 case SPE_BUILTIN_EVSTWHOX:
10872 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
10873 case SPE_BUILTIN_EVSTWWEX:
10874 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
10875 case SPE_BUILTIN_EVSTWWOX:
10876 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
10877 case SPE_BUILTIN_EVSTDD:
10878 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
10879 case SPE_BUILTIN_EVSTDH:
10880 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
10881 case SPE_BUILTIN_EVSTDW:
10882 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
10883 case SPE_BUILTIN_EVSTWHE:
10884 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
10885 case SPE_BUILTIN_EVSTWHO:
10886 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
10887 case SPE_BUILTIN_EVSTWWE:
10888 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
10889 case SPE_BUILTIN_EVSTWWO:
10890 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
10891 case SPE_BUILTIN_MFSPEFSCR:
10892 icode = CODE_FOR_spe_mfspefscr;
10893 tmode = insn_data[icode].operand[0].mode;
10896 || GET_MODE (target) != tmode
10897 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10898 target = gen_reg_rtx (tmode);
10900 pat = GEN_FCN (icode) (target);
10905 case SPE_BUILTIN_MTSPEFSCR:
10906 icode = CODE_FOR_spe_mtspefscr;
10907 arg0 = CALL_EXPR_ARG (exp, 0);
10908 op0 = expand_normal (arg0);
10909 mode0 = insn_data[icode].operand[0].mode;
10911 if (arg0 == error_mark_node)
10914 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10915 op0 = copy_to_mode_reg (mode0, op0);
10917 pat = GEN_FCN (icode) (op0);
10925 *expandedp = false;
10930 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10932 rtx pat, scratch, tmp;
10933 tree form = CALL_EXPR_ARG (exp, 0);
10934 tree arg0 = CALL_EXPR_ARG (exp, 1);
10935 tree arg1 = CALL_EXPR_ARG (exp, 2);
10936 rtx op0 = expand_normal (arg0);
10937 rtx op1 = expand_normal (arg1);
10938 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10939 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10941 enum rtx_code code;
10943 if (TREE_CODE (form) != INTEGER_CST)
10945 error ("argument 1 of __builtin_paired_predicate must be a constant");
10949 form_int = TREE_INT_CST_LOW (form);
10951 gcc_assert (mode0 == mode1);
10953 if (arg0 == error_mark_node || arg1 == error_mark_node)
10957 || GET_MODE (target) != SImode
10958 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
10959 target = gen_reg_rtx (SImode);
10960 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
10961 op0 = copy_to_mode_reg (mode0, op0);
10962 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
10963 op1 = copy_to_mode_reg (mode1, op1);
10965 scratch = gen_reg_rtx (CCFPmode);
10967 pat = GEN_FCN (icode) (scratch, op0, op1);
10989 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
10992 error ("argument 1 of __builtin_paired_predicate is out of range");
10996 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
10997 emit_move_insn (target, tmp);
11002 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11004 rtx pat, scratch, tmp;
11005 tree form = CALL_EXPR_ARG (exp, 0);
11006 tree arg0 = CALL_EXPR_ARG (exp, 1);
11007 tree arg1 = CALL_EXPR_ARG (exp, 2);
11008 rtx op0 = expand_normal (arg0);
11009 rtx op1 = expand_normal (arg1);
11010 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11011 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11013 enum rtx_code code;
11015 if (TREE_CODE (form) != INTEGER_CST)
11017 error ("argument 1 of __builtin_spe_predicate must be a constant");
11021 form_int = TREE_INT_CST_LOW (form);
11023 gcc_assert (mode0 == mode1);
11025 if (arg0 == error_mark_node || arg1 == error_mark_node)
11029 || GET_MODE (target) != SImode
11030 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11031 target = gen_reg_rtx (SImode);
11033 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11034 op0 = copy_to_mode_reg (mode0, op0);
11035 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11036 op1 = copy_to_mode_reg (mode1, op1);
11038 scratch = gen_reg_rtx (CCmode);
11040 pat = GEN_FCN (icode) (scratch, op0, op1);
11045 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11046 _lower_. We use one compare, but look in different bits of the
11047 CR for each variant.
11049 There are 2 elements in each SPE simd type (upper/lower). The CR
11050 bits are set as follows:
11052 BIT0 | BIT 1 | BIT 2 | BIT 3
11053 U | L | (U | L) | (U & L)
11055 So, for an "all" relationship, BIT 3 would be set.
11056 For an "any" relationship, BIT 2 would be set. Etc.
11058 Following traditional nomenclature, these bits map to:
11060 BIT0 | BIT 1 | BIT 2 | BIT 3
11063 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11068 /* All variant. OV bit. */
11070 /* We need to get to the OV bit, which is the ORDERED bit. We
11071 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11072 that's ugly and will make validate_condition_mode die.
11073 So let's just use another pattern. */
11074 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11076 /* Any variant. EQ bit. */
11080 /* Upper variant. LT bit. */
11084 /* Lower variant. GT bit. */
11089 error ("argument 1 of __builtin_spe_predicate is out of range");
11093 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11094 emit_move_insn (target, tmp);
11099 /* The evsel builtins look like this:
11101 e = __builtin_spe_evsel_OP (a, b, c, d);
11103 and work like this:
11105 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11106 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11110 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11113 tree arg0 = CALL_EXPR_ARG (exp, 0);
11114 tree arg1 = CALL_EXPR_ARG (exp, 1);
11115 tree arg2 = CALL_EXPR_ARG (exp, 2);
11116 tree arg3 = CALL_EXPR_ARG (exp, 3);
11117 rtx op0 = expand_normal (arg0);
11118 rtx op1 = expand_normal (arg1);
11119 rtx op2 = expand_normal (arg2);
11120 rtx op3 = expand_normal (arg3);
11121 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11122 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11124 gcc_assert (mode0 == mode1);
11126 if (arg0 == error_mark_node || arg1 == error_mark_node
11127 || arg2 == error_mark_node || arg3 == error_mark_node)
11131 || GET_MODE (target) != mode0
11132 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11133 target = gen_reg_rtx (mode0);
11135 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11136 op0 = copy_to_mode_reg (mode0, op0);
11137 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11138 op1 = copy_to_mode_reg (mode0, op1);
11139 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11140 op2 = copy_to_mode_reg (mode0, op2);
11141 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11142 op3 = copy_to_mode_reg (mode0, op3);
11144 /* Generate the compare. */
11145 scratch = gen_reg_rtx (CCmode);
11146 pat = GEN_FCN (icode) (scratch, op0, op1);
11151 if (mode0 == V2SImode)
11152 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11154 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11159 /* Raise an error message for a builtin function that is called without the
11160 appropriate target options being set. */
11163 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11165 size_t uns_fncode = (size_t)fncode;
11166 const char *name = rs6000_builtin_info[uns_fncode].name;
11167 unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
11169 gcc_assert (name != NULL);
11170 if ((fnmask & RS6000_BTM_CELL) != 0)
11171 error ("Builtin function %s is only valid for the cell processor", name);
11172 else if ((fnmask & RS6000_BTM_VSX) != 0)
11173 error ("Builtin function %s requires the -mvsx option", name);
11174 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11175 error ("Builtin function %s requires the -maltivec option", name);
11176 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11177 error ("Builtin function %s requires the -mpaired option", name);
11178 else if ((fnmask & RS6000_BTM_SPE) != 0)
11179 error ("Builtin function %s requires the -mspe option", name);
11181 error ("Builtin function %s is not supported with the current options",
11185 /* Expand an expression EXP that calls a built-in function,
11186 with result going to TARGET if that's convenient
11187 (and in mode MODE if that's convenient).
11188 SUBTARGET may be used as the target for computing one of EXP's operands.
11189 IGNORE is nonzero if the value is to be ignored. */
11192 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11193 enum machine_mode mode ATTRIBUTE_UNUSED,
11194 int ignore ATTRIBUTE_UNUSED)
11196 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11197 enum rs6000_builtins fcode
11198 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11199 size_t uns_fcode = (size_t)fcode;
11200 const struct builtin_description *d;
11204 unsigned mask = rs6000_builtin_info[uns_fcode].mask;
11205 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11207 if (TARGET_DEBUG_BUILTIN)
11209 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11210 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11211 const char *name2 = ((icode != CODE_FOR_nothing)
11212 ? get_insn_name ((int)icode)
11216 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11218 default: name3 = "unknown"; break;
11219 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11220 case RS6000_BTC_UNARY: name3 = "unary"; break;
11221 case RS6000_BTC_BINARY: name3 = "binary"; break;
11222 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11223 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11224 case RS6000_BTC_ABS: name3 = "abs"; break;
11225 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11226 case RS6000_BTC_DST: name3 = "dst"; break;
11231 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11232 (name1) ? name1 : "---", fcode,
11233 (name2) ? name2 : "---", (int)icode,
11235 func_valid_p ? "" : ", not valid");
11240 rs6000_invalid_builtin (fcode);
11242 /* Given it is invalid, just generate a normal call. */
11243 return expand_call (exp, target, ignore);
11248 case RS6000_BUILTIN_RECIP:
11249 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11251 case RS6000_BUILTIN_RECIPF:
11252 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11254 case RS6000_BUILTIN_RSQRTF:
11255 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11257 case RS6000_BUILTIN_RSQRT:
11258 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11260 case POWER7_BUILTIN_BPERMD:
11261 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11262 ? CODE_FOR_bpermd_di
11263 : CODE_FOR_bpermd_si), exp, target);
11265 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11266 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11268 int icode = (int) CODE_FOR_altivec_lvsr;
11269 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11270 enum machine_mode mode = insn_data[icode].operand[1].mode;
11274 gcc_assert (TARGET_ALTIVEC);
11276 arg = CALL_EXPR_ARG (exp, 0);
11277 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11278 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11279 addr = memory_address (mode, op);
11280 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11284 /* For the load case need to negate the address. */
11285 op = gen_reg_rtx (GET_MODE (addr));
11286 emit_insn (gen_rtx_SET (VOIDmode, op,
11287 gen_rtx_NEG (GET_MODE (addr), addr)));
11289 op = gen_rtx_MEM (mode, op);
11292 || GET_MODE (target) != tmode
11293 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11294 target = gen_reg_rtx (tmode);
11296 /*pat = gen_altivec_lvsr (target, op);*/
11297 pat = GEN_FCN (icode) (target, op);
11305 case ALTIVEC_BUILTIN_VCFUX:
11306 case ALTIVEC_BUILTIN_VCFSX:
11307 case ALTIVEC_BUILTIN_VCTUXS:
11308 case ALTIVEC_BUILTIN_VCTSXS:
11309 /* FIXME: There's got to be a nicer way to handle this case than
11310 constructing a new CALL_EXPR. */
11311 if (call_expr_nargs (exp) == 1)
11313 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11314 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11322 if (TARGET_ALTIVEC)
11324 ret = altivec_expand_builtin (exp, target, &success);
11331 ret = spe_expand_builtin (exp, target, &success);
11336 if (TARGET_PAIRED_FLOAT)
11338 ret = paired_expand_builtin (exp, target, &success);
11344 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11346 /* Handle simple unary operations. */
11348 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11349 if (d->code == fcode)
11350 return rs6000_expand_unop_builtin (d->icode, exp, target);
11352 /* Handle simple binary operations. */
11354 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11355 if (d->code == fcode)
11356 return rs6000_expand_binop_builtin (d->icode, exp, target);
11358 /* Handle simple ternary operations. */
11360 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11361 if (d->code == fcode)
11362 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11364 gcc_unreachable ();
11368 rs6000_init_builtins (void)
11372 enum machine_mode mode;
11374 if (TARGET_DEBUG_BUILTIN)
11375 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11376 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11377 (TARGET_SPE) ? ", spe" : "",
11378 (TARGET_ALTIVEC) ? ", altivec" : "",
11379 (TARGET_VSX) ? ", vsx" : "");
11381 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11382 V2SF_type_node = build_vector_type (float_type_node, 2);
11383 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11384 V2DF_type_node = build_vector_type (double_type_node, 2);
11385 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11386 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11387 V4SF_type_node = build_vector_type (float_type_node, 4);
11388 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11389 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11391 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11392 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11393 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11394 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11396 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11397 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11398 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11399 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11401 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11402 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11403 'vector unsigned short'. */
11405 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11406 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11407 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11408 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11409 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11411 long_integer_type_internal_node = long_integer_type_node;
11412 long_unsigned_type_internal_node = long_unsigned_type_node;
11413 long_long_integer_type_internal_node = long_long_integer_type_node;
11414 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11415 intQI_type_internal_node = intQI_type_node;
11416 uintQI_type_internal_node = unsigned_intQI_type_node;
11417 intHI_type_internal_node = intHI_type_node;
11418 uintHI_type_internal_node = unsigned_intHI_type_node;
11419 intSI_type_internal_node = intSI_type_node;
11420 uintSI_type_internal_node = unsigned_intSI_type_node;
11421 intDI_type_internal_node = intDI_type_node;
11422 uintDI_type_internal_node = unsigned_intDI_type_node;
11423 float_type_internal_node = float_type_node;
11424 double_type_internal_node = double_type_node;
11425 void_type_internal_node = void_type_node;
11427 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11429 builtin_mode_to_type[QImode][0] = integer_type_node;
11430 builtin_mode_to_type[HImode][0] = integer_type_node;
11431 builtin_mode_to_type[SImode][0] = intSI_type_node;
11432 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11433 builtin_mode_to_type[DImode][0] = intDI_type_node;
11434 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11435 builtin_mode_to_type[SFmode][0] = float_type_node;
11436 builtin_mode_to_type[DFmode][0] = double_type_node;
11437 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11438 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11439 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11440 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11441 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11442 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11443 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11444 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11445 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11446 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11447 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11448 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11449 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11451 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
11452 TYPE_NAME (bool_char_type_node) = tdecl;
11454 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
11455 TYPE_NAME (bool_short_type_node) = tdecl;
11457 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
11458 TYPE_NAME (bool_int_type_node) = tdecl;
11460 tdecl = add_builtin_type ("__pixel", pixel_type_node);
11461 TYPE_NAME (pixel_type_node) = tdecl;
11463 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11464 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11465 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11466 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11467 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11469 tdecl = add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node);
11470 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11472 tdecl = add_builtin_type ("__vector signed char", V16QI_type_node);
11473 TYPE_NAME (V16QI_type_node) = tdecl;
11475 tdecl = add_builtin_type ("__vector __bool char", bool_V16QI_type_node);
11476 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11478 tdecl = add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node);
11479 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11481 tdecl = add_builtin_type ("__vector signed short", V8HI_type_node);
11482 TYPE_NAME (V8HI_type_node) = tdecl;
11484 tdecl = add_builtin_type ("__vector __bool short", bool_V8HI_type_node);
11485 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11487 tdecl = add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node);
11488 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11490 tdecl = add_builtin_type ("__vector signed int", V4SI_type_node);
11491 TYPE_NAME (V4SI_type_node) = tdecl;
11493 tdecl = add_builtin_type ("__vector __bool int", bool_V4SI_type_node);
11494 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11496 tdecl = add_builtin_type ("__vector float", V4SF_type_node);
11497 TYPE_NAME (V4SF_type_node) = tdecl;
11499 tdecl = add_builtin_type ("__vector __pixel", pixel_V8HI_type_node);
11500 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11502 tdecl = add_builtin_type ("__vector double", V2DF_type_node);
11503 TYPE_NAME (V2DF_type_node) = tdecl;
11505 tdecl = add_builtin_type ("__vector long", V2DI_type_node);
11506 TYPE_NAME (V2DI_type_node) = tdecl;
11508 tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);
11509 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11511 tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
11512 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11514 /* Paired and SPE builtins are only available if you build a compiler with
11515 the appropriate options, so only create those builtins with the
11516 appropriate compiler option. Create Altivec and VSX builtins on machines
11517 with at least the general purpose extensions (970 and newer) to allow the
11518 use of the target attribute. */
11519 if (TARGET_PAIRED_FLOAT)
11520 paired_init_builtins ();
11522 spe_init_builtins ();
11523 if (TARGET_EXTRA_BUILTINS)
11524 altivec_init_builtins ();
11525 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11526 rs6000_common_init_builtins ();
11528 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11529 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11530 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11532 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11533 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11534 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11536 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11537 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11538 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11540 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11541 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11542 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11544 mode = (TARGET_64BIT) ? DImode : SImode;
11545 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11546 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11547 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11550 /* AIX libm provides clog as __clog. */
11551 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11552 set_user_assembler_name (tdecl, "__clog");
11555 #ifdef SUBTARGET_INIT_BUILTINS
11556 SUBTARGET_INIT_BUILTINS;
11560 /* Returns the rs6000 builtin decl for CODE. */
11563 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11567 if (code >= RS6000_BUILTIN_COUNT)
11568 return error_mark_node;
11570 fnmask = rs6000_builtin_info[code].mask;
11571 if ((fnmask & rs6000_builtin_mask) != fnmask)
11573 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11574 return error_mark_node;
11577 return rs6000_builtin_decls[code];
11581 spe_init_builtins (void)
11583 tree puint_type_node = build_pointer_type (unsigned_type_node);
11584 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11585 const struct builtin_description *d;
11588 tree v2si_ftype_4_v2si
11589 = build_function_type_list (opaque_V2SI_type_node,
11590 opaque_V2SI_type_node,
11591 opaque_V2SI_type_node,
11592 opaque_V2SI_type_node,
11593 opaque_V2SI_type_node,
11596 tree v2sf_ftype_4_v2sf
11597 = build_function_type_list (opaque_V2SF_type_node,
11598 opaque_V2SF_type_node,
11599 opaque_V2SF_type_node,
11600 opaque_V2SF_type_node,
11601 opaque_V2SF_type_node,
11604 tree int_ftype_int_v2si_v2si
11605 = build_function_type_list (integer_type_node,
11607 opaque_V2SI_type_node,
11608 opaque_V2SI_type_node,
11611 tree int_ftype_int_v2sf_v2sf
11612 = build_function_type_list (integer_type_node,
11614 opaque_V2SF_type_node,
11615 opaque_V2SF_type_node,
11618 tree void_ftype_v2si_puint_int
11619 = build_function_type_list (void_type_node,
11620 opaque_V2SI_type_node,
11625 tree void_ftype_v2si_puint_char
11626 = build_function_type_list (void_type_node,
11627 opaque_V2SI_type_node,
11632 tree void_ftype_v2si_pv2si_int
11633 = build_function_type_list (void_type_node,
11634 opaque_V2SI_type_node,
11635 opaque_p_V2SI_type_node,
11639 tree void_ftype_v2si_pv2si_char
11640 = build_function_type_list (void_type_node,
11641 opaque_V2SI_type_node,
11642 opaque_p_V2SI_type_node,
11646 tree void_ftype_int
11647 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11649 tree int_ftype_void
11650 = build_function_type_list (integer_type_node, NULL_TREE);
11652 tree v2si_ftype_pv2si_int
11653 = build_function_type_list (opaque_V2SI_type_node,
11654 opaque_p_V2SI_type_node,
11658 tree v2si_ftype_puint_int
11659 = build_function_type_list (opaque_V2SI_type_node,
11664 tree v2si_ftype_pushort_int
11665 = build_function_type_list (opaque_V2SI_type_node,
11670 tree v2si_ftype_signed_char
11671 = build_function_type_list (opaque_V2SI_type_node,
11672 signed_char_type_node,
11675 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
11677 /* Initialize irregular SPE builtins. */
11679 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11680 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11681 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11682 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11683 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11684 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11685 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11686 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11687 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11688 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11689 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11690 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11691 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11692 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11693 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11694 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11695 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11696 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11699 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11700 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11701 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11702 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11703 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11704 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11705 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11706 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11707 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11708 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11709 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11710 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11711 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11712 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11713 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11714 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11715 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11716 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11717 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11718 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11719 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11720 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11723 d = bdesc_spe_predicates;
11724 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11728 switch (insn_data[d->icode].operand[1].mode)
11731 type = int_ftype_int_v2si_v2si;
11734 type = int_ftype_int_v2sf_v2sf;
11737 gcc_unreachable ();
11740 def_builtin (d->name, type, d->code);
11743 /* Evsel predicates. */
11744 d = bdesc_spe_evsel;
11745 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11749 switch (insn_data[d->icode].operand[1].mode)
11752 type = v2si_ftype_4_v2si;
11755 type = v2sf_ftype_4_v2sf;
11758 gcc_unreachable ();
11761 def_builtin (d->name, type, d->code);
11766 paired_init_builtins (void)
11768 const struct builtin_description *d;
11771 tree int_ftype_int_v2sf_v2sf
11772 = build_function_type_list (integer_type_node,
11777 tree pcfloat_type_node =
11778 build_pointer_type (build_qualified_type
11779 (float_type_node, TYPE_QUAL_CONST));
11781 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
11782 long_integer_type_node,
11785 tree void_ftype_v2sf_long_pcfloat =
11786 build_function_type_list (void_type_node,
11788 long_integer_type_node,
11793 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
11794 PAIRED_BUILTIN_LX);
11797 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
11798 PAIRED_BUILTIN_STX);
11801 d = bdesc_paired_preds;
11802 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
11806 if (TARGET_DEBUG_BUILTIN)
11807 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
11808 (int)i, get_insn_name (d->icode), (int)d->icode,
11809 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
11811 switch (insn_data[d->icode].operand[1].mode)
11814 type = int_ftype_int_v2sf_v2sf;
11817 gcc_unreachable ();
11820 def_builtin (d->name, type, d->code);
11825 altivec_init_builtins (void)
11827 const struct builtin_description *d;
11832 tree pvoid_type_node = build_pointer_type (void_type_node);
11834 tree pcvoid_type_node
11835 = build_pointer_type (build_qualified_type (void_type_node,
11838 tree int_ftype_opaque
11839 = build_function_type_list (integer_type_node,
11840 opaque_V4SI_type_node, NULL_TREE);
11841 tree opaque_ftype_opaque
11842 = build_function_type_list (integer_type_node, NULL_TREE);
11843 tree opaque_ftype_opaque_int
11844 = build_function_type_list (opaque_V4SI_type_node,
11845 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
11846 tree opaque_ftype_opaque_opaque_int
11847 = build_function_type_list (opaque_V4SI_type_node,
11848 opaque_V4SI_type_node, opaque_V4SI_type_node,
11849 integer_type_node, NULL_TREE);
11850 tree int_ftype_int_opaque_opaque
11851 = build_function_type_list (integer_type_node,
11852 integer_type_node, opaque_V4SI_type_node,
11853 opaque_V4SI_type_node, NULL_TREE);
11854 tree int_ftype_int_v4si_v4si
11855 = build_function_type_list (integer_type_node,
11856 integer_type_node, V4SI_type_node,
11857 V4SI_type_node, NULL_TREE);
11858 tree void_ftype_v4si
11859 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
11860 tree v8hi_ftype_void
11861 = build_function_type_list (V8HI_type_node, NULL_TREE);
11862 tree void_ftype_void
11863 = build_function_type_list (void_type_node, NULL_TREE);
11864 tree void_ftype_int
11865 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11867 tree opaque_ftype_long_pcvoid
11868 = build_function_type_list (opaque_V4SI_type_node,
11869 long_integer_type_node, pcvoid_type_node,
11871 tree v16qi_ftype_long_pcvoid
11872 = build_function_type_list (V16QI_type_node,
11873 long_integer_type_node, pcvoid_type_node,
11875 tree v8hi_ftype_long_pcvoid
11876 = build_function_type_list (V8HI_type_node,
11877 long_integer_type_node, pcvoid_type_node,
11879 tree v4si_ftype_long_pcvoid
11880 = build_function_type_list (V4SI_type_node,
11881 long_integer_type_node, pcvoid_type_node,
11883 tree v4sf_ftype_long_pcvoid
11884 = build_function_type_list (V4SF_type_node,
11885 long_integer_type_node, pcvoid_type_node,
11887 tree v2df_ftype_long_pcvoid
11888 = build_function_type_list (V2DF_type_node,
11889 long_integer_type_node, pcvoid_type_node,
11891 tree v2di_ftype_long_pcvoid
11892 = build_function_type_list (V2DI_type_node,
11893 long_integer_type_node, pcvoid_type_node,
11896 tree void_ftype_opaque_long_pvoid
11897 = build_function_type_list (void_type_node,
11898 opaque_V4SI_type_node, long_integer_type_node,
11899 pvoid_type_node, NULL_TREE);
11900 tree void_ftype_v4si_long_pvoid
11901 = build_function_type_list (void_type_node,
11902 V4SI_type_node, long_integer_type_node,
11903 pvoid_type_node, NULL_TREE);
11904 tree void_ftype_v16qi_long_pvoid
11905 = build_function_type_list (void_type_node,
11906 V16QI_type_node, long_integer_type_node,
11907 pvoid_type_node, NULL_TREE);
11908 tree void_ftype_v8hi_long_pvoid
11909 = build_function_type_list (void_type_node,
11910 V8HI_type_node, long_integer_type_node,
11911 pvoid_type_node, NULL_TREE);
11912 tree void_ftype_v4sf_long_pvoid
11913 = build_function_type_list (void_type_node,
11914 V4SF_type_node, long_integer_type_node,
11915 pvoid_type_node, NULL_TREE);
11916 tree void_ftype_v2df_long_pvoid
11917 = build_function_type_list (void_type_node,
11918 V2DF_type_node, long_integer_type_node,
11919 pvoid_type_node, NULL_TREE);
11920 tree void_ftype_v2di_long_pvoid
11921 = build_function_type_list (void_type_node,
11922 V2DI_type_node, long_integer_type_node,
11923 pvoid_type_node, NULL_TREE);
11924 tree int_ftype_int_v8hi_v8hi
11925 = build_function_type_list (integer_type_node,
11926 integer_type_node, V8HI_type_node,
11927 V8HI_type_node, NULL_TREE);
11928 tree int_ftype_int_v16qi_v16qi
11929 = build_function_type_list (integer_type_node,
11930 integer_type_node, V16QI_type_node,
11931 V16QI_type_node, NULL_TREE);
11932 tree int_ftype_int_v4sf_v4sf
11933 = build_function_type_list (integer_type_node,
11934 integer_type_node, V4SF_type_node,
11935 V4SF_type_node, NULL_TREE);
11936 tree int_ftype_int_v2df_v2df
11937 = build_function_type_list (integer_type_node,
11938 integer_type_node, V2DF_type_node,
11939 V2DF_type_node, NULL_TREE);
11940 tree v4si_ftype_v4si
11941 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
11942 tree v8hi_ftype_v8hi
11943 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
11944 tree v16qi_ftype_v16qi
11945 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
11946 tree v4sf_ftype_v4sf
11947 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
11948 tree v2df_ftype_v2df
11949 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
11950 tree void_ftype_pcvoid_int_int
11951 = build_function_type_list (void_type_node,
11952 pcvoid_type_node, integer_type_node,
11953 integer_type_node, NULL_TREE);
11955 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
11956 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
11957 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
11958 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
11959 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
11960 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
11961 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
11962 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
11963 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
11964 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
11965 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
11966 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
11967 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
11968 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
11969 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
11970 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
11971 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
11972 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
11973 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
11974 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
11975 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
11976 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
11977 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
11978 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
11979 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
11980 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
11981 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
11982 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
11983 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
11984 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
11986 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
11987 VSX_BUILTIN_LXVD2X_V2DF);
11988 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
11989 VSX_BUILTIN_LXVD2X_V2DI);
11990 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
11991 VSX_BUILTIN_LXVW4X_V4SF);
11992 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
11993 VSX_BUILTIN_LXVW4X_V4SI);
11994 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
11995 VSX_BUILTIN_LXVW4X_V8HI);
11996 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
11997 VSX_BUILTIN_LXVW4X_V16QI);
11998 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
11999 VSX_BUILTIN_STXVD2X_V2DF);
12000 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12001 VSX_BUILTIN_STXVD2X_V2DI);
12002 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12003 VSX_BUILTIN_STXVW4X_V4SF);
12004 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12005 VSX_BUILTIN_STXVW4X_V4SI);
12006 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12007 VSX_BUILTIN_STXVW4X_V8HI);
12008 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12009 VSX_BUILTIN_STXVW4X_V16QI);
12010 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12011 VSX_BUILTIN_VEC_LD);
12012 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12013 VSX_BUILTIN_VEC_ST);
12015 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12016 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12017 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12019 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12020 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12021 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12022 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12023 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12024 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12025 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12026 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12027 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12028 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12029 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12030 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12032 /* Cell builtins. */
12033 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12034 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12035 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12036 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12038 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12039 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12040 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12041 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12043 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12044 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12045 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12046 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12048 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12049 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12050 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12051 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12053 /* Add the DST variants. */
12055 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12056 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12058 /* Initialize the predicates. */
12059 d = bdesc_altivec_preds;
12060 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12062 enum machine_mode mode1;
12065 if (rs6000_overloaded_builtin_p (d->code))
12068 mode1 = insn_data[d->icode].operand[1].mode;
12073 type = int_ftype_int_opaque_opaque;
12076 type = int_ftype_int_v4si_v4si;
12079 type = int_ftype_int_v8hi_v8hi;
12082 type = int_ftype_int_v16qi_v16qi;
12085 type = int_ftype_int_v4sf_v4sf;
12088 type = int_ftype_int_v2df_v2df;
12091 gcc_unreachable ();
12094 def_builtin (d->name, type, d->code);
12097 /* Initialize the abs* operators. */
12099 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12101 enum machine_mode mode0;
12104 mode0 = insn_data[d->icode].operand[0].mode;
12109 type = v4si_ftype_v4si;
12112 type = v8hi_ftype_v8hi;
12115 type = v16qi_ftype_v16qi;
12118 type = v4sf_ftype_v4sf;
12121 type = v2df_ftype_v2df;
12124 gcc_unreachable ();
12127 def_builtin (d->name, type, d->code);
12130 /* Initialize target builtin that implements
12131 targetm.vectorize.builtin_mask_for_load. */
12133 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12134 v16qi_ftype_long_pcvoid,
12135 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12136 BUILT_IN_MD, NULL, NULL_TREE);
12137 TREE_READONLY (decl) = 1;
12138 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12139 altivec_builtin_mask_for_load = decl;
12141 /* Access to the vec_init patterns. */
12142 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12143 integer_type_node, integer_type_node,
12144 integer_type_node, NULL_TREE);
12145 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12147 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12148 short_integer_type_node,
12149 short_integer_type_node,
12150 short_integer_type_node,
12151 short_integer_type_node,
12152 short_integer_type_node,
12153 short_integer_type_node,
12154 short_integer_type_node, NULL_TREE);
12155 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12157 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12158 char_type_node, char_type_node,
12159 char_type_node, char_type_node,
12160 char_type_node, char_type_node,
12161 char_type_node, char_type_node,
12162 char_type_node, char_type_node,
12163 char_type_node, char_type_node,
12164 char_type_node, char_type_node,
12165 char_type_node, NULL_TREE);
12166 def_builtin ("__builtin_vec_init_v16qi", ftype,
12167 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12169 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12170 float_type_node, float_type_node,
12171 float_type_node, NULL_TREE);
12172 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12174 /* VSX builtins. */
12175 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12176 double_type_node, NULL_TREE);
12177 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12179 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12180 intDI_type_node, NULL_TREE);
12181 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12183 /* Access to the vec_set patterns. */
12184 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12186 integer_type_node, NULL_TREE);
12187 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12189 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12191 integer_type_node, NULL_TREE);
12192 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12194 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12196 integer_type_node, NULL_TREE);
12197 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12199 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12201 integer_type_node, NULL_TREE);
12202 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12204 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12206 integer_type_node, NULL_TREE);
12207 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12209 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12211 integer_type_node, NULL_TREE);
12212 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12214 /* Access to the vec_extract patterns. */
12215 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12216 integer_type_node, NULL_TREE);
12217 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12219 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12220 integer_type_node, NULL_TREE);
12221 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12223 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12224 integer_type_node, NULL_TREE);
12225 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12227 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12228 integer_type_node, NULL_TREE);
12229 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12231 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12232 integer_type_node, NULL_TREE);
12233 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12235 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12236 integer_type_node, NULL_TREE);
12237 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12240 /* Hash function for builtin functions with up to 3 arguments and a return
12243 builtin_hash_function (const void *hash_entry)
12247 const struct builtin_hash_struct *bh =
12248 (const struct builtin_hash_struct *) hash_entry;
12250 for (i = 0; i < 4; i++)
12252 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12253 ret = (ret * 2) + bh->uns_p[i];
12259 /* Compare builtin hash entries H1 and H2 for equivalence. */
12261 builtin_hash_eq (const void *h1, const void *h2)
12263 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12264 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12266 return ((p1->mode[0] == p2->mode[0])
12267 && (p1->mode[1] == p2->mode[1])
12268 && (p1->mode[2] == p2->mode[2])
12269 && (p1->mode[3] == p2->mode[3])
12270 && (p1->uns_p[0] == p2->uns_p[0])
12271 && (p1->uns_p[1] == p2->uns_p[1])
12272 && (p1->uns_p[2] == p2->uns_p[2])
12273 && (p1->uns_p[3] == p2->uns_p[3]));
12276 /* Map types for builtin functions with an explicit return type and up to 3
12277 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12278 of the argument. */
12280 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12281 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12282 enum rs6000_builtins builtin, const char *name)
12284 struct builtin_hash_struct h;
12285 struct builtin_hash_struct *h2;
12289 tree ret_type = NULL_TREE;
12290 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12292 /* Create builtin_hash_table. */
12293 if (builtin_hash_table == NULL)
12294 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12295 builtin_hash_eq, NULL);
12297 h.type = NULL_TREE;
12298 h.mode[0] = mode_ret;
12299 h.mode[1] = mode_arg0;
12300 h.mode[2] = mode_arg1;
12301 h.mode[3] = mode_arg2;
12307 /* If the builtin is a type that produces unsigned results or takes unsigned
12308 arguments, and it is returned as a decl for the vectorizer (such as
12309 widening multiplies, permute), make sure the arguments and return value
12310 are type correct. */
12313 /* unsigned 2 argument functions. */
12314 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12315 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12316 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12317 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12323 /* unsigned 3 argument functions. */
12324 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12325 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12326 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12327 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12328 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12329 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12330 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12331 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12332 case VSX_BUILTIN_VPERM_16QI_UNS:
12333 case VSX_BUILTIN_VPERM_8HI_UNS:
12334 case VSX_BUILTIN_VPERM_4SI_UNS:
12335 case VSX_BUILTIN_VPERM_2DI_UNS:
12336 case VSX_BUILTIN_XXSEL_16QI_UNS:
12337 case VSX_BUILTIN_XXSEL_8HI_UNS:
12338 case VSX_BUILTIN_XXSEL_4SI_UNS:
12339 case VSX_BUILTIN_XXSEL_2DI_UNS:
12346 /* signed permute functions with unsigned char mask. */
12347 case ALTIVEC_BUILTIN_VPERM_16QI:
12348 case ALTIVEC_BUILTIN_VPERM_8HI:
12349 case ALTIVEC_BUILTIN_VPERM_4SI:
12350 case ALTIVEC_BUILTIN_VPERM_4SF:
12351 case ALTIVEC_BUILTIN_VPERM_2DI:
12352 case ALTIVEC_BUILTIN_VPERM_2DF:
12353 case VSX_BUILTIN_VPERM_16QI:
12354 case VSX_BUILTIN_VPERM_8HI:
12355 case VSX_BUILTIN_VPERM_4SI:
12356 case VSX_BUILTIN_VPERM_4SF:
12357 case VSX_BUILTIN_VPERM_2DI:
12358 case VSX_BUILTIN_VPERM_2DF:
12362 /* unsigned args, signed return. */
12363 case VSX_BUILTIN_XVCVUXDDP_UNS:
12364 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12368 /* signed args, unsigned return. */
12369 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12370 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12378 /* Figure out how many args are present. */
12379 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12383 fatal_error ("internal error: builtin function %s had no type", name);
12385 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12386 if (!ret_type && h.uns_p[0])
12387 ret_type = builtin_mode_to_type[h.mode[0]][0];
12390 fatal_error ("internal error: builtin function %s had an unexpected "
12391 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12393 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12394 arg_type[i] = NULL_TREE;
12396 for (i = 0; i < num_args; i++)
12398 int m = (int) h.mode[i+1];
12399 int uns_p = h.uns_p[i+1];
12401 arg_type[i] = builtin_mode_to_type[m][uns_p];
12402 if (!arg_type[i] && uns_p)
12403 arg_type[i] = builtin_mode_to_type[m][0];
12406 fatal_error ("internal error: builtin function %s, argument %d "
12407 "had unexpected argument type %s", name, i,
12408 GET_MODE_NAME (m));
12411 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12412 if (*found == NULL)
12414 h2 = ggc_alloc_builtin_hash_struct ();
12416 *found = (void *)h2;
12418 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12419 arg_type[2], NULL_TREE);
12422 return ((struct builtin_hash_struct *)(*found))->type;
12426 rs6000_common_init_builtins (void)
12428 const struct builtin_description *d;
12431 tree opaque_ftype_opaque = NULL_TREE;
12432 tree opaque_ftype_opaque_opaque = NULL_TREE;
12433 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12434 tree v2si_ftype_qi = NULL_TREE;
12435 tree v2si_ftype_v2si_qi = NULL_TREE;
12436 tree v2si_ftype_int_qi = NULL_TREE;
12437 unsigned builtin_mask = rs6000_builtin_mask;
12439 if (!TARGET_PAIRED_FLOAT)
12441 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12442 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12445 /* Paired and SPE builtins are only available if you build a compiler with
12446 the appropriate options, so only create those builtins with the
12447 appropriate compiler option. Create Altivec and VSX builtins on machines
12448 with at least the general purpose extensions (970 and newer) to allow the
12449 use of the target attribute.. */
12451 if (TARGET_EXTRA_BUILTINS)
12452 builtin_mask |= RS6000_BTM_COMMON;
12454 /* Add the ternary operators. */
12456 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12459 unsigned mask = d->mask;
12461 if ((mask & builtin_mask) != mask)
12463 if (TARGET_DEBUG_BUILTIN)
12464 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12468 if (rs6000_overloaded_builtin_p (d->code))
12470 if (! (type = opaque_ftype_opaque_opaque_opaque))
12471 type = opaque_ftype_opaque_opaque_opaque
12472 = build_function_type_list (opaque_V4SI_type_node,
12473 opaque_V4SI_type_node,
12474 opaque_V4SI_type_node,
12475 opaque_V4SI_type_node,
12480 enum insn_code icode = d->icode;
12481 if (d->name == 0 || icode == CODE_FOR_nothing)
12484 type = builtin_function_type (insn_data[icode].operand[0].mode,
12485 insn_data[icode].operand[1].mode,
12486 insn_data[icode].operand[2].mode,
12487 insn_data[icode].operand[3].mode,
12491 def_builtin (d->name, type, d->code);
12494 /* Add the binary operators. */
12496 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12498 enum machine_mode mode0, mode1, mode2;
12500 unsigned mask = d->mask;
12502 if ((mask & builtin_mask) != mask)
12504 if (TARGET_DEBUG_BUILTIN)
12505 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12509 if (rs6000_overloaded_builtin_p (d->code))
12511 if (! (type = opaque_ftype_opaque_opaque))
12512 type = opaque_ftype_opaque_opaque
12513 = build_function_type_list (opaque_V4SI_type_node,
12514 opaque_V4SI_type_node,
12515 opaque_V4SI_type_node,
12520 enum insn_code icode = d->icode;
12521 if (d->name == 0 || icode == CODE_FOR_nothing)
12524 mode0 = insn_data[icode].operand[0].mode;
12525 mode1 = insn_data[icode].operand[1].mode;
12526 mode2 = insn_data[icode].operand[2].mode;
12528 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12530 if (! (type = v2si_ftype_v2si_qi))
12531 type = v2si_ftype_v2si_qi
12532 = build_function_type_list (opaque_V2SI_type_node,
12533 opaque_V2SI_type_node,
12538 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12539 && mode2 == QImode)
12541 if (! (type = v2si_ftype_int_qi))
12542 type = v2si_ftype_int_qi
12543 = build_function_type_list (opaque_V2SI_type_node,
12550 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12554 def_builtin (d->name, type, d->code);
12557 /* Add the simple unary operators. */
12559 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12561 enum machine_mode mode0, mode1;
12563 unsigned mask = d->mask;
12565 if ((mask & builtin_mask) != mask)
12567 if (TARGET_DEBUG_BUILTIN)
12568 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12572 if (rs6000_overloaded_builtin_p (d->code))
12574 if (! (type = opaque_ftype_opaque))
12575 type = opaque_ftype_opaque
12576 = build_function_type_list (opaque_V4SI_type_node,
12577 opaque_V4SI_type_node,
12582 enum insn_code icode = d->icode;
12583 if (d->name == 0 || icode == CODE_FOR_nothing)
12586 mode0 = insn_data[icode].operand[0].mode;
12587 mode1 = insn_data[icode].operand[1].mode;
12589 if (mode0 == V2SImode && mode1 == QImode)
12591 if (! (type = v2si_ftype_qi))
12592 type = v2si_ftype_qi
12593 = build_function_type_list (opaque_V2SI_type_node,
12599 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12603 def_builtin (d->name, type, d->code);
12608 rs6000_init_libfuncs (void)
12610 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
12611 && !TARGET_POWER2 && !TARGET_POWERPC)
12613 /* AIX library routines for float->int conversion. */
12614 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
12615 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
12616 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
12617 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
12620 if (!TARGET_IEEEQUAD)
12621 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12622 if (!TARGET_XL_COMPAT)
12624 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12625 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12626 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12627 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12629 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12631 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12632 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12633 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12634 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12635 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12636 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12637 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12639 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12640 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12641 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12642 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12643 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12644 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12645 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12646 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12649 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12650 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12654 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12655 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12656 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12657 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12661 /* 32-bit SVR4 quad floating point routines. */
12663 set_optab_libfunc (add_optab, TFmode, "_q_add");
12664 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12665 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12666 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12667 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12668 if (TARGET_PPC_GPOPT || TARGET_POWER2)
12669 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12671 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12672 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12673 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12674 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12675 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12676 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12678 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12679 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12680 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12681 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12682 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12683 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12684 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12685 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12690 /* Expand a block clear operation, and return 1 if successful. Return 0
12691 if we should let the compiler generate normal code.
12693 operands[0] is the destination
12694 operands[1] is the length
12695 operands[3] is the alignment */
12698 expand_block_clear (rtx operands[])
12700 rtx orig_dest = operands[0];
12701 rtx bytes_rtx = operands[1];
12702 rtx align_rtx = operands[3];
12703 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12704 HOST_WIDE_INT align;
12705 HOST_WIDE_INT bytes;
12710 /* If this is not a fixed size move, just call memcpy */
12714 /* This must be a fixed size alignment */
12715 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12716 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12718 /* Anything to clear? */
12719 bytes = INTVAL (bytes_rtx);
12723 /* Use the builtin memset after a point, to avoid huge code bloat.
12724 When optimize_size, avoid any significant code bloat; calling
12725 memset is about 4 instructions, so allow for one instruction to
12726 load zero and three to do clearing. */
12727 if (TARGET_ALTIVEC && align >= 128)
12729 else if (TARGET_POWERPC64 && align >= 32)
12731 else if (TARGET_SPE && align >= 64)
12736 if (optimize_size && bytes > 3 * clear_step)
12738 if (! optimize_size && bytes > 8 * clear_step)
12741 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12743 enum machine_mode mode = BLKmode;
12746 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12751 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12756 else if (bytes >= 8 && TARGET_POWERPC64
12757 /* 64-bit loads and stores require word-aligned
12759 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12764 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12765 { /* move 4 bytes */
12769 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12770 { /* move 2 bytes */
12774 else /* move 1 byte at a time */
12780 dest = adjust_address (orig_dest, mode, offset);
12782 emit_move_insn (dest, CONST0_RTX (mode));
12789 /* Expand a block move operation, and return 1 if successful. Return 0
12790 if we should let the compiler generate normal code.
12792 operands[0] is the destination
12793 operands[1] is the source
12794 operands[2] is the length
12795 operands[3] is the alignment */
12797 #define MAX_MOVE_REG 4
12800 expand_block_move (rtx operands[])
12802 rtx orig_dest = operands[0];
12803 rtx orig_src = operands[1];
12804 rtx bytes_rtx = operands[2];
12805 rtx align_rtx = operands[3];
12806 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
12811 rtx stores[MAX_MOVE_REG];
12814 /* If this is not a fixed size move, just call memcpy */
12818 /* This must be a fixed size alignment */
12819 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12820 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12822 /* Anything to move? */
12823 bytes = INTVAL (bytes_rtx);
12827 if (bytes > rs6000_block_move_inline_limit)
12830 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
12833 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
12834 rtx (*mov) (rtx, rtx);
12836 enum machine_mode mode = BLKmode;
12839 /* Altivec first, since it will be faster than a string move
12840 when it applies, and usually not significantly larger. */
12841 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
12845 gen_func.mov = gen_movv4si;
12847 else if (TARGET_SPE && bytes >= 8 && align >= 64)
12851 gen_func.mov = gen_movv2si;
12853 else if (TARGET_STRING
12854 && bytes > 24 /* move up to 32 bytes at a time */
12860 && ! fixed_regs[10]
12861 && ! fixed_regs[11]
12862 && ! fixed_regs[12])
12864 move_bytes = (bytes > 32) ? 32 : bytes;
12865 gen_func.movmemsi = gen_movmemsi_8reg;
12867 else if (TARGET_STRING
12868 && bytes > 16 /* move up to 24 bytes at a time */
12874 && ! fixed_regs[10])
12876 move_bytes = (bytes > 24) ? 24 : bytes;
12877 gen_func.movmemsi = gen_movmemsi_6reg;
12879 else if (TARGET_STRING
12880 && bytes > 8 /* move up to 16 bytes at a time */
12884 && ! fixed_regs[8])
12886 move_bytes = (bytes > 16) ? 16 : bytes;
12887 gen_func.movmemsi = gen_movmemsi_4reg;
12889 else if (bytes >= 8 && TARGET_POWERPC64
12890 /* 64-bit loads and stores require word-aligned
12892 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12896 gen_func.mov = gen_movdi;
12898 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
12899 { /* move up to 8 bytes at a time */
12900 move_bytes = (bytes > 8) ? 8 : bytes;
12901 gen_func.movmemsi = gen_movmemsi_2reg;
12903 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12904 { /* move 4 bytes */
12907 gen_func.mov = gen_movsi;
12909 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12910 { /* move 2 bytes */
12913 gen_func.mov = gen_movhi;
12915 else if (TARGET_STRING && bytes > 1)
12916 { /* move up to 4 bytes at a time */
12917 move_bytes = (bytes > 4) ? 4 : bytes;
12918 gen_func.movmemsi = gen_movmemsi_1reg;
12920 else /* move 1 byte at a time */
12924 gen_func.mov = gen_movqi;
12927 src = adjust_address (orig_src, mode, offset);
12928 dest = adjust_address (orig_dest, mode, offset);
12930 if (mode != BLKmode)
12932 rtx tmp_reg = gen_reg_rtx (mode);
12934 emit_insn ((*gen_func.mov) (tmp_reg, src));
12935 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
12938 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
12941 for (i = 0; i < num_reg; i++)
12942 emit_insn (stores[i]);
12946 if (mode == BLKmode)
12948 /* Move the address into scratch registers. The movmemsi
12949 patterns require zero offset. */
12950 if (!REG_P (XEXP (src, 0)))
12952 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
12953 src = replace_equiv_address (src, src_reg);
12955 set_mem_size (src, move_bytes);
12957 if (!REG_P (XEXP (dest, 0)))
12959 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
12960 dest = replace_equiv_address (dest, dest_reg);
12962 set_mem_size (dest, move_bytes);
12964 emit_insn ((*gen_func.movmemsi) (dest, src,
12965 GEN_INT (move_bytes & 31),
12974 /* Return a string to perform a load_multiple operation.
12975 operands[0] is the vector.
12976 operands[1] is the source address.
12977 operands[2] is the first destination register. */
12980 rs6000_output_load_multiple (rtx operands[3])
12982 /* We have to handle the case where the pseudo used to contain the address
12983 is assigned to one of the output registers. */
12985 int words = XVECLEN (operands[0], 0);
12988 if (XVECLEN (operands[0], 0) == 1)
12989 return "{l|lwz} %2,0(%1)";
12991 for (i = 0; i < words; i++)
12992 if (refers_to_regno_p (REGNO (operands[2]) + i,
12993 REGNO (operands[2]) + i + 1, operands[1], 0))
12997 xop[0] = GEN_INT (4 * (words-1));
12998 xop[1] = operands[1];
12999 xop[2] = operands[2];
13000 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
13005 xop[0] = GEN_INT (4 * (words-1));
13006 xop[1] = operands[1];
13007 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13008 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
13013 for (j = 0; j < words; j++)
13016 xop[0] = GEN_INT (j * 4);
13017 xop[1] = operands[1];
13018 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13019 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
13021 xop[0] = GEN_INT (i * 4);
13022 xop[1] = operands[1];
13023 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
13028 return "{lsi|lswi} %2,%1,%N0";
13032 /* A validation routine: say whether CODE, a condition code, and MODE
13033 match. The other alternatives either don't make sense or should
13034 never be generated. */
13037 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13039 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13040 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13041 && GET_MODE_CLASS (mode) == MODE_CC);
13043 /* These don't make sense. */
13044 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13045 || mode != CCUNSmode);
13047 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13048 || mode == CCUNSmode);
13050 gcc_assert (mode == CCFPmode
13051 || (code != ORDERED && code != UNORDERED
13052 && code != UNEQ && code != LTGT
13053 && code != UNGT && code != UNLT
13054 && code != UNGE && code != UNLE));
13056 /* These should never be generated except for
13057 flag_finite_math_only. */
13058 gcc_assert (mode != CCFPmode
13059 || flag_finite_math_only
13060 || (code != LE && code != GE
13061 && code != UNEQ && code != LTGT
13062 && code != UNGT && code != UNLT));
13064 /* These are invalid; the information is not there. */
13065 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13069 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13070 mask required to convert the result of a rotate insn into a shift
13071 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13074 includes_lshift_p (rtx shiftop, rtx andop)
13076 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13078 shift_mask <<= INTVAL (shiftop);
13080 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13083 /* Similar, but for right shift. */
13086 includes_rshift_p (rtx shiftop, rtx andop)
13088 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13090 shift_mask >>= INTVAL (shiftop);
13092 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13095 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13096 to perform a left shift. It must have exactly SHIFTOP least
13097 significant 0's, then one or more 1's, then zero or more 0's. */
13100 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13102 if (GET_CODE (andop) == CONST_INT)
13104 HOST_WIDE_INT c, lsb, shift_mask;
13106 c = INTVAL (andop);
13107 if (c == 0 || c == ~0)
13111 shift_mask <<= INTVAL (shiftop);
13113 /* Find the least significant one bit. */
13116 /* It must coincide with the LSB of the shift mask. */
13117 if (-lsb != shift_mask)
13120 /* Invert to look for the next transition (if any). */
13123 /* Remove the low group of ones (originally low group of zeros). */
13126 /* Again find the lsb, and check we have all 1's above. */
13130 else if (GET_CODE (andop) == CONST_DOUBLE
13131 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13133 HOST_WIDE_INT low, high, lsb;
13134 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13136 low = CONST_DOUBLE_LOW (andop);
13137 if (HOST_BITS_PER_WIDE_INT < 64)
13138 high = CONST_DOUBLE_HIGH (andop);
13140 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13141 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13144 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13146 shift_mask_high = ~0;
13147 if (INTVAL (shiftop) > 32)
13148 shift_mask_high <<= INTVAL (shiftop) - 32;
13150 lsb = high & -high;
13152 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13158 lsb = high & -high;
13159 return high == -lsb;
13162 shift_mask_low = ~0;
13163 shift_mask_low <<= INTVAL (shiftop);
13167 if (-lsb != shift_mask_low)
13170 if (HOST_BITS_PER_WIDE_INT < 64)
13175 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13177 lsb = high & -high;
13178 return high == -lsb;
13182 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13188 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13189 to perform a left shift. It must have SHIFTOP or more least
13190 significant 0's, with the remainder of the word 1's. */
13193 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13195 if (GET_CODE (andop) == CONST_INT)
13197 HOST_WIDE_INT c, lsb, shift_mask;
13200 shift_mask <<= INTVAL (shiftop);
13201 c = INTVAL (andop);
13203 /* Find the least significant one bit. */
13206 /* It must be covered by the shift mask.
13207 This test also rejects c == 0. */
13208 if ((lsb & shift_mask) == 0)
13211 /* Check we have all 1's above the transition, and reject all 1's. */
13212 return c == -lsb && lsb != 1;
13214 else if (GET_CODE (andop) == CONST_DOUBLE
13215 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13217 HOST_WIDE_INT low, lsb, shift_mask_low;
13219 low = CONST_DOUBLE_LOW (andop);
13221 if (HOST_BITS_PER_WIDE_INT < 64)
13223 HOST_WIDE_INT high, shift_mask_high;
13225 high = CONST_DOUBLE_HIGH (andop);
13229 shift_mask_high = ~0;
13230 if (INTVAL (shiftop) > 32)
13231 shift_mask_high <<= INTVAL (shiftop) - 32;
13233 lsb = high & -high;
13235 if ((lsb & shift_mask_high) == 0)
13238 return high == -lsb;
13244 shift_mask_low = ~0;
13245 shift_mask_low <<= INTVAL (shiftop);
13249 if ((lsb & shift_mask_low) == 0)
13252 return low == -lsb && lsb != 1;
13258 /* Return 1 if operands will generate a valid arguments to rlwimi
13259 instruction for insert with right shift in 64-bit mode. The mask may
13260 not start on the first bit or stop on the last bit because wrap-around
13261 effects of instruction do not correspond to semantics of RTL insn. */
13264 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13266 if (INTVAL (startop) > 32
13267 && INTVAL (startop) < 64
13268 && INTVAL (sizeop) > 1
13269 && INTVAL (sizeop) + INTVAL (startop) < 64
13270 && INTVAL (shiftop) > 0
13271 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13272 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13278 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13279 for lfq and stfq insns iff the registers are hard registers. */
13282 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13284 /* We might have been passed a SUBREG. */
13285 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13288 /* We might have been passed non floating point registers. */
13289 if (!FP_REGNO_P (REGNO (reg1))
13290 || !FP_REGNO_P (REGNO (reg2)))
13293 return (REGNO (reg1) == REGNO (reg2) - 1);
13296 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13297 addr1 and addr2 must be in consecutive memory locations
13298 (addr2 == addr1 + 8). */
13301 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13304 unsigned int reg1, reg2;
13305 int offset1, offset2;
13307 /* The mems cannot be volatile. */
13308 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13311 addr1 = XEXP (mem1, 0);
13312 addr2 = XEXP (mem2, 0);
13314 /* Extract an offset (if used) from the first addr. */
13315 if (GET_CODE (addr1) == PLUS)
13317 /* If not a REG, return zero. */
13318 if (GET_CODE (XEXP (addr1, 0)) != REG)
13322 reg1 = REGNO (XEXP (addr1, 0));
13323 /* The offset must be constant! */
13324 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13326 offset1 = INTVAL (XEXP (addr1, 1));
13329 else if (GET_CODE (addr1) != REG)
13333 reg1 = REGNO (addr1);
13334 /* This was a simple (mem (reg)) expression. Offset is 0. */
13338 /* And now for the second addr. */
13339 if (GET_CODE (addr2) == PLUS)
13341 /* If not a REG, return zero. */
13342 if (GET_CODE (XEXP (addr2, 0)) != REG)
13346 reg2 = REGNO (XEXP (addr2, 0));
13347 /* The offset must be constant. */
13348 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13350 offset2 = INTVAL (XEXP (addr2, 1));
13353 else if (GET_CODE (addr2) != REG)
13357 reg2 = REGNO (addr2);
13358 /* This was a simple (mem (reg)) expression. Offset is 0. */
13362 /* Both of these must have the same base register. */
13366 /* The offset for the second addr must be 8 more than the first addr. */
13367 if (offset2 != offset1 + 8)
13370 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13377 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13379 static bool eliminated = false;
13382 if (mode != SDmode)
13383 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13386 rtx mem = cfun->machine->sdmode_stack_slot;
13387 gcc_assert (mem != NULL_RTX);
13391 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13392 cfun->machine->sdmode_stack_slot = mem;
13398 if (TARGET_DEBUG_ADDR)
13400 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13401 GET_MODE_NAME (mode));
13403 fprintf (stderr, "\tNULL_RTX\n");
13412 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13414 /* Don't walk into types. */
13415 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13417 *walk_subtrees = 0;
13421 switch (TREE_CODE (*tp))
13430 case VIEW_CONVERT_EXPR:
13431 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13441 enum reload_reg_type {
13443 VECTOR_REGISTER_TYPE,
13444 OTHER_REGISTER_TYPE
13447 static enum reload_reg_type
13448 rs6000_reload_register_type (enum reg_class rclass)
13454 return GPR_REGISTER_TYPE;
13459 return VECTOR_REGISTER_TYPE;
13462 return OTHER_REGISTER_TYPE;
13466 /* Inform reload about cases where moving X with a mode MODE to a register in
13467 RCLASS requires an extra scratch or immediate register. Return the class
13468 needed for the immediate register.
13470 For VSX and Altivec, we may need a register to convert sp+offset into
13473 For misaligned 64-bit gpr loads and stores we need a register to
13474 convert an offset address to indirect. */
13477 rs6000_secondary_reload (bool in_p,
13479 reg_class_t rclass_i,
13480 enum machine_mode mode,
13481 secondary_reload_info *sri)
13483 enum reg_class rclass = (enum reg_class) rclass_i;
13484 reg_class_t ret = ALL_REGS;
13485 enum insn_code icode;
13486 bool default_p = false;
13488 sri->icode = CODE_FOR_nothing;
13490 /* Convert vector loads and stores into gprs to use an additional base
13492 icode = rs6000_vector_reload[mode][in_p != false];
13493 if (icode != CODE_FOR_nothing)
13496 sri->icode = CODE_FOR_nothing;
13497 sri->extra_cost = 0;
13499 if (GET_CODE (x) == MEM)
13501 rtx addr = XEXP (x, 0);
13503 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13504 an extra register in that case, but it would need an extra
13505 register if the addressing is reg+reg or (reg+reg)&(-16). */
13506 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13508 if (!legitimate_indirect_address_p (addr, false)
13509 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13511 sri->icode = icode;
13512 /* account for splitting the loads, and converting the
13513 address from reg+reg to reg. */
13514 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13515 + ((GET_CODE (addr) == AND) ? 1 : 0));
13518 /* Loads to and stores from vector registers can only do reg+reg
13519 addressing. Altivec registers can also do (reg+reg)&(-16). */
13520 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13521 || rclass == FLOAT_REGS || rclass == NO_REGS)
13523 if (!VECTOR_MEM_ALTIVEC_P (mode)
13524 && GET_CODE (addr) == AND
13525 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13526 && INTVAL (XEXP (addr, 1)) == -16
13527 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13528 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13530 sri->icode = icode;
13531 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13534 else if (!legitimate_indirect_address_p (addr, false)
13535 && (rclass == NO_REGS
13536 || !legitimate_indexed_address_p (addr, false)))
13538 sri->icode = icode;
13539 sri->extra_cost = 1;
13542 icode = CODE_FOR_nothing;
13544 /* Any other loads, including to pseudo registers which haven't been
13545 assigned to a register yet, default to require a scratch
13549 sri->icode = icode;
13550 sri->extra_cost = 2;
13553 else if (REG_P (x))
13555 int regno = true_regnum (x);
13557 icode = CODE_FOR_nothing;
13558 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13562 enum reg_class xclass = REGNO_REG_CLASS (regno);
13563 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13564 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13566 /* If memory is needed, use default_secondary_reload to create the
13568 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13577 else if (TARGET_POWERPC64
13578 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13580 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13582 rtx addr = XEXP (x, 0);
13584 if (GET_CODE (addr) == PRE_MODIFY)
13585 addr = XEXP (addr, 1);
13586 else if (GET_CODE (addr) == LO_SUM
13587 && GET_CODE (XEXP (addr, 0)) == REG
13588 && GET_CODE (XEXP (addr, 1)) == CONST)
13589 addr = XEXP (XEXP (addr, 1), 0);
13591 if (GET_CODE (addr) == PLUS
13592 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13593 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
13596 sri->icode = CODE_FOR_reload_di_load;
13598 sri->icode = CODE_FOR_reload_di_store;
13599 sri->extra_cost = 2;
13609 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13611 gcc_assert (ret != ALL_REGS);
13613 if (TARGET_DEBUG_ADDR)
13616 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13618 reg_class_names[ret],
13619 in_p ? "true" : "false",
13620 reg_class_names[rclass],
13621 GET_MODE_NAME (mode));
13624 fprintf (stderr, ", default secondary reload");
13626 if (sri->icode != CODE_FOR_nothing)
13627 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13628 insn_data[sri->icode].name, sri->extra_cost);
13630 fprintf (stderr, "\n");
13638 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13639 to SP+reg addressing. */
13642 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13644 int regno = true_regnum (reg);
13645 enum machine_mode mode = GET_MODE (reg);
13646 enum reg_class rclass;
13648 rtx and_op2 = NULL_RTX;
13651 rtx scratch_or_premodify = scratch;
13655 if (TARGET_DEBUG_ADDR)
13657 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13658 store_p ? "store" : "load");
13659 fprintf (stderr, "reg:\n");
13661 fprintf (stderr, "mem:\n");
13663 fprintf (stderr, "scratch:\n");
13664 debug_rtx (scratch);
13667 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13668 gcc_assert (GET_CODE (mem) == MEM);
13669 rclass = REGNO_REG_CLASS (regno);
13670 addr = XEXP (mem, 0);
13674 /* GPRs can handle reg + small constant, all other addresses need to use
13675 the scratch register. */
13678 if (GET_CODE (addr) == AND)
13680 and_op2 = XEXP (addr, 1);
13681 addr = XEXP (addr, 0);
13684 if (GET_CODE (addr) == PRE_MODIFY)
13686 scratch_or_premodify = XEXP (addr, 0);
13687 gcc_assert (REG_P (scratch_or_premodify));
13688 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13689 addr = XEXP (addr, 1);
13692 if (GET_CODE (addr) == PLUS
13693 && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
13694 || and_op2 != NULL_RTX))
13696 addr_op1 = XEXP (addr, 0);
13697 addr_op2 = XEXP (addr, 1);
13698 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13700 if (!REG_P (addr_op2)
13701 && (GET_CODE (addr_op2) != CONST_INT
13702 || !satisfies_constraint_I (addr_op2)))
13704 if (TARGET_DEBUG_ADDR)
13707 "\nMove plus addr to register %s, mode = %s: ",
13708 rs6000_reg_names[REGNO (scratch)],
13709 GET_MODE_NAME (mode));
13710 debug_rtx (addr_op2);
13712 rs6000_emit_move (scratch, addr_op2, Pmode);
13713 addr_op2 = scratch;
13716 emit_insn (gen_rtx_SET (VOIDmode,
13717 scratch_or_premodify,
13718 gen_rtx_PLUS (Pmode,
13722 addr = scratch_or_premodify;
13723 scratch_or_premodify = scratch;
13725 else if (!legitimate_indirect_address_p (addr, false)
13726 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13728 if (TARGET_DEBUG_ADDR)
13730 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13731 rs6000_reg_names[REGNO (scratch_or_premodify)],
13732 GET_MODE_NAME (mode));
13735 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13736 addr = scratch_or_premodify;
13737 scratch_or_premodify = scratch;
13741 /* Float/Altivec registers can only handle reg+reg addressing. Move
13742 other addresses into a scratch register. */
13747 /* With float regs, we need to handle the AND ourselves, since we can't
13748 use the Altivec instruction with an implicit AND -16. Allow scalar
13749 loads to float registers to use reg+offset even if VSX. */
13750 if (GET_CODE (addr) == AND
13751 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13752 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13753 || INTVAL (XEXP (addr, 1)) != -16
13754 || !VECTOR_MEM_ALTIVEC_P (mode)))
13756 and_op2 = XEXP (addr, 1);
13757 addr = XEXP (addr, 0);
13760 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13761 as the address later. */
13762 if (GET_CODE (addr) == PRE_MODIFY
13763 && (!VECTOR_MEM_VSX_P (mode)
13764 || and_op2 != NULL_RTX
13765 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
13767 scratch_or_premodify = XEXP (addr, 0);
13768 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
13770 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13771 addr = XEXP (addr, 1);
13774 if (legitimate_indirect_address_p (addr, false) /* reg */
13775 || legitimate_indexed_address_p (addr, false) /* reg+reg */
13776 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
13777 || (GET_CODE (addr) == AND /* Altivec memory */
13778 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13779 && INTVAL (XEXP (addr, 1)) == -16
13780 && VECTOR_MEM_ALTIVEC_P (mode))
13781 || (rclass == FLOAT_REGS /* legacy float mem */
13782 && GET_MODE_SIZE (mode) == 8
13783 && and_op2 == NULL_RTX
13784 && scratch_or_premodify == scratch
13785 && rs6000_legitimate_offset_address_p (mode, addr, false)))
13788 else if (GET_CODE (addr) == PLUS)
13790 addr_op1 = XEXP (addr, 0);
13791 addr_op2 = XEXP (addr, 1);
13792 gcc_assert (REG_P (addr_op1));
13794 if (TARGET_DEBUG_ADDR)
13796 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
13797 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13798 debug_rtx (addr_op2);
13800 rs6000_emit_move (scratch, addr_op2, Pmode);
13801 emit_insn (gen_rtx_SET (VOIDmode,
13802 scratch_or_premodify,
13803 gen_rtx_PLUS (Pmode,
13806 addr = scratch_or_premodify;
13807 scratch_or_premodify = scratch;
13810 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
13811 || GET_CODE (addr) == CONST_INT || REG_P (addr))
13813 if (TARGET_DEBUG_ADDR)
13815 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13816 rs6000_reg_names[REGNO (scratch_or_premodify)],
13817 GET_MODE_NAME (mode));
13821 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13822 addr = scratch_or_premodify;
13823 scratch_or_premodify = scratch;
13827 gcc_unreachable ();
13832 gcc_unreachable ();
13835 /* If the original address involved a pre-modify that we couldn't use the VSX
13836 memory instruction with update, and we haven't taken care of already,
13837 store the address in the pre-modify register and use that as the
13839 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
13841 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
13842 addr = scratch_or_premodify;
13845 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
13846 memory instruction, recreate the AND now, including the clobber which is
13847 generated by the general ANDSI3/ANDDI3 patterns for the
13848 andi. instruction. */
13849 if (and_op2 != NULL_RTX)
13851 if (! legitimate_indirect_address_p (addr, false))
13853 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
13857 if (TARGET_DEBUG_ADDR)
13859 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
13860 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13861 debug_rtx (and_op2);
13864 and_rtx = gen_rtx_SET (VOIDmode,
13866 gen_rtx_AND (Pmode,
13870 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
13871 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13872 gen_rtvec (2, and_rtx, cc_clobber)));
13876 /* Adjust the address if it changed. */
13877 if (addr != XEXP (mem, 0))
13879 mem = change_address (mem, mode, addr);
13880 if (TARGET_DEBUG_ADDR)
13881 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
13884 /* Now create the move. */
13886 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
13888 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
13893 /* Convert reloads involving 64-bit gprs and misaligned offset
13894 addressing to use indirect addressing. */
13897 rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p)
13899 int regno = true_regnum (reg);
13900 enum reg_class rclass;
13902 rtx scratch_or_premodify = scratch;
13904 if (TARGET_DEBUG_ADDR)
13906 fprintf (stderr, "\nrs6000_secondary_reload_ppc64, type = %s\n",
13907 store_p ? "store" : "load");
13908 fprintf (stderr, "reg:\n");
13910 fprintf (stderr, "mem:\n");
13912 fprintf (stderr, "scratch:\n");
13913 debug_rtx (scratch);
13916 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13917 gcc_assert (GET_CODE (mem) == MEM);
13918 rclass = REGNO_REG_CLASS (regno);
13919 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
13920 addr = XEXP (mem, 0);
13922 if (GET_CODE (addr) == PRE_MODIFY)
13924 scratch_or_premodify = XEXP (addr, 0);
13925 gcc_assert (REG_P (scratch_or_premodify));
13926 addr = XEXP (addr, 1);
13928 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
13930 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13932 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
13934 /* Now create the move. */
13936 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
13938 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
13943 /* Allocate a 64-bit stack slot to be used for copying SDmode
13944 values through if this function has any SDmode references. */
13947 rs6000_alloc_sdmode_stack_slot (void)
13951 gimple_stmt_iterator gsi;
13953 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
13956 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
13958 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
13961 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
13962 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
13968 /* Check for any SDmode parameters of the function. */
13969 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
13971 if (TREE_TYPE (t) == error_mark_node)
13974 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
13975 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
13977 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
13978 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
13986 rs6000_instantiate_decls (void)
13988 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
13989 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
13992 /* Given an rtx X being reloaded into a reg required to be
13993 in class CLASS, return the class of reg to actually use.
13994 In general this is just CLASS; but on some machines
13995 in some cases it is preferable to use a more restrictive class.
13997 On the RS/6000, we have to return NO_REGS when we want to reload a
13998 floating-point CONST_DOUBLE to force it to be copied to memory.
14000 We also don't want to reload integer values into floating-point
14001 registers if we can at all help it. In fact, this can
14002 cause reload to die, if it tries to generate a reload of CTR
14003 into a FP register and discovers it doesn't have the memory location
14006 ??? Would it be a good idea to have reload do the converse, that is
14007 try to reload floating modes into FP registers if possible?
14010 static enum reg_class
14011 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14013 enum machine_mode mode = GET_MODE (x);
14015 if (VECTOR_UNIT_VSX_P (mode)
14016 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14019 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14020 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14021 && easy_vector_constant (x, mode))
14022 return ALTIVEC_REGS;
14024 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14027 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14028 return GENERAL_REGS;
14030 /* For VSX, prefer the traditional registers for 64-bit values because we can
14031 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14032 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14033 prefer Altivec loads.. */
14034 if (rclass == VSX_REGS)
14036 if (GET_MODE_SIZE (mode) <= 8)
14039 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14040 return ALTIVEC_REGS;
14048 /* Debug version of rs6000_preferred_reload_class. */
14049 static enum reg_class
14050 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14052 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14055 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14057 reg_class_names[ret], reg_class_names[rclass],
14058 GET_MODE_NAME (GET_MODE (x)));
14064 /* If we are copying between FP or AltiVec registers and anything else, we need
14065 a memory location. The exception is when we are targeting ppc64 and the
14066 move to/from fpr to gpr instructions are available. Also, under VSX, you
14067 can copy vector registers from the FP register set to the Altivec register
14068 set and vice versa. */
14071 rs6000_secondary_memory_needed (enum reg_class class1,
14072 enum reg_class class2,
14073 enum machine_mode mode)
14075 if (class1 == class2)
14078 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14079 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14080 between these classes. But we need memory for other things that can go in
14081 FLOAT_REGS like SFmode. */
14083 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14084 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14085 || class1 == FLOAT_REGS))
14086 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14087 && class2 != FLOAT_REGS);
14089 if (class1 == VSX_REGS || class2 == VSX_REGS)
14092 if (class1 == FLOAT_REGS
14093 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14094 || ((mode != DFmode)
14095 && (mode != DDmode)
14096 && (mode != DImode))))
14099 if (class2 == FLOAT_REGS
14100 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14101 || ((mode != DFmode)
14102 && (mode != DDmode)
14103 && (mode != DImode))))
14106 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14112 /* Debug version of rs6000_secondary_memory_needed. */
14114 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14115 enum reg_class class2,
14116 enum machine_mode mode)
14118 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14121 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14122 "class2 = %s, mode = %s\n",
14123 ret ? "true" : "false", reg_class_names[class1],
14124 reg_class_names[class2], GET_MODE_NAME (mode));
14129 /* Return the register class of a scratch register needed to copy IN into
14130 or out of a register in RCLASS in MODE. If it can be done directly,
14131 NO_REGS is returned. */
14133 static enum reg_class
14134 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14139 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14141 && MACHOPIC_INDIRECT
14145 /* We cannot copy a symbolic operand directly into anything
14146 other than BASE_REGS for TARGET_ELF. So indicate that a
14147 register from BASE_REGS is needed as an intermediate
14150 On Darwin, pic addresses require a load from memory, which
14151 needs a base register. */
14152 if (rclass != BASE_REGS
14153 && (GET_CODE (in) == SYMBOL_REF
14154 || GET_CODE (in) == HIGH
14155 || GET_CODE (in) == LABEL_REF
14156 || GET_CODE (in) == CONST))
14160 if (GET_CODE (in) == REG)
14162 regno = REGNO (in);
14163 if (regno >= FIRST_PSEUDO_REGISTER)
14165 regno = true_regnum (in);
14166 if (regno >= FIRST_PSEUDO_REGISTER)
14170 else if (GET_CODE (in) == SUBREG)
14172 regno = true_regnum (in);
14173 if (regno >= FIRST_PSEUDO_REGISTER)
14179 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14181 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14182 || (regno >= 0 && INT_REGNO_P (regno)))
14185 /* Constants, memory, and FP registers can go into FP registers. */
14186 if ((regno == -1 || FP_REGNO_P (regno))
14187 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14188 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14190 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14193 && (regno == -1 || VSX_REGNO_P (regno))
14194 && VSX_REG_CLASS_P (rclass))
14197 /* Memory, and AltiVec registers can go into AltiVec registers. */
14198 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14199 && rclass == ALTIVEC_REGS)
14202 /* We can copy among the CR registers. */
14203 if ((rclass == CR_REGS || rclass == CR0_REGS)
14204 && regno >= 0 && CR_REGNO_P (regno))
14207 /* Otherwise, we need GENERAL_REGS. */
14208 return GENERAL_REGS;
14211 /* Debug version of rs6000_secondary_reload_class. */
14212 static enum reg_class
14213 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14214 enum machine_mode mode, rtx in)
14216 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14218 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14219 "mode = %s, input rtx:\n",
14220 reg_class_names[ret], reg_class_names[rclass],
14221 GET_MODE_NAME (mode));
14227 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14230 rs6000_cannot_change_mode_class (enum machine_mode from,
14231 enum machine_mode to,
14232 enum reg_class rclass)
14234 unsigned from_size = GET_MODE_SIZE (from);
14235 unsigned to_size = GET_MODE_SIZE (to);
14237 if (from_size != to_size)
14239 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14240 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14241 && reg_classes_intersect_p (xclass, rclass));
14244 if (TARGET_E500_DOUBLE
14245 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14246 || (((to) == TFmode) + ((from) == TFmode)) == 1
14247 || (((to) == DDmode) + ((from) == DDmode)) == 1
14248 || (((to) == TDmode) + ((from) == TDmode)) == 1
14249 || (((to) == DImode) + ((from) == DImode)) == 1))
14252 /* Since the VSX register set includes traditional floating point registers
14253 and altivec registers, just check for the size being different instead of
14254 trying to check whether the modes are vector modes. Otherwise it won't
14255 allow say DF and DI to change classes. */
14256 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14257 return (from_size != 8 && from_size != 16);
14259 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14260 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14263 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14264 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14270 /* Debug version of rs6000_cannot_change_mode_class. */
14272 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14273 enum machine_mode to,
14274 enum reg_class rclass)
14276 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14279 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14280 "to = %s, rclass = %s\n",
14281 ret ? "true" : "false",
14282 GET_MODE_NAME (from), GET_MODE_NAME (to),
14283 reg_class_names[rclass]);
14288 /* Given a comparison operation, return the bit number in CCR to test. We
14289 know this is a valid comparison.
14291 SCC_P is 1 if this is for an scc. That means that %D will have been
14292 used instead of %C, so the bits will be in different places.
14294 Return -1 if OP isn't a valid comparison for some reason. */
14297 ccr_bit (rtx op, int scc_p)
14299 enum rtx_code code = GET_CODE (op);
14300 enum machine_mode cc_mode;
14305 if (!COMPARISON_P (op))
14308 reg = XEXP (op, 0);
14310 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14312 cc_mode = GET_MODE (reg);
14313 cc_regnum = REGNO (reg);
14314 base_bit = 4 * (cc_regnum - CR0_REGNO);
14316 validate_condition_mode (code, cc_mode);
14318 /* When generating a sCOND operation, only positive conditions are
14321 || code == EQ || code == GT || code == LT || code == UNORDERED
14322 || code == GTU || code == LTU);
14327 return scc_p ? base_bit + 3 : base_bit + 2;
14329 return base_bit + 2;
14330 case GT: case GTU: case UNLE:
14331 return base_bit + 1;
14332 case LT: case LTU: case UNGE:
14334 case ORDERED: case UNORDERED:
14335 return base_bit + 3;
14338 /* If scc, we will have done a cror to put the bit in the
14339 unordered position. So test that bit. For integer, this is ! LT
14340 unless this is an scc insn. */
14341 return scc_p ? base_bit + 3 : base_bit;
14344 return scc_p ? base_bit + 3 : base_bit + 1;
14347 gcc_unreachable ();
14351 /* Return the GOT register. */
14354 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14356 /* The second flow pass currently (June 1999) can't update
14357 regs_ever_live without disturbing other parts of the compiler, so
14358 update it here to make the prolog/epilogue code happy. */
14359 if (!can_create_pseudo_p ()
14360 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14361 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14363 crtl->uses_pic_offset_table = 1;
14365 return pic_offset_table_rtx;
14368 static rs6000_stack_t stack_info;
14370 /* Function to init struct machine_function.
14371 This will be called, via a pointer variable,
14372 from push_function_context. */
14374 static struct machine_function *
14375 rs6000_init_machine_status (void)
14377 stack_info.reload_completed = 0;
14378 return ggc_alloc_cleared_machine_function ();
14381 /* These macros test for integers and extract the low-order bits. */
14383 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14384 && GET_MODE (X) == VOIDmode)
14386 #define INT_LOWPART(X) \
14387 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14390 extract_MB (rtx op)
14393 unsigned long val = INT_LOWPART (op);
14395 /* If the high bit is zero, the value is the first 1 bit we find
14397 if ((val & 0x80000000) == 0)
14399 gcc_assert (val & 0xffffffff);
14402 while (((val <<= 1) & 0x80000000) == 0)
14407 /* If the high bit is set and the low bit is not, or the mask is all
14408 1's, the value is zero. */
14409 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14412 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14415 while (((val >>= 1) & 1) != 0)
14422 extract_ME (rtx op)
14425 unsigned long val = INT_LOWPART (op);
14427 /* If the low bit is zero, the value is the first 1 bit we find from
14429 if ((val & 1) == 0)
14431 gcc_assert (val & 0xffffffff);
14434 while (((val >>= 1) & 1) == 0)
14440 /* If the low bit is set and the high bit is not, or the mask is all
14441 1's, the value is 31. */
14442 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14445 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14448 while (((val <<= 1) & 0x80000000) != 0)
14454 /* Locate some local-dynamic symbol still in use by this function
14455 so that we can print its name in some tls_ld pattern. */
14457 static const char *
14458 rs6000_get_some_local_dynamic_name (void)
14462 if (cfun->machine->some_ld_name)
14463 return cfun->machine->some_ld_name;
14465 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14467 && for_each_rtx (&PATTERN (insn),
14468 rs6000_get_some_local_dynamic_name_1, 0))
14469 return cfun->machine->some_ld_name;
14471 gcc_unreachable ();
14474 /* Helper function for rs6000_get_some_local_dynamic_name. */
14477 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14481 if (GET_CODE (x) == SYMBOL_REF)
14483 const char *str = XSTR (x, 0);
14484 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14486 cfun->machine->some_ld_name = str;
14494 /* Write out a function code label. */
14497 rs6000_output_function_entry (FILE *file, const char *fname)
14499 if (fname[0] != '.')
14501 switch (DEFAULT_ABI)
14504 gcc_unreachable ();
14510 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14519 RS6000_OUTPUT_BASENAME (file, fname);
14522 /* Print an operand. Recognize special options, documented below. */
14525 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14526 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14528 #define SMALL_DATA_RELOC "sda21"
14529 #define SMALL_DATA_REG 0
14533 print_operand (FILE *file, rtx x, int code)
14536 unsigned HOST_WIDE_INT uval;
14541 /* Write out an instruction after the call which may be replaced
14542 with glue code by the loader. This depends on the AIX version. */
14543 asm_fprintf (file, RS6000_CALL_GLUE);
14546 /* %a is output_address. */
14549 /* If X is a constant integer whose low-order 5 bits are zero,
14550 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14551 in the AIX assembler where "sri" with a zero shift count
14552 writes a trash instruction. */
14553 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
14560 /* If constant, low-order 16 bits of constant, unsigned.
14561 Otherwise, write normally. */
14563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14565 print_operand (file, x, 0);
14569 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14570 for 64-bit mask direction. */
14571 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14574 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14578 /* X is a CR register. Print the number of the GT bit of the CR. */
14579 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14580 output_operand_lossage ("invalid %%c value");
14582 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
14586 /* Like 'J' but get to the GT bit only. */
14587 gcc_assert (REG_P (x));
14589 /* Bit 1 is GT bit. */
14590 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14592 /* Add one for shift count in rlinm for scc. */
14593 fprintf (file, "%d", i + 1);
14597 /* X is a CR register. Print the number of the EQ bit of the CR */
14598 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14599 output_operand_lossage ("invalid %%E value");
14601 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14605 /* X is a CR register. Print the shift count needed to move it
14606 to the high-order four bits. */
14607 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14608 output_operand_lossage ("invalid %%f value");
14610 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14614 /* Similar, but print the count for the rotate in the opposite
14616 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14617 output_operand_lossage ("invalid %%F value");
14619 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14623 /* X is a constant integer. If it is negative, print "m",
14624 otherwise print "z". This is to make an aze or ame insn. */
14625 if (GET_CODE (x) != CONST_INT)
14626 output_operand_lossage ("invalid %%G value");
14627 else if (INTVAL (x) >= 0)
14634 /* If constant, output low-order five bits. Otherwise, write
14637 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14639 print_operand (file, x, 0);
14643 /* If constant, output low-order six bits. Otherwise, write
14646 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14648 print_operand (file, x, 0);
14652 /* Print `i' if this is a constant, else nothing. */
14658 /* Write the bit number in CCR for jump. */
14659 i = ccr_bit (x, 0);
14661 output_operand_lossage ("invalid %%j code");
14663 fprintf (file, "%d", i);
14667 /* Similar, but add one for shift count in rlinm for scc and pass
14668 scc flag to `ccr_bit'. */
14669 i = ccr_bit (x, 1);
14671 output_operand_lossage ("invalid %%J code");
14673 /* If we want bit 31, write a shift count of zero, not 32. */
14674 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14678 /* X must be a constant. Write the 1's complement of the
14681 output_operand_lossage ("invalid %%k value");
14683 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14687 /* X must be a symbolic constant on ELF. Write an
14688 expression suitable for an 'addi' that adds in the low 16
14689 bits of the MEM. */
14690 if (GET_CODE (x) == CONST)
14692 if (GET_CODE (XEXP (x, 0)) != PLUS
14693 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14694 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14695 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14696 output_operand_lossage ("invalid %%K value");
14698 print_operand_address (file, x);
14699 fputs ("@l", file);
14702 /* %l is output_asm_label. */
14705 /* Write second word of DImode or DFmode reference. Works on register
14706 or non-indexed memory only. */
14708 fputs (reg_names[REGNO (x) + 1], file);
14709 else if (MEM_P (x))
14711 /* Handle possible auto-increment. Since it is pre-increment and
14712 we have already done it, we can just use an offset of word. */
14713 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14714 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14715 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14717 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14718 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14721 output_address (XEXP (adjust_address_nv (x, SImode,
14725 if (small_data_operand (x, GET_MODE (x)))
14726 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14727 reg_names[SMALL_DATA_REG]);
14732 /* MB value for a mask operand. */
14733 if (! mask_operand (x, SImode))
14734 output_operand_lossage ("invalid %%m value");
14736 fprintf (file, "%d", extract_MB (x));
14740 /* ME value for a mask operand. */
14741 if (! mask_operand (x, SImode))
14742 output_operand_lossage ("invalid %%M value");
14744 fprintf (file, "%d", extract_ME (x));
14747 /* %n outputs the negative of its operand. */
14750 /* Write the number of elements in the vector times 4. */
14751 if (GET_CODE (x) != PARALLEL)
14752 output_operand_lossage ("invalid %%N value");
14754 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14758 /* Similar, but subtract 1 first. */
14759 if (GET_CODE (x) != PARALLEL)
14760 output_operand_lossage ("invalid %%O value");
14762 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14766 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14768 || INT_LOWPART (x) < 0
14769 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14770 output_operand_lossage ("invalid %%p value");
14772 fprintf (file, "%d", i);
14776 /* The operand must be an indirect memory reference. The result
14777 is the register name. */
14778 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14779 || REGNO (XEXP (x, 0)) >= 32)
14780 output_operand_lossage ("invalid %%P value");
14782 fputs (reg_names[REGNO (XEXP (x, 0))], file);
14786 /* This outputs the logical code corresponding to a boolean
14787 expression. The expression may have one or both operands
14788 negated (if one, only the first one). For condition register
14789 logical operations, it will also treat the negated
14790 CR codes as NOTs, but not handle NOTs of them. */
14792 const char *const *t = 0;
14794 enum rtx_code code = GET_CODE (x);
14795 static const char * const tbl[3][3] = {
14796 { "and", "andc", "nor" },
14797 { "or", "orc", "nand" },
14798 { "xor", "eqv", "xor" } };
14802 else if (code == IOR)
14804 else if (code == XOR)
14807 output_operand_lossage ("invalid %%q value");
14809 if (GET_CODE (XEXP (x, 0)) != NOT)
14813 if (GET_CODE (XEXP (x, 1)) == NOT)
14831 /* X is a CR register. Print the mask for `mtcrf'. */
14832 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14833 output_operand_lossage ("invalid %%R value");
14835 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
14839 /* Low 5 bits of 32 - value */
14841 output_operand_lossage ("invalid %%s value");
14843 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
14847 /* PowerPC64 mask position. All 0's is excluded.
14848 CONST_INT 32-bit mask is considered sign-extended so any
14849 transition must occur within the CONST_INT, not on the boundary. */
14850 if (! mask64_operand (x, DImode))
14851 output_operand_lossage ("invalid %%S value");
14853 uval = INT_LOWPART (x);
14855 if (uval & 1) /* Clear Left */
14857 #if HOST_BITS_PER_WIDE_INT > 64
14858 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14862 else /* Clear Right */
14865 #if HOST_BITS_PER_WIDE_INT > 64
14866 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14872 gcc_assert (i >= 0);
14873 fprintf (file, "%d", i);
14877 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
14878 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
14880 /* Bit 3 is OV bit. */
14881 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
14883 /* If we want bit 31, write a shift count of zero, not 32. */
14884 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14888 /* Print the symbolic name of a branch target register. */
14889 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
14890 && REGNO (x) != CTR_REGNO))
14891 output_operand_lossage ("invalid %%T value");
14892 else if (REGNO (x) == LR_REGNO)
14893 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
14895 fputs ("ctr", file);
14899 /* High-order 16 bits of constant for use in unsigned operand. */
14901 output_operand_lossage ("invalid %%u value");
14903 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
14904 (INT_LOWPART (x) >> 16) & 0xffff);
14908 /* High-order 16 bits of constant for use in signed operand. */
14910 output_operand_lossage ("invalid %%v value");
14912 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
14913 (INT_LOWPART (x) >> 16) & 0xffff);
14917 /* Print `u' if this has an auto-increment or auto-decrement. */
14919 && (GET_CODE (XEXP (x, 0)) == PRE_INC
14920 || GET_CODE (XEXP (x, 0)) == PRE_DEC
14921 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
14926 /* Print the trap code for this operand. */
14927 switch (GET_CODE (x))
14930 fputs ("eq", file); /* 4 */
14933 fputs ("ne", file); /* 24 */
14936 fputs ("lt", file); /* 16 */
14939 fputs ("le", file); /* 20 */
14942 fputs ("gt", file); /* 8 */
14945 fputs ("ge", file); /* 12 */
14948 fputs ("llt", file); /* 2 */
14951 fputs ("lle", file); /* 6 */
14954 fputs ("lgt", file); /* 1 */
14957 fputs ("lge", file); /* 5 */
14960 gcc_unreachable ();
14965 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
14968 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
14969 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
14971 print_operand (file, x, 0);
14975 /* MB value for a PowerPC64 rldic operand. */
14976 i = clz_hwi (GET_CODE (x) == CONST_INT
14977 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
14979 #if HOST_BITS_PER_WIDE_INT == 32
14980 if (GET_CODE (x) == CONST_INT && i > 0)
14981 i += 32; /* zero-extend high-part was all 0's */
14982 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
14983 i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32;
14986 fprintf (file, "%d", i);
14990 /* X is a FPR or Altivec register used in a VSX context. */
14991 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
14992 output_operand_lossage ("invalid %%x value");
14995 int reg = REGNO (x);
14996 int vsx_reg = (FP_REGNO_P (reg)
14998 : reg - FIRST_ALTIVEC_REGNO + 32);
15000 #ifdef TARGET_REGNAMES
15001 if (TARGET_REGNAMES)
15002 fprintf (file, "%%vs%d", vsx_reg);
15005 fprintf (file, "%d", vsx_reg);
15011 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15012 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15013 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15018 /* Like 'L', for third word of TImode */
15020 fputs (reg_names[REGNO (x) + 2], file);
15021 else if (MEM_P (x))
15023 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15024 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15025 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15026 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15027 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15029 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15030 if (small_data_operand (x, GET_MODE (x)))
15031 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15032 reg_names[SMALL_DATA_REG]);
15037 /* X is a SYMBOL_REF. Write out the name preceded by a
15038 period and without any trailing data in brackets. Used for function
15039 names. If we are configured for System V (or the embedded ABI) on
15040 the PowerPC, do not emit the period, since those systems do not use
15041 TOCs and the like. */
15042 gcc_assert (GET_CODE (x) == SYMBOL_REF);
15044 /* Mark the decl as referenced so that cgraph will output the
15046 if (SYMBOL_REF_DECL (x))
15047 mark_decl_referenced (SYMBOL_REF_DECL (x));
15049 /* For macho, check to see if we need a stub. */
15052 const char *name = XSTR (x, 0);
15054 if (darwin_emit_branch_islands
15055 && MACHOPIC_INDIRECT
15056 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15057 name = machopic_indirection_name (x, /*stub_p=*/true);
15059 assemble_name (file, name);
15061 else if (!DOT_SYMBOLS)
15062 assemble_name (file, XSTR (x, 0));
15064 rs6000_output_function_entry (file, XSTR (x, 0));
15068 /* Like 'L', for last word of TImode. */
15070 fputs (reg_names[REGNO (x) + 3], file);
15071 else if (MEM_P (x))
15073 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15074 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15075 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15076 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15077 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15079 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15080 if (small_data_operand (x, GET_MODE (x)))
15081 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15082 reg_names[SMALL_DATA_REG]);
15086 /* Print AltiVec or SPE memory operand. */
15091 gcc_assert (MEM_P (x));
15095 /* Ugly hack because %y is overloaded. */
15096 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15097 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15098 || GET_MODE (x) == TFmode
15099 || GET_MODE (x) == TImode))
15101 /* Handle [reg]. */
15104 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15107 /* Handle [reg+UIMM]. */
15108 else if (GET_CODE (tmp) == PLUS &&
15109 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15113 gcc_assert (REG_P (XEXP (tmp, 0)));
15115 x = INTVAL (XEXP (tmp, 1));
15116 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15120 /* Fall through. Must be [reg+reg]. */
15122 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15123 && GET_CODE (tmp) == AND
15124 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15125 && INTVAL (XEXP (tmp, 1)) == -16)
15126 tmp = XEXP (tmp, 0);
15127 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15128 && GET_CODE (tmp) == PRE_MODIFY)
15129 tmp = XEXP (tmp, 1);
15131 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15134 if (!GET_CODE (tmp) == PLUS
15135 || !REG_P (XEXP (tmp, 0))
15136 || !REG_P (XEXP (tmp, 1)))
15138 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15142 if (REGNO (XEXP (tmp, 0)) == 0)
15143 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15144 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15146 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15147 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15154 fprintf (file, "%s", reg_names[REGNO (x)]);
15155 else if (MEM_P (x))
15157 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15158 know the width from the mode. */
15159 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15160 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15161 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15162 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15163 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15164 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15165 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15166 output_address (XEXP (XEXP (x, 0), 1));
15168 output_address (XEXP (x, 0));
15172 if (toc_relative_expr_p (x, false))
15173 /* This hack along with a corresponding hack in
15174 rs6000_output_addr_const_extra arranges to output addends
15175 where the assembler expects to find them. eg.
15176 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15177 without this hack would be output as "x@toc+4". We
15179 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15181 output_addr_const (file, x);
15186 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15190 output_operand_lossage ("invalid %%xn code");
15194 /* Print the address of an operand. */
15197 print_operand_address (FILE *file, rtx x)
15200 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15201 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15202 || GET_CODE (x) == LABEL_REF)
15204 output_addr_const (file, x);
15205 if (small_data_operand (x, GET_MODE (x)))
15206 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15207 reg_names[SMALL_DATA_REG]);
15209 gcc_assert (!TARGET_TOC);
15211 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15212 && REG_P (XEXP (x, 1)))
15214 if (REGNO (XEXP (x, 0)) == 0)
15215 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15216 reg_names[ REGNO (XEXP (x, 0)) ]);
15218 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15219 reg_names[ REGNO (XEXP (x, 1)) ]);
15221 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15222 && GET_CODE (XEXP (x, 1)) == CONST_INT)
15223 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15224 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15226 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15227 && CONSTANT_P (XEXP (x, 1)))
15229 fprintf (file, "lo16(");
15230 output_addr_const (file, XEXP (x, 1));
15231 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15235 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15236 && CONSTANT_P (XEXP (x, 1)))
15238 output_addr_const (file, XEXP (x, 1));
15239 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15242 else if (toc_relative_expr_p (x, false))
15244 /* This hack along with a corresponding hack in
15245 rs6000_output_addr_const_extra arranges to output addends
15246 where the assembler expects to find them. eg.
15248 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15249 without this hack would be output as "x@toc+8@l(9)". We
15250 want "x+8@toc@l(9)". */
15251 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15252 if (GET_CODE (x) == LO_SUM)
15253 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
15255 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base, 0, 1))]);
15258 gcc_unreachable ();
15261 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15264 rs6000_output_addr_const_extra (FILE *file, rtx x)
15266 if (GET_CODE (x) == UNSPEC)
15267 switch (XINT (x, 1))
15269 case UNSPEC_TOCREL:
15270 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
15271 && REG_P (XVECEXP (x, 0, 1))
15272 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
15273 output_addr_const (file, XVECEXP (x, 0, 0));
15274 if (x == tocrel_base && tocrel_offset != const0_rtx)
15276 if (INTVAL (tocrel_offset) >= 0)
15277 fprintf (file, "+");
15278 output_addr_const (file, CONST_CAST_RTX (tocrel_offset));
15280 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15283 assemble_name (file, toc_label_name);
15285 else if (TARGET_ELF)
15286 fputs ("@toc", file);
15290 case UNSPEC_MACHOPIC_OFFSET:
15291 output_addr_const (file, XVECEXP (x, 0, 0));
15293 machopic_output_function_base_name (file);
15300 /* Target hook for assembling integer objects. The PowerPC version has
15301 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15302 is defined. It also needs to handle DI-mode objects on 64-bit
15306 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15308 #ifdef RELOCATABLE_NEEDS_FIXUP
15309 /* Special handling for SI values. */
15310 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15312 static int recurse = 0;
15314 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15315 the .fixup section. Since the TOC section is already relocated, we
15316 don't need to mark it here. We used to skip the text section, but it
15317 should never be valid for relocated addresses to be placed in the text
15319 if (TARGET_RELOCATABLE
15320 && in_section != toc_section
15322 && GET_CODE (x) != CONST_INT
15323 && GET_CODE (x) != CONST_DOUBLE
15329 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15331 ASM_OUTPUT_LABEL (asm_out_file, buf);
15332 fprintf (asm_out_file, "\t.long\t(");
15333 output_addr_const (asm_out_file, x);
15334 fprintf (asm_out_file, ")@fixup\n");
15335 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15336 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15337 fprintf (asm_out_file, "\t.long\t");
15338 assemble_name (asm_out_file, buf);
15339 fprintf (asm_out_file, "\n\t.previous\n");
15343 /* Remove initial .'s to turn a -mcall-aixdesc function
15344 address into the address of the descriptor, not the function
15346 else if (GET_CODE (x) == SYMBOL_REF
15347 && XSTR (x, 0)[0] == '.'
15348 && DEFAULT_ABI == ABI_AIX)
15350 const char *name = XSTR (x, 0);
15351 while (*name == '.')
15354 fprintf (asm_out_file, "\t.long\t%s\n", name);
15358 #endif /* RELOCATABLE_NEEDS_FIXUP */
15359 return default_assemble_integer (x, size, aligned_p);
15362 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15363 /* Emit an assembler directive to set symbol visibility for DECL to
15364 VISIBILITY_TYPE. */
15367 rs6000_assemble_visibility (tree decl, int vis)
15369 /* Functions need to have their entry point symbol visibility set as
15370 well as their descriptor symbol visibility. */
15371 if (DEFAULT_ABI == ABI_AIX
15373 && TREE_CODE (decl) == FUNCTION_DECL)
15375 static const char * const visibility_types[] = {
15376 NULL, "internal", "hidden", "protected"
15379 const char *name, *type;
15381 name = ((* targetm.strip_name_encoding)
15382 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15383 type = visibility_types[vis];
15385 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15386 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15389 default_assemble_visibility (decl, vis);
15394 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15396 /* Reversal of FP compares takes care -- an ordered compare
15397 becomes an unordered compare and vice versa. */
15398 if (mode == CCFPmode
15399 && (!flag_finite_math_only
15400 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15401 || code == UNEQ || code == LTGT))
15402 return reverse_condition_maybe_unordered (code);
15404 return reverse_condition (code);
15407 /* Generate a compare for CODE. Return a brand-new rtx that
15408 represents the result of the compare. */
15411 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15413 enum machine_mode comp_mode;
15414 rtx compare_result;
15415 enum rtx_code code = GET_CODE (cmp);
15416 rtx op0 = XEXP (cmp, 0);
15417 rtx op1 = XEXP (cmp, 1);
15419 if (FLOAT_MODE_P (mode))
15420 comp_mode = CCFPmode;
15421 else if (code == GTU || code == LTU
15422 || code == GEU || code == LEU)
15423 comp_mode = CCUNSmode;
15424 else if ((code == EQ || code == NE)
15425 && unsigned_reg_p (op0)
15426 && (unsigned_reg_p (op1)
15427 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
15428 /* These are unsigned values, perhaps there will be a later
15429 ordering compare that can be shared with this one. */
15430 comp_mode = CCUNSmode;
15432 comp_mode = CCmode;
15434 /* If we have an unsigned compare, make sure we don't have a signed value as
15436 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
15437 && INTVAL (op1) < 0)
15439 op0 = copy_rtx_if_shared (op0);
15440 op1 = force_reg (GET_MODE (op0), op1);
15441 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
15444 /* First, the compare. */
15445 compare_result = gen_reg_rtx (comp_mode);
15447 /* E500 FP compare instructions on the GPRs. Yuck! */
15448 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15449 && FLOAT_MODE_P (mode))
15451 rtx cmp, or_result, compare_result2;
15452 enum machine_mode op_mode = GET_MODE (op0);
15454 if (op_mode == VOIDmode)
15455 op_mode = GET_MODE (op1);
15457 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15458 This explains the following mess. */
15462 case EQ: case UNEQ: case NE: case LTGT:
15466 cmp = (flag_finite_math_only && !flag_trapping_math)
15467 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15468 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15472 cmp = (flag_finite_math_only && !flag_trapping_math)
15473 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15474 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15478 cmp = (flag_finite_math_only && !flag_trapping_math)
15479 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15480 : gen_cmptfeq_gpr (compare_result, op0, op1);
15484 gcc_unreachable ();
15488 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15492 cmp = (flag_finite_math_only && !flag_trapping_math)
15493 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15494 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15498 cmp = (flag_finite_math_only && !flag_trapping_math)
15499 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15500 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15504 cmp = (flag_finite_math_only && !flag_trapping_math)
15505 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15506 : gen_cmptfgt_gpr (compare_result, op0, op1);
15510 gcc_unreachable ();
15514 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15518 cmp = (flag_finite_math_only && !flag_trapping_math)
15519 ? gen_tstsflt_gpr (compare_result, op0, op1)
15520 : gen_cmpsflt_gpr (compare_result, op0, op1);
15524 cmp = (flag_finite_math_only && !flag_trapping_math)
15525 ? gen_tstdflt_gpr (compare_result, op0, op1)
15526 : gen_cmpdflt_gpr (compare_result, op0, op1);
15530 cmp = (flag_finite_math_only && !flag_trapping_math)
15531 ? gen_tsttflt_gpr (compare_result, op0, op1)
15532 : gen_cmptflt_gpr (compare_result, op0, op1);
15536 gcc_unreachable ();
15540 gcc_unreachable ();
15543 /* Synthesize LE and GE from LT/GT || EQ. */
15544 if (code == LE || code == GE || code == LEU || code == GEU)
15550 case LE: code = LT; break;
15551 case GE: code = GT; break;
15552 case LEU: code = LT; break;
15553 case GEU: code = GT; break;
15554 default: gcc_unreachable ();
15557 compare_result2 = gen_reg_rtx (CCFPmode);
15563 cmp = (flag_finite_math_only && !flag_trapping_math)
15564 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15565 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15569 cmp = (flag_finite_math_only && !flag_trapping_math)
15570 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15571 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15575 cmp = (flag_finite_math_only && !flag_trapping_math)
15576 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15577 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15581 gcc_unreachable ();
15585 /* OR them together. */
15586 or_result = gen_reg_rtx (CCFPmode);
15587 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15589 compare_result = or_result;
15594 if (code == NE || code == LTGT)
15604 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15605 CLOBBERs to match cmptf_internal2 pattern. */
15606 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15607 && GET_MODE (op0) == TFmode
15608 && !TARGET_IEEEQUAD
15609 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15610 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15612 gen_rtx_SET (VOIDmode,
15614 gen_rtx_COMPARE (comp_mode, op0, op1)),
15615 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15616 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15617 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15618 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15619 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15620 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15621 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15622 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15623 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15624 else if (GET_CODE (op1) == UNSPEC
15625 && XINT (op1, 1) == UNSPEC_SP_TEST)
15627 rtx op1b = XVECEXP (op1, 0, 0);
15628 comp_mode = CCEQmode;
15629 compare_result = gen_reg_rtx (CCEQmode);
15631 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15633 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15636 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15637 gen_rtx_COMPARE (comp_mode, op0, op1)));
15640 /* Some kinds of FP comparisons need an OR operation;
15641 under flag_finite_math_only we don't bother. */
15642 if (FLOAT_MODE_P (mode)
15643 && !flag_finite_math_only
15644 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15645 && (code == LE || code == GE
15646 || code == UNEQ || code == LTGT
15647 || code == UNGT || code == UNLT))
15649 enum rtx_code or1, or2;
15650 rtx or1_rtx, or2_rtx, compare2_rtx;
15651 rtx or_result = gen_reg_rtx (CCEQmode);
15655 case LE: or1 = LT; or2 = EQ; break;
15656 case GE: or1 = GT; or2 = EQ; break;
15657 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15658 case LTGT: or1 = LT; or2 = GT; break;
15659 case UNGT: or1 = UNORDERED; or2 = GT; break;
15660 case UNLT: or1 = UNORDERED; or2 = LT; break;
15661 default: gcc_unreachable ();
15663 validate_condition_mode (or1, comp_mode);
15664 validate_condition_mode (or2, comp_mode);
15665 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15666 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15667 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15668 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15670 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15672 compare_result = or_result;
15676 validate_condition_mode (code, GET_MODE (compare_result));
15678 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15682 /* Emit the RTL for an sISEL pattern. */
15685 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15687 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15691 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15694 enum machine_mode op_mode;
15695 enum rtx_code cond_code;
15696 rtx result = operands[0];
15698 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15700 rs6000_emit_sISEL (mode, operands);
15704 condition_rtx = rs6000_generate_compare (operands[1], mode);
15705 cond_code = GET_CODE (condition_rtx);
15707 if (FLOAT_MODE_P (mode)
15708 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15712 PUT_MODE (condition_rtx, SImode);
15713 t = XEXP (condition_rtx, 0);
15715 gcc_assert (cond_code == NE || cond_code == EQ);
15717 if (cond_code == NE)
15718 emit_insn (gen_e500_flip_gt_bit (t, t));
15720 emit_insn (gen_move_from_CR_gt_bit (result, t));
15724 if (cond_code == NE
15725 || cond_code == GE || cond_code == LE
15726 || cond_code == GEU || cond_code == LEU
15727 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15729 rtx not_result = gen_reg_rtx (CCEQmode);
15730 rtx not_op, rev_cond_rtx;
15731 enum machine_mode cc_mode;
15733 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15735 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15736 SImode, XEXP (condition_rtx, 0), const0_rtx);
15737 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15738 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15739 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15742 op_mode = GET_MODE (XEXP (operands[1], 0));
15743 if (op_mode == VOIDmode)
15744 op_mode = GET_MODE (XEXP (operands[1], 1));
15746 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15748 PUT_MODE (condition_rtx, DImode);
15749 convert_move (result, condition_rtx, 0);
15753 PUT_MODE (condition_rtx, SImode);
15754 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15758 /* Emit a branch of kind CODE to location LOC. */
15761 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15763 rtx condition_rtx, loc_ref;
15765 condition_rtx = rs6000_generate_compare (operands[0], mode);
15766 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15767 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15768 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15769 loc_ref, pc_rtx)));
15772 /* Return the string to output a conditional branch to LABEL, which is
15773 the operand number of the label, or -1 if the branch is really a
15774 conditional return.
15776 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15777 condition code register and its mode specifies what kind of
15778 comparison we made.
15780 REVERSED is nonzero if we should reverse the sense of the comparison.
15782 INSN is the insn. */
15785 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
15787 static char string[64];
15788 enum rtx_code code = GET_CODE (op);
15789 rtx cc_reg = XEXP (op, 0);
15790 enum machine_mode mode = GET_MODE (cc_reg);
15791 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
15792 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
15793 int really_reversed = reversed ^ need_longbranch;
15799 validate_condition_mode (code, mode);
15801 /* Work out which way this really branches. We could use
15802 reverse_condition_maybe_unordered here always but this
15803 makes the resulting assembler clearer. */
15804 if (really_reversed)
15806 /* Reversal of FP compares takes care -- an ordered compare
15807 becomes an unordered compare and vice versa. */
15808 if (mode == CCFPmode)
15809 code = reverse_condition_maybe_unordered (code);
15811 code = reverse_condition (code);
15814 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
15816 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15821 /* Opposite of GT. */
15830 gcc_unreachable ();
15836 /* Not all of these are actually distinct opcodes, but
15837 we distinguish them for clarity of the resulting assembler. */
15838 case NE: case LTGT:
15839 ccode = "ne"; break;
15840 case EQ: case UNEQ:
15841 ccode = "eq"; break;
15843 ccode = "ge"; break;
15844 case GT: case GTU: case UNGT:
15845 ccode = "gt"; break;
15847 ccode = "le"; break;
15848 case LT: case LTU: case UNLT:
15849 ccode = "lt"; break;
15850 case UNORDERED: ccode = "un"; break;
15851 case ORDERED: ccode = "nu"; break;
15852 case UNGE: ccode = "nl"; break;
15853 case UNLE: ccode = "ng"; break;
15855 gcc_unreachable ();
15858 /* Maybe we have a guess as to how likely the branch is.
15859 The old mnemonics don't have a way to specify this information. */
15861 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
15862 if (note != NULL_RTX)
15864 /* PROB is the difference from 50%. */
15865 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
15867 /* Only hint for highly probable/improbable branches on newer
15868 cpus as static prediction overrides processor dynamic
15869 prediction. For older cpus we may as well always hint, but
15870 assume not taken for branches that are very close to 50% as a
15871 mispredicted taken branch is more expensive than a
15872 mispredicted not-taken branch. */
15873 if (rs6000_always_hint
15874 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
15875 && br_prob_note_reliable_p (note)))
15877 if (abs (prob) > REG_BR_PROB_BASE / 20
15878 && ((prob > 0) ^ need_longbranch))
15886 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
15888 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
15890 /* We need to escape any '%' characters in the reg_names string.
15891 Assume they'd only be the first character.... */
15892 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
15894 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
15898 /* If the branch distance was too far, we may have to use an
15899 unconditional branch to go the distance. */
15900 if (need_longbranch)
15901 s += sprintf (s, ",$+8\n\tb %s", label);
15903 s += sprintf (s, ",%s", label);
15909 /* Return the string to flip the GT bit on a CR. */
15911 output_e500_flip_gt_bit (rtx dst, rtx src)
15913 static char string[64];
15916 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
15917 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
15920 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
15921 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
15923 sprintf (string, "crnot %d,%d", a, b);
15927 /* Return insn for VSX or Altivec comparisons. */
15930 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
15933 enum machine_mode mode = GET_MODE (op0);
15941 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
15951 mask = gen_reg_rtx (mode);
15952 emit_insn (gen_rtx_SET (VOIDmode,
15954 gen_rtx_fmt_ee (code, mode, op0, op1)));
15961 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
15962 DMODE is expected destination mode. This is a recursive function. */
15965 rs6000_emit_vector_compare (enum rtx_code rcode,
15967 enum machine_mode dmode)
15970 bool swap_operands = false;
15971 bool try_again = false;
15973 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
15974 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
15976 /* See if the comparison works as is. */
15977 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
15985 swap_operands = true;
15990 swap_operands = true;
15998 /* Invert condition and try again.
15999 e.g., A != B becomes ~(A==B). */
16001 enum rtx_code rev_code;
16002 enum insn_code nor_code;
16005 rev_code = reverse_condition_maybe_unordered (rcode);
16006 if (rev_code == UNKNOWN)
16009 nor_code = optab_handler (one_cmpl_optab, dmode);
16010 if (nor_code == CODE_FOR_nothing)
16013 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16017 mask = gen_reg_rtx (dmode);
16018 emit_insn (GEN_FCN (nor_code) (mask, mask2));
16026 /* Try GT/GTU/LT/LTU OR EQ */
16029 enum insn_code ior_code;
16030 enum rtx_code new_code;
16051 gcc_unreachable ();
16054 ior_code = optab_handler (ior_optab, dmode);
16055 if (ior_code == CODE_FOR_nothing)
16058 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16062 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16066 mask = gen_reg_rtx (dmode);
16067 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16085 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16090 /* You only get two chances. */
16094 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16095 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16096 operands for the relation operation COND. */
16099 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16100 rtx cond, rtx cc_op0, rtx cc_op1)
16102 enum machine_mode dest_mode = GET_MODE (dest);
16103 enum machine_mode mask_mode = GET_MODE (cc_op0);
16104 enum rtx_code rcode = GET_CODE (cond);
16105 enum machine_mode cc_mode = CCmode;
16109 bool invert_move = false;
16111 if (VECTOR_UNIT_NONE_P (dest_mode))
16114 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16115 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16119 /* Swap operands if we can, and fall back to doing the operation as
16120 specified, and doing a NOR to invert the test. */
16126 /* Invert condition and try again.
16127 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16128 invert_move = true;
16129 rcode = reverse_condition_maybe_unordered (rcode);
16130 if (rcode == UNKNOWN)
16134 /* Mark unsigned tests with CCUNSmode. */
16139 cc_mode = CCUNSmode;
16146 /* Get the vector mask for the given relational operations. */
16147 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16155 op_true = op_false;
16159 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16160 CONST0_RTX (dest_mode));
16161 emit_insn (gen_rtx_SET (VOIDmode,
16163 gen_rtx_IF_THEN_ELSE (dest_mode,
16170 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16171 operands of the last comparison is nonzero/true, FALSE_COND if it
16172 is zero/false. Return 0 if the hardware has no such operation. */
16175 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16177 enum rtx_code code = GET_CODE (op);
16178 rtx op0 = XEXP (op, 0);
16179 rtx op1 = XEXP (op, 1);
16180 REAL_VALUE_TYPE c1;
16181 enum machine_mode compare_mode = GET_MODE (op0);
16182 enum machine_mode result_mode = GET_MODE (dest);
16184 bool is_against_zero;
16186 /* These modes should always match. */
16187 if (GET_MODE (op1) != compare_mode
16188 /* In the isel case however, we can use a compare immediate, so
16189 op1 may be a small constant. */
16190 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16192 if (GET_MODE (true_cond) != result_mode)
16194 if (GET_MODE (false_cond) != result_mode)
16197 /* Don't allow using floating point comparisons for integer results for
16199 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
16202 /* First, work out if the hardware can do this at all, or
16203 if it's too slow.... */
16204 if (!FLOAT_MODE_P (compare_mode))
16207 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16210 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16211 && SCALAR_FLOAT_MODE_P (compare_mode))
16214 is_against_zero = op1 == CONST0_RTX (compare_mode);
16216 /* A floating-point subtract might overflow, underflow, or produce
16217 an inexact result, thus changing the floating-point flags, so it
16218 can't be generated if we care about that. It's safe if one side
16219 of the construct is zero, since then no subtract will be
16221 if (SCALAR_FLOAT_MODE_P (compare_mode)
16222 && flag_trapping_math && ! is_against_zero)
16225 /* Eliminate half of the comparisons by switching operands, this
16226 makes the remaining code simpler. */
16227 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16228 || code == LTGT || code == LT || code == UNLE)
16230 code = reverse_condition_maybe_unordered (code);
16232 true_cond = false_cond;
16236 /* UNEQ and LTGT take four instructions for a comparison with zero,
16237 it'll probably be faster to use a branch here too. */
16238 if (code == UNEQ && HONOR_NANS (compare_mode))
16241 if (GET_CODE (op1) == CONST_DOUBLE)
16242 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16244 /* We're going to try to implement comparisons by performing
16245 a subtract, then comparing against zero. Unfortunately,
16246 Inf - Inf is NaN which is not zero, and so if we don't
16247 know that the operand is finite and the comparison
16248 would treat EQ different to UNORDERED, we can't do it. */
16249 if (HONOR_INFINITIES (compare_mode)
16250 && code != GT && code != UNGE
16251 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16252 /* Constructs of the form (a OP b ? a : b) are safe. */
16253 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16254 || (! rtx_equal_p (op0, true_cond)
16255 && ! rtx_equal_p (op1, true_cond))))
16258 /* At this point we know we can use fsel. */
16260 /* Reduce the comparison to a comparison against zero. */
16261 if (! is_against_zero)
16263 temp = gen_reg_rtx (compare_mode);
16264 emit_insn (gen_rtx_SET (VOIDmode, temp,
16265 gen_rtx_MINUS (compare_mode, op0, op1)));
16267 op1 = CONST0_RTX (compare_mode);
16270 /* If we don't care about NaNs we can reduce some of the comparisons
16271 down to faster ones. */
16272 if (! HONOR_NANS (compare_mode))
16278 true_cond = false_cond;
16291 /* Now, reduce everything down to a GE. */
16298 temp = gen_reg_rtx (compare_mode);
16299 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16304 temp = gen_reg_rtx (compare_mode);
16305 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16310 temp = gen_reg_rtx (compare_mode);
16311 emit_insn (gen_rtx_SET (VOIDmode, temp,
16312 gen_rtx_NEG (compare_mode,
16313 gen_rtx_ABS (compare_mode, op0))));
16318 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16319 temp = gen_reg_rtx (result_mode);
16320 emit_insn (gen_rtx_SET (VOIDmode, temp,
16321 gen_rtx_IF_THEN_ELSE (result_mode,
16322 gen_rtx_GE (VOIDmode,
16324 true_cond, false_cond)));
16325 false_cond = true_cond;
16328 temp = gen_reg_rtx (compare_mode);
16329 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16334 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16335 temp = gen_reg_rtx (result_mode);
16336 emit_insn (gen_rtx_SET (VOIDmode, temp,
16337 gen_rtx_IF_THEN_ELSE (result_mode,
16338 gen_rtx_GE (VOIDmode,
16340 true_cond, false_cond)));
16341 true_cond = false_cond;
16344 temp = gen_reg_rtx (compare_mode);
16345 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16350 gcc_unreachable ();
16353 emit_insn (gen_rtx_SET (VOIDmode, dest,
16354 gen_rtx_IF_THEN_ELSE (result_mode,
16355 gen_rtx_GE (VOIDmode,
16357 true_cond, false_cond)));
16361 /* Same as above, but for ints (isel). */
16364 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16366 rtx condition_rtx, cr;
16367 enum machine_mode mode = GET_MODE (dest);
16368 enum rtx_code cond_code;
16369 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16372 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16375 /* We still have to do the compare, because isel doesn't do a
16376 compare, it just looks at the CRx bits set by a previous compare
16378 condition_rtx = rs6000_generate_compare (op, mode);
16379 cond_code = GET_CODE (condition_rtx);
16380 cr = XEXP (condition_rtx, 0);
16381 signedp = GET_MODE (cr) == CCmode;
16383 isel_func = (mode == SImode
16384 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16385 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16389 case LT: case GT: case LTU: case GTU: case EQ:
16390 /* isel handles these directly. */
16394 /* We need to swap the sense of the comparison. */
16397 true_cond = false_cond;
16399 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16404 false_cond = force_reg (mode, false_cond);
16405 if (true_cond != const0_rtx)
16406 true_cond = force_reg (mode, true_cond);
16408 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16414 output_isel (rtx *operands)
16416 enum rtx_code code;
16418 code = GET_CODE (operands[1]);
16420 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16422 gcc_assert (GET_CODE (operands[2]) == REG
16423 && GET_CODE (operands[3]) == REG);
16424 PUT_CODE (operands[1], reverse_condition (code));
16425 return "isel %0,%3,%2,%j1";
16428 return "isel %0,%2,%3,%j1";
16432 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16434 enum machine_mode mode = GET_MODE (op0);
16438 /* VSX/altivec have direct min/max insns. */
16439 if ((code == SMAX || code == SMIN)
16440 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16441 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16443 emit_insn (gen_rtx_SET (VOIDmode,
16445 gen_rtx_fmt_ee (code, mode, op0, op1)));
16449 if (code == SMAX || code == SMIN)
16454 if (code == SMAX || code == UMAX)
16455 target = emit_conditional_move (dest, c, op0, op1, mode,
16456 op0, op1, mode, 0);
16458 target = emit_conditional_move (dest, c, op0, op1, mode,
16459 op1, op0, mode, 0);
16460 gcc_assert (target);
16461 if (target != dest)
16462 emit_move_insn (dest, target);
16465 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16466 COND is true. Mark the jump as unlikely to be taken. */
16469 emit_unlikely_jump (rtx cond, rtx label)
16471 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16474 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16475 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16476 add_reg_note (x, REG_BR_PROB, very_unlikely);
16479 /* A subroutine of the atomic operation splitters. Emit a load-locked
16480 instruction in MODE. */
16483 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16485 rtx (*fn) (rtx, rtx) = NULL;
16490 fn = gen_load_lockedsi;
16493 fn = gen_load_lockeddi;
16496 gcc_unreachable ();
16498 emit_insn (fn (reg, mem));
16501 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16502 instruction in MODE. */
16505 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16507 rtx (*fn) (rtx, rtx, rtx) = NULL;
16512 fn = gen_store_conditionalsi;
16515 fn = gen_store_conditionaldi;
16518 gcc_unreachable ();
16521 /* Emit sync before stwcx. to address PPC405 Erratum. */
16522 if (PPC405_ERRATUM77)
16523 emit_insn (gen_hwsync ());
16525 emit_insn (fn (res, mem, val));
16528 /* Expand barriers before and after a load_locked/store_cond sequence. */
16531 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
16533 rtx addr = XEXP (mem, 0);
16534 int strict_p = (reload_in_progress || reload_completed);
16536 if (!legitimate_indirect_address_p (addr, strict_p)
16537 && !legitimate_indexed_address_p (addr, strict_p))
16539 addr = force_reg (Pmode, addr);
16540 mem = replace_equiv_address_nv (mem, addr);
16545 case MEMMODEL_RELAXED:
16546 case MEMMODEL_CONSUME:
16547 case MEMMODEL_ACQUIRE:
16549 case MEMMODEL_RELEASE:
16550 case MEMMODEL_ACQ_REL:
16551 emit_insn (gen_lwsync ());
16553 case MEMMODEL_SEQ_CST:
16554 emit_insn (gen_hwsync ());
16557 gcc_unreachable ();
16563 rs6000_post_atomic_barrier (enum memmodel model)
16567 case MEMMODEL_RELAXED:
16568 case MEMMODEL_CONSUME:
16569 case MEMMODEL_RELEASE:
16571 case MEMMODEL_ACQUIRE:
16572 case MEMMODEL_ACQ_REL:
16573 case MEMMODEL_SEQ_CST:
16574 emit_insn (gen_isync ());
16577 gcc_unreachable ();
16581 /* A subroutine of the various atomic expanders. For sub-word operations,
16582 we must adjust things to operate on SImode. Given the original MEM,
16583 return a new aligned memory. Also build and return the quantities by
16584 which to shift and mask. */
16587 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16589 rtx addr, align, shift, mask, mem;
16590 HOST_WIDE_INT shift_mask;
16591 enum machine_mode mode = GET_MODE (orig_mem);
16593 /* For smaller modes, we have to implement this via SImode. */
16594 shift_mask = (mode == QImode ? 0x18 : 0x10);
16596 addr = XEXP (orig_mem, 0);
16597 addr = force_reg (GET_MODE (addr), addr);
16599 /* Aligned memory containing subword. Generate a new memory. We
16600 do not want any of the existing MEM_ATTR data, as we're now
16601 accessing memory outside the original object. */
16602 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16603 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16604 mem = gen_rtx_MEM (SImode, align);
16605 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16606 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16607 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16609 /* Shift amount for subword relative to aligned word. */
16610 shift = gen_reg_rtx (SImode);
16611 addr = gen_lowpart (SImode, addr);
16612 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16613 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16614 shift, 1, OPTAB_LIB_WIDEN);
16617 /* Mask for insertion. */
16618 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16619 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16625 /* A subroutine of the various atomic expanders. For sub-word operands,
16626 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16629 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16633 x = gen_reg_rtx (SImode);
16634 emit_insn (gen_rtx_SET (VOIDmode, x,
16635 gen_rtx_AND (SImode,
16636 gen_rtx_NOT (SImode, mask),
16639 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16644 /* A subroutine of the various atomic expanders. For sub-word operands,
16645 extract WIDE to NARROW via SHIFT. */
16648 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16650 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16651 wide, 1, OPTAB_LIB_WIDEN);
16652 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16655 /* Expand an atomic compare and swap operation. */
16658 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16660 rtx boolval, retval, mem, oldval, newval, cond;
16661 rtx label1, label2, x, mask, shift;
16662 enum machine_mode mode;
16663 enum memmodel mod_s, mod_f;
16666 boolval = operands[0];
16667 retval = operands[1];
16669 oldval = operands[3];
16670 newval = operands[4];
16671 is_weak = (INTVAL (operands[5]) != 0);
16672 mod_s = (enum memmodel) INTVAL (operands[6]);
16673 mod_f = (enum memmodel) INTVAL (operands[7]);
16674 mode = GET_MODE (mem);
16676 mask = shift = NULL_RTX;
16677 if (mode == QImode || mode == HImode)
16679 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16681 /* Shift and mask OLDVAL into position with the word. */
16682 oldval = convert_modes (SImode, mode, oldval, 1);
16683 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16684 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16686 /* Shift and mask NEWVAL into position within the word. */
16687 newval = convert_modes (SImode, mode, newval, 1);
16688 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16689 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16691 /* Prepare to adjust the return value. */
16692 retval = gen_reg_rtx (SImode);
16695 else if (reg_overlap_mentioned_p (retval, oldval))
16696 oldval = copy_to_reg (oldval);
16698 mem = rs6000_pre_atomic_barrier (mem, mod_s);
16703 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16704 emit_label (XEXP (label1, 0));
16706 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16708 emit_load_locked (mode, retval, mem);
16713 x = expand_simple_binop (SImode, AND, retval, mask,
16714 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16717 cond = gen_reg_rtx (CCmode);
16718 x = gen_rtx_COMPARE (CCmode, x, oldval);
16719 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16721 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16722 emit_unlikely_jump (x, label2);
16726 x = rs6000_mask_atomic_subword (retval, newval, mask);
16728 emit_store_conditional (mode, cond, mem, x);
16732 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16733 emit_unlikely_jump (x, label1);
16736 if (mod_f != MEMMODEL_RELAXED)
16737 emit_label (XEXP (label2, 0));
16739 rs6000_post_atomic_barrier (mod_s);
16741 if (mod_f == MEMMODEL_RELAXED)
16742 emit_label (XEXP (label2, 0));
16745 rs6000_finish_atomic_subword (operands[1], retval, shift);
16747 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16748 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16749 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16752 /* Expand an atomic exchange operation. */
16755 rs6000_expand_atomic_exchange (rtx operands[])
16757 rtx retval, mem, val, cond;
16758 enum machine_mode mode;
16759 enum memmodel model;
16760 rtx label, x, mask, shift;
16762 retval = operands[0];
16765 model = (enum memmodel) INTVAL (operands[3]);
16766 mode = GET_MODE (mem);
16768 mask = shift = NULL_RTX;
16769 if (mode == QImode || mode == HImode)
16771 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16773 /* Shift and mask VAL into position with the word. */
16774 val = convert_modes (SImode, mode, val, 1);
16775 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16776 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16778 /* Prepare to adjust the return value. */
16779 retval = gen_reg_rtx (SImode);
16783 mem = rs6000_pre_atomic_barrier (mem, model);
16785 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16786 emit_label (XEXP (label, 0));
16788 emit_load_locked (mode, retval, mem);
16792 x = rs6000_mask_atomic_subword (retval, val, mask);
16794 cond = gen_reg_rtx (CCmode);
16795 emit_store_conditional (mode, cond, mem, x);
16797 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16798 emit_unlikely_jump (x, label);
16800 rs6000_post_atomic_barrier (model);
16803 rs6000_finish_atomic_subword (operands[0], retval, shift);
16806 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16807 to perform. MEM is the memory on which to operate. VAL is the second
16808 operand of the binary operator. BEFORE and AFTER are optional locations to
16809 return the value of MEM either before of after the operation. MODEL_RTX
16810 is a CONST_INT containing the memory model to use. */
16813 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
16814 rtx orig_before, rtx orig_after, rtx model_rtx)
16816 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
16817 enum machine_mode mode = GET_MODE (mem);
16818 rtx label, x, cond, mask, shift;
16819 rtx before = orig_before, after = orig_after;
16821 mask = shift = NULL_RTX;
16822 if (mode == QImode || mode == HImode)
16824 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16826 /* Shift and mask VAL into position with the word. */
16827 val = convert_modes (SImode, mode, val, 1);
16828 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16829 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16835 /* We've already zero-extended VAL. That is sufficient to
16836 make certain that it does not affect other bits. */
16841 /* If we make certain that all of the other bits in VAL are
16842 set, that will be sufficient to not affect other bits. */
16843 x = gen_rtx_NOT (SImode, mask);
16844 x = gen_rtx_IOR (SImode, x, val);
16845 emit_insn (gen_rtx_SET (VOIDmode, val, x));
16852 /* These will all affect bits outside the field and need
16853 adjustment via MASK within the loop. */
16857 gcc_unreachable ();
16860 /* Prepare to adjust the return value. */
16861 before = gen_reg_rtx (SImode);
16863 after = gen_reg_rtx (SImode);
16867 mem = rs6000_pre_atomic_barrier (mem, model);
16869 label = gen_label_rtx ();
16870 emit_label (label);
16871 label = gen_rtx_LABEL_REF (VOIDmode, label);
16873 if (before == NULL_RTX)
16874 before = gen_reg_rtx (mode);
16876 emit_load_locked (mode, before, mem);
16880 x = expand_simple_binop (mode, AND, before, val,
16881 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16882 after = expand_simple_unop (mode, NOT, x, after, 1);
16886 after = expand_simple_binop (mode, code, before, val,
16887 after, 1, OPTAB_LIB_WIDEN);
16893 x = expand_simple_binop (SImode, AND, after, mask,
16894 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16895 x = rs6000_mask_atomic_subword (before, x, mask);
16898 cond = gen_reg_rtx (CCmode);
16899 emit_store_conditional (mode, cond, mem, x);
16901 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16902 emit_unlikely_jump (x, label);
16904 rs6000_post_atomic_barrier (model);
16909 rs6000_finish_atomic_subword (orig_before, before, shift);
16911 rs6000_finish_atomic_subword (orig_after, after, shift);
16913 else if (orig_after && after != orig_after)
16914 emit_move_insn (orig_after, after);
16917 /* Emit instructions to move SRC to DST. Called by splitters for
16918 multi-register moves. It will emit at most one instruction for
16919 each register that is accessed; that is, it won't emit li/lis pairs
16920 (or equivalent for 64-bit code). One of SRC or DST must be a hard
16924 rs6000_split_multireg_move (rtx dst, rtx src)
16926 /* The register number of the first register being moved. */
16928 /* The mode that is to be moved. */
16929 enum machine_mode mode;
16930 /* The mode that the move is being done in, and its size. */
16931 enum machine_mode reg_mode;
16933 /* The number of registers that will be moved. */
16936 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
16937 mode = GET_MODE (dst);
16938 nregs = hard_regno_nregs[reg][mode];
16939 if (FP_REGNO_P (reg))
16940 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
16941 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
16942 else if (ALTIVEC_REGNO_P (reg))
16943 reg_mode = V16QImode;
16944 else if (TARGET_E500_DOUBLE && mode == TFmode)
16947 reg_mode = word_mode;
16948 reg_mode_size = GET_MODE_SIZE (reg_mode);
16950 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
16952 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
16954 /* Move register range backwards, if we might have destructive
16957 for (i = nregs - 1; i >= 0; i--)
16958 emit_insn (gen_rtx_SET (VOIDmode,
16959 simplify_gen_subreg (reg_mode, dst, mode,
16960 i * reg_mode_size),
16961 simplify_gen_subreg (reg_mode, src, mode,
16962 i * reg_mode_size)));
16968 bool used_update = false;
16969 rtx restore_basereg = NULL_RTX;
16971 if (MEM_P (src) && INT_REGNO_P (reg))
16975 if (GET_CODE (XEXP (src, 0)) == PRE_INC
16976 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
16979 breg = XEXP (XEXP (src, 0), 0);
16980 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
16981 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
16982 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
16983 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
16984 src = replace_equiv_address (src, breg);
16986 else if (! rs6000_offsettable_memref_p (src))
16988 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
16990 rtx basereg = XEXP (XEXP (src, 0), 0);
16993 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
16994 emit_insn (gen_rtx_SET (VOIDmode, ndst,
16995 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
16996 used_update = true;
16999 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17000 XEXP (XEXP (src, 0), 1)));
17001 src = replace_equiv_address (src, basereg);
17005 rtx basereg = gen_rtx_REG (Pmode, reg);
17006 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17007 src = replace_equiv_address (src, basereg);
17011 breg = XEXP (src, 0);
17012 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17013 breg = XEXP (breg, 0);
17015 /* If the base register we are using to address memory is
17016 also a destination reg, then change that register last. */
17018 && REGNO (breg) >= REGNO (dst)
17019 && REGNO (breg) < REGNO (dst) + nregs)
17020 j = REGNO (breg) - REGNO (dst);
17022 else if (MEM_P (dst) && INT_REGNO_P (reg))
17026 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17027 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17030 breg = XEXP (XEXP (dst, 0), 0);
17031 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17032 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17033 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17035 /* We have to update the breg before doing the store.
17036 Use store with update, if available. */
17040 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17041 emit_insn (TARGET_32BIT
17042 ? (TARGET_POWERPC64
17043 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17044 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
17045 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17046 used_update = true;
17049 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17050 dst = replace_equiv_address (dst, breg);
17052 else if (!rs6000_offsettable_memref_p (dst)
17053 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17055 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17057 rtx basereg = XEXP (XEXP (dst, 0), 0);
17060 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17061 emit_insn (gen_rtx_SET (VOIDmode,
17062 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17063 used_update = true;
17066 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17067 XEXP (XEXP (dst, 0), 1)));
17068 dst = replace_equiv_address (dst, basereg);
17072 rtx basereg = XEXP (XEXP (dst, 0), 0);
17073 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17074 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17076 && REG_P (offsetreg)
17077 && REGNO (basereg) != REGNO (offsetreg));
17078 if (REGNO (basereg) == 0)
17080 rtx tmp = offsetreg;
17081 offsetreg = basereg;
17084 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17085 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17086 dst = replace_equiv_address (dst, basereg);
17089 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17090 gcc_assert (rs6000_offsettable_memref_p (dst));
17093 for (i = 0; i < nregs; i++)
17095 /* Calculate index to next subword. */
17100 /* If compiler already emitted move of first word by
17101 store with update, no need to do anything. */
17102 if (j == 0 && used_update)
17105 emit_insn (gen_rtx_SET (VOIDmode,
17106 simplify_gen_subreg (reg_mode, dst, mode,
17107 j * reg_mode_size),
17108 simplify_gen_subreg (reg_mode, src, mode,
17109 j * reg_mode_size)));
17111 if (restore_basereg != NULL_RTX)
17112 emit_insn (restore_basereg);
17117 /* This page contains routines that are used to determine what the
17118 function prologue and epilogue code will do and write them out. */
17123 return !call_used_regs[r] && df_regs_ever_live_p (r);
17126 /* Return the first fixed-point register that is required to be
17127 saved. 32 if none. */
17130 first_reg_to_save (void)
17134 /* Find lowest numbered live register. */
17135 for (first_reg = 13; first_reg <= 31; first_reg++)
17136 if (save_reg_p (first_reg))
17139 if (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM
17140 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17141 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17142 || (TARGET_TOC && TARGET_MINIMAL_TOC))
17143 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
17144 first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM;
17148 && crtl->uses_pic_offset_table
17149 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17150 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17156 /* Similar, for FP regs. */
17159 first_fp_reg_to_save (void)
17163 /* Find lowest numbered live register. */
17164 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17165 if (save_reg_p (first_reg))
17171 /* Similar, for AltiVec regs. */
17174 first_altivec_reg_to_save (void)
17178 /* Stack frame remains as is unless we are in AltiVec ABI. */
17179 if (! TARGET_ALTIVEC_ABI)
17180 return LAST_ALTIVEC_REGNO + 1;
17182 /* On Darwin, the unwind routines are compiled without
17183 TARGET_ALTIVEC, and use save_world to save/restore the
17184 altivec registers when necessary. */
17185 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17186 && ! TARGET_ALTIVEC)
17187 return FIRST_ALTIVEC_REGNO + 20;
17189 /* Find lowest numbered live register. */
17190 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17191 if (save_reg_p (i))
17197 /* Return a 32-bit mask of the AltiVec registers we need to set in
17198 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17199 the 32-bit word is 0. */
17201 static unsigned int
17202 compute_vrsave_mask (void)
17204 unsigned int i, mask = 0;
17206 /* On Darwin, the unwind routines are compiled without
17207 TARGET_ALTIVEC, and use save_world to save/restore the
17208 call-saved altivec registers when necessary. */
17209 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17210 && ! TARGET_ALTIVEC)
17213 /* First, find out if we use _any_ altivec registers. */
17214 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17215 if (df_regs_ever_live_p (i))
17216 mask |= ALTIVEC_REG_BIT (i);
17221 /* Next, remove the argument registers from the set. These must
17222 be in the VRSAVE mask set by the caller, so we don't need to add
17223 them in again. More importantly, the mask we compute here is
17224 used to generate CLOBBERs in the set_vrsave insn, and we do not
17225 wish the argument registers to die. */
17226 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17227 mask &= ~ALTIVEC_REG_BIT (i);
17229 /* Similarly, remove the return value from the set. */
17232 diddle_return_value (is_altivec_return_reg, &yes);
17234 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17240 /* For a very restricted set of circumstances, we can cut down the
17241 size of prologues/epilogues by calling our own save/restore-the-world
17245 compute_save_world_info (rs6000_stack_t *info_ptr)
17247 info_ptr->world_save_p = 1;
17248 info_ptr->world_save_p
17249 = (WORLD_SAVE_P (info_ptr)
17250 && DEFAULT_ABI == ABI_DARWIN
17251 && !cfun->has_nonlocal_label
17252 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17253 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17254 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17255 && info_ptr->cr_save_p);
17257 /* This will not work in conjunction with sibcalls. Make sure there
17258 are none. (This check is expensive, but seldom executed.) */
17259 if (WORLD_SAVE_P (info_ptr))
17262 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17263 if ( GET_CODE (insn) == CALL_INSN
17264 && SIBLING_CALL_P (insn))
17266 info_ptr->world_save_p = 0;
17271 if (WORLD_SAVE_P (info_ptr))
17273 /* Even if we're not touching VRsave, make sure there's room on the
17274 stack for it, if it looks like we're calling SAVE_WORLD, which
17275 will attempt to save it. */
17276 info_ptr->vrsave_size = 4;
17278 /* If we are going to save the world, we need to save the link register too. */
17279 info_ptr->lr_save_p = 1;
17281 /* "Save" the VRsave register too if we're saving the world. */
17282 if (info_ptr->vrsave_mask == 0)
17283 info_ptr->vrsave_mask = compute_vrsave_mask ();
17285 /* Because the Darwin register save/restore routines only handle
17286 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17288 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17289 && (info_ptr->first_altivec_reg_save
17290 >= FIRST_SAVED_ALTIVEC_REGNO));
17297 is_altivec_return_reg (rtx reg, void *xyes)
17299 bool *yes = (bool *) xyes;
17300 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17305 /* Look for user-defined global regs in the range FIRST to LAST-1.
17306 We should not restore these, and so cannot use lmw or out-of-line
17307 restore functions if there are any. We also can't save them
17308 (well, emit frame notes for them), because frame unwinding during
17309 exception handling will restore saved registers. */
17312 global_regs_p (unsigned first, unsigned last)
17314 while (first < last)
17315 if (global_regs[first++])
17320 /* Determine the strategy for savings/restoring registers. */
17323 SAVRES_MULTIPLE = 0x1,
17324 SAVE_INLINE_FPRS = 0x2,
17325 SAVE_INLINE_GPRS = 0x4,
17326 REST_INLINE_FPRS = 0x8,
17327 REST_INLINE_GPRS = 0x10,
17328 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17329 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17330 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80,
17331 SAVE_INLINE_VRS = 0x100,
17332 REST_INLINE_VRS = 0x200
17336 rs6000_savres_strategy (rs6000_stack_t *info,
17337 bool using_static_chain_p)
17342 if (TARGET_MULTIPLE
17343 && !TARGET_POWERPC64
17344 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17345 && info->first_gp_reg_save < 31
17346 && !global_regs_p (info->first_gp_reg_save, 32))
17347 strategy |= SAVRES_MULTIPLE;
17349 if (crtl->calls_eh_return
17350 || cfun->machine->ra_need_lr)
17351 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17352 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
17353 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17355 if (info->first_fp_reg_save == 64
17356 /* The out-of-line FP routines use double-precision stores;
17357 we can't use those routines if we don't have such stores. */
17358 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17359 || global_regs_p (info->first_fp_reg_save, 64))
17360 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17362 if (info->first_gp_reg_save == 32
17363 || (!(strategy & SAVRES_MULTIPLE)
17364 && global_regs_p (info->first_gp_reg_save, 32)))
17365 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17367 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
17368 || global_regs_p (info->first_altivec_reg_save, LAST_ALTIVEC_REGNO + 1))
17369 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17371 /* Define cutoff for using out-of-line functions to save registers. */
17372 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
17374 if (!optimize_size)
17376 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17377 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17378 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17382 /* Prefer out-of-line restore if it will exit. */
17383 if (info->first_fp_reg_save > 61)
17384 strategy |= SAVE_INLINE_FPRS;
17385 if (info->first_gp_reg_save > 29)
17387 if (info->first_fp_reg_save == 64)
17388 strategy |= SAVE_INLINE_GPRS;
17390 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17392 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
17393 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17396 else if (DEFAULT_ABI == ABI_DARWIN)
17398 if (info->first_fp_reg_save > 60)
17399 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17400 if (info->first_gp_reg_save > 29)
17401 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17402 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17406 gcc_checking_assert (DEFAULT_ABI == ABI_AIX);
17407 if (info->first_fp_reg_save > 61)
17408 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17409 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17410 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17413 /* Don't bother to try to save things out-of-line if r11 is occupied
17414 by the static chain. It would require too much fiddling and the
17415 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17416 pointer on Darwin, and AIX uses r1 or r12. */
17417 if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)
17418 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17420 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17422 /* We can only use the out-of-line routines to restore if we've
17423 saved all the registers from first_fp_reg_save in the prologue.
17424 Otherwise, we risk loading garbage. */
17425 if ((strategy & (SAVE_INLINE_FPRS | REST_INLINE_FPRS)) == SAVE_INLINE_FPRS)
17429 for (i = info->first_fp_reg_save; i < 64; i++)
17430 if (!save_reg_p (i))
17432 strategy |= REST_INLINE_FPRS;
17437 /* If we are going to use store multiple, then don't even bother
17438 with the out-of-line routines, since the store-multiple
17439 instruction will always be smaller. */
17440 if ((strategy & SAVRES_MULTIPLE))
17441 strategy |= SAVE_INLINE_GPRS;
17443 /* info->lr_save_p isn't yet set if the only reason lr needs to be
17444 saved is an out-of-line save or restore. Set up the value for
17445 the next test (excluding out-of-line gpr restore). */
17446 lr_save_p = (info->lr_save_p
17447 || !(strategy & SAVE_INLINE_GPRS)
17448 || !(strategy & SAVE_INLINE_FPRS)
17449 || !(strategy & SAVE_INLINE_VRS)
17450 || !(strategy & REST_INLINE_FPRS)
17451 || !(strategy & REST_INLINE_VRS));
17453 /* The situation is more complicated with load multiple. We'd
17454 prefer to use the out-of-line routines for restores, since the
17455 "exit" out-of-line routines can handle the restore of LR and the
17456 frame teardown. However if doesn't make sense to use the
17457 out-of-line routine if that is the only reason we'd need to save
17458 LR, and we can't use the "exit" out-of-line gpr restore if we
17459 have saved some fprs; In those cases it is advantageous to use
17460 load multiple when available. */
17461 if ((strategy & SAVRES_MULTIPLE)
17463 || info->first_fp_reg_save != 64))
17464 strategy |= REST_INLINE_GPRS;
17466 /* Saving CR interferes with the exit routines used on the SPE, so
17469 && info->spe_64bit_regs_used
17470 && info->cr_save_p)
17471 strategy |= REST_INLINE_GPRS;
17473 /* We can only use load multiple or the out-of-line routines to
17474 restore if we've used store multiple or out-of-line routines
17475 in the prologue, i.e. if we've saved all the registers from
17476 first_gp_reg_save. Otherwise, we risk loading garbage. */
17477 if ((strategy & (SAVE_INLINE_GPRS | REST_INLINE_GPRS | SAVRES_MULTIPLE))
17478 == SAVE_INLINE_GPRS)
17482 for (i = info->first_gp_reg_save; i < 32; i++)
17483 if (!save_reg_p (i))
17485 strategy |= REST_INLINE_GPRS;
17490 if (TARGET_ELF && TARGET_64BIT)
17492 if (!(strategy & SAVE_INLINE_FPRS))
17493 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17494 else if (!(strategy & SAVE_INLINE_GPRS)
17495 && info->first_fp_reg_save == 64)
17496 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17498 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17499 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17501 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17502 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17507 /* Calculate the stack information for the current function. This is
17508 complicated by having two separate calling sequences, the AIX calling
17509 sequence and the V.4 calling sequence.
17511 AIX (and Darwin/Mac OS X) stack frames look like:
17513 SP----> +---------------------------------------+
17514 | back chain to caller | 0 0
17515 +---------------------------------------+
17516 | saved CR | 4 8 (8-11)
17517 +---------------------------------------+
17519 +---------------------------------------+
17520 | reserved for compilers | 12 24
17521 +---------------------------------------+
17522 | reserved for binders | 16 32
17523 +---------------------------------------+
17524 | saved TOC pointer | 20 40
17525 +---------------------------------------+
17526 | Parameter save area (P) | 24 48
17527 +---------------------------------------+
17528 | Alloca space (A) | 24+P etc.
17529 +---------------------------------------+
17530 | Local variable space (L) | 24+P+A
17531 +---------------------------------------+
17532 | Float/int conversion temporary (X) | 24+P+A+L
17533 +---------------------------------------+
17534 | Save area for AltiVec registers (W) | 24+P+A+L+X
17535 +---------------------------------------+
17536 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17537 +---------------------------------------+
17538 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17539 +---------------------------------------+
17540 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17541 +---------------------------------------+
17542 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17543 +---------------------------------------+
17544 old SP->| back chain to caller's caller |
17545 +---------------------------------------+
17547 The required alignment for AIX configurations is two words (i.e., 8
17551 V.4 stack frames look like:
17553 SP----> +---------------------------------------+
17554 | back chain to caller | 0
17555 +---------------------------------------+
17556 | caller's saved LR | 4
17557 +---------------------------------------+
17558 | Parameter save area (P) | 8
17559 +---------------------------------------+
17560 | Alloca space (A) | 8+P
17561 +---------------------------------------+
17562 | Varargs save area (V) | 8+P+A
17563 +---------------------------------------+
17564 | Local variable space (L) | 8+P+A+V
17565 +---------------------------------------+
17566 | Float/int conversion temporary (X) | 8+P+A+V+L
17567 +---------------------------------------+
17568 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17569 +---------------------------------------+
17570 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17571 +---------------------------------------+
17572 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17573 +---------------------------------------+
17574 | SPE: area for 64-bit GP registers |
17575 +---------------------------------------+
17576 | SPE alignment padding |
17577 +---------------------------------------+
17578 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17579 +---------------------------------------+
17580 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17581 +---------------------------------------+
17582 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17583 +---------------------------------------+
17584 old SP->| back chain to caller's caller |
17585 +---------------------------------------+
17587 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17588 given. (But note below and in sysv4.h that we require only 8 and
17589 may round up the size of our stack frame anyways. The historical
17590 reason is early versions of powerpc-linux which didn't properly
17591 align the stack at program startup. A happy side-effect is that
17592 -mno-eabi libraries can be used with -meabi programs.)
17594 The EABI configuration defaults to the V.4 layout. However,
17595 the stack alignment requirements may differ. If -mno-eabi is not
17596 given, the required stack alignment is 8 bytes; if -mno-eabi is
17597 given, the required alignment is 16 bytes. (But see V.4 comment
17600 #ifndef ABI_STACK_BOUNDARY
17601 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17604 static rs6000_stack_t *
17605 rs6000_stack_info (void)
17607 rs6000_stack_t *info_ptr = &stack_info;
17608 int reg_size = TARGET_32BIT ? 4 : 8;
17612 HOST_WIDE_INT non_fixed_size;
17613 bool using_static_chain_p;
17615 if (reload_completed && info_ptr->reload_completed)
17618 memset (info_ptr, 0, sizeof (*info_ptr));
17619 info_ptr->reload_completed = reload_completed;
17623 /* Cache value so we don't rescan instruction chain over and over. */
17624 if (cfun->machine->insn_chain_scanned_p == 0)
17625 cfun->machine->insn_chain_scanned_p
17626 = spe_func_has_64bit_regs_p () + 1;
17627 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17630 /* Select which calling sequence. */
17631 info_ptr->abi = DEFAULT_ABI;
17633 /* Calculate which registers need to be saved & save area size. */
17634 info_ptr->first_gp_reg_save = first_reg_to_save ();
17635 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17636 even if it currently looks like we won't. Reload may need it to
17637 get at a constant; if so, it will have already created a constant
17638 pool entry for it. */
17639 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17640 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17641 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17642 && crtl->uses_const_pool
17643 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17644 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17646 first_gp = info_ptr->first_gp_reg_save;
17648 info_ptr->gp_size = reg_size * (32 - first_gp);
17650 /* For the SPE, we have an additional upper 32-bits on each GPR.
17651 Ideally we should save the entire 64-bits only when the upper
17652 half is used in SIMD instructions. Since we only record
17653 registers live (not the size they are used in), this proves
17654 difficult because we'd have to traverse the instruction chain at
17655 the right time, taking reload into account. This is a real pain,
17656 so we opt to save the GPRs in 64-bits always if but one register
17657 gets used in 64-bits. Otherwise, all the registers in the frame
17658 get saved in 32-bits.
17660 So... since when we save all GPRs (except the SP) in 64-bits, the
17661 traditional GP save area will be empty. */
17662 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17663 info_ptr->gp_size = 0;
17665 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17666 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17668 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17669 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17670 - info_ptr->first_altivec_reg_save);
17672 /* Does this function call anything? */
17673 info_ptr->calls_p = (! current_function_is_leaf
17674 || cfun->machine->ra_needs_full_frame);
17676 /* Determine if we need to save the condition code registers. */
17677 if (df_regs_ever_live_p (CR2_REGNO)
17678 || df_regs_ever_live_p (CR3_REGNO)
17679 || df_regs_ever_live_p (CR4_REGNO))
17681 info_ptr->cr_save_p = 1;
17682 if (DEFAULT_ABI == ABI_V4)
17683 info_ptr->cr_size = reg_size;
17686 /* If the current function calls __builtin_eh_return, then we need
17687 to allocate stack space for registers that will hold data for
17688 the exception handler. */
17689 if (crtl->calls_eh_return)
17692 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17695 /* SPE saves EH registers in 64-bits. */
17696 ehrd_size = i * (TARGET_SPE_ABI
17697 && info_ptr->spe_64bit_regs_used != 0
17698 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17703 /* Determine various sizes. */
17704 info_ptr->reg_size = reg_size;
17705 info_ptr->fixed_size = RS6000_SAVE_AREA;
17706 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17707 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17708 TARGET_ALTIVEC ? 16 : 8);
17709 if (FRAME_GROWS_DOWNWARD)
17710 info_ptr->vars_size
17711 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17712 + info_ptr->parm_size,
17713 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17714 - (info_ptr->fixed_size + info_ptr->vars_size
17715 + info_ptr->parm_size);
17717 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17718 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17720 info_ptr->spe_gp_size = 0;
17722 if (TARGET_ALTIVEC_ABI)
17723 info_ptr->vrsave_mask = compute_vrsave_mask ();
17725 info_ptr->vrsave_mask = 0;
17727 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17728 info_ptr->vrsave_size = 4;
17730 info_ptr->vrsave_size = 0;
17732 compute_save_world_info (info_ptr);
17734 /* Calculate the offsets. */
17735 switch (DEFAULT_ABI)
17739 gcc_unreachable ();
17743 info_ptr->fp_save_offset = - info_ptr->fp_size;
17744 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17746 if (TARGET_ALTIVEC_ABI)
17748 info_ptr->vrsave_save_offset
17749 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17751 /* Align stack so vector save area is on a quadword boundary.
17752 The padding goes above the vectors. */
17753 if (info_ptr->altivec_size != 0)
17754 info_ptr->altivec_padding_size
17755 = info_ptr->vrsave_save_offset & 0xF;
17757 info_ptr->altivec_padding_size = 0;
17759 info_ptr->altivec_save_offset
17760 = info_ptr->vrsave_save_offset
17761 - info_ptr->altivec_padding_size
17762 - info_ptr->altivec_size;
17763 gcc_assert (info_ptr->altivec_size == 0
17764 || info_ptr->altivec_save_offset % 16 == 0);
17766 /* Adjust for AltiVec case. */
17767 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17770 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17771 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17772 info_ptr->lr_save_offset = 2*reg_size;
17776 info_ptr->fp_save_offset = - info_ptr->fp_size;
17777 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17778 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
17780 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17782 /* Align stack so SPE GPR save area is aligned on a
17783 double-word boundary. */
17784 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
17785 info_ptr->spe_padding_size
17786 = 8 - (-info_ptr->cr_save_offset % 8);
17788 info_ptr->spe_padding_size = 0;
17790 info_ptr->spe_gp_save_offset
17791 = info_ptr->cr_save_offset
17792 - info_ptr->spe_padding_size
17793 - info_ptr->spe_gp_size;
17795 /* Adjust for SPE case. */
17796 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
17798 else if (TARGET_ALTIVEC_ABI)
17800 info_ptr->vrsave_save_offset
17801 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
17803 /* Align stack so vector save area is on a quadword boundary. */
17804 if (info_ptr->altivec_size != 0)
17805 info_ptr->altivec_padding_size
17806 = 16 - (-info_ptr->vrsave_save_offset % 16);
17808 info_ptr->altivec_padding_size = 0;
17810 info_ptr->altivec_save_offset
17811 = info_ptr->vrsave_save_offset
17812 - info_ptr->altivec_padding_size
17813 - info_ptr->altivec_size;
17815 /* Adjust for AltiVec case. */
17816 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
17819 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
17820 info_ptr->ehrd_offset -= ehrd_size;
17821 info_ptr->lr_save_offset = reg_size;
17825 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
17826 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
17827 + info_ptr->gp_size
17828 + info_ptr->altivec_size
17829 + info_ptr->altivec_padding_size
17830 + info_ptr->spe_gp_size
17831 + info_ptr->spe_padding_size
17833 + info_ptr->cr_size
17834 + info_ptr->vrsave_size,
17837 non_fixed_size = (info_ptr->vars_size
17838 + info_ptr->parm_size
17839 + info_ptr->save_size);
17841 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
17842 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
17844 /* Determine if we need to save the link register. */
17845 if (info_ptr->calls_p
17846 || (DEFAULT_ABI == ABI_AIX
17848 && !TARGET_PROFILE_KERNEL)
17849 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
17850 #ifdef TARGET_RELOCATABLE
17851 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
17853 || rs6000_ra_ever_killed ())
17854 info_ptr->lr_save_p = 1;
17856 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
17857 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
17858 && call_used_regs[STATIC_CHAIN_REGNUM]);
17859 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
17860 using_static_chain_p);
17862 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
17863 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
17864 || !(info_ptr->savres_strategy & SAVE_INLINE_VRS)
17865 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
17866 || !(info_ptr->savres_strategy & REST_INLINE_FPRS)
17867 || !(info_ptr->savres_strategy & REST_INLINE_VRS))
17868 info_ptr->lr_save_p = 1;
17870 if (info_ptr->lr_save_p)
17871 df_set_regs_ever_live (LR_REGNO, true);
17873 /* Determine if we need to allocate any stack frame:
17875 For AIX we need to push the stack if a frame pointer is needed
17876 (because the stack might be dynamically adjusted), if we are
17877 debugging, if we make calls, or if the sum of fp_save, gp_save,
17878 and local variables are more than the space needed to save all
17879 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17880 + 18*8 = 288 (GPR13 reserved).
17882 For V.4 we don't have the stack cushion that AIX uses, but assume
17883 that the debugger can handle stackless frames. */
17885 if (info_ptr->calls_p)
17886 info_ptr->push_p = 1;
17888 else if (DEFAULT_ABI == ABI_V4)
17889 info_ptr->push_p = non_fixed_size != 0;
17891 else if (frame_pointer_needed)
17892 info_ptr->push_p = 1;
17894 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
17895 info_ptr->push_p = 1;
17898 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
17900 /* Zero offsets if we're not saving those registers. */
17901 if (info_ptr->fp_size == 0)
17902 info_ptr->fp_save_offset = 0;
17904 if (info_ptr->gp_size == 0)
17905 info_ptr->gp_save_offset = 0;
17907 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
17908 info_ptr->altivec_save_offset = 0;
17910 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
17911 info_ptr->vrsave_save_offset = 0;
17913 if (! TARGET_SPE_ABI
17914 || info_ptr->spe_64bit_regs_used == 0
17915 || info_ptr->spe_gp_size == 0)
17916 info_ptr->spe_gp_save_offset = 0;
17918 if (! info_ptr->lr_save_p)
17919 info_ptr->lr_save_offset = 0;
17921 if (! info_ptr->cr_save_p)
17922 info_ptr->cr_save_offset = 0;
17927 /* Return true if the current function uses any GPRs in 64-bit SIMD
17931 spe_func_has_64bit_regs_p (void)
17935 /* Functions that save and restore all the call-saved registers will
17936 need to save/restore the registers in 64-bits. */
17937 if (crtl->calls_eh_return
17938 || cfun->calls_setjmp
17939 || crtl->has_nonlocal_goto)
17942 insns = get_insns ();
17944 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
17950 /* FIXME: This should be implemented with attributes...
17952 (set_attr "spe64" "true")....then,
17953 if (get_spe64(insn)) return true;
17955 It's the only reliable way to do the stuff below. */
17957 i = PATTERN (insn);
17958 if (GET_CODE (i) == SET)
17960 enum machine_mode mode = GET_MODE (SET_SRC (i));
17962 if (SPE_VECTOR_MODE (mode))
17964 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
17974 debug_stack_info (rs6000_stack_t *info)
17976 const char *abi_string;
17979 info = rs6000_stack_info ();
17981 fprintf (stderr, "\nStack information for function %s:\n",
17982 ((current_function_decl && DECL_NAME (current_function_decl))
17983 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
17988 default: abi_string = "Unknown"; break;
17989 case ABI_NONE: abi_string = "NONE"; break;
17990 case ABI_AIX: abi_string = "AIX"; break;
17991 case ABI_DARWIN: abi_string = "Darwin"; break;
17992 case ABI_V4: abi_string = "V.4"; break;
17995 fprintf (stderr, "\tABI = %5s\n", abi_string);
17997 if (TARGET_ALTIVEC_ABI)
17998 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18000 if (TARGET_SPE_ABI)
18001 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18003 if (info->first_gp_reg_save != 32)
18004 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
18006 if (info->first_fp_reg_save != 64)
18007 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
18009 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18010 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18011 info->first_altivec_reg_save);
18013 if (info->lr_save_p)
18014 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
18016 if (info->cr_save_p)
18017 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
18019 if (info->vrsave_mask)
18020 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
18023 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
18026 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
18028 if (info->gp_save_offset)
18029 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
18031 if (info->fp_save_offset)
18032 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
18034 if (info->altivec_save_offset)
18035 fprintf (stderr, "\taltivec_save_offset = %5d\n",
18036 info->altivec_save_offset);
18038 if (info->spe_gp_save_offset)
18039 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
18040 info->spe_gp_save_offset);
18042 if (info->vrsave_save_offset)
18043 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
18044 info->vrsave_save_offset);
18046 if (info->lr_save_offset)
18047 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
18049 if (info->cr_save_offset)
18050 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
18052 if (info->varargs_save_offset)
18053 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18055 if (info->total_size)
18056 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18059 if (info->vars_size)
18060 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18063 if (info->parm_size)
18064 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
18066 if (info->fixed_size)
18067 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
18070 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
18072 if (info->spe_gp_size)
18073 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
18076 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
18078 if (info->altivec_size)
18079 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
18081 if (info->vrsave_size)
18082 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
18084 if (info->altivec_padding_size)
18085 fprintf (stderr, "\taltivec_padding_size= %5d\n",
18086 info->altivec_padding_size);
18088 if (info->spe_padding_size)
18089 fprintf (stderr, "\tspe_padding_size = %5d\n",
18090 info->spe_padding_size);
18093 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
18095 if (info->save_size)
18096 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
18098 if (info->reg_size != 4)
18099 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
18101 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
18103 fprintf (stderr, "\n");
18107 rs6000_return_addr (int count, rtx frame)
18109 /* Currently we don't optimize very well between prolog and body
18110 code and for PIC code the code can be actually quite bad, so
18111 don't try to be too clever here. */
18112 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18114 cfun->machine->ra_needs_full_frame = 1;
18121 plus_constant (Pmode,
18123 (gen_rtx_MEM (Pmode,
18124 memory_address (Pmode, frame))),
18125 RETURN_ADDRESS_OFFSET)));
18128 cfun->machine->ra_need_lr = 1;
18129 return get_hard_reg_initial_val (Pmode, LR_REGNO);
18132 /* Say whether a function is a candidate for sibcall handling or not. */
18135 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18140 fntype = TREE_TYPE (decl);
18142 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18144 /* We can't do it if the called function has more vector parameters
18145 than the current function; there's nowhere to put the VRsave code. */
18146 if (TARGET_ALTIVEC_ABI
18147 && TARGET_ALTIVEC_VRSAVE
18148 && !(decl && decl == current_function_decl))
18150 function_args_iterator args_iter;
18154 /* Functions with vector parameters are required to have a
18155 prototype, so the argument type info must be available
18157 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18158 if (TREE_CODE (type) == VECTOR_TYPE
18159 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18162 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18163 if (TREE_CODE (type) == VECTOR_TYPE
18164 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18171 /* Under the AIX ABI we can't allow calls to non-local functions,
18172 because the callee may have a different TOC pointer to the
18173 caller and there's no way to ensure we restore the TOC when we
18174 return. With the secure-plt SYSV ABI we can't make non-local
18175 calls when -fpic/PIC because the plt call stubs use r30. */
18176 if (DEFAULT_ABI == ABI_DARWIN
18177 || (DEFAULT_ABI == ABI_AIX
18179 && !DECL_EXTERNAL (decl)
18180 && (*targetm.binds_local_p) (decl))
18181 || (DEFAULT_ABI == ABI_V4
18182 && (!TARGET_SECURE_PLT
18185 && (*targetm.binds_local_p) (decl)))))
18187 tree attr_list = TYPE_ATTRIBUTES (fntype);
18189 if (!lookup_attribute ("longcall", attr_list)
18190 || lookup_attribute ("shortcall", attr_list))
18197 /* NULL if INSN insn is valid within a low-overhead loop.
18198 Otherwise return why doloop cannot be applied.
18199 PowerPC uses the COUNT register for branch on table instructions. */
18201 static const char *
18202 rs6000_invalid_within_doloop (const_rtx insn)
18205 return "Function call in the loop.";
18208 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18209 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18210 return "Computed branch in the loop.";
18216 rs6000_ra_ever_killed (void)
18222 if (cfun->is_thunk)
18225 if (cfun->machine->lr_save_state)
18226 return cfun->machine->lr_save_state - 1;
18228 /* regs_ever_live has LR marked as used if any sibcalls are present,
18229 but this should not force saving and restoring in the
18230 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18231 clobbers LR, so that is inappropriate. */
18233 /* Also, the prologue can generate a store into LR that
18234 doesn't really count, like this:
18237 bcl to set PIC register
18241 When we're called from the epilogue, we need to avoid counting
18242 this as a store. */
18244 push_topmost_sequence ();
18245 top = get_insns ();
18246 pop_topmost_sequence ();
18247 reg = gen_rtx_REG (Pmode, LR_REGNO);
18249 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18255 if (!SIBLING_CALL_P (insn))
18258 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18260 else if (set_of (reg, insn) != NULL_RTX
18261 && !prologue_epilogue_contains (insn))
18268 /* Emit instructions needed to load the TOC register.
18269 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18270 a constant pool; or for SVR4 -fpic. */
18273 rs6000_emit_load_toc_table (int fromprolog)
18276 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18278 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18281 rtx lab, tmp1, tmp2, got;
18283 lab = gen_label_rtx ();
18284 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18285 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18287 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18289 got = rs6000_got_sym ();
18290 tmp1 = tmp2 = dest;
18293 tmp1 = gen_reg_rtx (Pmode);
18294 tmp2 = gen_reg_rtx (Pmode);
18296 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18297 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18298 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18299 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18301 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18303 emit_insn (gen_load_toc_v4_pic_si ());
18304 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18306 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18309 rtx temp0 = (fromprolog
18310 ? gen_rtx_REG (Pmode, 0)
18311 : gen_reg_rtx (Pmode));
18317 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18318 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18320 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18321 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18323 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18324 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18325 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18331 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18332 lab = gen_label_rtx ();
18333 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18334 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18335 if (TARGET_LINK_STACK)
18336 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18337 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18339 emit_insn (gen_addsi3 (dest, temp0, dest));
18341 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18343 /* This is for AIX code running in non-PIC ELF32. */
18346 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18347 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18349 emit_insn (gen_elf_high (dest, realsym));
18350 emit_insn (gen_elf_low (dest, dest, realsym));
18354 gcc_assert (DEFAULT_ABI == ABI_AIX);
18357 emit_insn (gen_load_toc_aix_si (dest));
18359 emit_insn (gen_load_toc_aix_di (dest));
18363 /* Emit instructions to restore the link register after determining where
18364 its value has been stored. */
18367 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18369 rs6000_stack_t *info = rs6000_stack_info ();
18372 operands[0] = source;
18373 operands[1] = scratch;
18375 if (info->lr_save_p)
18377 rtx frame_rtx = stack_pointer_rtx;
18378 HOST_WIDE_INT sp_offset = 0;
18381 if (frame_pointer_needed
18382 || cfun->calls_alloca
18383 || info->total_size > 32767)
18385 tmp = gen_frame_mem (Pmode, frame_rtx);
18386 emit_move_insn (operands[1], tmp);
18387 frame_rtx = operands[1];
18389 else if (info->push_p)
18390 sp_offset = info->total_size;
18392 tmp = plus_constant (Pmode, frame_rtx,
18393 info->lr_save_offset + sp_offset);
18394 tmp = gen_frame_mem (Pmode, tmp);
18395 emit_move_insn (tmp, operands[0]);
18398 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18400 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18401 state of lr_save_p so any change from here on would be a bug. In
18402 particular, stop rs6000_ra_ever_killed from considering the SET
18403 of lr we may have added just above. */
18404 cfun->machine->lr_save_state = info->lr_save_p + 1;
18407 static GTY(()) alias_set_type set = -1;
18410 get_TOC_alias_set (void)
18413 set = new_alias_set ();
18417 /* This returns nonzero if the current function uses the TOC. This is
18418 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18419 is generated by the ABI_V4 load_toc_* patterns. */
18426 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18429 rtx pat = PATTERN (insn);
18432 if (GET_CODE (pat) == PARALLEL)
18433 for (i = 0; i < XVECLEN (pat, 0); i++)
18435 rtx sub = XVECEXP (pat, 0, i);
18436 if (GET_CODE (sub) == USE)
18438 sub = XEXP (sub, 0);
18439 if (GET_CODE (sub) == UNSPEC
18440 && XINT (sub, 1) == UNSPEC_TOC)
18450 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18452 rtx tocrel, tocreg, hi;
18454 if (TARGET_DEBUG_ADDR)
18456 if (GET_CODE (symbol) == SYMBOL_REF)
18457 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18461 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18462 GET_RTX_NAME (GET_CODE (symbol)));
18463 debug_rtx (symbol);
18467 if (!can_create_pseudo_p ())
18468 df_set_regs_ever_live (TOC_REGISTER, true);
18470 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18471 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
18472 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
18475 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
18476 if (largetoc_reg != NULL)
18478 emit_move_insn (largetoc_reg, hi);
18481 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
18484 /* Issue assembly directives that create a reference to the given DWARF
18485 FRAME_TABLE_LABEL from the current function section. */
18487 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18489 fprintf (asm_out_file, "\t.ref %s\n",
18490 (* targetm.strip_name_encoding) (frame_table_label));
18493 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18494 and the change to the stack pointer. */
18497 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
18504 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18505 if (hard_frame_needed)
18506 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
18507 if (!(REGNO (fp) == STACK_POINTER_REGNUM
18508 || (hard_frame_needed
18509 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
18512 p = rtvec_alloc (i);
18515 rtx mem = gen_frame_mem (BLKmode, regs[i]);
18516 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, const0_rtx);
18519 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
18522 /* Emit the correct code for allocating stack space, as insns.
18523 If COPY_REG, make sure a copy of the old frame is left there.
18524 The generated code may use hard register 0 as a temporary. */
18527 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
18530 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18531 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18532 rtx todec = gen_int_mode (-size, Pmode);
18535 if (INTVAL (todec) != -size)
18537 warning (0, "stack frame too large");
18538 emit_insn (gen_trap ());
18542 if (crtl->limit_stack)
18544 if (REG_P (stack_limit_rtx)
18545 && REGNO (stack_limit_rtx) > 1
18546 && REGNO (stack_limit_rtx) <= 31)
18548 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18549 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18552 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18554 && DEFAULT_ABI == ABI_V4)
18556 rtx toload = gen_rtx_CONST (VOIDmode,
18557 gen_rtx_PLUS (Pmode,
18561 emit_insn (gen_elf_high (tmp_reg, toload));
18562 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18563 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18567 warning (0, "stack limit expression is not supported");
18573 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
18575 emit_move_insn (copy_reg, stack_reg);
18580 /* Need a note here so that try_split doesn't get confused. */
18581 if (get_last_insn () == NULL_RTX)
18582 emit_note (NOTE_INSN_DELETED);
18583 insn = emit_move_insn (tmp_reg, todec);
18584 try_split (PATTERN (insn), insn, 0);
18588 insn = emit_insn (TARGET_32BIT
18589 ? gen_movsi_update_stack (stack_reg, stack_reg,
18591 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18592 todec, stack_reg));
18593 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18594 it now and set the alias set/attributes. The above gen_*_update
18595 calls will generate a PARALLEL with the MEM set being the first
18597 par = PATTERN (insn);
18598 gcc_assert (GET_CODE (par) == PARALLEL);
18599 set = XVECEXP (par, 0, 0);
18600 gcc_assert (GET_CODE (set) == SET);
18601 mem = SET_DEST (set);
18602 gcc_assert (MEM_P (mem));
18603 MEM_NOTRAP_P (mem) = 1;
18604 set_mem_alias_set (mem, get_frame_alias_set ());
18606 RTX_FRAME_RELATED_P (insn) = 1;
18607 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18608 gen_rtx_SET (VOIDmode, stack_reg,
18609 gen_rtx_PLUS (Pmode, stack_reg,
18610 GEN_INT (-size))));
18613 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18615 #if PROBE_INTERVAL > 32768
18616 #error Cannot use indexed addressing mode for stack probing
18619 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18620 inclusive. These are offsets from the current stack pointer. */
18623 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18625 /* See if we have a constant small number of probes to generate. If so,
18626 that's the easy case. */
18627 if (first + size <= 32768)
18631 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18632 it exceeds SIZE. If only one probe is needed, this will not
18633 generate any code. Then probe at FIRST + SIZE. */
18634 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18635 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18638 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18642 /* Otherwise, do the same as above, but in a loop. Note that we must be
18643 extra careful with variables wrapping around because we might be at
18644 the very top (or the very bottom) of the address space and we have
18645 to be able to handle this case properly; in particular, we use an
18646 equality test for the loop condition. */
18649 HOST_WIDE_INT rounded_size;
18650 rtx r12 = gen_rtx_REG (Pmode, 12);
18651 rtx r0 = gen_rtx_REG (Pmode, 0);
18653 /* Sanity check for the addressing mode we're going to use. */
18654 gcc_assert (first <= 32768);
18656 /* Step 1: round SIZE to the previous multiple of the interval. */
18658 rounded_size = size & -PROBE_INTERVAL;
18661 /* Step 2: compute initial and final value of the loop counter. */
18663 /* TEST_ADDR = SP + FIRST. */
18664 emit_insn (gen_rtx_SET (VOIDmode, r12,
18665 plus_constant (Pmode, stack_pointer_rtx,
18668 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18669 if (rounded_size > 32768)
18671 emit_move_insn (r0, GEN_INT (-rounded_size));
18672 emit_insn (gen_rtx_SET (VOIDmode, r0,
18673 gen_rtx_PLUS (Pmode, r12, r0)));
18676 emit_insn (gen_rtx_SET (VOIDmode, r0,
18677 plus_constant (Pmode, r12, -rounded_size)));
18680 /* Step 3: the loop
18682 while (TEST_ADDR != LAST_ADDR)
18684 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18688 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18689 until it is equal to ROUNDED_SIZE. */
18692 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18694 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18697 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18698 that SIZE is equal to ROUNDED_SIZE. */
18700 if (size != rounded_size)
18701 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
18705 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18706 absolute addresses. */
18709 output_probe_stack_range (rtx reg1, rtx reg2)
18711 static int labelno = 0;
18712 char loop_lab[32], end_lab[32];
18715 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18716 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18718 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18720 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18724 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
18726 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
18728 fputs ("\tbeq 0,", asm_out_file);
18729 assemble_name_raw (asm_out_file, end_lab);
18730 fputc ('\n', asm_out_file);
18732 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18733 xops[1] = GEN_INT (-PROBE_INTERVAL);
18734 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
18736 /* Probe at TEST_ADDR and branch. */
18737 xops[1] = gen_rtx_REG (Pmode, 0);
18738 output_asm_insn ("{st|stw} %1,0(%0)", xops);
18739 fprintf (asm_out_file, "\tb ");
18740 assemble_name_raw (asm_out_file, loop_lab);
18741 fputc ('\n', asm_out_file);
18743 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18748 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18749 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18750 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18751 deduce these equivalences by itself so it wasn't necessary to hold
18752 its hand so much. Don't be tempted to always supply d2_f_d_e with
18753 the actual cfa register, ie. r31 when we are using a hard frame
18754 pointer. That fails when saving regs off r1, and sched moves the
18755 r31 setup past the reg saves. */
18758 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18759 rtx reg2, rtx rreg)
18763 if (REGNO (reg) == STACK_POINTER_REGNUM && reg2 == NULL_RTX)
18765 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
18768 gcc_checking_assert (val == 0);
18769 real = PATTERN (insn);
18770 if (GET_CODE (real) == PARALLEL)
18771 for (i = 0; i < XVECLEN (real, 0); i++)
18772 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18774 rtx set = XVECEXP (real, 0, i);
18776 RTX_FRAME_RELATED_P (set) = 1;
18778 RTX_FRAME_RELATED_P (insn) = 1;
18782 /* copy_rtx will not make unique copies of registers, so we need to
18783 ensure we don't have unwanted sharing here. */
18785 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18788 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18790 real = copy_rtx (PATTERN (insn));
18792 if (reg2 != NULL_RTX)
18793 real = replace_rtx (real, reg2, rreg);
18795 if (REGNO (reg) == STACK_POINTER_REGNUM)
18796 gcc_checking_assert (val == 0);
18798 real = replace_rtx (real, reg,
18799 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
18800 STACK_POINTER_REGNUM),
18803 /* We expect that 'real' is either a SET or a PARALLEL containing
18804 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18805 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18807 if (GET_CODE (real) == SET)
18811 temp = simplify_rtx (SET_SRC (set));
18813 SET_SRC (set) = temp;
18814 temp = simplify_rtx (SET_DEST (set));
18816 SET_DEST (set) = temp;
18817 if (GET_CODE (SET_DEST (set)) == MEM)
18819 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18821 XEXP (SET_DEST (set), 0) = temp;
18828 gcc_assert (GET_CODE (real) == PARALLEL);
18829 for (i = 0; i < XVECLEN (real, 0); i++)
18830 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18832 rtx set = XVECEXP (real, 0, i);
18834 temp = simplify_rtx (SET_SRC (set));
18836 SET_SRC (set) = temp;
18837 temp = simplify_rtx (SET_DEST (set));
18839 SET_DEST (set) = temp;
18840 if (GET_CODE (SET_DEST (set)) == MEM)
18842 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18844 XEXP (SET_DEST (set), 0) = temp;
18846 RTX_FRAME_RELATED_P (set) = 1;
18850 RTX_FRAME_RELATED_P (insn) = 1;
18851 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
18856 /* Returns an insn that has a vrsave set operation with the
18857 appropriate CLOBBERs. */
18860 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
18863 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
18864 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
18867 = gen_rtx_SET (VOIDmode,
18869 gen_rtx_UNSPEC_VOLATILE (SImode,
18870 gen_rtvec (2, reg, vrsave),
18871 UNSPECV_SET_VRSAVE));
18875 /* We need to clobber the registers in the mask so the scheduler
18876 does not move sets to VRSAVE before sets of AltiVec registers.
18878 However, if the function receives nonlocal gotos, reload will set
18879 all call saved registers live. We will end up with:
18881 (set (reg 999) (mem))
18882 (parallel [ (set (reg vrsave) (unspec blah))
18883 (clobber (reg 999))])
18885 The clobber will cause the store into reg 999 to be dead, and
18886 flow will attempt to delete an epilogue insn. In this case, we
18887 need an unspec use/set of the register. */
18889 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
18890 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
18892 if (!epiloguep || call_used_regs [i])
18893 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
18894 gen_rtx_REG (V4SImode, i));
18897 rtx reg = gen_rtx_REG (V4SImode, i);
18900 = gen_rtx_SET (VOIDmode,
18902 gen_rtx_UNSPEC (V4SImode,
18903 gen_rtvec (1, reg), 27));
18907 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
18909 for (i = 0; i < nclobs; ++i)
18910 XVECEXP (insn, 0, i) = clobs[i];
18916 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
18920 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
18921 mem = gen_frame_mem (GET_MODE (reg), addr);
18922 return gen_rtx_SET (VOIDmode, store ? mem : reg, store ? reg : mem);
18926 gen_frame_load (rtx reg, rtx frame_reg, int offset)
18928 return gen_frame_set (reg, frame_reg, offset, false);
18932 gen_frame_store (rtx reg, rtx frame_reg, int offset)
18934 return gen_frame_set (reg, frame_reg, offset, true);
18937 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18938 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18941 emit_frame_save (rtx frame_reg, enum machine_mode mode,
18942 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
18946 /* Some cases that need register indexed addressing. */
18947 gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
18948 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
18949 || (TARGET_E500_DOUBLE && mode == DFmode)
18951 && SPE_VECTOR_MODE (mode)
18952 && !SPE_CONST_OFFSET_OK (offset))));
18954 reg = gen_rtx_REG (mode, regno);
18955 insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
18956 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
18957 NULL_RTX, NULL_RTX);
18960 /* Emit an offset memory reference suitable for a frame store, while
18961 converting to a valid addressing mode. */
18964 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
18966 rtx int_rtx, offset_rtx;
18968 int_rtx = GEN_INT (offset);
18970 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
18971 || (TARGET_E500_DOUBLE && mode == DFmode))
18973 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
18974 emit_move_insn (offset_rtx, int_rtx);
18977 offset_rtx = int_rtx;
18979 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
18982 #ifndef TARGET_FIX_AND_CONTINUE
18983 #define TARGET_FIX_AND_CONTINUE 0
18986 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
18987 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
18988 #define LAST_SAVRES_REGISTER 31
18989 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19000 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
19002 /* Temporary holding space for an out-of-line register save/restore
19004 static char savres_routine_name[30];
19006 /* Return the name for an out-of-line register save/restore routine.
19007 We are saving/restoring GPRs if GPR is true. */
19010 rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
19012 const char *prefix = "";
19013 const char *suffix = "";
19015 /* Different targets are supposed to define
19016 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19017 routine name could be defined with:
19019 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19021 This is a nice idea in practice, but in reality, things are
19022 complicated in several ways:
19024 - ELF targets have save/restore routines for GPRs.
19026 - SPE targets use different prefixes for 32/64-bit registers, and
19027 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19029 - PPC64 ELF targets have routines for save/restore of GPRs that
19030 differ in what they do with the link register, so having a set
19031 prefix doesn't work. (We only use one of the save routines at
19032 the moment, though.)
19034 - PPC32 elf targets have "exit" versions of the restore routines
19035 that restore the link register and can save some extra space.
19036 These require an extra suffix. (There are also "tail" versions
19037 of the restore routines and "GOT" versions of the save routines,
19038 but we don't generate those at present. Same problems apply,
19041 We deal with all this by synthesizing our own prefix/suffix and
19042 using that for the simple sprintf call shown above. */
19045 /* No floating point saves on the SPE. */
19046 gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
19048 if ((sel & SAVRES_SAVE))
19049 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19051 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19053 if ((sel & SAVRES_LR))
19056 else if (DEFAULT_ABI == ABI_V4)
19061 if ((sel & SAVRES_REG) == SAVRES_GPR)
19062 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
19063 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19064 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
19065 else if ((sel & SAVRES_REG) == SAVRES_VR)
19066 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19070 if ((sel & SAVRES_LR))
19073 else if (DEFAULT_ABI == ABI_AIX)
19075 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19076 /* No out-of-line save/restore routines for GPRs on AIX. */
19077 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
19081 if ((sel & SAVRES_REG) == SAVRES_GPR)
19082 prefix = ((sel & SAVRES_SAVE)
19083 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
19084 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
19085 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19087 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19088 if ((sel & SAVRES_LR))
19089 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
19093 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19094 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19097 else if ((sel & SAVRES_REG) == SAVRES_VR)
19098 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19103 if (DEFAULT_ABI == ABI_DARWIN)
19105 /* The Darwin approach is (slightly) different, in order to be
19106 compatible with code generated by the system toolchain. There is a
19107 single symbol for the start of save sequence, and the code here
19108 embeds an offset into that code on the basis of the first register
19110 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
19111 if ((sel & SAVRES_REG) == SAVRES_GPR)
19112 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
19113 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
19114 (regno - 13) * 4, prefix, regno);
19115 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19116 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
19117 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
19118 else if ((sel & SAVRES_REG) == SAVRES_VR)
19119 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
19120 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
19125 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19127 return savres_routine_name;
19130 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19131 We are saving/restoring GPRs if GPR is true. */
19134 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
19136 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
19137 ? info->first_gp_reg_save
19138 : (sel & SAVRES_REG) == SAVRES_FPR
19139 ? info->first_fp_reg_save - 32
19140 : (sel & SAVRES_REG) == SAVRES_VR
19141 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
19146 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
19147 versions of the gpr routines. */
19148 if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
19149 && info->spe_64bit_regs_used)
19150 select ^= SAVRES_FPR ^ SAVRES_GPR;
19152 /* Don't generate bogus routine names. */
19153 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19154 && regno <= LAST_SAVRES_REGISTER
19155 && select >= 0 && select <= 12);
19157 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19163 name = rs6000_savres_routine_name (info, regno, sel);
19165 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19166 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19167 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19173 /* Emit a sequence of insns, including a stack tie if needed, for
19174 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
19175 reset the stack pointer, but move the base of the frame into
19176 reg UPDT_REGNO for use by out-of-line register restore routines. */
19179 rs6000_emit_stack_reset (rs6000_stack_t *info,
19180 rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
19181 unsigned updt_regno)
19185 /* This blockage is needed so that sched doesn't decide to move
19186 the sp change before the register restores. */
19187 if (DEFAULT_ABI == ABI_V4
19189 && info->spe_64bit_regs_used != 0
19190 && info->first_gp_reg_save != 32))
19191 rs6000_emit_stack_tie (frame_reg_rtx, frame_pointer_needed);
19193 /* If we are restoring registers out-of-line, we will be using the
19194 "exit" variants of the restore routines, which will reset the
19195 stack for us. But we do need to point updt_reg into the
19196 right place for those routines. */
19197 updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
19199 if (frame_off != 0)
19200 return emit_insn (gen_add3_insn (updt_reg_rtx,
19201 frame_reg_rtx, GEN_INT (frame_off)));
19202 else if (REGNO (frame_reg_rtx) != updt_regno)
19203 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
19208 /* Return the register number used as a pointer by out-of-line
19209 save/restore functions. */
19211 static inline unsigned
19212 ptr_regno_for_savres (int sel)
19214 if (DEFAULT_ABI == ABI_AIX)
19215 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
19216 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
19219 /* Construct a parallel rtx describing the effect of a call to an
19220 out-of-line register save/restore routine, and emit the insn
19221 or jump_insn as appropriate. */
19224 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19225 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
19226 enum machine_mode reg_mode, int sel)
19229 int offset, start_reg, end_reg, n_regs, use_reg;
19230 int reg_size = GET_MODE_SIZE (reg_mode);
19236 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19237 ? info->first_gp_reg_save
19238 : (sel & SAVRES_REG) == SAVRES_FPR
19239 ? info->first_fp_reg_save
19240 : (sel & SAVRES_REG) == SAVRES_VR
19241 ? info->first_altivec_reg_save
19243 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19245 : (sel & SAVRES_REG) == SAVRES_FPR
19247 : (sel & SAVRES_REG) == SAVRES_VR
19248 ? LAST_ALTIVEC_REGNO + 1
19250 n_regs = end_reg - start_reg;
19251 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
19252 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
19255 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19256 RTVEC_ELT (p, offset++) = ret_rtx;
19258 RTVEC_ELT (p, offset++)
19259 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19261 sym = rs6000_savres_routine_sym (info, sel);
19262 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19264 use_reg = ptr_regno_for_savres (sel);
19265 if ((sel & SAVRES_REG) == SAVRES_VR)
19267 /* Vector regs are saved/restored using [reg+reg] addressing. */
19268 RTVEC_ELT (p, offset++)
19269 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19270 RTVEC_ELT (p, offset++)
19271 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
19274 RTVEC_ELT (p, offset++)
19275 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19277 for (i = 0; i < end_reg - start_reg; i++)
19278 RTVEC_ELT (p, i + offset)
19279 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
19280 frame_reg_rtx, save_area_offset + reg_size * i,
19281 (sel & SAVRES_SAVE) != 0);
19283 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19284 RTVEC_ELT (p, i + offset)
19285 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
19287 par = gen_rtx_PARALLEL (VOIDmode, p);
19289 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19291 insn = emit_jump_insn (par);
19292 JUMP_LABEL (insn) = ret_rtx;
19295 insn = emit_insn (par);
19299 /* Determine whether the gp REG is really used. */
19302 rs6000_reg_live_or_pic_offset_p (int reg)
19304 /* If the function calls eh_return, claim used all the registers that would
19305 be checked for liveness otherwise. This is required for the PIC offset
19306 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19307 register allocation purposes in this case. */
19309 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19310 && (!call_used_regs[reg]
19311 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19312 && !TARGET_SINGLE_PIC_BASE
19313 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19314 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19315 && !TARGET_SINGLE_PIC_BASE
19316 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19317 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19320 /* Emit function prologue as insns. */
19323 rs6000_emit_prologue (void)
19325 rs6000_stack_t *info = rs6000_stack_info ();
19326 enum machine_mode reg_mode = Pmode;
19327 int reg_size = TARGET_32BIT ? 4 : 8;
19328 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19329 rtx frame_reg_rtx = sp_reg_rtx;
19330 unsigned int cr_save_regno;
19331 rtx cr_save_rtx = NULL_RTX;
19334 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19335 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19336 && call_used_regs[STATIC_CHAIN_REGNUM]);
19337 /* Offset to top of frame for frame_reg and sp respectively. */
19338 HOST_WIDE_INT frame_off = 0;
19339 HOST_WIDE_INT sp_off = 0;
19341 #ifdef ENABLE_CHECKING
19342 /* Track and check usage of r0, r11, r12. */
19343 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
19344 #define START_USE(R) do \
19346 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19347 reg_inuse |= 1 << (R); \
19349 #define END_USE(R) do \
19351 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
19352 reg_inuse &= ~(1 << (R)); \
19354 #define NOT_INUSE(R) do \
19356 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19359 #define START_USE(R) do {} while (0)
19360 #define END_USE(R) do {} while (0)
19361 #define NOT_INUSE(R) do {} while (0)
19364 if (flag_stack_usage_info)
19365 current_function_static_stack_size = info->total_size;
19367 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19368 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19370 if (TARGET_FIX_AND_CONTINUE)
19372 /* gdb on darwin arranges to forward a function from the old
19373 address by modifying the first 5 instructions of the function
19374 to branch to the overriding function. This is necessary to
19375 permit function pointers that point to the old function to
19376 actually forward to the new function. */
19377 emit_insn (gen_nop ());
19378 emit_insn (gen_nop ());
19379 emit_insn (gen_nop ());
19380 emit_insn (gen_nop ());
19381 emit_insn (gen_nop ());
19384 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19386 reg_mode = V2SImode;
19390 /* Handle world saves specially here. */
19391 if (WORLD_SAVE_P (info))
19398 /* save_world expects lr in r0. */
19399 reg0 = gen_rtx_REG (Pmode, 0);
19400 if (info->lr_save_p)
19402 insn = emit_move_insn (reg0,
19403 gen_rtx_REG (Pmode, LR_REGNO));
19404 RTX_FRAME_RELATED_P (insn) = 1;
19407 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19408 assumptions about the offsets of various bits of the stack
19410 gcc_assert (info->gp_save_offset == -220
19411 && info->fp_save_offset == -144
19412 && info->lr_save_offset == 8
19413 && info->cr_save_offset == 4
19416 && (!crtl->calls_eh_return
19417 || info->ehrd_offset == -432)
19418 && info->vrsave_save_offset == -224
19419 && info->altivec_save_offset == -416);
19421 treg = gen_rtx_REG (SImode, 11);
19422 emit_move_insn (treg, GEN_INT (-info->total_size));
19424 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19425 in R11. It also clobbers R12, so beware! */
19427 /* Preserve CR2 for save_world prologues */
19429 sz += 32 - info->first_gp_reg_save;
19430 sz += 64 - info->first_fp_reg_save;
19431 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19432 p = rtvec_alloc (sz);
19434 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19435 gen_rtx_REG (SImode,
19437 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19438 gen_rtx_SYMBOL_REF (Pmode,
19440 /* We do floats first so that the instruction pattern matches
19442 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19444 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19446 info->first_fp_reg_save + i),
19448 info->fp_save_offset + frame_off + 8 * i);
19449 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19451 = gen_frame_store (gen_rtx_REG (V4SImode,
19452 info->first_altivec_reg_save + i),
19454 info->altivec_save_offset + frame_off + 16 * i);
19455 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19457 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19459 info->gp_save_offset + frame_off + reg_size * i);
19461 /* CR register traditionally saved as CR2. */
19463 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
19464 frame_reg_rtx, info->cr_save_offset + frame_off);
19465 /* Explain about use of R0. */
19466 if (info->lr_save_p)
19468 = gen_frame_store (reg0,
19469 frame_reg_rtx, info->lr_save_offset + frame_off);
19470 /* Explain what happens to the stack pointer. */
19472 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19473 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19476 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19477 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19478 treg, GEN_INT (-info->total_size));
19479 sp_off = frame_off = info->total_size;
19482 strategy = info->savres_strategy;
19484 /* For V.4, update stack before we do any saving and set back pointer. */
19485 if (! WORLD_SAVE_P (info)
19487 && (DEFAULT_ABI == ABI_V4
19488 || crtl->calls_eh_return))
19490 bool need_r11 = (TARGET_SPE
19491 ? (!(strategy & SAVE_INLINE_GPRS)
19492 && info->spe_64bit_regs_used == 0)
19493 : (!(strategy & SAVE_INLINE_FPRS)
19494 || !(strategy & SAVE_INLINE_GPRS)
19495 || !(strategy & SAVE_INLINE_VRS)));
19496 int ptr_regno = -1;
19497 rtx ptr_reg = NULL_RTX;
19500 if (info->total_size < 32767)
19501 frame_off = info->total_size;
19504 else if (info->cr_save_p
19506 || info->first_fp_reg_save < 64
19507 || info->first_gp_reg_save < 32
19508 || info->altivec_size != 0
19509 || info->vrsave_mask != 0
19510 || crtl->calls_eh_return)
19514 /* The prologue won't be saving any regs so there is no need
19515 to set up a frame register to access any frame save area.
19516 We also won't be using frame_off anywhere below, but set
19517 the correct value anyway to protect against future
19518 changes to this function. */
19519 frame_off = info->total_size;
19521 if (ptr_regno != -1)
19523 /* Set up the frame offset to that needed by the first
19524 out-of-line save function. */
19525 START_USE (ptr_regno);
19526 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19527 frame_reg_rtx = ptr_reg;
19528 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
19529 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
19530 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
19531 ptr_off = info->gp_save_offset + info->gp_size;
19532 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
19533 ptr_off = info->altivec_save_offset + info->altivec_size;
19534 frame_off = -ptr_off;
19536 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19537 sp_off = info->total_size;
19538 if (frame_reg_rtx != sp_reg_rtx)
19539 rs6000_emit_stack_tie (frame_reg_rtx, false);
19542 /* If we use the link register, get it into r0. */
19543 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19545 rtx addr, reg, mem;
19547 reg = gen_rtx_REG (Pmode, 0);
19549 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
19550 RTX_FRAME_RELATED_P (insn) = 1;
19552 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19553 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19555 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19556 GEN_INT (info->lr_save_offset + frame_off));
19557 mem = gen_rtx_MEM (Pmode, addr);
19558 /* This should not be of rs6000_sr_alias_set, because of
19559 __builtin_return_address. */
19561 insn = emit_move_insn (mem, reg);
19562 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19563 NULL_RTX, NULL_RTX);
19568 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
19569 r12 will be needed by out-of-line gpr restore. */
19570 cr_save_regno = (DEFAULT_ABI == ABI_AIX
19571 && !(strategy & (SAVE_INLINE_GPRS
19572 | SAVE_NOINLINE_GPRS_SAVES_LR))
19574 if (!WORLD_SAVE_P (info)
19576 && REGNO (frame_reg_rtx) != cr_save_regno
19577 && !(using_static_chain_p && cr_save_regno == 11))
19581 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
19582 START_USE (cr_save_regno);
19583 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19584 RTX_FRAME_RELATED_P (insn) = 1;
19585 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19586 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19587 But that's OK. All we have to do is specify that _one_ condition
19588 code register is saved in this stack slot. The thrower's epilogue
19589 will then restore all the call-saved registers.
19590 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19591 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19592 gen_rtx_REG (SImode, CR2_REGNO));
19593 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19596 /* Do any required saving of fpr's. If only one or two to save, do
19597 it ourselves. Otherwise, call function. */
19598 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
19601 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19602 if (save_reg_p (info->first_fp_reg_save + i))
19603 emit_frame_save (frame_reg_rtx,
19604 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19605 ? DFmode : SFmode),
19606 info->first_fp_reg_save + i,
19607 info->fp_save_offset + frame_off + 8 * i,
19608 sp_off - frame_off);
19610 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19612 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
19613 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
19614 unsigned ptr_regno = ptr_regno_for_savres (sel);
19615 rtx ptr_reg = frame_reg_rtx;
19617 if (REGNO (frame_reg_rtx) == ptr_regno)
19618 gcc_checking_assert (frame_off == 0);
19621 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19622 NOT_INUSE (ptr_regno);
19623 emit_insn (gen_add3_insn (ptr_reg,
19624 frame_reg_rtx, GEN_INT (frame_off)));
19626 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19627 info->fp_save_offset,
19628 info->lr_save_offset,
19630 rs6000_frame_related (insn, ptr_reg, sp_off,
19631 NULL_RTX, NULL_RTX);
19636 /* Save GPRs. This is done as a PARALLEL if we are using
19637 the store-multiple instructions. */
19638 if (!WORLD_SAVE_P (info)
19640 && info->spe_64bit_regs_used != 0
19641 && info->first_gp_reg_save != 32)
19644 rtx spe_save_area_ptr;
19645 HOST_WIDE_INT save_off;
19646 int ool_adjust = 0;
19648 /* Determine whether we can address all of the registers that need
19649 to be saved with an offset from frame_reg_rtx that fits in
19650 the small const field for SPE memory instructions. */
19651 int spe_regs_addressable
19652 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
19653 + reg_size * (32 - info->first_gp_reg_save - 1))
19654 && (strategy & SAVE_INLINE_GPRS));
19656 if (spe_regs_addressable)
19658 spe_save_area_ptr = frame_reg_rtx;
19659 save_off = frame_off;
19663 /* Make r11 point to the start of the SPE save area. We need
19664 to be careful here if r11 is holding the static chain. If
19665 it is, then temporarily save it in r0. */
19666 HOST_WIDE_INT offset;
19668 if (!(strategy & SAVE_INLINE_GPRS))
19669 ool_adjust = 8 * (info->first_gp_reg_save
19670 - (FIRST_SAVRES_REGISTER + 1));
19671 offset = info->spe_gp_save_offset + frame_off - ool_adjust;
19672 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19673 save_off = frame_off - offset;
19675 if (using_static_chain_p)
19677 rtx r0 = gen_rtx_REG (Pmode, 0);
19680 gcc_assert (info->first_gp_reg_save > 11);
19682 emit_move_insn (r0, spe_save_area_ptr);
19684 else if (REGNO (frame_reg_rtx) != 11)
19687 emit_insn (gen_addsi3 (spe_save_area_ptr,
19688 frame_reg_rtx, GEN_INT (offset)));
19689 if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
19690 frame_off = -info->spe_gp_save_offset + ool_adjust;
19693 if ((strategy & SAVE_INLINE_GPRS))
19695 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19696 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19697 emit_frame_save (spe_save_area_ptr, reg_mode,
19698 info->first_gp_reg_save + i,
19699 (info->spe_gp_save_offset + save_off
19701 sp_off - save_off);
19705 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19706 info->spe_gp_save_offset + save_off,
19708 SAVRES_SAVE | SAVRES_GPR);
19710 rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
19711 NULL_RTX, NULL_RTX);
19714 /* Move the static chain pointer back. */
19715 if (!spe_regs_addressable)
19717 if (using_static_chain_p)
19719 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19722 else if (REGNO (frame_reg_rtx) != 11)
19726 else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
19728 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
19729 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
19730 unsigned ptr_regno = ptr_regno_for_savres (sel);
19731 rtx ptr_reg = frame_reg_rtx;
19732 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
19733 int end_save = info->gp_save_offset + info->gp_size;
19737 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19739 /* Need to adjust r11 (r12) if we saved any FPRs. */
19740 if (end_save + frame_off != 0)
19742 rtx offset = GEN_INT (end_save + frame_off);
19745 frame_off = -end_save;
19747 NOT_INUSE (ptr_regno);
19748 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
19750 else if (!ptr_set_up)
19752 NOT_INUSE (ptr_regno);
19753 emit_move_insn (ptr_reg, frame_reg_rtx);
19755 ptr_off = -end_save;
19756 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19757 info->gp_save_offset + ptr_off,
19758 info->lr_save_offset + ptr_off,
19760 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
19761 NULL_RTX, NULL_RTX);
19765 else if (!WORLD_SAVE_P (info) && (strategy & SAVRES_MULTIPLE))
19769 p = rtvec_alloc (32 - info->first_gp_reg_save);
19770 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19772 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19774 info->gp_save_offset + frame_off + reg_size * i);
19775 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19776 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19777 NULL_RTX, NULL_RTX);
19779 else if (!WORLD_SAVE_P (info))
19782 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19783 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19784 emit_frame_save (frame_reg_rtx, reg_mode,
19785 info->first_gp_reg_save + i,
19786 info->gp_save_offset + frame_off + reg_size * i,
19787 sp_off - frame_off);
19790 if (crtl->calls_eh_return)
19797 unsigned int regno = EH_RETURN_DATA_REGNO (i);
19798 if (regno == INVALID_REGNUM)
19802 p = rtvec_alloc (i);
19806 unsigned int regno = EH_RETURN_DATA_REGNO (i);
19807 if (regno == INVALID_REGNUM)
19811 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
19813 info->ehrd_offset + sp_off + reg_size * (int) i);
19814 RTVEC_ELT (p, i) = insn;
19815 RTX_FRAME_RELATED_P (insn) = 1;
19818 insn = emit_insn (gen_blockage ());
19819 RTX_FRAME_RELATED_P (insn) = 1;
19820 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
19823 /* In AIX ABI we need to make sure r2 is really saved. */
19824 if (TARGET_AIX && crtl->calls_eh_return)
19826 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
19827 rtx save_insn, join_insn, note;
19828 long toc_restore_insn;
19830 tmp_reg = gen_rtx_REG (Pmode, 11);
19831 tmp_reg_si = gen_rtx_REG (SImode, 11);
19832 if (using_static_chain_p)
19835 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
19839 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
19840 /* Peek at instruction to which this function returns. If it's
19841 restoring r2, then we know we've already saved r2. We can't
19842 unconditionally save r2 because the value we have will already
19843 be updated if we arrived at this function via a plt call or
19844 toc adjusting stub. */
19845 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
19846 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
19847 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
19848 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
19849 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
19850 validate_condition_mode (EQ, CCUNSmode);
19851 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
19852 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19853 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
19854 toc_save_done = gen_label_rtx ();
19855 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
19856 gen_rtx_EQ (VOIDmode, compare_result,
19858 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
19860 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
19861 JUMP_LABEL (jump) = toc_save_done;
19862 LABEL_NUSES (toc_save_done) += 1;
19864 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
19865 TOC_REGNUM, frame_off + 5 * reg_size,
19866 sp_off - frame_off);
19868 emit_label (toc_save_done);
19870 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19871 have a CFG that has different saves along different paths.
19872 Move the note to a dummy blockage insn, which describes that
19873 R2 is unconditionally saved after the label. */
19874 /* ??? An alternate representation might be a special insn pattern
19875 containing both the branch and the store. That might let the
19876 code that minimizes the number of DW_CFA_advance opcodes better
19877 freedom in placing the annotations. */
19878 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
19880 remove_note (save_insn, note);
19882 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
19883 copy_rtx (PATTERN (save_insn)), NULL_RTX);
19884 RTX_FRAME_RELATED_P (save_insn) = 0;
19886 join_insn = emit_insn (gen_blockage ());
19887 REG_NOTES (join_insn) = note;
19888 RTX_FRAME_RELATED_P (join_insn) = 1;
19890 if (using_static_chain_p)
19892 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
19899 /* Save CR if we use any that must be preserved. */
19900 if (!WORLD_SAVE_P (info) && info->cr_save_p)
19902 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19903 GEN_INT (info->cr_save_offset + frame_off));
19904 rtx mem = gen_frame_mem (SImode, addr);
19905 /* See the large comment above about why CR2_REGNO is used. */
19906 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
19908 /* If we didn't copy cr before, do so now using r0. */
19909 if (cr_save_rtx == NULL_RTX)
19914 cr_save_rtx = gen_rtx_REG (SImode, 0);
19915 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19916 RTX_FRAME_RELATED_P (insn) = 1;
19917 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
19918 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19920 insn = emit_move_insn (mem, cr_save_rtx);
19921 END_USE (REGNO (cr_save_rtx));
19923 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19924 NULL_RTX, NULL_RTX);
19927 /* Update stack and set back pointer unless this is V.4,
19928 for which it was done previously. */
19929 if (!WORLD_SAVE_P (info) && info->push_p
19930 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
19932 rtx ptr_reg = NULL;
19935 /* If saving altivec regs we need to be able to address all save
19936 locations using a 16-bit offset. */
19937 if ((strategy & SAVE_INLINE_VRS) == 0
19938 || (info->altivec_size != 0
19939 && (info->altivec_save_offset + info->altivec_size - 16
19940 + info->total_size - frame_off) > 32767)
19941 || (info->vrsave_mask != 0
19942 && (info->vrsave_save_offset
19943 + info->total_size - frame_off) > 32767))
19945 int sel = SAVRES_SAVE | SAVRES_VR;
19946 unsigned ptr_regno = ptr_regno_for_savres (sel);
19948 if (using_static_chain_p
19949 && ptr_regno == STATIC_CHAIN_REGNUM)
19951 if (REGNO (frame_reg_rtx) != ptr_regno)
19952 START_USE (ptr_regno);
19953 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19954 frame_reg_rtx = ptr_reg;
19955 ptr_off = info->altivec_save_offset + info->altivec_size;
19956 frame_off = -ptr_off;
19958 else if (REGNO (frame_reg_rtx) == 1)
19959 frame_off = info->total_size;
19960 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19961 sp_off = info->total_size;
19962 if (frame_reg_rtx != sp_reg_rtx)
19963 rs6000_emit_stack_tie (frame_reg_rtx, false);
19966 /* Set frame pointer, if needed. */
19967 if (frame_pointer_needed)
19969 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
19971 RTX_FRAME_RELATED_P (insn) = 1;
19974 /* Save AltiVec registers if needed. Save here because the red zone does
19975 not always include AltiVec registers. */
19976 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
19977 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
19979 int end_save = info->altivec_save_offset + info->altivec_size;
19981 /* Oddly, the vector save/restore functions point r0 at the end
19982 of the save area, then use r11 or r12 to load offsets for
19983 [reg+reg] addressing. */
19984 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
19985 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
19986 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
19988 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
19990 if (end_save + frame_off != 0)
19992 rtx offset = GEN_INT (end_save + frame_off);
19994 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
19997 emit_move_insn (ptr_reg, frame_reg_rtx);
19999 ptr_off = -end_save;
20000 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20001 info->altivec_save_offset + ptr_off,
20002 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
20003 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
20004 NULL_RTX, NULL_RTX);
20005 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20007 /* The oddity mentioned above clobbered our frame reg. */
20008 emit_move_insn (frame_reg_rtx, ptr_reg);
20009 frame_off = ptr_off;
20012 else if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
20013 && info->altivec_size != 0)
20017 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20018 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20020 rtx areg, savereg, mem;
20023 offset = (info->altivec_save_offset + frame_off
20024 + 16 * (i - info->first_altivec_reg_save));
20026 savereg = gen_rtx_REG (V4SImode, i);
20029 areg = gen_rtx_REG (Pmode, 0);
20030 emit_move_insn (areg, GEN_INT (offset));
20032 /* AltiVec addressing mode is [reg+reg]. */
20033 mem = gen_frame_mem (V4SImode,
20034 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
20036 insn = emit_move_insn (mem, savereg);
20038 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20039 areg, GEN_INT (offset));
20043 /* VRSAVE is a bit vector representing which AltiVec registers
20044 are used. The OS uses this to determine which vector
20045 registers to save on a context switch. We need to save
20046 VRSAVE on the stack frame, add whatever AltiVec registers we
20047 used in this function, and do the corresponding magic in the
20050 if (!WORLD_SAVE_P (info)
20052 && TARGET_ALTIVEC_VRSAVE
20053 && info->vrsave_mask != 0)
20059 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
20060 be using r12 as frame_reg_rtx and r11 as the static chain
20061 pointer for nested functions. */
20063 if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
20065 else if (REGNO (frame_reg_rtx) == 12)
20068 if (using_static_chain_p)
20072 NOT_INUSE (save_regno);
20073 reg = gen_rtx_REG (SImode, save_regno);
20074 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
20076 emit_insn (gen_get_vrsave_internal (reg));
20078 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
20081 offset = info->vrsave_save_offset + frame_off;
20082 insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
20084 /* Include the registers in the mask. */
20085 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
20087 insn = emit_insn (generate_set_vrsave (reg, info, 0));
20090 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
20091 if (!TARGET_SINGLE_PIC_BASE
20092 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
20093 || (DEFAULT_ABI == ABI_V4
20094 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
20095 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
20097 /* If emit_load_toc_table will use the link register, we need to save
20098 it. We use R12 for this purpose because emit_load_toc_table
20099 can use register 0. This allows us to use a plain 'blr' to return
20100 from the procedure more often. */
20101 int save_LR_around_toc_setup = (TARGET_ELF
20102 && DEFAULT_ABI != ABI_AIX
20104 && ! info->lr_save_p
20105 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
20106 if (save_LR_around_toc_setup)
20108 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20109 rtx tmp = gen_rtx_REG (Pmode, 12);
20111 insn = emit_move_insn (tmp, lr);
20112 RTX_FRAME_RELATED_P (insn) = 1;
20114 rs6000_emit_load_toc_table (TRUE);
20116 insn = emit_move_insn (lr, tmp);
20117 add_reg_note (insn, REG_CFA_RESTORE, lr);
20118 RTX_FRAME_RELATED_P (insn) = 1;
20121 rs6000_emit_load_toc_table (TRUE);
20125 if (!TARGET_SINGLE_PIC_BASE
20126 && DEFAULT_ABI == ABI_DARWIN
20127 && flag_pic && crtl->uses_pic_offset_table)
20129 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20130 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
20132 /* Save and restore LR locally around this call (in R0). */
20133 if (!info->lr_save_p)
20134 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
20136 emit_insn (gen_load_macho_picbase (src));
20138 emit_move_insn (gen_rtx_REG (Pmode,
20139 RS6000_PIC_OFFSET_TABLE_REGNUM),
20142 if (!info->lr_save_p)
20143 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
20147 /* If we need to, save the TOC register after doing the stack setup.
20148 Do not emit eh frame info for this save. The unwinder wants info,
20149 conceptually attached to instructions in this function, about
20150 register values in the caller of this function. This R2 may have
20151 already been changed from the value in the caller.
20152 We don't attempt to write accurate DWARF EH frame info for R2
20153 because code emitted by gcc for a (non-pointer) function call
20154 doesn't save and restore R2. Instead, R2 is managed out-of-line
20155 by a linker generated plt call stub when the function resides in
20156 a shared library. This behaviour is costly to describe in DWARF,
20157 both in terms of the size of DWARF info and the time taken in the
20158 unwinder to interpret it. R2 changes, apart from the
20159 calls_eh_return case earlier in this function, are handled by
20160 linux-unwind.h frob_update_context. */
20161 if (rs6000_save_toc_in_prologue_p ())
20163 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
20164 emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));
20168 /* Write function prologue. */
20171 rs6000_output_function_prologue (FILE *file,
20172 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20174 rs6000_stack_t *info = rs6000_stack_info ();
20176 if (TARGET_DEBUG_STACK)
20177 debug_stack_info (info);
20179 /* Write .extern for any function we will call to save and restore
20181 if (info->first_fp_reg_save < 64
20186 int regno = info->first_fp_reg_save - 32;
20188 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20190 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
20191 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
20192 name = rs6000_savres_routine_name (info, regno, sel);
20193 fprintf (file, "\t.extern %s\n", name);
20195 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20197 bool lr = (info->savres_strategy
20198 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20199 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20200 name = rs6000_savres_routine_name (info, regno, sel);
20201 fprintf (file, "\t.extern %s\n", name);
20205 /* Write .extern for AIX common mode routines, if needed. */
20206 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
20208 fputs ("\t.extern __mulh\n", file);
20209 fputs ("\t.extern __mull\n", file);
20210 fputs ("\t.extern __divss\n", file);
20211 fputs ("\t.extern __divus\n", file);
20212 fputs ("\t.extern __quoss\n", file);
20213 fputs ("\t.extern __quous\n", file);
20214 common_mode_defined = 1;
20217 rs6000_pic_labelno++;
20220 /* Non-zero if vmx regs are restored before the frame pop, zero if
20221 we restore after the pop when possible. */
20222 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20224 /* Restoring cr is a two step process: loading a reg from the frame
20225 save, then moving the reg to cr. For ABI_V4 we must let the
20226 unwinder know that the stack location is no longer valid at or
20227 before the stack deallocation, but we can't emit a cfa_restore for
20228 cr at the stack deallocation like we do for other registers.
20229 The trouble is that it is possible for the move to cr to be
20230 scheduled after the stack deallocation. So say exactly where cr
20231 is located on each of the two insns. */
20234 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
20236 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
20237 rtx reg = gen_rtx_REG (SImode, regno);
20238 rtx insn = emit_move_insn (reg, mem);
20240 if (!exit_func && DEFAULT_ABI == ABI_V4)
20242 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20243 rtx set = gen_rtx_SET (VOIDmode, reg, cr);
20245 add_reg_note (insn, REG_CFA_REGISTER, set);
20246 RTX_FRAME_RELATED_P (insn) = 1;
20251 /* Reload CR from REG. */
20254 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
20259 if (using_mfcr_multiple)
20261 for (i = 0; i < 8; i++)
20262 if (save_reg_p (CR0_REGNO + i))
20264 gcc_assert (count);
20267 if (using_mfcr_multiple && count > 1)
20272 p = rtvec_alloc (count);
20275 for (i = 0; i < 8; i++)
20276 if (save_reg_p (CR0_REGNO + i))
20278 rtvec r = rtvec_alloc (2);
20279 RTVEC_ELT (r, 0) = reg;
20280 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20281 RTVEC_ELT (p, ndx) =
20282 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i),
20283 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20286 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20287 gcc_assert (ndx == count);
20290 for (i = 0; i < 8; i++)
20291 if (save_reg_p (CR0_REGNO + i))
20292 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),
20295 if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20297 rtx insn = get_last_insn ();
20298 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20300 add_reg_note (insn, REG_CFA_RESTORE, cr);
20301 RTX_FRAME_RELATED_P (insn) = 1;
20305 /* Like cr, the move to lr instruction can be scheduled after the
20306 stack deallocation, but unlike cr, its stack frame save is still
20307 valid. So we only need to emit the cfa_restore on the correct
20311 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
20313 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
20314 rtx reg = gen_rtx_REG (Pmode, regno);
20316 emit_move_insn (reg, mem);
20320 restore_saved_lr (int regno, bool exit_func)
20322 rtx reg = gen_rtx_REG (Pmode, regno);
20323 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20324 rtx insn = emit_move_insn (lr, reg);
20326 if (!exit_func && flag_shrink_wrap)
20328 add_reg_note (insn, REG_CFA_RESTORE, lr);
20329 RTX_FRAME_RELATED_P (insn) = 1;
20334 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
20336 if (info->cr_save_p)
20337 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20338 gen_rtx_REG (SImode, CR2_REGNO),
20340 if (info->lr_save_p)
20341 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20342 gen_rtx_REG (Pmode, LR_REGNO),
20344 return cfa_restores;
20347 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20348 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20349 below stack pointer not cloberred by signals. */
20352 offset_below_red_zone_p (HOST_WIDE_INT offset)
20354 return offset < (DEFAULT_ABI == ABI_V4
20356 : TARGET_32BIT ? -220 : -288);
20359 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20362 emit_cfa_restores (rtx cfa_restores)
20364 rtx insn = get_last_insn ();
20365 rtx *loc = ®_NOTES (insn);
20368 loc = &XEXP (*loc, 1);
20369 *loc = cfa_restores;
20370 RTX_FRAME_RELATED_P (insn) = 1;
20373 /* Emit function epilogue as insns. */
20376 rs6000_emit_epilogue (int sibcall)
20378 rs6000_stack_t *info;
20379 int restoring_GPRs_inline;
20380 int restoring_FPRs_inline;
20381 int using_load_multiple;
20382 int using_mtcr_multiple;
20383 int use_backchain_to_restore_sp;
20386 HOST_WIDE_INT frame_off = 0;
20387 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20388 rtx frame_reg_rtx = sp_reg_rtx;
20389 rtx cfa_restores = NULL_RTX;
20391 rtx cr_save_reg = NULL_RTX;
20392 enum machine_mode reg_mode = Pmode;
20393 int reg_size = TARGET_32BIT ? 4 : 8;
20396 unsigned ptr_regno;
20398 info = rs6000_stack_info ();
20400 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20402 reg_mode = V2SImode;
20406 strategy = info->savres_strategy;
20407 using_load_multiple = strategy & SAVRES_MULTIPLE;
20408 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20409 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20410 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20411 || rs6000_cpu == PROCESSOR_PPC603
20412 || rs6000_cpu == PROCESSOR_PPC750
20414 /* Restore via the backchain when we have a large frame, since this
20415 is more efficient than an addis, addi pair. The second condition
20416 here will not trigger at the moment; We don't actually need a
20417 frame pointer for alloca, but the generic parts of the compiler
20418 give us one anyway. */
20419 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20420 || (cfun->calls_alloca
20421 && !frame_pointer_needed));
20422 restore_lr = (info->lr_save_p
20423 && (restoring_FPRs_inline
20424 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20425 && (restoring_GPRs_inline
20426 || info->first_fp_reg_save < 64));
20428 if (WORLD_SAVE_P (info))
20432 const char *alloc_rname;
20435 /* eh_rest_world_r10 will return to the location saved in the LR
20436 stack slot (which is not likely to be our caller.)
20437 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20438 rest_world is similar, except any R10 parameter is ignored.
20439 The exception-handling stuff that was here in 2.95 is no
20440 longer necessary. */
20444 + 32 - info->first_gp_reg_save
20445 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20446 + 63 + 1 - info->first_fp_reg_save);
20448 strcpy (rname, ((crtl->calls_eh_return) ?
20449 "*eh_rest_world_r10" : "*rest_world"));
20450 alloc_rname = ggc_strdup (rname);
20453 RTVEC_ELT (p, j++) = ret_rtx;
20454 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20455 gen_rtx_REG (Pmode,
20458 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20459 /* The instruction pattern requires a clobber here;
20460 it is shared with the restVEC helper. */
20462 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20465 /* CR register traditionally saved as CR2. */
20466 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
20468 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
20469 if (flag_shrink_wrap)
20471 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20472 gen_rtx_REG (Pmode, LR_REGNO),
20474 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20478 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20480 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20482 = gen_frame_load (reg,
20483 frame_reg_rtx, info->gp_save_offset + reg_size * i);
20484 if (flag_shrink_wrap)
20485 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20487 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20489 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20491 = gen_frame_load (reg,
20492 frame_reg_rtx, info->altivec_save_offset + 16 * i);
20493 if (flag_shrink_wrap)
20494 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20496 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20498 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
20499 ? DFmode : SFmode),
20500 info->first_fp_reg_save + i);
20502 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
20503 if (flag_shrink_wrap)
20504 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20507 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20509 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20511 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20513 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20515 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20516 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20518 if (flag_shrink_wrap)
20520 REG_NOTES (insn) = cfa_restores;
20521 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20522 RTX_FRAME_RELATED_P (insn) = 1;
20527 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
20529 frame_off = info->total_size;
20531 /* Restore AltiVec registers if we must do so before adjusting the
20533 if (TARGET_ALTIVEC_ABI
20534 && info->altivec_size != 0
20535 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20536 || (DEFAULT_ABI != ABI_V4
20537 && offset_below_red_zone_p (info->altivec_save_offset))))
20540 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20542 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20543 if (use_backchain_to_restore_sp)
20545 int frame_regno = 11;
20547 if ((strategy & REST_INLINE_VRS) == 0)
20549 /* Of r11 and r12, select the one not clobbered by an
20550 out-of-line restore function for the frame register. */
20551 frame_regno = 11 + 12 - scratch_regno;
20553 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
20554 emit_move_insn (frame_reg_rtx,
20555 gen_rtx_MEM (Pmode, sp_reg_rtx));
20558 else if (frame_pointer_needed)
20559 frame_reg_rtx = hard_frame_pointer_rtx;
20561 if ((strategy & REST_INLINE_VRS) == 0)
20563 int end_save = info->altivec_save_offset + info->altivec_size;
20565 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20566 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20568 if (end_save + frame_off != 0)
20570 rtx offset = GEN_INT (end_save + frame_off);
20572 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20575 emit_move_insn (ptr_reg, frame_reg_rtx);
20577 ptr_off = -end_save;
20578 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20579 info->altivec_save_offset + ptr_off,
20580 0, V4SImode, SAVRES_VR);
20584 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20585 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20587 rtx addr, areg, mem, reg;
20589 areg = gen_rtx_REG (Pmode, 0);
20591 (areg, GEN_INT (info->altivec_save_offset
20593 + 16 * (i - info->first_altivec_reg_save)));
20595 /* AltiVec addressing mode is [reg+reg]. */
20596 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20597 mem = gen_frame_mem (V4SImode, addr);
20599 reg = gen_rtx_REG (V4SImode, i);
20600 emit_move_insn (reg, mem);
20604 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20605 if (((strategy & REST_INLINE_VRS) == 0
20606 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20607 && (flag_shrink_wrap
20608 || (offset_below_red_zone_p
20609 (info->altivec_save_offset
20610 + 16 * (i - info->first_altivec_reg_save)))))
20612 rtx reg = gen_rtx_REG (V4SImode, i);
20613 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20617 /* Restore VRSAVE if we must do so before adjusting the stack. */
20619 && TARGET_ALTIVEC_VRSAVE
20620 && info->vrsave_mask != 0
20621 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20622 || (DEFAULT_ABI != ABI_V4
20623 && offset_below_red_zone_p (info->vrsave_save_offset))))
20627 if (frame_reg_rtx == sp_reg_rtx)
20629 if (use_backchain_to_restore_sp)
20631 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20632 emit_move_insn (frame_reg_rtx,
20633 gen_rtx_MEM (Pmode, sp_reg_rtx));
20636 else if (frame_pointer_needed)
20637 frame_reg_rtx = hard_frame_pointer_rtx;
20640 reg = gen_rtx_REG (SImode, 12);
20641 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20642 info->vrsave_save_offset + frame_off));
20644 emit_insn (generate_set_vrsave (reg, info, 1));
20648 /* If we have a large stack frame, restore the old stack pointer
20649 using the backchain. */
20650 if (use_backchain_to_restore_sp)
20652 if (frame_reg_rtx == sp_reg_rtx)
20654 /* Under V.4, don't reset the stack pointer until after we're done
20655 loading the saved registers. */
20656 if (DEFAULT_ABI == ABI_V4)
20657 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20659 insn = emit_move_insn (frame_reg_rtx,
20660 gen_rtx_MEM (Pmode, sp_reg_rtx));
20663 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20664 && DEFAULT_ABI == ABI_V4)
20665 /* frame_reg_rtx has been set up by the altivec restore. */
20669 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20670 frame_reg_rtx = sp_reg_rtx;
20673 /* If we have a frame pointer, we can restore the old stack pointer
20675 else if (frame_pointer_needed)
20677 frame_reg_rtx = sp_reg_rtx;
20678 if (DEFAULT_ABI == ABI_V4)
20679 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20680 /* Prevent reordering memory accesses against stack pointer restore. */
20681 else if (cfun->calls_alloca
20682 || offset_below_red_zone_p (-info->total_size))
20683 rs6000_emit_stack_tie (frame_reg_rtx, true);
20685 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20686 GEN_INT (info->total_size)));
20689 else if (info->push_p
20690 && DEFAULT_ABI != ABI_V4
20691 && !crtl->calls_eh_return)
20693 /* Prevent reordering memory accesses against stack pointer restore. */
20694 if (cfun->calls_alloca
20695 || offset_below_red_zone_p (-info->total_size))
20696 rs6000_emit_stack_tie (frame_reg_rtx, false);
20697 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20698 GEN_INT (info->total_size)));
20701 if (insn && frame_reg_rtx == sp_reg_rtx)
20705 REG_NOTES (insn) = cfa_restores;
20706 cfa_restores = NULL_RTX;
20708 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20709 RTX_FRAME_RELATED_P (insn) = 1;
20712 /* Restore AltiVec registers if we have not done so already. */
20713 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20714 && TARGET_ALTIVEC_ABI
20715 && info->altivec_size != 0
20716 && (DEFAULT_ABI == ABI_V4
20717 || !offset_below_red_zone_p (info->altivec_save_offset)))
20721 if ((strategy & REST_INLINE_VRS) == 0)
20723 int end_save = info->altivec_save_offset + info->altivec_size;
20725 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20726 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20727 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20729 if (end_save + frame_off != 0)
20731 rtx offset = GEN_INT (end_save + frame_off);
20733 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20736 emit_move_insn (ptr_reg, frame_reg_rtx);
20738 ptr_off = -end_save;
20739 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20740 info->altivec_save_offset + ptr_off,
20741 0, V4SImode, SAVRES_VR);
20742 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20744 /* Frame reg was clobbered by out-of-line save. Restore it
20745 from ptr_reg, and if we are calling out-of-line gpr or
20746 fpr restore set up the correct pointer and offset. */
20747 unsigned newptr_regno = 1;
20748 if (!restoring_GPRs_inline)
20750 bool lr = info->gp_save_offset + info->gp_size == 0;
20751 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
20752 newptr_regno = ptr_regno_for_savres (sel);
20753 end_save = info->gp_save_offset + info->gp_size;
20755 else if (!restoring_FPRs_inline)
20757 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
20758 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20759 newptr_regno = ptr_regno_for_savres (sel);
20760 end_save = info->gp_save_offset + info->gp_size;
20763 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
20764 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
20766 if (end_save + ptr_off != 0)
20768 rtx offset = GEN_INT (end_save + ptr_off);
20770 frame_off = -end_save;
20771 emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
20775 frame_off = ptr_off;
20776 emit_move_insn (frame_reg_rtx, ptr_reg);
20782 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20783 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20785 rtx addr, areg, mem, reg;
20787 areg = gen_rtx_REG (Pmode, 0);
20789 (areg, GEN_INT (info->altivec_save_offset
20791 + 16 * (i - info->first_altivec_reg_save)));
20793 /* AltiVec addressing mode is [reg+reg]. */
20794 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20795 mem = gen_frame_mem (V4SImode, addr);
20797 reg = gen_rtx_REG (V4SImode, i);
20798 emit_move_insn (reg, mem);
20802 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20803 if (((strategy & REST_INLINE_VRS) == 0
20804 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20805 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20807 rtx reg = gen_rtx_REG (V4SImode, i);
20808 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20812 /* Restore VRSAVE if we have not done so already. */
20813 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20815 && TARGET_ALTIVEC_VRSAVE
20816 && info->vrsave_mask != 0
20817 && (DEFAULT_ABI == ABI_V4
20818 || !offset_below_red_zone_p (info->vrsave_save_offset)))
20822 reg = gen_rtx_REG (SImode, 12);
20823 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20824 info->vrsave_save_offset + frame_off));
20826 emit_insn (generate_set_vrsave (reg, info, 1));
20829 /* If we exit by an out-of-line restore function on ABI_V4 then that
20830 function will deallocate the stack, so we don't need to worry
20831 about the unwinder restoring cr from an invalid stack frame
20833 exit_func = (!restoring_FPRs_inline
20834 || (!restoring_GPRs_inline
20835 && info->first_fp_reg_save == 64));
20837 /* Get the old lr if we saved it. If we are restoring registers
20838 out-of-line, then the out-of-line routines can do this for us. */
20839 if (restore_lr && restoring_GPRs_inline)
20840 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
20842 /* Get the old cr if we saved it. */
20843 if (info->cr_save_p)
20845 unsigned cr_save_regno = 12;
20847 if (!restoring_GPRs_inline)
20849 /* Ensure we don't use the register used by the out-of-line
20850 gpr register restore below. */
20851 bool lr = info->gp_save_offset + info->gp_size == 0;
20852 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
20853 int gpr_ptr_regno = ptr_regno_for_savres (sel);
20855 if (gpr_ptr_regno == 12)
20856 cr_save_regno = 11;
20857 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
20859 else if (REGNO (frame_reg_rtx) == 12)
20860 cr_save_regno = 11;
20862 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
20863 info->cr_save_offset + frame_off,
20867 /* Set LR here to try to overlap restores below. */
20868 if (restore_lr && restoring_GPRs_inline)
20869 restore_saved_lr (0, exit_func);
20871 /* Load exception handler data registers, if needed. */
20872 if (crtl->calls_eh_return)
20874 unsigned int i, regno;
20878 rtx reg = gen_rtx_REG (reg_mode, 2);
20879 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20880 frame_off + 5 * reg_size));
20887 regno = EH_RETURN_DATA_REGNO (i);
20888 if (regno == INVALID_REGNUM)
20891 /* Note: possible use of r0 here to address SPE regs. */
20892 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
20893 info->ehrd_offset + frame_off
20894 + reg_size * (int) i);
20896 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
20900 /* Restore GPRs. This is done as a PARALLEL if we are using
20901 the load-multiple instructions. */
20903 && info->spe_64bit_regs_used
20904 && info->first_gp_reg_save != 32)
20906 /* Determine whether we can address all of the registers that need
20907 to be saved with an offset from frame_reg_rtx that fits in
20908 the small const field for SPE memory instructions. */
20909 int spe_regs_addressable
20910 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
20911 + reg_size * (32 - info->first_gp_reg_save - 1))
20912 && restoring_GPRs_inline);
20914 if (!spe_regs_addressable)
20916 int ool_adjust = 0;
20917 rtx old_frame_reg_rtx = frame_reg_rtx;
20918 /* Make r11 point to the start of the SPE save area. We worried about
20919 not clobbering it when we were saving registers in the prologue.
20920 There's no need to worry here because the static chain is passed
20921 anew to every function. */
20923 if (!restoring_GPRs_inline)
20924 ool_adjust = 8 * (info->first_gp_reg_save
20925 - (FIRST_SAVRES_REGISTER + 1));
20926 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20927 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
20928 GEN_INT (info->spe_gp_save_offset
20931 /* Keep the invariant that frame_reg_rtx + frame_off points
20932 at the top of the stack frame. */
20933 frame_off = -info->spe_gp_save_offset + ool_adjust;
20936 if (restoring_GPRs_inline)
20938 HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
20940 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20941 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20943 rtx offset, addr, mem, reg;
20945 /* We're doing all this to ensure that the immediate offset
20946 fits into the immediate field of 'evldd'. */
20947 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
20949 offset = GEN_INT (spe_offset + reg_size * i);
20950 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
20951 mem = gen_rtx_MEM (V2SImode, addr);
20952 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20954 emit_move_insn (reg, mem);
20958 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20959 info->spe_gp_save_offset + frame_off,
20960 info->lr_save_offset + frame_off,
20962 SAVRES_GPR | SAVRES_LR);
20964 else if (!restoring_GPRs_inline)
20966 /* We are jumping to an out-of-line function. */
20968 int end_save = info->gp_save_offset + info->gp_size;
20969 bool can_use_exit = end_save == 0;
20970 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
20973 /* Emit stack reset code if we need it. */
20974 ptr_regno = ptr_regno_for_savres (sel);
20975 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
20977 rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
20978 else if (end_save + frame_off != 0)
20979 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
20980 GEN_INT (end_save + frame_off)));
20981 else if (REGNO (frame_reg_rtx) != ptr_regno)
20982 emit_move_insn (ptr_reg, frame_reg_rtx);
20983 if (REGNO (frame_reg_rtx) == ptr_regno)
20984 frame_off = -end_save;
20986 if (can_use_exit && info->cr_save_p)
20987 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
20989 ptr_off = -end_save;
20990 rs6000_emit_savres_rtx (info, ptr_reg,
20991 info->gp_save_offset + ptr_off,
20992 info->lr_save_offset + ptr_off,
20995 else if (using_load_multiple)
20998 p = rtvec_alloc (32 - info->first_gp_reg_save);
20999 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21001 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21003 info->gp_save_offset + frame_off + reg_size * i);
21004 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
21008 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21009 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
21010 emit_insn (gen_frame_load
21011 (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21013 info->gp_save_offset + frame_off + reg_size * i));
21016 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21018 /* If the frame pointer was used then we can't delay emitting
21019 a REG_CFA_DEF_CFA note. This must happen on the insn that
21020 restores the frame pointer, r31. We may have already emitted
21021 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
21022 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
21023 be harmless if emitted. */
21024 if (frame_pointer_needed)
21026 insn = get_last_insn ();
21027 add_reg_note (insn, REG_CFA_DEF_CFA,
21028 plus_constant (Pmode, frame_reg_rtx, frame_off));
21029 RTX_FRAME_RELATED_P (insn) = 1;
21032 /* Set up cfa_restores. We always need these when
21033 shrink-wrapping. If not shrink-wrapping then we only need
21034 the cfa_restore when the stack location is no longer valid.
21035 The cfa_restores must be emitted on or before the insn that
21036 invalidates the stack, and of course must not be emitted
21037 before the insn that actually does the restore. The latter
21038 is why it is a bad idea to emit the cfa_restores as a group
21039 on the last instruction here that actually does a restore:
21040 That insn may be reordered with respect to others doing
21042 if (flag_shrink_wrap
21043 && !restoring_GPRs_inline
21044 && info->first_fp_reg_save == 64)
21045 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21047 for (i = info->first_gp_reg_save; i < 32; i++)
21048 if (!restoring_GPRs_inline
21049 || using_load_multiple
21050 || rs6000_reg_live_or_pic_offset_p (i))
21052 rtx reg = gen_rtx_REG (reg_mode, i);
21054 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21058 if (!restoring_GPRs_inline
21059 && info->first_fp_reg_save == 64)
21061 /* We are jumping to an out-of-line function. */
21063 emit_cfa_restores (cfa_restores);
21067 if (restore_lr && !restoring_GPRs_inline)
21069 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
21070 restore_saved_lr (0, exit_func);
21073 /* Restore fpr's if we need to do it without calling a function. */
21074 if (restoring_FPRs_inline)
21075 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21076 if (save_reg_p (info->first_fp_reg_save + i))
21078 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
21079 ? DFmode : SFmode),
21080 info->first_fp_reg_save + i);
21081 emit_insn (gen_frame_load (reg, frame_reg_rtx,
21082 info->fp_save_offset + frame_off + 8 * i));
21083 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21084 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21087 /* If we saved cr, restore it here. Just those that were used. */
21088 if (info->cr_save_p)
21089 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
21091 /* If this is V.4, unwind the stack pointer after all of the loads
21092 have been done, or set up r11 if we are restoring fp out of line. */
21094 if (!restoring_FPRs_inline)
21096 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21097 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
21098 ptr_regno = ptr_regno_for_savres (sel);
21101 insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
21102 if (REGNO (frame_reg_rtx) == ptr_regno)
21105 if (insn && restoring_FPRs_inline)
21109 REG_NOTES (insn) = cfa_restores;
21110 cfa_restores = NULL_RTX;
21112 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
21113 RTX_FRAME_RELATED_P (insn) = 1;
21116 if (crtl->calls_eh_return)
21118 rtx sa = EH_RETURN_STACKADJ_RTX;
21119 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
21125 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21126 if (! restoring_FPRs_inline)
21128 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
21129 RTVEC_ELT (p, 0) = ret_rtx;
21135 /* We can't hang the cfa_restores off a simple return,
21136 since the shrink-wrap code sometimes uses an existing
21137 return. This means there might be a path from
21138 pre-prologue code to this return, and dwarf2cfi code
21139 wants the eh_frame unwinder state to be the same on
21140 all paths to any point. So we need to emit the
21141 cfa_restores before the return. For -m64 we really
21142 don't need epilogue cfa_restores at all, except for
21143 this irritating dwarf2cfi with shrink-wrap
21144 requirement; The stack red-zone means eh_frame info
21145 from the prologue telling the unwinder to restore
21146 from the stack is perfectly good right to the end of
21148 emit_insn (gen_blockage ());
21149 emit_cfa_restores (cfa_restores);
21150 cfa_restores = NULL_RTX;
21152 p = rtvec_alloc (2);
21153 RTVEC_ELT (p, 0) = simple_return_rtx;
21156 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
21157 ? gen_rtx_USE (VOIDmode,
21158 gen_rtx_REG (Pmode, LR_REGNO))
21159 : gen_rtx_CLOBBER (VOIDmode,
21160 gen_rtx_REG (Pmode, LR_REGNO)));
21162 /* If we have to restore more than two FP registers, branch to the
21163 restore function. It will return to our caller. */
21164 if (! restoring_FPRs_inline)
21169 if (flag_shrink_wrap)
21170 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21172 sym = rs6000_savres_routine_sym (info,
21173 SAVRES_FPR | (lr ? SAVRES_LR : 0));
21174 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
21175 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
21176 gen_rtx_REG (Pmode,
21177 DEFAULT_ABI == ABI_AIX
21179 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21181 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
21183 RTVEC_ELT (p, i + 4)
21184 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
21185 if (flag_shrink_wrap)
21186 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
21191 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
21197 /* Ensure the cfa_restores are hung off an insn that won't
21198 be reordered above other restores. */
21199 emit_insn (gen_blockage ());
21201 emit_cfa_restores (cfa_restores);
21205 /* Write function epilogue. */
21208 rs6000_output_function_epilogue (FILE *file,
21209 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
21212 macho_branch_islands ();
21213 /* Mach-O doesn't support labels at the end of objects, so if
21214 it looks like we might want one, insert a NOP. */
21216 rtx insn = get_last_insn ();
21217 rtx deleted_debug_label = NULL_RTX;
21220 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
21222 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21223 notes only, instead set their CODE_LABEL_NUMBER to -1,
21224 otherwise there would be code generation differences
21225 in between -g and -g0. */
21226 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21227 deleted_debug_label = insn;
21228 insn = PREV_INSN (insn);
21233 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
21234 fputs ("\tnop\n", file);
21235 else if (deleted_debug_label)
21236 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
21237 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21238 CODE_LABEL_NUMBER (insn) = -1;
21242 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21245 We don't output a traceback table if -finhibit-size-directive was
21246 used. The documentation for -finhibit-size-directive reads
21247 ``don't output a @code{.size} assembler directive, or anything
21248 else that would cause trouble if the function is split in the
21249 middle, and the two halves are placed at locations far apart in
21250 memory.'' The traceback table has this property, since it
21251 includes the offset from the start of the function to the
21252 traceback table itself.
21254 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21255 different traceback table. */
21256 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
21257 && rs6000_traceback != traceback_none && !cfun->is_thunk)
21259 const char *fname = NULL;
21260 const char *language_string = lang_hooks.name;
21261 int fixed_parms = 0, float_parms = 0, parm_info = 0;
21263 int optional_tbtab;
21264 rs6000_stack_t *info = rs6000_stack_info ();
21266 if (rs6000_traceback == traceback_full)
21267 optional_tbtab = 1;
21268 else if (rs6000_traceback == traceback_part)
21269 optional_tbtab = 0;
21271 optional_tbtab = !optimize_size && !TARGET_ELF;
21273 if (optional_tbtab)
21275 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
21276 while (*fname == '.') /* V.4 encodes . in the name */
21279 /* Need label immediately before tbtab, so we can compute
21280 its offset from the function start. */
21281 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21282 ASM_OUTPUT_LABEL (file, fname);
21285 /* The .tbtab pseudo-op can only be used for the first eight
21286 expressions, since it can't handle the possibly variable
21287 length fields that follow. However, if you omit the optional
21288 fields, the assembler outputs zeros for all optional fields
21289 anyways, giving each variable length field is minimum length
21290 (as defined in sys/debug.h). Thus we can not use the .tbtab
21291 pseudo-op at all. */
21293 /* An all-zero word flags the start of the tbtab, for debuggers
21294 that have to find it by searching forward from the entry
21295 point or from the current pc. */
21296 fputs ("\t.long 0\n", file);
21298 /* Tbtab format type. Use format type 0. */
21299 fputs ("\t.byte 0,", file);
21301 /* Language type. Unfortunately, there does not seem to be any
21302 official way to discover the language being compiled, so we
21303 use language_string.
21304 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21305 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21306 a number, so for now use 9. LTO and Go aren't assigned numbers
21307 either, so for now use 0. */
21308 if (! strcmp (language_string, "GNU C")
21309 || ! strcmp (language_string, "GNU GIMPLE")
21310 || ! strcmp (language_string, "GNU Go"))
21312 else if (! strcmp (language_string, "GNU F77")
21313 || ! strcmp (language_string, "GNU Fortran"))
21315 else if (! strcmp (language_string, "GNU Pascal"))
21317 else if (! strcmp (language_string, "GNU Ada"))
21319 else if (! strcmp (language_string, "GNU C++")
21320 || ! strcmp (language_string, "GNU Objective-C++"))
21322 else if (! strcmp (language_string, "GNU Java"))
21324 else if (! strcmp (language_string, "GNU Objective-C"))
21327 gcc_unreachable ();
21328 fprintf (file, "%d,", i);
21330 /* 8 single bit fields: global linkage (not set for C extern linkage,
21331 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21332 from start of procedure stored in tbtab, internal function, function
21333 has controlled storage, function has no toc, function uses fp,
21334 function logs/aborts fp operations. */
21335 /* Assume that fp operations are used if any fp reg must be saved. */
21336 fprintf (file, "%d,",
21337 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21339 /* 6 bitfields: function is interrupt handler, name present in
21340 proc table, function calls alloca, on condition directives
21341 (controls stack walks, 3 bits), saves condition reg, saves
21343 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21344 set up as a frame pointer, even when there is no alloca call. */
21345 fprintf (file, "%d,",
21346 ((optional_tbtab << 6)
21347 | ((optional_tbtab & frame_pointer_needed) << 5)
21348 | (info->cr_save_p << 1)
21349 | (info->lr_save_p)));
21351 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21353 fprintf (file, "%d,",
21354 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21356 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21357 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21359 if (optional_tbtab)
21361 /* Compute the parameter info from the function decl argument
21364 int next_parm_info_bit = 31;
21366 for (decl = DECL_ARGUMENTS (current_function_decl);
21367 decl; decl = DECL_CHAIN (decl))
21369 rtx parameter = DECL_INCOMING_RTL (decl);
21370 enum machine_mode mode = GET_MODE (parameter);
21372 if (GET_CODE (parameter) == REG)
21374 if (SCALAR_FLOAT_MODE_P (mode))
21395 gcc_unreachable ();
21398 /* If only one bit will fit, don't or in this entry. */
21399 if (next_parm_info_bit > 0)
21400 parm_info |= (bits << (next_parm_info_bit - 1));
21401 next_parm_info_bit -= 2;
21405 fixed_parms += ((GET_MODE_SIZE (mode)
21406 + (UNITS_PER_WORD - 1))
21408 next_parm_info_bit -= 1;
21414 /* Number of fixed point parameters. */
21415 /* This is actually the number of words of fixed point parameters; thus
21416 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21417 fprintf (file, "%d,", fixed_parms);
21419 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21421 /* This is actually the number of fp registers that hold parameters;
21422 and thus the maximum value is 13. */
21423 /* Set parameters on stack bit if parameters are not in their original
21424 registers, regardless of whether they are on the stack? Xlc
21425 seems to set the bit when not optimizing. */
21426 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21428 if (! optional_tbtab)
21431 /* Optional fields follow. Some are variable length. */
21433 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21434 11 double float. */
21435 /* There is an entry for each parameter in a register, in the order that
21436 they occur in the parameter list. Any intervening arguments on the
21437 stack are ignored. If the list overflows a long (max possible length
21438 34 bits) then completely leave off all elements that don't fit. */
21439 /* Only emit this long if there was at least one parameter. */
21440 if (fixed_parms || float_parms)
21441 fprintf (file, "\t.long %d\n", parm_info);
21443 /* Offset from start of code to tb table. */
21444 fputs ("\t.long ", file);
21445 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21446 RS6000_OUTPUT_BASENAME (file, fname);
21448 rs6000_output_function_entry (file, fname);
21451 /* Interrupt handler mask. */
21452 /* Omit this long, since we never set the interrupt handler bit
21455 /* Number of CTL (controlled storage) anchors. */
21456 /* Omit this long, since the has_ctl bit is never set above. */
21458 /* Displacement into stack of each CTL anchor. */
21459 /* Omit this list of longs, because there are no CTL anchors. */
21461 /* Length of function name. */
21464 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21466 /* Function name. */
21467 assemble_string (fname, strlen (fname));
21469 /* Register for alloca automatic storage; this is always reg 31.
21470 Only emit this if the alloca bit was set above. */
21471 if (frame_pointer_needed)
21472 fputs ("\t.byte 31\n", file);
21474 fputs ("\t.align 2\n", file);
21478 /* A C compound statement that outputs the assembler code for a thunk
21479 function, used to implement C++ virtual function calls with
21480 multiple inheritance. The thunk acts as a wrapper around a virtual
21481 function, adjusting the implicit object parameter before handing
21482 control off to the real function.
21484 First, emit code to add the integer DELTA to the location that
21485 contains the incoming first argument. Assume that this argument
21486 contains a pointer, and is the one used to pass the `this' pointer
21487 in C++. This is the incoming argument *before* the function
21488 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21489 values of all other incoming arguments.
21491 After the addition, emit code to jump to FUNCTION, which is a
21492 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21493 not touch the return address. Hence returning from FUNCTION will
21494 return to whoever called the current `thunk'.
21496 The effect must be as if FUNCTION had been called directly with the
21497 adjusted first argument. This macro is responsible for emitting
21498 all of the code for a thunk function; output_function_prologue()
21499 and output_function_epilogue() are not invoked.
21501 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21502 been extracted from it.) It might possibly be useful on some
21503 targets, but probably not.
21505 If you do not define this macro, the target-independent code in the
21506 C++ frontend will generate a less efficient heavyweight thunk that
21507 calls FUNCTION instead of jumping to it. The generic approach does
21508 not support varargs. */
21511 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21512 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21515 rtx this_rtx, insn, funexp;
21517 reload_completed = 1;
21518 epilogue_completed = 1;
21520 /* Mark the end of the (empty) prologue. */
21521 emit_note (NOTE_INSN_PROLOGUE_END);
21523 /* Find the "this" pointer. If the function returns a structure,
21524 the structure return pointer is in r3. */
21525 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21526 this_rtx = gen_rtx_REG (Pmode, 4);
21528 this_rtx = gen_rtx_REG (Pmode, 3);
21530 /* Apply the constant offset, if required. */
21532 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21534 /* Apply the offset from the vtable, if required. */
21537 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21538 rtx tmp = gen_rtx_REG (Pmode, 12);
21540 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21541 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21543 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21544 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21548 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21550 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21552 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21555 /* Generate a tail call to the target function. */
21556 if (!TREE_USED (function))
21558 assemble_external (function);
21559 TREE_USED (function) = 1;
21561 funexp = XEXP (DECL_RTL (function), 0);
21562 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21565 if (MACHOPIC_INDIRECT)
21566 funexp = machopic_indirect_call_target (funexp);
21569 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21570 generate sibcall RTL explicitly. */
21571 insn = emit_call_insn (
21572 gen_rtx_PARALLEL (VOIDmode,
21574 gen_rtx_CALL (VOIDmode,
21575 funexp, const0_rtx),
21576 gen_rtx_USE (VOIDmode, const0_rtx),
21577 gen_rtx_USE (VOIDmode,
21578 gen_rtx_REG (SImode,
21580 simple_return_rtx)));
21581 SIBLING_CALL_P (insn) = 1;
21584 /* Run just enough of rest_of_compilation to get the insns emitted.
21585 There's not really enough bulk here to make other passes such as
21586 instruction scheduling worth while. Note that use_thunk calls
21587 assemble_start_function and assemble_end_function. */
21588 insn = get_insns ();
21589 insn_locators_alloc ();
21590 shorten_branches (insn);
21591 final_start_function (insn, file, 1);
21592 final (insn, file, 1);
21593 final_end_function ();
21595 reload_completed = 0;
21596 epilogue_completed = 0;
21599 /* A quick summary of the various types of 'constant-pool tables'
21602 Target Flags Name One table per
21603 AIX (none) AIX TOC object file
21604 AIX -mfull-toc AIX TOC object file
21605 AIX -mminimal-toc AIX minimal TOC translation unit
21606 SVR4/EABI (none) SVR4 SDATA object file
21607 SVR4/EABI -fpic SVR4 pic object file
21608 SVR4/EABI -fPIC SVR4 PIC translation unit
21609 SVR4/EABI -mrelocatable EABI TOC function
21610 SVR4/EABI -maix AIX TOC object file
21611 SVR4/EABI -maix -mminimal-toc
21612 AIX minimal TOC translation unit
21614 Name Reg. Set by entries contains:
21615 made by addrs? fp? sum?
21617 AIX TOC 2 crt0 as Y option option
21618 AIX minimal TOC 30 prolog gcc Y Y option
21619 SVR4 SDATA 13 crt0 gcc N Y N
21620 SVR4 pic 30 prolog ld Y not yet N
21621 SVR4 PIC 30 prolog gcc Y option option
21622 EABI TOC 30 prolog gcc Y option option
21626 /* Hash functions for the hash table. */
21629 rs6000_hash_constant (rtx k)
21631 enum rtx_code code = GET_CODE (k);
21632 enum machine_mode mode = GET_MODE (k);
21633 unsigned result = (code << 3) ^ mode;
21634 const char *format;
21637 format = GET_RTX_FORMAT (code);
21638 flen = strlen (format);
21644 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21647 if (mode != VOIDmode)
21648 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21660 for (; fidx < flen; fidx++)
21661 switch (format[fidx])
21666 const char *str = XSTR (k, fidx);
21667 len = strlen (str);
21668 result = result * 613 + len;
21669 for (i = 0; i < len; i++)
21670 result = result * 613 + (unsigned) str[i];
21675 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21679 result = result * 613 + (unsigned) XINT (k, fidx);
21682 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21683 result = result * 613 + (unsigned) XWINT (k, fidx);
21687 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21688 result = result * 613 + (unsigned) (XWINT (k, fidx)
21695 gcc_unreachable ();
21702 toc_hash_function (const void *hash_entry)
21704 const struct toc_hash_struct *thc =
21705 (const struct toc_hash_struct *) hash_entry;
21706 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21709 /* Compare H1 and H2 for equivalence. */
21712 toc_hash_eq (const void *h1, const void *h2)
21714 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21715 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21717 if (((const struct toc_hash_struct *) h1)->key_mode
21718 != ((const struct toc_hash_struct *) h2)->key_mode)
21721 return rtx_equal_p (r1, r2);
21724 /* These are the names given by the C++ front-end to vtables, and
21725 vtable-like objects. Ideally, this logic should not be here;
21726 instead, there should be some programmatic way of inquiring as
21727 to whether or not an object is a vtable. */
21729 #define VTABLE_NAME_P(NAME) \
21730 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21731 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21732 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21733 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21734 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21736 #ifdef NO_DOLLAR_IN_LABEL
21737 /* Return a GGC-allocated character string translating dollar signs in
21738 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21741 rs6000_xcoff_strip_dollar (const char *name)
21747 q = (const char *) strchr (name, '$');
21749 if (q == 0 || q == name)
21752 len = strlen (name);
21753 strip = XALLOCAVEC (char, len + 1);
21754 strcpy (strip, name);
21755 p = strip + (q - name);
21759 p = strchr (p + 1, '$');
21762 return ggc_alloc_string (strip, len);
21767 rs6000_output_symbol_ref (FILE *file, rtx x)
21769 /* Currently C++ toc references to vtables can be emitted before it
21770 is decided whether the vtable is public or private. If this is
21771 the case, then the linker will eventually complain that there is
21772 a reference to an unknown section. Thus, for vtables only,
21773 we emit the TOC reference to reference the symbol and not the
21775 const char *name = XSTR (x, 0);
21777 if (VTABLE_NAME_P (name))
21779 RS6000_OUTPUT_BASENAME (file, name);
21782 assemble_name (file, name);
21785 /* Output a TOC entry. We derive the entry name from what is being
21789 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
21792 const char *name = buf;
21794 HOST_WIDE_INT offset = 0;
21796 gcc_assert (!TARGET_NO_TOC);
21798 /* When the linker won't eliminate them, don't output duplicate
21799 TOC entries (this happens on AIX if there is any kind of TOC,
21800 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21802 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
21804 struct toc_hash_struct *h;
21807 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21808 time because GGC is not initialized at that point. */
21809 if (toc_hash_table == NULL)
21810 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
21811 toc_hash_eq, NULL);
21813 h = ggc_alloc_toc_hash_struct ();
21815 h->key_mode = mode;
21816 h->labelno = labelno;
21818 found = htab_find_slot (toc_hash_table, h, INSERT);
21819 if (*found == NULL)
21821 else /* This is indeed a duplicate.
21822 Set this label equal to that label. */
21824 fputs ("\t.set ", file);
21825 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21826 fprintf (file, "%d,", labelno);
21827 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21828 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
21834 /* If we're going to put a double constant in the TOC, make sure it's
21835 aligned properly when strict alignment is on. */
21836 if (GET_CODE (x) == CONST_DOUBLE
21837 && STRICT_ALIGNMENT
21838 && GET_MODE_BITSIZE (mode) >= 64
21839 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
21840 ASM_OUTPUT_ALIGN (file, 3);
21843 (*targetm.asm_out.internal_label) (file, "LC", labelno);
21845 /* Handle FP constants specially. Note that if we have a minimal
21846 TOC, things we put here aren't actually in the TOC, so we can allow
21848 if (GET_CODE (x) == CONST_DOUBLE &&
21849 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
21851 REAL_VALUE_TYPE rv;
21854 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21855 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21856 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
21858 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
21862 if (TARGET_MINIMAL_TOC)
21863 fputs (DOUBLE_INT_ASM_OP, file);
21865 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21866 k[0] & 0xffffffff, k[1] & 0xffffffff,
21867 k[2] & 0xffffffff, k[3] & 0xffffffff);
21868 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
21869 k[0] & 0xffffffff, k[1] & 0xffffffff,
21870 k[2] & 0xffffffff, k[3] & 0xffffffff);
21875 if (TARGET_MINIMAL_TOC)
21876 fputs ("\t.long ", file);
21878 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21879 k[0] & 0xffffffff, k[1] & 0xffffffff,
21880 k[2] & 0xffffffff, k[3] & 0xffffffff);
21881 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21882 k[0] & 0xffffffff, k[1] & 0xffffffff,
21883 k[2] & 0xffffffff, k[3] & 0xffffffff);
21887 else if (GET_CODE (x) == CONST_DOUBLE &&
21888 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
21890 REAL_VALUE_TYPE rv;
21893 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21895 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21896 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
21898 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
21902 if (TARGET_MINIMAL_TOC)
21903 fputs (DOUBLE_INT_ASM_OP, file);
21905 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21906 k[0] & 0xffffffff, k[1] & 0xffffffff);
21907 fprintf (file, "0x%lx%08lx\n",
21908 k[0] & 0xffffffff, k[1] & 0xffffffff);
21913 if (TARGET_MINIMAL_TOC)
21914 fputs ("\t.long ", file);
21916 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21917 k[0] & 0xffffffff, k[1] & 0xffffffff);
21918 fprintf (file, "0x%lx,0x%lx\n",
21919 k[0] & 0xffffffff, k[1] & 0xffffffff);
21923 else if (GET_CODE (x) == CONST_DOUBLE &&
21924 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
21926 REAL_VALUE_TYPE rv;
21929 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21930 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21931 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
21933 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
21937 if (TARGET_MINIMAL_TOC)
21938 fputs (DOUBLE_INT_ASM_OP, file);
21940 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21941 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
21946 if (TARGET_MINIMAL_TOC)
21947 fputs ("\t.long ", file);
21949 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21950 fprintf (file, "0x%lx\n", l & 0xffffffff);
21954 else if (GET_MODE (x) == VOIDmode
21955 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
21957 unsigned HOST_WIDE_INT low;
21958 HOST_WIDE_INT high;
21960 if (GET_CODE (x) == CONST_DOUBLE)
21962 low = CONST_DOUBLE_LOW (x);
21963 high = CONST_DOUBLE_HIGH (x);
21966 #if HOST_BITS_PER_WIDE_INT == 32
21969 high = (low & 0x80000000) ? ~0 : 0;
21973 low = INTVAL (x) & 0xffffffff;
21974 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
21978 /* TOC entries are always Pmode-sized, but since this
21979 is a bigendian machine then if we're putting smaller
21980 integer constants in the TOC we have to pad them.
21981 (This is still a win over putting the constants in
21982 a separate constant pool, because then we'd have
21983 to have both a TOC entry _and_ the actual constant.)
21985 For a 32-bit target, CONST_INT values are loaded and shifted
21986 entirely within `low' and can be stored in one TOC entry. */
21988 /* It would be easy to make this work, but it doesn't now. */
21989 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
21991 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
21993 #if HOST_BITS_PER_WIDE_INT == 32
21994 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
21995 POINTER_SIZE, &low, &high, 0);
21998 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
21999 high = (HOST_WIDE_INT) low >> 32;
22006 if (TARGET_MINIMAL_TOC)
22007 fputs (DOUBLE_INT_ASM_OP, file);
22009 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22010 (long) high & 0xffffffff, (long) low & 0xffffffff);
22011 fprintf (file, "0x%lx%08lx\n",
22012 (long) high & 0xffffffff, (long) low & 0xffffffff);
22017 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
22019 if (TARGET_MINIMAL_TOC)
22020 fputs ("\t.long ", file);
22022 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22023 (long) high & 0xffffffff, (long) low & 0xffffffff);
22024 fprintf (file, "0x%lx,0x%lx\n",
22025 (long) high & 0xffffffff, (long) low & 0xffffffff);
22029 if (TARGET_MINIMAL_TOC)
22030 fputs ("\t.long ", file);
22032 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
22033 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
22039 if (GET_CODE (x) == CONST)
22041 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
22042 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
22044 base = XEXP (XEXP (x, 0), 0);
22045 offset = INTVAL (XEXP (XEXP (x, 0), 1));
22048 switch (GET_CODE (base))
22051 name = XSTR (base, 0);
22055 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
22056 CODE_LABEL_NUMBER (XEXP (base, 0)));
22060 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
22064 gcc_unreachable ();
22067 if (TARGET_MINIMAL_TOC)
22068 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
22071 fputs ("\t.tc ", file);
22072 RS6000_OUTPUT_BASENAME (file, name);
22075 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
22077 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
22079 fputs ("[TC],", file);
22082 /* Currently C++ toc references to vtables can be emitted before it
22083 is decided whether the vtable is public or private. If this is
22084 the case, then the linker will eventually complain that there is
22085 a TOC reference to an unknown section. Thus, for vtables only,
22086 we emit the TOC reference to reference the symbol and not the
22088 if (VTABLE_NAME_P (name))
22090 RS6000_OUTPUT_BASENAME (file, name);
22092 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
22093 else if (offset > 0)
22094 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
22097 output_addr_const (file, x);
22101 /* Output an assembler pseudo-op to write an ASCII string of N characters
22102 starting at P to FILE.
22104 On the RS/6000, we have to do this using the .byte operation and
22105 write out special characters outside the quoted string.
22106 Also, the assembler is broken; very long strings are truncated,
22107 so we must artificially break them up early. */
22110 output_ascii (FILE *file, const char *p, int n)
22113 int i, count_string;
22114 const char *for_string = "\t.byte \"";
22115 const char *for_decimal = "\t.byte ";
22116 const char *to_close = NULL;
22119 for (i = 0; i < n; i++)
22122 if (c >= ' ' && c < 0177)
22125 fputs (for_string, file);
22128 /* Write two quotes to get one. */
22136 for_decimal = "\"\n\t.byte ";
22140 if (count_string >= 512)
22142 fputs (to_close, file);
22144 for_string = "\t.byte \"";
22145 for_decimal = "\t.byte ";
22153 fputs (for_decimal, file);
22154 fprintf (file, "%d", c);
22156 for_string = "\n\t.byte \"";
22157 for_decimal = ", ";
22163 /* Now close the string if we have written one. Then end the line. */
22165 fputs (to_close, file);
22168 /* Generate a unique section name for FILENAME for a section type
22169 represented by SECTION_DESC. Output goes into BUF.
22171 SECTION_DESC can be any string, as long as it is different for each
22172 possible section type.
22174 We name the section in the same manner as xlc. The name begins with an
22175 underscore followed by the filename (after stripping any leading directory
22176 names) with the last period replaced by the string SECTION_DESC. If
22177 FILENAME does not contain a period, SECTION_DESC is appended to the end of
22181 rs6000_gen_section_name (char **buf, const char *filename,
22182 const char *section_desc)
22184 const char *q, *after_last_slash, *last_period = 0;
22188 after_last_slash = filename;
22189 for (q = filename; *q; q++)
22192 after_last_slash = q + 1;
22193 else if (*q == '.')
22197 len = strlen (after_last_slash) + strlen (section_desc) + 2;
22198 *buf = (char *) xmalloc (len);
22203 for (q = after_last_slash; *q; q++)
22205 if (q == last_period)
22207 strcpy (p, section_desc);
22208 p += strlen (section_desc);
22212 else if (ISALNUM (*q))
22216 if (last_period == 0)
22217 strcpy (p, section_desc);
22222 /* Emit profile function. */
22225 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
22227 /* Non-standard profiling for kernels, which just saves LR then calls
22228 _mcount without worrying about arg saves. The idea is to change
22229 the function prologue as little as possible as it isn't easy to
22230 account for arg save/restore code added just for _mcount. */
22231 if (TARGET_PROFILE_KERNEL)
22234 if (DEFAULT_ABI == ABI_AIX)
22236 #ifndef NO_PROFILE_COUNTERS
22237 # define NO_PROFILE_COUNTERS 0
22239 if (NO_PROFILE_COUNTERS)
22240 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22241 LCT_NORMAL, VOIDmode, 0);
22245 const char *label_name;
22248 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22249 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
22250 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
22252 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22253 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
22256 else if (DEFAULT_ABI == ABI_DARWIN)
22258 const char *mcount_name = RS6000_MCOUNT;
22259 int caller_addr_regno = LR_REGNO;
22261 /* Be conservative and always set this, at least for now. */
22262 crtl->uses_pic_offset_table = 1;
22265 /* For PIC code, set up a stub and collect the caller's address
22266 from r0, which is where the prologue puts it. */
22267 if (MACHOPIC_INDIRECT
22268 && crtl->uses_pic_offset_table)
22269 caller_addr_regno = 0;
22271 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
22272 LCT_NORMAL, VOIDmode, 1,
22273 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
22277 /* Write function profiler code. */
22280 output_function_profiler (FILE *file, int labelno)
22284 switch (DEFAULT_ABI)
22287 gcc_unreachable ();
22292 warning (0, "no profiling of 64-bit code for this ABI");
22295 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22296 fprintf (file, "\tmflr %s\n", reg_names[0]);
22297 if (NO_PROFILE_COUNTERS)
22299 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22300 reg_names[0], reg_names[1]);
22302 else if (TARGET_SECURE_PLT && flag_pic)
22304 if (TARGET_LINK_STACK)
22307 get_ppc476_thunk_name (name);
22308 asm_fprintf (file, "\tbl %s\n", name);
22311 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22312 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22313 reg_names[0], reg_names[1]);
22314 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22315 asm_fprintf (file, "\t{cau|addis} %s,%s,",
22316 reg_names[12], reg_names[12]);
22317 assemble_name (file, buf);
22318 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
22319 assemble_name (file, buf);
22320 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22322 else if (flag_pic == 1)
22324 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22325 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22326 reg_names[0], reg_names[1]);
22327 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22328 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
22329 assemble_name (file, buf);
22330 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22332 else if (flag_pic > 1)
22334 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22335 reg_names[0], reg_names[1]);
22336 /* Now, we need to get the address of the label. */
22337 if (TARGET_LINK_STACK)
22340 get_ppc476_thunk_name (name);
22341 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22342 assemble_name (file, buf);
22343 fputs ("-.\n1:", file);
22344 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22345 asm_fprintf (file, "\taddi %s,%s,4\n",
22346 reg_names[11], reg_names[11]);
22350 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22351 assemble_name (file, buf);
22352 fputs ("-.\n1:", file);
22353 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22355 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
22356 reg_names[0], reg_names[11]);
22357 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
22358 reg_names[0], reg_names[0], reg_names[11]);
22362 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
22363 assemble_name (file, buf);
22364 fputs ("@ha\n", file);
22365 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22366 reg_names[0], reg_names[1]);
22367 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
22368 assemble_name (file, buf);
22369 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22372 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22373 fprintf (file, "\tbl %s%s\n",
22374 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22379 if (!TARGET_PROFILE_KERNEL)
22381 /* Don't do anything, done in output_profile_hook (). */
22385 gcc_assert (!TARGET_32BIT);
22387 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22388 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22390 if (cfun->static_chain_decl != NULL)
22392 asm_fprintf (file, "\tstd %s,24(%s)\n",
22393 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22394 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22395 asm_fprintf (file, "\tld %s,24(%s)\n",
22396 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22399 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22407 /* The following variable value is the last issued insn. */
22409 static rtx last_scheduled_insn;
22411 /* The following variable helps to balance issuing of load and
22412 store instructions */
22414 static int load_store_pendulum;
22416 /* Power4 load update and store update instructions are cracked into a
22417 load or store and an integer insn which are executed in the same cycle.
22418 Branches have their own dispatch slot which does not count against the
22419 GCC issue rate, but it changes the program flow so there are no other
22420 instructions to issue in this cycle. */
22423 rs6000_variable_issue_1 (rtx insn, int more)
22425 last_scheduled_insn = insn;
22426 if (GET_CODE (PATTERN (insn)) == USE
22427 || GET_CODE (PATTERN (insn)) == CLOBBER)
22429 cached_can_issue_more = more;
22430 return cached_can_issue_more;
22433 if (insn_terminates_group_p (insn, current_group))
22435 cached_can_issue_more = 0;
22436 return cached_can_issue_more;
22439 /* If no reservation, but reach here */
22440 if (recog_memoized (insn) < 0)
22443 if (rs6000_sched_groups)
22445 if (is_microcoded_insn (insn))
22446 cached_can_issue_more = 0;
22447 else if (is_cracked_insn (insn))
22448 cached_can_issue_more = more > 2 ? more - 2 : 0;
22450 cached_can_issue_more = more - 1;
22452 return cached_can_issue_more;
22455 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22458 cached_can_issue_more = more - 1;
22459 return cached_can_issue_more;
22463 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22465 int r = rs6000_variable_issue_1 (insn, more);
22467 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22471 /* Adjust the cost of a scheduling dependency. Return the new cost of
22472 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22475 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22477 enum attr_type attr_type;
22479 if (! recog_memoized (insn))
22482 switch (REG_NOTE_KIND (link))
22486 /* Data dependency; DEP_INSN writes a register that INSN reads
22487 some cycles later. */
22489 /* Separate a load from a narrower, dependent store. */
22490 if (rs6000_sched_groups
22491 && GET_CODE (PATTERN (insn)) == SET
22492 && GET_CODE (PATTERN (dep_insn)) == SET
22493 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22494 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22495 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22496 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22499 attr_type = get_attr_type (insn);
22504 /* Tell the first scheduling pass about the latency between
22505 a mtctr and bctr (and mtlr and br/blr). The first
22506 scheduling pass will not know about this latency since
22507 the mtctr instruction, which has the latency associated
22508 to it, will be generated by reload. */
22509 return TARGET_POWER ? 5 : 4;
22511 /* Leave some extra cycles between a compare and its
22512 dependent branch, to inhibit expensive mispredicts. */
22513 if ((rs6000_cpu_attr == CPU_PPC603
22514 || rs6000_cpu_attr == CPU_PPC604
22515 || rs6000_cpu_attr == CPU_PPC604E
22516 || rs6000_cpu_attr == CPU_PPC620
22517 || rs6000_cpu_attr == CPU_PPC630
22518 || rs6000_cpu_attr == CPU_PPC750
22519 || rs6000_cpu_attr == CPU_PPC7400
22520 || rs6000_cpu_attr == CPU_PPC7450
22521 || rs6000_cpu_attr == CPU_PPCE5500
22522 || rs6000_cpu_attr == CPU_PPCE6500
22523 || rs6000_cpu_attr == CPU_POWER4
22524 || rs6000_cpu_attr == CPU_POWER5
22525 || rs6000_cpu_attr == CPU_POWER7
22526 || rs6000_cpu_attr == CPU_CELL)
22527 && recog_memoized (dep_insn)
22528 && (INSN_CODE (dep_insn) >= 0))
22530 switch (get_attr_type (dep_insn))
22534 case TYPE_DELAYED_COMPARE:
22535 case TYPE_IMUL_COMPARE:
22536 case TYPE_LMUL_COMPARE:
22537 case TYPE_FPCOMPARE:
22538 case TYPE_CR_LOGICAL:
22539 case TYPE_DELAYED_CR:
22548 case TYPE_STORE_UX:
22550 case TYPE_FPSTORE_U:
22551 case TYPE_FPSTORE_UX:
22552 if ((rs6000_cpu == PROCESSOR_POWER6)
22553 && recog_memoized (dep_insn)
22554 && (INSN_CODE (dep_insn) >= 0))
22557 if (GET_CODE (PATTERN (insn)) != SET)
22558 /* If this happens, we have to extend this to schedule
22559 optimally. Return default for now. */
22562 /* Adjust the cost for the case where the value written
22563 by a fixed point operation is used as the address
22564 gen value on a store. */
22565 switch (get_attr_type (dep_insn))
22572 if (! store_data_bypass_p (dep_insn, insn))
22576 case TYPE_LOAD_EXT:
22577 case TYPE_LOAD_EXT_U:
22578 case TYPE_LOAD_EXT_UX:
22579 case TYPE_VAR_SHIFT_ROTATE:
22580 case TYPE_VAR_DELAYED_COMPARE:
22582 if (! store_data_bypass_p (dep_insn, insn))
22588 case TYPE_FAST_COMPARE:
22591 case TYPE_INSERT_WORD:
22592 case TYPE_INSERT_DWORD:
22593 case TYPE_FPLOAD_U:
22594 case TYPE_FPLOAD_UX:
22596 case TYPE_STORE_UX:
22597 case TYPE_FPSTORE_U:
22598 case TYPE_FPSTORE_UX:
22600 if (! store_data_bypass_p (dep_insn, insn))
22608 case TYPE_IMUL_COMPARE:
22609 case TYPE_LMUL_COMPARE:
22611 if (! store_data_bypass_p (dep_insn, insn))
22617 if (! store_data_bypass_p (dep_insn, insn))
22623 if (! store_data_bypass_p (dep_insn, insn))
22636 case TYPE_LOAD_EXT:
22637 case TYPE_LOAD_EXT_U:
22638 case TYPE_LOAD_EXT_UX:
22639 if ((rs6000_cpu == PROCESSOR_POWER6)
22640 && recog_memoized (dep_insn)
22641 && (INSN_CODE (dep_insn) >= 0))
22644 /* Adjust the cost for the case where the value written
22645 by a fixed point instruction is used within the address
22646 gen portion of a subsequent load(u)(x) */
22647 switch (get_attr_type (dep_insn))
22654 if (set_to_load_agen (dep_insn, insn))
22658 case TYPE_LOAD_EXT:
22659 case TYPE_LOAD_EXT_U:
22660 case TYPE_LOAD_EXT_UX:
22661 case TYPE_VAR_SHIFT_ROTATE:
22662 case TYPE_VAR_DELAYED_COMPARE:
22664 if (set_to_load_agen (dep_insn, insn))
22670 case TYPE_FAST_COMPARE:
22673 case TYPE_INSERT_WORD:
22674 case TYPE_INSERT_DWORD:
22675 case TYPE_FPLOAD_U:
22676 case TYPE_FPLOAD_UX:
22678 case TYPE_STORE_UX:
22679 case TYPE_FPSTORE_U:
22680 case TYPE_FPSTORE_UX:
22682 if (set_to_load_agen (dep_insn, insn))
22690 case TYPE_IMUL_COMPARE:
22691 case TYPE_LMUL_COMPARE:
22693 if (set_to_load_agen (dep_insn, insn))
22699 if (set_to_load_agen (dep_insn, insn))
22705 if (set_to_load_agen (dep_insn, insn))
22716 if ((rs6000_cpu == PROCESSOR_POWER6)
22717 && recog_memoized (dep_insn)
22718 && (INSN_CODE (dep_insn) >= 0)
22719 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22726 /* Fall out to return default cost. */
22730 case REG_DEP_OUTPUT:
22731 /* Output dependency; DEP_INSN writes a register that INSN writes some
22733 if ((rs6000_cpu == PROCESSOR_POWER6)
22734 && recog_memoized (dep_insn)
22735 && (INSN_CODE (dep_insn) >= 0))
22737 attr_type = get_attr_type (insn);
22742 if (get_attr_type (dep_insn) == TYPE_FP)
22746 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22754 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22759 gcc_unreachable ();
22765 /* Debug version of rs6000_adjust_cost. */
22768 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22770 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
22776 switch (REG_NOTE_KIND (link))
22778 default: dep = "unknown depencency"; break;
22779 case REG_DEP_TRUE: dep = "data dependency"; break;
22780 case REG_DEP_OUTPUT: dep = "output dependency"; break;
22781 case REG_DEP_ANTI: dep = "anti depencency"; break;
22785 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22786 "%s, insn:\n", ret, cost, dep);
22794 /* The function returns a true if INSN is microcoded.
22795 Return false otherwise. */
22798 is_microcoded_insn (rtx insn)
22800 if (!insn || !NONDEBUG_INSN_P (insn)
22801 || GET_CODE (PATTERN (insn)) == USE
22802 || GET_CODE (PATTERN (insn)) == CLOBBER)
22805 if (rs6000_cpu_attr == CPU_CELL)
22806 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
22808 if (rs6000_sched_groups)
22810 enum attr_type type = get_attr_type (insn);
22811 if (type == TYPE_LOAD_EXT_U
22812 || type == TYPE_LOAD_EXT_UX
22813 || type == TYPE_LOAD_UX
22814 || type == TYPE_STORE_UX
22815 || type == TYPE_MFCR)
22822 /* The function returns true if INSN is cracked into 2 instructions
22823 by the processor (and therefore occupies 2 issue slots). */
22826 is_cracked_insn (rtx insn)
22828 if (!insn || !NONDEBUG_INSN_P (insn)
22829 || GET_CODE (PATTERN (insn)) == USE
22830 || GET_CODE (PATTERN (insn)) == CLOBBER)
22833 if (rs6000_sched_groups)
22835 enum attr_type type = get_attr_type (insn);
22836 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
22837 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
22838 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
22839 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
22840 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
22841 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
22842 || type == TYPE_IDIV || type == TYPE_LDIV
22843 || type == TYPE_INSERT_WORD)
22850 /* The function returns true if INSN can be issued only from
22851 the branch slot. */
22854 is_branch_slot_insn (rtx insn)
22856 if (!insn || !NONDEBUG_INSN_P (insn)
22857 || GET_CODE (PATTERN (insn)) == USE
22858 || GET_CODE (PATTERN (insn)) == CLOBBER)
22861 if (rs6000_sched_groups)
22863 enum attr_type type = get_attr_type (insn);
22864 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
22872 /* The function returns true if out_inst sets a value that is
22873 used in the address generation computation of in_insn */
22875 set_to_load_agen (rtx out_insn, rtx in_insn)
22877 rtx out_set, in_set;
22879 /* For performance reasons, only handle the simple case where
22880 both loads are a single_set. */
22881 out_set = single_set (out_insn);
22884 in_set = single_set (in_insn);
22886 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
22892 /* Try to determine base/offset/size parts of the given MEM.
22893 Return true if successful, false if all the values couldn't
22896 This function only looks for REG or REG+CONST address forms.
22897 REG+REG address form will return false. */
22900 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
22901 HOST_WIDE_INT *size)
22904 if MEM_SIZE_KNOWN_P (mem)
22905 *size = MEM_SIZE (mem);
22909 if (GET_CODE (XEXP (mem, 0)) == PRE_MODIFY)
22910 addr_rtx = XEXP (XEXP (mem, 0), 1);
22912 addr_rtx = (XEXP (mem, 0));
22914 if (GET_CODE (addr_rtx) == REG)
22919 else if (GET_CODE (addr_rtx) == PLUS
22920 && CONST_INT_P (XEXP (addr_rtx, 1)))
22922 *base = XEXP (addr_rtx, 0);
22923 *offset = INTVAL (XEXP (addr_rtx, 1));
22931 /* The function returns true if the target storage location of
22932 mem1 is adjacent to the target storage location of mem2 */
22933 /* Return 1 if memory locations are adjacent. */
22936 adjacent_mem_locations (rtx mem1, rtx mem2)
22939 HOST_WIDE_INT off1, size1, off2, size2;
22941 if (get_memref_parts (mem1, ®1, &off1, &size1)
22942 && get_memref_parts (mem2, ®2, &off2, &size2))
22943 return ((REGNO (reg1) == REGNO (reg2))
22944 && ((off1 + size1 == off2)
22945 || (off2 + size2 == off1)));
22950 /* This function returns true if it can be determined that the two MEM
22951 locations overlap by at least 1 byte based on base reg/offset/size. */
22954 mem_locations_overlap (rtx mem1, rtx mem2)
22957 HOST_WIDE_INT off1, size1, off2, size2;
22959 if (get_memref_parts (mem1, ®1, &off1, &size1)
22960 && get_memref_parts (mem2, ®2, &off2, &size2))
22961 return ((REGNO (reg1) == REGNO (reg2))
22962 && (((off1 <= off2) && (off1 + size1 > off2))
22963 || ((off2 <= off1) && (off2 + size2 > off1))));
22968 /* A C statement (sans semicolon) to update the integer scheduling
22969 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22970 INSN earlier, reduce the priority to execute INSN later. Do not
22971 define this macro if you do not need to adjust the scheduling
22972 priorities of insns. */
22975 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
22977 rtx load_mem, str_mem;
22978 /* On machines (like the 750) which have asymmetric integer units,
22979 where one integer unit can do multiply and divides and the other
22980 can't, reduce the priority of multiply/divide so it is scheduled
22981 before other integer operations. */
22984 if (! INSN_P (insn))
22987 if (GET_CODE (PATTERN (insn)) == USE)
22990 switch (rs6000_cpu_attr) {
22992 switch (get_attr_type (insn))
22999 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
23000 priority, priority);
23001 if (priority >= 0 && priority < 0x01000000)
23008 if (insn_must_be_first_in_group (insn)
23009 && reload_completed
23010 && current_sched_info->sched_max_insns_priority
23011 && rs6000_sched_restricted_insns_priority)
23014 /* Prioritize insns that can be dispatched only in the first
23016 if (rs6000_sched_restricted_insns_priority == 1)
23017 /* Attach highest priority to insn. This means that in
23018 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
23019 precede 'priority' (critical path) considerations. */
23020 return current_sched_info->sched_max_insns_priority;
23021 else if (rs6000_sched_restricted_insns_priority == 2)
23022 /* Increase priority of insn by a minimal amount. This means that in
23023 haifa-sched.c:ready_sort(), only 'priority' (critical path)
23024 considerations precede dispatch-slot restriction considerations. */
23025 return (priority + 1);
23028 if (rs6000_cpu == PROCESSOR_POWER6
23029 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
23030 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
23031 /* Attach highest priority to insn if the scheduler has just issued two
23032 stores and this instruction is a load, or two loads and this instruction
23033 is a store. Power6 wants loads and stores scheduled alternately
23035 return current_sched_info->sched_max_insns_priority;
23040 /* Return true if the instruction is nonpipelined on the Cell. */
23042 is_nonpipeline_insn (rtx insn)
23044 enum attr_type type;
23045 if (!insn || !NONDEBUG_INSN_P (insn)
23046 || GET_CODE (PATTERN (insn)) == USE
23047 || GET_CODE (PATTERN (insn)) == CLOBBER)
23050 type = get_attr_type (insn);
23051 if (type == TYPE_IMUL
23052 || type == TYPE_IMUL2
23053 || type == TYPE_IMUL3
23054 || type == TYPE_LMUL
23055 || type == TYPE_IDIV
23056 || type == TYPE_LDIV
23057 || type == TYPE_SDIV
23058 || type == TYPE_DDIV
23059 || type == TYPE_SSQRT
23060 || type == TYPE_DSQRT
23061 || type == TYPE_MFCR
23062 || type == TYPE_MFCRF
23063 || type == TYPE_MFJMPR)
23071 /* Return how many instructions the machine can issue per cycle. */
23074 rs6000_issue_rate (void)
23076 /* Unless scheduling for register pressure, use issue rate of 1 for
23077 first scheduling pass to decrease degradation. */
23078 if (!reload_completed && !flag_sched_pressure)
23081 switch (rs6000_cpu_attr) {
23082 case CPU_RIOS1: /* ? */
23084 case CPU_PPC601: /* ? */
23094 case CPU_PPCE300C2:
23095 case CPU_PPCE300C3:
23096 case CPU_PPCE500MC:
23097 case CPU_PPCE500MC64:
23119 /* Return how many instructions to look ahead for better insn
23123 rs6000_use_sched_lookahead (void)
23125 switch (rs6000_cpu_attr)
23132 return (reload_completed ? 8 : 0);
23139 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
23141 rs6000_use_sched_lookahead_guard (rtx insn)
23143 if (rs6000_cpu_attr != CPU_CELL)
23146 if (insn == NULL_RTX || !INSN_P (insn))
23149 if (!reload_completed
23150 || is_nonpipeline_insn (insn)
23151 || is_microcoded_insn (insn))
23157 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
23158 and return true. */
23161 find_mem_ref (rtx pat, rtx *mem_ref)
23166 /* stack_tie does not produce any real memory traffic. */
23167 if (tie_operand (pat, VOIDmode))
23170 if (GET_CODE (pat) == MEM)
23176 /* Recursively process the pattern. */
23177 fmt = GET_RTX_FORMAT (GET_CODE (pat));
23179 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
23183 if (find_mem_ref (XEXP (pat, i), mem_ref))
23186 else if (fmt[i] == 'E')
23187 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
23189 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
23197 /* Determine if PAT is a PATTERN of a load insn. */
23200 is_load_insn1 (rtx pat, rtx *load_mem)
23202 if (!pat || pat == NULL_RTX)
23205 if (GET_CODE (pat) == SET)
23206 return find_mem_ref (SET_SRC (pat), load_mem);
23208 if (GET_CODE (pat) == PARALLEL)
23212 for (i = 0; i < XVECLEN (pat, 0); i++)
23213 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
23220 /* Determine if INSN loads from memory. */
23223 is_load_insn (rtx insn, rtx *load_mem)
23225 if (!insn || !INSN_P (insn))
23228 if (GET_CODE (insn) == CALL_INSN)
23231 return is_load_insn1 (PATTERN (insn), load_mem);
23234 /* Determine if PAT is a PATTERN of a store insn. */
23237 is_store_insn1 (rtx pat, rtx *str_mem)
23239 if (!pat || pat == NULL_RTX)
23242 if (GET_CODE (pat) == SET)
23243 return find_mem_ref (SET_DEST (pat), str_mem);
23245 if (GET_CODE (pat) == PARALLEL)
23249 for (i = 0; i < XVECLEN (pat, 0); i++)
23250 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
23257 /* Determine if INSN stores to memory. */
23260 is_store_insn (rtx insn, rtx *str_mem)
23262 if (!insn || !INSN_P (insn))
23265 return is_store_insn1 (PATTERN (insn), str_mem);
23268 /* Returns whether the dependence between INSN and NEXT is considered
23269 costly by the given target. */
23272 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
23276 rtx load_mem, str_mem;
23278 /* If the flag is not enabled - no dependence is considered costly;
23279 allow all dependent insns in the same group.
23280 This is the most aggressive option. */
23281 if (rs6000_sched_costly_dep == no_dep_costly)
23284 /* If the flag is set to 1 - a dependence is always considered costly;
23285 do not allow dependent instructions in the same group.
23286 This is the most conservative option. */
23287 if (rs6000_sched_costly_dep == all_deps_costly)
23290 insn = DEP_PRO (dep);
23291 next = DEP_CON (dep);
23293 if (rs6000_sched_costly_dep == store_to_load_dep_costly
23294 && is_load_insn (next, &load_mem)
23295 && is_store_insn (insn, &str_mem))
23296 /* Prevent load after store in the same group. */
23299 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
23300 && is_load_insn (next, &load_mem)
23301 && is_store_insn (insn, &str_mem)
23302 && DEP_TYPE (dep) == REG_DEP_TRUE
23303 && mem_locations_overlap(str_mem, load_mem))
23304 /* Prevent load after store in the same group if it is a true
23308 /* The flag is set to X; dependences with latency >= X are considered costly,
23309 and will not be scheduled in the same group. */
23310 if (rs6000_sched_costly_dep <= max_dep_latency
23311 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23317 /* Return the next insn after INSN that is found before TAIL is reached,
23318 skipping any "non-active" insns - insns that will not actually occupy
23319 an issue slot. Return NULL_RTX if such an insn is not found. */
23322 get_next_active_insn (rtx insn, rtx tail)
23324 if (insn == NULL_RTX || insn == tail)
23329 insn = NEXT_INSN (insn);
23330 if (insn == NULL_RTX || insn == tail)
23335 || (NONJUMP_INSN_P (insn)
23336 && GET_CODE (PATTERN (insn)) != USE
23337 && GET_CODE (PATTERN (insn)) != CLOBBER
23338 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23344 /* We are about to begin issuing insns for this clock cycle. */
23347 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23348 rtx *ready ATTRIBUTE_UNUSED,
23349 int *pn_ready ATTRIBUTE_UNUSED,
23350 int clock_var ATTRIBUTE_UNUSED)
23352 int n_ready = *pn_ready;
23355 fprintf (dump, "// rs6000_sched_reorder :\n");
23357 /* Reorder the ready list, if the second to last ready insn
23358 is a nonepipeline insn. */
23359 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23361 if (is_nonpipeline_insn (ready[n_ready - 1])
23362 && (recog_memoized (ready[n_ready - 2]) > 0))
23363 /* Simply swap first two insns. */
23365 rtx tmp = ready[n_ready - 1];
23366 ready[n_ready - 1] = ready[n_ready - 2];
23367 ready[n_ready - 2] = tmp;
23371 if (rs6000_cpu == PROCESSOR_POWER6)
23372 load_store_pendulum = 0;
23374 return rs6000_issue_rate ();
23377 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23380 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23381 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23384 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23386 /* For Power6, we need to handle some special cases to try and keep the
23387 store queue from overflowing and triggering expensive flushes.
23389 This code monitors how load and store instructions are being issued
23390 and skews the ready list one way or the other to increase the likelihood
23391 that a desired instruction is issued at the proper time.
23393 A couple of things are done. First, we maintain a "load_store_pendulum"
23394 to track the current state of load/store issue.
23396 - If the pendulum is at zero, then no loads or stores have been
23397 issued in the current cycle so we do nothing.
23399 - If the pendulum is 1, then a single load has been issued in this
23400 cycle and we attempt to locate another load in the ready list to
23403 - If the pendulum is -2, then two stores have already been
23404 issued in this cycle, so we increase the priority of the first load
23405 in the ready list to increase it's likelihood of being chosen first
23408 - If the pendulum is -1, then a single store has been issued in this
23409 cycle and we attempt to locate another store in the ready list to
23410 issue with it, preferring a store to an adjacent memory location to
23411 facilitate store pairing in the store queue.
23413 - If the pendulum is 2, then two loads have already been
23414 issued in this cycle, so we increase the priority of the first store
23415 in the ready list to increase it's likelihood of being chosen first
23418 - If the pendulum < -2 or > 2, then do nothing.
23420 Note: This code covers the most common scenarios. There exist non
23421 load/store instructions which make use of the LSU and which
23422 would need to be accounted for to strictly model the behavior
23423 of the machine. Those instructions are currently unaccounted
23424 for to help minimize compile time overhead of this code.
23426 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23430 rtx tmp, load_mem, str_mem;
23432 if (is_store_insn (last_scheduled_insn, &str_mem))
23433 /* Issuing a store, swing the load_store_pendulum to the left */
23434 load_store_pendulum--;
23435 else if (is_load_insn (last_scheduled_insn, &load_mem))
23436 /* Issuing a load, swing the load_store_pendulum to the right */
23437 load_store_pendulum++;
23439 return cached_can_issue_more;
23441 /* If the pendulum is balanced, or there is only one instruction on
23442 the ready list, then all is well, so return. */
23443 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23444 return cached_can_issue_more;
23446 if (load_store_pendulum == 1)
23448 /* A load has been issued in this cycle. Scan the ready list
23449 for another load to issue with it */
23454 if (is_load_insn (ready[pos], &load_mem))
23456 /* Found a load. Move it to the head of the ready list,
23457 and adjust it's priority so that it is more likely to
23460 for (i=pos; i<*pn_ready-1; i++)
23461 ready[i] = ready[i + 1];
23462 ready[*pn_ready-1] = tmp;
23464 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23465 INSN_PRIORITY (tmp)++;
23471 else if (load_store_pendulum == -2)
23473 /* Two stores have been issued in this cycle. Increase the
23474 priority of the first load in the ready list to favor it for
23475 issuing in the next cycle. */
23480 if (is_load_insn (ready[pos], &load_mem)
23482 && INSN_PRIORITY_KNOWN (ready[pos]))
23484 INSN_PRIORITY (ready[pos])++;
23486 /* Adjust the pendulum to account for the fact that a load
23487 was found and increased in priority. This is to prevent
23488 increasing the priority of multiple loads */
23489 load_store_pendulum--;
23496 else if (load_store_pendulum == -1)
23498 /* A store has been issued in this cycle. Scan the ready list for
23499 another store to issue with it, preferring a store to an adjacent
23501 int first_store_pos = -1;
23507 if (is_store_insn (ready[pos], &str_mem))
23510 /* Maintain the index of the first store found on the
23512 if (first_store_pos == -1)
23513 first_store_pos = pos;
23515 if (is_store_insn (last_scheduled_insn, &str_mem2)
23516 && adjacent_mem_locations (str_mem, str_mem2))
23518 /* Found an adjacent store. Move it to the head of the
23519 ready list, and adjust it's priority so that it is
23520 more likely to stay there */
23522 for (i=pos; i<*pn_ready-1; i++)
23523 ready[i] = ready[i + 1];
23524 ready[*pn_ready-1] = tmp;
23526 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23527 INSN_PRIORITY (tmp)++;
23529 first_store_pos = -1;
23537 if (first_store_pos >= 0)
23539 /* An adjacent store wasn't found, but a non-adjacent store was,
23540 so move the non-adjacent store to the front of the ready
23541 list, and adjust its priority so that it is more likely to
23543 tmp = ready[first_store_pos];
23544 for (i=first_store_pos; i<*pn_ready-1; i++)
23545 ready[i] = ready[i + 1];
23546 ready[*pn_ready-1] = tmp;
23547 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23548 INSN_PRIORITY (tmp)++;
23551 else if (load_store_pendulum == 2)
23553 /* Two loads have been issued in this cycle. Increase the priority
23554 of the first store in the ready list to favor it for issuing in
23560 if (is_store_insn (ready[pos], &str_mem)
23562 && INSN_PRIORITY_KNOWN (ready[pos]))
23564 INSN_PRIORITY (ready[pos])++;
23566 /* Adjust the pendulum to account for the fact that a store
23567 was found and increased in priority. This is to prevent
23568 increasing the priority of multiple stores */
23569 load_store_pendulum++;
23578 return cached_can_issue_more;
23581 /* Return whether the presence of INSN causes a dispatch group termination
23582 of group WHICH_GROUP.
23584 If WHICH_GROUP == current_group, this function will return true if INSN
23585 causes the termination of the current group (i.e, the dispatch group to
23586 which INSN belongs). This means that INSN will be the last insn in the
23587 group it belongs to.
23589 If WHICH_GROUP == previous_group, this function will return true if INSN
23590 causes the termination of the previous group (i.e, the dispatch group that
23591 precedes the group to which INSN belongs). This means that INSN will be
23592 the first insn in the group it belongs to). */
23595 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23602 first = insn_must_be_first_in_group (insn);
23603 last = insn_must_be_last_in_group (insn);
23608 if (which_group == current_group)
23610 else if (which_group == previous_group)
23618 insn_must_be_first_in_group (rtx insn)
23620 enum attr_type type;
23623 || GET_CODE (insn) == NOTE
23624 || DEBUG_INSN_P (insn)
23625 || GET_CODE (PATTERN (insn)) == USE
23626 || GET_CODE (PATTERN (insn)) == CLOBBER)
23629 switch (rs6000_cpu)
23631 case PROCESSOR_POWER5:
23632 if (is_cracked_insn (insn))
23634 case PROCESSOR_POWER4:
23635 if (is_microcoded_insn (insn))
23638 if (!rs6000_sched_groups)
23641 type = get_attr_type (insn);
23648 case TYPE_DELAYED_CR:
23649 case TYPE_CR_LOGICAL:
23663 case PROCESSOR_POWER6:
23664 type = get_attr_type (insn);
23668 case TYPE_INSERT_DWORD:
23672 case TYPE_VAR_SHIFT_ROTATE:
23679 case TYPE_INSERT_WORD:
23680 case TYPE_DELAYED_COMPARE:
23681 case TYPE_IMUL_COMPARE:
23682 case TYPE_LMUL_COMPARE:
23683 case TYPE_FPCOMPARE:
23694 case TYPE_LOAD_EXT_UX:
23696 case TYPE_STORE_UX:
23697 case TYPE_FPLOAD_U:
23698 case TYPE_FPLOAD_UX:
23699 case TYPE_FPSTORE_U:
23700 case TYPE_FPSTORE_UX:
23706 case PROCESSOR_POWER7:
23707 type = get_attr_type (insn);
23711 case TYPE_CR_LOGICAL:
23718 case TYPE_DELAYED_COMPARE:
23719 case TYPE_VAR_DELAYED_COMPARE:
23725 case TYPE_LOAD_EXT:
23726 case TYPE_LOAD_EXT_U:
23727 case TYPE_LOAD_EXT_UX:
23729 case TYPE_STORE_UX:
23730 case TYPE_FPLOAD_U:
23731 case TYPE_FPLOAD_UX:
23732 case TYPE_FPSTORE_U:
23733 case TYPE_FPSTORE_UX:
23749 insn_must_be_last_in_group (rtx insn)
23751 enum attr_type type;
23754 || GET_CODE (insn) == NOTE
23755 || DEBUG_INSN_P (insn)
23756 || GET_CODE (PATTERN (insn)) == USE
23757 || GET_CODE (PATTERN (insn)) == CLOBBER)
23760 switch (rs6000_cpu) {
23761 case PROCESSOR_POWER4:
23762 case PROCESSOR_POWER5:
23763 if (is_microcoded_insn (insn))
23766 if (is_branch_slot_insn (insn))
23770 case PROCESSOR_POWER6:
23771 type = get_attr_type (insn);
23778 case TYPE_VAR_SHIFT_ROTATE:
23785 case TYPE_DELAYED_COMPARE:
23786 case TYPE_IMUL_COMPARE:
23787 case TYPE_LMUL_COMPARE:
23788 case TYPE_FPCOMPARE:
23802 case PROCESSOR_POWER7:
23803 type = get_attr_type (insn);
23811 case TYPE_LOAD_EXT_U:
23812 case TYPE_LOAD_EXT_UX:
23813 case TYPE_STORE_UX:
23826 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23827 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23830 is_costly_group (rtx *group_insns, rtx next_insn)
23833 int issue_rate = rs6000_issue_rate ();
23835 for (i = 0; i < issue_rate; i++)
23837 sd_iterator_def sd_it;
23839 rtx insn = group_insns[i];
23844 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
23846 rtx next = DEP_CON (dep);
23848 if (next == next_insn
23849 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
23857 /* Utility of the function redefine_groups.
23858 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23859 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23860 to keep it "far" (in a separate group) from GROUP_INSNS, following
23861 one of the following schemes, depending on the value of the flag
23862 -minsert_sched_nops = X:
23863 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23864 in order to force NEXT_INSN into a separate group.
23865 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23866 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23867 insertion (has a group just ended, how many vacant issue slots remain in the
23868 last group, and how many dispatch groups were encountered so far). */
23871 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
23872 rtx next_insn, bool *group_end, int can_issue_more,
23877 int issue_rate = rs6000_issue_rate ();
23878 bool end = *group_end;
23881 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
23882 return can_issue_more;
23884 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
23885 return can_issue_more;
23887 force = is_costly_group (group_insns, next_insn);
23889 return can_issue_more;
23891 if (sched_verbose > 6)
23892 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
23893 *group_count ,can_issue_more);
23895 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
23898 can_issue_more = 0;
23900 /* Since only a branch can be issued in the last issue_slot, it is
23901 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23902 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23903 in this case the last nop will start a new group and the branch
23904 will be forced to the new group. */
23905 if (can_issue_more && !is_branch_slot_insn (next_insn))
23908 /* Power6 and Power7 have special group ending nop. */
23909 if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)
23911 nop = gen_group_ending_nop ();
23912 emit_insn_before (nop, next_insn);
23913 can_issue_more = 0;
23916 while (can_issue_more > 0)
23919 emit_insn_before (nop, next_insn);
23927 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
23929 int n_nops = rs6000_sched_insert_nops;
23931 /* Nops can't be issued from the branch slot, so the effective
23932 issue_rate for nops is 'issue_rate - 1'. */
23933 if (can_issue_more == 0)
23934 can_issue_more = issue_rate;
23936 if (can_issue_more == 0)
23938 can_issue_more = issue_rate - 1;
23941 for (i = 0; i < issue_rate; i++)
23943 group_insns[i] = 0;
23950 emit_insn_before (nop, next_insn);
23951 if (can_issue_more == issue_rate - 1) /* new group begins */
23954 if (can_issue_more == 0)
23956 can_issue_more = issue_rate - 1;
23959 for (i = 0; i < issue_rate; i++)
23961 group_insns[i] = 0;
23967 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23970 /* Is next_insn going to start a new group? */
23973 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23974 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23975 || (can_issue_more < issue_rate &&
23976 insn_terminates_group_p (next_insn, previous_group)));
23977 if (*group_end && end)
23980 if (sched_verbose > 6)
23981 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
23982 *group_count, can_issue_more);
23983 return can_issue_more;
23986 return can_issue_more;
23989 /* This function tries to synch the dispatch groups that the compiler "sees"
23990 with the dispatch groups that the processor dispatcher is expected to
23991 form in practice. It tries to achieve this synchronization by forcing the
23992 estimated processor grouping on the compiler (as opposed to the function
23993 'pad_goups' which tries to force the scheduler's grouping on the processor).
23995 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23996 examines the (estimated) dispatch groups that will be formed by the processor
23997 dispatcher. It marks these group boundaries to reflect the estimated
23998 processor grouping, overriding the grouping that the scheduler had marked.
23999 Depending on the value of the flag '-minsert-sched-nops' this function can
24000 force certain insns into separate groups or force a certain distance between
24001 them by inserting nops, for example, if there exists a "costly dependence"
24004 The function estimates the group boundaries that the processor will form as
24005 follows: It keeps track of how many vacant issue slots are available after
24006 each insn. A subsequent insn will start a new group if one of the following
24008 - no more vacant issue slots remain in the current dispatch group.
24009 - only the last issue slot, which is the branch slot, is vacant, but the next
24010 insn is not a branch.
24011 - only the last 2 or less issue slots, including the branch slot, are vacant,
24012 which means that a cracked insn (which occupies two issue slots) can't be
24013 issued in this group.
24014 - less than 'issue_rate' slots are vacant, and the next insn always needs to
24015 start a new group. */
24018 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24020 rtx insn, next_insn;
24022 int can_issue_more;
24025 int group_count = 0;
24029 issue_rate = rs6000_issue_rate ();
24030 group_insns = XALLOCAVEC (rtx, issue_rate);
24031 for (i = 0; i < issue_rate; i++)
24033 group_insns[i] = 0;
24035 can_issue_more = issue_rate;
24037 insn = get_next_active_insn (prev_head_insn, tail);
24040 while (insn != NULL_RTX)
24042 slot = (issue_rate - can_issue_more);
24043 group_insns[slot] = insn;
24045 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24046 if (insn_terminates_group_p (insn, current_group))
24047 can_issue_more = 0;
24049 next_insn = get_next_active_insn (insn, tail);
24050 if (next_insn == NULL_RTX)
24051 return group_count + 1;
24053 /* Is next_insn going to start a new group? */
24055 = (can_issue_more == 0
24056 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
24057 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
24058 || (can_issue_more < issue_rate &&
24059 insn_terminates_group_p (next_insn, previous_group)));
24061 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
24062 next_insn, &group_end, can_issue_more,
24068 can_issue_more = 0;
24069 for (i = 0; i < issue_rate; i++)
24071 group_insns[i] = 0;
24075 if (GET_MODE (next_insn) == TImode && can_issue_more)
24076 PUT_MODE (next_insn, VOIDmode);
24077 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
24078 PUT_MODE (next_insn, TImode);
24081 if (can_issue_more == 0)
24082 can_issue_more = issue_rate;
24085 return group_count;
24088 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
24089 dispatch group boundaries that the scheduler had marked. Pad with nops
24090 any dispatch groups which have vacant issue slots, in order to force the
24091 scheduler's grouping on the processor dispatcher. The function
24092 returns the number of dispatch groups found. */
24095 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24097 rtx insn, next_insn;
24100 int can_issue_more;
24102 int group_count = 0;
24104 /* Initialize issue_rate. */
24105 issue_rate = rs6000_issue_rate ();
24106 can_issue_more = issue_rate;
24108 insn = get_next_active_insn (prev_head_insn, tail);
24109 next_insn = get_next_active_insn (insn, tail);
24111 while (insn != NULL_RTX)
24114 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24116 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
24118 if (next_insn == NULL_RTX)
24123 /* If the scheduler had marked group termination at this location
24124 (between insn and next_insn), and neither insn nor next_insn will
24125 force group termination, pad the group with nops to force group
24128 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
24129 && !insn_terminates_group_p (insn, current_group)
24130 && !insn_terminates_group_p (next_insn, previous_group))
24132 if (!is_branch_slot_insn (next_insn))
24135 while (can_issue_more)
24138 emit_insn_before (nop, next_insn);
24143 can_issue_more = issue_rate;
24148 next_insn = get_next_active_insn (insn, tail);
24151 return group_count;
24154 /* We're beginning a new block. Initialize data structures as necessary. */
24157 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
24158 int sched_verbose ATTRIBUTE_UNUSED,
24159 int max_ready ATTRIBUTE_UNUSED)
24161 last_scheduled_insn = NULL_RTX;
24162 load_store_pendulum = 0;
24165 /* The following function is called at the end of scheduling BB.
24166 After reload, it inserts nops at insn group bundling. */
24169 rs6000_sched_finish (FILE *dump, int sched_verbose)
24174 fprintf (dump, "=== Finishing schedule.\n");
24176 if (reload_completed && rs6000_sched_groups)
24178 /* Do not run sched_finish hook when selective scheduling enabled. */
24179 if (sel_sched_p ())
24182 if (rs6000_sched_insert_nops == sched_finish_none)
24185 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
24186 n_groups = pad_groups (dump, sched_verbose,
24187 current_sched_info->prev_head,
24188 current_sched_info->next_tail);
24190 n_groups = redefine_groups (dump, sched_verbose,
24191 current_sched_info->prev_head,
24192 current_sched_info->next_tail);
24194 if (sched_verbose >= 6)
24196 fprintf (dump, "ngroups = %d\n", n_groups);
24197 print_rtl (dump, current_sched_info->prev_head);
24198 fprintf (dump, "Done finish_sched\n");
24203 struct _rs6000_sched_context
24205 short cached_can_issue_more;
24206 rtx last_scheduled_insn;
24207 int load_store_pendulum;
24210 typedef struct _rs6000_sched_context rs6000_sched_context_def;
24211 typedef rs6000_sched_context_def *rs6000_sched_context_t;
24213 /* Allocate store for new scheduling context. */
24215 rs6000_alloc_sched_context (void)
24217 return xmalloc (sizeof (rs6000_sched_context_def));
24220 /* If CLEAN_P is true then initializes _SC with clean data,
24221 and from the global context otherwise. */
24223 rs6000_init_sched_context (void *_sc, bool clean_p)
24225 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24229 sc->cached_can_issue_more = 0;
24230 sc->last_scheduled_insn = NULL_RTX;
24231 sc->load_store_pendulum = 0;
24235 sc->cached_can_issue_more = cached_can_issue_more;
24236 sc->last_scheduled_insn = last_scheduled_insn;
24237 sc->load_store_pendulum = load_store_pendulum;
24241 /* Sets the global scheduling context to the one pointed to by _SC. */
24243 rs6000_set_sched_context (void *_sc)
24245 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24247 gcc_assert (sc != NULL);
24249 cached_can_issue_more = sc->cached_can_issue_more;
24250 last_scheduled_insn = sc->last_scheduled_insn;
24251 load_store_pendulum = sc->load_store_pendulum;
24256 rs6000_free_sched_context (void *_sc)
24258 gcc_assert (_sc != NULL);
24264 /* Length in units of the trampoline for entering a nested function. */
24267 rs6000_trampoline_size (void)
24271 switch (DEFAULT_ABI)
24274 gcc_unreachable ();
24277 ret = (TARGET_32BIT) ? 12 : 24;
24282 ret = (TARGET_32BIT) ? 40 : 48;
24289 /* Emit RTL insns to initialize the variable parts of a trampoline.
24290 FNADDR is an RTX for the address of the function's pure code.
24291 CXT is an RTX for the static chain value for the function. */
24294 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
24296 int regsize = (TARGET_32BIT) ? 4 : 8;
24297 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
24298 rtx ctx_reg = force_reg (Pmode, cxt);
24299 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
24301 switch (DEFAULT_ABI)
24304 gcc_unreachable ();
24306 /* Under AIX, just build the 3 word function descriptor */
24309 rtx fnmem, fn_reg, toc_reg;
24311 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
24312 error ("You cannot take the address of a nested function if you use "
24313 "the -mno-pointers-to-nested-functions option.");
24315 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
24316 fn_reg = gen_reg_rtx (Pmode);
24317 toc_reg = gen_reg_rtx (Pmode);
24319 /* Macro to shorten the code expansions below. */
24320 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24322 m_tramp = replace_equiv_address (m_tramp, addr);
24324 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24325 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24326 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24327 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24328 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24334 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24337 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24338 LCT_NORMAL, VOIDmode, 4,
24340 GEN_INT (rs6000_trampoline_size ()), SImode,
24348 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24349 identifier as an argument, so the front end shouldn't look it up. */
24352 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24354 return is_attribute_p ("altivec", attr_id);
24357 /* Handle the "altivec" attribute. The attribute may have
24358 arguments as follows:
24360 __attribute__((altivec(vector__)))
24361 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24362 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24364 and may appear more than once (e.g., 'vector bool char') in a
24365 given declaration. */
24368 rs6000_handle_altivec_attribute (tree *node,
24369 tree name ATTRIBUTE_UNUSED,
24371 int flags ATTRIBUTE_UNUSED,
24372 bool *no_add_attrs)
24374 tree type = *node, result = NULL_TREE;
24375 enum machine_mode mode;
24378 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24379 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24380 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24383 while (POINTER_TYPE_P (type)
24384 || TREE_CODE (type) == FUNCTION_TYPE
24385 || TREE_CODE (type) == METHOD_TYPE
24386 || TREE_CODE (type) == ARRAY_TYPE)
24387 type = TREE_TYPE (type);
24389 mode = TYPE_MODE (type);
24391 /* Check for invalid AltiVec type qualifiers. */
24392 if (type == long_double_type_node)
24393 error ("use of %<long double%> in AltiVec types is invalid");
24394 else if (type == boolean_type_node)
24395 error ("use of boolean types in AltiVec types is invalid");
24396 else if (TREE_CODE (type) == COMPLEX_TYPE)
24397 error ("use of %<complex%> in AltiVec types is invalid");
24398 else if (DECIMAL_FLOAT_MODE_P (mode))
24399 error ("use of decimal floating point types in AltiVec types is invalid");
24400 else if (!TARGET_VSX)
24402 if (type == long_unsigned_type_node || type == long_integer_type_node)
24405 error ("use of %<long%> in AltiVec types is invalid for "
24406 "64-bit code without -mvsx");
24407 else if (rs6000_warn_altivec_long)
24408 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24411 else if (type == long_long_unsigned_type_node
24412 || type == long_long_integer_type_node)
24413 error ("use of %<long long%> in AltiVec types is invalid without "
24415 else if (type == double_type_node)
24416 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24419 switch (altivec_type)
24422 unsigned_p = TYPE_UNSIGNED (type);
24426 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24429 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24432 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24435 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24437 case SFmode: result = V4SF_type_node; break;
24438 case DFmode: result = V2DF_type_node; break;
24439 /* If the user says 'vector int bool', we may be handed the 'bool'
24440 attribute _before_ the 'vector' attribute, and so select the
24441 proper type in the 'b' case below. */
24442 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24443 case V2DImode: case V2DFmode:
24451 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24452 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24453 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24454 case QImode: case V16QImode: result = bool_V16QI_type_node;
24461 case V8HImode: result = pixel_V8HI_type_node;
24467 /* Propagate qualifiers attached to the element type
24468 onto the vector type. */
24469 if (result && result != type && TYPE_QUALS (type))
24470 result = build_qualified_type (result, TYPE_QUALS (type));
24472 *no_add_attrs = true; /* No need to hang on to the attribute. */
24475 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24480 /* AltiVec defines four built-in scalar types that serve as vector
24481 elements; we must teach the compiler how to mangle them. */
24483 static const char *
24484 rs6000_mangle_type (const_tree type)
24486 type = TYPE_MAIN_VARIANT (type);
24488 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24489 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24492 if (type == bool_char_type_node) return "U6__boolc";
24493 if (type == bool_short_type_node) return "U6__bools";
24494 if (type == pixel_type_node) return "u7__pixel";
24495 if (type == bool_int_type_node) return "U6__booli";
24496 if (type == bool_long_type_node) return "U6__booll";
24498 /* Mangle IBM extended float long double as `g' (__float128) on
24499 powerpc*-linux where long-double-64 previously was the default. */
24500 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24502 && TARGET_LONG_DOUBLE_128
24503 && !TARGET_IEEEQUAD)
24506 /* For all other types, use normal C++ mangling. */
24510 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24511 struct attribute_spec.handler. */
24514 rs6000_handle_longcall_attribute (tree *node, tree name,
24515 tree args ATTRIBUTE_UNUSED,
24516 int flags ATTRIBUTE_UNUSED,
24517 bool *no_add_attrs)
24519 if (TREE_CODE (*node) != FUNCTION_TYPE
24520 && TREE_CODE (*node) != FIELD_DECL
24521 && TREE_CODE (*node) != TYPE_DECL)
24523 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24525 *no_add_attrs = true;
24531 /* Set longcall attributes on all functions declared when
24532 rs6000_default_long_calls is true. */
24534 rs6000_set_default_type_attributes (tree type)
24536 if (rs6000_default_long_calls
24537 && (TREE_CODE (type) == FUNCTION_TYPE
24538 || TREE_CODE (type) == METHOD_TYPE))
24539 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24541 TYPE_ATTRIBUTES (type));
24544 darwin_set_default_type_attributes (type);
24548 /* Return a reference suitable for calling a function with the
24549 longcall attribute. */
24552 rs6000_longcall_ref (rtx call_ref)
24554 const char *call_name;
24557 if (GET_CODE (call_ref) != SYMBOL_REF)
24560 /* System V adds '.' to the internal name, so skip them. */
24561 call_name = XSTR (call_ref, 0);
24562 if (*call_name == '.')
24564 while (*call_name == '.')
24567 node = get_identifier (call_name);
24568 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24571 return force_reg (Pmode, call_ref);
24574 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24575 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24578 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24579 struct attribute_spec.handler. */
24581 rs6000_handle_struct_attribute (tree *node, tree name,
24582 tree args ATTRIBUTE_UNUSED,
24583 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24586 if (DECL_P (*node))
24588 if (TREE_CODE (*node) == TYPE_DECL)
24589 type = &TREE_TYPE (*node);
24594 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24595 || TREE_CODE (*type) == UNION_TYPE)))
24597 warning (OPT_Wattributes, "%qE attribute ignored", name);
24598 *no_add_attrs = true;
24601 else if ((is_attribute_p ("ms_struct", name)
24602 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24603 || ((is_attribute_p ("gcc_struct", name)
24604 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24606 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24608 *no_add_attrs = true;
24615 rs6000_ms_bitfield_layout_p (const_tree record_type)
24617 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24618 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24619 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24622 #ifdef USING_ELFOS_H
24624 /* A get_unnamed_section callback, used for switching to toc_section. */
24627 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24629 if (DEFAULT_ABI == ABI_AIX
24630 && TARGET_MINIMAL_TOC
24631 && !TARGET_RELOCATABLE)
24633 if (!toc_initialized)
24635 toc_initialized = 1;
24636 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24637 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24638 fprintf (asm_out_file, "\t.tc ");
24639 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24640 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24641 fprintf (asm_out_file, "\n");
24643 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24644 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24645 fprintf (asm_out_file, " = .+32768\n");
24648 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24650 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24651 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24654 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24655 if (!toc_initialized)
24657 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24658 fprintf (asm_out_file, " = .+32768\n");
24659 toc_initialized = 1;
24664 /* Implement TARGET_ASM_INIT_SECTIONS. */
24667 rs6000_elf_asm_init_sections (void)
24670 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24673 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24674 SDATA2_SECTION_ASM_OP);
24677 /* Implement TARGET_SELECT_RTX_SECTION. */
24680 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24681 unsigned HOST_WIDE_INT align)
24683 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24684 return toc_section;
24686 return default_elf_select_rtx_section (mode, x, align);
24689 /* For a SYMBOL_REF, set generic flags and then perform some
24690 target-specific processing.
24692 When the AIX ABI is requested on a non-AIX system, replace the
24693 function name with the real name (with a leading .) rather than the
24694 function descriptor name. This saves a lot of overriding code to
24695 read the prefixes. */
24697 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
24699 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24701 default_encode_section_info (decl, rtl, first);
24704 && TREE_CODE (decl) == FUNCTION_DECL
24706 && DEFAULT_ABI == ABI_AIX)
24708 rtx sym_ref = XEXP (rtl, 0);
24709 size_t len = strlen (XSTR (sym_ref, 0));
24710 char *str = XALLOCAVEC (char, len + 2);
24712 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24713 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24718 compare_section_name (const char *section, const char *templ)
24722 len = strlen (templ);
24723 return (strncmp (section, templ, len) == 0
24724 && (section[len] == 0 || section[len] == '.'));
24728 rs6000_elf_in_small_data_p (const_tree decl)
24730 if (rs6000_sdata == SDATA_NONE)
24733 /* We want to merge strings, so we never consider them small data. */
24734 if (TREE_CODE (decl) == STRING_CST)
24737 /* Functions are never in the small data area. */
24738 if (TREE_CODE (decl) == FUNCTION_DECL)
24741 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24743 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24744 if (compare_section_name (section, ".sdata")
24745 || compare_section_name (section, ".sdata2")
24746 || compare_section_name (section, ".gnu.linkonce.s")
24747 || compare_section_name (section, ".sbss")
24748 || compare_section_name (section, ".sbss2")
24749 || compare_section_name (section, ".gnu.linkonce.sb")
24750 || strcmp (section, ".PPC.EMB.sdata0") == 0
24751 || strcmp (section, ".PPC.EMB.sbss0") == 0)
24756 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
24759 && size <= g_switch_value
24760 /* If it's not public, and we're not going to reference it there,
24761 there's no need to put it in the small data section. */
24762 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
24769 #endif /* USING_ELFOS_H */
24771 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24774 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
24776 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
24779 /* Return a REG that occurs in ADDR with coefficient 1.
24780 ADDR can be effectively incremented by incrementing REG.
24782 r0 is special and we must not select it as an address
24783 register by this routine since our caller will try to
24784 increment the returned register via an "la" instruction. */
24787 find_addr_reg (rtx addr)
24789 while (GET_CODE (addr) == PLUS)
24791 if (GET_CODE (XEXP (addr, 0)) == REG
24792 && REGNO (XEXP (addr, 0)) != 0)
24793 addr = XEXP (addr, 0);
24794 else if (GET_CODE (XEXP (addr, 1)) == REG
24795 && REGNO (XEXP (addr, 1)) != 0)
24796 addr = XEXP (addr, 1);
24797 else if (CONSTANT_P (XEXP (addr, 0)))
24798 addr = XEXP (addr, 1);
24799 else if (CONSTANT_P (XEXP (addr, 1)))
24800 addr = XEXP (addr, 0);
24802 gcc_unreachable ();
24804 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
24809 rs6000_fatal_bad_address (rtx op)
24811 fatal_insn ("bad address", op);
24816 typedef struct branch_island_d {
24817 tree function_name;
24822 DEF_VEC_O(branch_island);
24823 DEF_VEC_ALLOC_O(branch_island,gc);
24825 static VEC(branch_island,gc) *branch_islands;
24827 /* Remember to generate a branch island for far calls to the given
24831 add_compiler_branch_island (tree label_name, tree function_name,
24834 branch_island *bi = VEC_safe_push (branch_island, gc, branch_islands, NULL);
24836 bi->function_name = function_name;
24837 bi->label_name = label_name;
24838 bi->line_number = line_number;
24841 /* Generate far-jump branch islands for everything recorded in
24842 branch_islands. Invoked immediately after the last instruction of
24843 the epilogue has been emitted; the branch islands must be appended
24844 to, and contiguous with, the function body. Mach-O stubs are
24845 generated in machopic_output_stub(). */
24848 macho_branch_islands (void)
24852 while (!VEC_empty (branch_island, branch_islands))
24854 branch_island *bi = VEC_last (branch_island, branch_islands);
24855 const char *label = IDENTIFIER_POINTER (bi->label_name);
24856 const char *name = IDENTIFIER_POINTER (bi->function_name);
24857 char name_buf[512];
24858 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24859 if (name[0] == '*' || name[0] == '&')
24860 strcpy (name_buf, name+1);
24864 strcpy (name_buf+1, name);
24866 strcpy (tmp_buf, "\n");
24867 strcat (tmp_buf, label);
24868 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24869 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24870 dbxout_stabd (N_SLINE, bi->line_number);
24871 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24874 if (TARGET_LINK_STACK)
24877 get_ppc476_thunk_name (name);
24878 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
24879 strcat (tmp_buf, name);
24880 strcat (tmp_buf, "\n");
24881 strcat (tmp_buf, label);
24882 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24886 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
24887 strcat (tmp_buf, label);
24888 strcat (tmp_buf, "_pic\n");
24889 strcat (tmp_buf, label);
24890 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24893 strcat (tmp_buf, "\taddis r11,r11,ha16(");
24894 strcat (tmp_buf, name_buf);
24895 strcat (tmp_buf, " - ");
24896 strcat (tmp_buf, label);
24897 strcat (tmp_buf, "_pic)\n");
24899 strcat (tmp_buf, "\tmtlr r0\n");
24901 strcat (tmp_buf, "\taddi r12,r11,lo16(");
24902 strcat (tmp_buf, name_buf);
24903 strcat (tmp_buf, " - ");
24904 strcat (tmp_buf, label);
24905 strcat (tmp_buf, "_pic)\n");
24907 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
24911 strcat (tmp_buf, ":\nlis r12,hi16(");
24912 strcat (tmp_buf, name_buf);
24913 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
24914 strcat (tmp_buf, name_buf);
24915 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
24917 output_asm_insn (tmp_buf, 0);
24918 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24919 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24920 dbxout_stabd (N_SLINE, bi->line_number);
24921 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24922 VEC_pop (branch_island, branch_islands);
24926 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24927 already there or not. */
24930 no_previous_def (tree function_name)
24935 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24936 if (function_name == bi->function_name)
24941 /* GET_PREV_LABEL gets the label name from the previous definition of
24945 get_prev_label (tree function_name)
24950 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24951 if (function_name == bi->function_name)
24952 return bi->label_name;
24956 /* INSN is either a function call or a millicode call. It may have an
24957 unconditional jump in its delay slot.
24959 CALL_DEST is the routine we are calling. */
24962 output_call (rtx insn, rtx *operands, int dest_operand_number,
24963 int cookie_operand_number)
24965 static char buf[256];
24966 if (darwin_emit_branch_islands
24967 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
24968 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
24971 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
24973 if (no_previous_def (funname))
24975 rtx label_rtx = gen_label_rtx ();
24976 char *label_buf, temp_buf[256];
24977 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
24978 CODE_LABEL_NUMBER (label_rtx));
24979 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
24980 labelname = get_identifier (label_buf);
24981 add_compiler_branch_island (labelname, funname, insn_line (insn));
24984 labelname = get_prev_label (funname);
24986 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24987 instruction will reach 'foo', otherwise link as 'bl L42'".
24988 "L42" should be a 'branch island', that will do a far jump to
24989 'foo'. Branch islands are generated in
24990 macho_branch_islands(). */
24991 sprintf (buf, "jbsr %%z%d,%.246s",
24992 dest_operand_number, IDENTIFIER_POINTER (labelname));
24995 sprintf (buf, "bl %%z%d", dest_operand_number);
24999 /* Generate PIC and indirect symbol stubs. */
25002 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25004 unsigned int length;
25005 char *symbol_name, *lazy_ptr_name;
25006 char *local_label_0;
25007 static int label = 0;
25009 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25010 symb = (*targetm.strip_name_encoding) (symb);
25013 length = strlen (symb);
25014 symbol_name = XALLOCAVEC (char, length + 32);
25015 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25017 lazy_ptr_name = XALLOCAVEC (char, length + 32);
25018 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
25021 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
25023 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
25027 fprintf (file, "\t.align 5\n");
25029 fprintf (file, "%s:\n", stub);
25030 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25033 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
25034 sprintf (local_label_0, "\"L%011d$spb\"", label);
25036 fprintf (file, "\tmflr r0\n");
25037 if (TARGET_LINK_STACK)
25040 get_ppc476_thunk_name (name);
25041 fprintf (file, "\tbl %s\n", name);
25042 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25046 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
25047 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25049 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
25050 lazy_ptr_name, local_label_0);
25051 fprintf (file, "\tmtlr r0\n");
25052 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
25053 (TARGET_64BIT ? "ldu" : "lwzu"),
25054 lazy_ptr_name, local_label_0);
25055 fprintf (file, "\tmtctr r12\n");
25056 fprintf (file, "\tbctr\n");
25060 fprintf (file, "\t.align 4\n");
25062 fprintf (file, "%s:\n", stub);
25063 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25065 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
25066 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
25067 (TARGET_64BIT ? "ldu" : "lwzu"),
25069 fprintf (file, "\tmtctr r12\n");
25070 fprintf (file, "\tbctr\n");
25073 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25074 fprintf (file, "%s:\n", lazy_ptr_name);
25075 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25076 fprintf (file, "%sdyld_stub_binding_helper\n",
25077 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
25080 /* Legitimize PIC addresses. If the address is already
25081 position-independent, we return ORIG. Newly generated
25082 position-independent addresses go into a reg. This is REG if non
25083 zero, otherwise we allocate register(s) as necessary. */
25085 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
25088 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
25093 if (reg == NULL && ! reload_in_progress && ! reload_completed)
25094 reg = gen_reg_rtx (Pmode);
25096 if (GET_CODE (orig) == CONST)
25100 if (GET_CODE (XEXP (orig, 0)) == PLUS
25101 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
25104 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
25106 /* Use a different reg for the intermediate value, as
25107 it will be marked UNCHANGING. */
25108 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
25109 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
25112 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
25115 if (GET_CODE (offset) == CONST_INT)
25117 if (SMALL_INT (offset))
25118 return plus_constant (Pmode, base, INTVAL (offset));
25119 else if (! reload_in_progress && ! reload_completed)
25120 offset = force_reg (Pmode, offset);
25123 rtx mem = force_const_mem (Pmode, orig);
25124 return machopic_legitimize_pic_address (mem, Pmode, reg);
25127 return gen_rtx_PLUS (Pmode, base, offset);
25130 /* Fall back on generic machopic code. */
25131 return machopic_legitimize_pic_address (orig, mode, reg);
25134 /* Output a .machine directive for the Darwin assembler, and call
25135 the generic start_file routine. */
25138 rs6000_darwin_file_start (void)
25140 static const struct
25146 { "ppc64", "ppc64", MASK_64BIT },
25147 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
25148 { "power4", "ppc970", 0 },
25149 { "G5", "ppc970", 0 },
25150 { "7450", "ppc7450", 0 },
25151 { "7400", "ppc7400", MASK_ALTIVEC },
25152 { "G4", "ppc7400", 0 },
25153 { "750", "ppc750", 0 },
25154 { "740", "ppc750", 0 },
25155 { "G3", "ppc750", 0 },
25156 { "604e", "ppc604e", 0 },
25157 { "604", "ppc604", 0 },
25158 { "603e", "ppc603", 0 },
25159 { "603", "ppc603", 0 },
25160 { "601", "ppc601", 0 },
25161 { NULL, "ppc", 0 } };
25162 const char *cpu_id = "";
25165 rs6000_file_start ();
25166 darwin_file_start ();
25168 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
25170 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
25171 cpu_id = rs6000_default_cpu;
25173 if (global_options_set.x_rs6000_cpu_index)
25174 cpu_id = processor_target_table[rs6000_cpu_index].name;
25176 /* Look through the mapping array. Pick the first name that either
25177 matches the argument, has a bit set in IF_SET that is also set
25178 in the target flags, or has a NULL name. */
25181 while (mapping[i].arg != NULL
25182 && strcmp (mapping[i].arg, cpu_id) != 0
25183 && (mapping[i].if_set & target_flags) == 0)
25186 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
25189 #endif /* TARGET_MACHO */
25193 rs6000_elf_reloc_rw_mask (void)
25197 else if (DEFAULT_ABI == ABI_AIX)
25203 /* Record an element in the table of global constructors. SYMBOL is
25204 a SYMBOL_REF of the function to be called; PRIORITY is a number
25205 between 0 and MAX_INIT_PRIORITY.
25207 This differs from default_named_section_asm_out_constructor in
25208 that we have special handling for -mrelocatable. */
25210 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
25212 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
25214 const char *section = ".ctors";
25217 if (priority != DEFAULT_INIT_PRIORITY)
25219 sprintf (buf, ".ctors.%.5u",
25220 /* Invert the numbering so the linker puts us in the proper
25221 order; constructors are run from right to left, and the
25222 linker sorts in increasing order. */
25223 MAX_INIT_PRIORITY - priority);
25227 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25228 assemble_align (POINTER_SIZE);
25230 if (TARGET_RELOCATABLE)
25232 fputs ("\t.long (", asm_out_file);
25233 output_addr_const (asm_out_file, symbol);
25234 fputs (")@fixup\n", asm_out_file);
25237 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25240 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
25242 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
25244 const char *section = ".dtors";
25247 if (priority != DEFAULT_INIT_PRIORITY)
25249 sprintf (buf, ".dtors.%.5u",
25250 /* Invert the numbering so the linker puts us in the proper
25251 order; constructors are run from right to left, and the
25252 linker sorts in increasing order. */
25253 MAX_INIT_PRIORITY - priority);
25257 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25258 assemble_align (POINTER_SIZE);
25260 if (TARGET_RELOCATABLE)
25262 fputs ("\t.long (", asm_out_file);
25263 output_addr_const (asm_out_file, symbol);
25264 fputs (")@fixup\n", asm_out_file);
25267 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25271 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
25275 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
25276 ASM_OUTPUT_LABEL (file, name);
25277 fputs (DOUBLE_INT_ASM_OP, file);
25278 rs6000_output_function_entry (file, name);
25279 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
25282 fputs ("\t.size\t", file);
25283 assemble_name (file, name);
25284 fputs (",24\n\t.type\t.", file);
25285 assemble_name (file, name);
25286 fputs (",@function\n", file);
25287 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
25289 fputs ("\t.globl\t.", file);
25290 assemble_name (file, name);
25295 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25296 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25297 rs6000_output_function_entry (file, name);
25298 fputs (":\n", file);
25302 if (TARGET_RELOCATABLE
25303 && !TARGET_SECURE_PLT
25304 && (get_pool_size () != 0 || crtl->profile)
25309 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
25311 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
25312 fprintf (file, "\t.long ");
25313 assemble_name (file, buf);
25315 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25316 assemble_name (file, buf);
25320 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25321 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25323 if (DEFAULT_ABI == ABI_AIX)
25325 const char *desc_name, *orig_name;
25327 orig_name = (*targetm.strip_name_encoding) (name);
25328 desc_name = orig_name;
25329 while (*desc_name == '.')
25332 if (TREE_PUBLIC (decl))
25333 fprintf (file, "\t.globl %s\n", desc_name);
25335 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25336 fprintf (file, "%s:\n", desc_name);
25337 fprintf (file, "\t.long %s\n", orig_name);
25338 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25339 if (DEFAULT_ABI == ABI_AIX)
25340 fputs ("\t.long 0\n", file);
25341 fprintf (file, "\t.previous\n");
25343 ASM_OUTPUT_LABEL (file, name);
25346 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
25348 rs6000_elf_file_end (void)
25350 #ifdef HAVE_AS_GNU_ATTRIBUTE
25351 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25353 if (rs6000_passes_float)
25354 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25355 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25356 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25358 if (rs6000_passes_vector)
25359 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25360 (TARGET_ALTIVEC_ABI ? 2
25361 : TARGET_SPE_ABI ? 3
25363 if (rs6000_returns_struct)
25364 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25365 aix_struct_return ? 2 : 1);
25368 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25370 file_end_indicate_exec_stack ();
25377 rs6000_xcoff_asm_output_anchor (rtx symbol)
25381 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25382 SYMBOL_REF_BLOCK_OFFSET (symbol));
25383 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25387 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25389 fputs (GLOBAL_ASM_OP, stream);
25390 RS6000_OUTPUT_BASENAME (stream, name);
25391 putc ('\n', stream);
25394 /* A get_unnamed_decl callback, used for read-only sections. PTR
25395 points to the section string variable. */
25398 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25400 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25401 *(const char *const *) directive,
25402 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25405 /* Likewise for read-write sections. */
25408 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25410 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25411 *(const char *const *) directive,
25412 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25415 /* A get_unnamed_section callback, used for switching to toc_section. */
25418 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25420 if (TARGET_MINIMAL_TOC)
25422 /* toc_section is always selected at least once from
25423 rs6000_xcoff_file_start, so this is guaranteed to
25424 always be defined once and only once in each file. */
25425 if (!toc_initialized)
25427 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25428 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25429 toc_initialized = 1;
25431 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25432 (TARGET_32BIT ? "" : ",3"));
25435 fputs ("\t.toc\n", asm_out_file);
25438 /* Implement TARGET_ASM_INIT_SECTIONS. */
25441 rs6000_xcoff_asm_init_sections (void)
25443 read_only_data_section
25444 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25445 &xcoff_read_only_section_name);
25447 private_data_section
25448 = get_unnamed_section (SECTION_WRITE,
25449 rs6000_xcoff_output_readwrite_section_asm_op,
25450 &xcoff_private_data_section_name);
25452 read_only_private_data_section
25453 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25454 &xcoff_private_data_section_name);
25457 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25459 readonly_data_section = read_only_data_section;
25460 exception_section = data_section;
25464 rs6000_xcoff_reloc_rw_mask (void)
25470 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25471 tree decl ATTRIBUTE_UNUSED)
25474 static const char * const suffix[3] = { "PR", "RO", "RW" };
25476 if (flags & SECTION_CODE)
25478 else if (flags & SECTION_WRITE)
25483 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25484 (flags & SECTION_CODE) ? "." : "",
25485 name, suffix[smclass], flags & SECTION_ENTSIZE);
25489 rs6000_xcoff_select_section (tree decl, int reloc,
25490 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25492 if (decl_readonly_section (decl, reloc))
25494 if (TREE_PUBLIC (decl))
25495 return read_only_data_section;
25497 return read_only_private_data_section;
25501 if (TREE_PUBLIC (decl))
25502 return data_section;
25504 return private_data_section;
25509 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25513 /* Use select_section for private and uninitialized data. */
25514 if (!TREE_PUBLIC (decl)
25515 || DECL_COMMON (decl)
25516 || DECL_INITIAL (decl) == NULL_TREE
25517 || DECL_INITIAL (decl) == error_mark_node
25518 || (flag_zero_initialized_in_bss
25519 && initializer_zerop (DECL_INITIAL (decl))))
25522 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25523 name = (*targetm.strip_name_encoding) (name);
25524 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25527 /* Select section for constant in constant pool.
25529 On RS/6000, all constants are in the private read-only data area.
25530 However, if this is being placed in the TOC it must be output as a
25534 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25535 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25537 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25538 return toc_section;
25540 return read_only_private_data_section;
25543 /* Remove any trailing [DS] or the like from the symbol name. */
25545 static const char *
25546 rs6000_xcoff_strip_name_encoding (const char *name)
25551 len = strlen (name);
25552 if (name[len - 1] == ']')
25553 return ggc_alloc_string (name, len - 4);
25558 /* Section attributes. AIX is always PIC. */
25560 static unsigned int
25561 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25563 unsigned int align;
25564 unsigned int flags = default_section_type_flags (decl, name, reloc);
25566 /* Align to at least UNIT size. */
25567 if (flags & SECTION_CODE || !decl)
25568 align = MIN_UNITS_PER_WORD;
25570 /* Increase alignment of large objects if not already stricter. */
25571 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25572 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25573 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25575 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25578 /* Output at beginning of assembler file.
25580 Initialize the section names for the RS/6000 at this point.
25582 Specify filename, including full path, to assembler.
25584 We want to go into the TOC section so at least one .toc will be emitted.
25585 Also, in order to output proper .bs/.es pairs, we need at least one static
25586 [RW] section emitted.
25588 Finally, declare mcount when profiling to make the assembler happy. */
25591 rs6000_xcoff_file_start (void)
25593 rs6000_gen_section_name (&xcoff_bss_section_name,
25594 main_input_filename, ".bss_");
25595 rs6000_gen_section_name (&xcoff_private_data_section_name,
25596 main_input_filename, ".rw_");
25597 rs6000_gen_section_name (&xcoff_read_only_section_name,
25598 main_input_filename, ".ro_");
25600 fputs ("\t.file\t", asm_out_file);
25601 output_quoted_string (asm_out_file, main_input_filename);
25602 fputc ('\n', asm_out_file);
25603 if (write_symbols != NO_DEBUG)
25604 switch_to_section (private_data_section);
25605 switch_to_section (text_section);
25607 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25608 rs6000_file_start ();
25611 /* Output at end of assembler file.
25612 On the RS/6000, referencing data should automatically pull in text. */
25615 rs6000_xcoff_file_end (void)
25617 switch_to_section (text_section);
25618 fputs ("_section_.text:\n", asm_out_file);
25619 switch_to_section (data_section);
25620 fputs (TARGET_32BIT
25621 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25624 #endif /* TARGET_XCOFF */
25626 /* Compute a (partial) cost for rtx X. Return true if the complete
25627 cost has been computed, and false if subexpressions should be
25628 scanned. In either case, *TOTAL contains the cost result. */
25631 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25632 int *total, bool speed)
25634 enum machine_mode mode = GET_MODE (x);
25638 /* On the RS/6000, if it is valid in the insn, it is free. */
25640 if (((outer_code == SET
25641 || outer_code == PLUS
25642 || outer_code == MINUS)
25643 && (satisfies_constraint_I (x)
25644 || satisfies_constraint_L (x)))
25645 || (outer_code == AND
25646 && (satisfies_constraint_K (x)
25648 ? satisfies_constraint_L (x)
25649 : satisfies_constraint_J (x))
25650 || mask_operand (x, mode)
25652 && mask64_operand (x, DImode))))
25653 || ((outer_code == IOR || outer_code == XOR)
25654 && (satisfies_constraint_K (x)
25656 ? satisfies_constraint_L (x)
25657 : satisfies_constraint_J (x))))
25658 || outer_code == ASHIFT
25659 || outer_code == ASHIFTRT
25660 || outer_code == LSHIFTRT
25661 || outer_code == ROTATE
25662 || outer_code == ROTATERT
25663 || outer_code == ZERO_EXTRACT
25664 || (outer_code == MULT
25665 && satisfies_constraint_I (x))
25666 || ((outer_code == DIV || outer_code == UDIV
25667 || outer_code == MOD || outer_code == UMOD)
25668 && exact_log2 (INTVAL (x)) >= 0)
25669 || (outer_code == COMPARE
25670 && (satisfies_constraint_I (x)
25671 || satisfies_constraint_K (x)))
25672 || ((outer_code == EQ || outer_code == NE)
25673 && (satisfies_constraint_I (x)
25674 || satisfies_constraint_K (x)
25676 ? satisfies_constraint_L (x)
25677 : satisfies_constraint_J (x))))
25678 || (outer_code == GTU
25679 && satisfies_constraint_I (x))
25680 || (outer_code == LTU
25681 && satisfies_constraint_P (x)))
25686 else if ((outer_code == PLUS
25687 && reg_or_add_cint_operand (x, VOIDmode))
25688 || (outer_code == MINUS
25689 && reg_or_sub_cint_operand (x, VOIDmode))
25690 || ((outer_code == SET
25691 || outer_code == IOR
25692 || outer_code == XOR)
25694 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25696 *total = COSTS_N_INSNS (1);
25702 if (mode == DImode && code == CONST_DOUBLE)
25704 if ((outer_code == IOR || outer_code == XOR)
25705 && CONST_DOUBLE_HIGH (x) == 0
25706 && (CONST_DOUBLE_LOW (x)
25707 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25712 else if ((outer_code == AND && and64_2_operand (x, DImode))
25713 || ((outer_code == SET
25714 || outer_code == IOR
25715 || outer_code == XOR)
25716 && CONST_DOUBLE_HIGH (x) == 0))
25718 *total = COSTS_N_INSNS (1);
25728 /* When optimizing for size, MEM should be slightly more expensive
25729 than generating address, e.g., (plus (reg) (const)).
25730 L1 cache latency is about two instructions. */
25731 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25740 if (FLOAT_MODE_P (mode))
25741 *total = rs6000_cost->fp;
25743 *total = COSTS_N_INSNS (1);
25747 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25748 && satisfies_constraint_I (XEXP (x, 1)))
25750 if (INTVAL (XEXP (x, 1)) >= -256
25751 && INTVAL (XEXP (x, 1)) <= 255)
25752 *total = rs6000_cost->mulsi_const9;
25754 *total = rs6000_cost->mulsi_const;
25756 else if (mode == SFmode)
25757 *total = rs6000_cost->fp;
25758 else if (FLOAT_MODE_P (mode))
25759 *total = rs6000_cost->dmul;
25760 else if (mode == DImode)
25761 *total = rs6000_cost->muldi;
25763 *total = rs6000_cost->mulsi;
25767 if (mode == SFmode)
25768 *total = rs6000_cost->fp;
25770 *total = rs6000_cost->dmul;
25775 if (FLOAT_MODE_P (mode))
25777 *total = mode == DFmode ? rs6000_cost->ddiv
25778 : rs6000_cost->sdiv;
25785 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25786 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
25788 if (code == DIV || code == MOD)
25790 *total = COSTS_N_INSNS (2);
25793 *total = COSTS_N_INSNS (1);
25797 if (GET_MODE (XEXP (x, 1)) == DImode)
25798 *total = rs6000_cost->divdi;
25800 *total = rs6000_cost->divsi;
25802 /* Add in shift and subtract for MOD. */
25803 if (code == MOD || code == UMOD)
25804 *total += COSTS_N_INSNS (2);
25809 *total = COSTS_N_INSNS (4);
25813 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
25817 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
25821 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
25833 *total = COSTS_N_INSNS (1);
25841 /* Handle mul_highpart. */
25842 if (outer_code == TRUNCATE
25843 && GET_CODE (XEXP (x, 0)) == MULT)
25845 if (mode == DImode)
25846 *total = rs6000_cost->muldi;
25848 *total = rs6000_cost->mulsi;
25851 else if (outer_code == AND)
25854 *total = COSTS_N_INSNS (1);
25859 if (GET_CODE (XEXP (x, 0)) == MEM)
25862 *total = COSTS_N_INSNS (1);
25868 if (!FLOAT_MODE_P (mode))
25870 *total = COSTS_N_INSNS (1);
25876 case UNSIGNED_FLOAT:
25879 case FLOAT_TRUNCATE:
25880 *total = rs6000_cost->fp;
25884 if (mode == DFmode)
25887 *total = rs6000_cost->fp;
25891 switch (XINT (x, 1))
25894 *total = rs6000_cost->fp;
25906 *total = COSTS_N_INSNS (1);
25909 else if (FLOAT_MODE_P (mode)
25910 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
25912 *total = rs6000_cost->fp;
25920 /* Carry bit requires mode == Pmode.
25921 NEG or PLUS already counted so only add one. */
25923 && (outer_code == NEG || outer_code == PLUS))
25925 *total = COSTS_N_INSNS (1);
25928 if (outer_code == SET)
25930 if (XEXP (x, 1) == const0_rtx)
25932 if (TARGET_ISEL && !TARGET_MFCRF)
25933 *total = COSTS_N_INSNS (8);
25935 *total = COSTS_N_INSNS (2);
25938 else if (mode == Pmode)
25940 *total = COSTS_N_INSNS (3);
25949 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
25951 if (TARGET_ISEL && !TARGET_MFCRF)
25952 *total = COSTS_N_INSNS (8);
25954 *total = COSTS_N_INSNS (2);
25958 if (outer_code == COMPARE)
25972 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25975 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
25978 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
25981 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25982 "opno = %d, total = %d, speed = %s, x:\n",
25983 ret ? "complete" : "scan inner",
25984 GET_RTX_NAME (code),
25985 GET_RTX_NAME (outer_code),
25988 speed ? "true" : "false");
25995 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25998 rs6000_debug_address_cost (rtx x, bool speed)
26000 int ret = TARGET_ADDRESS_COST (x, speed);
26002 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
26003 ret, speed ? "true" : "false");
26010 /* A C expression returning the cost of moving data from a register of class
26011 CLASS1 to one of CLASS2. */
26014 rs6000_register_move_cost (enum machine_mode mode,
26015 reg_class_t from, reg_class_t to)
26019 if (TARGET_DEBUG_COST)
26022 /* Moves from/to GENERAL_REGS. */
26023 if (reg_classes_intersect_p (to, GENERAL_REGS)
26024 || reg_classes_intersect_p (from, GENERAL_REGS))
26026 reg_class_t rclass = from;
26028 if (! reg_classes_intersect_p (to, GENERAL_REGS))
26031 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
26032 ret = (rs6000_memory_move_cost (mode, rclass, false)
26033 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
26035 /* It's more expensive to move CR_REGS than CR0_REGS because of the
26037 else if (rclass == CR_REGS)
26040 /* For those processors that have slow LR/CTR moves, make them more
26041 expensive than memory in order to bias spills to memory .*/
26042 else if ((rs6000_cpu == PROCESSOR_POWER6
26043 || rs6000_cpu == PROCESSOR_POWER7)
26044 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
26045 ret = 6 * hard_regno_nregs[0][mode];
26048 /* A move will cost one instruction per GPR moved. */
26049 ret = 2 * hard_regno_nregs[0][mode];
26052 /* If we have VSX, we can easily move between FPR or Altivec registers. */
26053 else if (VECTOR_UNIT_VSX_P (mode)
26054 && reg_classes_intersect_p (to, VSX_REGS)
26055 && reg_classes_intersect_p (from, VSX_REGS))
26056 ret = 2 * hard_regno_nregs[32][mode];
26058 /* Moving between two similar registers is just one instruction. */
26059 else if (reg_classes_intersect_p (to, from))
26060 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
26062 /* Everything else has to go through GENERAL_REGS. */
26064 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
26065 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
26067 if (TARGET_DEBUG_COST)
26069 if (dbg_cost_ctrl == 1)
26071 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
26072 ret, GET_MODE_NAME (mode), reg_class_names[from],
26073 reg_class_names[to]);
26080 /* A C expressions returning the cost of moving data of MODE from a register to
26084 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
26085 bool in ATTRIBUTE_UNUSED)
26089 if (TARGET_DEBUG_COST)
26092 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
26093 ret = 4 * hard_regno_nregs[0][mode];
26094 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
26095 ret = 4 * hard_regno_nregs[32][mode];
26096 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
26097 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
26099 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
26101 if (TARGET_DEBUG_COST)
26103 if (dbg_cost_ctrl == 1)
26105 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
26106 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
26113 /* Returns a code for a target-specific builtin that implements
26114 reciprocal of the function, or NULL_TREE if not available. */
26117 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
26118 bool sqrt ATTRIBUTE_UNUSED)
26120 if (optimize_insn_for_size_p ())
26126 case VSX_BUILTIN_XVSQRTDP:
26127 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
26130 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
26132 case VSX_BUILTIN_XVSQRTSP:
26133 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
26136 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
26145 case BUILT_IN_SQRT:
26146 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
26149 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
26151 case BUILT_IN_SQRTF:
26152 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
26155 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
26162 /* Load up a constant. If the mode is a vector mode, splat the value across
26163 all of the vector elements. */
26166 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
26170 if (mode == SFmode || mode == DFmode)
26172 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
26173 reg = force_reg (mode, d);
26175 else if (mode == V4SFmode)
26177 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
26178 rtvec v = gen_rtvec (4, d, d, d, d);
26179 reg = gen_reg_rtx (mode);
26180 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26182 else if (mode == V2DFmode)
26184 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
26185 rtvec v = gen_rtvec (2, d, d);
26186 reg = gen_reg_rtx (mode);
26187 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26190 gcc_unreachable ();
26195 /* Generate an FMA instruction. */
26198 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
26200 enum machine_mode mode = GET_MODE (target);
26203 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26204 gcc_assert (dst != NULL);
26207 emit_move_insn (target, dst);
26210 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
26213 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
26215 enum machine_mode mode = GET_MODE (target);
26218 /* Altivec does not support fms directly;
26219 generate in terms of fma in that case. */
26220 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
26221 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
26224 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
26225 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26227 gcc_assert (dst != NULL);
26230 emit_move_insn (target, dst);
26233 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
26236 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
26238 enum machine_mode mode = GET_MODE (dst);
26241 /* This is a tad more complicated, since the fnma_optab is for
26242 a different expression: fma(-m1, m2, a), which is the same
26243 thing except in the case of signed zeros.
26245 Fortunately we know that if FMA is supported that FNMSUB is
26246 also supported in the ISA. Just expand it directly. */
26248 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
26250 r = gen_rtx_NEG (mode, a);
26251 r = gen_rtx_FMA (mode, m1, m2, r);
26252 r = gen_rtx_NEG (mode, r);
26253 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
26256 /* Newton-Raphson approximation of floating point divide with just 2 passes
26257 (either single precision floating point, or newer machines with higher
26258 accuracy estimates). Support both scalar and vector divide. Assumes no
26259 trapping math and finite arguments. */
26262 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
26264 enum machine_mode mode = GET_MODE (dst);
26265 rtx x0, e0, e1, y1, u0, v0;
26266 enum insn_code code = optab_handler (smul_optab, mode);
26267 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26268 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
26270 gcc_assert (code != CODE_FOR_nothing);
26272 /* x0 = 1./d estimate */
26273 x0 = gen_reg_rtx (mode);
26274 emit_insn (gen_rtx_SET (VOIDmode, x0,
26275 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26278 e0 = gen_reg_rtx (mode);
26279 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
26281 e1 = gen_reg_rtx (mode);
26282 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
26284 y1 = gen_reg_rtx (mode);
26285 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
26287 u0 = gen_reg_rtx (mode);
26288 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
26290 v0 = gen_reg_rtx (mode);
26291 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
26293 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
26296 /* Newton-Raphson approximation of floating point divide that has a low
26297 precision estimate. Assumes no trapping math and finite arguments. */
26300 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
26302 enum machine_mode mode = GET_MODE (dst);
26303 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
26304 enum insn_code code = optab_handler (smul_optab, mode);
26305 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26307 gcc_assert (code != CODE_FOR_nothing);
26309 one = rs6000_load_constant_and_splat (mode, dconst1);
26311 /* x0 = 1./d estimate */
26312 x0 = gen_reg_rtx (mode);
26313 emit_insn (gen_rtx_SET (VOIDmode, x0,
26314 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26317 e0 = gen_reg_rtx (mode);
26318 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
26320 y1 = gen_reg_rtx (mode);
26321 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
26323 e1 = gen_reg_rtx (mode);
26324 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
26326 y2 = gen_reg_rtx (mode);
26327 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26329 e2 = gen_reg_rtx (mode);
26330 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26332 y3 = gen_reg_rtx (mode);
26333 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26335 u0 = gen_reg_rtx (mode);
26336 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26338 v0 = gen_reg_rtx (mode);
26339 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26341 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26344 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26345 add a reg_note saying that this was a division. Support both scalar and
26346 vector divide. Assumes no trapping math and finite arguments. */
26349 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26351 enum machine_mode mode = GET_MODE (dst);
26353 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26354 rs6000_emit_swdiv_high_precision (dst, n, d);
26356 rs6000_emit_swdiv_low_precision (dst, n, d);
26359 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26362 /* Newton-Raphson approximation of single/double-precision floating point
26363 rsqrt. Assumes no trapping math and finite arguments. */
26366 rs6000_emit_swrsqrt (rtx dst, rtx src)
26368 enum machine_mode mode = GET_MODE (src);
26369 rtx x0 = gen_reg_rtx (mode);
26370 rtx y = gen_reg_rtx (mode);
26371 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26372 REAL_VALUE_TYPE dconst3_2;
26375 enum insn_code code = optab_handler (smul_optab, mode);
26376 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26378 gcc_assert (code != CODE_FOR_nothing);
26380 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26381 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26382 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26384 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26386 /* x0 = rsqrt estimate */
26387 emit_insn (gen_rtx_SET (VOIDmode, x0,
26388 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26391 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26392 rs6000_emit_msub (y, src, halfthree, src);
26394 for (i = 0; i < passes; i++)
26396 rtx x1 = gen_reg_rtx (mode);
26397 rtx u = gen_reg_rtx (mode);
26398 rtx v = gen_reg_rtx (mode);
26400 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26401 emit_insn (gen_mul (u, x0, x0));
26402 rs6000_emit_nmsub (v, y, u, halfthree);
26403 emit_insn (gen_mul (x1, x0, v));
26407 emit_move_insn (dst, x0);
26411 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26412 (Power7) targets. DST is the target, and SRC is the argument operand. */
26415 rs6000_emit_popcount (rtx dst, rtx src)
26417 enum machine_mode mode = GET_MODE (dst);
26420 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26421 if (TARGET_POPCNTD)
26423 if (mode == SImode)
26424 emit_insn (gen_popcntdsi2 (dst, src));
26426 emit_insn (gen_popcntddi2 (dst, src));
26430 tmp1 = gen_reg_rtx (mode);
26432 if (mode == SImode)
26434 emit_insn (gen_popcntbsi2 (tmp1, src));
26435 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26437 tmp2 = force_reg (SImode, tmp2);
26438 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26442 emit_insn (gen_popcntbdi2 (tmp1, src));
26443 tmp2 = expand_mult (DImode, tmp1,
26444 GEN_INT ((HOST_WIDE_INT)
26445 0x01010101 << 32 | 0x01010101),
26447 tmp2 = force_reg (DImode, tmp2);
26448 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26453 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26454 target, and SRC is the argument operand. */
26457 rs6000_emit_parity (rtx dst, rtx src)
26459 enum machine_mode mode = GET_MODE (dst);
26462 tmp = gen_reg_rtx (mode);
26464 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26467 if (mode == SImode)
26469 emit_insn (gen_popcntbsi2 (tmp, src));
26470 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26474 emit_insn (gen_popcntbdi2 (tmp, src));
26475 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26480 if (mode == SImode)
26482 /* Is mult+shift >= shift+xor+shift+xor? */
26483 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26485 rtx tmp1, tmp2, tmp3, tmp4;
26487 tmp1 = gen_reg_rtx (SImode);
26488 emit_insn (gen_popcntbsi2 (tmp1, src));
26490 tmp2 = gen_reg_rtx (SImode);
26491 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26492 tmp3 = gen_reg_rtx (SImode);
26493 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26495 tmp4 = gen_reg_rtx (SImode);
26496 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26497 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26500 rs6000_emit_popcount (tmp, src);
26501 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26505 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26506 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26508 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26510 tmp1 = gen_reg_rtx (DImode);
26511 emit_insn (gen_popcntbdi2 (tmp1, src));
26513 tmp2 = gen_reg_rtx (DImode);
26514 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26515 tmp3 = gen_reg_rtx (DImode);
26516 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26518 tmp4 = gen_reg_rtx (DImode);
26519 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26520 tmp5 = gen_reg_rtx (DImode);
26521 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26523 tmp6 = gen_reg_rtx (DImode);
26524 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26525 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26528 rs6000_emit_popcount (tmp, src);
26529 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26533 /* Expand an Altivec constant permutation. Return true if we match
26534 an efficient implementation; false to fall back to VPERM. */
26537 altivec_expand_vec_perm_const (rtx operands[4])
26539 struct altivec_perm_insn {
26540 enum insn_code impl;
26541 unsigned char perm[16];
26543 static const struct altivec_perm_insn patterns[] = {
26544 { CODE_FOR_altivec_vpkuhum,
26545 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26546 { CODE_FOR_altivec_vpkuwum,
26547 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26548 { CODE_FOR_altivec_vmrghb,
26549 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26550 { CODE_FOR_altivec_vmrghh,
26551 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26552 { CODE_FOR_altivec_vmrghw,
26553 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26554 { CODE_FOR_altivec_vmrglb,
26555 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26556 { CODE_FOR_altivec_vmrglh,
26557 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26558 { CODE_FOR_altivec_vmrglw,
26559 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26562 unsigned int i, j, elt, which;
26563 unsigned char perm[16];
26564 rtx target, op0, op1, sel, x;
26567 target = operands[0];
26572 /* Unpack the constant selector. */
26573 for (i = which = 0; i < 16; ++i)
26575 rtx e = XVECEXP (sel, 0, i);
26576 elt = INTVAL (e) & 31;
26577 which |= (elt < 16 ? 1 : 2);
26581 /* Simplify the constant selector based on operands. */
26585 gcc_unreachable ();
26589 if (!rtx_equal_p (op0, op1))
26594 for (i = 0; i < 16; ++i)
26606 /* Look for splat patterns. */
26611 for (i = 0; i < 16; ++i)
26612 if (perm[i] != elt)
26616 emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
26622 for (i = 0; i < 16; i += 2)
26623 if (perm[i] != elt || perm[i + 1] != elt + 1)
26627 x = gen_reg_rtx (V8HImode);
26628 emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
26629 GEN_INT (elt / 2)));
26630 emit_move_insn (target, gen_lowpart (V16QImode, x));
26637 for (i = 0; i < 16; i += 4)
26639 || perm[i + 1] != elt + 1
26640 || perm[i + 2] != elt + 2
26641 || perm[i + 3] != elt + 3)
26645 x = gen_reg_rtx (V4SImode);
26646 emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
26647 GEN_INT (elt / 4)));
26648 emit_move_insn (target, gen_lowpart (V16QImode, x));
26654 /* Look for merge and pack patterns. */
26655 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
26659 elt = patterns[j].perm[0];
26660 if (perm[0] == elt)
26662 else if (perm[0] == elt + 16)
26666 for (i = 1; i < 16; ++i)
26668 elt = patterns[j].perm[i];
26670 elt = (elt >= 16 ? elt - 16 : elt + 16);
26671 else if (one_vec && elt >= 16)
26673 if (perm[i] != elt)
26678 enum insn_code icode = patterns[j].impl;
26679 enum machine_mode omode = insn_data[icode].operand[0].mode;
26680 enum machine_mode imode = insn_data[icode].operand[1].mode;
26683 x = op0, op0 = op1, op1 = x;
26684 if (imode != V16QImode)
26686 op0 = gen_lowpart (imode, op0);
26687 op1 = gen_lowpart (imode, op1);
26689 if (omode == V16QImode)
26692 x = gen_reg_rtx (omode);
26693 emit_insn (GEN_FCN (icode) (x, op0, op1));
26694 if (omode != V16QImode)
26695 emit_move_insn (target, gen_lowpart (V16QImode, x));
26703 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26704 Return true if we match an efficient implementation. */
26707 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
26708 unsigned char perm0, unsigned char perm1)
26712 /* If both selectors come from the same operand, fold to single op. */
26713 if ((perm0 & 2) == (perm1 & 2))
26720 /* If both operands are equal, fold to simpler permutation. */
26721 if (rtx_equal_p (op0, op1))
26724 perm1 = (perm1 & 1) + 2;
26726 /* If the first selector comes from the second operand, swap. */
26727 else if (perm0 & 2)
26733 x = op0, op0 = op1, op1 = x;
26735 /* If the second selector does not come from the second operand, fail. */
26736 else if ((perm1 & 2) == 0)
26740 if (target != NULL)
26742 enum machine_mode vmode, dmode;
26745 vmode = GET_MODE (target);
26746 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
26747 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
26749 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
26750 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
26751 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
26752 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26758 rs6000_expand_vec_perm_const (rtx operands[4])
26760 rtx target, op0, op1, sel;
26761 unsigned char perm0, perm1;
26763 target = operands[0];
26768 /* Unpack the constant selector. */
26769 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
26770 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
26772 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
26775 /* Test whether a constant permutation is supported. */
26778 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
26779 const unsigned char *sel)
26781 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
26782 if (TARGET_ALTIVEC)
26785 /* Check for ps_merge* or evmerge* insns. */
26786 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
26787 || (TARGET_SPE && vmode == V2SImode))
26789 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
26790 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
26791 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
26797 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
26800 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
26801 enum machine_mode vmode, unsigned nelt, rtx perm[])
26803 enum machine_mode imode;
26807 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
26809 imode = GET_MODE_INNER (vmode);
26810 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
26811 imode = mode_for_vector (imode, nelt);
26814 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
26815 x = expand_vec_perm (vmode, op0, op1, x, target);
26817 emit_move_insn (target, x);
26820 /* Expand an extract even operation. */
26823 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
26825 enum machine_mode vmode = GET_MODE (target);
26826 unsigned i, nelt = GET_MODE_NUNITS (vmode);
26829 for (i = 0; i < nelt; i++)
26830 perm[i] = GEN_INT (i * 2);
26832 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26835 /* Expand a vector interleave operation. */
26838 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
26840 enum machine_mode vmode = GET_MODE (target);
26841 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
26844 high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
26845 for (i = 0; i < nelt / 2; i++)
26847 perm[i * 2] = GEN_INT (i + high);
26848 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
26851 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26854 /* Return an RTX representing where to find the function value of a
26855 function returning MODE. */
26857 rs6000_complex_function_value (enum machine_mode mode)
26859 unsigned int regno;
26861 enum machine_mode inner = GET_MODE_INNER (mode);
26862 unsigned int inner_bytes = GET_MODE_SIZE (inner);
26864 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26865 regno = FP_ARG_RETURN;
26868 regno = GP_ARG_RETURN;
26870 /* 32-bit is OK since it'll go in r3/r4. */
26871 if (TARGET_32BIT && inner_bytes >= 4)
26872 return gen_rtx_REG (mode, regno);
26875 if (inner_bytes >= 8)
26876 return gen_rtx_REG (mode, regno);
26878 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
26880 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
26881 GEN_INT (inner_bytes));
26882 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
26885 /* Target hook for TARGET_FUNCTION_VALUE.
26887 On the SPE, both FPs and vectors are returned in r3.
26889 On RS/6000 an integer value is in r3 and a floating-point value is in
26890 fp1, unless -msoft-float. */
26893 rs6000_function_value (const_tree valtype,
26894 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
26895 bool outgoing ATTRIBUTE_UNUSED)
26897 enum machine_mode mode;
26898 unsigned int regno;
26900 /* Special handling for structs in darwin64. */
26902 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
26904 CUMULATIVE_ARGS valcum;
26908 valcum.fregno = FP_ARG_MIN_REG;
26909 valcum.vregno = ALTIVEC_ARG_MIN_REG;
26910 /* Do a trial code generation as if this were going to be passed as
26911 an argument; if any part goes in memory, we return NULL. */
26912 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
26915 /* Otherwise fall through to standard ABI rules. */
26918 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
26920 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26921 return gen_rtx_PARALLEL (DImode,
26923 gen_rtx_EXPR_LIST (VOIDmode,
26924 gen_rtx_REG (SImode, GP_ARG_RETURN),
26926 gen_rtx_EXPR_LIST (VOIDmode,
26927 gen_rtx_REG (SImode,
26928 GP_ARG_RETURN + 1),
26931 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
26933 return gen_rtx_PARALLEL (DCmode,
26935 gen_rtx_EXPR_LIST (VOIDmode,
26936 gen_rtx_REG (SImode, GP_ARG_RETURN),
26938 gen_rtx_EXPR_LIST (VOIDmode,
26939 gen_rtx_REG (SImode,
26940 GP_ARG_RETURN + 1),
26942 gen_rtx_EXPR_LIST (VOIDmode,
26943 gen_rtx_REG (SImode,
26944 GP_ARG_RETURN + 2),
26946 gen_rtx_EXPR_LIST (VOIDmode,
26947 gen_rtx_REG (SImode,
26948 GP_ARG_RETURN + 3),
26952 mode = TYPE_MODE (valtype);
26953 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
26954 || POINTER_TYPE_P (valtype))
26955 mode = TARGET_32BIT ? SImode : DImode;
26957 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26958 /* _Decimal128 must use an even/odd register pair. */
26959 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26960 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
26961 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
26962 regno = FP_ARG_RETURN;
26963 else if (TREE_CODE (valtype) == COMPLEX_TYPE
26964 && targetm.calls.split_complex_arg)
26965 return rs6000_complex_function_value (mode);
26966 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26967 return register is used in both cases, and we won't see V2DImode/V2DFmode
26968 for pure altivec, combine the two cases. */
26969 else if (TREE_CODE (valtype) == VECTOR_TYPE
26970 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
26971 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
26972 regno = ALTIVEC_ARG_RETURN;
26973 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26974 && (mode == DFmode || mode == DCmode
26975 || mode == TFmode || mode == TCmode))
26976 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26978 regno = GP_ARG_RETURN;
26980 return gen_rtx_REG (mode, regno);
26983 /* Define how to find the value returned by a library function
26984 assuming the value has mode MODE. */
26986 rs6000_libcall_value (enum machine_mode mode)
26988 unsigned int regno;
26990 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
26992 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26993 return gen_rtx_PARALLEL (DImode,
26995 gen_rtx_EXPR_LIST (VOIDmode,
26996 gen_rtx_REG (SImode, GP_ARG_RETURN),
26998 gen_rtx_EXPR_LIST (VOIDmode,
26999 gen_rtx_REG (SImode,
27000 GP_ARG_RETURN + 1),
27004 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27005 /* _Decimal128 must use an even/odd register pair. */
27006 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
27007 else if (SCALAR_FLOAT_MODE_P (mode)
27008 && TARGET_HARD_FLOAT && TARGET_FPRS
27009 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
27010 regno = FP_ARG_RETURN;
27011 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27012 return register is used in both cases, and we won't see V2DImode/V2DFmode
27013 for pure altivec, combine the two cases. */
27014 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
27015 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
27016 regno = ALTIVEC_ARG_RETURN;
27017 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
27018 return rs6000_complex_function_value (mode);
27019 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
27020 && (mode == DFmode || mode == DCmode
27021 || mode == TFmode || mode == TCmode))
27022 return spe_build_register_parallel (mode, GP_ARG_RETURN);
27024 regno = GP_ARG_RETURN;
27026 return gen_rtx_REG (mode, regno);
27030 /* Given FROM and TO register numbers, say whether this elimination is allowed.
27031 Frame pointer elimination is automatically handled.
27033 For the RS/6000, if frame pointer elimination is being done, we would like
27034 to convert ap into fp, not sp.
27036 We need r30 if -mminimal-toc was specified, and there are constant pool
27040 rs6000_can_eliminate (const int from, const int to)
27042 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
27043 ? ! frame_pointer_needed
27044 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
27045 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
27049 /* Define the offset between two registers, FROM to be eliminated and its
27050 replacement TO, at the start of a routine. */
27052 rs6000_initial_elimination_offset (int from, int to)
27054 rs6000_stack_t *info = rs6000_stack_info ();
27055 HOST_WIDE_INT offset;
27057 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27058 offset = info->push_p ? 0 : -info->total_size;
27059 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27061 offset = info->push_p ? 0 : -info->total_size;
27062 if (FRAME_GROWS_DOWNWARD)
27063 offset += info->fixed_size + info->vars_size + info->parm_size;
27065 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27066 offset = FRAME_GROWS_DOWNWARD
27067 ? info->fixed_size + info->vars_size + info->parm_size
27069 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27070 offset = info->total_size;
27071 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27072 offset = info->push_p ? info->total_size : 0;
27073 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
27076 gcc_unreachable ();
27082 rs6000_dwarf_register_span (rtx reg)
27086 unsigned regno = REGNO (reg);
27087 enum machine_mode mode = GET_MODE (reg);
27091 && (SPE_VECTOR_MODE (GET_MODE (reg))
27092 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
27093 && mode != SFmode && mode != SDmode && mode != SCmode)))
27098 regno = REGNO (reg);
27100 /* The duality of the SPE register size wreaks all kinds of havoc.
27101 This is a way of distinguishing r0 in 32-bits from r0 in
27103 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
27104 gcc_assert (words <= 4);
27105 for (i = 0; i < words; i++, regno++)
27107 if (BYTES_BIG_ENDIAN)
27109 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
27110 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
27114 parts[2 * i] = gen_rtx_REG (SImode, regno);
27115 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
27119 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
27122 /* Fill in sizes for SPE register high parts in table used by unwinder. */
27125 rs6000_init_dwarf_reg_sizes_extra (tree address)
27130 enum machine_mode mode = TYPE_MODE (char_type_node);
27131 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
27132 rtx mem = gen_rtx_MEM (BLKmode, addr);
27133 rtx value = gen_int_mode (4, mode);
27135 for (i = 1201; i < 1232; i++)
27137 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
27138 HOST_WIDE_INT offset
27139 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
27141 emit_move_insn (adjust_address (mem, mode, offset), value);
27146 /* Map internal gcc register numbers to DWARF2 register numbers. */
27149 rs6000_dbx_register_number (unsigned int regno)
27151 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
27153 if (regno == MQ_REGNO)
27155 if (regno == LR_REGNO)
27157 if (regno == CTR_REGNO)
27159 if (CR_REGNO_P (regno))
27160 return regno - CR0_REGNO + 86;
27161 if (regno == CA_REGNO)
27162 return 101; /* XER */
27163 if (ALTIVEC_REGNO_P (regno))
27164 return regno - FIRST_ALTIVEC_REGNO + 1124;
27165 if (regno == VRSAVE_REGNO)
27167 if (regno == VSCR_REGNO)
27169 if (regno == SPE_ACC_REGNO)
27171 if (regno == SPEFSCR_REGNO)
27173 /* SPE high reg number. We get these values of regno from
27174 rs6000_dwarf_register_span. */
27175 gcc_assert (regno >= 1200 && regno < 1232);
27179 /* target hook eh_return_filter_mode */
27180 static enum machine_mode
27181 rs6000_eh_return_filter_mode (void)
27183 return TARGET_32BIT ? SImode : word_mode;
27186 /* Target hook for scalar_mode_supported_p. */
27188 rs6000_scalar_mode_supported_p (enum machine_mode mode)
27190 if (DECIMAL_FLOAT_MODE_P (mode))
27191 return default_decimal_float_supported_p ();
27193 return default_scalar_mode_supported_p (mode);
27196 /* Target hook for vector_mode_supported_p. */
27198 rs6000_vector_mode_supported_p (enum machine_mode mode)
27201 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
27204 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
27207 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
27214 /* Target hook for invalid_arg_for_unprototyped_fn. */
27215 static const char *
27216 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
27218 return (!rs6000_darwin64_abi
27220 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
27221 && (funcdecl == NULL_TREE
27222 || (TREE_CODE (funcdecl) == FUNCTION_DECL
27223 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
27224 ? N_("AltiVec argument passed to unprototyped function")
27228 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27229 setup by using __stack_chk_fail_local hidden function instead of
27230 calling __stack_chk_fail directly. Otherwise it is better to call
27231 __stack_chk_fail directly. */
27233 static tree ATTRIBUTE_UNUSED
27234 rs6000_stack_protect_fail (void)
27236 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
27237 ? default_hidden_stack_protect_fail ()
27238 : default_external_stack_protect_fail ();
27242 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
27243 int num_operands ATTRIBUTE_UNUSED)
27245 if (rs6000_warn_cell_microcode)
27248 int insn_code_number = recog_memoized (insn);
27249 location_t location = locator_location (INSN_LOCATOR (insn));
27251 /* Punt on insns we cannot recognize. */
27252 if (insn_code_number < 0)
27255 temp = get_insn_template (insn_code_number, insn);
27257 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
27258 warning_at (location, OPT_mwarn_cell_microcode,
27259 "emitting microcode insn %s\t[%s] #%d",
27260 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27261 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
27262 warning_at (location, OPT_mwarn_cell_microcode,
27263 "emitting conditional microcode insn %s\t[%s] #%d",
27264 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27269 /* Mask options that we want to support inside of attribute((target)) and
27270 #pragma GCC target operations. Note, we do not include things like
27271 64/32-bit, endianess, hard/soft floating point, etc. that would have
27272 different calling sequences. */
27274 struct rs6000_opt_mask {
27275 const char *name; /* option name */
27276 int mask; /* mask to set */
27277 bool invert; /* invert sense of mask */
27278 bool valid_target; /* option is a target option */
27281 static struct rs6000_opt_mask const rs6000_opt_masks[] =
27283 { "altivec", MASK_ALTIVEC, false, true },
27284 { "cmpb", MASK_CMPB, false, true },
27285 { "dlmzb", MASK_DLMZB, false, true },
27286 { "fprnd", MASK_FPRND, false, true },
27287 { "hard-dfp", MASK_DFP, false, true },
27288 { "isel", MASK_ISEL, false, true },
27289 { "mfcrf", MASK_MFCRF, false, true },
27290 { "mfpgpr", MASK_MFPGPR, false, true },
27291 { "mulhw", MASK_MULHW, false, true },
27292 { "multiple", MASK_MULTIPLE, false, true },
27293 { "update", MASK_NO_UPDATE, true , true },
27294 { "popcntb", MASK_POPCNTB, false, true },
27295 { "popcntd", MASK_POPCNTD, false, true },
27296 { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
27297 { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
27298 { "recip-precision", MASK_RECIP_PRECISION, false, true },
27299 { "string", MASK_STRING, false, true },
27300 { "vsx", MASK_VSX, false, true },
27303 { "aix64", MASK_64BIT, false, false },
27304 { "aix32", MASK_64BIT, true, false },
27306 { "64", MASK_64BIT, false, false },
27307 { "32", MASK_64BIT, true, false },
27311 { "eabi", MASK_EABI, false, false },
27313 #ifdef MASK_LITTLE_ENDIAN
27314 { "little", MASK_LITTLE_ENDIAN, false, false },
27315 { "big", MASK_LITTLE_ENDIAN, true, false },
27317 #ifdef MASK_RELOCATABLE
27318 { "relocatable", MASK_RELOCATABLE, false, false },
27320 #ifdef MASK_STRICT_ALIGN
27321 { "strict-align", MASK_STRICT_ALIGN, false, false },
27323 { "power", MASK_POWER, false, false },
27324 { "power2", MASK_POWER2, false, false },
27325 { "powerpc", MASK_POWERPC, false, false },
27326 { "soft-float", MASK_SOFT_FLOAT, false, false },
27327 { "string", MASK_STRING, false, false },
27330 /* Builtin mask mapping for printing the flags. */
27331 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27333 { "altivec", RS6000_BTM_ALTIVEC, false, false },
27334 { "vsx", RS6000_BTM_VSX, false, false },
27335 { "spe", RS6000_BTM_SPE, false, false },
27336 { "paired", RS6000_BTM_PAIRED, false, false },
27337 { "fre", RS6000_BTM_FRE, false, false },
27338 { "fres", RS6000_BTM_FRES, false, false },
27339 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
27340 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
27341 { "popcntd", RS6000_BTM_POPCNTD, false, false },
27342 { "powerpc", RS6000_BTM_POWERPC, false, false },
27343 { "cell", RS6000_BTM_CELL, false, false },
27346 /* Option variables that we want to support inside attribute((target)) and
27347 #pragma GCC target operations. */
27349 struct rs6000_opt_var {
27350 const char *name; /* option name */
27351 size_t global_offset; /* offset of the option in global_options. */
27352 size_t target_offset; /* offset of the option in target optiosn. */
27355 static struct rs6000_opt_var const rs6000_opt_vars[] =
27358 offsetof (struct gcc_options, x_TARGET_FRIZ),
27359 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27360 { "avoid-indexed-addresses",
27361 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27362 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27364 offsetof (struct gcc_options, x_rs6000_paired_float),
27365 offsetof (struct cl_target_option, x_rs6000_paired_float), },
27367 offsetof (struct gcc_options, x_rs6000_default_long_calls),
27368 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27371 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27372 parsing. Return true if there were no errors. */
27375 rs6000_inner_target_options (tree args, bool attr_p)
27379 if (args == NULL_TREE)
27382 else if (TREE_CODE (args) == STRING_CST)
27384 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27387 while ((q = strtok (p, ",")) != NULL)
27389 bool error_p = false;
27390 bool not_valid_p = false;
27391 const char *cpu_opt = NULL;
27394 if (strncmp (q, "cpu=", 4) == 0)
27396 int cpu_index = rs6000_cpu_name_lookup (q+4);
27397 if (cpu_index >= 0)
27398 rs6000_cpu_index = cpu_index;
27405 else if (strncmp (q, "tune=", 5) == 0)
27407 int tune_index = rs6000_cpu_name_lookup (q+5);
27408 if (tune_index >= 0)
27409 rs6000_tune_index = tune_index;
27419 bool invert = false;
27423 if (strncmp (r, "no-", 3) == 0)
27429 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27430 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27432 int mask = rs6000_opt_masks[i].mask;
27434 if (!rs6000_opt_masks[i].valid_target)
27435 not_valid_p = true;
27439 target_flags_explicit |= mask;
27441 /* VSX needs altivec, so -mvsx automagically sets
27443 if (mask == MASK_VSX && !invert)
27444 mask |= MASK_ALTIVEC;
27446 if (rs6000_opt_masks[i].invert)
27450 target_flags &= ~mask;
27452 target_flags |= mask;
27457 if (error_p && !not_valid_p)
27459 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27460 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27462 size_t j = rs6000_opt_vars[i].global_offset;
27463 *((int *) ((char *)&global_options + j)) = !invert;
27472 const char *eprefix, *esuffix;
27477 eprefix = "__attribute__((__target__(";
27482 eprefix = "#pragma GCC target ";
27487 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27489 else if (not_valid_p)
27490 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27492 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27497 else if (TREE_CODE (args) == TREE_LIST)
27501 tree value = TREE_VALUE (args);
27504 bool ret2 = rs6000_inner_target_options (value, attr_p);
27508 args = TREE_CHAIN (args);
27510 while (args != NULL_TREE);
27514 gcc_unreachable ();
27519 /* Print out the target options as a list for -mdebug=target. */
27522 rs6000_debug_target_options (tree args, const char *prefix)
27524 if (args == NULL_TREE)
27525 fprintf (stderr, "%s<NULL>", prefix);
27527 else if (TREE_CODE (args) == STRING_CST)
27529 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27532 while ((q = strtok (p, ",")) != NULL)
27535 fprintf (stderr, "%s\"%s\"", prefix, q);
27540 else if (TREE_CODE (args) == TREE_LIST)
27544 tree value = TREE_VALUE (args);
27547 rs6000_debug_target_options (value, prefix);
27550 args = TREE_CHAIN (args);
27552 while (args != NULL_TREE);
27556 gcc_unreachable ();
27562 /* Hook to validate attribute((target("..."))). */
27565 rs6000_valid_attribute_p (tree fndecl,
27566 tree ARG_UNUSED (name),
27570 struct cl_target_option cur_target;
27572 tree old_optimize = build_optimization_node ();
27573 tree new_target, new_optimize;
27574 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27576 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27578 if (TARGET_DEBUG_TARGET)
27580 tree tname = DECL_NAME (fndecl);
27581 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27583 fprintf (stderr, "function: %.*s\n",
27584 (int) IDENTIFIER_LENGTH (tname),
27585 IDENTIFIER_POINTER (tname));
27587 fprintf (stderr, "function: unknown\n");
27589 fprintf (stderr, "args:");
27590 rs6000_debug_target_options (args, " ");
27591 fprintf (stderr, "\n");
27594 fprintf (stderr, "flags: 0x%x\n", flags);
27596 fprintf (stderr, "--------------------\n");
27599 old_optimize = build_optimization_node ();
27600 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27602 /* If the function changed the optimization levels as well as setting target
27603 options, start with the optimizations specified. */
27604 if (func_optimize && func_optimize != old_optimize)
27605 cl_optimization_restore (&global_options,
27606 TREE_OPTIMIZATION (func_optimize));
27608 /* The target attributes may also change some optimization flags, so update
27609 the optimization options if necessary. */
27610 cl_target_option_save (&cur_target, &global_options);
27611 rs6000_cpu_index = rs6000_tune_index = -1;
27612 ret = rs6000_inner_target_options (args, true);
27614 /* Set up any additional state. */
27617 ret = rs6000_option_override_internal (false);
27618 new_target = build_target_option_node ();
27623 new_optimize = build_optimization_node ();
27630 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
27632 if (old_optimize != new_optimize)
27633 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
27636 cl_target_option_restore (&global_options, &cur_target);
27638 if (old_optimize != new_optimize)
27639 cl_optimization_restore (&global_options,
27640 TREE_OPTIMIZATION (old_optimize));
27646 /* Hook to validate the current #pragma GCC target and set the state, and
27647 update the macros based on what was changed. If ARGS is NULL, then
27648 POP_TARGET is used to reset the options. */
27651 rs6000_pragma_target_parse (tree args, tree pop_target)
27653 tree prev_tree = build_target_option_node ();
27655 struct cl_target_option *prev_opt, *cur_opt;
27656 unsigned prev_bumask, cur_bumask, diff_bumask;
27657 int prev_flags, cur_flags, diff_flags;
27659 if (TARGET_DEBUG_TARGET)
27661 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27662 fprintf (stderr, "args:");
27663 rs6000_debug_target_options (args, " ");
27664 fprintf (stderr, "\n");
27668 fprintf (stderr, "pop_target:\n");
27669 debug_tree (pop_target);
27672 fprintf (stderr, "pop_target: <NULL>\n");
27674 fprintf (stderr, "--------------------\n");
27679 cur_tree = ((pop_target)
27681 : target_option_default_node);
27682 cl_target_option_restore (&global_options,
27683 TREE_TARGET_OPTION (cur_tree));
27687 rs6000_cpu_index = rs6000_tune_index = -1;
27688 if (!rs6000_inner_target_options (args, false)
27689 || !rs6000_option_override_internal (false)
27690 || (cur_tree = build_target_option_node ()) == NULL_TREE)
27692 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27693 fprintf (stderr, "invalid pragma\n");
27699 target_option_current_node = cur_tree;
27701 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27702 change the macros that are defined. */
27703 if (rs6000_target_modify_macros_ptr)
27705 prev_opt = TREE_TARGET_OPTION (prev_tree);
27706 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27707 prev_flags = prev_opt->x_target_flags;
27709 cur_opt = TREE_TARGET_OPTION (cur_tree);
27710 cur_flags = cur_opt->x_target_flags;
27711 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27713 diff_bumask = (prev_bumask ^ cur_bumask);
27714 diff_flags = (prev_flags ^ cur_flags);
27716 if ((diff_flags != 0) || (diff_bumask != 0))
27718 /* Delete old macros. */
27719 rs6000_target_modify_macros_ptr (false,
27720 prev_flags & diff_flags,
27721 prev_bumask & diff_bumask);
27723 /* Define new macros. */
27724 rs6000_target_modify_macros_ptr (true,
27725 cur_flags & diff_flags,
27726 cur_bumask & diff_bumask);
27734 /* Remember the last target of rs6000_set_current_function. */
27735 static GTY(()) tree rs6000_previous_fndecl;
27737 /* Establish appropriate back-end context for processing the function
27738 FNDECL. The argument might be NULL to indicate processing at top
27739 level, outside of any function scope. */
27741 rs6000_set_current_function (tree fndecl)
27743 tree old_tree = (rs6000_previous_fndecl
27744 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
27747 tree new_tree = (fndecl
27748 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
27751 if (TARGET_DEBUG_TARGET)
27753 bool print_final = false;
27754 fprintf (stderr, "\n==================== rs6000_set_current_function");
27757 fprintf (stderr, ", fndecl %s (%p)",
27758 (DECL_NAME (fndecl)
27759 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
27760 : "<unknown>"), (void *)fndecl);
27762 if (rs6000_previous_fndecl)
27763 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
27765 fprintf (stderr, "\n");
27768 fprintf (stderr, "\nnew fndecl target specific options:\n");
27769 debug_tree (new_tree);
27770 print_final = true;
27775 fprintf (stderr, "\nold fndecl target specific options:\n");
27776 debug_tree (old_tree);
27777 print_final = true;
27781 fprintf (stderr, "--------------------\n");
27784 /* Only change the context if the function changes. This hook is called
27785 several times in the course of compiling a function, and we don't want to
27786 slow things down too much or call target_reinit when it isn't safe. */
27787 if (fndecl && fndecl != rs6000_previous_fndecl)
27789 rs6000_previous_fndecl = fndecl;
27790 if (old_tree == new_tree)
27795 cl_target_option_restore (&global_options,
27796 TREE_TARGET_OPTION (new_tree));
27802 struct cl_target_option *def
27803 = TREE_TARGET_OPTION (target_option_current_node);
27805 cl_target_option_restore (&global_options, def);
27812 /* Save the current options */
27815 rs6000_function_specific_save (struct cl_target_option *ptr)
27817 ptr->rs6000_target_flags_explicit = target_flags_explicit;
27820 /* Restore the current options */
27823 rs6000_function_specific_restore (struct cl_target_option *ptr)
27825 target_flags_explicit = ptr->rs6000_target_flags_explicit;
27826 (void) rs6000_option_override_internal (false);
27829 /* Print the current options */
27832 rs6000_function_specific_print (FILE *file, int indent,
27833 struct cl_target_option *ptr)
27836 int flags = ptr->x_target_flags;
27837 unsigned bu_mask = ptr->x_rs6000_builtin_mask;
27839 /* Print the various mask options. */
27840 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27841 if ((flags & rs6000_opt_masks[i].mask) != 0)
27843 flags &= ~ rs6000_opt_masks[i].mask;
27844 fprintf (file, "%*s-m%s%s\n", indent, "",
27845 rs6000_opt_masks[i].invert ? "no-" : "",
27846 rs6000_opt_masks[i].name);
27849 /* Print the various options that are variables. */
27850 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27852 size_t j = rs6000_opt_vars[i].target_offset;
27853 if (((signed char *) ptr)[j])
27854 fprintf (file, "%*s-m%s\n", indent, "",
27855 rs6000_opt_vars[i].name);
27858 /* Print the various builtin flags. */
27859 fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
27860 for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
27861 if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
27863 fprintf (file, "%*s%s builtins supported\n", indent, "",
27864 rs6000_builtin_mask_names[i].name);
27869 /* Hook to determine if one function can safely inline another. */
27872 rs6000_can_inline_p (tree caller, tree callee)
27875 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
27876 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
27878 /* If callee has no option attributes, then it is ok to inline. */
27882 /* If caller has no option attributes, but callee does then it is not ok to
27884 else if (!caller_tree)
27889 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
27890 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
27892 /* Callee's options should a subset of the caller's, i.e. a vsx function
27893 can inline an altivec function but a non-vsx function can't inline a
27895 if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
27896 == callee_opts->x_target_flags)
27900 if (TARGET_DEBUG_TARGET)
27901 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27902 (DECL_NAME (caller)
27903 ? IDENTIFIER_POINTER (DECL_NAME (caller))
27905 (DECL_NAME (callee)
27906 ? IDENTIFIER_POINTER (DECL_NAME (callee))
27908 (ret ? "can" : "cannot"));
27913 /* Allocate a stack temp and fixup the address so it meets the particular
27914 memory requirements (either offetable or REG+REG addressing). */
27917 rs6000_allocate_stack_temp (enum machine_mode mode,
27918 bool offsettable_p,
27921 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
27922 rtx addr = XEXP (stack, 0);
27923 int strict_p = (reload_in_progress || reload_completed);
27925 if (!legitimate_indirect_address_p (addr, strict_p))
27928 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
27929 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27931 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
27932 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27938 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27939 to such a form to deal with memory reference instructions like STFIWX that
27940 only take reg+reg addressing. */
27943 rs6000_address_for_fpconvert (rtx x)
27945 int strict_p = (reload_in_progress || reload_completed);
27948 gcc_assert (MEM_P (x));
27949 addr = XEXP (x, 0);
27950 if (! legitimate_indirect_address_p (addr, strict_p)
27951 && ! legitimate_indexed_address_p (addr, strict_p))
27953 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
27955 rtx reg = XEXP (addr, 0);
27956 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
27957 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
27958 gcc_assert (REG_P (reg));
27959 emit_insn (gen_add3_insn (reg, reg, size_rtx));
27962 else if (GET_CODE (addr) == PRE_MODIFY)
27964 rtx reg = XEXP (addr, 0);
27965 rtx expr = XEXP (addr, 1);
27966 gcc_assert (REG_P (reg));
27967 gcc_assert (GET_CODE (expr) == PLUS);
27968 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
27972 x = replace_equiv_address (x, copy_addr_to_reg (addr));
27978 /* Given a memory reference, if it is not in the form for altivec memory
27979 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27980 convert to the altivec format. */
27983 rs6000_address_for_altivec (rtx x)
27985 gcc_assert (MEM_P (x));
27986 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
27988 rtx addr = XEXP (x, 0);
27989 int strict_p = (reload_in_progress || reload_completed);
27991 if (!legitimate_indexed_address_p (addr, strict_p)
27992 && !legitimate_indirect_address_p (addr, strict_p))
27993 addr = copy_to_mode_reg (Pmode, addr);
27995 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
27996 x = change_address (x, GET_MODE (x), addr);
28002 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
28004 On the RS/6000, all integer constants are acceptable, most won't be valid
28005 for particular insns, though. Only easy FP constants are acceptable. */
28008 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
28010 if (rs6000_tls_referenced_p (x))
28013 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
28014 || GET_MODE (x) == VOIDmode
28015 || (TARGET_POWERPC64 && mode == DImode)
28016 || easy_fp_constant (x, mode)
28017 || easy_vector_constant (x, mode));
28021 /* A function pointer under AIX is a pointer to a data area whose first word
28022 contains the actual address of the function, whose second word contains a
28023 pointer to its TOC, and whose third word contains a value to place in the
28024 static chain register (r11). Note that if we load the static chain, our
28025 "trampoline" need not have any executable code. */
28028 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
28034 rtx stack_toc_offset;
28036 rtx func_toc_offset;
28038 rtx func_sc_offset;
28041 rtx (*call_func) (rtx, rtx, rtx, rtx);
28042 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
28044 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28045 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
28047 /* Load up address of the actual function. */
28048 func_desc = force_reg (Pmode, func_desc);
28049 func_addr = gen_reg_rtx (Pmode);
28050 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
28055 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
28056 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
28057 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
28058 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28060 call_func = gen_call_indirect_aix32bit;
28061 call_value_func = gen_call_value_indirect_aix32bit;
28065 call_func = gen_call_indirect_aix32bit_nor11;
28066 call_value_func = gen_call_value_indirect_aix32bit_nor11;
28071 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
28072 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
28073 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
28074 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28076 call_func = gen_call_indirect_aix64bit;
28077 call_value_func = gen_call_value_indirect_aix64bit;
28081 call_func = gen_call_indirect_aix64bit_nor11;
28082 call_value_func = gen_call_value_indirect_aix64bit_nor11;
28086 /* Reserved spot to store the TOC. */
28087 stack_toc_mem = gen_frame_mem (Pmode,
28088 gen_rtx_PLUS (Pmode,
28090 stack_toc_offset));
28093 gcc_assert (cfun->machine);
28095 /* Can we optimize saving the TOC in the prologue or do we need to do it at
28097 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
28098 cfun->machine->save_toc_in_prologue = true;
28102 MEM_VOLATILE_P (stack_toc_mem) = 1;
28103 emit_move_insn (stack_toc_mem, toc_reg);
28106 /* Calculate the address to load the TOC of the called function. We don't
28107 actually load this until the split after reload. */
28108 func_toc_mem = gen_rtx_MEM (Pmode,
28109 gen_rtx_PLUS (Pmode,
28113 /* If we have a static chain, load it up. */
28114 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28116 func_sc_mem = gen_rtx_MEM (Pmode,
28117 gen_rtx_PLUS (Pmode,
28121 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
28122 emit_move_insn (sc_reg, func_sc_mem);
28125 /* Create the call. */
28127 insn = call_value_func (value, func_addr, flag, func_toc_mem,
28130 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
28132 emit_call_insn (insn);
28135 /* Return whether we need to always update the saved TOC pointer when we update
28136 the stack pointer. */
28139 rs6000_save_toc_in_prologue_p (void)
28141 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
28144 #ifdef HAVE_GAS_HIDDEN
28145 # define USE_HIDDEN_LINKONCE 1
28147 # define USE_HIDDEN_LINKONCE 0
28150 /* Fills in the label name that should be used for a 476 link stack thunk. */
28153 get_ppc476_thunk_name (char name[32])
28155 gcc_assert (TARGET_LINK_STACK);
28157 if (USE_HIDDEN_LINKONCE)
28158 sprintf (name, "__ppc476.get_thunk");
28160 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
28163 /* This function emits the simple thunk routine that is used to preserve
28164 the link stack on the 476 cpu. */
28166 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
28168 rs6000_code_end (void)
28173 if (!TARGET_LINK_STACK)
28176 get_ppc476_thunk_name (name);
28178 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
28179 build_function_type_list (void_type_node, NULL_TREE));
28180 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
28181 NULL_TREE, void_type_node);
28182 TREE_PUBLIC (decl) = 1;
28183 TREE_STATIC (decl) = 1;
28185 if (USE_HIDDEN_LINKONCE)
28187 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
28188 targetm.asm_out.unique_section (decl, 0);
28189 switch_to_section (get_named_section (decl, NULL, 0));
28190 DECL_WEAK (decl) = 1;
28191 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
28192 targetm.asm_out.globalize_label (asm_out_file, name);
28193 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
28194 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
28198 switch_to_section (text_section);
28199 ASM_OUTPUT_LABEL (asm_out_file, name);
28202 DECL_INITIAL (decl) = make_node (BLOCK);
28203 current_function_decl = decl;
28204 init_function_start (decl);
28205 first_function_block_is_cold = false;
28206 /* Make sure unwind info is emitted for the thunk if needed. */
28207 final_start_function (emit_barrier (), asm_out_file, 1);
28209 fputs ("\tblr\n", asm_out_file);
28211 final_end_function ();
28212 init_insn_lengths ();
28213 free_after_compilation (cfun);
28215 current_function_decl = NULL;
28218 /* Add r30 to hard reg set if the prologue sets it up and it is not
28219 pic_offset_table_rtx. */
28222 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
28224 if (!TARGET_SINGLE_PIC_BASE
28226 && TARGET_MINIMAL_TOC
28227 && get_pool_size () != 0)
28228 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
28231 struct gcc_target targetm = TARGET_INITIALIZER;
28233 #include "gt-rs6000.h"