1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 #define min(A,B) ((A) < (B) ? (A) : (B))
107 #define max(A,B) ((A) > (B) ? (A) : (B))
109 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
111 /* Structure used to define the rs6000 stack */
112 typedef struct rs6000_stack {
113 int reload_completed; /* stack info won't change from here on */
114 int first_gp_reg_save; /* first callee saved GP register used */
115 int first_fp_reg_save; /* first callee saved FP register used */
116 int first_altivec_reg_save; /* first callee saved AltiVec register used */
117 int lr_save_p; /* true if the link reg needs to be saved */
118 int cr_save_p; /* true if the CR reg needs to be saved */
119 unsigned int vrsave_mask; /* mask of vec registers to save */
120 int push_p; /* true if we need to allocate stack space */
121 int calls_p; /* true if the function makes any calls */
122 int world_save_p; /* true if we're saving *everything*:
123 r13-r31, cr, f14-f31, vrsave, v20-v31 */
124 enum rs6000_abi abi; /* which ABI to use */
125 int gp_save_offset; /* offset to save GP regs from initial SP */
126 int fp_save_offset; /* offset to save FP regs from initial SP */
127 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
128 int lr_save_offset; /* offset to save LR from initial SP */
129 int cr_save_offset; /* offset to save CR from initial SP */
130 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
131 int varargs_save_offset; /* offset to save the varargs registers */
132 int ehrd_offset; /* offset to EH return data */
133 int ehcr_offset; /* offset to EH CR field data */
134 int reg_size; /* register size (4 or 8) */
135 HOST_WIDE_INT vars_size; /* variable save area size */
136 int parm_size; /* outgoing parameter size */
137 int save_size; /* save area size */
138 int fixed_size; /* fixed size of stack frame */
139 int gp_size; /* size of saved GP registers */
140 int fp_size; /* size of saved FP registers */
141 int altivec_size; /* size of saved AltiVec registers */
142 int cr_size; /* size to hold CR if not in fixed area */
143 int vrsave_size; /* size to hold VRSAVE */
144 int altivec_padding_size; /* size of altivec alignment padding */
145 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
149 /* A C structure for machine-specific, per-function data.
150 This is added to the cfun structure. */
151 typedef struct GTY(()) machine_function
153 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
154 int ra_needs_full_frame;
155 /* Flags if __builtin_return_address (0) was used. */
157 /* Cache lr_save_p after expansion of builtin_eh_return. */
159 /* Whether we need to save the TOC to the reserved stack location in the
160 function prologue. */
161 bool save_toc_in_prologue;
162 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
163 varargs save area. */
164 HOST_WIDE_INT varargs_save_offset;
165 /* Alternative internal arg pointer for -fsplit-stack. */
166 rtx split_stack_arg_pointer;
167 bool split_stack_argp_used;
168 /* Flag if r2 setup is needed with ELFv2 ABI. */
169 bool r2_setup_needed;
170 /* The number of components we use for separate shrink-wrapping. */
172 /* The components already handled by separate shrink-wrapping, which should
173 not be considered by the prologue and epilogue. */
174 bool gpr_is_wrapped_separately[32];
175 bool fpr_is_wrapped_separately[32];
176 bool lr_is_wrapped_separately;
177 bool toc_is_wrapped_separately;
180 /* Support targetm.vectorize.builtin_mask_for_load. */
181 static GTY(()) tree altivec_builtin_mask_for_load;
183 /* Set to nonzero once AIX common-mode calls have been defined. */
184 static GTY(()) int common_mode_defined;
186 /* Label number of label created for -mrelocatable, to call to so we can
187 get the address of the GOT section */
188 static int rs6000_pic_labelno;
191 /* Counter for labels which are to be placed in .fixup. */
192 int fixuplabelno = 0;
195 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
198 /* Specify the machine mode that pointers have. After generation of rtl, the
199 compiler makes no further distinction between pointers and any other objects
200 of this machine mode. */
201 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
210 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
211 name used in current releases (i.e. u9__ieee128). */
212 static bool ieee128_mangling_gcc_8_1;
214 /* Width in bits of a pointer. */
215 unsigned rs6000_pointer_size;
217 #ifdef HAVE_AS_GNU_ATTRIBUTE
218 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
219 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
221 /* Flag whether floating point values have been passed/returned.
222 Note that this doesn't say whether fprs are used, since the
223 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
224 should be set for soft-float values passed in gprs and ieee128
225 values passed in vsx registers. */
226 static bool rs6000_passes_float;
227 static bool rs6000_passes_long_double;
228 /* Flag whether vector values have been passed/returned. */
229 static bool rs6000_passes_vector;
230 /* Flag whether small (<= 8 byte) structures have been returned. */
231 static bool rs6000_returns_struct;
234 /* Value is TRUE if register/mode pair is acceptable. */
235 static bool rs6000_hard_regno_mode_ok_p
236 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
238 /* Maximum number of registers needed for a given register class and mode. */
239 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
241 /* How many registers are needed for a given register and mode. */
242 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
244 /* Map register number to register class. */
245 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
247 static int dbg_cost_ctrl;
249 /* Built in types. */
250 tree rs6000_builtin_types[RS6000_BTI_MAX];
251 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
253 /* Flag to say the TOC is initialized */
254 int toc_initialized, need_toc_init;
255 char toc_label_name[10];
257 /* Cached value of rs6000_variable_issue. This is cached in
258 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
259 static short cached_can_issue_more;
261 static GTY(()) section *read_only_data_section;
262 static GTY(()) section *private_data_section;
263 static GTY(()) section *tls_data_section;
264 static GTY(()) section *tls_private_data_section;
265 static GTY(()) section *read_only_private_data_section;
266 static GTY(()) section *sdata2_section;
267 static GTY(()) section *toc_section;
269 struct builtin_description
271 const HOST_WIDE_INT mask;
272 const enum insn_code icode;
273 const char *const name;
274 const enum rs6000_builtins code;
277 /* Describe the vector unit used for modes. */
278 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
279 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
281 /* Register classes for various constraints that are based on the target
283 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
285 /* Describe the alignment of a vector. */
286 int rs6000_vector_align[NUM_MACHINE_MODES];
288 /* Map selected modes to types for builtins. */
289 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
291 /* What modes to automatically generate reciprocal divide estimate (fre) and
292 reciprocal sqrt (frsqrte) for. */
293 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
295 /* Masks to determine which reciprocal esitmate instructions to generate
297 enum rs6000_recip_mask {
298 RECIP_SF_DIV = 0x001, /* Use divide estimate */
299 RECIP_DF_DIV = 0x002,
300 RECIP_V4SF_DIV = 0x004,
301 RECIP_V2DF_DIV = 0x008,
303 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
304 RECIP_DF_RSQRT = 0x020,
305 RECIP_V4SF_RSQRT = 0x040,
306 RECIP_V2DF_RSQRT = 0x080,
308 /* Various combination of flags for -mrecip=xxx. */
310 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
311 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
312 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
314 RECIP_HIGH_PRECISION = RECIP_ALL,
316 /* On low precision machines like the power5, don't enable double precision
317 reciprocal square root estimate, since it isn't accurate enough. */
318 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
321 /* -mrecip options. */
324 const char *string; /* option name */
325 unsigned int mask; /* mask bits to set */
326 } recip_options[] = {
327 { "all", RECIP_ALL },
328 { "none", RECIP_NONE },
329 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
331 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
332 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
333 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
334 | RECIP_V2DF_RSQRT) },
335 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
336 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
339 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
345 { "power9", PPC_PLATFORM_POWER9 },
346 { "power8", PPC_PLATFORM_POWER8 },
347 { "power7", PPC_PLATFORM_POWER7 },
348 { "power6x", PPC_PLATFORM_POWER6X },
349 { "power6", PPC_PLATFORM_POWER6 },
350 { "power5+", PPC_PLATFORM_POWER5_PLUS },
351 { "power5", PPC_PLATFORM_POWER5 },
352 { "ppc970", PPC_PLATFORM_PPC970 },
353 { "power4", PPC_PLATFORM_POWER4 },
354 { "ppca2", PPC_PLATFORM_PPCA2 },
355 { "ppc476", PPC_PLATFORM_PPC476 },
356 { "ppc464", PPC_PLATFORM_PPC464 },
357 { "ppc440", PPC_PLATFORM_PPC440 },
358 { "ppc405", PPC_PLATFORM_PPC405 },
359 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
362 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
368 } cpu_supports_info[] = {
369 /* AT_HWCAP masks. */
370 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
371 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
372 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
373 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
374 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
375 { "booke", PPC_FEATURE_BOOKE, 0 },
376 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
377 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
378 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
379 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
380 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
381 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
382 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
383 { "notb", PPC_FEATURE_NO_TB, 0 },
384 { "pa6t", PPC_FEATURE_PA6T, 0 },
385 { "power4", PPC_FEATURE_POWER4, 0 },
386 { "power5", PPC_FEATURE_POWER5, 0 },
387 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
388 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
389 { "ppc32", PPC_FEATURE_32, 0 },
390 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
391 { "ppc64", PPC_FEATURE_64, 0 },
392 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
393 { "smt", PPC_FEATURE_SMT, 0 },
394 { "spe", PPC_FEATURE_HAS_SPE, 0 },
395 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
396 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
397 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
399 /* AT_HWCAP2 masks. */
400 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
401 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
402 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
403 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
404 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
405 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
406 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
407 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
408 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
409 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
410 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
411 { "darn", PPC_FEATURE2_DARN, 1 },
412 { "scv", PPC_FEATURE2_SCV, 1 }
415 /* On PowerPC, we have a limited number of target clones that we care about
416 which means we can use an array to hold the options, rather than having more
417 elaborate data structures to identify each possible variation. Order the
418 clones from the default to the highest ISA. */
420 CLONE_DEFAULT = 0, /* default clone. */
421 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
422 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
423 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
424 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
428 /* Map compiler ISA bits into HWCAP names. */
430 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
431 const char *name; /* name to use in __builtin_cpu_supports. */
434 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
435 { 0, "" }, /* Default options. */
436 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
437 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
438 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
439 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
443 /* Newer LIBCs explicitly export this symbol to declare that they provide
444 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
445 reference to this symbol whenever we expand a CPU builtin, so that
446 we never link against an old LIBC. */
447 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
449 /* True if we have expanded a CPU builtin. */
452 /* Pointer to function (in rs6000-c.c) that can define or undefine target
453 macros that have changed. Languages that don't support the preprocessor
454 don't link in rs6000-c.c, so we can't call it directly. */
455 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
457 /* Simplfy register classes into simpler classifications. We assume
458 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
459 check for standard register classes (gpr/floating/altivec/vsx) and
460 floating/vector classes (float/altivec/vsx). */
462 enum rs6000_reg_type {
473 /* Map register class to register type. */
474 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
476 /* First/last register type for the 'normal' register types (i.e. general
477 purpose, floating point, altivec, and VSX registers). */
478 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
480 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
483 /* Register classes we care about in secondary reload or go if legitimate
484 address. We only need to worry about GPR, FPR, and Altivec registers here,
485 along an ANY field that is the OR of the 3 register classes. */
487 enum rs6000_reload_reg_type {
488 RELOAD_REG_GPR, /* General purpose registers. */
489 RELOAD_REG_FPR, /* Traditional floating point regs. */
490 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
491 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
495 /* For setting up register classes, loop through the 3 register classes mapping
496 into real registers, and skip the ANY class, which is just an OR of the
498 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
499 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
501 /* Map reload register type to a register in the register class. */
502 struct reload_reg_map_type {
503 const char *name; /* Register class name. */
504 int reg; /* Register in the register class. */
507 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
508 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
509 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
510 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
511 { "Any", -1 }, /* RELOAD_REG_ANY. */
514 /* Mask bits for each register class, indexed per mode. Historically the
515 compiler has been more restrictive which types can do PRE_MODIFY instead of
516 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
517 typedef unsigned char addr_mask_type;
519 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
520 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
521 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
522 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
523 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
524 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
525 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
526 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
528 /* Register type masks based on the type, of valid addressing modes. */
529 struct rs6000_reg_addr {
530 enum insn_code reload_load; /* INSN to reload for loading. */
531 enum insn_code reload_store; /* INSN to reload for storing. */
532 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
533 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
534 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
535 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
536 /* INSNs for fusing addi with loads
537 or stores for each reg. class. */
538 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
539 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
540 /* INSNs for fusing addis with loads
541 or stores for each reg. class. */
542 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
543 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
544 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
545 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
546 bool fused_toc; /* Mode supports TOC fusion. */
549 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
551 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
553 mode_supports_pre_incdec_p (machine_mode mode)
555 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
559 /* Helper function to say whether a mode supports PRE_MODIFY. */
561 mode_supports_pre_modify_p (machine_mode mode)
563 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
567 /* Return true if we have D-form addressing in altivec registers. */
569 mode_supports_vmx_dform (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
574 /* Return true if we have D-form addressing in VSX registers. This addressing
575 is more limited than normal d-form addressing in that the offset must be
576 aligned on a 16-byte boundary. */
578 mode_supports_dq_form (machine_mode mode)
580 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
584 /* Given that there exists at least one variable that is set (produced)
585 by OUT_INSN and read (consumed) by IN_INSN, return true iff
586 IN_INSN represents one or more memory store operations and none of
587 the variables set by OUT_INSN is used by IN_INSN as the address of a
588 store operation. If either IN_INSN or OUT_INSN does not represent
589 a "single" RTL SET expression (as loosely defined by the
590 implementation of the single_set function) or a PARALLEL with only
591 SETs, CLOBBERs, and USEs inside, this function returns false.
593 This rs6000-specific version of store_data_bypass_p checks for
594 certain conditions that result in assertion failures (and internal
595 compiler errors) in the generic store_data_bypass_p function and
596 returns false rather than calling store_data_bypass_p if one of the
597 problematic conditions is detected. */
600 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
607 in_set = single_set (in_insn);
610 if (MEM_P (SET_DEST (in_set)))
612 out_set = single_set (out_insn);
615 out_pat = PATTERN (out_insn);
616 if (GET_CODE (out_pat) == PARALLEL)
618 for (i = 0; i < XVECLEN (out_pat, 0); i++)
620 out_exp = XVECEXP (out_pat, 0, i);
621 if ((GET_CODE (out_exp) == CLOBBER)
622 || (GET_CODE (out_exp) == USE))
624 else if (GET_CODE (out_exp) != SET)
633 in_pat = PATTERN (in_insn);
634 if (GET_CODE (in_pat) != PARALLEL)
637 for (i = 0; i < XVECLEN (in_pat, 0); i++)
639 in_exp = XVECEXP (in_pat, 0, i);
640 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
642 else if (GET_CODE (in_exp) != SET)
645 if (MEM_P (SET_DEST (in_exp)))
647 out_set = single_set (out_insn);
650 out_pat = PATTERN (out_insn);
651 if (GET_CODE (out_pat) != PARALLEL)
653 for (j = 0; j < XVECLEN (out_pat, 0); j++)
655 out_exp = XVECEXP (out_pat, 0, j);
656 if ((GET_CODE (out_exp) == CLOBBER)
657 || (GET_CODE (out_exp) == USE))
659 else if (GET_CODE (out_exp) != SET)
666 return store_data_bypass_p (out_insn, in_insn);
670 /* Processor costs (relative to an add) */
672 const struct processor_costs *rs6000_cost;
674 /* Instruction size costs on 32bit processors. */
676 struct processor_costs size32_cost = {
677 COSTS_N_INSNS (1), /* mulsi */
678 COSTS_N_INSNS (1), /* mulsi_const */
679 COSTS_N_INSNS (1), /* mulsi_const9 */
680 COSTS_N_INSNS (1), /* muldi */
681 COSTS_N_INSNS (1), /* divsi */
682 COSTS_N_INSNS (1), /* divdi */
683 COSTS_N_INSNS (1), /* fp */
684 COSTS_N_INSNS (1), /* dmul */
685 COSTS_N_INSNS (1), /* sdiv */
686 COSTS_N_INSNS (1), /* ddiv */
687 32, /* cache line size */
691 0, /* SF->DF convert */
694 /* Instruction size costs on 64bit processors. */
696 struct processor_costs size64_cost = {
697 COSTS_N_INSNS (1), /* mulsi */
698 COSTS_N_INSNS (1), /* mulsi_const */
699 COSTS_N_INSNS (1), /* mulsi_const9 */
700 COSTS_N_INSNS (1), /* muldi */
701 COSTS_N_INSNS (1), /* divsi */
702 COSTS_N_INSNS (1), /* divdi */
703 COSTS_N_INSNS (1), /* fp */
704 COSTS_N_INSNS (1), /* dmul */
705 COSTS_N_INSNS (1), /* sdiv */
706 COSTS_N_INSNS (1), /* ddiv */
707 128, /* cache line size */
711 0, /* SF->DF convert */
714 /* Instruction costs on RS64A processors. */
716 struct processor_costs rs64a_cost = {
717 COSTS_N_INSNS (20), /* mulsi */
718 COSTS_N_INSNS (12), /* mulsi_const */
719 COSTS_N_INSNS (8), /* mulsi_const9 */
720 COSTS_N_INSNS (34), /* muldi */
721 COSTS_N_INSNS (65), /* divsi */
722 COSTS_N_INSNS (67), /* divdi */
723 COSTS_N_INSNS (4), /* fp */
724 COSTS_N_INSNS (4), /* dmul */
725 COSTS_N_INSNS (31), /* sdiv */
726 COSTS_N_INSNS (31), /* ddiv */
727 128, /* cache line size */
731 0, /* SF->DF convert */
734 /* Instruction costs on MPCCORE processors. */
736 struct processor_costs mpccore_cost = {
737 COSTS_N_INSNS (2), /* mulsi */
738 COSTS_N_INSNS (2), /* mulsi_const */
739 COSTS_N_INSNS (2), /* mulsi_const9 */
740 COSTS_N_INSNS (2), /* muldi */
741 COSTS_N_INSNS (6), /* divsi */
742 COSTS_N_INSNS (6), /* divdi */
743 COSTS_N_INSNS (4), /* fp */
744 COSTS_N_INSNS (5), /* dmul */
745 COSTS_N_INSNS (10), /* sdiv */
746 COSTS_N_INSNS (17), /* ddiv */
747 32, /* cache line size */
751 0, /* SF->DF convert */
754 /* Instruction costs on PPC403 processors. */
756 struct processor_costs ppc403_cost = {
757 COSTS_N_INSNS (4), /* mulsi */
758 COSTS_N_INSNS (4), /* mulsi_const */
759 COSTS_N_INSNS (4), /* mulsi_const9 */
760 COSTS_N_INSNS (4), /* muldi */
761 COSTS_N_INSNS (33), /* divsi */
762 COSTS_N_INSNS (33), /* divdi */
763 COSTS_N_INSNS (11), /* fp */
764 COSTS_N_INSNS (11), /* dmul */
765 COSTS_N_INSNS (11), /* sdiv */
766 COSTS_N_INSNS (11), /* ddiv */
767 32, /* cache line size */
771 0, /* SF->DF convert */
774 /* Instruction costs on PPC405 processors. */
776 struct processor_costs ppc405_cost = {
777 COSTS_N_INSNS (5), /* mulsi */
778 COSTS_N_INSNS (4), /* mulsi_const */
779 COSTS_N_INSNS (3), /* mulsi_const9 */
780 COSTS_N_INSNS (5), /* muldi */
781 COSTS_N_INSNS (35), /* divsi */
782 COSTS_N_INSNS (35), /* divdi */
783 COSTS_N_INSNS (11), /* fp */
784 COSTS_N_INSNS (11), /* dmul */
785 COSTS_N_INSNS (11), /* sdiv */
786 COSTS_N_INSNS (11), /* ddiv */
787 32, /* cache line size */
791 0, /* SF->DF convert */
794 /* Instruction costs on PPC440 processors. */
796 struct processor_costs ppc440_cost = {
797 COSTS_N_INSNS (3), /* mulsi */
798 COSTS_N_INSNS (2), /* mulsi_const */
799 COSTS_N_INSNS (2), /* mulsi_const9 */
800 COSTS_N_INSNS (3), /* muldi */
801 COSTS_N_INSNS (34), /* divsi */
802 COSTS_N_INSNS (34), /* divdi */
803 COSTS_N_INSNS (5), /* fp */
804 COSTS_N_INSNS (5), /* dmul */
805 COSTS_N_INSNS (19), /* sdiv */
806 COSTS_N_INSNS (33), /* ddiv */
807 32, /* cache line size */
811 0, /* SF->DF convert */
814 /* Instruction costs on PPC476 processors. */
816 struct processor_costs ppc476_cost = {
817 COSTS_N_INSNS (4), /* mulsi */
818 COSTS_N_INSNS (4), /* mulsi_const */
819 COSTS_N_INSNS (4), /* mulsi_const9 */
820 COSTS_N_INSNS (4), /* muldi */
821 COSTS_N_INSNS (11), /* divsi */
822 COSTS_N_INSNS (11), /* divdi */
823 COSTS_N_INSNS (6), /* fp */
824 COSTS_N_INSNS (6), /* dmul */
825 COSTS_N_INSNS (19), /* sdiv */
826 COSTS_N_INSNS (33), /* ddiv */
827 32, /* l1 cache line size */
831 0, /* SF->DF convert */
834 /* Instruction costs on PPC601 processors. */
836 struct processor_costs ppc601_cost = {
837 COSTS_N_INSNS (5), /* mulsi */
838 COSTS_N_INSNS (5), /* mulsi_const */
839 COSTS_N_INSNS (5), /* mulsi_const9 */
840 COSTS_N_INSNS (5), /* muldi */
841 COSTS_N_INSNS (36), /* divsi */
842 COSTS_N_INSNS (36), /* divdi */
843 COSTS_N_INSNS (4), /* fp */
844 COSTS_N_INSNS (5), /* dmul */
845 COSTS_N_INSNS (17), /* sdiv */
846 COSTS_N_INSNS (31), /* ddiv */
847 32, /* cache line size */
851 0, /* SF->DF convert */
854 /* Instruction costs on PPC603 processors. */
856 struct processor_costs ppc603_cost = {
857 COSTS_N_INSNS (5), /* mulsi */
858 COSTS_N_INSNS (3), /* mulsi_const */
859 COSTS_N_INSNS (2), /* mulsi_const9 */
860 COSTS_N_INSNS (5), /* muldi */
861 COSTS_N_INSNS (37), /* divsi */
862 COSTS_N_INSNS (37), /* divdi */
863 COSTS_N_INSNS (3), /* fp */
864 COSTS_N_INSNS (4), /* dmul */
865 COSTS_N_INSNS (18), /* sdiv */
866 COSTS_N_INSNS (33), /* ddiv */
867 32, /* cache line size */
871 0, /* SF->DF convert */
874 /* Instruction costs on PPC604 processors. */
876 struct processor_costs ppc604_cost = {
877 COSTS_N_INSNS (4), /* mulsi */
878 COSTS_N_INSNS (4), /* mulsi_const */
879 COSTS_N_INSNS (4), /* mulsi_const9 */
880 COSTS_N_INSNS (4), /* muldi */
881 COSTS_N_INSNS (20), /* divsi */
882 COSTS_N_INSNS (20), /* divdi */
883 COSTS_N_INSNS (3), /* fp */
884 COSTS_N_INSNS (3), /* dmul */
885 COSTS_N_INSNS (18), /* sdiv */
886 COSTS_N_INSNS (32), /* ddiv */
887 32, /* cache line size */
891 0, /* SF->DF convert */
894 /* Instruction costs on PPC604e processors. */
896 struct processor_costs ppc604e_cost = {
897 COSTS_N_INSNS (2), /* mulsi */
898 COSTS_N_INSNS (2), /* mulsi_const */
899 COSTS_N_INSNS (2), /* mulsi_const9 */
900 COSTS_N_INSNS (2), /* muldi */
901 COSTS_N_INSNS (20), /* divsi */
902 COSTS_N_INSNS (20), /* divdi */
903 COSTS_N_INSNS (3), /* fp */
904 COSTS_N_INSNS (3), /* dmul */
905 COSTS_N_INSNS (18), /* sdiv */
906 COSTS_N_INSNS (32), /* ddiv */
907 32, /* cache line size */
911 0, /* SF->DF convert */
914 /* Instruction costs on PPC620 processors. */
916 struct processor_costs ppc620_cost = {
917 COSTS_N_INSNS (5), /* mulsi */
918 COSTS_N_INSNS (4), /* mulsi_const */
919 COSTS_N_INSNS (3), /* mulsi_const9 */
920 COSTS_N_INSNS (7), /* muldi */
921 COSTS_N_INSNS (21), /* divsi */
922 COSTS_N_INSNS (37), /* divdi */
923 COSTS_N_INSNS (3), /* fp */
924 COSTS_N_INSNS (3), /* dmul */
925 COSTS_N_INSNS (18), /* sdiv */
926 COSTS_N_INSNS (32), /* ddiv */
927 128, /* cache line size */
931 0, /* SF->DF convert */
934 /* Instruction costs on PPC630 processors. */
936 struct processor_costs ppc630_cost = {
937 COSTS_N_INSNS (5), /* mulsi */
938 COSTS_N_INSNS (4), /* mulsi_const */
939 COSTS_N_INSNS (3), /* mulsi_const9 */
940 COSTS_N_INSNS (7), /* muldi */
941 COSTS_N_INSNS (21), /* divsi */
942 COSTS_N_INSNS (37), /* divdi */
943 COSTS_N_INSNS (3), /* fp */
944 COSTS_N_INSNS (3), /* dmul */
945 COSTS_N_INSNS (17), /* sdiv */
946 COSTS_N_INSNS (21), /* ddiv */
947 128, /* cache line size */
951 0, /* SF->DF convert */
954 /* Instruction costs on Cell processor. */
955 /* COSTS_N_INSNS (1) ~ one add. */
957 struct processor_costs ppccell_cost = {
958 COSTS_N_INSNS (9/2)+2, /* mulsi */
959 COSTS_N_INSNS (6/2), /* mulsi_const */
960 COSTS_N_INSNS (6/2), /* mulsi_const9 */
961 COSTS_N_INSNS (15/2)+2, /* muldi */
962 COSTS_N_INSNS (38/2), /* divsi */
963 COSTS_N_INSNS (70/2), /* divdi */
964 COSTS_N_INSNS (10/2), /* fp */
965 COSTS_N_INSNS (10/2), /* dmul */
966 COSTS_N_INSNS (74/2), /* sdiv */
967 COSTS_N_INSNS (74/2), /* ddiv */
968 128, /* cache line size */
972 0, /* SF->DF convert */
975 /* Instruction costs on PPC750 and PPC7400 processors. */
977 struct processor_costs ppc750_cost = {
978 COSTS_N_INSNS (5), /* mulsi */
979 COSTS_N_INSNS (3), /* mulsi_const */
980 COSTS_N_INSNS (2), /* mulsi_const9 */
981 COSTS_N_INSNS (5), /* muldi */
982 COSTS_N_INSNS (17), /* divsi */
983 COSTS_N_INSNS (17), /* divdi */
984 COSTS_N_INSNS (3), /* fp */
985 COSTS_N_INSNS (3), /* dmul */
986 COSTS_N_INSNS (17), /* sdiv */
987 COSTS_N_INSNS (31), /* ddiv */
988 32, /* cache line size */
992 0, /* SF->DF convert */
995 /* Instruction costs on PPC7450 processors. */
997 struct processor_costs ppc7450_cost = {
998 COSTS_N_INSNS (4), /* mulsi */
999 COSTS_N_INSNS (3), /* mulsi_const */
1000 COSTS_N_INSNS (3), /* mulsi_const9 */
1001 COSTS_N_INSNS (4), /* muldi */
1002 COSTS_N_INSNS (23), /* divsi */
1003 COSTS_N_INSNS (23), /* divdi */
1004 COSTS_N_INSNS (5), /* fp */
1005 COSTS_N_INSNS (5), /* dmul */
1006 COSTS_N_INSNS (21), /* sdiv */
1007 COSTS_N_INSNS (35), /* ddiv */
1008 32, /* cache line size */
1010 1024, /* l2 cache */
1012 0, /* SF->DF convert */
1015 /* Instruction costs on PPC8540 processors. */
1017 struct processor_costs ppc8540_cost = {
1018 COSTS_N_INSNS (4), /* mulsi */
1019 COSTS_N_INSNS (4), /* mulsi_const */
1020 COSTS_N_INSNS (4), /* mulsi_const9 */
1021 COSTS_N_INSNS (4), /* muldi */
1022 COSTS_N_INSNS (19), /* divsi */
1023 COSTS_N_INSNS (19), /* divdi */
1024 COSTS_N_INSNS (4), /* fp */
1025 COSTS_N_INSNS (4), /* dmul */
1026 COSTS_N_INSNS (29), /* sdiv */
1027 COSTS_N_INSNS (29), /* ddiv */
1028 32, /* cache line size */
1031 1, /* prefetch streams /*/
1032 0, /* SF->DF convert */
1035 /* Instruction costs on E300C2 and E300C3 cores. */
1037 struct processor_costs ppce300c2c3_cost = {
1038 COSTS_N_INSNS (4), /* mulsi */
1039 COSTS_N_INSNS (4), /* mulsi_const */
1040 COSTS_N_INSNS (4), /* mulsi_const9 */
1041 COSTS_N_INSNS (4), /* muldi */
1042 COSTS_N_INSNS (19), /* divsi */
1043 COSTS_N_INSNS (19), /* divdi */
1044 COSTS_N_INSNS (3), /* fp */
1045 COSTS_N_INSNS (4), /* dmul */
1046 COSTS_N_INSNS (18), /* sdiv */
1047 COSTS_N_INSNS (33), /* ddiv */
1051 1, /* prefetch streams /*/
1052 0, /* SF->DF convert */
1055 /* Instruction costs on PPCE500MC processors. */
1057 struct processor_costs ppce500mc_cost = {
1058 COSTS_N_INSNS (4), /* mulsi */
1059 COSTS_N_INSNS (4), /* mulsi_const */
1060 COSTS_N_INSNS (4), /* mulsi_const9 */
1061 COSTS_N_INSNS (4), /* muldi */
1062 COSTS_N_INSNS (14), /* divsi */
1063 COSTS_N_INSNS (14), /* divdi */
1064 COSTS_N_INSNS (8), /* fp */
1065 COSTS_N_INSNS (10), /* dmul */
1066 COSTS_N_INSNS (36), /* sdiv */
1067 COSTS_N_INSNS (66), /* ddiv */
1068 64, /* cache line size */
1071 1, /* prefetch streams /*/
1072 0, /* SF->DF convert */
1075 /* Instruction costs on PPCE500MC64 processors. */
1077 struct processor_costs ppce500mc64_cost = {
1078 COSTS_N_INSNS (4), /* mulsi */
1079 COSTS_N_INSNS (4), /* mulsi_const */
1080 COSTS_N_INSNS (4), /* mulsi_const9 */
1081 COSTS_N_INSNS (4), /* muldi */
1082 COSTS_N_INSNS (14), /* divsi */
1083 COSTS_N_INSNS (14), /* divdi */
1084 COSTS_N_INSNS (4), /* fp */
1085 COSTS_N_INSNS (10), /* dmul */
1086 COSTS_N_INSNS (36), /* sdiv */
1087 COSTS_N_INSNS (66), /* ddiv */
1088 64, /* cache line size */
1091 1, /* prefetch streams /*/
1092 0, /* SF->DF convert */
1095 /* Instruction costs on PPCE5500 processors. */
1097 struct processor_costs ppce5500_cost = {
1098 COSTS_N_INSNS (5), /* mulsi */
1099 COSTS_N_INSNS (5), /* mulsi_const */
1100 COSTS_N_INSNS (4), /* mulsi_const9 */
1101 COSTS_N_INSNS (5), /* muldi */
1102 COSTS_N_INSNS (14), /* divsi */
1103 COSTS_N_INSNS (14), /* divdi */
1104 COSTS_N_INSNS (7), /* fp */
1105 COSTS_N_INSNS (10), /* dmul */
1106 COSTS_N_INSNS (36), /* sdiv */
1107 COSTS_N_INSNS (66), /* ddiv */
1108 64, /* cache line size */
1111 1, /* prefetch streams /*/
1112 0, /* SF->DF convert */
1115 /* Instruction costs on PPCE6500 processors. */
1117 struct processor_costs ppce6500_cost = {
1118 COSTS_N_INSNS (5), /* mulsi */
1119 COSTS_N_INSNS (5), /* mulsi_const */
1120 COSTS_N_INSNS (4), /* mulsi_const9 */
1121 COSTS_N_INSNS (5), /* muldi */
1122 COSTS_N_INSNS (14), /* divsi */
1123 COSTS_N_INSNS (14), /* divdi */
1124 COSTS_N_INSNS (7), /* fp */
1125 COSTS_N_INSNS (10), /* dmul */
1126 COSTS_N_INSNS (36), /* sdiv */
1127 COSTS_N_INSNS (66), /* ddiv */
1128 64, /* cache line size */
1131 1, /* prefetch streams /*/
1132 0, /* SF->DF convert */
1135 /* Instruction costs on AppliedMicro Titan processors. */
1137 struct processor_costs titan_cost = {
1138 COSTS_N_INSNS (5), /* mulsi */
1139 COSTS_N_INSNS (5), /* mulsi_const */
1140 COSTS_N_INSNS (5), /* mulsi_const9 */
1141 COSTS_N_INSNS (5), /* muldi */
1142 COSTS_N_INSNS (18), /* divsi */
1143 COSTS_N_INSNS (18), /* divdi */
1144 COSTS_N_INSNS (10), /* fp */
1145 COSTS_N_INSNS (10), /* dmul */
1146 COSTS_N_INSNS (46), /* sdiv */
1147 COSTS_N_INSNS (72), /* ddiv */
1148 32, /* cache line size */
1151 1, /* prefetch streams /*/
1152 0, /* SF->DF convert */
1155 /* Instruction costs on POWER4 and POWER5 processors. */
1157 struct processor_costs power4_cost = {
1158 COSTS_N_INSNS (3), /* mulsi */
1159 COSTS_N_INSNS (2), /* mulsi_const */
1160 COSTS_N_INSNS (2), /* mulsi_const9 */
1161 COSTS_N_INSNS (4), /* muldi */
1162 COSTS_N_INSNS (18), /* divsi */
1163 COSTS_N_INSNS (34), /* divdi */
1164 COSTS_N_INSNS (3), /* fp */
1165 COSTS_N_INSNS (3), /* dmul */
1166 COSTS_N_INSNS (17), /* sdiv */
1167 COSTS_N_INSNS (17), /* ddiv */
1168 128, /* cache line size */
1170 1024, /* l2 cache */
1171 8, /* prefetch streams /*/
1172 0, /* SF->DF convert */
1175 /* Instruction costs on POWER6 processors. */
1177 struct processor_costs power6_cost = {
1178 COSTS_N_INSNS (8), /* mulsi */
1179 COSTS_N_INSNS (8), /* mulsi_const */
1180 COSTS_N_INSNS (8), /* mulsi_const9 */
1181 COSTS_N_INSNS (8), /* muldi */
1182 COSTS_N_INSNS (22), /* divsi */
1183 COSTS_N_INSNS (28), /* divdi */
1184 COSTS_N_INSNS (3), /* fp */
1185 COSTS_N_INSNS (3), /* dmul */
1186 COSTS_N_INSNS (13), /* sdiv */
1187 COSTS_N_INSNS (16), /* ddiv */
1188 128, /* cache line size */
1190 2048, /* l2 cache */
1191 16, /* prefetch streams */
1192 0, /* SF->DF convert */
1195 /* Instruction costs on POWER7 processors. */
1197 struct processor_costs power7_cost = {
1198 COSTS_N_INSNS (2), /* mulsi */
1199 COSTS_N_INSNS (2), /* mulsi_const */
1200 COSTS_N_INSNS (2), /* mulsi_const9 */
1201 COSTS_N_INSNS (2), /* muldi */
1202 COSTS_N_INSNS (18), /* divsi */
1203 COSTS_N_INSNS (34), /* divdi */
1204 COSTS_N_INSNS (3), /* fp */
1205 COSTS_N_INSNS (3), /* dmul */
1206 COSTS_N_INSNS (13), /* sdiv */
1207 COSTS_N_INSNS (16), /* ddiv */
1208 128, /* cache line size */
1211 12, /* prefetch streams */
1212 COSTS_N_INSNS (3), /* SF->DF convert */
1215 /* Instruction costs on POWER8 processors. */
1217 struct processor_costs power8_cost = {
1218 COSTS_N_INSNS (3), /* mulsi */
1219 COSTS_N_INSNS (3), /* mulsi_const */
1220 COSTS_N_INSNS (3), /* mulsi_const9 */
1221 COSTS_N_INSNS (3), /* muldi */
1222 COSTS_N_INSNS (19), /* divsi */
1223 COSTS_N_INSNS (35), /* divdi */
1224 COSTS_N_INSNS (3), /* fp */
1225 COSTS_N_INSNS (3), /* dmul */
1226 COSTS_N_INSNS (14), /* sdiv */
1227 COSTS_N_INSNS (17), /* ddiv */
1228 128, /* cache line size */
1231 12, /* prefetch streams */
1232 COSTS_N_INSNS (3), /* SF->DF convert */
1235 /* Instruction costs on POWER9 processors. */
1237 struct processor_costs power9_cost = {
1238 COSTS_N_INSNS (3), /* mulsi */
1239 COSTS_N_INSNS (3), /* mulsi_const */
1240 COSTS_N_INSNS (3), /* mulsi_const9 */
1241 COSTS_N_INSNS (3), /* muldi */
1242 COSTS_N_INSNS (8), /* divsi */
1243 COSTS_N_INSNS (12), /* divdi */
1244 COSTS_N_INSNS (3), /* fp */
1245 COSTS_N_INSNS (3), /* dmul */
1246 COSTS_N_INSNS (13), /* sdiv */
1247 COSTS_N_INSNS (18), /* ddiv */
1248 128, /* cache line size */
1251 8, /* prefetch streams */
1252 COSTS_N_INSNS (3), /* SF->DF convert */
1255 /* Instruction costs on POWER A2 processors. */
1257 struct processor_costs ppca2_cost = {
1258 COSTS_N_INSNS (16), /* mulsi */
1259 COSTS_N_INSNS (16), /* mulsi_const */
1260 COSTS_N_INSNS (16), /* mulsi_const9 */
1261 COSTS_N_INSNS (16), /* muldi */
1262 COSTS_N_INSNS (22), /* divsi */
1263 COSTS_N_INSNS (28), /* divdi */
1264 COSTS_N_INSNS (3), /* fp */
1265 COSTS_N_INSNS (3), /* dmul */
1266 COSTS_N_INSNS (59), /* sdiv */
1267 COSTS_N_INSNS (72), /* ddiv */
1270 2048, /* l2 cache */
1271 16, /* prefetch streams */
1272 0, /* SF->DF convert */
1276 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1277 #undef RS6000_BUILTIN_0
1278 #undef RS6000_BUILTIN_1
1279 #undef RS6000_BUILTIN_2
1280 #undef RS6000_BUILTIN_3
1281 #undef RS6000_BUILTIN_A
1282 #undef RS6000_BUILTIN_D
1283 #undef RS6000_BUILTIN_H
1284 #undef RS6000_BUILTIN_P
1285 #undef RS6000_BUILTIN_X
1287 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1306 { NAME, ICODE, MASK, ATTR },
1308 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1309 { NAME, ICODE, MASK, ATTR },
1311 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1312 { NAME, ICODE, MASK, ATTR },
1314 struct rs6000_builtin_info_type {
1316 const enum insn_code icode;
1317 const HOST_WIDE_INT mask;
1318 const unsigned attr;
1321 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1323 #include "rs6000-builtin.def"
1326 #undef RS6000_BUILTIN_0
1327 #undef RS6000_BUILTIN_1
1328 #undef RS6000_BUILTIN_2
1329 #undef RS6000_BUILTIN_3
1330 #undef RS6000_BUILTIN_A
1331 #undef RS6000_BUILTIN_D
1332 #undef RS6000_BUILTIN_H
1333 #undef RS6000_BUILTIN_P
1334 #undef RS6000_BUILTIN_X
1336 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1337 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1340 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1341 static struct machine_function * rs6000_init_machine_status (void);
1342 static int rs6000_ra_ever_killed (void);
1343 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1344 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1345 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1346 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1347 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1348 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1349 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1350 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1352 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1354 static bool is_microcoded_insn (rtx_insn *);
1355 static bool is_nonpipeline_insn (rtx_insn *);
1356 static bool is_cracked_insn (rtx_insn *);
1357 static bool is_load_insn (rtx, rtx *);
1358 static bool is_store_insn (rtx, rtx *);
1359 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1360 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1361 static bool insn_must_be_first_in_group (rtx_insn *);
1362 static bool insn_must_be_last_in_group (rtx_insn *);
1363 static void altivec_init_builtins (void);
1364 static tree builtin_function_type (machine_mode, machine_mode,
1365 machine_mode, machine_mode,
1366 enum rs6000_builtins, const char *name);
1367 static void rs6000_common_init_builtins (void);
1368 static void htm_init_builtins (void);
1369 static rs6000_stack_t *rs6000_stack_info (void);
1370 static void is_altivec_return_reg (rtx, void *);
1371 int easy_vector_constant (rtx, machine_mode);
1372 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1373 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1374 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1377 static void macho_branch_islands (void);
1379 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1381 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1383 static bool rs6000_mode_dependent_address (const_rtx);
1384 static bool rs6000_debug_mode_dependent_address (const_rtx);
1385 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1386 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1388 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1391 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1392 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1394 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1397 static bool rs6000_debug_can_change_mode_class (machine_mode,
1400 static bool rs6000_save_toc_in_prologue_p (void);
1401 static rtx rs6000_internal_arg_pointer (void);
1403 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1405 = rs6000_legitimize_reload_address;
1407 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1408 = rs6000_mode_dependent_address;
1410 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1412 = rs6000_secondary_reload_class;
1414 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1415 = rs6000_preferred_reload_class;
1417 const int INSN_NOT_AVAILABLE = -1;
1419 static void rs6000_print_isa_options (FILE *, int, const char *,
1421 static void rs6000_print_builtin_options (FILE *, int, const char *,
1423 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1425 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1426 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1427 enum rs6000_reg_type,
1429 secondary_reload_info *,
1431 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1432 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1433 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1435 /* Hash table stuff for keeping track of TOC entries. */
1437 struct GTY((for_user)) toc_hash_struct
1439 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1440 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1442 machine_mode key_mode;
1446 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1448 static hashval_t hash (toc_hash_struct *);
1449 static bool equal (toc_hash_struct *, toc_hash_struct *);
1452 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1454 /* Hash table to keep track of the argument types for builtin functions. */
1456 struct GTY((for_user)) builtin_hash_struct
1459 machine_mode mode[4]; /* return value + 3 arguments. */
1460 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1463 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1465 static hashval_t hash (builtin_hash_struct *);
1466 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1469 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1472 /* Default register names. */
1473 char rs6000_reg_names[][8] =
1475 "0", "1", "2", "3", "4", "5", "6", "7",
1476 "8", "9", "10", "11", "12", "13", "14", "15",
1477 "16", "17", "18", "19", "20", "21", "22", "23",
1478 "24", "25", "26", "27", "28", "29", "30", "31",
1479 "0", "1", "2", "3", "4", "5", "6", "7",
1480 "8", "9", "10", "11", "12", "13", "14", "15",
1481 "16", "17", "18", "19", "20", "21", "22", "23",
1482 "24", "25", "26", "27", "28", "29", "30", "31",
1483 "mq", "lr", "ctr","ap",
1484 "0", "1", "2", "3", "4", "5", "6", "7",
1486 /* AltiVec registers. */
1487 "0", "1", "2", "3", "4", "5", "6", "7",
1488 "8", "9", "10", "11", "12", "13", "14", "15",
1489 "16", "17", "18", "19", "20", "21", "22", "23",
1490 "24", "25", "26", "27", "28", "29", "30", "31",
1492 /* Soft frame pointer. */
1494 /* HTM SPR registers. */
1495 "tfhar", "tfiar", "texasr"
1498 #ifdef TARGET_REGNAMES
1499 static const char alt_reg_names[][8] =
1501 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1502 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1503 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1504 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1505 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1506 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1507 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1508 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1509 "mq", "lr", "ctr", "ap",
1510 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1512 /* AltiVec registers. */
1513 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1514 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1515 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1516 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1518 /* Soft frame pointer. */
1520 /* HTM SPR registers. */
1521 "tfhar", "tfiar", "texasr"
1525 /* Table of valid machine attributes. */
1527 static const struct attribute_spec rs6000_attribute_table[] =
1529 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1530 affects_type_identity, handler, exclude } */
1531 { "altivec", 1, 1, false, true, false, false,
1532 rs6000_handle_altivec_attribute, NULL },
1533 { "longcall", 0, 0, false, true, true, false,
1534 rs6000_handle_longcall_attribute, NULL },
1535 { "shortcall", 0, 0, false, true, true, false,
1536 rs6000_handle_longcall_attribute, NULL },
1537 { "ms_struct", 0, 0, false, false, false, false,
1538 rs6000_handle_struct_attribute, NULL },
1539 { "gcc_struct", 0, 0, false, false, false, false,
1540 rs6000_handle_struct_attribute, NULL },
1541 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1542 SUBTARGET_ATTRIBUTE_TABLE,
1544 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1547 #ifndef TARGET_PROFILE_KERNEL
1548 #define TARGET_PROFILE_KERNEL 0
1551 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1552 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1554 /* Initialize the GCC target structure. */
1555 #undef TARGET_ATTRIBUTE_TABLE
1556 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1557 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1558 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1559 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1560 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1562 #undef TARGET_ASM_ALIGNED_DI_OP
1563 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1565 /* Default unaligned ops are only provided for ELF. Find the ops needed
1566 for non-ELF systems. */
1567 #ifndef OBJECT_FORMAT_ELF
1569 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1571 #undef TARGET_ASM_UNALIGNED_HI_OP
1572 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1573 #undef TARGET_ASM_UNALIGNED_SI_OP
1574 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1575 #undef TARGET_ASM_UNALIGNED_DI_OP
1576 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1579 #undef TARGET_ASM_UNALIGNED_HI_OP
1580 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1581 #undef TARGET_ASM_UNALIGNED_SI_OP
1582 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1583 #undef TARGET_ASM_UNALIGNED_DI_OP
1584 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1585 #undef TARGET_ASM_ALIGNED_DI_OP
1586 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1590 /* This hook deals with fixups for relocatable code and DI-mode objects
1592 #undef TARGET_ASM_INTEGER
1593 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1595 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1596 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1597 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1600 #undef TARGET_SET_UP_BY_PROLOGUE
1601 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1603 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1604 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1605 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1606 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1607 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1608 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1609 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1610 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1611 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1612 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1613 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1614 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1616 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1617 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1619 #undef TARGET_INTERNAL_ARG_POINTER
1620 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1622 #undef TARGET_HAVE_TLS
1623 #define TARGET_HAVE_TLS HAVE_AS_TLS
1625 #undef TARGET_CANNOT_FORCE_CONST_MEM
1626 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1628 #undef TARGET_DELEGITIMIZE_ADDRESS
1629 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1631 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1632 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1634 #undef TARGET_LEGITIMATE_COMBINED_INSN
1635 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1637 #undef TARGET_ASM_FUNCTION_PROLOGUE
1638 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1639 #undef TARGET_ASM_FUNCTION_EPILOGUE
1640 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1642 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1643 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1645 #undef TARGET_LEGITIMIZE_ADDRESS
1646 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1648 #undef TARGET_SCHED_VARIABLE_ISSUE
1649 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1651 #undef TARGET_SCHED_ISSUE_RATE
1652 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1653 #undef TARGET_SCHED_ADJUST_COST
1654 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1655 #undef TARGET_SCHED_ADJUST_PRIORITY
1656 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1657 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1658 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1659 #undef TARGET_SCHED_INIT
1660 #define TARGET_SCHED_INIT rs6000_sched_init
1661 #undef TARGET_SCHED_FINISH
1662 #define TARGET_SCHED_FINISH rs6000_sched_finish
1663 #undef TARGET_SCHED_REORDER
1664 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1665 #undef TARGET_SCHED_REORDER2
1666 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1668 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1669 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1671 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1672 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1674 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1675 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1676 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1677 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1678 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1679 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1680 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1681 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1683 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1684 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1686 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1687 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1688 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1689 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1690 rs6000_builtin_support_vector_misalignment
1691 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1692 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1693 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1694 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1695 rs6000_builtin_vectorization_cost
1696 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1697 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1698 rs6000_preferred_simd_mode
1699 #undef TARGET_VECTORIZE_INIT_COST
1700 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1701 #undef TARGET_VECTORIZE_ADD_STMT_COST
1702 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1703 #undef TARGET_VECTORIZE_FINISH_COST
1704 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1705 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1706 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1708 #undef TARGET_INIT_BUILTINS
1709 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1710 #undef TARGET_BUILTIN_DECL
1711 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1713 #undef TARGET_FOLD_BUILTIN
1714 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1715 #undef TARGET_GIMPLE_FOLD_BUILTIN
1716 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1718 #undef TARGET_EXPAND_BUILTIN
1719 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1721 #undef TARGET_MANGLE_TYPE
1722 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1724 #undef TARGET_INIT_LIBFUNCS
1725 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1728 #undef TARGET_BINDS_LOCAL_P
1729 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1732 #undef TARGET_MS_BITFIELD_LAYOUT_P
1733 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1735 #undef TARGET_ASM_OUTPUT_MI_THUNK
1736 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1738 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1739 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1741 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1742 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1744 #undef TARGET_REGISTER_MOVE_COST
1745 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1746 #undef TARGET_MEMORY_MOVE_COST
1747 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1748 #undef TARGET_CANNOT_COPY_INSN_P
1749 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1750 #undef TARGET_RTX_COSTS
1751 #define TARGET_RTX_COSTS rs6000_rtx_costs
1752 #undef TARGET_ADDRESS_COST
1753 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1754 #undef TARGET_INSN_COST
1755 #define TARGET_INSN_COST rs6000_insn_cost
1757 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1758 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1760 #undef TARGET_PROMOTE_FUNCTION_MODE
1761 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1763 #undef TARGET_RETURN_IN_MEMORY
1764 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1766 #undef TARGET_RETURN_IN_MSB
1767 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1769 #undef TARGET_SETUP_INCOMING_VARARGS
1770 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1772 /* Always strict argument naming on rs6000. */
1773 #undef TARGET_STRICT_ARGUMENT_NAMING
1774 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1775 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1776 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1777 #undef TARGET_SPLIT_COMPLEX_ARG
1778 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1779 #undef TARGET_MUST_PASS_IN_STACK
1780 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1781 #undef TARGET_PASS_BY_REFERENCE
1782 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1783 #undef TARGET_ARG_PARTIAL_BYTES
1784 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1785 #undef TARGET_FUNCTION_ARG_ADVANCE
1786 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1787 #undef TARGET_FUNCTION_ARG
1788 #define TARGET_FUNCTION_ARG rs6000_function_arg
1789 #undef TARGET_FUNCTION_ARG_PADDING
1790 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1791 #undef TARGET_FUNCTION_ARG_BOUNDARY
1792 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1794 #undef TARGET_BUILD_BUILTIN_VA_LIST
1795 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1797 #undef TARGET_EXPAND_BUILTIN_VA_START
1798 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1800 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1801 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1803 #undef TARGET_EH_RETURN_FILTER_MODE
1804 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1806 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1807 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1809 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1810 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1812 #undef TARGET_FLOATN_MODE
1813 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1815 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1816 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1818 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1819 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1821 #undef TARGET_MD_ASM_ADJUST
1822 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1824 #undef TARGET_OPTION_OVERRIDE
1825 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1827 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1828 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1829 rs6000_builtin_vectorized_function
1831 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1832 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1833 rs6000_builtin_md_vectorized_function
1835 #undef TARGET_STACK_PROTECT_GUARD
1836 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1839 #undef TARGET_STACK_PROTECT_FAIL
1840 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1844 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1845 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1848 /* Use a 32-bit anchor range. This leads to sequences like:
1850 addis tmp,anchor,high
1853 where tmp itself acts as an anchor, and can be shared between
1854 accesses to the same 64k page. */
1855 #undef TARGET_MIN_ANCHOR_OFFSET
1856 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1857 #undef TARGET_MAX_ANCHOR_OFFSET
1858 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1859 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1860 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1861 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1862 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1864 #undef TARGET_BUILTIN_RECIPROCAL
1865 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1867 #undef TARGET_SECONDARY_RELOAD
1868 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1869 #undef TARGET_SECONDARY_MEMORY_NEEDED
1870 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1871 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1872 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1874 #undef TARGET_LEGITIMATE_ADDRESS_P
1875 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1877 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1878 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1880 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1881 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1883 #undef TARGET_CAN_ELIMINATE
1884 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1886 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1887 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1889 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1890 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1892 #undef TARGET_TRAMPOLINE_INIT
1893 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1895 #undef TARGET_FUNCTION_VALUE
1896 #define TARGET_FUNCTION_VALUE rs6000_function_value
1898 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1899 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1901 #undef TARGET_OPTION_SAVE
1902 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1904 #undef TARGET_OPTION_RESTORE
1905 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1907 #undef TARGET_OPTION_PRINT
1908 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1910 #undef TARGET_CAN_INLINE_P
1911 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1913 #undef TARGET_SET_CURRENT_FUNCTION
1914 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1916 #undef TARGET_LEGITIMATE_CONSTANT_P
1917 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1919 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1920 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1922 #undef TARGET_CAN_USE_DOLOOP_P
1923 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1925 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1926 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1928 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1929 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1930 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1931 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1932 #undef TARGET_UNWIND_WORD_MODE
1933 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1935 #undef TARGET_OFFLOAD_OPTIONS
1936 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1938 #undef TARGET_C_MODE_FOR_SUFFIX
1939 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1941 #undef TARGET_INVALID_BINARY_OP
1942 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1944 #undef TARGET_OPTAB_SUPPORTED_P
1945 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1947 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1948 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1950 #undef TARGET_COMPARE_VERSION_PRIORITY
1951 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1953 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1954 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1955 rs6000_generate_version_dispatcher_body
1957 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1958 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1959 rs6000_get_function_versions_dispatcher
1961 #undef TARGET_OPTION_FUNCTION_VERSIONS
1962 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1964 #undef TARGET_HARD_REGNO_NREGS
1965 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1966 #undef TARGET_HARD_REGNO_MODE_OK
1967 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1969 #undef TARGET_MODES_TIEABLE_P
1970 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1972 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1973 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1974 rs6000_hard_regno_call_part_clobbered
1976 #undef TARGET_SLOW_UNALIGNED_ACCESS
1977 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1979 #undef TARGET_CAN_CHANGE_MODE_CLASS
1980 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1982 #undef TARGET_CONSTANT_ALIGNMENT
1983 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1985 #undef TARGET_STARTING_FRAME_OFFSET
1986 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1988 #if TARGET_ELF && RS6000_WEAK
1989 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1990 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1994 /* Processor table. */
1997 const char *const name; /* Canonical processor name. */
1998 const enum processor_type processor; /* Processor type enum value. */
1999 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
2002 static struct rs6000_ptt const processor_target_table[] =
2004 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2005 #include "rs6000-cpus.def"
2009 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2013 rs6000_cpu_name_lookup (const char *name)
2019 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2020 if (! strcmp (name, processor_target_table[i].name))
2028 /* Return number of consecutive hard regs needed starting at reg REGNO
2029 to hold something of mode MODE.
2030 This is ordinarily the length in words of a value of mode MODE
2031 but can be less for certain modes in special long registers.
2033 POWER and PowerPC GPRs hold 32 bits worth;
2034 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2037 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2039 unsigned HOST_WIDE_INT reg_size;
2041 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2042 128-bit floating point that can go in vector registers, which has VSX
2043 memory addressing. */
2044 if (FP_REGNO_P (regno))
2045 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2046 ? UNITS_PER_VSX_WORD
2047 : UNITS_PER_FP_WORD);
2049 else if (ALTIVEC_REGNO_P (regno))
2050 reg_size = UNITS_PER_ALTIVEC_WORD;
2053 reg_size = UNITS_PER_WORD;
2055 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2058 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2061 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2063 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2065 if (COMPLEX_MODE_P (mode))
2066 mode = GET_MODE_INNER (mode);
2068 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2069 register combinations, and use PTImode where we need to deal with quad
2070 word memory operations. Don't allow quad words in the argument or frame
2071 pointer registers, just registers 0..31. */
2072 if (mode == PTImode)
2073 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2074 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2075 && ((regno & 1) == 0));
2077 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2078 implementations. Don't allow an item to be split between a FP register
2079 and an Altivec register. Allow TImode in all VSX registers if the user
2081 if (TARGET_VSX && VSX_REGNO_P (regno)
2082 && (VECTOR_MEM_VSX_P (mode)
2083 || FLOAT128_VECTOR_P (mode)
2084 || reg_addr[mode].scalar_in_vmx_p
2086 || (TARGET_VADDUQM && mode == V1TImode)))
2088 if (FP_REGNO_P (regno))
2089 return FP_REGNO_P (last_regno);
2091 if (ALTIVEC_REGNO_P (regno))
2093 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2096 return ALTIVEC_REGNO_P (last_regno);
2100 /* The GPRs can hold any mode, but values bigger than one register
2101 cannot go past R31. */
2102 if (INT_REGNO_P (regno))
2103 return INT_REGNO_P (last_regno);
2105 /* The float registers (except for VSX vector modes) can only hold floating
2106 modes and DImode. */
2107 if (FP_REGNO_P (regno))
2109 if (FLOAT128_VECTOR_P (mode))
2112 if (SCALAR_FLOAT_MODE_P (mode)
2113 && (mode != TDmode || (regno % 2) == 0)
2114 && FP_REGNO_P (last_regno))
2117 if (GET_MODE_CLASS (mode) == MODE_INT)
2119 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2122 if (TARGET_P8_VECTOR && (mode == SImode))
2125 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2132 /* The CR register can only hold CC modes. */
2133 if (CR_REGNO_P (regno))
2134 return GET_MODE_CLASS (mode) == MODE_CC;
2136 if (CA_REGNO_P (regno))
2137 return mode == Pmode || mode == SImode;
2139 /* AltiVec only in AldyVec registers. */
2140 if (ALTIVEC_REGNO_P (regno))
2141 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2142 || mode == V1TImode);
2144 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2145 and it must be able to fit within the register set. */
2147 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2150 /* Implement TARGET_HARD_REGNO_NREGS. */
2153 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2155 return rs6000_hard_regno_nregs[mode][regno];
2158 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2161 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2163 return rs6000_hard_regno_mode_ok_p[mode][regno];
2166 /* Implement TARGET_MODES_TIEABLE_P.
2168 PTImode cannot tie with other modes because PTImode is restricted to even
2169 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2172 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2173 128-bit floating point on VSX systems ties with other vectors. */
2176 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2178 if (mode1 == PTImode)
2179 return mode2 == PTImode;
2180 if (mode2 == PTImode)
2183 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2184 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2185 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2188 if (SCALAR_FLOAT_MODE_P (mode1))
2189 return SCALAR_FLOAT_MODE_P (mode2);
2190 if (SCALAR_FLOAT_MODE_P (mode2))
2193 if (GET_MODE_CLASS (mode1) == MODE_CC)
2194 return GET_MODE_CLASS (mode2) == MODE_CC;
2195 if (GET_MODE_CLASS (mode2) == MODE_CC)
2201 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2204 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2208 && GET_MODE_SIZE (mode) > 4
2209 && INT_REGNO_P (regno))
2213 && FP_REGNO_P (regno)
2214 && GET_MODE_SIZE (mode) > 8
2215 && !FLOAT128_2REG_P (mode))
2221 /* Print interesting facts about registers. */
2223 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2227 for (r = first_regno; r <= last_regno; ++r)
2229 const char *comma = "";
2232 if (first_regno == last_regno)
2233 fprintf (stderr, "%s:\t", reg_name);
2235 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2238 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2239 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2243 fprintf (stderr, ",\n\t");
2248 if (rs6000_hard_regno_nregs[m][r] > 1)
2249 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2250 rs6000_hard_regno_nregs[m][r]);
2252 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2257 if (call_used_regs[r])
2261 fprintf (stderr, ",\n\t");
2266 len += fprintf (stderr, "%s%s", comma, "call-used");
2274 fprintf (stderr, ",\n\t");
2279 len += fprintf (stderr, "%s%s", comma, "fixed");
2285 fprintf (stderr, ",\n\t");
2289 len += fprintf (stderr, "%sreg-class = %s", comma,
2290 reg_class_names[(int)rs6000_regno_regclass[r]]);
2295 fprintf (stderr, ",\n\t");
2299 fprintf (stderr, "%sregno = %d\n", comma, r);
2304 rs6000_debug_vector_unit (enum rs6000_vector v)
2310 case VECTOR_NONE: ret = "none"; break;
2311 case VECTOR_ALTIVEC: ret = "altivec"; break;
2312 case VECTOR_VSX: ret = "vsx"; break;
2313 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2314 case VECTOR_OTHER: ret = "other"; break;
2315 default: ret = "unknown"; break;
2321 /* Inner function printing just the address mask for a particular reload
2323 DEBUG_FUNCTION char *
2324 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2329 if ((mask & RELOAD_REG_VALID) != 0)
2331 else if (keep_spaces)
2334 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2336 else if (keep_spaces)
2339 if ((mask & RELOAD_REG_INDEXED) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2346 else if ((mask & RELOAD_REG_OFFSET) != 0)
2348 else if (keep_spaces)
2351 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2353 else if (keep_spaces)
2356 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2358 else if (keep_spaces)
2361 if ((mask & RELOAD_REG_AND_M16) != 0)
2363 else if (keep_spaces)
2371 /* Print the address masks in a human readble fashion. */
2373 rs6000_debug_print_mode (ssize_t m)
2379 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2380 for (rc = 0; rc < N_RELOAD_REG; rc++)
2381 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2382 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2384 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2385 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2386 fprintf (stderr, " Reload=%c%c",
2387 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2388 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2390 spaces += sizeof (" Reload=sl") - 1;
2392 if (reg_addr[m].scalar_in_vmx_p)
2394 fprintf (stderr, "%*s Upper=y", spaces, "");
2398 spaces += sizeof (" Upper=y") - 1;
2400 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2401 || reg_addr[m].fused_toc);
2404 for (rc = 0; rc < N_RELOAD_REG; rc++)
2406 if (rc != RELOAD_REG_ANY)
2408 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2410 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2411 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2412 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2414 fuse_extra_p = true;
2423 fprintf (stderr, "%*s Fuse:", spaces, "");
2426 for (rc = 0; rc < N_RELOAD_REG; rc++)
2428 if (rc != RELOAD_REG_ANY)
2432 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2434 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2439 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2441 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2446 if (load == '-' && store == '-')
2450 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2451 reload_reg_map[rc].name[0], load, store);
2457 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2459 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2463 spaces += sizeof (" P8gpr") - 1;
2465 if (reg_addr[m].fused_toc)
2467 fprintf (stderr, "%*sToc", (spaces + 1), "");
2471 spaces += sizeof (" Toc") - 1;
2474 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2476 if (rs6000_vector_unit[m] != VECTOR_NONE
2477 || rs6000_vector_mem[m] != VECTOR_NONE)
2479 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2481 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2482 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2485 fputs ("\n", stderr);
2488 #define DEBUG_FMT_ID "%-32s= "
2489 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2490 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2491 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2493 /* Print various interesting information with -mdebug=reg. */
2495 rs6000_debug_reg_global (void)
2497 static const char *const tf[2] = { "false", "true" };
2498 const char *nl = (const char *)0;
2501 char costly_num[20];
2503 char flags_buffer[40];
2504 const char *costly_str;
2505 const char *nop_str;
2506 const char *trace_str;
2507 const char *abi_str;
2508 const char *cmodel_str;
2509 struct cl_target_option cl_opts;
2511 /* Modes we want tieable information on. */
2512 static const machine_mode print_tieable_modes[] = {
2546 /* Virtual regs we are interested in. */
2547 const static struct {
2548 int regno; /* register number. */
2549 const char *name; /* register name. */
2550 } virtual_regs[] = {
2551 { STACK_POINTER_REGNUM, "stack pointer:" },
2552 { TOC_REGNUM, "toc: " },
2553 { STATIC_CHAIN_REGNUM, "static chain: " },
2554 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2555 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2556 { ARG_POINTER_REGNUM, "arg pointer: " },
2557 { FRAME_POINTER_REGNUM, "frame pointer:" },
2558 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2559 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2560 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2561 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2562 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2563 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2564 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2565 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2566 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2569 fputs ("\nHard register information:\n", stderr);
2570 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2571 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2572 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2575 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2576 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2577 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2578 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2579 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2580 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2582 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2583 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2584 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2588 "d reg_class = %s\n"
2589 "f reg_class = %s\n"
2590 "v reg_class = %s\n"
2591 "wa reg_class = %s\n"
2592 "wb reg_class = %s\n"
2593 "wd reg_class = %s\n"
2594 "we reg_class = %s\n"
2595 "wf reg_class = %s\n"
2596 "wg reg_class = %s\n"
2597 "wh reg_class = %s\n"
2598 "wi reg_class = %s\n"
2599 "wj reg_class = %s\n"
2600 "wk reg_class = %s\n"
2601 "wl reg_class = %s\n"
2602 "wm reg_class = %s\n"
2603 "wo reg_class = %s\n"
2604 "wp reg_class = %s\n"
2605 "wq reg_class = %s\n"
2606 "wr reg_class = %s\n"
2607 "ws reg_class = %s\n"
2608 "wt reg_class = %s\n"
2609 "wu reg_class = %s\n"
2610 "wv reg_class = %s\n"
2611 "ww reg_class = %s\n"
2612 "wx reg_class = %s\n"
2613 "wy reg_class = %s\n"
2614 "wz reg_class = %s\n"
2615 "wA reg_class = %s\n"
2616 "wH reg_class = %s\n"
2617 "wI reg_class = %s\n"
2618 "wJ reg_class = %s\n"
2619 "wK reg_class = %s\n"
2621 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2622 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2651 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2652 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2655 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2656 rs6000_debug_print_mode (m);
2658 fputs ("\n", stderr);
2660 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2662 machine_mode mode1 = print_tieable_modes[m1];
2663 bool first_time = true;
2665 nl = (const char *)0;
2666 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2668 machine_mode mode2 = print_tieable_modes[m2];
2669 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2673 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2678 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2683 fputs ("\n", stderr);
2689 if (rs6000_recip_control)
2691 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2693 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2694 if (rs6000_recip_bits[m])
2697 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2699 (RS6000_RECIP_AUTO_RE_P (m)
2701 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2702 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2704 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2707 fputs ("\n", stderr);
2710 if (rs6000_cpu_index >= 0)
2712 const char *name = processor_target_table[rs6000_cpu_index].name;
2714 = processor_target_table[rs6000_cpu_index].target_enable;
2716 sprintf (flags_buffer, "-mcpu=%s flags", name);
2717 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2720 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2722 if (rs6000_tune_index >= 0)
2724 const char *name = processor_target_table[rs6000_tune_index].name;
2726 = processor_target_table[rs6000_tune_index].target_enable;
2728 sprintf (flags_buffer, "-mtune=%s flags", name);
2729 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2732 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2734 cl_target_option_save (&cl_opts, &global_options);
2735 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2738 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2739 rs6000_isa_flags_explicit);
2741 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2742 rs6000_builtin_mask);
2744 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2746 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2747 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2749 switch (rs6000_sched_costly_dep)
2751 case max_dep_latency:
2752 costly_str = "max_dep_latency";
2756 costly_str = "no_dep_costly";
2759 case all_deps_costly:
2760 costly_str = "all_deps_costly";
2763 case true_store_to_load_dep_costly:
2764 costly_str = "true_store_to_load_dep_costly";
2767 case store_to_load_dep_costly:
2768 costly_str = "store_to_load_dep_costly";
2772 costly_str = costly_num;
2773 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2777 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2779 switch (rs6000_sched_insert_nops)
2781 case sched_finish_regroup_exact:
2782 nop_str = "sched_finish_regroup_exact";
2785 case sched_finish_pad_groups:
2786 nop_str = "sched_finish_pad_groups";
2789 case sched_finish_none:
2790 nop_str = "sched_finish_none";
2795 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2799 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2801 switch (rs6000_sdata)
2808 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2812 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2816 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2821 switch (rs6000_traceback)
2823 case traceback_default: trace_str = "default"; break;
2824 case traceback_none: trace_str = "none"; break;
2825 case traceback_part: trace_str = "part"; break;
2826 case traceback_full: trace_str = "full"; break;
2827 default: trace_str = "unknown"; break;
2830 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2832 switch (rs6000_current_cmodel)
2834 case CMODEL_SMALL: cmodel_str = "small"; break;
2835 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2836 case CMODEL_LARGE: cmodel_str = "large"; break;
2837 default: cmodel_str = "unknown"; break;
2840 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2842 switch (rs6000_current_abi)
2844 case ABI_NONE: abi_str = "none"; break;
2845 case ABI_AIX: abi_str = "aix"; break;
2846 case ABI_ELFv2: abi_str = "ELFv2"; break;
2847 case ABI_V4: abi_str = "V4"; break;
2848 case ABI_DARWIN: abi_str = "darwin"; break;
2849 default: abi_str = "unknown"; break;
2852 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2854 if (rs6000_altivec_abi)
2855 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2857 if (rs6000_darwin64_abi)
2858 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2860 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2861 (TARGET_SOFT_FLOAT ? "true" : "false"));
2863 if (TARGET_LINK_STACK)
2864 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2866 if (TARGET_P8_FUSION)
2870 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2871 if (TARGET_TOC_FUSION)
2872 strcat (options, ", toc");
2874 if (TARGET_P8_FUSION_SIGN)
2875 strcat (options, ", sign");
2877 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2880 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2881 TARGET_SECURE_PLT ? "secure" : "bss");
2882 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2883 aix_struct_return ? "aix" : "sysv");
2884 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2885 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2886 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2887 tf[!!rs6000_align_branch_targets]);
2888 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2889 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2890 rs6000_long_double_type_size);
2891 if (rs6000_long_double_type_size == 128)
2893 fprintf (stderr, DEBUG_FMT_S, "long double type",
2894 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2895 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2896 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2898 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2899 (int)rs6000_sched_restricted_insns_priority);
2900 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2902 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2903 (int)RS6000_BUILTIN_COUNT);
2905 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2906 (int)TARGET_FLOAT128_ENABLE_TYPE);
2909 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2910 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2912 if (TARGET_DIRECT_MOVE_128)
2913 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2914 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2918 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2919 legitimate address support to figure out the appropriate addressing to
2923 rs6000_setup_reg_addr_masks (void)
2925 ssize_t rc, reg, m, nregs;
2926 addr_mask_type any_addr_mask, addr_mask;
2928 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2930 machine_mode m2 = (machine_mode) m;
2931 bool complex_p = false;
2932 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2935 if (COMPLEX_MODE_P (m2))
2938 m2 = GET_MODE_INNER (m2);
2941 msize = GET_MODE_SIZE (m2);
2943 /* SDmode is special in that we want to access it only via REG+REG
2944 addressing on power7 and above, since we want to use the LFIWZX and
2945 STFIWZX instructions to load it. */
2946 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2949 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2952 reg = reload_reg_map[rc].reg;
2954 /* Can mode values go in the GPR/FPR/Altivec registers? */
2955 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2957 bool small_int_vsx_p = (small_int_p
2958 && (rc == RELOAD_REG_FPR
2959 || rc == RELOAD_REG_VMX));
2961 nregs = rs6000_hard_regno_nregs[m][reg];
2962 addr_mask |= RELOAD_REG_VALID;
2964 /* Indicate if the mode takes more than 1 physical register. If
2965 it takes a single register, indicate it can do REG+REG
2966 addressing. Small integers in VSX registers can only do
2967 REG+REG addressing. */
2968 if (small_int_vsx_p)
2969 addr_mask |= RELOAD_REG_INDEXED;
2970 else if (nregs > 1 || m == BLKmode || complex_p)
2971 addr_mask |= RELOAD_REG_MULTIPLE;
2973 addr_mask |= RELOAD_REG_INDEXED;
2975 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2976 addressing. If we allow scalars into Altivec registers,
2977 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2979 For VSX systems, we don't allow update addressing for
2980 DFmode/SFmode if those registers can go in both the
2981 traditional floating point registers and Altivec registers.
2982 The load/store instructions for the Altivec registers do not
2983 have update forms. If we allowed update addressing, it seems
2984 to break IV-OPT code using floating point if the index type is
2985 int instead of long (PR target/81550 and target/84042). */
2988 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2990 && !VECTOR_MODE_P (m2)
2991 && !FLOAT128_VECTOR_P (m2)
2993 && (m != E_DFmode || !TARGET_VSX)
2994 && (m != E_SFmode || !TARGET_P8_VECTOR)
2995 && !small_int_vsx_p)
2997 addr_mask |= RELOAD_REG_PRE_INCDEC;
2999 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
3000 we don't allow PRE_MODIFY for some multi-register
3005 addr_mask |= RELOAD_REG_PRE_MODIFY;
3009 if (TARGET_POWERPC64)
3010 addr_mask |= RELOAD_REG_PRE_MODIFY;
3015 if (TARGET_HARD_FLOAT)
3016 addr_mask |= RELOAD_REG_PRE_MODIFY;
3022 /* GPR and FPR registers can do REG+OFFSET addressing, except
3023 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3024 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3025 if ((addr_mask != 0) && !indexed_only_p
3027 && (rc == RELOAD_REG_GPR
3028 || ((msize == 8 || m2 == SFmode)
3029 && (rc == RELOAD_REG_FPR
3030 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3031 addr_mask |= RELOAD_REG_OFFSET;
3033 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3034 instructions are enabled. The offset for 128-bit VSX registers is
3035 only 12-bits. While GPRs can handle the full offset range, VSX
3036 registers can only handle the restricted range. */
3037 else if ((addr_mask != 0) && !indexed_only_p
3038 && msize == 16 && TARGET_P9_VECTOR
3039 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3040 || (m2 == TImode && TARGET_VSX)))
3042 addr_mask |= RELOAD_REG_OFFSET;
3043 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3044 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3047 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3048 addressing on 128-bit types. */
3049 if (rc == RELOAD_REG_VMX && msize == 16
3050 && (addr_mask & RELOAD_REG_VALID) != 0)
3051 addr_mask |= RELOAD_REG_AND_M16;
3053 reg_addr[m].addr_mask[rc] = addr_mask;
3054 any_addr_mask |= addr_mask;
3057 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3062 /* Initialize the various global tables that are based on register size. */
3064 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3070 /* Precalculate REGNO_REG_CLASS. */
3071 rs6000_regno_regclass[0] = GENERAL_REGS;
3072 for (r = 1; r < 32; ++r)
3073 rs6000_regno_regclass[r] = BASE_REGS;
3075 for (r = 32; r < 64; ++r)
3076 rs6000_regno_regclass[r] = FLOAT_REGS;
3078 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3079 rs6000_regno_regclass[r] = NO_REGS;
3081 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3082 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3084 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3085 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3086 rs6000_regno_regclass[r] = CR_REGS;
3088 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3089 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3090 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3091 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3092 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3093 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3094 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3095 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3096 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3097 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3099 /* Precalculate register class to simpler reload register class. We don't
3100 need all of the register classes that are combinations of different
3101 classes, just the simple ones that have constraint letters. */
3102 for (c = 0; c < N_REG_CLASSES; c++)
3103 reg_class_to_reg_type[c] = NO_REG_TYPE;
3105 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3106 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3107 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3108 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3109 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3110 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3111 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3112 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3113 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3114 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3118 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3119 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3123 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3124 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3127 /* Precalculate the valid memory formats as well as the vector information,
3128 this must be set up before the rs6000_hard_regno_nregs_internal calls
3130 gcc_assert ((int)VECTOR_NONE == 0);
3131 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3132 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3134 gcc_assert ((int)CODE_FOR_nothing == 0);
3135 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3137 gcc_assert ((int)NO_REGS == 0);
3138 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3140 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3141 believes it can use native alignment or still uses 128-bit alignment. */
3142 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3153 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3154 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3155 if (TARGET_FLOAT128_TYPE)
3157 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3158 rs6000_vector_align[KFmode] = 128;
3160 if (FLOAT128_IEEE_P (TFmode))
3162 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3163 rs6000_vector_align[TFmode] = 128;
3167 /* V2DF mode, VSX only. */
3170 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3171 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3172 rs6000_vector_align[V2DFmode] = align64;
3175 /* V4SF mode, either VSX or Altivec. */
3178 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3179 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3180 rs6000_vector_align[V4SFmode] = align32;
3182 else if (TARGET_ALTIVEC)
3184 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3185 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3186 rs6000_vector_align[V4SFmode] = align32;
3189 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3193 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3194 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3195 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3196 rs6000_vector_align[V4SImode] = align32;
3197 rs6000_vector_align[V8HImode] = align32;
3198 rs6000_vector_align[V16QImode] = align32;
3202 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3203 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3204 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3208 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3209 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3210 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3214 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3215 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3218 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3219 rs6000_vector_unit[V2DImode]
3220 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3221 rs6000_vector_align[V2DImode] = align64;
3223 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3224 rs6000_vector_unit[V1TImode]
3225 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3226 rs6000_vector_align[V1TImode] = 128;
3229 /* DFmode, see if we want to use the VSX unit. Memory is handled
3230 differently, so don't set rs6000_vector_mem. */
3233 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3234 rs6000_vector_align[DFmode] = 64;
3237 /* SFmode, see if we want to use the VSX unit. */
3238 if (TARGET_P8_VECTOR)
3240 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3241 rs6000_vector_align[SFmode] = 32;
3244 /* Allow TImode in VSX register and set the VSX memory macros. */
3247 rs6000_vector_mem[TImode] = VECTOR_VSX;
3248 rs6000_vector_align[TImode] = align64;
3251 /* Register class constraints for the constraints that depend on compile
3252 switches. When the VSX code was added, different constraints were added
3253 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3254 of the VSX registers are used. The register classes for scalar floating
3255 point types is set, based on whether we allow that type into the upper
3256 (Altivec) registers. GCC has register classes to target the Altivec
3257 registers for load/store operations, to select using a VSX memory
3258 operation instead of the traditional floating point operation. The
3261 d - Register class to use with traditional DFmode instructions.
3262 f - Register class to use with traditional SFmode instructions.
3263 v - Altivec register.
3264 wa - Any VSX register.
3265 wc - Reserved to represent individual CR bits (used in LLVM).
3266 wd - Preferred register class for V2DFmode.
3267 wf - Preferred register class for V4SFmode.
3268 wg - Float register for power6x move insns.
3269 wh - FP register for direct move instructions.
3270 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3271 wj - FP or VSX register to hold 64-bit integers for direct moves.
3272 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3273 wl - Float register if we can do 32-bit signed int loads.
3274 wm - VSX register for ISA 2.07 direct move operations.
3275 wn - always NO_REGS.
3276 wr - GPR if 64-bit mode is permitted.
3277 ws - Register class to do ISA 2.06 DF operations.
3278 wt - VSX register for TImode in VSX registers.
3279 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3280 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3281 ww - Register class to do SF conversions in with VSX operations.
3282 wx - Float register if we can do 32-bit int stores.
3283 wy - Register class to do ISA 2.07 SF operations.
3284 wz - Float register if we can do 32-bit unsigned int loads.
3285 wH - Altivec register if SImode is allowed in VSX registers.
3286 wI - VSX register if SImode is allowed in VSX registers.
3287 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3288 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3290 if (TARGET_HARD_FLOAT)
3292 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3293 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3298 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3299 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3300 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3301 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3302 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3303 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3304 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3307 /* Add conditional constraints based on various options, to allow us to
3308 collapse multiple insn patterns. */
3310 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3312 if (TARGET_MFPGPR) /* DFmode */
3313 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3316 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3318 if (TARGET_DIRECT_MOVE)
3320 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3321 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3322 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3323 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3324 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3325 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3328 if (TARGET_POWERPC64)
3330 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3331 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3334 if (TARGET_P8_VECTOR) /* SFmode */
3336 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3337 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3338 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3340 else if (TARGET_VSX)
3341 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3344 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3347 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3349 if (TARGET_FLOAT128_TYPE)
3351 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3352 if (FLOAT128_IEEE_P (TFmode))
3353 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3356 if (TARGET_P9_VECTOR)
3358 /* Support for new D-form instructions. */
3359 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3361 /* Support for ISA 3.0 (power9) vectors. */
3362 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3365 /* Support for new direct moves (ISA 3.0 + 64bit). */
3366 if (TARGET_DIRECT_MOVE_128)
3367 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3369 /* Support small integers in VSX registers. */
3370 if (TARGET_P8_VECTOR)
3372 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3373 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3374 if (TARGET_P9_VECTOR)
3376 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3377 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3381 /* Set up the reload helper and direct move functions. */
3382 if (TARGET_VSX || TARGET_ALTIVEC)
3386 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3387 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3388 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3389 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3390 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3391 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3392 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3393 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3394 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3395 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3396 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3397 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3398 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3399 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3400 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3401 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3402 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3403 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3404 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3405 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3407 if (FLOAT128_VECTOR_P (KFmode))
3409 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3410 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3413 if (FLOAT128_VECTOR_P (TFmode))
3415 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3416 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3419 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3421 if (TARGET_NO_SDMODE_STACK)
3423 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3424 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3429 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3430 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3433 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3435 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3436 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3437 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3438 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3439 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3440 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3441 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3442 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3443 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3445 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3446 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3447 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3448 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3449 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3450 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3451 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3452 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3453 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3455 if (FLOAT128_VECTOR_P (KFmode))
3457 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3458 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3461 if (FLOAT128_VECTOR_P (TFmode))
3463 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3464 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3470 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3471 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3472 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3473 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3474 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3475 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3476 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3477 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3478 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3479 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3480 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3481 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3482 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3483 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3484 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3485 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3486 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3487 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3488 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3489 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3491 if (FLOAT128_VECTOR_P (KFmode))
3493 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3494 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3497 if (FLOAT128_IEEE_P (TFmode))
3499 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3500 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3503 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3505 if (TARGET_NO_SDMODE_STACK)
3507 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3508 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3513 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3514 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3517 if (TARGET_DIRECT_MOVE)
3519 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3520 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3521 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3525 reg_addr[DFmode].scalar_in_vmx_p = true;
3526 reg_addr[DImode].scalar_in_vmx_p = true;
3528 if (TARGET_P8_VECTOR)
3530 reg_addr[SFmode].scalar_in_vmx_p = true;
3531 reg_addr[SImode].scalar_in_vmx_p = true;
3533 if (TARGET_P9_VECTOR)
3535 reg_addr[HImode].scalar_in_vmx_p = true;
3536 reg_addr[QImode].scalar_in_vmx_p = true;
3541 /* Setup the fusion operations. */
3542 if (TARGET_P8_FUSION)
3544 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3545 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3546 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3548 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3551 if (TARGET_P9_FUSION)
3554 enum machine_mode mode; /* mode of the fused type. */
3555 enum machine_mode pmode; /* pointer mode. */
3556 enum rs6000_reload_reg_type rtype; /* register type. */
3557 enum insn_code load; /* load insn. */
3558 enum insn_code store; /* store insn. */
3561 static const struct fuse_insns addis_insns[] = {
3562 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3563 CODE_FOR_fusion_vsx_di_sf_load,
3564 CODE_FOR_fusion_vsx_di_sf_store },
3566 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3567 CODE_FOR_fusion_vsx_si_sf_load,
3568 CODE_FOR_fusion_vsx_si_sf_store },
3570 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3571 CODE_FOR_fusion_vsx_di_df_load,
3572 CODE_FOR_fusion_vsx_di_df_store },
3574 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3575 CODE_FOR_fusion_vsx_si_df_load,
3576 CODE_FOR_fusion_vsx_si_df_store },
3578 { E_DImode, E_DImode, RELOAD_REG_FPR,
3579 CODE_FOR_fusion_vsx_di_di_load,
3580 CODE_FOR_fusion_vsx_di_di_store },
3582 { E_DImode, E_SImode, RELOAD_REG_FPR,
3583 CODE_FOR_fusion_vsx_si_di_load,
3584 CODE_FOR_fusion_vsx_si_di_store },
3586 { E_QImode, E_DImode, RELOAD_REG_GPR,
3587 CODE_FOR_fusion_gpr_di_qi_load,
3588 CODE_FOR_fusion_gpr_di_qi_store },
3590 { E_QImode, E_SImode, RELOAD_REG_GPR,
3591 CODE_FOR_fusion_gpr_si_qi_load,
3592 CODE_FOR_fusion_gpr_si_qi_store },
3594 { E_HImode, E_DImode, RELOAD_REG_GPR,
3595 CODE_FOR_fusion_gpr_di_hi_load,
3596 CODE_FOR_fusion_gpr_di_hi_store },
3598 { E_HImode, E_SImode, RELOAD_REG_GPR,
3599 CODE_FOR_fusion_gpr_si_hi_load,
3600 CODE_FOR_fusion_gpr_si_hi_store },
3602 { E_SImode, E_DImode, RELOAD_REG_GPR,
3603 CODE_FOR_fusion_gpr_di_si_load,
3604 CODE_FOR_fusion_gpr_di_si_store },
3606 { E_SImode, E_SImode, RELOAD_REG_GPR,
3607 CODE_FOR_fusion_gpr_si_si_load,
3608 CODE_FOR_fusion_gpr_si_si_store },
3610 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3611 CODE_FOR_fusion_gpr_di_sf_load,
3612 CODE_FOR_fusion_gpr_di_sf_store },
3614 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3615 CODE_FOR_fusion_gpr_si_sf_load,
3616 CODE_FOR_fusion_gpr_si_sf_store },
3618 { E_DImode, E_DImode, RELOAD_REG_GPR,
3619 CODE_FOR_fusion_gpr_di_di_load,
3620 CODE_FOR_fusion_gpr_di_di_store },
3622 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3623 CODE_FOR_fusion_gpr_di_df_load,
3624 CODE_FOR_fusion_gpr_di_df_store },
3627 machine_mode cur_pmode = Pmode;
3630 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3632 machine_mode xmode = addis_insns[i].mode;
3633 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3635 if (addis_insns[i].pmode != cur_pmode)
3638 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3641 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3642 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3644 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3646 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3647 = addis_insns[i].load;
3648 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3649 = addis_insns[i].store;
3654 /* Note which types we support fusing TOC setup plus memory insn. We only do
3655 fused TOCs for medium/large code models. */
3656 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3657 && (TARGET_CMODEL != CMODEL_SMALL))
3659 reg_addr[QImode].fused_toc = true;
3660 reg_addr[HImode].fused_toc = true;
3661 reg_addr[SImode].fused_toc = true;
3662 reg_addr[DImode].fused_toc = true;
3663 if (TARGET_HARD_FLOAT)
3665 reg_addr[SFmode].fused_toc = true;
3666 reg_addr[DFmode].fused_toc = true;
3670 /* Precalculate HARD_REGNO_NREGS. */
3671 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3672 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3673 rs6000_hard_regno_nregs[m][r]
3674 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3676 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3677 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3678 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3679 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3680 rs6000_hard_regno_mode_ok_p[m][r] = true;
3682 /* Precalculate CLASS_MAX_NREGS sizes. */
3683 for (c = 0; c < LIM_REG_CLASSES; ++c)
3687 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3688 reg_size = UNITS_PER_VSX_WORD;
3690 else if (c == ALTIVEC_REGS)
3691 reg_size = UNITS_PER_ALTIVEC_WORD;
3693 else if (c == FLOAT_REGS)
3694 reg_size = UNITS_PER_FP_WORD;
3697 reg_size = UNITS_PER_WORD;
3699 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3701 machine_mode m2 = (machine_mode)m;
3702 int reg_size2 = reg_size;
3704 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3706 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3707 reg_size2 = UNITS_PER_FP_WORD;
3709 rs6000_class_max_nregs[m][c]
3710 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3714 /* Calculate which modes to automatically generate code to use a the
3715 reciprocal divide and square root instructions. In the future, possibly
3716 automatically generate the instructions even if the user did not specify
3717 -mrecip. The older machines double precision reciprocal sqrt estimate is
3718 not accurate enough. */
3719 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3721 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3723 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3724 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3725 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3726 if (VECTOR_UNIT_VSX_P (V2DFmode))
3727 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3729 if (TARGET_FRSQRTES)
3730 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3732 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3733 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3734 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3735 if (VECTOR_UNIT_VSX_P (V2DFmode))
3736 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3738 if (rs6000_recip_control)
3740 if (!flag_finite_math_only)
3741 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3743 if (flag_trapping_math)
3744 warning (0, "%qs requires %qs or %qs", "-mrecip",
3745 "-fno-trapping-math", "-ffast-math");
3746 if (!flag_reciprocal_math)
3747 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3749 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3751 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3752 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3753 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3755 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3756 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3757 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3759 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3760 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3761 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3763 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3764 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3765 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3767 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3768 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3769 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3771 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3772 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3773 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3775 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3776 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3777 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3779 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3780 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3781 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3785 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3786 legitimate address support to figure out the appropriate addressing to
3788 rs6000_setup_reg_addr_masks ();
3790 if (global_init_p || TARGET_DEBUG_TARGET)
3792 if (TARGET_DEBUG_REG)
3793 rs6000_debug_reg_global ();
3795 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3797 "SImode variable mult cost = %d\n"
3798 "SImode constant mult cost = %d\n"
3799 "SImode short constant mult cost = %d\n"
3800 "DImode multipliciation cost = %d\n"
3801 "SImode division cost = %d\n"
3802 "DImode division cost = %d\n"
3803 "Simple fp operation cost = %d\n"
3804 "DFmode multiplication cost = %d\n"
3805 "SFmode division cost = %d\n"
3806 "DFmode division cost = %d\n"
3807 "cache line size = %d\n"
3808 "l1 cache size = %d\n"
3809 "l2 cache size = %d\n"
3810 "simultaneous prefetches = %d\n"
3813 rs6000_cost->mulsi_const,
3814 rs6000_cost->mulsi_const9,
3822 rs6000_cost->cache_line_size,
3823 rs6000_cost->l1_cache_size,
3824 rs6000_cost->l2_cache_size,
3825 rs6000_cost->simultaneous_prefetches);
3830 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3833 darwin_rs6000_override_options (void)
3835 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3837 rs6000_altivec_abi = 1;
3838 TARGET_ALTIVEC_VRSAVE = 1;
3839 rs6000_current_abi = ABI_DARWIN;
3841 if (DEFAULT_ABI == ABI_DARWIN
3843 darwin_one_byte_bool = 1;
3845 if (TARGET_64BIT && ! TARGET_POWERPC64)
3847 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3848 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3852 rs6000_default_long_calls = 1;
3853 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3856 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3858 if (!flag_mkernel && !flag_apple_kext
3860 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3861 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3863 /* Unless the user (not the configurer) has explicitly overridden
3864 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3865 G4 unless targeting the kernel. */
3868 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3869 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3870 && ! global_options_set.x_rs6000_cpu_index)
3872 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3877 /* If not otherwise specified by a target, make 'long double' equivalent to
3880 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3881 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3884 /* Return the builtin mask of the various options used that could affect which
3885 builtins were used. In the past we used target_flags, but we've run out of
3886 bits, and some options are no longer in target_flags. */
3889 rs6000_builtin_mask_calculate (void)
3891 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3892 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3893 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3894 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3895 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3896 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3897 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3898 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3899 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3900 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3901 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3902 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3903 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3904 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3905 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3906 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3907 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3908 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3909 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3910 | ((TARGET_LONG_DOUBLE_128
3911 && TARGET_HARD_FLOAT
3912 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3913 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3914 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3917 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3918 to clobber the XER[CA] bit because clobbering that bit without telling
3919 the compiler worked just fine with versions of GCC before GCC 5, and
3920 breaking a lot of older code in ways that are hard to track down is
3921 not such a great idea. */
3924 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3925 vec<const char *> &/*constraints*/,
3926 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3928 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3929 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3933 /* Override command line options.
3935 Combine build-specific configuration information with options
3936 specified on the command line to set various state variables which
3937 influence code generation, optimization, and expansion of built-in
3938 functions. Assure that command-line configuration preferences are
3939 compatible with each other and with the build configuration; issue
3940 warnings while adjusting configuration or error messages while
3941 rejecting configuration.
3943 Upon entry to this function:
3945 This function is called once at the beginning of
3946 compilation, and then again at the start and end of compiling
3947 each section of code that has a different configuration, as
3948 indicated, for example, by adding the
3950 __attribute__((__target__("cpu=power9")))
3952 qualifier to a function definition or, for example, by bracketing
3955 #pragma GCC target("altivec")
3959 #pragma GCC reset_options
3961 directives. Parameter global_init_p is true for the initial
3962 invocation, which initializes global variables, and false for all
3963 subsequent invocations.
3966 Various global state information is assumed to be valid. This
3967 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3968 default CPU specified at build configure time, TARGET_DEFAULT,
3969 representing the default set of option flags for the default
3970 target, and global_options_set.x_rs6000_isa_flags, representing
3971 which options were requested on the command line.
3973 Upon return from this function:
3975 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3976 was set by name on the command line. Additionally, if certain
3977 attributes are automatically enabled or disabled by this function
3978 in order to assure compatibility between options and
3979 configuration, the flags associated with those attributes are
3980 also set. By setting these "explicit bits", we avoid the risk
3981 that other code might accidentally overwrite these particular
3982 attributes with "default values".
3984 The various bits of rs6000_isa_flags are set to indicate the
3985 target options that have been selected for the most current
3986 compilation efforts. This has the effect of also turning on the
3987 associated TARGET_XXX values since these are macros which are
3988 generally defined to test the corresponding bit of the
3989 rs6000_isa_flags variable.
3991 The variable rs6000_builtin_mask is set to represent the target
3992 options for the most current compilation efforts, consistent with
3993 the current contents of rs6000_isa_flags. This variable controls
3994 expansion of built-in functions.
3996 Various other global variables and fields of global structures
3997 (over 50 in all) are initialized to reflect the desired options
3998 for the most current compilation efforts. */
4001 rs6000_option_override_internal (bool global_init_p)
4005 HOST_WIDE_INT set_masks;
4006 HOST_WIDE_INT ignore_masks;
4009 struct cl_target_option *main_target_opt
4010 = ((global_init_p || target_option_default_node == NULL)
4011 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4013 /* Print defaults. */
4014 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4015 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4017 /* Remember the explicit arguments. */
4019 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4021 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4022 library functions, so warn about it. The flag may be useful for
4023 performance studies from time to time though, so don't disable it
4025 if (global_options_set.x_rs6000_alignment_flags
4026 && rs6000_alignment_flags == MASK_ALIGN_POWER
4027 && DEFAULT_ABI == ABI_DARWIN
4029 warning (0, "%qs is not supported for 64-bit Darwin;"
4030 " it is incompatible with the installed C and C++ libraries",
4033 /* Numerous experiment shows that IRA based loop pressure
4034 calculation works better for RTL loop invariant motion on targets
4035 with enough (>= 32) registers. It is an expensive optimization.
4036 So it is on only for peak performance. */
4037 if (optimize >= 3 && global_init_p
4038 && !global_options_set.x_flag_ira_loop_pressure)
4039 flag_ira_loop_pressure = 1;
4041 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4042 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4043 options were already specified. */
4044 if (flag_sanitize & SANITIZE_USER_ADDRESS
4045 && !global_options_set.x_flag_asynchronous_unwind_tables)
4046 flag_asynchronous_unwind_tables = 1;
4048 /* Set the pointer size. */
4051 rs6000_pmode = DImode;
4052 rs6000_pointer_size = 64;
4056 rs6000_pmode = SImode;
4057 rs6000_pointer_size = 32;
4060 /* Some OSs don't support saving the high part of 64-bit registers on context
4061 switch. Other OSs don't support saving Altivec registers. On those OSs,
4062 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4063 if the user wants either, the user must explicitly specify them and we
4064 won't interfere with the user's specification. */
4066 set_masks = POWERPC_MASKS;
4067 #ifdef OS_MISSING_POWERPC64
4068 if (OS_MISSING_POWERPC64)
4069 set_masks &= ~OPTION_MASK_POWERPC64;
4071 #ifdef OS_MISSING_ALTIVEC
4072 if (OS_MISSING_ALTIVEC)
4073 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4074 | OTHER_VSX_VECTOR_MASKS);
4077 /* Don't override by the processor default if given explicitly. */
4078 set_masks &= ~rs6000_isa_flags_explicit;
4080 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4081 the cpu in a target attribute or pragma, but did not specify a tuning
4082 option, use the cpu for the tuning option rather than the option specified
4083 with -mtune on the command line. Process a '--with-cpu' configuration
4084 request as an implicit --cpu. */
4085 if (rs6000_cpu_index >= 0)
4086 cpu_index = rs6000_cpu_index;
4087 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4088 cpu_index = main_target_opt->x_rs6000_cpu_index;
4089 else if (OPTION_TARGET_CPU_DEFAULT)
4090 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4094 const char *unavailable_cpu = NULL;
4095 switch (processor_target_table[cpu_index].processor)
4097 #ifndef HAVE_AS_POWER9
4098 case PROCESSOR_POWER9:
4099 unavailable_cpu = "power9";
4102 #ifndef HAVE_AS_POWER8
4103 case PROCESSOR_POWER8:
4104 unavailable_cpu = "power8";
4107 #ifndef HAVE_AS_POPCNTD
4108 case PROCESSOR_POWER7:
4109 unavailable_cpu = "power7";
4113 case PROCESSOR_POWER6:
4114 unavailable_cpu = "power6";
4117 #ifndef HAVE_AS_POPCNTB
4118 case PROCESSOR_POWER5:
4119 unavailable_cpu = "power5";
4125 if (unavailable_cpu)
4128 warning (0, "will not generate %qs instructions because "
4129 "assembler lacks %qs support", unavailable_cpu,
4134 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4135 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4136 with those from the cpu, except for options that were explicitly set. If
4137 we don't have a cpu, do not override the target bits set in
4141 rs6000_cpu_index = cpu_index;
4142 rs6000_isa_flags &= ~set_masks;
4143 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4148 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4149 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4150 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4151 to using rs6000_isa_flags, we need to do the initialization here.
4153 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4154 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4155 HOST_WIDE_INT flags;
4157 flags = TARGET_DEFAULT;
4160 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4161 const char *default_cpu = (!TARGET_POWERPC64
4166 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4167 flags = processor_target_table[default_cpu_index].target_enable;
4169 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4172 if (rs6000_tune_index >= 0)
4173 tune_index = rs6000_tune_index;
4174 else if (cpu_index >= 0)
4175 rs6000_tune_index = tune_index = cpu_index;
4179 enum processor_type tune_proc
4180 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4183 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4184 if (processor_target_table[i].processor == tune_proc)
4192 rs6000_cpu = processor_target_table[cpu_index].processor;
4194 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4196 gcc_assert (tune_index >= 0);
4197 rs6000_tune = processor_target_table[tune_index].processor;
4199 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4200 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4201 || rs6000_cpu == PROCESSOR_PPCE5500)
4204 error ("AltiVec not supported in this target");
4207 /* If we are optimizing big endian systems for space, use the load/store
4208 multiple instructions. */
4209 if (BYTES_BIG_ENDIAN && optimize_size)
4210 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
4212 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
4213 because the hardware doesn't support the instructions used in little
4214 endian mode, and causes an alignment trap. The 750 does not cause an
4215 alignment trap (except when the target is unaligned). */
4217 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
4219 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4220 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4221 warning (0, "%qs is not supported on little endian systems",
4225 /* If little-endian, default to -mstrict-align on older processors.
4226 Testing for htm matches power8 and later. */
4227 if (!BYTES_BIG_ENDIAN
4228 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4229 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4231 if (!rs6000_fold_gimple)
4233 "gimple folding of rs6000 builtins has been disabled.\n");
4235 /* Add some warnings for VSX. */
4238 const char *msg = NULL;
4239 if (!TARGET_HARD_FLOAT)
4241 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4242 msg = N_("-mvsx requires hardware floating point");
4245 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4246 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4249 else if (TARGET_AVOID_XFORM > 0)
4250 msg = N_("-mvsx needs indexed addressing");
4251 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4252 & OPTION_MASK_ALTIVEC))
4254 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4255 msg = N_("-mvsx and -mno-altivec are incompatible");
4257 msg = N_("-mno-altivec disables vsx");
4263 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4264 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4268 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4269 the -mcpu setting to enable options that conflict. */
4270 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4271 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4272 | OPTION_MASK_ALTIVEC
4273 | OPTION_MASK_VSX)) != 0)
4274 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4275 | OPTION_MASK_DIRECT_MOVE)
4276 & ~rs6000_isa_flags_explicit);
4278 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4279 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4281 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4282 off all of the options that depend on those flags. */
4283 ignore_masks = rs6000_disable_incompatible_switches ();
4285 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4286 unless the user explicitly used the -mno-<option> to disable the code. */
4287 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4288 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4289 else if (TARGET_P9_MINMAX)
4293 if (cpu_index == PROCESSOR_POWER9)
4295 /* legacy behavior: allow -mcpu=power9 with certain
4296 capabilities explicitly disabled. */
4297 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4300 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4301 "for <xxx> less than power9", "-mcpu");
4303 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4304 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4305 & rs6000_isa_flags_explicit))
4306 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4307 were explicitly cleared. */
4308 error ("%qs incompatible with explicitly disabled options",
4311 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4313 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4314 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4315 else if (TARGET_VSX)
4316 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4317 else if (TARGET_POPCNTD)
4318 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4319 else if (TARGET_DFP)
4320 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4321 else if (TARGET_CMPB)
4322 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4323 else if (TARGET_FPRND)
4324 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4325 else if (TARGET_POPCNTB)
4326 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4327 else if (TARGET_ALTIVEC)
4328 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4330 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4332 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4333 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4334 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4337 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4339 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4340 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4341 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4344 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4346 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4347 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4348 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4351 if (TARGET_P8_VECTOR && !TARGET_VSX)
4353 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4354 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4355 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4356 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4358 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4359 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4360 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4364 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4366 rs6000_isa_flags |= OPTION_MASK_VSX;
4367 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4371 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4373 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4374 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4375 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4378 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4379 silently turn off quad memory mode. */
4380 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4382 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4383 warning (0, N_("-mquad-memory requires 64-bit mode"));
4385 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4386 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4388 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4389 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4392 /* Non-atomic quad memory load/store are disabled for little endian, since
4393 the words are reversed, but atomic operations can still be done by
4394 swapping the words. */
4395 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4397 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4398 warning (0, N_("-mquad-memory is not available in little endian "
4401 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4404 /* Assume if the user asked for normal quad memory instructions, they want
4405 the atomic versions as well, unless they explicity told us not to use quad
4406 word atomic instructions. */
4407 if (TARGET_QUAD_MEMORY
4408 && !TARGET_QUAD_MEMORY_ATOMIC
4409 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4410 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4412 /* If we can shrink-wrap the TOC register save separately, then use
4413 -msave-toc-indirect unless explicitly disabled. */
4414 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4415 && flag_shrink_wrap_separate
4416 && optimize_function_for_speed_p (cfun))
4417 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4419 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4420 generating power8 instructions. */
4421 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4422 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4423 & OPTION_MASK_P8_FUSION);
4425 /* Setting additional fusion flags turns on base fusion. */
4426 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4428 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4430 if (TARGET_P8_FUSION_SIGN)
4431 error ("%qs requires %qs", "-mpower8-fusion-sign",
4434 if (TARGET_TOC_FUSION)
4435 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4437 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4440 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4443 /* Power9 fusion is a superset over power8 fusion. */
4444 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4446 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4448 /* We prefer to not mention undocumented options in
4449 error messages. However, if users have managed to select
4450 power9-fusion without selecting power8-fusion, they
4451 already know about undocumented flags. */
4452 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4453 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4456 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4459 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4460 generating power9 instructions. */
4461 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4462 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4463 & OPTION_MASK_P9_FUSION);
4465 /* Power8 does not fuse sign extended loads with the addis. If we are
4466 optimizing at high levels for speed, convert a sign extended load into a
4467 zero extending load, and an explicit sign extension. */
4468 if (TARGET_P8_FUSION
4469 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4470 && optimize_function_for_speed_p (cfun)
4472 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4474 /* TOC fusion requires 64-bit and medium/large code model. */
4475 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4477 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4478 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4479 warning (0, N_("-mtoc-fusion requires 64-bit"));
4482 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4484 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4485 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4486 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4489 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4491 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4492 && (TARGET_CMODEL != CMODEL_SMALL)
4493 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4494 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4496 /* ISA 3.0 vector instructions include ISA 2.07. */
4497 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4499 /* We prefer to not mention undocumented options in
4500 error messages. However, if users have managed to select
4501 power9-vector without selecting power8-vector, they
4502 already know about undocumented flags. */
4503 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4504 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4505 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4506 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4508 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4509 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4510 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4514 /* OPTION_MASK_P9_VECTOR is explicit and
4515 OPTION_MASK_P8_VECTOR is not explicit. */
4516 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4517 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4521 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4522 support. If we only have ISA 2.06 support, and the user did not specify
4523 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4524 but we don't enable the full vectorization support */
4525 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4526 TARGET_ALLOW_MOVMISALIGN = 1;
4528 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4530 if (TARGET_ALLOW_MOVMISALIGN > 0
4531 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4532 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4534 TARGET_ALLOW_MOVMISALIGN = 0;
4537 /* Determine when unaligned vector accesses are permitted, and when
4538 they are preferred over masked Altivec loads. Note that if
4539 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4540 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4542 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4546 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4547 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4549 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4552 else if (!TARGET_ALLOW_MOVMISALIGN)
4554 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4555 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4556 "-mallow-movmisalign");
4558 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4562 /* Set long double size before the IEEE 128-bit tests. */
4563 if (!global_options_set.x_rs6000_long_double_type_size)
4565 if (main_target_opt != NULL
4566 && (main_target_opt->x_rs6000_long_double_type_size
4567 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4568 error ("target attribute or pragma changes long double size");
4570 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4573 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4574 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4575 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4576 those systems will not pick up this default. Warn if the user changes the
4577 default unless either the user used the -Wno-psabi option, or the compiler
4578 was built to enable multilibs to switch between the two long double
4580 if (!global_options_set.x_rs6000_ieeequad)
4581 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4583 else if (!TARGET_IEEEQUAD_MULTILIB
4584 && rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT
4585 && TARGET_LONG_DOUBLE_128)
4587 static bool warned_change_long_double;
4588 if (!warned_change_long_double)
4590 warned_change_long_double = true;
4591 if (TARGET_IEEEQUAD)
4592 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4594 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4598 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4599 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4600 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4601 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4602 the keyword as well as the type. */
4603 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4605 /* IEEE 128-bit floating point requires VSX support. */
4606 if (TARGET_FLOAT128_KEYWORD)
4610 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4611 error ("%qs requires VSX support", "-mfloat128");
4613 TARGET_FLOAT128_TYPE = 0;
4614 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4615 | OPTION_MASK_FLOAT128_HW);
4617 else if (!TARGET_FLOAT128_TYPE)
4619 TARGET_FLOAT128_TYPE = 1;
4620 warning (0, "The -mfloat128 option may not be fully supported");
4624 /* Enable the __float128 keyword under Linux by default. */
4625 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4626 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4627 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4629 /* If we have are supporting the float128 type and full ISA 3.0 support,
4630 enable -mfloat128-hardware by default. However, don't enable the
4631 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4632 because sometimes the compiler wants to put things in an integer
4633 container, and if we don't have __int128 support, it is impossible. */
4634 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4635 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4636 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4637 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4639 if (TARGET_FLOAT128_HW
4640 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4642 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4643 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4645 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4648 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4650 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4651 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4653 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4656 /* Print the options after updating the defaults. */
4657 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4658 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4660 /* E500mc does "better" if we inline more aggressively. Respect the
4661 user's opinion, though. */
4662 if (rs6000_block_move_inline_limit == 0
4663 && (rs6000_tune == PROCESSOR_PPCE500MC
4664 || rs6000_tune == PROCESSOR_PPCE500MC64
4665 || rs6000_tune == PROCESSOR_PPCE5500
4666 || rs6000_tune == PROCESSOR_PPCE6500))
4667 rs6000_block_move_inline_limit = 128;
4669 /* store_one_arg depends on expand_block_move to handle at least the
4670 size of reg_parm_stack_space. */
4671 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4672 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4676 /* If the appropriate debug option is enabled, replace the target hooks
4677 with debug versions that call the real version and then prints
4678 debugging information. */
4679 if (TARGET_DEBUG_COST)
4681 targetm.rtx_costs = rs6000_debug_rtx_costs;
4682 targetm.address_cost = rs6000_debug_address_cost;
4683 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4686 if (TARGET_DEBUG_ADDR)
4688 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4689 targetm.legitimize_address = rs6000_debug_legitimize_address;
4690 rs6000_secondary_reload_class_ptr
4691 = rs6000_debug_secondary_reload_class;
4692 targetm.secondary_memory_needed
4693 = rs6000_debug_secondary_memory_needed;
4694 targetm.can_change_mode_class
4695 = rs6000_debug_can_change_mode_class;
4696 rs6000_preferred_reload_class_ptr
4697 = rs6000_debug_preferred_reload_class;
4698 rs6000_legitimize_reload_address_ptr
4699 = rs6000_debug_legitimize_reload_address;
4700 rs6000_mode_dependent_address_ptr
4701 = rs6000_debug_mode_dependent_address;
4704 if (rs6000_veclibabi_name)
4706 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4707 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4710 error ("unknown vectorization library ABI type (%qs) for "
4711 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4717 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4718 target attribute or pragma which automatically enables both options,
4719 unless the altivec ABI was set. This is set by default for 64-bit, but
4721 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4723 TARGET_FLOAT128_TYPE = 0;
4724 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4725 | OPTION_MASK_FLOAT128_KEYWORD)
4726 & ~rs6000_isa_flags_explicit);
4729 /* Enable Altivec ABI for AIX -maltivec. */
4730 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4732 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4733 error ("target attribute or pragma changes AltiVec ABI");
4735 rs6000_altivec_abi = 1;
4738 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4739 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4740 be explicitly overridden in either case. */
4743 if (!global_options_set.x_rs6000_altivec_abi
4744 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4746 if (main_target_opt != NULL &&
4747 !main_target_opt->x_rs6000_altivec_abi)
4748 error ("target attribute or pragma changes AltiVec ABI");
4750 rs6000_altivec_abi = 1;
4754 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4755 So far, the only darwin64 targets are also MACH-O. */
4757 && DEFAULT_ABI == ABI_DARWIN
4760 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4761 error ("target attribute or pragma changes darwin64 ABI");
4764 rs6000_darwin64_abi = 1;
4765 /* Default to natural alignment, for better performance. */
4766 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4770 /* Place FP constants in the constant pool instead of TOC
4771 if section anchors enabled. */
4772 if (flag_section_anchors
4773 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4774 TARGET_NO_FP_IN_TOC = 1;
4776 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4777 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4779 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4780 SUBTARGET_OVERRIDE_OPTIONS;
4782 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4783 SUBSUBTARGET_OVERRIDE_OPTIONS;
4785 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4786 SUB3TARGET_OVERRIDE_OPTIONS;
4789 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4790 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4792 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4793 && rs6000_tune != PROCESSOR_POWER5
4794 && rs6000_tune != PROCESSOR_POWER6
4795 && rs6000_tune != PROCESSOR_POWER7
4796 && rs6000_tune != PROCESSOR_POWER8
4797 && rs6000_tune != PROCESSOR_POWER9
4798 && rs6000_tune != PROCESSOR_PPCA2
4799 && rs6000_tune != PROCESSOR_CELL
4800 && rs6000_tune != PROCESSOR_PPC476);
4801 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4802 || rs6000_tune == PROCESSOR_POWER5
4803 || rs6000_tune == PROCESSOR_POWER7
4804 || rs6000_tune == PROCESSOR_POWER8);
4805 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4806 || rs6000_tune == PROCESSOR_POWER5
4807 || rs6000_tune == PROCESSOR_POWER6
4808 || rs6000_tune == PROCESSOR_POWER7
4809 || rs6000_tune == PROCESSOR_POWER8
4810 || rs6000_tune == PROCESSOR_POWER9
4811 || rs6000_tune == PROCESSOR_PPCE500MC
4812 || rs6000_tune == PROCESSOR_PPCE500MC64
4813 || rs6000_tune == PROCESSOR_PPCE5500
4814 || rs6000_tune == PROCESSOR_PPCE6500);
4816 /* Allow debug switches to override the above settings. These are set to -1
4817 in rs6000.opt to indicate the user hasn't directly set the switch. */
4818 if (TARGET_ALWAYS_HINT >= 0)
4819 rs6000_always_hint = TARGET_ALWAYS_HINT;
4821 if (TARGET_SCHED_GROUPS >= 0)
4822 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4824 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4825 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4827 rs6000_sched_restricted_insns_priority
4828 = (rs6000_sched_groups ? 1 : 0);
4830 /* Handle -msched-costly-dep option. */
4831 rs6000_sched_costly_dep
4832 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4834 if (rs6000_sched_costly_dep_str)
4836 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4837 rs6000_sched_costly_dep = no_dep_costly;
4838 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4839 rs6000_sched_costly_dep = all_deps_costly;
4840 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4841 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4842 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4843 rs6000_sched_costly_dep = store_to_load_dep_costly;
4845 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4846 atoi (rs6000_sched_costly_dep_str));
4849 /* Handle -minsert-sched-nops option. */
4850 rs6000_sched_insert_nops
4851 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4853 if (rs6000_sched_insert_nops_str)
4855 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4856 rs6000_sched_insert_nops = sched_finish_none;
4857 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4858 rs6000_sched_insert_nops = sched_finish_pad_groups;
4859 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4860 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4862 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4863 atoi (rs6000_sched_insert_nops_str));
4866 /* Handle stack protector */
4867 if (!global_options_set.x_rs6000_stack_protector_guard)
4868 #ifdef TARGET_THREAD_SSP_OFFSET
4869 rs6000_stack_protector_guard = SSP_TLS;
4871 rs6000_stack_protector_guard = SSP_GLOBAL;
4874 #ifdef TARGET_THREAD_SSP_OFFSET
4875 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4876 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4879 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4882 const char *str = rs6000_stack_protector_guard_offset_str;
4885 long offset = strtol (str, &endp, 0);
4886 if (!*str || *endp || errno)
4887 error ("%qs is not a valid number in %qs", str,
4888 "-mstack-protector-guard-offset=");
4890 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4891 || (TARGET_64BIT && (offset & 3)))
4892 error ("%qs is not a valid offset in %qs", str,
4893 "-mstack-protector-guard-offset=");
4895 rs6000_stack_protector_guard_offset = offset;
4898 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4900 const char *str = rs6000_stack_protector_guard_reg_str;
4901 int reg = decode_reg_name (str);
4903 if (!IN_RANGE (reg, 1, 31))
4904 error ("%qs is not a valid base register in %qs", str,
4905 "-mstack-protector-guard-reg=");
4907 rs6000_stack_protector_guard_reg = reg;
4910 if (rs6000_stack_protector_guard == SSP_TLS
4911 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4912 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4916 #ifdef TARGET_REGNAMES
4917 /* If the user desires alternate register names, copy in the
4918 alternate names now. */
4919 if (TARGET_REGNAMES)
4920 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4923 /* Set aix_struct_return last, after the ABI is determined.
4924 If -maix-struct-return or -msvr4-struct-return was explicitly
4925 used, don't override with the ABI default. */
4926 if (!global_options_set.x_aix_struct_return)
4927 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4930 /* IBM XL compiler defaults to unsigned bitfields. */
4931 if (TARGET_XL_COMPAT)
4932 flag_signed_bitfields = 0;
4935 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4936 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4938 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4940 /* We can only guarantee the availability of DI pseudo-ops when
4941 assembling for 64-bit targets. */
4944 targetm.asm_out.aligned_op.di = NULL;
4945 targetm.asm_out.unaligned_op.di = NULL;
4949 /* Set branch target alignment, if not optimizing for size. */
4952 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4953 aligned 8byte to avoid misprediction by the branch predictor. */
4954 if (rs6000_tune == PROCESSOR_TITAN
4955 || rs6000_tune == PROCESSOR_CELL)
4957 if (align_functions <= 0)
4958 align_functions = 8;
4959 if (align_jumps <= 0)
4961 if (align_loops <= 0)
4964 if (rs6000_align_branch_targets)
4966 if (align_functions <= 0)
4967 align_functions = 16;
4968 if (align_jumps <= 0)
4970 if (align_loops <= 0)
4972 can_override_loop_align = 1;
4976 if (align_jumps_max_skip <= 0)
4977 align_jumps_max_skip = 15;
4978 if (align_loops_max_skip <= 0)
4979 align_loops_max_skip = 15;
4982 /* Arrange to save and restore machine status around nested functions. */
4983 init_machine_status = rs6000_init_machine_status;
4985 /* We should always be splitting complex arguments, but we can't break
4986 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4987 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4988 targetm.calls.split_complex_arg = NULL;
4990 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4991 if (DEFAULT_ABI == ABI_AIX)
4992 targetm.calls.custom_function_descriptors = 0;
4995 /* Initialize rs6000_cost with the appropriate target costs. */
4997 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4999 switch (rs6000_tune)
5001 case PROCESSOR_RS64A:
5002 rs6000_cost = &rs64a_cost;
5005 case PROCESSOR_MPCCORE:
5006 rs6000_cost = &mpccore_cost;
5009 case PROCESSOR_PPC403:
5010 rs6000_cost = &ppc403_cost;
5013 case PROCESSOR_PPC405:
5014 rs6000_cost = &ppc405_cost;
5017 case PROCESSOR_PPC440:
5018 rs6000_cost = &ppc440_cost;
5021 case PROCESSOR_PPC476:
5022 rs6000_cost = &ppc476_cost;
5025 case PROCESSOR_PPC601:
5026 rs6000_cost = &ppc601_cost;
5029 case PROCESSOR_PPC603:
5030 rs6000_cost = &ppc603_cost;
5033 case PROCESSOR_PPC604:
5034 rs6000_cost = &ppc604_cost;
5037 case PROCESSOR_PPC604e:
5038 rs6000_cost = &ppc604e_cost;
5041 case PROCESSOR_PPC620:
5042 rs6000_cost = &ppc620_cost;
5045 case PROCESSOR_PPC630:
5046 rs6000_cost = &ppc630_cost;
5049 case PROCESSOR_CELL:
5050 rs6000_cost = &ppccell_cost;
5053 case PROCESSOR_PPC750:
5054 case PROCESSOR_PPC7400:
5055 rs6000_cost = &ppc750_cost;
5058 case PROCESSOR_PPC7450:
5059 rs6000_cost = &ppc7450_cost;
5062 case PROCESSOR_PPC8540:
5063 case PROCESSOR_PPC8548:
5064 rs6000_cost = &ppc8540_cost;
5067 case PROCESSOR_PPCE300C2:
5068 case PROCESSOR_PPCE300C3:
5069 rs6000_cost = &ppce300c2c3_cost;
5072 case PROCESSOR_PPCE500MC:
5073 rs6000_cost = &ppce500mc_cost;
5076 case PROCESSOR_PPCE500MC64:
5077 rs6000_cost = &ppce500mc64_cost;
5080 case PROCESSOR_PPCE5500:
5081 rs6000_cost = &ppce5500_cost;
5084 case PROCESSOR_PPCE6500:
5085 rs6000_cost = &ppce6500_cost;
5088 case PROCESSOR_TITAN:
5089 rs6000_cost = &titan_cost;
5092 case PROCESSOR_POWER4:
5093 case PROCESSOR_POWER5:
5094 rs6000_cost = &power4_cost;
5097 case PROCESSOR_POWER6:
5098 rs6000_cost = &power6_cost;
5101 case PROCESSOR_POWER7:
5102 rs6000_cost = &power7_cost;
5105 case PROCESSOR_POWER8:
5106 rs6000_cost = &power8_cost;
5109 case PROCESSOR_POWER9:
5110 rs6000_cost = &power9_cost;
5113 case PROCESSOR_PPCA2:
5114 rs6000_cost = &ppca2_cost;
5123 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5124 rs6000_cost->simultaneous_prefetches,
5125 global_options.x_param_values,
5126 global_options_set.x_param_values);
5127 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5128 global_options.x_param_values,
5129 global_options_set.x_param_values);
5130 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5131 rs6000_cost->cache_line_size,
5132 global_options.x_param_values,
5133 global_options_set.x_param_values);
5134 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5135 global_options.x_param_values,
5136 global_options_set.x_param_values);
5138 /* Increase loop peeling limits based on performance analysis. */
5139 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5140 global_options.x_param_values,
5141 global_options_set.x_param_values);
5142 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5143 global_options.x_param_values,
5144 global_options_set.x_param_values);
5146 /* Use the 'model' -fsched-pressure algorithm by default. */
5147 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5148 SCHED_PRESSURE_MODEL,
5149 global_options.x_param_values,
5150 global_options_set.x_param_values);
5152 /* If using typedef char *va_list, signal that
5153 __builtin_va_start (&ap, 0) can be optimized to
5154 ap = __builtin_next_arg (0). */
5155 if (DEFAULT_ABI != ABI_V4)
5156 targetm.expand_builtin_va_start = NULL;
5159 /* If not explicitly specified via option, decide whether to generate indexed
5160 load/store instructions. A value of -1 indicates that the
5161 initial value of this variable has not been overwritten. During
5162 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5163 if (TARGET_AVOID_XFORM == -1)
5164 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5165 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5166 need indexed accesses and the type used is the scalar type of the element
5167 being loaded or stored. */
5168 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5169 && !TARGET_ALTIVEC);
5171 /* Set the -mrecip options. */
5172 if (rs6000_recip_name)
5174 char *p = ASTRDUP (rs6000_recip_name);
5176 unsigned int mask, i;
5179 while ((q = strtok (p, ",")) != NULL)
5190 if (!strcmp (q, "default"))
5191 mask = ((TARGET_RECIP_PRECISION)
5192 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5195 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5196 if (!strcmp (q, recip_options[i].string))
5198 mask = recip_options[i].mask;
5202 if (i == ARRAY_SIZE (recip_options))
5204 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5212 rs6000_recip_control &= ~mask;
5214 rs6000_recip_control |= mask;
5218 /* Set the builtin mask of the various options used that could affect which
5219 builtins were used. In the past we used target_flags, but we've run out
5220 of bits, and some options are no longer in target_flags. */
5221 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5222 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5223 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5224 rs6000_builtin_mask);
5226 /* Initialize all of the registers. */
5227 rs6000_init_hard_regno_mode_ok (global_init_p);
5229 /* Save the initial options in case the user does function specific options */
5231 target_option_default_node = target_option_current_node
5232 = build_target_option_node (&global_options);
5234 /* If not explicitly specified via option, decide whether to generate the
5235 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5236 if (TARGET_LINK_STACK == -1)
5237 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5239 /* Deprecate use of -mno-speculate-indirect-jumps. */
5240 if (!rs6000_speculate_indirect_jumps)
5241 warning (0, "%qs is deprecated and not recommended in any circumstances",
5242 "-mno-speculate-indirect-jumps");
5247 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5248 define the target cpu type. */
5251 rs6000_option_override (void)
5253 (void) rs6000_option_override_internal (true);
5257 /* Implement targetm.vectorize.builtin_mask_for_load. */
5259 rs6000_builtin_mask_for_load (void)
5261 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5262 if ((TARGET_ALTIVEC && !TARGET_VSX)
5263 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5264 return altivec_builtin_mask_for_load;
5269 /* Implement LOOP_ALIGN. */
5271 rs6000_loop_align (rtx label)
5276 /* Don't override loop alignment if -falign-loops was specified. */
5277 if (!can_override_loop_align)
5278 return align_loops_log;
5280 bb = BLOCK_FOR_INSN (label);
5281 ninsns = num_loop_insns(bb->loop_father);
5283 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5284 if (ninsns > 4 && ninsns <= 8
5285 && (rs6000_tune == PROCESSOR_POWER4
5286 || rs6000_tune == PROCESSOR_POWER5
5287 || rs6000_tune == PROCESSOR_POWER6
5288 || rs6000_tune == PROCESSOR_POWER7
5289 || rs6000_tune == PROCESSOR_POWER8))
5292 return align_loops_log;
5295 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5297 rs6000_loop_align_max_skip (rtx_insn *label)
5299 return (1 << rs6000_loop_align (label)) - 1;
5302 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5303 after applying N number of iterations. This routine does not determine
5304 how may iterations are required to reach desired alignment. */
5307 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5314 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5317 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5327 /* Assuming that all other types are naturally aligned. CHECKME! */
5332 /* Return true if the vector misalignment factor is supported by the
5335 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5342 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5345 /* Return if movmisalign pattern is not supported for this mode. */
5346 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5349 if (misalignment == -1)
5351 /* Misalignment factor is unknown at compile time but we know
5352 it's word aligned. */
5353 if (rs6000_vector_alignment_reachable (type, is_packed))
5355 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5357 if (element_size == 64 || element_size == 32)
5364 /* VSX supports word-aligned vector. */
5365 if (misalignment % 4 == 0)
5371 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5373 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5374 tree vectype, int misalign)
5379 switch (type_of_cost)
5389 case cond_branch_not_taken:
5398 case vec_promote_demote:
5404 case cond_branch_taken:
5407 case unaligned_load:
5408 case vector_gather_load:
5409 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5412 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5414 elements = TYPE_VECTOR_SUBPARTS (vectype);
5416 /* Double word aligned. */
5424 /* Double word aligned. */
5428 /* Unknown misalignment. */
5441 /* Misaligned loads are not supported. */
5446 case unaligned_store:
5447 case vector_scatter_store:
5448 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5451 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5453 elements = TYPE_VECTOR_SUBPARTS (vectype);
5455 /* Double word aligned. */
5463 /* Double word aligned. */
5467 /* Unknown misalignment. */
5480 /* Misaligned stores are not supported. */
5486 /* This is a rough approximation assuming non-constant elements
5487 constructed into a vector via element insertion. FIXME:
5488 vec_construct is not granular enough for uniformly good
5489 decisions. If the initialization is a splat, this is
5490 cheaper than we estimate. Improve this someday. */
5491 elem_type = TREE_TYPE (vectype);
5492 /* 32-bit vectors loaded into registers are stored as double
5493 precision, so we need 2 permutes, 2 converts, and 1 merge
5494 to construct a vector of short floats from them. */
5495 if (SCALAR_FLOAT_TYPE_P (elem_type)
5496 && TYPE_PRECISION (elem_type) == 32)
5498 /* On POWER9, integer vector types are built up in GPRs and then
5499 use a direct move (2 cycles). For POWER8 this is even worse,
5500 as we need two direct moves and a merge, and the direct moves
5502 else if (INTEGRAL_TYPE_P (elem_type))
5504 if (TARGET_P9_VECTOR)
5505 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5507 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5510 /* V2DFmode doesn't need a direct move. */
5518 /* Implement targetm.vectorize.preferred_simd_mode. */
5521 rs6000_preferred_simd_mode (scalar_mode mode)
5530 if (TARGET_ALTIVEC || TARGET_VSX)
5550 typedef struct _rs6000_cost_data
5552 struct loop *loop_info;
5556 /* Test for likely overcommitment of vector hardware resources. If a
5557 loop iteration is relatively large, and too large a percentage of
5558 instructions in the loop are vectorized, the cost model may not
5559 adequately reflect delays from unavailable vector resources.
5560 Penalize the loop body cost for this case. */
5563 rs6000_density_test (rs6000_cost_data *data)
5565 const int DENSITY_PCT_THRESHOLD = 85;
5566 const int DENSITY_SIZE_THRESHOLD = 70;
5567 const int DENSITY_PENALTY = 10;
5568 struct loop *loop = data->loop_info;
5569 basic_block *bbs = get_loop_body (loop);
5570 int nbbs = loop->num_nodes;
5571 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5574 for (i = 0; i < nbbs; i++)
5576 basic_block bb = bbs[i];
5577 gimple_stmt_iterator gsi;
5579 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5581 gimple *stmt = gsi_stmt (gsi);
5582 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5584 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5585 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5591 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5593 if (density_pct > DENSITY_PCT_THRESHOLD
5594 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5596 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5597 if (dump_enabled_p ())
5598 dump_printf_loc (MSG_NOTE, vect_location,
5599 "density %d%%, cost %d exceeds threshold, penalizing "
5600 "loop body cost by %d%%", density_pct,
5601 vec_cost + not_vec_cost, DENSITY_PENALTY);
5605 /* Implement targetm.vectorize.init_cost. */
5607 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5608 instruction is needed by the vectorization. */
5609 static bool rs6000_vect_nonmem;
5612 rs6000_init_cost (struct loop *loop_info)
5614 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5615 data->loop_info = loop_info;
5616 data->cost[vect_prologue] = 0;
5617 data->cost[vect_body] = 0;
5618 data->cost[vect_epilogue] = 0;
5619 rs6000_vect_nonmem = false;
5623 /* Implement targetm.vectorize.add_stmt_cost. */
5626 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5627 struct _stmt_vec_info *stmt_info, int misalign,
5628 enum vect_cost_model_location where)
5630 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5631 unsigned retval = 0;
5633 if (flag_vect_cost_model)
5635 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5636 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5638 /* Statements in an inner loop relative to the loop being
5639 vectorized are weighted more heavily. The value here is
5640 arbitrary and could potentially be improved with analysis. */
5641 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5642 count *= 50; /* FIXME. */
5644 retval = (unsigned) (count * stmt_cost);
5645 cost_data->cost[where] += retval;
5647 /* Check whether we're doing something other than just a copy loop.
5648 Not all such loops may be profitably vectorized; see
5649 rs6000_finish_cost. */
5650 if ((kind == vec_to_scalar || kind == vec_perm
5651 || kind == vec_promote_demote || kind == vec_construct
5652 || kind == scalar_to_vec)
5653 || (where == vect_body && kind == vector_stmt))
5654 rs6000_vect_nonmem = true;
5660 /* Implement targetm.vectorize.finish_cost. */
5663 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5664 unsigned *body_cost, unsigned *epilogue_cost)
5666 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5668 if (cost_data->loop_info)
5669 rs6000_density_test (cost_data);
5671 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5672 that require versioning for any reason. The vectorization is at
5673 best a wash inside the loop, and the versioning checks make
5674 profitability highly unlikely and potentially quite harmful. */
5675 if (cost_data->loop_info)
5677 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5678 if (!rs6000_vect_nonmem
5679 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5680 && LOOP_REQUIRES_VERSIONING (vec_info))
5681 cost_data->cost[vect_body] += 10000;
5684 *prologue_cost = cost_data->cost[vect_prologue];
5685 *body_cost = cost_data->cost[vect_body];
5686 *epilogue_cost = cost_data->cost[vect_epilogue];
5689 /* Implement targetm.vectorize.destroy_cost_data. */
5692 rs6000_destroy_cost_data (void *data)
5697 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5698 library with vectorized intrinsics. */
5701 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5705 const char *suffix = NULL;
5706 tree fntype, new_fndecl, bdecl = NULL_TREE;
5709 machine_mode el_mode, in_mode;
5712 /* Libmass is suitable for unsafe math only as it does not correctly support
5713 parts of IEEE with the required precision such as denormals. Only support
5714 it if we have VSX to use the simd d2 or f4 functions.
5715 XXX: Add variable length support. */
5716 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5719 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5720 n = TYPE_VECTOR_SUBPARTS (type_out);
5721 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5722 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5723 if (el_mode != in_mode
5759 if (el_mode == DFmode && n == 2)
5761 bdecl = mathfn_built_in (double_type_node, fn);
5762 suffix = "d2"; /* pow -> powd2 */
5764 else if (el_mode == SFmode && n == 4)
5766 bdecl = mathfn_built_in (float_type_node, fn);
5767 suffix = "4"; /* powf -> powf4 */
5779 gcc_assert (suffix != NULL);
5780 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5784 strcpy (name, bname + sizeof ("__builtin_") - 1);
5785 strcat (name, suffix);
5788 fntype = build_function_type_list (type_out, type_in, NULL);
5789 else if (n_args == 2)
5790 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5794 /* Build a function declaration for the vectorized function. */
5795 new_fndecl = build_decl (BUILTINS_LOCATION,
5796 FUNCTION_DECL, get_identifier (name), fntype);
5797 TREE_PUBLIC (new_fndecl) = 1;
5798 DECL_EXTERNAL (new_fndecl) = 1;
5799 DECL_IS_NOVOPS (new_fndecl) = 1;
5800 TREE_READONLY (new_fndecl) = 1;
5805 /* Returns a function decl for a vectorized version of the builtin function
5806 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5807 if it is not available. */
5810 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5813 machine_mode in_mode, out_mode;
5816 if (TARGET_DEBUG_BUILTIN)
5817 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5818 combined_fn_name (combined_fn (fn)),
5819 GET_MODE_NAME (TYPE_MODE (type_out)),
5820 GET_MODE_NAME (TYPE_MODE (type_in)));
5822 if (TREE_CODE (type_out) != VECTOR_TYPE
5823 || TREE_CODE (type_in) != VECTOR_TYPE)
5826 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5827 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5828 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5829 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5834 if (VECTOR_UNIT_VSX_P (V2DFmode)
5835 && out_mode == DFmode && out_n == 2
5836 && in_mode == DFmode && in_n == 2)
5837 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5838 if (VECTOR_UNIT_VSX_P (V4SFmode)
5839 && out_mode == SFmode && out_n == 4
5840 && in_mode == SFmode && in_n == 4)
5841 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5842 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5843 && out_mode == SFmode && out_n == 4
5844 && in_mode == SFmode && in_n == 4)
5845 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5848 if (VECTOR_UNIT_VSX_P (V2DFmode)
5849 && out_mode == DFmode && out_n == 2
5850 && in_mode == DFmode && in_n == 2)
5851 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5852 if (VECTOR_UNIT_VSX_P (V4SFmode)
5853 && out_mode == SFmode && out_n == 4
5854 && in_mode == SFmode && in_n == 4)
5855 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5856 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5857 && out_mode == SFmode && out_n == 4
5858 && in_mode == SFmode && in_n == 4)
5859 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5862 if (VECTOR_UNIT_VSX_P (V2DFmode)
5863 && out_mode == DFmode && out_n == 2
5864 && in_mode == DFmode && in_n == 2)
5865 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5866 if (VECTOR_UNIT_VSX_P (V4SFmode)
5867 && out_mode == SFmode && out_n == 4
5868 && in_mode == SFmode && in_n == 4)
5869 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5870 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5871 && out_mode == SFmode && out_n == 4
5872 && in_mode == SFmode && in_n == 4)
5873 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5876 if (VECTOR_UNIT_VSX_P (V2DFmode)
5877 && out_mode == DFmode && out_n == 2
5878 && in_mode == DFmode && in_n == 2)
5879 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5880 if (VECTOR_UNIT_VSX_P (V4SFmode)
5881 && out_mode == SFmode && out_n == 4
5882 && in_mode == SFmode && in_n == 4)
5883 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5884 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5885 && out_mode == SFmode && out_n == 4
5886 && in_mode == SFmode && in_n == 4)
5887 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5890 if (VECTOR_UNIT_VSX_P (V2DFmode)
5891 && out_mode == DFmode && out_n == 2
5892 && in_mode == DFmode && in_n == 2)
5893 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5894 if (VECTOR_UNIT_VSX_P (V4SFmode)
5895 && out_mode == SFmode && out_n == 4
5896 && in_mode == SFmode && in_n == 4)
5897 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5898 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5899 && out_mode == SFmode && out_n == 4
5900 && in_mode == SFmode && in_n == 4)
5901 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5904 if (VECTOR_UNIT_VSX_P (V2DFmode)
5905 && flag_unsafe_math_optimizations
5906 && out_mode == DFmode && out_n == 2
5907 && in_mode == DFmode && in_n == 2)
5908 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5909 if (VECTOR_UNIT_VSX_P (V4SFmode)
5910 && flag_unsafe_math_optimizations
5911 && out_mode == SFmode && out_n == 4
5912 && in_mode == SFmode && in_n == 4)
5913 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5916 if (VECTOR_UNIT_VSX_P (V2DFmode)
5917 && !flag_trapping_math
5918 && out_mode == DFmode && out_n == 2
5919 && in_mode == DFmode && in_n == 2)
5920 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5921 if (VECTOR_UNIT_VSX_P (V4SFmode)
5922 && !flag_trapping_math
5923 && out_mode == SFmode && out_n == 4
5924 && in_mode == SFmode && in_n == 4)
5925 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5931 /* Generate calls to libmass if appropriate. */
5932 if (rs6000_veclib_handler)
5933 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5938 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5941 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5944 machine_mode in_mode, out_mode;
5947 if (TARGET_DEBUG_BUILTIN)
5948 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5949 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5950 GET_MODE_NAME (TYPE_MODE (type_out)),
5951 GET_MODE_NAME (TYPE_MODE (type_in)));
5953 if (TREE_CODE (type_out) != VECTOR_TYPE
5954 || TREE_CODE (type_in) != VECTOR_TYPE)
5957 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5958 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5959 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5960 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5962 enum rs6000_builtins fn
5963 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5966 case RS6000_BUILTIN_RSQRTF:
5967 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5968 && out_mode == SFmode && out_n == 4
5969 && in_mode == SFmode && in_n == 4)
5970 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5972 case RS6000_BUILTIN_RSQRT:
5973 if (VECTOR_UNIT_VSX_P (V2DFmode)
5974 && out_mode == DFmode && out_n == 2
5975 && in_mode == DFmode && in_n == 2)
5976 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5978 case RS6000_BUILTIN_RECIPF:
5979 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5980 && out_mode == SFmode && out_n == 4
5981 && in_mode == SFmode && in_n == 4)
5982 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5984 case RS6000_BUILTIN_RECIP:
5985 if (VECTOR_UNIT_VSX_P (V2DFmode)
5986 && out_mode == DFmode && out_n == 2
5987 && in_mode == DFmode && in_n == 2)
5988 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5996 /* Default CPU string for rs6000*_file_start functions. */
5997 static const char *rs6000_default_cpu;
5999 /* Do anything needed at the start of the asm file. */
6002 rs6000_file_start (void)
6005 const char *start = buffer;
6006 FILE *file = asm_out_file;
6008 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6010 default_file_start ();
6012 if (flag_verbose_asm)
6014 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6016 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6018 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6022 if (global_options_set.x_rs6000_cpu_index)
6024 fprintf (file, "%s -mcpu=%s", start,
6025 processor_target_table[rs6000_cpu_index].name);
6029 if (global_options_set.x_rs6000_tune_index)
6031 fprintf (file, "%s -mtune=%s", start,
6032 processor_target_table[rs6000_tune_index].name);
6036 if (PPC405_ERRATUM77)
6038 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6042 #ifdef USING_ELFOS_H
6043 switch (rs6000_sdata)
6045 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6046 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6047 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6048 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6051 if (rs6000_sdata && g_switch_value)
6053 fprintf (file, "%s -G %d", start,
6063 #ifdef USING_ELFOS_H
6064 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6065 && !global_options_set.x_rs6000_cpu_index)
6067 fputs ("\t.machine ", asm_out_file);
6068 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6069 fputs ("power9\n", asm_out_file);
6070 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6071 fputs ("power8\n", asm_out_file);
6072 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6073 fputs ("power7\n", asm_out_file);
6074 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6075 fputs ("power6\n", asm_out_file);
6076 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6077 fputs ("power5\n", asm_out_file);
6078 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6079 fputs ("power4\n", asm_out_file);
6080 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6081 fputs ("ppc64\n", asm_out_file);
6083 fputs ("ppc\n", asm_out_file);
6087 if (DEFAULT_ABI == ABI_ELFv2)
6088 fprintf (file, "\t.abiversion 2\n");
6092 /* Return nonzero if this function is known to have a null epilogue. */
6095 direct_return (void)
6097 if (reload_completed)
6099 rs6000_stack_t *info = rs6000_stack_info ();
6101 if (info->first_gp_reg_save == 32
6102 && info->first_fp_reg_save == 64
6103 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6104 && ! info->lr_save_p
6105 && ! info->cr_save_p
6106 && info->vrsave_size == 0
6114 /* Return the number of instructions it takes to form a constant in an
6115 integer register. */
6118 num_insns_constant_wide (HOST_WIDE_INT value)
6120 /* signed constant loadable with addi */
6121 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6124 /* constant loadable with addis */
6125 else if ((value & 0xffff) == 0
6126 && (value >> 31 == -1 || value >> 31 == 0))
6129 else if (TARGET_POWERPC64)
6131 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6132 HOST_WIDE_INT high = value >> 31;
6134 if (high == 0 || high == -1)
6140 return num_insns_constant_wide (high) + 1;
6142 return num_insns_constant_wide (low) + 1;
6144 return (num_insns_constant_wide (high)
6145 + num_insns_constant_wide (low) + 1);
6153 num_insns_constant (rtx op, machine_mode mode)
6155 HOST_WIDE_INT low, high;
6157 switch (GET_CODE (op))
6160 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6161 && rs6000_is_valid_and_mask (op, mode))
6164 return num_insns_constant_wide (INTVAL (op));
6166 case CONST_WIDE_INT:
6169 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6170 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6171 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6176 if (mode == SFmode || mode == SDmode)
6180 if (DECIMAL_FLOAT_MODE_P (mode))
6181 REAL_VALUE_TO_TARGET_DECIMAL32
6182 (*CONST_DOUBLE_REAL_VALUE (op), l);
6184 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6185 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6189 if (DECIMAL_FLOAT_MODE_P (mode))
6190 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6192 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6193 high = l[WORDS_BIG_ENDIAN == 0];
6194 low = l[WORDS_BIG_ENDIAN != 0];
6197 return (num_insns_constant_wide (low)
6198 + num_insns_constant_wide (high));
6201 if ((high == 0 && low >= 0)
6202 || (high == -1 && low < 0))
6203 return num_insns_constant_wide (low);
6205 else if (rs6000_is_valid_and_mask (op, mode))
6209 return num_insns_constant_wide (high) + 1;
6212 return (num_insns_constant_wide (high)
6213 + num_insns_constant_wide (low) + 1);
6221 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6222 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6223 corresponding element of the vector, but for V4SFmode, the
6224 corresponding "float" is interpreted as an SImode integer. */
6227 const_vector_elt_as_int (rtx op, unsigned int elt)
6231 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6232 gcc_assert (GET_MODE (op) != V2DImode
6233 && GET_MODE (op) != V2DFmode);
6235 tmp = CONST_VECTOR_ELT (op, elt);
6236 if (GET_MODE (op) == V4SFmode)
6237 tmp = gen_lowpart (SImode, tmp);
6238 return INTVAL (tmp);
6241 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6242 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6243 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6244 all items are set to the same value and contain COPIES replicas of the
6245 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6246 operand and the others are set to the value of the operand's msb. */
6249 vspltis_constant (rtx op, unsigned step, unsigned copies)
6251 machine_mode mode = GET_MODE (op);
6252 machine_mode inner = GET_MODE_INNER (mode);
6260 HOST_WIDE_INT splat_val;
6261 HOST_WIDE_INT msb_val;
6263 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6266 nunits = GET_MODE_NUNITS (mode);
6267 bitsize = GET_MODE_BITSIZE (inner);
6268 mask = GET_MODE_MASK (inner);
6270 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6272 msb_val = val >= 0 ? 0 : -1;
6274 /* Construct the value to be splatted, if possible. If not, return 0. */
6275 for (i = 2; i <= copies; i *= 2)
6277 HOST_WIDE_INT small_val;
6279 small_val = splat_val >> bitsize;
6281 if (splat_val != ((HOST_WIDE_INT)
6282 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6283 | (small_val & mask)))
6285 splat_val = small_val;
6288 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6289 if (EASY_VECTOR_15 (splat_val))
6292 /* Also check if we can splat, and then add the result to itself. Do so if
6293 the value is positive, of if the splat instruction is using OP's mode;
6294 for splat_val < 0, the splat and the add should use the same mode. */
6295 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6296 && (splat_val >= 0 || (step == 1 && copies == 1)))
6299 /* Also check if are loading up the most significant bit which can be done by
6300 loading up -1 and shifting the value left by -1. */
6301 else if (EASY_VECTOR_MSB (splat_val, inner))
6307 /* Check if VAL is present in every STEP-th element, and the
6308 other elements are filled with its most significant bit. */
6309 for (i = 1; i < nunits; ++i)
6311 HOST_WIDE_INT desired_val;
6312 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6313 if ((i & (step - 1)) == 0)
6316 desired_val = msb_val;
6318 if (desired_val != const_vector_elt_as_int (op, elt))
6325 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6326 instruction, filling in the bottom elements with 0 or -1.
6328 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6329 for the number of zeroes to shift in, or negative for the number of 0xff
6332 OP is a CONST_VECTOR. */
6335 vspltis_shifted (rtx op)
6337 machine_mode mode = GET_MODE (op);
6338 machine_mode inner = GET_MODE_INNER (mode);
6346 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6349 /* We need to create pseudo registers to do the shift, so don't recognize
6350 shift vector constants after reload. */
6351 if (!can_create_pseudo_p ())
6354 nunits = GET_MODE_NUNITS (mode);
6355 mask = GET_MODE_MASK (inner);
6357 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6359 /* Check if the value can really be the operand of a vspltis[bhw]. */
6360 if (EASY_VECTOR_15 (val))
6363 /* Also check if we are loading up the most significant bit which can be done
6364 by loading up -1 and shifting the value left by -1. */
6365 else if (EASY_VECTOR_MSB (val, inner))
6371 /* Check if VAL is present in every STEP-th element until we find elements
6372 that are 0 or all 1 bits. */
6373 for (i = 1; i < nunits; ++i)
6375 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6376 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6378 /* If the value isn't the splat value, check for the remaining elements
6384 for (j = i+1; j < nunits; ++j)
6386 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6387 if (const_vector_elt_as_int (op, elt2) != 0)
6391 return (nunits - i) * GET_MODE_SIZE (inner);
6394 else if ((elt_val & mask) == mask)
6396 for (j = i+1; j < nunits; ++j)
6398 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6399 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6403 return -((nunits - i) * GET_MODE_SIZE (inner));
6411 /* If all elements are equal, we don't need to do VLSDOI. */
6416 /* Return true if OP is of the given MODE and can be synthesized
6417 with a vspltisb, vspltish or vspltisw. */
6420 easy_altivec_constant (rtx op, machine_mode mode)
6422 unsigned step, copies;
6424 if (mode == VOIDmode)
6425 mode = GET_MODE (op);
6426 else if (mode != GET_MODE (op))
6429 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6431 if (mode == V2DFmode)
6432 return zero_constant (op, mode);
6434 else if (mode == V2DImode)
6436 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6437 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6440 if (zero_constant (op, mode))
6443 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6444 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6450 /* V1TImode is a special container for TImode. Ignore for now. */
6451 else if (mode == V1TImode)
6454 /* Start with a vspltisw. */
6455 step = GET_MODE_NUNITS (mode) / 4;
6458 if (vspltis_constant (op, step, copies))
6461 /* Then try with a vspltish. */
6467 if (vspltis_constant (op, step, copies))
6470 /* And finally a vspltisb. */
6476 if (vspltis_constant (op, step, copies))
6479 if (vspltis_shifted (op) != 0)
6485 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6486 result is OP. Abort if it is not possible. */
6489 gen_easy_altivec_constant (rtx op)
6491 machine_mode mode = GET_MODE (op);
6492 int nunits = GET_MODE_NUNITS (mode);
6493 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6494 unsigned step = nunits / 4;
6495 unsigned copies = 1;
6497 /* Start with a vspltisw. */
6498 if (vspltis_constant (op, step, copies))
6499 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6501 /* Then try with a vspltish. */
6507 if (vspltis_constant (op, step, copies))
6508 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6510 /* And finally a vspltisb. */
6516 if (vspltis_constant (op, step, copies))
6517 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6522 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6523 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6525 Return the number of instructions needed (1 or 2) into the address pointed
6528 Return the constant that is being split via CONSTANT_PTR. */
6531 xxspltib_constant_p (rtx op,
6536 size_t nunits = GET_MODE_NUNITS (mode);
6538 HOST_WIDE_INT value;
6541 /* Set the returned values to out of bound values. */
6542 *num_insns_ptr = -1;
6543 *constant_ptr = 256;
6545 if (!TARGET_P9_VECTOR)
6548 if (mode == VOIDmode)
6549 mode = GET_MODE (op);
6551 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6554 /* Handle (vec_duplicate <constant>). */
6555 if (GET_CODE (op) == VEC_DUPLICATE)
6557 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6558 && mode != V2DImode)
6561 element = XEXP (op, 0);
6562 if (!CONST_INT_P (element))
6565 value = INTVAL (element);
6566 if (!IN_RANGE (value, -128, 127))
6570 /* Handle (const_vector [...]). */
6571 else if (GET_CODE (op) == CONST_VECTOR)
6573 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6574 && mode != V2DImode)
6577 element = CONST_VECTOR_ELT (op, 0);
6578 if (!CONST_INT_P (element))
6581 value = INTVAL (element);
6582 if (!IN_RANGE (value, -128, 127))
6585 for (i = 1; i < nunits; i++)
6587 element = CONST_VECTOR_ELT (op, i);
6588 if (!CONST_INT_P (element))
6591 if (value != INTVAL (element))
6596 /* Handle integer constants being loaded into the upper part of the VSX
6597 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6598 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6599 else if (CONST_INT_P (op))
6601 if (!SCALAR_INT_MODE_P (mode))
6604 value = INTVAL (op);
6605 if (!IN_RANGE (value, -128, 127))
6608 if (!IN_RANGE (value, -1, 0))
6610 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6613 if (EASY_VECTOR_15 (value))
6621 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6622 sign extend. Special case 0/-1 to allow getting any VSX register instead
6623 of an Altivec register. */
6624 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6625 && EASY_VECTOR_15 (value))
6628 /* Return # of instructions and the constant byte for XXSPLTIB. */
6629 if (mode == V16QImode)
6632 else if (IN_RANGE (value, -1, 0))
6638 *constant_ptr = (int) value;
6643 output_vec_const_move (rtx *operands)
6651 mode = GET_MODE (dest);
6655 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6656 int xxspltib_value = 256;
6659 if (zero_constant (vec, mode))
6661 if (TARGET_P9_VECTOR)
6662 return "xxspltib %x0,0";
6664 else if (dest_vmx_p)
6665 return "vspltisw %0,0";
6668 return "xxlxor %x0,%x0,%x0";
6671 if (all_ones_constant (vec, mode))
6673 if (TARGET_P9_VECTOR)
6674 return "xxspltib %x0,255";
6676 else if (dest_vmx_p)
6677 return "vspltisw %0,-1";
6679 else if (TARGET_P8_VECTOR)
6680 return "xxlorc %x0,%x0,%x0";
6686 if (TARGET_P9_VECTOR
6687 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6691 operands[2] = GEN_INT (xxspltib_value & 0xff);
6692 return "xxspltib %x0,%2";
6703 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6704 if (zero_constant (vec, mode))
6705 return "vspltisw %0,0";
6707 if (all_ones_constant (vec, mode))
6708 return "vspltisw %0,-1";
6710 /* Do we need to construct a value using VSLDOI? */
6711 shift = vspltis_shifted (vec);
6715 splat_vec = gen_easy_altivec_constant (vec);
6716 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6717 operands[1] = XEXP (splat_vec, 0);
6718 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6721 switch (GET_MODE (splat_vec))
6724 return "vspltisw %0,%1";
6727 return "vspltish %0,%1";
6730 return "vspltisb %0,%1";
6740 /* Initialize vector TARGET to VALS. */
6743 rs6000_expand_vector_init (rtx target, rtx vals)
6745 machine_mode mode = GET_MODE (target);
6746 machine_mode inner_mode = GET_MODE_INNER (mode);
6747 int n_elts = GET_MODE_NUNITS (mode);
6748 int n_var = 0, one_var = -1;
6749 bool all_same = true, all_const_zero = true;
6753 for (i = 0; i < n_elts; ++i)
6755 x = XVECEXP (vals, 0, i);
6756 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6757 ++n_var, one_var = i;
6758 else if (x != CONST0_RTX (inner_mode))
6759 all_const_zero = false;
6761 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6767 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6768 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6769 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6771 /* Zero register. */
6772 emit_move_insn (target, CONST0_RTX (mode));
6775 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6777 /* Splat immediate. */
6778 emit_insn (gen_rtx_SET (target, const_vec));
6783 /* Load from constant pool. */
6784 emit_move_insn (target, const_vec);
6789 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6790 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6794 size_t num_elements = all_same ? 1 : 2;
6795 for (i = 0; i < num_elements; i++)
6797 op[i] = XVECEXP (vals, 0, i);
6798 /* Just in case there is a SUBREG with a smaller mode, do a
6800 if (GET_MODE (op[i]) != inner_mode)
6802 rtx tmp = gen_reg_rtx (inner_mode);
6803 convert_move (tmp, op[i], 0);
6806 /* Allow load with splat double word. */
6807 else if (MEM_P (op[i]))
6810 op[i] = force_reg (inner_mode, op[i]);
6812 else if (!REG_P (op[i]))
6813 op[i] = force_reg (inner_mode, op[i]);
6818 if (mode == V2DFmode)
6819 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6821 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6825 if (mode == V2DFmode)
6826 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6828 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6833 /* Special case initializing vector int if we are on 64-bit systems with
6834 direct move or we have the ISA 3.0 instructions. */
6835 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6836 && TARGET_DIRECT_MOVE_64BIT)
6840 rtx element0 = XVECEXP (vals, 0, 0);
6841 if (MEM_P (element0))
6842 element0 = rs6000_address_for_fpconvert (element0);
6844 element0 = force_reg (SImode, element0);
6846 if (TARGET_P9_VECTOR)
6847 emit_insn (gen_vsx_splat_v4si (target, element0));
6850 rtx tmp = gen_reg_rtx (DImode);
6851 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6852 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6861 for (i = 0; i < 4; i++)
6863 elements[i] = XVECEXP (vals, 0, i);
6864 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
6865 elements[i] = copy_to_mode_reg (SImode, elements[i]);
6868 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6869 elements[2], elements[3]));
6874 /* With single precision floating point on VSX, know that internally single
6875 precision is actually represented as a double, and either make 2 V2DF
6876 vectors, and convert these vectors to single precision, or do one
6877 conversion, and splat the result to the other elements. */
6878 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6882 rtx element0 = XVECEXP (vals, 0, 0);
6884 if (TARGET_P9_VECTOR)
6886 if (MEM_P (element0))
6887 element0 = rs6000_address_for_fpconvert (element0);
6889 emit_insn (gen_vsx_splat_v4sf (target, element0));
6894 rtx freg = gen_reg_rtx (V4SFmode);
6895 rtx sreg = force_reg (SFmode, element0);
6896 rtx cvt = (TARGET_XSCVDPSPN
6897 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6898 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6901 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6907 rtx dbl_even = gen_reg_rtx (V2DFmode);
6908 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6909 rtx flt_even = gen_reg_rtx (V4SFmode);
6910 rtx flt_odd = gen_reg_rtx (V4SFmode);
6911 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6912 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6913 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6914 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6916 /* Use VMRGEW if we can instead of doing a permute. */
6917 if (TARGET_P8_VECTOR)
6919 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6920 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6921 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6922 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6923 if (BYTES_BIG_ENDIAN)
6924 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6926 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6930 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6931 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6932 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6933 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6934 rs6000_expand_extract_even (target, flt_even, flt_odd);
6940 /* Special case initializing vector short/char that are splats if we are on
6941 64-bit systems with direct move. */
6942 if (all_same && TARGET_DIRECT_MOVE_64BIT
6943 && (mode == V16QImode || mode == V8HImode))
6945 rtx op0 = XVECEXP (vals, 0, 0);
6946 rtx di_tmp = gen_reg_rtx (DImode);
6949 op0 = force_reg (GET_MODE_INNER (mode), op0);
6951 if (mode == V16QImode)
6953 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6954 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6958 if (mode == V8HImode)
6960 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6961 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6966 /* Store value to stack temp. Load vector element. Splat. However, splat
6967 of 64-bit items is not supported on Altivec. */
6968 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6970 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6971 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6972 XVECEXP (vals, 0, 0));
6973 x = gen_rtx_UNSPEC (VOIDmode,
6974 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6975 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6977 gen_rtx_SET (target, mem),
6979 x = gen_rtx_VEC_SELECT (inner_mode, target,
6980 gen_rtx_PARALLEL (VOIDmode,
6981 gen_rtvec (1, const0_rtx)));
6982 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6986 /* One field is non-constant. Load constant then overwrite
6990 rtx copy = copy_rtx (vals);
6992 /* Load constant part of vector, substitute neighboring value for
6994 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6995 rs6000_expand_vector_init (target, copy);
6997 /* Insert variable. */
6998 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7002 /* Construct the vector in memory one field at a time
7003 and load the whole vector. */
7004 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7005 for (i = 0; i < n_elts; i++)
7006 emit_move_insn (adjust_address_nv (mem, inner_mode,
7007 i * GET_MODE_SIZE (inner_mode)),
7008 XVECEXP (vals, 0, i));
7009 emit_move_insn (target, mem);
7012 /* Set field ELT of TARGET to VAL. */
7015 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7017 machine_mode mode = GET_MODE (target);
7018 machine_mode inner_mode = GET_MODE_INNER (mode);
7019 rtx reg = gen_reg_rtx (mode);
7021 int width = GET_MODE_SIZE (inner_mode);
7024 val = force_reg (GET_MODE (val), val);
7026 if (VECTOR_MEM_VSX_P (mode))
7028 rtx insn = NULL_RTX;
7029 rtx elt_rtx = GEN_INT (elt);
7031 if (mode == V2DFmode)
7032 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7034 else if (mode == V2DImode)
7035 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7037 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7039 if (mode == V4SImode)
7040 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7041 else if (mode == V8HImode)
7042 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7043 else if (mode == V16QImode)
7044 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7045 else if (mode == V4SFmode)
7046 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7056 /* Simplify setting single element vectors like V1TImode. */
7057 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7059 emit_move_insn (target, gen_lowpart (mode, val));
7063 /* Load single variable value. */
7064 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7065 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7066 x = gen_rtx_UNSPEC (VOIDmode,
7067 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7068 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7070 gen_rtx_SET (reg, mem),
7073 /* Linear sequence. */
7074 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7075 for (i = 0; i < 16; ++i)
7076 XVECEXP (mask, 0, i) = GEN_INT (i);
7078 /* Set permute mask to insert element into target. */
7079 for (i = 0; i < width; ++i)
7080 XVECEXP (mask, 0, elt*width + i)
7081 = GEN_INT (i + 0x10);
7082 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7084 if (BYTES_BIG_ENDIAN)
7085 x = gen_rtx_UNSPEC (mode,
7086 gen_rtvec (3, target, reg,
7087 force_reg (V16QImode, x)),
7091 if (TARGET_P9_VECTOR)
7092 x = gen_rtx_UNSPEC (mode,
7093 gen_rtvec (3, reg, target,
7094 force_reg (V16QImode, x)),
7098 /* Invert selector. We prefer to generate VNAND on P8 so
7099 that future fusion opportunities can kick in, but must
7100 generate VNOR elsewhere. */
7101 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7102 rtx iorx = (TARGET_P8_VECTOR
7103 ? gen_rtx_IOR (V16QImode, notx, notx)
7104 : gen_rtx_AND (V16QImode, notx, notx));
7105 rtx tmp = gen_reg_rtx (V16QImode);
7106 emit_insn (gen_rtx_SET (tmp, iorx));
7108 /* Permute with operands reversed and adjusted selector. */
7109 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7114 emit_insn (gen_rtx_SET (target, x));
7117 /* Extract field ELT from VEC into TARGET. */
7120 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7122 machine_mode mode = GET_MODE (vec);
7123 machine_mode inner_mode = GET_MODE_INNER (mode);
7126 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7133 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7134 emit_move_insn (target, gen_lowpart (TImode, vec));
7137 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7140 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7143 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7146 if (TARGET_DIRECT_MOVE_64BIT)
7148 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7154 if (TARGET_DIRECT_MOVE_64BIT)
7156 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7162 if (TARGET_DIRECT_MOVE_64BIT)
7164 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7170 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7171 && TARGET_DIRECT_MOVE_64BIT)
7173 if (GET_MODE (elt) != DImode)
7175 rtx tmp = gen_reg_rtx (DImode);
7176 convert_move (tmp, elt, 0);
7179 else if (!REG_P (elt))
7180 elt = force_reg (DImode, elt);
7185 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7189 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7193 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7197 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7201 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7205 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7213 gcc_assert (CONST_INT_P (elt));
7215 /* Allocate mode-sized buffer. */
7216 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7218 emit_move_insn (mem, vec);
7220 /* Add offset to field within buffer matching vector element. */
7221 mem = adjust_address_nv (mem, inner_mode,
7222 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7224 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7227 /* Helper function to return the register number of a RTX. */
7229 regno_or_subregno (rtx op)
7233 else if (SUBREG_P (op))
7234 return subreg_regno (op);
7239 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7240 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7241 temporary (BASE_TMP) to fixup the address. Return the new memory address
7242 that is valid for reads or writes to a given register (SCALAR_REG). */
7245 rs6000_adjust_vec_address (rtx scalar_reg,
7249 machine_mode scalar_mode)
7251 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7252 rtx addr = XEXP (mem, 0);
7257 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7258 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7260 /* Calculate what we need to add to the address to get the element
7262 if (CONST_INT_P (element))
7263 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7266 int byte_shift = exact_log2 (scalar_size);
7267 gcc_assert (byte_shift >= 0);
7269 if (byte_shift == 0)
7270 element_offset = element;
7274 if (TARGET_POWERPC64)
7275 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7277 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7279 element_offset = base_tmp;
7283 /* Create the new address pointing to the element within the vector. If we
7284 are adding 0, we don't have to change the address. */
7285 if (element_offset == const0_rtx)
7288 /* A simple indirect address can be converted into a reg + offset
7290 else if (REG_P (addr) || SUBREG_P (addr))
7291 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7293 /* Optimize D-FORM addresses with constant offset with a constant element, to
7294 include the element offset in the address directly. */
7295 else if (GET_CODE (addr) == PLUS)
7297 rtx op0 = XEXP (addr, 0);
7298 rtx op1 = XEXP (addr, 1);
7301 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7302 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7304 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7305 rtx offset_rtx = GEN_INT (offset);
7307 if (IN_RANGE (offset, -32768, 32767)
7308 && (scalar_size < 8 || (offset & 0x3) == 0))
7309 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7312 emit_move_insn (base_tmp, offset_rtx);
7313 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7318 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7319 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7321 /* Note, ADDI requires the register being added to be a base
7322 register. If the register was R0, load it up into the temporary
7325 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7327 insn = gen_add3_insn (base_tmp, op1, element_offset);
7328 gcc_assert (insn != NULL_RTX);
7333 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7335 insn = gen_add3_insn (base_tmp, element_offset, op1);
7336 gcc_assert (insn != NULL_RTX);
7342 emit_move_insn (base_tmp, op1);
7343 emit_insn (gen_add2_insn (base_tmp, element_offset));
7346 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7352 emit_move_insn (base_tmp, addr);
7353 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7356 /* If we have a PLUS, we need to see whether the particular register class
7357 allows for D-FORM or X-FORM addressing. */
7358 if (GET_CODE (new_addr) == PLUS)
7360 rtx op1 = XEXP (new_addr, 1);
7361 addr_mask_type addr_mask;
7362 int scalar_regno = regno_or_subregno (scalar_reg);
7364 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7365 if (INT_REGNO_P (scalar_regno))
7366 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7368 else if (FP_REGNO_P (scalar_regno))
7369 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7371 else if (ALTIVEC_REGNO_P (scalar_regno))
7372 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7377 if (REG_P (op1) || SUBREG_P (op1))
7378 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7380 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7383 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7384 valid_addr_p = true;
7387 valid_addr_p = false;
7391 emit_move_insn (base_tmp, new_addr);
7392 new_addr = base_tmp;
7395 return change_address (mem, scalar_mode, new_addr);
7398 /* Split a variable vec_extract operation into the component instructions. */
7401 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7404 machine_mode mode = GET_MODE (src);
7405 machine_mode scalar_mode = GET_MODE (dest);
7406 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7407 int byte_shift = exact_log2 (scalar_size);
7409 gcc_assert (byte_shift >= 0);
7411 /* If we are given a memory address, optimize to load just the element. We
7412 don't have to adjust the vector element number on little endian
7416 gcc_assert (REG_P (tmp_gpr));
7417 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7418 tmp_gpr, scalar_mode));
7422 else if (REG_P (src) || SUBREG_P (src))
7424 int bit_shift = byte_shift + 3;
7426 int dest_regno = regno_or_subregno (dest);
7427 int src_regno = regno_or_subregno (src);
7428 int element_regno = regno_or_subregno (element);
7430 gcc_assert (REG_P (tmp_gpr));
7432 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7433 a general purpose register. */
7434 if (TARGET_P9_VECTOR
7435 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7436 && INT_REGNO_P (dest_regno)
7437 && ALTIVEC_REGNO_P (src_regno)
7438 && INT_REGNO_P (element_regno))
7440 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7441 rtx element_si = gen_rtx_REG (SImode, element_regno);
7443 if (mode == V16QImode)
7444 emit_insn (BYTES_BIG_ENDIAN
7445 ? gen_vextublx (dest_si, element_si, src)
7446 : gen_vextubrx (dest_si, element_si, src));
7448 else if (mode == V8HImode)
7450 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7451 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7452 emit_insn (BYTES_BIG_ENDIAN
7453 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7454 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7460 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7461 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7462 emit_insn (BYTES_BIG_ENDIAN
7463 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7464 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7471 gcc_assert (REG_P (tmp_altivec));
7473 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7474 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7475 will shift the element into the upper position (adding 3 to convert a
7476 byte shift into a bit shift). */
7477 if (scalar_size == 8)
7479 if (!BYTES_BIG_ENDIAN)
7481 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7487 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7489 emit_insn (gen_rtx_SET (tmp_gpr,
7490 gen_rtx_AND (DImode,
7491 gen_rtx_ASHIFT (DImode,
7498 if (!BYTES_BIG_ENDIAN)
7500 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7502 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7503 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7509 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7512 /* Get the value into the lower byte of the Altivec register where VSLO
7514 if (TARGET_P9_VECTOR)
7515 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7516 else if (can_create_pseudo_p ())
7517 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7520 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7521 emit_move_insn (tmp_di, tmp_gpr);
7522 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7525 /* Do the VSLO to get the value into the final location. */
7529 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7533 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7538 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7539 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7540 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7541 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7544 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7552 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7553 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7554 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7555 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7557 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7558 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7559 GEN_INT (64 - (8 * scalar_size))));
7573 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7574 two SImode values. */
7577 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7579 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7581 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7583 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7584 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7586 emit_move_insn (dest, GEN_INT (const1 | const2));
7590 /* Put si1 into upper 32-bits of dest. */
7591 if (CONST_INT_P (si1))
7592 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7595 /* Generate RLDIC. */
7596 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7597 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7598 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7599 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7600 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7601 emit_insn (gen_rtx_SET (dest, and_rtx));
7604 /* Put si2 into the temporary. */
7605 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7606 if (CONST_INT_P (si2))
7607 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7609 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7611 /* Combine the two parts. */
7612 emit_insn (gen_iordi3 (dest, dest, tmp));
7616 /* Split a V4SI initialization. */
7619 rs6000_split_v4si_init (rtx operands[])
7621 rtx dest = operands[0];
7623 /* Destination is a GPR, build up the two DImode parts in place. */
7624 if (REG_P (dest) || SUBREG_P (dest))
7626 int d_regno = regno_or_subregno (dest);
7627 rtx scalar1 = operands[1];
7628 rtx scalar2 = operands[2];
7629 rtx scalar3 = operands[3];
7630 rtx scalar4 = operands[4];
7631 rtx tmp1 = operands[5];
7632 rtx tmp2 = operands[6];
7634 /* Even though we only need one temporary (plus the destination, which
7635 has an early clobber constraint, try to use two temporaries, one for
7636 each double word created. That way the 2nd insn scheduling pass can
7637 rearrange things so the two parts are done in parallel. */
7638 if (BYTES_BIG_ENDIAN)
7640 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7641 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7642 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7643 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7647 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7648 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7649 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7650 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7659 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7660 selects whether the alignment is abi mandated, optional, or
7661 both abi and optional alignment. */
7664 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7666 if (how != align_opt)
7668 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7672 if (how != align_abi)
7674 if (TREE_CODE (type) == ARRAY_TYPE
7675 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7677 if (align < BITS_PER_WORD)
7678 align = BITS_PER_WORD;
7685 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7686 instructions simply ignore the low bits; VSX memory instructions
7687 are aligned to 4 or 8 bytes. */
7690 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7692 return (STRICT_ALIGNMENT
7693 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7694 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7695 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7696 && (int) align < VECTOR_ALIGN (mode)))));
7699 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7702 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7704 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7706 if (computed != 128)
7709 if (!warned && warn_psabi)
7712 inform (input_location,
7713 "the layout of aggregates containing vectors with"
7714 " %d-byte alignment has changed in GCC 5",
7715 computed / BITS_PER_UNIT);
7718 /* In current GCC there is no special case. */
7725 /* AIX increases natural record alignment to doubleword if the first
7726 field is an FP double while the FP fields remain word aligned. */
7729 rs6000_special_round_type_align (tree type, unsigned int computed,
7730 unsigned int specified)
7732 unsigned int align = MAX (computed, specified);
7733 tree field = TYPE_FIELDS (type);
7735 /* Skip all non field decls */
7736 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7737 field = DECL_CHAIN (field);
7739 if (field != NULL && field != type)
7741 type = TREE_TYPE (field);
7742 while (TREE_CODE (type) == ARRAY_TYPE)
7743 type = TREE_TYPE (type);
7745 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7746 align = MAX (align, 64);
7752 /* Darwin increases record alignment to the natural alignment of
7756 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7757 unsigned int specified)
7759 unsigned int align = MAX (computed, specified);
7761 if (TYPE_PACKED (type))
7764 /* Find the first field, looking down into aggregates. */
7766 tree field = TYPE_FIELDS (type);
7767 /* Skip all non field decls */
7768 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7769 field = DECL_CHAIN (field);
7772 /* A packed field does not contribute any extra alignment. */
7773 if (DECL_PACKED (field))
7775 type = TREE_TYPE (field);
7776 while (TREE_CODE (type) == ARRAY_TYPE)
7777 type = TREE_TYPE (type);
7778 } while (AGGREGATE_TYPE_P (type));
7780 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7781 align = MAX (align, TYPE_ALIGN (type));
7786 /* Return 1 for an operand in small memory on V.4/eabi. */
7789 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7790 machine_mode mode ATTRIBUTE_UNUSED)
7795 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7798 if (DEFAULT_ABI != ABI_V4)
7801 if (GET_CODE (op) == SYMBOL_REF)
7804 else if (GET_CODE (op) != CONST
7805 || GET_CODE (XEXP (op, 0)) != PLUS
7806 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
7807 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7812 rtx sum = XEXP (op, 0);
7813 HOST_WIDE_INT summand;
7815 /* We have to be careful here, because it is the referenced address
7816 that must be 32k from _SDA_BASE_, not just the symbol. */
7817 summand = INTVAL (XEXP (sum, 1));
7818 if (summand < 0 || summand > g_switch_value)
7821 sym_ref = XEXP (sum, 0);
7824 return SYMBOL_REF_SMALL_P (sym_ref);
7830 /* Return true if either operand is a general purpose register. */
7833 gpr_or_gpr_p (rtx op0, rtx op1)
7835 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7836 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7839 /* Return true if this is a move direct operation between GPR registers and
7840 floating point/VSX registers. */
7843 direct_move_p (rtx op0, rtx op1)
7847 if (!REG_P (op0) || !REG_P (op1))
7850 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7853 regno0 = REGNO (op0);
7854 regno1 = REGNO (op1);
7855 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
7858 if (INT_REGNO_P (regno0))
7859 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7861 else if (INT_REGNO_P (regno1))
7863 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7866 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7873 /* Return true if the OFFSET is valid for the quad address instructions that
7874 use d-form (register + offset) addressing. */
7877 quad_address_offset_p (HOST_WIDE_INT offset)
7879 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7882 /* Return true if the ADDR is an acceptable address for a quad memory
7883 operation of mode MODE (either LQ/STQ for general purpose registers, or
7884 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7885 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7886 3.0 LXV/STXV instruction. */
7889 quad_address_p (rtx addr, machine_mode mode, bool strict)
7893 if (GET_MODE_SIZE (mode) != 16)
7896 if (legitimate_indirect_address_p (addr, strict))
7899 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7902 if (GET_CODE (addr) != PLUS)
7905 op0 = XEXP (addr, 0);
7906 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7909 op1 = XEXP (addr, 1);
7910 if (!CONST_INT_P (op1))
7913 return quad_address_offset_p (INTVAL (op1));
7916 /* Return true if this is a load or store quad operation. This function does
7917 not handle the atomic quad memory instructions. */
7920 quad_load_store_p (rtx op0, rtx op1)
7924 if (!TARGET_QUAD_MEMORY)
7927 else if (REG_P (op0) && MEM_P (op1))
7928 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7929 && quad_memory_operand (op1, GET_MODE (op1))
7930 && !reg_overlap_mentioned_p (op0, op1));
7932 else if (MEM_P (op0) && REG_P (op1))
7933 ret = (quad_memory_operand (op0, GET_MODE (op0))
7934 && quad_int_reg_operand (op1, GET_MODE (op1)));
7939 if (TARGET_DEBUG_ADDR)
7941 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7942 ret ? "true" : "false");
7943 debug_rtx (gen_rtx_SET (op0, op1));
7949 /* Given an address, return a constant offset term if one exists. */
7952 address_offset (rtx op)
7954 if (GET_CODE (op) == PRE_INC
7955 || GET_CODE (op) == PRE_DEC)
7957 else if (GET_CODE (op) == PRE_MODIFY
7958 || GET_CODE (op) == LO_SUM)
7961 if (GET_CODE (op) == CONST)
7964 if (GET_CODE (op) == PLUS)
7967 if (CONST_INT_P (op))
7973 /* Return true if the MEM operand is a memory operand suitable for use
7974 with a (full width, possibly multiple) gpr load/store. On
7975 powerpc64 this means the offset must be divisible by 4.
7976 Implements 'Y' constraint.
7978 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7979 a constraint function we know the operand has satisfied a suitable
7980 memory predicate. Also accept some odd rtl generated by reload
7981 (see rs6000_legitimize_reload_address for various forms). It is
7982 important that reload rtl be accepted by appropriate constraints
7983 but not by the operand predicate.
7985 Offsetting a lo_sum should not be allowed, except where we know by
7986 alignment that a 32k boundary is not crossed, but see the ???
7987 comment in rs6000_legitimize_reload_address. Note that by
7988 "offsetting" here we mean a further offset to access parts of the
7989 MEM. It's fine to have a lo_sum where the inner address is offset
7990 from a sym, since the same sym+offset will appear in the high part
7991 of the address calculation. */
7994 mem_operand_gpr (rtx op, machine_mode mode)
7996 unsigned HOST_WIDE_INT offset;
7998 rtx addr = XEXP (op, 0);
8000 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
8001 if (!rs6000_offsettable_memref_p (op, mode, false))
8004 op = address_offset (addr);
8008 offset = INTVAL (op);
8009 if (TARGET_POWERPC64 && (offset & 3) != 0)
8012 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8016 if (GET_CODE (addr) == LO_SUM)
8017 /* For lo_sum addresses, we must allow any offset except one that
8018 causes a wrap, so test only the low 16 bits. */
8019 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8021 return offset + 0x8000 < 0x10000u - extra;
8024 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8025 enforce an offset divisible by 4 even for 32-bit. */
8028 mem_operand_ds_form (rtx op, machine_mode mode)
8030 unsigned HOST_WIDE_INT offset;
8032 rtx addr = XEXP (op, 0);
8034 if (!offsettable_address_p (false, mode, addr))
8037 op = address_offset (addr);
8041 offset = INTVAL (op);
8042 if ((offset & 3) != 0)
8045 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8049 if (GET_CODE (addr) == LO_SUM)
8050 /* For lo_sum addresses, we must allow any offset except one that
8051 causes a wrap, so test only the low 16 bits. */
8052 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8054 return offset + 0x8000 < 0x10000u - extra;
8057 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8060 reg_offset_addressing_ok_p (machine_mode mode)
8074 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8075 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8076 a vector mode, if we want to use the VSX registers to move it around,
8077 we need to restrict ourselves to reg+reg addressing. Similarly for
8078 IEEE 128-bit floating point that is passed in a single vector
8080 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8081 return mode_supports_dq_form (mode);
8085 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8086 addressing for the LFIWZX and STFIWX instructions. */
8087 if (TARGET_NO_SDMODE_STACK)
8099 virtual_stack_registers_memory_p (rtx op)
8103 if (GET_CODE (op) == REG)
8104 regnum = REGNO (op);
8106 else if (GET_CODE (op) == PLUS
8107 && GET_CODE (XEXP (op, 0)) == REG
8108 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8109 regnum = REGNO (XEXP (op, 0));
8114 return (regnum >= FIRST_VIRTUAL_REGISTER
8115 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8118 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8119 is known to not straddle a 32k boundary. This function is used
8120 to determine whether -mcmodel=medium code can use TOC pointer
8121 relative addressing for OP. This means the alignment of the TOC
8122 pointer must also be taken into account, and unfortunately that is
8125 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8126 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8130 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8134 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8136 if (GET_CODE (op) != SYMBOL_REF)
8139 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8141 if (mode_supports_dq_form (mode))
8144 dsize = GET_MODE_SIZE (mode);
8145 decl = SYMBOL_REF_DECL (op);
8151 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8152 replacing memory addresses with an anchor plus offset. We
8153 could find the decl by rummaging around in the block->objects
8154 VEC for the given offset but that seems like too much work. */
8155 dalign = BITS_PER_UNIT;
8156 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8157 && SYMBOL_REF_ANCHOR_P (op)
8158 && SYMBOL_REF_BLOCK (op) != NULL)
8160 struct object_block *block = SYMBOL_REF_BLOCK (op);
8162 dalign = block->alignment;
8163 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8165 else if (CONSTANT_POOL_ADDRESS_P (op))
8167 /* It would be nice to have get_pool_align().. */
8168 machine_mode cmode = get_pool_mode (op);
8170 dalign = GET_MODE_ALIGNMENT (cmode);
8173 else if (DECL_P (decl))
8175 dalign = DECL_ALIGN (decl);
8179 /* Allow BLKmode when the entire object is known to not
8180 cross a 32k boundary. */
8181 if (!DECL_SIZE_UNIT (decl))
8184 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8187 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8191 dalign /= BITS_PER_UNIT;
8192 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8193 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8194 return dalign >= dsize;
8200 /* Find how many bits of the alignment we know for this access. */
8201 dalign /= BITS_PER_UNIT;
8202 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8203 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8205 lsb = offset & -offset;
8209 return dalign >= dsize;
8213 constant_pool_expr_p (rtx op)
8217 split_const (op, &base, &offset);
8218 return (GET_CODE (base) == SYMBOL_REF
8219 && CONSTANT_POOL_ADDRESS_P (base)
8220 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8223 /* These are only used to pass through from print_operand/print_operand_address
8224 to rs6000_output_addr_const_extra over the intervening function
8225 output_addr_const which is not target code. */
8226 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8228 /* Return true if OP is a toc pointer relative address (the output
8229 of create_TOC_reference). If STRICT, do not match non-split
8230 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8231 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8232 TOCREL_OFFSET_RET respectively. */
8235 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8236 const_rtx *tocrel_offset_ret)
8241 if (TARGET_CMODEL != CMODEL_SMALL)
8243 /* When strict ensure we have everything tidy. */
8245 && !(GET_CODE (op) == LO_SUM
8246 && REG_P (XEXP (op, 0))
8247 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8250 /* When not strict, allow non-split TOC addresses and also allow
8251 (lo_sum (high ..)) TOC addresses created during reload. */
8252 if (GET_CODE (op) == LO_SUM)
8256 const_rtx tocrel_base = op;
8257 const_rtx tocrel_offset = const0_rtx;
8259 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8261 tocrel_base = XEXP (op, 0);
8262 tocrel_offset = XEXP (op, 1);
8265 if (tocrel_base_ret)
8266 *tocrel_base_ret = tocrel_base;
8267 if (tocrel_offset_ret)
8268 *tocrel_offset_ret = tocrel_offset;
8270 return (GET_CODE (tocrel_base) == UNSPEC
8271 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8274 /* Return true if X is a constant pool address, and also for cmodel=medium
8275 if X is a toc-relative address known to be offsettable within MODE. */
8278 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8281 const_rtx tocrel_base, tocrel_offset;
8282 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8283 && (TARGET_CMODEL != CMODEL_MEDIUM
8284 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8286 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8287 INTVAL (tocrel_offset), mode)));
8291 legitimate_small_data_p (machine_mode mode, rtx x)
8293 return (DEFAULT_ABI == ABI_V4
8294 && !flag_pic && !TARGET_TOC
8295 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8296 && small_data_operand (x, mode));
8300 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8301 bool strict, bool worst_case)
8303 unsigned HOST_WIDE_INT offset;
8306 if (GET_CODE (x) != PLUS)
8308 if (!REG_P (XEXP (x, 0)))
8310 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8312 if (mode_supports_dq_form (mode))
8313 return quad_address_p (x, mode, strict);
8314 if (!reg_offset_addressing_ok_p (mode))
8315 return virtual_stack_registers_memory_p (x);
8316 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8318 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8321 offset = INTVAL (XEXP (x, 1));
8328 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8330 if (VECTOR_MEM_VSX_P (mode))
8335 if (!TARGET_POWERPC64)
8337 else if (offset & 3)
8350 if (!TARGET_POWERPC64)
8352 else if (offset & 3)
8361 return offset < 0x10000 - extra;
8365 legitimate_indexed_address_p (rtx x, int strict)
8369 if (GET_CODE (x) != PLUS)
8375 return (REG_P (op0) && REG_P (op1)
8376 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8377 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8378 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8379 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8383 avoiding_indexed_address_p (machine_mode mode)
8385 /* Avoid indexed addressing for modes that have non-indexed
8386 load/store instruction forms. */
8387 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8391 legitimate_indirect_address_p (rtx x, int strict)
8393 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8397 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8399 if (!TARGET_MACHO || !flag_pic
8400 || mode != SImode || GET_CODE (x) != MEM)
8404 if (GET_CODE (x) != LO_SUM)
8406 if (GET_CODE (XEXP (x, 0)) != REG)
8408 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8412 return CONSTANT_P (x);
8416 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8418 if (GET_CODE (x) != LO_SUM)
8420 if (GET_CODE (XEXP (x, 0)) != REG)
8422 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8424 /* quad word addresses are restricted, and we can't use LO_SUM. */
8425 if (mode_supports_dq_form (mode))
8429 if (TARGET_ELF || TARGET_MACHO)
8433 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8435 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8436 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8437 recognizes some LO_SUM addresses as valid although this
8438 function says opposite. In most cases, LRA through different
8439 transformations can generate correct code for address reloads.
8440 It can not manage only some LO_SUM cases. So we need to add
8441 code analogous to one in rs6000_legitimize_reload_address for
8442 LOW_SUM here saying that some addresses are still valid. */
8443 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8444 && small_toc_ref (x, VOIDmode));
8445 if (TARGET_TOC && ! large_toc_ok)
8447 if (GET_MODE_NUNITS (mode) != 1)
8449 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8450 && !(/* ??? Assume floating point reg based on mode? */
8451 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8454 return CONSTANT_P (x) || large_toc_ok;
8461 /* Try machine-dependent ways of modifying an illegitimate address
8462 to be legitimate. If we find one, return the new, valid address.
8463 This is used from only one place: `memory_address' in explow.c.
8465 OLDX is the address as it was before break_out_memory_refs was
8466 called. In some cases it is useful to look at this to decide what
8469 It is always safe for this function to do nothing. It exists to
8470 recognize opportunities to optimize the output.
8472 On RS/6000, first check for the sum of a register with a constant
8473 integer that is out of range. If so, generate code to add the
8474 constant with the low-order 16 bits masked to the register and force
8475 this result into another register (this can be done with `cau').
8476 Then generate an address of REG+(CONST&0xffff), allowing for the
8477 possibility of bit 16 being a one.
8479 Then check for the sum of a register and something not constant, try to
8480 load the other things into a register and return the sum. */
8483 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8488 if (!reg_offset_addressing_ok_p (mode)
8489 || mode_supports_dq_form (mode))
8491 if (virtual_stack_registers_memory_p (x))
8494 /* In theory we should not be seeing addresses of the form reg+0,
8495 but just in case it is generated, optimize it away. */
8496 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8497 return force_reg (Pmode, XEXP (x, 0));
8499 /* For TImode with load/store quad, restrict addresses to just a single
8500 pointer, so it works with both GPRs and VSX registers. */
8501 /* Make sure both operands are registers. */
8502 else if (GET_CODE (x) == PLUS
8503 && (mode != TImode || !TARGET_VSX))
8504 return gen_rtx_PLUS (Pmode,
8505 force_reg (Pmode, XEXP (x, 0)),
8506 force_reg (Pmode, XEXP (x, 1)));
8508 return force_reg (Pmode, x);
8510 if (GET_CODE (x) == SYMBOL_REF)
8512 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8514 return rs6000_legitimize_tls_address (x, model);
8526 /* As in legitimate_offset_address_p we do not assume
8527 worst-case. The mode here is just a hint as to the registers
8528 used. A TImode is usually in gprs, but may actually be in
8529 fprs. Leave worst-case scenario for reload to handle via
8530 insn constraints. PTImode is only GPRs. */
8537 if (GET_CODE (x) == PLUS
8538 && GET_CODE (XEXP (x, 0)) == REG
8539 && GET_CODE (XEXP (x, 1)) == CONST_INT
8540 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8541 >= 0x10000 - extra))
8543 HOST_WIDE_INT high_int, low_int;
8545 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8546 if (low_int >= 0x8000 - extra)
8548 high_int = INTVAL (XEXP (x, 1)) - low_int;
8549 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8550 GEN_INT (high_int)), 0);
8551 return plus_constant (Pmode, sum, low_int);
8553 else if (GET_CODE (x) == PLUS
8554 && GET_CODE (XEXP (x, 0)) == REG
8555 && GET_CODE (XEXP (x, 1)) != CONST_INT
8556 && GET_MODE_NUNITS (mode) == 1
8557 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8558 || (/* ??? Assume floating point reg based on mode? */
8559 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8560 && !avoiding_indexed_address_p (mode))
8562 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8563 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8565 else if ((TARGET_ELF
8567 || !MACHO_DYNAMIC_NO_PIC_P
8573 && GET_CODE (x) != CONST_INT
8574 && GET_CODE (x) != CONST_WIDE_INT
8575 && GET_CODE (x) != CONST_DOUBLE
8577 && GET_MODE_NUNITS (mode) == 1
8578 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8579 || (/* ??? Assume floating point reg based on mode? */
8580 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8582 rtx reg = gen_reg_rtx (Pmode);
8584 emit_insn (gen_elf_high (reg, x));
8586 emit_insn (gen_macho_high (reg, x));
8587 return gen_rtx_LO_SUM (Pmode, reg, x);
8590 && GET_CODE (x) == SYMBOL_REF
8591 && constant_pool_expr_p (x)
8592 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8593 return create_TOC_reference (x, NULL_RTX);
8598 /* Debug version of rs6000_legitimize_address. */
8600 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8606 ret = rs6000_legitimize_address (x, oldx, mode);
8607 insns = get_insns ();
8613 "\nrs6000_legitimize_address: mode %s, old code %s, "
8614 "new code %s, modified\n",
8615 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8616 GET_RTX_NAME (GET_CODE (ret)));
8618 fprintf (stderr, "Original address:\n");
8621 fprintf (stderr, "oldx:\n");
8624 fprintf (stderr, "New address:\n");
8629 fprintf (stderr, "Insns added:\n");
8630 debug_rtx_list (insns, 20);
8636 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8637 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8648 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8649 We need to emit DTP-relative relocations. */
8651 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8653 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8658 fputs ("\t.long\t", file);
8661 fputs (DOUBLE_INT_ASM_OP, file);
8666 output_addr_const (file, x);
8668 fputs ("@dtprel+0x8000", file);
8669 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8671 switch (SYMBOL_REF_TLS_MODEL (x))
8675 case TLS_MODEL_LOCAL_EXEC:
8676 fputs ("@le", file);
8678 case TLS_MODEL_INITIAL_EXEC:
8679 fputs ("@ie", file);
8681 case TLS_MODEL_GLOBAL_DYNAMIC:
8682 case TLS_MODEL_LOCAL_DYNAMIC:
8691 /* Return true if X is a symbol that refers to real (rather than emulated)
8695 rs6000_real_tls_symbol_ref_p (rtx x)
8697 return (GET_CODE (x) == SYMBOL_REF
8698 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8701 /* In the name of slightly smaller debug output, and to cater to
8702 general assembler lossage, recognize various UNSPEC sequences
8703 and turn them back into a direct symbol reference. */
8706 rs6000_delegitimize_address (rtx orig_x)
8710 orig_x = delegitimize_mem_from_attrs (orig_x);
8716 if (TARGET_CMODEL != CMODEL_SMALL
8717 && GET_CODE (y) == LO_SUM)
8721 if (GET_CODE (y) == PLUS
8722 && GET_MODE (y) == Pmode
8723 && CONST_INT_P (XEXP (y, 1)))
8725 offset = XEXP (y, 1);
8729 if (GET_CODE (y) == UNSPEC
8730 && XINT (y, 1) == UNSPEC_TOCREL)
8732 y = XVECEXP (y, 0, 0);
8735 /* Do not associate thread-local symbols with the original
8736 constant pool symbol. */
8738 && GET_CODE (y) == SYMBOL_REF
8739 && CONSTANT_POOL_ADDRESS_P (y)
8740 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8744 if (offset != NULL_RTX)
8745 y = gen_rtx_PLUS (Pmode, y, offset);
8746 if (!MEM_P (orig_x))
8749 return replace_equiv_address_nv (orig_x, y);
8753 && GET_CODE (orig_x) == LO_SUM
8754 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8756 y = XEXP (XEXP (orig_x, 1), 0);
8757 if (GET_CODE (y) == UNSPEC
8758 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8759 return XVECEXP (y, 0, 0);
8765 /* Return true if X shouldn't be emitted into the debug info.
8766 The linker doesn't like .toc section references from
8767 .debug_* sections, so reject .toc section symbols. */
8770 rs6000_const_not_ok_for_debug_p (rtx x)
8772 if (GET_CODE (x) == UNSPEC)
8774 if (GET_CODE (x) == SYMBOL_REF
8775 && CONSTANT_POOL_ADDRESS_P (x))
8777 rtx c = get_pool_constant (x);
8778 machine_mode cmode = get_pool_mode (x);
8779 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8787 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8790 rs6000_legitimate_combined_insn (rtx_insn *insn)
8792 int icode = INSN_CODE (insn);
8794 /* Reject creating doloop insns. Combine should not be allowed
8795 to create these for a number of reasons:
8796 1) In a nested loop, if combine creates one of these in an
8797 outer loop and the register allocator happens to allocate ctr
8798 to the outer loop insn, then the inner loop can't use ctr.
8799 Inner loops ought to be more highly optimized.
8800 2) Combine often wants to create one of these from what was
8801 originally a three insn sequence, first combining the three
8802 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8803 allocated ctr, the splitter takes use back to the three insn
8804 sequence. It's better to stop combine at the two insn
8806 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8807 insns, the register allocator sometimes uses floating point
8808 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8809 jump insn and output reloads are not implemented for jumps,
8810 the ctrsi/ctrdi splitters need to handle all possible cases.
8811 That's a pain, and it gets to be seriously difficult when a
8812 splitter that runs after reload needs memory to transfer from
8813 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8814 for the difficult case. It's better to not create problems
8815 in the first place. */
8816 if (icode != CODE_FOR_nothing
8817 && (icode == CODE_FOR_bdz_si
8818 || icode == CODE_FOR_bdz_di
8819 || icode == CODE_FOR_bdnz_si
8820 || icode == CODE_FOR_bdnz_di
8821 || icode == CODE_FOR_bdztf_si
8822 || icode == CODE_FOR_bdztf_di
8823 || icode == CODE_FOR_bdnztf_si
8824 || icode == CODE_FOR_bdnztf_di))
8830 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8832 static GTY(()) rtx rs6000_tls_symbol;
8834 rs6000_tls_get_addr (void)
8836 if (!rs6000_tls_symbol)
8837 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8839 return rs6000_tls_symbol;
8842 /* Construct the SYMBOL_REF for TLS GOT references. */
8844 static GTY(()) rtx rs6000_got_symbol;
8846 rs6000_got_sym (void)
8848 if (!rs6000_got_symbol)
8850 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8851 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8852 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8855 return rs6000_got_symbol;
8858 /* AIX Thread-Local Address support. */
8861 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8863 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8867 name = XSTR (addr, 0);
8868 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8869 or the symbol will be in TLS private data section. */
8870 if (name[strlen (name) - 1] != ']'
8871 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8872 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8874 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8875 strcpy (tlsname, name);
8877 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8878 tlsaddr = copy_rtx (addr);
8879 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8884 /* Place addr into TOC constant pool. */
8885 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8887 /* Output the TOC entry and create the MEM referencing the value. */
8888 if (constant_pool_expr_p (XEXP (sym, 0))
8889 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8891 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8892 mem = gen_const_mem (Pmode, tocref);
8893 set_mem_alias_set (mem, get_TOC_alias_set ());
8898 /* Use global-dynamic for local-dynamic. */
8899 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8900 || model == TLS_MODEL_LOCAL_DYNAMIC)
8902 /* Create new TOC reference for @m symbol. */
8903 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8904 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8905 strcpy (tlsname, "*LCM");
8906 strcat (tlsname, name + 3);
8907 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8908 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8909 tocref = create_TOC_reference (modaddr, NULL_RTX);
8910 rtx modmem = gen_const_mem (Pmode, tocref);
8911 set_mem_alias_set (modmem, get_TOC_alias_set ());
8913 rtx modreg = gen_reg_rtx (Pmode);
8914 emit_insn (gen_rtx_SET (modreg, modmem));
8916 tmpreg = gen_reg_rtx (Pmode);
8917 emit_insn (gen_rtx_SET (tmpreg, mem));
8919 dest = gen_reg_rtx (Pmode);
8921 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8923 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8926 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8927 else if (TARGET_32BIT)
8929 tlsreg = gen_reg_rtx (SImode);
8930 emit_insn (gen_tls_get_tpointer (tlsreg));
8933 tlsreg = gen_rtx_REG (DImode, 13);
8935 /* Load the TOC value into temporary register. */
8936 tmpreg = gen_reg_rtx (Pmode);
8937 emit_insn (gen_rtx_SET (tmpreg, mem));
8938 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8939 gen_rtx_MINUS (Pmode, addr, tlsreg));
8941 /* Add TOC symbol value to TLS pointer. */
8942 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8947 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8948 this (thread-local) address. */
8951 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8956 return rs6000_legitimize_tls_address_aix (addr, model);
8958 dest = gen_reg_rtx (Pmode);
8959 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8965 tlsreg = gen_rtx_REG (Pmode, 13);
8966 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8970 tlsreg = gen_rtx_REG (Pmode, 2);
8971 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8975 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8979 tmp = gen_reg_rtx (Pmode);
8982 tlsreg = gen_rtx_REG (Pmode, 13);
8983 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8987 tlsreg = gen_rtx_REG (Pmode, 2);
8988 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8992 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8994 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8999 rtx r3, got, tga, tmp1, tmp2, call_insn;
9001 /* We currently use relocations like @got@tlsgd for tls, which
9002 means the linker will handle allocation of tls entries, placing
9003 them in the .got section. So use a pointer to the .got section,
9004 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9005 or to secondary GOT sections used by 32-bit -fPIC. */
9007 got = gen_rtx_REG (Pmode, 2);
9011 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9014 rtx gsym = rs6000_got_sym ();
9015 got = gen_reg_rtx (Pmode);
9017 rs6000_emit_move (got, gsym, Pmode);
9022 tmp1 = gen_reg_rtx (Pmode);
9023 tmp2 = gen_reg_rtx (Pmode);
9024 mem = gen_const_mem (Pmode, tmp1);
9025 lab = gen_label_rtx ();
9026 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9027 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9028 if (TARGET_LINK_STACK)
9029 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9030 emit_move_insn (tmp2, mem);
9031 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9032 set_unique_reg_note (last, REG_EQUAL, gsym);
9037 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9039 tga = rs6000_tls_get_addr ();
9040 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9043 r3 = gen_rtx_REG (Pmode, 3);
9044 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9047 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9049 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9051 else if (DEFAULT_ABI == ABI_V4)
9052 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9055 call_insn = last_call_insn ();
9056 PATTERN (call_insn) = insn;
9057 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9058 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9059 pic_offset_table_rtx);
9061 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9063 tga = rs6000_tls_get_addr ();
9064 tmp1 = gen_reg_rtx (Pmode);
9065 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9068 r3 = gen_rtx_REG (Pmode, 3);
9069 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9072 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9074 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9076 else if (DEFAULT_ABI == ABI_V4)
9077 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9080 call_insn = last_call_insn ();
9081 PATTERN (call_insn) = insn;
9082 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9083 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9084 pic_offset_table_rtx);
9086 if (rs6000_tls_size == 16)
9089 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9091 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9093 else if (rs6000_tls_size == 32)
9095 tmp2 = gen_reg_rtx (Pmode);
9097 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9099 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9102 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9104 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9108 tmp2 = gen_reg_rtx (Pmode);
9110 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9112 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9114 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9120 /* IE, or 64-bit offset LE. */
9121 tmp2 = gen_reg_rtx (Pmode);
9123 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9125 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9128 insn = gen_tls_tls_64 (dest, tmp2, addr);
9130 insn = gen_tls_tls_32 (dest, tmp2, addr);
9138 /* Only create the global variable for the stack protect guard if we are using
9139 the global flavor of that guard. */
9141 rs6000_init_stack_protect_guard (void)
9143 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9144 return default_stack_protect_guard ();
9149 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9152 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9154 if (GET_CODE (x) == HIGH
9155 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9158 /* A TLS symbol in the TOC cannot contain a sum. */
9159 if (GET_CODE (x) == CONST
9160 && GET_CODE (XEXP (x, 0)) == PLUS
9161 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9162 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9165 /* Do not place an ELF TLS symbol in the constant pool. */
9166 return TARGET_ELF && tls_referenced_p (x);
9169 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9170 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9171 can be addressed relative to the toc pointer. */
9174 use_toc_relative_ref (rtx sym, machine_mode mode)
9176 return ((constant_pool_expr_p (sym)
9177 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9178 get_pool_mode (sym)))
9179 || (TARGET_CMODEL == CMODEL_MEDIUM
9180 && SYMBOL_REF_LOCAL_P (sym)
9181 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9184 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9185 replace the input X, or the original X if no replacement is called for.
9186 The output parameter *WIN is 1 if the calling macro should goto WIN,
9189 For RS/6000, we wish to handle large displacements off a base
9190 register by splitting the addend across an addiu/addis and the mem insn.
9191 This cuts number of extra insns needed from 3 to 1.
9193 On Darwin, we use this to generate code for floating point constants.
9194 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9195 The Darwin code is inside #if TARGET_MACHO because only then are the
9196 machopic_* functions defined. */
9198 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9199 int opnum, int type,
9200 int ind_levels ATTRIBUTE_UNUSED, int *win)
9202 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9203 bool quad_offset_p = mode_supports_dq_form (mode);
9205 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9206 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9209 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9210 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9211 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9212 && TARGET_P9_VECTOR)
9213 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9214 && TARGET_P9_VECTOR)))
9215 reg_offset_p = false;
9217 /* We must recognize output that we have already generated ourselves. */
9218 if (GET_CODE (x) == PLUS
9219 && GET_CODE (XEXP (x, 0)) == PLUS
9220 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9221 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9222 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9224 if (TARGET_DEBUG_ADDR)
9226 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9229 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9230 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9231 opnum, (enum reload_type) type);
9236 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9237 if (GET_CODE (x) == LO_SUM
9238 && GET_CODE (XEXP (x, 0)) == HIGH)
9240 if (TARGET_DEBUG_ADDR)
9242 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9245 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9246 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9247 opnum, (enum reload_type) type);
9253 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9254 && GET_CODE (x) == LO_SUM
9255 && GET_CODE (XEXP (x, 0)) == PLUS
9256 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9257 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9258 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9259 && machopic_operand_p (XEXP (x, 1)))
9261 /* Result of previous invocation of this function on Darwin
9262 floating point constant. */
9263 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9264 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9265 opnum, (enum reload_type) type);
9271 if (TARGET_CMODEL != CMODEL_SMALL
9274 && small_toc_ref (x, VOIDmode))
9276 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9277 x = gen_rtx_LO_SUM (Pmode, hi, x);
9278 if (TARGET_DEBUG_ADDR)
9280 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9283 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9284 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9285 opnum, (enum reload_type) type);
9290 if (GET_CODE (x) == PLUS
9291 && REG_P (XEXP (x, 0))
9292 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9293 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9294 && CONST_INT_P (XEXP (x, 1))
9296 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9298 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9299 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9301 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9303 /* Check for 32-bit overflow or quad addresses with one of the
9304 four least significant bits set. */
9305 if (high + low != val
9306 || (quad_offset_p && (low & 0xf)))
9312 /* Reload the high part into a base reg; leave the low part
9313 in the mem directly. */
9315 x = gen_rtx_PLUS (GET_MODE (x),
9316 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9320 if (TARGET_DEBUG_ADDR)
9322 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9325 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9326 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9327 opnum, (enum reload_type) type);
9332 if (GET_CODE (x) == SYMBOL_REF
9335 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9337 && DEFAULT_ABI == ABI_DARWIN
9338 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9339 && machopic_symbol_defined_p (x)
9341 && DEFAULT_ABI == ABI_V4
9344 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9345 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9347 ??? Assume floating point reg based on mode? This assumption is
9348 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9349 where reload ends up doing a DFmode load of a constant from
9350 mem using two gprs. Unfortunately, at this point reload
9351 hasn't yet selected regs so poking around in reload data
9352 won't help and even if we could figure out the regs reliably,
9353 we'd still want to allow this transformation when the mem is
9354 naturally aligned. Since we say the address is good here, we
9355 can't disable offsets from LO_SUMs in mem_operand_gpr.
9356 FIXME: Allow offset from lo_sum for other modes too, when
9357 mem is sufficiently aligned.
9359 Also disallow this if the type can go in VMX/Altivec registers, since
9360 those registers do not have d-form (reg+offset) address modes. */
9361 && !reg_addr[mode].scalar_in_vmx_p
9366 && (mode != TImode || !TARGET_VSX)
9368 && (mode != DImode || TARGET_POWERPC64)
9369 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9370 || TARGET_HARD_FLOAT))
9375 rtx offset = machopic_gen_offset (x);
9376 x = gen_rtx_LO_SUM (GET_MODE (x),
9377 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9378 gen_rtx_HIGH (Pmode, offset)), offset);
9382 x = gen_rtx_LO_SUM (GET_MODE (x),
9383 gen_rtx_HIGH (Pmode, x), x);
9385 if (TARGET_DEBUG_ADDR)
9387 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9390 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9391 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9392 opnum, (enum reload_type) type);
9397 /* Reload an offset address wrapped by an AND that represents the
9398 masking of the lower bits. Strip the outer AND and let reload
9399 convert the offset address into an indirect address. For VSX,
9400 force reload to create the address with an AND in a separate
9401 register, because we can't guarantee an altivec register will
9403 if (VECTOR_MEM_ALTIVEC_P (mode)
9404 && GET_CODE (x) == AND
9405 && GET_CODE (XEXP (x, 0)) == PLUS
9406 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9407 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9408 && GET_CODE (XEXP (x, 1)) == CONST_INT
9409 && INTVAL (XEXP (x, 1)) == -16)
9419 && GET_CODE (x) == SYMBOL_REF
9420 && use_toc_relative_ref (x, mode))
9422 x = create_TOC_reference (x, NULL_RTX);
9423 if (TARGET_CMODEL != CMODEL_SMALL)
9425 if (TARGET_DEBUG_ADDR)
9427 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9430 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9431 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9432 opnum, (enum reload_type) type);
9441 /* Debug version of rs6000_legitimize_reload_address. */
9443 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9444 int opnum, int type,
9445 int ind_levels, int *win)
9447 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9450 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9451 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9452 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9456 fprintf (stderr, "Same address returned\n");
9458 fprintf (stderr, "NULL returned\n");
9461 fprintf (stderr, "New address:\n");
9468 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9469 that is a valid memory address for an instruction.
9470 The MODE argument is the machine mode for the MEM expression
9471 that wants to use this address.
9473 On the RS/6000, there are four valid address: a SYMBOL_REF that
9474 refers to a constant pool entry of an address (or the sum of it
9475 plus a constant), a short (16-bit signed) constant plus a register,
9476 the sum of two registers, or a register indirect, possibly with an
9477 auto-increment. For DFmode, DDmode and DImode with a constant plus
9478 register, we must ensure that both words are addressable or PowerPC64
9479 with offset word aligned.
9481 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9482 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9483 because adjacent memory cells are accessed by adding word-sized offsets
9484 during assembly output. */
9486 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9488 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9489 bool quad_offset_p = mode_supports_dq_form (mode);
9491 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9492 if (VECTOR_MEM_ALTIVEC_P (mode)
9493 && GET_CODE (x) == AND
9494 && GET_CODE (XEXP (x, 1)) == CONST_INT
9495 && INTVAL (XEXP (x, 1)) == -16)
9498 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9500 if (legitimate_indirect_address_p (x, reg_ok_strict))
9503 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9504 && mode_supports_pre_incdec_p (mode)
9505 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9507 /* Handle restricted vector d-form offsets in ISA 3.0. */
9510 if (quad_address_p (x, mode, reg_ok_strict))
9513 else if (virtual_stack_registers_memory_p (x))
9516 else if (reg_offset_p)
9518 if (legitimate_small_data_p (mode, x))
9520 if (legitimate_constant_pool_address_p (x, mode,
9521 reg_ok_strict || lra_in_progress))
9523 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9524 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9528 /* For TImode, if we have TImode in VSX registers, only allow register
9529 indirect addresses. This will allow the values to go in either GPRs
9530 or VSX registers without reloading. The vector types would tend to
9531 go into VSX registers, so we allow REG+REG, while TImode seems
9532 somewhat split, in that some uses are GPR based, and some VSX based. */
9533 /* FIXME: We could loosen this by changing the following to
9534 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9535 but currently we cannot allow REG+REG addressing for TImode. See
9536 PR72827 for complete details on how this ends up hoodwinking DSE. */
9537 if (mode == TImode && TARGET_VSX)
9539 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9542 && GET_CODE (x) == PLUS
9543 && GET_CODE (XEXP (x, 0)) == REG
9544 && (XEXP (x, 0) == virtual_stack_vars_rtx
9545 || XEXP (x, 0) == arg_pointer_rtx)
9546 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9548 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9550 if (!FLOAT128_2REG_P (mode)
9551 && (TARGET_HARD_FLOAT
9553 || (mode != DFmode && mode != DDmode))
9554 && (TARGET_POWERPC64 || mode != DImode)
9555 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9557 && !avoiding_indexed_address_p (mode)
9558 && legitimate_indexed_address_p (x, reg_ok_strict))
9560 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9561 && mode_supports_pre_modify_p (mode)
9562 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9563 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9564 reg_ok_strict, false)
9565 || (!avoiding_indexed_address_p (mode)
9566 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9567 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9569 if (reg_offset_p && !quad_offset_p
9570 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9575 /* Debug version of rs6000_legitimate_address_p. */
9577 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9580 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9582 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9583 "strict = %d, reload = %s, code = %s\n",
9584 ret ? "true" : "false",
9585 GET_MODE_NAME (mode),
9587 (reload_completed ? "after" : "before"),
9588 GET_RTX_NAME (GET_CODE (x)));
9594 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9597 rs6000_mode_dependent_address_p (const_rtx addr,
9598 addr_space_t as ATTRIBUTE_UNUSED)
9600 return rs6000_mode_dependent_address_ptr (addr);
9603 /* Go to LABEL if ADDR (a legitimate address expression)
9604 has an effect that depends on the machine mode it is used for.
9606 On the RS/6000 this is true of all integral offsets (since AltiVec
9607 and VSX modes don't allow them) or is a pre-increment or decrement.
9609 ??? Except that due to conceptual problems in offsettable_address_p
9610 we can't really report the problems of integral offsets. So leave
9611 this assuming that the adjustable offset must be valid for the
9612 sub-words of a TFmode operand, which is what we had before. */
9615 rs6000_mode_dependent_address (const_rtx addr)
9617 switch (GET_CODE (addr))
9620 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9621 is considered a legitimate address before reload, so there
9622 are no offset restrictions in that case. Note that this
9623 condition is safe in strict mode because any address involving
9624 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9625 been rejected as illegitimate. */
9626 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9627 && XEXP (addr, 0) != arg_pointer_rtx
9628 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9630 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9631 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9636 /* Anything in the constant pool is sufficiently aligned that
9637 all bytes have the same high part address. */
9638 return !legitimate_constant_pool_address_p (addr, QImode, false);
9640 /* Auto-increment cases are now treated generically in recog.c. */
9642 return TARGET_UPDATE;
9644 /* AND is only allowed in Altivec loads. */
9655 /* Debug version of rs6000_mode_dependent_address. */
9657 rs6000_debug_mode_dependent_address (const_rtx addr)
9659 bool ret = rs6000_mode_dependent_address (addr);
9661 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9662 ret ? "true" : "false");
9668 /* Implement FIND_BASE_TERM. */
9671 rs6000_find_base_term (rtx op)
9676 if (GET_CODE (base) == CONST)
9677 base = XEXP (base, 0);
9678 if (GET_CODE (base) == PLUS)
9679 base = XEXP (base, 0);
9680 if (GET_CODE (base) == UNSPEC)
9681 switch (XINT (base, 1))
9684 case UNSPEC_MACHOPIC_OFFSET:
9685 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9686 for aliasing purposes. */
9687 return XVECEXP (base, 0, 0);
9693 /* More elaborate version of recog's offsettable_memref_p predicate
9694 that works around the ??? note of rs6000_mode_dependent_address.
9695 In particular it accepts
9697 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9699 in 32-bit mode, that the recog predicate rejects. */
9702 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9709 /* First mimic offsettable_memref_p. */
9710 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9713 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9714 the latter predicate knows nothing about the mode of the memory
9715 reference and, therefore, assumes that it is the largest supported
9716 mode (TFmode). As a consequence, legitimate offsettable memory
9717 references are rejected. rs6000_legitimate_offset_address_p contains
9718 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9719 at least with a little bit of help here given that we know the
9720 actual registers used. */
9721 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9722 || GET_MODE_SIZE (reg_mode) == 4);
9723 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9724 strict, worst_case);
9727 /* Determine the reassociation width to be used in reassociate_bb.
9728 This takes into account how many parallel operations we
9729 can actually do of a given type, and also the latency.
9733 vect add/sub/mul 2/cycle
9734 fp add/sub/mul 2/cycle
9739 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9742 switch (rs6000_tune)
9744 case PROCESSOR_POWER8:
9745 case PROCESSOR_POWER9:
9746 if (DECIMAL_FLOAT_MODE_P (mode))
9748 if (VECTOR_MODE_P (mode))
9750 if (INTEGRAL_MODE_P (mode))
9752 if (FLOAT_MODE_P (mode))
9761 /* Change register usage conditional on target flags. */
9763 rs6000_conditional_register_usage (void)
9767 if (TARGET_DEBUG_TARGET)
9768 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9770 /* Set MQ register fixed (already call_used) so that it will not be
9774 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9776 fixed_regs[13] = call_used_regs[13]
9777 = call_really_used_regs[13] = 1;
9779 /* Conditionally disable FPRs. */
9780 if (TARGET_SOFT_FLOAT)
9781 for (i = 32; i < 64; i++)
9782 fixed_regs[i] = call_used_regs[i]
9783 = call_really_used_regs[i] = 1;
9785 /* The TOC register is not killed across calls in a way that is
9786 visible to the compiler. */
9787 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9788 call_really_used_regs[2] = 0;
9790 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9791 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9793 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9794 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9795 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9796 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9798 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9799 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9800 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9801 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9803 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9804 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9805 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9807 if (!TARGET_ALTIVEC && !TARGET_VSX)
9809 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9810 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9811 call_really_used_regs[VRSAVE_REGNO] = 1;
9814 if (TARGET_ALTIVEC || TARGET_VSX)
9815 global_regs[VSCR_REGNO] = 1;
9817 if (TARGET_ALTIVEC_ABI)
9819 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9820 call_used_regs[i] = call_really_used_regs[i] = 1;
9822 /* AIX reserves VR20:31 in non-extended ABI mode. */
9824 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9825 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9830 /* Output insns to set DEST equal to the constant SOURCE as a series of
9831 lis, ori and shl instructions and return TRUE. */
9834 rs6000_emit_set_const (rtx dest, rtx source)
9836 machine_mode mode = GET_MODE (dest);
9841 gcc_checking_assert (CONST_INT_P (source));
9842 c = INTVAL (source);
9847 emit_insn (gen_rtx_SET (dest, source));
9851 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9853 emit_insn (gen_rtx_SET (copy_rtx (temp),
9854 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9855 emit_insn (gen_rtx_SET (dest,
9856 gen_rtx_IOR (SImode, copy_rtx (temp),
9857 GEN_INT (c & 0xffff))));
9861 if (!TARGET_POWERPC64)
9865 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9867 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9869 emit_move_insn (hi, GEN_INT (c >> 32));
9870 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9871 emit_move_insn (lo, GEN_INT (c));
9874 rs6000_emit_set_long_const (dest, c);
9881 insn = get_last_insn ();
9882 set = single_set (insn);
9883 if (! CONSTANT_P (SET_SRC (set)))
9884 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9889 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9890 Output insns to set DEST equal to the constant C as a series of
9891 lis, ori and shl instructions. */
9894 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9897 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9907 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9908 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9909 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9911 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9912 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9914 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9916 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9917 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9919 emit_move_insn (dest,
9920 gen_rtx_IOR (DImode, copy_rtx (temp),
9923 else if (ud3 == 0 && ud4 == 0)
9925 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9927 gcc_assert (ud2 & 0x8000);
9928 emit_move_insn (copy_rtx (temp),
9929 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9931 emit_move_insn (copy_rtx (temp),
9932 gen_rtx_IOR (DImode, copy_rtx (temp),
9934 emit_move_insn (dest,
9935 gen_rtx_ZERO_EXTEND (DImode,
9936 gen_lowpart (SImode,
9939 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9940 || (ud4 == 0 && ! (ud3 & 0x8000)))
9942 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9944 emit_move_insn (copy_rtx (temp),
9945 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9947 emit_move_insn (copy_rtx (temp),
9948 gen_rtx_IOR (DImode, copy_rtx (temp),
9950 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9951 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9954 emit_move_insn (dest,
9955 gen_rtx_IOR (DImode, copy_rtx (temp),
9960 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9962 emit_move_insn (copy_rtx (temp),
9963 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9965 emit_move_insn (copy_rtx (temp),
9966 gen_rtx_IOR (DImode, copy_rtx (temp),
9969 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9970 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9973 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9974 gen_rtx_IOR (DImode, copy_rtx (temp),
9975 GEN_INT (ud2 << 16)));
9977 emit_move_insn (dest,
9978 gen_rtx_IOR (DImode, copy_rtx (temp),
9983 /* Helper for the following. Get rid of [r+r] memory refs
9984 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9987 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9989 if (GET_CODE (operands[0]) == MEM
9990 && GET_CODE (XEXP (operands[0], 0)) != REG
9991 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9992 GET_MODE (operands[0]), false))
9994 = replace_equiv_address (operands[0],
9995 copy_addr_to_reg (XEXP (operands[0], 0)));
9997 if (GET_CODE (operands[1]) == MEM
9998 && GET_CODE (XEXP (operands[1], 0)) != REG
9999 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10000 GET_MODE (operands[1]), false))
10002 = replace_equiv_address (operands[1],
10003 copy_addr_to_reg (XEXP (operands[1], 0)));
10006 /* Generate a vector of constants to permute MODE for a little-endian
10007 storage operation by swapping the two halves of a vector. */
10009 rs6000_const_vec (machine_mode mode)
10037 v = rtvec_alloc (subparts);
10039 for (i = 0; i < subparts / 2; ++i)
10040 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10041 for (i = subparts / 2; i < subparts; ++i)
10042 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10047 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10048 store operation. */
10050 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10052 /* Scalar permutations are easier to express in integer modes rather than
10053 floating-point modes, so cast them here. We use V1TImode instead
10054 of TImode to ensure that the values don't go through GPRs. */
10055 if (FLOAT128_VECTOR_P (mode))
10057 dest = gen_lowpart (V1TImode, dest);
10058 source = gen_lowpart (V1TImode, source);
10062 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10064 if (mode == TImode || mode == V1TImode)
10065 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10069 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10070 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10074 /* Emit a little-endian load from vector memory location SOURCE to VSX
10075 register DEST in mode MODE. The load is done with two permuting
10076 insn's that represent an lxvd2x and xxpermdi. */
10078 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10080 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10082 if (mode == TImode || mode == V1TImode)
10085 dest = gen_lowpart (V2DImode, dest);
10086 source = adjust_address (source, V2DImode, 0);
10089 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10090 rs6000_emit_le_vsx_permute (tmp, source, mode);
10091 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10094 /* Emit a little-endian store to vector memory location DEST from VSX
10095 register SOURCE in mode MODE. The store is done with two permuting
10096 insn's that represent an xxpermdi and an stxvd2x. */
10098 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10100 /* This should never be called during or after LRA, because it does
10101 not re-permute the source register. It is intended only for use
10103 gcc_assert (!lra_in_progress && !reload_completed);
10105 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10107 if (mode == TImode || mode == V1TImode)
10110 dest = adjust_address (dest, V2DImode, 0);
10111 source = gen_lowpart (V2DImode, source);
10114 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10115 rs6000_emit_le_vsx_permute (tmp, source, mode);
10116 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10119 /* Emit a sequence representing a little-endian VSX load or store,
10120 moving data from SOURCE to DEST in mode MODE. This is done
10121 separately from rs6000_emit_move to ensure it is called only
10122 during expand. LE VSX loads and stores introduced later are
10123 handled with a split. The expand-time RTL generation allows
10124 us to optimize away redundant pairs of register-permutes. */
10126 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10128 gcc_assert (!BYTES_BIG_ENDIAN
10129 && VECTOR_MEM_VSX_P (mode)
10130 && !TARGET_P9_VECTOR
10131 && !gpr_or_gpr_p (dest, source)
10132 && (MEM_P (source) ^ MEM_P (dest)));
10134 if (MEM_P (source))
10136 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10137 rs6000_emit_le_vsx_load (dest, source, mode);
10141 if (!REG_P (source))
10142 source = force_reg (mode, source);
10143 rs6000_emit_le_vsx_store (dest, source, mode);
10147 /* Return whether a SFmode or SImode move can be done without converting one
10148 mode to another. This arrises when we have:
10150 (SUBREG:SF (REG:SI ...))
10151 (SUBREG:SI (REG:SF ...))
10153 and one of the values is in a floating point/vector register, where SFmode
10154 scalars are stored in DFmode format. */
10157 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10159 if (TARGET_ALLOW_SF_SUBREG)
10162 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10165 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10168 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10169 if (SUBREG_P (dest))
10171 rtx dest_subreg = SUBREG_REG (dest);
10172 rtx src_subreg = SUBREG_REG (src);
10173 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10180 /* Helper function to change moves with:
10182 (SUBREG:SF (REG:SI)) and
10183 (SUBREG:SI (REG:SF))
10185 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10186 values are stored as DFmode values in the VSX registers. We need to convert
10187 the bits before we can use a direct move or operate on the bits in the
10188 vector register as an integer type.
10190 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10193 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10195 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10196 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10197 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10199 rtx inner_source = SUBREG_REG (source);
10200 machine_mode inner_mode = GET_MODE (inner_source);
10202 if (mode == SImode && inner_mode == SFmode)
10204 emit_insn (gen_movsi_from_sf (dest, inner_source));
10208 if (mode == SFmode && inner_mode == SImode)
10210 emit_insn (gen_movsf_from_si (dest, inner_source));
10218 /* Emit a move from SOURCE to DEST in mode MODE. */
10220 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10223 operands[0] = dest;
10224 operands[1] = source;
10226 if (TARGET_DEBUG_ADDR)
10229 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10230 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10231 GET_MODE_NAME (mode),
10234 can_create_pseudo_p ());
10236 fprintf (stderr, "source:\n");
10237 debug_rtx (source);
10240 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10241 if (CONST_WIDE_INT_P (operands[1])
10242 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10244 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10245 gcc_unreachable ();
10248 #ifdef HAVE_AS_GNU_ATTRIBUTE
10249 /* If we use a long double type, set the flags in .gnu_attribute that say
10250 what the long double type is. This is to allow the linker's warning
10251 message for the wrong long double to be useful, even if the function does
10252 not do a call (for example, doing a 128-bit add on power9 if the long
10253 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
10254 used if they aren't the default long dobule type. */
10255 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
10257 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
10258 rs6000_passes_float = rs6000_passes_long_double = true;
10260 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
10261 rs6000_passes_float = rs6000_passes_long_double = true;
10265 /* See if we need to special case SImode/SFmode SUBREG moves. */
10266 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10267 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10270 /* Check if GCC is setting up a block move that will end up using FP
10271 registers as temporaries. We must make sure this is acceptable. */
10272 if (GET_CODE (operands[0]) == MEM
10273 && GET_CODE (operands[1]) == MEM
10275 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10276 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10277 && ! (rs6000_slow_unaligned_access (SImode,
10278 (MEM_ALIGN (operands[0]) > 32
10279 ? 32 : MEM_ALIGN (operands[0])))
10280 || rs6000_slow_unaligned_access (SImode,
10281 (MEM_ALIGN (operands[1]) > 32
10282 ? 32 : MEM_ALIGN (operands[1]))))
10283 && ! MEM_VOLATILE_P (operands [0])
10284 && ! MEM_VOLATILE_P (operands [1]))
10286 emit_move_insn (adjust_address (operands[0], SImode, 0),
10287 adjust_address (operands[1], SImode, 0));
10288 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10289 adjust_address (copy_rtx (operands[1]), SImode, 4));
10293 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10294 && !gpc_reg_operand (operands[1], mode))
10295 operands[1] = force_reg (mode, operands[1]);
10297 /* Recognize the case where operand[1] is a reference to thread-local
10298 data and load its address to a register. */
10299 if (tls_referenced_p (operands[1]))
10301 enum tls_model model;
10302 rtx tmp = operands[1];
10305 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10307 addend = XEXP (XEXP (tmp, 0), 1);
10308 tmp = XEXP (XEXP (tmp, 0), 0);
10311 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10312 model = SYMBOL_REF_TLS_MODEL (tmp);
10313 gcc_assert (model != 0);
10315 tmp = rs6000_legitimize_tls_address (tmp, model);
10318 tmp = gen_rtx_PLUS (mode, tmp, addend);
10319 tmp = force_operand (tmp, operands[0]);
10324 /* 128-bit constant floating-point values on Darwin should really be loaded
10325 as two parts. However, this premature splitting is a problem when DFmode
10326 values can go into Altivec registers. */
10327 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10328 && GET_CODE (operands[1]) == CONST_DOUBLE)
10330 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10331 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10333 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10334 GET_MODE_SIZE (DFmode)),
10335 simplify_gen_subreg (DFmode, operands[1], mode,
10336 GET_MODE_SIZE (DFmode)),
10341 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10342 p1:SD) if p1 is not of floating point class and p0 is spilled as
10343 we can have no analogous movsd_store for this. */
10344 if (lra_in_progress && mode == DDmode
10345 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10346 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10347 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10348 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10351 int regno = REGNO (SUBREG_REG (operands[1]));
10353 if (regno >= FIRST_PSEUDO_REGISTER)
10355 cl = reg_preferred_class (regno);
10356 regno = reg_renumber[regno];
10358 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10360 if (regno >= 0 && ! FP_REGNO_P (regno))
10363 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10364 operands[1] = SUBREG_REG (operands[1]);
10367 if (lra_in_progress
10369 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10370 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10371 && (REG_P (operands[1])
10372 || (GET_CODE (operands[1]) == SUBREG
10373 && REG_P (SUBREG_REG (operands[1])))))
10375 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10376 ? SUBREG_REG (operands[1]) : operands[1]);
10379 if (regno >= FIRST_PSEUDO_REGISTER)
10381 cl = reg_preferred_class (regno);
10382 gcc_assert (cl != NO_REGS);
10383 regno = reg_renumber[regno];
10385 regno = ira_class_hard_regs[cl][0];
10387 if (FP_REGNO_P (regno))
10389 if (GET_MODE (operands[0]) != DDmode)
10390 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10391 emit_insn (gen_movsd_store (operands[0], operands[1]));
10393 else if (INT_REGNO_P (regno))
10394 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10399 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10400 p:DD)) if p0 is not of floating point class and p1 is spilled as
10401 we can have no analogous movsd_load for this. */
10402 if (lra_in_progress && mode == DDmode
10403 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10404 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10405 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10406 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10409 int regno = REGNO (SUBREG_REG (operands[0]));
10411 if (regno >= FIRST_PSEUDO_REGISTER)
10413 cl = reg_preferred_class (regno);
10414 regno = reg_renumber[regno];
10416 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10418 if (regno >= 0 && ! FP_REGNO_P (regno))
10421 operands[0] = SUBREG_REG (operands[0]);
10422 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10425 if (lra_in_progress
10427 && (REG_P (operands[0])
10428 || (GET_CODE (operands[0]) == SUBREG
10429 && REG_P (SUBREG_REG (operands[0]))))
10430 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10431 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10433 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10434 ? SUBREG_REG (operands[0]) : operands[0]);
10437 if (regno >= FIRST_PSEUDO_REGISTER)
10439 cl = reg_preferred_class (regno);
10440 gcc_assert (cl != NO_REGS);
10441 regno = reg_renumber[regno];
10443 regno = ira_class_hard_regs[cl][0];
10445 if (FP_REGNO_P (regno))
10447 if (GET_MODE (operands[1]) != DDmode)
10448 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10449 emit_insn (gen_movsd_load (operands[0], operands[1]));
10451 else if (INT_REGNO_P (regno))
10452 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10458 /* FIXME: In the long term, this switch statement should go away
10459 and be replaced by a sequence of tests based on things like
10465 if (CONSTANT_P (operands[1])
10466 && GET_CODE (operands[1]) != CONST_INT)
10467 operands[1] = force_const_mem (mode, operands[1]);
10474 if (FLOAT128_2REG_P (mode))
10475 rs6000_eliminate_indexed_memrefs (operands);
10482 if (CONSTANT_P (operands[1])
10483 && ! easy_fp_constant (operands[1], mode))
10484 operands[1] = force_const_mem (mode, operands[1]);
10494 if (CONSTANT_P (operands[1])
10495 && !easy_vector_constant (operands[1], mode))
10496 operands[1] = force_const_mem (mode, operands[1]);
10501 /* Use default pattern for address of ELF small data */
10504 && DEFAULT_ABI == ABI_V4
10505 && (GET_CODE (operands[1]) == SYMBOL_REF
10506 || GET_CODE (operands[1]) == CONST)
10507 && small_data_operand (operands[1], mode))
10509 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10513 if (DEFAULT_ABI == ABI_V4
10514 && mode == Pmode && mode == SImode
10515 && flag_pic == 1 && got_operand (operands[1], mode))
10517 emit_insn (gen_movsi_got (operands[0], operands[1]));
10521 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10525 && CONSTANT_P (operands[1])
10526 && GET_CODE (operands[1]) != HIGH
10527 && GET_CODE (operands[1]) != CONST_INT)
10529 rtx target = (!can_create_pseudo_p ()
10531 : gen_reg_rtx (mode));
10533 /* If this is a function address on -mcall-aixdesc,
10534 convert it to the address of the descriptor. */
10535 if (DEFAULT_ABI == ABI_AIX
10536 && GET_CODE (operands[1]) == SYMBOL_REF
10537 && XSTR (operands[1], 0)[0] == '.')
10539 const char *name = XSTR (operands[1], 0);
10541 while (*name == '.')
10543 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10544 CONSTANT_POOL_ADDRESS_P (new_ref)
10545 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10546 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10547 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10548 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10549 operands[1] = new_ref;
10552 if (DEFAULT_ABI == ABI_DARWIN)
10555 if (MACHO_DYNAMIC_NO_PIC_P)
10557 /* Take care of any required data indirection. */
10558 operands[1] = rs6000_machopic_legitimize_pic_address (
10559 operands[1], mode, operands[0]);
10560 if (operands[0] != operands[1])
10561 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10565 emit_insn (gen_macho_high (target, operands[1]));
10566 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10570 emit_insn (gen_elf_high (target, operands[1]));
10571 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10575 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10576 and we have put it in the TOC, we just need to make a TOC-relative
10577 reference to it. */
10579 && GET_CODE (operands[1]) == SYMBOL_REF
10580 && use_toc_relative_ref (operands[1], mode))
10581 operands[1] = create_TOC_reference (operands[1], operands[0]);
10582 else if (mode == Pmode
10583 && CONSTANT_P (operands[1])
10584 && GET_CODE (operands[1]) != HIGH
10585 && ((GET_CODE (operands[1]) != CONST_INT
10586 && ! easy_fp_constant (operands[1], mode))
10587 || (GET_CODE (operands[1]) == CONST_INT
10588 && (num_insns_constant (operands[1], mode)
10589 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10590 || (GET_CODE (operands[0]) == REG
10591 && FP_REGNO_P (REGNO (operands[0]))))
10592 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10593 && (TARGET_CMODEL == CMODEL_SMALL
10594 || can_create_pseudo_p ()
10595 || (REG_P (operands[0])
10596 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10600 /* Darwin uses a special PIC legitimizer. */
10601 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10604 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10606 if (operands[0] != operands[1])
10607 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10612 /* If we are to limit the number of things we put in the TOC and
10613 this is a symbol plus a constant we can add in one insn,
10614 just put the symbol in the TOC and add the constant. */
10615 if (GET_CODE (operands[1]) == CONST
10616 && TARGET_NO_SUM_IN_TOC
10617 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10618 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10619 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10620 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10621 && ! side_effects_p (operands[0]))
10624 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10625 rtx other = XEXP (XEXP (operands[1], 0), 1);
10627 sym = force_reg (mode, sym);
10628 emit_insn (gen_add3_insn (operands[0], sym, other));
10632 operands[1] = force_const_mem (mode, operands[1]);
10635 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10636 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10638 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10640 operands[1] = gen_const_mem (mode, tocref);
10641 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10647 if (!VECTOR_MEM_VSX_P (TImode))
10648 rs6000_eliminate_indexed_memrefs (operands);
10652 rs6000_eliminate_indexed_memrefs (operands);
10656 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10659 /* Above, we may have called force_const_mem which may have returned
10660 an invalid address. If we can, fix this up; otherwise, reload will
10661 have to deal with it. */
10662 if (GET_CODE (operands[1]) == MEM)
10663 operands[1] = validize_mem (operands[1]);
10665 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10668 /* Nonzero if we can use a floating-point register to pass this arg. */
10669 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10670 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10671 && (CUM)->fregno <= FP_ARG_MAX_REG \
10672 && TARGET_HARD_FLOAT)
10674 /* Nonzero if we can use an AltiVec register to pass this arg. */
10675 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10676 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10677 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10678 && TARGET_ALTIVEC_ABI \
10681 /* Walk down the type tree of TYPE counting consecutive base elements.
10682 If *MODEP is VOIDmode, then set it to the first valid floating point
10683 or vector type. If a non-floating point or vector type is found, or
10684 if a floating point or vector type that doesn't match a non-VOIDmode
10685 *MODEP is found, then return -1, otherwise return the count in the
10689 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10692 HOST_WIDE_INT size;
10694 switch (TREE_CODE (type))
10697 mode = TYPE_MODE (type);
10698 if (!SCALAR_FLOAT_MODE_P (mode))
10701 if (*modep == VOIDmode)
10704 if (*modep == mode)
10710 mode = TYPE_MODE (TREE_TYPE (type));
10711 if (!SCALAR_FLOAT_MODE_P (mode))
10714 if (*modep == VOIDmode)
10717 if (*modep == mode)
10723 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10726 /* Use V4SImode as representative of all 128-bit vector types. */
10727 size = int_size_in_bytes (type);
10737 if (*modep == VOIDmode)
10740 /* Vector modes are considered to be opaque: two vectors are
10741 equivalent for the purposes of being homogeneous aggregates
10742 if they are the same size. */
10743 if (*modep == mode)
10751 tree index = TYPE_DOMAIN (type);
10753 /* Can't handle incomplete types nor sizes that are not
10755 if (!COMPLETE_TYPE_P (type)
10756 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10759 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10762 || !TYPE_MAX_VALUE (index)
10763 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10764 || !TYPE_MIN_VALUE (index)
10765 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10769 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10770 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10772 /* There must be no padding. */
10773 if (wi::to_wide (TYPE_SIZE (type))
10774 != count * GET_MODE_BITSIZE (*modep))
10786 /* Can't handle incomplete types nor sizes that are not
10788 if (!COMPLETE_TYPE_P (type)
10789 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10792 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10794 if (TREE_CODE (field) != FIELD_DECL)
10797 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10800 count += sub_count;
10803 /* There must be no padding. */
10804 if (wi::to_wide (TYPE_SIZE (type))
10805 != count * GET_MODE_BITSIZE (*modep))
10812 case QUAL_UNION_TYPE:
10814 /* These aren't very interesting except in a degenerate case. */
10819 /* Can't handle incomplete types nor sizes that are not
10821 if (!COMPLETE_TYPE_P (type)
10822 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10825 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10827 if (TREE_CODE (field) != FIELD_DECL)
10830 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10833 count = count > sub_count ? count : sub_count;
10836 /* There must be no padding. */
10837 if (wi::to_wide (TYPE_SIZE (type))
10838 != count * GET_MODE_BITSIZE (*modep))
10851 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10852 float or vector aggregate that shall be passed in FP/vector registers
10853 according to the ELFv2 ABI, return the homogeneous element mode in
10854 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10856 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10859 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10860 machine_mode *elt_mode,
10863 /* Note that we do not accept complex types at the top level as
10864 homogeneous aggregates; these types are handled via the
10865 targetm.calls.split_complex_arg mechanism. Complex types
10866 can be elements of homogeneous aggregates, however. */
10867 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10868 && AGGREGATE_TYPE_P (type))
10870 machine_mode field_mode = VOIDmode;
10871 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10873 if (field_count > 0)
10875 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
10876 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
10878 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10879 up to AGGR_ARG_NUM_REG registers. */
10880 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
10883 *elt_mode = field_mode;
10885 *n_elts = field_count;
10898 /* Return a nonzero value to say to return the function value in
10899 memory, just as large structures are always returned. TYPE will be
10900 the data type of the value, and FNTYPE will be the type of the
10901 function doing the returning, or @code{NULL} for libcalls.
10903 The AIX ABI for the RS/6000 specifies that all structures are
10904 returned in memory. The Darwin ABI does the same.
10906 For the Darwin 64 Bit ABI, a function result can be returned in
10907 registers or in memory, depending on the size of the return data
10908 type. If it is returned in registers, the value occupies the same
10909 registers as it would if it were the first and only function
10910 argument. Otherwise, the function places its result in memory at
10911 the location pointed to by GPR3.
10913 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10914 but a draft put them in memory, and GCC used to implement the draft
10915 instead of the final standard. Therefore, aix_struct_return
10916 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10917 compatibility can change DRAFT_V4_STRUCT_RET to override the
10918 default, and -m switches get the final word. See
10919 rs6000_option_override_internal for more details.
10921 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10922 long double support is enabled. These values are returned in memory.
10924 int_size_in_bytes returns -1 for variable size objects, which go in
10925 memory always. The cast to unsigned makes -1 > 8. */
10928 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10930 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10932 && rs6000_darwin64_abi
10933 && TREE_CODE (type) == RECORD_TYPE
10934 && int_size_in_bytes (type) > 0)
10936 CUMULATIVE_ARGS valcum;
10940 valcum.fregno = FP_ARG_MIN_REG;
10941 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10942 /* Do a trial code generation as if this were going to be passed
10943 as an argument; if any part goes in memory, we return NULL. */
10944 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10947 /* Otherwise fall through to more conventional ABI rules. */
10950 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10951 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10955 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10956 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10957 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10960 if (AGGREGATE_TYPE_P (type)
10961 && (aix_struct_return
10962 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10965 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10966 modes only exist for GCC vector types if -maltivec. */
10967 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10968 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10971 /* Return synthetic vectors in memory. */
10972 if (TREE_CODE (type) == VECTOR_TYPE
10973 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10975 static bool warned_for_return_big_vectors = false;
10976 if (!warned_for_return_big_vectors)
10978 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10979 "non-standard ABI extension with no compatibility "
10981 warned_for_return_big_vectors = true;
10986 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10987 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10993 /* Specify whether values returned in registers should be at the most
10994 significant end of a register. We want aggregates returned by
10995 value to match the way aggregates are passed to functions. */
10998 rs6000_return_in_msb (const_tree valtype)
11000 return (DEFAULT_ABI == ABI_ELFv2
11001 && BYTES_BIG_ENDIAN
11002 && AGGREGATE_TYPE_P (valtype)
11003 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11007 #ifdef HAVE_AS_GNU_ATTRIBUTE
11008 /* Return TRUE if a call to function FNDECL may be one that
11009 potentially affects the function calling ABI of the object file. */
11012 call_ABI_of_interest (tree fndecl)
11014 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11016 struct cgraph_node *c_node;
11018 /* Libcalls are always interesting. */
11019 if (fndecl == NULL_TREE)
11022 /* Any call to an external function is interesting. */
11023 if (DECL_EXTERNAL (fndecl))
11026 /* Interesting functions that we are emitting in this object file. */
11027 c_node = cgraph_node::get (fndecl);
11028 c_node = c_node->ultimate_alias_target ();
11029 return !c_node->only_called_directly_p ();
11035 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11036 for a call to a function whose data type is FNTYPE.
11037 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11039 For incoming args we set the number of arguments in the prototype large
11040 so we never return a PARALLEL. */
11043 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11044 rtx libname ATTRIBUTE_UNUSED, int incoming,
11045 int libcall, int n_named_args,
11046 tree fndecl ATTRIBUTE_UNUSED,
11047 machine_mode return_mode ATTRIBUTE_UNUSED)
11049 static CUMULATIVE_ARGS zero_cumulative;
11051 *cum = zero_cumulative;
11053 cum->fregno = FP_ARG_MIN_REG;
11054 cum->vregno = ALTIVEC_ARG_MIN_REG;
11055 cum->prototype = (fntype && prototype_p (fntype));
11056 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11057 ? CALL_LIBCALL : CALL_NORMAL);
11058 cum->sysv_gregno = GP_ARG_MIN_REG;
11059 cum->stdarg = stdarg_p (fntype);
11060 cum->libcall = libcall;
11062 cum->nargs_prototype = 0;
11063 if (incoming || cum->prototype)
11064 cum->nargs_prototype = n_named_args;
11066 /* Check for a longcall attribute. */
11067 if ((!fntype && rs6000_default_long_calls)
11069 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11070 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11071 cum->call_cookie |= CALL_LONG;
11073 if (TARGET_DEBUG_ARG)
11075 fprintf (stderr, "\ninit_cumulative_args:");
11078 tree ret_type = TREE_TYPE (fntype);
11079 fprintf (stderr, " ret code = %s,",
11080 get_tree_code_name (TREE_CODE (ret_type)));
11083 if (cum->call_cookie & CALL_LONG)
11084 fprintf (stderr, " longcall,");
11086 fprintf (stderr, " proto = %d, nargs = %d\n",
11087 cum->prototype, cum->nargs_prototype);
11090 #ifdef HAVE_AS_GNU_ATTRIBUTE
11091 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11093 cum->escapes = call_ABI_of_interest (fndecl);
11100 return_type = TREE_TYPE (fntype);
11101 return_mode = TYPE_MODE (return_type);
11104 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11106 if (return_type != NULL)
11108 if (TREE_CODE (return_type) == RECORD_TYPE
11109 && TYPE_TRANSPARENT_AGGR (return_type))
11111 return_type = TREE_TYPE (first_field (return_type));
11112 return_mode = TYPE_MODE (return_type);
11114 if (AGGREGATE_TYPE_P (return_type)
11115 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11117 rs6000_returns_struct = true;
11119 if (SCALAR_FLOAT_MODE_P (return_mode))
11121 rs6000_passes_float = true;
11122 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11123 && (FLOAT128_IBM_P (return_mode)
11124 || FLOAT128_IEEE_P (return_mode)
11125 || (return_type != NULL
11126 && (TYPE_MAIN_VARIANT (return_type)
11127 == long_double_type_node))))
11128 rs6000_passes_long_double = true;
11130 /* Note if we passed or return a IEEE 128-bit type. We changed
11131 the mangling for these types, and we may need to make an alias
11132 with the old mangling. */
11133 if (FLOAT128_IEEE_P (return_mode))
11134 rs6000_passes_ieee128 = true;
11136 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
11137 rs6000_passes_vector = true;
11144 && TARGET_ALTIVEC_ABI
11145 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11147 error ("cannot return value in vector register because"
11148 " altivec instructions are disabled, use %qs"
11149 " to enable them", "-maltivec");
11153 /* The mode the ABI uses for a word. This is not the same as word_mode
11154 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11156 static scalar_int_mode
11157 rs6000_abi_word_mode (void)
11159 return TARGET_32BIT ? SImode : DImode;
11162 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11164 rs6000_offload_options (void)
11167 return xstrdup ("-foffload-abi=lp64");
11169 return xstrdup ("-foffload-abi=ilp32");
11172 /* On rs6000, function arguments are promoted, as are function return
11175 static machine_mode
11176 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11178 int *punsignedp ATTRIBUTE_UNUSED,
11181 PROMOTE_MODE (mode, *punsignedp, type);
11186 /* Return true if TYPE must be passed on the stack and not in registers. */
11189 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11191 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11192 return must_pass_in_stack_var_size (mode, type);
11194 return must_pass_in_stack_var_size_or_pad (mode, type);
11198 is_complex_IBM_long_double (machine_mode mode)
11200 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
11203 /* Whether ABI_V4 passes MODE args to a function in floating point
11207 abi_v4_pass_in_fpr (machine_mode mode, bool named)
11209 if (!TARGET_HARD_FLOAT)
11211 if (mode == DFmode)
11213 if (mode == SFmode && named)
11215 /* ABI_V4 passes complex IBM long double in 8 gprs.
11216 Stupid, but we can't change the ABI now. */
11217 if (is_complex_IBM_long_double (mode))
11219 if (FLOAT128_2REG_P (mode))
11221 if (DECIMAL_FLOAT_MODE_P (mode))
11226 /* Implement TARGET_FUNCTION_ARG_PADDING.
11228 For the AIX ABI structs are always stored left shifted in their
11231 static pad_direction
11232 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11234 #ifndef AGGREGATE_PADDING_FIXED
11235 #define AGGREGATE_PADDING_FIXED 0
11237 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11238 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11241 if (!AGGREGATE_PADDING_FIXED)
11243 /* GCC used to pass structures of the same size as integer types as
11244 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11245 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11246 passed padded downward, except that -mstrict-align further
11247 muddied the water in that multi-component structures of 2 and 4
11248 bytes in size were passed padded upward.
11250 The following arranges for best compatibility with previous
11251 versions of gcc, but removes the -mstrict-align dependency. */
11252 if (BYTES_BIG_ENDIAN)
11254 HOST_WIDE_INT size = 0;
11256 if (mode == BLKmode)
11258 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11259 size = int_size_in_bytes (type);
11262 size = GET_MODE_SIZE (mode);
11264 if (size == 1 || size == 2 || size == 4)
11265 return PAD_DOWNWARD;
11270 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11272 if (type != 0 && AGGREGATE_TYPE_P (type))
11276 /* Fall back to the default. */
11277 return default_function_arg_padding (mode, type);
11280 /* If defined, a C expression that gives the alignment boundary, in bits,
11281 of an argument with the specified mode and type. If it is not defined,
11282 PARM_BOUNDARY is used for all arguments.
11284 V.4 wants long longs and doubles to be double word aligned. Just
11285 testing the mode size is a boneheaded way to do this as it means
11286 that other types such as complex int are also double word aligned.
11287 However, we're stuck with this because changing the ABI might break
11288 existing library interfaces.
11290 Quadword align Altivec/VSX vectors.
11291 Quadword align large synthetic vector types. */
11293 static unsigned int
11294 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11296 machine_mode elt_mode;
11299 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11301 if (DEFAULT_ABI == ABI_V4
11302 && (GET_MODE_SIZE (mode) == 8
11303 || (TARGET_HARD_FLOAT
11304 && !is_complex_IBM_long_double (mode)
11305 && FLOAT128_2REG_P (mode))))
11307 else if (FLOAT128_VECTOR_P (mode))
11309 else if (type && TREE_CODE (type) == VECTOR_TYPE
11310 && int_size_in_bytes (type) >= 8
11311 && int_size_in_bytes (type) < 16)
11313 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11314 || (type && TREE_CODE (type) == VECTOR_TYPE
11315 && int_size_in_bytes (type) >= 16))
11318 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11319 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11320 -mcompat-align-parm is used. */
11321 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11322 || DEFAULT_ABI == ABI_ELFv2)
11323 && type && TYPE_ALIGN (type) > 64)
11325 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11326 or homogeneous float/vector aggregates here. We already handled
11327 vector aggregates above, but still need to check for float here. */
11328 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11329 && !SCALAR_FLOAT_MODE_P (elt_mode));
11331 /* We used to check for BLKmode instead of the above aggregate type
11332 check. Warn when this results in any difference to the ABI. */
11333 if (aggregate_p != (mode == BLKmode))
11335 static bool warned;
11336 if (!warned && warn_psabi)
11339 inform (input_location,
11340 "the ABI of passing aggregates with %d-byte alignment"
11341 " has changed in GCC 5",
11342 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11350 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11351 implement the "aggregate type" check as a BLKmode check here; this
11352 means certain aggregate types are in fact not aligned. */
11353 if (TARGET_MACHO && rs6000_darwin64_abi
11355 && type && TYPE_ALIGN (type) > 64)
11358 return PARM_BOUNDARY;
11361 /* The offset in words to the start of the parameter save area. */
11363 static unsigned int
11364 rs6000_parm_offset (void)
11366 return (DEFAULT_ABI == ABI_V4 ? 2
11367 : DEFAULT_ABI == ABI_ELFv2 ? 4
11371 /* For a function parm of MODE and TYPE, return the starting word in
11372 the parameter area. NWORDS of the parameter area are already used. */
11374 static unsigned int
11375 rs6000_parm_start (machine_mode mode, const_tree type,
11376 unsigned int nwords)
11378 unsigned int align;
11380 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11381 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11384 /* Compute the size (in words) of a function argument. */
11386 static unsigned long
11387 rs6000_arg_size (machine_mode mode, const_tree type)
11389 unsigned long size;
11391 if (mode != BLKmode)
11392 size = GET_MODE_SIZE (mode);
11394 size = int_size_in_bytes (type);
11397 return (size + 3) >> 2;
11399 return (size + 7) >> 3;
11402 /* Use this to flush pending int fields. */
11405 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11406 HOST_WIDE_INT bitpos, int final)
11408 unsigned int startbit, endbit;
11409 int intregs, intoffset;
11411 /* Handle the situations where a float is taking up the first half
11412 of the GPR, and the other half is empty (typically due to
11413 alignment restrictions). We can detect this by a 8-byte-aligned
11414 int field, or by seeing that this is the final flush for this
11415 argument. Count the word and continue on. */
11416 if (cum->floats_in_gpr == 1
11417 && (cum->intoffset % 64 == 0
11418 || (cum->intoffset == -1 && final)))
11421 cum->floats_in_gpr = 0;
11424 if (cum->intoffset == -1)
11427 intoffset = cum->intoffset;
11428 cum->intoffset = -1;
11429 cum->floats_in_gpr = 0;
11431 if (intoffset % BITS_PER_WORD != 0)
11433 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11434 if (!int_mode_for_size (bits, 0).exists ())
11436 /* We couldn't find an appropriate mode, which happens,
11437 e.g., in packed structs when there are 3 bytes to load.
11438 Back intoffset back to the beginning of the word in this
11440 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11444 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11445 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11446 intregs = (endbit - startbit) / BITS_PER_WORD;
11447 cum->words += intregs;
11448 /* words should be unsigned. */
11449 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11451 int pad = (endbit/BITS_PER_WORD) - cum->words;
11456 /* The darwin64 ABI calls for us to recurse down through structs,
11457 looking for elements passed in registers. Unfortunately, we have
11458 to track int register count here also because of misalignments
11459 in powerpc alignment mode. */
11462 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11464 HOST_WIDE_INT startbitpos)
11468 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11469 if (TREE_CODE (f) == FIELD_DECL)
11471 HOST_WIDE_INT bitpos = startbitpos;
11472 tree ftype = TREE_TYPE (f);
11474 if (ftype == error_mark_node)
11476 mode = TYPE_MODE (ftype);
11478 if (DECL_SIZE (f) != 0
11479 && tree_fits_uhwi_p (bit_position (f)))
11480 bitpos += int_bit_position (f);
11482 /* ??? FIXME: else assume zero offset. */
11484 if (TREE_CODE (ftype) == RECORD_TYPE)
11485 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11486 else if (USE_FP_FOR_ARG_P (cum, mode))
11488 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11489 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11490 cum->fregno += n_fpregs;
11491 /* Single-precision floats present a special problem for
11492 us, because they are smaller than an 8-byte GPR, and so
11493 the structure-packing rules combined with the standard
11494 varargs behavior mean that we want to pack float/float
11495 and float/int combinations into a single register's
11496 space. This is complicated by the arg advance flushing,
11497 which works on arbitrarily large groups of int-type
11499 if (mode == SFmode)
11501 if (cum->floats_in_gpr == 1)
11503 /* Two floats in a word; count the word and reset
11504 the float count. */
11506 cum->floats_in_gpr = 0;
11508 else if (bitpos % 64 == 0)
11510 /* A float at the beginning of an 8-byte word;
11511 count it and put off adjusting cum->words until
11512 we see if a arg advance flush is going to do it
11514 cum->floats_in_gpr++;
11518 /* The float is at the end of a word, preceded
11519 by integer fields, so the arg advance flush
11520 just above has already set cum->words and
11521 everything is taken care of. */
11525 cum->words += n_fpregs;
11527 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11529 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11533 else if (cum->intoffset == -1)
11534 cum->intoffset = bitpos;
11538 /* Check for an item that needs to be considered specially under the darwin 64
11539 bit ABI. These are record types where the mode is BLK or the structure is
11540 8 bytes in size. */
11542 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11544 return rs6000_darwin64_abi
11545 && ((mode == BLKmode
11546 && TREE_CODE (type) == RECORD_TYPE
11547 && int_size_in_bytes (type) > 0)
11548 || (type && TREE_CODE (type) == RECORD_TYPE
11549 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11552 /* Update the data in CUM to advance over an argument
11553 of mode MODE and data type TYPE.
11554 (TYPE is null for libcalls where that information may not be available.)
11556 Note that for args passed by reference, function_arg will be called
11557 with MODE and TYPE set to that of the pointer to the arg, not the arg
11561 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11562 const_tree type, bool named, int depth)
11564 machine_mode elt_mode;
11567 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11569 /* Only tick off an argument if we're not recursing. */
11571 cum->nargs_prototype--;
11573 #ifdef HAVE_AS_GNU_ATTRIBUTE
11574 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11577 if (SCALAR_FLOAT_MODE_P (mode))
11579 rs6000_passes_float = true;
11580 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11581 && (FLOAT128_IBM_P (mode)
11582 || FLOAT128_IEEE_P (mode)
11584 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11585 rs6000_passes_long_double = true;
11587 /* Note if we passed or return a IEEE 128-bit type. We changed the
11588 mangling for these types, and we may need to make an alias with
11589 the old mangling. */
11590 if (FLOAT128_IEEE_P (mode))
11591 rs6000_passes_ieee128 = true;
11593 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11594 rs6000_passes_vector = true;
11598 if (TARGET_ALTIVEC_ABI
11599 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11600 || (type && TREE_CODE (type) == VECTOR_TYPE
11601 && int_size_in_bytes (type) == 16)))
11603 bool stack = false;
11605 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11607 cum->vregno += n_elts;
11609 if (!TARGET_ALTIVEC)
11610 error ("cannot pass argument in vector register because"
11611 " altivec instructions are disabled, use %qs"
11612 " to enable them", "-maltivec");
11614 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11615 even if it is going to be passed in a vector register.
11616 Darwin does the same for variable-argument functions. */
11617 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11619 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11629 /* Vector parameters must be 16-byte aligned. In 32-bit
11630 mode this means we need to take into account the offset
11631 to the parameter save area. In 64-bit mode, they just
11632 have to start on an even word, since the parameter save
11633 area is 16-byte aligned. */
11635 align = -(rs6000_parm_offset () + cum->words) & 3;
11637 align = cum->words & 1;
11638 cum->words += align + rs6000_arg_size (mode, type);
11640 if (TARGET_DEBUG_ARG)
11642 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11643 cum->words, align);
11644 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11645 cum->nargs_prototype, cum->prototype,
11646 GET_MODE_NAME (mode));
11650 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11652 int size = int_size_in_bytes (type);
11653 /* Variable sized types have size == -1 and are
11654 treated as if consisting entirely of ints.
11655 Pad to 16 byte boundary if needed. */
11656 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11657 && (cum->words % 2) != 0)
11659 /* For varargs, we can just go up by the size of the struct. */
11661 cum->words += (size + 7) / 8;
11664 /* It is tempting to say int register count just goes up by
11665 sizeof(type)/8, but this is wrong in a case such as
11666 { int; double; int; } [powerpc alignment]. We have to
11667 grovel through the fields for these too. */
11668 cum->intoffset = 0;
11669 cum->floats_in_gpr = 0;
11670 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11671 rs6000_darwin64_record_arg_advance_flush (cum,
11672 size * BITS_PER_UNIT, 1);
11674 if (TARGET_DEBUG_ARG)
11676 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11677 cum->words, TYPE_ALIGN (type), size);
11679 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11680 cum->nargs_prototype, cum->prototype,
11681 GET_MODE_NAME (mode));
11684 else if (DEFAULT_ABI == ABI_V4)
11686 if (abi_v4_pass_in_fpr (mode, named))
11688 /* _Decimal128 must use an even/odd register pair. This assumes
11689 that the register number is odd when fregno is odd. */
11690 if (mode == TDmode && (cum->fregno % 2) == 1)
11693 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11694 <= FP_ARG_V4_MAX_REG)
11695 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11698 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11699 if (mode == DFmode || FLOAT128_IBM_P (mode)
11700 || mode == DDmode || mode == TDmode)
11701 cum->words += cum->words & 1;
11702 cum->words += rs6000_arg_size (mode, type);
11707 int n_words = rs6000_arg_size (mode, type);
11708 int gregno = cum->sysv_gregno;
11710 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11711 As does any other 2 word item such as complex int due to a
11712 historical mistake. */
11714 gregno += (1 - gregno) & 1;
11716 /* Multi-reg args are not split between registers and stack. */
11717 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11719 /* Long long is aligned on the stack. So are other 2 word
11720 items such as complex int due to a historical mistake. */
11722 cum->words += cum->words & 1;
11723 cum->words += n_words;
11726 /* Note: continuing to accumulate gregno past when we've started
11727 spilling to the stack indicates the fact that we've started
11728 spilling to the stack to expand_builtin_saveregs. */
11729 cum->sysv_gregno = gregno + n_words;
11732 if (TARGET_DEBUG_ARG)
11734 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11735 cum->words, cum->fregno);
11736 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11737 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11738 fprintf (stderr, "mode = %4s, named = %d\n",
11739 GET_MODE_NAME (mode), named);
11744 int n_words = rs6000_arg_size (mode, type);
11745 int start_words = cum->words;
11746 int align_words = rs6000_parm_start (mode, type, start_words);
11748 cum->words = align_words + n_words;
11750 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11752 /* _Decimal128 must be passed in an even/odd float register pair.
11753 This assumes that the register number is odd when fregno is
11755 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11757 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11760 if (TARGET_DEBUG_ARG)
11762 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11763 cum->words, cum->fregno);
11764 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11765 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11766 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11767 named, align_words - start_words, depth);
11773 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11774 const_tree type, bool named)
11776 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11780 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11781 structure between cum->intoffset and bitpos to integer registers. */
11784 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11785 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11788 unsigned int regno;
11789 unsigned int startbit, endbit;
11790 int this_regno, intregs, intoffset;
11793 if (cum->intoffset == -1)
11796 intoffset = cum->intoffset;
11797 cum->intoffset = -1;
11799 /* If this is the trailing part of a word, try to only load that
11800 much into the register. Otherwise load the whole register. Note
11801 that in the latter case we may pick up unwanted bits. It's not a
11802 problem at the moment but may wish to revisit. */
11804 if (intoffset % BITS_PER_WORD != 0)
11806 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11807 if (!int_mode_for_size (bits, 0).exists (&mode))
11809 /* We couldn't find an appropriate mode, which happens,
11810 e.g., in packed structs when there are 3 bytes to load.
11811 Back intoffset back to the beginning of the word in this
11813 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11820 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11821 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11822 intregs = (endbit - startbit) / BITS_PER_WORD;
11823 this_regno = cum->words + intoffset / BITS_PER_WORD;
11825 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11826 cum->use_stack = 1;
11828 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11832 intoffset /= BITS_PER_UNIT;
11835 regno = GP_ARG_MIN_REG + this_regno;
11836 reg = gen_rtx_REG (mode, regno);
11838 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11841 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11845 while (intregs > 0);
11848 /* Recursive workhorse for the following. */
11851 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11852 HOST_WIDE_INT startbitpos, rtx rvec[],
11857 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11858 if (TREE_CODE (f) == FIELD_DECL)
11860 HOST_WIDE_INT bitpos = startbitpos;
11861 tree ftype = TREE_TYPE (f);
11863 if (ftype == error_mark_node)
11865 mode = TYPE_MODE (ftype);
11867 if (DECL_SIZE (f) != 0
11868 && tree_fits_uhwi_p (bit_position (f)))
11869 bitpos += int_bit_position (f);
11871 /* ??? FIXME: else assume zero offset. */
11873 if (TREE_CODE (ftype) == RECORD_TYPE)
11874 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11875 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11877 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11881 case E_SCmode: mode = SFmode; break;
11882 case E_DCmode: mode = DFmode; break;
11883 case E_TCmode: mode = TFmode; break;
11887 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11888 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11890 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11891 && (mode == TFmode || mode == TDmode));
11892 /* Long double or _Decimal128 split over regs and memory. */
11893 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11897 = gen_rtx_EXPR_LIST (VOIDmode,
11898 gen_rtx_REG (mode, cum->fregno++),
11899 GEN_INT (bitpos / BITS_PER_UNIT));
11900 if (FLOAT128_2REG_P (mode))
11903 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11905 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11907 = gen_rtx_EXPR_LIST (VOIDmode,
11908 gen_rtx_REG (mode, cum->vregno++),
11909 GEN_INT (bitpos / BITS_PER_UNIT));
11911 else if (cum->intoffset == -1)
11912 cum->intoffset = bitpos;
11916 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11917 the register(s) to be used for each field and subfield of a struct
11918 being passed by value, along with the offset of where the
11919 register's value may be found in the block. FP fields go in FP
11920 register, vector fields go in vector registers, and everything
11921 else goes in int registers, packed as in memory.
11923 This code is also used for function return values. RETVAL indicates
11924 whether this is the case.
11926 Much of this is taken from the SPARC V9 port, which has a similar
11927 calling convention. */
11930 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11931 bool named, bool retval)
11933 rtx rvec[FIRST_PSEUDO_REGISTER];
11934 int k = 1, kbase = 1;
11935 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11936 /* This is a copy; modifications are not visible to our caller. */
11937 CUMULATIVE_ARGS copy_cum = *orig_cum;
11938 CUMULATIVE_ARGS *cum = ©_cum;
11940 /* Pad to 16 byte boundary if needed. */
11941 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11942 && (cum->words % 2) != 0)
11945 cum->intoffset = 0;
11946 cum->use_stack = 0;
11947 cum->named = named;
11949 /* Put entries into rvec[] for individual FP and vector fields, and
11950 for the chunks of memory that go in int regs. Note we start at
11951 element 1; 0 is reserved for an indication of using memory, and
11952 may or may not be filled in below. */
11953 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11954 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11956 /* If any part of the struct went on the stack put all of it there.
11957 This hack is because the generic code for
11958 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11959 parts of the struct are not at the beginning. */
11960 if (cum->use_stack)
11963 return NULL_RTX; /* doesn't go in registers at all */
11965 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11967 if (k > 1 || cum->use_stack)
11968 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11973 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11976 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11981 rtx rvec[GP_ARG_NUM_REG + 1];
11983 if (align_words >= GP_ARG_NUM_REG)
11986 n_units = rs6000_arg_size (mode, type);
11988 /* Optimize the simple case where the arg fits in one gpr, except in
11989 the case of BLKmode due to assign_parms assuming that registers are
11990 BITS_PER_WORD wide. */
11992 || (n_units == 1 && mode != BLKmode))
11993 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11996 if (align_words + n_units > GP_ARG_NUM_REG)
11997 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11998 using a magic NULL_RTX component.
11999 This is not strictly correct. Only some of the arg belongs in
12000 memory, not all of it. However, the normal scheme using
12001 function_arg_partial_nregs can result in unusual subregs, eg.
12002 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12003 store the whole arg to memory is often more efficient than code
12004 to store pieces, and we know that space is available in the right
12005 place for the whole arg. */
12006 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12011 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12012 rtx off = GEN_INT (i++ * 4);
12013 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12015 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12017 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12020 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12021 but must also be copied into the parameter save area starting at
12022 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12023 to the GPRs and/or memory. Return the number of elements used. */
12026 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12027 int align_words, rtx *rvec)
12031 if (align_words < GP_ARG_NUM_REG)
12033 int n_words = rs6000_arg_size (mode, type);
12035 if (align_words + n_words > GP_ARG_NUM_REG
12037 || (TARGET_32BIT && TARGET_POWERPC64))
12039 /* If this is partially on the stack, then we only
12040 include the portion actually in registers here. */
12041 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12044 if (align_words + n_words > GP_ARG_NUM_REG)
12046 /* Not all of the arg fits in gprs. Say that it goes in memory
12047 too, using a magic NULL_RTX component. Also see comment in
12048 rs6000_mixed_function_arg for why the normal
12049 function_arg_partial_nregs scheme doesn't work in this case. */
12050 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12055 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12056 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12057 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12059 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12063 /* The whole arg fits in gprs. */
12064 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12065 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12070 /* It's entirely in memory. */
12071 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12077 /* RVEC is a vector of K components of an argument of mode MODE.
12078 Construct the final function_arg return value from it. */
12081 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12083 gcc_assert (k >= 1);
12085 /* Avoid returning a PARALLEL in the trivial cases. */
12088 if (XEXP (rvec[0], 0) == NULL_RTX)
12091 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12092 return XEXP (rvec[0], 0);
12095 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12098 /* Determine where to put an argument to a function.
12099 Value is zero to push the argument on the stack,
12100 or a hard register in which to store the argument.
12102 MODE is the argument's machine mode.
12103 TYPE is the data type of the argument (as a tree).
12104 This is null for libcalls where that information may
12106 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12107 the preceding args and about the function being called. It is
12108 not modified in this routine.
12109 NAMED is nonzero if this argument is a named parameter
12110 (otherwise it is an extra parameter matching an ellipsis).
12112 On RS/6000 the first eight words of non-FP are normally in registers
12113 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12114 Under V.4, the first 8 FP args are in registers.
12116 If this is floating-point and no prototype is specified, we use
12117 both an FP and integer register (or possibly FP reg and stack). Library
12118 functions (when CALL_LIBCALL is set) always have the proper types for args,
12119 so we can pass the FP value just in one register. emit_library_function
12120 doesn't support PARALLEL anyway.
12122 Note that for args passed by reference, function_arg will be called
12123 with MODE and TYPE set to that of the pointer to the arg, not the arg
12127 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12128 const_tree type, bool named)
12130 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12131 enum rs6000_abi abi = DEFAULT_ABI;
12132 machine_mode elt_mode;
12135 /* Return a marker to indicate whether CR1 needs to set or clear the
12136 bit that V.4 uses to say fp args were passed in registers.
12137 Assume that we don't need the marker for software floating point,
12138 or compiler generated library calls. */
12139 if (mode == VOIDmode)
12142 && (cum->call_cookie & CALL_LIBCALL) == 0
12144 || (cum->nargs_prototype < 0
12145 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12146 && TARGET_HARD_FLOAT)
12147 return GEN_INT (cum->call_cookie
12148 | ((cum->fregno == FP_ARG_MIN_REG)
12149 ? CALL_V4_SET_FP_ARGS
12150 : CALL_V4_CLEAR_FP_ARGS));
12152 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12155 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12157 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12159 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12160 if (rslt != NULL_RTX)
12162 /* Else fall through to usual handling. */
12165 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12167 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12171 /* Do we also need to pass this argument in the parameter save area?
12172 Library support functions for IEEE 128-bit are assumed to not need the
12173 value passed both in GPRs and in vector registers. */
12174 if (TARGET_64BIT && !cum->prototype
12175 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12177 int align_words = ROUND_UP (cum->words, 2);
12178 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12181 /* Describe where this argument goes in the vector registers. */
12182 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12184 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12185 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12186 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12189 return rs6000_finish_function_arg (mode, rvec, k);
12191 else if (TARGET_ALTIVEC_ABI
12192 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12193 || (type && TREE_CODE (type) == VECTOR_TYPE
12194 && int_size_in_bytes (type) == 16)))
12196 if (named || abi == ABI_V4)
12200 /* Vector parameters to varargs functions under AIX or Darwin
12201 get passed in memory and possibly also in GPRs. */
12202 int align, align_words, n_words;
12203 machine_mode part_mode;
12205 /* Vector parameters must be 16-byte aligned. In 32-bit
12206 mode this means we need to take into account the offset
12207 to the parameter save area. In 64-bit mode, they just
12208 have to start on an even word, since the parameter save
12209 area is 16-byte aligned. */
12211 align = -(rs6000_parm_offset () + cum->words) & 3;
12213 align = cum->words & 1;
12214 align_words = cum->words + align;
12216 /* Out of registers? Memory, then. */
12217 if (align_words >= GP_ARG_NUM_REG)
12220 if (TARGET_32BIT && TARGET_POWERPC64)
12221 return rs6000_mixed_function_arg (mode, type, align_words);
12223 /* The vector value goes in GPRs. Only the part of the
12224 value in GPRs is reported here. */
12226 n_words = rs6000_arg_size (mode, type);
12227 if (align_words + n_words > GP_ARG_NUM_REG)
12228 /* Fortunately, there are only two possibilities, the value
12229 is either wholly in GPRs or half in GPRs and half not. */
12230 part_mode = DImode;
12232 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12236 else if (abi == ABI_V4)
12238 if (abi_v4_pass_in_fpr (mode, named))
12240 /* _Decimal128 must use an even/odd register pair. This assumes
12241 that the register number is odd when fregno is odd. */
12242 if (mode == TDmode && (cum->fregno % 2) == 1)
12245 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12246 <= FP_ARG_V4_MAX_REG)
12247 return gen_rtx_REG (mode, cum->fregno);
12253 int n_words = rs6000_arg_size (mode, type);
12254 int gregno = cum->sysv_gregno;
12256 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12257 As does any other 2 word item such as complex int due to a
12258 historical mistake. */
12260 gregno += (1 - gregno) & 1;
12262 /* Multi-reg args are not split between registers and stack. */
12263 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12266 if (TARGET_32BIT && TARGET_POWERPC64)
12267 return rs6000_mixed_function_arg (mode, type,
12268 gregno - GP_ARG_MIN_REG);
12269 return gen_rtx_REG (mode, gregno);
12274 int align_words = rs6000_parm_start (mode, type, cum->words);
12276 /* _Decimal128 must be passed in an even/odd float register pair.
12277 This assumes that the register number is odd when fregno is odd. */
12278 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12281 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12283 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12286 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12289 /* Do we also need to pass this argument in the parameter
12291 if (type && (cum->nargs_prototype <= 0
12292 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12293 && TARGET_XL_COMPAT
12294 && align_words >= GP_ARG_NUM_REG)))
12295 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12297 /* Describe where this argument goes in the fprs. */
12298 for (i = 0; i < n_elts
12299 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12301 /* Check if the argument is split over registers and memory.
12302 This can only ever happen for long double or _Decimal128;
12303 complex types are handled via split_complex_arg. */
12304 machine_mode fmode = elt_mode;
12305 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12307 gcc_assert (FLOAT128_2REG_P (fmode));
12308 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12311 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12312 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12313 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12316 /* If there were not enough FPRs to hold the argument, the rest
12317 usually goes into memory. However, if the current position
12318 is still within the register parameter area, a portion may
12319 actually have to go into GPRs.
12321 Note that it may happen that the portion of the argument
12322 passed in the first "half" of the first GPR was already
12323 passed in the last FPR as well.
12325 For unnamed arguments, we already set up GPRs to cover the
12326 whole argument in rs6000_psave_function_arg, so there is
12327 nothing further to do at this point. */
12328 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12329 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12330 && cum->nargs_prototype > 0)
12332 static bool warned;
12334 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12335 int n_words = rs6000_arg_size (mode, type);
12337 align_words += fpr_words;
12338 n_words -= fpr_words;
12342 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12343 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12344 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12346 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12348 if (!warned && warn_psabi)
12351 inform (input_location,
12352 "the ABI of passing homogeneous float aggregates"
12353 " has changed in GCC 5");
12357 return rs6000_finish_function_arg (mode, rvec, k);
12359 else if (align_words < GP_ARG_NUM_REG)
12361 if (TARGET_32BIT && TARGET_POWERPC64)
12362 return rs6000_mixed_function_arg (mode, type, align_words);
12364 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12371 /* For an arg passed partly in registers and partly in memory, this is
12372 the number of bytes passed in registers. For args passed entirely in
12373 registers or entirely in memory, zero. When an arg is described by a
12374 PARALLEL, perhaps using more than one register type, this function
12375 returns the number of bytes used by the first element of the PARALLEL. */
12378 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12379 tree type, bool named)
12381 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12382 bool passed_in_gprs = true;
12385 machine_mode elt_mode;
12388 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12390 if (DEFAULT_ABI == ABI_V4)
12393 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12395 /* If we are passing this arg in the fixed parameter save area (gprs or
12396 memory) as well as VRs, we do not use the partial bytes mechanism;
12397 instead, rs6000_function_arg will return a PARALLEL including a memory
12398 element as necessary. Library support functions for IEEE 128-bit are
12399 assumed to not need the value passed both in GPRs and in vector
12401 if (TARGET_64BIT && !cum->prototype
12402 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12405 /* Otherwise, we pass in VRs only. Check for partial copies. */
12406 passed_in_gprs = false;
12407 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12408 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12411 /* In this complicated case we just disable the partial_nregs code. */
12412 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12415 align_words = rs6000_parm_start (mode, type, cum->words);
12417 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12419 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12421 /* If we are passing this arg in the fixed parameter save area
12422 (gprs or memory) as well as FPRs, we do not use the partial
12423 bytes mechanism; instead, rs6000_function_arg will return a
12424 PARALLEL including a memory element as necessary. */
12426 && (cum->nargs_prototype <= 0
12427 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12428 && TARGET_XL_COMPAT
12429 && align_words >= GP_ARG_NUM_REG)))
12432 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12433 passed_in_gprs = false;
12434 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12436 /* Compute number of bytes / words passed in FPRs. If there
12437 is still space available in the register parameter area
12438 *after* that amount, a part of the argument will be passed
12439 in GPRs. In that case, the total amount passed in any
12440 registers is equal to the amount that would have been passed
12441 in GPRs if everything were passed there, so we fall back to
12442 the GPR code below to compute the appropriate value. */
12443 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12444 * MIN (8, GET_MODE_SIZE (elt_mode)));
12445 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12447 if (align_words + fpr_words < GP_ARG_NUM_REG)
12448 passed_in_gprs = true;
12455 && align_words < GP_ARG_NUM_REG
12456 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12457 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12459 if (ret != 0 && TARGET_DEBUG_ARG)
12460 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12465 /* A C expression that indicates when an argument must be passed by
12466 reference. If nonzero for an argument, a copy of that argument is
12467 made in memory and a pointer to the argument is passed instead of
12468 the argument itself. The pointer is passed in whatever way is
12469 appropriate for passing a pointer to that type.
12471 Under V.4, aggregates and long double are passed by reference.
12473 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12474 reference unless the AltiVec vector extension ABI is in force.
12476 As an extension to all ABIs, variable sized types are passed by
12480 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12481 machine_mode mode, const_tree type,
12482 bool named ATTRIBUTE_UNUSED)
12487 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12488 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12490 if (TARGET_DEBUG_ARG)
12491 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12495 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12497 if (TARGET_DEBUG_ARG)
12498 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12502 if (int_size_in_bytes (type) < 0)
12504 if (TARGET_DEBUG_ARG)
12505 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12509 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12510 modes only exist for GCC vector types if -maltivec. */
12511 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12513 if (TARGET_DEBUG_ARG)
12514 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12518 /* Pass synthetic vectors in memory. */
12519 if (TREE_CODE (type) == VECTOR_TYPE
12520 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12522 static bool warned_for_pass_big_vectors = false;
12523 if (TARGET_DEBUG_ARG)
12524 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12525 if (!warned_for_pass_big_vectors)
12527 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12528 "non-standard ABI extension with no compatibility "
12530 warned_for_pass_big_vectors = true;
12538 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12539 already processes. Return true if the parameter must be passed
12540 (fully or partially) on the stack. */
12543 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12549 /* Catch errors. */
12550 if (type == NULL || type == error_mark_node)
12553 /* Handle types with no storage requirement. */
12554 if (TYPE_MODE (type) == VOIDmode)
12557 /* Handle complex types. */
12558 if (TREE_CODE (type) == COMPLEX_TYPE)
12559 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12560 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12562 /* Handle transparent aggregates. */
12563 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12564 && TYPE_TRANSPARENT_AGGR (type))
12565 type = TREE_TYPE (first_field (type));
12567 /* See if this arg was passed by invisible reference. */
12568 if (pass_by_reference (get_cumulative_args (args_so_far),
12569 TYPE_MODE (type), type, true))
12570 type = build_pointer_type (type);
12572 /* Find mode as it is passed by the ABI. */
12573 unsignedp = TYPE_UNSIGNED (type);
12574 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12576 /* If we must pass in stack, we need a stack. */
12577 if (rs6000_must_pass_in_stack (mode, type))
12580 /* If there is no incoming register, we need a stack. */
12581 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12582 if (entry_parm == NULL)
12585 /* Likewise if we need to pass both in registers and on the stack. */
12586 if (GET_CODE (entry_parm) == PARALLEL
12587 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12590 /* Also true if we're partially in registers and partially not. */
12591 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12594 /* Update info on where next arg arrives in registers. */
12595 rs6000_function_arg_advance (args_so_far, mode, type, true);
12599 /* Return true if FUN has no prototype, has a variable argument
12600 list, or passes any parameter in memory. */
12603 rs6000_function_parms_need_stack (tree fun, bool incoming)
12605 tree fntype, result;
12606 CUMULATIVE_ARGS args_so_far_v;
12607 cumulative_args_t args_so_far;
12610 /* Must be a libcall, all of which only use reg parms. */
12615 fntype = TREE_TYPE (fun);
12617 /* Varargs functions need the parameter save area. */
12618 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12621 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12622 args_so_far = pack_cumulative_args (&args_so_far_v);
12624 /* When incoming, we will have been passed the function decl.
12625 It is necessary to use the decl to handle K&R style functions,
12626 where TYPE_ARG_TYPES may not be available. */
12629 gcc_assert (DECL_P (fun));
12630 result = DECL_RESULT (fun);
12633 result = TREE_TYPE (fntype);
12635 if (result && aggregate_value_p (result, fntype))
12637 if (!TYPE_P (result))
12638 result = TREE_TYPE (result);
12639 result = build_pointer_type (result);
12640 rs6000_parm_needs_stack (args_so_far, result);
12647 for (parm = DECL_ARGUMENTS (fun);
12648 parm && parm != void_list_node;
12649 parm = TREE_CHAIN (parm))
12650 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12655 function_args_iterator args_iter;
12658 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12659 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12666 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12667 usually a constant depending on the ABI. However, in the ELFv2 ABI
12668 the register parameter area is optional when calling a function that
12669 has a prototype is scope, has no variable argument list, and passes
12670 all parameters in registers. */
12673 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12675 int reg_parm_stack_space;
12677 switch (DEFAULT_ABI)
12680 reg_parm_stack_space = 0;
12685 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12689 /* ??? Recomputing this every time is a bit expensive. Is there
12690 a place to cache this information? */
12691 if (rs6000_function_parms_need_stack (fun, incoming))
12692 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12694 reg_parm_stack_space = 0;
12698 return reg_parm_stack_space;
12702 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12705 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12710 for (i = 0; i < nregs; i++)
12712 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12713 if (reload_completed)
12715 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12718 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12719 i * GET_MODE_SIZE (reg_mode));
12722 tem = replace_equiv_address (tem, XEXP (tem, 0));
12726 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12730 /* Perform any needed actions needed for a function that is receiving a
12731 variable number of arguments.
12735 MODE and TYPE are the mode and type of the current parameter.
12737 PRETEND_SIZE is a variable that should be set to the amount of stack
12738 that must be pushed by the prolog to pretend that our caller pushed
12741 Normally, this macro will push all remaining incoming registers on the
12742 stack and set PRETEND_SIZE to the length of the registers pushed. */
12745 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12746 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12749 CUMULATIVE_ARGS next_cum;
12750 int reg_size = TARGET_32BIT ? 4 : 8;
12751 rtx save_area = NULL_RTX, mem;
12752 int first_reg_offset;
12753 alias_set_type set;
12755 /* Skip the last named argument. */
12756 next_cum = *get_cumulative_args (cum);
12757 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12759 if (DEFAULT_ABI == ABI_V4)
12761 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12765 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12766 HOST_WIDE_INT offset = 0;
12768 /* Try to optimize the size of the varargs save area.
12769 The ABI requires that ap.reg_save_area is doubleword
12770 aligned, but we don't need to allocate space for all
12771 the bytes, only those to which we actually will save
12773 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12774 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12775 if (TARGET_HARD_FLOAT
12776 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12777 && cfun->va_list_fpr_size)
12780 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12781 * UNITS_PER_FP_WORD;
12782 if (cfun->va_list_fpr_size
12783 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12784 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12786 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12787 * UNITS_PER_FP_WORD;
12791 offset = -((first_reg_offset * reg_size) & ~7);
12792 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12794 gpr_reg_num = cfun->va_list_gpr_size;
12795 if (reg_size == 4 && (first_reg_offset & 1))
12798 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12801 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12802 * UNITS_PER_FP_WORD
12803 - (int) (GP_ARG_NUM_REG * reg_size);
12805 if (gpr_size + fpr_size)
12808 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12809 gcc_assert (GET_CODE (reg_save_area) == MEM);
12810 reg_save_area = XEXP (reg_save_area, 0);
12811 if (GET_CODE (reg_save_area) == PLUS)
12813 gcc_assert (XEXP (reg_save_area, 0)
12814 == virtual_stack_vars_rtx);
12815 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
12816 offset += INTVAL (XEXP (reg_save_area, 1));
12819 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12822 cfun->machine->varargs_save_offset = offset;
12823 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12828 first_reg_offset = next_cum.words;
12829 save_area = crtl->args.internal_arg_pointer;
12831 if (targetm.calls.must_pass_in_stack (mode, type))
12832 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12835 set = get_varargs_alias_set ();
12836 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12837 && cfun->va_list_gpr_size)
12839 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12841 if (va_list_gpr_counter_field)
12842 /* V4 va_list_gpr_size counts number of registers needed. */
12843 n_gpr = cfun->va_list_gpr_size;
12845 /* char * va_list instead counts number of bytes needed. */
12846 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12851 mem = gen_rtx_MEM (BLKmode,
12852 plus_constant (Pmode, save_area,
12853 first_reg_offset * reg_size));
12854 MEM_NOTRAP_P (mem) = 1;
12855 set_mem_alias_set (mem, set);
12856 set_mem_align (mem, BITS_PER_WORD);
12858 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12862 /* Save FP registers if needed. */
12863 if (DEFAULT_ABI == ABI_V4
12864 && TARGET_HARD_FLOAT
12866 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12867 && cfun->va_list_fpr_size)
12869 int fregno = next_cum.fregno, nregs;
12870 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12871 rtx lab = gen_label_rtx ();
12872 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12873 * UNITS_PER_FP_WORD);
12876 (gen_rtx_SET (pc_rtx,
12877 gen_rtx_IF_THEN_ELSE (VOIDmode,
12878 gen_rtx_NE (VOIDmode, cr1,
12880 gen_rtx_LABEL_REF (VOIDmode, lab),
12884 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12885 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12887 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12888 plus_constant (Pmode, save_area, off));
12889 MEM_NOTRAP_P (mem) = 1;
12890 set_mem_alias_set (mem, set);
12891 set_mem_align (mem, GET_MODE_ALIGNMENT (
12892 TARGET_HARD_FLOAT ? DFmode : SFmode));
12893 emit_move_insn (mem, gen_rtx_REG (
12894 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12901 /* Create the va_list data type. */
12904 rs6000_build_builtin_va_list (void)
12906 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12908 /* For AIX, prefer 'char *' because that's what the system
12909 header files like. */
12910 if (DEFAULT_ABI != ABI_V4)
12911 return build_pointer_type (char_type_node);
12913 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12914 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12915 get_identifier ("__va_list_tag"), record);
12917 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12918 unsigned_char_type_node);
12919 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12920 unsigned_char_type_node);
12921 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12922 every user file. */
12923 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12924 get_identifier ("reserved"), short_unsigned_type_node);
12925 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12926 get_identifier ("overflow_arg_area"),
12928 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12929 get_identifier ("reg_save_area"),
12932 va_list_gpr_counter_field = f_gpr;
12933 va_list_fpr_counter_field = f_fpr;
12935 DECL_FIELD_CONTEXT (f_gpr) = record;
12936 DECL_FIELD_CONTEXT (f_fpr) = record;
12937 DECL_FIELD_CONTEXT (f_res) = record;
12938 DECL_FIELD_CONTEXT (f_ovf) = record;
12939 DECL_FIELD_CONTEXT (f_sav) = record;
12941 TYPE_STUB_DECL (record) = type_decl;
12942 TYPE_NAME (record) = type_decl;
12943 TYPE_FIELDS (record) = f_gpr;
12944 DECL_CHAIN (f_gpr) = f_fpr;
12945 DECL_CHAIN (f_fpr) = f_res;
12946 DECL_CHAIN (f_res) = f_ovf;
12947 DECL_CHAIN (f_ovf) = f_sav;
12949 layout_type (record);
12951 /* The correct type is an array type of one element. */
12952 return build_array_type (record, build_index_type (size_zero_node));
12955 /* Implement va_start. */
12958 rs6000_va_start (tree valist, rtx nextarg)
12960 HOST_WIDE_INT words, n_gpr, n_fpr;
12961 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12962 tree gpr, fpr, ovf, sav, t;
12964 /* Only SVR4 needs something special. */
12965 if (DEFAULT_ABI != ABI_V4)
12967 std_expand_builtin_va_start (valist, nextarg);
12971 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12972 f_fpr = DECL_CHAIN (f_gpr);
12973 f_res = DECL_CHAIN (f_fpr);
12974 f_ovf = DECL_CHAIN (f_res);
12975 f_sav = DECL_CHAIN (f_ovf);
12977 valist = build_simple_mem_ref (valist);
12978 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12979 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12981 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12983 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12986 /* Count number of gp and fp argument registers used. */
12987 words = crtl->args.info.words;
12988 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12990 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12993 if (TARGET_DEBUG_ARG)
12994 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12995 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12996 words, n_gpr, n_fpr);
12998 if (cfun->va_list_gpr_size)
13000 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13001 build_int_cst (NULL_TREE, n_gpr));
13002 TREE_SIDE_EFFECTS (t) = 1;
13003 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13006 if (cfun->va_list_fpr_size)
13008 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13009 build_int_cst (NULL_TREE, n_fpr));
13010 TREE_SIDE_EFFECTS (t) = 1;
13011 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13013 #ifdef HAVE_AS_GNU_ATTRIBUTE
13014 if (call_ABI_of_interest (cfun->decl))
13015 rs6000_passes_float = true;
13019 /* Find the overflow area. */
13020 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13022 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13023 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13024 TREE_SIDE_EFFECTS (t) = 1;
13025 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13027 /* If there were no va_arg invocations, don't set up the register
13029 if (!cfun->va_list_gpr_size
13030 && !cfun->va_list_fpr_size
13031 && n_gpr < GP_ARG_NUM_REG
13032 && n_fpr < FP_ARG_V4_MAX_REG)
13035 /* Find the register save area. */
13036 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13037 if (cfun->machine->varargs_save_offset)
13038 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13039 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13040 TREE_SIDE_EFFECTS (t) = 1;
13041 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13044 /* Implement va_arg. */
13047 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13048 gimple_seq *post_p)
13050 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13051 tree gpr, fpr, ovf, sav, reg, t, u;
13052 int size, rsize, n_reg, sav_ofs, sav_scale;
13053 tree lab_false, lab_over, addr;
13055 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13059 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13061 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13062 return build_va_arg_indirect_ref (t);
13065 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13066 earlier version of gcc, with the property that it always applied alignment
13067 adjustments to the va-args (even for zero-sized types). The cheapest way
13068 to deal with this is to replicate the effect of the part of
13069 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13071 We don't need to check for pass-by-reference because of the test above.
13072 We can return a simplifed answer, since we know there's no offset to add. */
13075 && rs6000_darwin64_abi)
13076 || DEFAULT_ABI == ABI_ELFv2
13077 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13078 && integer_zerop (TYPE_SIZE (type)))
13080 unsigned HOST_WIDE_INT align, boundary;
13081 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13082 align = PARM_BOUNDARY / BITS_PER_UNIT;
13083 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13084 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13085 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13086 boundary /= BITS_PER_UNIT;
13087 if (boundary > align)
13090 /* This updates arg ptr by the amount that would be necessary
13091 to align the zero-sized (but not zero-alignment) item. */
13092 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13093 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13094 gimplify_and_add (t, pre_p);
13096 t = fold_convert (sizetype, valist_tmp);
13097 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13098 fold_convert (TREE_TYPE (valist),
13099 fold_build2 (BIT_AND_EXPR, sizetype, t,
13100 size_int (-boundary))));
13101 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13102 gimplify_and_add (t, pre_p);
13104 /* Since it is zero-sized there's no increment for the item itself. */
13105 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13106 return build_va_arg_indirect_ref (valist_tmp);
13109 if (DEFAULT_ABI != ABI_V4)
13111 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13113 tree elem_type = TREE_TYPE (type);
13114 machine_mode elem_mode = TYPE_MODE (elem_type);
13115 int elem_size = GET_MODE_SIZE (elem_mode);
13117 if (elem_size < UNITS_PER_WORD)
13119 tree real_part, imag_part;
13120 gimple_seq post = NULL;
13122 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13124 /* Copy the value into a temporary, lest the formal temporary
13125 be reused out from under us. */
13126 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13127 gimple_seq_add_seq (pre_p, post);
13129 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13132 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13136 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13139 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13140 f_fpr = DECL_CHAIN (f_gpr);
13141 f_res = DECL_CHAIN (f_fpr);
13142 f_ovf = DECL_CHAIN (f_res);
13143 f_sav = DECL_CHAIN (f_ovf);
13145 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13146 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13148 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13150 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13153 size = int_size_in_bytes (type);
13154 rsize = (size + 3) / 4;
13155 int pad = 4 * rsize - size;
13158 machine_mode mode = TYPE_MODE (type);
13159 if (abi_v4_pass_in_fpr (mode, false))
13161 /* FP args go in FP registers, if present. */
13163 n_reg = (size + 7) / 8;
13164 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
13165 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
13166 if (mode != SFmode && mode != SDmode)
13171 /* Otherwise into GP registers. */
13180 /* Pull the value out of the saved registers.... */
13183 addr = create_tmp_var (ptr_type_node, "addr");
13185 /* AltiVec vectors never go in registers when -mabi=altivec. */
13186 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13190 lab_false = create_artificial_label (input_location);
13191 lab_over = create_artificial_label (input_location);
13193 /* Long long is aligned in the registers. As are any other 2 gpr
13194 item such as complex int due to a historical mistake. */
13196 if (n_reg == 2 && reg == gpr)
13199 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13200 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13201 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13202 unshare_expr (reg), u);
13204 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13205 reg number is 0 for f1, so we want to make it odd. */
13206 else if (reg == fpr && mode == TDmode)
13208 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13209 build_int_cst (TREE_TYPE (reg), 1));
13210 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13213 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13214 t = build2 (GE_EXPR, boolean_type_node, u, t);
13215 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13216 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13217 gimplify_and_add (t, pre_p);
13221 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13223 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13224 build_int_cst (TREE_TYPE (reg), n_reg));
13225 u = fold_convert (sizetype, u);
13226 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13227 t = fold_build_pointer_plus (t, u);
13229 /* _Decimal32 varargs are located in the second word of the 64-bit
13230 FP register for 32-bit binaries. */
13231 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13232 t = fold_build_pointer_plus_hwi (t, size);
13234 /* Args are passed right-aligned. */
13235 if (BYTES_BIG_ENDIAN)
13236 t = fold_build_pointer_plus_hwi (t, pad);
13238 gimplify_assign (addr, t, pre_p);
13240 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13242 stmt = gimple_build_label (lab_false);
13243 gimple_seq_add_stmt (pre_p, stmt);
13245 if ((n_reg == 2 && !regalign) || n_reg > 2)
13247 /* Ensure that we don't find any more args in regs.
13248 Alignment has taken care of for special cases. */
13249 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13253 /* ... otherwise out of the overflow area. */
13255 /* Care for on-stack alignment if needed. */
13259 t = fold_build_pointer_plus_hwi (t, align - 1);
13260 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13261 build_int_cst (TREE_TYPE (t), -align));
13264 /* Args are passed right-aligned. */
13265 if (BYTES_BIG_ENDIAN)
13266 t = fold_build_pointer_plus_hwi (t, pad);
13268 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13270 gimplify_assign (unshare_expr (addr), t, pre_p);
13272 t = fold_build_pointer_plus_hwi (t, size);
13273 gimplify_assign (unshare_expr (ovf), t, pre_p);
13277 stmt = gimple_build_label (lab_over);
13278 gimple_seq_add_stmt (pre_p, stmt);
13281 if (STRICT_ALIGNMENT
13282 && (TYPE_ALIGN (type)
13283 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13285 /* The value (of type complex double, for example) may not be
13286 aligned in memory in the saved registers, so copy via a
13287 temporary. (This is the same code as used for SPARC.) */
13288 tree tmp = create_tmp_var (type, "va_arg_tmp");
13289 tree dest_addr = build_fold_addr_expr (tmp);
13291 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13292 3, dest_addr, addr, size_int (rsize * 4));
13293 TREE_ADDRESSABLE (tmp) = 1;
13295 gimplify_and_add (copy, pre_p);
13299 addr = fold_convert (ptrtype, addr);
13300 return build_va_arg_indirect_ref (addr);
13306 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13309 unsigned classify = rs6000_builtin_info[(int)code].attr;
13310 const char *attr_string = "";
13312 gcc_assert (name != NULL);
13313 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13315 if (rs6000_builtin_decls[(int)code])
13316 fatal_error (input_location,
13317 "internal error: builtin function %qs already processed",
13320 rs6000_builtin_decls[(int)code] = t =
13321 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13323 /* Set any special attributes. */
13324 if ((classify & RS6000_BTC_CONST) != 0)
13326 /* const function, function only depends on the inputs. */
13327 TREE_READONLY (t) = 1;
13328 TREE_NOTHROW (t) = 1;
13329 attr_string = ", const";
13331 else if ((classify & RS6000_BTC_PURE) != 0)
13333 /* pure function, function can read global memory, but does not set any
13335 DECL_PURE_P (t) = 1;
13336 TREE_NOTHROW (t) = 1;
13337 attr_string = ", pure";
13339 else if ((classify & RS6000_BTC_FP) != 0)
13341 /* Function is a math function. If rounding mode is on, then treat the
13342 function as not reading global memory, but it can have arbitrary side
13343 effects. If it is off, then assume the function is a const function.
13344 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13345 builtin-attribute.def that is used for the math functions. */
13346 TREE_NOTHROW (t) = 1;
13347 if (flag_rounding_math)
13349 DECL_PURE_P (t) = 1;
13350 DECL_IS_NOVOPS (t) = 1;
13351 attr_string = ", fp, pure";
13355 TREE_READONLY (t) = 1;
13356 attr_string = ", fp, const";
13359 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13360 gcc_unreachable ();
13362 if (TARGET_DEBUG_BUILTIN)
13363 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13364 (int)code, name, attr_string);
13367 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13369 #undef RS6000_BUILTIN_0
13370 #undef RS6000_BUILTIN_1
13371 #undef RS6000_BUILTIN_2
13372 #undef RS6000_BUILTIN_3
13373 #undef RS6000_BUILTIN_A
13374 #undef RS6000_BUILTIN_D
13375 #undef RS6000_BUILTIN_H
13376 #undef RS6000_BUILTIN_P
13377 #undef RS6000_BUILTIN_X
13379 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13380 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13381 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13382 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13383 { MASK, ICODE, NAME, ENUM },
13385 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13386 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13387 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13388 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13389 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13391 static const struct builtin_description bdesc_3arg[] =
13393 #include "rs6000-builtin.def"
13396 /* DST operations: void foo (void *, const int, const char). */
13398 #undef RS6000_BUILTIN_0
13399 #undef RS6000_BUILTIN_1
13400 #undef RS6000_BUILTIN_2
13401 #undef RS6000_BUILTIN_3
13402 #undef RS6000_BUILTIN_A
13403 #undef RS6000_BUILTIN_D
13404 #undef RS6000_BUILTIN_H
13405 #undef RS6000_BUILTIN_P
13406 #undef RS6000_BUILTIN_X
13408 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13409 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13410 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13411 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13412 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13413 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13414 { MASK, ICODE, NAME, ENUM },
13416 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13417 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13418 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13420 static const struct builtin_description bdesc_dst[] =
13422 #include "rs6000-builtin.def"
13425 /* Simple binary operations: VECc = foo (VECa, VECb). */
13427 #undef RS6000_BUILTIN_0
13428 #undef RS6000_BUILTIN_1
13429 #undef RS6000_BUILTIN_2
13430 #undef RS6000_BUILTIN_3
13431 #undef RS6000_BUILTIN_A
13432 #undef RS6000_BUILTIN_D
13433 #undef RS6000_BUILTIN_H
13434 #undef RS6000_BUILTIN_P
13435 #undef RS6000_BUILTIN_X
13437 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13438 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13439 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13440 { MASK, ICODE, NAME, ENUM },
13442 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13443 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13444 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13445 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13446 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13447 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13449 static const struct builtin_description bdesc_2arg[] =
13451 #include "rs6000-builtin.def"
13454 #undef RS6000_BUILTIN_0
13455 #undef RS6000_BUILTIN_1
13456 #undef RS6000_BUILTIN_2
13457 #undef RS6000_BUILTIN_3
13458 #undef RS6000_BUILTIN_A
13459 #undef RS6000_BUILTIN_D
13460 #undef RS6000_BUILTIN_H
13461 #undef RS6000_BUILTIN_P
13462 #undef RS6000_BUILTIN_X
13464 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13465 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13466 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13467 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13468 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13469 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13470 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13471 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13472 { MASK, ICODE, NAME, ENUM },
13474 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13476 /* AltiVec predicates. */
13478 static const struct builtin_description bdesc_altivec_preds[] =
13480 #include "rs6000-builtin.def"
13483 /* ABS* operations. */
13485 #undef RS6000_BUILTIN_0
13486 #undef RS6000_BUILTIN_1
13487 #undef RS6000_BUILTIN_2
13488 #undef RS6000_BUILTIN_3
13489 #undef RS6000_BUILTIN_A
13490 #undef RS6000_BUILTIN_D
13491 #undef RS6000_BUILTIN_H
13492 #undef RS6000_BUILTIN_P
13493 #undef RS6000_BUILTIN_X
13495 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13496 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13497 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13498 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13499 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13500 { MASK, ICODE, NAME, ENUM },
13502 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13503 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13504 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13505 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13507 static const struct builtin_description bdesc_abs[] =
13509 #include "rs6000-builtin.def"
13512 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13515 #undef RS6000_BUILTIN_0
13516 #undef RS6000_BUILTIN_1
13517 #undef RS6000_BUILTIN_2
13518 #undef RS6000_BUILTIN_3
13519 #undef RS6000_BUILTIN_A
13520 #undef RS6000_BUILTIN_D
13521 #undef RS6000_BUILTIN_H
13522 #undef RS6000_BUILTIN_P
13523 #undef RS6000_BUILTIN_X
13525 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13526 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13527 { MASK, ICODE, NAME, ENUM },
13529 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13530 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13531 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13532 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13533 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13534 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13535 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13537 static const struct builtin_description bdesc_1arg[] =
13539 #include "rs6000-builtin.def"
13542 /* Simple no-argument operations: result = __builtin_darn_32 () */
13544 #undef RS6000_BUILTIN_0
13545 #undef RS6000_BUILTIN_1
13546 #undef RS6000_BUILTIN_2
13547 #undef RS6000_BUILTIN_3
13548 #undef RS6000_BUILTIN_A
13549 #undef RS6000_BUILTIN_D
13550 #undef RS6000_BUILTIN_H
13551 #undef RS6000_BUILTIN_P
13552 #undef RS6000_BUILTIN_X
13554 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13555 { MASK, ICODE, NAME, ENUM },
13557 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13558 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13559 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13560 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13561 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13562 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13563 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13564 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13566 static const struct builtin_description bdesc_0arg[] =
13568 #include "rs6000-builtin.def"
13571 /* HTM builtins. */
13572 #undef RS6000_BUILTIN_0
13573 #undef RS6000_BUILTIN_1
13574 #undef RS6000_BUILTIN_2
13575 #undef RS6000_BUILTIN_3
13576 #undef RS6000_BUILTIN_A
13577 #undef RS6000_BUILTIN_D
13578 #undef RS6000_BUILTIN_H
13579 #undef RS6000_BUILTIN_P
13580 #undef RS6000_BUILTIN_X
13582 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13583 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13584 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13585 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13586 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13587 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13588 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13589 { MASK, ICODE, NAME, ENUM },
13591 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13592 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13594 static const struct builtin_description bdesc_htm[] =
13596 #include "rs6000-builtin.def"
13599 #undef RS6000_BUILTIN_0
13600 #undef RS6000_BUILTIN_1
13601 #undef RS6000_BUILTIN_2
13602 #undef RS6000_BUILTIN_3
13603 #undef RS6000_BUILTIN_A
13604 #undef RS6000_BUILTIN_D
13605 #undef RS6000_BUILTIN_H
13606 #undef RS6000_BUILTIN_P
13608 /* Return true if a builtin function is overloaded. */
13610 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13612 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13616 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13618 return rs6000_builtin_info[(int)fncode].name;
13621 /* Expand an expression EXP that calls a builtin without arguments. */
13623 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13626 machine_mode tmode = insn_data[icode].operand[0].mode;
13628 if (icode == CODE_FOR_nothing)
13629 /* Builtin not supported on this processor. */
13633 || GET_MODE (target) != tmode
13634 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13635 target = gen_reg_rtx (tmode);
13637 pat = GEN_FCN (icode) (target);
13647 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13650 tree arg0 = CALL_EXPR_ARG (exp, 0);
13651 tree arg1 = CALL_EXPR_ARG (exp, 1);
13652 rtx op0 = expand_normal (arg0);
13653 rtx op1 = expand_normal (arg1);
13654 machine_mode mode0 = insn_data[icode].operand[0].mode;
13655 machine_mode mode1 = insn_data[icode].operand[1].mode;
13657 if (icode == CODE_FOR_nothing)
13658 /* Builtin not supported on this processor. */
13661 /* If we got invalid arguments bail out before generating bad rtl. */
13662 if (arg0 == error_mark_node || arg1 == error_mark_node)
13665 if (GET_CODE (op0) != CONST_INT
13666 || INTVAL (op0) > 255
13667 || INTVAL (op0) < 0)
13669 error ("argument 1 must be an 8-bit field value");
13673 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13674 op0 = copy_to_mode_reg (mode0, op0);
13676 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13677 op1 = copy_to_mode_reg (mode1, op1);
13679 pat = GEN_FCN (icode) (op0, op1);
13688 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13691 tree arg0 = CALL_EXPR_ARG (exp, 0);
13692 rtx op0 = expand_normal (arg0);
13693 machine_mode tmode = insn_data[icode].operand[0].mode;
13694 machine_mode mode0 = insn_data[icode].operand[1].mode;
13696 if (icode == CODE_FOR_nothing)
13697 /* Builtin not supported on this processor. */
13700 /* If we got invalid arguments bail out before generating bad rtl. */
13701 if (arg0 == error_mark_node)
13704 if (icode == CODE_FOR_altivec_vspltisb
13705 || icode == CODE_FOR_altivec_vspltish
13706 || icode == CODE_FOR_altivec_vspltisw)
13708 /* Only allow 5-bit *signed* literals. */
13709 if (GET_CODE (op0) != CONST_INT
13710 || INTVAL (op0) > 15
13711 || INTVAL (op0) < -16)
13713 error ("argument 1 must be a 5-bit signed literal");
13714 return CONST0_RTX (tmode);
13719 || GET_MODE (target) != tmode
13720 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13721 target = gen_reg_rtx (tmode);
13723 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13724 op0 = copy_to_mode_reg (mode0, op0);
13726 pat = GEN_FCN (icode) (target, op0);
13735 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13737 rtx pat, scratch1, scratch2;
13738 tree arg0 = CALL_EXPR_ARG (exp, 0);
13739 rtx op0 = expand_normal (arg0);
13740 machine_mode tmode = insn_data[icode].operand[0].mode;
13741 machine_mode mode0 = insn_data[icode].operand[1].mode;
13743 /* If we have invalid arguments, bail out before generating bad rtl. */
13744 if (arg0 == error_mark_node)
13748 || GET_MODE (target) != tmode
13749 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13750 target = gen_reg_rtx (tmode);
13752 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13753 op0 = copy_to_mode_reg (mode0, op0);
13755 scratch1 = gen_reg_rtx (mode0);
13756 scratch2 = gen_reg_rtx (mode0);
13758 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13767 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13770 tree arg0 = CALL_EXPR_ARG (exp, 0);
13771 tree arg1 = CALL_EXPR_ARG (exp, 1);
13772 rtx op0 = expand_normal (arg0);
13773 rtx op1 = expand_normal (arg1);
13774 machine_mode tmode = insn_data[icode].operand[0].mode;
13775 machine_mode mode0 = insn_data[icode].operand[1].mode;
13776 machine_mode mode1 = insn_data[icode].operand[2].mode;
13778 if (icode == CODE_FOR_nothing)
13779 /* Builtin not supported on this processor. */
13782 /* If we got invalid arguments bail out before generating bad rtl. */
13783 if (arg0 == error_mark_node || arg1 == error_mark_node)
13786 if (icode == CODE_FOR_altivec_vcfux
13787 || icode == CODE_FOR_altivec_vcfsx
13788 || icode == CODE_FOR_altivec_vctsxs
13789 || icode == CODE_FOR_altivec_vctuxs
13790 || icode == CODE_FOR_altivec_vspltb
13791 || icode == CODE_FOR_altivec_vsplth
13792 || icode == CODE_FOR_altivec_vspltw)
13794 /* Only allow 5-bit unsigned literals. */
13796 if (TREE_CODE (arg1) != INTEGER_CST
13797 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13799 error ("argument 2 must be a 5-bit unsigned literal");
13800 return CONST0_RTX (tmode);
13803 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13804 || icode == CODE_FOR_dfptstsfi_lt_dd
13805 || icode == CODE_FOR_dfptstsfi_gt_dd
13806 || icode == CODE_FOR_dfptstsfi_unordered_dd
13807 || icode == CODE_FOR_dfptstsfi_eq_td
13808 || icode == CODE_FOR_dfptstsfi_lt_td
13809 || icode == CODE_FOR_dfptstsfi_gt_td
13810 || icode == CODE_FOR_dfptstsfi_unordered_td)
13812 /* Only allow 6-bit unsigned literals. */
13814 if (TREE_CODE (arg0) != INTEGER_CST
13815 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13817 error ("argument 1 must be a 6-bit unsigned literal");
13818 return CONST0_RTX (tmode);
13821 else if (icode == CODE_FOR_xststdcqp_kf
13822 || icode == CODE_FOR_xststdcqp_tf
13823 || icode == CODE_FOR_xststdcdp
13824 || icode == CODE_FOR_xststdcsp
13825 || icode == CODE_FOR_xvtstdcdp
13826 || icode == CODE_FOR_xvtstdcsp)
13828 /* Only allow 7-bit unsigned literals. */
13830 if (TREE_CODE (arg1) != INTEGER_CST
13831 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13833 error ("argument 2 must be a 7-bit unsigned literal");
13834 return CONST0_RTX (tmode);
13837 else if (icode == CODE_FOR_unpackv1ti
13838 || icode == CODE_FOR_unpackkf
13839 || icode == CODE_FOR_unpacktf
13840 || icode == CODE_FOR_unpackif
13841 || icode == CODE_FOR_unpacktd)
13843 /* Only allow 1-bit unsigned literals. */
13845 if (TREE_CODE (arg1) != INTEGER_CST
13846 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13848 error ("argument 2 must be a 1-bit unsigned literal");
13849 return CONST0_RTX (tmode);
13854 || GET_MODE (target) != tmode
13855 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13856 target = gen_reg_rtx (tmode);
13858 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13859 op0 = copy_to_mode_reg (mode0, op0);
13860 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13861 op1 = copy_to_mode_reg (mode1, op1);
13863 pat = GEN_FCN (icode) (target, op0, op1);
13872 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13875 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13876 tree arg0 = CALL_EXPR_ARG (exp, 1);
13877 tree arg1 = CALL_EXPR_ARG (exp, 2);
13878 rtx op0 = expand_normal (arg0);
13879 rtx op1 = expand_normal (arg1);
13880 machine_mode tmode = SImode;
13881 machine_mode mode0 = insn_data[icode].operand[1].mode;
13882 machine_mode mode1 = insn_data[icode].operand[2].mode;
13885 if (TREE_CODE (cr6_form) != INTEGER_CST)
13887 error ("argument 1 of %qs must be a constant",
13888 "__builtin_altivec_predicate");
13892 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13894 gcc_assert (mode0 == mode1);
13896 /* If we have invalid arguments, bail out before generating bad rtl. */
13897 if (arg0 == error_mark_node || arg1 == error_mark_node)
13901 || GET_MODE (target) != tmode
13902 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13903 target = gen_reg_rtx (tmode);
13905 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13906 op0 = copy_to_mode_reg (mode0, op0);
13907 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13908 op1 = copy_to_mode_reg (mode1, op1);
13910 /* Note that for many of the relevant operations (e.g. cmpne or
13911 cmpeq) with float or double operands, it makes more sense for the
13912 mode of the allocated scratch register to select a vector of
13913 integer. But the choice to copy the mode of operand 0 was made
13914 long ago and there are no plans to change it. */
13915 scratch = gen_reg_rtx (mode0);
13917 pat = GEN_FCN (icode) (scratch, op0, op1);
13922 /* The vec_any* and vec_all* predicates use the same opcodes for two
13923 different operations, but the bits in CR6 will be different
13924 depending on what information we want. So we have to play tricks
13925 with CR6 to get the right bits out.
13927 If you think this is disgusting, look at the specs for the
13928 AltiVec predicates. */
13930 switch (cr6_form_int)
13933 emit_insn (gen_cr6_test_for_zero (target));
13936 emit_insn (gen_cr6_test_for_zero_reverse (target));
13939 emit_insn (gen_cr6_test_for_lt (target));
13942 emit_insn (gen_cr6_test_for_lt_reverse (target));
13945 error ("argument 1 of %qs is out of range",
13946 "__builtin_altivec_predicate");
13954 swap_endian_selector_for_mode (machine_mode mode)
13956 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13957 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13958 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13959 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13961 unsigned int *swaparray, i;
13981 gcc_unreachable ();
13984 for (i = 0; i < 16; ++i)
13985 perm[i] = GEN_INT (swaparray[i]);
13987 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13988 gen_rtvec_v (16, perm)));
13992 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13995 tree arg0 = CALL_EXPR_ARG (exp, 0);
13996 tree arg1 = CALL_EXPR_ARG (exp, 1);
13997 machine_mode tmode = insn_data[icode].operand[0].mode;
13998 machine_mode mode0 = Pmode;
13999 machine_mode mode1 = Pmode;
14000 rtx op0 = expand_normal (arg0);
14001 rtx op1 = expand_normal (arg1);
14003 if (icode == CODE_FOR_nothing)
14004 /* Builtin not supported on this processor. */
14007 /* If we got invalid arguments bail out before generating bad rtl. */
14008 if (arg0 == error_mark_node || arg1 == error_mark_node)
14012 || GET_MODE (target) != tmode
14013 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14014 target = gen_reg_rtx (tmode);
14016 op1 = copy_to_mode_reg (mode1, op1);
14018 /* For LVX, express the RTL accurately by ANDing the address with -16.
14019 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14020 so the raw address is fine. */
14021 if (icode == CODE_FOR_altivec_lvx_v1ti
14022 || icode == CODE_FOR_altivec_lvx_v2df
14023 || icode == CODE_FOR_altivec_lvx_v2di
14024 || icode == CODE_FOR_altivec_lvx_v4sf
14025 || icode == CODE_FOR_altivec_lvx_v4si
14026 || icode == CODE_FOR_altivec_lvx_v8hi
14027 || icode == CODE_FOR_altivec_lvx_v16qi)
14030 if (op0 == const0_rtx)
14034 op0 = copy_to_mode_reg (mode0, op0);
14035 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14037 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14038 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14040 emit_insn (gen_rtx_SET (target, addr));
14044 if (op0 == const0_rtx)
14045 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14048 op0 = copy_to_mode_reg (mode0, op0);
14049 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14050 gen_rtx_PLUS (Pmode, op1, op0));
14053 pat = GEN_FCN (icode) (target, addr);
14063 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14066 tree arg0 = CALL_EXPR_ARG (exp, 0);
14067 tree arg1 = CALL_EXPR_ARG (exp, 1);
14068 tree arg2 = CALL_EXPR_ARG (exp, 2);
14069 rtx op0 = expand_normal (arg0);
14070 rtx op1 = expand_normal (arg1);
14071 rtx op2 = expand_normal (arg2);
14072 machine_mode mode0 = insn_data[icode].operand[0].mode;
14073 machine_mode mode1 = insn_data[icode].operand[1].mode;
14074 machine_mode mode2 = insn_data[icode].operand[2].mode;
14076 if (icode == CODE_FOR_nothing)
14077 /* Builtin not supported on this processor. */
14080 /* If we got invalid arguments bail out before generating bad rtl. */
14081 if (arg0 == error_mark_node
14082 || arg1 == error_mark_node
14083 || arg2 == error_mark_node)
14086 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14087 op0 = copy_to_mode_reg (mode0, op0);
14088 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14089 op1 = copy_to_mode_reg (mode1, op1);
14090 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14091 op2 = copy_to_mode_reg (mode2, op2);
14093 pat = GEN_FCN (icode) (op0, op1, op2);
14101 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14103 tree arg0 = CALL_EXPR_ARG (exp, 0);
14104 tree arg1 = CALL_EXPR_ARG (exp, 1);
14105 tree arg2 = CALL_EXPR_ARG (exp, 2);
14106 rtx op0 = expand_normal (arg0);
14107 rtx op1 = expand_normal (arg1);
14108 rtx op2 = expand_normal (arg2);
14109 rtx pat, addr, rawaddr;
14110 machine_mode tmode = insn_data[icode].operand[0].mode;
14111 machine_mode smode = insn_data[icode].operand[1].mode;
14112 machine_mode mode1 = Pmode;
14113 machine_mode mode2 = Pmode;
14115 /* Invalid arguments. Bail before doing anything stoopid! */
14116 if (arg0 == error_mark_node
14117 || arg1 == error_mark_node
14118 || arg2 == error_mark_node)
14121 op2 = copy_to_mode_reg (mode2, op2);
14123 /* For STVX, express the RTL accurately by ANDing the address with -16.
14124 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14125 so the raw address is fine. */
14126 if (icode == CODE_FOR_altivec_stvx_v2df
14127 || icode == CODE_FOR_altivec_stvx_v2di
14128 || icode == CODE_FOR_altivec_stvx_v4sf
14129 || icode == CODE_FOR_altivec_stvx_v4si
14130 || icode == CODE_FOR_altivec_stvx_v8hi
14131 || icode == CODE_FOR_altivec_stvx_v16qi)
14133 if (op1 == const0_rtx)
14137 op1 = copy_to_mode_reg (mode1, op1);
14138 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14141 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14142 addr = gen_rtx_MEM (tmode, addr);
14144 op0 = copy_to_mode_reg (tmode, op0);
14146 emit_insn (gen_rtx_SET (addr, op0));
14150 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14151 op0 = copy_to_mode_reg (smode, op0);
14153 if (op1 == const0_rtx)
14154 addr = gen_rtx_MEM (tmode, op2);
14157 op1 = copy_to_mode_reg (mode1, op1);
14158 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14161 pat = GEN_FCN (icode) (addr, op0);
14169 /* Return the appropriate SPR number associated with the given builtin. */
14170 static inline HOST_WIDE_INT
14171 htm_spr_num (enum rs6000_builtins code)
14173 if (code == HTM_BUILTIN_GET_TFHAR
14174 || code == HTM_BUILTIN_SET_TFHAR)
14176 else if (code == HTM_BUILTIN_GET_TFIAR
14177 || code == HTM_BUILTIN_SET_TFIAR)
14179 else if (code == HTM_BUILTIN_GET_TEXASR
14180 || code == HTM_BUILTIN_SET_TEXASR)
14182 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14183 || code == HTM_BUILTIN_SET_TEXASRU);
14184 return TEXASRU_SPR;
14187 /* Return the appropriate SPR regno associated with the given builtin. */
14188 static inline HOST_WIDE_INT
14189 htm_spr_regno (enum rs6000_builtins code)
14191 if (code == HTM_BUILTIN_GET_TFHAR
14192 || code == HTM_BUILTIN_SET_TFHAR)
14193 return TFHAR_REGNO;
14194 else if (code == HTM_BUILTIN_GET_TFIAR
14195 || code == HTM_BUILTIN_SET_TFIAR)
14196 return TFIAR_REGNO;
14197 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14198 || code == HTM_BUILTIN_SET_TEXASR
14199 || code == HTM_BUILTIN_GET_TEXASRU
14200 || code == HTM_BUILTIN_SET_TEXASRU);
14201 return TEXASR_REGNO;
14204 /* Return the correct ICODE value depending on whether we are
14205 setting or reading the HTM SPRs. */
14206 static inline enum insn_code
14207 rs6000_htm_spr_icode (bool nonvoid)
14210 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14212 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14215 /* Expand the HTM builtin in EXP and store the result in TARGET.
14216 Store true in *EXPANDEDP if we found a builtin to expand. */
14218 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14220 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14221 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14222 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14223 const struct builtin_description *d;
14228 if (!TARGET_POWERPC64
14229 && (fcode == HTM_BUILTIN_TABORTDC
14230 || fcode == HTM_BUILTIN_TABORTDCI))
14232 size_t uns_fcode = (size_t)fcode;
14233 const char *name = rs6000_builtin_info[uns_fcode].name;
14234 error ("builtin %qs is only valid in 64-bit mode", name);
14238 /* Expand the HTM builtins. */
14240 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14241 if (d->code == fcode)
14243 rtx op[MAX_HTM_OPERANDS], pat;
14246 call_expr_arg_iterator iter;
14247 unsigned attr = rs6000_builtin_info[fcode].attr;
14248 enum insn_code icode = d->icode;
14249 const struct insn_operand_data *insn_op;
14250 bool uses_spr = (attr & RS6000_BTC_SPR);
14254 icode = rs6000_htm_spr_icode (nonvoid);
14255 insn_op = &insn_data[icode].operand[0];
14259 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14261 || GET_MODE (target) != tmode
14262 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14263 target = gen_reg_rtx (tmode);
14265 op[nopnds++] = target;
14268 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14270 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14273 insn_op = &insn_data[icode].operand[nopnds];
14275 op[nopnds] = expand_normal (arg);
14277 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14279 if (!strcmp (insn_op->constraint, "n"))
14281 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14282 if (!CONST_INT_P (op[nopnds]))
14283 error ("argument %d must be an unsigned literal", arg_num);
14285 error ("argument %d is an unsigned literal that is "
14286 "out of range", arg_num);
14289 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14295 /* Handle the builtins for extended mnemonics. These accept
14296 no arguments, but map to builtins that take arguments. */
14299 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14300 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14301 op[nopnds++] = GEN_INT (1);
14303 attr |= RS6000_BTC_UNARY;
14305 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14306 op[nopnds++] = GEN_INT (0);
14308 attr |= RS6000_BTC_UNARY;
14314 /* If this builtin accesses SPRs, then pass in the appropriate
14315 SPR number and SPR regno as the last two operands. */
14318 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14319 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14320 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14322 /* If this builtin accesses a CR, then pass in a scratch
14323 CR as the last operand. */
14324 else if (attr & RS6000_BTC_CR)
14325 { cr = gen_reg_rtx (CCmode);
14331 int expected_nopnds = 0;
14332 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14333 expected_nopnds = 1;
14334 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14335 expected_nopnds = 2;
14336 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14337 expected_nopnds = 3;
14338 if (!(attr & RS6000_BTC_VOID))
14339 expected_nopnds += 1;
14341 expected_nopnds += 2;
14343 gcc_assert (nopnds == expected_nopnds
14344 && nopnds <= MAX_HTM_OPERANDS);
14350 pat = GEN_FCN (icode) (op[0]);
14353 pat = GEN_FCN (icode) (op[0], op[1]);
14356 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14359 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14362 gcc_unreachable ();
14368 if (attr & RS6000_BTC_CR)
14370 if (fcode == HTM_BUILTIN_TBEGIN)
14372 /* Emit code to set TARGET to true or false depending on
14373 whether the tbegin. instruction successfully or failed
14374 to start a transaction. We do this by placing the 1's
14375 complement of CR's EQ bit into TARGET. */
14376 rtx scratch = gen_reg_rtx (SImode);
14377 emit_insn (gen_rtx_SET (scratch,
14378 gen_rtx_EQ (SImode, cr,
14380 emit_insn (gen_rtx_SET (target,
14381 gen_rtx_XOR (SImode, scratch,
14386 /* Emit code to copy the 4-bit condition register field
14387 CR into the least significant end of register TARGET. */
14388 rtx scratch1 = gen_reg_rtx (SImode);
14389 rtx scratch2 = gen_reg_rtx (SImode);
14390 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14391 emit_insn (gen_movcc (subreg, cr));
14392 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14393 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14402 *expandedp = false;
14406 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14409 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14412 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14413 if (fcode == RS6000_BUILTIN_CPU_INIT)
14416 if (target == 0 || GET_MODE (target) != SImode)
14417 target = gen_reg_rtx (SImode);
14419 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14420 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14421 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14422 to a STRING_CST. */
14423 if (TREE_CODE (arg) == ARRAY_REF
14424 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14425 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14426 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14427 arg = TREE_OPERAND (arg, 0);
14429 if (TREE_CODE (arg) != STRING_CST)
14431 error ("builtin %qs only accepts a string argument",
14432 rs6000_builtin_info[(size_t) fcode].name);
14436 if (fcode == RS6000_BUILTIN_CPU_IS)
14438 const char *cpu = TREE_STRING_POINTER (arg);
14439 rtx cpuid = NULL_RTX;
14440 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14441 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14443 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14444 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14447 if (cpuid == NULL_RTX)
14449 /* Invalid CPU argument. */
14450 error ("cpu %qs is an invalid argument to builtin %qs",
14451 cpu, rs6000_builtin_info[(size_t) fcode].name);
14455 rtx platform = gen_reg_rtx (SImode);
14456 rtx tcbmem = gen_const_mem (SImode,
14457 gen_rtx_PLUS (Pmode,
14458 gen_rtx_REG (Pmode, TLS_REGNUM),
14459 GEN_INT (TCB_PLATFORM_OFFSET)));
14460 emit_move_insn (platform, tcbmem);
14461 emit_insn (gen_eqsi3 (target, platform, cpuid));
14463 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14465 const char *hwcap = TREE_STRING_POINTER (arg);
14466 rtx mask = NULL_RTX;
14468 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14469 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14471 mask = GEN_INT (cpu_supports_info[i].mask);
14472 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14475 if (mask == NULL_RTX)
14477 /* Invalid HWCAP argument. */
14478 error ("%s %qs is an invalid argument to builtin %qs",
14479 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14483 rtx tcb_hwcap = gen_reg_rtx (SImode);
14484 rtx tcbmem = gen_const_mem (SImode,
14485 gen_rtx_PLUS (Pmode,
14486 gen_rtx_REG (Pmode, TLS_REGNUM),
14487 GEN_INT (hwcap_offset)));
14488 emit_move_insn (tcb_hwcap, tcbmem);
14489 rtx scratch1 = gen_reg_rtx (SImode);
14490 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14491 rtx scratch2 = gen_reg_rtx (SImode);
14492 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14493 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14496 gcc_unreachable ();
14498 /* Record that we have expanded a CPU builtin, so that we can later
14499 emit a reference to the special symbol exported by LIBC to ensure we
14500 do not link against an old LIBC that doesn't support this feature. */
14501 cpu_builtin_p = true;
14504 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14505 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14507 /* For old LIBCs, always return FALSE. */
14508 emit_move_insn (target, GEN_INT (0));
14509 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14515 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14518 tree arg0 = CALL_EXPR_ARG (exp, 0);
14519 tree arg1 = CALL_EXPR_ARG (exp, 1);
14520 tree arg2 = CALL_EXPR_ARG (exp, 2);
14521 rtx op0 = expand_normal (arg0);
14522 rtx op1 = expand_normal (arg1);
14523 rtx op2 = expand_normal (arg2);
14524 machine_mode tmode = insn_data[icode].operand[0].mode;
14525 machine_mode mode0 = insn_data[icode].operand[1].mode;
14526 machine_mode mode1 = insn_data[icode].operand[2].mode;
14527 machine_mode mode2 = insn_data[icode].operand[3].mode;
14529 if (icode == CODE_FOR_nothing)
14530 /* Builtin not supported on this processor. */
14533 /* If we got invalid arguments bail out before generating bad rtl. */
14534 if (arg0 == error_mark_node
14535 || arg1 == error_mark_node
14536 || arg2 == error_mark_node)
14539 /* Check and prepare argument depending on the instruction code.
14541 Note that a switch statement instead of the sequence of tests
14542 would be incorrect as many of the CODE_FOR values could be
14543 CODE_FOR_nothing and that would yield multiple alternatives
14544 with identical values. We'd never reach here at runtime in
14546 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14547 || icode == CODE_FOR_altivec_vsldoi_v2df
14548 || icode == CODE_FOR_altivec_vsldoi_v4si
14549 || icode == CODE_FOR_altivec_vsldoi_v8hi
14550 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14552 /* Only allow 4-bit unsigned literals. */
14554 if (TREE_CODE (arg2) != INTEGER_CST
14555 || TREE_INT_CST_LOW (arg2) & ~0xf)
14557 error ("argument 3 must be a 4-bit unsigned literal");
14558 return CONST0_RTX (tmode);
14561 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14562 || icode == CODE_FOR_vsx_xxpermdi_v2di
14563 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14564 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14565 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14566 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14567 || icode == CODE_FOR_vsx_xxpermdi_v4si
14568 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14569 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14570 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14571 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14572 || icode == CODE_FOR_vsx_xxsldwi_v4si
14573 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14574 || icode == CODE_FOR_vsx_xxsldwi_v2di
14575 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14577 /* Only allow 2-bit unsigned literals. */
14579 if (TREE_CODE (arg2) != INTEGER_CST
14580 || TREE_INT_CST_LOW (arg2) & ~0x3)
14582 error ("argument 3 must be a 2-bit unsigned literal");
14583 return CONST0_RTX (tmode);
14586 else if (icode == CODE_FOR_vsx_set_v2df
14587 || icode == CODE_FOR_vsx_set_v2di
14588 || icode == CODE_FOR_bcdadd
14589 || icode == CODE_FOR_bcdadd_lt
14590 || icode == CODE_FOR_bcdadd_eq
14591 || icode == CODE_FOR_bcdadd_gt
14592 || icode == CODE_FOR_bcdsub
14593 || icode == CODE_FOR_bcdsub_lt
14594 || icode == CODE_FOR_bcdsub_eq
14595 || icode == CODE_FOR_bcdsub_gt)
14597 /* Only allow 1-bit unsigned literals. */
14599 if (TREE_CODE (arg2) != INTEGER_CST
14600 || TREE_INT_CST_LOW (arg2) & ~0x1)
14602 error ("argument 3 must be a 1-bit unsigned literal");
14603 return CONST0_RTX (tmode);
14606 else if (icode == CODE_FOR_dfp_ddedpd_dd
14607 || icode == CODE_FOR_dfp_ddedpd_td)
14609 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14611 if (TREE_CODE (arg0) != INTEGER_CST
14612 || TREE_INT_CST_LOW (arg2) & ~0x3)
14614 error ("argument 1 must be 0 or 2");
14615 return CONST0_RTX (tmode);
14618 else if (icode == CODE_FOR_dfp_denbcd_dd
14619 || icode == CODE_FOR_dfp_denbcd_td)
14621 /* Only allow 1-bit unsigned literals. */
14623 if (TREE_CODE (arg0) != INTEGER_CST
14624 || TREE_INT_CST_LOW (arg0) & ~0x1)
14626 error ("argument 1 must be a 1-bit unsigned literal");
14627 return CONST0_RTX (tmode);
14630 else if (icode == CODE_FOR_dfp_dscli_dd
14631 || icode == CODE_FOR_dfp_dscli_td
14632 || icode == CODE_FOR_dfp_dscri_dd
14633 || icode == CODE_FOR_dfp_dscri_td)
14635 /* Only allow 6-bit unsigned literals. */
14637 if (TREE_CODE (arg1) != INTEGER_CST
14638 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14640 error ("argument 2 must be a 6-bit unsigned literal");
14641 return CONST0_RTX (tmode);
14644 else if (icode == CODE_FOR_crypto_vshasigmaw
14645 || icode == CODE_FOR_crypto_vshasigmad)
14647 /* Check whether the 2nd and 3rd arguments are integer constants and in
14648 range and prepare arguments. */
14650 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14652 error ("argument 2 must be 0 or 1");
14653 return CONST0_RTX (tmode);
14657 if (TREE_CODE (arg2) != INTEGER_CST
14658 || wi::geu_p (wi::to_wide (arg2), 16))
14660 error ("argument 3 must be in the range 0..15");
14661 return CONST0_RTX (tmode);
14666 || GET_MODE (target) != tmode
14667 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14668 target = gen_reg_rtx (tmode);
14670 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14671 op0 = copy_to_mode_reg (mode0, op0);
14672 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14673 op1 = copy_to_mode_reg (mode1, op1);
14674 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14675 op2 = copy_to_mode_reg (mode2, op2);
14677 pat = GEN_FCN (icode) (target, op0, op1, op2);
14686 /* Expand the dst builtins. */
14688 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14691 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14692 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14693 tree arg0, arg1, arg2;
14694 machine_mode mode0, mode1;
14695 rtx pat, op0, op1, op2;
14696 const struct builtin_description *d;
14699 *expandedp = false;
14701 /* Handle DST variants. */
14703 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14704 if (d->code == fcode)
14706 arg0 = CALL_EXPR_ARG (exp, 0);
14707 arg1 = CALL_EXPR_ARG (exp, 1);
14708 arg2 = CALL_EXPR_ARG (exp, 2);
14709 op0 = expand_normal (arg0);
14710 op1 = expand_normal (arg1);
14711 op2 = expand_normal (arg2);
14712 mode0 = insn_data[d->icode].operand[0].mode;
14713 mode1 = insn_data[d->icode].operand[1].mode;
14715 /* Invalid arguments, bail out before generating bad rtl. */
14716 if (arg0 == error_mark_node
14717 || arg1 == error_mark_node
14718 || arg2 == error_mark_node)
14723 if (TREE_CODE (arg2) != INTEGER_CST
14724 || TREE_INT_CST_LOW (arg2) & ~0x3)
14726 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14730 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14731 op0 = copy_to_mode_reg (Pmode, op0);
14732 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14733 op1 = copy_to_mode_reg (mode1, op1);
14735 pat = GEN_FCN (d->icode) (op0, op1, op2);
14745 /* Expand vec_init builtin. */
14747 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14749 machine_mode tmode = TYPE_MODE (type);
14750 machine_mode inner_mode = GET_MODE_INNER (tmode);
14751 int i, n_elt = GET_MODE_NUNITS (tmode);
14753 gcc_assert (VECTOR_MODE_P (tmode));
14754 gcc_assert (n_elt == call_expr_nargs (exp));
14756 if (!target || !register_operand (target, tmode))
14757 target = gen_reg_rtx (tmode);
14759 /* If we have a vector compromised of a single element, such as V1TImode, do
14760 the initialization directly. */
14761 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14763 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14764 emit_move_insn (target, gen_lowpart (tmode, x));
14768 rtvec v = rtvec_alloc (n_elt);
14770 for (i = 0; i < n_elt; ++i)
14772 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14773 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14776 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14782 /* Return the integer constant in ARG. Constrain it to be in the range
14783 of the subparts of VEC_TYPE; issue an error if not. */
14786 get_element_number (tree vec_type, tree arg)
14788 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14790 if (!tree_fits_uhwi_p (arg)
14791 || (elt = tree_to_uhwi (arg), elt > max))
14793 error ("selector must be an integer constant in the range 0..%wi", max);
14800 /* Expand vec_set builtin. */
14802 altivec_expand_vec_set_builtin (tree exp)
14804 machine_mode tmode, mode1;
14805 tree arg0, arg1, arg2;
14809 arg0 = CALL_EXPR_ARG (exp, 0);
14810 arg1 = CALL_EXPR_ARG (exp, 1);
14811 arg2 = CALL_EXPR_ARG (exp, 2);
14813 tmode = TYPE_MODE (TREE_TYPE (arg0));
14814 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14815 gcc_assert (VECTOR_MODE_P (tmode));
14817 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14818 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14819 elt = get_element_number (TREE_TYPE (arg0), arg2);
14821 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14822 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14824 op0 = force_reg (tmode, op0);
14825 op1 = force_reg (mode1, op1);
14827 rs6000_expand_vector_set (op0, op1, elt);
14832 /* Expand vec_ext builtin. */
14834 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14836 machine_mode tmode, mode0;
14841 arg0 = CALL_EXPR_ARG (exp, 0);
14842 arg1 = CALL_EXPR_ARG (exp, 1);
14844 op0 = expand_normal (arg0);
14845 op1 = expand_normal (arg1);
14847 /* Call get_element_number to validate arg1 if it is a constant. */
14848 if (TREE_CODE (arg1) == INTEGER_CST)
14849 (void) get_element_number (TREE_TYPE (arg0), arg1);
14851 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14852 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14853 gcc_assert (VECTOR_MODE_P (mode0));
14855 op0 = force_reg (mode0, op0);
14857 if (optimize || !target || !register_operand (target, tmode))
14858 target = gen_reg_rtx (tmode);
14860 rs6000_expand_vector_extract (target, op0, op1);
14865 /* Expand the builtin in EXP and store the result in TARGET. Store
14866 true in *EXPANDEDP if we found a builtin to expand. */
14868 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14870 const struct builtin_description *d;
14872 enum insn_code icode;
14873 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14874 tree arg0, arg1, arg2;
14876 machine_mode tmode, mode0;
14877 enum rs6000_builtins fcode
14878 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14880 if (rs6000_overloaded_builtin_p (fcode))
14883 error ("unresolved overload for Altivec builtin %qF", fndecl);
14885 /* Given it is invalid, just generate a normal call. */
14886 return expand_call (exp, target, false);
14889 target = altivec_expand_dst_builtin (exp, target, expandedp);
14897 case ALTIVEC_BUILTIN_STVX_V2DF:
14898 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14899 case ALTIVEC_BUILTIN_STVX_V2DI:
14900 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14901 case ALTIVEC_BUILTIN_STVX_V4SF:
14902 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14903 case ALTIVEC_BUILTIN_STVX:
14904 case ALTIVEC_BUILTIN_STVX_V4SI:
14905 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14906 case ALTIVEC_BUILTIN_STVX_V8HI:
14907 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14908 case ALTIVEC_BUILTIN_STVX_V16QI:
14909 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14910 case ALTIVEC_BUILTIN_STVEBX:
14911 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14912 case ALTIVEC_BUILTIN_STVEHX:
14913 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14914 case ALTIVEC_BUILTIN_STVEWX:
14915 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14916 case ALTIVEC_BUILTIN_STVXL_V2DF:
14917 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14918 case ALTIVEC_BUILTIN_STVXL_V2DI:
14919 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14920 case ALTIVEC_BUILTIN_STVXL_V4SF:
14921 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14922 case ALTIVEC_BUILTIN_STVXL:
14923 case ALTIVEC_BUILTIN_STVXL_V4SI:
14924 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14925 case ALTIVEC_BUILTIN_STVXL_V8HI:
14926 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14927 case ALTIVEC_BUILTIN_STVXL_V16QI:
14928 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14930 case ALTIVEC_BUILTIN_STVLX:
14931 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14932 case ALTIVEC_BUILTIN_STVLXL:
14933 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14934 case ALTIVEC_BUILTIN_STVRX:
14935 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14936 case ALTIVEC_BUILTIN_STVRXL:
14937 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14939 case P9V_BUILTIN_STXVL:
14940 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14942 case P9V_BUILTIN_XST_LEN_R:
14943 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14945 case VSX_BUILTIN_STXVD2X_V1TI:
14946 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14947 case VSX_BUILTIN_STXVD2X_V2DF:
14948 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14949 case VSX_BUILTIN_STXVD2X_V2DI:
14950 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14951 case VSX_BUILTIN_STXVW4X_V4SF:
14952 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14953 case VSX_BUILTIN_STXVW4X_V4SI:
14954 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14955 case VSX_BUILTIN_STXVW4X_V8HI:
14956 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14957 case VSX_BUILTIN_STXVW4X_V16QI:
14958 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14960 /* For the following on big endian, it's ok to use any appropriate
14961 unaligned-supporting store, so use a generic expander. For
14962 little-endian, the exact element-reversing instruction must
14964 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14966 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14967 : CODE_FOR_vsx_st_elemrev_v1ti);
14968 return altivec_expand_stv_builtin (code, exp);
14970 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14972 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14973 : CODE_FOR_vsx_st_elemrev_v2df);
14974 return altivec_expand_stv_builtin (code, exp);
14976 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14978 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14979 : CODE_FOR_vsx_st_elemrev_v2di);
14980 return altivec_expand_stv_builtin (code, exp);
14982 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14984 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14985 : CODE_FOR_vsx_st_elemrev_v4sf);
14986 return altivec_expand_stv_builtin (code, exp);
14988 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14990 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14991 : CODE_FOR_vsx_st_elemrev_v4si);
14992 return altivec_expand_stv_builtin (code, exp);
14994 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14996 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14997 : CODE_FOR_vsx_st_elemrev_v8hi);
14998 return altivec_expand_stv_builtin (code, exp);
15000 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15002 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15003 : CODE_FOR_vsx_st_elemrev_v16qi);
15004 return altivec_expand_stv_builtin (code, exp);
15007 case ALTIVEC_BUILTIN_MFVSCR:
15008 icode = CODE_FOR_altivec_mfvscr;
15009 tmode = insn_data[icode].operand[0].mode;
15012 || GET_MODE (target) != tmode
15013 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15014 target = gen_reg_rtx (tmode);
15016 pat = GEN_FCN (icode) (target);
15022 case ALTIVEC_BUILTIN_MTVSCR:
15023 icode = CODE_FOR_altivec_mtvscr;
15024 arg0 = CALL_EXPR_ARG (exp, 0);
15025 op0 = expand_normal (arg0);
15026 mode0 = insn_data[icode].operand[0].mode;
15028 /* If we got invalid arguments bail out before generating bad rtl. */
15029 if (arg0 == error_mark_node)
15032 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15033 op0 = copy_to_mode_reg (mode0, op0);
15035 pat = GEN_FCN (icode) (op0);
15040 case ALTIVEC_BUILTIN_DSSALL:
15041 emit_insn (gen_altivec_dssall ());
15044 case ALTIVEC_BUILTIN_DSS:
15045 icode = CODE_FOR_altivec_dss;
15046 arg0 = CALL_EXPR_ARG (exp, 0);
15048 op0 = expand_normal (arg0);
15049 mode0 = insn_data[icode].operand[0].mode;
15051 /* If we got invalid arguments bail out before generating bad rtl. */
15052 if (arg0 == error_mark_node)
15055 if (TREE_CODE (arg0) != INTEGER_CST
15056 || TREE_INT_CST_LOW (arg0) & ~0x3)
15058 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15062 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15063 op0 = copy_to_mode_reg (mode0, op0);
15065 emit_insn (gen_altivec_dss (op0));
15068 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15069 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15070 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15071 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15072 case VSX_BUILTIN_VEC_INIT_V2DF:
15073 case VSX_BUILTIN_VEC_INIT_V2DI:
15074 case VSX_BUILTIN_VEC_INIT_V1TI:
15075 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15077 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15078 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15079 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15080 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15081 case VSX_BUILTIN_VEC_SET_V2DF:
15082 case VSX_BUILTIN_VEC_SET_V2DI:
15083 case VSX_BUILTIN_VEC_SET_V1TI:
15084 return altivec_expand_vec_set_builtin (exp);
15086 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15087 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15088 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15089 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15090 case VSX_BUILTIN_VEC_EXT_V2DF:
15091 case VSX_BUILTIN_VEC_EXT_V2DI:
15092 case VSX_BUILTIN_VEC_EXT_V1TI:
15093 return altivec_expand_vec_ext_builtin (exp, target);
15095 case P9V_BUILTIN_VEC_EXTRACT4B:
15096 arg1 = CALL_EXPR_ARG (exp, 1);
15099 /* Generate a normal call if it is invalid. */
15100 if (arg1 == error_mark_node)
15101 return expand_call (exp, target, false);
15103 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15105 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15106 return expand_call (exp, target, false);
15110 case P9V_BUILTIN_VEC_INSERT4B:
15111 arg2 = CALL_EXPR_ARG (exp, 2);
15114 /* Generate a normal call if it is invalid. */
15115 if (arg2 == error_mark_node)
15116 return expand_call (exp, target, false);
15118 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15120 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15121 return expand_call (exp, target, false);
15127 /* Fall through. */
15130 /* Expand abs* operations. */
15132 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15133 if (d->code == fcode)
15134 return altivec_expand_abs_builtin (d->icode, exp, target);
15136 /* Expand the AltiVec predicates. */
15137 d = bdesc_altivec_preds;
15138 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15139 if (d->code == fcode)
15140 return altivec_expand_predicate_builtin (d->icode, exp, target);
15142 /* LV* are funky. We initialized them differently. */
15145 case ALTIVEC_BUILTIN_LVSL:
15146 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15147 exp, target, false);
15148 case ALTIVEC_BUILTIN_LVSR:
15149 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15150 exp, target, false);
15151 case ALTIVEC_BUILTIN_LVEBX:
15152 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15153 exp, target, false);
15154 case ALTIVEC_BUILTIN_LVEHX:
15155 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15156 exp, target, false);
15157 case ALTIVEC_BUILTIN_LVEWX:
15158 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15159 exp, target, false);
15160 case ALTIVEC_BUILTIN_LVXL_V2DF:
15161 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15162 exp, target, false);
15163 case ALTIVEC_BUILTIN_LVXL_V2DI:
15164 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15165 exp, target, false);
15166 case ALTIVEC_BUILTIN_LVXL_V4SF:
15167 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15168 exp, target, false);
15169 case ALTIVEC_BUILTIN_LVXL:
15170 case ALTIVEC_BUILTIN_LVXL_V4SI:
15171 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15172 exp, target, false);
15173 case ALTIVEC_BUILTIN_LVXL_V8HI:
15174 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15175 exp, target, false);
15176 case ALTIVEC_BUILTIN_LVXL_V16QI:
15177 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15178 exp, target, false);
15179 case ALTIVEC_BUILTIN_LVX_V1TI:
15180 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
15181 exp, target, false);
15182 case ALTIVEC_BUILTIN_LVX_V2DF:
15183 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
15184 exp, target, false);
15185 case ALTIVEC_BUILTIN_LVX_V2DI:
15186 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
15187 exp, target, false);
15188 case ALTIVEC_BUILTIN_LVX_V4SF:
15189 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
15190 exp, target, false);
15191 case ALTIVEC_BUILTIN_LVX:
15192 case ALTIVEC_BUILTIN_LVX_V4SI:
15193 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
15194 exp, target, false);
15195 case ALTIVEC_BUILTIN_LVX_V8HI:
15196 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
15197 exp, target, false);
15198 case ALTIVEC_BUILTIN_LVX_V16QI:
15199 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
15200 exp, target, false);
15201 case ALTIVEC_BUILTIN_LVLX:
15202 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15203 exp, target, true);
15204 case ALTIVEC_BUILTIN_LVLXL:
15205 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15206 exp, target, true);
15207 case ALTIVEC_BUILTIN_LVRX:
15208 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15209 exp, target, true);
15210 case ALTIVEC_BUILTIN_LVRXL:
15211 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15212 exp, target, true);
15213 case VSX_BUILTIN_LXVD2X_V1TI:
15214 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15215 exp, target, false);
15216 case VSX_BUILTIN_LXVD2X_V2DF:
15217 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15218 exp, target, false);
15219 case VSX_BUILTIN_LXVD2X_V2DI:
15220 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15221 exp, target, false);
15222 case VSX_BUILTIN_LXVW4X_V4SF:
15223 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15224 exp, target, false);
15225 case VSX_BUILTIN_LXVW4X_V4SI:
15226 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15227 exp, target, false);
15228 case VSX_BUILTIN_LXVW4X_V8HI:
15229 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15230 exp, target, false);
15231 case VSX_BUILTIN_LXVW4X_V16QI:
15232 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15233 exp, target, false);
15234 /* For the following on big endian, it's ok to use any appropriate
15235 unaligned-supporting load, so use a generic expander. For
15236 little-endian, the exact element-reversing instruction must
15238 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15240 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15241 : CODE_FOR_vsx_ld_elemrev_v2df);
15242 return altivec_expand_lv_builtin (code, exp, target, false);
15244 case VSX_BUILTIN_LD_ELEMREV_V1TI:
15246 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
15247 : CODE_FOR_vsx_ld_elemrev_v1ti);
15248 return altivec_expand_lv_builtin (code, exp, target, false);
15250 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15252 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15253 : CODE_FOR_vsx_ld_elemrev_v2di);
15254 return altivec_expand_lv_builtin (code, exp, target, false);
15256 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15258 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15259 : CODE_FOR_vsx_ld_elemrev_v4sf);
15260 return altivec_expand_lv_builtin (code, exp, target, false);
15262 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15264 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15265 : CODE_FOR_vsx_ld_elemrev_v4si);
15266 return altivec_expand_lv_builtin (code, exp, target, false);
15268 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15270 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15271 : CODE_FOR_vsx_ld_elemrev_v8hi);
15272 return altivec_expand_lv_builtin (code, exp, target, false);
15274 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15276 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15277 : CODE_FOR_vsx_ld_elemrev_v16qi);
15278 return altivec_expand_lv_builtin (code, exp, target, false);
15283 /* Fall through. */
15286 *expandedp = false;
15290 /* Check whether a builtin function is supported in this target
15293 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
15295 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
15296 if ((fnmask & rs6000_builtin_mask) != fnmask)
15302 /* Raise an error message for a builtin function that is called without the
15303 appropriate target options being set. */
15306 rs6000_invalid_builtin (enum rs6000_builtins fncode)
15308 size_t uns_fncode = (size_t) fncode;
15309 const char *name = rs6000_builtin_info[uns_fncode].name;
15310 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
15312 gcc_assert (name != NULL);
15313 if ((fnmask & RS6000_BTM_CELL) != 0)
15314 error ("builtin function %qs is only valid for the cell processor", name);
15315 else if ((fnmask & RS6000_BTM_VSX) != 0)
15316 error ("builtin function %qs requires the %qs option", name, "-mvsx");
15317 else if ((fnmask & RS6000_BTM_HTM) != 0)
15318 error ("builtin function %qs requires the %qs option", name, "-mhtm");
15319 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
15320 error ("builtin function %qs requires the %qs option", name, "-maltivec");
15321 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15322 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15323 error ("builtin function %qs requires the %qs and %qs options",
15324 name, "-mhard-dfp", "-mpower8-vector");
15325 else if ((fnmask & RS6000_BTM_DFP) != 0)
15326 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
15327 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
15328 error ("builtin function %qs requires the %qs option", name,
15329 "-mpower8-vector");
15330 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15331 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15332 error ("builtin function %qs requires the %qs and %qs options",
15333 name, "-mcpu=power9", "-m64");
15334 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
15335 error ("builtin function %qs requires the %qs option", name,
15337 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15338 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15339 error ("builtin function %qs requires the %qs and %qs options",
15340 name, "-mcpu=power9", "-m64");
15341 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
15342 error ("builtin function %qs requires the %qs option", name,
15344 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
15346 if (!TARGET_HARD_FLOAT)
15347 error ("builtin function %qs requires the %qs option", name,
15350 error ("builtin function %qs requires the %qs option", name,
15351 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
15353 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
15354 error ("builtin function %qs requires the %qs option", name,
15356 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
15357 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15359 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
15360 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
15361 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15362 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15363 error ("builtin function %qs requires the %qs (or newer), and "
15364 "%qs or %qs options",
15365 name, "-mcpu=power7", "-m64", "-mpowerpc64");
15367 error ("builtin function %qs is not supported with the current options",
15371 /* Target hook for early folding of built-ins, shamelessly stolen
15375 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
15376 int n_args ATTRIBUTE_UNUSED,
15377 tree *args ATTRIBUTE_UNUSED,
15378 bool ignore ATTRIBUTE_UNUSED)
15380 #ifdef SUBTARGET_FOLD_BUILTIN
15381 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
15387 /* Helper function to sort out which built-ins may be valid without having
15390 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
15394 case ALTIVEC_BUILTIN_STVX_V16QI:
15395 case ALTIVEC_BUILTIN_STVX_V8HI:
15396 case ALTIVEC_BUILTIN_STVX_V4SI:
15397 case ALTIVEC_BUILTIN_STVX_V4SF:
15398 case ALTIVEC_BUILTIN_STVX_V2DI:
15399 case ALTIVEC_BUILTIN_STVX_V2DF:
15406 /* Helper function to handle the gimple folding of a vector compare
15407 operation. This sets up true/false vectors, and uses the
15408 VEC_COND_EXPR operation.
15409 CODE indicates which comparison is to be made. (EQ, GT, ...).
15410 TYPE indicates the type of the result. */
15412 fold_build_vec_cmp (tree_code code, tree type,
15413 tree arg0, tree arg1)
15415 tree cmp_type = build_same_sized_truth_vector_type (type);
15416 tree zero_vec = build_zero_cst (type);
15417 tree minus_one_vec = build_minus_one_cst (type);
15418 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
15419 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
15422 /* Helper function to handle the in-between steps for the
15423 vector compare built-ins. */
15425 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
15427 tree arg0 = gimple_call_arg (stmt, 0);
15428 tree arg1 = gimple_call_arg (stmt, 1);
15429 tree lhs = gimple_call_lhs (stmt);
15430 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
15431 gimple *g = gimple_build_assign (lhs, cmp);
15432 gimple_set_location (g, gimple_location (stmt));
15433 gsi_replace (gsi, g, true);
15436 /* Helper function to handle the vector merge[hl] built-ins. The
15437 implementation difference between h and l versions for this code are in
15438 the values used when building of the permute vector for high word versus
15439 low word merge. The variance is keyed off the use_high parameter. */
15441 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15443 tree arg0 = gimple_call_arg (stmt, 0);
15444 tree arg1 = gimple_call_arg (stmt, 1);
15445 tree lhs = gimple_call_lhs (stmt);
15446 tree lhs_type = TREE_TYPE (lhs);
15447 tree lhs_type_type = TREE_TYPE (lhs_type);
15448 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15449 int midpoint = n_elts / 2;
15455 tree_vector_builder elts (lhs_type, VECTOR_CST_NELTS (arg0), 1);
15457 for (int i = 0; i < midpoint; i++)
15459 elts.safe_push (build_int_cst (lhs_type_type, offset + i));
15460 elts.safe_push (build_int_cst (lhs_type_type, offset + n_elts + i));
15463 tree permute = elts.build ();
15465 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15466 gimple_set_location (g, gimple_location (stmt));
15467 gsi_replace (gsi, g, true);
15470 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15471 a constant, use rs6000_fold_builtin.) */
15474 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15476 gimple *stmt = gsi_stmt (*gsi);
15477 tree fndecl = gimple_call_fndecl (stmt);
15478 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15479 enum rs6000_builtins fn_code
15480 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15481 tree arg0, arg1, lhs, temp;
15484 size_t uns_fncode = (size_t) fn_code;
15485 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15486 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15487 const char *fn_name2 = (icode != CODE_FOR_nothing)
15488 ? get_insn_name ((int) icode)
15491 if (TARGET_DEBUG_BUILTIN)
15492 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15493 fn_code, fn_name1, fn_name2);
15495 if (!rs6000_fold_gimple)
15498 /* Prevent gimple folding for code that does not have a LHS, unless it is
15499 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15500 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15503 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15504 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15505 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15511 /* Flavors of vec_add. We deliberately don't expand
15512 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15513 TImode, resulting in much poorer code generation. */
15514 case ALTIVEC_BUILTIN_VADDUBM:
15515 case ALTIVEC_BUILTIN_VADDUHM:
15516 case ALTIVEC_BUILTIN_VADDUWM:
15517 case P8V_BUILTIN_VADDUDM:
15518 case ALTIVEC_BUILTIN_VADDFP:
15519 case VSX_BUILTIN_XVADDDP:
15520 arg0 = gimple_call_arg (stmt, 0);
15521 arg1 = gimple_call_arg (stmt, 1);
15522 lhs = gimple_call_lhs (stmt);
15523 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
15524 gimple_set_location (g, gimple_location (stmt));
15525 gsi_replace (gsi, g, true);
15527 /* Flavors of vec_sub. We deliberately don't expand
15528 P8V_BUILTIN_VSUBUQM. */
15529 case ALTIVEC_BUILTIN_VSUBUBM:
15530 case ALTIVEC_BUILTIN_VSUBUHM:
15531 case ALTIVEC_BUILTIN_VSUBUWM:
15532 case P8V_BUILTIN_VSUBUDM:
15533 case ALTIVEC_BUILTIN_VSUBFP:
15534 case VSX_BUILTIN_XVSUBDP:
15535 arg0 = gimple_call_arg (stmt, 0);
15536 arg1 = gimple_call_arg (stmt, 1);
15537 lhs = gimple_call_lhs (stmt);
15538 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
15539 gimple_set_location (g, gimple_location (stmt));
15540 gsi_replace (gsi, g, true);
15542 case VSX_BUILTIN_XVMULSP:
15543 case VSX_BUILTIN_XVMULDP:
15544 arg0 = gimple_call_arg (stmt, 0);
15545 arg1 = gimple_call_arg (stmt, 1);
15546 lhs = gimple_call_lhs (stmt);
15547 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15548 gimple_set_location (g, gimple_location (stmt));
15549 gsi_replace (gsi, g, true);
15551 /* Even element flavors of vec_mul (signed). */
15552 case ALTIVEC_BUILTIN_VMULESB:
15553 case ALTIVEC_BUILTIN_VMULESH:
15554 case P8V_BUILTIN_VMULESW:
15555 /* Even element flavors of vec_mul (unsigned). */
15556 case ALTIVEC_BUILTIN_VMULEUB:
15557 case ALTIVEC_BUILTIN_VMULEUH:
15558 case P8V_BUILTIN_VMULEUW:
15559 arg0 = gimple_call_arg (stmt, 0);
15560 arg1 = gimple_call_arg (stmt, 1);
15561 lhs = gimple_call_lhs (stmt);
15562 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15563 gimple_set_location (g, gimple_location (stmt));
15564 gsi_replace (gsi, g, true);
15566 /* Odd element flavors of vec_mul (signed). */
15567 case ALTIVEC_BUILTIN_VMULOSB:
15568 case ALTIVEC_BUILTIN_VMULOSH:
15569 case P8V_BUILTIN_VMULOSW:
15570 /* Odd element flavors of vec_mul (unsigned). */
15571 case ALTIVEC_BUILTIN_VMULOUB:
15572 case ALTIVEC_BUILTIN_VMULOUH:
15573 case P8V_BUILTIN_VMULOUW:
15574 arg0 = gimple_call_arg (stmt, 0);
15575 arg1 = gimple_call_arg (stmt, 1);
15576 lhs = gimple_call_lhs (stmt);
15577 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15578 gimple_set_location (g, gimple_location (stmt));
15579 gsi_replace (gsi, g, true);
15581 /* Flavors of vec_div (Integer). */
15582 case VSX_BUILTIN_DIV_V2DI:
15583 case VSX_BUILTIN_UDIV_V2DI:
15584 arg0 = gimple_call_arg (stmt, 0);
15585 arg1 = gimple_call_arg (stmt, 1);
15586 lhs = gimple_call_lhs (stmt);
15587 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15588 gimple_set_location (g, gimple_location (stmt));
15589 gsi_replace (gsi, g, true);
15591 /* Flavors of vec_div (Float). */
15592 case VSX_BUILTIN_XVDIVSP:
15593 case VSX_BUILTIN_XVDIVDP:
15594 arg0 = gimple_call_arg (stmt, 0);
15595 arg1 = gimple_call_arg (stmt, 1);
15596 lhs = gimple_call_lhs (stmt);
15597 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15598 gimple_set_location (g, gimple_location (stmt));
15599 gsi_replace (gsi, g, true);
15601 /* Flavors of vec_and. */
15602 case ALTIVEC_BUILTIN_VAND:
15603 arg0 = gimple_call_arg (stmt, 0);
15604 arg1 = gimple_call_arg (stmt, 1);
15605 lhs = gimple_call_lhs (stmt);
15606 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15607 gimple_set_location (g, gimple_location (stmt));
15608 gsi_replace (gsi, g, true);
15610 /* Flavors of vec_andc. */
15611 case ALTIVEC_BUILTIN_VANDC:
15612 arg0 = gimple_call_arg (stmt, 0);
15613 arg1 = gimple_call_arg (stmt, 1);
15614 lhs = gimple_call_lhs (stmt);
15615 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15616 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15617 gimple_set_location (g, gimple_location (stmt));
15618 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15619 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15620 gimple_set_location (g, gimple_location (stmt));
15621 gsi_replace (gsi, g, true);
15623 /* Flavors of vec_nand. */
15624 case P8V_BUILTIN_VEC_NAND:
15625 case P8V_BUILTIN_NAND_V16QI:
15626 case P8V_BUILTIN_NAND_V8HI:
15627 case P8V_BUILTIN_NAND_V4SI:
15628 case P8V_BUILTIN_NAND_V4SF:
15629 case P8V_BUILTIN_NAND_V2DF:
15630 case P8V_BUILTIN_NAND_V2DI:
15631 arg0 = gimple_call_arg (stmt, 0);
15632 arg1 = gimple_call_arg (stmt, 1);
15633 lhs = gimple_call_lhs (stmt);
15634 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15635 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15636 gimple_set_location (g, gimple_location (stmt));
15637 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15638 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15639 gimple_set_location (g, gimple_location (stmt));
15640 gsi_replace (gsi, g, true);
15642 /* Flavors of vec_or. */
15643 case ALTIVEC_BUILTIN_VOR:
15644 arg0 = gimple_call_arg (stmt, 0);
15645 arg1 = gimple_call_arg (stmt, 1);
15646 lhs = gimple_call_lhs (stmt);
15647 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15648 gimple_set_location (g, gimple_location (stmt));
15649 gsi_replace (gsi, g, true);
15651 /* flavors of vec_orc. */
15652 case P8V_BUILTIN_ORC_V16QI:
15653 case P8V_BUILTIN_ORC_V8HI:
15654 case P8V_BUILTIN_ORC_V4SI:
15655 case P8V_BUILTIN_ORC_V4SF:
15656 case P8V_BUILTIN_ORC_V2DF:
15657 case P8V_BUILTIN_ORC_V2DI:
15658 arg0 = gimple_call_arg (stmt, 0);
15659 arg1 = gimple_call_arg (stmt, 1);
15660 lhs = gimple_call_lhs (stmt);
15661 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15662 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15663 gimple_set_location (g, gimple_location (stmt));
15664 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15665 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15666 gimple_set_location (g, gimple_location (stmt));
15667 gsi_replace (gsi, g, true);
15669 /* Flavors of vec_xor. */
15670 case ALTIVEC_BUILTIN_VXOR:
15671 arg0 = gimple_call_arg (stmt, 0);
15672 arg1 = gimple_call_arg (stmt, 1);
15673 lhs = gimple_call_lhs (stmt);
15674 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15675 gimple_set_location (g, gimple_location (stmt));
15676 gsi_replace (gsi, g, true);
15678 /* Flavors of vec_nor. */
15679 case ALTIVEC_BUILTIN_VNOR:
15680 arg0 = gimple_call_arg (stmt, 0);
15681 arg1 = gimple_call_arg (stmt, 1);
15682 lhs = gimple_call_lhs (stmt);
15683 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15684 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15685 gimple_set_location (g, gimple_location (stmt));
15686 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15687 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15688 gimple_set_location (g, gimple_location (stmt));
15689 gsi_replace (gsi, g, true);
15691 /* flavors of vec_abs. */
15692 case ALTIVEC_BUILTIN_ABS_V16QI:
15693 case ALTIVEC_BUILTIN_ABS_V8HI:
15694 case ALTIVEC_BUILTIN_ABS_V4SI:
15695 case ALTIVEC_BUILTIN_ABS_V4SF:
15696 case P8V_BUILTIN_ABS_V2DI:
15697 case VSX_BUILTIN_XVABSDP:
15698 arg0 = gimple_call_arg (stmt, 0);
15699 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15700 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15702 lhs = gimple_call_lhs (stmt);
15703 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15704 gimple_set_location (g, gimple_location (stmt));
15705 gsi_replace (gsi, g, true);
15707 /* flavors of vec_min. */
15708 case VSX_BUILTIN_XVMINDP:
15709 case P8V_BUILTIN_VMINSD:
15710 case P8V_BUILTIN_VMINUD:
15711 case ALTIVEC_BUILTIN_VMINSB:
15712 case ALTIVEC_BUILTIN_VMINSH:
15713 case ALTIVEC_BUILTIN_VMINSW:
15714 case ALTIVEC_BUILTIN_VMINUB:
15715 case ALTIVEC_BUILTIN_VMINUH:
15716 case ALTIVEC_BUILTIN_VMINUW:
15717 case ALTIVEC_BUILTIN_VMINFP:
15718 arg0 = gimple_call_arg (stmt, 0);
15719 arg1 = gimple_call_arg (stmt, 1);
15720 lhs = gimple_call_lhs (stmt);
15721 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15722 gimple_set_location (g, gimple_location (stmt));
15723 gsi_replace (gsi, g, true);
15725 /* flavors of vec_max. */
15726 case VSX_BUILTIN_XVMAXDP:
15727 case P8V_BUILTIN_VMAXSD:
15728 case P8V_BUILTIN_VMAXUD:
15729 case ALTIVEC_BUILTIN_VMAXSB:
15730 case ALTIVEC_BUILTIN_VMAXSH:
15731 case ALTIVEC_BUILTIN_VMAXSW:
15732 case ALTIVEC_BUILTIN_VMAXUB:
15733 case ALTIVEC_BUILTIN_VMAXUH:
15734 case ALTIVEC_BUILTIN_VMAXUW:
15735 case ALTIVEC_BUILTIN_VMAXFP:
15736 arg0 = gimple_call_arg (stmt, 0);
15737 arg1 = gimple_call_arg (stmt, 1);
15738 lhs = gimple_call_lhs (stmt);
15739 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15740 gimple_set_location (g, gimple_location (stmt));
15741 gsi_replace (gsi, g, true);
15743 /* Flavors of vec_eqv. */
15744 case P8V_BUILTIN_EQV_V16QI:
15745 case P8V_BUILTIN_EQV_V8HI:
15746 case P8V_BUILTIN_EQV_V4SI:
15747 case P8V_BUILTIN_EQV_V4SF:
15748 case P8V_BUILTIN_EQV_V2DF:
15749 case P8V_BUILTIN_EQV_V2DI:
15750 arg0 = gimple_call_arg (stmt, 0);
15751 arg1 = gimple_call_arg (stmt, 1);
15752 lhs = gimple_call_lhs (stmt);
15753 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15754 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15755 gimple_set_location (g, gimple_location (stmt));
15756 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15757 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15758 gimple_set_location (g, gimple_location (stmt));
15759 gsi_replace (gsi, g, true);
15761 /* Flavors of vec_rotate_left. */
15762 case ALTIVEC_BUILTIN_VRLB:
15763 case ALTIVEC_BUILTIN_VRLH:
15764 case ALTIVEC_BUILTIN_VRLW:
15765 case P8V_BUILTIN_VRLD:
15766 arg0 = gimple_call_arg (stmt, 0);
15767 arg1 = gimple_call_arg (stmt, 1);
15768 lhs = gimple_call_lhs (stmt);
15769 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15770 gimple_set_location (g, gimple_location (stmt));
15771 gsi_replace (gsi, g, true);
15773 /* Flavors of vector shift right algebraic.
15774 vec_sra{b,h,w} -> vsra{b,h,w}. */
15775 case ALTIVEC_BUILTIN_VSRAB:
15776 case ALTIVEC_BUILTIN_VSRAH:
15777 case ALTIVEC_BUILTIN_VSRAW:
15778 case P8V_BUILTIN_VSRAD:
15779 arg0 = gimple_call_arg (stmt, 0);
15780 arg1 = gimple_call_arg (stmt, 1);
15781 lhs = gimple_call_lhs (stmt);
15782 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
15783 gimple_set_location (g, gimple_location (stmt));
15784 gsi_replace (gsi, g, true);
15786 /* Flavors of vector shift left.
15787 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15788 case ALTIVEC_BUILTIN_VSLB:
15789 case ALTIVEC_BUILTIN_VSLH:
15790 case ALTIVEC_BUILTIN_VSLW:
15791 case P8V_BUILTIN_VSLD:
15792 arg0 = gimple_call_arg (stmt, 0);
15793 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15794 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15796 arg1 = gimple_call_arg (stmt, 1);
15797 lhs = gimple_call_lhs (stmt);
15798 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
15799 gimple_set_location (g, gimple_location (stmt));
15800 gsi_replace (gsi, g, true);
15802 /* Flavors of vector shift right. */
15803 case ALTIVEC_BUILTIN_VSRB:
15804 case ALTIVEC_BUILTIN_VSRH:
15805 case ALTIVEC_BUILTIN_VSRW:
15806 case P8V_BUILTIN_VSRD:
15808 arg0 = gimple_call_arg (stmt, 0);
15809 arg1 = gimple_call_arg (stmt, 1);
15810 lhs = gimple_call_lhs (stmt);
15811 gimple_seq stmts = NULL;
15812 /* Convert arg0 to unsigned. */
15814 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15815 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15817 = gimple_build (&stmts, RSHIFT_EXPR,
15818 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
15819 /* Convert result back to the lhs type. */
15820 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15821 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15822 update_call_from_tree (gsi, res);
15825 /* Vector loads. */
15826 case ALTIVEC_BUILTIN_LVX_V16QI:
15827 case ALTIVEC_BUILTIN_LVX_V8HI:
15828 case ALTIVEC_BUILTIN_LVX_V4SI:
15829 case ALTIVEC_BUILTIN_LVX_V4SF:
15830 case ALTIVEC_BUILTIN_LVX_V2DI:
15831 case ALTIVEC_BUILTIN_LVX_V2DF:
15832 case ALTIVEC_BUILTIN_LVX_V1TI:
15834 arg0 = gimple_call_arg (stmt, 0); // offset
15835 arg1 = gimple_call_arg (stmt, 1); // address
15836 lhs = gimple_call_lhs (stmt);
15837 location_t loc = gimple_location (stmt);
15838 /* Since arg1 may be cast to a different type, just use ptr_type_node
15839 here instead of trying to enforce TBAA on pointer types. */
15840 tree arg1_type = ptr_type_node;
15841 tree lhs_type = TREE_TYPE (lhs);
15842 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15843 the tree using the value from arg0. The resulting type will match
15844 the type of arg1. */
15845 gimple_seq stmts = NULL;
15846 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15847 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15848 arg1_type, arg1, temp_offset);
15849 /* Mask off any lower bits from the address. */
15850 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15851 arg1_type, temp_addr,
15852 build_int_cst (arg1_type, -16));
15853 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15854 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15855 take an offset, but since we've already incorporated the offset
15856 above, here we just pass in a zero. */
15858 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15859 build_int_cst (arg1_type, 0)));
15860 gimple_set_location (g, loc);
15861 gsi_replace (gsi, g, true);
15864 /* Vector stores. */
15865 case ALTIVEC_BUILTIN_STVX_V16QI:
15866 case ALTIVEC_BUILTIN_STVX_V8HI:
15867 case ALTIVEC_BUILTIN_STVX_V4SI:
15868 case ALTIVEC_BUILTIN_STVX_V4SF:
15869 case ALTIVEC_BUILTIN_STVX_V2DI:
15870 case ALTIVEC_BUILTIN_STVX_V2DF:
15872 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15873 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15874 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15875 location_t loc = gimple_location (stmt);
15876 tree arg0_type = TREE_TYPE (arg0);
15877 /* Use ptr_type_node (no TBAA) for the arg2_type.
15878 FIXME: (Richard) "A proper fix would be to transition this type as
15879 seen from the frontend to GIMPLE, for example in a similar way we
15880 do for MEM_REFs by piggy-backing that on an extra argument, a
15881 constant zero pointer of the alias pointer type to use (which would
15882 also serve as a type indicator of the store itself). I'd use a
15883 target specific internal function for this (not sure if we can have
15884 those target specific, but I guess if it's folded away then that's
15885 fine) and get away with the overload set." */
15886 tree arg2_type = ptr_type_node;
15887 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15888 the tree using the value from arg0. The resulting type will match
15889 the type of arg2. */
15890 gimple_seq stmts = NULL;
15891 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15892 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15893 arg2_type, arg2, temp_offset);
15894 /* Mask off any lower bits from the address. */
15895 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15896 arg2_type, temp_addr,
15897 build_int_cst (arg2_type, -16));
15898 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15899 /* The desired gimple result should be similar to:
15900 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15902 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15903 build_int_cst (arg2_type, 0)), arg0);
15904 gimple_set_location (g, loc);
15905 gsi_replace (gsi, g, true);
15909 /* Vector Fused multiply-add (fma). */
15910 case ALTIVEC_BUILTIN_VMADDFP:
15911 case VSX_BUILTIN_XVMADDDP:
15912 case ALTIVEC_BUILTIN_VMLADDUHM:
15914 arg0 = gimple_call_arg (stmt, 0);
15915 arg1 = gimple_call_arg (stmt, 1);
15916 tree arg2 = gimple_call_arg (stmt, 2);
15917 lhs = gimple_call_lhs (stmt);
15918 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15919 gimple_call_set_lhs (g, lhs);
15920 gimple_call_set_nothrow (g, true);
15921 gimple_set_location (g, gimple_location (stmt));
15922 gsi_replace (gsi, g, true);
15926 /* Vector compares; EQ, NE, GE, GT, LE. */
15927 case ALTIVEC_BUILTIN_VCMPEQUB:
15928 case ALTIVEC_BUILTIN_VCMPEQUH:
15929 case ALTIVEC_BUILTIN_VCMPEQUW:
15930 case P8V_BUILTIN_VCMPEQUD:
15931 fold_compare_helper (gsi, EQ_EXPR, stmt);
15934 case P9V_BUILTIN_CMPNEB:
15935 case P9V_BUILTIN_CMPNEH:
15936 case P9V_BUILTIN_CMPNEW:
15937 fold_compare_helper (gsi, NE_EXPR, stmt);
15940 case VSX_BUILTIN_CMPGE_16QI:
15941 case VSX_BUILTIN_CMPGE_U16QI:
15942 case VSX_BUILTIN_CMPGE_8HI:
15943 case VSX_BUILTIN_CMPGE_U8HI:
15944 case VSX_BUILTIN_CMPGE_4SI:
15945 case VSX_BUILTIN_CMPGE_U4SI:
15946 case VSX_BUILTIN_CMPGE_2DI:
15947 case VSX_BUILTIN_CMPGE_U2DI:
15948 fold_compare_helper (gsi, GE_EXPR, stmt);
15951 case ALTIVEC_BUILTIN_VCMPGTSB:
15952 case ALTIVEC_BUILTIN_VCMPGTUB:
15953 case ALTIVEC_BUILTIN_VCMPGTSH:
15954 case ALTIVEC_BUILTIN_VCMPGTUH:
15955 case ALTIVEC_BUILTIN_VCMPGTSW:
15956 case ALTIVEC_BUILTIN_VCMPGTUW:
15957 case P8V_BUILTIN_VCMPGTUD:
15958 case P8V_BUILTIN_VCMPGTSD:
15959 fold_compare_helper (gsi, GT_EXPR, stmt);
15962 case VSX_BUILTIN_CMPLE_16QI:
15963 case VSX_BUILTIN_CMPLE_U16QI:
15964 case VSX_BUILTIN_CMPLE_8HI:
15965 case VSX_BUILTIN_CMPLE_U8HI:
15966 case VSX_BUILTIN_CMPLE_4SI:
15967 case VSX_BUILTIN_CMPLE_U4SI:
15968 case VSX_BUILTIN_CMPLE_2DI:
15969 case VSX_BUILTIN_CMPLE_U2DI:
15970 fold_compare_helper (gsi, LE_EXPR, stmt);
15973 /* flavors of vec_splat_[us]{8,16,32}. */
15974 case ALTIVEC_BUILTIN_VSPLTISB:
15975 case ALTIVEC_BUILTIN_VSPLTISH:
15976 case ALTIVEC_BUILTIN_VSPLTISW:
15980 if (fn_code == ALTIVEC_BUILTIN_VSPLTISB)
15982 else if (fn_code == ALTIVEC_BUILTIN_VSPLTISH)
15987 arg0 = gimple_call_arg (stmt, 0);
15988 lhs = gimple_call_lhs (stmt);
15990 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15991 5-bit signed constant in range -16 to +15. */
15992 if (TREE_CODE (arg0) != INTEGER_CST
15993 || !IN_RANGE (sext_hwi(TREE_INT_CST_LOW (arg0), size),
15996 gimple_seq stmts = NULL;
15997 location_t loc = gimple_location (stmt);
15998 tree splat_value = gimple_convert (&stmts, loc,
15999 TREE_TYPE (TREE_TYPE (lhs)), arg0);
16000 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16001 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
16002 g = gimple_build_assign (lhs, splat_tree);
16003 gimple_set_location (g, gimple_location (stmt));
16004 gsi_replace (gsi, g, true);
16008 /* vec_mergel (integrals). */
16009 case ALTIVEC_BUILTIN_VMRGLH:
16010 case ALTIVEC_BUILTIN_VMRGLW:
16011 case VSX_BUILTIN_XXMRGLW_4SI:
16012 case ALTIVEC_BUILTIN_VMRGLB:
16013 case VSX_BUILTIN_VEC_MERGEL_V2DI:
16014 fold_mergehl_helper (gsi, stmt, 1);
16016 /* vec_mergeh (integrals). */
16017 case ALTIVEC_BUILTIN_VMRGHH:
16018 case ALTIVEC_BUILTIN_VMRGHW:
16019 case VSX_BUILTIN_XXMRGHW_4SI:
16020 case ALTIVEC_BUILTIN_VMRGHB:
16021 case VSX_BUILTIN_VEC_MERGEH_V2DI:
16022 fold_mergehl_helper (gsi, stmt, 0);
16025 if (TARGET_DEBUG_BUILTIN)
16026 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16027 fn_code, fn_name1, fn_name2);
16034 /* Expand an expression EXP that calls a built-in function,
16035 with result going to TARGET if that's convenient
16036 (and in mode MODE if that's convenient).
16037 SUBTARGET may be used as the target for computing one of EXP's operands.
16038 IGNORE is nonzero if the value is to be ignored. */
16041 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16042 machine_mode mode ATTRIBUTE_UNUSED,
16043 int ignore ATTRIBUTE_UNUSED)
16045 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16046 enum rs6000_builtins fcode
16047 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16048 size_t uns_fcode = (size_t)fcode;
16049 const struct builtin_description *d;
16053 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16054 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16055 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16057 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16058 floating point type, depending on whether long double is the IBM extended
16059 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16060 we only define one variant of the built-in function, and switch the code
16061 when defining it, rather than defining two built-ins and using the
16062 overload table in rs6000-c.c to switch between the two. If we don't have
16063 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16064 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16065 #ifdef HAVE_AS_POWER9
16066 if (FLOAT128_IEEE_P (TFmode))
16072 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16073 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16074 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16075 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16076 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16077 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16078 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16079 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16080 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16081 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16082 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16083 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16084 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16088 if (TARGET_DEBUG_BUILTIN)
16090 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16091 const char *name2 = (icode != CODE_FOR_nothing)
16092 ? get_insn_name ((int) icode)
16096 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16098 default: name3 = "unknown"; break;
16099 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16100 case RS6000_BTC_UNARY: name3 = "unary"; break;
16101 case RS6000_BTC_BINARY: name3 = "binary"; break;
16102 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16103 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16104 case RS6000_BTC_ABS: name3 = "abs"; break;
16105 case RS6000_BTC_DST: name3 = "dst"; break;
16110 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16111 (name1) ? name1 : "---", fcode,
16112 (name2) ? name2 : "---", (int) icode,
16114 func_valid_p ? "" : ", not valid");
16119 rs6000_invalid_builtin (fcode);
16121 /* Given it is invalid, just generate a normal call. */
16122 return expand_call (exp, target, ignore);
16127 case RS6000_BUILTIN_RECIP:
16128 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16130 case RS6000_BUILTIN_RECIPF:
16131 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16133 case RS6000_BUILTIN_RSQRTF:
16134 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16136 case RS6000_BUILTIN_RSQRT:
16137 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16139 case POWER7_BUILTIN_BPERMD:
16140 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16141 ? CODE_FOR_bpermd_di
16142 : CODE_FOR_bpermd_si), exp, target);
16144 case RS6000_BUILTIN_GET_TB:
16145 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16148 case RS6000_BUILTIN_MFTB:
16149 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16150 ? CODE_FOR_rs6000_mftb_di
16151 : CODE_FOR_rs6000_mftb_si),
16154 case RS6000_BUILTIN_MFFS:
16155 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16157 case RS6000_BUILTIN_MTFSF:
16158 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16160 case RS6000_BUILTIN_CPU_INIT:
16161 case RS6000_BUILTIN_CPU_IS:
16162 case RS6000_BUILTIN_CPU_SUPPORTS:
16163 return cpu_expand_builtin (fcode, exp, target);
16165 case MISC_BUILTIN_SPEC_BARRIER:
16167 emit_insn (gen_rs6000_speculation_barrier ());
16171 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16172 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16174 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16175 : (int) CODE_FOR_altivec_lvsl_direct);
16176 machine_mode tmode = insn_data[icode2].operand[0].mode;
16177 machine_mode mode = insn_data[icode2].operand[1].mode;
16181 gcc_assert (TARGET_ALTIVEC);
16183 arg = CALL_EXPR_ARG (exp, 0);
16184 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16185 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16186 addr = memory_address (mode, op);
16187 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16191 /* For the load case need to negate the address. */
16192 op = gen_reg_rtx (GET_MODE (addr));
16193 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16195 op = gen_rtx_MEM (mode, op);
16198 || GET_MODE (target) != tmode
16199 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16200 target = gen_reg_rtx (tmode);
16202 pat = GEN_FCN (icode2) (target, op);
16210 case ALTIVEC_BUILTIN_VCFUX:
16211 case ALTIVEC_BUILTIN_VCFSX:
16212 case ALTIVEC_BUILTIN_VCTUXS:
16213 case ALTIVEC_BUILTIN_VCTSXS:
16214 /* FIXME: There's got to be a nicer way to handle this case than
16215 constructing a new CALL_EXPR. */
16216 if (call_expr_nargs (exp) == 1)
16218 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16219 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16223 /* For the pack and unpack int128 routines, fix up the builtin so it
16224 uses the correct IBM128 type. */
16225 case MISC_BUILTIN_PACK_IF:
16226 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16228 icode = CODE_FOR_packtf;
16229 fcode = MISC_BUILTIN_PACK_TF;
16230 uns_fcode = (size_t)fcode;
16234 case MISC_BUILTIN_UNPACK_IF:
16235 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16237 icode = CODE_FOR_unpacktf;
16238 fcode = MISC_BUILTIN_UNPACK_TF;
16239 uns_fcode = (size_t)fcode;
16247 if (TARGET_ALTIVEC)
16249 ret = altivec_expand_builtin (exp, target, &success);
16256 ret = htm_expand_builtin (exp, target, &success);
16262 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16263 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16264 gcc_assert (attr == RS6000_BTC_UNARY
16265 || attr == RS6000_BTC_BINARY
16266 || attr == RS6000_BTC_TERNARY
16267 || attr == RS6000_BTC_SPECIAL);
16269 /* Handle simple unary operations. */
16271 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16272 if (d->code == fcode)
16273 return rs6000_expand_unop_builtin (icode, exp, target);
16275 /* Handle simple binary operations. */
16277 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16278 if (d->code == fcode)
16279 return rs6000_expand_binop_builtin (icode, exp, target);
16281 /* Handle simple ternary operations. */
16283 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16284 if (d->code == fcode)
16285 return rs6000_expand_ternop_builtin (icode, exp, target);
16287 /* Handle simple no-argument operations. */
16289 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16290 if (d->code == fcode)
16291 return rs6000_expand_zeroop_builtin (icode, target);
16293 gcc_unreachable ();
16296 /* Create a builtin vector type with a name. Taking care not to give
16297 the canonical type a name. */
16300 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16302 tree result = build_vector_type (elt_type, num_elts);
16304 /* Copy so we don't give the canonical type a name. */
16305 result = build_variant_type_copy (result);
16307 add_builtin_type (name, result);
16313 rs6000_init_builtins (void)
16319 if (TARGET_DEBUG_BUILTIN)
16320 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16321 (TARGET_ALTIVEC) ? ", altivec" : "",
16322 (TARGET_VSX) ? ", vsx" : "");
16324 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16325 : "__vector long long",
16326 intDI_type_node, 2);
16327 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16328 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16329 intSI_type_node, 4);
16330 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16331 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16332 intHI_type_node, 8);
16333 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16334 intQI_type_node, 16);
16336 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16337 unsigned_intQI_type_node, 16);
16338 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16339 unsigned_intHI_type_node, 8);
16340 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16341 unsigned_intSI_type_node, 4);
16342 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16343 ? "__vector unsigned long"
16344 : "__vector unsigned long long",
16345 unsigned_intDI_type_node, 2);
16347 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16349 const_str_type_node
16350 = build_pointer_type (build_qualified_type (char_type_node,
16353 /* We use V1TI mode as a special container to hold __int128_t items that
16354 must live in VSX registers. */
16355 if (intTI_type_node)
16357 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16358 intTI_type_node, 1);
16359 unsigned_V1TI_type_node
16360 = rs6000_vector_type ("__vector unsigned __int128",
16361 unsigned_intTI_type_node, 1);
16364 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16365 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16366 'vector unsigned short'. */
16368 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16369 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16370 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16371 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16372 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16374 long_integer_type_internal_node = long_integer_type_node;
16375 long_unsigned_type_internal_node = long_unsigned_type_node;
16376 long_long_integer_type_internal_node = long_long_integer_type_node;
16377 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16378 intQI_type_internal_node = intQI_type_node;
16379 uintQI_type_internal_node = unsigned_intQI_type_node;
16380 intHI_type_internal_node = intHI_type_node;
16381 uintHI_type_internal_node = unsigned_intHI_type_node;
16382 intSI_type_internal_node = intSI_type_node;
16383 uintSI_type_internal_node = unsigned_intSI_type_node;
16384 intDI_type_internal_node = intDI_type_node;
16385 uintDI_type_internal_node = unsigned_intDI_type_node;
16386 intTI_type_internal_node = intTI_type_node;
16387 uintTI_type_internal_node = unsigned_intTI_type_node;
16388 float_type_internal_node = float_type_node;
16389 double_type_internal_node = double_type_node;
16390 long_double_type_internal_node = long_double_type_node;
16391 dfloat64_type_internal_node = dfloat64_type_node;
16392 dfloat128_type_internal_node = dfloat128_type_node;
16393 void_type_internal_node = void_type_node;
16395 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16396 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16397 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16398 format that uses a pair of doubles, depending on the switches and
16401 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16402 floating point, we need make sure the type is non-zero or else self-test
16403 fails during bootstrap.
16405 Always create __ibm128 as a separate type, even if the current long double
16406 format is IBM extended double.
16408 For IEEE 128-bit floating point, always create the type __ieee128. If the
16409 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16411 if (TARGET_FLOAT128_TYPE)
16413 if (TARGET_IEEEQUAD || !TARGET_LONG_DOUBLE_128)
16415 ibm128_float_type_node = make_node (REAL_TYPE);
16416 TYPE_PRECISION (ibm128_float_type_node) = 128;
16417 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16418 layout_type (ibm128_float_type_node);
16421 ibm128_float_type_node = long_double_type_node;
16423 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16426 ieee128_float_type_node
16427 = TARGET_IEEEQUAD ? long_double_type_node : float128_type_node;
16428 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16433 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16435 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16437 builtin_mode_to_type[QImode][0] = integer_type_node;
16438 builtin_mode_to_type[HImode][0] = integer_type_node;
16439 builtin_mode_to_type[SImode][0] = intSI_type_node;
16440 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16441 builtin_mode_to_type[DImode][0] = intDI_type_node;
16442 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16443 builtin_mode_to_type[TImode][0] = intTI_type_node;
16444 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16445 builtin_mode_to_type[SFmode][0] = float_type_node;
16446 builtin_mode_to_type[DFmode][0] = double_type_node;
16447 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16448 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16449 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16450 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16451 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16452 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16453 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16454 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16455 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16456 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16457 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16458 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16459 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16460 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16461 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16462 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16463 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16465 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16466 TYPE_NAME (bool_char_type_node) = tdecl;
16468 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16469 TYPE_NAME (bool_short_type_node) = tdecl;
16471 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16472 TYPE_NAME (bool_int_type_node) = tdecl;
16474 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16475 TYPE_NAME (pixel_type_node) = tdecl;
16477 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16478 bool_char_type_node, 16);
16479 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16480 bool_short_type_node, 8);
16481 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16482 bool_int_type_node, 4);
16483 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16484 ? "__vector __bool long"
16485 : "__vector __bool long long",
16486 bool_long_long_type_node, 2);
16487 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16488 pixel_type_node, 8);
16490 /* Create Altivec and VSX builtins on machines with at least the
16491 general purpose extensions (970 and newer) to allow the use of
16492 the target attribute. */
16493 if (TARGET_EXTRA_BUILTINS)
16494 altivec_init_builtins ();
16496 htm_init_builtins ();
16498 if (TARGET_EXTRA_BUILTINS)
16499 rs6000_common_init_builtins ();
16501 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16502 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16503 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16505 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16506 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16507 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16509 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16510 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16511 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16513 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16514 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16515 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16517 mode = (TARGET_64BIT) ? DImode : SImode;
16518 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16519 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16520 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16522 ftype = build_function_type_list (unsigned_intDI_type_node,
16524 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16527 ftype = build_function_type_list (unsigned_intDI_type_node,
16530 ftype = build_function_type_list (unsigned_intSI_type_node,
16532 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16534 ftype = build_function_type_list (double_type_node, NULL_TREE);
16535 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16537 ftype = build_function_type_list (void_type_node,
16538 intSI_type_node, double_type_node,
16540 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16542 ftype = build_function_type_list (void_type_node, NULL_TREE);
16543 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16544 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16545 MISC_BUILTIN_SPEC_BARRIER);
16547 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16549 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16550 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16552 /* AIX libm provides clog as __clog. */
16553 if (TARGET_XCOFF &&
16554 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16555 set_user_assembler_name (tdecl, "__clog");
16557 #ifdef SUBTARGET_INIT_BUILTINS
16558 SUBTARGET_INIT_BUILTINS;
16562 /* Returns the rs6000 builtin decl for CODE. */
16565 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16567 HOST_WIDE_INT fnmask;
16569 if (code >= RS6000_BUILTIN_COUNT)
16570 return error_mark_node;
16572 fnmask = rs6000_builtin_info[code].mask;
16573 if ((fnmask & rs6000_builtin_mask) != fnmask)
16575 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16576 return error_mark_node;
16579 return rs6000_builtin_decls[code];
16583 altivec_init_builtins (void)
16585 const struct builtin_description *d;
16589 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16591 tree pvoid_type_node = build_pointer_type (void_type_node);
16593 tree pcvoid_type_node
16594 = build_pointer_type (build_qualified_type (void_type_node,
16597 tree int_ftype_opaque
16598 = build_function_type_list (integer_type_node,
16599 opaque_V4SI_type_node, NULL_TREE);
16600 tree opaque_ftype_opaque
16601 = build_function_type_list (integer_type_node, NULL_TREE);
16602 tree opaque_ftype_opaque_int
16603 = build_function_type_list (opaque_V4SI_type_node,
16604 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16605 tree opaque_ftype_opaque_opaque_int
16606 = build_function_type_list (opaque_V4SI_type_node,
16607 opaque_V4SI_type_node, opaque_V4SI_type_node,
16608 integer_type_node, NULL_TREE);
16609 tree opaque_ftype_opaque_opaque_opaque
16610 = build_function_type_list (opaque_V4SI_type_node,
16611 opaque_V4SI_type_node, opaque_V4SI_type_node,
16612 opaque_V4SI_type_node, NULL_TREE);
16613 tree opaque_ftype_opaque_opaque
16614 = build_function_type_list (opaque_V4SI_type_node,
16615 opaque_V4SI_type_node, opaque_V4SI_type_node,
16617 tree int_ftype_int_opaque_opaque
16618 = build_function_type_list (integer_type_node,
16619 integer_type_node, opaque_V4SI_type_node,
16620 opaque_V4SI_type_node, NULL_TREE);
16621 tree int_ftype_int_v4si_v4si
16622 = build_function_type_list (integer_type_node,
16623 integer_type_node, V4SI_type_node,
16624 V4SI_type_node, NULL_TREE);
16625 tree int_ftype_int_v2di_v2di
16626 = build_function_type_list (integer_type_node,
16627 integer_type_node, V2DI_type_node,
16628 V2DI_type_node, NULL_TREE);
16629 tree void_ftype_v4si
16630 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16631 tree v8hi_ftype_void
16632 = build_function_type_list (V8HI_type_node, NULL_TREE);
16633 tree void_ftype_void
16634 = build_function_type_list (void_type_node, NULL_TREE);
16635 tree void_ftype_int
16636 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16638 tree opaque_ftype_long_pcvoid
16639 = build_function_type_list (opaque_V4SI_type_node,
16640 long_integer_type_node, pcvoid_type_node,
16642 tree v16qi_ftype_long_pcvoid
16643 = build_function_type_list (V16QI_type_node,
16644 long_integer_type_node, pcvoid_type_node,
16646 tree v8hi_ftype_long_pcvoid
16647 = build_function_type_list (V8HI_type_node,
16648 long_integer_type_node, pcvoid_type_node,
16650 tree v4si_ftype_long_pcvoid
16651 = build_function_type_list (V4SI_type_node,
16652 long_integer_type_node, pcvoid_type_node,
16654 tree v4sf_ftype_long_pcvoid
16655 = build_function_type_list (V4SF_type_node,
16656 long_integer_type_node, pcvoid_type_node,
16658 tree v2df_ftype_long_pcvoid
16659 = build_function_type_list (V2DF_type_node,
16660 long_integer_type_node, pcvoid_type_node,
16662 tree v2di_ftype_long_pcvoid
16663 = build_function_type_list (V2DI_type_node,
16664 long_integer_type_node, pcvoid_type_node,
16666 tree v1ti_ftype_long_pcvoid
16667 = build_function_type_list (V1TI_type_node,
16668 long_integer_type_node, pcvoid_type_node,
16671 tree void_ftype_opaque_long_pvoid
16672 = build_function_type_list (void_type_node,
16673 opaque_V4SI_type_node, long_integer_type_node,
16674 pvoid_type_node, NULL_TREE);
16675 tree void_ftype_v4si_long_pvoid
16676 = build_function_type_list (void_type_node,
16677 V4SI_type_node, long_integer_type_node,
16678 pvoid_type_node, NULL_TREE);
16679 tree void_ftype_v16qi_long_pvoid
16680 = build_function_type_list (void_type_node,
16681 V16QI_type_node, long_integer_type_node,
16682 pvoid_type_node, NULL_TREE);
16684 tree void_ftype_v16qi_pvoid_long
16685 = build_function_type_list (void_type_node,
16686 V16QI_type_node, pvoid_type_node,
16687 long_integer_type_node, NULL_TREE);
16689 tree void_ftype_v8hi_long_pvoid
16690 = build_function_type_list (void_type_node,
16691 V8HI_type_node, long_integer_type_node,
16692 pvoid_type_node, NULL_TREE);
16693 tree void_ftype_v4sf_long_pvoid
16694 = build_function_type_list (void_type_node,
16695 V4SF_type_node, long_integer_type_node,
16696 pvoid_type_node, NULL_TREE);
16697 tree void_ftype_v2df_long_pvoid
16698 = build_function_type_list (void_type_node,
16699 V2DF_type_node, long_integer_type_node,
16700 pvoid_type_node, NULL_TREE);
16701 tree void_ftype_v1ti_long_pvoid
16702 = build_function_type_list (void_type_node,
16703 V1TI_type_node, long_integer_type_node,
16704 pvoid_type_node, NULL_TREE);
16705 tree void_ftype_v2di_long_pvoid
16706 = build_function_type_list (void_type_node,
16707 V2DI_type_node, long_integer_type_node,
16708 pvoid_type_node, NULL_TREE);
16709 tree int_ftype_int_v8hi_v8hi
16710 = build_function_type_list (integer_type_node,
16711 integer_type_node, V8HI_type_node,
16712 V8HI_type_node, NULL_TREE);
16713 tree int_ftype_int_v16qi_v16qi
16714 = build_function_type_list (integer_type_node,
16715 integer_type_node, V16QI_type_node,
16716 V16QI_type_node, NULL_TREE);
16717 tree int_ftype_int_v4sf_v4sf
16718 = build_function_type_list (integer_type_node,
16719 integer_type_node, V4SF_type_node,
16720 V4SF_type_node, NULL_TREE);
16721 tree int_ftype_int_v2df_v2df
16722 = build_function_type_list (integer_type_node,
16723 integer_type_node, V2DF_type_node,
16724 V2DF_type_node, NULL_TREE);
16725 tree v2di_ftype_v2di
16726 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16727 tree v4si_ftype_v4si
16728 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16729 tree v8hi_ftype_v8hi
16730 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16731 tree v16qi_ftype_v16qi
16732 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16733 tree v4sf_ftype_v4sf
16734 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16735 tree v2df_ftype_v2df
16736 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16737 tree void_ftype_pcvoid_int_int
16738 = build_function_type_list (void_type_node,
16739 pcvoid_type_node, integer_type_node,
16740 integer_type_node, NULL_TREE);
16742 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16743 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16744 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16745 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16746 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16747 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16748 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16749 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16750 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16751 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16752 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16753 ALTIVEC_BUILTIN_LVXL_V2DF);
16754 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16755 ALTIVEC_BUILTIN_LVXL_V2DI);
16756 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16757 ALTIVEC_BUILTIN_LVXL_V4SF);
16758 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16759 ALTIVEC_BUILTIN_LVXL_V4SI);
16760 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16761 ALTIVEC_BUILTIN_LVXL_V8HI);
16762 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16763 ALTIVEC_BUILTIN_LVXL_V16QI);
16764 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16765 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16766 ALTIVEC_BUILTIN_LVX_V1TI);
16767 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16768 ALTIVEC_BUILTIN_LVX_V2DF);
16769 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16770 ALTIVEC_BUILTIN_LVX_V2DI);
16771 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16772 ALTIVEC_BUILTIN_LVX_V4SF);
16773 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16774 ALTIVEC_BUILTIN_LVX_V4SI);
16775 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16776 ALTIVEC_BUILTIN_LVX_V8HI);
16777 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16778 ALTIVEC_BUILTIN_LVX_V16QI);
16779 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16780 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16781 ALTIVEC_BUILTIN_STVX_V2DF);
16782 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16783 ALTIVEC_BUILTIN_STVX_V2DI);
16784 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16785 ALTIVEC_BUILTIN_STVX_V4SF);
16786 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16787 ALTIVEC_BUILTIN_STVX_V4SI);
16788 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16789 ALTIVEC_BUILTIN_STVX_V8HI);
16790 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16791 ALTIVEC_BUILTIN_STVX_V16QI);
16792 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16793 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16794 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16795 ALTIVEC_BUILTIN_STVXL_V2DF);
16796 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16797 ALTIVEC_BUILTIN_STVXL_V2DI);
16798 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16799 ALTIVEC_BUILTIN_STVXL_V4SF);
16800 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16801 ALTIVEC_BUILTIN_STVXL_V4SI);
16802 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16803 ALTIVEC_BUILTIN_STVXL_V8HI);
16804 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16805 ALTIVEC_BUILTIN_STVXL_V16QI);
16806 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16807 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16808 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16809 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16810 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16811 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16812 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16813 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16814 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16815 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16816 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16817 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16818 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16819 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16820 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16821 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16823 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16824 VSX_BUILTIN_LXVD2X_V2DF);
16825 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16826 VSX_BUILTIN_LXVD2X_V2DI);
16827 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16828 VSX_BUILTIN_LXVW4X_V4SF);
16829 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16830 VSX_BUILTIN_LXVW4X_V4SI);
16831 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16832 VSX_BUILTIN_LXVW4X_V8HI);
16833 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16834 VSX_BUILTIN_LXVW4X_V16QI);
16835 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16836 VSX_BUILTIN_STXVD2X_V2DF);
16837 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16838 VSX_BUILTIN_STXVD2X_V2DI);
16839 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16840 VSX_BUILTIN_STXVW4X_V4SF);
16841 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16842 VSX_BUILTIN_STXVW4X_V4SI);
16843 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16844 VSX_BUILTIN_STXVW4X_V8HI);
16845 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16846 VSX_BUILTIN_STXVW4X_V16QI);
16848 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16849 VSX_BUILTIN_LD_ELEMREV_V2DF);
16850 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16851 VSX_BUILTIN_LD_ELEMREV_V2DI);
16852 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16853 VSX_BUILTIN_LD_ELEMREV_V4SF);
16854 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16855 VSX_BUILTIN_LD_ELEMREV_V4SI);
16856 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16857 VSX_BUILTIN_LD_ELEMREV_V8HI);
16858 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16859 VSX_BUILTIN_LD_ELEMREV_V16QI);
16860 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16861 VSX_BUILTIN_ST_ELEMREV_V2DF);
16862 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16863 VSX_BUILTIN_ST_ELEMREV_V1TI);
16864 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16865 VSX_BUILTIN_ST_ELEMREV_V2DI);
16866 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16867 VSX_BUILTIN_ST_ELEMREV_V4SF);
16868 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16869 VSX_BUILTIN_ST_ELEMREV_V4SI);
16870 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16871 VSX_BUILTIN_ST_ELEMREV_V8HI);
16872 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16873 VSX_BUILTIN_ST_ELEMREV_V16QI);
16875 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16876 VSX_BUILTIN_VEC_LD);
16877 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16878 VSX_BUILTIN_VEC_ST);
16879 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16880 VSX_BUILTIN_VEC_XL);
16881 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16882 VSX_BUILTIN_VEC_XL_BE);
16883 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16884 VSX_BUILTIN_VEC_XST);
16885 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16886 VSX_BUILTIN_VEC_XST_BE);
16888 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16889 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16890 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16892 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16893 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16894 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16895 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16896 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16897 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16898 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16899 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16900 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16901 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16902 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16903 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16905 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16906 ALTIVEC_BUILTIN_VEC_ADDE);
16907 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16908 ALTIVEC_BUILTIN_VEC_ADDEC);
16909 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16910 ALTIVEC_BUILTIN_VEC_CMPNE);
16911 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16912 ALTIVEC_BUILTIN_VEC_MUL);
16913 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16914 ALTIVEC_BUILTIN_VEC_SUBE);
16915 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16916 ALTIVEC_BUILTIN_VEC_SUBEC);
16918 /* Cell builtins. */
16919 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16920 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16921 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16922 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16924 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16925 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16926 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16927 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16929 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16930 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16931 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16932 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16934 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16935 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16936 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16937 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16939 if (TARGET_P9_VECTOR)
16941 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16942 P9V_BUILTIN_STXVL);
16943 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16944 P9V_BUILTIN_XST_LEN_R);
16947 /* Add the DST variants. */
16949 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16951 HOST_WIDE_INT mask = d->mask;
16953 /* It is expected that these dst built-in functions may have
16954 d->icode equal to CODE_FOR_nothing. */
16955 if ((mask & builtin_mask) != mask)
16957 if (TARGET_DEBUG_BUILTIN)
16958 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16962 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16965 /* Initialize the predicates. */
16966 d = bdesc_altivec_preds;
16967 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16969 machine_mode mode1;
16971 HOST_WIDE_INT mask = d->mask;
16973 if ((mask & builtin_mask) != mask)
16975 if (TARGET_DEBUG_BUILTIN)
16976 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16981 if (rs6000_overloaded_builtin_p (d->code))
16985 /* Cannot define builtin if the instruction is disabled. */
16986 gcc_assert (d->icode != CODE_FOR_nothing);
16987 mode1 = insn_data[d->icode].operand[1].mode;
16993 type = int_ftype_int_opaque_opaque;
16996 type = int_ftype_int_v2di_v2di;
16999 type = int_ftype_int_v4si_v4si;
17002 type = int_ftype_int_v8hi_v8hi;
17005 type = int_ftype_int_v16qi_v16qi;
17008 type = int_ftype_int_v4sf_v4sf;
17011 type = int_ftype_int_v2df_v2df;
17014 gcc_unreachable ();
17017 def_builtin (d->name, type, d->code);
17020 /* Initialize the abs* operators. */
17022 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17024 machine_mode mode0;
17026 HOST_WIDE_INT mask = d->mask;
17028 if ((mask & builtin_mask) != mask)
17030 if (TARGET_DEBUG_BUILTIN)
17031 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17036 /* Cannot define builtin if the instruction is disabled. */
17037 gcc_assert (d->icode != CODE_FOR_nothing);
17038 mode0 = insn_data[d->icode].operand[0].mode;
17043 type = v2di_ftype_v2di;
17046 type = v4si_ftype_v4si;
17049 type = v8hi_ftype_v8hi;
17052 type = v16qi_ftype_v16qi;
17055 type = v4sf_ftype_v4sf;
17058 type = v2df_ftype_v2df;
17061 gcc_unreachable ();
17064 def_builtin (d->name, type, d->code);
17067 /* Initialize target builtin that implements
17068 targetm.vectorize.builtin_mask_for_load. */
17070 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17071 v16qi_ftype_long_pcvoid,
17072 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17073 BUILT_IN_MD, NULL, NULL_TREE);
17074 TREE_READONLY (decl) = 1;
17075 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17076 altivec_builtin_mask_for_load = decl;
17078 /* Access to the vec_init patterns. */
17079 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17080 integer_type_node, integer_type_node,
17081 integer_type_node, NULL_TREE);
17082 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17084 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17085 short_integer_type_node,
17086 short_integer_type_node,
17087 short_integer_type_node,
17088 short_integer_type_node,
17089 short_integer_type_node,
17090 short_integer_type_node,
17091 short_integer_type_node, NULL_TREE);
17092 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17094 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17095 char_type_node, char_type_node,
17096 char_type_node, char_type_node,
17097 char_type_node, char_type_node,
17098 char_type_node, char_type_node,
17099 char_type_node, char_type_node,
17100 char_type_node, char_type_node,
17101 char_type_node, char_type_node,
17102 char_type_node, NULL_TREE);
17103 def_builtin ("__builtin_vec_init_v16qi", ftype,
17104 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17106 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17107 float_type_node, float_type_node,
17108 float_type_node, NULL_TREE);
17109 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17111 /* VSX builtins. */
17112 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17113 double_type_node, NULL_TREE);
17114 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17116 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17117 intDI_type_node, NULL_TREE);
17118 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17120 /* Access to the vec_set patterns. */
17121 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17123 integer_type_node, NULL_TREE);
17124 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17126 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17128 integer_type_node, NULL_TREE);
17129 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17131 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17133 integer_type_node, NULL_TREE);
17134 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17136 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17138 integer_type_node, NULL_TREE);
17139 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17141 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17143 integer_type_node, NULL_TREE);
17144 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17146 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17148 integer_type_node, NULL_TREE);
17149 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17151 /* Access to the vec_extract patterns. */
17152 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17153 integer_type_node, NULL_TREE);
17154 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17156 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17157 integer_type_node, NULL_TREE);
17158 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17160 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17161 integer_type_node, NULL_TREE);
17162 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17164 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17165 integer_type_node, NULL_TREE);
17166 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17168 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17169 integer_type_node, NULL_TREE);
17170 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17172 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17173 integer_type_node, NULL_TREE);
17174 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17177 if (V1TI_type_node)
17179 tree v1ti_ftype_long_pcvoid
17180 = build_function_type_list (V1TI_type_node,
17181 long_integer_type_node, pcvoid_type_node,
17183 tree void_ftype_v1ti_long_pvoid
17184 = build_function_type_list (void_type_node,
17185 V1TI_type_node, long_integer_type_node,
17186 pvoid_type_node, NULL_TREE);
17187 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17188 VSX_BUILTIN_LD_ELEMREV_V1TI);
17189 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17190 VSX_BUILTIN_LXVD2X_V1TI);
17191 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17192 VSX_BUILTIN_STXVD2X_V1TI);
17193 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17194 NULL_TREE, NULL_TREE);
17195 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17196 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17198 integer_type_node, NULL_TREE);
17199 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17200 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17201 integer_type_node, NULL_TREE);
17202 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17208 htm_init_builtins (void)
17210 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17211 const struct builtin_description *d;
17215 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17217 tree op[MAX_HTM_OPERANDS], type;
17218 HOST_WIDE_INT mask = d->mask;
17219 unsigned attr = rs6000_builtin_info[d->code].attr;
17220 bool void_func = (attr & RS6000_BTC_VOID);
17221 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17223 tree gpr_type_node;
17227 /* It is expected that these htm built-in functions may have
17228 d->icode equal to CODE_FOR_nothing. */
17230 if (TARGET_32BIT && TARGET_POWERPC64)
17231 gpr_type_node = long_long_unsigned_type_node;
17233 gpr_type_node = long_unsigned_type_node;
17235 if (attr & RS6000_BTC_SPR)
17237 rettype = gpr_type_node;
17238 argtype = gpr_type_node;
17240 else if (d->code == HTM_BUILTIN_TABORTDC
17241 || d->code == HTM_BUILTIN_TABORTDCI)
17243 rettype = unsigned_type_node;
17244 argtype = gpr_type_node;
17248 rettype = unsigned_type_node;
17249 argtype = unsigned_type_node;
17252 if ((mask & builtin_mask) != mask)
17254 if (TARGET_DEBUG_BUILTIN)
17255 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17261 if (TARGET_DEBUG_BUILTIN)
17262 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17263 (long unsigned) i);
17267 op[nopnds++] = (void_func) ? void_type_node : rettype;
17269 if (attr_args == RS6000_BTC_UNARY)
17270 op[nopnds++] = argtype;
17271 else if (attr_args == RS6000_BTC_BINARY)
17273 op[nopnds++] = argtype;
17274 op[nopnds++] = argtype;
17276 else if (attr_args == RS6000_BTC_TERNARY)
17278 op[nopnds++] = argtype;
17279 op[nopnds++] = argtype;
17280 op[nopnds++] = argtype;
17286 type = build_function_type_list (op[0], NULL_TREE);
17289 type = build_function_type_list (op[0], op[1], NULL_TREE);
17292 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17295 type = build_function_type_list (op[0], op[1], op[2], op[3],
17299 gcc_unreachable ();
17302 def_builtin (d->name, type, d->code);
17306 /* Hash function for builtin functions with up to 3 arguments and a return
17309 builtin_hasher::hash (builtin_hash_struct *bh)
17314 for (i = 0; i < 4; i++)
17316 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17317 ret = (ret * 2) + bh->uns_p[i];
17323 /* Compare builtin hash entries H1 and H2 for equivalence. */
17325 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17327 return ((p1->mode[0] == p2->mode[0])
17328 && (p1->mode[1] == p2->mode[1])
17329 && (p1->mode[2] == p2->mode[2])
17330 && (p1->mode[3] == p2->mode[3])
17331 && (p1->uns_p[0] == p2->uns_p[0])
17332 && (p1->uns_p[1] == p2->uns_p[1])
17333 && (p1->uns_p[2] == p2->uns_p[2])
17334 && (p1->uns_p[3] == p2->uns_p[3]));
17337 /* Map types for builtin functions with an explicit return type and up to 3
17338 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17339 of the argument. */
17341 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17342 machine_mode mode_arg1, machine_mode mode_arg2,
17343 enum rs6000_builtins builtin, const char *name)
17345 struct builtin_hash_struct h;
17346 struct builtin_hash_struct *h2;
17349 tree ret_type = NULL_TREE;
17350 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17352 /* Create builtin_hash_table. */
17353 if (builtin_hash_table == NULL)
17354 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17356 h.type = NULL_TREE;
17357 h.mode[0] = mode_ret;
17358 h.mode[1] = mode_arg0;
17359 h.mode[2] = mode_arg1;
17360 h.mode[3] = mode_arg2;
17366 /* If the builtin is a type that produces unsigned results or takes unsigned
17367 arguments, and it is returned as a decl for the vectorizer (such as
17368 widening multiplies, permute), make sure the arguments and return value
17369 are type correct. */
17372 /* unsigned 1 argument functions. */
17373 case CRYPTO_BUILTIN_VSBOX:
17374 case P8V_BUILTIN_VGBBD:
17375 case MISC_BUILTIN_CDTBCD:
17376 case MISC_BUILTIN_CBCDTD:
17381 /* unsigned 2 argument functions. */
17382 case ALTIVEC_BUILTIN_VMULEUB:
17383 case ALTIVEC_BUILTIN_VMULEUH:
17384 case P8V_BUILTIN_VMULEUW:
17385 case ALTIVEC_BUILTIN_VMULOUB:
17386 case ALTIVEC_BUILTIN_VMULOUH:
17387 case P8V_BUILTIN_VMULOUW:
17388 case CRYPTO_BUILTIN_VCIPHER:
17389 case CRYPTO_BUILTIN_VCIPHERLAST:
17390 case CRYPTO_BUILTIN_VNCIPHER:
17391 case CRYPTO_BUILTIN_VNCIPHERLAST:
17392 case CRYPTO_BUILTIN_VPMSUMB:
17393 case CRYPTO_BUILTIN_VPMSUMH:
17394 case CRYPTO_BUILTIN_VPMSUMW:
17395 case CRYPTO_BUILTIN_VPMSUMD:
17396 case CRYPTO_BUILTIN_VPMSUM:
17397 case MISC_BUILTIN_ADDG6S:
17398 case MISC_BUILTIN_DIVWEU:
17399 case MISC_BUILTIN_DIVDEU:
17400 case VSX_BUILTIN_UDIV_V2DI:
17401 case ALTIVEC_BUILTIN_VMAXUB:
17402 case ALTIVEC_BUILTIN_VMINUB:
17403 case ALTIVEC_BUILTIN_VMAXUH:
17404 case ALTIVEC_BUILTIN_VMINUH:
17405 case ALTIVEC_BUILTIN_VMAXUW:
17406 case ALTIVEC_BUILTIN_VMINUW:
17407 case P8V_BUILTIN_VMAXUD:
17408 case P8V_BUILTIN_VMINUD:
17414 /* unsigned 3 argument functions. */
17415 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17416 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17417 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17418 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17419 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17420 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17421 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17422 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17423 case VSX_BUILTIN_VPERM_16QI_UNS:
17424 case VSX_BUILTIN_VPERM_8HI_UNS:
17425 case VSX_BUILTIN_VPERM_4SI_UNS:
17426 case VSX_BUILTIN_VPERM_2DI_UNS:
17427 case VSX_BUILTIN_XXSEL_16QI_UNS:
17428 case VSX_BUILTIN_XXSEL_8HI_UNS:
17429 case VSX_BUILTIN_XXSEL_4SI_UNS:
17430 case VSX_BUILTIN_XXSEL_2DI_UNS:
17431 case CRYPTO_BUILTIN_VPERMXOR:
17432 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17433 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17434 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17435 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17436 case CRYPTO_BUILTIN_VSHASIGMAW:
17437 case CRYPTO_BUILTIN_VSHASIGMAD:
17438 case CRYPTO_BUILTIN_VSHASIGMA:
17445 /* signed permute functions with unsigned char mask. */
17446 case ALTIVEC_BUILTIN_VPERM_16QI:
17447 case ALTIVEC_BUILTIN_VPERM_8HI:
17448 case ALTIVEC_BUILTIN_VPERM_4SI:
17449 case ALTIVEC_BUILTIN_VPERM_4SF:
17450 case ALTIVEC_BUILTIN_VPERM_2DI:
17451 case ALTIVEC_BUILTIN_VPERM_2DF:
17452 case VSX_BUILTIN_VPERM_16QI:
17453 case VSX_BUILTIN_VPERM_8HI:
17454 case VSX_BUILTIN_VPERM_4SI:
17455 case VSX_BUILTIN_VPERM_4SF:
17456 case VSX_BUILTIN_VPERM_2DI:
17457 case VSX_BUILTIN_VPERM_2DF:
17461 /* unsigned args, signed return. */
17462 case VSX_BUILTIN_XVCVUXDSP:
17463 case VSX_BUILTIN_XVCVUXDDP_UNS:
17464 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17468 /* signed args, unsigned return. */
17469 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17470 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17471 case MISC_BUILTIN_UNPACK_TD:
17472 case MISC_BUILTIN_UNPACK_V1TI:
17476 /* unsigned arguments, bool return (compares). */
17477 case ALTIVEC_BUILTIN_VCMPEQUB:
17478 case ALTIVEC_BUILTIN_VCMPEQUH:
17479 case ALTIVEC_BUILTIN_VCMPEQUW:
17480 case P8V_BUILTIN_VCMPEQUD:
17481 case VSX_BUILTIN_CMPGE_U16QI:
17482 case VSX_BUILTIN_CMPGE_U8HI:
17483 case VSX_BUILTIN_CMPGE_U4SI:
17484 case VSX_BUILTIN_CMPGE_U2DI:
17485 case ALTIVEC_BUILTIN_VCMPGTUB:
17486 case ALTIVEC_BUILTIN_VCMPGTUH:
17487 case ALTIVEC_BUILTIN_VCMPGTUW:
17488 case P8V_BUILTIN_VCMPGTUD:
17493 /* unsigned arguments for 128-bit pack instructions. */
17494 case MISC_BUILTIN_PACK_TD:
17495 case MISC_BUILTIN_PACK_V1TI:
17500 /* unsigned second arguments (vector shift right). */
17501 case ALTIVEC_BUILTIN_VSRB:
17502 case ALTIVEC_BUILTIN_VSRH:
17503 case ALTIVEC_BUILTIN_VSRW:
17504 case P8V_BUILTIN_VSRD:
17512 /* Figure out how many args are present. */
17513 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17516 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17517 if (!ret_type && h.uns_p[0])
17518 ret_type = builtin_mode_to_type[h.mode[0]][0];
17521 fatal_error (input_location,
17522 "internal error: builtin function %qs had an unexpected "
17523 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17525 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17526 arg_type[i] = NULL_TREE;
17528 for (i = 0; i < num_args; i++)
17530 int m = (int) h.mode[i+1];
17531 int uns_p = h.uns_p[i+1];
17533 arg_type[i] = builtin_mode_to_type[m][uns_p];
17534 if (!arg_type[i] && uns_p)
17535 arg_type[i] = builtin_mode_to_type[m][0];
17538 fatal_error (input_location,
17539 "internal error: builtin function %qs, argument %d "
17540 "had unexpected argument type %qs", name, i,
17541 GET_MODE_NAME (m));
17544 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17545 if (*found == NULL)
17547 h2 = ggc_alloc<builtin_hash_struct> ();
17551 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17552 arg_type[2], NULL_TREE);
17555 return (*found)->type;
17559 rs6000_common_init_builtins (void)
17561 const struct builtin_description *d;
17564 tree opaque_ftype_opaque = NULL_TREE;
17565 tree opaque_ftype_opaque_opaque = NULL_TREE;
17566 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17567 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17569 /* Create Altivec and VSX builtins on machines with at least the
17570 general purpose extensions (970 and newer) to allow the use of
17571 the target attribute. */
17573 if (TARGET_EXTRA_BUILTINS)
17574 builtin_mask |= RS6000_BTM_COMMON;
17576 /* Add the ternary operators. */
17578 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17581 HOST_WIDE_INT mask = d->mask;
17583 if ((mask & builtin_mask) != mask)
17585 if (TARGET_DEBUG_BUILTIN)
17586 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17590 if (rs6000_overloaded_builtin_p (d->code))
17592 if (! (type = opaque_ftype_opaque_opaque_opaque))
17593 type = opaque_ftype_opaque_opaque_opaque
17594 = build_function_type_list (opaque_V4SI_type_node,
17595 opaque_V4SI_type_node,
17596 opaque_V4SI_type_node,
17597 opaque_V4SI_type_node,
17602 enum insn_code icode = d->icode;
17605 if (TARGET_DEBUG_BUILTIN)
17606 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17612 if (icode == CODE_FOR_nothing)
17614 if (TARGET_DEBUG_BUILTIN)
17615 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17621 type = builtin_function_type (insn_data[icode].operand[0].mode,
17622 insn_data[icode].operand[1].mode,
17623 insn_data[icode].operand[2].mode,
17624 insn_data[icode].operand[3].mode,
17628 def_builtin (d->name, type, d->code);
17631 /* Add the binary operators. */
17633 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17635 machine_mode mode0, mode1, mode2;
17637 HOST_WIDE_INT mask = d->mask;
17639 if ((mask & builtin_mask) != mask)
17641 if (TARGET_DEBUG_BUILTIN)
17642 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17646 if (rs6000_overloaded_builtin_p (d->code))
17648 if (! (type = opaque_ftype_opaque_opaque))
17649 type = opaque_ftype_opaque_opaque
17650 = build_function_type_list (opaque_V4SI_type_node,
17651 opaque_V4SI_type_node,
17652 opaque_V4SI_type_node,
17657 enum insn_code icode = d->icode;
17660 if (TARGET_DEBUG_BUILTIN)
17661 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17667 if (icode == CODE_FOR_nothing)
17669 if (TARGET_DEBUG_BUILTIN)
17670 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17676 mode0 = insn_data[icode].operand[0].mode;
17677 mode1 = insn_data[icode].operand[1].mode;
17678 mode2 = insn_data[icode].operand[2].mode;
17680 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17684 def_builtin (d->name, type, d->code);
17687 /* Add the simple unary operators. */
17689 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17691 machine_mode mode0, mode1;
17693 HOST_WIDE_INT mask = d->mask;
17695 if ((mask & builtin_mask) != mask)
17697 if (TARGET_DEBUG_BUILTIN)
17698 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17702 if (rs6000_overloaded_builtin_p (d->code))
17704 if (! (type = opaque_ftype_opaque))
17705 type = opaque_ftype_opaque
17706 = build_function_type_list (opaque_V4SI_type_node,
17707 opaque_V4SI_type_node,
17712 enum insn_code icode = d->icode;
17715 if (TARGET_DEBUG_BUILTIN)
17716 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17722 if (icode == CODE_FOR_nothing)
17724 if (TARGET_DEBUG_BUILTIN)
17725 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17731 mode0 = insn_data[icode].operand[0].mode;
17732 mode1 = insn_data[icode].operand[1].mode;
17734 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17738 def_builtin (d->name, type, d->code);
17741 /* Add the simple no-argument operators. */
17743 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17745 machine_mode mode0;
17747 HOST_WIDE_INT mask = d->mask;
17749 if ((mask & builtin_mask) != mask)
17751 if (TARGET_DEBUG_BUILTIN)
17752 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17755 if (rs6000_overloaded_builtin_p (d->code))
17757 if (!opaque_ftype_opaque)
17758 opaque_ftype_opaque
17759 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17760 type = opaque_ftype_opaque;
17764 enum insn_code icode = d->icode;
17767 if (TARGET_DEBUG_BUILTIN)
17768 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17769 (long unsigned) i);
17772 if (icode == CODE_FOR_nothing)
17774 if (TARGET_DEBUG_BUILTIN)
17776 "rs6000_builtin, skip no-argument %s (no code)\n",
17780 mode0 = insn_data[icode].operand[0].mode;
17781 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17784 def_builtin (d->name, type, d->code);
17788 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17790 init_float128_ibm (machine_mode mode)
17792 if (!TARGET_XL_COMPAT)
17794 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17795 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17796 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17797 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17799 if (!TARGET_HARD_FLOAT)
17801 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17802 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17803 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17804 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17805 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17806 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17807 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17808 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17810 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17811 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17812 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17813 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17814 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17815 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17816 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17817 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17822 set_optab_libfunc (add_optab, mode, "_xlqadd");
17823 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17824 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17825 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17828 /* Add various conversions for IFmode to use the traditional TFmode
17830 if (mode == IFmode)
17832 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
17833 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
17834 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
17835 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
17836 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
17837 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
17839 if (TARGET_POWERPC64)
17841 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17842 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17843 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17844 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17849 /* Create a decl for either complex long double multiply or complex long double
17850 divide when long double is IEEE 128-bit floating point. We can't use
17851 __multc3 and __divtc3 because the original long double using IBM extended
17852 double used those names. The complex multiply/divide functions are encoded
17853 as builtin functions with a complex result and 4 scalar inputs. */
17856 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17858 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17861 set_builtin_decl (fncode, fndecl, true);
17863 if (TARGET_DEBUG_BUILTIN)
17864 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17869 /* Set up IEEE 128-bit floating point routines. Use different names if the
17870 arguments can be passed in a vector register. The historical PowerPC
17871 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17872 continue to use that if we aren't using vector registers to pass IEEE
17873 128-bit floating point. */
17876 init_float128_ieee (machine_mode mode)
17878 if (FLOAT128_VECTOR_P (mode))
17880 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. */
17881 if (mode == TFmode && TARGET_IEEEQUAD)
17883 built_in_function fncode_mul =
17884 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17885 - MIN_MODE_COMPLEX_FLOAT);
17886 built_in_function fncode_div =
17887 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17888 - MIN_MODE_COMPLEX_FLOAT);
17890 tree fntype = build_function_type_list (complex_long_double_type_node,
17891 long_double_type_node,
17892 long_double_type_node,
17893 long_double_type_node,
17894 long_double_type_node,
17897 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17898 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17901 set_optab_libfunc (add_optab, mode, "__addkf3");
17902 set_optab_libfunc (sub_optab, mode, "__subkf3");
17903 set_optab_libfunc (neg_optab, mode, "__negkf2");
17904 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17905 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17906 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17907 set_optab_libfunc (abs_optab, mode, "__abskf2");
17908 set_optab_libfunc (powi_optab, mode, "__powikf2");
17910 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17911 set_optab_libfunc (ne_optab, mode, "__nekf2");
17912 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17913 set_optab_libfunc (ge_optab, mode, "__gekf2");
17914 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17915 set_optab_libfunc (le_optab, mode, "__lekf2");
17916 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17918 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17919 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17920 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17921 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17923 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17924 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17925 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17927 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17928 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17929 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17931 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
17932 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
17933 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
17934 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
17935 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
17936 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
17938 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17939 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17940 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17941 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17943 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17944 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17945 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17946 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17948 if (TARGET_POWERPC64)
17950 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17951 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17952 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17953 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17959 set_optab_libfunc (add_optab, mode, "_q_add");
17960 set_optab_libfunc (sub_optab, mode, "_q_sub");
17961 set_optab_libfunc (neg_optab, mode, "_q_neg");
17962 set_optab_libfunc (smul_optab, mode, "_q_mul");
17963 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17964 if (TARGET_PPC_GPOPT)
17965 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17967 set_optab_libfunc (eq_optab, mode, "_q_feq");
17968 set_optab_libfunc (ne_optab, mode, "_q_fne");
17969 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17970 set_optab_libfunc (ge_optab, mode, "_q_fge");
17971 set_optab_libfunc (lt_optab, mode, "_q_flt");
17972 set_optab_libfunc (le_optab, mode, "_q_fle");
17974 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17975 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17976 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17977 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17978 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17979 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17980 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17981 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17986 rs6000_init_libfuncs (void)
17988 /* __float128 support. */
17989 if (TARGET_FLOAT128_TYPE)
17991 init_float128_ibm (IFmode);
17992 init_float128_ieee (KFmode);
17995 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17996 if (TARGET_LONG_DOUBLE_128)
17998 if (!TARGET_IEEEQUAD)
17999 init_float128_ibm (TFmode);
18001 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18003 init_float128_ieee (TFmode);
18007 /* Emit a potentially record-form instruction, setting DST from SRC.
18008 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18009 signed comparison of DST with zero. If DOT is 1, the generated RTL
18010 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18011 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18012 a separate COMPARE. */
18015 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18019 emit_move_insn (dst, src);
18023 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18025 emit_move_insn (dst, src);
18026 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18030 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18033 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18034 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18038 rtx set = gen_rtx_SET (dst, src);
18039 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18044 /* A validation routine: say whether CODE, a condition code, and MODE
18045 match. The other alternatives either don't make sense or should
18046 never be generated. */
18049 validate_condition_mode (enum rtx_code code, machine_mode mode)
18051 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18052 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18053 && GET_MODE_CLASS (mode) == MODE_CC);
18055 /* These don't make sense. */
18056 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18057 || mode != CCUNSmode);
18059 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18060 || mode == CCUNSmode);
18062 gcc_assert (mode == CCFPmode
18063 || (code != ORDERED && code != UNORDERED
18064 && code != UNEQ && code != LTGT
18065 && code != UNGT && code != UNLT
18066 && code != UNGE && code != UNLE));
18068 /* These should never be generated except for
18069 flag_finite_math_only. */
18070 gcc_assert (mode != CCFPmode
18071 || flag_finite_math_only
18072 || (code != LE && code != GE
18073 && code != UNEQ && code != LTGT
18074 && code != UNGT && code != UNLT));
18076 /* These are invalid; the information is not there. */
18077 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18081 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18082 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18083 not zero, store there the bit offset (counted from the right) where
18084 the single stretch of 1 bits begins; and similarly for B, the bit
18085 offset where it ends. */
18088 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18090 unsigned HOST_WIDE_INT val = INTVAL (mask);
18091 unsigned HOST_WIDE_INT bit;
18093 int n = GET_MODE_PRECISION (mode);
18095 if (mode != DImode && mode != SImode)
18098 if (INTVAL (mask) >= 0)
18101 ne = exact_log2 (bit);
18102 nb = exact_log2 (val + bit);
18104 else if (val + 1 == 0)
18113 nb = exact_log2 (bit);
18114 ne = exact_log2 (val + bit);
18119 ne = exact_log2 (bit);
18120 if (val + bit == 0)
18128 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18139 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18140 or rldicr instruction, to implement an AND with it in mode MODE. */
18143 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18147 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18150 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18152 if (mode == DImode)
18153 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18155 /* For SImode, rlwinm can do everything. */
18156 if (mode == SImode)
18157 return (nb < 32 && ne < 32);
18162 /* Return the instruction template for an AND with mask in mode MODE, with
18163 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18166 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18170 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18171 gcc_unreachable ();
18173 if (mode == DImode && ne == 0)
18175 operands[3] = GEN_INT (63 - nb);
18177 return "rldicl. %0,%1,0,%3";
18178 return "rldicl %0,%1,0,%3";
18181 if (mode == DImode && nb == 63)
18183 operands[3] = GEN_INT (63 - ne);
18185 return "rldicr. %0,%1,0,%3";
18186 return "rldicr %0,%1,0,%3";
18189 if (nb < 32 && ne < 32)
18191 operands[3] = GEN_INT (31 - nb);
18192 operands[4] = GEN_INT (31 - ne);
18194 return "rlwinm. %0,%1,0,%3,%4";
18195 return "rlwinm %0,%1,0,%3,%4";
18198 gcc_unreachable ();
18201 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18202 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18203 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18206 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18210 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18213 int n = GET_MODE_PRECISION (mode);
18216 if (CONST_INT_P (XEXP (shift, 1)))
18218 sh = INTVAL (XEXP (shift, 1));
18219 if (sh < 0 || sh >= n)
18223 rtx_code code = GET_CODE (shift);
18225 /* Convert any shift by 0 to a rotate, to simplify below code. */
18229 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18230 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18232 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18238 /* DImode rotates need rld*. */
18239 if (mode == DImode && code == ROTATE)
18240 return (nb == 63 || ne == 0 || ne == sh);
18242 /* SImode rotates need rlw*. */
18243 if (mode == SImode && code == ROTATE)
18244 return (nb < 32 && ne < 32 && sh < 32);
18246 /* Wrap-around masks are only okay for rotates. */
18250 /* Variable shifts are only okay for rotates. */
18254 /* Don't allow ASHIFT if the mask is wrong for that. */
18255 if (code == ASHIFT && ne < sh)
18258 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18259 if the mask is wrong for that. */
18260 if (nb < 32 && ne < 32 && sh < 32
18261 && !(code == LSHIFTRT && nb >= 32 - sh))
18264 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18265 if the mask is wrong for that. */
18266 if (code == LSHIFTRT)
18268 if (nb == 63 || ne == 0 || ne == sh)
18269 return !(code == LSHIFTRT && nb >= sh);
18274 /* Return the instruction template for a shift with mask in mode MODE, with
18275 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18278 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18282 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18283 gcc_unreachable ();
18285 if (mode == DImode && ne == 0)
18287 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18288 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18289 operands[3] = GEN_INT (63 - nb);
18291 return "rld%I2cl. %0,%1,%2,%3";
18292 return "rld%I2cl %0,%1,%2,%3";
18295 if (mode == DImode && nb == 63)
18297 operands[3] = GEN_INT (63 - ne);
18299 return "rld%I2cr. %0,%1,%2,%3";
18300 return "rld%I2cr %0,%1,%2,%3";
18304 && GET_CODE (operands[4]) != LSHIFTRT
18305 && CONST_INT_P (operands[2])
18306 && ne == INTVAL (operands[2]))
18308 operands[3] = GEN_INT (63 - nb);
18310 return "rld%I2c. %0,%1,%2,%3";
18311 return "rld%I2c %0,%1,%2,%3";
18314 if (nb < 32 && ne < 32)
18316 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18317 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18318 operands[3] = GEN_INT (31 - nb);
18319 operands[4] = GEN_INT (31 - ne);
18320 /* This insn can also be a 64-bit rotate with mask that really makes
18321 it just a shift right (with mask); the %h below are to adjust for
18322 that situation (shift count is >= 32 in that case). */
18324 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18325 return "rlw%I2nm %0,%1,%h2,%3,%4";
18328 gcc_unreachable ();
18331 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18332 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18333 ASHIFT, or LSHIFTRT) in mode MODE. */
18336 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18340 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18343 int n = GET_MODE_PRECISION (mode);
18345 int sh = INTVAL (XEXP (shift, 1));
18346 if (sh < 0 || sh >= n)
18349 rtx_code code = GET_CODE (shift);
18351 /* Convert any shift by 0 to a rotate, to simplify below code. */
18355 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18356 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18358 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18364 /* DImode rotates need rldimi. */
18365 if (mode == DImode && code == ROTATE)
18368 /* SImode rotates need rlwimi. */
18369 if (mode == SImode && code == ROTATE)
18370 return (nb < 32 && ne < 32 && sh < 32);
18372 /* Wrap-around masks are only okay for rotates. */
18376 /* Don't allow ASHIFT if the mask is wrong for that. */
18377 if (code == ASHIFT && ne < sh)
18380 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18381 if the mask is wrong for that. */
18382 if (nb < 32 && ne < 32 && sh < 32
18383 && !(code == LSHIFTRT && nb >= 32 - sh))
18386 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18387 if the mask is wrong for that. */
18388 if (code == LSHIFTRT)
18391 return !(code == LSHIFTRT && nb >= sh);
18396 /* Return the instruction template for an insert with mask in mode MODE, with
18397 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18400 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18404 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18405 gcc_unreachable ();
18407 /* Prefer rldimi because rlwimi is cracked. */
18408 if (TARGET_POWERPC64
18409 && (!dot || mode == DImode)
18410 && GET_CODE (operands[4]) != LSHIFTRT
18411 && ne == INTVAL (operands[2]))
18413 operands[3] = GEN_INT (63 - nb);
18415 return "rldimi. %0,%1,%2,%3";
18416 return "rldimi %0,%1,%2,%3";
18419 if (nb < 32 && ne < 32)
18421 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18422 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18423 operands[3] = GEN_INT (31 - nb);
18424 operands[4] = GEN_INT (31 - ne);
18426 return "rlwimi. %0,%1,%2,%3,%4";
18427 return "rlwimi %0,%1,%2,%3,%4";
18430 gcc_unreachable ();
18433 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18434 using two machine instructions. */
18437 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18439 /* There are two kinds of AND we can handle with two insns:
18440 1) those we can do with two rl* insn;
18443 We do not handle that last case yet. */
18445 /* If there is just one stretch of ones, we can do it. */
18446 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18449 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18450 one insn, we can do the whole thing with two. */
18451 unsigned HOST_WIDE_INT val = INTVAL (c);
18452 unsigned HOST_WIDE_INT bit1 = val & -val;
18453 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18454 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18455 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18456 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18459 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18460 If EXPAND is true, split rotate-and-mask instructions we generate to
18461 their constituent parts as well (this is used during expand); if DOT
18462 is 1, make the last insn a record-form instruction clobbering the
18463 destination GPR and setting the CC reg (from operands[3]); if 2, set
18464 that GPR as well as the CC reg. */
18467 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18469 gcc_assert (!(expand && dot));
18471 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18473 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18474 shift right. This generates better code than doing the masks without
18475 shifts, or shifting first right and then left. */
18477 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18479 gcc_assert (mode == DImode);
18481 int shift = 63 - nb;
18484 rtx tmp1 = gen_reg_rtx (DImode);
18485 rtx tmp2 = gen_reg_rtx (DImode);
18486 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18487 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18488 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18492 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18493 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18494 emit_move_insn (operands[0], tmp);
18495 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18496 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18501 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18502 that does the rest. */
18503 unsigned HOST_WIDE_INT bit1 = val & -val;
18504 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18505 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18506 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18508 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18509 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18511 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18513 /* Two "no-rotate"-and-mask instructions, for SImode. */
18514 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18516 gcc_assert (mode == SImode);
18518 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18519 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18520 emit_move_insn (reg, tmp);
18521 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18522 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18526 gcc_assert (mode == DImode);
18528 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18529 insns; we have to do the first in SImode, because it wraps. */
18530 if (mask2 <= 0xffffffff
18531 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18533 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18534 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18536 rtx reg_low = gen_lowpart (SImode, reg);
18537 emit_move_insn (reg_low, tmp);
18538 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18539 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18543 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18544 at the top end), rotate back and clear the other hole. */
18545 int right = exact_log2 (bit3);
18546 int left = 64 - right;
18548 /* Rotate the mask too. */
18549 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18553 rtx tmp1 = gen_reg_rtx (DImode);
18554 rtx tmp2 = gen_reg_rtx (DImode);
18555 rtx tmp3 = gen_reg_rtx (DImode);
18556 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18557 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18558 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18559 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18563 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18564 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18565 emit_move_insn (operands[0], tmp);
18566 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18567 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18568 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18572 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18573 for lfq and stfq insns iff the registers are hard registers. */
18576 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18578 /* We might have been passed a SUBREG. */
18579 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
18582 /* We might have been passed non floating point registers. */
18583 if (!FP_REGNO_P (REGNO (reg1))
18584 || !FP_REGNO_P (REGNO (reg2)))
18587 return (REGNO (reg1) == REGNO (reg2) - 1);
18590 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18591 addr1 and addr2 must be in consecutive memory locations
18592 (addr2 == addr1 + 8). */
18595 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18598 unsigned int reg1, reg2;
18599 int offset1, offset2;
18601 /* The mems cannot be volatile. */
18602 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18605 addr1 = XEXP (mem1, 0);
18606 addr2 = XEXP (mem2, 0);
18608 /* Extract an offset (if used) from the first addr. */
18609 if (GET_CODE (addr1) == PLUS)
18611 /* If not a REG, return zero. */
18612 if (GET_CODE (XEXP (addr1, 0)) != REG)
18616 reg1 = REGNO (XEXP (addr1, 0));
18617 /* The offset must be constant! */
18618 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
18620 offset1 = INTVAL (XEXP (addr1, 1));
18623 else if (GET_CODE (addr1) != REG)
18627 reg1 = REGNO (addr1);
18628 /* This was a simple (mem (reg)) expression. Offset is 0. */
18632 /* And now for the second addr. */
18633 if (GET_CODE (addr2) == PLUS)
18635 /* If not a REG, return zero. */
18636 if (GET_CODE (XEXP (addr2, 0)) != REG)
18640 reg2 = REGNO (XEXP (addr2, 0));
18641 /* The offset must be constant. */
18642 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
18644 offset2 = INTVAL (XEXP (addr2, 1));
18647 else if (GET_CODE (addr2) != REG)
18651 reg2 = REGNO (addr2);
18652 /* This was a simple (mem (reg)) expression. Offset is 0. */
18656 /* Both of these must have the same base register. */
18660 /* The offset for the second addr must be 8 more than the first addr. */
18661 if (offset2 != offset1 + 8)
18664 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18669 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18670 need to use DDmode, in all other cases we can use the same mode. */
18671 static machine_mode
18672 rs6000_secondary_memory_needed_mode (machine_mode mode)
18674 if (lra_in_progress && mode == SDmode)
18679 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18680 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18681 only work on the traditional altivec registers, note if an altivec register
18684 static enum rs6000_reg_type
18685 register_to_reg_type (rtx reg, bool *is_altivec)
18687 HOST_WIDE_INT regno;
18688 enum reg_class rclass;
18690 if (GET_CODE (reg) == SUBREG)
18691 reg = SUBREG_REG (reg);
18694 return NO_REG_TYPE;
18696 regno = REGNO (reg);
18697 if (regno >= FIRST_PSEUDO_REGISTER)
18699 if (!lra_in_progress && !reload_completed)
18700 return PSEUDO_REG_TYPE;
18702 regno = true_regnum (reg);
18703 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
18704 return PSEUDO_REG_TYPE;
18707 gcc_assert (regno >= 0);
18709 if (is_altivec && ALTIVEC_REGNO_P (regno))
18710 *is_altivec = true;
18712 rclass = rs6000_regno_regclass[regno];
18713 return reg_class_to_reg_type[(int)rclass];
18716 /* Helper function to return the cost of adding a TOC entry address. */
18719 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18723 if (TARGET_CMODEL != CMODEL_SMALL)
18724 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18727 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18732 /* Helper function for rs6000_secondary_reload to determine whether the memory
18733 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18734 needs reloading. Return negative if the memory is not handled by the memory
18735 helper functions and to try a different reload method, 0 if no additional
18736 instructions are need, and positive to give the extra cost for the
18740 rs6000_secondary_reload_memory (rtx addr,
18741 enum reg_class rclass,
18744 int extra_cost = 0;
18745 rtx reg, and_arg, plus_arg0, plus_arg1;
18746 addr_mask_type addr_mask;
18747 const char *type = NULL;
18748 const char *fail_msg = NULL;
18750 if (GPR_REG_CLASS_P (rclass))
18751 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18753 else if (rclass == FLOAT_REGS)
18754 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18756 else if (rclass == ALTIVEC_REGS)
18757 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18759 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18760 else if (rclass == VSX_REGS)
18761 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18762 & ~RELOAD_REG_AND_M16);
18764 /* If the register allocator hasn't made up its mind yet on the register
18765 class to use, settle on defaults to use. */
18766 else if (rclass == NO_REGS)
18768 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18769 & ~RELOAD_REG_AND_M16);
18771 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18772 addr_mask &= ~(RELOAD_REG_INDEXED
18773 | RELOAD_REG_PRE_INCDEC
18774 | RELOAD_REG_PRE_MODIFY);
18780 /* If the register isn't valid in this register class, just return now. */
18781 if ((addr_mask & RELOAD_REG_VALID) == 0)
18783 if (TARGET_DEBUG_ADDR)
18786 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18787 "not valid in class\n",
18788 GET_MODE_NAME (mode), reg_class_names[rclass]);
18795 switch (GET_CODE (addr))
18797 /* Does the register class supports auto update forms for this mode? We
18798 don't need a scratch register, since the powerpc only supports
18799 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18802 reg = XEXP (addr, 0);
18803 if (!base_reg_operand (addr, GET_MODE (reg)))
18805 fail_msg = "no base register #1";
18809 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18817 reg = XEXP (addr, 0);
18818 plus_arg1 = XEXP (addr, 1);
18819 if (!base_reg_operand (reg, GET_MODE (reg))
18820 || GET_CODE (plus_arg1) != PLUS
18821 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18823 fail_msg = "bad PRE_MODIFY";
18827 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18834 /* Do we need to simulate AND -16 to clear the bottom address bits used
18835 in VMX load/stores? Only allow the AND for vector sizes. */
18837 and_arg = XEXP (addr, 0);
18838 if (GET_MODE_SIZE (mode) != 16
18839 || GET_CODE (XEXP (addr, 1)) != CONST_INT
18840 || INTVAL (XEXP (addr, 1)) != -16)
18842 fail_msg = "bad Altivec AND #1";
18846 if (rclass != ALTIVEC_REGS)
18848 if (legitimate_indirect_address_p (and_arg, false))
18851 else if (legitimate_indexed_address_p (and_arg, false))
18856 fail_msg = "bad Altivec AND #2";
18864 /* If this is an indirect address, make sure it is a base register. */
18867 if (!legitimate_indirect_address_p (addr, false))
18874 /* If this is an indexed address, make sure the register class can handle
18875 indexed addresses for this mode. */
18877 plus_arg0 = XEXP (addr, 0);
18878 plus_arg1 = XEXP (addr, 1);
18880 /* (plus (plus (reg) (constant)) (constant)) is generated during
18881 push_reload processing, so handle it now. */
18882 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18884 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18891 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18892 push_reload processing, so handle it now. */
18893 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18895 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18898 type = "indexed #2";
18902 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18904 fail_msg = "no base register #2";
18908 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18910 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18911 || !legitimate_indexed_address_p (addr, false))
18918 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18919 && CONST_INT_P (plus_arg1))
18921 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18924 type = "vector d-form offset";
18928 /* Make sure the register class can handle offset addresses. */
18929 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18931 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18934 type = "offset #2";
18940 fail_msg = "bad PLUS";
18947 /* Quad offsets are restricted and can't handle normal addresses. */
18948 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18951 type = "vector d-form lo_sum";
18954 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18956 fail_msg = "bad LO_SUM";
18960 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18967 /* Static addresses need to create a TOC entry. */
18971 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18974 type = "vector d-form lo_sum #2";
18980 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18984 /* TOC references look like offsetable memory. */
18986 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18988 fail_msg = "bad UNSPEC";
18992 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18995 type = "vector d-form lo_sum #3";
18998 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19001 type = "toc reference";
19007 fail_msg = "bad address";
19012 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19014 if (extra_cost < 0)
19016 "rs6000_secondary_reload_memory error: mode = %s, "
19017 "class = %s, addr_mask = '%s', %s\n",
19018 GET_MODE_NAME (mode),
19019 reg_class_names[rclass],
19020 rs6000_debug_addr_mask (addr_mask, false),
19021 (fail_msg != NULL) ? fail_msg : "<bad address>");
19025 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19026 "addr_mask = '%s', extra cost = %d, %s\n",
19027 GET_MODE_NAME (mode),
19028 reg_class_names[rclass],
19029 rs6000_debug_addr_mask (addr_mask, false),
19031 (type) ? type : "<none>");
19039 /* Helper function for rs6000_secondary_reload to return true if a move to a
19040 different register classe is really a simple move. */
19043 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19044 enum rs6000_reg_type from_type,
19047 int size = GET_MODE_SIZE (mode);
19049 /* Add support for various direct moves available. In this function, we only
19050 look at cases where we don't need any extra registers, and one or more
19051 simple move insns are issued. Originally small integers are not allowed
19052 in FPR/VSX registers. Single precision binary floating is not a simple
19053 move because we need to convert to the single precision memory layout.
19054 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19055 need special direct move handling, which we do not support yet. */
19056 if (TARGET_DIRECT_MOVE
19057 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19058 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19060 if (TARGET_POWERPC64)
19062 /* ISA 2.07: MTVSRD or MVFVSRD. */
19066 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19067 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19071 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19072 if (TARGET_P8_VECTOR)
19074 if (mode == SImode)
19077 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19081 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19082 if (mode == SDmode)
19086 /* Power6+: MFTGPR or MFFGPR. */
19087 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19088 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19089 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19092 /* Move to/from SPR. */
19093 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19094 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19095 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19101 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19102 special direct moves that involve allocating an extra register, return the
19103 insn code of the helper function if there is such a function or
19104 CODE_FOR_nothing if not. */
19107 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19108 enum rs6000_reg_type from_type,
19110 secondary_reload_info *sri,
19114 enum insn_code icode = CODE_FOR_nothing;
19116 int size = GET_MODE_SIZE (mode);
19118 if (TARGET_POWERPC64 && size == 16)
19120 /* Handle moving 128-bit values from GPRs to VSX point registers on
19121 ISA 2.07 (power8, power9) when running in 64-bit mode using
19122 XXPERMDI to glue the two 64-bit values back together. */
19123 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19125 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19126 icode = reg_addr[mode].reload_vsx_gpr;
19129 /* Handle moving 128-bit values from VSX point registers to GPRs on
19130 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19131 bottom 64-bit value. */
19132 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19134 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19135 icode = reg_addr[mode].reload_gpr_vsx;
19139 else if (TARGET_POWERPC64 && mode == SFmode)
19141 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19143 cost = 3; /* xscvdpspn, mfvsrd, and. */
19144 icode = reg_addr[mode].reload_gpr_vsx;
19147 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19149 cost = 2; /* mtvsrz, xscvspdpn. */
19150 icode = reg_addr[mode].reload_vsx_gpr;
19154 else if (!TARGET_POWERPC64 && size == 8)
19156 /* Handle moving 64-bit values from GPRs to floating point registers on
19157 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19158 32-bit values back together. Altivec register classes must be handled
19159 specially since a different instruction is used, and the secondary
19160 reload support requires a single instruction class in the scratch
19161 register constraint. However, right now TFmode is not allowed in
19162 Altivec registers, so the pattern will never match. */
19163 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19165 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19166 icode = reg_addr[mode].reload_fpr_gpr;
19170 if (icode != CODE_FOR_nothing)
19175 sri->icode = icode;
19176 sri->extra_cost = cost;
19183 /* Return whether a move between two register classes can be done either
19184 directly (simple move) or via a pattern that uses a single extra temporary
19185 (using ISA 2.07's direct move in this case. */
19188 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19189 enum rs6000_reg_type from_type,
19191 secondary_reload_info *sri,
19194 /* Fall back to load/store reloads if either type is not a register. */
19195 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19198 /* If we haven't allocated registers yet, assume the move can be done for the
19199 standard register types. */
19200 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19201 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19202 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19205 /* Moves to the same set of registers is a simple move for non-specialized
19207 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19210 /* Check whether a simple move can be done directly. */
19211 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19215 sri->icode = CODE_FOR_nothing;
19216 sri->extra_cost = 0;
19221 /* Now check if we can do it in a few steps. */
19222 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19226 /* Inform reload about cases where moving X with a mode MODE to a register in
19227 RCLASS requires an extra scratch or immediate register. Return the class
19228 needed for the immediate register.
19230 For VSX and Altivec, we may need a register to convert sp+offset into
19233 For misaligned 64-bit gpr loads and stores we need a register to
19234 convert an offset address to indirect. */
19237 rs6000_secondary_reload (bool in_p,
19239 reg_class_t rclass_i,
19241 secondary_reload_info *sri)
19243 enum reg_class rclass = (enum reg_class) rclass_i;
19244 reg_class_t ret = ALL_REGS;
19245 enum insn_code icode;
19246 bool default_p = false;
19247 bool done_p = false;
19249 /* Allow subreg of memory before/during reload. */
19250 bool memory_p = (MEM_P (x)
19251 || (!reload_completed && GET_CODE (x) == SUBREG
19252 && MEM_P (SUBREG_REG (x))));
19254 sri->icode = CODE_FOR_nothing;
19255 sri->t_icode = CODE_FOR_nothing;
19256 sri->extra_cost = 0;
19258 ? reg_addr[mode].reload_load
19259 : reg_addr[mode].reload_store);
19261 if (REG_P (x) || register_operand (x, mode))
19263 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19264 bool altivec_p = (rclass == ALTIVEC_REGS);
19265 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19268 std::swap (to_type, from_type);
19270 /* Can we do a direct move of some sort? */
19271 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19274 icode = (enum insn_code)sri->icode;
19281 /* Make sure 0.0 is not reloaded or forced into memory. */
19282 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19289 /* If this is a scalar floating point value and we want to load it into the
19290 traditional Altivec registers, do it via a move via a traditional floating
19291 point register, unless we have D-form addressing. Also make sure that
19292 non-zero constants use a FPR. */
19293 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19294 && !mode_supports_vmx_dform (mode)
19295 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19296 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
19303 /* Handle reload of load/stores if we have reload helper functions. */
19304 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19306 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19309 if (extra_cost >= 0)
19313 if (extra_cost > 0)
19315 sri->extra_cost = extra_cost;
19316 sri->icode = icode;
19321 /* Handle unaligned loads and stores of integer registers. */
19322 if (!done_p && TARGET_POWERPC64
19323 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19325 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19327 rtx addr = XEXP (x, 0);
19328 rtx off = address_offset (addr);
19330 if (off != NULL_RTX)
19332 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19333 unsigned HOST_WIDE_INT offset = INTVAL (off);
19335 /* We need a secondary reload when our legitimate_address_p
19336 says the address is good (as otherwise the entire address
19337 will be reloaded), and the offset is not a multiple of
19338 four or we have an address wrap. Address wrap will only
19339 occur for LO_SUMs since legitimate_offset_address_p
19340 rejects addresses for 16-byte mems that will wrap. */
19341 if (GET_CODE (addr) == LO_SUM
19342 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19343 && ((offset & 3) != 0
19344 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19345 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19346 && (offset & 3) != 0))
19348 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19350 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19351 : CODE_FOR_reload_di_load);
19353 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19354 : CODE_FOR_reload_di_store);
19355 sri->extra_cost = 2;
19366 if (!done_p && !TARGET_POWERPC64
19367 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19369 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19371 rtx addr = XEXP (x, 0);
19372 rtx off = address_offset (addr);
19374 if (off != NULL_RTX)
19376 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19377 unsigned HOST_WIDE_INT offset = INTVAL (off);
19379 /* We need a secondary reload when our legitimate_address_p
19380 says the address is good (as otherwise the entire address
19381 will be reloaded), and we have a wrap.
19383 legitimate_lo_sum_address_p allows LO_SUM addresses to
19384 have any offset so test for wrap in the low 16 bits.
19386 legitimate_offset_address_p checks for the range
19387 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19388 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19389 [0x7ff4,0x7fff] respectively, so test for the
19390 intersection of these ranges, [0x7ffc,0x7fff] and
19391 [0x7ff4,0x7ff7] respectively.
19393 Note that the address we see here may have been
19394 manipulated by legitimize_reload_address. */
19395 if (GET_CODE (addr) == LO_SUM
19396 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19397 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19400 sri->icode = CODE_FOR_reload_si_load;
19402 sri->icode = CODE_FOR_reload_si_store;
19403 sri->extra_cost = 2;
19418 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19420 gcc_assert (ret != ALL_REGS);
19422 if (TARGET_DEBUG_ADDR)
19425 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19427 reg_class_names[ret],
19428 in_p ? "true" : "false",
19429 reg_class_names[rclass],
19430 GET_MODE_NAME (mode));
19432 if (reload_completed)
19433 fputs (", after reload", stderr);
19436 fputs (", done_p not set", stderr);
19439 fputs (", default secondary reload", stderr);
19441 if (sri->icode != CODE_FOR_nothing)
19442 fprintf (stderr, ", reload func = %s, extra cost = %d",
19443 insn_data[sri->icode].name, sri->extra_cost);
19445 else if (sri->extra_cost > 0)
19446 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19448 fputs ("\n", stderr);
19455 /* Better tracing for rs6000_secondary_reload_inner. */
19458 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19463 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19465 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19466 store_p ? "store" : "load");
19469 set = gen_rtx_SET (mem, reg);
19471 set = gen_rtx_SET (reg, mem);
19473 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19474 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19477 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19478 ATTRIBUTE_NORETURN;
19481 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19484 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19485 gcc_unreachable ();
19488 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19489 reload helper functions. These were identified in
19490 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19491 reload, it calls the insns:
19492 reload_<RELOAD:mode>_<P:mptrsize>_store
19493 reload_<RELOAD:mode>_<P:mptrsize>_load
19495 which in turn calls this function, to do whatever is necessary to create
19496 valid addresses. */
19499 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19501 int regno = true_regnum (reg);
19502 machine_mode mode = GET_MODE (reg);
19503 addr_mask_type addr_mask;
19506 rtx op_reg, op0, op1;
19511 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
19512 || !base_reg_operand (scratch, GET_MODE (scratch)))
19513 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19515 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19516 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19518 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19519 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19521 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19522 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19525 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19527 /* Make sure the mode is valid in this register class. */
19528 if ((addr_mask & RELOAD_REG_VALID) == 0)
19529 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19531 if (TARGET_DEBUG_ADDR)
19532 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19534 new_addr = addr = XEXP (mem, 0);
19535 switch (GET_CODE (addr))
19537 /* Does the register class support auto update forms for this mode? If
19538 not, do the update now. We don't need a scratch register, since the
19539 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19542 op_reg = XEXP (addr, 0);
19543 if (!base_reg_operand (op_reg, Pmode))
19544 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19546 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19548 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
19554 op0 = XEXP (addr, 0);
19555 op1 = XEXP (addr, 1);
19556 if (!base_reg_operand (op0, Pmode)
19557 || GET_CODE (op1) != PLUS
19558 || !rtx_equal_p (op0, XEXP (op1, 0)))
19559 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19561 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19563 emit_insn (gen_rtx_SET (op0, op1));
19568 /* Do we need to simulate AND -16 to clear the bottom address bits used
19569 in VMX load/stores? */
19571 op0 = XEXP (addr, 0);
19572 op1 = XEXP (addr, 1);
19573 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19575 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
19578 else if (GET_CODE (op1) == PLUS)
19580 emit_insn (gen_rtx_SET (scratch, op1));
19585 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19587 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19588 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19589 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19590 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19591 new_addr = scratch;
19595 /* If this is an indirect address, make sure it is a base register. */
19598 if (!base_reg_operand (addr, GET_MODE (addr)))
19600 emit_insn (gen_rtx_SET (scratch, addr));
19601 new_addr = scratch;
19605 /* If this is an indexed address, make sure the register class can handle
19606 indexed addresses for this mode. */
19608 op0 = XEXP (addr, 0);
19609 op1 = XEXP (addr, 1);
19610 if (!base_reg_operand (op0, Pmode))
19611 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19613 else if (int_reg_operand (op1, Pmode))
19615 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19617 emit_insn (gen_rtx_SET (scratch, addr));
19618 new_addr = scratch;
19622 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19624 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19625 || !quad_address_p (addr, mode, false))
19627 emit_insn (gen_rtx_SET (scratch, addr));
19628 new_addr = scratch;
19632 /* Make sure the register class can handle offset addresses. */
19633 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19635 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19637 emit_insn (gen_rtx_SET (scratch, addr));
19638 new_addr = scratch;
19643 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19648 op0 = XEXP (addr, 0);
19649 op1 = XEXP (addr, 1);
19650 if (!base_reg_operand (op0, Pmode))
19651 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19653 else if (int_reg_operand (op1, Pmode))
19655 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19657 emit_insn (gen_rtx_SET (scratch, addr));
19658 new_addr = scratch;
19662 /* Quad offsets are restricted and can't handle normal addresses. */
19663 else if (mode_supports_dq_form (mode))
19665 emit_insn (gen_rtx_SET (scratch, addr));
19666 new_addr = scratch;
19669 /* Make sure the register class can handle offset addresses. */
19670 else if (legitimate_lo_sum_address_p (mode, addr, false))
19672 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19674 emit_insn (gen_rtx_SET (scratch, addr));
19675 new_addr = scratch;
19680 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19687 rs6000_emit_move (scratch, addr, Pmode);
19688 new_addr = scratch;
19692 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19695 /* Adjust the address if it changed. */
19696 if (addr != new_addr)
19698 mem = replace_equiv_address_nv (mem, new_addr);
19699 if (TARGET_DEBUG_ADDR)
19700 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19703 /* Now create the move. */
19705 emit_insn (gen_rtx_SET (mem, reg));
19707 emit_insn (gen_rtx_SET (reg, mem));
19712 /* Convert reloads involving 64-bit gprs and misaligned offset
19713 addressing, or multiple 32-bit gprs and offsets that are too large,
19714 to use indirect addressing. */
19717 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19719 int regno = true_regnum (reg);
19720 enum reg_class rclass;
19722 rtx scratch_or_premodify = scratch;
19724 if (TARGET_DEBUG_ADDR)
19726 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19727 store_p ? "store" : "load");
19728 fprintf (stderr, "reg:\n");
19730 fprintf (stderr, "mem:\n");
19732 fprintf (stderr, "scratch:\n");
19733 debug_rtx (scratch);
19736 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
19737 gcc_assert (GET_CODE (mem) == MEM);
19738 rclass = REGNO_REG_CLASS (regno);
19739 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19740 addr = XEXP (mem, 0);
19742 if (GET_CODE (addr) == PRE_MODIFY)
19744 gcc_assert (REG_P (XEXP (addr, 0))
19745 && GET_CODE (XEXP (addr, 1)) == PLUS
19746 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19747 scratch_or_premodify = XEXP (addr, 0);
19748 if (!HARD_REGISTER_P (scratch_or_premodify))
19749 /* If we have a pseudo here then reload will have arranged
19750 to have it replaced, but only in the original insn.
19751 Use the replacement here too. */
19752 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
19754 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
19755 expressions from the original insn, without unsharing them.
19756 Any RTL that points into the original insn will of course
19757 have register replacements applied. That is why we don't
19758 need to look for replacements under the PLUS. */
19759 addr = XEXP (addr, 1);
19761 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19763 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19765 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19767 /* Now create the move. */
19769 emit_insn (gen_rtx_SET (mem, reg));
19771 emit_insn (gen_rtx_SET (reg, mem));
19776 /* Given an rtx X being reloaded into a reg required to be
19777 in class CLASS, return the class of reg to actually use.
19778 In general this is just CLASS; but on some machines
19779 in some cases it is preferable to use a more restrictive class.
19781 On the RS/6000, we have to return NO_REGS when we want to reload a
19782 floating-point CONST_DOUBLE to force it to be copied to memory.
19784 We also don't want to reload integer values into floating-point
19785 registers if we can at all help it. In fact, this can
19786 cause reload to die, if it tries to generate a reload of CTR
19787 into a FP register and discovers it doesn't have the memory location
19790 ??? Would it be a good idea to have reload do the converse, that is
19791 try to reload floating modes into FP registers if possible?
19794 static enum reg_class
19795 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19797 machine_mode mode = GET_MODE (x);
19798 bool is_constant = CONSTANT_P (x);
19800 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19801 reload class for it. */
19802 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19803 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19806 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19807 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19810 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19811 the reloading of address expressions using PLUS into floating point
19813 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19817 /* Zero is always allowed in all VSX registers. */
19818 if (x == CONST0_RTX (mode))
19821 /* If this is a vector constant that can be formed with a few Altivec
19822 instructions, we want altivec registers. */
19823 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19824 return ALTIVEC_REGS;
19826 /* If this is an integer constant that can easily be loaded into
19827 vector registers, allow it. */
19828 if (CONST_INT_P (x))
19830 HOST_WIDE_INT value = INTVAL (x);
19832 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19833 2.06 can generate it in the Altivec registers with
19837 if (TARGET_P8_VECTOR)
19839 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19840 return ALTIVEC_REGS;
19845 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19846 a sign extend in the Altivec registers. */
19847 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19848 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19849 return ALTIVEC_REGS;
19852 /* Force constant to memory. */
19856 /* D-form addressing can easily reload the value. */
19857 if (mode_supports_vmx_dform (mode)
19858 || mode_supports_dq_form (mode))
19861 /* If this is a scalar floating point value and we don't have D-form
19862 addressing, prefer the traditional floating point registers so that we
19863 can use D-form (register+offset) addressing. */
19864 if (rclass == VSX_REGS
19865 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19868 /* Prefer the Altivec registers if Altivec is handling the vector
19869 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19871 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19872 || mode == V1TImode)
19873 return ALTIVEC_REGS;
19878 if (is_constant || GET_CODE (x) == PLUS)
19880 if (reg_class_subset_p (GENERAL_REGS, rclass))
19881 return GENERAL_REGS;
19882 if (reg_class_subset_p (BASE_REGS, rclass))
19887 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
19888 return GENERAL_REGS;
19893 /* Debug version of rs6000_preferred_reload_class. */
19894 static enum reg_class
19895 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19897 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19900 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19902 reg_class_names[ret], reg_class_names[rclass],
19903 GET_MODE_NAME (GET_MODE (x)));
19909 /* If we are copying between FP or AltiVec registers and anything else, we need
19910 a memory location. The exception is when we are targeting ppc64 and the
19911 move to/from fpr to gpr instructions are available. Also, under VSX, you
19912 can copy vector registers from the FP register set to the Altivec register
19913 set and vice versa. */
19916 rs6000_secondary_memory_needed (machine_mode mode,
19917 reg_class_t from_class,
19918 reg_class_t to_class)
19920 enum rs6000_reg_type from_type, to_type;
19921 bool altivec_p = ((from_class == ALTIVEC_REGS)
19922 || (to_class == ALTIVEC_REGS));
19924 /* If a simple/direct move is available, we don't need secondary memory */
19925 from_type = reg_class_to_reg_type[(int)from_class];
19926 to_type = reg_class_to_reg_type[(int)to_class];
19928 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19929 (secondary_reload_info *)0, altivec_p))
19932 /* If we have a floating point or vector register class, we need to use
19933 memory to transfer the data. */
19934 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19940 /* Debug version of rs6000_secondary_memory_needed. */
19942 rs6000_debug_secondary_memory_needed (machine_mode mode,
19943 reg_class_t from_class,
19944 reg_class_t to_class)
19946 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19949 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19950 "to_class = %s, mode = %s\n",
19951 ret ? "true" : "false",
19952 reg_class_names[from_class],
19953 reg_class_names[to_class],
19954 GET_MODE_NAME (mode));
19959 /* Return the register class of a scratch register needed to copy IN into
19960 or out of a register in RCLASS in MODE. If it can be done directly,
19961 NO_REGS is returned. */
19963 static enum reg_class
19964 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19969 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19971 && MACHOPIC_INDIRECT
19975 /* We cannot copy a symbolic operand directly into anything
19976 other than BASE_REGS for TARGET_ELF. So indicate that a
19977 register from BASE_REGS is needed as an intermediate
19980 On Darwin, pic addresses require a load from memory, which
19981 needs a base register. */
19982 if (rclass != BASE_REGS
19983 && (GET_CODE (in) == SYMBOL_REF
19984 || GET_CODE (in) == HIGH
19985 || GET_CODE (in) == LABEL_REF
19986 || GET_CODE (in) == CONST))
19990 if (GET_CODE (in) == REG)
19992 regno = REGNO (in);
19993 if (regno >= FIRST_PSEUDO_REGISTER)
19995 regno = true_regnum (in);
19996 if (regno >= FIRST_PSEUDO_REGISTER)
20000 else if (GET_CODE (in) == SUBREG)
20002 regno = true_regnum (in);
20003 if (regno >= FIRST_PSEUDO_REGISTER)
20009 /* If we have VSX register moves, prefer moving scalar values between
20010 Altivec registers and GPR by going via an FPR (and then via memory)
20011 instead of reloading the secondary memory address for Altivec moves. */
20013 && GET_MODE_SIZE (mode) < 16
20014 && !mode_supports_vmx_dform (mode)
20015 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20016 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20017 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20018 && (regno >= 0 && INT_REGNO_P (regno)))))
20021 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20023 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20024 || (regno >= 0 && INT_REGNO_P (regno)))
20027 /* Constants, memory, and VSX registers can go into VSX registers (both the
20028 traditional floating point and the altivec registers). */
20029 if (rclass == VSX_REGS
20030 && (regno == -1 || VSX_REGNO_P (regno)))
20033 /* Constants, memory, and FP registers can go into FP registers. */
20034 if ((regno == -1 || FP_REGNO_P (regno))
20035 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20036 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20038 /* Memory, and AltiVec registers can go into AltiVec registers. */
20039 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20040 && rclass == ALTIVEC_REGS)
20043 /* We can copy among the CR registers. */
20044 if ((rclass == CR_REGS || rclass == CR0_REGS)
20045 && regno >= 0 && CR_REGNO_P (regno))
20048 /* Otherwise, we need GENERAL_REGS. */
20049 return GENERAL_REGS;
20052 /* Debug version of rs6000_secondary_reload_class. */
20053 static enum reg_class
20054 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20055 machine_mode mode, rtx in)
20057 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20059 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20060 "mode = %s, input rtx:\n",
20061 reg_class_names[ret], reg_class_names[rclass],
20062 GET_MODE_NAME (mode));
20068 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20071 rs6000_can_change_mode_class (machine_mode from,
20073 reg_class_t rclass)
20075 unsigned from_size = GET_MODE_SIZE (from);
20076 unsigned to_size = GET_MODE_SIZE (to);
20078 if (from_size != to_size)
20080 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20082 if (reg_classes_intersect_p (xclass, rclass))
20084 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20085 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20086 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20087 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20089 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20090 single register under VSX because the scalar part of the register
20091 is in the upper 64-bits, and not the lower 64-bits. Types like
20092 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20093 IEEE floating point can't overlap, and neither can small
20096 if (to_float128_vector_p && from_float128_vector_p)
20099 else if (to_float128_vector_p || from_float128_vector_p)
20102 /* TDmode in floating-mode registers must always go into a register
20103 pair with the most significant word in the even-numbered register
20104 to match ISA requirements. In little-endian mode, this does not
20105 match subreg numbering, so we cannot allow subregs. */
20106 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20109 if (from_size < 8 || to_size < 8)
20112 if (from_size == 8 && (8 * to_nregs) != to_size)
20115 if (to_size == 8 && (8 * from_nregs) != from_size)
20124 /* Since the VSX register set includes traditional floating point registers
20125 and altivec registers, just check for the size being different instead of
20126 trying to check whether the modes are vector modes. Otherwise it won't
20127 allow say DF and DI to change classes. For types like TFmode and TDmode
20128 that take 2 64-bit registers, rather than a single 128-bit register, don't
20129 allow subregs of those types to other 128 bit types. */
20130 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20132 unsigned num_regs = (from_size + 15) / 16;
20133 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20134 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20137 return (from_size == 8 || from_size == 16);
20140 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20141 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20147 /* Debug version of rs6000_can_change_mode_class. */
20149 rs6000_debug_can_change_mode_class (machine_mode from,
20151 reg_class_t rclass)
20153 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20156 "rs6000_can_change_mode_class, return %s, from = %s, "
20157 "to = %s, rclass = %s\n",
20158 ret ? "true" : "false",
20159 GET_MODE_NAME (from), GET_MODE_NAME (to),
20160 reg_class_names[rclass]);
20165 /* Return a string to do a move operation of 128 bits of data. */
20168 rs6000_output_move_128bit (rtx operands[])
20170 rtx dest = operands[0];
20171 rtx src = operands[1];
20172 machine_mode mode = GET_MODE (dest);
20175 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20176 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20180 dest_regno = REGNO (dest);
20181 dest_gpr_p = INT_REGNO_P (dest_regno);
20182 dest_fp_p = FP_REGNO_P (dest_regno);
20183 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20184 dest_vsx_p = dest_fp_p | dest_vmx_p;
20189 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20194 src_regno = REGNO (src);
20195 src_gpr_p = INT_REGNO_P (src_regno);
20196 src_fp_p = FP_REGNO_P (src_regno);
20197 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20198 src_vsx_p = src_fp_p | src_vmx_p;
20203 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20206 /* Register moves. */
20207 if (dest_regno >= 0 && src_regno >= 0)
20214 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20215 return (WORDS_BIG_ENDIAN
20216 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20217 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20219 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20223 else if (TARGET_VSX && dest_vsx_p)
20226 return "xxlor %x0,%x1,%x1";
20228 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20229 return (WORDS_BIG_ENDIAN
20230 ? "mtvsrdd %x0,%1,%L1"
20231 : "mtvsrdd %x0,%L1,%1");
20233 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20237 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20238 return "vor %0,%1,%1";
20240 else if (dest_fp_p && src_fp_p)
20245 else if (dest_regno >= 0 && MEM_P (src))
20249 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20255 else if (TARGET_ALTIVEC && dest_vmx_p
20256 && altivec_indexed_or_indirect_operand (src, mode))
20257 return "lvx %0,%y1";
20259 else if (TARGET_VSX && dest_vsx_p)
20261 if (mode_supports_dq_form (mode)
20262 && quad_address_p (XEXP (src, 0), mode, true))
20263 return "lxv %x0,%1";
20265 else if (TARGET_P9_VECTOR)
20266 return "lxvx %x0,%y1";
20268 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20269 return "lxvw4x %x0,%y1";
20272 return "lxvd2x %x0,%y1";
20275 else if (TARGET_ALTIVEC && dest_vmx_p)
20276 return "lvx %0,%y1";
20278 else if (dest_fp_p)
20283 else if (src_regno >= 0 && MEM_P (dest))
20287 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20288 return "stq %1,%0";
20293 else if (TARGET_ALTIVEC && src_vmx_p
20294 && altivec_indexed_or_indirect_operand (dest, mode))
20295 return "stvx %1,%y0";
20297 else if (TARGET_VSX && src_vsx_p)
20299 if (mode_supports_dq_form (mode)
20300 && quad_address_p (XEXP (dest, 0), mode, true))
20301 return "stxv %x1,%0";
20303 else if (TARGET_P9_VECTOR)
20304 return "stxvx %x1,%y0";
20306 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20307 return "stxvw4x %x1,%y0";
20310 return "stxvd2x %x1,%y0";
20313 else if (TARGET_ALTIVEC && src_vmx_p)
20314 return "stvx %1,%y0";
20321 else if (dest_regno >= 0
20322 && (GET_CODE (src) == CONST_INT
20323 || GET_CODE (src) == CONST_WIDE_INT
20324 || GET_CODE (src) == CONST_DOUBLE
20325 || GET_CODE (src) == CONST_VECTOR))
20330 else if ((dest_vmx_p && TARGET_ALTIVEC)
20331 || (dest_vsx_p && TARGET_VSX))
20332 return output_vec_const_move (operands);
20335 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20338 /* Validate a 128-bit move. */
20340 rs6000_move_128bit_ok_p (rtx operands[])
20342 machine_mode mode = GET_MODE (operands[0]);
20343 return (gpc_reg_operand (operands[0], mode)
20344 || gpc_reg_operand (operands[1], mode));
20347 /* Return true if a 128-bit move needs to be split. */
20349 rs6000_split_128bit_ok_p (rtx operands[])
20351 if (!reload_completed)
20354 if (!gpr_or_gpr_p (operands[0], operands[1]))
20357 if (quad_load_store_p (operands[0], operands[1]))
20364 /* Given a comparison operation, return the bit number in CCR to test. We
20365 know this is a valid comparison.
20367 SCC_P is 1 if this is for an scc. That means that %D will have been
20368 used instead of %C, so the bits will be in different places.
20370 Return -1 if OP isn't a valid comparison for some reason. */
20373 ccr_bit (rtx op, int scc_p)
20375 enum rtx_code code = GET_CODE (op);
20376 machine_mode cc_mode;
20381 if (!COMPARISON_P (op))
20384 reg = XEXP (op, 0);
20386 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
20388 cc_mode = GET_MODE (reg);
20389 cc_regnum = REGNO (reg);
20390 base_bit = 4 * (cc_regnum - CR0_REGNO);
20392 validate_condition_mode (code, cc_mode);
20394 /* When generating a sCOND operation, only positive conditions are
20397 || code == EQ || code == GT || code == LT || code == UNORDERED
20398 || code == GTU || code == LTU);
20403 return scc_p ? base_bit + 3 : base_bit + 2;
20405 return base_bit + 2;
20406 case GT: case GTU: case UNLE:
20407 return base_bit + 1;
20408 case LT: case LTU: case UNGE:
20410 case ORDERED: case UNORDERED:
20411 return base_bit + 3;
20414 /* If scc, we will have done a cror to put the bit in the
20415 unordered position. So test that bit. For integer, this is ! LT
20416 unless this is an scc insn. */
20417 return scc_p ? base_bit + 3 : base_bit;
20420 return scc_p ? base_bit + 3 : base_bit + 1;
20423 gcc_unreachable ();
20427 /* Return the GOT register. */
20430 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20432 /* The second flow pass currently (June 1999) can't update
20433 regs_ever_live without disturbing other parts of the compiler, so
20434 update it here to make the prolog/epilogue code happy. */
20435 if (!can_create_pseudo_p ()
20436 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20437 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20439 crtl->uses_pic_offset_table = 1;
20441 return pic_offset_table_rtx;
20444 static rs6000_stack_t stack_info;
20446 /* Function to init struct machine_function.
20447 This will be called, via a pointer variable,
20448 from push_function_context. */
20450 static struct machine_function *
20451 rs6000_init_machine_status (void)
20453 stack_info.reload_completed = 0;
20454 return ggc_cleared_alloc<machine_function> ();
20457 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
20459 /* Write out a function code label. */
20462 rs6000_output_function_entry (FILE *file, const char *fname)
20464 if (fname[0] != '.')
20466 switch (DEFAULT_ABI)
20469 gcc_unreachable ();
20475 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20485 RS6000_OUTPUT_BASENAME (file, fname);
20488 /* Print an operand. Recognize special options, documented below. */
20491 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20492 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20494 #define SMALL_DATA_RELOC "sda21"
20495 #define SMALL_DATA_REG 0
20499 print_operand (FILE *file, rtx x, int code)
20502 unsigned HOST_WIDE_INT uval;
20506 /* %a is output_address. */
20508 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20512 /* Like 'J' but get to the GT bit only. */
20513 gcc_assert (REG_P (x));
20515 /* Bit 1 is GT bit. */
20516 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20518 /* Add one for shift count in rlinm for scc. */
20519 fprintf (file, "%d", i + 1);
20523 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20526 output_operand_lossage ("invalid %%e value");
20531 if ((uval & 0xffff) == 0 && uval != 0)
20536 /* X is a CR register. Print the number of the EQ bit of the CR */
20537 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20538 output_operand_lossage ("invalid %%E value");
20540 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20544 /* X is a CR register. Print the shift count needed to move it
20545 to the high-order four bits. */
20546 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20547 output_operand_lossage ("invalid %%f value");
20549 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20553 /* Similar, but print the count for the rotate in the opposite
20555 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20556 output_operand_lossage ("invalid %%F value");
20558 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20562 /* X is a constant integer. If it is negative, print "m",
20563 otherwise print "z". This is to make an aze or ame insn. */
20564 if (GET_CODE (x) != CONST_INT)
20565 output_operand_lossage ("invalid %%G value");
20566 else if (INTVAL (x) >= 0)
20573 /* If constant, output low-order five bits. Otherwise, write
20576 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20578 print_operand (file, x, 0);
20582 /* If constant, output low-order six bits. Otherwise, write
20585 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20587 print_operand (file, x, 0);
20591 /* Print `i' if this is a constant, else nothing. */
20597 /* Write the bit number in CCR for jump. */
20598 i = ccr_bit (x, 0);
20600 output_operand_lossage ("invalid %%j code");
20602 fprintf (file, "%d", i);
20606 /* Similar, but add one for shift count in rlinm for scc and pass
20607 scc flag to `ccr_bit'. */
20608 i = ccr_bit (x, 1);
20610 output_operand_lossage ("invalid %%J code");
20612 /* If we want bit 31, write a shift count of zero, not 32. */
20613 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20617 /* X must be a constant. Write the 1's complement of the
20620 output_operand_lossage ("invalid %%k value");
20622 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20626 /* X must be a symbolic constant on ELF. Write an
20627 expression suitable for an 'addi' that adds in the low 16
20628 bits of the MEM. */
20629 if (GET_CODE (x) == CONST)
20631 if (GET_CODE (XEXP (x, 0)) != PLUS
20632 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
20633 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20634 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
20635 output_operand_lossage ("invalid %%K value");
20637 print_operand_address (file, x);
20638 fputs ("@l", file);
20641 /* %l is output_asm_label. */
20644 /* Write second word of DImode or DFmode reference. Works on register
20645 or non-indexed memory only. */
20647 fputs (reg_names[REGNO (x) + 1], file);
20648 else if (MEM_P (x))
20650 machine_mode mode = GET_MODE (x);
20651 /* Handle possible auto-increment. Since it is pre-increment and
20652 we have already done it, we can just use an offset of word. */
20653 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20654 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20655 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20657 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20658 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20661 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20665 if (small_data_operand (x, GET_MODE (x)))
20666 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20667 reg_names[SMALL_DATA_REG]);
20671 case 'N': /* Unused */
20672 /* Write the number of elements in the vector times 4. */
20673 if (GET_CODE (x) != PARALLEL)
20674 output_operand_lossage ("invalid %%N value");
20676 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20679 case 'O': /* Unused */
20680 /* Similar, but subtract 1 first. */
20681 if (GET_CODE (x) != PARALLEL)
20682 output_operand_lossage ("invalid %%O value");
20684 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20688 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20691 || (i = exact_log2 (INTVAL (x))) < 0)
20692 output_operand_lossage ("invalid %%p value");
20694 fprintf (file, "%d", i);
20698 /* The operand must be an indirect memory reference. The result
20699 is the register name. */
20700 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
20701 || REGNO (XEXP (x, 0)) >= 32)
20702 output_operand_lossage ("invalid %%P value");
20704 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20708 /* This outputs the logical code corresponding to a boolean
20709 expression. The expression may have one or both operands
20710 negated (if one, only the first one). For condition register
20711 logical operations, it will also treat the negated
20712 CR codes as NOTs, but not handle NOTs of them. */
20714 const char *const *t = 0;
20716 enum rtx_code code = GET_CODE (x);
20717 static const char * const tbl[3][3] = {
20718 { "and", "andc", "nor" },
20719 { "or", "orc", "nand" },
20720 { "xor", "eqv", "xor" } };
20724 else if (code == IOR)
20726 else if (code == XOR)
20729 output_operand_lossage ("invalid %%q value");
20731 if (GET_CODE (XEXP (x, 0)) != NOT)
20735 if (GET_CODE (XEXP (x, 1)) == NOT)
20746 if (! TARGET_MFCRF)
20752 /* X is a CR register. Print the mask for `mtcrf'. */
20753 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20754 output_operand_lossage ("invalid %%R value");
20756 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20760 /* Low 5 bits of 32 - value */
20762 output_operand_lossage ("invalid %%s value");
20764 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20768 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20769 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
20771 /* Bit 3 is OV bit. */
20772 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20774 /* If we want bit 31, write a shift count of zero, not 32. */
20775 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20779 /* Print the symbolic name of a branch target register. */
20780 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
20781 && REGNO (x) != CTR_REGNO))
20782 output_operand_lossage ("invalid %%T value");
20783 else if (REGNO (x) == LR_REGNO)
20784 fputs ("lr", file);
20786 fputs ("ctr", file);
20790 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20791 for use in unsigned operand. */
20794 output_operand_lossage ("invalid %%u value");
20799 if ((uval & 0xffff) == 0)
20802 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20806 /* High-order 16 bits of constant for use in signed operand. */
20808 output_operand_lossage ("invalid %%v value");
20810 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20811 (INTVAL (x) >> 16) & 0xffff);
20815 /* Print `u' if this has an auto-increment or auto-decrement. */
20817 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20818 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20819 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20824 /* Print the trap code for this operand. */
20825 switch (GET_CODE (x))
20828 fputs ("eq", file); /* 4 */
20831 fputs ("ne", file); /* 24 */
20834 fputs ("lt", file); /* 16 */
20837 fputs ("le", file); /* 20 */
20840 fputs ("gt", file); /* 8 */
20843 fputs ("ge", file); /* 12 */
20846 fputs ("llt", file); /* 2 */
20849 fputs ("lle", file); /* 6 */
20852 fputs ("lgt", file); /* 1 */
20855 fputs ("lge", file); /* 5 */
20858 gcc_unreachable ();
20863 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20866 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20867 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20869 print_operand (file, x, 0);
20873 /* X is a FPR or Altivec register used in a VSX context. */
20874 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
20875 output_operand_lossage ("invalid %%x value");
20878 int reg = REGNO (x);
20879 int vsx_reg = (FP_REGNO_P (reg)
20881 : reg - FIRST_ALTIVEC_REGNO + 32);
20883 #ifdef TARGET_REGNAMES
20884 if (TARGET_REGNAMES)
20885 fprintf (file, "%%vs%d", vsx_reg);
20888 fprintf (file, "%d", vsx_reg);
20894 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20895 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20896 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20901 /* Like 'L', for third word of TImode/PTImode */
20903 fputs (reg_names[REGNO (x) + 2], file);
20904 else if (MEM_P (x))
20906 machine_mode mode = GET_MODE (x);
20907 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20908 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20909 output_address (mode, plus_constant (Pmode,
20910 XEXP (XEXP (x, 0), 0), 8));
20911 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20912 output_address (mode, plus_constant (Pmode,
20913 XEXP (XEXP (x, 0), 0), 8));
20915 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20916 if (small_data_operand (x, GET_MODE (x)))
20917 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20918 reg_names[SMALL_DATA_REG]);
20923 /* X is a SYMBOL_REF. Write out the name preceded by a
20924 period and without any trailing data in brackets. Used for function
20925 names. If we are configured for System V (or the embedded ABI) on
20926 the PowerPC, do not emit the period, since those systems do not use
20927 TOCs and the like. */
20928 gcc_assert (GET_CODE (x) == SYMBOL_REF);
20930 /* For macho, check to see if we need a stub. */
20933 const char *name = XSTR (x, 0);
20935 if (darwin_emit_branch_islands
20936 && MACHOPIC_INDIRECT
20937 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20938 name = machopic_indirection_name (x, /*stub_p=*/true);
20940 assemble_name (file, name);
20942 else if (!DOT_SYMBOLS)
20943 assemble_name (file, XSTR (x, 0));
20945 rs6000_output_function_entry (file, XSTR (x, 0));
20949 /* Like 'L', for last word of TImode/PTImode. */
20951 fputs (reg_names[REGNO (x) + 3], file);
20952 else if (MEM_P (x))
20954 machine_mode mode = GET_MODE (x);
20955 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20956 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20957 output_address (mode, plus_constant (Pmode,
20958 XEXP (XEXP (x, 0), 0), 12));
20959 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20960 output_address (mode, plus_constant (Pmode,
20961 XEXP (XEXP (x, 0), 0), 12));
20963 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20964 if (small_data_operand (x, GET_MODE (x)))
20965 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20966 reg_names[SMALL_DATA_REG]);
20970 /* Print AltiVec memory operand. */
20975 gcc_assert (MEM_P (x));
20979 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20980 && GET_CODE (tmp) == AND
20981 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
20982 && INTVAL (XEXP (tmp, 1)) == -16)
20983 tmp = XEXP (tmp, 0);
20984 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20985 && GET_CODE (tmp) == PRE_MODIFY)
20986 tmp = XEXP (tmp, 1);
20988 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
20991 if (GET_CODE (tmp) != PLUS
20992 || !REG_P (XEXP (tmp, 0))
20993 || !REG_P (XEXP (tmp, 1)))
20995 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20999 if (REGNO (XEXP (tmp, 0)) == 0)
21000 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21001 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21003 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21004 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21011 fprintf (file, "%s", reg_names[REGNO (x)]);
21012 else if (MEM_P (x))
21014 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21015 know the width from the mode. */
21016 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21017 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21018 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21019 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21020 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21021 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21022 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21023 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21025 output_address (GET_MODE (x), XEXP (x, 0));
21029 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21030 /* This hack along with a corresponding hack in
21031 rs6000_output_addr_const_extra arranges to output addends
21032 where the assembler expects to find them. eg.
21033 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21034 without this hack would be output as "x@toc+4". We
21036 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21038 output_addr_const (file, x);
21043 if (const char *name = get_some_local_dynamic_name ())
21044 assemble_name (file, name);
21046 output_operand_lossage ("'%%&' used without any "
21047 "local dynamic TLS references");
21051 output_operand_lossage ("invalid %%xn code");
21055 /* Print the address of an operand. */
21058 print_operand_address (FILE *file, rtx x)
21061 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21062 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21063 || GET_CODE (x) == LABEL_REF)
21065 output_addr_const (file, x);
21066 if (small_data_operand (x, GET_MODE (x)))
21067 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21068 reg_names[SMALL_DATA_REG]);
21070 gcc_assert (!TARGET_TOC);
21072 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21073 && REG_P (XEXP (x, 1)))
21075 if (REGNO (XEXP (x, 0)) == 0)
21076 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21077 reg_names[ REGNO (XEXP (x, 0)) ]);
21079 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21080 reg_names[ REGNO (XEXP (x, 1)) ]);
21082 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21083 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21084 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21085 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21087 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21088 && CONSTANT_P (XEXP (x, 1)))
21090 fprintf (file, "lo16(");
21091 output_addr_const (file, XEXP (x, 1));
21092 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21096 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21097 && CONSTANT_P (XEXP (x, 1)))
21099 output_addr_const (file, XEXP (x, 1));
21100 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21103 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21105 /* This hack along with a corresponding hack in
21106 rs6000_output_addr_const_extra arranges to output addends
21107 where the assembler expects to find them. eg.
21109 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21110 without this hack would be output as "x@toc+8@l(9)". We
21111 want "x+8@toc@l(9)". */
21112 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21113 if (GET_CODE (x) == LO_SUM)
21114 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21116 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21119 gcc_unreachable ();
21122 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21125 rs6000_output_addr_const_extra (FILE *file, rtx x)
21127 if (GET_CODE (x) == UNSPEC)
21128 switch (XINT (x, 1))
21130 case UNSPEC_TOCREL:
21131 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21132 && REG_P (XVECEXP (x, 0, 1))
21133 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21134 output_addr_const (file, XVECEXP (x, 0, 0));
21135 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21137 if (INTVAL (tocrel_offset_oac) >= 0)
21138 fprintf (file, "+");
21139 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21141 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21144 assemble_name (file, toc_label_name);
21147 else if (TARGET_ELF)
21148 fputs ("@toc", file);
21152 case UNSPEC_MACHOPIC_OFFSET:
21153 output_addr_const (file, XVECEXP (x, 0, 0));
21155 machopic_output_function_base_name (file);
21162 /* Target hook for assembling integer objects. The PowerPC version has
21163 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21164 is defined. It also needs to handle DI-mode objects on 64-bit
21168 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21170 #ifdef RELOCATABLE_NEEDS_FIXUP
21171 /* Special handling for SI values. */
21172 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21174 static int recurse = 0;
21176 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21177 the .fixup section. Since the TOC section is already relocated, we
21178 don't need to mark it here. We used to skip the text section, but it
21179 should never be valid for relocated addresses to be placed in the text
21181 if (DEFAULT_ABI == ABI_V4
21182 && (TARGET_RELOCATABLE || flag_pic > 1)
21183 && in_section != toc_section
21185 && !CONST_SCALAR_INT_P (x)
21191 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21193 ASM_OUTPUT_LABEL (asm_out_file, buf);
21194 fprintf (asm_out_file, "\t.long\t(");
21195 output_addr_const (asm_out_file, x);
21196 fprintf (asm_out_file, ")@fixup\n");
21197 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21198 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21199 fprintf (asm_out_file, "\t.long\t");
21200 assemble_name (asm_out_file, buf);
21201 fprintf (asm_out_file, "\n\t.previous\n");
21205 /* Remove initial .'s to turn a -mcall-aixdesc function
21206 address into the address of the descriptor, not the function
21208 else if (GET_CODE (x) == SYMBOL_REF
21209 && XSTR (x, 0)[0] == '.'
21210 && DEFAULT_ABI == ABI_AIX)
21212 const char *name = XSTR (x, 0);
21213 while (*name == '.')
21216 fprintf (asm_out_file, "\t.long\t%s\n", name);
21220 #endif /* RELOCATABLE_NEEDS_FIXUP */
21221 return default_assemble_integer (x, size, aligned_p);
21224 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21225 /* Emit an assembler directive to set symbol visibility for DECL to
21226 VISIBILITY_TYPE. */
21229 rs6000_assemble_visibility (tree decl, int vis)
21234 /* Functions need to have their entry point symbol visibility set as
21235 well as their descriptor symbol visibility. */
21236 if (DEFAULT_ABI == ABI_AIX
21238 && TREE_CODE (decl) == FUNCTION_DECL)
21240 static const char * const visibility_types[] = {
21241 NULL, "protected", "hidden", "internal"
21244 const char *name, *type;
21246 name = ((* targetm.strip_name_encoding)
21247 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21248 type = visibility_types[vis];
21250 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21251 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21254 default_assemble_visibility (decl, vis);
21259 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21261 /* Reversal of FP compares takes care -- an ordered compare
21262 becomes an unordered compare and vice versa. */
21263 if (mode == CCFPmode
21264 && (!flag_finite_math_only
21265 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21266 || code == UNEQ || code == LTGT))
21267 return reverse_condition_maybe_unordered (code);
21269 return reverse_condition (code);
21272 /* Generate a compare for CODE. Return a brand-new rtx that
21273 represents the result of the compare. */
21276 rs6000_generate_compare (rtx cmp, machine_mode mode)
21278 machine_mode comp_mode;
21279 rtx compare_result;
21280 enum rtx_code code = GET_CODE (cmp);
21281 rtx op0 = XEXP (cmp, 0);
21282 rtx op1 = XEXP (cmp, 1);
21284 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21285 comp_mode = CCmode;
21286 else if (FLOAT_MODE_P (mode))
21287 comp_mode = CCFPmode;
21288 else if (code == GTU || code == LTU
21289 || code == GEU || code == LEU)
21290 comp_mode = CCUNSmode;
21291 else if ((code == EQ || code == NE)
21292 && unsigned_reg_p (op0)
21293 && (unsigned_reg_p (op1)
21294 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21295 /* These are unsigned values, perhaps there will be a later
21296 ordering compare that can be shared with this one. */
21297 comp_mode = CCUNSmode;
21299 comp_mode = CCmode;
21301 /* If we have an unsigned compare, make sure we don't have a signed value as
21303 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
21304 && INTVAL (op1) < 0)
21306 op0 = copy_rtx_if_shared (op0);
21307 op1 = force_reg (GET_MODE (op0), op1);
21308 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21311 /* First, the compare. */
21312 compare_result = gen_reg_rtx (comp_mode);
21314 /* IEEE 128-bit support in VSX registers when we do not have hardware
21316 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21318 rtx libfunc = NULL_RTX;
21319 bool check_nan = false;
21326 libfunc = optab_libfunc (eq_optab, mode);
21331 libfunc = optab_libfunc (ge_optab, mode);
21336 libfunc = optab_libfunc (le_optab, mode);
21341 libfunc = optab_libfunc (unord_optab, mode);
21342 code = (code == UNORDERED) ? NE : EQ;
21348 libfunc = optab_libfunc (ge_optab, mode);
21349 code = (code == UNGE) ? GE : GT;
21355 libfunc = optab_libfunc (le_optab, mode);
21356 code = (code == UNLE) ? LE : LT;
21362 libfunc = optab_libfunc (eq_optab, mode);
21363 code = (code = UNEQ) ? EQ : NE;
21367 gcc_unreachable ();
21370 gcc_assert (libfunc);
21373 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21374 SImode, op0, mode, op1, mode);
21376 /* The library signals an exception for signalling NaNs, so we need to
21377 handle isgreater, etc. by first checking isordered. */
21380 rtx ne_rtx, normal_dest, unord_dest;
21381 rtx unord_func = optab_libfunc (unord_optab, mode);
21382 rtx join_label = gen_label_rtx ();
21383 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21384 rtx unord_cmp = gen_reg_rtx (comp_mode);
21387 /* Test for either value being a NaN. */
21388 gcc_assert (unord_func);
21389 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21390 SImode, op0, mode, op1, mode);
21392 /* Set value (0) if either value is a NaN, and jump to the join
21394 dest = gen_reg_rtx (SImode);
21395 emit_move_insn (dest, const1_rtx);
21396 emit_insn (gen_rtx_SET (unord_cmp,
21397 gen_rtx_COMPARE (comp_mode, unord_dest,
21400 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21401 emit_jump_insn (gen_rtx_SET (pc_rtx,
21402 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21406 /* Do the normal comparison, knowing that the values are not
21408 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21409 SImode, op0, mode, op1, mode);
21411 emit_insn (gen_cstoresi4 (dest,
21412 gen_rtx_fmt_ee (code, SImode, normal_dest,
21414 normal_dest, const0_rtx));
21416 /* Join NaN and non-Nan paths. Compare dest against 0. */
21417 emit_label (join_label);
21421 emit_insn (gen_rtx_SET (compare_result,
21422 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21427 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21428 CLOBBERs to match cmptf_internal2 pattern. */
21429 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21430 && FLOAT128_IBM_P (GET_MODE (op0))
21431 && TARGET_HARD_FLOAT)
21432 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21434 gen_rtx_SET (compare_result,
21435 gen_rtx_COMPARE (comp_mode, op0, op1)),
21436 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21437 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21438 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21439 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21440 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21441 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21442 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21443 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21444 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21445 else if (GET_CODE (op1) == UNSPEC
21446 && XINT (op1, 1) == UNSPEC_SP_TEST)
21448 rtx op1b = XVECEXP (op1, 0, 0);
21449 comp_mode = CCEQmode;
21450 compare_result = gen_reg_rtx (CCEQmode);
21452 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21454 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21457 emit_insn (gen_rtx_SET (compare_result,
21458 gen_rtx_COMPARE (comp_mode, op0, op1)));
21461 /* Some kinds of FP comparisons need an OR operation;
21462 under flag_finite_math_only we don't bother. */
21463 if (FLOAT_MODE_P (mode)
21464 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21465 && !flag_finite_math_only
21466 && (code == LE || code == GE
21467 || code == UNEQ || code == LTGT
21468 || code == UNGT || code == UNLT))
21470 enum rtx_code or1, or2;
21471 rtx or1_rtx, or2_rtx, compare2_rtx;
21472 rtx or_result = gen_reg_rtx (CCEQmode);
21476 case LE: or1 = LT; or2 = EQ; break;
21477 case GE: or1 = GT; or2 = EQ; break;
21478 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21479 case LTGT: or1 = LT; or2 = GT; break;
21480 case UNGT: or1 = UNORDERED; or2 = GT; break;
21481 case UNLT: or1 = UNORDERED; or2 = LT; break;
21482 default: gcc_unreachable ();
21484 validate_condition_mode (or1, comp_mode);
21485 validate_condition_mode (or2, comp_mode);
21486 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21487 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21488 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21489 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21491 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21493 compare_result = or_result;
21497 validate_condition_mode (code, GET_MODE (compare_result));
21499 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21503 /* Return the diagnostic message string if the binary operation OP is
21504 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21507 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21511 machine_mode mode1 = TYPE_MODE (type1);
21512 machine_mode mode2 = TYPE_MODE (type2);
21514 /* For complex modes, use the inner type. */
21515 if (COMPLEX_MODE_P (mode1))
21516 mode1 = GET_MODE_INNER (mode1);
21518 if (COMPLEX_MODE_P (mode2))
21519 mode2 = GET_MODE_INNER (mode2);
21521 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21522 double to intermix unless -mfloat128-convert. */
21523 if (mode1 == mode2)
21526 if (!TARGET_FLOAT128_CVT)
21528 if ((mode1 == KFmode && mode2 == IFmode)
21529 || (mode1 == IFmode && mode2 == KFmode))
21530 return N_("__float128 and __ibm128 cannot be used in the same "
21533 if (TARGET_IEEEQUAD
21534 && ((mode1 == IFmode && mode2 == TFmode)
21535 || (mode1 == TFmode && mode2 == IFmode)))
21536 return N_("__ibm128 and long double cannot be used in the same "
21539 if (!TARGET_IEEEQUAD
21540 && ((mode1 == KFmode && mode2 == TFmode)
21541 || (mode1 == TFmode && mode2 == KFmode)))
21542 return N_("__float128 and long double cannot be used in the same "
21550 /* Expand floating point conversion to/from __float128 and __ibm128. */
21553 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21555 machine_mode dest_mode = GET_MODE (dest);
21556 machine_mode src_mode = GET_MODE (src);
21557 convert_optab cvt = unknown_optab;
21558 bool do_move = false;
21559 rtx libfunc = NULL_RTX;
21561 typedef rtx (*rtx_2func_t) (rtx, rtx);
21562 rtx_2func_t hw_convert = (rtx_2func_t)0;
21566 rtx_2func_t from_df;
21567 rtx_2func_t from_sf;
21568 rtx_2func_t from_si_sign;
21569 rtx_2func_t from_si_uns;
21570 rtx_2func_t from_di_sign;
21571 rtx_2func_t from_di_uns;
21574 rtx_2func_t to_si_sign;
21575 rtx_2func_t to_si_uns;
21576 rtx_2func_t to_di_sign;
21577 rtx_2func_t to_di_uns;
21578 } hw_conversions[2] = {
21579 /* convertions to/from KFmode */
21581 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21582 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21583 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21584 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21585 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21586 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21587 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21588 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21589 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21590 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21591 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21592 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21595 /* convertions to/from TFmode */
21597 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21598 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21599 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21600 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21601 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21602 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21603 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21604 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21605 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21606 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21607 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21608 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21612 if (dest_mode == src_mode)
21613 gcc_unreachable ();
21615 /* Eliminate memory operations. */
21617 src = force_reg (src_mode, src);
21621 rtx tmp = gen_reg_rtx (dest_mode);
21622 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21623 rs6000_emit_move (dest, tmp, dest_mode);
21627 /* Convert to IEEE 128-bit floating point. */
21628 if (FLOAT128_IEEE_P (dest_mode))
21630 if (dest_mode == KFmode)
21632 else if (dest_mode == TFmode)
21635 gcc_unreachable ();
21641 hw_convert = hw_conversions[kf_or_tf].from_df;
21646 hw_convert = hw_conversions[kf_or_tf].from_sf;
21652 if (FLOAT128_IBM_P (src_mode))
21661 cvt = ufloat_optab;
21662 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21666 cvt = sfloat_optab;
21667 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21674 cvt = ufloat_optab;
21675 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21679 cvt = sfloat_optab;
21680 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21685 gcc_unreachable ();
21689 /* Convert from IEEE 128-bit floating point. */
21690 else if (FLOAT128_IEEE_P (src_mode))
21692 if (src_mode == KFmode)
21694 else if (src_mode == TFmode)
21697 gcc_unreachable ();
21703 hw_convert = hw_conversions[kf_or_tf].to_df;
21708 hw_convert = hw_conversions[kf_or_tf].to_sf;
21714 if (FLOAT128_IBM_P (dest_mode))
21724 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
21729 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
21737 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
21742 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
21747 gcc_unreachable ();
21751 /* Both IBM format. */
21752 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
21756 gcc_unreachable ();
21758 /* Handle conversion between TFmode/KFmode/IFmode. */
21760 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
21762 /* Handle conversion if we have hardware support. */
21763 else if (TARGET_FLOAT128_HW && hw_convert)
21764 emit_insn ((hw_convert) (dest, src));
21766 /* Call an external function to do the conversion. */
21767 else if (cvt != unknown_optab)
21769 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
21770 gcc_assert (libfunc != NULL_RTX);
21772 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
21775 gcc_assert (dest2 != NULL_RTX);
21776 if (!rtx_equal_p (dest, dest2))
21777 emit_move_insn (dest, dest2);
21781 gcc_unreachable ();
21787 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
21788 can be used as that dest register. Return the dest register. */
21791 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
21793 if (op2 == const0_rtx)
21796 if (GET_CODE (scratch) == SCRATCH)
21797 scratch = gen_reg_rtx (mode);
21799 if (logical_operand (op2, mode))
21800 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
21802 emit_insn (gen_rtx_SET (scratch,
21803 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
21809 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
21812 machine_mode op_mode;
21813 enum rtx_code cond_code;
21814 rtx result = operands[0];
21816 condition_rtx = rs6000_generate_compare (operands[1], mode);
21817 cond_code = GET_CODE (condition_rtx);
21819 if (cond_code == NE
21820 || cond_code == GE || cond_code == LE
21821 || cond_code == GEU || cond_code == LEU
21822 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
21824 rtx not_result = gen_reg_rtx (CCEQmode);
21825 rtx not_op, rev_cond_rtx;
21826 machine_mode cc_mode;
21828 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
21830 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
21831 SImode, XEXP (condition_rtx, 0), const0_rtx);
21832 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
21833 emit_insn (gen_rtx_SET (not_result, not_op));
21834 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
21837 op_mode = GET_MODE (XEXP (operands[1], 0));
21838 if (op_mode == VOIDmode)
21839 op_mode = GET_MODE (XEXP (operands[1], 1));
21841 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
21843 PUT_MODE (condition_rtx, DImode);
21844 convert_move (result, condition_rtx, 0);
21848 PUT_MODE (condition_rtx, SImode);
21849 emit_insn (gen_rtx_SET (result, condition_rtx));
21853 /* Emit a branch of kind CODE to location LOC. */
21856 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
21858 rtx condition_rtx, loc_ref;
21860 condition_rtx = rs6000_generate_compare (operands[0], mode);
21861 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
21862 emit_jump_insn (gen_rtx_SET (pc_rtx,
21863 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
21864 loc_ref, pc_rtx)));
21867 /* Return the string to output a conditional branch to LABEL, which is
21868 the operand template of the label, or NULL if the branch is really a
21869 conditional return.
21871 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
21872 condition code register and its mode specifies what kind of
21873 comparison we made.
21875 REVERSED is nonzero if we should reverse the sense of the comparison.
21877 INSN is the insn. */
21880 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
21882 static char string[64];
21883 enum rtx_code code = GET_CODE (op);
21884 rtx cc_reg = XEXP (op, 0);
21885 machine_mode mode = GET_MODE (cc_reg);
21886 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
21887 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
21888 int really_reversed = reversed ^ need_longbranch;
21894 validate_condition_mode (code, mode);
21896 /* Work out which way this really branches. We could use
21897 reverse_condition_maybe_unordered here always but this
21898 makes the resulting assembler clearer. */
21899 if (really_reversed)
21901 /* Reversal of FP compares takes care -- an ordered compare
21902 becomes an unordered compare and vice versa. */
21903 if (mode == CCFPmode)
21904 code = reverse_condition_maybe_unordered (code);
21906 code = reverse_condition (code);
21911 /* Not all of these are actually distinct opcodes, but
21912 we distinguish them for clarity of the resulting assembler. */
21913 case NE: case LTGT:
21914 ccode = "ne"; break;
21915 case EQ: case UNEQ:
21916 ccode = "eq"; break;
21918 ccode = "ge"; break;
21919 case GT: case GTU: case UNGT:
21920 ccode = "gt"; break;
21922 ccode = "le"; break;
21923 case LT: case LTU: case UNLT:
21924 ccode = "lt"; break;
21925 case UNORDERED: ccode = "un"; break;
21926 case ORDERED: ccode = "nu"; break;
21927 case UNGE: ccode = "nl"; break;
21928 case UNLE: ccode = "ng"; break;
21930 gcc_unreachable ();
21933 /* Maybe we have a guess as to how likely the branch is. */
21935 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
21936 if (note != NULL_RTX)
21938 /* PROB is the difference from 50%. */
21939 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
21940 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
21942 /* Only hint for highly probable/improbable branches on newer cpus when
21943 we have real profile data, as static prediction overrides processor
21944 dynamic prediction. For older cpus we may as well always hint, but
21945 assume not taken for branches that are very close to 50% as a
21946 mispredicted taken branch is more expensive than a
21947 mispredicted not-taken branch. */
21948 if (rs6000_always_hint
21949 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
21950 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
21951 && br_prob_note_reliable_p (note)))
21953 if (abs (prob) > REG_BR_PROB_BASE / 20
21954 && ((prob > 0) ^ need_longbranch))
21962 s += sprintf (s, "b%slr%s ", ccode, pred);
21964 s += sprintf (s, "b%s%s ", ccode, pred);
21966 /* We need to escape any '%' characters in the reg_names string.
21967 Assume they'd only be the first character.... */
21968 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
21970 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
21974 /* If the branch distance was too far, we may have to use an
21975 unconditional branch to go the distance. */
21976 if (need_longbranch)
21977 s += sprintf (s, ",$+8\n\tb %s", label);
21979 s += sprintf (s, ",%s", label);
21985 /* Return insn for VSX or Altivec comparisons. */
21988 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
21991 machine_mode mode = GET_MODE (op0);
21999 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22010 mask = gen_reg_rtx (mode);
22011 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22018 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22019 DMODE is expected destination mode. This is a recursive function. */
22022 rs6000_emit_vector_compare (enum rtx_code rcode,
22024 machine_mode dmode)
22027 bool swap_operands = false;
22028 bool try_again = false;
22030 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22031 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22033 /* See if the comparison works as is. */
22034 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22042 swap_operands = true;
22047 swap_operands = true;
22055 /* Invert condition and try again.
22056 e.g., A != B becomes ~(A==B). */
22058 enum rtx_code rev_code;
22059 enum insn_code nor_code;
22062 rev_code = reverse_condition_maybe_unordered (rcode);
22063 if (rev_code == UNKNOWN)
22066 nor_code = optab_handler (one_cmpl_optab, dmode);
22067 if (nor_code == CODE_FOR_nothing)
22070 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22074 mask = gen_reg_rtx (dmode);
22075 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22083 /* Try GT/GTU/LT/LTU OR EQ */
22086 enum insn_code ior_code;
22087 enum rtx_code new_code;
22108 gcc_unreachable ();
22111 ior_code = optab_handler (ior_optab, dmode);
22112 if (ior_code == CODE_FOR_nothing)
22115 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22119 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22123 mask = gen_reg_rtx (dmode);
22124 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22135 std::swap (op0, op1);
22137 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22142 /* You only get two chances. */
22146 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22147 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22148 operands for the relation operation COND. */
22151 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22152 rtx cond, rtx cc_op0, rtx cc_op1)
22154 machine_mode dest_mode = GET_MODE (dest);
22155 machine_mode mask_mode = GET_MODE (cc_op0);
22156 enum rtx_code rcode = GET_CODE (cond);
22157 machine_mode cc_mode = CCmode;
22160 bool invert_move = false;
22162 if (VECTOR_UNIT_NONE_P (dest_mode))
22165 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22166 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22170 /* Swap operands if we can, and fall back to doing the operation as
22171 specified, and doing a NOR to invert the test. */
22177 /* Invert condition and try again.
22178 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22179 invert_move = true;
22180 rcode = reverse_condition_maybe_unordered (rcode);
22181 if (rcode == UNKNOWN)
22187 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22189 /* Invert condition to avoid compound test. */
22190 invert_move = true;
22191 rcode = reverse_condition (rcode);
22199 /* Mark unsigned tests with CCUNSmode. */
22200 cc_mode = CCUNSmode;
22202 /* Invert condition to avoid compound test if necessary. */
22203 if (rcode == GEU || rcode == LEU)
22205 invert_move = true;
22206 rcode = reverse_condition (rcode);
22214 /* Get the vector mask for the given relational operations. */
22215 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22221 std::swap (op_true, op_false);
22223 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22224 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22225 && (GET_CODE (op_true) == CONST_VECTOR
22226 || GET_CODE (op_false) == CONST_VECTOR))
22228 rtx constant_0 = CONST0_RTX (dest_mode);
22229 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22231 if (op_true == constant_m1 && op_false == constant_0)
22233 emit_move_insn (dest, mask);
22237 else if (op_true == constant_0 && op_false == constant_m1)
22239 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22243 /* If we can't use the vector comparison directly, perhaps we can use
22244 the mask for the true or false fields, instead of loading up a
22246 if (op_true == constant_m1)
22249 if (op_false == constant_0)
22253 if (!REG_P (op_true) && !SUBREG_P (op_true))
22254 op_true = force_reg (dest_mode, op_true);
22256 if (!REG_P (op_false) && !SUBREG_P (op_false))
22257 op_false = force_reg (dest_mode, op_false);
22259 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22260 CONST0_RTX (dest_mode));
22261 emit_insn (gen_rtx_SET (dest,
22262 gen_rtx_IF_THEN_ELSE (dest_mode,
22269 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22270 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22271 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22272 hardware has no such operation. */
22275 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22277 enum rtx_code code = GET_CODE (op);
22278 rtx op0 = XEXP (op, 0);
22279 rtx op1 = XEXP (op, 1);
22280 machine_mode compare_mode = GET_MODE (op0);
22281 machine_mode result_mode = GET_MODE (dest);
22282 bool max_p = false;
22284 if (result_mode != compare_mode)
22287 if (code == GE || code == GT)
22289 else if (code == LE || code == LT)
22294 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22297 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22303 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22307 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22308 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22309 operands of the last comparison is nonzero/true, FALSE_COND if it is
22310 zero/false. Return 0 if the hardware has no such operation. */
22313 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22315 enum rtx_code code = GET_CODE (op);
22316 rtx op0 = XEXP (op, 0);
22317 rtx op1 = XEXP (op, 1);
22318 machine_mode result_mode = GET_MODE (dest);
22323 if (!can_create_pseudo_p ())
22336 code = swap_condition (code);
22337 std::swap (op0, op1);
22344 /* Generate: [(parallel [(set (dest)
22345 (if_then_else (op (cmp1) (cmp2))
22348 (clobber (scratch))])]. */
22350 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22351 cmove_rtx = gen_rtx_SET (dest,
22352 gen_rtx_IF_THEN_ELSE (result_mode,
22357 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22358 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22359 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22364 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22365 operands of the last comparison is nonzero/true, FALSE_COND if it
22366 is zero/false. Return 0 if the hardware has no such operation. */
22369 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22371 enum rtx_code code = GET_CODE (op);
22372 rtx op0 = XEXP (op, 0);
22373 rtx op1 = XEXP (op, 1);
22374 machine_mode compare_mode = GET_MODE (op0);
22375 machine_mode result_mode = GET_MODE (dest);
22377 bool is_against_zero;
22379 /* These modes should always match. */
22380 if (GET_MODE (op1) != compare_mode
22381 /* In the isel case however, we can use a compare immediate, so
22382 op1 may be a small constant. */
22383 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22385 if (GET_MODE (true_cond) != result_mode)
22387 if (GET_MODE (false_cond) != result_mode)
22390 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22391 if (TARGET_P9_MINMAX
22392 && (compare_mode == SFmode || compare_mode == DFmode)
22393 && (result_mode == SFmode || result_mode == DFmode))
22395 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22398 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22402 /* Don't allow using floating point comparisons for integer results for
22404 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22407 /* First, work out if the hardware can do this at all, or
22408 if it's too slow.... */
22409 if (!FLOAT_MODE_P (compare_mode))
22412 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22416 is_against_zero = op1 == CONST0_RTX (compare_mode);
22418 /* A floating-point subtract might overflow, underflow, or produce
22419 an inexact result, thus changing the floating-point flags, so it
22420 can't be generated if we care about that. It's safe if one side
22421 of the construct is zero, since then no subtract will be
22423 if (SCALAR_FLOAT_MODE_P (compare_mode)
22424 && flag_trapping_math && ! is_against_zero)
22427 /* Eliminate half of the comparisons by switching operands, this
22428 makes the remaining code simpler. */
22429 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22430 || code == LTGT || code == LT || code == UNLE)
22432 code = reverse_condition_maybe_unordered (code);
22434 true_cond = false_cond;
22438 /* UNEQ and LTGT take four instructions for a comparison with zero,
22439 it'll probably be faster to use a branch here too. */
22440 if (code == UNEQ && HONOR_NANS (compare_mode))
22443 /* We're going to try to implement comparisons by performing
22444 a subtract, then comparing against zero. Unfortunately,
22445 Inf - Inf is NaN which is not zero, and so if we don't
22446 know that the operand is finite and the comparison
22447 would treat EQ different to UNORDERED, we can't do it. */
22448 if (HONOR_INFINITIES (compare_mode)
22449 && code != GT && code != UNGE
22450 && (GET_CODE (op1) != CONST_DOUBLE
22451 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22452 /* Constructs of the form (a OP b ? a : b) are safe. */
22453 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22454 || (! rtx_equal_p (op0, true_cond)
22455 && ! rtx_equal_p (op1, true_cond))))
22458 /* At this point we know we can use fsel. */
22460 /* Reduce the comparison to a comparison against zero. */
22461 if (! is_against_zero)
22463 temp = gen_reg_rtx (compare_mode);
22464 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22466 op1 = CONST0_RTX (compare_mode);
22469 /* If we don't care about NaNs we can reduce some of the comparisons
22470 down to faster ones. */
22471 if (! HONOR_NANS (compare_mode))
22477 true_cond = false_cond;
22490 /* Now, reduce everything down to a GE. */
22497 temp = gen_reg_rtx (compare_mode);
22498 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22503 temp = gen_reg_rtx (compare_mode);
22504 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22509 temp = gen_reg_rtx (compare_mode);
22510 emit_insn (gen_rtx_SET (temp,
22511 gen_rtx_NEG (compare_mode,
22512 gen_rtx_ABS (compare_mode, op0))));
22517 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22518 temp = gen_reg_rtx (result_mode);
22519 emit_insn (gen_rtx_SET (temp,
22520 gen_rtx_IF_THEN_ELSE (result_mode,
22521 gen_rtx_GE (VOIDmode,
22523 true_cond, false_cond)));
22524 false_cond = true_cond;
22527 temp = gen_reg_rtx (compare_mode);
22528 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22533 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22534 temp = gen_reg_rtx (result_mode);
22535 emit_insn (gen_rtx_SET (temp,
22536 gen_rtx_IF_THEN_ELSE (result_mode,
22537 gen_rtx_GE (VOIDmode,
22539 true_cond, false_cond)));
22540 true_cond = false_cond;
22543 temp = gen_reg_rtx (compare_mode);
22544 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22549 gcc_unreachable ();
22552 emit_insn (gen_rtx_SET (dest,
22553 gen_rtx_IF_THEN_ELSE (result_mode,
22554 gen_rtx_GE (VOIDmode,
22556 true_cond, false_cond)));
22560 /* Same as above, but for ints (isel). */
22563 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22565 rtx condition_rtx, cr;
22566 machine_mode mode = GET_MODE (dest);
22567 enum rtx_code cond_code;
22568 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22571 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22574 /* We still have to do the compare, because isel doesn't do a
22575 compare, it just looks at the CRx bits set by a previous compare
22577 condition_rtx = rs6000_generate_compare (op, mode);
22578 cond_code = GET_CODE (condition_rtx);
22579 cr = XEXP (condition_rtx, 0);
22580 signedp = GET_MODE (cr) == CCmode;
22582 isel_func = (mode == SImode
22583 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22584 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22588 case LT: case GT: case LTU: case GTU: case EQ:
22589 /* isel handles these directly. */
22593 /* We need to swap the sense of the comparison. */
22595 std::swap (false_cond, true_cond);
22596 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22601 false_cond = force_reg (mode, false_cond);
22602 if (true_cond != const0_rtx)
22603 true_cond = force_reg (mode, true_cond);
22605 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22611 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22613 machine_mode mode = GET_MODE (op0);
22617 /* VSX/altivec have direct min/max insns. */
22618 if ((code == SMAX || code == SMIN)
22619 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22620 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22622 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22626 if (code == SMAX || code == SMIN)
22631 if (code == SMAX || code == UMAX)
22632 target = emit_conditional_move (dest, c, op0, op1, mode,
22633 op0, op1, mode, 0);
22635 target = emit_conditional_move (dest, c, op0, op1, mode,
22636 op1, op0, mode, 0);
22637 gcc_assert (target);
22638 if (target != dest)
22639 emit_move_insn (dest, target);
22642 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22643 COND is true. Mark the jump as unlikely to be taken. */
22646 emit_unlikely_jump (rtx cond, rtx label)
22648 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22649 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22650 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22653 /* A subroutine of the atomic operation splitters. Emit a load-locked
22654 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22655 the zero_extend operation. */
22658 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22660 rtx (*fn) (rtx, rtx) = NULL;
22665 fn = gen_load_lockedqi;
22668 fn = gen_load_lockedhi;
22671 if (GET_MODE (mem) == QImode)
22672 fn = gen_load_lockedqi_si;
22673 else if (GET_MODE (mem) == HImode)
22674 fn = gen_load_lockedhi_si;
22676 fn = gen_load_lockedsi;
22679 fn = gen_load_lockeddi;
22682 fn = gen_load_lockedti;
22685 gcc_unreachable ();
22687 emit_insn (fn (reg, mem));
22690 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22691 instruction in MODE. */
22694 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
22696 rtx (*fn) (rtx, rtx, rtx) = NULL;
22701 fn = gen_store_conditionalqi;
22704 fn = gen_store_conditionalhi;
22707 fn = gen_store_conditionalsi;
22710 fn = gen_store_conditionaldi;
22713 fn = gen_store_conditionalti;
22716 gcc_unreachable ();
22719 /* Emit sync before stwcx. to address PPC405 Erratum. */
22720 if (PPC405_ERRATUM77)
22721 emit_insn (gen_hwsync ());
22723 emit_insn (fn (res, mem, val));
22726 /* Expand barriers before and after a load_locked/store_cond sequence. */
22729 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
22731 rtx addr = XEXP (mem, 0);
22733 if (!legitimate_indirect_address_p (addr, reload_completed)
22734 && !legitimate_indexed_address_p (addr, reload_completed))
22736 addr = force_reg (Pmode, addr);
22737 mem = replace_equiv_address_nv (mem, addr);
22742 case MEMMODEL_RELAXED:
22743 case MEMMODEL_CONSUME:
22744 case MEMMODEL_ACQUIRE:
22746 case MEMMODEL_RELEASE:
22747 case MEMMODEL_ACQ_REL:
22748 emit_insn (gen_lwsync ());
22750 case MEMMODEL_SEQ_CST:
22751 emit_insn (gen_hwsync ());
22754 gcc_unreachable ();
22760 rs6000_post_atomic_barrier (enum memmodel model)
22764 case MEMMODEL_RELAXED:
22765 case MEMMODEL_CONSUME:
22766 case MEMMODEL_RELEASE:
22768 case MEMMODEL_ACQUIRE:
22769 case MEMMODEL_ACQ_REL:
22770 case MEMMODEL_SEQ_CST:
22771 emit_insn (gen_isync ());
22774 gcc_unreachable ();
22778 /* A subroutine of the various atomic expanders. For sub-word operations,
22779 we must adjust things to operate on SImode. Given the original MEM,
22780 return a new aligned memory. Also build and return the quantities by
22781 which to shift and mask. */
22784 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
22786 rtx addr, align, shift, mask, mem;
22787 HOST_WIDE_INT shift_mask;
22788 machine_mode mode = GET_MODE (orig_mem);
22790 /* For smaller modes, we have to implement this via SImode. */
22791 shift_mask = (mode == QImode ? 0x18 : 0x10);
22793 addr = XEXP (orig_mem, 0);
22794 addr = force_reg (GET_MODE (addr), addr);
22796 /* Aligned memory containing subword. Generate a new memory. We
22797 do not want any of the existing MEM_ATTR data, as we're now
22798 accessing memory outside the original object. */
22799 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
22800 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22801 mem = gen_rtx_MEM (SImode, align);
22802 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
22803 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
22804 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
22806 /* Shift amount for subword relative to aligned word. */
22807 shift = gen_reg_rtx (SImode);
22808 addr = gen_lowpart (SImode, addr);
22809 rtx tmp = gen_reg_rtx (SImode);
22810 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
22811 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
22812 if (BYTES_BIG_ENDIAN)
22813 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
22814 shift, 1, OPTAB_LIB_WIDEN);
22817 /* Mask for insertion. */
22818 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
22819 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
22825 /* A subroutine of the various atomic expanders. For sub-word operands,
22826 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
22829 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
22833 x = gen_reg_rtx (SImode);
22834 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
22835 gen_rtx_NOT (SImode, mask),
22838 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
22843 /* A subroutine of the various atomic expanders. For sub-word operands,
22844 extract WIDE to NARROW via SHIFT. */
22847 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
22849 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
22850 wide, 1, OPTAB_LIB_WIDEN);
22851 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
22854 /* Expand an atomic compare and swap operation. */
22857 rs6000_expand_atomic_compare_and_swap (rtx operands[])
22859 rtx boolval, retval, mem, oldval, newval, cond;
22860 rtx label1, label2, x, mask, shift;
22861 machine_mode mode, orig_mode;
22862 enum memmodel mod_s, mod_f;
22865 boolval = operands[0];
22866 retval = operands[1];
22868 oldval = operands[3];
22869 newval = operands[4];
22870 is_weak = (INTVAL (operands[5]) != 0);
22871 mod_s = memmodel_base (INTVAL (operands[6]));
22872 mod_f = memmodel_base (INTVAL (operands[7]));
22873 orig_mode = mode = GET_MODE (mem);
22875 mask = shift = NULL_RTX;
22876 if (mode == QImode || mode == HImode)
22878 /* Before power8, we didn't have access to lbarx/lharx, so generate a
22879 lwarx and shift/mask operations. With power8, we need to do the
22880 comparison in SImode, but the store is still done in QI/HImode. */
22881 oldval = convert_modes (SImode, mode, oldval, 1);
22883 if (!TARGET_SYNC_HI_QI)
22885 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
22887 /* Shift and mask OLDVAL into position with the word. */
22888 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
22889 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22891 /* Shift and mask NEWVAL into position within the word. */
22892 newval = convert_modes (SImode, mode, newval, 1);
22893 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
22894 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22897 /* Prepare to adjust the return value. */
22898 retval = gen_reg_rtx (SImode);
22901 else if (reg_overlap_mentioned_p (retval, oldval))
22902 oldval = copy_to_reg (oldval);
22904 if (mode != TImode && !reg_or_short_operand (oldval, mode))
22905 oldval = copy_to_mode_reg (mode, oldval);
22907 if (reg_overlap_mentioned_p (retval, newval))
22908 newval = copy_to_reg (newval);
22910 mem = rs6000_pre_atomic_barrier (mem, mod_s);
22915 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
22916 emit_label (XEXP (label1, 0));
22918 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
22920 emit_load_locked (mode, retval, mem);
22924 x = expand_simple_binop (SImode, AND, retval, mask,
22925 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22927 cond = gen_reg_rtx (CCmode);
22928 /* If we have TImode, synthesize a comparison. */
22929 if (mode != TImode)
22930 x = gen_rtx_COMPARE (CCmode, x, oldval);
22933 rtx xor1_result = gen_reg_rtx (DImode);
22934 rtx xor2_result = gen_reg_rtx (DImode);
22935 rtx or_result = gen_reg_rtx (DImode);
22936 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
22937 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
22938 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
22939 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
22941 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
22942 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
22943 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
22944 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
22947 emit_insn (gen_rtx_SET (cond, x));
22949 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
22950 emit_unlikely_jump (x, label2);
22954 x = rs6000_mask_atomic_subword (retval, newval, mask);
22956 emit_store_conditional (orig_mode, cond, mem, x);
22960 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
22961 emit_unlikely_jump (x, label1);
22964 if (!is_mm_relaxed (mod_f))
22965 emit_label (XEXP (label2, 0));
22967 rs6000_post_atomic_barrier (mod_s);
22969 if (is_mm_relaxed (mod_f))
22970 emit_label (XEXP (label2, 0));
22973 rs6000_finish_atomic_subword (operands[1], retval, shift);
22974 else if (mode != GET_MODE (operands[1]))
22975 convert_move (operands[1], retval, 1);
22977 /* In all cases, CR0 contains EQ on success, and NE on failure. */
22978 x = gen_rtx_EQ (SImode, cond, const0_rtx);
22979 emit_insn (gen_rtx_SET (boolval, x));
22982 /* Expand an atomic exchange operation. */
22985 rs6000_expand_atomic_exchange (rtx operands[])
22987 rtx retval, mem, val, cond;
22989 enum memmodel model;
22990 rtx label, x, mask, shift;
22992 retval = operands[0];
22995 model = memmodel_base (INTVAL (operands[3]));
22996 mode = GET_MODE (mem);
22998 mask = shift = NULL_RTX;
22999 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23001 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23003 /* Shift and mask VAL into position with the word. */
23004 val = convert_modes (SImode, mode, val, 1);
23005 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23006 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23008 /* Prepare to adjust the return value. */
23009 retval = gen_reg_rtx (SImode);
23013 mem = rs6000_pre_atomic_barrier (mem, model);
23015 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23016 emit_label (XEXP (label, 0));
23018 emit_load_locked (mode, retval, mem);
23022 x = rs6000_mask_atomic_subword (retval, val, mask);
23024 cond = gen_reg_rtx (CCmode);
23025 emit_store_conditional (mode, cond, mem, x);
23027 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23028 emit_unlikely_jump (x, label);
23030 rs6000_post_atomic_barrier (model);
23033 rs6000_finish_atomic_subword (operands[0], retval, shift);
23036 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23037 to perform. MEM is the memory on which to operate. VAL is the second
23038 operand of the binary operator. BEFORE and AFTER are optional locations to
23039 return the value of MEM either before of after the operation. MODEL_RTX
23040 is a CONST_INT containing the memory model to use. */
23043 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23044 rtx orig_before, rtx orig_after, rtx model_rtx)
23046 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23047 machine_mode mode = GET_MODE (mem);
23048 machine_mode store_mode = mode;
23049 rtx label, x, cond, mask, shift;
23050 rtx before = orig_before, after = orig_after;
23052 mask = shift = NULL_RTX;
23053 /* On power8, we want to use SImode for the operation. On previous systems,
23054 use the operation in a subword and shift/mask to get the proper byte or
23056 if (mode == QImode || mode == HImode)
23058 if (TARGET_SYNC_HI_QI)
23060 val = convert_modes (SImode, mode, val, 1);
23062 /* Prepare to adjust the return value. */
23063 before = gen_reg_rtx (SImode);
23065 after = gen_reg_rtx (SImode);
23070 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23072 /* Shift and mask VAL into position with the word. */
23073 val = convert_modes (SImode, mode, val, 1);
23074 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23075 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23081 /* We've already zero-extended VAL. That is sufficient to
23082 make certain that it does not affect other bits. */
23087 /* If we make certain that all of the other bits in VAL are
23088 set, that will be sufficient to not affect other bits. */
23089 x = gen_rtx_NOT (SImode, mask);
23090 x = gen_rtx_IOR (SImode, x, val);
23091 emit_insn (gen_rtx_SET (val, x));
23098 /* These will all affect bits outside the field and need
23099 adjustment via MASK within the loop. */
23103 gcc_unreachable ();
23106 /* Prepare to adjust the return value. */
23107 before = gen_reg_rtx (SImode);
23109 after = gen_reg_rtx (SImode);
23110 store_mode = mode = SImode;
23114 mem = rs6000_pre_atomic_barrier (mem, model);
23116 label = gen_label_rtx ();
23117 emit_label (label);
23118 label = gen_rtx_LABEL_REF (VOIDmode, label);
23120 if (before == NULL_RTX)
23121 before = gen_reg_rtx (mode);
23123 emit_load_locked (mode, before, mem);
23127 x = expand_simple_binop (mode, AND, before, val,
23128 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23129 after = expand_simple_unop (mode, NOT, x, after, 1);
23133 after = expand_simple_binop (mode, code, before, val,
23134 after, 1, OPTAB_LIB_WIDEN);
23140 x = expand_simple_binop (SImode, AND, after, mask,
23141 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23142 x = rs6000_mask_atomic_subword (before, x, mask);
23144 else if (store_mode != mode)
23145 x = convert_modes (store_mode, mode, x, 1);
23147 cond = gen_reg_rtx (CCmode);
23148 emit_store_conditional (store_mode, cond, mem, x);
23150 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23151 emit_unlikely_jump (x, label);
23153 rs6000_post_atomic_barrier (model);
23157 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23158 then do the calcuations in a SImode register. */
23160 rs6000_finish_atomic_subword (orig_before, before, shift);
23162 rs6000_finish_atomic_subword (orig_after, after, shift);
23164 else if (store_mode != mode)
23166 /* QImode/HImode on machines with lbarx/lharx where we do the native
23167 operation and then do the calcuations in a SImode register. */
23169 convert_move (orig_before, before, 1);
23171 convert_move (orig_after, after, 1);
23173 else if (orig_after && after != orig_after)
23174 emit_move_insn (orig_after, after);
23177 /* Emit instructions to move SRC to DST. Called by splitters for
23178 multi-register moves. It will emit at most one instruction for
23179 each register that is accessed; that is, it won't emit li/lis pairs
23180 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23184 rs6000_split_multireg_move (rtx dst, rtx src)
23186 /* The register number of the first register being moved. */
23188 /* The mode that is to be moved. */
23190 /* The mode that the move is being done in, and its size. */
23191 machine_mode reg_mode;
23193 /* The number of registers that will be moved. */
23196 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23197 mode = GET_MODE (dst);
23198 nregs = hard_regno_nregs (reg, mode);
23199 if (FP_REGNO_P (reg))
23200 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23201 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23202 else if (ALTIVEC_REGNO_P (reg))
23203 reg_mode = V16QImode;
23205 reg_mode = word_mode;
23206 reg_mode_size = GET_MODE_SIZE (reg_mode);
23208 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23210 /* TDmode residing in FP registers is special, since the ISA requires that
23211 the lower-numbered word of a register pair is always the most significant
23212 word, even in little-endian mode. This does not match the usual subreg
23213 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23214 the appropriate constituent registers "by hand" in little-endian mode.
23216 Note we do not need to check for destructive overlap here since TDmode
23217 can only reside in even/odd register pairs. */
23218 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23223 for (i = 0; i < nregs; i++)
23225 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23226 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23228 p_src = simplify_gen_subreg (reg_mode, src, mode,
23229 i * reg_mode_size);
23231 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23232 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23234 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23235 i * reg_mode_size);
23237 emit_insn (gen_rtx_SET (p_dst, p_src));
23243 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23245 /* Move register range backwards, if we might have destructive
23248 for (i = nregs - 1; i >= 0; i--)
23249 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23250 i * reg_mode_size),
23251 simplify_gen_subreg (reg_mode, src, mode,
23252 i * reg_mode_size)));
23258 bool used_update = false;
23259 rtx restore_basereg = NULL_RTX;
23261 if (MEM_P (src) && INT_REGNO_P (reg))
23265 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23266 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23269 breg = XEXP (XEXP (src, 0), 0);
23270 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23271 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23272 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23273 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23274 src = replace_equiv_address (src, breg);
23276 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23278 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23280 rtx basereg = XEXP (XEXP (src, 0), 0);
23283 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23284 emit_insn (gen_rtx_SET (ndst,
23285 gen_rtx_MEM (reg_mode,
23287 used_update = true;
23290 emit_insn (gen_rtx_SET (basereg,
23291 XEXP (XEXP (src, 0), 1)));
23292 src = replace_equiv_address (src, basereg);
23296 rtx basereg = gen_rtx_REG (Pmode, reg);
23297 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23298 src = replace_equiv_address (src, basereg);
23302 breg = XEXP (src, 0);
23303 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23304 breg = XEXP (breg, 0);
23306 /* If the base register we are using to address memory is
23307 also a destination reg, then change that register last. */
23309 && REGNO (breg) >= REGNO (dst)
23310 && REGNO (breg) < REGNO (dst) + nregs)
23311 j = REGNO (breg) - REGNO (dst);
23313 else if (MEM_P (dst) && INT_REGNO_P (reg))
23317 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23318 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23321 breg = XEXP (XEXP (dst, 0), 0);
23322 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23323 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23324 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23326 /* We have to update the breg before doing the store.
23327 Use store with update, if available. */
23331 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23332 emit_insn (TARGET_32BIT
23333 ? (TARGET_POWERPC64
23334 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23335 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
23336 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23337 used_update = true;
23340 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23341 dst = replace_equiv_address (dst, breg);
23343 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23344 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23346 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23348 rtx basereg = XEXP (XEXP (dst, 0), 0);
23351 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23352 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23355 used_update = true;
23358 emit_insn (gen_rtx_SET (basereg,
23359 XEXP (XEXP (dst, 0), 1)));
23360 dst = replace_equiv_address (dst, basereg);
23364 rtx basereg = XEXP (XEXP (dst, 0), 0);
23365 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23366 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23368 && REG_P (offsetreg)
23369 && REGNO (basereg) != REGNO (offsetreg));
23370 if (REGNO (basereg) == 0)
23372 rtx tmp = offsetreg;
23373 offsetreg = basereg;
23376 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23377 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23378 dst = replace_equiv_address (dst, basereg);
23381 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23382 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23385 for (i = 0; i < nregs; i++)
23387 /* Calculate index to next subword. */
23392 /* If compiler already emitted move of first word by
23393 store with update, no need to do anything. */
23394 if (j == 0 && used_update)
23397 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23398 j * reg_mode_size),
23399 simplify_gen_subreg (reg_mode, src, mode,
23400 j * reg_mode_size)));
23402 if (restore_basereg != NULL_RTX)
23403 emit_insn (restore_basereg);
23408 /* This page contains routines that are used to determine what the
23409 function prologue and epilogue code will do and write them out. */
23411 /* Determine whether the REG is really used. */
23414 save_reg_p (int reg)
23416 /* We need to mark the PIC offset register live for the same conditions
23417 as it is set up, or otherwise it won't be saved before we clobber it. */
23419 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23421 /* When calling eh_return, we must return true for all the cases
23422 where conditional_register_usage marks the PIC offset reg
23424 if (TARGET_TOC && TARGET_MINIMAL_TOC
23425 && (crtl->calls_eh_return
23426 || df_regs_ever_live_p (reg)
23427 || !constant_pool_empty_p ()))
23430 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
23435 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23438 /* Return the first fixed-point register that is required to be
23439 saved. 32 if none. */
23442 first_reg_to_save (void)
23446 /* Find lowest numbered live register. */
23447 for (first_reg = 13; first_reg <= 31; first_reg++)
23448 if (save_reg_p (first_reg))
23453 && crtl->uses_pic_offset_table
23454 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
23455 return RS6000_PIC_OFFSET_TABLE_REGNUM;
23461 /* Similar, for FP regs. */
23464 first_fp_reg_to_save (void)
23468 /* Find lowest numbered live register. */
23469 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23470 if (save_reg_p (first_reg))
23476 /* Similar, for AltiVec regs. */
23479 first_altivec_reg_to_save (void)
23483 /* Stack frame remains as is unless we are in AltiVec ABI. */
23484 if (! TARGET_ALTIVEC_ABI)
23485 return LAST_ALTIVEC_REGNO + 1;
23487 /* On Darwin, the unwind routines are compiled without
23488 TARGET_ALTIVEC, and use save_world to save/restore the
23489 altivec registers when necessary. */
23490 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23491 && ! TARGET_ALTIVEC)
23492 return FIRST_ALTIVEC_REGNO + 20;
23494 /* Find lowest numbered live register. */
23495 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23496 if (save_reg_p (i))
23502 /* Return a 32-bit mask of the AltiVec registers we need to set in
23503 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23504 the 32-bit word is 0. */
23506 static unsigned int
23507 compute_vrsave_mask (void)
23509 unsigned int i, mask = 0;
23511 /* On Darwin, the unwind routines are compiled without
23512 TARGET_ALTIVEC, and use save_world to save/restore the
23513 call-saved altivec registers when necessary. */
23514 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23515 && ! TARGET_ALTIVEC)
23518 /* First, find out if we use _any_ altivec registers. */
23519 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23520 if (df_regs_ever_live_p (i))
23521 mask |= ALTIVEC_REG_BIT (i);
23526 /* Next, remove the argument registers from the set. These must
23527 be in the VRSAVE mask set by the caller, so we don't need to add
23528 them in again. More importantly, the mask we compute here is
23529 used to generate CLOBBERs in the set_vrsave insn, and we do not
23530 wish the argument registers to die. */
23531 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23532 mask &= ~ALTIVEC_REG_BIT (i);
23534 /* Similarly, remove the return value from the set. */
23537 diddle_return_value (is_altivec_return_reg, &yes);
23539 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23545 /* For a very restricted set of circumstances, we can cut down the
23546 size of prologues/epilogues by calling our own save/restore-the-world
23550 compute_save_world_info (rs6000_stack_t *info)
23552 info->world_save_p = 1;
23554 = (WORLD_SAVE_P (info)
23555 && DEFAULT_ABI == ABI_DARWIN
23556 && !cfun->has_nonlocal_label
23557 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23558 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23559 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23560 && info->cr_save_p);
23562 /* This will not work in conjunction with sibcalls. Make sure there
23563 are none. (This check is expensive, but seldom executed.) */
23564 if (WORLD_SAVE_P (info))
23567 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23568 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23570 info->world_save_p = 0;
23575 if (WORLD_SAVE_P (info))
23577 /* Even if we're not touching VRsave, make sure there's room on the
23578 stack for it, if it looks like we're calling SAVE_WORLD, which
23579 will attempt to save it. */
23580 info->vrsave_size = 4;
23582 /* If we are going to save the world, we need to save the link register too. */
23583 info->lr_save_p = 1;
23585 /* "Save" the VRsave register too if we're saving the world. */
23586 if (info->vrsave_mask == 0)
23587 info->vrsave_mask = compute_vrsave_mask ();
23589 /* Because the Darwin register save/restore routines only handle
23590 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23592 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23593 && (info->first_altivec_reg_save
23594 >= FIRST_SAVED_ALTIVEC_REGNO));
23602 is_altivec_return_reg (rtx reg, void *xyes)
23604 bool *yes = (bool *) xyes;
23605 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23610 /* Return whether REG is a global user reg or has been specifed by
23611 -ffixed-REG. We should not restore these, and so cannot use
23612 lmw or out-of-line restore functions if there are any. We also
23613 can't save them (well, emit frame notes for them), because frame
23614 unwinding during exception handling will restore saved registers. */
23617 fixed_reg_p (int reg)
23619 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23620 backend sets it, overriding anything the user might have given. */
23621 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23622 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23623 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23624 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23627 return fixed_regs[reg];
23630 /* Determine the strategy for savings/restoring registers. */
23633 SAVE_MULTIPLE = 0x1,
23634 SAVE_INLINE_GPRS = 0x2,
23635 SAVE_INLINE_FPRS = 0x4,
23636 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23637 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23638 SAVE_INLINE_VRS = 0x20,
23639 REST_MULTIPLE = 0x100,
23640 REST_INLINE_GPRS = 0x200,
23641 REST_INLINE_FPRS = 0x400,
23642 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23643 REST_INLINE_VRS = 0x1000
23647 rs6000_savres_strategy (rs6000_stack_t *info,
23648 bool using_static_chain_p)
23652 /* Select between in-line and out-of-line save and restore of regs.
23653 First, all the obvious cases where we don't use out-of-line. */
23654 if (crtl->calls_eh_return
23655 || cfun->machine->ra_need_lr)
23656 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23657 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23658 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23660 if (info->first_gp_reg_save == 32)
23661 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23663 if (info->first_fp_reg_save == 64)
23664 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23666 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23667 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23669 /* Define cutoff for using out-of-line functions to save registers. */
23670 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23672 if (!optimize_size)
23674 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23675 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23676 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23680 /* Prefer out-of-line restore if it will exit. */
23681 if (info->first_fp_reg_save > 61)
23682 strategy |= SAVE_INLINE_FPRS;
23683 if (info->first_gp_reg_save > 29)
23685 if (info->first_fp_reg_save == 64)
23686 strategy |= SAVE_INLINE_GPRS;
23688 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23690 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
23691 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23694 else if (DEFAULT_ABI == ABI_DARWIN)
23696 if (info->first_fp_reg_save > 60)
23697 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23698 if (info->first_gp_reg_save > 29)
23699 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23700 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23704 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
23705 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
23706 || info->first_fp_reg_save > 61)
23707 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23708 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23709 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23712 /* Don't bother to try to save things out-of-line if r11 is occupied
23713 by the static chain. It would require too much fiddling and the
23714 static chain is rarely used anyway. FPRs are saved w.r.t the stack
23715 pointer on Darwin, and AIX uses r1 or r12. */
23716 if (using_static_chain_p
23717 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
23718 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
23720 | SAVE_INLINE_VRS);
23722 /* Don't ever restore fixed regs. That means we can't use the
23723 out-of-line register restore functions if a fixed reg is in the
23724 range of regs restored. */
23725 if (!(strategy & REST_INLINE_FPRS))
23726 for (int i = info->first_fp_reg_save; i < 64; i++)
23729 strategy |= REST_INLINE_FPRS;
23733 /* We can only use the out-of-line routines to restore fprs if we've
23734 saved all the registers from first_fp_reg_save in the prologue.
23735 Otherwise, we risk loading garbage. Of course, if we have saved
23736 out-of-line then we know we haven't skipped any fprs. */
23737 if ((strategy & SAVE_INLINE_FPRS)
23738 && !(strategy & REST_INLINE_FPRS))
23739 for (int i = info->first_fp_reg_save; i < 64; i++)
23740 if (!save_reg_p (i))
23742 strategy |= REST_INLINE_FPRS;
23746 /* Similarly, for altivec regs. */
23747 if (!(strategy & REST_INLINE_VRS))
23748 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23751 strategy |= REST_INLINE_VRS;
23755 if ((strategy & SAVE_INLINE_VRS)
23756 && !(strategy & REST_INLINE_VRS))
23757 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23758 if (!save_reg_p (i))
23760 strategy |= REST_INLINE_VRS;
23764 /* info->lr_save_p isn't yet set if the only reason lr needs to be
23765 saved is an out-of-line save or restore. Set up the value for
23766 the next test (excluding out-of-line gprs). */
23767 bool lr_save_p = (info->lr_save_p
23768 || !(strategy & SAVE_INLINE_FPRS)
23769 || !(strategy & SAVE_INLINE_VRS)
23770 || !(strategy & REST_INLINE_FPRS)
23771 || !(strategy & REST_INLINE_VRS));
23773 if (TARGET_MULTIPLE
23774 && !TARGET_POWERPC64
23775 && info->first_gp_reg_save < 31
23776 && !(flag_shrink_wrap
23777 && flag_shrink_wrap_separate
23778 && optimize_function_for_speed_p (cfun)))
23781 for (int i = info->first_gp_reg_save; i < 32; i++)
23782 if (save_reg_p (i))
23786 /* Don't use store multiple if only one reg needs to be
23787 saved. This can occur for example when the ABI_V4 pic reg
23788 (r30) needs to be saved to make calls, but r31 is not
23790 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23793 /* Prefer store multiple for saves over out-of-line
23794 routines, since the store-multiple instruction will
23795 always be smaller. */
23796 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
23798 /* The situation is more complicated with load multiple.
23799 We'd prefer to use the out-of-line routines for restores,
23800 since the "exit" out-of-line routines can handle the
23801 restore of LR and the frame teardown. However if doesn't
23802 make sense to use the out-of-line routine if that is the
23803 only reason we'd need to save LR, and we can't use the
23804 "exit" out-of-line gpr restore if we have saved some
23805 fprs; In those cases it is advantageous to use load
23806 multiple when available. */
23807 if (info->first_fp_reg_save != 64 || !lr_save_p)
23808 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
23812 /* Using the "exit" out-of-line routine does not improve code size
23813 if using it would require lr to be saved and if only saving one
23815 else if (!lr_save_p && info->first_gp_reg_save > 29)
23816 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23818 /* Don't ever restore fixed regs. */
23819 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23820 for (int i = info->first_gp_reg_save; i < 32; i++)
23821 if (fixed_reg_p (i))
23823 strategy |= REST_INLINE_GPRS;
23824 strategy &= ~REST_MULTIPLE;
23828 /* We can only use load multiple or the out-of-line routines to
23829 restore gprs if we've saved all the registers from
23830 first_gp_reg_save. Otherwise, we risk loading garbage.
23831 Of course, if we have saved out-of-line or used stmw then we know
23832 we haven't skipped any gprs. */
23833 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
23834 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23835 for (int i = info->first_gp_reg_save; i < 32; i++)
23836 if (!save_reg_p (i))
23838 strategy |= REST_INLINE_GPRS;
23839 strategy &= ~REST_MULTIPLE;
23843 if (TARGET_ELF && TARGET_64BIT)
23845 if (!(strategy & SAVE_INLINE_FPRS))
23846 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
23847 else if (!(strategy & SAVE_INLINE_GPRS)
23848 && info->first_fp_reg_save == 64)
23849 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
23851 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
23852 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
23854 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
23855 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
23860 /* Calculate the stack information for the current function. This is
23861 complicated by having two separate calling sequences, the AIX calling
23862 sequence and the V.4 calling sequence.
23864 AIX (and Darwin/Mac OS X) stack frames look like:
23866 SP----> +---------------------------------------+
23867 | back chain to caller | 0 0
23868 +---------------------------------------+
23869 | saved CR | 4 8 (8-11)
23870 +---------------------------------------+
23872 +---------------------------------------+
23873 | reserved for compilers | 12 24
23874 +---------------------------------------+
23875 | reserved for binders | 16 32
23876 +---------------------------------------+
23877 | saved TOC pointer | 20 40
23878 +---------------------------------------+
23879 | Parameter save area (+padding*) (P) | 24 48
23880 +---------------------------------------+
23881 | Alloca space (A) | 24+P etc.
23882 +---------------------------------------+
23883 | Local variable space (L) | 24+P+A
23884 +---------------------------------------+
23885 | Float/int conversion temporary (X) | 24+P+A+L
23886 +---------------------------------------+
23887 | Save area for AltiVec registers (W) | 24+P+A+L+X
23888 +---------------------------------------+
23889 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
23890 +---------------------------------------+
23891 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
23892 +---------------------------------------+
23893 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
23894 +---------------------------------------+
23895 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
23896 +---------------------------------------+
23897 old SP->| back chain to caller's caller |
23898 +---------------------------------------+
23900 * If the alloca area is present, the parameter save area is
23901 padded so that the former starts 16-byte aligned.
23903 The required alignment for AIX configurations is two words (i.e., 8
23906 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
23908 SP----> +---------------------------------------+
23909 | Back chain to caller | 0
23910 +---------------------------------------+
23911 | Save area for CR | 8
23912 +---------------------------------------+
23914 +---------------------------------------+
23915 | Saved TOC pointer | 24
23916 +---------------------------------------+
23917 | Parameter save area (+padding*) (P) | 32
23918 +---------------------------------------+
23919 | Alloca space (A) | 32+P
23920 +---------------------------------------+
23921 | Local variable space (L) | 32+P+A
23922 +---------------------------------------+
23923 | Save area for AltiVec registers (W) | 32+P+A+L
23924 +---------------------------------------+
23925 | AltiVec alignment padding (Y) | 32+P+A+L+W
23926 +---------------------------------------+
23927 | Save area for GP registers (G) | 32+P+A+L+W+Y
23928 +---------------------------------------+
23929 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
23930 +---------------------------------------+
23931 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
23932 +---------------------------------------+
23934 * If the alloca area is present, the parameter save area is
23935 padded so that the former starts 16-byte aligned.
23937 V.4 stack frames look like:
23939 SP----> +---------------------------------------+
23940 | back chain to caller | 0
23941 +---------------------------------------+
23942 | caller's saved LR | 4
23943 +---------------------------------------+
23944 | Parameter save area (+padding*) (P) | 8
23945 +---------------------------------------+
23946 | Alloca space (A) | 8+P
23947 +---------------------------------------+
23948 | Varargs save area (V) | 8+P+A
23949 +---------------------------------------+
23950 | Local variable space (L) | 8+P+A+V
23951 +---------------------------------------+
23952 | Float/int conversion temporary (X) | 8+P+A+V+L
23953 +---------------------------------------+
23954 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
23955 +---------------------------------------+
23956 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
23957 +---------------------------------------+
23958 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
23959 +---------------------------------------+
23960 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
23961 +---------------------------------------+
23962 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
23963 +---------------------------------------+
23964 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
23965 +---------------------------------------+
23966 old SP->| back chain to caller's caller |
23967 +---------------------------------------+
23969 * If the alloca area is present and the required alignment is
23970 16 bytes, the parameter save area is padded so that the
23971 alloca area starts 16-byte aligned.
23973 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
23974 given. (But note below and in sysv4.h that we require only 8 and
23975 may round up the size of our stack frame anyways. The historical
23976 reason is early versions of powerpc-linux which didn't properly
23977 align the stack at program startup. A happy side-effect is that
23978 -mno-eabi libraries can be used with -meabi programs.)
23980 The EABI configuration defaults to the V.4 layout. However,
23981 the stack alignment requirements may differ. If -mno-eabi is not
23982 given, the required stack alignment is 8 bytes; if -mno-eabi is
23983 given, the required alignment is 16 bytes. (But see V.4 comment
23986 #ifndef ABI_STACK_BOUNDARY
23987 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
23990 static rs6000_stack_t *
23991 rs6000_stack_info (void)
23993 /* We should never be called for thunks, we are not set up for that. */
23994 gcc_assert (!cfun->is_thunk);
23996 rs6000_stack_t *info = &stack_info;
23997 int reg_size = TARGET_32BIT ? 4 : 8;
24002 HOST_WIDE_INT non_fixed_size;
24003 bool using_static_chain_p;
24005 if (reload_completed && info->reload_completed)
24008 memset (info, 0, sizeof (*info));
24009 info->reload_completed = reload_completed;
24011 /* Select which calling sequence. */
24012 info->abi = DEFAULT_ABI;
24014 /* Calculate which registers need to be saved & save area size. */
24015 info->first_gp_reg_save = first_reg_to_save ();
24016 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24017 even if it currently looks like we won't. Reload may need it to
24018 get at a constant; if so, it will have already created a constant
24019 pool entry for it. */
24020 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24021 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24022 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24023 && crtl->uses_const_pool
24024 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24025 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24027 first_gp = info->first_gp_reg_save;
24029 info->gp_size = reg_size * (32 - first_gp);
24031 info->first_fp_reg_save = first_fp_reg_to_save ();
24032 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24034 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24035 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24036 - info->first_altivec_reg_save);
24038 /* Does this function call anything? */
24039 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24041 /* Determine if we need to save the condition code registers. */
24042 if (save_reg_p (CR2_REGNO)
24043 || save_reg_p (CR3_REGNO)
24044 || save_reg_p (CR4_REGNO))
24046 info->cr_save_p = 1;
24047 if (DEFAULT_ABI == ABI_V4)
24048 info->cr_size = reg_size;
24051 /* If the current function calls __builtin_eh_return, then we need
24052 to allocate stack space for registers that will hold data for
24053 the exception handler. */
24054 if (crtl->calls_eh_return)
24057 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24060 ehrd_size = i * UNITS_PER_WORD;
24065 /* In the ELFv2 ABI, we also need to allocate space for separate
24066 CR field save areas if the function calls __builtin_eh_return. */
24067 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24069 /* This hard-codes that we have three call-saved CR fields. */
24070 ehcr_size = 3 * reg_size;
24071 /* We do *not* use the regular CR save mechanism. */
24072 info->cr_save_p = 0;
24077 /* Determine various sizes. */
24078 info->reg_size = reg_size;
24079 info->fixed_size = RS6000_SAVE_AREA;
24080 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24081 if (cfun->calls_alloca)
24083 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24084 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24086 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24087 TARGET_ALTIVEC ? 16 : 8);
24088 if (FRAME_GROWS_DOWNWARD)
24090 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24091 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24092 - (info->fixed_size + info->vars_size + info->parm_size);
24094 if (TARGET_ALTIVEC_ABI)
24095 info->vrsave_mask = compute_vrsave_mask ();
24097 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24098 info->vrsave_size = 4;
24100 compute_save_world_info (info);
24102 /* Calculate the offsets. */
24103 switch (DEFAULT_ABI)
24107 gcc_unreachable ();
24112 info->fp_save_offset = -info->fp_size;
24113 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24115 if (TARGET_ALTIVEC_ABI)
24117 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24119 /* Align stack so vector save area is on a quadword boundary.
24120 The padding goes above the vectors. */
24121 if (info->altivec_size != 0)
24122 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24124 info->altivec_save_offset = info->vrsave_save_offset
24125 - info->altivec_padding_size
24126 - info->altivec_size;
24127 gcc_assert (info->altivec_size == 0
24128 || info->altivec_save_offset % 16 == 0);
24130 /* Adjust for AltiVec case. */
24131 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24134 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24136 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24137 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24138 info->lr_save_offset = 2*reg_size;
24142 info->fp_save_offset = -info->fp_size;
24143 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24144 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24146 if (TARGET_ALTIVEC_ABI)
24148 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24150 /* Align stack so vector save area is on a quadword boundary. */
24151 if (info->altivec_size != 0)
24152 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24154 info->altivec_save_offset = info->vrsave_save_offset
24155 - info->altivec_padding_size
24156 - info->altivec_size;
24158 /* Adjust for AltiVec case. */
24159 info->ehrd_offset = info->altivec_save_offset;
24162 info->ehrd_offset = info->cr_save_offset;
24164 info->ehrd_offset -= ehrd_size;
24165 info->lr_save_offset = reg_size;
24168 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24169 info->save_size = RS6000_ALIGN (info->fp_size
24171 + info->altivec_size
24172 + info->altivec_padding_size
24176 + info->vrsave_size,
24179 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24181 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24182 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24184 /* Determine if we need to save the link register. */
24186 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24188 && !TARGET_PROFILE_KERNEL)
24189 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24190 #ifdef TARGET_RELOCATABLE
24191 || (DEFAULT_ABI == ABI_V4
24192 && (TARGET_RELOCATABLE || flag_pic > 1)
24193 && !constant_pool_empty_p ())
24195 || rs6000_ra_ever_killed ())
24196 info->lr_save_p = 1;
24198 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24199 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24200 && call_used_regs[STATIC_CHAIN_REGNUM]);
24201 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24203 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24204 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24205 || !(info->savres_strategy & SAVE_INLINE_VRS)
24206 || !(info->savres_strategy & REST_INLINE_GPRS)
24207 || !(info->savres_strategy & REST_INLINE_FPRS)
24208 || !(info->savres_strategy & REST_INLINE_VRS))
24209 info->lr_save_p = 1;
24211 if (info->lr_save_p)
24212 df_set_regs_ever_live (LR_REGNO, true);
24214 /* Determine if we need to allocate any stack frame:
24216 For AIX we need to push the stack if a frame pointer is needed
24217 (because the stack might be dynamically adjusted), if we are
24218 debugging, if we make calls, or if the sum of fp_save, gp_save,
24219 and local variables are more than the space needed to save all
24220 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24221 + 18*8 = 288 (GPR13 reserved).
24223 For V.4 we don't have the stack cushion that AIX uses, but assume
24224 that the debugger can handle stackless frames. */
24229 else if (DEFAULT_ABI == ABI_V4)
24230 info->push_p = non_fixed_size != 0;
24232 else if (frame_pointer_needed)
24235 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24239 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24245 debug_stack_info (rs6000_stack_t *info)
24247 const char *abi_string;
24250 info = rs6000_stack_info ();
24252 fprintf (stderr, "\nStack information for function %s:\n",
24253 ((current_function_decl && DECL_NAME (current_function_decl))
24254 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24259 default: abi_string = "Unknown"; break;
24260 case ABI_NONE: abi_string = "NONE"; break;
24261 case ABI_AIX: abi_string = "AIX"; break;
24262 case ABI_ELFv2: abi_string = "ELFv2"; break;
24263 case ABI_DARWIN: abi_string = "Darwin"; break;
24264 case ABI_V4: abi_string = "V.4"; break;
24267 fprintf (stderr, "\tABI = %5s\n", abi_string);
24269 if (TARGET_ALTIVEC_ABI)
24270 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24272 if (info->first_gp_reg_save != 32)
24273 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24275 if (info->first_fp_reg_save != 64)
24276 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24278 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24279 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24280 info->first_altivec_reg_save);
24282 if (info->lr_save_p)
24283 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24285 if (info->cr_save_p)
24286 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24288 if (info->vrsave_mask)
24289 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24292 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24295 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24298 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24301 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24303 if (info->altivec_size)
24304 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24305 info->altivec_save_offset);
24307 if (info->vrsave_size)
24308 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24309 info->vrsave_save_offset);
24311 if (info->lr_save_p)
24312 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24314 if (info->cr_save_p)
24315 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24317 if (info->varargs_save_offset)
24318 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24320 if (info->total_size)
24321 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24324 if (info->vars_size)
24325 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24328 if (info->parm_size)
24329 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24331 if (info->fixed_size)
24332 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24335 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24338 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24340 if (info->altivec_size)
24341 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24343 if (info->vrsave_size)
24344 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24346 if (info->altivec_padding_size)
24347 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24348 info->altivec_padding_size);
24351 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24353 if (info->save_size)
24354 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24356 if (info->reg_size != 4)
24357 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24359 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24361 fprintf (stderr, "\n");
24365 rs6000_return_addr (int count, rtx frame)
24367 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24368 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24370 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24372 cfun->machine->ra_needs_full_frame = 1;
24375 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24376 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24377 frame = stack_pointer_rtx;
24378 rtx prev_frame_addr = memory_address (Pmode, frame);
24379 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24380 rtx lr_save_off = plus_constant (Pmode,
24381 prev_frame, RETURN_ADDRESS_OFFSET);
24382 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24383 return gen_rtx_MEM (Pmode, lr_save_addr);
24386 cfun->machine->ra_need_lr = 1;
24387 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24390 /* Say whether a function is a candidate for sibcall handling or not. */
24393 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24398 fntype = TREE_TYPE (decl);
24400 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24402 /* We can't do it if the called function has more vector parameters
24403 than the current function; there's nowhere to put the VRsave code. */
24404 if (TARGET_ALTIVEC_ABI
24405 && TARGET_ALTIVEC_VRSAVE
24406 && !(decl && decl == current_function_decl))
24408 function_args_iterator args_iter;
24412 /* Functions with vector parameters are required to have a
24413 prototype, so the argument type info must be available
24415 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24416 if (TREE_CODE (type) == VECTOR_TYPE
24417 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24420 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24421 if (TREE_CODE (type) == VECTOR_TYPE
24422 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24429 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24430 functions, because the callee may have a different TOC pointer to
24431 the caller and there's no way to ensure we restore the TOC when
24432 we return. With the secure-plt SYSV ABI we can't make non-local
24433 calls when -fpic/PIC because the plt call stubs use r30. */
24434 if (DEFAULT_ABI == ABI_DARWIN
24435 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24437 && !DECL_EXTERNAL (decl)
24438 && !DECL_WEAK (decl)
24439 && (*targetm.binds_local_p) (decl))
24440 || (DEFAULT_ABI == ABI_V4
24441 && (!TARGET_SECURE_PLT
24444 && (*targetm.binds_local_p) (decl)))))
24446 tree attr_list = TYPE_ATTRIBUTES (fntype);
24448 if (!lookup_attribute ("longcall", attr_list)
24449 || lookup_attribute ("shortcall", attr_list))
24457 rs6000_ra_ever_killed (void)
24463 if (cfun->is_thunk)
24466 if (cfun->machine->lr_save_state)
24467 return cfun->machine->lr_save_state - 1;
24469 /* regs_ever_live has LR marked as used if any sibcalls are present,
24470 but this should not force saving and restoring in the
24471 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24472 clobbers LR, so that is inappropriate. */
24474 /* Also, the prologue can generate a store into LR that
24475 doesn't really count, like this:
24478 bcl to set PIC register
24482 When we're called from the epilogue, we need to avoid counting
24483 this as a store. */
24485 push_topmost_sequence ();
24486 top = get_insns ();
24487 pop_topmost_sequence ();
24488 reg = gen_rtx_REG (Pmode, LR_REGNO);
24490 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24496 if (!SIBLING_CALL_P (insn))
24499 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24501 else if (set_of (reg, insn) != NULL_RTX
24502 && !prologue_epilogue_contains (insn))
24509 /* Emit instructions needed to load the TOC register.
24510 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24511 a constant pool; or for SVR4 -fpic. */
24514 rs6000_emit_load_toc_table (int fromprolog)
24517 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24519 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24522 rtx lab, tmp1, tmp2, got;
24524 lab = gen_label_rtx ();
24525 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24526 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24529 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24533 got = rs6000_got_sym ();
24534 tmp1 = tmp2 = dest;
24537 tmp1 = gen_reg_rtx (Pmode);
24538 tmp2 = gen_reg_rtx (Pmode);
24540 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24541 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24542 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24543 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24545 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24547 emit_insn (gen_load_toc_v4_pic_si ());
24548 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24550 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24553 rtx temp0 = (fromprolog
24554 ? gen_rtx_REG (Pmode, 0)
24555 : gen_reg_rtx (Pmode));
24561 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24562 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24564 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24565 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24567 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24568 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24569 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24575 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24577 lab = gen_label_rtx ();
24578 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24579 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24580 if (TARGET_LINK_STACK)
24581 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24582 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24584 emit_insn (gen_addsi3 (dest, temp0, dest));
24586 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24588 /* This is for AIX code running in non-PIC ELF32. */
24589 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24592 emit_insn (gen_elf_high (dest, realsym));
24593 emit_insn (gen_elf_low (dest, dest, realsym));
24597 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24600 emit_insn (gen_load_toc_aix_si (dest));
24602 emit_insn (gen_load_toc_aix_di (dest));
24606 /* Emit instructions to restore the link register after determining where
24607 its value has been stored. */
24610 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24612 rs6000_stack_t *info = rs6000_stack_info ();
24615 operands[0] = source;
24616 operands[1] = scratch;
24618 if (info->lr_save_p)
24620 rtx frame_rtx = stack_pointer_rtx;
24621 HOST_WIDE_INT sp_offset = 0;
24624 if (frame_pointer_needed
24625 || cfun->calls_alloca
24626 || info->total_size > 32767)
24628 tmp = gen_frame_mem (Pmode, frame_rtx);
24629 emit_move_insn (operands[1], tmp);
24630 frame_rtx = operands[1];
24632 else if (info->push_p)
24633 sp_offset = info->total_size;
24635 tmp = plus_constant (Pmode, frame_rtx,
24636 info->lr_save_offset + sp_offset);
24637 tmp = gen_frame_mem (Pmode, tmp);
24638 emit_move_insn (tmp, operands[0]);
24641 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24643 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24644 state of lr_save_p so any change from here on would be a bug. In
24645 particular, stop rs6000_ra_ever_killed from considering the SET
24646 of lr we may have added just above. */
24647 cfun->machine->lr_save_state = info->lr_save_p + 1;
24650 static GTY(()) alias_set_type set = -1;
24653 get_TOC_alias_set (void)
24656 set = new_alias_set ();
24660 /* This returns nonzero if the current function uses the TOC. This is
24661 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24662 is generated by the ABI_V4 load_toc_* patterns.
24663 Return 2 instead of 1 if the load_toc_* pattern is in the function
24664 partition that doesn't start the function. */
24672 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24676 rtx pat = PATTERN (insn);
24679 if (GET_CODE (pat) == PARALLEL)
24680 for (i = 0; i < XVECLEN (pat, 0); i++)
24682 rtx sub = XVECEXP (pat, 0, i);
24683 if (GET_CODE (sub) == USE)
24685 sub = XEXP (sub, 0);
24686 if (GET_CODE (sub) == UNSPEC
24687 && XINT (sub, 1) == UNSPEC_TOC)
24692 else if (crtl->has_bb_partition
24694 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
24702 create_TOC_reference (rtx symbol, rtx largetoc_reg)
24704 rtx tocrel, tocreg, hi;
24706 if (TARGET_DEBUG_ADDR)
24708 if (GET_CODE (symbol) == SYMBOL_REF)
24709 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
24713 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
24714 GET_RTX_NAME (GET_CODE (symbol)));
24715 debug_rtx (symbol);
24719 if (!can_create_pseudo_p ())
24720 df_set_regs_ever_live (TOC_REGISTER, true);
24722 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
24723 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
24724 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
24727 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
24728 if (largetoc_reg != NULL)
24730 emit_move_insn (largetoc_reg, hi);
24733 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
24736 /* Issue assembly directives that create a reference to the given DWARF
24737 FRAME_TABLE_LABEL from the current function section. */
24739 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
24741 fprintf (asm_out_file, "\t.ref %s\n",
24742 (* targetm.strip_name_encoding) (frame_table_label));
24745 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
24746 and the change to the stack pointer. */
24749 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
24756 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
24757 if (hard_frame_needed)
24758 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
24759 if (!(REGNO (fp) == STACK_POINTER_REGNUM
24760 || (hard_frame_needed
24761 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
24764 p = rtvec_alloc (i);
24767 rtx mem = gen_frame_mem (BLKmode, regs[i]);
24768 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
24771 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
24774 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
24775 and set the appropriate attributes for the generated insn. Return the
24776 first insn which adjusts the stack pointer or the last insn before
24777 the stack adjustment loop.
24779 SIZE_INT is used to create the CFI note for the allocation.
24781 SIZE_RTX is an rtx containing the size of the adjustment. Note that
24782 since stacks grow to lower addresses its runtime value is -SIZE_INT.
24784 ORIG_SP contains the backchain value that must be stored at *sp. */
24787 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
24791 rtx size_rtx = GEN_INT (-size_int);
24792 if (size_int > 32767)
24794 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
24795 /* Need a note here so that try_split doesn't get confused. */
24796 if (get_last_insn () == NULL_RTX)
24797 emit_note (NOTE_INSN_DELETED);
24798 insn = emit_move_insn (tmp_reg, size_rtx);
24799 try_split (PATTERN (insn), insn, 0);
24800 size_rtx = tmp_reg;
24803 if (Pmode == SImode)
24804 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
24809 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
24813 rtx par = PATTERN (insn);
24814 gcc_assert (GET_CODE (par) == PARALLEL);
24815 rtx set = XVECEXP (par, 0, 0);
24816 gcc_assert (GET_CODE (set) == SET);
24817 rtx mem = SET_DEST (set);
24818 gcc_assert (MEM_P (mem));
24819 MEM_NOTRAP_P (mem) = 1;
24820 set_mem_alias_set (mem, get_frame_alias_set ());
24822 RTX_FRAME_RELATED_P (insn) = 1;
24823 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
24824 gen_rtx_SET (stack_pointer_rtx,
24825 gen_rtx_PLUS (Pmode,
24827 GEN_INT (-size_int))));
24829 /* Emit a blockage to ensure the allocation/probing insns are
24830 not optimized, combined, removed, etc. Add REG_STACK_CHECK
24831 note for similar reasons. */
24832 if (flag_stack_clash_protection)
24834 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
24835 emit_insn (gen_blockage ());
24841 static HOST_WIDE_INT
24842 get_stack_clash_protection_probe_interval (void)
24844 return (HOST_WIDE_INT_1U
24845 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
24848 static HOST_WIDE_INT
24849 get_stack_clash_protection_guard_size (void)
24851 return (HOST_WIDE_INT_1U
24852 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
24855 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
24856 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
24858 COPY_REG, if non-null, should contain a copy of the original
24859 stack pointer at exit from this function.
24861 This is subtly different than the Ada probing in that it tries hard to
24862 prevent attacks that jump the stack guard. Thus it is never allowed to
24863 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
24864 space without a suitable probe. */
24866 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
24869 rtx orig_sp = copy_reg;
24871 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
24873 /* Round the size down to a multiple of PROBE_INTERVAL. */
24874 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
24876 /* If explicitly requested,
24877 or the rounded size is not the same as the original size
24878 or the the rounded size is greater than a page,
24879 then we will need a copy of the original stack pointer. */
24880 if (rounded_size != orig_size
24881 || rounded_size > probe_interval
24884 /* If the caller did not request a copy of the incoming stack
24885 pointer, then we use r0 to hold the copy. */
24887 orig_sp = gen_rtx_REG (Pmode, 0);
24888 emit_move_insn (orig_sp, stack_pointer_rtx);
24891 /* There's three cases here.
24893 One is a single probe which is the most common and most efficiently
24894 implemented as it does not have to have a copy of the original
24895 stack pointer if there are no residuals.
24897 Second is unrolled allocation/probes which we use if there's just
24898 a few of them. It needs to save the original stack pointer into a
24899 temporary for use as a source register in the allocation/probe.
24901 Last is a loop. This is the most uncommon case and least efficient. */
24902 rtx_insn *retval = NULL;
24903 if (rounded_size == probe_interval)
24905 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
24907 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
24909 else if (rounded_size <= 8 * probe_interval)
24911 /* The ABI requires using the store with update insns to allocate
24912 space and store the backchain into the stack
24914 So we save the current stack pointer into a temporary, then
24915 emit the store-with-update insns to store the saved stack pointer
24916 into the right location in each new page. */
24917 for (int i = 0; i < rounded_size; i += probe_interval)
24920 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
24922 /* Save the first stack adjustment in RETVAL. */
24927 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
24931 /* Compute the ending address. */
24933 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
24934 rtx rs = GEN_INT (-rounded_size);
24936 if (add_operand (rs, Pmode))
24937 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
24940 emit_move_insn (end_addr, GEN_INT (-rounded_size));
24941 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
24942 stack_pointer_rtx));
24943 /* Describe the effect of INSN to the CFI engine. */
24944 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
24945 gen_rtx_SET (end_addr,
24946 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
24949 RTX_FRAME_RELATED_P (insn) = 1;
24951 /* Emit the loop. */
24953 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
24954 stack_pointer_rtx, orig_sp,
24957 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
24958 stack_pointer_rtx, orig_sp,
24960 RTX_FRAME_RELATED_P (retval) = 1;
24961 /* Describe the effect of INSN to the CFI engine. */
24962 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
24963 gen_rtx_SET (stack_pointer_rtx, end_addr));
24965 /* Emit a blockage to ensure the allocation/probing insns are
24966 not optimized, combined, removed, etc. Other cases handle this
24967 within their call to rs6000_emit_allocate_stack_1. */
24968 emit_insn (gen_blockage ());
24970 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
24973 if (orig_size != rounded_size)
24975 /* Allocate (and implicitly probe) any residual space. */
24976 HOST_WIDE_INT residual = orig_size - rounded_size;
24978 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
24980 /* If the residual was the only allocation, then we can return the
24981 allocating insn. */
24989 /* Emit the correct code for allocating stack space, as insns.
24990 If COPY_REG, make sure a copy of the old frame is left there.
24991 The generated code may use hard register 0 as a temporary. */
24994 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
24997 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
24998 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
24999 rtx todec = gen_int_mode (-size, Pmode);
25001 if (INTVAL (todec) != -size)
25003 warning (0, "stack frame too large");
25004 emit_insn (gen_trap ());
25008 if (crtl->limit_stack)
25010 if (REG_P (stack_limit_rtx)
25011 && REGNO (stack_limit_rtx) > 1
25012 && REGNO (stack_limit_rtx) <= 31)
25015 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25018 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25020 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25022 && DEFAULT_ABI == ABI_V4
25025 rtx toload = gen_rtx_CONST (VOIDmode,
25026 gen_rtx_PLUS (Pmode,
25030 emit_insn (gen_elf_high (tmp_reg, toload));
25031 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25032 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25036 warning (0, "stack limit expression is not supported");
25039 if (flag_stack_clash_protection)
25041 if (size < get_stack_clash_protection_guard_size ())
25042 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25045 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25048 /* If we asked for a copy with an offset, then we still need add in
25050 if (copy_reg && copy_off)
25051 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25059 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25061 emit_move_insn (copy_reg, stack_reg);
25064 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25065 it now and set the alias set/attributes. The above gen_*_update
25066 calls will generate a PARALLEL with the MEM set being the first
25068 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25072 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25074 #if PROBE_INTERVAL > 32768
25075 #error Cannot use indexed addressing mode for stack probing
25078 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25079 inclusive. These are offsets from the current stack pointer. */
25082 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25084 /* See if we have a constant small number of probes to generate. If so,
25085 that's the easy case. */
25086 if (first + size <= 32768)
25090 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25091 it exceeds SIZE. If only one probe is needed, this will not
25092 generate any code. Then probe at FIRST + SIZE. */
25093 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25094 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25097 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25101 /* Otherwise, do the same as above, but in a loop. Note that we must be
25102 extra careful with variables wrapping around because we might be at
25103 the very top (or the very bottom) of the address space and we have
25104 to be able to handle this case properly; in particular, we use an
25105 equality test for the loop condition. */
25108 HOST_WIDE_INT rounded_size;
25109 rtx r12 = gen_rtx_REG (Pmode, 12);
25110 rtx r0 = gen_rtx_REG (Pmode, 0);
25112 /* Sanity check for the addressing mode we're going to use. */
25113 gcc_assert (first <= 32768);
25115 /* Step 1: round SIZE to the previous multiple of the interval. */
25117 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25120 /* Step 2: compute initial and final value of the loop counter. */
25122 /* TEST_ADDR = SP + FIRST. */
25123 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25126 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25127 if (rounded_size > 32768)
25129 emit_move_insn (r0, GEN_INT (-rounded_size));
25130 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25133 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25137 /* Step 3: the loop
25141 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25144 while (TEST_ADDR != LAST_ADDR)
25146 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25147 until it is equal to ROUNDED_SIZE. */
25150 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25152 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25155 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25156 that SIZE is equal to ROUNDED_SIZE. */
25158 if (size != rounded_size)
25159 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25163 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25164 addresses, not offsets. */
25166 static const char *
25167 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25169 static int labelno = 0;
25173 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25176 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25178 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25180 xops[1] = GEN_INT (-PROBE_INTERVAL);
25181 output_asm_insn ("addi %0,%0,%1", xops);
25183 /* Probe at TEST_ADDR. */
25184 xops[1] = gen_rtx_REG (Pmode, 0);
25185 output_asm_insn ("stw %1,0(%0)", xops);
25187 /* Test if TEST_ADDR == LAST_ADDR. */
25190 output_asm_insn ("cmpd 0,%0,%1", xops);
25192 output_asm_insn ("cmpw 0,%0,%1", xops);
25195 fputs ("\tbne 0,", asm_out_file);
25196 assemble_name_raw (asm_out_file, loop_lab);
25197 fputc ('\n', asm_out_file);
25202 /* This function is called when rs6000_frame_related is processing
25203 SETs within a PARALLEL, and returns whether the REGNO save ought to
25204 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25205 for out-of-line register save functions, store multiple, and the
25206 Darwin world_save. They may contain registers that don't really
25210 interesting_frame_related_regno (unsigned int regno)
25212 /* Saves apparently of r0 are actually saving LR. It doesn't make
25213 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25214 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25215 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25216 as frame related. */
25219 /* If we see CR2 then we are here on a Darwin world save. Saves of
25220 CR2 signify the whole CR is being saved. This is a long-standing
25221 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25222 that CR needs to be saved. */
25223 if (regno == CR2_REGNO)
25225 /* Omit frame info for any user-defined global regs. If frame info
25226 is supplied for them, frame unwinding will restore a user reg.
25227 Also omit frame info for any reg we don't need to save, as that
25228 bloats frame info and can cause problems with shrink wrapping.
25229 Since global regs won't be seen as needing to be saved, both of
25230 these conditions are covered by save_reg_p. */
25231 return save_reg_p (regno);
25234 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25235 addresses, not offsets.
25237 REG2 contains the backchain that must be stored into *sp at each allocation.
25239 This is subtly different than the Ada probing above in that it tries hard
25240 to prevent attacks that jump the stack guard. Thus, it is never allowed
25241 to allocate more than PROBE_INTERVAL bytes of stack space without a
25244 static const char *
25245 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25247 static int labelno = 0;
25251 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25253 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25255 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25257 /* This allocates and probes. */
25260 xops[2] = GEN_INT (-probe_interval);
25262 output_asm_insn ("stdu %1,%2(%0)", xops);
25264 output_asm_insn ("stwu %1,%2(%0)", xops);
25266 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25270 output_asm_insn ("cmpd 0,%0,%1", xops);
25272 output_asm_insn ("cmpw 0,%0,%1", xops);
25274 fputs ("\tbne 0,", asm_out_file);
25275 assemble_name_raw (asm_out_file, loop_lab);
25276 fputc ('\n', asm_out_file);
25281 /* Wrapper around the output_probe_stack_range routines. */
25283 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25285 if (flag_stack_clash_protection)
25286 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25288 return output_probe_stack_range_1 (reg1, reg3);
25291 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25292 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25293 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25294 deduce these equivalences by itself so it wasn't necessary to hold
25295 its hand so much. Don't be tempted to always supply d2_f_d_e with
25296 the actual cfa register, ie. r31 when we are using a hard frame
25297 pointer. That fails when saving regs off r1, and sched moves the
25298 r31 setup past the reg saves. */
25301 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25302 rtx reg2, rtx repl2)
25306 if (REGNO (reg) == STACK_POINTER_REGNUM)
25308 gcc_checking_assert (val == 0);
25312 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25315 rtx pat = PATTERN (insn);
25316 if (!repl && !reg2)
25318 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25319 if (GET_CODE (pat) == PARALLEL)
25320 for (int i = 0; i < XVECLEN (pat, 0); i++)
25321 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25323 rtx set = XVECEXP (pat, 0, i);
25325 if (!REG_P (SET_SRC (set))
25326 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25327 RTX_FRAME_RELATED_P (set) = 1;
25329 RTX_FRAME_RELATED_P (insn) = 1;
25333 /* We expect that 'pat' is either a SET or a PARALLEL containing
25334 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25335 are important so they all have to be marked RTX_FRAME_RELATED_P.
25336 Call simplify_replace_rtx on the SETs rather than the whole insn
25337 so as to leave the other stuff alone (for example USE of r12). */
25339 set_used_flags (pat);
25340 if (GET_CODE (pat) == SET)
25343 pat = simplify_replace_rtx (pat, reg, repl);
25345 pat = simplify_replace_rtx (pat, reg2, repl2);
25347 else if (GET_CODE (pat) == PARALLEL)
25349 pat = shallow_copy_rtx (pat);
25350 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25352 for (int i = 0; i < XVECLEN (pat, 0); i++)
25353 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25355 rtx set = XVECEXP (pat, 0, i);
25358 set = simplify_replace_rtx (set, reg, repl);
25360 set = simplify_replace_rtx (set, reg2, repl2);
25361 XVECEXP (pat, 0, i) = set;
25363 if (!REG_P (SET_SRC (set))
25364 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25365 RTX_FRAME_RELATED_P (set) = 1;
25369 gcc_unreachable ();
25371 RTX_FRAME_RELATED_P (insn) = 1;
25372 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25377 /* Returns an insn that has a vrsave set operation with the
25378 appropriate CLOBBERs. */
25381 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25384 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25385 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25388 = gen_rtx_SET (vrsave,
25389 gen_rtx_UNSPEC_VOLATILE (SImode,
25390 gen_rtvec (2, reg, vrsave),
25391 UNSPECV_SET_VRSAVE));
25395 /* We need to clobber the registers in the mask so the scheduler
25396 does not move sets to VRSAVE before sets of AltiVec registers.
25398 However, if the function receives nonlocal gotos, reload will set
25399 all call saved registers live. We will end up with:
25401 (set (reg 999) (mem))
25402 (parallel [ (set (reg vrsave) (unspec blah))
25403 (clobber (reg 999))])
25405 The clobber will cause the store into reg 999 to be dead, and
25406 flow will attempt to delete an epilogue insn. In this case, we
25407 need an unspec use/set of the register. */
25409 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25410 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25412 if (!epiloguep || call_used_regs [i])
25413 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
25414 gen_rtx_REG (V4SImode, i));
25417 rtx reg = gen_rtx_REG (V4SImode, i);
25420 = gen_rtx_SET (reg,
25421 gen_rtx_UNSPEC (V4SImode,
25422 gen_rtvec (1, reg), 27));
25426 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25428 for (i = 0; i < nclobs; ++i)
25429 XVECEXP (insn, 0, i) = clobs[i];
25435 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25439 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25440 mem = gen_frame_mem (GET_MODE (reg), addr);
25441 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25445 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25447 return gen_frame_set (reg, frame_reg, offset, false);
25451 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25453 return gen_frame_set (reg, frame_reg, offset, true);
25456 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25457 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25460 emit_frame_save (rtx frame_reg, machine_mode mode,
25461 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25465 /* Some cases that need register indexed addressing. */
25466 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25467 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25469 reg = gen_rtx_REG (mode, regno);
25470 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25471 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25472 NULL_RTX, NULL_RTX);
25475 /* Emit an offset memory reference suitable for a frame store, while
25476 converting to a valid addressing mode. */
25479 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25481 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25484 #ifndef TARGET_FIX_AND_CONTINUE
25485 #define TARGET_FIX_AND_CONTINUE 0
25488 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25489 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25490 #define LAST_SAVRES_REGISTER 31
25491 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25502 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25504 /* Temporary holding space for an out-of-line register save/restore
25506 static char savres_routine_name[30];
25508 /* Return the name for an out-of-line register save/restore routine.
25509 We are saving/restoring GPRs if GPR is true. */
25512 rs6000_savres_routine_name (int regno, int sel)
25514 const char *prefix = "";
25515 const char *suffix = "";
25517 /* Different targets are supposed to define
25518 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25519 routine name could be defined with:
25521 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25523 This is a nice idea in practice, but in reality, things are
25524 complicated in several ways:
25526 - ELF targets have save/restore routines for GPRs.
25528 - PPC64 ELF targets have routines for save/restore of GPRs that
25529 differ in what they do with the link register, so having a set
25530 prefix doesn't work. (We only use one of the save routines at
25531 the moment, though.)
25533 - PPC32 elf targets have "exit" versions of the restore routines
25534 that restore the link register and can save some extra space.
25535 These require an extra suffix. (There are also "tail" versions
25536 of the restore routines and "GOT" versions of the save routines,
25537 but we don't generate those at present. Same problems apply,
25540 We deal with all this by synthesizing our own prefix/suffix and
25541 using that for the simple sprintf call shown above. */
25542 if (DEFAULT_ABI == ABI_V4)
25547 if ((sel & SAVRES_REG) == SAVRES_GPR)
25548 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25549 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25550 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25551 else if ((sel & SAVRES_REG) == SAVRES_VR)
25552 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25556 if ((sel & SAVRES_LR))
25559 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25561 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25562 /* No out-of-line save/restore routines for GPRs on AIX. */
25563 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25567 if ((sel & SAVRES_REG) == SAVRES_GPR)
25568 prefix = ((sel & SAVRES_SAVE)
25569 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25570 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25571 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25573 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25574 if ((sel & SAVRES_LR))
25575 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25579 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25580 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25583 else if ((sel & SAVRES_REG) == SAVRES_VR)
25584 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25589 if (DEFAULT_ABI == ABI_DARWIN)
25591 /* The Darwin approach is (slightly) different, in order to be
25592 compatible with code generated by the system toolchain. There is a
25593 single symbol for the start of save sequence, and the code here
25594 embeds an offset into that code on the basis of the first register
25596 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25597 if ((sel & SAVRES_REG) == SAVRES_GPR)
25598 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25599 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25600 (regno - 13) * 4, prefix, regno);
25601 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25602 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25603 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25604 else if ((sel & SAVRES_REG) == SAVRES_VR)
25605 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25606 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25611 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25613 return savres_routine_name;
25616 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25617 We are saving/restoring GPRs if GPR is true. */
25620 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25622 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25623 ? info->first_gp_reg_save
25624 : (sel & SAVRES_REG) == SAVRES_FPR
25625 ? info->first_fp_reg_save - 32
25626 : (sel & SAVRES_REG) == SAVRES_VR
25627 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25632 /* Don't generate bogus routine names. */
25633 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25634 && regno <= LAST_SAVRES_REGISTER
25635 && select >= 0 && select <= 12);
25637 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25643 name = rs6000_savres_routine_name (regno, sel);
25645 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25646 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25647 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25653 /* Emit a sequence of insns, including a stack tie if needed, for
25654 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25655 reset the stack pointer, but move the base of the frame into
25656 reg UPDT_REGNO for use by out-of-line register restore routines. */
25659 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25660 unsigned updt_regno)
25662 /* If there is nothing to do, don't do anything. */
25663 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25666 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25668 /* This blockage is needed so that sched doesn't decide to move
25669 the sp change before the register restores. */
25670 if (DEFAULT_ABI == ABI_V4)
25671 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25672 GEN_INT (frame_off)));
25674 /* If we are restoring registers out-of-line, we will be using the
25675 "exit" variants of the restore routines, which will reset the
25676 stack for us. But we do need to point updt_reg into the
25677 right place for those routines. */
25678 if (frame_off != 0)
25679 return emit_insn (gen_add3_insn (updt_reg_rtx,
25680 frame_reg_rtx, GEN_INT (frame_off)));
25682 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
25687 /* Return the register number used as a pointer by out-of-line
25688 save/restore functions. */
25690 static inline unsigned
25691 ptr_regno_for_savres (int sel)
25693 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25694 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
25695 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
25698 /* Construct a parallel rtx describing the effect of a call to an
25699 out-of-line register save/restore routine, and emit the insn
25700 or jump_insn as appropriate. */
25703 rs6000_emit_savres_rtx (rs6000_stack_t *info,
25704 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
25705 machine_mode reg_mode, int sel)
25708 int offset, start_reg, end_reg, n_regs, use_reg;
25709 int reg_size = GET_MODE_SIZE (reg_mode);
25716 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25717 ? info->first_gp_reg_save
25718 : (sel & SAVRES_REG) == SAVRES_FPR
25719 ? info->first_fp_reg_save
25720 : (sel & SAVRES_REG) == SAVRES_VR
25721 ? info->first_altivec_reg_save
25723 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25725 : (sel & SAVRES_REG) == SAVRES_FPR
25727 : (sel & SAVRES_REG) == SAVRES_VR
25728 ? LAST_ALTIVEC_REGNO + 1
25730 n_regs = end_reg - start_reg;
25731 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
25732 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
25735 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25736 RTVEC_ELT (p, offset++) = ret_rtx;
25738 RTVEC_ELT (p, offset++)
25739 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
25741 sym = rs6000_savres_routine_sym (info, sel);
25742 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
25744 use_reg = ptr_regno_for_savres (sel);
25745 if ((sel & SAVRES_REG) == SAVRES_VR)
25747 /* Vector regs are saved/restored using [reg+reg] addressing. */
25748 RTVEC_ELT (p, offset++)
25749 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25750 RTVEC_ELT (p, offset++)
25751 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
25754 RTVEC_ELT (p, offset++)
25755 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25757 for (i = 0; i < end_reg - start_reg; i++)
25758 RTVEC_ELT (p, i + offset)
25759 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
25760 frame_reg_rtx, save_area_offset + reg_size * i,
25761 (sel & SAVRES_SAVE) != 0);
25763 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25764 RTVEC_ELT (p, i + offset)
25765 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
25767 par = gen_rtx_PARALLEL (VOIDmode, p);
25769 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25771 insn = emit_jump_insn (par);
25772 JUMP_LABEL (insn) = ret_rtx;
25775 insn = emit_insn (par);
25779 /* Emit prologue code to store CR fields that need to be saved into REG. This
25780 function should only be called when moving the non-volatile CRs to REG, it
25781 is not a general purpose routine to move the entire set of CRs to REG.
25782 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
25786 rs6000_emit_prologue_move_from_cr (rtx reg)
25788 /* Only the ELFv2 ABI allows storing only selected fields. */
25789 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
25791 int i, cr_reg[8], count = 0;
25793 /* Collect CR fields that must be saved. */
25794 for (i = 0; i < 8; i++)
25795 if (save_reg_p (CR0_REGNO + i))
25796 cr_reg[count++] = i;
25798 /* If it's just a single one, use mfcrf. */
25801 rtvec p = rtvec_alloc (1);
25802 rtvec r = rtvec_alloc (2);
25803 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
25804 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
25806 = gen_rtx_SET (reg,
25807 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
25809 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
25813 /* ??? It might be better to handle count == 2 / 3 cases here
25814 as well, using logical operations to combine the values. */
25817 emit_insn (gen_prologue_movesi_from_cr (reg));
25820 /* Return whether the split-stack arg pointer (r12) is used. */
25823 split_stack_arg_pointer_used_p (void)
25825 /* If the pseudo holding the arg pointer is no longer a pseudo,
25826 then the arg pointer is used. */
25827 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
25828 && (!REG_P (cfun->machine->split_stack_arg_pointer)
25829 || (REGNO (cfun->machine->split_stack_arg_pointer)
25830 < FIRST_PSEUDO_REGISTER)))
25833 /* Unfortunately we also need to do some code scanning, since
25834 r12 may have been substituted for the pseudo. */
25836 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
25837 FOR_BB_INSNS (bb, insn)
25838 if (NONDEBUG_INSN_P (insn))
25840 /* A call destroys r12. */
25845 FOR_EACH_INSN_USE (use, insn)
25847 rtx x = DF_REF_REG (use);
25848 if (REG_P (x) && REGNO (x) == 12)
25852 FOR_EACH_INSN_DEF (def, insn)
25854 rtx x = DF_REF_REG (def);
25855 if (REG_P (x) && REGNO (x) == 12)
25859 return bitmap_bit_p (DF_LR_OUT (bb), 12);
25862 /* Return whether we need to emit an ELFv2 global entry point prologue. */
25865 rs6000_global_entry_point_needed_p (void)
25867 /* Only needed for the ELFv2 ABI. */
25868 if (DEFAULT_ABI != ABI_ELFv2)
25871 /* With -msingle-pic-base, we assume the whole program shares the same
25872 TOC, so no global entry point prologues are needed anywhere. */
25873 if (TARGET_SINGLE_PIC_BASE)
25876 /* Ensure we have a global entry point for thunks. ??? We could
25877 avoid that if the target routine doesn't need a global entry point,
25878 but we do not know whether this is the case at this point. */
25879 if (cfun->is_thunk)
25882 /* For regular functions, rs6000_emit_prologue sets this flag if the
25883 routine ever uses the TOC pointer. */
25884 return cfun->machine->r2_setup_needed;
25887 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
25889 rs6000_get_separate_components (void)
25891 rs6000_stack_t *info = rs6000_stack_info ();
25893 if (WORLD_SAVE_P (info))
25896 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
25897 && !(info->savres_strategy & REST_MULTIPLE));
25899 /* Component 0 is the save/restore of LR (done via GPR0).
25900 Component 2 is the save of the TOC (GPR2).
25901 Components 13..31 are the save/restore of GPR13..GPR31.
25902 Components 46..63 are the save/restore of FPR14..FPR31. */
25904 cfun->machine->n_components = 64;
25906 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
25907 bitmap_clear (components);
25909 int reg_size = TARGET_32BIT ? 4 : 8;
25910 int fp_reg_size = 8;
25912 /* The GPRs we need saved to the frame. */
25913 if ((info->savres_strategy & SAVE_INLINE_GPRS)
25914 && (info->savres_strategy & REST_INLINE_GPRS))
25916 int offset = info->gp_save_offset;
25918 offset += info->total_size;
25920 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
25922 if (IN_RANGE (offset, -0x8000, 0x7fff)
25923 && save_reg_p (regno))
25924 bitmap_set_bit (components, regno);
25926 offset += reg_size;
25930 /* Don't mess with the hard frame pointer. */
25931 if (frame_pointer_needed)
25932 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
25934 /* Don't mess with the fixed TOC register. */
25935 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
25936 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
25937 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
25938 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
25940 /* The FPRs we need saved to the frame. */
25941 if ((info->savres_strategy & SAVE_INLINE_FPRS)
25942 && (info->savres_strategy & REST_INLINE_FPRS))
25944 int offset = info->fp_save_offset;
25946 offset += info->total_size;
25948 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
25950 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
25951 bitmap_set_bit (components, regno);
25953 offset += fp_reg_size;
25957 /* Optimize LR save and restore if we can. This is component 0. Any
25958 out-of-line register save/restore routines need LR. */
25959 if (info->lr_save_p
25960 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
25961 && (info->savres_strategy & SAVE_INLINE_GPRS)
25962 && (info->savres_strategy & REST_INLINE_GPRS)
25963 && (info->savres_strategy & SAVE_INLINE_FPRS)
25964 && (info->savres_strategy & REST_INLINE_FPRS)
25965 && (info->savres_strategy & SAVE_INLINE_VRS)
25966 && (info->savres_strategy & REST_INLINE_VRS))
25968 int offset = info->lr_save_offset;
25970 offset += info->total_size;
25971 if (IN_RANGE (offset, -0x8000, 0x7fff))
25972 bitmap_set_bit (components, 0);
25975 /* Optimize saving the TOC. This is component 2. */
25976 if (cfun->machine->save_toc_in_prologue)
25977 bitmap_set_bit (components, 2);
25982 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
25984 rs6000_components_for_bb (basic_block bb)
25986 rs6000_stack_t *info = rs6000_stack_info ();
25988 bitmap in = DF_LIVE_IN (bb);
25989 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
25990 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
25992 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
25993 bitmap_clear (components);
25995 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
25998 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
25999 if (bitmap_bit_p (in, regno)
26000 || bitmap_bit_p (gen, regno)
26001 || bitmap_bit_p (kill, regno))
26002 bitmap_set_bit (components, regno);
26005 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26006 if (bitmap_bit_p (in, regno)
26007 || bitmap_bit_p (gen, regno)
26008 || bitmap_bit_p (kill, regno))
26009 bitmap_set_bit (components, regno);
26011 /* The link register. */
26012 if (bitmap_bit_p (in, LR_REGNO)
26013 || bitmap_bit_p (gen, LR_REGNO)
26014 || bitmap_bit_p (kill, LR_REGNO))
26015 bitmap_set_bit (components, 0);
26017 /* The TOC save. */
26018 if (bitmap_bit_p (in, TOC_REGNUM)
26019 || bitmap_bit_p (gen, TOC_REGNUM)
26020 || bitmap_bit_p (kill, TOC_REGNUM))
26021 bitmap_set_bit (components, 2);
26026 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26028 rs6000_disqualify_components (sbitmap components, edge e,
26029 sbitmap edge_components, bool /*is_prologue*/)
26031 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26032 live where we want to place that code. */
26033 if (bitmap_bit_p (edge_components, 0)
26034 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26037 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26038 "on entry to bb %d\n", e->dest->index);
26039 bitmap_clear_bit (components, 0);
26043 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26045 rs6000_emit_prologue_components (sbitmap components)
26047 rs6000_stack_t *info = rs6000_stack_info ();
26048 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26049 ? HARD_FRAME_POINTER_REGNUM
26050 : STACK_POINTER_REGNUM);
26052 machine_mode reg_mode = Pmode;
26053 int reg_size = TARGET_32BIT ? 4 : 8;
26054 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26055 int fp_reg_size = 8;
26057 /* Prologue for LR. */
26058 if (bitmap_bit_p (components, 0))
26060 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26061 rtx reg = gen_rtx_REG (reg_mode, 0);
26062 rtx_insn *insn = emit_move_insn (reg, lr);
26063 RTX_FRAME_RELATED_P (insn) = 1;
26064 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26066 int offset = info->lr_save_offset;
26068 offset += info->total_size;
26070 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26071 RTX_FRAME_RELATED_P (insn) = 1;
26072 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26073 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26076 /* Prologue for TOC. */
26077 if (bitmap_bit_p (components, 2))
26079 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26080 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26081 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26084 /* Prologue for the GPRs. */
26085 int offset = info->gp_save_offset;
26087 offset += info->total_size;
26089 for (int i = info->first_gp_reg_save; i < 32; i++)
26091 if (bitmap_bit_p (components, i))
26093 rtx reg = gen_rtx_REG (reg_mode, i);
26094 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26095 RTX_FRAME_RELATED_P (insn) = 1;
26096 rtx set = copy_rtx (single_set (insn));
26097 add_reg_note (insn, REG_CFA_OFFSET, set);
26100 offset += reg_size;
26103 /* Prologue for the FPRs. */
26104 offset = info->fp_save_offset;
26106 offset += info->total_size;
26108 for (int i = info->first_fp_reg_save; i < 64; i++)
26110 if (bitmap_bit_p (components, i))
26112 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26113 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26114 RTX_FRAME_RELATED_P (insn) = 1;
26115 rtx set = copy_rtx (single_set (insn));
26116 add_reg_note (insn, REG_CFA_OFFSET, set);
26119 offset += fp_reg_size;
26123 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26125 rs6000_emit_epilogue_components (sbitmap components)
26127 rs6000_stack_t *info = rs6000_stack_info ();
26128 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26129 ? HARD_FRAME_POINTER_REGNUM
26130 : STACK_POINTER_REGNUM);
26132 machine_mode reg_mode = Pmode;
26133 int reg_size = TARGET_32BIT ? 4 : 8;
26135 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26136 int fp_reg_size = 8;
26138 /* Epilogue for the FPRs. */
26139 int offset = info->fp_save_offset;
26141 offset += info->total_size;
26143 for (int i = info->first_fp_reg_save; i < 64; i++)
26145 if (bitmap_bit_p (components, i))
26147 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26148 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26149 RTX_FRAME_RELATED_P (insn) = 1;
26150 add_reg_note (insn, REG_CFA_RESTORE, reg);
26153 offset += fp_reg_size;
26156 /* Epilogue for the GPRs. */
26157 offset = info->gp_save_offset;
26159 offset += info->total_size;
26161 for (int i = info->first_gp_reg_save; i < 32; i++)
26163 if (bitmap_bit_p (components, i))
26165 rtx reg = gen_rtx_REG (reg_mode, i);
26166 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26167 RTX_FRAME_RELATED_P (insn) = 1;
26168 add_reg_note (insn, REG_CFA_RESTORE, reg);
26171 offset += reg_size;
26174 /* Epilogue for LR. */
26175 if (bitmap_bit_p (components, 0))
26177 int offset = info->lr_save_offset;
26179 offset += info->total_size;
26181 rtx reg = gen_rtx_REG (reg_mode, 0);
26182 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26184 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26185 insn = emit_move_insn (lr, reg);
26186 RTX_FRAME_RELATED_P (insn) = 1;
26187 add_reg_note (insn, REG_CFA_RESTORE, lr);
26191 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26193 rs6000_set_handled_components (sbitmap components)
26195 rs6000_stack_t *info = rs6000_stack_info ();
26197 for (int i = info->first_gp_reg_save; i < 32; i++)
26198 if (bitmap_bit_p (components, i))
26199 cfun->machine->gpr_is_wrapped_separately[i] = true;
26201 for (int i = info->first_fp_reg_save; i < 64; i++)
26202 if (bitmap_bit_p (components, i))
26203 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26205 if (bitmap_bit_p (components, 0))
26206 cfun->machine->lr_is_wrapped_separately = true;
26208 if (bitmap_bit_p (components, 2))
26209 cfun->machine->toc_is_wrapped_separately = true;
26212 /* VRSAVE is a bit vector representing which AltiVec registers
26213 are used. The OS uses this to determine which vector
26214 registers to save on a context switch. We need to save
26215 VRSAVE on the stack frame, add whatever AltiVec registers we
26216 used in this function, and do the corresponding magic in the
26219 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26220 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26222 /* Get VRSAVE into a GPR. */
26223 rtx reg = gen_rtx_REG (SImode, save_regno);
26224 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26226 emit_insn (gen_get_vrsave_internal (reg));
26228 emit_insn (gen_rtx_SET (reg, vrsave));
26231 int offset = info->vrsave_save_offset + frame_off;
26232 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26234 /* Include the registers in the mask. */
26235 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26237 emit_insn (generate_set_vrsave (reg, info, 0));
26240 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26241 called, it left the arg pointer to the old stack in r29. Otherwise, the
26242 arg pointer is the top of the current frame. */
26244 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26245 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26247 cfun->machine->split_stack_argp_used = true;
26251 rtx r12 = gen_rtx_REG (Pmode, 12);
26252 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26253 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26254 emit_insn_before (set_r12, sp_adjust);
26256 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26258 rtx r12 = gen_rtx_REG (Pmode, 12);
26259 if (frame_off == 0)
26260 emit_move_insn (r12, frame_reg_rtx);
26262 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26267 rtx r12 = gen_rtx_REG (Pmode, 12);
26268 rtx r29 = gen_rtx_REG (Pmode, 29);
26269 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26270 rtx not_more = gen_label_rtx ();
26273 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26274 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26275 gen_rtx_LABEL_REF (VOIDmode, not_more),
26277 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26278 JUMP_LABEL (jump) = not_more;
26279 LABEL_NUSES (not_more) += 1;
26280 emit_move_insn (r12, r29);
26281 emit_label (not_more);
26285 /* Emit function prologue as insns. */
26288 rs6000_emit_prologue (void)
26290 rs6000_stack_t *info = rs6000_stack_info ();
26291 machine_mode reg_mode = Pmode;
26292 int reg_size = TARGET_32BIT ? 4 : 8;
26293 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26294 int fp_reg_size = 8;
26295 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26296 rtx frame_reg_rtx = sp_reg_rtx;
26297 unsigned int cr_save_regno;
26298 rtx cr_save_rtx = NULL_RTX;
26301 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26302 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26303 && call_used_regs[STATIC_CHAIN_REGNUM]);
26304 int using_split_stack = (flag_split_stack
26305 && (lookup_attribute ("no_split_stack",
26306 DECL_ATTRIBUTES (cfun->decl))
26309 /* Offset to top of frame for frame_reg and sp respectively. */
26310 HOST_WIDE_INT frame_off = 0;
26311 HOST_WIDE_INT sp_off = 0;
26312 /* sp_adjust is the stack adjusting instruction, tracked so that the
26313 insn setting up the split-stack arg pointer can be emitted just
26314 prior to it, when r12 is not used here for other purposes. */
26315 rtx_insn *sp_adjust = 0;
26318 /* Track and check usage of r0, r11, r12. */
26319 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26320 #define START_USE(R) do \
26322 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26323 reg_inuse |= 1 << (R); \
26325 #define END_USE(R) do \
26327 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26328 reg_inuse &= ~(1 << (R)); \
26330 #define NOT_INUSE(R) do \
26332 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26335 #define START_USE(R) do {} while (0)
26336 #define END_USE(R) do {} while (0)
26337 #define NOT_INUSE(R) do {} while (0)
26340 if (DEFAULT_ABI == ABI_ELFv2
26341 && !TARGET_SINGLE_PIC_BASE)
26343 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26345 /* With -mminimal-toc we may generate an extra use of r2 below. */
26346 if (TARGET_TOC && TARGET_MINIMAL_TOC
26347 && !constant_pool_empty_p ())
26348 cfun->machine->r2_setup_needed = true;
26352 if (flag_stack_usage_info)
26353 current_function_static_stack_size = info->total_size;
26355 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26357 HOST_WIDE_INT size = info->total_size;
26359 if (crtl->is_leaf && !cfun->calls_alloca)
26361 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26362 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26363 size - get_stack_check_protect ());
26366 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26369 if (TARGET_FIX_AND_CONTINUE)
26371 /* gdb on darwin arranges to forward a function from the old
26372 address by modifying the first 5 instructions of the function
26373 to branch to the overriding function. This is necessary to
26374 permit function pointers that point to the old function to
26375 actually forward to the new function. */
26376 emit_insn (gen_nop ());
26377 emit_insn (gen_nop ());
26378 emit_insn (gen_nop ());
26379 emit_insn (gen_nop ());
26380 emit_insn (gen_nop ());
26383 /* Handle world saves specially here. */
26384 if (WORLD_SAVE_P (info))
26391 /* save_world expects lr in r0. */
26392 reg0 = gen_rtx_REG (Pmode, 0);
26393 if (info->lr_save_p)
26395 insn = emit_move_insn (reg0,
26396 gen_rtx_REG (Pmode, LR_REGNO));
26397 RTX_FRAME_RELATED_P (insn) = 1;
26400 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26401 assumptions about the offsets of various bits of the stack
26403 gcc_assert (info->gp_save_offset == -220
26404 && info->fp_save_offset == -144
26405 && info->lr_save_offset == 8
26406 && info->cr_save_offset == 4
26409 && (!crtl->calls_eh_return
26410 || info->ehrd_offset == -432)
26411 && info->vrsave_save_offset == -224
26412 && info->altivec_save_offset == -416);
26414 treg = gen_rtx_REG (SImode, 11);
26415 emit_move_insn (treg, GEN_INT (-info->total_size));
26417 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26418 in R11. It also clobbers R12, so beware! */
26420 /* Preserve CR2 for save_world prologues */
26422 sz += 32 - info->first_gp_reg_save;
26423 sz += 64 - info->first_fp_reg_save;
26424 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26425 p = rtvec_alloc (sz);
26427 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
26428 gen_rtx_REG (SImode,
26430 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26431 gen_rtx_SYMBOL_REF (Pmode,
26433 /* We do floats first so that the instruction pattern matches
26435 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26437 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26438 info->first_fp_reg_save + i),
26440 info->fp_save_offset + frame_off + 8 * i);
26441 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26443 = gen_frame_store (gen_rtx_REG (V4SImode,
26444 info->first_altivec_reg_save + i),
26446 info->altivec_save_offset + frame_off + 16 * i);
26447 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26449 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26451 info->gp_save_offset + frame_off + reg_size * i);
26453 /* CR register traditionally saved as CR2. */
26455 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26456 frame_reg_rtx, info->cr_save_offset + frame_off);
26457 /* Explain about use of R0. */
26458 if (info->lr_save_p)
26460 = gen_frame_store (reg0,
26461 frame_reg_rtx, info->lr_save_offset + frame_off);
26462 /* Explain what happens to the stack pointer. */
26464 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26465 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26468 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26469 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26470 treg, GEN_INT (-info->total_size));
26471 sp_off = frame_off = info->total_size;
26474 strategy = info->savres_strategy;
26476 /* For V.4, update stack before we do any saving and set back pointer. */
26477 if (! WORLD_SAVE_P (info)
26479 && (DEFAULT_ABI == ABI_V4
26480 || crtl->calls_eh_return))
26482 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26483 || !(strategy & SAVE_INLINE_GPRS)
26484 || !(strategy & SAVE_INLINE_VRS));
26485 int ptr_regno = -1;
26486 rtx ptr_reg = NULL_RTX;
26489 if (info->total_size < 32767)
26490 frame_off = info->total_size;
26493 else if (info->cr_save_p
26495 || info->first_fp_reg_save < 64
26496 || info->first_gp_reg_save < 32
26497 || info->altivec_size != 0
26498 || info->vrsave_size != 0
26499 || crtl->calls_eh_return)
26503 /* The prologue won't be saving any regs so there is no need
26504 to set up a frame register to access any frame save area.
26505 We also won't be using frame_off anywhere below, but set
26506 the correct value anyway to protect against future
26507 changes to this function. */
26508 frame_off = info->total_size;
26510 if (ptr_regno != -1)
26512 /* Set up the frame offset to that needed by the first
26513 out-of-line save function. */
26514 START_USE (ptr_regno);
26515 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26516 frame_reg_rtx = ptr_reg;
26517 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26518 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26519 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26520 ptr_off = info->gp_save_offset + info->gp_size;
26521 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26522 ptr_off = info->altivec_save_offset + info->altivec_size;
26523 frame_off = -ptr_off;
26525 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26527 if (REGNO (frame_reg_rtx) == 12)
26529 sp_off = info->total_size;
26530 if (frame_reg_rtx != sp_reg_rtx)
26531 rs6000_emit_stack_tie (frame_reg_rtx, false);
26534 /* If we use the link register, get it into r0. */
26535 if (!WORLD_SAVE_P (info) && info->lr_save_p
26536 && !cfun->machine->lr_is_wrapped_separately)
26538 rtx addr, reg, mem;
26540 reg = gen_rtx_REG (Pmode, 0);
26542 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26543 RTX_FRAME_RELATED_P (insn) = 1;
26545 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26546 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26548 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26549 GEN_INT (info->lr_save_offset + frame_off));
26550 mem = gen_rtx_MEM (Pmode, addr);
26551 /* This should not be of rs6000_sr_alias_set, because of
26552 __builtin_return_address. */
26554 insn = emit_move_insn (mem, reg);
26555 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26556 NULL_RTX, NULL_RTX);
26561 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26562 r12 will be needed by out-of-line gpr restore. */
26563 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26564 && !(strategy & (SAVE_INLINE_GPRS
26565 | SAVE_NOINLINE_GPRS_SAVES_LR))
26567 if (!WORLD_SAVE_P (info)
26569 && REGNO (frame_reg_rtx) != cr_save_regno
26570 && !(using_static_chain_p && cr_save_regno == 11)
26571 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26573 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26574 START_USE (cr_save_regno);
26575 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26578 /* Do any required saving of fpr's. If only one or two to save, do
26579 it ourselves. Otherwise, call function. */
26580 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26582 int offset = info->fp_save_offset + frame_off;
26583 for (int i = info->first_fp_reg_save; i < 64; i++)
26586 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26587 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26588 sp_off - frame_off);
26590 offset += fp_reg_size;
26593 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26595 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26596 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26597 unsigned ptr_regno = ptr_regno_for_savres (sel);
26598 rtx ptr_reg = frame_reg_rtx;
26600 if (REGNO (frame_reg_rtx) == ptr_regno)
26601 gcc_checking_assert (frame_off == 0);
26604 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26605 NOT_INUSE (ptr_regno);
26606 emit_insn (gen_add3_insn (ptr_reg,
26607 frame_reg_rtx, GEN_INT (frame_off)));
26609 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26610 info->fp_save_offset,
26611 info->lr_save_offset,
26613 rs6000_frame_related (insn, ptr_reg, sp_off,
26614 NULL_RTX, NULL_RTX);
26619 /* Save GPRs. This is done as a PARALLEL if we are using
26620 the store-multiple instructions. */
26621 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26623 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26624 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26625 unsigned ptr_regno = ptr_regno_for_savres (sel);
26626 rtx ptr_reg = frame_reg_rtx;
26627 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26628 int end_save = info->gp_save_offset + info->gp_size;
26631 if (ptr_regno == 12)
26634 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26636 /* Need to adjust r11 (r12) if we saved any FPRs. */
26637 if (end_save + frame_off != 0)
26639 rtx offset = GEN_INT (end_save + frame_off);
26642 frame_off = -end_save;
26644 NOT_INUSE (ptr_regno);
26645 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26647 else if (!ptr_set_up)
26649 NOT_INUSE (ptr_regno);
26650 emit_move_insn (ptr_reg, frame_reg_rtx);
26652 ptr_off = -end_save;
26653 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26654 info->gp_save_offset + ptr_off,
26655 info->lr_save_offset + ptr_off,
26657 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26658 NULL_RTX, NULL_RTX);
26662 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26666 p = rtvec_alloc (32 - info->first_gp_reg_save);
26667 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26669 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26671 info->gp_save_offset + frame_off + reg_size * i);
26672 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26673 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26674 NULL_RTX, NULL_RTX);
26676 else if (!WORLD_SAVE_P (info))
26678 int offset = info->gp_save_offset + frame_off;
26679 for (int i = info->first_gp_reg_save; i < 32; i++)
26682 && !cfun->machine->gpr_is_wrapped_separately[i])
26683 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26684 sp_off - frame_off);
26686 offset += reg_size;
26690 if (crtl->calls_eh_return)
26697 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26698 if (regno == INVALID_REGNUM)
26702 p = rtvec_alloc (i);
26706 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26707 if (regno == INVALID_REGNUM)
26711 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
26713 info->ehrd_offset + sp_off + reg_size * (int) i);
26714 RTVEC_ELT (p, i) = set;
26715 RTX_FRAME_RELATED_P (set) = 1;
26718 insn = emit_insn (gen_blockage ());
26719 RTX_FRAME_RELATED_P (insn) = 1;
26720 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
26723 /* In AIX ABI we need to make sure r2 is really saved. */
26724 if (TARGET_AIX && crtl->calls_eh_return)
26726 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
26727 rtx join_insn, note;
26728 rtx_insn *save_insn;
26729 long toc_restore_insn;
26731 tmp_reg = gen_rtx_REG (Pmode, 11);
26732 tmp_reg_si = gen_rtx_REG (SImode, 11);
26733 if (using_static_chain_p)
26736 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
26740 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
26741 /* Peek at instruction to which this function returns. If it's
26742 restoring r2, then we know we've already saved r2. We can't
26743 unconditionally save r2 because the value we have will already
26744 be updated if we arrived at this function via a plt call or
26745 toc adjusting stub. */
26746 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
26747 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
26748 + RS6000_TOC_SAVE_SLOT);
26749 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
26750 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
26751 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
26752 validate_condition_mode (EQ, CCUNSmode);
26753 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
26754 emit_insn (gen_rtx_SET (compare_result,
26755 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
26756 toc_save_done = gen_label_rtx ();
26757 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26758 gen_rtx_EQ (VOIDmode, compare_result,
26760 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
26762 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26763 JUMP_LABEL (jump) = toc_save_done;
26764 LABEL_NUSES (toc_save_done) += 1;
26766 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
26767 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
26768 sp_off - frame_off);
26770 emit_label (toc_save_done);
26772 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
26773 have a CFG that has different saves along different paths.
26774 Move the note to a dummy blockage insn, which describes that
26775 R2 is unconditionally saved after the label. */
26776 /* ??? An alternate representation might be a special insn pattern
26777 containing both the branch and the store. That might let the
26778 code that minimizes the number of DW_CFA_advance opcodes better
26779 freedom in placing the annotations. */
26780 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
26782 remove_note (save_insn, note);
26784 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
26785 copy_rtx (PATTERN (save_insn)), NULL_RTX);
26786 RTX_FRAME_RELATED_P (save_insn) = 0;
26788 join_insn = emit_insn (gen_blockage ());
26789 REG_NOTES (join_insn) = note;
26790 RTX_FRAME_RELATED_P (join_insn) = 1;
26792 if (using_static_chain_p)
26794 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
26801 /* Save CR if we use any that must be preserved. */
26802 if (!WORLD_SAVE_P (info) && info->cr_save_p)
26804 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26805 GEN_INT (info->cr_save_offset + frame_off));
26806 rtx mem = gen_frame_mem (SImode, addr);
26808 /* If we didn't copy cr before, do so now using r0. */
26809 if (cr_save_rtx == NULL_RTX)
26812 cr_save_rtx = gen_rtx_REG (SImode, 0);
26813 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26816 /* Saving CR requires a two-instruction sequence: one instruction
26817 to move the CR to a general-purpose register, and a second
26818 instruction that stores the GPR to memory.
26820 We do not emit any DWARF CFI records for the first of these,
26821 because we cannot properly represent the fact that CR is saved in
26822 a register. One reason is that we cannot express that multiple
26823 CR fields are saved; another reason is that on 64-bit, the size
26824 of the CR register in DWARF (4 bytes) differs from the size of
26825 a general-purpose register.
26827 This means if any intervening instruction were to clobber one of
26828 the call-saved CR fields, we'd have incorrect CFI. To prevent
26829 this from happening, we mark the store to memory as a use of
26830 those CR fields, which prevents any such instruction from being
26831 scheduled in between the two instructions. */
26836 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
26837 for (i = 0; i < 8; i++)
26838 if (save_reg_p (CR0_REGNO + i))
26839 crsave_v[n_crsave++]
26840 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
26842 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
26843 gen_rtvec_v (n_crsave, crsave_v)));
26844 END_USE (REGNO (cr_save_rtx));
26846 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
26847 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
26848 so we need to construct a frame expression manually. */
26849 RTX_FRAME_RELATED_P (insn) = 1;
26851 /* Update address to be stack-pointer relative, like
26852 rs6000_frame_related would do. */
26853 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26854 GEN_INT (info->cr_save_offset + sp_off));
26855 mem = gen_frame_mem (SImode, addr);
26857 if (DEFAULT_ABI == ABI_ELFv2)
26859 /* In the ELFv2 ABI we generate separate CFI records for each
26860 CR field that was actually saved. They all point to the
26861 same 32-bit stack slot. */
26865 for (i = 0; i < 8; i++)
26866 if (save_reg_p (CR0_REGNO + i))
26869 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
26871 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
26875 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
26876 gen_rtx_PARALLEL (VOIDmode,
26877 gen_rtvec_v (n_crframe, crframe)));
26881 /* In other ABIs, by convention, we use a single CR regnum to
26882 represent the fact that all call-saved CR fields are saved.
26883 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
26884 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
26885 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
26889 /* In the ELFv2 ABI we need to save all call-saved CR fields into
26890 *separate* slots if the routine calls __builtin_eh_return, so
26891 that they can be independently restored by the unwinder. */
26892 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
26894 int i, cr_off = info->ehcr_offset;
26897 /* ??? We might get better performance by using multiple mfocrf
26899 crsave = gen_rtx_REG (SImode, 0);
26900 emit_insn (gen_prologue_movesi_from_cr (crsave));
26902 for (i = 0; i < 8; i++)
26903 if (!call_used_regs[CR0_REGNO + i])
26905 rtvec p = rtvec_alloc (2);
26907 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
26909 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
26911 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26913 RTX_FRAME_RELATED_P (insn) = 1;
26914 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
26915 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
26916 sp_reg_rtx, cr_off + sp_off));
26918 cr_off += reg_size;
26922 /* If we are emitting stack probes, but allocate no stack, then
26923 just note that in the dump file. */
26924 if (flag_stack_clash_protection
26927 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
26929 /* Update stack and set back pointer unless this is V.4,
26930 for which it was done previously. */
26931 if (!WORLD_SAVE_P (info) && info->push_p
26932 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
26934 rtx ptr_reg = NULL;
26937 /* If saving altivec regs we need to be able to address all save
26938 locations using a 16-bit offset. */
26939 if ((strategy & SAVE_INLINE_VRS) == 0
26940 || (info->altivec_size != 0
26941 && (info->altivec_save_offset + info->altivec_size - 16
26942 + info->total_size - frame_off) > 32767)
26943 || (info->vrsave_size != 0
26944 && (info->vrsave_save_offset
26945 + info->total_size - frame_off) > 32767))
26947 int sel = SAVRES_SAVE | SAVRES_VR;
26948 unsigned ptr_regno = ptr_regno_for_savres (sel);
26950 if (using_static_chain_p
26951 && ptr_regno == STATIC_CHAIN_REGNUM)
26953 if (REGNO (frame_reg_rtx) != ptr_regno)
26954 START_USE (ptr_regno);
26955 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26956 frame_reg_rtx = ptr_reg;
26957 ptr_off = info->altivec_save_offset + info->altivec_size;
26958 frame_off = -ptr_off;
26960 else if (REGNO (frame_reg_rtx) == 1)
26961 frame_off = info->total_size;
26962 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26964 if (REGNO (frame_reg_rtx) == 12)
26966 sp_off = info->total_size;
26967 if (frame_reg_rtx != sp_reg_rtx)
26968 rs6000_emit_stack_tie (frame_reg_rtx, false);
26971 /* Set frame pointer, if needed. */
26972 if (frame_pointer_needed)
26974 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
26976 RTX_FRAME_RELATED_P (insn) = 1;
26979 /* Save AltiVec registers if needed. Save here because the red zone does
26980 not always include AltiVec registers. */
26981 if (!WORLD_SAVE_P (info)
26982 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
26984 int end_save = info->altivec_save_offset + info->altivec_size;
26986 /* Oddly, the vector save/restore functions point r0 at the end
26987 of the save area, then use r11 or r12 to load offsets for
26988 [reg+reg] addressing. */
26989 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
26990 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
26991 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
26993 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
26995 if (scratch_regno == 12)
26997 if (end_save + frame_off != 0)
26999 rtx offset = GEN_INT (end_save + frame_off);
27001 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27004 emit_move_insn (ptr_reg, frame_reg_rtx);
27006 ptr_off = -end_save;
27007 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27008 info->altivec_save_offset + ptr_off,
27009 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27010 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27011 NULL_RTX, NULL_RTX);
27012 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27014 /* The oddity mentioned above clobbered our frame reg. */
27015 emit_move_insn (frame_reg_rtx, ptr_reg);
27016 frame_off = ptr_off;
27019 else if (!WORLD_SAVE_P (info)
27020 && info->altivec_size != 0)
27024 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27025 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27027 rtx areg, savereg, mem;
27028 HOST_WIDE_INT offset;
27030 offset = (info->altivec_save_offset + frame_off
27031 + 16 * (i - info->first_altivec_reg_save));
27033 savereg = gen_rtx_REG (V4SImode, i);
27035 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27037 mem = gen_frame_mem (V4SImode,
27038 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27039 GEN_INT (offset)));
27040 insn = emit_insn (gen_rtx_SET (mem, savereg));
27046 areg = gen_rtx_REG (Pmode, 0);
27047 emit_move_insn (areg, GEN_INT (offset));
27049 /* AltiVec addressing mode is [reg+reg]. */
27050 mem = gen_frame_mem (V4SImode,
27051 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27053 /* Rather than emitting a generic move, force use of the stvx
27054 instruction, which we always want on ISA 2.07 (power8) systems.
27055 In particular we don't want xxpermdi/stxvd2x for little
27057 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27060 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27061 areg, GEN_INT (offset));
27065 /* VRSAVE is a bit vector representing which AltiVec registers
27066 are used. The OS uses this to determine which vector
27067 registers to save on a context switch. We need to save
27068 VRSAVE on the stack frame, add whatever AltiVec registers we
27069 used in this function, and do the corresponding magic in the
27072 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27074 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27075 be using r12 as frame_reg_rtx and r11 as the static chain
27076 pointer for nested functions. */
27077 int save_regno = 12;
27078 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27079 && !using_static_chain_p)
27081 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27084 if (using_static_chain_p)
27087 NOT_INUSE (save_regno);
27089 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27092 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27093 if (!TARGET_SINGLE_PIC_BASE
27094 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27095 && !constant_pool_empty_p ())
27096 || (DEFAULT_ABI == ABI_V4
27097 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27098 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27100 /* If emit_load_toc_table will use the link register, we need to save
27101 it. We use R12 for this purpose because emit_load_toc_table
27102 can use register 0. This allows us to use a plain 'blr' to return
27103 from the procedure more often. */
27104 int save_LR_around_toc_setup = (TARGET_ELF
27105 && DEFAULT_ABI == ABI_V4
27107 && ! info->lr_save_p
27108 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27109 if (save_LR_around_toc_setup)
27111 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27112 rtx tmp = gen_rtx_REG (Pmode, 12);
27115 insn = emit_move_insn (tmp, lr);
27116 RTX_FRAME_RELATED_P (insn) = 1;
27118 rs6000_emit_load_toc_table (TRUE);
27120 insn = emit_move_insn (lr, tmp);
27121 add_reg_note (insn, REG_CFA_RESTORE, lr);
27122 RTX_FRAME_RELATED_P (insn) = 1;
27125 rs6000_emit_load_toc_table (TRUE);
27129 if (!TARGET_SINGLE_PIC_BASE
27130 && DEFAULT_ABI == ABI_DARWIN
27131 && flag_pic && crtl->uses_pic_offset_table)
27133 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27134 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27136 /* Save and restore LR locally around this call (in R0). */
27137 if (!info->lr_save_p)
27138 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27140 emit_insn (gen_load_macho_picbase (src));
27142 emit_move_insn (gen_rtx_REG (Pmode,
27143 RS6000_PIC_OFFSET_TABLE_REGNUM),
27146 if (!info->lr_save_p)
27147 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27151 /* If we need to, save the TOC register after doing the stack setup.
27152 Do not emit eh frame info for this save. The unwinder wants info,
27153 conceptually attached to instructions in this function, about
27154 register values in the caller of this function. This R2 may have
27155 already been changed from the value in the caller.
27156 We don't attempt to write accurate DWARF EH frame info for R2
27157 because code emitted by gcc for a (non-pointer) function call
27158 doesn't save and restore R2. Instead, R2 is managed out-of-line
27159 by a linker generated plt call stub when the function resides in
27160 a shared library. This behavior is costly to describe in DWARF,
27161 both in terms of the size of DWARF info and the time taken in the
27162 unwinder to interpret it. R2 changes, apart from the
27163 calls_eh_return case earlier in this function, are handled by
27164 linux-unwind.h frob_update_context. */
27165 if (rs6000_save_toc_in_prologue_p ()
27166 && !cfun->machine->toc_is_wrapped_separately)
27168 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27169 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27172 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27173 if (using_split_stack && split_stack_arg_pointer_used_p ())
27174 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27177 /* Output .extern statements for the save/restore routines we use. */
27180 rs6000_output_savres_externs (FILE *file)
27182 rs6000_stack_t *info = rs6000_stack_info ();
27184 if (TARGET_DEBUG_STACK)
27185 debug_stack_info (info);
27187 /* Write .extern for any function we will call to save and restore
27189 if (info->first_fp_reg_save < 64
27194 int regno = info->first_fp_reg_save - 32;
27196 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27198 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27199 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27200 name = rs6000_savres_routine_name (regno, sel);
27201 fprintf (file, "\t.extern %s\n", name);
27203 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27205 bool lr = (info->savres_strategy
27206 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27207 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27208 name = rs6000_savres_routine_name (regno, sel);
27209 fprintf (file, "\t.extern %s\n", name);
27214 /* Write function prologue. */
27217 rs6000_output_function_prologue (FILE *file)
27219 if (!cfun->is_thunk)
27220 rs6000_output_savres_externs (file);
27222 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27223 immediately after the global entry point label. */
27224 if (rs6000_global_entry_point_needed_p ())
27226 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27228 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27230 if (TARGET_CMODEL != CMODEL_LARGE)
27232 /* In the small and medium code models, we assume the TOC is less
27233 2 GB away from the text section, so it can be computed via the
27234 following two-instruction sequence. */
27237 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27238 fprintf (file, "0:\taddis 2,12,.TOC.-");
27239 assemble_name (file, buf);
27240 fprintf (file, "@ha\n");
27241 fprintf (file, "\taddi 2,2,.TOC.-");
27242 assemble_name (file, buf);
27243 fprintf (file, "@l\n");
27247 /* In the large code model, we allow arbitrary offsets between the
27248 TOC and the text section, so we have to load the offset from
27249 memory. The data field is emitted directly before the global
27250 entry point in rs6000_elf_declare_function_name. */
27253 #ifdef HAVE_AS_ENTRY_MARKERS
27254 /* If supported by the linker, emit a marker relocation. If the
27255 total code size of the final executable or shared library
27256 happens to fit into 2 GB after all, the linker will replace
27257 this code sequence with the sequence for the small or medium
27259 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27261 fprintf (file, "\tld 2,");
27262 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27263 assemble_name (file, buf);
27264 fprintf (file, "-");
27265 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27266 assemble_name (file, buf);
27267 fprintf (file, "(12)\n");
27268 fprintf (file, "\tadd 2,2,12\n");
27271 fputs ("\t.localentry\t", file);
27272 assemble_name (file, name);
27273 fputs (",.-", file);
27274 assemble_name (file, name);
27275 fputs ("\n", file);
27278 /* Output -mprofile-kernel code. This needs to be done here instead of
27279 in output_function_profile since it must go after the ELFv2 ABI
27280 local entry point. */
27281 if (TARGET_PROFILE_KERNEL && crtl->profile)
27283 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27284 gcc_assert (!TARGET_32BIT);
27286 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27288 /* In the ELFv2 ABI we have no compiler stack word. It must be
27289 the resposibility of _mcount to preserve the static chain
27290 register if required. */
27291 if (DEFAULT_ABI != ABI_ELFv2
27292 && cfun->static_chain_decl != NULL)
27294 asm_fprintf (file, "\tstd %s,24(%s)\n",
27295 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27296 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27297 asm_fprintf (file, "\tld %s,24(%s)\n",
27298 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27301 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27304 rs6000_pic_labelno++;
27307 /* -mprofile-kernel code calls mcount before the function prolog,
27308 so a profiled leaf function should stay a leaf function. */
27310 rs6000_keep_leaf_when_profiled ()
27312 return TARGET_PROFILE_KERNEL;
27315 /* Non-zero if vmx regs are restored before the frame pop, zero if
27316 we restore after the pop when possible. */
27317 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27319 /* Restoring cr is a two step process: loading a reg from the frame
27320 save, then moving the reg to cr. For ABI_V4 we must let the
27321 unwinder know that the stack location is no longer valid at or
27322 before the stack deallocation, but we can't emit a cfa_restore for
27323 cr at the stack deallocation like we do for other registers.
27324 The trouble is that it is possible for the move to cr to be
27325 scheduled after the stack deallocation. So say exactly where cr
27326 is located on each of the two insns. */
27329 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27331 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27332 rtx reg = gen_rtx_REG (SImode, regno);
27333 rtx_insn *insn = emit_move_insn (reg, mem);
27335 if (!exit_func && DEFAULT_ABI == ABI_V4)
27337 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27338 rtx set = gen_rtx_SET (reg, cr);
27340 add_reg_note (insn, REG_CFA_REGISTER, set);
27341 RTX_FRAME_RELATED_P (insn) = 1;
27346 /* Reload CR from REG. */
27349 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
27354 if (using_mfcr_multiple)
27356 for (i = 0; i < 8; i++)
27357 if (save_reg_p (CR0_REGNO + i))
27359 gcc_assert (count);
27362 if (using_mfcr_multiple && count > 1)
27368 p = rtvec_alloc (count);
27371 for (i = 0; i < 8; i++)
27372 if (save_reg_p (CR0_REGNO + i))
27374 rtvec r = rtvec_alloc (2);
27375 RTVEC_ELT (r, 0) = reg;
27376 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27377 RTVEC_ELT (p, ndx) =
27378 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27379 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27382 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27383 gcc_assert (ndx == count);
27385 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27386 CR field separately. */
27387 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27389 for (i = 0; i < 8; i++)
27390 if (save_reg_p (CR0_REGNO + i))
27391 add_reg_note (insn, REG_CFA_RESTORE,
27392 gen_rtx_REG (SImode, CR0_REGNO + i));
27394 RTX_FRAME_RELATED_P (insn) = 1;
27398 for (i = 0; i < 8; i++)
27399 if (save_reg_p (CR0_REGNO + i))
27401 rtx insn = emit_insn (gen_movsi_to_cr_one
27402 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27404 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27405 CR field separately, attached to the insn that in fact
27406 restores this particular CR field. */
27407 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27409 add_reg_note (insn, REG_CFA_RESTORE,
27410 gen_rtx_REG (SImode, CR0_REGNO + i));
27412 RTX_FRAME_RELATED_P (insn) = 1;
27416 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27417 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27418 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27420 rtx_insn *insn = get_last_insn ();
27421 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27423 add_reg_note (insn, REG_CFA_RESTORE, cr);
27424 RTX_FRAME_RELATED_P (insn) = 1;
27428 /* Like cr, the move to lr instruction can be scheduled after the
27429 stack deallocation, but unlike cr, its stack frame save is still
27430 valid. So we only need to emit the cfa_restore on the correct
27434 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27436 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27437 rtx reg = gen_rtx_REG (Pmode, regno);
27439 emit_move_insn (reg, mem);
27443 restore_saved_lr (int regno, bool exit_func)
27445 rtx reg = gen_rtx_REG (Pmode, regno);
27446 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27447 rtx_insn *insn = emit_move_insn (lr, reg);
27449 if (!exit_func && flag_shrink_wrap)
27451 add_reg_note (insn, REG_CFA_RESTORE, lr);
27452 RTX_FRAME_RELATED_P (insn) = 1;
27457 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27459 if (DEFAULT_ABI == ABI_ELFv2)
27462 for (i = 0; i < 8; i++)
27463 if (save_reg_p (CR0_REGNO + i))
27465 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27466 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27470 else if (info->cr_save_p)
27471 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27472 gen_rtx_REG (SImode, CR2_REGNO),
27475 if (info->lr_save_p)
27476 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27477 gen_rtx_REG (Pmode, LR_REGNO),
27479 return cfa_restores;
27482 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27483 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27484 below stack pointer not cloberred by signals. */
27487 offset_below_red_zone_p (HOST_WIDE_INT offset)
27489 return offset < (DEFAULT_ABI == ABI_V4
27491 : TARGET_32BIT ? -220 : -288);
27494 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27497 emit_cfa_restores (rtx cfa_restores)
27499 rtx_insn *insn = get_last_insn ();
27500 rtx *loc = ®_NOTES (insn);
27503 loc = &XEXP (*loc, 1);
27504 *loc = cfa_restores;
27505 RTX_FRAME_RELATED_P (insn) = 1;
27508 /* Emit function epilogue as insns. */
27511 rs6000_emit_epilogue (int sibcall)
27513 rs6000_stack_t *info;
27514 int restoring_GPRs_inline;
27515 int restoring_FPRs_inline;
27516 int using_load_multiple;
27517 int using_mtcr_multiple;
27518 int use_backchain_to_restore_sp;
27521 HOST_WIDE_INT frame_off = 0;
27522 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27523 rtx frame_reg_rtx = sp_reg_rtx;
27524 rtx cfa_restores = NULL_RTX;
27526 rtx cr_save_reg = NULL_RTX;
27527 machine_mode reg_mode = Pmode;
27528 int reg_size = TARGET_32BIT ? 4 : 8;
27529 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27530 int fp_reg_size = 8;
27533 unsigned ptr_regno;
27535 info = rs6000_stack_info ();
27537 strategy = info->savres_strategy;
27538 using_load_multiple = strategy & REST_MULTIPLE;
27539 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
27540 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
27541 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27542 || rs6000_tune == PROCESSOR_PPC603
27543 || rs6000_tune == PROCESSOR_PPC750
27545 /* Restore via the backchain when we have a large frame, since this
27546 is more efficient than an addis, addi pair. The second condition
27547 here will not trigger at the moment; We don't actually need a
27548 frame pointer for alloca, but the generic parts of the compiler
27549 give us one anyway. */
27550 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
27551 ? info->lr_save_offset
27553 || (cfun->calls_alloca
27554 && !frame_pointer_needed));
27555 restore_lr = (info->lr_save_p
27556 && (restoring_FPRs_inline
27557 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27558 && (restoring_GPRs_inline
27559 || info->first_fp_reg_save < 64)
27560 && !cfun->machine->lr_is_wrapped_separately);
27563 if (WORLD_SAVE_P (info))
27567 const char *alloc_rname;
27570 /* eh_rest_world_r10 will return to the location saved in the LR
27571 stack slot (which is not likely to be our caller.)
27572 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27573 rest_world is similar, except any R10 parameter is ignored.
27574 The exception-handling stuff that was here in 2.95 is no
27575 longer necessary. */
27578 + 32 - info->first_gp_reg_save
27579 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27580 + 63 + 1 - info->first_fp_reg_save);
27582 strcpy (rname, ((crtl->calls_eh_return) ?
27583 "*eh_rest_world_r10" : "*rest_world"));
27584 alloc_rname = ggc_strdup (rname);
27587 RTVEC_ELT (p, j++) = ret_rtx;
27589 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
27590 /* The instruction pattern requires a clobber here;
27591 it is shared with the restVEC helper. */
27593 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
27596 /* CR register traditionally saved as CR2. */
27597 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27599 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27600 if (flag_shrink_wrap)
27602 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27603 gen_rtx_REG (Pmode, LR_REGNO),
27605 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27609 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27611 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27613 = gen_frame_load (reg,
27614 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27615 if (flag_shrink_wrap
27616 && save_reg_p (info->first_gp_reg_save + i))
27617 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27619 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27621 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27623 = gen_frame_load (reg,
27624 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27625 if (flag_shrink_wrap
27626 && save_reg_p (info->first_altivec_reg_save + i))
27627 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27629 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27631 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27632 info->first_fp_reg_save + i);
27634 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27635 if (flag_shrink_wrap
27636 && save_reg_p (info->first_fp_reg_save + i))
27637 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27640 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
27642 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
27644 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
27646 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
27648 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27649 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27651 if (flag_shrink_wrap)
27653 REG_NOTES (insn) = cfa_restores;
27654 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27655 RTX_FRAME_RELATED_P (insn) = 1;
27660 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27662 frame_off = info->total_size;
27664 /* Restore AltiVec registers if we must do so before adjusting the
27666 if (info->altivec_size != 0
27667 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27668 || (DEFAULT_ABI != ABI_V4
27669 && offset_below_red_zone_p (info->altivec_save_offset))))
27672 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27674 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27675 if (use_backchain_to_restore_sp)
27677 int frame_regno = 11;
27679 if ((strategy & REST_INLINE_VRS) == 0)
27681 /* Of r11 and r12, select the one not clobbered by an
27682 out-of-line restore function for the frame register. */
27683 frame_regno = 11 + 12 - scratch_regno;
27685 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
27686 emit_move_insn (frame_reg_rtx,
27687 gen_rtx_MEM (Pmode, sp_reg_rtx));
27690 else if (frame_pointer_needed)
27691 frame_reg_rtx = hard_frame_pointer_rtx;
27693 if ((strategy & REST_INLINE_VRS) == 0)
27695 int end_save = info->altivec_save_offset + info->altivec_size;
27697 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27698 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27700 if (end_save + frame_off != 0)
27702 rtx offset = GEN_INT (end_save + frame_off);
27704 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27707 emit_move_insn (ptr_reg, frame_reg_rtx);
27709 ptr_off = -end_save;
27710 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27711 info->altivec_save_offset + ptr_off,
27712 0, V4SImode, SAVRES_VR);
27716 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27717 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27719 rtx addr, areg, mem, insn;
27720 rtx reg = gen_rtx_REG (V4SImode, i);
27721 HOST_WIDE_INT offset
27722 = (info->altivec_save_offset + frame_off
27723 + 16 * (i - info->first_altivec_reg_save));
27725 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27727 mem = gen_frame_mem (V4SImode,
27728 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27729 GEN_INT (offset)));
27730 insn = gen_rtx_SET (reg, mem);
27734 areg = gen_rtx_REG (Pmode, 0);
27735 emit_move_insn (areg, GEN_INT (offset));
27737 /* AltiVec addressing mode is [reg+reg]. */
27738 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
27739 mem = gen_frame_mem (V4SImode, addr);
27741 /* Rather than emitting a generic move, force use of the
27742 lvx instruction, which we always want. In particular we
27743 don't want lxvd2x/xxpermdi for little endian. */
27744 insn = gen_altivec_lvx_v4si_internal (reg, mem);
27747 (void) emit_insn (insn);
27751 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27752 if (((strategy & REST_INLINE_VRS) == 0
27753 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
27754 && (flag_shrink_wrap
27755 || (offset_below_red_zone_p
27756 (info->altivec_save_offset
27757 + 16 * (i - info->first_altivec_reg_save))))
27760 rtx reg = gen_rtx_REG (V4SImode, i);
27761 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27765 /* Restore VRSAVE if we must do so before adjusting the stack. */
27766 if (info->vrsave_size != 0
27767 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27768 || (DEFAULT_ABI != ABI_V4
27769 && offset_below_red_zone_p (info->vrsave_save_offset))))
27773 if (frame_reg_rtx == sp_reg_rtx)
27775 if (use_backchain_to_restore_sp)
27777 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27778 emit_move_insn (frame_reg_rtx,
27779 gen_rtx_MEM (Pmode, sp_reg_rtx));
27782 else if (frame_pointer_needed)
27783 frame_reg_rtx = hard_frame_pointer_rtx;
27786 reg = gen_rtx_REG (SImode, 12);
27787 emit_insn (gen_frame_load (reg, frame_reg_rtx,
27788 info->vrsave_save_offset + frame_off));
27790 emit_insn (generate_set_vrsave (reg, info, 1));
27794 /* If we have a large stack frame, restore the old stack pointer
27795 using the backchain. */
27796 if (use_backchain_to_restore_sp)
27798 if (frame_reg_rtx == sp_reg_rtx)
27800 /* Under V.4, don't reset the stack pointer until after we're done
27801 loading the saved registers. */
27802 if (DEFAULT_ABI == ABI_V4)
27803 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27805 insn = emit_move_insn (frame_reg_rtx,
27806 gen_rtx_MEM (Pmode, sp_reg_rtx));
27809 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27810 && DEFAULT_ABI == ABI_V4)
27811 /* frame_reg_rtx has been set up by the altivec restore. */
27815 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
27816 frame_reg_rtx = sp_reg_rtx;
27819 /* If we have a frame pointer, we can restore the old stack pointer
27821 else if (frame_pointer_needed)
27823 frame_reg_rtx = sp_reg_rtx;
27824 if (DEFAULT_ABI == ABI_V4)
27825 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27826 /* Prevent reordering memory accesses against stack pointer restore. */
27827 else if (cfun->calls_alloca
27828 || offset_below_red_zone_p (-info->total_size))
27829 rs6000_emit_stack_tie (frame_reg_rtx, true);
27831 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
27832 GEN_INT (info->total_size)));
27835 else if (info->push_p
27836 && DEFAULT_ABI != ABI_V4
27837 && !crtl->calls_eh_return)
27839 /* Prevent reordering memory accesses against stack pointer restore. */
27840 if (cfun->calls_alloca
27841 || offset_below_red_zone_p (-info->total_size))
27842 rs6000_emit_stack_tie (frame_reg_rtx, false);
27843 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
27844 GEN_INT (info->total_size)));
27847 if (insn && frame_reg_rtx == sp_reg_rtx)
27851 REG_NOTES (insn) = cfa_restores;
27852 cfa_restores = NULL_RTX;
27854 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27855 RTX_FRAME_RELATED_P (insn) = 1;
27858 /* Restore AltiVec registers if we have not done so already. */
27859 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27860 && info->altivec_size != 0
27861 && (DEFAULT_ABI == ABI_V4
27862 || !offset_below_red_zone_p (info->altivec_save_offset)))
27866 if ((strategy & REST_INLINE_VRS) == 0)
27868 int end_save = info->altivec_save_offset + info->altivec_size;
27870 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27871 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27872 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27874 if (end_save + frame_off != 0)
27876 rtx offset = GEN_INT (end_save + frame_off);
27878 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27881 emit_move_insn (ptr_reg, frame_reg_rtx);
27883 ptr_off = -end_save;
27884 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27885 info->altivec_save_offset + ptr_off,
27886 0, V4SImode, SAVRES_VR);
27887 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27889 /* Frame reg was clobbered by out-of-line save. Restore it
27890 from ptr_reg, and if we are calling out-of-line gpr or
27891 fpr restore set up the correct pointer and offset. */
27892 unsigned newptr_regno = 1;
27893 if (!restoring_GPRs_inline)
27895 bool lr = info->gp_save_offset + info->gp_size == 0;
27896 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
27897 newptr_regno = ptr_regno_for_savres (sel);
27898 end_save = info->gp_save_offset + info->gp_size;
27900 else if (!restoring_FPRs_inline)
27902 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
27903 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27904 newptr_regno = ptr_regno_for_savres (sel);
27905 end_save = info->fp_save_offset + info->fp_size;
27908 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
27909 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
27911 if (end_save + ptr_off != 0)
27913 rtx offset = GEN_INT (end_save + ptr_off);
27915 frame_off = -end_save;
27917 emit_insn (gen_addsi3_carry (frame_reg_rtx,
27920 emit_insn (gen_adddi3_carry (frame_reg_rtx,
27925 frame_off = ptr_off;
27926 emit_move_insn (frame_reg_rtx, ptr_reg);
27932 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27933 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27935 rtx addr, areg, mem, insn;
27936 rtx reg = gen_rtx_REG (V4SImode, i);
27937 HOST_WIDE_INT offset
27938 = (info->altivec_save_offset + frame_off
27939 + 16 * (i - info->first_altivec_reg_save));
27941 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27943 mem = gen_frame_mem (V4SImode,
27944 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27945 GEN_INT (offset)));
27946 insn = gen_rtx_SET (reg, mem);
27950 areg = gen_rtx_REG (Pmode, 0);
27951 emit_move_insn (areg, GEN_INT (offset));
27953 /* AltiVec addressing mode is [reg+reg]. */
27954 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
27955 mem = gen_frame_mem (V4SImode, addr);
27957 /* Rather than emitting a generic move, force use of the
27958 lvx instruction, which we always want. In particular we
27959 don't want lxvd2x/xxpermdi for little endian. */
27960 insn = gen_altivec_lvx_v4si_internal (reg, mem);
27963 (void) emit_insn (insn);
27967 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27968 if (((strategy & REST_INLINE_VRS) == 0
27969 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
27970 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
27973 rtx reg = gen_rtx_REG (V4SImode, i);
27974 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27978 /* Restore VRSAVE if we have not done so already. */
27979 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27980 && info->vrsave_size != 0
27981 && (DEFAULT_ABI == ABI_V4
27982 || !offset_below_red_zone_p (info->vrsave_save_offset)))
27986 reg = gen_rtx_REG (SImode, 12);
27987 emit_insn (gen_frame_load (reg, frame_reg_rtx,
27988 info->vrsave_save_offset + frame_off));
27990 emit_insn (generate_set_vrsave (reg, info, 1));
27993 /* If we exit by an out-of-line restore function on ABI_V4 then that
27994 function will deallocate the stack, so we don't need to worry
27995 about the unwinder restoring cr from an invalid stack frame
27997 exit_func = (!restoring_FPRs_inline
27998 || (!restoring_GPRs_inline
27999 && info->first_fp_reg_save == 64));
28001 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28002 *separate* slots if the routine calls __builtin_eh_return, so
28003 that they can be independently restored by the unwinder. */
28004 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28006 int i, cr_off = info->ehcr_offset;
28008 for (i = 0; i < 8; i++)
28009 if (!call_used_regs[CR0_REGNO + i])
28011 rtx reg = gen_rtx_REG (SImode, 0);
28012 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28013 cr_off + frame_off));
28015 insn = emit_insn (gen_movsi_to_cr_one
28016 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28018 if (!exit_func && flag_shrink_wrap)
28020 add_reg_note (insn, REG_CFA_RESTORE,
28021 gen_rtx_REG (SImode, CR0_REGNO + i));
28023 RTX_FRAME_RELATED_P (insn) = 1;
28026 cr_off += reg_size;
28030 /* Get the old lr if we saved it. If we are restoring registers
28031 out-of-line, then the out-of-line routines can do this for us. */
28032 if (restore_lr && restoring_GPRs_inline)
28033 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28035 /* Get the old cr if we saved it. */
28036 if (info->cr_save_p)
28038 unsigned cr_save_regno = 12;
28040 if (!restoring_GPRs_inline)
28042 /* Ensure we don't use the register used by the out-of-line
28043 gpr register restore below. */
28044 bool lr = info->gp_save_offset + info->gp_size == 0;
28045 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28046 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28048 if (gpr_ptr_regno == 12)
28049 cr_save_regno = 11;
28050 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28052 else if (REGNO (frame_reg_rtx) == 12)
28053 cr_save_regno = 11;
28055 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28056 info->cr_save_offset + frame_off,
28060 /* Set LR here to try to overlap restores below. */
28061 if (restore_lr && restoring_GPRs_inline)
28062 restore_saved_lr (0, exit_func);
28064 /* Load exception handler data registers, if needed. */
28065 if (crtl->calls_eh_return)
28067 unsigned int i, regno;
28071 rtx reg = gen_rtx_REG (reg_mode, 2);
28072 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28073 frame_off + RS6000_TOC_SAVE_SLOT));
28080 regno = EH_RETURN_DATA_REGNO (i);
28081 if (regno == INVALID_REGNUM)
28084 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28085 info->ehrd_offset + frame_off
28086 + reg_size * (int) i);
28088 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28092 /* Restore GPRs. This is done as a PARALLEL if we are using
28093 the load-multiple instructions. */
28094 if (!restoring_GPRs_inline)
28096 /* We are jumping to an out-of-line function. */
28098 int end_save = info->gp_save_offset + info->gp_size;
28099 bool can_use_exit = end_save == 0;
28100 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28103 /* Emit stack reset code if we need it. */
28104 ptr_regno = ptr_regno_for_savres (sel);
28105 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28107 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28108 else if (end_save + frame_off != 0)
28109 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28110 GEN_INT (end_save + frame_off)));
28111 else if (REGNO (frame_reg_rtx) != ptr_regno)
28112 emit_move_insn (ptr_reg, frame_reg_rtx);
28113 if (REGNO (frame_reg_rtx) == ptr_regno)
28114 frame_off = -end_save;
28116 if (can_use_exit && info->cr_save_p)
28117 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28119 ptr_off = -end_save;
28120 rs6000_emit_savres_rtx (info, ptr_reg,
28121 info->gp_save_offset + ptr_off,
28122 info->lr_save_offset + ptr_off,
28125 else if (using_load_multiple)
28128 p = rtvec_alloc (32 - info->first_gp_reg_save);
28129 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28131 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28133 info->gp_save_offset + frame_off + reg_size * i);
28134 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28138 int offset = info->gp_save_offset + frame_off;
28139 for (i = info->first_gp_reg_save; i < 32; i++)
28142 && !cfun->machine->gpr_is_wrapped_separately[i])
28144 rtx reg = gen_rtx_REG (reg_mode, i);
28145 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28148 offset += reg_size;
28152 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28154 /* If the frame pointer was used then we can't delay emitting
28155 a REG_CFA_DEF_CFA note. This must happen on the insn that
28156 restores the frame pointer, r31. We may have already emitted
28157 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28158 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28159 be harmless if emitted. */
28160 if (frame_pointer_needed)
28162 insn = get_last_insn ();
28163 add_reg_note (insn, REG_CFA_DEF_CFA,
28164 plus_constant (Pmode, frame_reg_rtx, frame_off));
28165 RTX_FRAME_RELATED_P (insn) = 1;
28168 /* Set up cfa_restores. We always need these when
28169 shrink-wrapping. If not shrink-wrapping then we only need
28170 the cfa_restore when the stack location is no longer valid.
28171 The cfa_restores must be emitted on or before the insn that
28172 invalidates the stack, and of course must not be emitted
28173 before the insn that actually does the restore. The latter
28174 is why it is a bad idea to emit the cfa_restores as a group
28175 on the last instruction here that actually does a restore:
28176 That insn may be reordered with respect to others doing
28178 if (flag_shrink_wrap
28179 && !restoring_GPRs_inline
28180 && info->first_fp_reg_save == 64)
28181 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28183 for (i = info->first_gp_reg_save; i < 32; i++)
28185 && !cfun->machine->gpr_is_wrapped_separately[i])
28187 rtx reg = gen_rtx_REG (reg_mode, i);
28188 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28192 if (!restoring_GPRs_inline
28193 && info->first_fp_reg_save == 64)
28195 /* We are jumping to an out-of-line function. */
28197 emit_cfa_restores (cfa_restores);
28201 if (restore_lr && !restoring_GPRs_inline)
28203 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28204 restore_saved_lr (0, exit_func);
28207 /* Restore fpr's if we need to do it without calling a function. */
28208 if (restoring_FPRs_inline)
28210 int offset = info->fp_save_offset + frame_off;
28211 for (i = info->first_fp_reg_save; i < 64; i++)
28214 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28216 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28217 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28218 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28219 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28223 offset += fp_reg_size;
28227 /* If we saved cr, restore it here. Just those that were used. */
28228 if (info->cr_save_p)
28229 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28231 /* If this is V.4, unwind the stack pointer after all of the loads
28232 have been done, or set up r11 if we are restoring fp out of line. */
28234 if (!restoring_FPRs_inline)
28236 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28237 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28238 ptr_regno = ptr_regno_for_savres (sel);
28241 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28242 if (REGNO (frame_reg_rtx) == ptr_regno)
28245 if (insn && restoring_FPRs_inline)
28249 REG_NOTES (insn) = cfa_restores;
28250 cfa_restores = NULL_RTX;
28252 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28253 RTX_FRAME_RELATED_P (insn) = 1;
28256 if (crtl->calls_eh_return)
28258 rtx sa = EH_RETURN_STACKADJ_RTX;
28259 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28262 if (!sibcall && restoring_FPRs_inline)
28266 /* We can't hang the cfa_restores off a simple return,
28267 since the shrink-wrap code sometimes uses an existing
28268 return. This means there might be a path from
28269 pre-prologue code to this return, and dwarf2cfi code
28270 wants the eh_frame unwinder state to be the same on
28271 all paths to any point. So we need to emit the
28272 cfa_restores before the return. For -m64 we really
28273 don't need epilogue cfa_restores at all, except for
28274 this irritating dwarf2cfi with shrink-wrap
28275 requirement; The stack red-zone means eh_frame info
28276 from the prologue telling the unwinder to restore
28277 from the stack is perfectly good right to the end of
28279 emit_insn (gen_blockage ());
28280 emit_cfa_restores (cfa_restores);
28281 cfa_restores = NULL_RTX;
28284 emit_jump_insn (targetm.gen_simple_return ());
28287 if (!sibcall && !restoring_FPRs_inline)
28289 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28290 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28292 RTVEC_ELT (p, elt++) = ret_rtx;
28294 RTVEC_ELT (p, elt++)
28295 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
28297 /* We have to restore more than two FP registers, so branch to the
28298 restore function. It will return to our caller. */
28303 if (flag_shrink_wrap)
28304 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28306 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28307 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28308 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28309 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28311 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28313 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28315 RTVEC_ELT (p, elt++)
28316 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28317 if (flag_shrink_wrap
28318 && save_reg_p (info->first_fp_reg_save + i))
28319 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28322 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28328 /* Ensure the cfa_restores are hung off an insn that won't
28329 be reordered above other restores. */
28330 emit_insn (gen_blockage ());
28332 emit_cfa_restores (cfa_restores);
28336 /* Write function epilogue. */
28339 rs6000_output_function_epilogue (FILE *file)
28342 macho_branch_islands ();
28345 rtx_insn *insn = get_last_insn ();
28346 rtx_insn *deleted_debug_label = NULL;
28348 /* Mach-O doesn't support labels at the end of objects, so if
28349 it looks like we might want one, take special action.
28351 First, collect any sequence of deleted debug labels. */
28354 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28356 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28357 notes only, instead set their CODE_LABEL_NUMBER to -1,
28358 otherwise there would be code generation differences
28359 in between -g and -g0. */
28360 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28361 deleted_debug_label = insn;
28362 insn = PREV_INSN (insn);
28365 /* Second, if we have:
28368 then this needs to be detected, so skip past the barrier. */
28370 if (insn && BARRIER_P (insn))
28371 insn = PREV_INSN (insn);
28373 /* Up to now we've only seen notes or barriers. */
28378 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28379 /* Trailing label: <barrier>. */
28380 fputs ("\tnop\n", file);
28383 /* Lastly, see if we have a completely empty function body. */
28384 while (insn && ! INSN_P (insn))
28385 insn = PREV_INSN (insn);
28386 /* If we don't find any insns, we've got an empty function body;
28387 I.e. completely empty - without a return or branch. This is
28388 taken as the case where a function body has been removed
28389 because it contains an inline __builtin_unreachable(). GCC
28390 states that reaching __builtin_unreachable() means UB so we're
28391 not obliged to do anything special; however, we want
28392 non-zero-sized function bodies. To meet this, and help the
28393 user out, let's trap the case. */
28395 fputs ("\ttrap\n", file);
28398 else if (deleted_debug_label)
28399 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28400 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28401 CODE_LABEL_NUMBER (insn) = -1;
28405 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28408 We don't output a traceback table if -finhibit-size-directive was
28409 used. The documentation for -finhibit-size-directive reads
28410 ``don't output a @code{.size} assembler directive, or anything
28411 else that would cause trouble if the function is split in the
28412 middle, and the two halves are placed at locations far apart in
28413 memory.'' The traceback table has this property, since it
28414 includes the offset from the start of the function to the
28415 traceback table itself.
28417 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28418 different traceback table. */
28419 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28420 && ! flag_inhibit_size_directive
28421 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28423 const char *fname = NULL;
28424 const char *language_string = lang_hooks.name;
28425 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28427 int optional_tbtab;
28428 rs6000_stack_t *info = rs6000_stack_info ();
28430 if (rs6000_traceback == traceback_full)
28431 optional_tbtab = 1;
28432 else if (rs6000_traceback == traceback_part)
28433 optional_tbtab = 0;
28435 optional_tbtab = !optimize_size && !TARGET_ELF;
28437 if (optional_tbtab)
28439 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28440 while (*fname == '.') /* V.4 encodes . in the name */
28443 /* Need label immediately before tbtab, so we can compute
28444 its offset from the function start. */
28445 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28446 ASM_OUTPUT_LABEL (file, fname);
28449 /* The .tbtab pseudo-op can only be used for the first eight
28450 expressions, since it can't handle the possibly variable
28451 length fields that follow. However, if you omit the optional
28452 fields, the assembler outputs zeros for all optional fields
28453 anyways, giving each variable length field is minimum length
28454 (as defined in sys/debug.h). Thus we can not use the .tbtab
28455 pseudo-op at all. */
28457 /* An all-zero word flags the start of the tbtab, for debuggers
28458 that have to find it by searching forward from the entry
28459 point or from the current pc. */
28460 fputs ("\t.long 0\n", file);
28462 /* Tbtab format type. Use format type 0. */
28463 fputs ("\t.byte 0,", file);
28465 /* Language type. Unfortunately, there does not seem to be any
28466 official way to discover the language being compiled, so we
28467 use language_string.
28468 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
28469 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28470 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
28471 either, so for now use 0. */
28473 || ! strcmp (language_string, "GNU GIMPLE")
28474 || ! strcmp (language_string, "GNU Go")
28475 || ! strcmp (language_string, "libgccjit"))
28477 else if (! strcmp (language_string, "GNU F77")
28478 || lang_GNU_Fortran ())
28480 else if (! strcmp (language_string, "GNU Pascal"))
28482 else if (! strcmp (language_string, "GNU Ada"))
28484 else if (lang_GNU_CXX ()
28485 || ! strcmp (language_string, "GNU Objective-C++"))
28487 else if (! strcmp (language_string, "GNU Java"))
28489 else if (! strcmp (language_string, "GNU Objective-C"))
28492 gcc_unreachable ();
28493 fprintf (file, "%d,", i);
28495 /* 8 single bit fields: global linkage (not set for C extern linkage,
28496 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28497 from start of procedure stored in tbtab, internal function, function
28498 has controlled storage, function has no toc, function uses fp,
28499 function logs/aborts fp operations. */
28500 /* Assume that fp operations are used if any fp reg must be saved. */
28501 fprintf (file, "%d,",
28502 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28504 /* 6 bitfields: function is interrupt handler, name present in
28505 proc table, function calls alloca, on condition directives
28506 (controls stack walks, 3 bits), saves condition reg, saves
28508 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28509 set up as a frame pointer, even when there is no alloca call. */
28510 fprintf (file, "%d,",
28511 ((optional_tbtab << 6)
28512 | ((optional_tbtab & frame_pointer_needed) << 5)
28513 | (info->cr_save_p << 1)
28514 | (info->lr_save_p)));
28516 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28518 fprintf (file, "%d,",
28519 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28521 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28522 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28524 if (optional_tbtab)
28526 /* Compute the parameter info from the function decl argument
28529 int next_parm_info_bit = 31;
28531 for (decl = DECL_ARGUMENTS (current_function_decl);
28532 decl; decl = DECL_CHAIN (decl))
28534 rtx parameter = DECL_INCOMING_RTL (decl);
28535 machine_mode mode = GET_MODE (parameter);
28537 if (GET_CODE (parameter) == REG)
28539 if (SCALAR_FLOAT_MODE_P (mode))
28562 gcc_unreachable ();
28565 /* If only one bit will fit, don't or in this entry. */
28566 if (next_parm_info_bit > 0)
28567 parm_info |= (bits << (next_parm_info_bit - 1));
28568 next_parm_info_bit -= 2;
28572 fixed_parms += ((GET_MODE_SIZE (mode)
28573 + (UNITS_PER_WORD - 1))
28575 next_parm_info_bit -= 1;
28581 /* Number of fixed point parameters. */
28582 /* This is actually the number of words of fixed point parameters; thus
28583 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28584 fprintf (file, "%d,", fixed_parms);
28586 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28588 /* This is actually the number of fp registers that hold parameters;
28589 and thus the maximum value is 13. */
28590 /* Set parameters on stack bit if parameters are not in their original
28591 registers, regardless of whether they are on the stack? Xlc
28592 seems to set the bit when not optimizing. */
28593 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28595 if (optional_tbtab)
28597 /* Optional fields follow. Some are variable length. */
28599 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28600 float, 11 double float. */
28601 /* There is an entry for each parameter in a register, in the order
28602 that they occur in the parameter list. Any intervening arguments
28603 on the stack are ignored. If the list overflows a long (max
28604 possible length 34 bits) then completely leave off all elements
28606 /* Only emit this long if there was at least one parameter. */
28607 if (fixed_parms || float_parms)
28608 fprintf (file, "\t.long %d\n", parm_info);
28610 /* Offset from start of code to tb table. */
28611 fputs ("\t.long ", file);
28612 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28613 RS6000_OUTPUT_BASENAME (file, fname);
28615 rs6000_output_function_entry (file, fname);
28618 /* Interrupt handler mask. */
28619 /* Omit this long, since we never set the interrupt handler bit
28622 /* Number of CTL (controlled storage) anchors. */
28623 /* Omit this long, since the has_ctl bit is never set above. */
28625 /* Displacement into stack of each CTL anchor. */
28626 /* Omit this list of longs, because there are no CTL anchors. */
28628 /* Length of function name. */
28631 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28633 /* Function name. */
28634 assemble_string (fname, strlen (fname));
28636 /* Register for alloca automatic storage; this is always reg 31.
28637 Only emit this if the alloca bit was set above. */
28638 if (frame_pointer_needed)
28639 fputs ("\t.byte 31\n", file);
28641 fputs ("\t.align 2\n", file);
28645 /* Arrange to define .LCTOC1 label, if not already done. */
28649 if (!toc_initialized)
28651 switch_to_section (toc_section);
28652 switch_to_section (current_function_section ());
28657 /* -fsplit-stack support. */
28659 /* A SYMBOL_REF for __morestack. */
28660 static GTY(()) rtx morestack_ref;
28663 gen_add3_const (rtx rt, rtx ra, long c)
28666 return gen_adddi3 (rt, ra, GEN_INT (c));
28668 return gen_addsi3 (rt, ra, GEN_INT (c));
28671 /* Emit -fsplit-stack prologue, which goes before the regular function
28672 prologue (at local entry point in the case of ELFv2). */
28675 rs6000_expand_split_stack_prologue (void)
28677 rs6000_stack_t *info = rs6000_stack_info ();
28678 unsigned HOST_WIDE_INT allocate;
28679 long alloc_hi, alloc_lo;
28680 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28683 gcc_assert (flag_split_stack && reload_completed);
28688 if (global_regs[29])
28690 error ("%qs uses register r29", "-fsplit-stack");
28691 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
28692 "conflicts with %qD", global_regs_decl[29]);
28695 allocate = info->total_size;
28696 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
28698 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
28701 if (morestack_ref == NULL_RTX)
28703 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
28704 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
28705 | SYMBOL_FLAG_FUNCTION);
28708 r0 = gen_rtx_REG (Pmode, 0);
28709 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28710 r12 = gen_rtx_REG (Pmode, 12);
28711 emit_insn (gen_load_split_stack_limit (r0));
28712 /* Always emit two insns here to calculate the requested stack,
28713 so that the linker can edit them when adjusting size for calling
28714 non-split-stack code. */
28715 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
28716 alloc_lo = -allocate - alloc_hi;
28719 emit_insn (gen_add3_const (r12, r1, alloc_hi));
28721 emit_insn (gen_add3_const (r12, r12, alloc_lo));
28723 emit_insn (gen_nop ());
28727 emit_insn (gen_add3_const (r12, r1, alloc_lo));
28728 emit_insn (gen_nop ());
28731 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
28732 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
28733 ok_label = gen_label_rtx ();
28734 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28735 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
28736 gen_rtx_LABEL_REF (VOIDmode, ok_label),
28738 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28739 JUMP_LABEL (insn) = ok_label;
28740 /* Mark the jump as very likely to be taken. */
28741 add_reg_br_prob_note (insn, profile_probability::very_likely ());
28743 lr = gen_rtx_REG (Pmode, LR_REGNO);
28744 insn = emit_move_insn (r0, lr);
28745 RTX_FRAME_RELATED_P (insn) = 1;
28746 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
28747 RTX_FRAME_RELATED_P (insn) = 1;
28749 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
28750 const0_rtx, const0_rtx));
28751 call_fusage = NULL_RTX;
28752 use_reg (&call_fusage, r12);
28753 /* Say the call uses r0, even though it doesn't, to stop regrename
28754 from twiddling with the insns saving lr, trashing args for cfun.
28755 The insns restoring lr are similarly protected by making
28756 split_stack_return use r0. */
28757 use_reg (&call_fusage, r0);
28758 add_function_usage_to (insn, call_fusage);
28759 /* Indicate that this function can't jump to non-local gotos. */
28760 make_reg_eh_region_note_nothrow_nononlocal (insn);
28761 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
28762 insn = emit_move_insn (lr, r0);
28763 add_reg_note (insn, REG_CFA_RESTORE, lr);
28764 RTX_FRAME_RELATED_P (insn) = 1;
28765 emit_insn (gen_split_stack_return ());
28767 emit_label (ok_label);
28768 LABEL_NUSES (ok_label) = 1;
28771 /* Return the internal arg pointer used for function incoming
28772 arguments. When -fsplit-stack, the arg pointer is r12 so we need
28773 to copy it to a pseudo in order for it to be preserved over calls
28774 and suchlike. We'd really like to use a pseudo here for the
28775 internal arg pointer but data-flow analysis is not prepared to
28776 accept pseudos as live at the beginning of a function. */
28779 rs6000_internal_arg_pointer (void)
28781 if (flag_split_stack
28782 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
28786 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
28790 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
28791 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
28793 /* Put the pseudo initialization right after the note at the
28794 beginning of the function. */
28795 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
28796 gen_rtx_REG (Pmode, 12));
28797 push_topmost_sequence ();
28798 emit_insn_after (pat, get_insns ());
28799 pop_topmost_sequence ();
28801 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
28802 FIRST_PARM_OFFSET (current_function_decl));
28803 return copy_to_reg (ret);
28805 return virtual_incoming_args_rtx;
28808 /* We may have to tell the dataflow pass that the split stack prologue
28809 is initializing a register. */
28812 rs6000_live_on_entry (bitmap regs)
28814 if (flag_split_stack)
28815 bitmap_set_bit (regs, 12);
28818 /* Emit -fsplit-stack dynamic stack allocation space check. */
28821 rs6000_split_stack_space_check (rtx size, rtx label)
28823 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28824 rtx limit = gen_reg_rtx (Pmode);
28825 rtx requested = gen_reg_rtx (Pmode);
28826 rtx cmp = gen_reg_rtx (CCUNSmode);
28829 emit_insn (gen_load_split_stack_limit (limit));
28830 if (CONST_INT_P (size))
28831 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
28834 size = force_reg (Pmode, size);
28835 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
28837 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
28838 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28839 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
28840 gen_rtx_LABEL_REF (VOIDmode, label),
28842 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28843 JUMP_LABEL (jump) = label;
28846 /* A C compound statement that outputs the assembler code for a thunk
28847 function, used to implement C++ virtual function calls with
28848 multiple inheritance. The thunk acts as a wrapper around a virtual
28849 function, adjusting the implicit object parameter before handing
28850 control off to the real function.
28852 First, emit code to add the integer DELTA to the location that
28853 contains the incoming first argument. Assume that this argument
28854 contains a pointer, and is the one used to pass the `this' pointer
28855 in C++. This is the incoming argument *before* the function
28856 prologue, e.g. `%o0' on a sparc. The addition must preserve the
28857 values of all other incoming arguments.
28859 After the addition, emit code to jump to FUNCTION, which is a
28860 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
28861 not touch the return address. Hence returning from FUNCTION will
28862 return to whoever called the current `thunk'.
28864 The effect must be as if FUNCTION had been called directly with the
28865 adjusted first argument. This macro is responsible for emitting
28866 all of the code for a thunk function; output_function_prologue()
28867 and output_function_epilogue() are not invoked.
28869 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
28870 been extracted from it.) It might possibly be useful on some
28871 targets, but probably not.
28873 If you do not define this macro, the target-independent code in the
28874 C++ frontend will generate a less efficient heavyweight thunk that
28875 calls FUNCTION instead of jumping to it. The generic approach does
28876 not support varargs. */
28879 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
28880 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
28883 rtx this_rtx, funexp;
28886 reload_completed = 1;
28887 epilogue_completed = 1;
28889 /* Mark the end of the (empty) prologue. */
28890 emit_note (NOTE_INSN_PROLOGUE_END);
28892 /* Find the "this" pointer. If the function returns a structure,
28893 the structure return pointer is in r3. */
28894 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
28895 this_rtx = gen_rtx_REG (Pmode, 4);
28897 this_rtx = gen_rtx_REG (Pmode, 3);
28899 /* Apply the constant offset, if required. */
28901 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
28903 /* Apply the offset from the vtable, if required. */
28906 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
28907 rtx tmp = gen_rtx_REG (Pmode, 12);
28909 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
28910 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
28912 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
28913 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
28917 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
28919 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
28921 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
28924 /* Generate a tail call to the target function. */
28925 if (!TREE_USED (function))
28927 assemble_external (function);
28928 TREE_USED (function) = 1;
28930 funexp = XEXP (DECL_RTL (function), 0);
28931 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
28934 if (MACHOPIC_INDIRECT)
28935 funexp = machopic_indirect_call_target (funexp);
28938 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
28939 generate sibcall RTL explicitly. */
28940 insn = emit_call_insn (
28941 gen_rtx_PARALLEL (VOIDmode,
28943 gen_rtx_CALL (VOIDmode,
28944 funexp, const0_rtx),
28945 gen_rtx_USE (VOIDmode, const0_rtx),
28946 simple_return_rtx)));
28947 SIBLING_CALL_P (insn) = 1;
28950 /* Run just enough of rest_of_compilation to get the insns emitted.
28951 There's not really enough bulk here to make other passes such as
28952 instruction scheduling worth while. Note that use_thunk calls
28953 assemble_start_function and assemble_end_function. */
28954 insn = get_insns ();
28955 shorten_branches (insn);
28956 final_start_function (insn, file, 1);
28957 final (insn, file, 1);
28958 final_end_function ();
28960 reload_completed = 0;
28961 epilogue_completed = 0;
28964 /* A quick summary of the various types of 'constant-pool tables'
28967 Target Flags Name One table per
28968 AIX (none) AIX TOC object file
28969 AIX -mfull-toc AIX TOC object file
28970 AIX -mminimal-toc AIX minimal TOC translation unit
28971 SVR4/EABI (none) SVR4 SDATA object file
28972 SVR4/EABI -fpic SVR4 pic object file
28973 SVR4/EABI -fPIC SVR4 PIC translation unit
28974 SVR4/EABI -mrelocatable EABI TOC function
28975 SVR4/EABI -maix AIX TOC object file
28976 SVR4/EABI -maix -mminimal-toc
28977 AIX minimal TOC translation unit
28979 Name Reg. Set by entries contains:
28980 made by addrs? fp? sum?
28982 AIX TOC 2 crt0 as Y option option
28983 AIX minimal TOC 30 prolog gcc Y Y option
28984 SVR4 SDATA 13 crt0 gcc N Y N
28985 SVR4 pic 30 prolog ld Y not yet N
28986 SVR4 PIC 30 prolog gcc Y option option
28987 EABI TOC 30 prolog gcc Y option option
28991 /* Hash functions for the hash table. */
28994 rs6000_hash_constant (rtx k)
28996 enum rtx_code code = GET_CODE (k);
28997 machine_mode mode = GET_MODE (k);
28998 unsigned result = (code << 3) ^ mode;
28999 const char *format;
29002 format = GET_RTX_FORMAT (code);
29003 flen = strlen (format);
29009 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29011 case CONST_WIDE_INT:
29014 flen = CONST_WIDE_INT_NUNITS (k);
29015 for (i = 0; i < flen; i++)
29016 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29021 if (mode != VOIDmode)
29022 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29034 for (; fidx < flen; fidx++)
29035 switch (format[fidx])
29040 const char *str = XSTR (k, fidx);
29041 len = strlen (str);
29042 result = result * 613 + len;
29043 for (i = 0; i < len; i++)
29044 result = result * 613 + (unsigned) str[i];
29049 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29053 result = result * 613 + (unsigned) XINT (k, fidx);
29056 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29057 result = result * 613 + (unsigned) XWINT (k, fidx);
29061 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29062 result = result * 613 + (unsigned) (XWINT (k, fidx)
29069 gcc_unreachable ();
29076 toc_hasher::hash (toc_hash_struct *thc)
29078 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29081 /* Compare H1 and H2 for equivalence. */
29084 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29089 if (h1->key_mode != h2->key_mode)
29092 return rtx_equal_p (r1, r2);
29095 /* These are the names given by the C++ front-end to vtables, and
29096 vtable-like objects. Ideally, this logic should not be here;
29097 instead, there should be some programmatic way of inquiring as
29098 to whether or not an object is a vtable. */
29100 #define VTABLE_NAME_P(NAME) \
29101 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29102 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29103 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29104 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29105 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29107 #ifdef NO_DOLLAR_IN_LABEL
29108 /* Return a GGC-allocated character string translating dollar signs in
29109 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29112 rs6000_xcoff_strip_dollar (const char *name)
29118 q = (const char *) strchr (name, '$');
29120 if (q == 0 || q == name)
29123 len = strlen (name);
29124 strip = XALLOCAVEC (char, len + 1);
29125 strcpy (strip, name);
29126 p = strip + (q - name);
29130 p = strchr (p + 1, '$');
29133 return ggc_alloc_string (strip, len);
29138 rs6000_output_symbol_ref (FILE *file, rtx x)
29140 const char *name = XSTR (x, 0);
29142 /* Currently C++ toc references to vtables can be emitted before it
29143 is decided whether the vtable is public or private. If this is
29144 the case, then the linker will eventually complain that there is
29145 a reference to an unknown section. Thus, for vtables only,
29146 we emit the TOC reference to reference the identifier and not the
29148 if (VTABLE_NAME_P (name))
29150 RS6000_OUTPUT_BASENAME (file, name);
29153 assemble_name (file, name);
29156 /* Output a TOC entry. We derive the entry name from what is being
29160 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29163 const char *name = buf;
29165 HOST_WIDE_INT offset = 0;
29167 gcc_assert (!TARGET_NO_TOC);
29169 /* When the linker won't eliminate them, don't output duplicate
29170 TOC entries (this happens on AIX if there is any kind of TOC,
29171 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29173 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29175 struct toc_hash_struct *h;
29177 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29178 time because GGC is not initialized at that point. */
29179 if (toc_hash_table == NULL)
29180 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29182 h = ggc_alloc<toc_hash_struct> ();
29184 h->key_mode = mode;
29185 h->labelno = labelno;
29187 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29188 if (*found == NULL)
29190 else /* This is indeed a duplicate.
29191 Set this label equal to that label. */
29193 fputs ("\t.set ", file);
29194 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29195 fprintf (file, "%d,", labelno);
29196 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29197 fprintf (file, "%d\n", ((*found)->labelno));
29200 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
29201 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29202 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29204 fputs ("\t.set ", file);
29205 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29206 fprintf (file, "%d,", labelno);
29207 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29208 fprintf (file, "%d\n", ((*found)->labelno));
29215 /* If we're going to put a double constant in the TOC, make sure it's
29216 aligned properly when strict alignment is on. */
29217 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29218 && STRICT_ALIGNMENT
29219 && GET_MODE_BITSIZE (mode) >= 64
29220 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29221 ASM_OUTPUT_ALIGN (file, 3);
29224 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29226 /* Handle FP constants specially. Note that if we have a minimal
29227 TOC, things we put here aren't actually in the TOC, so we can allow
29229 if (GET_CODE (x) == CONST_DOUBLE &&
29230 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29231 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29235 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29236 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29238 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29242 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29243 fputs (DOUBLE_INT_ASM_OP, file);
29245 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29246 k[0] & 0xffffffff, k[1] & 0xffffffff,
29247 k[2] & 0xffffffff, k[3] & 0xffffffff);
29248 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29249 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29250 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29251 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29252 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29257 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29258 fputs ("\t.long ", file);
29260 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29261 k[0] & 0xffffffff, k[1] & 0xffffffff,
29262 k[2] & 0xffffffff, k[3] & 0xffffffff);
29263 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29264 k[0] & 0xffffffff, k[1] & 0xffffffff,
29265 k[2] & 0xffffffff, k[3] & 0xffffffff);
29269 else if (GET_CODE (x) == CONST_DOUBLE &&
29270 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29274 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29275 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29277 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29281 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29282 fputs (DOUBLE_INT_ASM_OP, file);
29284 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29285 k[0] & 0xffffffff, k[1] & 0xffffffff);
29286 fprintf (file, "0x%lx%08lx\n",
29287 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29288 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29293 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29294 fputs ("\t.long ", file);
29296 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29297 k[0] & 0xffffffff, k[1] & 0xffffffff);
29298 fprintf (file, "0x%lx,0x%lx\n",
29299 k[0] & 0xffffffff, k[1] & 0xffffffff);
29303 else if (GET_CODE (x) == CONST_DOUBLE &&
29304 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29308 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29309 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29311 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29315 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29316 fputs (DOUBLE_INT_ASM_OP, file);
29318 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29319 if (WORDS_BIG_ENDIAN)
29320 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29322 fprintf (file, "0x%lx\n", l & 0xffffffff);
29327 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29328 fputs ("\t.long ", file);
29330 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29331 fprintf (file, "0x%lx\n", l & 0xffffffff);
29335 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
29337 unsigned HOST_WIDE_INT low;
29338 HOST_WIDE_INT high;
29340 low = INTVAL (x) & 0xffffffff;
29341 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29343 /* TOC entries are always Pmode-sized, so when big-endian
29344 smaller integer constants in the TOC need to be padded.
29345 (This is still a win over putting the constants in
29346 a separate constant pool, because then we'd have
29347 to have both a TOC entry _and_ the actual constant.)
29349 For a 32-bit target, CONST_INT values are loaded and shifted
29350 entirely within `low' and can be stored in one TOC entry. */
29352 /* It would be easy to make this work, but it doesn't now. */
29353 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29355 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29358 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29359 high = (HOST_WIDE_INT) low >> 32;
29365 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29366 fputs (DOUBLE_INT_ASM_OP, file);
29368 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29369 (long) high & 0xffffffff, (long) low & 0xffffffff);
29370 fprintf (file, "0x%lx%08lx\n",
29371 (long) high & 0xffffffff, (long) low & 0xffffffff);
29376 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29378 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29379 fputs ("\t.long ", file);
29381 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29382 (long) high & 0xffffffff, (long) low & 0xffffffff);
29383 fprintf (file, "0x%lx,0x%lx\n",
29384 (long) high & 0xffffffff, (long) low & 0xffffffff);
29388 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29389 fputs ("\t.long ", file);
29391 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29392 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29398 if (GET_CODE (x) == CONST)
29400 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29401 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
29403 base = XEXP (XEXP (x, 0), 0);
29404 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29407 switch (GET_CODE (base))
29410 name = XSTR (base, 0);
29414 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29415 CODE_LABEL_NUMBER (XEXP (base, 0)));
29419 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29423 gcc_unreachable ();
29426 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29427 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29430 fputs ("\t.tc ", file);
29431 RS6000_OUTPUT_BASENAME (file, name);
29434 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29436 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29438 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29439 after other TOC symbols, reducing overflow of small TOC access
29440 to [TC] symbols. */
29441 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29442 ? "[TE]," : "[TC],", file);
29445 /* Currently C++ toc references to vtables can be emitted before it
29446 is decided whether the vtable is public or private. If this is
29447 the case, then the linker will eventually complain that there is
29448 a TOC reference to an unknown section. Thus, for vtables only,
29449 we emit the TOC reference to reference the symbol and not the
29451 if (VTABLE_NAME_P (name))
29453 RS6000_OUTPUT_BASENAME (file, name);
29455 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29456 else if (offset > 0)
29457 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29460 output_addr_const (file, x);
29463 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
29465 switch (SYMBOL_REF_TLS_MODEL (base))
29469 case TLS_MODEL_LOCAL_EXEC:
29470 fputs ("@le", file);
29472 case TLS_MODEL_INITIAL_EXEC:
29473 fputs ("@ie", file);
29475 /* Use global-dynamic for local-dynamic. */
29476 case TLS_MODEL_GLOBAL_DYNAMIC:
29477 case TLS_MODEL_LOCAL_DYNAMIC:
29479 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29480 fputs ("\t.tc .", file);
29481 RS6000_OUTPUT_BASENAME (file, name);
29482 fputs ("[TC],", file);
29483 output_addr_const (file, x);
29484 fputs ("@m", file);
29487 gcc_unreachable ();
29495 /* Output an assembler pseudo-op to write an ASCII string of N characters
29496 starting at P to FILE.
29498 On the RS/6000, we have to do this using the .byte operation and
29499 write out special characters outside the quoted string.
29500 Also, the assembler is broken; very long strings are truncated,
29501 so we must artificially break them up early. */
29504 output_ascii (FILE *file, const char *p, int n)
29507 int i, count_string;
29508 const char *for_string = "\t.byte \"";
29509 const char *for_decimal = "\t.byte ";
29510 const char *to_close = NULL;
29513 for (i = 0; i < n; i++)
29516 if (c >= ' ' && c < 0177)
29519 fputs (for_string, file);
29522 /* Write two quotes to get one. */
29530 for_decimal = "\"\n\t.byte ";
29534 if (count_string >= 512)
29536 fputs (to_close, file);
29538 for_string = "\t.byte \"";
29539 for_decimal = "\t.byte ";
29547 fputs (for_decimal, file);
29548 fprintf (file, "%d", c);
29550 for_string = "\n\t.byte \"";
29551 for_decimal = ", ";
29557 /* Now close the string if we have written one. Then end the line. */
29559 fputs (to_close, file);
29562 /* Generate a unique section name for FILENAME for a section type
29563 represented by SECTION_DESC. Output goes into BUF.
29565 SECTION_DESC can be any string, as long as it is different for each
29566 possible section type.
29568 We name the section in the same manner as xlc. The name begins with an
29569 underscore followed by the filename (after stripping any leading directory
29570 names) with the last period replaced by the string SECTION_DESC. If
29571 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29575 rs6000_gen_section_name (char **buf, const char *filename,
29576 const char *section_desc)
29578 const char *q, *after_last_slash, *last_period = 0;
29582 after_last_slash = filename;
29583 for (q = filename; *q; q++)
29586 after_last_slash = q + 1;
29587 else if (*q == '.')
29591 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29592 *buf = (char *) xmalloc (len);
29597 for (q = after_last_slash; *q; q++)
29599 if (q == last_period)
29601 strcpy (p, section_desc);
29602 p += strlen (section_desc);
29606 else if (ISALNUM (*q))
29610 if (last_period == 0)
29611 strcpy (p, section_desc);
29616 /* Emit profile function. */
29619 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29621 /* Non-standard profiling for kernels, which just saves LR then calls
29622 _mcount without worrying about arg saves. The idea is to change
29623 the function prologue as little as possible as it isn't easy to
29624 account for arg save/restore code added just for _mcount. */
29625 if (TARGET_PROFILE_KERNEL)
29628 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29630 #ifndef NO_PROFILE_COUNTERS
29631 # define NO_PROFILE_COUNTERS 0
29633 if (NO_PROFILE_COUNTERS)
29634 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29635 LCT_NORMAL, VOIDmode);
29639 const char *label_name;
29642 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29643 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29644 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29646 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29647 LCT_NORMAL, VOIDmode, fun, Pmode);
29650 else if (DEFAULT_ABI == ABI_DARWIN)
29652 const char *mcount_name = RS6000_MCOUNT;
29653 int caller_addr_regno = LR_REGNO;
29655 /* Be conservative and always set this, at least for now. */
29656 crtl->uses_pic_offset_table = 1;
29659 /* For PIC code, set up a stub and collect the caller's address
29660 from r0, which is where the prologue puts it. */
29661 if (MACHOPIC_INDIRECT
29662 && crtl->uses_pic_offset_table)
29663 caller_addr_regno = 0;
29665 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29666 LCT_NORMAL, VOIDmode,
29667 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29671 /* Write function profiler code. */
29674 output_function_profiler (FILE *file, int labelno)
29678 switch (DEFAULT_ABI)
29681 gcc_unreachable ();
29686 warning (0, "no profiling of 64-bit code for this ABI");
29689 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29690 fprintf (file, "\tmflr %s\n", reg_names[0]);
29691 if (NO_PROFILE_COUNTERS)
29693 asm_fprintf (file, "\tstw %s,4(%s)\n",
29694 reg_names[0], reg_names[1]);
29696 else if (TARGET_SECURE_PLT && flag_pic)
29698 if (TARGET_LINK_STACK)
29701 get_ppc476_thunk_name (name);
29702 asm_fprintf (file, "\tbl %s\n", name);
29705 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
29706 asm_fprintf (file, "\tstw %s,4(%s)\n",
29707 reg_names[0], reg_names[1]);
29708 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29709 asm_fprintf (file, "\taddis %s,%s,",
29710 reg_names[12], reg_names[12]);
29711 assemble_name (file, buf);
29712 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
29713 assemble_name (file, buf);
29714 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
29716 else if (flag_pic == 1)
29718 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
29719 asm_fprintf (file, "\tstw %s,4(%s)\n",
29720 reg_names[0], reg_names[1]);
29721 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29722 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
29723 assemble_name (file, buf);
29724 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
29726 else if (flag_pic > 1)
29728 asm_fprintf (file, "\tstw %s,4(%s)\n",
29729 reg_names[0], reg_names[1]);
29730 /* Now, we need to get the address of the label. */
29731 if (TARGET_LINK_STACK)
29734 get_ppc476_thunk_name (name);
29735 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
29736 assemble_name (file, buf);
29737 fputs ("-.\n1:", file);
29738 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29739 asm_fprintf (file, "\taddi %s,%s,4\n",
29740 reg_names[11], reg_names[11]);
29744 fputs ("\tbcl 20,31,1f\n\t.long ", file);
29745 assemble_name (file, buf);
29746 fputs ("-.\n1:", file);
29747 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29749 asm_fprintf (file, "\tlwz %s,0(%s)\n",
29750 reg_names[0], reg_names[11]);
29751 asm_fprintf (file, "\tadd %s,%s,%s\n",
29752 reg_names[0], reg_names[0], reg_names[11]);
29756 asm_fprintf (file, "\tlis %s,", reg_names[12]);
29757 assemble_name (file, buf);
29758 fputs ("@ha\n", file);
29759 asm_fprintf (file, "\tstw %s,4(%s)\n",
29760 reg_names[0], reg_names[1]);
29761 asm_fprintf (file, "\tla %s,", reg_names[0]);
29762 assemble_name (file, buf);
29763 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
29766 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
29767 fprintf (file, "\tbl %s%s\n",
29768 RS6000_MCOUNT, flag_pic ? "@plt" : "");
29774 /* Don't do anything, done in output_profile_hook (). */
29781 /* The following variable value is the last issued insn. */
29783 static rtx_insn *last_scheduled_insn;
29785 /* The following variable helps to balance issuing of load and
29786 store instructions */
29788 static int load_store_pendulum;
29790 /* The following variable helps pair divide insns during scheduling. */
29791 static int divide_cnt;
29792 /* The following variable helps pair and alternate vector and vector load
29793 insns during scheduling. */
29794 static int vec_pairing;
29797 /* Power4 load update and store update instructions are cracked into a
29798 load or store and an integer insn which are executed in the same cycle.
29799 Branches have their own dispatch slot which does not count against the
29800 GCC issue rate, but it changes the program flow so there are no other
29801 instructions to issue in this cycle. */
29804 rs6000_variable_issue_1 (rtx_insn *insn, int more)
29806 last_scheduled_insn = insn;
29807 if (GET_CODE (PATTERN (insn)) == USE
29808 || GET_CODE (PATTERN (insn)) == CLOBBER)
29810 cached_can_issue_more = more;
29811 return cached_can_issue_more;
29814 if (insn_terminates_group_p (insn, current_group))
29816 cached_can_issue_more = 0;
29817 return cached_can_issue_more;
29820 /* If no reservation, but reach here */
29821 if (recog_memoized (insn) < 0)
29824 if (rs6000_sched_groups)
29826 if (is_microcoded_insn (insn))
29827 cached_can_issue_more = 0;
29828 else if (is_cracked_insn (insn))
29829 cached_can_issue_more = more > 2 ? more - 2 : 0;
29831 cached_can_issue_more = more - 1;
29833 return cached_can_issue_more;
29836 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
29839 cached_can_issue_more = more - 1;
29840 return cached_can_issue_more;
29844 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
29846 int r = rs6000_variable_issue_1 (insn, more);
29848 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
29852 /* Adjust the cost of a scheduling dependency. Return the new cost of
29853 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
29856 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
29859 enum attr_type attr_type;
29861 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
29868 /* Data dependency; DEP_INSN writes a register that INSN reads
29869 some cycles later. */
29871 /* Separate a load from a narrower, dependent store. */
29872 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
29873 && GET_CODE (PATTERN (insn)) == SET
29874 && GET_CODE (PATTERN (dep_insn)) == SET
29875 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
29876 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
29877 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
29878 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
29881 attr_type = get_attr_type (insn);
29886 /* Tell the first scheduling pass about the latency between
29887 a mtctr and bctr (and mtlr and br/blr). The first
29888 scheduling pass will not know about this latency since
29889 the mtctr instruction, which has the latency associated
29890 to it, will be generated by reload. */
29893 /* Leave some extra cycles between a compare and its
29894 dependent branch, to inhibit expensive mispredicts. */
29895 if ((rs6000_tune == PROCESSOR_PPC603
29896 || rs6000_tune == PROCESSOR_PPC604
29897 || rs6000_tune == PROCESSOR_PPC604e
29898 || rs6000_tune == PROCESSOR_PPC620
29899 || rs6000_tune == PROCESSOR_PPC630
29900 || rs6000_tune == PROCESSOR_PPC750
29901 || rs6000_tune == PROCESSOR_PPC7400
29902 || rs6000_tune == PROCESSOR_PPC7450
29903 || rs6000_tune == PROCESSOR_PPCE5500
29904 || rs6000_tune == PROCESSOR_PPCE6500
29905 || rs6000_tune == PROCESSOR_POWER4
29906 || rs6000_tune == PROCESSOR_POWER5
29907 || rs6000_tune == PROCESSOR_POWER7
29908 || rs6000_tune == PROCESSOR_POWER8
29909 || rs6000_tune == PROCESSOR_POWER9
29910 || rs6000_tune == PROCESSOR_CELL)
29911 && recog_memoized (dep_insn)
29912 && (INSN_CODE (dep_insn) >= 0))
29914 switch (get_attr_type (dep_insn))
29917 case TYPE_FPCOMPARE:
29918 case TYPE_CR_LOGICAL:
29922 if (get_attr_dot (dep_insn) == DOT_YES)
29927 if (get_attr_dot (dep_insn) == DOT_YES
29928 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
29939 if ((rs6000_tune == PROCESSOR_POWER6)
29940 && recog_memoized (dep_insn)
29941 && (INSN_CODE (dep_insn) >= 0))
29944 if (GET_CODE (PATTERN (insn)) != SET)
29945 /* If this happens, we have to extend this to schedule
29946 optimally. Return default for now. */
29949 /* Adjust the cost for the case where the value written
29950 by a fixed point operation is used as the address
29951 gen value on a store. */
29952 switch (get_attr_type (dep_insn))
29957 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29958 return get_attr_sign_extend (dep_insn)
29959 == SIGN_EXTEND_YES ? 6 : 4;
29964 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29965 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
29975 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29983 if (get_attr_update (dep_insn) == UPDATE_YES
29984 && ! rs6000_store_data_bypass_p (dep_insn, insn))
29990 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29996 if (! rs6000_store_data_bypass_p (dep_insn, insn))
29997 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30007 if ((rs6000_tune == PROCESSOR_POWER6)
30008 && recog_memoized (dep_insn)
30009 && (INSN_CODE (dep_insn) >= 0))
30012 /* Adjust the cost for the case where the value written
30013 by a fixed point instruction is used within the address
30014 gen portion of a subsequent load(u)(x) */
30015 switch (get_attr_type (dep_insn))
30020 if (set_to_load_agen (dep_insn, insn))
30021 return get_attr_sign_extend (dep_insn)
30022 == SIGN_EXTEND_YES ? 6 : 4;
30027 if (set_to_load_agen (dep_insn, insn))
30028 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30038 if (set_to_load_agen (dep_insn, insn))
30046 if (get_attr_update (dep_insn) == UPDATE_YES
30047 && set_to_load_agen (dep_insn, insn))
30053 if (set_to_load_agen (dep_insn, insn))
30059 if (set_to_load_agen (dep_insn, insn))
30060 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30070 if ((rs6000_tune == PROCESSOR_POWER6)
30071 && get_attr_update (insn) == UPDATE_NO
30072 && recog_memoized (dep_insn)
30073 && (INSN_CODE (dep_insn) >= 0)
30074 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30081 /* Fall out to return default cost. */
30085 case REG_DEP_OUTPUT:
30086 /* Output dependency; DEP_INSN writes a register that INSN writes some
30088 if ((rs6000_tune == PROCESSOR_POWER6)
30089 && recog_memoized (dep_insn)
30090 && (INSN_CODE (dep_insn) >= 0))
30092 attr_type = get_attr_type (insn);
30097 case TYPE_FPSIMPLE:
30098 if (get_attr_type (dep_insn) == TYPE_FP
30099 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30103 if (get_attr_update (insn) == UPDATE_NO
30104 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30111 /* Fall through, no cost for output dependency. */
30115 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30120 gcc_unreachable ();
30126 /* Debug version of rs6000_adjust_cost. */
30129 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30130 int cost, unsigned int dw)
30132 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30140 default: dep = "unknown depencency"; break;
30141 case REG_DEP_TRUE: dep = "data dependency"; break;
30142 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30143 case REG_DEP_ANTI: dep = "anti depencency"; break;
30147 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30148 "%s, insn:\n", ret, cost, dep);
30156 /* The function returns a true if INSN is microcoded.
30157 Return false otherwise. */
30160 is_microcoded_insn (rtx_insn *insn)
30162 if (!insn || !NONDEBUG_INSN_P (insn)
30163 || GET_CODE (PATTERN (insn)) == USE
30164 || GET_CODE (PATTERN (insn)) == CLOBBER)
30167 if (rs6000_tune == PROCESSOR_CELL)
30168 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30170 if (rs6000_sched_groups
30171 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30173 enum attr_type type = get_attr_type (insn);
30174 if ((type == TYPE_LOAD
30175 && get_attr_update (insn) == UPDATE_YES
30176 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30177 || ((type == TYPE_LOAD || type == TYPE_STORE)
30178 && get_attr_update (insn) == UPDATE_YES
30179 && get_attr_indexed (insn) == INDEXED_YES)
30180 || type == TYPE_MFCR)
30187 /* The function returns true if INSN is cracked into 2 instructions
30188 by the processor (and therefore occupies 2 issue slots). */
30191 is_cracked_insn (rtx_insn *insn)
30193 if (!insn || !NONDEBUG_INSN_P (insn)
30194 || GET_CODE (PATTERN (insn)) == USE
30195 || GET_CODE (PATTERN (insn)) == CLOBBER)
30198 if (rs6000_sched_groups
30199 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30201 enum attr_type type = get_attr_type (insn);
30202 if ((type == TYPE_LOAD
30203 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30204 && get_attr_update (insn) == UPDATE_NO)
30205 || (type == TYPE_LOAD
30206 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30207 && get_attr_update (insn) == UPDATE_YES
30208 && get_attr_indexed (insn) == INDEXED_NO)
30209 || (type == TYPE_STORE
30210 && get_attr_update (insn) == UPDATE_YES
30211 && get_attr_indexed (insn) == INDEXED_NO)
30212 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30213 && get_attr_update (insn) == UPDATE_YES)
30214 || (type == TYPE_CR_LOGICAL
30215 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30216 || (type == TYPE_EXTS
30217 && get_attr_dot (insn) == DOT_YES)
30218 || (type == TYPE_SHIFT
30219 && get_attr_dot (insn) == DOT_YES
30220 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30221 || (type == TYPE_MUL
30222 && get_attr_dot (insn) == DOT_YES)
30223 || type == TYPE_DIV
30224 || (type == TYPE_INSERT
30225 && get_attr_size (insn) == SIZE_32))
30232 /* The function returns true if INSN can be issued only from
30233 the branch slot. */
30236 is_branch_slot_insn (rtx_insn *insn)
30238 if (!insn || !NONDEBUG_INSN_P (insn)
30239 || GET_CODE (PATTERN (insn)) == USE
30240 || GET_CODE (PATTERN (insn)) == CLOBBER)
30243 if (rs6000_sched_groups)
30245 enum attr_type type = get_attr_type (insn);
30246 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30254 /* The function returns true if out_inst sets a value that is
30255 used in the address generation computation of in_insn */
30257 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30259 rtx out_set, in_set;
30261 /* For performance reasons, only handle the simple case where
30262 both loads are a single_set. */
30263 out_set = single_set (out_insn);
30266 in_set = single_set (in_insn);
30268 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30274 /* Try to determine base/offset/size parts of the given MEM.
30275 Return true if successful, false if all the values couldn't
30278 This function only looks for REG or REG+CONST address forms.
30279 REG+REG address form will return false. */
30282 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30283 HOST_WIDE_INT *size)
30286 if MEM_SIZE_KNOWN_P (mem)
30287 *size = MEM_SIZE (mem);
30291 addr_rtx = (XEXP (mem, 0));
30292 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30293 addr_rtx = XEXP (addr_rtx, 1);
30296 while (GET_CODE (addr_rtx) == PLUS
30297 && CONST_INT_P (XEXP (addr_rtx, 1)))
30299 *offset += INTVAL (XEXP (addr_rtx, 1));
30300 addr_rtx = XEXP (addr_rtx, 0);
30302 if (!REG_P (addr_rtx))
30309 /* The function returns true if the target storage location of
30310 mem1 is adjacent to the target storage location of mem2 */
30311 /* Return 1 if memory locations are adjacent. */
30314 adjacent_mem_locations (rtx mem1, rtx mem2)
30317 HOST_WIDE_INT off1, size1, off2, size2;
30319 if (get_memref_parts (mem1, ®1, &off1, &size1)
30320 && get_memref_parts (mem2, ®2, &off2, &size2))
30321 return ((REGNO (reg1) == REGNO (reg2))
30322 && ((off1 + size1 == off2)
30323 || (off2 + size2 == off1)));
30328 /* This function returns true if it can be determined that the two MEM
30329 locations overlap by at least 1 byte based on base reg/offset/size. */
30332 mem_locations_overlap (rtx mem1, rtx mem2)
30335 HOST_WIDE_INT off1, size1, off2, size2;
30337 if (get_memref_parts (mem1, ®1, &off1, &size1)
30338 && get_memref_parts (mem2, ®2, &off2, &size2))
30339 return ((REGNO (reg1) == REGNO (reg2))
30340 && (((off1 <= off2) && (off1 + size1 > off2))
30341 || ((off2 <= off1) && (off2 + size2 > off1))));
30346 /* A C statement (sans semicolon) to update the integer scheduling
30347 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30348 INSN earlier, reduce the priority to execute INSN later. Do not
30349 define this macro if you do not need to adjust the scheduling
30350 priorities of insns. */
30353 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30355 rtx load_mem, str_mem;
30356 /* On machines (like the 750) which have asymmetric integer units,
30357 where one integer unit can do multiply and divides and the other
30358 can't, reduce the priority of multiply/divide so it is scheduled
30359 before other integer operations. */
30362 if (! INSN_P (insn))
30365 if (GET_CODE (PATTERN (insn)) == USE)
30368 switch (rs6000_tune) {
30369 case PROCESSOR_PPC750:
30370 switch (get_attr_type (insn))
30377 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30378 priority, priority);
30379 if (priority >= 0 && priority < 0x01000000)
30386 if (insn_must_be_first_in_group (insn)
30387 && reload_completed
30388 && current_sched_info->sched_max_insns_priority
30389 && rs6000_sched_restricted_insns_priority)
30392 /* Prioritize insns that can be dispatched only in the first
30394 if (rs6000_sched_restricted_insns_priority == 1)
30395 /* Attach highest priority to insn. This means that in
30396 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30397 precede 'priority' (critical path) considerations. */
30398 return current_sched_info->sched_max_insns_priority;
30399 else if (rs6000_sched_restricted_insns_priority == 2)
30400 /* Increase priority of insn by a minimal amount. This means that in
30401 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30402 considerations precede dispatch-slot restriction considerations. */
30403 return (priority + 1);
30406 if (rs6000_tune == PROCESSOR_POWER6
30407 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30408 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30409 /* Attach highest priority to insn if the scheduler has just issued two
30410 stores and this instruction is a load, or two loads and this instruction
30411 is a store. Power6 wants loads and stores scheduled alternately
30413 return current_sched_info->sched_max_insns_priority;
30418 /* Return true if the instruction is nonpipelined on the Cell. */
30420 is_nonpipeline_insn (rtx_insn *insn)
30422 enum attr_type type;
30423 if (!insn || !NONDEBUG_INSN_P (insn)
30424 || GET_CODE (PATTERN (insn)) == USE
30425 || GET_CODE (PATTERN (insn)) == CLOBBER)
30428 type = get_attr_type (insn);
30429 if (type == TYPE_MUL
30430 || type == TYPE_DIV
30431 || type == TYPE_SDIV
30432 || type == TYPE_DDIV
30433 || type == TYPE_SSQRT
30434 || type == TYPE_DSQRT
30435 || type == TYPE_MFCR
30436 || type == TYPE_MFCRF
30437 || type == TYPE_MFJMPR)
30445 /* Return how many instructions the machine can issue per cycle. */
30448 rs6000_issue_rate (void)
30450 /* Unless scheduling for register pressure, use issue rate of 1 for
30451 first scheduling pass to decrease degradation. */
30452 if (!reload_completed && !flag_sched_pressure)
30455 switch (rs6000_tune) {
30456 case PROCESSOR_RS64A:
30457 case PROCESSOR_PPC601: /* ? */
30458 case PROCESSOR_PPC7450:
30460 case PROCESSOR_PPC440:
30461 case PROCESSOR_PPC603:
30462 case PROCESSOR_PPC750:
30463 case PROCESSOR_PPC7400:
30464 case PROCESSOR_PPC8540:
30465 case PROCESSOR_PPC8548:
30466 case PROCESSOR_CELL:
30467 case PROCESSOR_PPCE300C2:
30468 case PROCESSOR_PPCE300C3:
30469 case PROCESSOR_PPCE500MC:
30470 case PROCESSOR_PPCE500MC64:
30471 case PROCESSOR_PPCE5500:
30472 case PROCESSOR_PPCE6500:
30473 case PROCESSOR_TITAN:
30475 case PROCESSOR_PPC476:
30476 case PROCESSOR_PPC604:
30477 case PROCESSOR_PPC604e:
30478 case PROCESSOR_PPC620:
30479 case PROCESSOR_PPC630:
30481 case PROCESSOR_POWER4:
30482 case PROCESSOR_POWER5:
30483 case PROCESSOR_POWER6:
30484 case PROCESSOR_POWER7:
30486 case PROCESSOR_POWER8:
30488 case PROCESSOR_POWER9:
30495 /* Return how many instructions to look ahead for better insn
30499 rs6000_use_sched_lookahead (void)
30501 switch (rs6000_tune)
30503 case PROCESSOR_PPC8540:
30504 case PROCESSOR_PPC8548:
30507 case PROCESSOR_CELL:
30508 return (reload_completed ? 8 : 0);
30515 /* We are choosing insn from the ready queue. Return zero if INSN can be
30518 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30520 if (ready_index == 0)
30523 if (rs6000_tune != PROCESSOR_CELL)
30526 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30528 if (!reload_completed
30529 || is_nonpipeline_insn (insn)
30530 || is_microcoded_insn (insn))
30536 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30537 and return true. */
30540 find_mem_ref (rtx pat, rtx *mem_ref)
30545 /* stack_tie does not produce any real memory traffic. */
30546 if (tie_operand (pat, VOIDmode))
30549 if (GET_CODE (pat) == MEM)
30555 /* Recursively process the pattern. */
30556 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30558 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30562 if (find_mem_ref (XEXP (pat, i), mem_ref))
30565 else if (fmt[i] == 'E')
30566 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30568 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30576 /* Determine if PAT is a PATTERN of a load insn. */
30579 is_load_insn1 (rtx pat, rtx *load_mem)
30581 if (!pat || pat == NULL_RTX)
30584 if (GET_CODE (pat) == SET)
30585 return find_mem_ref (SET_SRC (pat), load_mem);
30587 if (GET_CODE (pat) == PARALLEL)
30591 for (i = 0; i < XVECLEN (pat, 0); i++)
30592 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30599 /* Determine if INSN loads from memory. */
30602 is_load_insn (rtx insn, rtx *load_mem)
30604 if (!insn || !INSN_P (insn))
30610 return is_load_insn1 (PATTERN (insn), load_mem);
30613 /* Determine if PAT is a PATTERN of a store insn. */
30616 is_store_insn1 (rtx pat, rtx *str_mem)
30618 if (!pat || pat == NULL_RTX)
30621 if (GET_CODE (pat) == SET)
30622 return find_mem_ref (SET_DEST (pat), str_mem);
30624 if (GET_CODE (pat) == PARALLEL)
30628 for (i = 0; i < XVECLEN (pat, 0); i++)
30629 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30636 /* Determine if INSN stores to memory. */
30639 is_store_insn (rtx insn, rtx *str_mem)
30641 if (!insn || !INSN_P (insn))
30644 return is_store_insn1 (PATTERN (insn), str_mem);
30647 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30650 is_power9_pairable_vec_type (enum attr_type type)
30654 case TYPE_VECSIMPLE:
30655 case TYPE_VECCOMPLEX:
30659 case TYPE_VECFLOAT:
30661 case TYPE_VECDOUBLE:
30669 /* Returns whether the dependence between INSN and NEXT is considered
30670 costly by the given target. */
30673 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30677 rtx load_mem, str_mem;
30679 /* If the flag is not enabled - no dependence is considered costly;
30680 allow all dependent insns in the same group.
30681 This is the most aggressive option. */
30682 if (rs6000_sched_costly_dep == no_dep_costly)
30685 /* If the flag is set to 1 - a dependence is always considered costly;
30686 do not allow dependent instructions in the same group.
30687 This is the most conservative option. */
30688 if (rs6000_sched_costly_dep == all_deps_costly)
30691 insn = DEP_PRO (dep);
30692 next = DEP_CON (dep);
30694 if (rs6000_sched_costly_dep == store_to_load_dep_costly
30695 && is_load_insn (next, &load_mem)
30696 && is_store_insn (insn, &str_mem))
30697 /* Prevent load after store in the same group. */
30700 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
30701 && is_load_insn (next, &load_mem)
30702 && is_store_insn (insn, &str_mem)
30703 && DEP_TYPE (dep) == REG_DEP_TRUE
30704 && mem_locations_overlap(str_mem, load_mem))
30705 /* Prevent load after store in the same group if it is a true
30709 /* The flag is set to X; dependences with latency >= X are considered costly,
30710 and will not be scheduled in the same group. */
30711 if (rs6000_sched_costly_dep <= max_dep_latency
30712 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
30718 /* Return the next insn after INSN that is found before TAIL is reached,
30719 skipping any "non-active" insns - insns that will not actually occupy
30720 an issue slot. Return NULL_RTX if such an insn is not found. */
30723 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
30725 if (insn == NULL_RTX || insn == tail)
30730 insn = NEXT_INSN (insn);
30731 if (insn == NULL_RTX || insn == tail)
30735 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
30736 || (NONJUMP_INSN_P (insn)
30737 && GET_CODE (PATTERN (insn)) != USE
30738 && GET_CODE (PATTERN (insn)) != CLOBBER
30739 && INSN_CODE (insn) != CODE_FOR_stack_tie))
30745 /* Do Power9 specific sched_reorder2 reordering of ready list. */
30748 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
30753 enum attr_type type, type2;
30755 type = get_attr_type (last_scheduled_insn);
30757 /* Try to issue fixed point divides back-to-back in pairs so they will be
30758 routed to separate execution units and execute in parallel. */
30759 if (type == TYPE_DIV && divide_cnt == 0)
30761 /* First divide has been scheduled. */
30764 /* Scan the ready list looking for another divide, if found move it
30765 to the end of the list so it is chosen next. */
30769 if (recog_memoized (ready[pos]) >= 0
30770 && get_attr_type (ready[pos]) == TYPE_DIV)
30773 for (i = pos; i < lastpos; i++)
30774 ready[i] = ready[i + 1];
30775 ready[lastpos] = tmp;
30783 /* Last insn was the 2nd divide or not a divide, reset the counter. */
30786 /* The best dispatch throughput for vector and vector load insns can be
30787 achieved by interleaving a vector and vector load such that they'll
30788 dispatch to the same superslice. If this pairing cannot be achieved
30789 then it is best to pair vector insns together and vector load insns
30792 To aid in this pairing, vec_pairing maintains the current state with
30793 the following values:
30795 0 : Initial state, no vecload/vector pairing has been started.
30797 1 : A vecload or vector insn has been issued and a candidate for
30798 pairing has been found and moved to the end of the ready
30800 if (type == TYPE_VECLOAD)
30802 /* Issued a vecload. */
30803 if (vec_pairing == 0)
30805 int vecload_pos = -1;
30806 /* We issued a single vecload, look for a vector insn to pair it
30807 with. If one isn't found, try to pair another vecload. */
30811 if (recog_memoized (ready[pos]) >= 0)
30813 type2 = get_attr_type (ready[pos]);
30814 if (is_power9_pairable_vec_type (type2))
30816 /* Found a vector insn to pair with, move it to the
30817 end of the ready list so it is scheduled next. */
30819 for (i = pos; i < lastpos; i++)
30820 ready[i] = ready[i + 1];
30821 ready[lastpos] = tmp;
30823 return cached_can_issue_more;
30825 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
30826 /* Remember position of first vecload seen. */
30831 if (vecload_pos >= 0)
30833 /* Didn't find a vector to pair with but did find a vecload,
30834 move it to the end of the ready list. */
30835 tmp = ready[vecload_pos];
30836 for (i = vecload_pos; i < lastpos; i++)
30837 ready[i] = ready[i + 1];
30838 ready[lastpos] = tmp;
30840 return cached_can_issue_more;
30844 else if (is_power9_pairable_vec_type (type))
30846 /* Issued a vector operation. */
30847 if (vec_pairing == 0)
30850 /* We issued a single vector insn, look for a vecload to pair it
30851 with. If one isn't found, try to pair another vector. */
30855 if (recog_memoized (ready[pos]) >= 0)
30857 type2 = get_attr_type (ready[pos]);
30858 if (type2 == TYPE_VECLOAD)
30860 /* Found a vecload insn to pair with, move it to the
30861 end of the ready list so it is scheduled next. */
30863 for (i = pos; i < lastpos; i++)
30864 ready[i] = ready[i + 1];
30865 ready[lastpos] = tmp;
30867 return cached_can_issue_more;
30869 else if (is_power9_pairable_vec_type (type2)
30871 /* Remember position of first vector insn seen. */
30878 /* Didn't find a vecload to pair with but did find a vector
30879 insn, move it to the end of the ready list. */
30880 tmp = ready[vec_pos];
30881 for (i = vec_pos; i < lastpos; i++)
30882 ready[i] = ready[i + 1];
30883 ready[lastpos] = tmp;
30885 return cached_can_issue_more;
30890 /* We've either finished a vec/vecload pair, couldn't find an insn to
30891 continue the current pair, or the last insn had nothing to do with
30892 with pairing. In any case, reset the state. */
30896 return cached_can_issue_more;
30899 /* We are about to begin issuing insns for this clock cycle. */
30902 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
30903 rtx_insn **ready ATTRIBUTE_UNUSED,
30904 int *pn_ready ATTRIBUTE_UNUSED,
30905 int clock_var ATTRIBUTE_UNUSED)
30907 int n_ready = *pn_ready;
30910 fprintf (dump, "// rs6000_sched_reorder :\n");
30912 /* Reorder the ready list, if the second to last ready insn
30913 is a nonepipeline insn. */
30914 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
30916 if (is_nonpipeline_insn (ready[n_ready - 1])
30917 && (recog_memoized (ready[n_ready - 2]) > 0))
30918 /* Simply swap first two insns. */
30919 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
30922 if (rs6000_tune == PROCESSOR_POWER6)
30923 load_store_pendulum = 0;
30925 return rs6000_issue_rate ();
30928 /* Like rs6000_sched_reorder, but called after issuing each insn. */
30931 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
30932 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
30935 fprintf (dump, "// rs6000_sched_reorder2 :\n");
30937 /* For Power6, we need to handle some special cases to try and keep the
30938 store queue from overflowing and triggering expensive flushes.
30940 This code monitors how load and store instructions are being issued
30941 and skews the ready list one way or the other to increase the likelihood
30942 that a desired instruction is issued at the proper time.
30944 A couple of things are done. First, we maintain a "load_store_pendulum"
30945 to track the current state of load/store issue.
30947 - If the pendulum is at zero, then no loads or stores have been
30948 issued in the current cycle so we do nothing.
30950 - If the pendulum is 1, then a single load has been issued in this
30951 cycle and we attempt to locate another load in the ready list to
30954 - If the pendulum is -2, then two stores have already been
30955 issued in this cycle, so we increase the priority of the first load
30956 in the ready list to increase it's likelihood of being chosen first
30959 - If the pendulum is -1, then a single store has been issued in this
30960 cycle and we attempt to locate another store in the ready list to
30961 issue with it, preferring a store to an adjacent memory location to
30962 facilitate store pairing in the store queue.
30964 - If the pendulum is 2, then two loads have already been
30965 issued in this cycle, so we increase the priority of the first store
30966 in the ready list to increase it's likelihood of being chosen first
30969 - If the pendulum < -2 or > 2, then do nothing.
30971 Note: This code covers the most common scenarios. There exist non
30972 load/store instructions which make use of the LSU and which
30973 would need to be accounted for to strictly model the behavior
30974 of the machine. Those instructions are currently unaccounted
30975 for to help minimize compile time overhead of this code.
30977 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
30982 rtx load_mem, str_mem;
30984 if (is_store_insn (last_scheduled_insn, &str_mem))
30985 /* Issuing a store, swing the load_store_pendulum to the left */
30986 load_store_pendulum--;
30987 else if (is_load_insn (last_scheduled_insn, &load_mem))
30988 /* Issuing a load, swing the load_store_pendulum to the right */
30989 load_store_pendulum++;
30991 return cached_can_issue_more;
30993 /* If the pendulum is balanced, or there is only one instruction on
30994 the ready list, then all is well, so return. */
30995 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
30996 return cached_can_issue_more;
30998 if (load_store_pendulum == 1)
31000 /* A load has been issued in this cycle. Scan the ready list
31001 for another load to issue with it */
31006 if (is_load_insn (ready[pos], &load_mem))
31008 /* Found a load. Move it to the head of the ready list,
31009 and adjust it's priority so that it is more likely to
31012 for (i=pos; i<*pn_ready-1; i++)
31013 ready[i] = ready[i + 1];
31014 ready[*pn_ready-1] = tmp;
31016 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31017 INSN_PRIORITY (tmp)++;
31023 else if (load_store_pendulum == -2)
31025 /* Two stores have been issued in this cycle. Increase the
31026 priority of the first load in the ready list to favor it for
31027 issuing in the next cycle. */
31032 if (is_load_insn (ready[pos], &load_mem)
31034 && INSN_PRIORITY_KNOWN (ready[pos]))
31036 INSN_PRIORITY (ready[pos])++;
31038 /* Adjust the pendulum to account for the fact that a load
31039 was found and increased in priority. This is to prevent
31040 increasing the priority of multiple loads */
31041 load_store_pendulum--;
31048 else if (load_store_pendulum == -1)
31050 /* A store has been issued in this cycle. Scan the ready list for
31051 another store to issue with it, preferring a store to an adjacent
31053 int first_store_pos = -1;
31059 if (is_store_insn (ready[pos], &str_mem))
31062 /* Maintain the index of the first store found on the
31064 if (first_store_pos == -1)
31065 first_store_pos = pos;
31067 if (is_store_insn (last_scheduled_insn, &str_mem2)
31068 && adjacent_mem_locations (str_mem, str_mem2))
31070 /* Found an adjacent store. Move it to the head of the
31071 ready list, and adjust it's priority so that it is
31072 more likely to stay there */
31074 for (i=pos; i<*pn_ready-1; i++)
31075 ready[i] = ready[i + 1];
31076 ready[*pn_ready-1] = tmp;
31078 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31079 INSN_PRIORITY (tmp)++;
31081 first_store_pos = -1;
31089 if (first_store_pos >= 0)
31091 /* An adjacent store wasn't found, but a non-adjacent store was,
31092 so move the non-adjacent store to the front of the ready
31093 list, and adjust its priority so that it is more likely to
31095 tmp = ready[first_store_pos];
31096 for (i=first_store_pos; i<*pn_ready-1; i++)
31097 ready[i] = ready[i + 1];
31098 ready[*pn_ready-1] = tmp;
31099 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31100 INSN_PRIORITY (tmp)++;
31103 else if (load_store_pendulum == 2)
31105 /* Two loads have been issued in this cycle. Increase the priority
31106 of the first store in the ready list to favor it for issuing in
31112 if (is_store_insn (ready[pos], &str_mem)
31114 && INSN_PRIORITY_KNOWN (ready[pos]))
31116 INSN_PRIORITY (ready[pos])++;
31118 /* Adjust the pendulum to account for the fact that a store
31119 was found and increased in priority. This is to prevent
31120 increasing the priority of multiple stores */
31121 load_store_pendulum++;
31130 /* Do Power9 dependent reordering if necessary. */
31131 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31132 && recog_memoized (last_scheduled_insn) >= 0)
31133 return power9_sched_reorder2 (ready, *pn_ready - 1);
31135 return cached_can_issue_more;
31138 /* Return whether the presence of INSN causes a dispatch group termination
31139 of group WHICH_GROUP.
31141 If WHICH_GROUP == current_group, this function will return true if INSN
31142 causes the termination of the current group (i.e, the dispatch group to
31143 which INSN belongs). This means that INSN will be the last insn in the
31144 group it belongs to.
31146 If WHICH_GROUP == previous_group, this function will return true if INSN
31147 causes the termination of the previous group (i.e, the dispatch group that
31148 precedes the group to which INSN belongs). This means that INSN will be
31149 the first insn in the group it belongs to). */
31152 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31159 first = insn_must_be_first_in_group (insn);
31160 last = insn_must_be_last_in_group (insn);
31165 if (which_group == current_group)
31167 else if (which_group == previous_group)
31175 insn_must_be_first_in_group (rtx_insn *insn)
31177 enum attr_type type;
31181 || DEBUG_INSN_P (insn)
31182 || GET_CODE (PATTERN (insn)) == USE
31183 || GET_CODE (PATTERN (insn)) == CLOBBER)
31186 switch (rs6000_tune)
31188 case PROCESSOR_POWER5:
31189 if (is_cracked_insn (insn))
31192 case PROCESSOR_POWER4:
31193 if (is_microcoded_insn (insn))
31196 if (!rs6000_sched_groups)
31199 type = get_attr_type (insn);
31206 case TYPE_CR_LOGICAL:
31219 case PROCESSOR_POWER6:
31220 type = get_attr_type (insn);
31229 case TYPE_FPCOMPARE:
31240 if (get_attr_dot (insn) == DOT_NO
31241 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31246 if (get_attr_size (insn) == SIZE_32)
31254 if (get_attr_update (insn) == UPDATE_YES)
31262 case PROCESSOR_POWER7:
31263 type = get_attr_type (insn);
31267 case TYPE_CR_LOGICAL:
31281 if (get_attr_dot (insn) == DOT_YES)
31286 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31287 || get_attr_update (insn) == UPDATE_YES)
31294 if (get_attr_update (insn) == UPDATE_YES)
31302 case PROCESSOR_POWER8:
31303 type = get_attr_type (insn);
31307 case TYPE_CR_LOGICAL:
31315 case TYPE_VECSTORE:
31322 if (get_attr_dot (insn) == DOT_YES)
31327 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31328 || get_attr_update (insn) == UPDATE_YES)
31333 if (get_attr_update (insn) == UPDATE_YES
31334 && get_attr_indexed (insn) == INDEXED_YES)
31350 insn_must_be_last_in_group (rtx_insn *insn)
31352 enum attr_type type;
31356 || DEBUG_INSN_P (insn)
31357 || GET_CODE (PATTERN (insn)) == USE
31358 || GET_CODE (PATTERN (insn)) == CLOBBER)
31361 switch (rs6000_tune) {
31362 case PROCESSOR_POWER4:
31363 case PROCESSOR_POWER5:
31364 if (is_microcoded_insn (insn))
31367 if (is_branch_slot_insn (insn))
31371 case PROCESSOR_POWER6:
31372 type = get_attr_type (insn);
31380 case TYPE_FPCOMPARE:
31391 if (get_attr_dot (insn) == DOT_NO
31392 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31397 if (get_attr_size (insn) == SIZE_32)
31405 case PROCESSOR_POWER7:
31406 type = get_attr_type (insn);
31416 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31417 && get_attr_update (insn) == UPDATE_YES)
31422 if (get_attr_update (insn) == UPDATE_YES
31423 && get_attr_indexed (insn) == INDEXED_YES)
31431 case PROCESSOR_POWER8:
31432 type = get_attr_type (insn);
31444 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31445 && get_attr_update (insn) == UPDATE_YES)
31450 if (get_attr_update (insn) == UPDATE_YES
31451 && get_attr_indexed (insn) == INDEXED_YES)
31466 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31467 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31470 is_costly_group (rtx *group_insns, rtx next_insn)
31473 int issue_rate = rs6000_issue_rate ();
31475 for (i = 0; i < issue_rate; i++)
31477 sd_iterator_def sd_it;
31479 rtx insn = group_insns[i];
31484 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31486 rtx next = DEP_CON (dep);
31488 if (next == next_insn
31489 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31497 /* Utility of the function redefine_groups.
31498 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31499 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31500 to keep it "far" (in a separate group) from GROUP_INSNS, following
31501 one of the following schemes, depending on the value of the flag
31502 -minsert_sched_nops = X:
31503 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31504 in order to force NEXT_INSN into a separate group.
31505 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31506 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31507 insertion (has a group just ended, how many vacant issue slots remain in the
31508 last group, and how many dispatch groups were encountered so far). */
31511 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31512 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31517 int issue_rate = rs6000_issue_rate ();
31518 bool end = *group_end;
31521 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31522 return can_issue_more;
31524 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31525 return can_issue_more;
31527 force = is_costly_group (group_insns, next_insn);
31529 return can_issue_more;
31531 if (sched_verbose > 6)
31532 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31533 *group_count ,can_issue_more);
31535 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31538 can_issue_more = 0;
31540 /* Since only a branch can be issued in the last issue_slot, it is
31541 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31542 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31543 in this case the last nop will start a new group and the branch
31544 will be forced to the new group. */
31545 if (can_issue_more && !is_branch_slot_insn (next_insn))
31548 /* Do we have a special group ending nop? */
31549 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31550 || rs6000_tune == PROCESSOR_POWER8)
31552 nop = gen_group_ending_nop ();
31553 emit_insn_before (nop, next_insn);
31554 can_issue_more = 0;
31557 while (can_issue_more > 0)
31560 emit_insn_before (nop, next_insn);
31568 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31570 int n_nops = rs6000_sched_insert_nops;
31572 /* Nops can't be issued from the branch slot, so the effective
31573 issue_rate for nops is 'issue_rate - 1'. */
31574 if (can_issue_more == 0)
31575 can_issue_more = issue_rate;
31577 if (can_issue_more == 0)
31579 can_issue_more = issue_rate - 1;
31582 for (i = 0; i < issue_rate; i++)
31584 group_insns[i] = 0;
31591 emit_insn_before (nop, next_insn);
31592 if (can_issue_more == issue_rate - 1) /* new group begins */
31595 if (can_issue_more == 0)
31597 can_issue_more = issue_rate - 1;
31600 for (i = 0; i < issue_rate; i++)
31602 group_insns[i] = 0;
31608 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31611 /* Is next_insn going to start a new group? */
31614 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31615 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31616 || (can_issue_more < issue_rate &&
31617 insn_terminates_group_p (next_insn, previous_group)));
31618 if (*group_end && end)
31621 if (sched_verbose > 6)
31622 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31623 *group_count, can_issue_more);
31624 return can_issue_more;
31627 return can_issue_more;
31630 /* This function tries to synch the dispatch groups that the compiler "sees"
31631 with the dispatch groups that the processor dispatcher is expected to
31632 form in practice. It tries to achieve this synchronization by forcing the
31633 estimated processor grouping on the compiler (as opposed to the function
31634 'pad_goups' which tries to force the scheduler's grouping on the processor).
31636 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31637 examines the (estimated) dispatch groups that will be formed by the processor
31638 dispatcher. It marks these group boundaries to reflect the estimated
31639 processor grouping, overriding the grouping that the scheduler had marked.
31640 Depending on the value of the flag '-minsert-sched-nops' this function can
31641 force certain insns into separate groups or force a certain distance between
31642 them by inserting nops, for example, if there exists a "costly dependence"
31645 The function estimates the group boundaries that the processor will form as
31646 follows: It keeps track of how many vacant issue slots are available after
31647 each insn. A subsequent insn will start a new group if one of the following
31649 - no more vacant issue slots remain in the current dispatch group.
31650 - only the last issue slot, which is the branch slot, is vacant, but the next
31651 insn is not a branch.
31652 - only the last 2 or less issue slots, including the branch slot, are vacant,
31653 which means that a cracked insn (which occupies two issue slots) can't be
31654 issued in this group.
31655 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31656 start a new group. */
31659 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31662 rtx_insn *insn, *next_insn;
31664 int can_issue_more;
31667 int group_count = 0;
31671 issue_rate = rs6000_issue_rate ();
31672 group_insns = XALLOCAVEC (rtx, issue_rate);
31673 for (i = 0; i < issue_rate; i++)
31675 group_insns[i] = 0;
31677 can_issue_more = issue_rate;
31679 insn = get_next_active_insn (prev_head_insn, tail);
31682 while (insn != NULL_RTX)
31684 slot = (issue_rate - can_issue_more);
31685 group_insns[slot] = insn;
31687 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31688 if (insn_terminates_group_p (insn, current_group))
31689 can_issue_more = 0;
31691 next_insn = get_next_active_insn (insn, tail);
31692 if (next_insn == NULL_RTX)
31693 return group_count + 1;
31695 /* Is next_insn going to start a new group? */
31697 = (can_issue_more == 0
31698 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31699 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31700 || (can_issue_more < issue_rate &&
31701 insn_terminates_group_p (next_insn, previous_group)));
31703 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
31704 next_insn, &group_end, can_issue_more,
31710 can_issue_more = 0;
31711 for (i = 0; i < issue_rate; i++)
31713 group_insns[i] = 0;
31717 if (GET_MODE (next_insn) == TImode && can_issue_more)
31718 PUT_MODE (next_insn, VOIDmode);
31719 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
31720 PUT_MODE (next_insn, TImode);
31723 if (can_issue_more == 0)
31724 can_issue_more = issue_rate;
31727 return group_count;
31730 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
31731 dispatch group boundaries that the scheduler had marked. Pad with nops
31732 any dispatch groups which have vacant issue slots, in order to force the
31733 scheduler's grouping on the processor dispatcher. The function
31734 returns the number of dispatch groups found. */
31737 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31740 rtx_insn *insn, *next_insn;
31743 int can_issue_more;
31745 int group_count = 0;
31747 /* Initialize issue_rate. */
31748 issue_rate = rs6000_issue_rate ();
31749 can_issue_more = issue_rate;
31751 insn = get_next_active_insn (prev_head_insn, tail);
31752 next_insn = get_next_active_insn (insn, tail);
31754 while (insn != NULL_RTX)
31757 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31759 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
31761 if (next_insn == NULL_RTX)
31766 /* If the scheduler had marked group termination at this location
31767 (between insn and next_insn), and neither insn nor next_insn will
31768 force group termination, pad the group with nops to force group
31771 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
31772 && !insn_terminates_group_p (insn, current_group)
31773 && !insn_terminates_group_p (next_insn, previous_group))
31775 if (!is_branch_slot_insn (next_insn))
31778 while (can_issue_more)
31781 emit_insn_before (nop, next_insn);
31786 can_issue_more = issue_rate;
31791 next_insn = get_next_active_insn (insn, tail);
31794 return group_count;
31797 /* We're beginning a new block. Initialize data structures as necessary. */
31800 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
31801 int sched_verbose ATTRIBUTE_UNUSED,
31802 int max_ready ATTRIBUTE_UNUSED)
31804 last_scheduled_insn = NULL;
31805 load_store_pendulum = 0;
31810 /* The following function is called at the end of scheduling BB.
31811 After reload, it inserts nops at insn group bundling. */
31814 rs6000_sched_finish (FILE *dump, int sched_verbose)
31819 fprintf (dump, "=== Finishing schedule.\n");
31821 if (reload_completed && rs6000_sched_groups)
31823 /* Do not run sched_finish hook when selective scheduling enabled. */
31824 if (sel_sched_p ())
31827 if (rs6000_sched_insert_nops == sched_finish_none)
31830 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
31831 n_groups = pad_groups (dump, sched_verbose,
31832 current_sched_info->prev_head,
31833 current_sched_info->next_tail);
31835 n_groups = redefine_groups (dump, sched_verbose,
31836 current_sched_info->prev_head,
31837 current_sched_info->next_tail);
31839 if (sched_verbose >= 6)
31841 fprintf (dump, "ngroups = %d\n", n_groups);
31842 print_rtl (dump, current_sched_info->prev_head);
31843 fprintf (dump, "Done finish_sched\n");
31848 struct rs6000_sched_context
31850 short cached_can_issue_more;
31851 rtx_insn *last_scheduled_insn;
31852 int load_store_pendulum;
31857 typedef struct rs6000_sched_context rs6000_sched_context_def;
31858 typedef rs6000_sched_context_def *rs6000_sched_context_t;
31860 /* Allocate store for new scheduling context. */
31862 rs6000_alloc_sched_context (void)
31864 return xmalloc (sizeof (rs6000_sched_context_def));
31867 /* If CLEAN_P is true then initializes _SC with clean data,
31868 and from the global context otherwise. */
31870 rs6000_init_sched_context (void *_sc, bool clean_p)
31872 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
31876 sc->cached_can_issue_more = 0;
31877 sc->last_scheduled_insn = NULL;
31878 sc->load_store_pendulum = 0;
31879 sc->divide_cnt = 0;
31880 sc->vec_pairing = 0;
31884 sc->cached_can_issue_more = cached_can_issue_more;
31885 sc->last_scheduled_insn = last_scheduled_insn;
31886 sc->load_store_pendulum = load_store_pendulum;
31887 sc->divide_cnt = divide_cnt;
31888 sc->vec_pairing = vec_pairing;
31892 /* Sets the global scheduling context to the one pointed to by _SC. */
31894 rs6000_set_sched_context (void *_sc)
31896 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
31898 gcc_assert (sc != NULL);
31900 cached_can_issue_more = sc->cached_can_issue_more;
31901 last_scheduled_insn = sc->last_scheduled_insn;
31902 load_store_pendulum = sc->load_store_pendulum;
31903 divide_cnt = sc->divide_cnt;
31904 vec_pairing = sc->vec_pairing;
31909 rs6000_free_sched_context (void *_sc)
31911 gcc_assert (_sc != NULL);
31917 rs6000_sched_can_speculate_insn (rtx_insn *insn)
31919 switch (get_attr_type (insn))
31934 /* Length in units of the trampoline for entering a nested function. */
31937 rs6000_trampoline_size (void)
31941 switch (DEFAULT_ABI)
31944 gcc_unreachable ();
31947 ret = (TARGET_32BIT) ? 12 : 24;
31951 gcc_assert (!TARGET_32BIT);
31957 ret = (TARGET_32BIT) ? 40 : 48;
31964 /* Emit RTL insns to initialize the variable parts of a trampoline.
31965 FNADDR is an RTX for the address of the function's pure code.
31966 CXT is an RTX for the static chain value for the function. */
31969 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
31971 int regsize = (TARGET_32BIT) ? 4 : 8;
31972 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
31973 rtx ctx_reg = force_reg (Pmode, cxt);
31974 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
31976 switch (DEFAULT_ABI)
31979 gcc_unreachable ();
31981 /* Under AIX, just build the 3 word function descriptor */
31984 rtx fnmem, fn_reg, toc_reg;
31986 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
31987 error ("you cannot take the address of a nested function if you use "
31988 "the %qs option", "-mno-pointers-to-nested-functions");
31990 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
31991 fn_reg = gen_reg_rtx (Pmode);
31992 toc_reg = gen_reg_rtx (Pmode);
31994 /* Macro to shorten the code expansions below. */
31995 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
31997 m_tramp = replace_equiv_address (m_tramp, addr);
31999 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32000 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32001 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32002 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32003 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32009 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32013 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32014 LCT_NORMAL, VOIDmode,
32016 GEN_INT (rs6000_trampoline_size ()), SImode,
32024 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32025 identifier as an argument, so the front end shouldn't look it up. */
32028 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32030 return is_attribute_p ("altivec", attr_id);
32033 /* Handle the "altivec" attribute. The attribute may have
32034 arguments as follows:
32036 __attribute__((altivec(vector__)))
32037 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32038 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32040 and may appear more than once (e.g., 'vector bool char') in a
32041 given declaration. */
32044 rs6000_handle_altivec_attribute (tree *node,
32045 tree name ATTRIBUTE_UNUSED,
32047 int flags ATTRIBUTE_UNUSED,
32048 bool *no_add_attrs)
32050 tree type = *node, result = NULL_TREE;
32054 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32055 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32056 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32059 while (POINTER_TYPE_P (type)
32060 || TREE_CODE (type) == FUNCTION_TYPE
32061 || TREE_CODE (type) == METHOD_TYPE
32062 || TREE_CODE (type) == ARRAY_TYPE)
32063 type = TREE_TYPE (type);
32065 mode = TYPE_MODE (type);
32067 /* Check for invalid AltiVec type qualifiers. */
32068 if (type == long_double_type_node)
32069 error ("use of %<long double%> in AltiVec types is invalid");
32070 else if (type == boolean_type_node)
32071 error ("use of boolean types in AltiVec types is invalid");
32072 else if (TREE_CODE (type) == COMPLEX_TYPE)
32073 error ("use of %<complex%> in AltiVec types is invalid");
32074 else if (DECIMAL_FLOAT_MODE_P (mode))
32075 error ("use of decimal floating point types in AltiVec types is invalid");
32076 else if (!TARGET_VSX)
32078 if (type == long_unsigned_type_node || type == long_integer_type_node)
32081 error ("use of %<long%> in AltiVec types is invalid for "
32082 "64-bit code without %qs", "-mvsx");
32083 else if (rs6000_warn_altivec_long)
32084 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32087 else if (type == long_long_unsigned_type_node
32088 || type == long_long_integer_type_node)
32089 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32091 else if (type == double_type_node)
32092 error ("use of %<double%> in AltiVec types is invalid without %qs",
32096 switch (altivec_type)
32099 unsigned_p = TYPE_UNSIGNED (type);
32103 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32106 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32109 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32112 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32115 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32117 case E_SFmode: result = V4SF_type_node; break;
32118 case E_DFmode: result = V2DF_type_node; break;
32119 /* If the user says 'vector int bool', we may be handed the 'bool'
32120 attribute _before_ the 'vector' attribute, and so select the
32121 proper type in the 'b' case below. */
32122 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32123 case E_V2DImode: case E_V2DFmode:
32131 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32132 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32133 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32134 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32141 case E_V8HImode: result = pixel_V8HI_type_node;
32147 /* Propagate qualifiers attached to the element type
32148 onto the vector type. */
32149 if (result && result != type && TYPE_QUALS (type))
32150 result = build_qualified_type (result, TYPE_QUALS (type));
32152 *no_add_attrs = true; /* No need to hang on to the attribute. */
32155 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32160 /* AltiVec defines five built-in scalar types that serve as vector
32161 elements; we must teach the compiler how to mangle them. The 128-bit
32162 floating point mangling is target-specific as well. */
32164 static const char *
32165 rs6000_mangle_type (const_tree type)
32167 type = TYPE_MAIN_VARIANT (type);
32169 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32170 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32173 if (type == bool_char_type_node) return "U6__boolc";
32174 if (type == bool_short_type_node) return "U6__bools";
32175 if (type == pixel_type_node) return "u7__pixel";
32176 if (type == bool_int_type_node) return "U6__booli";
32177 if (type == bool_long_long_type_node) return "U6__boolx";
32179 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32181 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32182 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32184 /* For all other types, use the default mangling. */
32188 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32189 struct attribute_spec.handler. */
32192 rs6000_handle_longcall_attribute (tree *node, tree name,
32193 tree args ATTRIBUTE_UNUSED,
32194 int flags ATTRIBUTE_UNUSED,
32195 bool *no_add_attrs)
32197 if (TREE_CODE (*node) != FUNCTION_TYPE
32198 && TREE_CODE (*node) != FIELD_DECL
32199 && TREE_CODE (*node) != TYPE_DECL)
32201 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32203 *no_add_attrs = true;
32209 /* Set longcall attributes on all functions declared when
32210 rs6000_default_long_calls is true. */
32212 rs6000_set_default_type_attributes (tree type)
32214 if (rs6000_default_long_calls
32215 && (TREE_CODE (type) == FUNCTION_TYPE
32216 || TREE_CODE (type) == METHOD_TYPE))
32217 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32219 TYPE_ATTRIBUTES (type));
32222 darwin_set_default_type_attributes (type);
32226 /* Return a reference suitable for calling a function with the
32227 longcall attribute. */
32230 rs6000_longcall_ref (rtx call_ref)
32232 const char *call_name;
32235 if (GET_CODE (call_ref) != SYMBOL_REF)
32238 /* System V adds '.' to the internal name, so skip them. */
32239 call_name = XSTR (call_ref, 0);
32240 if (*call_name == '.')
32242 while (*call_name == '.')
32245 node = get_identifier (call_name);
32246 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32249 return force_reg (Pmode, call_ref);
32252 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32253 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32256 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32257 struct attribute_spec.handler. */
32259 rs6000_handle_struct_attribute (tree *node, tree name,
32260 tree args ATTRIBUTE_UNUSED,
32261 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32264 if (DECL_P (*node))
32266 if (TREE_CODE (*node) == TYPE_DECL)
32267 type = &TREE_TYPE (*node);
32272 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32273 || TREE_CODE (*type) == UNION_TYPE)))
32275 warning (OPT_Wattributes, "%qE attribute ignored", name);
32276 *no_add_attrs = true;
32279 else if ((is_attribute_p ("ms_struct", name)
32280 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32281 || ((is_attribute_p ("gcc_struct", name)
32282 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32284 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32286 *no_add_attrs = true;
32293 rs6000_ms_bitfield_layout_p (const_tree record_type)
32295 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32296 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32297 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32300 #ifdef USING_ELFOS_H
32302 /* A get_unnamed_section callback, used for switching to toc_section. */
32305 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32307 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32308 && TARGET_MINIMAL_TOC)
32310 if (!toc_initialized)
32312 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32313 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32314 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32315 fprintf (asm_out_file, "\t.tc ");
32316 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32317 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32318 fprintf (asm_out_file, "\n");
32320 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32321 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32322 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32323 fprintf (asm_out_file, " = .+32768\n");
32324 toc_initialized = 1;
32327 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32329 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32331 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32332 if (!toc_initialized)
32334 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32335 toc_initialized = 1;
32340 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32341 if (!toc_initialized)
32343 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32344 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32345 fprintf (asm_out_file, " = .+32768\n");
32346 toc_initialized = 1;
32351 /* Implement TARGET_ASM_INIT_SECTIONS. */
32354 rs6000_elf_asm_init_sections (void)
32357 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32360 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32361 SDATA2_SECTION_ASM_OP);
32364 /* Implement TARGET_SELECT_RTX_SECTION. */
32367 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32368 unsigned HOST_WIDE_INT align)
32370 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32371 return toc_section;
32373 return default_elf_select_rtx_section (mode, x, align);
32376 /* For a SYMBOL_REF, set generic flags and then perform some
32377 target-specific processing.
32379 When the AIX ABI is requested on a non-AIX system, replace the
32380 function name with the real name (with a leading .) rather than the
32381 function descriptor name. This saves a lot of overriding code to
32382 read the prefixes. */
32384 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32386 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32388 default_encode_section_info (decl, rtl, first);
32391 && TREE_CODE (decl) == FUNCTION_DECL
32393 && DEFAULT_ABI == ABI_AIX)
32395 rtx sym_ref = XEXP (rtl, 0);
32396 size_t len = strlen (XSTR (sym_ref, 0));
32397 char *str = XALLOCAVEC (char, len + 2);
32399 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32400 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32405 compare_section_name (const char *section, const char *templ)
32409 len = strlen (templ);
32410 return (strncmp (section, templ, len) == 0
32411 && (section[len] == 0 || section[len] == '.'));
32415 rs6000_elf_in_small_data_p (const_tree decl)
32417 if (rs6000_sdata == SDATA_NONE)
32420 /* We want to merge strings, so we never consider them small data. */
32421 if (TREE_CODE (decl) == STRING_CST)
32424 /* Functions are never in the small data area. */
32425 if (TREE_CODE (decl) == FUNCTION_DECL)
32428 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32430 const char *section = DECL_SECTION_NAME (decl);
32431 if (compare_section_name (section, ".sdata")
32432 || compare_section_name (section, ".sdata2")
32433 || compare_section_name (section, ".gnu.linkonce.s")
32434 || compare_section_name (section, ".sbss")
32435 || compare_section_name (section, ".sbss2")
32436 || compare_section_name (section, ".gnu.linkonce.sb")
32437 || strcmp (section, ".PPC.EMB.sdata0") == 0
32438 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32443 /* If we are told not to put readonly data in sdata, then don't. */
32444 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32445 && !rs6000_readonly_in_sdata)
32448 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32451 && size <= g_switch_value
32452 /* If it's not public, and we're not going to reference it there,
32453 there's no need to put it in the small data section. */
32454 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32461 #endif /* USING_ELFOS_H */
32463 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32466 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32468 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32471 /* Do not place thread-local symbols refs in the object blocks. */
32474 rs6000_use_blocks_for_decl_p (const_tree decl)
32476 return !DECL_THREAD_LOCAL_P (decl);
32479 /* Return a REG that occurs in ADDR with coefficient 1.
32480 ADDR can be effectively incremented by incrementing REG.
32482 r0 is special and we must not select it as an address
32483 register by this routine since our caller will try to
32484 increment the returned register via an "la" instruction. */
32487 find_addr_reg (rtx addr)
32489 while (GET_CODE (addr) == PLUS)
32491 if (GET_CODE (XEXP (addr, 0)) == REG
32492 && REGNO (XEXP (addr, 0)) != 0)
32493 addr = XEXP (addr, 0);
32494 else if (GET_CODE (XEXP (addr, 1)) == REG
32495 && REGNO (XEXP (addr, 1)) != 0)
32496 addr = XEXP (addr, 1);
32497 else if (CONSTANT_P (XEXP (addr, 0)))
32498 addr = XEXP (addr, 1);
32499 else if (CONSTANT_P (XEXP (addr, 1)))
32500 addr = XEXP (addr, 0);
32502 gcc_unreachable ();
32504 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
32509 rs6000_fatal_bad_address (rtx op)
32511 fatal_insn ("bad address", op);
32516 typedef struct branch_island_d {
32517 tree function_name;
32523 static vec<branch_island, va_gc> *branch_islands;
32525 /* Remember to generate a branch island for far calls to the given
32529 add_compiler_branch_island (tree label_name, tree function_name,
32532 branch_island bi = {function_name, label_name, line_number};
32533 vec_safe_push (branch_islands, bi);
32536 /* Generate far-jump branch islands for everything recorded in
32537 branch_islands. Invoked immediately after the last instruction of
32538 the epilogue has been emitted; the branch islands must be appended
32539 to, and contiguous with, the function body. Mach-O stubs are
32540 generated in machopic_output_stub(). */
32543 macho_branch_islands (void)
32547 while (!vec_safe_is_empty (branch_islands))
32549 branch_island *bi = &branch_islands->last ();
32550 const char *label = IDENTIFIER_POINTER (bi->label_name);
32551 const char *name = IDENTIFIER_POINTER (bi->function_name);
32552 char name_buf[512];
32553 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32554 if (name[0] == '*' || name[0] == '&')
32555 strcpy (name_buf, name+1);
32559 strcpy (name_buf+1, name);
32561 strcpy (tmp_buf, "\n");
32562 strcat (tmp_buf, label);
32563 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32564 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32565 dbxout_stabd (N_SLINE, bi->line_number);
32566 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32569 if (TARGET_LINK_STACK)
32572 get_ppc476_thunk_name (name);
32573 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32574 strcat (tmp_buf, name);
32575 strcat (tmp_buf, "\n");
32576 strcat (tmp_buf, label);
32577 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32581 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32582 strcat (tmp_buf, label);
32583 strcat (tmp_buf, "_pic\n");
32584 strcat (tmp_buf, label);
32585 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32588 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32589 strcat (tmp_buf, name_buf);
32590 strcat (tmp_buf, " - ");
32591 strcat (tmp_buf, label);
32592 strcat (tmp_buf, "_pic)\n");
32594 strcat (tmp_buf, "\tmtlr r0\n");
32596 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32597 strcat (tmp_buf, name_buf);
32598 strcat (tmp_buf, " - ");
32599 strcat (tmp_buf, label);
32600 strcat (tmp_buf, "_pic)\n");
32602 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32606 strcat (tmp_buf, ":\nlis r12,hi16(");
32607 strcat (tmp_buf, name_buf);
32608 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32609 strcat (tmp_buf, name_buf);
32610 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32612 output_asm_insn (tmp_buf, 0);
32613 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32614 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32615 dbxout_stabd (N_SLINE, bi->line_number);
32616 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32617 branch_islands->pop ();
32621 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32622 already there or not. */
32625 no_previous_def (tree function_name)
32630 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32631 if (function_name == bi->function_name)
32636 /* GET_PREV_LABEL gets the label name from the previous definition of
32640 get_prev_label (tree function_name)
32645 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32646 if (function_name == bi->function_name)
32647 return bi->label_name;
32651 /* INSN is either a function call or a millicode call. It may have an
32652 unconditional jump in its delay slot.
32654 CALL_DEST is the routine we are calling. */
32657 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
32658 int cookie_operand_number)
32660 static char buf[256];
32661 if (darwin_emit_branch_islands
32662 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
32663 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
32666 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
32668 if (no_previous_def (funname))
32670 rtx label_rtx = gen_label_rtx ();
32671 char *label_buf, temp_buf[256];
32672 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
32673 CODE_LABEL_NUMBER (label_rtx));
32674 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
32675 labelname = get_identifier (label_buf);
32676 add_compiler_branch_island (labelname, funname, insn_line (insn));
32679 labelname = get_prev_label (funname);
32681 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
32682 instruction will reach 'foo', otherwise link as 'bl L42'".
32683 "L42" should be a 'branch island', that will do a far jump to
32684 'foo'. Branch islands are generated in
32685 macho_branch_islands(). */
32686 sprintf (buf, "jbsr %%z%d,%.246s",
32687 dest_operand_number, IDENTIFIER_POINTER (labelname));
32690 sprintf (buf, "bl %%z%d", dest_operand_number);
32694 /* Generate PIC and indirect symbol stubs. */
32697 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32699 unsigned int length;
32700 char *symbol_name, *lazy_ptr_name;
32701 char *local_label_0;
32702 static int label = 0;
32704 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32705 symb = (*targetm.strip_name_encoding) (symb);
32708 length = strlen (symb);
32709 symbol_name = XALLOCAVEC (char, length + 32);
32710 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
32712 lazy_ptr_name = XALLOCAVEC (char, length + 32);
32713 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
32716 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
32718 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
32722 fprintf (file, "\t.align 5\n");
32724 fprintf (file, "%s:\n", stub);
32725 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32728 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
32729 sprintf (local_label_0, "\"L%011d$spb\"", label);
32731 fprintf (file, "\tmflr r0\n");
32732 if (TARGET_LINK_STACK)
32735 get_ppc476_thunk_name (name);
32736 fprintf (file, "\tbl %s\n", name);
32737 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32741 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
32742 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32744 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
32745 lazy_ptr_name, local_label_0);
32746 fprintf (file, "\tmtlr r0\n");
32747 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
32748 (TARGET_64BIT ? "ldu" : "lwzu"),
32749 lazy_ptr_name, local_label_0);
32750 fprintf (file, "\tmtctr r12\n");
32751 fprintf (file, "\tbctr\n");
32755 fprintf (file, "\t.align 4\n");
32757 fprintf (file, "%s:\n", stub);
32758 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32760 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
32761 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
32762 (TARGET_64BIT ? "ldu" : "lwzu"),
32764 fprintf (file, "\tmtctr r12\n");
32765 fprintf (file, "\tbctr\n");
32768 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
32769 fprintf (file, "%s:\n", lazy_ptr_name);
32770 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32771 fprintf (file, "%sdyld_stub_binding_helper\n",
32772 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
32775 /* Legitimize PIC addresses. If the address is already
32776 position-independent, we return ORIG. Newly generated
32777 position-independent addresses go into a reg. This is REG if non
32778 zero, otherwise we allocate register(s) as necessary. */
32780 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
32783 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
32788 if (reg == NULL && !reload_completed)
32789 reg = gen_reg_rtx (Pmode);
32791 if (GET_CODE (orig) == CONST)
32795 if (GET_CODE (XEXP (orig, 0)) == PLUS
32796 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
32799 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
32801 /* Use a different reg for the intermediate value, as
32802 it will be marked UNCHANGING. */
32803 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
32804 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
32807 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
32810 if (GET_CODE (offset) == CONST_INT)
32812 if (SMALL_INT (offset))
32813 return plus_constant (Pmode, base, INTVAL (offset));
32814 else if (!reload_completed)
32815 offset = force_reg (Pmode, offset);
32818 rtx mem = force_const_mem (Pmode, orig);
32819 return machopic_legitimize_pic_address (mem, Pmode, reg);
32822 return gen_rtx_PLUS (Pmode, base, offset);
32825 /* Fall back on generic machopic code. */
32826 return machopic_legitimize_pic_address (orig, mode, reg);
32829 /* Output a .machine directive for the Darwin assembler, and call
32830 the generic start_file routine. */
32833 rs6000_darwin_file_start (void)
32835 static const struct
32839 HOST_WIDE_INT if_set;
32841 { "ppc64", "ppc64", MASK_64BIT },
32842 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
32843 { "power4", "ppc970", 0 },
32844 { "G5", "ppc970", 0 },
32845 { "7450", "ppc7450", 0 },
32846 { "7400", "ppc7400", MASK_ALTIVEC },
32847 { "G4", "ppc7400", 0 },
32848 { "750", "ppc750", 0 },
32849 { "740", "ppc750", 0 },
32850 { "G3", "ppc750", 0 },
32851 { "604e", "ppc604e", 0 },
32852 { "604", "ppc604", 0 },
32853 { "603e", "ppc603", 0 },
32854 { "603", "ppc603", 0 },
32855 { "601", "ppc601", 0 },
32856 { NULL, "ppc", 0 } };
32857 const char *cpu_id = "";
32860 rs6000_file_start ();
32861 darwin_file_start ();
32863 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
32865 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
32866 cpu_id = rs6000_default_cpu;
32868 if (global_options_set.x_rs6000_cpu_index)
32869 cpu_id = processor_target_table[rs6000_cpu_index].name;
32871 /* Look through the mapping array. Pick the first name that either
32872 matches the argument, has a bit set in IF_SET that is also set
32873 in the target flags, or has a NULL name. */
32876 while (mapping[i].arg != NULL
32877 && strcmp (mapping[i].arg, cpu_id) != 0
32878 && (mapping[i].if_set & rs6000_isa_flags) == 0)
32881 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
32884 #endif /* TARGET_MACHO */
32888 rs6000_elf_reloc_rw_mask (void)
32892 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32898 /* Record an element in the table of global constructors. SYMBOL is
32899 a SYMBOL_REF of the function to be called; PRIORITY is a number
32900 between 0 and MAX_INIT_PRIORITY.
32902 This differs from default_named_section_asm_out_constructor in
32903 that we have special handling for -mrelocatable. */
32905 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
32907 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
32909 const char *section = ".ctors";
32912 if (priority != DEFAULT_INIT_PRIORITY)
32914 sprintf (buf, ".ctors.%.5u",
32915 /* Invert the numbering so the linker puts us in the proper
32916 order; constructors are run from right to left, and the
32917 linker sorts in increasing order. */
32918 MAX_INIT_PRIORITY - priority);
32922 switch_to_section (get_section (section, SECTION_WRITE, NULL));
32923 assemble_align (POINTER_SIZE);
32925 if (DEFAULT_ABI == ABI_V4
32926 && (TARGET_RELOCATABLE || flag_pic > 1))
32928 fputs ("\t.long (", asm_out_file);
32929 output_addr_const (asm_out_file, symbol);
32930 fputs (")@fixup\n", asm_out_file);
32933 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
32936 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
32938 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
32940 const char *section = ".dtors";
32943 if (priority != DEFAULT_INIT_PRIORITY)
32945 sprintf (buf, ".dtors.%.5u",
32946 /* Invert the numbering so the linker puts us in the proper
32947 order; constructors are run from right to left, and the
32948 linker sorts in increasing order. */
32949 MAX_INIT_PRIORITY - priority);
32953 switch_to_section (get_section (section, SECTION_WRITE, NULL));
32954 assemble_align (POINTER_SIZE);
32956 if (DEFAULT_ABI == ABI_V4
32957 && (TARGET_RELOCATABLE || flag_pic > 1))
32959 fputs ("\t.long (", asm_out_file);
32960 output_addr_const (asm_out_file, symbol);
32961 fputs (")@fixup\n", asm_out_file);
32964 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
32968 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
32970 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
32972 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
32973 ASM_OUTPUT_LABEL (file, name);
32974 fputs (DOUBLE_INT_ASM_OP, file);
32975 rs6000_output_function_entry (file, name);
32976 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
32979 fputs ("\t.size\t", file);
32980 assemble_name (file, name);
32981 fputs (",24\n\t.type\t.", file);
32982 assemble_name (file, name);
32983 fputs (",@function\n", file);
32984 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
32986 fputs ("\t.globl\t.", file);
32987 assemble_name (file, name);
32992 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
32993 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
32994 rs6000_output_function_entry (file, name);
32995 fputs (":\n", file);
33000 if (DEFAULT_ABI == ABI_V4
33001 && (TARGET_RELOCATABLE || flag_pic > 1)
33002 && !TARGET_SECURE_PLT
33003 && (!constant_pool_empty_p () || crtl->profile)
33004 && (uses_toc = uses_TOC ()))
33009 switch_to_other_text_partition ();
33010 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33012 fprintf (file, "\t.long ");
33013 assemble_name (file, toc_label_name);
33016 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33017 assemble_name (file, buf);
33020 switch_to_other_text_partition ();
33023 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33024 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33026 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33030 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33032 fprintf (file, "\t.quad .TOC.-");
33033 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33034 assemble_name (file, buf);
33038 if (DEFAULT_ABI == ABI_AIX)
33040 const char *desc_name, *orig_name;
33042 orig_name = (*targetm.strip_name_encoding) (name);
33043 desc_name = orig_name;
33044 while (*desc_name == '.')
33047 if (TREE_PUBLIC (decl))
33048 fprintf (file, "\t.globl %s\n", desc_name);
33050 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33051 fprintf (file, "%s:\n", desc_name);
33052 fprintf (file, "\t.long %s\n", orig_name);
33053 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33054 fputs ("\t.long 0\n", file);
33055 fprintf (file, "\t.previous\n");
33057 ASM_OUTPUT_LABEL (file, name);
33060 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33062 rs6000_elf_file_end (void)
33064 #ifdef HAVE_AS_GNU_ATTRIBUTE
33065 /* ??? The value emitted depends on options active at file end.
33066 Assume anyone using #pragma or attributes that might change
33067 options knows what they are doing. */
33068 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33069 && rs6000_passes_float)
33073 if (TARGET_HARD_FLOAT)
33077 if (rs6000_passes_long_double)
33079 if (!TARGET_LONG_DOUBLE_128)
33081 else if (TARGET_IEEEQUAD)
33086 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33088 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33090 if (rs6000_passes_vector)
33091 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33092 (TARGET_ALTIVEC_ABI ? 2 : 1));
33093 if (rs6000_returns_struct)
33094 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33095 aix_struct_return ? 2 : 1);
33098 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33099 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33100 file_end_indicate_exec_stack ();
33103 if (flag_split_stack)
33104 file_end_indicate_split_stack ();
33108 /* We have expanded a CPU builtin, so we need to emit a reference to
33109 the special symbol that LIBC uses to declare it supports the
33110 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33111 switch_to_section (data_section);
33112 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33113 fprintf (asm_out_file, "\t%s %s\n",
33114 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33121 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33122 #define HAVE_XCOFF_DWARF_EXTRAS 0
33125 static enum unwind_info_type
33126 rs6000_xcoff_debug_unwind_info (void)
33132 rs6000_xcoff_asm_output_anchor (rtx symbol)
33136 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33137 SYMBOL_REF_BLOCK_OFFSET (symbol));
33138 fprintf (asm_out_file, "%s", SET_ASM_OP);
33139 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33140 fprintf (asm_out_file, ",");
33141 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33142 fprintf (asm_out_file, "\n");
33146 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33148 fputs (GLOBAL_ASM_OP, stream);
33149 RS6000_OUTPUT_BASENAME (stream, name);
33150 putc ('\n', stream);
33153 /* A get_unnamed_decl callback, used for read-only sections. PTR
33154 points to the section string variable. */
33157 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33159 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33160 *(const char *const *) directive,
33161 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33164 /* Likewise for read-write sections. */
33167 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33169 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33170 *(const char *const *) directive,
33171 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33175 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33177 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33178 *(const char *const *) directive,
33179 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33182 /* A get_unnamed_section callback, used for switching to toc_section. */
33185 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33187 if (TARGET_MINIMAL_TOC)
33189 /* toc_section is always selected at least once from
33190 rs6000_xcoff_file_start, so this is guaranteed to
33191 always be defined once and only once in each file. */
33192 if (!toc_initialized)
33194 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33195 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33196 toc_initialized = 1;
33198 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33199 (TARGET_32BIT ? "" : ",3"));
33202 fputs ("\t.toc\n", asm_out_file);
33205 /* Implement TARGET_ASM_INIT_SECTIONS. */
33208 rs6000_xcoff_asm_init_sections (void)
33210 read_only_data_section
33211 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33212 &xcoff_read_only_section_name);
33214 private_data_section
33215 = get_unnamed_section (SECTION_WRITE,
33216 rs6000_xcoff_output_readwrite_section_asm_op,
33217 &xcoff_private_data_section_name);
33220 = get_unnamed_section (SECTION_TLS,
33221 rs6000_xcoff_output_tls_section_asm_op,
33222 &xcoff_tls_data_section_name);
33224 tls_private_data_section
33225 = get_unnamed_section (SECTION_TLS,
33226 rs6000_xcoff_output_tls_section_asm_op,
33227 &xcoff_private_data_section_name);
33229 read_only_private_data_section
33230 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33231 &xcoff_private_data_section_name);
33234 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33236 readonly_data_section = read_only_data_section;
33240 rs6000_xcoff_reloc_rw_mask (void)
33246 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33247 tree decl ATTRIBUTE_UNUSED)
33250 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33252 if (flags & SECTION_EXCLUDE)
33254 else if (flags & SECTION_DEBUG)
33256 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33259 else if (flags & SECTION_CODE)
33261 else if (flags & SECTION_TLS)
33263 else if (flags & SECTION_WRITE)
33268 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33269 (flags & SECTION_CODE) ? "." : "",
33270 name, suffix[smclass], flags & SECTION_ENTSIZE);
33273 #define IN_NAMED_SECTION(DECL) \
33274 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33275 && DECL_SECTION_NAME (DECL) != NULL)
33278 rs6000_xcoff_select_section (tree decl, int reloc,
33279 unsigned HOST_WIDE_INT align)
33281 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33283 if (align > BIGGEST_ALIGNMENT)
33285 resolve_unique_section (decl, reloc, true);
33286 if (IN_NAMED_SECTION (decl))
33287 return get_named_section (decl, NULL, reloc);
33290 if (decl_readonly_section (decl, reloc))
33292 if (TREE_PUBLIC (decl))
33293 return read_only_data_section;
33295 return read_only_private_data_section;
33300 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33302 if (TREE_PUBLIC (decl))
33303 return tls_data_section;
33304 else if (bss_initializer_p (decl))
33306 /* Convert to COMMON to emit in BSS. */
33307 DECL_COMMON (decl) = 1;
33308 return tls_comm_section;
33311 return tls_private_data_section;
33315 if (TREE_PUBLIC (decl))
33316 return data_section;
33318 return private_data_section;
33323 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33327 /* Use select_section for private data and uninitialized data with
33328 alignment <= BIGGEST_ALIGNMENT. */
33329 if (!TREE_PUBLIC (decl)
33330 || DECL_COMMON (decl)
33331 || (DECL_INITIAL (decl) == NULL_TREE
33332 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33333 || DECL_INITIAL (decl) == error_mark_node
33334 || (flag_zero_initialized_in_bss
33335 && initializer_zerop (DECL_INITIAL (decl))))
33338 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33339 name = (*targetm.strip_name_encoding) (name);
33340 set_decl_section_name (decl, name);
33343 /* Select section for constant in constant pool.
33345 On RS/6000, all constants are in the private read-only data area.
33346 However, if this is being placed in the TOC it must be output as a
33350 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33351 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33353 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33354 return toc_section;
33356 return read_only_private_data_section;
33359 /* Remove any trailing [DS] or the like from the symbol name. */
33361 static const char *
33362 rs6000_xcoff_strip_name_encoding (const char *name)
33367 len = strlen (name);
33368 if (name[len - 1] == ']')
33369 return ggc_alloc_string (name, len - 4);
33374 /* Section attributes. AIX is always PIC. */
33376 static unsigned int
33377 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33379 unsigned int align;
33380 unsigned int flags = default_section_type_flags (decl, name, reloc);
33382 /* Align to at least UNIT size. */
33383 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33384 align = MIN_UNITS_PER_WORD;
33386 /* Increase alignment of large objects if not already stricter. */
33387 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33388 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33389 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33391 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33394 /* Output at beginning of assembler file.
33396 Initialize the section names for the RS/6000 at this point.
33398 Specify filename, including full path, to assembler.
33400 We want to go into the TOC section so at least one .toc will be emitted.
33401 Also, in order to output proper .bs/.es pairs, we need at least one static
33402 [RW] section emitted.
33404 Finally, declare mcount when profiling to make the assembler happy. */
33407 rs6000_xcoff_file_start (void)
33409 rs6000_gen_section_name (&xcoff_bss_section_name,
33410 main_input_filename, ".bss_");
33411 rs6000_gen_section_name (&xcoff_private_data_section_name,
33412 main_input_filename, ".rw_");
33413 rs6000_gen_section_name (&xcoff_read_only_section_name,
33414 main_input_filename, ".ro_");
33415 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33416 main_input_filename, ".tls_");
33417 rs6000_gen_section_name (&xcoff_tbss_section_name,
33418 main_input_filename, ".tbss_[UL]");
33420 fputs ("\t.file\t", asm_out_file);
33421 output_quoted_string (asm_out_file, main_input_filename);
33422 fputc ('\n', asm_out_file);
33423 if (write_symbols != NO_DEBUG)
33424 switch_to_section (private_data_section);
33425 switch_to_section (toc_section);
33426 switch_to_section (text_section);
33428 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33429 rs6000_file_start ();
33432 /* Output at end of assembler file.
33433 On the RS/6000, referencing data should automatically pull in text. */
33436 rs6000_xcoff_file_end (void)
33438 switch_to_section (text_section);
33439 fputs ("_section_.text:\n", asm_out_file);
33440 switch_to_section (data_section);
33441 fputs (TARGET_32BIT
33442 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33446 struct declare_alias_data
33449 bool function_descriptor;
33452 /* Declare alias N. A helper function for for_node_and_aliases. */
33455 rs6000_declare_alias (struct symtab_node *n, void *d)
33457 struct declare_alias_data *data = (struct declare_alias_data *)d;
33458 /* Main symbol is output specially, because varasm machinery does part of
33459 the job for us - we do not need to declare .globl/lglobs and such. */
33460 if (!n->alias || n->weakref)
33463 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33466 /* Prevent assemble_alias from trying to use .set pseudo operation
33467 that does not behave as expected by the middle-end. */
33468 TREE_ASM_WRITTEN (n->decl) = true;
33470 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33471 char *buffer = (char *) alloca (strlen (name) + 2);
33473 int dollar_inside = 0;
33475 strcpy (buffer, name);
33476 p = strchr (buffer, '$');
33480 p = strchr (p + 1, '$');
33482 if (TREE_PUBLIC (n->decl))
33484 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33486 if (dollar_inside) {
33487 if (data->function_descriptor)
33488 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33489 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33491 if (data->function_descriptor)
33493 fputs ("\t.globl .", data->file);
33494 RS6000_OUTPUT_BASENAME (data->file, buffer);
33495 putc ('\n', data->file);
33497 fputs ("\t.globl ", data->file);
33498 RS6000_OUTPUT_BASENAME (data->file, buffer);
33499 putc ('\n', data->file);
33501 #ifdef ASM_WEAKEN_DECL
33502 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33503 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33510 if (data->function_descriptor)
33511 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33512 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33514 if (data->function_descriptor)
33516 fputs ("\t.lglobl .", data->file);
33517 RS6000_OUTPUT_BASENAME (data->file, buffer);
33518 putc ('\n', data->file);
33520 fputs ("\t.lglobl ", data->file);
33521 RS6000_OUTPUT_BASENAME (data->file, buffer);
33522 putc ('\n', data->file);
33524 if (data->function_descriptor)
33525 fputs (".", data->file);
33526 RS6000_OUTPUT_BASENAME (data->file, buffer);
33527 fputs (":\n", data->file);
33532 #ifdef HAVE_GAS_HIDDEN
33533 /* Helper function to calculate visibility of a DECL
33534 and return the value as a const string. */
33536 static const char *
33537 rs6000_xcoff_visibility (tree decl)
33539 static const char * const visibility_types[] = {
33540 "", ",protected", ",hidden", ",internal"
33543 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33544 return visibility_types[vis];
33549 /* This macro produces the initial definition of a function name.
33550 On the RS/6000, we need to place an extra '.' in the function name and
33551 output the function descriptor.
33552 Dollar signs are converted to underscores.
33554 The csect for the function will have already been created when
33555 text_section was selected. We do have to go back to that csect, however.
33557 The third and fourth parameters to the .function pseudo-op (16 and 044)
33558 are placeholders which no longer have any use.
33560 Because AIX assembler's .set command has unexpected semantics, we output
33561 all aliases as alternative labels in front of the definition. */
33564 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33566 char *buffer = (char *) alloca (strlen (name) + 1);
33568 int dollar_inside = 0;
33569 struct declare_alias_data data = {file, false};
33571 strcpy (buffer, name);
33572 p = strchr (buffer, '$');
33576 p = strchr (p + 1, '$');
33578 if (TREE_PUBLIC (decl))
33580 if (!RS6000_WEAK || !DECL_WEAK (decl))
33582 if (dollar_inside) {
33583 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33584 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33586 fputs ("\t.globl .", file);
33587 RS6000_OUTPUT_BASENAME (file, buffer);
33588 #ifdef HAVE_GAS_HIDDEN
33589 fputs (rs6000_xcoff_visibility (decl), file);
33596 if (dollar_inside) {
33597 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33598 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33600 fputs ("\t.lglobl .", file);
33601 RS6000_OUTPUT_BASENAME (file, buffer);
33604 fputs ("\t.csect ", file);
33605 RS6000_OUTPUT_BASENAME (file, buffer);
33606 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33607 RS6000_OUTPUT_BASENAME (file, buffer);
33608 fputs (":\n", file);
33609 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33611 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33612 RS6000_OUTPUT_BASENAME (file, buffer);
33613 fputs (", TOC[tc0], 0\n", file);
33615 switch_to_section (function_section (decl));
33617 RS6000_OUTPUT_BASENAME (file, buffer);
33618 fputs (":\n", file);
33619 data.function_descriptor = true;
33620 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33622 if (!DECL_IGNORED_P (decl))
33624 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33625 xcoffout_declare_function (file, decl, buffer);
33626 else if (write_symbols == DWARF2_DEBUG)
33628 name = (*targetm.strip_name_encoding) (name);
33629 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33636 /* Output assembly language to globalize a symbol from a DECL,
33637 possibly with visibility. */
33640 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33642 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33643 fputs (GLOBAL_ASM_OP, stream);
33644 RS6000_OUTPUT_BASENAME (stream, name);
33645 #ifdef HAVE_GAS_HIDDEN
33646 fputs (rs6000_xcoff_visibility (decl), stream);
33648 putc ('\n', stream);
33651 /* Output assembly language to define a symbol as COMMON from a DECL,
33652 possibly with visibility. */
33655 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33656 tree decl ATTRIBUTE_UNUSED,
33658 unsigned HOST_WIDE_INT size,
33659 unsigned HOST_WIDE_INT align)
33661 unsigned HOST_WIDE_INT align2 = 2;
33664 align2 = floor_log2 (align / BITS_PER_UNIT);
33668 fputs (COMMON_ASM_OP, stream);
33669 RS6000_OUTPUT_BASENAME (stream, name);
33672 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33675 #ifdef HAVE_GAS_HIDDEN
33677 fputs (rs6000_xcoff_visibility (decl), stream);
33679 putc ('\n', stream);
33682 /* This macro produces the initial definition of a object (variable) name.
33683 Because AIX assembler's .set command has unexpected semantics, we output
33684 all aliases as alternative labels in front of the definition. */
33687 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33689 struct declare_alias_data data = {file, false};
33690 RS6000_OUTPUT_BASENAME (file, name);
33691 fputs (":\n", file);
33692 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33696 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33699 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33701 fputs (integer_asm_op (size, FALSE), file);
33702 assemble_name (file, label);
33703 fputs ("-$", file);
33706 /* Output a symbol offset relative to the dbase for the current object.
33707 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
33710 __gcc_unwind_dbase is embedded in all executables/libraries through
33711 libgcc/config/rs6000/crtdbase.S. */
33714 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
33716 fputs (integer_asm_op (size, FALSE), file);
33717 assemble_name (file, label);
33718 fputs("-__gcc_unwind_dbase", file);
33723 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
33727 const char *symname;
33729 default_encode_section_info (decl, rtl, first);
33731 /* Careful not to prod global register variables. */
33734 symbol = XEXP (rtl, 0);
33735 if (GET_CODE (symbol) != SYMBOL_REF)
33738 flags = SYMBOL_REF_FLAGS (symbol);
33740 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33741 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
33743 SYMBOL_REF_FLAGS (symbol) = flags;
33745 /* Append mapping class to extern decls. */
33746 symname = XSTR (symbol, 0);
33747 if (decl /* sync condition with assemble_external () */
33748 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
33749 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
33750 || TREE_CODE (decl) == FUNCTION_DECL)
33751 && symname[strlen (symname) - 1] != ']')
33753 char *newname = (char *) alloca (strlen (symname) + 5);
33754 strcpy (newname, symname);
33755 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
33756 ? "[DS]" : "[UA]"));
33757 XSTR (symbol, 0) = ggc_strdup (newname);
33760 #endif /* HAVE_AS_TLS */
33761 #endif /* TARGET_XCOFF */
33764 rs6000_asm_weaken_decl (FILE *stream, tree decl,
33765 const char *name, const char *val)
33767 fputs ("\t.weak\t", stream);
33768 RS6000_OUTPUT_BASENAME (stream, name);
33769 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33770 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33773 fputs ("[DS]", stream);
33774 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33776 fputs (rs6000_xcoff_visibility (decl), stream);
33778 fputs ("\n\t.weak\t.", stream);
33779 RS6000_OUTPUT_BASENAME (stream, name);
33781 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33783 fputs (rs6000_xcoff_visibility (decl), stream);
33785 fputc ('\n', stream);
33788 #ifdef ASM_OUTPUT_DEF
33789 ASM_OUTPUT_DEF (stream, name, val);
33791 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33792 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33794 fputs ("\t.set\t.", stream);
33795 RS6000_OUTPUT_BASENAME (stream, name);
33796 fputs (",.", stream);
33797 RS6000_OUTPUT_BASENAME (stream, val);
33798 fputc ('\n', stream);
33804 /* Return true if INSN should not be copied. */
33807 rs6000_cannot_copy_insn_p (rtx_insn *insn)
33809 return recog_memoized (insn) >= 0
33810 && get_attr_cannot_copy (insn);
33813 /* Compute a (partial) cost for rtx X. Return true if the complete
33814 cost has been computed, and false if subexpressions should be
33815 scanned. In either case, *TOTAL contains the cost result. */
33818 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
33819 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
33821 int code = GET_CODE (x);
33825 /* On the RS/6000, if it is valid in the insn, it is free. */
33827 if (((outer_code == SET
33828 || outer_code == PLUS
33829 || outer_code == MINUS)
33830 && (satisfies_constraint_I (x)
33831 || satisfies_constraint_L (x)))
33832 || (outer_code == AND
33833 && (satisfies_constraint_K (x)
33835 ? satisfies_constraint_L (x)
33836 : satisfies_constraint_J (x))))
33837 || ((outer_code == IOR || outer_code == XOR)
33838 && (satisfies_constraint_K (x)
33840 ? satisfies_constraint_L (x)
33841 : satisfies_constraint_J (x))))
33842 || outer_code == ASHIFT
33843 || outer_code == ASHIFTRT
33844 || outer_code == LSHIFTRT
33845 || outer_code == ROTATE
33846 || outer_code == ROTATERT
33847 || outer_code == ZERO_EXTRACT
33848 || (outer_code == MULT
33849 && satisfies_constraint_I (x))
33850 || ((outer_code == DIV || outer_code == UDIV
33851 || outer_code == MOD || outer_code == UMOD)
33852 && exact_log2 (INTVAL (x)) >= 0)
33853 || (outer_code == COMPARE
33854 && (satisfies_constraint_I (x)
33855 || satisfies_constraint_K (x)))
33856 || ((outer_code == EQ || outer_code == NE)
33857 && (satisfies_constraint_I (x)
33858 || satisfies_constraint_K (x)
33860 ? satisfies_constraint_L (x)
33861 : satisfies_constraint_J (x))))
33862 || (outer_code == GTU
33863 && satisfies_constraint_I (x))
33864 || (outer_code == LTU
33865 && satisfies_constraint_P (x)))
33870 else if ((outer_code == PLUS
33871 && reg_or_add_cint_operand (x, VOIDmode))
33872 || (outer_code == MINUS
33873 && reg_or_sub_cint_operand (x, VOIDmode))
33874 || ((outer_code == SET
33875 || outer_code == IOR
33876 || outer_code == XOR)
33878 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
33880 *total = COSTS_N_INSNS (1);
33886 case CONST_WIDE_INT:
33890 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
33894 /* When optimizing for size, MEM should be slightly more expensive
33895 than generating address, e.g., (plus (reg) (const)).
33896 L1 cache latency is about two instructions. */
33897 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
33898 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
33899 *total += COSTS_N_INSNS (100);
33908 if (FLOAT_MODE_P (mode))
33909 *total = rs6000_cost->fp;
33911 *total = COSTS_N_INSNS (1);
33915 if (GET_CODE (XEXP (x, 1)) == CONST_INT
33916 && satisfies_constraint_I (XEXP (x, 1)))
33918 if (INTVAL (XEXP (x, 1)) >= -256
33919 && INTVAL (XEXP (x, 1)) <= 255)
33920 *total = rs6000_cost->mulsi_const9;
33922 *total = rs6000_cost->mulsi_const;
33924 else if (mode == SFmode)
33925 *total = rs6000_cost->fp;
33926 else if (FLOAT_MODE_P (mode))
33927 *total = rs6000_cost->dmul;
33928 else if (mode == DImode)
33929 *total = rs6000_cost->muldi;
33931 *total = rs6000_cost->mulsi;
33935 if (mode == SFmode)
33936 *total = rs6000_cost->fp;
33938 *total = rs6000_cost->dmul;
33943 if (FLOAT_MODE_P (mode))
33945 *total = mode == DFmode ? rs6000_cost->ddiv
33946 : rs6000_cost->sdiv;
33953 if (GET_CODE (XEXP (x, 1)) == CONST_INT
33954 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
33956 if (code == DIV || code == MOD)
33958 *total = COSTS_N_INSNS (2);
33961 *total = COSTS_N_INSNS (1);
33965 if (GET_MODE (XEXP (x, 1)) == DImode)
33966 *total = rs6000_cost->divdi;
33968 *total = rs6000_cost->divsi;
33970 /* Add in shift and subtract for MOD unless we have a mod instruction. */
33971 if (!TARGET_MODULO && (code == MOD || code == UMOD))
33972 *total += COSTS_N_INSNS (2);
33976 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
33980 *total = COSTS_N_INSNS (4);
33984 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
33988 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
33992 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
33995 *total = COSTS_N_INSNS (1);
33999 if (CONST_INT_P (XEXP (x, 1)))
34001 rtx left = XEXP (x, 0);
34002 rtx_code left_code = GET_CODE (left);
34004 /* rotate-and-mask: 1 insn. */
34005 if ((left_code == ROTATE
34006 || left_code == ASHIFT
34007 || left_code == LSHIFTRT)
34008 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34010 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34011 if (!CONST_INT_P (XEXP (left, 1)))
34012 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34013 *total += COSTS_N_INSNS (1);
34017 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34018 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34019 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34020 || (val & 0xffff) == val
34021 || (val & 0xffff0000) == val
34022 || ((val & 0xffff) == 0 && mode == SImode))
34024 *total = rtx_cost (left, mode, AND, 0, speed);
34025 *total += COSTS_N_INSNS (1);
34030 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34032 *total = rtx_cost (left, mode, AND, 0, speed);
34033 *total += COSTS_N_INSNS (2);
34038 *total = COSTS_N_INSNS (1);
34043 *total = COSTS_N_INSNS (1);
34049 *total = COSTS_N_INSNS (1);
34053 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34054 the sign extend and shift separately within the insn. */
34055 if (TARGET_EXTSWSLI && mode == DImode
34056 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34057 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34068 /* Handle mul_highpart. */
34069 if (outer_code == TRUNCATE
34070 && GET_CODE (XEXP (x, 0)) == MULT)
34072 if (mode == DImode)
34073 *total = rs6000_cost->muldi;
34075 *total = rs6000_cost->mulsi;
34078 else if (outer_code == AND)
34081 *total = COSTS_N_INSNS (1);
34086 if (GET_CODE (XEXP (x, 0)) == MEM)
34089 *total = COSTS_N_INSNS (1);
34095 if (!FLOAT_MODE_P (mode))
34097 *total = COSTS_N_INSNS (1);
34103 case UNSIGNED_FLOAT:
34106 case FLOAT_TRUNCATE:
34107 *total = rs6000_cost->fp;
34111 if (mode == DFmode)
34112 *total = rs6000_cost->sfdf_convert;
34114 *total = rs6000_cost->fp;
34118 switch (XINT (x, 1))
34121 *total = rs6000_cost->fp;
34133 *total = COSTS_N_INSNS (1);
34136 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34138 *total = rs6000_cost->fp;
34147 /* Carry bit requires mode == Pmode.
34148 NEG or PLUS already counted so only add one. */
34150 && (outer_code == NEG || outer_code == PLUS))
34152 *total = COSTS_N_INSNS (1);
34160 if (outer_code == SET)
34162 if (XEXP (x, 1) == const0_rtx)
34164 *total = COSTS_N_INSNS (2);
34169 *total = COSTS_N_INSNS (3);
34174 if (outer_code == COMPARE)
34188 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34191 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34192 int opno, int *total, bool speed)
34194 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34197 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34198 "opno = %d, total = %d, speed = %s, x:\n",
34199 ret ? "complete" : "scan inner",
34200 GET_MODE_NAME (mode),
34201 GET_RTX_NAME (outer_code),
34204 speed ? "true" : "false");
34212 rs6000_insn_cost (rtx_insn *insn, bool speed)
34214 if (recog_memoized (insn) < 0)
34218 return get_attr_length (insn);
34220 int cost = get_attr_cost (insn);
34224 int n = get_attr_length (insn) / 4;
34225 enum attr_type type = get_attr_type (insn);
34232 cost = COSTS_N_INSNS (n + 1);
34236 switch (get_attr_size (insn))
34239 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34242 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34245 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34248 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34251 gcc_unreachable ();
34255 switch (get_attr_size (insn))
34258 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34261 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34264 gcc_unreachable ();
34269 cost = n * rs6000_cost->fp;
34272 cost = n * rs6000_cost->dmul;
34275 cost = n * rs6000_cost->sdiv;
34278 cost = n * rs6000_cost->ddiv;
34285 cost = COSTS_N_INSNS (n + 2);
34289 cost = COSTS_N_INSNS (n);
34295 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34298 rs6000_debug_address_cost (rtx x, machine_mode mode,
34299 addr_space_t as, bool speed)
34301 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34303 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34304 ret, speed ? "true" : "false");
34311 /* A C expression returning the cost of moving data from a register of class
34312 CLASS1 to one of CLASS2. */
34315 rs6000_register_move_cost (machine_mode mode,
34316 reg_class_t from, reg_class_t to)
34320 if (TARGET_DEBUG_COST)
34323 /* Moves from/to GENERAL_REGS. */
34324 if (reg_classes_intersect_p (to, GENERAL_REGS)
34325 || reg_classes_intersect_p (from, GENERAL_REGS))
34327 reg_class_t rclass = from;
34329 if (! reg_classes_intersect_p (to, GENERAL_REGS))
34332 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34333 ret = (rs6000_memory_move_cost (mode, rclass, false)
34334 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34336 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34338 else if (rclass == CR_REGS)
34341 /* For those processors that have slow LR/CTR moves, make them more
34342 expensive than memory in order to bias spills to memory .*/
34343 else if ((rs6000_tune == PROCESSOR_POWER6
34344 || rs6000_tune == PROCESSOR_POWER7
34345 || rs6000_tune == PROCESSOR_POWER8
34346 || rs6000_tune == PROCESSOR_POWER9)
34347 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
34348 ret = 6 * hard_regno_nregs (0, mode);
34351 /* A move will cost one instruction per GPR moved. */
34352 ret = 2 * hard_regno_nregs (0, mode);
34355 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34356 else if (VECTOR_MEM_VSX_P (mode)
34357 && reg_classes_intersect_p (to, VSX_REGS)
34358 && reg_classes_intersect_p (from, VSX_REGS))
34359 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
34361 /* Moving between two similar registers is just one instruction. */
34362 else if (reg_classes_intersect_p (to, from))
34363 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
34365 /* Everything else has to go through GENERAL_REGS. */
34367 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34368 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34370 if (TARGET_DEBUG_COST)
34372 if (dbg_cost_ctrl == 1)
34374 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34375 ret, GET_MODE_NAME (mode), reg_class_names[from],
34376 reg_class_names[to]);
34383 /* A C expressions returning the cost of moving data of MODE from a register to
34387 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34388 bool in ATTRIBUTE_UNUSED)
34392 if (TARGET_DEBUG_COST)
34395 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34396 ret = 4 * hard_regno_nregs (0, mode);
34397 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34398 || reg_classes_intersect_p (rclass, VSX_REGS)))
34399 ret = 4 * hard_regno_nregs (32, mode);
34400 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34401 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34403 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34405 if (TARGET_DEBUG_COST)
34407 if (dbg_cost_ctrl == 1)
34409 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34410 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34417 /* Returns a code for a target-specific builtin that implements
34418 reciprocal of the function, or NULL_TREE if not available. */
34421 rs6000_builtin_reciprocal (tree fndecl)
34423 switch (DECL_FUNCTION_CODE (fndecl))
34425 case VSX_BUILTIN_XVSQRTDP:
34426 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34429 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34431 case VSX_BUILTIN_XVSQRTSP:
34432 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34435 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34442 /* Load up a constant. If the mode is a vector mode, splat the value across
34443 all of the vector elements. */
34446 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34450 if (mode == SFmode || mode == DFmode)
34452 rtx d = const_double_from_real_value (dconst, mode);
34453 reg = force_reg (mode, d);
34455 else if (mode == V4SFmode)
34457 rtx d = const_double_from_real_value (dconst, SFmode);
34458 rtvec v = gen_rtvec (4, d, d, d, d);
34459 reg = gen_reg_rtx (mode);
34460 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34462 else if (mode == V2DFmode)
34464 rtx d = const_double_from_real_value (dconst, DFmode);
34465 rtvec v = gen_rtvec (2, d, d);
34466 reg = gen_reg_rtx (mode);
34467 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34470 gcc_unreachable ();
34475 /* Generate an FMA instruction. */
34478 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34480 machine_mode mode = GET_MODE (target);
34483 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34484 gcc_assert (dst != NULL);
34487 emit_move_insn (target, dst);
34490 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34493 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34495 machine_mode mode = GET_MODE (dst);
34498 /* This is a tad more complicated, since the fnma_optab is for
34499 a different expression: fma(-m1, m2, a), which is the same
34500 thing except in the case of signed zeros.
34502 Fortunately we know that if FMA is supported that FNMSUB is
34503 also supported in the ISA. Just expand it directly. */
34505 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34507 r = gen_rtx_NEG (mode, a);
34508 r = gen_rtx_FMA (mode, m1, m2, r);
34509 r = gen_rtx_NEG (mode, r);
34510 emit_insn (gen_rtx_SET (dst, r));
34513 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34514 add a reg_note saying that this was a division. Support both scalar and
34515 vector divide. Assumes no trapping math and finite arguments. */
34518 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34520 machine_mode mode = GET_MODE (dst);
34521 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34524 /* Low precision estimates guarantee 5 bits of accuracy. High
34525 precision estimates guarantee 14 bits of accuracy. SFmode
34526 requires 23 bits of accuracy. DFmode requires 52 bits of
34527 accuracy. Each pass at least doubles the accuracy, leading
34528 to the following. */
34529 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34530 if (mode == DFmode || mode == V2DFmode)
34533 enum insn_code code = optab_handler (smul_optab, mode);
34534 insn_gen_fn gen_mul = GEN_FCN (code);
34536 gcc_assert (code != CODE_FOR_nothing);
34538 one = rs6000_load_constant_and_splat (mode, dconst1);
34540 /* x0 = 1./d estimate */
34541 x0 = gen_reg_rtx (mode);
34542 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34545 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34548 /* e0 = 1. - d * x0 */
34549 e0 = gen_reg_rtx (mode);
34550 rs6000_emit_nmsub (e0, d, x0, one);
34552 /* x1 = x0 + e0 * x0 */
34553 x1 = gen_reg_rtx (mode);
34554 rs6000_emit_madd (x1, e0, x0, x0);
34556 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34557 ++i, xprev = xnext, eprev = enext) {
34559 /* enext = eprev * eprev */
34560 enext = gen_reg_rtx (mode);
34561 emit_insn (gen_mul (enext, eprev, eprev));
34563 /* xnext = xprev + enext * xprev */
34564 xnext = gen_reg_rtx (mode);
34565 rs6000_emit_madd (xnext, enext, xprev, xprev);
34571 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34573 /* u = n * xprev */
34574 u = gen_reg_rtx (mode);
34575 emit_insn (gen_mul (u, n, xprev));
34577 /* v = n - (d * u) */
34578 v = gen_reg_rtx (mode);
34579 rs6000_emit_nmsub (v, d, u, n);
34581 /* dst = (v * xprev) + u */
34582 rs6000_emit_madd (dst, v, xprev, u);
34585 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34588 /* Goldschmidt's Algorithm for single/double-precision floating point
34589 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34592 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34594 machine_mode mode = GET_MODE (src);
34595 rtx e = gen_reg_rtx (mode);
34596 rtx g = gen_reg_rtx (mode);
34597 rtx h = gen_reg_rtx (mode);
34599 /* Low precision estimates guarantee 5 bits of accuracy. High
34600 precision estimates guarantee 14 bits of accuracy. SFmode
34601 requires 23 bits of accuracy. DFmode requires 52 bits of
34602 accuracy. Each pass at least doubles the accuracy, leading
34603 to the following. */
34604 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34605 if (mode == DFmode || mode == V2DFmode)
34610 enum insn_code code = optab_handler (smul_optab, mode);
34611 insn_gen_fn gen_mul = GEN_FCN (code);
34613 gcc_assert (code != CODE_FOR_nothing);
34615 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
34617 /* e = rsqrt estimate */
34618 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
34621 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34624 rtx zero = force_reg (mode, CONST0_RTX (mode));
34626 if (mode == SFmode)
34628 rtx target = emit_conditional_move (e, GT, src, zero, mode,
34631 emit_move_insn (e, target);
34635 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
34636 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
34640 /* g = sqrt estimate. */
34641 emit_insn (gen_mul (g, e, src));
34642 /* h = 1/(2*sqrt) estimate. */
34643 emit_insn (gen_mul (h, e, mhalf));
34649 rtx t = gen_reg_rtx (mode);
34650 rs6000_emit_nmsub (t, g, h, mhalf);
34651 /* Apply correction directly to 1/rsqrt estimate. */
34652 rs6000_emit_madd (dst, e, t, e);
34656 for (i = 0; i < passes; i++)
34658 rtx t1 = gen_reg_rtx (mode);
34659 rtx g1 = gen_reg_rtx (mode);
34660 rtx h1 = gen_reg_rtx (mode);
34662 rs6000_emit_nmsub (t1, g, h, mhalf);
34663 rs6000_emit_madd (g1, g, t1, g);
34664 rs6000_emit_madd (h1, h, t1, h);
34669 /* Multiply by 2 for 1/rsqrt. */
34670 emit_insn (gen_add3_insn (dst, h, h));
34675 rtx t = gen_reg_rtx (mode);
34676 rs6000_emit_nmsub (t, g, h, mhalf);
34677 rs6000_emit_madd (dst, g, t, g);
34683 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
34684 (Power7) targets. DST is the target, and SRC is the argument operand. */
34687 rs6000_emit_popcount (rtx dst, rtx src)
34689 machine_mode mode = GET_MODE (dst);
34692 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
34693 if (TARGET_POPCNTD)
34695 if (mode == SImode)
34696 emit_insn (gen_popcntdsi2 (dst, src));
34698 emit_insn (gen_popcntddi2 (dst, src));
34702 tmp1 = gen_reg_rtx (mode);
34704 if (mode == SImode)
34706 emit_insn (gen_popcntbsi2 (tmp1, src));
34707 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
34709 tmp2 = force_reg (SImode, tmp2);
34710 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
34714 emit_insn (gen_popcntbdi2 (tmp1, src));
34715 tmp2 = expand_mult (DImode, tmp1,
34716 GEN_INT ((HOST_WIDE_INT)
34717 0x01010101 << 32 | 0x01010101),
34719 tmp2 = force_reg (DImode, tmp2);
34720 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
34725 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
34726 target, and SRC is the argument operand. */
34729 rs6000_emit_parity (rtx dst, rtx src)
34731 machine_mode mode = GET_MODE (dst);
34734 tmp = gen_reg_rtx (mode);
34736 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
34739 if (mode == SImode)
34741 emit_insn (gen_popcntbsi2 (tmp, src));
34742 emit_insn (gen_paritysi2_cmpb (dst, tmp));
34746 emit_insn (gen_popcntbdi2 (tmp, src));
34747 emit_insn (gen_paritydi2_cmpb (dst, tmp));
34752 if (mode == SImode)
34754 /* Is mult+shift >= shift+xor+shift+xor? */
34755 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
34757 rtx tmp1, tmp2, tmp3, tmp4;
34759 tmp1 = gen_reg_rtx (SImode);
34760 emit_insn (gen_popcntbsi2 (tmp1, src));
34762 tmp2 = gen_reg_rtx (SImode);
34763 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
34764 tmp3 = gen_reg_rtx (SImode);
34765 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
34767 tmp4 = gen_reg_rtx (SImode);
34768 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
34769 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
34772 rs6000_emit_popcount (tmp, src);
34773 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
34777 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
34778 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
34780 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
34782 tmp1 = gen_reg_rtx (DImode);
34783 emit_insn (gen_popcntbdi2 (tmp1, src));
34785 tmp2 = gen_reg_rtx (DImode);
34786 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
34787 tmp3 = gen_reg_rtx (DImode);
34788 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
34790 tmp4 = gen_reg_rtx (DImode);
34791 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
34792 tmp5 = gen_reg_rtx (DImode);
34793 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
34795 tmp6 = gen_reg_rtx (DImode);
34796 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
34797 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
34800 rs6000_emit_popcount (tmp, src);
34801 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
34805 /* Expand an Altivec constant permutation for little endian mode.
34806 OP0 and OP1 are the input vectors and TARGET is the output vector.
34807 SEL specifies the constant permutation vector.
34809 There are two issues: First, the two input operands must be
34810 swapped so that together they form a double-wide array in LE
34811 order. Second, the vperm instruction has surprising behavior
34812 in LE mode: it interprets the elements of the source vectors
34813 in BE mode ("left to right") and interprets the elements of
34814 the destination vector in LE mode ("right to left"). To
34815 correct for this, we must subtract each element of the permute
34816 control vector from 31.
34818 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
34819 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
34820 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
34821 serve as the permute control vector. Then, in BE mode,
34825 places the desired result in vr9. However, in LE mode the
34826 vector contents will be
34828 vr10 = 00000003 00000002 00000001 00000000
34829 vr11 = 00000007 00000006 00000005 00000004
34831 The result of the vperm using the same permute control vector is
34833 vr9 = 05000000 07000000 01000000 03000000
34835 That is, the leftmost 4 bytes of vr10 are interpreted as the
34836 source for the rightmost 4 bytes of vr9, and so on.
34838 If we change the permute control vector to
34840 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
34848 vr9 = 00000006 00000004 00000002 00000000. */
34851 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
34852 const vec_perm_indices &sel)
34856 rtx constv, unspec;
34858 /* Unpack and adjust the constant selector. */
34859 for (i = 0; i < 16; ++i)
34861 unsigned int elt = 31 - (sel[i] & 31);
34862 perm[i] = GEN_INT (elt);
34865 /* Expand to a permute, swapping the inputs and using the
34866 adjusted selector. */
34868 op0 = force_reg (V16QImode, op0);
34870 op1 = force_reg (V16QImode, op1);
34872 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
34873 constv = force_reg (V16QImode, constv);
34874 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
34876 if (!REG_P (target))
34878 rtx tmp = gen_reg_rtx (V16QImode);
34879 emit_move_insn (tmp, unspec);
34883 emit_move_insn (target, unspec);
34886 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
34887 permute control vector. But here it's not a constant, so we must
34888 generate a vector NAND or NOR to do the adjustment. */
34891 altivec_expand_vec_perm_le (rtx operands[4])
34893 rtx notx, iorx, unspec;
34894 rtx target = operands[0];
34895 rtx op0 = operands[1];
34896 rtx op1 = operands[2];
34897 rtx sel = operands[3];
34899 rtx norreg = gen_reg_rtx (V16QImode);
34900 machine_mode mode = GET_MODE (target);
34902 /* Get everything in regs so the pattern matches. */
34904 op0 = force_reg (mode, op0);
34906 op1 = force_reg (mode, op1);
34908 sel = force_reg (V16QImode, sel);
34909 if (!REG_P (target))
34910 tmp = gen_reg_rtx (mode);
34912 if (TARGET_P9_VECTOR)
34914 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
34919 /* Invert the selector with a VNAND if available, else a VNOR.
34920 The VNAND is preferred for future fusion opportunities. */
34921 notx = gen_rtx_NOT (V16QImode, sel);
34922 iorx = (TARGET_P8_VECTOR
34923 ? gen_rtx_IOR (V16QImode, notx, notx)
34924 : gen_rtx_AND (V16QImode, notx, notx));
34925 emit_insn (gen_rtx_SET (norreg, iorx));
34927 /* Permute with operands reversed and adjusted selector. */
34928 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
34932 /* Copy into target, possibly by way of a register. */
34933 if (!REG_P (target))
34935 emit_move_insn (tmp, unspec);
34939 emit_move_insn (target, unspec);
34942 /* Expand an Altivec constant permutation. Return true if we match
34943 an efficient implementation; false to fall back to VPERM.
34945 OP0 and OP1 are the input vectors and TARGET is the output vector.
34946 SEL specifies the constant permutation vector. */
34949 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
34950 const vec_perm_indices &sel)
34952 struct altivec_perm_insn {
34953 HOST_WIDE_INT mask;
34954 enum insn_code impl;
34955 unsigned char perm[16];
34957 static const struct altivec_perm_insn patterns[] = {
34958 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
34959 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
34960 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
34961 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
34962 { OPTION_MASK_ALTIVEC,
34963 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
34964 : CODE_FOR_altivec_vmrglb_direct),
34965 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
34966 { OPTION_MASK_ALTIVEC,
34967 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
34968 : CODE_FOR_altivec_vmrglh_direct),
34969 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
34970 { OPTION_MASK_ALTIVEC,
34971 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
34972 : CODE_FOR_altivec_vmrglw_direct),
34973 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
34974 { OPTION_MASK_ALTIVEC,
34975 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
34976 : CODE_FOR_altivec_vmrghb_direct),
34977 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
34978 { OPTION_MASK_ALTIVEC,
34979 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
34980 : CODE_FOR_altivec_vmrghh_direct),
34981 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
34982 { OPTION_MASK_ALTIVEC,
34983 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
34984 : CODE_FOR_altivec_vmrghw_direct),
34985 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
34986 { OPTION_MASK_P8_VECTOR,
34987 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
34988 : CODE_FOR_p8_vmrgow_v4sf_direct),
34989 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
34990 { OPTION_MASK_P8_VECTOR,
34991 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
34992 : CODE_FOR_p8_vmrgew_v4sf_direct),
34993 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
34996 unsigned int i, j, elt, which;
34997 unsigned char perm[16];
35001 /* Unpack the constant selector. */
35002 for (i = which = 0; i < 16; ++i)
35005 which |= (elt < 16 ? 1 : 2);
35009 /* Simplify the constant selector based on operands. */
35013 gcc_unreachable ();
35017 if (!rtx_equal_p (op0, op1))
35022 for (i = 0; i < 16; ++i)
35034 /* Look for splat patterns. */
35039 for (i = 0; i < 16; ++i)
35040 if (perm[i] != elt)
35044 if (!BYTES_BIG_ENDIAN)
35046 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35052 for (i = 0; i < 16; i += 2)
35053 if (perm[i] != elt || perm[i + 1] != elt + 1)
35057 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35058 x = gen_reg_rtx (V8HImode);
35059 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35061 emit_move_insn (target, gen_lowpart (V16QImode, x));
35068 for (i = 0; i < 16; i += 4)
35070 || perm[i + 1] != elt + 1
35071 || perm[i + 2] != elt + 2
35072 || perm[i + 3] != elt + 3)
35076 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35077 x = gen_reg_rtx (V4SImode);
35078 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35080 emit_move_insn (target, gen_lowpart (V16QImode, x));
35086 /* Look for merge and pack patterns. */
35087 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35091 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35094 elt = patterns[j].perm[0];
35095 if (perm[0] == elt)
35097 else if (perm[0] == elt + 16)
35101 for (i = 1; i < 16; ++i)
35103 elt = patterns[j].perm[i];
35105 elt = (elt >= 16 ? elt - 16 : elt + 16);
35106 else if (one_vec && elt >= 16)
35108 if (perm[i] != elt)
35113 enum insn_code icode = patterns[j].impl;
35114 machine_mode omode = insn_data[icode].operand[0].mode;
35115 machine_mode imode = insn_data[icode].operand[1].mode;
35117 /* For little-endian, don't use vpkuwum and vpkuhum if the
35118 underlying vector type is not V4SI and V8HI, respectively.
35119 For example, using vpkuwum with a V8HI picks up the even
35120 halfwords (BE numbering) when the even halfwords (LE
35121 numbering) are what we need. */
35122 if (!BYTES_BIG_ENDIAN
35123 && icode == CODE_FOR_altivec_vpkuwum_direct
35124 && ((GET_CODE (op0) == REG
35125 && GET_MODE (op0) != V4SImode)
35126 || (GET_CODE (op0) == SUBREG
35127 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35129 if (!BYTES_BIG_ENDIAN
35130 && icode == CODE_FOR_altivec_vpkuhum_direct
35131 && ((GET_CODE (op0) == REG
35132 && GET_MODE (op0) != V8HImode)
35133 || (GET_CODE (op0) == SUBREG
35134 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35137 /* For little-endian, the two input operands must be swapped
35138 (or swapped back) to ensure proper right-to-left numbering
35140 if (swapped ^ !BYTES_BIG_ENDIAN)
35141 std::swap (op0, op1);
35142 if (imode != V16QImode)
35144 op0 = gen_lowpart (imode, op0);
35145 op1 = gen_lowpart (imode, op1);
35147 if (omode == V16QImode)
35150 x = gen_reg_rtx (omode);
35151 emit_insn (GEN_FCN (icode) (x, op0, op1));
35152 if (omode != V16QImode)
35153 emit_move_insn (target, gen_lowpart (V16QImode, x));
35158 if (!BYTES_BIG_ENDIAN)
35160 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35167 /* Expand a VSX Permute Doubleword constant permutation.
35168 Return true if we match an efficient implementation. */
35171 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35172 unsigned char perm0, unsigned char perm1)
35176 /* If both selectors come from the same operand, fold to single op. */
35177 if ((perm0 & 2) == (perm1 & 2))
35184 /* If both operands are equal, fold to simpler permutation. */
35185 if (rtx_equal_p (op0, op1))
35188 perm1 = (perm1 & 1) + 2;
35190 /* If the first selector comes from the second operand, swap. */
35191 else if (perm0 & 2)
35197 std::swap (op0, op1);
35199 /* If the second selector does not come from the second operand, fail. */
35200 else if ((perm1 & 2) == 0)
35204 if (target != NULL)
35206 machine_mode vmode, dmode;
35209 vmode = GET_MODE (target);
35210 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35211 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35212 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35213 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35214 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35215 emit_insn (gen_rtx_SET (target, x));
35220 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35223 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35224 rtx op1, const vec_perm_indices &sel)
35226 bool testing_p = !target;
35228 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35229 if (TARGET_ALTIVEC && testing_p)
35232 /* Check for ps_merge* or xxpermdi insns. */
35233 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35237 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35238 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35240 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35244 if (TARGET_ALTIVEC)
35246 /* Force the target-independent code to lower to V16QImode. */
35247 if (vmode != V16QImode)
35249 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35256 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35257 OP0 and OP1 are the input vectors and TARGET is the output vector.
35258 PERM specifies the constant permutation vector. */
35261 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35262 machine_mode vmode, const vec_perm_builder &perm)
35264 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35266 emit_move_insn (target, x);
35269 /* Expand an extract even operation. */
35272 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35274 machine_mode vmode = GET_MODE (target);
35275 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35276 vec_perm_builder perm (nelt, nelt, 1);
35278 for (i = 0; i < nelt; i++)
35279 perm.quick_push (i * 2);
35281 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35284 /* Expand a vector interleave operation. */
35287 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35289 machine_mode vmode = GET_MODE (target);
35290 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35291 vec_perm_builder perm (nelt, nelt, 1);
35293 high = (highp ? 0 : nelt / 2);
35294 for (i = 0; i < nelt / 2; i++)
35296 perm.quick_push (i + high);
35297 perm.quick_push (i + nelt + high);
35300 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35303 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35305 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35307 HOST_WIDE_INT hwi_scale (scale);
35308 REAL_VALUE_TYPE r_pow;
35309 rtvec v = rtvec_alloc (2);
35311 rtx scale_vec = gen_reg_rtx (V2DFmode);
35312 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35313 elt = const_double_from_real_value (r_pow, DFmode);
35314 RTVEC_ELT (v, 0) = elt;
35315 RTVEC_ELT (v, 1) = elt;
35316 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35317 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35320 /* Return an RTX representing where to find the function value of a
35321 function returning MODE. */
35323 rs6000_complex_function_value (machine_mode mode)
35325 unsigned int regno;
35327 machine_mode inner = GET_MODE_INNER (mode);
35328 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35330 if (TARGET_FLOAT128_TYPE
35332 || (mode == TCmode && TARGET_IEEEQUAD)))
35333 regno = ALTIVEC_ARG_RETURN;
35335 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35336 regno = FP_ARG_RETURN;
35340 regno = GP_ARG_RETURN;
35342 /* 32-bit is OK since it'll go in r3/r4. */
35343 if (TARGET_32BIT && inner_bytes >= 4)
35344 return gen_rtx_REG (mode, regno);
35347 if (inner_bytes >= 8)
35348 return gen_rtx_REG (mode, regno);
35350 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35352 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35353 GEN_INT (inner_bytes));
35354 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35357 /* Return an rtx describing a return value of MODE as a PARALLEL
35358 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35359 stride REG_STRIDE. */
35362 rs6000_parallel_return (machine_mode mode,
35363 int n_elts, machine_mode elt_mode,
35364 unsigned int regno, unsigned int reg_stride)
35366 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35369 for (i = 0; i < n_elts; i++)
35371 rtx r = gen_rtx_REG (elt_mode, regno);
35372 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35373 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35374 regno += reg_stride;
35380 /* Target hook for TARGET_FUNCTION_VALUE.
35382 An integer value is in r3 and a floating-point value is in fp1,
35383 unless -msoft-float. */
35386 rs6000_function_value (const_tree valtype,
35387 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35388 bool outgoing ATTRIBUTE_UNUSED)
35391 unsigned int regno;
35392 machine_mode elt_mode;
35395 /* Special handling for structs in darwin64. */
35397 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35399 CUMULATIVE_ARGS valcum;
35403 valcum.fregno = FP_ARG_MIN_REG;
35404 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35405 /* Do a trial code generation as if this were going to be passed as
35406 an argument; if any part goes in memory, we return NULL. */
35407 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35410 /* Otherwise fall through to standard ABI rules. */
35413 mode = TYPE_MODE (valtype);
35415 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35416 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35418 int first_reg, n_regs;
35420 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35422 /* _Decimal128 must use even/odd register pairs. */
35423 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35424 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35428 first_reg = ALTIVEC_ARG_RETURN;
35432 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35435 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35436 if (TARGET_32BIT && TARGET_POWERPC64)
35445 int count = GET_MODE_SIZE (mode) / 4;
35446 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35449 if ((INTEGRAL_TYPE_P (valtype)
35450 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35451 || POINTER_TYPE_P (valtype))
35452 mode = TARGET_32BIT ? SImode : DImode;
35454 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35455 /* _Decimal128 must use an even/odd register pair. */
35456 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35457 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35458 && !FLOAT128_VECTOR_P (mode))
35459 regno = FP_ARG_RETURN;
35460 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35461 && targetm.calls.split_complex_arg)
35462 return rs6000_complex_function_value (mode);
35463 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35464 return register is used in both cases, and we won't see V2DImode/V2DFmode
35465 for pure altivec, combine the two cases. */
35466 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35467 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35468 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35469 regno = ALTIVEC_ARG_RETURN;
35471 regno = GP_ARG_RETURN;
35473 return gen_rtx_REG (mode, regno);
35476 /* Define how to find the value returned by a library function
35477 assuming the value has mode MODE. */
35479 rs6000_libcall_value (machine_mode mode)
35481 unsigned int regno;
35483 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35484 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35485 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35487 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35488 /* _Decimal128 must use an even/odd register pair. */
35489 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35490 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35491 regno = FP_ARG_RETURN;
35492 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35493 return register is used in both cases, and we won't see V2DImode/V2DFmode
35494 for pure altivec, combine the two cases. */
35495 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35496 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35497 regno = ALTIVEC_ARG_RETURN;
35498 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35499 return rs6000_complex_function_value (mode);
35501 regno = GP_ARG_RETURN;
35503 return gen_rtx_REG (mode, regno);
35506 /* Compute register pressure classes. We implement the target hook to avoid
35507 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35508 lead to incorrect estimates of number of available registers and therefor
35509 increased register pressure/spill. */
35511 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35516 pressure_classes[n++] = GENERAL_REGS;
35518 pressure_classes[n++] = VSX_REGS;
35521 if (TARGET_ALTIVEC)
35522 pressure_classes[n++] = ALTIVEC_REGS;
35523 if (TARGET_HARD_FLOAT)
35524 pressure_classes[n++] = FLOAT_REGS;
35526 pressure_classes[n++] = CR_REGS;
35527 pressure_classes[n++] = SPECIAL_REGS;
35532 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35533 Frame pointer elimination is automatically handled.
35535 For the RS/6000, if frame pointer elimination is being done, we would like
35536 to convert ap into fp, not sp.
35538 We need r30 if -mminimal-toc was specified, and there are constant pool
35542 rs6000_can_eliminate (const int from, const int to)
35544 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35545 ? ! frame_pointer_needed
35546 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35547 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35548 || constant_pool_empty_p ()
35552 /* Define the offset between two registers, FROM to be eliminated and its
35553 replacement TO, at the start of a routine. */
35555 rs6000_initial_elimination_offset (int from, int to)
35557 rs6000_stack_t *info = rs6000_stack_info ();
35558 HOST_WIDE_INT offset;
35560 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35561 offset = info->push_p ? 0 : -info->total_size;
35562 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35564 offset = info->push_p ? 0 : -info->total_size;
35565 if (FRAME_GROWS_DOWNWARD)
35566 offset += info->fixed_size + info->vars_size + info->parm_size;
35568 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35569 offset = FRAME_GROWS_DOWNWARD
35570 ? info->fixed_size + info->vars_size + info->parm_size
35572 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35573 offset = info->total_size;
35574 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35575 offset = info->push_p ? info->total_size : 0;
35576 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35579 gcc_unreachable ();
35584 /* Fill in sizes of registers used by unwinder. */
35587 rs6000_init_dwarf_reg_sizes_extra (tree address)
35589 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35592 machine_mode mode = TYPE_MODE (char_type_node);
35593 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35594 rtx mem = gen_rtx_MEM (BLKmode, addr);
35595 rtx value = gen_int_mode (16, mode);
35597 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35598 The unwinder still needs to know the size of Altivec registers. */
35600 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35602 int column = DWARF_REG_TO_UNWIND_COLUMN
35603 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35604 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35606 emit_move_insn (adjust_address (mem, mode, offset), value);
35611 /* Map internal gcc register numbers to debug format register numbers.
35612 FORMAT specifies the type of debug register number to use:
35613 0 -- debug information, except for frame-related sections
35614 1 -- DWARF .debug_frame section
35615 2 -- DWARF .eh_frame section */
35618 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
35620 /* Except for the above, we use the internal number for non-DWARF
35621 debug information, and also for .eh_frame. */
35622 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
35625 /* On some platforms, we use the standard DWARF register
35626 numbering for .debug_info and .debug_frame. */
35627 #ifdef RS6000_USE_DWARF_NUMBERING
35630 if (regno == LR_REGNO)
35632 if (regno == CTR_REGNO)
35634 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
35635 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
35636 The actual code emitted saves the whole of CR, so we map CR2_REGNO
35637 to the DWARF reg for CR. */
35638 if (format == 1 && regno == CR2_REGNO)
35640 if (CR_REGNO_P (regno))
35641 return regno - CR0_REGNO + 86;
35642 if (regno == CA_REGNO)
35643 return 101; /* XER */
35644 if (ALTIVEC_REGNO_P (regno))
35645 return regno - FIRST_ALTIVEC_REGNO + 1124;
35646 if (regno == VRSAVE_REGNO)
35648 if (regno == VSCR_REGNO)
35654 /* target hook eh_return_filter_mode */
35655 static scalar_int_mode
35656 rs6000_eh_return_filter_mode (void)
35658 return TARGET_32BIT ? SImode : word_mode;
35661 /* Target hook for scalar_mode_supported_p. */
35663 rs6000_scalar_mode_supported_p (scalar_mode mode)
35665 /* -m32 does not support TImode. This is the default, from
35666 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
35667 same ABI as for -m32. But default_scalar_mode_supported_p allows
35668 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
35669 for -mpowerpc64. */
35670 if (TARGET_32BIT && mode == TImode)
35673 if (DECIMAL_FLOAT_MODE_P (mode))
35674 return default_decimal_float_supported_p ();
35675 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
35678 return default_scalar_mode_supported_p (mode);
35681 /* Target hook for vector_mode_supported_p. */
35683 rs6000_vector_mode_supported_p (machine_mode mode)
35685 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
35686 128-bit, the compiler might try to widen IEEE 128-bit to IBM
35688 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
35695 /* Target hook for floatn_mode. */
35696 static opt_scalar_float_mode
35697 rs6000_floatn_mode (int n, bool extended)
35707 if (TARGET_FLOAT128_TYPE)
35708 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35710 return opt_scalar_float_mode ();
35713 return opt_scalar_float_mode ();
35716 /* Those are the only valid _FloatNx types. */
35717 gcc_unreachable ();
35731 if (TARGET_FLOAT128_TYPE)
35732 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35734 return opt_scalar_float_mode ();
35737 return opt_scalar_float_mode ();
35743 /* Target hook for c_mode_for_suffix. */
35744 static machine_mode
35745 rs6000_c_mode_for_suffix (char suffix)
35747 if (TARGET_FLOAT128_TYPE)
35749 if (suffix == 'q' || suffix == 'Q')
35750 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35752 /* At the moment, we are not defining a suffix for IBM extended double.
35753 If/when the default for -mabi=ieeelongdouble is changed, and we want
35754 to support __ibm128 constants in legacy library code, we may need to
35755 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
35756 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
35757 __float80 constants. */
35763 /* Target hook for invalid_arg_for_unprototyped_fn. */
35764 static const char *
35765 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
35767 return (!rs6000_darwin64_abi
35769 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
35770 && (funcdecl == NULL_TREE
35771 || (TREE_CODE (funcdecl) == FUNCTION_DECL
35772 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
35773 ? N_("AltiVec argument passed to unprototyped function")
35777 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
35778 setup by using __stack_chk_fail_local hidden function instead of
35779 calling __stack_chk_fail directly. Otherwise it is better to call
35780 __stack_chk_fail directly. */
35782 static tree ATTRIBUTE_UNUSED
35783 rs6000_stack_protect_fail (void)
35785 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
35786 ? default_hidden_stack_protect_fail ()
35787 : default_external_stack_protect_fail ();
35790 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
35793 static unsigned HOST_WIDE_INT
35794 rs6000_asan_shadow_offset (void)
35796 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
35800 /* Mask options that we want to support inside of attribute((target)) and
35801 #pragma GCC target operations. Note, we do not include things like
35802 64/32-bit, endianness, hard/soft floating point, etc. that would have
35803 different calling sequences. */
35805 struct rs6000_opt_mask {
35806 const char *name; /* option name */
35807 HOST_WIDE_INT mask; /* mask to set */
35808 bool invert; /* invert sense of mask */
35809 bool valid_target; /* option is a target option */
35812 static struct rs6000_opt_mask const rs6000_opt_masks[] =
35814 { "altivec", OPTION_MASK_ALTIVEC, false, true },
35815 { "cmpb", OPTION_MASK_CMPB, false, true },
35816 { "crypto", OPTION_MASK_CRYPTO, false, true },
35817 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
35818 { "dlmzb", OPTION_MASK_DLMZB, false, true },
35819 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
35821 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
35822 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
35823 { "fprnd", OPTION_MASK_FPRND, false, true },
35824 { "hard-dfp", OPTION_MASK_DFP, false, true },
35825 { "htm", OPTION_MASK_HTM, false, true },
35826 { "isel", OPTION_MASK_ISEL, false, true },
35827 { "mfcrf", OPTION_MASK_MFCRF, false, true },
35828 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
35829 { "modulo", OPTION_MASK_MODULO, false, true },
35830 { "mulhw", OPTION_MASK_MULHW, false, true },
35831 { "multiple", OPTION_MASK_MULTIPLE, false, true },
35832 { "popcntb", OPTION_MASK_POPCNTB, false, true },
35833 { "popcntd", OPTION_MASK_POPCNTD, false, true },
35834 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
35835 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
35836 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
35837 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
35838 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
35839 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
35840 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
35841 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
35842 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
35843 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
35844 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
35845 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
35846 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
35847 { "string", 0, false, true },
35848 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
35849 { "update", OPTION_MASK_NO_UPDATE, true , true },
35850 { "vsx", OPTION_MASK_VSX, false, true },
35851 #ifdef OPTION_MASK_64BIT
35853 { "aix64", OPTION_MASK_64BIT, false, false },
35854 { "aix32", OPTION_MASK_64BIT, true, false },
35856 { "64", OPTION_MASK_64BIT, false, false },
35857 { "32", OPTION_MASK_64BIT, true, false },
35860 #ifdef OPTION_MASK_EABI
35861 { "eabi", OPTION_MASK_EABI, false, false },
35863 #ifdef OPTION_MASK_LITTLE_ENDIAN
35864 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
35865 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
35867 #ifdef OPTION_MASK_RELOCATABLE
35868 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
35870 #ifdef OPTION_MASK_STRICT_ALIGN
35871 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
35873 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
35874 { "string", 0, false, false },
35877 /* Builtin mask mapping for printing the flags. */
35878 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
35880 { "altivec", RS6000_BTM_ALTIVEC, false, false },
35881 { "vsx", RS6000_BTM_VSX, false, false },
35882 { "fre", RS6000_BTM_FRE, false, false },
35883 { "fres", RS6000_BTM_FRES, false, false },
35884 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
35885 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
35886 { "popcntd", RS6000_BTM_POPCNTD, false, false },
35887 { "cell", RS6000_BTM_CELL, false, false },
35888 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
35889 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
35890 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
35891 { "crypto", RS6000_BTM_CRYPTO, false, false },
35892 { "htm", RS6000_BTM_HTM, false, false },
35893 { "hard-dfp", RS6000_BTM_DFP, false, false },
35894 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
35895 { "long-double-128", RS6000_BTM_LDBL128, false, false },
35896 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
35897 { "float128", RS6000_BTM_FLOAT128, false, false },
35898 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
35901 /* Option variables that we want to support inside attribute((target)) and
35902 #pragma GCC target operations. */
35904 struct rs6000_opt_var {
35905 const char *name; /* option name */
35906 size_t global_offset; /* offset of the option in global_options. */
35907 size_t target_offset; /* offset of the option in target options. */
35910 static struct rs6000_opt_var const rs6000_opt_vars[] =
35913 offsetof (struct gcc_options, x_TARGET_FRIZ),
35914 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
35915 { "avoid-indexed-addresses",
35916 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
35917 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
35919 offsetof (struct gcc_options, x_rs6000_default_long_calls),
35920 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
35921 { "optimize-swaps",
35922 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
35923 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
35924 { "allow-movmisalign",
35925 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
35926 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
35928 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
35929 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
35931 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
35932 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
35933 { "align-branch-targets",
35934 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
35935 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
35937 offsetof (struct gcc_options, x_tls_markers),
35938 offsetof (struct cl_target_option, x_tls_markers), },
35940 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
35941 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
35943 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
35944 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
35945 { "speculate-indirect-jumps",
35946 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
35947 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
35950 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
35951 parsing. Return true if there were no errors. */
35954 rs6000_inner_target_options (tree args, bool attr_p)
35958 if (args == NULL_TREE)
35961 else if (TREE_CODE (args) == STRING_CST)
35963 char *p = ASTRDUP (TREE_STRING_POINTER (args));
35966 while ((q = strtok (p, ",")) != NULL)
35968 bool error_p = false;
35969 bool not_valid_p = false;
35970 const char *cpu_opt = NULL;
35973 if (strncmp (q, "cpu=", 4) == 0)
35975 int cpu_index = rs6000_cpu_name_lookup (q+4);
35976 if (cpu_index >= 0)
35977 rs6000_cpu_index = cpu_index;
35984 else if (strncmp (q, "tune=", 5) == 0)
35986 int tune_index = rs6000_cpu_name_lookup (q+5);
35987 if (tune_index >= 0)
35988 rs6000_tune_index = tune_index;
35998 bool invert = false;
36002 if (strncmp (r, "no-", 3) == 0)
36008 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36009 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36011 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36013 if (!rs6000_opt_masks[i].valid_target)
36014 not_valid_p = true;
36018 rs6000_isa_flags_explicit |= mask;
36020 /* VSX needs altivec, so -mvsx automagically sets
36021 altivec and disables -mavoid-indexed-addresses. */
36024 if (mask == OPTION_MASK_VSX)
36026 mask |= OPTION_MASK_ALTIVEC;
36027 TARGET_AVOID_XFORM = 0;
36031 if (rs6000_opt_masks[i].invert)
36035 rs6000_isa_flags &= ~mask;
36037 rs6000_isa_flags |= mask;
36042 if (error_p && !not_valid_p)
36044 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36045 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36047 size_t j = rs6000_opt_vars[i].global_offset;
36048 *((int *) ((char *)&global_options + j)) = !invert;
36050 not_valid_p = false;
36058 const char *eprefix, *esuffix;
36063 eprefix = "__attribute__((__target__(";
36068 eprefix = "#pragma GCC target ";
36073 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36075 else if (not_valid_p)
36076 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36078 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36083 else if (TREE_CODE (args) == TREE_LIST)
36087 tree value = TREE_VALUE (args);
36090 bool ret2 = rs6000_inner_target_options (value, attr_p);
36094 args = TREE_CHAIN (args);
36096 while (args != NULL_TREE);
36101 error ("attribute %<target%> argument not a string");
36108 /* Print out the target options as a list for -mdebug=target. */
36111 rs6000_debug_target_options (tree args, const char *prefix)
36113 if (args == NULL_TREE)
36114 fprintf (stderr, "%s<NULL>", prefix);
36116 else if (TREE_CODE (args) == STRING_CST)
36118 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36121 while ((q = strtok (p, ",")) != NULL)
36124 fprintf (stderr, "%s\"%s\"", prefix, q);
36129 else if (TREE_CODE (args) == TREE_LIST)
36133 tree value = TREE_VALUE (args);
36136 rs6000_debug_target_options (value, prefix);
36139 args = TREE_CHAIN (args);
36141 while (args != NULL_TREE);
36145 gcc_unreachable ();
36151 /* Hook to validate attribute((target("..."))). */
36154 rs6000_valid_attribute_p (tree fndecl,
36155 tree ARG_UNUSED (name),
36159 struct cl_target_option cur_target;
36162 tree new_target, new_optimize;
36163 tree func_optimize;
36165 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36167 if (TARGET_DEBUG_TARGET)
36169 tree tname = DECL_NAME (fndecl);
36170 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36172 fprintf (stderr, "function: %.*s\n",
36173 (int) IDENTIFIER_LENGTH (tname),
36174 IDENTIFIER_POINTER (tname));
36176 fprintf (stderr, "function: unknown\n");
36178 fprintf (stderr, "args:");
36179 rs6000_debug_target_options (args, " ");
36180 fprintf (stderr, "\n");
36183 fprintf (stderr, "flags: 0x%x\n", flags);
36185 fprintf (stderr, "--------------------\n");
36188 /* attribute((target("default"))) does nothing, beyond
36189 affecting multi-versioning. */
36190 if (TREE_VALUE (args)
36191 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36192 && TREE_CHAIN (args) == NULL_TREE
36193 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36196 old_optimize = build_optimization_node (&global_options);
36197 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36199 /* If the function changed the optimization levels as well as setting target
36200 options, start with the optimizations specified. */
36201 if (func_optimize && func_optimize != old_optimize)
36202 cl_optimization_restore (&global_options,
36203 TREE_OPTIMIZATION (func_optimize));
36205 /* The target attributes may also change some optimization flags, so update
36206 the optimization options if necessary. */
36207 cl_target_option_save (&cur_target, &global_options);
36208 rs6000_cpu_index = rs6000_tune_index = -1;
36209 ret = rs6000_inner_target_options (args, true);
36211 /* Set up any additional state. */
36214 ret = rs6000_option_override_internal (false);
36215 new_target = build_target_option_node (&global_options);
36220 new_optimize = build_optimization_node (&global_options);
36227 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36229 if (old_optimize != new_optimize)
36230 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36233 cl_target_option_restore (&global_options, &cur_target);
36235 if (old_optimize != new_optimize)
36236 cl_optimization_restore (&global_options,
36237 TREE_OPTIMIZATION (old_optimize));
36243 /* Hook to validate the current #pragma GCC target and set the state, and
36244 update the macros based on what was changed. If ARGS is NULL, then
36245 POP_TARGET is used to reset the options. */
36248 rs6000_pragma_target_parse (tree args, tree pop_target)
36250 tree prev_tree = build_target_option_node (&global_options);
36252 struct cl_target_option *prev_opt, *cur_opt;
36253 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36254 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36256 if (TARGET_DEBUG_TARGET)
36258 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36259 fprintf (stderr, "args:");
36260 rs6000_debug_target_options (args, " ");
36261 fprintf (stderr, "\n");
36265 fprintf (stderr, "pop_target:\n");
36266 debug_tree (pop_target);
36269 fprintf (stderr, "pop_target: <NULL>\n");
36271 fprintf (stderr, "--------------------\n");
36276 cur_tree = ((pop_target)
36278 : target_option_default_node);
36279 cl_target_option_restore (&global_options,
36280 TREE_TARGET_OPTION (cur_tree));
36284 rs6000_cpu_index = rs6000_tune_index = -1;
36285 if (!rs6000_inner_target_options (args, false)
36286 || !rs6000_option_override_internal (false)
36287 || (cur_tree = build_target_option_node (&global_options))
36290 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36291 fprintf (stderr, "invalid pragma\n");
36297 target_option_current_node = cur_tree;
36298 rs6000_activate_target_options (target_option_current_node);
36300 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36301 change the macros that are defined. */
36302 if (rs6000_target_modify_macros_ptr)
36304 prev_opt = TREE_TARGET_OPTION (prev_tree);
36305 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36306 prev_flags = prev_opt->x_rs6000_isa_flags;
36308 cur_opt = TREE_TARGET_OPTION (cur_tree);
36309 cur_flags = cur_opt->x_rs6000_isa_flags;
36310 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36312 diff_bumask = (prev_bumask ^ cur_bumask);
36313 diff_flags = (prev_flags ^ cur_flags);
36315 if ((diff_flags != 0) || (diff_bumask != 0))
36317 /* Delete old macros. */
36318 rs6000_target_modify_macros_ptr (false,
36319 prev_flags & diff_flags,
36320 prev_bumask & diff_bumask);
36322 /* Define new macros. */
36323 rs6000_target_modify_macros_ptr (true,
36324 cur_flags & diff_flags,
36325 cur_bumask & diff_bumask);
36333 /* Remember the last target of rs6000_set_current_function. */
36334 static GTY(()) tree rs6000_previous_fndecl;
36336 /* Restore target's globals from NEW_TREE and invalidate the
36337 rs6000_previous_fndecl cache. */
36340 rs6000_activate_target_options (tree new_tree)
36342 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36343 if (TREE_TARGET_GLOBALS (new_tree))
36344 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36345 else if (new_tree == target_option_default_node)
36346 restore_target_globals (&default_target_globals);
36348 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36349 rs6000_previous_fndecl = NULL_TREE;
36352 /* Establish appropriate back-end context for processing the function
36353 FNDECL. The argument might be NULL to indicate processing at top
36354 level, outside of any function scope. */
36356 rs6000_set_current_function (tree fndecl)
36358 if (TARGET_DEBUG_TARGET)
36360 fprintf (stderr, "\n==================== rs6000_set_current_function");
36363 fprintf (stderr, ", fndecl %s (%p)",
36364 (DECL_NAME (fndecl)
36365 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36366 : "<unknown>"), (void *)fndecl);
36368 if (rs6000_previous_fndecl)
36369 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36371 fprintf (stderr, "\n");
36374 /* Only change the context if the function changes. This hook is called
36375 several times in the course of compiling a function, and we don't want to
36376 slow things down too much or call target_reinit when it isn't safe. */
36377 if (fndecl == rs6000_previous_fndecl)
36381 if (rs6000_previous_fndecl == NULL_TREE)
36382 old_tree = target_option_current_node;
36383 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36384 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36386 old_tree = target_option_default_node;
36389 if (fndecl == NULL_TREE)
36391 if (old_tree != target_option_current_node)
36392 new_tree = target_option_current_node;
36394 new_tree = NULL_TREE;
36398 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36399 if (new_tree == NULL_TREE)
36400 new_tree = target_option_default_node;
36403 if (TARGET_DEBUG_TARGET)
36407 fprintf (stderr, "\nnew fndecl target specific options:\n");
36408 debug_tree (new_tree);
36413 fprintf (stderr, "\nold fndecl target specific options:\n");
36414 debug_tree (old_tree);
36417 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36418 fprintf (stderr, "--------------------\n");
36421 if (new_tree && old_tree != new_tree)
36422 rs6000_activate_target_options (new_tree);
36425 rs6000_previous_fndecl = fndecl;
36429 /* Save the current options */
36432 rs6000_function_specific_save (struct cl_target_option *ptr,
36433 struct gcc_options *opts)
36435 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36436 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36439 /* Restore the current options */
36442 rs6000_function_specific_restore (struct gcc_options *opts,
36443 struct cl_target_option *ptr)
36446 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36447 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36448 (void) rs6000_option_override_internal (false);
36451 /* Print the current options */
36454 rs6000_function_specific_print (FILE *file, int indent,
36455 struct cl_target_option *ptr)
36457 rs6000_print_isa_options (file, indent, "Isa options set",
36458 ptr->x_rs6000_isa_flags);
36460 rs6000_print_isa_options (file, indent, "Isa options explicit",
36461 ptr->x_rs6000_isa_flags_explicit);
36464 /* Helper function to print the current isa or misc options on a line. */
36467 rs6000_print_options_internal (FILE *file,
36469 const char *string,
36470 HOST_WIDE_INT flags,
36471 const char *prefix,
36472 const struct rs6000_opt_mask *opts,
36473 size_t num_elements)
36476 size_t start_column = 0;
36478 size_t max_column = 120;
36479 size_t prefix_len = strlen (prefix);
36480 size_t comma_len = 0;
36481 const char *comma = "";
36484 start_column += fprintf (file, "%*s", indent, "");
36488 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36492 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36494 /* Print the various mask options. */
36495 cur_column = start_column;
36496 for (i = 0; i < num_elements; i++)
36498 bool invert = opts[i].invert;
36499 const char *name = opts[i].name;
36500 const char *no_str = "";
36501 HOST_WIDE_INT mask = opts[i].mask;
36502 size_t len = comma_len + prefix_len + strlen (name);
36506 if ((flags & mask) == 0)
36509 len += sizeof ("no-") - 1;
36517 if ((flags & mask) != 0)
36520 len += sizeof ("no-") - 1;
36527 if (cur_column > max_column)
36529 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36530 cur_column = start_column + len;
36534 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36536 comma_len = sizeof (", ") - 1;
36539 fputs ("\n", file);
36542 /* Helper function to print the current isa options on a line. */
36545 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36546 HOST_WIDE_INT flags)
36548 rs6000_print_options_internal (file, indent, string, flags, "-m",
36549 &rs6000_opt_masks[0],
36550 ARRAY_SIZE (rs6000_opt_masks));
36554 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36555 HOST_WIDE_INT flags)
36557 rs6000_print_options_internal (file, indent, string, flags, "",
36558 &rs6000_builtin_mask_names[0],
36559 ARRAY_SIZE (rs6000_builtin_mask_names));
36562 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36563 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36564 -mupper-regs-df, etc.).
36566 If the user used -mno-power8-vector, we need to turn off all of the implicit
36567 ISA 2.07 and 3.0 options that relate to the vector unit.
36569 If the user used -mno-power9-vector, we need to turn off all of the implicit
36570 ISA 3.0 options that relate to the vector unit.
36572 This function does not handle explicit options such as the user specifying
36573 -mdirect-move. These are handled in rs6000_option_override_internal, and
36574 the appropriate error is given if needed.
36576 We return a mask of all of the implicit options that should not be enabled
36579 static HOST_WIDE_INT
36580 rs6000_disable_incompatible_switches (void)
36582 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
36585 static const struct {
36586 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
36587 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
36588 const char *const name; /* name of the switch. */
36590 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
36591 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
36592 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
36595 for (i = 0; i < ARRAY_SIZE (flags); i++)
36597 HOST_WIDE_INT no_flag = flags[i].no_flag;
36599 if ((rs6000_isa_flags & no_flag) == 0
36600 && (rs6000_isa_flags_explicit & no_flag) != 0)
36602 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
36603 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
36609 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
36610 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
36612 set_flags &= ~rs6000_opt_masks[j].mask;
36613 error ("%<-mno-%s%> turns off %<-m%s%>",
36615 rs6000_opt_masks[j].name);
36618 gcc_assert (!set_flags);
36621 rs6000_isa_flags &= ~dep_flags;
36622 ignore_masks |= no_flag | dep_flags;
36626 return ignore_masks;
36630 /* Helper function for printing the function name when debugging. */
36632 static const char *
36633 get_decl_name (tree fn)
36640 name = DECL_NAME (fn);
36642 return "<no-name>";
36644 return IDENTIFIER_POINTER (name);
36647 /* Return the clone id of the target we are compiling code for in a target
36648 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
36649 the priority list for the target clones (ordered from lowest to
36653 rs6000_clone_priority (tree fndecl)
36655 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36656 HOST_WIDE_INT isa_masks;
36657 int ret = CLONE_DEFAULT;
36658 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
36659 const char *attrs_str = NULL;
36661 attrs = TREE_VALUE (TREE_VALUE (attrs));
36662 attrs_str = TREE_STRING_POINTER (attrs);
36664 /* Return priority zero for default function. Return the ISA needed for the
36665 function if it is not the default. */
36666 if (strcmp (attrs_str, "default") != 0)
36668 if (fn_opts == NULL_TREE)
36669 fn_opts = target_option_default_node;
36671 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
36672 isa_masks = rs6000_isa_flags;
36674 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
36676 for (ret = CLONE_MAX - 1; ret != 0; ret--)
36677 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
36681 if (TARGET_DEBUG_TARGET)
36682 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
36683 get_decl_name (fndecl), ret);
36688 /* This compares the priority of target features in function DECL1 and DECL2.
36689 It returns positive value if DECL1 is higher priority, negative value if
36690 DECL2 is higher priority and 0 if they are the same. Note, priorities are
36691 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
36694 rs6000_compare_version_priority (tree decl1, tree decl2)
36696 int priority1 = rs6000_clone_priority (decl1);
36697 int priority2 = rs6000_clone_priority (decl2);
36698 int ret = priority1 - priority2;
36700 if (TARGET_DEBUG_TARGET)
36701 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
36702 get_decl_name (decl1), get_decl_name (decl2), ret);
36707 /* Make a dispatcher declaration for the multi-versioned function DECL.
36708 Calls to DECL function will be replaced with calls to the dispatcher
36709 by the front-end. Returns the decl of the dispatcher function. */
36712 rs6000_get_function_versions_dispatcher (void *decl)
36714 tree fn = (tree) decl;
36715 struct cgraph_node *node = NULL;
36716 struct cgraph_node *default_node = NULL;
36717 struct cgraph_function_version_info *node_v = NULL;
36718 struct cgraph_function_version_info *first_v = NULL;
36720 tree dispatch_decl = NULL;
36722 struct cgraph_function_version_info *default_version_info = NULL;
36723 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
36725 if (TARGET_DEBUG_TARGET)
36726 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
36727 get_decl_name (fn));
36729 node = cgraph_node::get (fn);
36730 gcc_assert (node != NULL);
36732 node_v = node->function_version ();
36733 gcc_assert (node_v != NULL);
36735 if (node_v->dispatcher_resolver != NULL)
36736 return node_v->dispatcher_resolver;
36738 /* Find the default version and make it the first node. */
36740 /* Go to the beginning of the chain. */
36741 while (first_v->prev != NULL)
36742 first_v = first_v->prev;
36744 default_version_info = first_v;
36745 while (default_version_info != NULL)
36747 const tree decl2 = default_version_info->this_node->decl;
36748 if (is_function_default_version (decl2))
36750 default_version_info = default_version_info->next;
36753 /* If there is no default node, just return NULL. */
36754 if (default_version_info == NULL)
36757 /* Make default info the first node. */
36758 if (first_v != default_version_info)
36760 default_version_info->prev->next = default_version_info->next;
36761 if (default_version_info->next)
36762 default_version_info->next->prev = default_version_info->prev;
36763 first_v->prev = default_version_info;
36764 default_version_info->next = first_v;
36765 default_version_info->prev = NULL;
36768 default_node = default_version_info->this_node;
36770 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
36771 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36772 "target_clones attribute needs GLIBC (2.23 and newer) that "
36773 "exports hardware capability bits");
36776 if (targetm.has_ifunc_p ())
36778 struct cgraph_function_version_info *it_v = NULL;
36779 struct cgraph_node *dispatcher_node = NULL;
36780 struct cgraph_function_version_info *dispatcher_version_info = NULL;
36782 /* Right now, the dispatching is done via ifunc. */
36783 dispatch_decl = make_dispatcher_decl (default_node->decl);
36785 dispatcher_node = cgraph_node::get_create (dispatch_decl);
36786 gcc_assert (dispatcher_node != NULL);
36787 dispatcher_node->dispatcher_function = 1;
36788 dispatcher_version_info
36789 = dispatcher_node->insert_new_function_version ();
36790 dispatcher_version_info->next = default_version_info;
36791 dispatcher_node->definition = 1;
36793 /* Set the dispatcher for all the versions. */
36794 it_v = default_version_info;
36795 while (it_v != NULL)
36797 it_v->dispatcher_resolver = dispatch_decl;
36803 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36804 "multiversioning needs ifunc which is not supported "
36809 return dispatch_decl;
36812 /* Make the resolver function decl to dispatch the versions of a multi-
36813 versioned function, DEFAULT_DECL. Create an empty basic block in the
36814 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
36818 make_resolver_func (const tree default_decl,
36819 const tree dispatch_decl,
36820 basic_block *empty_bb)
36822 /* Make the resolver function static. The resolver function returns
36824 tree decl_name = clone_function_name (default_decl, "resolver");
36825 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
36826 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
36827 tree decl = build_fn_decl (resolver_name, type);
36828 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
36830 DECL_NAME (decl) = decl_name;
36831 TREE_USED (decl) = 1;
36832 DECL_ARTIFICIAL (decl) = 1;
36833 DECL_IGNORED_P (decl) = 0;
36834 TREE_PUBLIC (decl) = 0;
36835 DECL_UNINLINABLE (decl) = 1;
36837 /* Resolver is not external, body is generated. */
36838 DECL_EXTERNAL (decl) = 0;
36839 DECL_EXTERNAL (dispatch_decl) = 0;
36841 DECL_CONTEXT (decl) = NULL_TREE;
36842 DECL_INITIAL (decl) = make_node (BLOCK);
36843 DECL_STATIC_CONSTRUCTOR (decl) = 0;
36845 /* Build result decl and add to function_decl. */
36846 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
36847 DECL_ARTIFICIAL (t) = 1;
36848 DECL_IGNORED_P (t) = 1;
36849 DECL_RESULT (decl) = t;
36851 gimplify_function_tree (decl);
36852 push_cfun (DECL_STRUCT_FUNCTION (decl));
36853 *empty_bb = init_lowered_empty_function (decl, false,
36854 profile_count::uninitialized ());
36856 cgraph_node::add_new_function (decl, true);
36857 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
36861 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
36862 DECL_ATTRIBUTES (dispatch_decl)
36863 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
36865 cgraph_node::create_same_body_alias (dispatch_decl, decl);
36870 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
36871 return a pointer to VERSION_DECL if we are running on a machine that
36872 supports the index CLONE_ISA hardware architecture bits. This function will
36873 be called during version dispatch to decide which function version to
36874 execute. It returns the basic block at the end, to which more conditions
36878 add_condition_to_bb (tree function_decl, tree version_decl,
36879 int clone_isa, basic_block new_bb)
36881 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
36883 gcc_assert (new_bb != NULL);
36884 gimple_seq gseq = bb_seq (new_bb);
36887 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
36888 build_fold_addr_expr (version_decl));
36889 tree result_var = create_tmp_var (ptr_type_node);
36890 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
36891 gimple *return_stmt = gimple_build_return (result_var);
36893 if (clone_isa == CLONE_DEFAULT)
36895 gimple_seq_add_stmt (&gseq, convert_stmt);
36896 gimple_seq_add_stmt (&gseq, return_stmt);
36897 set_bb_seq (new_bb, gseq);
36898 gimple_set_bb (convert_stmt, new_bb);
36899 gimple_set_bb (return_stmt, new_bb);
36904 tree bool_zero = build_int_cst (bool_int_type_node, 0);
36905 tree cond_var = create_tmp_var (bool_int_type_node);
36906 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
36907 const char *arg_str = rs6000_clone_map[clone_isa].name;
36908 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
36909 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
36910 gimple_call_set_lhs (call_cond_stmt, cond_var);
36912 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
36913 gimple_set_bb (call_cond_stmt, new_bb);
36914 gimple_seq_add_stmt (&gseq, call_cond_stmt);
36916 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
36917 NULL_TREE, NULL_TREE);
36918 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
36919 gimple_set_bb (if_else_stmt, new_bb);
36920 gimple_seq_add_stmt (&gseq, if_else_stmt);
36922 gimple_seq_add_stmt (&gseq, convert_stmt);
36923 gimple_seq_add_stmt (&gseq, return_stmt);
36924 set_bb_seq (new_bb, gseq);
36926 basic_block bb1 = new_bb;
36927 edge e12 = split_block (bb1, if_else_stmt);
36928 basic_block bb2 = e12->dest;
36929 e12->flags &= ~EDGE_FALLTHRU;
36930 e12->flags |= EDGE_TRUE_VALUE;
36932 edge e23 = split_block (bb2, return_stmt);
36933 gimple_set_bb (convert_stmt, bb2);
36934 gimple_set_bb (return_stmt, bb2);
36936 basic_block bb3 = e23->dest;
36937 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
36940 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
36946 /* This function generates the dispatch function for multi-versioned functions.
36947 DISPATCH_DECL is the function which will contain the dispatch logic.
36948 FNDECLS are the function choices for dispatch, and is a tree chain.
36949 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
36950 code is generated. */
36953 dispatch_function_versions (tree dispatch_decl,
36955 basic_block *empty_bb)
36959 vec<tree> *fndecls;
36960 tree clones[CLONE_MAX];
36962 if (TARGET_DEBUG_TARGET)
36963 fputs ("dispatch_function_versions, top\n", stderr);
36965 gcc_assert (dispatch_decl != NULL
36966 && fndecls_p != NULL
36967 && empty_bb != NULL);
36969 /* fndecls_p is actually a vector. */
36970 fndecls = static_cast<vec<tree> *> (fndecls_p);
36972 /* At least one more version other than the default. */
36973 gcc_assert (fndecls->length () >= 2);
36975 /* The first version in the vector is the default decl. */
36976 memset ((void *) clones, '\0', sizeof (clones));
36977 clones[CLONE_DEFAULT] = (*fndecls)[0];
36979 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
36980 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
36981 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
36982 recent glibc. If we ever need to call __builtin_cpu_init, we would need
36983 to insert the code here to do the call. */
36985 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
36987 int priority = rs6000_clone_priority (ele);
36988 if (!clones[priority])
36989 clones[priority] = ele;
36992 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
36995 if (TARGET_DEBUG_TARGET)
36996 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
36997 ix, get_decl_name (clones[ix]));
36999 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37006 /* Generate the dispatching code body to dispatch multi-versioned function
37007 DECL. The target hook is called to process the "target" attributes and
37008 provide the code to dispatch the right function at run-time. NODE points
37009 to the dispatcher decl whose body will be created. */
37012 rs6000_generate_version_dispatcher_body (void *node_p)
37015 basic_block empty_bb;
37016 struct cgraph_node *node = (cgraph_node *) node_p;
37017 struct cgraph_function_version_info *ninfo = node->function_version ();
37019 if (ninfo->dispatcher_resolver)
37020 return ninfo->dispatcher_resolver;
37022 /* node is going to be an alias, so remove the finalized bit. */
37023 node->definition = false;
37025 /* The first version in the chain corresponds to the default version. */
37026 ninfo->dispatcher_resolver = resolver
37027 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37029 if (TARGET_DEBUG_TARGET)
37030 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37031 get_decl_name (resolver));
37033 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37034 auto_vec<tree, 2> fn_ver_vec;
37036 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37038 vinfo = vinfo->next)
37040 struct cgraph_node *version = vinfo->this_node;
37041 /* Check for virtual functions here again, as by this time it should
37042 have been determined if this function needs a vtable index or
37043 not. This happens for methods in derived classes that override
37044 virtual methods in base classes but are not explicitly marked as
37046 if (DECL_VINDEX (version->decl))
37047 sorry ("Virtual function multiversioning not supported");
37049 fn_ver_vec.safe_push (version->decl);
37052 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37053 cgraph_edge::rebuild_edges ();
37059 /* Hook to determine if one function can safely inline another. */
37062 rs6000_can_inline_p (tree caller, tree callee)
37065 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37066 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37068 /* If callee has no option attributes, then it is ok to inline. */
37072 /* If caller has no option attributes, but callee does then it is not ok to
37074 else if (!caller_tree)
37079 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37080 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37082 /* Callee's options should a subset of the caller's, i.e. a vsx function
37083 can inline an altivec function but a non-vsx function can't inline a
37085 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37086 == callee_opts->x_rs6000_isa_flags)
37090 if (TARGET_DEBUG_TARGET)
37091 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37092 get_decl_name (caller), get_decl_name (callee),
37093 (ret ? "can" : "cannot"));
37098 /* Allocate a stack temp and fixup the address so it meets the particular
37099 memory requirements (either offetable or REG+REG addressing). */
37102 rs6000_allocate_stack_temp (machine_mode mode,
37103 bool offsettable_p,
37106 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37107 rtx addr = XEXP (stack, 0);
37108 int strict_p = reload_completed;
37110 if (!legitimate_indirect_address_p (addr, strict_p))
37113 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37114 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37116 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37117 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37123 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37124 to such a form to deal with memory reference instructions like STFIWX that
37125 only take reg+reg addressing. */
37128 rs6000_address_for_fpconvert (rtx x)
37132 gcc_assert (MEM_P (x));
37133 addr = XEXP (x, 0);
37134 if (can_create_pseudo_p ()
37135 && ! legitimate_indirect_address_p (addr, reload_completed)
37136 && ! legitimate_indexed_address_p (addr, reload_completed))
37138 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37140 rtx reg = XEXP (addr, 0);
37141 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37142 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37143 gcc_assert (REG_P (reg));
37144 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37147 else if (GET_CODE (addr) == PRE_MODIFY)
37149 rtx reg = XEXP (addr, 0);
37150 rtx expr = XEXP (addr, 1);
37151 gcc_assert (REG_P (reg));
37152 gcc_assert (GET_CODE (expr) == PLUS);
37153 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37157 x = replace_equiv_address (x, copy_addr_to_reg (addr));
37163 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37165 On the RS/6000, all integer constants are acceptable, most won't be valid
37166 for particular insns, though. Only easy FP constants are acceptable. */
37169 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37171 if (TARGET_ELF && tls_referenced_p (x))
37174 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
37175 || GET_MODE (x) == VOIDmode
37176 || (TARGET_POWERPC64 && mode == DImode)
37177 || easy_fp_constant (x, mode)
37178 || easy_vector_constant (x, mode));
37182 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37185 chain_already_loaded (rtx_insn *last)
37187 for (; last != NULL; last = PREV_INSN (last))
37189 if (NONJUMP_INSN_P (last))
37191 rtx patt = PATTERN (last);
37193 if (GET_CODE (patt) == SET)
37195 rtx lhs = XEXP (patt, 0);
37197 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37205 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37208 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37210 const bool direct_call_p
37211 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
37212 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37213 rtx toc_load = NULL_RTX;
37214 rtx toc_restore = NULL_RTX;
37216 rtx abi_reg = NULL_RTX;
37221 /* Handle longcall attributes. */
37222 if (INTVAL (cookie) & CALL_LONG)
37223 func_desc = rs6000_longcall_ref (func_desc);
37225 /* Handle indirect calls. */
37226 if (GET_CODE (func_desc) != SYMBOL_REF
37227 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
37229 /* Save the TOC into its reserved slot before the call,
37230 and prepare to restore it after the call. */
37231 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37232 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37233 rtx stack_toc_mem = gen_frame_mem (Pmode,
37234 gen_rtx_PLUS (Pmode, stack_ptr,
37235 stack_toc_offset));
37236 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37237 gen_rtvec (1, stack_toc_offset),
37239 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37241 /* Can we optimize saving the TOC in the prologue or
37242 do we need to do it at every call? */
37243 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37244 cfun->machine->save_toc_in_prologue = true;
37247 MEM_VOLATILE_P (stack_toc_mem) = 1;
37248 emit_move_insn (stack_toc_mem, toc_reg);
37251 if (DEFAULT_ABI == ABI_ELFv2)
37253 /* A function pointer in the ELFv2 ABI is just a plain address, but
37254 the ABI requires it to be loaded into r12 before the call. */
37255 func_addr = gen_rtx_REG (Pmode, 12);
37256 emit_move_insn (func_addr, func_desc);
37257 abi_reg = func_addr;
37261 /* A function pointer under AIX is a pointer to a data area whose
37262 first word contains the actual address of the function, whose
37263 second word contains a pointer to its TOC, and whose third word
37264 contains a value to place in the static chain register (r11).
37265 Note that if we load the static chain, our "trampoline" need
37266 not have any executable code. */
37268 /* Load up address of the actual function. */
37269 func_desc = force_reg (Pmode, func_desc);
37270 func_addr = gen_reg_rtx (Pmode);
37271 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
37273 /* Prepare to load the TOC of the called function. Note that the
37274 TOC load must happen immediately before the actual call so
37275 that unwinding the TOC registers works correctly. See the
37276 comment in frob_update_context. */
37277 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37278 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37279 gen_rtx_PLUS (Pmode, func_desc,
37281 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37283 /* If we have a static chain, load it up. But, if the call was
37284 originally direct, the 3rd word has not been written since no
37285 trampoline has been built, so we ought not to load it, lest we
37286 override a static chain value. */
37288 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37289 && !chain_already_loaded (get_current_sequence ()->next->last))
37291 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37292 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37293 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37294 gen_rtx_PLUS (Pmode, func_desc,
37296 emit_move_insn (sc_reg, func_sc_mem);
37303 /* Direct calls use the TOC: for local calls, the callee will
37304 assume the TOC register is set; for non-local calls, the
37305 PLT stub needs the TOC register. */
37307 func_addr = func_desc;
37310 /* Create the call. */
37311 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
37312 if (value != NULL_RTX)
37313 call[0] = gen_rtx_SET (value, call[0]);
37317 call[n_call++] = toc_load;
37319 call[n_call++] = toc_restore;
37321 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
37323 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37324 insn = emit_call_insn (insn);
37326 /* Mention all registers defined by the ABI to hold information
37327 as uses in CALL_INSN_FUNCTION_USAGE. */
37329 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37332 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37335 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37340 gcc_assert (INTVAL (cookie) == 0);
37342 /* Create the call. */
37343 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
37344 if (value != NULL_RTX)
37345 call[0] = gen_rtx_SET (value, call[0]);
37347 call[1] = simple_return_rtx;
37349 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37350 insn = emit_call_insn (insn);
37352 /* Note use of the TOC register. */
37353 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37356 /* Return whether we need to always update the saved TOC pointer when we update
37357 the stack pointer. */
37360 rs6000_save_toc_in_prologue_p (void)
37362 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
37365 #ifdef HAVE_GAS_HIDDEN
37366 # define USE_HIDDEN_LINKONCE 1
37368 # define USE_HIDDEN_LINKONCE 0
37371 /* Fills in the label name that should be used for a 476 link stack thunk. */
37374 get_ppc476_thunk_name (char name[32])
37376 gcc_assert (TARGET_LINK_STACK);
37378 if (USE_HIDDEN_LINKONCE)
37379 sprintf (name, "__ppc476.get_thunk");
37381 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
37384 /* This function emits the simple thunk routine that is used to preserve
37385 the link stack on the 476 cpu. */
37387 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
37389 rs6000_code_end (void)
37394 if (!TARGET_LINK_STACK)
37397 get_ppc476_thunk_name (name);
37399 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
37400 build_function_type_list (void_type_node, NULL_TREE));
37401 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
37402 NULL_TREE, void_type_node);
37403 TREE_PUBLIC (decl) = 1;
37404 TREE_STATIC (decl) = 1;
37407 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
37409 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
37410 targetm.asm_out.unique_section (decl, 0);
37411 switch_to_section (get_named_section (decl, NULL, 0));
37412 DECL_WEAK (decl) = 1;
37413 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
37414 targetm.asm_out.globalize_label (asm_out_file, name);
37415 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
37416 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
37421 switch_to_section (text_section);
37422 ASM_OUTPUT_LABEL (asm_out_file, name);
37425 DECL_INITIAL (decl) = make_node (BLOCK);
37426 current_function_decl = decl;
37427 allocate_struct_function (decl, false);
37428 init_function_start (decl);
37429 first_function_block_is_cold = false;
37430 /* Make sure unwind info is emitted for the thunk if needed. */
37431 final_start_function (emit_barrier (), asm_out_file, 1);
37433 fputs ("\tblr\n", asm_out_file);
37435 final_end_function ();
37436 init_insn_lengths ();
37437 free_after_compilation (cfun);
37439 current_function_decl = NULL;
37442 /* Add r30 to hard reg set if the prologue sets it up and it is not
37443 pic_offset_table_rtx. */
37446 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
37448 if (!TARGET_SINGLE_PIC_BASE
37450 && TARGET_MINIMAL_TOC
37451 && !constant_pool_empty_p ())
37452 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
37453 if (cfun->machine->split_stack_argp_used)
37454 add_to_hard_reg_set (&set->set, Pmode, 12);
37456 /* Make sure the hard reg set doesn't include r2, which was possibly added
37457 via PIC_OFFSET_TABLE_REGNUM. */
37459 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
37463 /* Helper function for rs6000_split_logical to emit a logical instruction after
37464 spliting the operation to single GPR registers.
37466 DEST is the destination register.
37467 OP1 and OP2 are the input source registers.
37468 CODE is the base operation (AND, IOR, XOR, NOT).
37469 MODE is the machine mode.
37470 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37471 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37472 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37475 rs6000_split_logical_inner (rtx dest,
37478 enum rtx_code code,
37480 bool complement_final_p,
37481 bool complement_op1_p,
37482 bool complement_op2_p)
37486 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
37487 if (op2 && GET_CODE (op2) == CONST_INT
37488 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
37489 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37491 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
37492 HOST_WIDE_INT value = INTVAL (op2) & mask;
37494 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
37499 emit_insn (gen_rtx_SET (dest, const0_rtx));
37503 else if (value == mask)
37505 if (!rtx_equal_p (dest, op1))
37506 emit_insn (gen_rtx_SET (dest, op1));
37511 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
37512 into separate ORI/ORIS or XORI/XORIS instrucitons. */
37513 else if (code == IOR || code == XOR)
37517 if (!rtx_equal_p (dest, op1))
37518 emit_insn (gen_rtx_SET (dest, op1));
37524 if (code == AND && mode == SImode
37525 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37527 emit_insn (gen_andsi3 (dest, op1, op2));
37531 if (complement_op1_p)
37532 op1 = gen_rtx_NOT (mode, op1);
37534 if (complement_op2_p)
37535 op2 = gen_rtx_NOT (mode, op2);
37537 /* For canonical RTL, if only one arm is inverted it is the first. */
37538 if (!complement_op1_p && complement_op2_p)
37539 std::swap (op1, op2);
37541 bool_rtx = ((code == NOT)
37542 ? gen_rtx_NOT (mode, op1)
37543 : gen_rtx_fmt_ee (code, mode, op1, op2));
37545 if (complement_final_p)
37546 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
37548 emit_insn (gen_rtx_SET (dest, bool_rtx));
37551 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
37552 operations are split immediately during RTL generation to allow for more
37553 optimizations of the AND/IOR/XOR.
37555 OPERANDS is an array containing the destination and two input operands.
37556 CODE is the base operation (AND, IOR, XOR, NOT).
37557 MODE is the machine mode.
37558 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37559 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37560 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
37561 CLOBBER_REG is either NULL or a scratch register of type CC to allow
37562 formation of the AND instructions. */
37565 rs6000_split_logical_di (rtx operands[3],
37566 enum rtx_code code,
37567 bool complement_final_p,
37568 bool complement_op1_p,
37569 bool complement_op2_p)
37571 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
37572 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
37573 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
37574 enum hi_lo { hi = 0, lo = 1 };
37575 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
37578 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
37579 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
37580 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
37581 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
37584 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
37587 if (GET_CODE (operands[2]) != CONST_INT)
37589 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
37590 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
37594 HOST_WIDE_INT value = INTVAL (operands[2]);
37595 HOST_WIDE_INT value_hi_lo[2];
37597 gcc_assert (!complement_final_p);
37598 gcc_assert (!complement_op1_p);
37599 gcc_assert (!complement_op2_p);
37601 value_hi_lo[hi] = value >> 32;
37602 value_hi_lo[lo] = value & lower_32bits;
37604 for (i = 0; i < 2; i++)
37606 HOST_WIDE_INT sub_value = value_hi_lo[i];
37608 if (sub_value & sign_bit)
37609 sub_value |= upper_32bits;
37611 op2_hi_lo[i] = GEN_INT (sub_value);
37613 /* If this is an AND instruction, check to see if we need to load
37614 the value in a register. */
37615 if (code == AND && sub_value != -1 && sub_value != 0
37616 && !and_operand (op2_hi_lo[i], SImode))
37617 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
37622 for (i = 0; i < 2; i++)
37624 /* Split large IOR/XOR operations. */
37625 if ((code == IOR || code == XOR)
37626 && GET_CODE (op2_hi_lo[i]) == CONST_INT
37627 && !complement_final_p
37628 && !complement_op1_p
37629 && !complement_op2_p
37630 && !logical_const_operand (op2_hi_lo[i], SImode))
37632 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
37633 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
37634 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
37635 rtx tmp = gen_reg_rtx (SImode);
37637 /* Make sure the constant is sign extended. */
37638 if ((hi_16bits & sign_bit) != 0)
37639 hi_16bits |= upper_32bits;
37641 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
37642 code, SImode, false, false, false);
37644 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
37645 code, SImode, false, false, false);
37648 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
37649 code, SImode, complement_final_p,
37650 complement_op1_p, complement_op2_p);
37656 /* Split the insns that make up boolean operations operating on multiple GPR
37657 registers. The boolean MD patterns ensure that the inputs either are
37658 exactly the same as the output registers, or there is no overlap.
37660 OPERANDS is an array containing the destination and two input operands.
37661 CODE is the base operation (AND, IOR, XOR, NOT).
37662 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37663 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37664 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37667 rs6000_split_logical (rtx operands[3],
37668 enum rtx_code code,
37669 bool complement_final_p,
37670 bool complement_op1_p,
37671 bool complement_op2_p)
37673 machine_mode mode = GET_MODE (operands[0]);
37674 machine_mode sub_mode;
37676 int sub_size, regno0, regno1, nregs, i;
37678 /* If this is DImode, use the specialized version that can run before
37679 register allocation. */
37680 if (mode == DImode && !TARGET_POWERPC64)
37682 rs6000_split_logical_di (operands, code, complement_final_p,
37683 complement_op1_p, complement_op2_p);
37689 op2 = (code == NOT) ? NULL_RTX : operands[2];
37690 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
37691 sub_size = GET_MODE_SIZE (sub_mode);
37692 regno0 = REGNO (op0);
37693 regno1 = REGNO (op1);
37695 gcc_assert (reload_completed);
37696 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37697 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37699 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
37700 gcc_assert (nregs > 1);
37702 if (op2 && REG_P (op2))
37703 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
37705 for (i = 0; i < nregs; i++)
37707 int offset = i * sub_size;
37708 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
37709 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
37710 rtx sub_op2 = ((code == NOT)
37712 : simplify_subreg (sub_mode, op2, mode, offset));
37714 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
37715 complement_final_p, complement_op1_p,
37723 /* Return true if the peephole2 can combine a load involving a combination of
37724 an addis instruction and a load with an offset that can be fused together on
37728 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
37729 rtx addis_value, /* addis value. */
37730 rtx target, /* target register that is loaded. */
37731 rtx mem) /* bottom part of the memory addr. */
37736 /* Validate arguments. */
37737 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
37740 if (!base_reg_operand (target, GET_MODE (target)))
37743 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
37746 /* Allow sign/zero extension. */
37747 if (GET_CODE (mem) == ZERO_EXTEND
37748 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
37749 mem = XEXP (mem, 0);
37754 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
37757 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
37758 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
37761 /* Validate that the register used to load the high value is either the
37762 register being loaded, or we can safely replace its use.
37764 This function is only called from the peephole2 pass and we assume that
37765 there are 2 instructions in the peephole (addis and load), so we want to
37766 check if the target register was not used in the memory address and the
37767 register to hold the addis result is dead after the peephole. */
37768 if (REGNO (addis_reg) != REGNO (target))
37770 if (reg_mentioned_p (target, mem))
37773 if (!peep2_reg_dead_p (2, addis_reg))
37776 /* If the target register being loaded is the stack pointer, we must
37777 avoid loading any other value into it, even temporarily. */
37778 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
37782 base_reg = XEXP (addr, 0);
37783 return REGNO (addis_reg) == REGNO (base_reg);
37786 /* During the peephole2 pass, adjust and expand the insns for a load fusion
37787 sequence. We adjust the addis register to use the target register. If the
37788 load sign extends, we adjust the code to do the zero extending load, and an
37789 explicit sign extension later since the fusion only covers zero extending
37793 operands[0] register set with addis (to be replaced with target)
37794 operands[1] value set via addis
37795 operands[2] target register being loaded
37796 operands[3] D-form memory reference using operands[0]. */
37799 expand_fusion_gpr_load (rtx *operands)
37801 rtx addis_value = operands[1];
37802 rtx target = operands[2];
37803 rtx orig_mem = operands[3];
37804 rtx new_addr, new_mem, orig_addr, offset;
37805 enum rtx_code plus_or_lo_sum;
37806 machine_mode target_mode = GET_MODE (target);
37807 machine_mode extend_mode = target_mode;
37808 machine_mode ptr_mode = Pmode;
37809 enum rtx_code extend = UNKNOWN;
37811 if (GET_CODE (orig_mem) == ZERO_EXTEND
37812 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
37814 extend = GET_CODE (orig_mem);
37815 orig_mem = XEXP (orig_mem, 0);
37816 target_mode = GET_MODE (orig_mem);
37819 gcc_assert (MEM_P (orig_mem));
37821 orig_addr = XEXP (orig_mem, 0);
37822 plus_or_lo_sum = GET_CODE (orig_addr);
37823 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
37825 offset = XEXP (orig_addr, 1);
37826 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
37827 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
37829 if (extend != UNKNOWN)
37830 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
37832 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
37833 UNSPEC_FUSION_GPR);
37834 emit_insn (gen_rtx_SET (target, new_mem));
37836 if (extend == SIGN_EXTEND)
37838 int sub_off = ((BYTES_BIG_ENDIAN)
37839 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
37842 = simplify_subreg (target_mode, target, extend_mode, sub_off);
37844 emit_insn (gen_rtx_SET (target,
37845 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
37851 /* Emit the addis instruction that will be part of a fused instruction
37855 emit_fusion_addis (rtx target, rtx addis_value)
37858 const char *addis_str = NULL;
37860 /* Emit the addis instruction. */
37861 fuse_ops[0] = target;
37862 if (satisfies_constraint_L (addis_value))
37864 fuse_ops[1] = addis_value;
37865 addis_str = "lis %0,%v1";
37868 else if (GET_CODE (addis_value) == PLUS)
37870 rtx op0 = XEXP (addis_value, 0);
37871 rtx op1 = XEXP (addis_value, 1);
37873 if (REG_P (op0) && CONST_INT_P (op1)
37874 && satisfies_constraint_L (op1))
37878 addis_str = "addis %0,%1,%v2";
37882 else if (GET_CODE (addis_value) == HIGH)
37884 rtx value = XEXP (addis_value, 0);
37885 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
37887 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
37888 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
37890 addis_str = "addis %0,%2,%1@toc@ha";
37892 else if (TARGET_XCOFF)
37893 addis_str = "addis %0,%1@u(%2)";
37896 gcc_unreachable ();
37899 else if (GET_CODE (value) == PLUS)
37901 rtx op0 = XEXP (value, 0);
37902 rtx op1 = XEXP (value, 1);
37904 if (GET_CODE (op0) == UNSPEC
37905 && XINT (op0, 1) == UNSPEC_TOCREL
37906 && CONST_INT_P (op1))
37908 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
37909 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
37912 addis_str = "addis %0,%2,%1+%3@toc@ha";
37914 else if (TARGET_XCOFF)
37915 addis_str = "addis %0,%1+%3@u(%2)";
37918 gcc_unreachable ();
37922 else if (satisfies_constraint_L (value))
37924 fuse_ops[1] = value;
37925 addis_str = "lis %0,%v1";
37928 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
37930 fuse_ops[1] = value;
37931 addis_str = "lis %0,%1@ha";
37936 fatal_insn ("Could not generate addis value for fusion", addis_value);
37938 output_asm_insn (addis_str, fuse_ops);
37941 /* Emit a D-form load or store instruction that is the second instruction
37942 of a fusion sequence. */
37945 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
37946 const char *insn_str)
37949 char insn_template[80];
37951 fuse_ops[0] = load_store_reg;
37952 fuse_ops[1] = addis_reg;
37954 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
37956 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
37957 fuse_ops[2] = offset;
37958 output_asm_insn (insn_template, fuse_ops);
37961 else if (GET_CODE (offset) == UNSPEC
37962 && XINT (offset, 1) == UNSPEC_TOCREL)
37965 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
37967 else if (TARGET_XCOFF)
37968 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
37971 gcc_unreachable ();
37973 fuse_ops[2] = XVECEXP (offset, 0, 0);
37974 output_asm_insn (insn_template, fuse_ops);
37977 else if (GET_CODE (offset) == PLUS
37978 && GET_CODE (XEXP (offset, 0)) == UNSPEC
37979 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
37980 && CONST_INT_P (XEXP (offset, 1)))
37982 rtx tocrel_unspec = XEXP (offset, 0);
37984 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
37986 else if (TARGET_XCOFF)
37987 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
37990 gcc_unreachable ();
37992 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
37993 fuse_ops[3] = XEXP (offset, 1);
37994 output_asm_insn (insn_template, fuse_ops);
37997 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
37999 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38001 fuse_ops[2] = offset;
38002 output_asm_insn (insn_template, fuse_ops);
38006 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38011 /* Wrap a TOC address that can be fused to indicate that special fusion
38012 processing is needed. */
38015 fusion_wrap_memory_address (rtx old_mem)
38017 rtx old_addr = XEXP (old_mem, 0);
38018 rtvec v = gen_rtvec (1, old_addr);
38019 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38020 return replace_equiv_address_nv (old_mem, new_addr, false);
38023 /* Given an address, convert it into the addis and load offset parts. Addresses
38024 created during the peephole2 process look like:
38025 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38026 (unspec [(...)] UNSPEC_TOCREL))
38028 Addresses created via toc fusion look like:
38029 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38032 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38036 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38038 lo = XVECEXP (addr, 0, 0);
38039 hi = gen_rtx_HIGH (Pmode, lo);
38041 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38043 hi = XEXP (addr, 0);
38044 lo = XEXP (addr, 1);
38047 gcc_unreachable ();
38053 /* Return a string to fuse an addis instruction with a gpr load to the same
38054 register that we loaded up the addis instruction. The address that is used
38055 is the logical address that was formed during peephole2:
38056 (lo_sum (high) (low-part))
38058 Or the address is the TOC address that is wrapped before register allocation:
38059 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38061 The code is complicated, so we call output_asm_insn directly, and just
38065 emit_fusion_gpr_load (rtx target, rtx mem)
38070 const char *load_str = NULL;
38073 if (GET_CODE (mem) == ZERO_EXTEND)
38074 mem = XEXP (mem, 0);
38076 gcc_assert (REG_P (target) && MEM_P (mem));
38078 addr = XEXP (mem, 0);
38079 fusion_split_address (addr, &addis_value, &load_offset);
38081 /* Now emit the load instruction to the same register. */
38082 mode = GET_MODE (mem);
38100 gcc_assert (TARGET_POWERPC64);
38105 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38108 /* Emit the addis instruction. */
38109 emit_fusion_addis (target, addis_value);
38111 /* Emit the D-form load instruction. */
38112 emit_fusion_load_store (target, target, load_offset, load_str);
38118 /* Return true if the peephole2 can combine a load/store involving a
38119 combination of an addis instruction and the memory operation. This was
38120 added to the ISA 3.0 (power9) hardware. */
38123 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38124 rtx addis_value, /* addis value. */
38125 rtx dest, /* destination (memory or register). */
38126 rtx src) /* source (register or memory). */
38128 rtx addr, mem, offset;
38129 machine_mode mode = GET_MODE (src);
38131 /* Validate arguments. */
38132 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38135 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38138 /* Ignore extend operations that are part of the load. */
38139 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
38140 src = XEXP (src, 0);
38142 /* Test for memory<-register or register<-memory. */
38143 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
38151 else if (MEM_P (src))
38153 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
38162 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38163 if (GET_CODE (addr) == PLUS)
38165 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38168 return satisfies_constraint_I (XEXP (addr, 1));
38171 else if (GET_CODE (addr) == LO_SUM)
38173 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38176 offset = XEXP (addr, 1);
38177 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
38178 return small_toc_ref (offset, GET_MODE (offset));
38180 else if (TARGET_ELF && !TARGET_POWERPC64)
38181 return CONSTANT_P (offset);
38187 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38191 operands[0] register set with addis
38192 operands[1] value set via addis
38193 operands[2] target register being loaded
38194 operands[3] D-form memory reference using operands[0].
38196 This is similar to the fusion introduced with power8, except it scales to
38197 both loads/stores and does not require the result register to be the same as
38198 the base register. At the moment, we only do this if register set with addis
38202 expand_fusion_p9_load (rtx *operands)
38204 rtx tmp_reg = operands[0];
38205 rtx addis_value = operands[1];
38206 rtx target = operands[2];
38207 rtx orig_mem = operands[3];
38208 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
38209 enum rtx_code plus_or_lo_sum;
38210 machine_mode target_mode = GET_MODE (target);
38211 machine_mode extend_mode = target_mode;
38212 machine_mode ptr_mode = Pmode;
38213 enum rtx_code extend = UNKNOWN;
38215 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
38217 extend = GET_CODE (orig_mem);
38218 orig_mem = XEXP (orig_mem, 0);
38219 target_mode = GET_MODE (orig_mem);
38222 gcc_assert (MEM_P (orig_mem));
38224 orig_addr = XEXP (orig_mem, 0);
38225 plus_or_lo_sum = GET_CODE (orig_addr);
38226 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38228 offset = XEXP (orig_addr, 1);
38229 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38230 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38232 if (extend != UNKNOWN)
38233 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
38235 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38238 set = gen_rtx_SET (target, new_mem);
38239 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
38240 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
38246 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38250 operands[0] register set with addis
38251 operands[1] value set via addis
38252 operands[2] target D-form memory being stored to
38253 operands[3] register being stored
38255 This is similar to the fusion introduced with power8, except it scales to
38256 both loads/stores and does not require the result register to be the same as
38257 the base register. At the moment, we only do this if register set with addis
38261 expand_fusion_p9_store (rtx *operands)
38263 rtx tmp_reg = operands[0];
38264 rtx addis_value = operands[1];
38265 rtx orig_mem = operands[2];
38266 rtx src = operands[3];
38267 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
38268 enum rtx_code plus_or_lo_sum;
38269 machine_mode target_mode = GET_MODE (orig_mem);
38270 machine_mode ptr_mode = Pmode;
38272 gcc_assert (MEM_P (orig_mem));
38274 orig_addr = XEXP (orig_mem, 0);
38275 plus_or_lo_sum = GET_CODE (orig_addr);
38276 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38278 offset = XEXP (orig_addr, 1);
38279 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38280 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38282 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
38285 set = gen_rtx_SET (new_mem, new_src);
38286 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
38287 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
38293 /* Return a string to fuse an addis instruction with a load using extended
38294 fusion. The address that is used is the logical address that was formed
38295 during peephole2: (lo_sum (high) (low-part))
38297 The code is complicated, so we call output_asm_insn directly, and just
38301 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
38303 machine_mode mode = GET_MODE (reg);
38307 const char *load_string;
38310 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
38312 mem = XEXP (mem, 0);
38313 mode = GET_MODE (mem);
38316 if (GET_CODE (reg) == SUBREG)
38318 gcc_assert (SUBREG_BYTE (reg) == 0);
38319 reg = SUBREG_REG (reg);
38323 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
38326 if (FP_REGNO_P (r))
38328 if (mode == SFmode)
38329 load_string = "lfs";
38330 else if (mode == DFmode || mode == DImode)
38331 load_string = "lfd";
38333 gcc_unreachable ();
38335 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
38337 if (mode == SFmode)
38338 load_string = "lxssp";
38339 else if (mode == DFmode || mode == DImode)
38340 load_string = "lxsd";
38342 gcc_unreachable ();
38344 else if (INT_REGNO_P (r))
38349 load_string = "lbz";
38352 load_string = "lhz";
38356 load_string = "lwz";
38360 if (!TARGET_POWERPC64)
38361 gcc_unreachable ();
38362 load_string = "ld";
38365 gcc_unreachable ();
38369 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
38372 fatal_insn ("emit_fusion_p9_load not MEM", mem);
38374 addr = XEXP (mem, 0);
38375 fusion_split_address (addr, &hi, &lo);
38377 /* Emit the addis instruction. */
38378 emit_fusion_addis (tmp_reg, hi);
38380 /* Emit the D-form load instruction. */
38381 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
38386 /* Return a string to fuse an addis instruction with a store using extended
38387 fusion. The address that is used is the logical address that was formed
38388 during peephole2: (lo_sum (high) (low-part))
38390 The code is complicated, so we call output_asm_insn directly, and just
38394 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
38396 machine_mode mode = GET_MODE (reg);
38400 const char *store_string;
38403 if (GET_CODE (reg) == SUBREG)
38405 gcc_assert (SUBREG_BYTE (reg) == 0);
38406 reg = SUBREG_REG (reg);
38410 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
38413 if (FP_REGNO_P (r))
38415 if (mode == SFmode)
38416 store_string = "stfs";
38417 else if (mode == DFmode)
38418 store_string = "stfd";
38420 gcc_unreachable ();
38422 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
38424 if (mode == SFmode)
38425 store_string = "stxssp";
38426 else if (mode == DFmode || mode == DImode)
38427 store_string = "stxsd";
38429 gcc_unreachable ();
38431 else if (INT_REGNO_P (r))
38436 store_string = "stb";
38439 store_string = "sth";
38443 store_string = "stw";
38447 if (!TARGET_POWERPC64)
38448 gcc_unreachable ();
38449 store_string = "std";
38452 gcc_unreachable ();
38456 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
38459 fatal_insn ("emit_fusion_p9_store not MEM", mem);
38461 addr = XEXP (mem, 0);
38462 fusion_split_address (addr, &hi, &lo);
38464 /* Emit the addis instruction. */
38465 emit_fusion_addis (tmp_reg, hi);
38467 /* Emit the D-form load instruction. */
38468 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
38473 #ifdef RS6000_GLIBC_ATOMIC_FENV
38474 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38475 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38478 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38481 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38483 if (!TARGET_HARD_FLOAT)
38485 #ifdef RS6000_GLIBC_ATOMIC_FENV
38486 if (atomic_hold_decl == NULL_TREE)
38489 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38490 get_identifier ("__atomic_feholdexcept"),
38491 build_function_type_list (void_type_node,
38492 double_ptr_type_node,
38494 TREE_PUBLIC (atomic_hold_decl) = 1;
38495 DECL_EXTERNAL (atomic_hold_decl) = 1;
38498 if (atomic_clear_decl == NULL_TREE)
38501 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38502 get_identifier ("__atomic_feclearexcept"),
38503 build_function_type_list (void_type_node,
38505 TREE_PUBLIC (atomic_clear_decl) = 1;
38506 DECL_EXTERNAL (atomic_clear_decl) = 1;
38509 tree const_double = build_qualified_type (double_type_node,
38511 tree const_double_ptr = build_pointer_type (const_double);
38512 if (atomic_update_decl == NULL_TREE)
38515 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38516 get_identifier ("__atomic_feupdateenv"),
38517 build_function_type_list (void_type_node,
38520 TREE_PUBLIC (atomic_update_decl) = 1;
38521 DECL_EXTERNAL (atomic_update_decl) = 1;
38524 tree fenv_var = create_tmp_var_raw (double_type_node);
38525 TREE_ADDRESSABLE (fenv_var) = 1;
38526 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38528 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38529 *clear = build_call_expr (atomic_clear_decl, 0);
38530 *update = build_call_expr (atomic_update_decl, 1,
38531 fold_convert (const_double_ptr, fenv_addr));
38536 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38537 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38538 tree call_mffs = build_call_expr (mffs, 0);
38540 /* Generates the equivalent of feholdexcept (&fenv_var)
38542 *fenv_var = __builtin_mffs ();
38544 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38545 __builtin_mtfsf (0xff, fenv_hold); */
38547 /* Mask to clear everything except for the rounding modes and non-IEEE
38548 arithmetic flag. */
38549 const unsigned HOST_WIDE_INT hold_exception_mask =
38550 HOST_WIDE_INT_C (0xffffffff00000007);
38552 tree fenv_var = create_tmp_var_raw (double_type_node);
38554 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38556 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38557 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38558 build_int_cst (uint64_type_node,
38559 hold_exception_mask));
38561 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38564 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38565 build_int_cst (unsigned_type_node, 0xff),
38568 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38570 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38572 double fenv_clear = __builtin_mffs ();
38573 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38574 __builtin_mtfsf (0xff, fenv_clear); */
38576 /* Mask to clear everything except for the rounding modes and non-IEEE
38577 arithmetic flag. */
38578 const unsigned HOST_WIDE_INT clear_exception_mask =
38579 HOST_WIDE_INT_C (0xffffffff00000000);
38581 tree fenv_clear = create_tmp_var_raw (double_type_node);
38583 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38585 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38586 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38588 build_int_cst (uint64_type_node,
38589 clear_exception_mask));
38591 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38592 fenv_clear_llu_and);
38594 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38595 build_int_cst (unsigned_type_node, 0xff),
38598 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38600 /* Generates the equivalent of feupdateenv (&fenv_var)
38602 double old_fenv = __builtin_mffs ();
38603 double fenv_update;
38604 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38605 (*(uint64_t*)fenv_var 0x1ff80fff);
38606 __builtin_mtfsf (0xff, fenv_update); */
38608 const unsigned HOST_WIDE_INT update_exception_mask =
38609 HOST_WIDE_INT_C (0xffffffff1fffff00);
38610 const unsigned HOST_WIDE_INT new_exception_mask =
38611 HOST_WIDE_INT_C (0x1ff80fff);
38613 tree old_fenv = create_tmp_var_raw (double_type_node);
38614 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38616 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38617 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38618 build_int_cst (uint64_type_node,
38619 update_exception_mask));
38621 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38622 build_int_cst (uint64_type_node,
38623 new_exception_mask));
38625 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38626 old_llu_and, new_llu_and);
38628 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38631 tree update_mtfsf = build_call_expr (mtfsf, 2,
38632 build_int_cst (unsigned_type_node, 0xff),
38633 fenv_update_mtfsf);
38635 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
38639 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
38641 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38643 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38644 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38646 /* The destination of the vmrgew instruction layout is:
38647 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38648 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38649 vmrgew instruction will be correct. */
38650 if (BYTES_BIG_ENDIAN)
38652 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
38654 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
38659 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
38660 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
38663 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38664 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38666 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
38667 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
38669 if (BYTES_BIG_ENDIAN)
38670 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38672 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38676 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
38678 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38680 rtx_tmp0 = gen_reg_rtx (V2DImode);
38681 rtx_tmp1 = gen_reg_rtx (V2DImode);
38683 /* The destination of the vmrgew instruction layout is:
38684 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38685 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38686 vmrgew instruction will be correct. */
38687 if (BYTES_BIG_ENDIAN)
38689 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
38690 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
38694 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
38695 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
38698 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38699 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38701 if (signed_convert)
38703 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
38704 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
38708 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
38709 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
38712 if (BYTES_BIG_ENDIAN)
38713 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38715 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38719 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
38722 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38724 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38725 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38727 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
38728 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
38730 rtx_tmp2 = gen_reg_rtx (V4SImode);
38731 rtx_tmp3 = gen_reg_rtx (V4SImode);
38733 if (signed_convert)
38735 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
38736 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
38740 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
38741 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
38744 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
38747 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
38750 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
38751 optimization_type opt_type)
38756 return (opt_type == OPTIMIZE_FOR_SPEED
38757 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
38764 /* Implement TARGET_CONSTANT_ALIGNMENT. */
38766 static HOST_WIDE_INT
38767 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
38769 if (TREE_CODE (exp) == STRING_CST
38770 && (STRICT_ALIGNMENT || !optimize_size))
38771 return MAX (align, BITS_PER_WORD);
38775 /* Implement TARGET_STARTING_FRAME_OFFSET. */
38777 static HOST_WIDE_INT
38778 rs6000_starting_frame_offset (void)
38780 if (FRAME_GROWS_DOWNWARD)
38782 return RS6000_STARTING_FRAME_OFFSET;
38786 /* Create an alias for a mangled name where we have changed the mangling (in
38787 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
38788 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
38790 #if TARGET_ELF && RS6000_WEAK
38792 rs6000_globalize_decl_name (FILE * stream, tree decl)
38794 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
38796 targetm.asm_out.globalize_label (stream, name);
38798 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
38800 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
38801 const char *old_name;
38803 ieee128_mangling_gcc_8_1 = true;
38804 lang_hooks.set_decl_assembler_name (decl);
38805 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
38806 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
38807 ieee128_mangling_gcc_8_1 = false;
38809 if (strcmp (name, old_name) != 0)
38811 fprintf (stream, "\t.weak %s\n", old_name);
38812 fprintf (stream, "\t.set %s,%s\n", old_name, name);
38819 struct gcc_target targetm = TARGET_INITIALIZER;
38821 #include "gt-rs6000.h"