1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float;
228 static bool rs6000_passes_long_double;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
248 static int dbg_cost_ctrl;
250 /* Built in types. */
251 tree rs6000_builtin_types[RS6000_BTI_MAX];
252 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized, need_toc_init;
256 char toc_label_name[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more;
262 static GTY(()) section *read_only_data_section;
263 static GTY(()) section *private_data_section;
264 static GTY(()) section *tls_data_section;
265 static GTY(()) section *tls_private_data_section;
266 static GTY(()) section *read_only_private_data_section;
267 static GTY(()) section *sdata2_section;
268 static GTY(()) section *toc_section;
270 struct builtin_description
272 const HOST_WIDE_INT mask;
273 const enum insn_code icode;
274 const char *const name;
275 const enum rs6000_builtins code;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
280 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align[NUM_MACHINE_MODES];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask {
299 RECIP_SF_DIV = 0x001, /* Use divide estimate */
300 RECIP_DF_DIV = 0x002,
301 RECIP_V4SF_DIV = 0x004,
302 RECIP_V2DF_DIV = 0x008,
304 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT = 0x020,
306 RECIP_V4SF_RSQRT = 0x040,
307 RECIP_V2DF_RSQRT = 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
315 RECIP_HIGH_PRECISION = RECIP_ALL,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
322 /* -mrecip options. */
325 const char *string; /* option name */
326 unsigned int mask; /* mask bits to set */
327 } recip_options[] = {
328 { "all", RECIP_ALL },
329 { "none", RECIP_NONE },
330 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
334 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT) },
336 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
337 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9 },
347 { "power8", PPC_PLATFORM_POWER8 },
348 { "power7", PPC_PLATFORM_POWER7 },
349 { "power6x", PPC_PLATFORM_POWER6X },
350 { "power6", PPC_PLATFORM_POWER6 },
351 { "power5+", PPC_PLATFORM_POWER5_PLUS },
352 { "power5", PPC_PLATFORM_POWER5 },
353 { "ppc970", PPC_PLATFORM_PPC970 },
354 { "power4", PPC_PLATFORM_POWER4 },
355 { "ppca2", PPC_PLATFORM_PPCA2 },
356 { "ppc476", PPC_PLATFORM_PPC476 },
357 { "ppc464", PPC_PLATFORM_PPC464 },
358 { "ppc440", PPC_PLATFORM_PPC440 },
359 { "ppc405", PPC_PLATFORM_PPC405 },
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
376 { "booke", PPC_FEATURE_BOOKE, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
384 { "notb", PPC_FEATURE_NO_TB, 0 },
385 { "pa6t", PPC_FEATURE_PA6T, 0 },
386 { "power4", PPC_FEATURE_POWER4, 0 },
387 { "power5", PPC_FEATURE_POWER5, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
390 { "ppc32", PPC_FEATURE_32, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
392 { "ppc64", PPC_FEATURE_64, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
394 { "smt", PPC_FEATURE_SMT, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
412 { "darn", PPC_FEATURE2_DARN, 1 },
413 { "scv", PPC_FEATURE2_SCV, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT = 0, /* default clone. */
422 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
432 const char *name; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type {
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type {
489 RELOAD_REG_GPR, /* General purpose registers. */
490 RELOAD_REG_FPR, /* Traditional floating point regs. */
491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type {
504 const char *name; /* Register class name. */
505 int reg; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
509 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr {
531 enum insn_code reload_load; /* INSN to reload for loading. */
532 enum insn_code reload_store; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
537 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode)
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode)
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode)
562 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
598 in_set = single_set (in_insn);
601 if (MEM_P (SET_DEST (in_set)))
603 out_set = single_set (out_insn);
606 out_pat = PATTERN (out_insn);
607 if (GET_CODE (out_pat) == PARALLEL)
609 for (i = 0; i < XVECLEN (out_pat, 0); i++)
611 out_exp = XVECEXP (out_pat, 0, i);
612 if ((GET_CODE (out_exp) == CLOBBER)
613 || (GET_CODE (out_exp) == USE))
615 else if (GET_CODE (out_exp) != SET)
624 in_pat = PATTERN (in_insn);
625 if (GET_CODE (in_pat) != PARALLEL)
628 for (i = 0; i < XVECLEN (in_pat, 0); i++)
630 in_exp = XVECEXP (in_pat, 0, i);
631 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
633 else if (GET_CODE (in_exp) != SET)
636 if (MEM_P (SET_DEST (in_exp)))
638 out_set = single_set (out_insn);
641 out_pat = PATTERN (out_insn);
642 if (GET_CODE (out_pat) != PARALLEL)
644 for (j = 0; j < XVECLEN (out_pat, 0); j++)
646 out_exp = XVECEXP (out_pat, 0, j);
647 if ((GET_CODE (out_exp) == CLOBBER)
648 || (GET_CODE (out_exp) == USE))
650 else if (GET_CODE (out_exp) != SET)
657 return store_data_bypass_p (out_insn, in_insn);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs *rs6000_cost;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost = {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost = {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost = {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost = {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost = {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost = {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost = {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost = {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost = {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost = {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost = {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost = {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost = {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost = {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost = {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost = {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost = {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost = {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost = {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost = {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost = {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost = {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost = {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost = {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost = {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost = {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost = {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost = {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost = {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost = {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type {
1307 const enum insn_code icode;
1308 const HOST_WIDE_INT mask;
1309 const unsigned attr;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1332 static struct machine_function * rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1338 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1339 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1340 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1343 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1345 static bool is_microcoded_insn (rtx_insn *);
1346 static bool is_nonpipeline_insn (rtx_insn *);
1347 static bool is_cracked_insn (rtx_insn *);
1348 static bool is_load_insn (rtx, rtx *);
1349 static bool is_store_insn (rtx, rtx *);
1350 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1351 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1352 static bool insn_must_be_first_in_group (rtx_insn *);
1353 static bool insn_must_be_last_in_group (rtx_insn *);
1354 static void altivec_init_builtins (void);
1355 static tree builtin_function_type (machine_mode, machine_mode,
1356 machine_mode, machine_mode,
1357 enum rs6000_builtins, const char *name);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t *rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx, void *);
1362 int easy_vector_constant (rtx, machine_mode);
1363 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1364 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1365 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1368 static void macho_branch_islands (void);
1369 static tree get_prev_label (tree);
1371 static bool rs6000_mode_dependent_address (const_rtx);
1372 static bool rs6000_debug_mode_dependent_address (const_rtx);
1373 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1374 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1376 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1380 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1382 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1385 static bool rs6000_debug_can_change_mode_class (machine_mode,
1388 static bool rs6000_save_toc_in_prologue_p (void);
1389 static rtx rs6000_internal_arg_pointer (void);
1391 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1392 = rs6000_mode_dependent_address;
1394 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1396 = rs6000_secondary_reload_class;
1398 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1399 = rs6000_preferred_reload_class;
1401 const int INSN_NOT_AVAILABLE = -1;
1403 static void rs6000_print_isa_options (FILE *, int, const char *,
1405 static void rs6000_print_builtin_options (FILE *, int, const char *,
1407 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1409 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1410 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1411 enum rs6000_reg_type,
1413 secondary_reload_info *,
1415 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1416 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1417 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1419 /* Hash table stuff for keeping track of TOC entries. */
1421 struct GTY((for_user)) toc_hash_struct
1423 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1424 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1426 machine_mode key_mode;
1430 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1432 static hashval_t hash (toc_hash_struct *);
1433 static bool equal (toc_hash_struct *, toc_hash_struct *);
1436 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1438 /* Hash table to keep track of the argument types for builtin functions. */
1440 struct GTY((for_user)) builtin_hash_struct
1443 machine_mode mode[4]; /* return value + 3 arguments. */
1444 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1447 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1449 static hashval_t hash (builtin_hash_struct *);
1450 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1453 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1456 /* Default register names. */
1457 char rs6000_reg_names[][8] =
1460 "0", "1", "2", "3", "4", "5", "6", "7",
1461 "8", "9", "10", "11", "12", "13", "14", "15",
1462 "16", "17", "18", "19", "20", "21", "22", "23",
1463 "24", "25", "26", "27", "28", "29", "30", "31",
1465 "0", "1", "2", "3", "4", "5", "6", "7",
1466 "8", "9", "10", "11", "12", "13", "14", "15",
1467 "16", "17", "18", "19", "20", "21", "22", "23",
1468 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "lr", "ctr", "ca", "ap",
1477 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* vrsave vscr sfp */
1479 "vrsave", "vscr", "sfp",
1482 #ifdef TARGET_REGNAMES
1483 static const char alt_reg_names[][8] =
1486 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1487 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1488 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1489 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1491 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1492 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1493 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1494 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1496 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1497 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1498 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1499 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1501 "lr", "ctr", "ca", "ap",
1503 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* vrsave vscr sfp */
1505 "vrsave", "vscr", "sfp",
1509 /* Table of valid machine attributes. */
1511 static const struct attribute_spec rs6000_attribute_table[] =
1513 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1514 affects_type_identity, handler, exclude } */
1515 { "altivec", 1, 1, false, true, false, false,
1516 rs6000_handle_altivec_attribute, NULL },
1517 { "longcall", 0, 0, false, true, true, false,
1518 rs6000_handle_longcall_attribute, NULL },
1519 { "shortcall", 0, 0, false, true, true, false,
1520 rs6000_handle_longcall_attribute, NULL },
1521 { "ms_struct", 0, 0, false, false, false, false,
1522 rs6000_handle_struct_attribute, NULL },
1523 { "gcc_struct", 0, 0, false, false, false, false,
1524 rs6000_handle_struct_attribute, NULL },
1525 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1526 SUBTARGET_ATTRIBUTE_TABLE,
1528 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1531 #ifndef TARGET_PROFILE_KERNEL
1532 #define TARGET_PROFILE_KERNEL 0
1535 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1536 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1538 /* Initialize the GCC target structure. */
1539 #undef TARGET_ATTRIBUTE_TABLE
1540 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1541 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1542 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1543 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1544 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1546 #undef TARGET_ASM_ALIGNED_DI_OP
1547 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1549 /* Default unaligned ops are only provided for ELF. Find the ops needed
1550 for non-ELF systems. */
1551 #ifndef OBJECT_FORMAT_ELF
1553 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1555 #undef TARGET_ASM_UNALIGNED_HI_OP
1556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1557 #undef TARGET_ASM_UNALIGNED_SI_OP
1558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1559 #undef TARGET_ASM_UNALIGNED_DI_OP
1560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1569 #undef TARGET_ASM_ALIGNED_DI_OP
1570 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1574 /* This hook deals with fixups for relocatable code and DI-mode objects
1576 #undef TARGET_ASM_INTEGER
1577 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1579 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1580 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1581 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1584 #undef TARGET_SET_UP_BY_PROLOGUE
1585 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1587 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1588 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1589 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1590 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1591 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1592 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1593 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1594 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1595 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1597 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1600 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1601 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1603 #undef TARGET_INTERNAL_ARG_POINTER
1604 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1606 #undef TARGET_HAVE_TLS
1607 #define TARGET_HAVE_TLS HAVE_AS_TLS
1609 #undef TARGET_CANNOT_FORCE_CONST_MEM
1610 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1612 #undef TARGET_DELEGITIMIZE_ADDRESS
1613 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1615 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1616 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1618 #undef TARGET_LEGITIMATE_COMBINED_INSN
1619 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1621 #undef TARGET_ASM_FUNCTION_PROLOGUE
1622 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1623 #undef TARGET_ASM_FUNCTION_EPILOGUE
1624 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1626 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1627 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1629 #undef TARGET_LEGITIMIZE_ADDRESS
1630 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1632 #undef TARGET_SCHED_VARIABLE_ISSUE
1633 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1635 #undef TARGET_SCHED_ISSUE_RATE
1636 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1637 #undef TARGET_SCHED_ADJUST_COST
1638 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1639 #undef TARGET_SCHED_ADJUST_PRIORITY
1640 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1641 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1642 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1643 #undef TARGET_SCHED_INIT
1644 #define TARGET_SCHED_INIT rs6000_sched_init
1645 #undef TARGET_SCHED_FINISH
1646 #define TARGET_SCHED_FINISH rs6000_sched_finish
1647 #undef TARGET_SCHED_REORDER
1648 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1649 #undef TARGET_SCHED_REORDER2
1650 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1652 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1653 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1658 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1659 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1660 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1661 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1662 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1663 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1664 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1665 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1667 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1668 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1670 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1671 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1672 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1673 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1674 rs6000_builtin_support_vector_misalignment
1675 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1676 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1677 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1678 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1679 rs6000_builtin_vectorization_cost
1680 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1681 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1682 rs6000_preferred_simd_mode
1683 #undef TARGET_VECTORIZE_INIT_COST
1684 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1685 #undef TARGET_VECTORIZE_ADD_STMT_COST
1686 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1687 #undef TARGET_VECTORIZE_FINISH_COST
1688 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1689 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1690 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1692 #undef TARGET_INIT_BUILTINS
1693 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1694 #undef TARGET_BUILTIN_DECL
1695 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1697 #undef TARGET_FOLD_BUILTIN
1698 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1699 #undef TARGET_GIMPLE_FOLD_BUILTIN
1700 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1702 #undef TARGET_EXPAND_BUILTIN
1703 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1705 #undef TARGET_MANGLE_TYPE
1706 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1708 #undef TARGET_INIT_LIBFUNCS
1709 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1712 #undef TARGET_BINDS_LOCAL_P
1713 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1716 #undef TARGET_MS_BITFIELD_LAYOUT_P
1717 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1719 #undef TARGET_ASM_OUTPUT_MI_THUNK
1720 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1722 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1723 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1726 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1728 #undef TARGET_REGISTER_MOVE_COST
1729 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1730 #undef TARGET_MEMORY_MOVE_COST
1731 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1732 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1733 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
1734 rs6000_ira_change_pseudo_allocno_class
1735 #undef TARGET_CANNOT_COPY_INSN_P
1736 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1737 #undef TARGET_RTX_COSTS
1738 #define TARGET_RTX_COSTS rs6000_rtx_costs
1739 #undef TARGET_ADDRESS_COST
1740 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1741 #undef TARGET_INSN_COST
1742 #define TARGET_INSN_COST rs6000_insn_cost
1744 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1745 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1747 #undef TARGET_PROMOTE_FUNCTION_MODE
1748 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1750 #undef TARGET_RETURN_IN_MEMORY
1751 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1753 #undef TARGET_RETURN_IN_MSB
1754 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1759 /* Always strict argument naming on rs6000. */
1760 #undef TARGET_STRICT_ARGUMENT_NAMING
1761 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1762 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1763 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_SPLIT_COMPLEX_ARG
1765 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1766 #undef TARGET_MUST_PASS_IN_STACK
1767 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1768 #undef TARGET_PASS_BY_REFERENCE
1769 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1770 #undef TARGET_ARG_PARTIAL_BYTES
1771 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1772 #undef TARGET_FUNCTION_ARG_ADVANCE
1773 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1774 #undef TARGET_FUNCTION_ARG
1775 #define TARGET_FUNCTION_ARG rs6000_function_arg
1776 #undef TARGET_FUNCTION_ARG_PADDING
1777 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1778 #undef TARGET_FUNCTION_ARG_BOUNDARY
1779 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1781 #undef TARGET_BUILD_BUILTIN_VA_LIST
1782 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1784 #undef TARGET_EXPAND_BUILTIN_VA_START
1785 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1788 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1790 #undef TARGET_EH_RETURN_FILTER_MODE
1791 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1793 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1794 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1796 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1797 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1799 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1800 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1802 #undef TARGET_FLOATN_MODE
1803 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1805 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1806 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1808 #undef TARGET_MD_ASM_ADJUST
1809 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1811 #undef TARGET_OPTION_OVERRIDE
1812 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1814 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1815 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1816 rs6000_builtin_vectorized_function
1818 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1820 rs6000_builtin_md_vectorized_function
1822 #undef TARGET_STACK_PROTECT_GUARD
1823 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1826 #undef TARGET_STACK_PROTECT_FAIL
1827 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1831 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1832 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1835 /* Use a 32-bit anchor range. This leads to sequences like:
1837 addis tmp,anchor,high
1840 where tmp itself acts as an anchor, and can be shared between
1841 accesses to the same 64k page. */
1842 #undef TARGET_MIN_ANCHOR_OFFSET
1843 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1844 #undef TARGET_MAX_ANCHOR_OFFSET
1845 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1846 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1847 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1848 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1849 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1851 #undef TARGET_BUILTIN_RECIPROCAL
1852 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1854 #undef TARGET_SECONDARY_RELOAD
1855 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1856 #undef TARGET_SECONDARY_MEMORY_NEEDED
1857 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1859 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1861 #undef TARGET_LEGITIMATE_ADDRESS_P
1862 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1864 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1865 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1867 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1868 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1870 #undef TARGET_CAN_ELIMINATE
1871 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1873 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1874 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1876 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1877 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1879 #undef TARGET_TRAMPOLINE_INIT
1880 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1882 #undef TARGET_FUNCTION_VALUE
1883 #define TARGET_FUNCTION_VALUE rs6000_function_value
1885 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1886 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1888 #undef TARGET_OPTION_SAVE
1889 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1891 #undef TARGET_OPTION_RESTORE
1892 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1894 #undef TARGET_OPTION_PRINT
1895 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1897 #undef TARGET_CAN_INLINE_P
1898 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1900 #undef TARGET_SET_CURRENT_FUNCTION
1901 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1903 #undef TARGET_LEGITIMATE_CONSTANT_P
1904 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1906 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1907 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1909 #undef TARGET_CAN_USE_DOLOOP_P
1910 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1912 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1913 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1916 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1919 #undef TARGET_UNWIND_WORD_MODE
1920 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1922 #undef TARGET_OFFLOAD_OPTIONS
1923 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1925 #undef TARGET_C_MODE_FOR_SUFFIX
1926 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1928 #undef TARGET_INVALID_BINARY_OP
1929 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1931 #undef TARGET_OPTAB_SUPPORTED_P
1932 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1934 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1935 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1937 #undef TARGET_COMPARE_VERSION_PRIORITY
1938 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1940 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1941 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1942 rs6000_generate_version_dispatcher_body
1944 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1945 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1946 rs6000_get_function_versions_dispatcher
1948 #undef TARGET_OPTION_FUNCTION_VERSIONS
1949 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1951 #undef TARGET_HARD_REGNO_NREGS
1952 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1953 #undef TARGET_HARD_REGNO_MODE_OK
1954 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1956 #undef TARGET_MODES_TIEABLE_P
1957 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1959 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1960 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1961 rs6000_hard_regno_call_part_clobbered
1963 #undef TARGET_SLOW_UNALIGNED_ACCESS
1964 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1966 #undef TARGET_CAN_CHANGE_MODE_CLASS
1967 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1969 #undef TARGET_CONSTANT_ALIGNMENT
1970 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1972 #undef TARGET_STARTING_FRAME_OFFSET
1973 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1975 #if TARGET_ELF && RS6000_WEAK
1976 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1977 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1980 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1981 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1983 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1984 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1987 /* Processor table. */
1990 const char *const name; /* Canonical processor name. */
1991 const enum processor_type processor; /* Processor type enum value. */
1992 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1995 static struct rs6000_ptt const processor_target_table[] =
1997 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1998 #include "rs6000-cpus.def"
2002 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2006 rs6000_cpu_name_lookup (const char *name)
2012 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2013 if (! strcmp (name, processor_target_table[i].name))
2021 /* Return number of consecutive hard regs needed starting at reg REGNO
2022 to hold something of mode MODE.
2023 This is ordinarily the length in words of a value of mode MODE
2024 but can be less for certain modes in special long registers.
2026 POWER and PowerPC GPRs hold 32 bits worth;
2027 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2030 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2032 unsigned HOST_WIDE_INT reg_size;
2034 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2035 128-bit floating point that can go in vector registers, which has VSX
2036 memory addressing. */
2037 if (FP_REGNO_P (regno))
2038 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2039 ? UNITS_PER_VSX_WORD
2040 : UNITS_PER_FP_WORD);
2042 else if (ALTIVEC_REGNO_P (regno))
2043 reg_size = UNITS_PER_ALTIVEC_WORD;
2046 reg_size = UNITS_PER_WORD;
2048 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2054 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2056 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2058 if (COMPLEX_MODE_P (mode))
2059 mode = GET_MODE_INNER (mode);
2061 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2062 register combinations, and use PTImode where we need to deal with quad
2063 word memory operations. Don't allow quad words in the argument or frame
2064 pointer registers, just registers 0..31. */
2065 if (mode == PTImode)
2066 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2067 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2068 && ((regno & 1) == 0));
2070 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2071 implementations. Don't allow an item to be split between a FP register
2072 and an Altivec register. Allow TImode in all VSX registers if the user
2074 if (TARGET_VSX && VSX_REGNO_P (regno)
2075 && (VECTOR_MEM_VSX_P (mode)
2076 || FLOAT128_VECTOR_P (mode)
2077 || reg_addr[mode].scalar_in_vmx_p
2079 || (TARGET_VADDUQM && mode == V1TImode)))
2081 if (FP_REGNO_P (regno))
2082 return FP_REGNO_P (last_regno);
2084 if (ALTIVEC_REGNO_P (regno))
2086 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2089 return ALTIVEC_REGNO_P (last_regno);
2093 /* The GPRs can hold any mode, but values bigger than one register
2094 cannot go past R31. */
2095 if (INT_REGNO_P (regno))
2096 return INT_REGNO_P (last_regno);
2098 /* The float registers (except for VSX vector modes) can only hold floating
2099 modes and DImode. */
2100 if (FP_REGNO_P (regno))
2102 if (FLOAT128_VECTOR_P (mode))
2105 if (SCALAR_FLOAT_MODE_P (mode)
2106 && (mode != TDmode || (regno % 2) == 0)
2107 && FP_REGNO_P (last_regno))
2110 if (GET_MODE_CLASS (mode) == MODE_INT)
2112 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2115 if (TARGET_P8_VECTOR && (mode == SImode))
2118 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2194 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2197 rs6000_hard_regno_call_part_clobbered (rtx_insn *insn ATTRIBUTE_UNUSED,
2198 unsigned int regno, machine_mode mode)
2202 && GET_MODE_SIZE (mode) > 4
2203 && INT_REGNO_P (regno))
2207 && FP_REGNO_P (regno)
2208 && GET_MODE_SIZE (mode) > 8
2209 && !FLOAT128_2REG_P (mode))
2215 /* Print interesting facts about registers. */
2217 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2221 for (r = first_regno; r <= last_regno; ++r)
2223 const char *comma = "";
2226 if (first_regno == last_regno)
2227 fprintf (stderr, "%s:\t", reg_name);
2229 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2232 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2233 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2237 fprintf (stderr, ",\n\t");
2242 if (rs6000_hard_regno_nregs[m][r] > 1)
2243 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2244 rs6000_hard_regno_nregs[m][r]);
2246 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2251 if (call_used_regs[r])
2255 fprintf (stderr, ",\n\t");
2260 len += fprintf (stderr, "%s%s", comma, "call-used");
2268 fprintf (stderr, ",\n\t");
2273 len += fprintf (stderr, "%s%s", comma, "fixed");
2279 fprintf (stderr, ",\n\t");
2283 len += fprintf (stderr, "%sreg-class = %s", comma,
2284 reg_class_names[(int)rs6000_regno_regclass[r]]);
2289 fprintf (stderr, ",\n\t");
2293 fprintf (stderr, "%sregno = %d\n", comma, r);
2298 rs6000_debug_vector_unit (enum rs6000_vector v)
2304 case VECTOR_NONE: ret = "none"; break;
2305 case VECTOR_ALTIVEC: ret = "altivec"; break;
2306 case VECTOR_VSX: ret = "vsx"; break;
2307 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2308 default: ret = "unknown"; break;
2314 /* Inner function printing just the address mask for a particular reload
2316 DEBUG_FUNCTION char *
2317 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2322 if ((mask & RELOAD_REG_VALID) != 0)
2324 else if (keep_spaces)
2327 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2329 else if (keep_spaces)
2332 if ((mask & RELOAD_REG_INDEXED) != 0)
2334 else if (keep_spaces)
2337 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2339 else if ((mask & RELOAD_REG_OFFSET) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2346 else if (keep_spaces)
2349 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2351 else if (keep_spaces)
2354 if ((mask & RELOAD_REG_AND_M16) != 0)
2356 else if (keep_spaces)
2364 /* Print the address masks in a human readble fashion. */
2366 rs6000_debug_print_mode (ssize_t m)
2371 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2372 for (rc = 0; rc < N_RELOAD_REG; rc++)
2373 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2374 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2376 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2377 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2379 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2380 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2381 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2385 spaces += sizeof (" Reload=sl") - 1;
2387 if (reg_addr[m].scalar_in_vmx_p)
2389 fprintf (stderr, "%*s Upper=y", spaces, "");
2393 spaces += sizeof (" Upper=y") - 1;
2395 if (rs6000_vector_unit[m] != VECTOR_NONE
2396 || rs6000_vector_mem[m] != VECTOR_NONE)
2398 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2400 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2401 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2404 fputs ("\n", stderr);
2407 #define DEBUG_FMT_ID "%-32s= "
2408 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2409 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2410 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2412 /* Print various interesting information with -mdebug=reg. */
2414 rs6000_debug_reg_global (void)
2416 static const char *const tf[2] = { "false", "true" };
2417 const char *nl = (const char *)0;
2420 char costly_num[20];
2422 char flags_buffer[40];
2423 const char *costly_str;
2424 const char *nop_str;
2425 const char *trace_str;
2426 const char *abi_str;
2427 const char *cmodel_str;
2428 struct cl_target_option cl_opts;
2430 /* Modes we want tieable information on. */
2431 static const machine_mode print_tieable_modes[] = {
2465 /* Virtual regs we are interested in. */
2466 const static struct {
2467 int regno; /* register number. */
2468 const char *name; /* register name. */
2469 } virtual_regs[] = {
2470 { STACK_POINTER_REGNUM, "stack pointer:" },
2471 { TOC_REGNUM, "toc: " },
2472 { STATIC_CHAIN_REGNUM, "static chain: " },
2473 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2474 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2475 { ARG_POINTER_REGNUM, "arg pointer: " },
2476 { FRAME_POINTER_REGNUM, "frame pointer:" },
2477 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2478 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2479 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2480 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2481 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2482 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2483 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2484 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2485 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2488 fputs ("\nHard register information:\n", stderr);
2489 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2490 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2491 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2494 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2495 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2496 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2497 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2498 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2499 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2501 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2502 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2503 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2507 "d reg_class = %s\n"
2508 "f reg_class = %s\n"
2509 "v reg_class = %s\n"
2510 "wa reg_class = %s\n"
2511 "wd reg_class = %s\n"
2512 "we reg_class = %s\n"
2513 "wf reg_class = %s\n"
2514 "wp reg_class = %s\n"
2515 "wq reg_class = %s\n"
2516 "wr reg_class = %s\n"
2517 "ww reg_class = %s\n"
2518 "wx reg_class = %s\n"
2519 "wA reg_class = %s\n"
2521 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2522 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2523 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2524 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2525 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2526 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2527 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2528 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2529 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2530 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2531 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2532 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2533 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
2536 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2537 rs6000_debug_print_mode (m);
2539 fputs ("\n", stderr);
2541 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2543 machine_mode mode1 = print_tieable_modes[m1];
2544 bool first_time = true;
2546 nl = (const char *)0;
2547 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2549 machine_mode mode2 = print_tieable_modes[m2];
2550 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2554 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2559 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2564 fputs ("\n", stderr);
2570 if (rs6000_recip_control)
2572 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2574 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2575 if (rs6000_recip_bits[m])
2578 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2580 (RS6000_RECIP_AUTO_RE_P (m)
2582 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2583 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2585 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2588 fputs ("\n", stderr);
2591 if (rs6000_cpu_index >= 0)
2593 const char *name = processor_target_table[rs6000_cpu_index].name;
2595 = processor_target_table[rs6000_cpu_index].target_enable;
2597 sprintf (flags_buffer, "-mcpu=%s flags", name);
2598 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2601 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2603 if (rs6000_tune_index >= 0)
2605 const char *name = processor_target_table[rs6000_tune_index].name;
2607 = processor_target_table[rs6000_tune_index].target_enable;
2609 sprintf (flags_buffer, "-mtune=%s flags", name);
2610 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2613 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2615 cl_target_option_save (&cl_opts, &global_options);
2616 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2619 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2620 rs6000_isa_flags_explicit);
2622 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2623 rs6000_builtin_mask);
2625 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2627 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2628 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2630 switch (rs6000_sched_costly_dep)
2632 case max_dep_latency:
2633 costly_str = "max_dep_latency";
2637 costly_str = "no_dep_costly";
2640 case all_deps_costly:
2641 costly_str = "all_deps_costly";
2644 case true_store_to_load_dep_costly:
2645 costly_str = "true_store_to_load_dep_costly";
2648 case store_to_load_dep_costly:
2649 costly_str = "store_to_load_dep_costly";
2653 costly_str = costly_num;
2654 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2658 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2660 switch (rs6000_sched_insert_nops)
2662 case sched_finish_regroup_exact:
2663 nop_str = "sched_finish_regroup_exact";
2666 case sched_finish_pad_groups:
2667 nop_str = "sched_finish_pad_groups";
2670 case sched_finish_none:
2671 nop_str = "sched_finish_none";
2676 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2680 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2682 switch (rs6000_sdata)
2689 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2693 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2697 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2702 switch (rs6000_traceback)
2704 case traceback_default: trace_str = "default"; break;
2705 case traceback_none: trace_str = "none"; break;
2706 case traceback_part: trace_str = "part"; break;
2707 case traceback_full: trace_str = "full"; break;
2708 default: trace_str = "unknown"; break;
2711 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2713 switch (rs6000_current_cmodel)
2715 case CMODEL_SMALL: cmodel_str = "small"; break;
2716 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2717 case CMODEL_LARGE: cmodel_str = "large"; break;
2718 default: cmodel_str = "unknown"; break;
2721 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2723 switch (rs6000_current_abi)
2725 case ABI_NONE: abi_str = "none"; break;
2726 case ABI_AIX: abi_str = "aix"; break;
2727 case ABI_ELFv2: abi_str = "ELFv2"; break;
2728 case ABI_V4: abi_str = "V4"; break;
2729 case ABI_DARWIN: abi_str = "darwin"; break;
2730 default: abi_str = "unknown"; break;
2733 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2735 if (rs6000_altivec_abi)
2736 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2738 if (rs6000_darwin64_abi)
2739 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2741 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2742 (TARGET_SOFT_FLOAT ? "true" : "false"));
2744 if (TARGET_LINK_STACK)
2745 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2747 if (TARGET_P8_FUSION)
2751 strcpy (options, "power8");
2752 if (TARGET_P8_FUSION_SIGN)
2753 strcat (options, ", sign");
2755 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2758 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2759 TARGET_SECURE_PLT ? "secure" : "bss");
2760 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2761 aix_struct_return ? "aix" : "sysv");
2762 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2763 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2764 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2765 tf[!!rs6000_align_branch_targets]);
2766 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2767 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2768 rs6000_long_double_type_size);
2769 if (rs6000_long_double_type_size > 64)
2771 fprintf (stderr, DEBUG_FMT_S, "long double type",
2772 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2773 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2774 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2776 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2777 (int)rs6000_sched_restricted_insns_priority);
2778 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2780 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2781 (int)RS6000_BUILTIN_COUNT);
2783 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2784 (int)TARGET_FLOAT128_ENABLE_TYPE);
2787 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2788 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2790 if (TARGET_DIRECT_MOVE_128)
2791 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2792 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2796 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2797 legitimate address support to figure out the appropriate addressing to
2801 rs6000_setup_reg_addr_masks (void)
2803 ssize_t rc, reg, m, nregs;
2804 addr_mask_type any_addr_mask, addr_mask;
2806 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2808 machine_mode m2 = (machine_mode) m;
2809 bool complex_p = false;
2810 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2813 if (COMPLEX_MODE_P (m2))
2816 m2 = GET_MODE_INNER (m2);
2819 msize = GET_MODE_SIZE (m2);
2821 /* SDmode is special in that we want to access it only via REG+REG
2822 addressing on power7 and above, since we want to use the LFIWZX and
2823 STFIWZX instructions to load it. */
2824 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2827 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2830 reg = reload_reg_map[rc].reg;
2832 /* Can mode values go in the GPR/FPR/Altivec registers? */
2833 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2835 bool small_int_vsx_p = (small_int_p
2836 && (rc == RELOAD_REG_FPR
2837 || rc == RELOAD_REG_VMX));
2839 nregs = rs6000_hard_regno_nregs[m][reg];
2840 addr_mask |= RELOAD_REG_VALID;
2842 /* Indicate if the mode takes more than 1 physical register. If
2843 it takes a single register, indicate it can do REG+REG
2844 addressing. Small integers in VSX registers can only do
2845 REG+REG addressing. */
2846 if (small_int_vsx_p)
2847 addr_mask |= RELOAD_REG_INDEXED;
2848 else if (nregs > 1 || m == BLKmode || complex_p)
2849 addr_mask |= RELOAD_REG_MULTIPLE;
2851 addr_mask |= RELOAD_REG_INDEXED;
2853 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2854 addressing. If we allow scalars into Altivec registers,
2855 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2857 For VSX systems, we don't allow update addressing for
2858 DFmode/SFmode if those registers can go in both the
2859 traditional floating point registers and Altivec registers.
2860 The load/store instructions for the Altivec registers do not
2861 have update forms. If we allowed update addressing, it seems
2862 to break IV-OPT code using floating point if the index type is
2863 int instead of long (PR target/81550 and target/84042). */
2866 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2868 && !VECTOR_MODE_P (m2)
2869 && !FLOAT128_VECTOR_P (m2)
2871 && (m != E_DFmode || !TARGET_VSX)
2872 && (m != E_SFmode || !TARGET_P8_VECTOR)
2873 && !small_int_vsx_p)
2875 addr_mask |= RELOAD_REG_PRE_INCDEC;
2877 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2878 we don't allow PRE_MODIFY for some multi-register
2883 addr_mask |= RELOAD_REG_PRE_MODIFY;
2887 if (TARGET_POWERPC64)
2888 addr_mask |= RELOAD_REG_PRE_MODIFY;
2893 if (TARGET_HARD_FLOAT)
2894 addr_mask |= RELOAD_REG_PRE_MODIFY;
2900 /* GPR and FPR registers can do REG+OFFSET addressing, except
2901 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2902 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2903 if ((addr_mask != 0) && !indexed_only_p
2905 && (rc == RELOAD_REG_GPR
2906 || ((msize == 8 || m2 == SFmode)
2907 && (rc == RELOAD_REG_FPR
2908 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2909 addr_mask |= RELOAD_REG_OFFSET;
2911 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2912 instructions are enabled. The offset for 128-bit VSX registers is
2913 only 12-bits. While GPRs can handle the full offset range, VSX
2914 registers can only handle the restricted range. */
2915 else if ((addr_mask != 0) && !indexed_only_p
2916 && msize == 16 && TARGET_P9_VECTOR
2917 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2918 || (m2 == TImode && TARGET_VSX)))
2920 addr_mask |= RELOAD_REG_OFFSET;
2921 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2922 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2925 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2926 addressing on 128-bit types. */
2927 if (rc == RELOAD_REG_VMX && msize == 16
2928 && (addr_mask & RELOAD_REG_VALID) != 0)
2929 addr_mask |= RELOAD_REG_AND_M16;
2931 reg_addr[m].addr_mask[rc] = addr_mask;
2932 any_addr_mask |= addr_mask;
2935 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2940 /* Initialize the various global tables that are based on register size. */
2942 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2948 /* Precalculate REGNO_REG_CLASS. */
2949 rs6000_regno_regclass[0] = GENERAL_REGS;
2950 for (r = 1; r < 32; ++r)
2951 rs6000_regno_regclass[r] = BASE_REGS;
2953 for (r = 32; r < 64; ++r)
2954 rs6000_regno_regclass[r] = FLOAT_REGS;
2956 for (r = 64; HARD_REGISTER_NUM_P (r); ++r)
2957 rs6000_regno_regclass[r] = NO_REGS;
2959 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2960 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2962 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2963 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2964 rs6000_regno_regclass[r] = CR_REGS;
2966 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2967 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2968 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2969 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2970 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2971 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2972 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2974 /* Precalculate register class to simpler reload register class. We don't
2975 need all of the register classes that are combinations of different
2976 classes, just the simple ones that have constraint letters. */
2977 for (c = 0; c < N_REG_CLASSES; c++)
2978 reg_class_to_reg_type[c] = NO_REG_TYPE;
2980 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2981 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
2982 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
2983 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
2984 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
2985 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
2986 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
2987 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
2988 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
2989 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
2993 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
2994 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
2998 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
2999 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3002 /* Precalculate the valid memory formats as well as the vector information,
3003 this must be set up before the rs6000_hard_regno_nregs_internal calls
3005 gcc_assert ((int)VECTOR_NONE == 0);
3006 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3007 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem));
3009 gcc_assert ((int)CODE_FOR_nothing == 0);
3010 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3012 gcc_assert ((int)NO_REGS == 0);
3013 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3015 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3016 believes it can use native alignment or still uses 128-bit alignment. */
3017 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3028 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3029 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3030 if (TARGET_FLOAT128_TYPE)
3032 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3033 rs6000_vector_align[KFmode] = 128;
3035 if (FLOAT128_IEEE_P (TFmode))
3037 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3038 rs6000_vector_align[TFmode] = 128;
3042 /* V2DF mode, VSX only. */
3045 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3046 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3047 rs6000_vector_align[V2DFmode] = align64;
3050 /* V4SF mode, either VSX or Altivec. */
3053 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3054 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3055 rs6000_vector_align[V4SFmode] = align32;
3057 else if (TARGET_ALTIVEC)
3059 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3060 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3061 rs6000_vector_align[V4SFmode] = align32;
3064 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3068 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3069 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3070 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3071 rs6000_vector_align[V4SImode] = align32;
3072 rs6000_vector_align[V8HImode] = align32;
3073 rs6000_vector_align[V16QImode] = align32;
3077 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3078 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3079 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3083 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3084 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3085 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3089 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3090 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3093 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3094 rs6000_vector_unit[V2DImode]
3095 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3096 rs6000_vector_align[V2DImode] = align64;
3098 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3099 rs6000_vector_unit[V1TImode]
3100 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3101 rs6000_vector_align[V1TImode] = 128;
3104 /* DFmode, see if we want to use the VSX unit. Memory is handled
3105 differently, so don't set rs6000_vector_mem. */
3108 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3109 rs6000_vector_align[DFmode] = 64;
3112 /* SFmode, see if we want to use the VSX unit. */
3113 if (TARGET_P8_VECTOR)
3115 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3116 rs6000_vector_align[SFmode] = 32;
3119 /* Allow TImode in VSX register and set the VSX memory macros. */
3122 rs6000_vector_mem[TImode] = VECTOR_VSX;
3123 rs6000_vector_align[TImode] = align64;
3126 /* Register class constraints for the constraints that depend on compile
3127 switches. When the VSX code was added, different constraints were added
3128 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3129 of the VSX registers are used. The register classes for scalar floating
3130 point types is set, based on whether we allow that type into the upper
3131 (Altivec) registers. GCC has register classes to target the Altivec
3132 registers for load/store operations, to select using a VSX memory
3133 operation instead of the traditional floating point operation. The
3136 d - Register class to use with traditional DFmode instructions.
3137 f - Register class to use with traditional SFmode instructions.
3138 v - Altivec register.
3139 wa - Any VSX register.
3140 wc - Reserved to represent individual CR bits (used in LLVM).
3141 wd - Preferred register class for V2DFmode.
3142 wf - Preferred register class for V4SFmode.
3143 wn - always NO_REGS.
3144 wr - GPR if 64-bit mode is permitted.
3145 ww - Register class to do SF conversions in with VSX operations.
3146 wx - Float register if we can do 32-bit int stores. */
3148 if (TARGET_HARD_FLOAT)
3150 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3151 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3156 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3157 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3158 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3161 /* Add conditional constraints based on various options, to allow us to
3162 collapse multiple insn patterns. */
3164 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3166 if (TARGET_POWERPC64)
3168 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3169 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3172 if (TARGET_P8_VECTOR) /* SFmode */
3173 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3174 else if (TARGET_VSX)
3175 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3178 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3180 if (TARGET_FLOAT128_TYPE)
3182 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3183 if (FLOAT128_IEEE_P (TFmode))
3184 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3187 /* Support for new direct moves (ISA 3.0 + 64bit). */
3188 if (TARGET_DIRECT_MOVE_128)
3189 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3191 /* Set up the reload helper and direct move functions. */
3192 if (TARGET_VSX || TARGET_ALTIVEC)
3196 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3197 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3198 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3199 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3200 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3201 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3202 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3203 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3204 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3205 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3206 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3207 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3208 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3209 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3210 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3211 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3212 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3213 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3214 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3215 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3217 if (FLOAT128_VECTOR_P (KFmode))
3219 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3220 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3223 if (FLOAT128_VECTOR_P (TFmode))
3225 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3226 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3229 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3231 if (TARGET_NO_SDMODE_STACK)
3233 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3234 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3239 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3240 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3243 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3245 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3246 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3247 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3248 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3249 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3250 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3251 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3252 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3253 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3255 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3256 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3257 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3258 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3259 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3260 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3261 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3262 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3263 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3265 if (FLOAT128_VECTOR_P (KFmode))
3267 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3268 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3271 if (FLOAT128_VECTOR_P (TFmode))
3273 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3274 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3280 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3281 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3282 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3283 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3284 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3285 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3286 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3287 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3288 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3289 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3290 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3291 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3292 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3293 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3294 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3295 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3296 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3297 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3298 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3299 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3301 if (FLOAT128_VECTOR_P (KFmode))
3303 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3304 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3307 if (FLOAT128_IEEE_P (TFmode))
3309 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3310 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3313 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3315 if (TARGET_NO_SDMODE_STACK)
3317 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3318 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3323 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3324 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3327 if (TARGET_DIRECT_MOVE)
3329 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3330 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3331 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3335 reg_addr[DFmode].scalar_in_vmx_p = true;
3336 reg_addr[DImode].scalar_in_vmx_p = true;
3338 if (TARGET_P8_VECTOR)
3340 reg_addr[SFmode].scalar_in_vmx_p = true;
3341 reg_addr[SImode].scalar_in_vmx_p = true;
3343 if (TARGET_P9_VECTOR)
3345 reg_addr[HImode].scalar_in_vmx_p = true;
3346 reg_addr[QImode].scalar_in_vmx_p = true;
3351 /* Precalculate HARD_REGNO_NREGS. */
3352 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3353 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3354 rs6000_hard_regno_nregs[m][r]
3355 = rs6000_hard_regno_nregs_internal (r, (machine_mode) m);
3357 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3358 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3359 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3360 rs6000_hard_regno_mode_ok_p[m][r]
3361 = rs6000_hard_regno_mode_ok_uncached (r, (machine_mode) m);
3363 /* Precalculate CLASS_MAX_NREGS sizes. */
3364 for (c = 0; c < LIM_REG_CLASSES; ++c)
3368 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3369 reg_size = UNITS_PER_VSX_WORD;
3371 else if (c == ALTIVEC_REGS)
3372 reg_size = UNITS_PER_ALTIVEC_WORD;
3374 else if (c == FLOAT_REGS)
3375 reg_size = UNITS_PER_FP_WORD;
3378 reg_size = UNITS_PER_WORD;
3380 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3382 machine_mode m2 = (machine_mode)m;
3383 int reg_size2 = reg_size;
3385 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3387 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3388 reg_size2 = UNITS_PER_FP_WORD;
3390 rs6000_class_max_nregs[m][c]
3391 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3395 /* Calculate which modes to automatically generate code to use a the
3396 reciprocal divide and square root instructions. In the future, possibly
3397 automatically generate the instructions even if the user did not specify
3398 -mrecip. The older machines double precision reciprocal sqrt estimate is
3399 not accurate enough. */
3400 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3402 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3404 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3405 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3406 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3407 if (VECTOR_UNIT_VSX_P (V2DFmode))
3408 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3410 if (TARGET_FRSQRTES)
3411 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3413 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3414 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3415 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3416 if (VECTOR_UNIT_VSX_P (V2DFmode))
3417 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3419 if (rs6000_recip_control)
3421 if (!flag_finite_math_only)
3422 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3424 if (flag_trapping_math)
3425 warning (0, "%qs requires %qs or %qs", "-mrecip",
3426 "-fno-trapping-math", "-ffast-math");
3427 if (!flag_reciprocal_math)
3428 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3430 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3432 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3433 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3434 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3436 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3437 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3438 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3440 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3441 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3442 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3444 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3445 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3446 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3448 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3449 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3450 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3452 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3453 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3454 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3456 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3457 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3458 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3460 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3461 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3462 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3466 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3467 legitimate address support to figure out the appropriate addressing to
3469 rs6000_setup_reg_addr_masks ();
3471 if (global_init_p || TARGET_DEBUG_TARGET)
3473 if (TARGET_DEBUG_REG)
3474 rs6000_debug_reg_global ();
3476 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3478 "SImode variable mult cost = %d\n"
3479 "SImode constant mult cost = %d\n"
3480 "SImode short constant mult cost = %d\n"
3481 "DImode multipliciation cost = %d\n"
3482 "SImode division cost = %d\n"
3483 "DImode division cost = %d\n"
3484 "Simple fp operation cost = %d\n"
3485 "DFmode multiplication cost = %d\n"
3486 "SFmode division cost = %d\n"
3487 "DFmode division cost = %d\n"
3488 "cache line size = %d\n"
3489 "l1 cache size = %d\n"
3490 "l2 cache size = %d\n"
3491 "simultaneous prefetches = %d\n"
3494 rs6000_cost->mulsi_const,
3495 rs6000_cost->mulsi_const9,
3503 rs6000_cost->cache_line_size,
3504 rs6000_cost->l1_cache_size,
3505 rs6000_cost->l2_cache_size,
3506 rs6000_cost->simultaneous_prefetches);
3511 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3514 darwin_rs6000_override_options (void)
3516 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3518 rs6000_altivec_abi = 1;
3519 TARGET_ALTIVEC_VRSAVE = 1;
3520 rs6000_current_abi = ABI_DARWIN;
3522 if (DEFAULT_ABI == ABI_DARWIN
3524 darwin_one_byte_bool = 1;
3526 if (TARGET_64BIT && ! TARGET_POWERPC64)
3528 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3529 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3533 rs6000_default_long_calls = 1;
3534 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3537 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3539 if (!flag_mkernel && !flag_apple_kext
3541 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3542 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3544 /* Unless the user (not the configurer) has explicitly overridden
3545 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3546 G4 unless targeting the kernel. */
3549 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3550 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3551 && ! global_options_set.x_rs6000_cpu_index)
3553 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3558 /* If not otherwise specified by a target, make 'long double' equivalent to
3561 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3562 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3565 /* Return the builtin mask of the various options used that could affect which
3566 builtins were used. In the past we used target_flags, but we've run out of
3567 bits, and some options are no longer in target_flags. */
3570 rs6000_builtin_mask_calculate (void)
3572 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3573 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3574 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3575 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3576 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3577 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3578 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3579 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3580 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3581 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3582 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3583 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3584 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3585 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3586 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3587 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3588 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3589 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3590 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3591 | ((TARGET_LONG_DOUBLE_128
3592 && TARGET_HARD_FLOAT
3593 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3594 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3595 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3598 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3599 to clobber the XER[CA] bit because clobbering that bit without telling
3600 the compiler worked just fine with versions of GCC before GCC 5, and
3601 breaking a lot of older code in ways that are hard to track down is
3602 not such a great idea. */
3605 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3606 vec<const char *> &/*constraints*/,
3607 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3609 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3610 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3614 /* Override command line options.
3616 Combine build-specific configuration information with options
3617 specified on the command line to set various state variables which
3618 influence code generation, optimization, and expansion of built-in
3619 functions. Assure that command-line configuration preferences are
3620 compatible with each other and with the build configuration; issue
3621 warnings while adjusting configuration or error messages while
3622 rejecting configuration.
3624 Upon entry to this function:
3626 This function is called once at the beginning of
3627 compilation, and then again at the start and end of compiling
3628 each section of code that has a different configuration, as
3629 indicated, for example, by adding the
3631 __attribute__((__target__("cpu=power9")))
3633 qualifier to a function definition or, for example, by bracketing
3636 #pragma GCC target("altivec")
3640 #pragma GCC reset_options
3642 directives. Parameter global_init_p is true for the initial
3643 invocation, which initializes global variables, and false for all
3644 subsequent invocations.
3647 Various global state information is assumed to be valid. This
3648 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3649 default CPU specified at build configure time, TARGET_DEFAULT,
3650 representing the default set of option flags for the default
3651 target, and global_options_set.x_rs6000_isa_flags, representing
3652 which options were requested on the command line.
3654 Upon return from this function:
3656 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3657 was set by name on the command line. Additionally, if certain
3658 attributes are automatically enabled or disabled by this function
3659 in order to assure compatibility between options and
3660 configuration, the flags associated with those attributes are
3661 also set. By setting these "explicit bits", we avoid the risk
3662 that other code might accidentally overwrite these particular
3663 attributes with "default values".
3665 The various bits of rs6000_isa_flags are set to indicate the
3666 target options that have been selected for the most current
3667 compilation efforts. This has the effect of also turning on the
3668 associated TARGET_XXX values since these are macros which are
3669 generally defined to test the corresponding bit of the
3670 rs6000_isa_flags variable.
3672 The variable rs6000_builtin_mask is set to represent the target
3673 options for the most current compilation efforts, consistent with
3674 the current contents of rs6000_isa_flags. This variable controls
3675 expansion of built-in functions.
3677 Various other global variables and fields of global structures
3678 (over 50 in all) are initialized to reflect the desired options
3679 for the most current compilation efforts. */
3682 rs6000_option_override_internal (bool global_init_p)
3686 HOST_WIDE_INT set_masks;
3687 HOST_WIDE_INT ignore_masks;
3690 struct cl_target_option *main_target_opt
3691 = ((global_init_p || target_option_default_node == NULL)
3692 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3694 /* Print defaults. */
3695 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3696 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3698 /* Remember the explicit arguments. */
3700 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3702 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3703 library functions, so warn about it. The flag may be useful for
3704 performance studies from time to time though, so don't disable it
3706 if (global_options_set.x_rs6000_alignment_flags
3707 && rs6000_alignment_flags == MASK_ALIGN_POWER
3708 && DEFAULT_ABI == ABI_DARWIN
3710 warning (0, "%qs is not supported for 64-bit Darwin;"
3711 " it is incompatible with the installed C and C++ libraries",
3714 /* Numerous experiment shows that IRA based loop pressure
3715 calculation works better for RTL loop invariant motion on targets
3716 with enough (>= 32) registers. It is an expensive optimization.
3717 So it is on only for peak performance. */
3718 if (optimize >= 3 && global_init_p
3719 && !global_options_set.x_flag_ira_loop_pressure)
3720 flag_ira_loop_pressure = 1;
3722 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3723 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3724 options were already specified. */
3725 if (flag_sanitize & SANITIZE_USER_ADDRESS
3726 && !global_options_set.x_flag_asynchronous_unwind_tables)
3727 flag_asynchronous_unwind_tables = 1;
3729 /* Set the pointer size. */
3732 rs6000_pmode = DImode;
3733 rs6000_pointer_size = 64;
3737 rs6000_pmode = SImode;
3738 rs6000_pointer_size = 32;
3741 /* Some OSs don't support saving the high part of 64-bit registers on context
3742 switch. Other OSs don't support saving Altivec registers. On those OSs,
3743 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3744 if the user wants either, the user must explicitly specify them and we
3745 won't interfere with the user's specification. */
3747 set_masks = POWERPC_MASKS;
3748 #ifdef OS_MISSING_POWERPC64
3749 if (OS_MISSING_POWERPC64)
3750 set_masks &= ~OPTION_MASK_POWERPC64;
3752 #ifdef OS_MISSING_ALTIVEC
3753 if (OS_MISSING_ALTIVEC)
3754 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3755 | OTHER_VSX_VECTOR_MASKS);
3758 /* Don't override by the processor default if given explicitly. */
3759 set_masks &= ~rs6000_isa_flags_explicit;
3761 if (global_init_p && rs6000_dejagnu_cpu_index >= 0)
3762 rs6000_cpu_index = rs6000_dejagnu_cpu_index;
3764 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3765 the cpu in a target attribute or pragma, but did not specify a tuning
3766 option, use the cpu for the tuning option rather than the option specified
3767 with -mtune on the command line. Process a '--with-cpu' configuration
3768 request as an implicit --cpu. */
3769 if (rs6000_cpu_index >= 0)
3770 cpu_index = rs6000_cpu_index;
3771 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3772 cpu_index = main_target_opt->x_rs6000_cpu_index;
3773 else if (OPTION_TARGET_CPU_DEFAULT)
3774 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3776 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3777 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3778 with those from the cpu, except for options that were explicitly set. If
3779 we don't have a cpu, do not override the target bits set in
3783 rs6000_cpu_index = cpu_index;
3784 rs6000_isa_flags &= ~set_masks;
3785 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3790 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3791 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3792 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3793 to using rs6000_isa_flags, we need to do the initialization here.
3795 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3796 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3797 HOST_WIDE_INT flags;
3799 flags = TARGET_DEFAULT;
3802 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3803 const char *default_cpu = (!TARGET_POWERPC64
3808 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3809 flags = processor_target_table[default_cpu_index].target_enable;
3811 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3814 if (rs6000_tune_index >= 0)
3815 tune_index = rs6000_tune_index;
3816 else if (cpu_index >= 0)
3817 rs6000_tune_index = tune_index = cpu_index;
3821 enum processor_type tune_proc
3822 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3825 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3826 if (processor_target_table[i].processor == tune_proc)
3834 rs6000_cpu = processor_target_table[cpu_index].processor;
3836 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3838 gcc_assert (tune_index >= 0);
3839 rs6000_tune = processor_target_table[tune_index].processor;
3841 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3842 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3843 || rs6000_cpu == PROCESSOR_PPCE5500)
3846 error ("AltiVec not supported in this target");
3849 /* If we are optimizing big endian systems for space, use the load/store
3850 multiple instructions. */
3851 if (BYTES_BIG_ENDIAN && optimize_size)
3852 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3854 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3855 because the hardware doesn't support the instructions used in little
3856 endian mode, and causes an alignment trap. The 750 does not cause an
3857 alignment trap (except when the target is unaligned). */
3859 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3861 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3862 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3863 warning (0, "%qs is not supported on little endian systems",
3867 /* If little-endian, default to -mstrict-align on older processors.
3868 Testing for htm matches power8 and later. */
3869 if (!BYTES_BIG_ENDIAN
3870 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3871 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3873 if (!rs6000_fold_gimple)
3875 "gimple folding of rs6000 builtins has been disabled.\n");
3877 /* Add some warnings for VSX. */
3880 const char *msg = NULL;
3881 if (!TARGET_HARD_FLOAT)
3883 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3884 msg = N_("%<-mvsx%> requires hardware floating point");
3887 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3888 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3891 else if (TARGET_AVOID_XFORM > 0)
3892 msg = N_("%<-mvsx%> needs indexed addressing");
3893 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3894 & OPTION_MASK_ALTIVEC))
3896 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3897 msg = N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
3899 msg = N_("%<-mno-altivec%> disables vsx");
3905 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3906 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3910 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3911 the -mcpu setting to enable options that conflict. */
3912 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3913 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3914 | OPTION_MASK_ALTIVEC
3915 | OPTION_MASK_VSX)) != 0)
3916 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3917 | OPTION_MASK_DIRECT_MOVE)
3918 & ~rs6000_isa_flags_explicit);
3920 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3921 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3923 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
3924 off all of the options that depend on those flags. */
3925 ignore_masks = rs6000_disable_incompatible_switches ();
3927 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3928 unless the user explicitly used the -mno-<option> to disable the code. */
3929 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
3930 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3931 else if (TARGET_P9_MINMAX)
3935 if (cpu_index == PROCESSOR_POWER9)
3937 /* legacy behavior: allow -mcpu=power9 with certain
3938 capabilities explicitly disabled. */
3939 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3942 error ("power9 target option is incompatible with %<%s=<xxx>%> "
3943 "for <xxx> less than power9", "-mcpu");
3945 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
3946 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
3947 & rs6000_isa_flags_explicit))
3948 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
3949 were explicitly cleared. */
3950 error ("%qs incompatible with explicitly disabled options",
3953 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
3955 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
3956 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
3957 else if (TARGET_VSX)
3958 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
3959 else if (TARGET_POPCNTD)
3960 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
3961 else if (TARGET_DFP)
3962 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
3963 else if (TARGET_CMPB)
3964 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
3965 else if (TARGET_FPRND)
3966 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
3967 else if (TARGET_POPCNTB)
3968 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
3969 else if (TARGET_ALTIVEC)
3970 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
3972 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
3974 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
3975 error ("%qs requires %qs", "-mcrypto", "-maltivec");
3976 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
3979 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
3981 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
3982 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
3983 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
3986 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
3988 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
3989 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
3990 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
3993 if (TARGET_P8_VECTOR && !TARGET_VSX)
3995 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
3996 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
3997 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
3998 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4000 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4001 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4002 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4006 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4008 rs6000_isa_flags |= OPTION_MASK_VSX;
4009 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4013 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4015 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4016 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4017 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4020 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4021 silently turn off quad memory mode. */
4022 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4024 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4025 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4027 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4028 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4030 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4031 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4034 /* Non-atomic quad memory load/store are disabled for little endian, since
4035 the words are reversed, but atomic operations can still be done by
4036 swapping the words. */
4037 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4039 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4040 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4043 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4046 /* Assume if the user asked for normal quad memory instructions, they want
4047 the atomic versions as well, unless they explicity told us not to use quad
4048 word atomic instructions. */
4049 if (TARGET_QUAD_MEMORY
4050 && !TARGET_QUAD_MEMORY_ATOMIC
4051 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4052 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4054 /* If we can shrink-wrap the TOC register save separately, then use
4055 -msave-toc-indirect unless explicitly disabled. */
4056 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4057 && flag_shrink_wrap_separate
4058 && optimize_function_for_speed_p (cfun))
4059 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4061 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4062 generating power8 instructions. Power9 does not optimize power8 fusion
4064 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4066 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4067 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4069 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4072 /* Setting additional fusion flags turns on base fusion. */
4073 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4075 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4077 if (TARGET_P8_FUSION_SIGN)
4078 error ("%qs requires %qs", "-mpower8-fusion-sign",
4081 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4084 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4087 /* Power8 does not fuse sign extended loads with the addis. If we are
4088 optimizing at high levels for speed, convert a sign extended load into a
4089 zero extending load, and an explicit sign extension. */
4090 if (TARGET_P8_FUSION
4091 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4092 && optimize_function_for_speed_p (cfun)
4094 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4096 /* ISA 3.0 vector instructions include ISA 2.07. */
4097 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4099 /* We prefer to not mention undocumented options in
4100 error messages. However, if users have managed to select
4101 power9-vector without selecting power8-vector, they
4102 already know about undocumented flags. */
4103 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4104 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4105 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4106 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4108 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4109 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4110 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4114 /* OPTION_MASK_P9_VECTOR is explicit and
4115 OPTION_MASK_P8_VECTOR is not explicit. */
4116 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4117 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4121 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4122 support. If we only have ISA 2.06 support, and the user did not specify
4123 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4124 but we don't enable the full vectorization support */
4125 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4126 TARGET_ALLOW_MOVMISALIGN = 1;
4128 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4130 if (TARGET_ALLOW_MOVMISALIGN > 0
4131 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4132 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4134 TARGET_ALLOW_MOVMISALIGN = 0;
4137 /* Determine when unaligned vector accesses are permitted, and when
4138 they are preferred over masked Altivec loads. Note that if
4139 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4140 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4142 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4146 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4147 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4149 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4152 else if (!TARGET_ALLOW_MOVMISALIGN)
4154 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4155 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4156 "-mallow-movmisalign");
4158 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4162 /* Use long double size to select the appropriate long double. We use
4163 TYPE_PRECISION to differentiate the 3 different long double types. We map
4164 128 into the precision used for TFmode. */
4165 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4167 : FLOAT_PRECISION_TFmode);
4169 /* Set long double size before the IEEE 128-bit tests. */
4170 if (!global_options_set.x_rs6000_long_double_type_size)
4172 if (main_target_opt != NULL
4173 && (main_target_opt->x_rs6000_long_double_type_size
4174 != default_long_double_size))
4175 error ("target attribute or pragma changes %<long double%> size");
4177 rs6000_long_double_type_size = default_long_double_size;
4179 else if (rs6000_long_double_type_size == 128)
4180 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4181 else if (global_options_set.x_rs6000_ieeequad)
4183 if (global_options.x_rs6000_ieeequad)
4184 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4186 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4189 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4190 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4191 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4192 those systems will not pick up this default. Warn if the user changes the
4193 default unless -Wno-psabi. */
4194 if (!global_options_set.x_rs6000_ieeequad)
4195 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4199 if (global_options.x_rs6000_ieeequad
4200 && (!TARGET_POPCNTD || !TARGET_VSX))
4201 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4203 if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4205 static bool warned_change_long_double;
4206 if (!warned_change_long_double)
4208 warned_change_long_double = true;
4209 if (TARGET_IEEEQUAD)
4210 warning (OPT_Wpsabi, "Using IEEE extended precision "
4213 warning (OPT_Wpsabi, "Using IBM extended precision "
4219 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4220 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4221 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4222 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4223 the keyword as well as the type. */
4224 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4226 /* IEEE 128-bit floating point requires VSX support. */
4227 if (TARGET_FLOAT128_KEYWORD)
4231 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4232 error ("%qs requires VSX support", "%<-mfloat128%>");
4234 TARGET_FLOAT128_TYPE = 0;
4235 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4236 | OPTION_MASK_FLOAT128_HW);
4238 else if (!TARGET_FLOAT128_TYPE)
4240 TARGET_FLOAT128_TYPE = 1;
4241 warning (0, "The %<-mfloat128%> option may not be fully supported");
4245 /* Enable the __float128 keyword under Linux by default. */
4246 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4247 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4248 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4250 /* If we have are supporting the float128 type and full ISA 3.0 support,
4251 enable -mfloat128-hardware by default. However, don't enable the
4252 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4253 because sometimes the compiler wants to put things in an integer
4254 container, and if we don't have __int128 support, it is impossible. */
4255 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4256 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4257 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4258 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4260 if (TARGET_FLOAT128_HW
4261 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4263 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4264 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4266 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4269 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4271 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4272 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4274 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4277 /* -mpcrel requires prefixed load/store addressing. */
4278 if (TARGET_PCREL && !TARGET_PREFIXED_ADDR)
4280 if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
4281 error ("%qs requires %qs", "-mpcrel", "-mprefixed-addr");
4283 rs6000_isa_flags &= ~OPTION_MASK_PCREL;
4286 /* -mprefixed-addr (and hence -mpcrel) requires -mcpu=future. */
4287 if (TARGET_PREFIXED_ADDR && !TARGET_FUTURE)
4289 if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
4290 error ("%qs requires %qs", "-mprefixed-addr", "-mcpu=future");
4292 rs6000_isa_flags &= ~(OPTION_MASK_PCREL | OPTION_MASK_PREFIXED_ADDR);
4295 /* Print the options after updating the defaults. */
4296 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4297 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4299 /* E500mc does "better" if we inline more aggressively. Respect the
4300 user's opinion, though. */
4301 if (rs6000_block_move_inline_limit == 0
4302 && (rs6000_tune == PROCESSOR_PPCE500MC
4303 || rs6000_tune == PROCESSOR_PPCE500MC64
4304 || rs6000_tune == PROCESSOR_PPCE5500
4305 || rs6000_tune == PROCESSOR_PPCE6500))
4306 rs6000_block_move_inline_limit = 128;
4308 /* store_one_arg depends on expand_block_move to handle at least the
4309 size of reg_parm_stack_space. */
4310 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4311 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4315 /* If the appropriate debug option is enabled, replace the target hooks
4316 with debug versions that call the real version and then prints
4317 debugging information. */
4318 if (TARGET_DEBUG_COST)
4320 targetm.rtx_costs = rs6000_debug_rtx_costs;
4321 targetm.address_cost = rs6000_debug_address_cost;
4322 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4325 if (TARGET_DEBUG_ADDR)
4327 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4328 targetm.legitimize_address = rs6000_debug_legitimize_address;
4329 rs6000_secondary_reload_class_ptr
4330 = rs6000_debug_secondary_reload_class;
4331 targetm.secondary_memory_needed
4332 = rs6000_debug_secondary_memory_needed;
4333 targetm.can_change_mode_class
4334 = rs6000_debug_can_change_mode_class;
4335 rs6000_preferred_reload_class_ptr
4336 = rs6000_debug_preferred_reload_class;
4337 rs6000_mode_dependent_address_ptr
4338 = rs6000_debug_mode_dependent_address;
4341 if (rs6000_veclibabi_name)
4343 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4344 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4347 error ("unknown vectorization library ABI type (%qs) for "
4348 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4354 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4355 target attribute or pragma which automatically enables both options,
4356 unless the altivec ABI was set. This is set by default for 64-bit, but
4358 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4360 TARGET_FLOAT128_TYPE = 0;
4361 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4362 | OPTION_MASK_FLOAT128_KEYWORD)
4363 & ~rs6000_isa_flags_explicit);
4366 /* Enable Altivec ABI for AIX -maltivec. */
4367 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4369 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4370 error ("target attribute or pragma changes AltiVec ABI");
4372 rs6000_altivec_abi = 1;
4375 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4376 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4377 be explicitly overridden in either case. */
4380 if (!global_options_set.x_rs6000_altivec_abi
4381 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4383 if (main_target_opt != NULL &&
4384 !main_target_opt->x_rs6000_altivec_abi)
4385 error ("target attribute or pragma changes AltiVec ABI");
4387 rs6000_altivec_abi = 1;
4391 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4392 So far, the only darwin64 targets are also MACH-O. */
4394 && DEFAULT_ABI == ABI_DARWIN
4397 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4398 error ("target attribute or pragma changes darwin64 ABI");
4401 rs6000_darwin64_abi = 1;
4402 /* Default to natural alignment, for better performance. */
4403 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4407 /* Place FP constants in the constant pool instead of TOC
4408 if section anchors enabled. */
4409 if (flag_section_anchors
4410 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4411 TARGET_NO_FP_IN_TOC = 1;
4413 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4414 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4416 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4417 SUBTARGET_OVERRIDE_OPTIONS;
4419 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4420 SUBSUBTARGET_OVERRIDE_OPTIONS;
4422 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4423 SUB3TARGET_OVERRIDE_OPTIONS;
4426 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4427 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4429 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4430 && rs6000_tune != PROCESSOR_POWER5
4431 && rs6000_tune != PROCESSOR_POWER6
4432 && rs6000_tune != PROCESSOR_POWER7
4433 && rs6000_tune != PROCESSOR_POWER8
4434 && rs6000_tune != PROCESSOR_POWER9
4435 && rs6000_tune != PROCESSOR_FUTURE
4436 && rs6000_tune != PROCESSOR_PPCA2
4437 && rs6000_tune != PROCESSOR_CELL
4438 && rs6000_tune != PROCESSOR_PPC476);
4439 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4440 || rs6000_tune == PROCESSOR_POWER5
4441 || rs6000_tune == PROCESSOR_POWER7
4442 || rs6000_tune == PROCESSOR_POWER8);
4443 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4444 || rs6000_tune == PROCESSOR_POWER5
4445 || rs6000_tune == PROCESSOR_POWER6
4446 || rs6000_tune == PROCESSOR_POWER7
4447 || rs6000_tune == PROCESSOR_POWER8
4448 || rs6000_tune == PROCESSOR_POWER9
4449 || rs6000_tune == PROCESSOR_FUTURE
4450 || rs6000_tune == PROCESSOR_PPCE500MC
4451 || rs6000_tune == PROCESSOR_PPCE500MC64
4452 || rs6000_tune == PROCESSOR_PPCE5500
4453 || rs6000_tune == PROCESSOR_PPCE6500);
4455 /* Allow debug switches to override the above settings. These are set to -1
4456 in rs6000.opt to indicate the user hasn't directly set the switch. */
4457 if (TARGET_ALWAYS_HINT >= 0)
4458 rs6000_always_hint = TARGET_ALWAYS_HINT;
4460 if (TARGET_SCHED_GROUPS >= 0)
4461 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4463 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4464 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4466 rs6000_sched_restricted_insns_priority
4467 = (rs6000_sched_groups ? 1 : 0);
4469 /* Handle -msched-costly-dep option. */
4470 rs6000_sched_costly_dep
4471 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4473 if (rs6000_sched_costly_dep_str)
4475 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4476 rs6000_sched_costly_dep = no_dep_costly;
4477 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4478 rs6000_sched_costly_dep = all_deps_costly;
4479 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4480 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4481 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4482 rs6000_sched_costly_dep = store_to_load_dep_costly;
4484 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4485 atoi (rs6000_sched_costly_dep_str));
4488 /* Handle -minsert-sched-nops option. */
4489 rs6000_sched_insert_nops
4490 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4492 if (rs6000_sched_insert_nops_str)
4494 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4495 rs6000_sched_insert_nops = sched_finish_none;
4496 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4497 rs6000_sched_insert_nops = sched_finish_pad_groups;
4498 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4499 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4501 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4502 atoi (rs6000_sched_insert_nops_str));
4505 /* Handle stack protector */
4506 if (!global_options_set.x_rs6000_stack_protector_guard)
4507 #ifdef TARGET_THREAD_SSP_OFFSET
4508 rs6000_stack_protector_guard = SSP_TLS;
4510 rs6000_stack_protector_guard = SSP_GLOBAL;
4513 #ifdef TARGET_THREAD_SSP_OFFSET
4514 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4515 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4518 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4521 const char *str = rs6000_stack_protector_guard_offset_str;
4524 long offset = strtol (str, &endp, 0);
4525 if (!*str || *endp || errno)
4526 error ("%qs is not a valid number in %qs", str,
4527 "-mstack-protector-guard-offset=");
4529 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4530 || (TARGET_64BIT && (offset & 3)))
4531 error ("%qs is not a valid offset in %qs", str,
4532 "-mstack-protector-guard-offset=");
4534 rs6000_stack_protector_guard_offset = offset;
4537 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4539 const char *str = rs6000_stack_protector_guard_reg_str;
4540 int reg = decode_reg_name (str);
4542 if (!IN_RANGE (reg, 1, 31))
4543 error ("%qs is not a valid base register in %qs", str,
4544 "-mstack-protector-guard-reg=");
4546 rs6000_stack_protector_guard_reg = reg;
4549 if (rs6000_stack_protector_guard == SSP_TLS
4550 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4551 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4555 #ifdef TARGET_REGNAMES
4556 /* If the user desires alternate register names, copy in the
4557 alternate names now. */
4558 if (TARGET_REGNAMES)
4559 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4562 /* Set aix_struct_return last, after the ABI is determined.
4563 If -maix-struct-return or -msvr4-struct-return was explicitly
4564 used, don't override with the ABI default. */
4565 if (!global_options_set.x_aix_struct_return)
4566 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4569 /* IBM XL compiler defaults to unsigned bitfields. */
4570 if (TARGET_XL_COMPAT)
4571 flag_signed_bitfields = 0;
4574 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4575 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4577 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4579 /* We can only guarantee the availability of DI pseudo-ops when
4580 assembling for 64-bit targets. */
4583 targetm.asm_out.aligned_op.di = NULL;
4584 targetm.asm_out.unaligned_op.di = NULL;
4588 /* Set branch target alignment, if not optimizing for size. */
4591 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4592 aligned 8byte to avoid misprediction by the branch predictor. */
4593 if (rs6000_tune == PROCESSOR_TITAN
4594 || rs6000_tune == PROCESSOR_CELL)
4596 if (flag_align_functions && !str_align_functions)
4597 str_align_functions = "8";
4598 if (flag_align_jumps && !str_align_jumps)
4599 str_align_jumps = "8";
4600 if (flag_align_loops && !str_align_loops)
4601 str_align_loops = "8";
4603 if (rs6000_align_branch_targets)
4605 if (flag_align_functions && !str_align_functions)
4606 str_align_functions = "16";
4607 if (flag_align_jumps && !str_align_jumps)
4608 str_align_jumps = "16";
4609 if (flag_align_loops && !str_align_loops)
4611 can_override_loop_align = 1;
4612 str_align_loops = "16";
4616 if (flag_align_jumps && !str_align_jumps)
4617 str_align_jumps = "16";
4618 if (flag_align_loops && !str_align_loops)
4619 str_align_loops = "16";
4622 /* Arrange to save and restore machine status around nested functions. */
4623 init_machine_status = rs6000_init_machine_status;
4625 /* We should always be splitting complex arguments, but we can't break
4626 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4627 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4628 targetm.calls.split_complex_arg = NULL;
4630 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4631 if (DEFAULT_ABI == ABI_AIX)
4632 targetm.calls.custom_function_descriptors = 0;
4635 /* Initialize rs6000_cost with the appropriate target costs. */
4637 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4639 switch (rs6000_tune)
4641 case PROCESSOR_RS64A:
4642 rs6000_cost = &rs64a_cost;
4645 case PROCESSOR_MPCCORE:
4646 rs6000_cost = &mpccore_cost;
4649 case PROCESSOR_PPC403:
4650 rs6000_cost = &ppc403_cost;
4653 case PROCESSOR_PPC405:
4654 rs6000_cost = &ppc405_cost;
4657 case PROCESSOR_PPC440:
4658 rs6000_cost = &ppc440_cost;
4661 case PROCESSOR_PPC476:
4662 rs6000_cost = &ppc476_cost;
4665 case PROCESSOR_PPC601:
4666 rs6000_cost = &ppc601_cost;
4669 case PROCESSOR_PPC603:
4670 rs6000_cost = &ppc603_cost;
4673 case PROCESSOR_PPC604:
4674 rs6000_cost = &ppc604_cost;
4677 case PROCESSOR_PPC604e:
4678 rs6000_cost = &ppc604e_cost;
4681 case PROCESSOR_PPC620:
4682 rs6000_cost = &ppc620_cost;
4685 case PROCESSOR_PPC630:
4686 rs6000_cost = &ppc630_cost;
4689 case PROCESSOR_CELL:
4690 rs6000_cost = &ppccell_cost;
4693 case PROCESSOR_PPC750:
4694 case PROCESSOR_PPC7400:
4695 rs6000_cost = &ppc750_cost;
4698 case PROCESSOR_PPC7450:
4699 rs6000_cost = &ppc7450_cost;
4702 case PROCESSOR_PPC8540:
4703 case PROCESSOR_PPC8548:
4704 rs6000_cost = &ppc8540_cost;
4707 case PROCESSOR_PPCE300C2:
4708 case PROCESSOR_PPCE300C3:
4709 rs6000_cost = &ppce300c2c3_cost;
4712 case PROCESSOR_PPCE500MC:
4713 rs6000_cost = &ppce500mc_cost;
4716 case PROCESSOR_PPCE500MC64:
4717 rs6000_cost = &ppce500mc64_cost;
4720 case PROCESSOR_PPCE5500:
4721 rs6000_cost = &ppce5500_cost;
4724 case PROCESSOR_PPCE6500:
4725 rs6000_cost = &ppce6500_cost;
4728 case PROCESSOR_TITAN:
4729 rs6000_cost = &titan_cost;
4732 case PROCESSOR_POWER4:
4733 case PROCESSOR_POWER5:
4734 rs6000_cost = &power4_cost;
4737 case PROCESSOR_POWER6:
4738 rs6000_cost = &power6_cost;
4741 case PROCESSOR_POWER7:
4742 rs6000_cost = &power7_cost;
4745 case PROCESSOR_POWER8:
4746 rs6000_cost = &power8_cost;
4749 case PROCESSOR_POWER9:
4750 case PROCESSOR_FUTURE:
4751 rs6000_cost = &power9_cost;
4754 case PROCESSOR_PPCA2:
4755 rs6000_cost = &ppca2_cost;
4764 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4765 rs6000_cost->simultaneous_prefetches,
4766 global_options.x_param_values,
4767 global_options_set.x_param_values);
4768 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4769 global_options.x_param_values,
4770 global_options_set.x_param_values);
4771 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4772 rs6000_cost->cache_line_size,
4773 global_options.x_param_values,
4774 global_options_set.x_param_values);
4775 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4776 global_options.x_param_values,
4777 global_options_set.x_param_values);
4779 /* Increase loop peeling limits based on performance analysis. */
4780 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4781 global_options.x_param_values,
4782 global_options_set.x_param_values);
4783 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4784 global_options.x_param_values,
4785 global_options_set.x_param_values);
4787 /* Use the 'model' -fsched-pressure algorithm by default. */
4788 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4789 SCHED_PRESSURE_MODEL,
4790 global_options.x_param_values,
4791 global_options_set.x_param_values);
4793 /* If using typedef char *va_list, signal that
4794 __builtin_va_start (&ap, 0) can be optimized to
4795 ap = __builtin_next_arg (0). */
4796 if (DEFAULT_ABI != ABI_V4)
4797 targetm.expand_builtin_va_start = NULL;
4800 /* If not explicitly specified via option, decide whether to generate indexed
4801 load/store instructions. A value of -1 indicates that the
4802 initial value of this variable has not been overwritten. During
4803 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4804 if (TARGET_AVOID_XFORM == -1)
4805 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4806 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4807 need indexed accesses and the type used is the scalar type of the element
4808 being loaded or stored. */
4809 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4810 && !TARGET_ALTIVEC);
4812 /* Set the -mrecip options. */
4813 if (rs6000_recip_name)
4815 char *p = ASTRDUP (rs6000_recip_name);
4817 unsigned int mask, i;
4820 while ((q = strtok (p, ",")) != NULL)
4831 if (!strcmp (q, "default"))
4832 mask = ((TARGET_RECIP_PRECISION)
4833 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4836 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4837 if (!strcmp (q, recip_options[i].string))
4839 mask = recip_options[i].mask;
4843 if (i == ARRAY_SIZE (recip_options))
4845 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4853 rs6000_recip_control &= ~mask;
4855 rs6000_recip_control |= mask;
4859 /* Set the builtin mask of the various options used that could affect which
4860 builtins were used. In the past we used target_flags, but we've run out
4861 of bits, and some options are no longer in target_flags. */
4862 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4863 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4864 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4865 rs6000_builtin_mask);
4867 /* Initialize all of the registers. */
4868 rs6000_init_hard_regno_mode_ok (global_init_p);
4870 /* Save the initial options in case the user does function specific options */
4872 target_option_default_node = target_option_current_node
4873 = build_target_option_node (&global_options);
4875 /* If not explicitly specified via option, decide whether to generate the
4876 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4877 if (TARGET_LINK_STACK == -1)
4878 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4880 /* Deprecate use of -mno-speculate-indirect-jumps. */
4881 if (!rs6000_speculate_indirect_jumps)
4882 warning (0, "%qs is deprecated and not recommended in any circumstances",
4883 "-mno-speculate-indirect-jumps");
4888 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4889 define the target cpu type. */
4892 rs6000_option_override (void)
4894 (void) rs6000_option_override_internal (true);
4898 /* Implement targetm.vectorize.builtin_mask_for_load. */
4900 rs6000_builtin_mask_for_load (void)
4902 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4903 if ((TARGET_ALTIVEC && !TARGET_VSX)
4904 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4905 return altivec_builtin_mask_for_load;
4910 /* Implement LOOP_ALIGN. */
4912 rs6000_loop_align (rtx label)
4917 /* Don't override loop alignment if -falign-loops was specified. */
4918 if (!can_override_loop_align)
4921 bb = BLOCK_FOR_INSN (label);
4922 ninsns = num_loop_insns(bb->loop_father);
4924 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4925 if (ninsns > 4 && ninsns <= 8
4926 && (rs6000_tune == PROCESSOR_POWER4
4927 || rs6000_tune == PROCESSOR_POWER5
4928 || rs6000_tune == PROCESSOR_POWER6
4929 || rs6000_tune == PROCESSOR_POWER7
4930 || rs6000_tune == PROCESSOR_POWER8))
4931 return align_flags (5);
4936 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4937 after applying N number of iterations. This routine does not determine
4938 how may iterations are required to reach desired alignment. */
4941 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4948 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4951 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4961 /* Assuming that all other types are naturally aligned. CHECKME! */
4966 /* Return true if the vector misalignment factor is supported by the
4969 rs6000_builtin_support_vector_misalignment (machine_mode mode,
4976 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4979 /* Return if movmisalign pattern is not supported for this mode. */
4980 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
4983 if (misalignment == -1)
4985 /* Misalignment factor is unknown at compile time but we know
4986 it's word aligned. */
4987 if (rs6000_vector_alignment_reachable (type, is_packed))
4989 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
4991 if (element_size == 64 || element_size == 32)
4998 /* VSX supports word-aligned vector. */
4999 if (misalignment % 4 == 0)
5005 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5007 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5008 tree vectype, int misalign)
5013 switch (type_of_cost)
5023 case cond_branch_not_taken:
5032 case vec_promote_demote:
5038 case cond_branch_taken:
5041 case unaligned_load:
5042 case vector_gather_load:
5043 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5046 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5048 elements = TYPE_VECTOR_SUBPARTS (vectype);
5050 /* Double word aligned. */
5058 /* Double word aligned. */
5062 /* Unknown misalignment. */
5075 /* Misaligned loads are not supported. */
5080 case unaligned_store:
5081 case vector_scatter_store:
5082 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5085 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5087 elements = TYPE_VECTOR_SUBPARTS (vectype);
5089 /* Double word aligned. */
5097 /* Double word aligned. */
5101 /* Unknown misalignment. */
5114 /* Misaligned stores are not supported. */
5120 /* This is a rough approximation assuming non-constant elements
5121 constructed into a vector via element insertion. FIXME:
5122 vec_construct is not granular enough for uniformly good
5123 decisions. If the initialization is a splat, this is
5124 cheaper than we estimate. Improve this someday. */
5125 elem_type = TREE_TYPE (vectype);
5126 /* 32-bit vectors loaded into registers are stored as double
5127 precision, so we need 2 permutes, 2 converts, and 1 merge
5128 to construct a vector of short floats from them. */
5129 if (SCALAR_FLOAT_TYPE_P (elem_type)
5130 && TYPE_PRECISION (elem_type) == 32)
5132 /* On POWER9, integer vector types are built up in GPRs and then
5133 use a direct move (2 cycles). For POWER8 this is even worse,
5134 as we need two direct moves and a merge, and the direct moves
5136 else if (INTEGRAL_TYPE_P (elem_type))
5138 if (TARGET_P9_VECTOR)
5139 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5141 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5144 /* V2DFmode doesn't need a direct move. */
5152 /* Implement targetm.vectorize.preferred_simd_mode. */
5155 rs6000_preferred_simd_mode (scalar_mode mode)
5164 if (TARGET_ALTIVEC || TARGET_VSX)
5184 typedef struct _rs6000_cost_data
5186 struct loop *loop_info;
5190 /* Test for likely overcommitment of vector hardware resources. If a
5191 loop iteration is relatively large, and too large a percentage of
5192 instructions in the loop are vectorized, the cost model may not
5193 adequately reflect delays from unavailable vector resources.
5194 Penalize the loop body cost for this case. */
5197 rs6000_density_test (rs6000_cost_data *data)
5199 const int DENSITY_PCT_THRESHOLD = 85;
5200 const int DENSITY_SIZE_THRESHOLD = 70;
5201 const int DENSITY_PENALTY = 10;
5202 struct loop *loop = data->loop_info;
5203 basic_block *bbs = get_loop_body (loop);
5204 int nbbs = loop->num_nodes;
5205 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5206 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5209 for (i = 0; i < nbbs; i++)
5211 basic_block bb = bbs[i];
5212 gimple_stmt_iterator gsi;
5214 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5216 gimple *stmt = gsi_stmt (gsi);
5217 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5219 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5220 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5226 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5228 if (density_pct > DENSITY_PCT_THRESHOLD
5229 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5231 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5232 if (dump_enabled_p ())
5233 dump_printf_loc (MSG_NOTE, vect_location,
5234 "density %d%%, cost %d exceeds threshold, penalizing "
5235 "loop body cost by %d%%", density_pct,
5236 vec_cost + not_vec_cost, DENSITY_PENALTY);
5240 /* Implement targetm.vectorize.init_cost. */
5242 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5243 instruction is needed by the vectorization. */
5244 static bool rs6000_vect_nonmem;
5247 rs6000_init_cost (struct loop *loop_info)
5249 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5250 data->loop_info = loop_info;
5251 data->cost[vect_prologue] = 0;
5252 data->cost[vect_body] = 0;
5253 data->cost[vect_epilogue] = 0;
5254 rs6000_vect_nonmem = false;
5258 /* Implement targetm.vectorize.add_stmt_cost. */
5261 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5262 struct _stmt_vec_info *stmt_info, int misalign,
5263 enum vect_cost_model_location where)
5265 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5266 unsigned retval = 0;
5268 if (flag_vect_cost_model)
5270 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5271 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5273 /* Statements in an inner loop relative to the loop being
5274 vectorized are weighted more heavily. The value here is
5275 arbitrary and could potentially be improved with analysis. */
5276 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5277 count *= 50; /* FIXME. */
5279 retval = (unsigned) (count * stmt_cost);
5280 cost_data->cost[where] += retval;
5282 /* Check whether we're doing something other than just a copy loop.
5283 Not all such loops may be profitably vectorized; see
5284 rs6000_finish_cost. */
5285 if ((kind == vec_to_scalar || kind == vec_perm
5286 || kind == vec_promote_demote || kind == vec_construct
5287 || kind == scalar_to_vec)
5288 || (where == vect_body && kind == vector_stmt))
5289 rs6000_vect_nonmem = true;
5295 /* Implement targetm.vectorize.finish_cost. */
5298 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5299 unsigned *body_cost, unsigned *epilogue_cost)
5301 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5303 if (cost_data->loop_info)
5304 rs6000_density_test (cost_data);
5306 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5307 that require versioning for any reason. The vectorization is at
5308 best a wash inside the loop, and the versioning checks make
5309 profitability highly unlikely and potentially quite harmful. */
5310 if (cost_data->loop_info)
5312 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5313 if (!rs6000_vect_nonmem
5314 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5315 && LOOP_REQUIRES_VERSIONING (vec_info))
5316 cost_data->cost[vect_body] += 10000;
5319 *prologue_cost = cost_data->cost[vect_prologue];
5320 *body_cost = cost_data->cost[vect_body];
5321 *epilogue_cost = cost_data->cost[vect_epilogue];
5324 /* Implement targetm.vectorize.destroy_cost_data. */
5327 rs6000_destroy_cost_data (void *data)
5332 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5333 library with vectorized intrinsics. */
5336 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5340 const char *suffix = NULL;
5341 tree fntype, new_fndecl, bdecl = NULL_TREE;
5344 machine_mode el_mode, in_mode;
5347 /* Libmass is suitable for unsafe math only as it does not correctly support
5348 parts of IEEE with the required precision such as denormals. Only support
5349 it if we have VSX to use the simd d2 or f4 functions.
5350 XXX: Add variable length support. */
5351 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5354 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5355 n = TYPE_VECTOR_SUBPARTS (type_out);
5356 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5357 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5358 if (el_mode != in_mode
5394 if (el_mode == DFmode && n == 2)
5396 bdecl = mathfn_built_in (double_type_node, fn);
5397 suffix = "d2"; /* pow -> powd2 */
5399 else if (el_mode == SFmode && n == 4)
5401 bdecl = mathfn_built_in (float_type_node, fn);
5402 suffix = "4"; /* powf -> powf4 */
5414 gcc_assert (suffix != NULL);
5415 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5419 strcpy (name, bname + sizeof ("__builtin_") - 1);
5420 strcat (name, suffix);
5423 fntype = build_function_type_list (type_out, type_in, NULL);
5424 else if (n_args == 2)
5425 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5429 /* Build a function declaration for the vectorized function. */
5430 new_fndecl = build_decl (BUILTINS_LOCATION,
5431 FUNCTION_DECL, get_identifier (name), fntype);
5432 TREE_PUBLIC (new_fndecl) = 1;
5433 DECL_EXTERNAL (new_fndecl) = 1;
5434 DECL_IS_NOVOPS (new_fndecl) = 1;
5435 TREE_READONLY (new_fndecl) = 1;
5440 /* Returns a function decl for a vectorized version of the builtin function
5441 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5442 if it is not available. */
5445 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5448 machine_mode in_mode, out_mode;
5451 if (TARGET_DEBUG_BUILTIN)
5452 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5453 combined_fn_name (combined_fn (fn)),
5454 GET_MODE_NAME (TYPE_MODE (type_out)),
5455 GET_MODE_NAME (TYPE_MODE (type_in)));
5457 if (TREE_CODE (type_out) != VECTOR_TYPE
5458 || TREE_CODE (type_in) != VECTOR_TYPE)
5461 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5462 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5463 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5464 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5469 if (VECTOR_UNIT_VSX_P (V2DFmode)
5470 && out_mode == DFmode && out_n == 2
5471 && in_mode == DFmode && in_n == 2)
5472 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5473 if (VECTOR_UNIT_VSX_P (V4SFmode)
5474 && out_mode == SFmode && out_n == 4
5475 && in_mode == SFmode && in_n == 4)
5476 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5477 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5478 && out_mode == SFmode && out_n == 4
5479 && in_mode == SFmode && in_n == 4)
5480 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5483 if (VECTOR_UNIT_VSX_P (V2DFmode)
5484 && out_mode == DFmode && out_n == 2
5485 && in_mode == DFmode && in_n == 2)
5486 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5487 if (VECTOR_UNIT_VSX_P (V4SFmode)
5488 && out_mode == SFmode && out_n == 4
5489 && in_mode == SFmode && in_n == 4)
5490 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5491 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5492 && out_mode == SFmode && out_n == 4
5493 && in_mode == SFmode && in_n == 4)
5494 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5497 if (VECTOR_UNIT_VSX_P (V2DFmode)
5498 && out_mode == DFmode && out_n == 2
5499 && in_mode == DFmode && in_n == 2)
5500 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5501 if (VECTOR_UNIT_VSX_P (V4SFmode)
5502 && out_mode == SFmode && out_n == 4
5503 && in_mode == SFmode && in_n == 4)
5504 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5505 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5506 && out_mode == SFmode && out_n == 4
5507 && in_mode == SFmode && in_n == 4)
5508 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5511 if (VECTOR_UNIT_VSX_P (V2DFmode)
5512 && out_mode == DFmode && out_n == 2
5513 && in_mode == DFmode && in_n == 2)
5514 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5515 if (VECTOR_UNIT_VSX_P (V4SFmode)
5516 && out_mode == SFmode && out_n == 4
5517 && in_mode == SFmode && in_n == 4)
5518 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5519 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5520 && out_mode == SFmode && out_n == 4
5521 && in_mode == SFmode && in_n == 4)
5522 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5525 if (VECTOR_UNIT_VSX_P (V2DFmode)
5526 && out_mode == DFmode && out_n == 2
5527 && in_mode == DFmode && in_n == 2)
5528 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5529 if (VECTOR_UNIT_VSX_P (V4SFmode)
5530 && out_mode == SFmode && out_n == 4
5531 && in_mode == SFmode && in_n == 4)
5532 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5533 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5534 && out_mode == SFmode && out_n == 4
5535 && in_mode == SFmode && in_n == 4)
5536 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5539 if (VECTOR_UNIT_VSX_P (V2DFmode)
5540 && flag_unsafe_math_optimizations
5541 && out_mode == DFmode && out_n == 2
5542 && in_mode == DFmode && in_n == 2)
5543 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5544 if (VECTOR_UNIT_VSX_P (V4SFmode)
5545 && flag_unsafe_math_optimizations
5546 && out_mode == SFmode && out_n == 4
5547 && in_mode == SFmode && in_n == 4)
5548 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5551 if (VECTOR_UNIT_VSX_P (V2DFmode)
5552 && !flag_trapping_math
5553 && out_mode == DFmode && out_n == 2
5554 && in_mode == DFmode && in_n == 2)
5555 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5556 if (VECTOR_UNIT_VSX_P (V4SFmode)
5557 && !flag_trapping_math
5558 && out_mode == SFmode && out_n == 4
5559 && in_mode == SFmode && in_n == 4)
5560 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5566 /* Generate calls to libmass if appropriate. */
5567 if (rs6000_veclib_handler)
5568 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5573 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5576 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5579 machine_mode in_mode, out_mode;
5582 if (TARGET_DEBUG_BUILTIN)
5583 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5584 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5585 GET_MODE_NAME (TYPE_MODE (type_out)),
5586 GET_MODE_NAME (TYPE_MODE (type_in)));
5588 if (TREE_CODE (type_out) != VECTOR_TYPE
5589 || TREE_CODE (type_in) != VECTOR_TYPE)
5592 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5593 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5594 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5595 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5597 enum rs6000_builtins fn
5598 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5601 case RS6000_BUILTIN_RSQRTF:
5602 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5603 && out_mode == SFmode && out_n == 4
5604 && in_mode == SFmode && in_n == 4)
5605 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5607 case RS6000_BUILTIN_RSQRT:
5608 if (VECTOR_UNIT_VSX_P (V2DFmode)
5609 && out_mode == DFmode && out_n == 2
5610 && in_mode == DFmode && in_n == 2)
5611 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5613 case RS6000_BUILTIN_RECIPF:
5614 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5615 && out_mode == SFmode && out_n == 4
5616 && in_mode == SFmode && in_n == 4)
5617 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5619 case RS6000_BUILTIN_RECIP:
5620 if (VECTOR_UNIT_VSX_P (V2DFmode)
5621 && out_mode == DFmode && out_n == 2
5622 && in_mode == DFmode && in_n == 2)
5623 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5631 /* Default CPU string for rs6000*_file_start functions. */
5632 static const char *rs6000_default_cpu;
5634 #ifdef USING_ELFOS_H
5635 static const char *rs6000_machine;
5638 rs6000_machine_from_flags (void)
5640 if ((rs6000_isa_flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER))
5643 if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
5645 if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
5647 if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
5649 if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
5651 if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
5653 if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0)
5655 if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5661 emit_asm_machine (void)
5663 fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
5667 /* Do anything needed at the start of the asm file. */
5670 rs6000_file_start (void)
5673 const char *start = buffer;
5674 FILE *file = asm_out_file;
5676 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5678 default_file_start ();
5680 if (flag_verbose_asm)
5682 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5684 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5686 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5690 if (global_options_set.x_rs6000_cpu_index)
5692 fprintf (file, "%s -mcpu=%s", start,
5693 processor_target_table[rs6000_cpu_index].name);
5697 if (global_options_set.x_rs6000_tune_index)
5699 fprintf (file, "%s -mtune=%s", start,
5700 processor_target_table[rs6000_tune_index].name);
5704 if (PPC405_ERRATUM77)
5706 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5710 #ifdef USING_ELFOS_H
5711 switch (rs6000_sdata)
5713 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5714 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5715 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5716 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5719 if (rs6000_sdata && g_switch_value)
5721 fprintf (file, "%s -G %d", start,
5731 #ifdef USING_ELFOS_H
5732 rs6000_machine = rs6000_machine_from_flags ();
5733 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5734 && !global_options_set.x_rs6000_cpu_index)
5735 emit_asm_machine ();
5738 if (DEFAULT_ABI == ABI_ELFv2)
5739 fprintf (file, "\t.abiversion 2\n");
5743 /* Return nonzero if this function is known to have a null epilogue. */
5746 direct_return (void)
5748 if (reload_completed)
5750 rs6000_stack_t *info = rs6000_stack_info ();
5752 if (info->first_gp_reg_save == 32
5753 && info->first_fp_reg_save == 64
5754 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5755 && ! info->lr_save_p
5756 && ! info->cr_save_p
5757 && info->vrsave_size == 0
5765 /* Helper for num_insns_constant. Calculate number of instructions to
5766 load VALUE to a single gpr using combinations of addi, addis, ori,
5767 oris and sldi instructions. */
5770 num_insns_constant_gpr (HOST_WIDE_INT value)
5772 /* signed constant loadable with addi */
5773 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5776 /* constant loadable with addis */
5777 else if ((value & 0xffff) == 0
5778 && (value >> 31 == -1 || value >> 31 == 0))
5781 else if (TARGET_POWERPC64)
5783 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5784 HOST_WIDE_INT high = value >> 31;
5786 if (high == 0 || high == -1)
5792 return num_insns_constant_gpr (high) + 1;
5794 return num_insns_constant_gpr (low) + 1;
5796 return (num_insns_constant_gpr (high)
5797 + num_insns_constant_gpr (low) + 1);
5804 /* Helper for num_insns_constant. Allow constants formed by the
5805 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5806 and handle modes that require multiple gprs. */
5809 num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
5811 int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5815 HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
5816 int insns = num_insns_constant_gpr (low);
5818 /* We won't get more than 2 from num_insns_constant_gpr
5819 except when TARGET_POWERPC64 and mode is DImode or
5820 wider, so the register mode must be DImode. */
5821 && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5824 value >>= BITS_PER_WORD;
5829 /* Return the number of instructions it takes to form a constant in as
5830 many gprs are needed for MODE. */
5833 num_insns_constant (rtx op, machine_mode mode)
5837 switch (GET_CODE (op))
5843 case CONST_WIDE_INT:
5846 for (int i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5847 insns += num_insns_constant_multi (CONST_WIDE_INT_ELT (op, i),
5854 const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
5856 if (mode == SFmode || mode == SDmode)
5861 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv, l);
5863 REAL_VALUE_TO_TARGET_SINGLE (*rv, l);
5864 /* See the first define_split in rs6000.md handling a
5865 const_double_operand. */
5869 else if (mode == DFmode || mode == DDmode)
5874 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv, l);
5876 REAL_VALUE_TO_TARGET_DOUBLE (*rv, l);
5878 /* See the second (32-bit) and third (64-bit) define_split
5879 in rs6000.md handling a const_double_operand. */
5880 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 1] << 32;
5881 val |= l[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffffUL;
5884 else if (mode == TFmode || mode == TDmode
5885 || mode == KFmode || mode == IFmode)
5891 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv, l);
5893 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv, l);
5895 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 3] << 32;
5896 val |= l[WORDS_BIG_ENDIAN ? 1 : 2] & 0xffffffffUL;
5897 insns = num_insns_constant_multi (val, DImode);
5898 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 2 : 1] << 32;
5899 val |= l[WORDS_BIG_ENDIAN ? 3 : 0] & 0xffffffffUL;
5900 insns += num_insns_constant_multi (val, DImode);
5912 return num_insns_constant_multi (val, mode);
5915 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5916 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5917 corresponding element of the vector, but for V4SFmode, the
5918 corresponding "float" is interpreted as an SImode integer. */
5921 const_vector_elt_as_int (rtx op, unsigned int elt)
5925 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5926 gcc_assert (GET_MODE (op) != V2DImode
5927 && GET_MODE (op) != V2DFmode);
5929 tmp = CONST_VECTOR_ELT (op, elt);
5930 if (GET_MODE (op) == V4SFmode)
5931 tmp = gen_lowpart (SImode, tmp);
5932 return INTVAL (tmp);
5935 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5936 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5937 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5938 all items are set to the same value and contain COPIES replicas of the
5939 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5940 operand and the others are set to the value of the operand's msb. */
5943 vspltis_constant (rtx op, unsigned step, unsigned copies)
5945 machine_mode mode = GET_MODE (op);
5946 machine_mode inner = GET_MODE_INNER (mode);
5954 HOST_WIDE_INT splat_val;
5955 HOST_WIDE_INT msb_val;
5957 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5960 nunits = GET_MODE_NUNITS (mode);
5961 bitsize = GET_MODE_BITSIZE (inner);
5962 mask = GET_MODE_MASK (inner);
5964 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5966 msb_val = val >= 0 ? 0 : -1;
5968 /* Construct the value to be splatted, if possible. If not, return 0. */
5969 for (i = 2; i <= copies; i *= 2)
5971 HOST_WIDE_INT small_val;
5973 small_val = splat_val >> bitsize;
5975 if (splat_val != ((HOST_WIDE_INT)
5976 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5977 | (small_val & mask)))
5979 splat_val = small_val;
5982 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5983 if (EASY_VECTOR_15 (splat_val))
5986 /* Also check if we can splat, and then add the result to itself. Do so if
5987 the value is positive, of if the splat instruction is using OP's mode;
5988 for splat_val < 0, the splat and the add should use the same mode. */
5989 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
5990 && (splat_val >= 0 || (step == 1 && copies == 1)))
5993 /* Also check if are loading up the most significant bit which can be done by
5994 loading up -1 and shifting the value left by -1. */
5995 else if (EASY_VECTOR_MSB (splat_val, inner))
6001 /* Check if VAL is present in every STEP-th element, and the
6002 other elements are filled with its most significant bit. */
6003 for (i = 1; i < nunits; ++i)
6005 HOST_WIDE_INT desired_val;
6006 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6007 if ((i & (step - 1)) == 0)
6010 desired_val = msb_val;
6012 if (desired_val != const_vector_elt_as_int (op, elt))
6019 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6020 instruction, filling in the bottom elements with 0 or -1.
6022 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6023 for the number of zeroes to shift in, or negative for the number of 0xff
6026 OP is a CONST_VECTOR. */
6029 vspltis_shifted (rtx op)
6031 machine_mode mode = GET_MODE (op);
6032 machine_mode inner = GET_MODE_INNER (mode);
6040 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6043 /* We need to create pseudo registers to do the shift, so don't recognize
6044 shift vector constants after reload. */
6045 if (!can_create_pseudo_p ())
6048 nunits = GET_MODE_NUNITS (mode);
6049 mask = GET_MODE_MASK (inner);
6051 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6053 /* Check if the value can really be the operand of a vspltis[bhw]. */
6054 if (EASY_VECTOR_15 (val))
6057 /* Also check if we are loading up the most significant bit which can be done
6058 by loading up -1 and shifting the value left by -1. */
6059 else if (EASY_VECTOR_MSB (val, inner))
6065 /* Check if VAL is present in every STEP-th element until we find elements
6066 that are 0 or all 1 bits. */
6067 for (i = 1; i < nunits; ++i)
6069 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6070 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6072 /* If the value isn't the splat value, check for the remaining elements
6078 for (j = i+1; j < nunits; ++j)
6080 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6081 if (const_vector_elt_as_int (op, elt2) != 0)
6085 return (nunits - i) * GET_MODE_SIZE (inner);
6088 else if ((elt_val & mask) == mask)
6090 for (j = i+1; j < nunits; ++j)
6092 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6093 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6097 return -((nunits - i) * GET_MODE_SIZE (inner));
6105 /* If all elements are equal, we don't need to do VLSDOI. */
6110 /* Return true if OP is of the given MODE and can be synthesized
6111 with a vspltisb, vspltish or vspltisw. */
6114 easy_altivec_constant (rtx op, machine_mode mode)
6116 unsigned step, copies;
6118 if (mode == VOIDmode)
6119 mode = GET_MODE (op);
6120 else if (mode != GET_MODE (op))
6123 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6125 if (mode == V2DFmode)
6126 return zero_constant (op, mode);
6128 else if (mode == V2DImode)
6130 if (!CONST_INT_P (CONST_VECTOR_ELT (op, 0))
6131 || !CONST_INT_P (CONST_VECTOR_ELT (op, 1)))
6134 if (zero_constant (op, mode))
6137 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6138 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6144 /* V1TImode is a special container for TImode. Ignore for now. */
6145 else if (mode == V1TImode)
6148 /* Start with a vspltisw. */
6149 step = GET_MODE_NUNITS (mode) / 4;
6152 if (vspltis_constant (op, step, copies))
6155 /* Then try with a vspltish. */
6161 if (vspltis_constant (op, step, copies))
6164 /* And finally a vspltisb. */
6170 if (vspltis_constant (op, step, copies))
6173 if (vspltis_shifted (op) != 0)
6179 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6180 result is OP. Abort if it is not possible. */
6183 gen_easy_altivec_constant (rtx op)
6185 machine_mode mode = GET_MODE (op);
6186 int nunits = GET_MODE_NUNITS (mode);
6187 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6188 unsigned step = nunits / 4;
6189 unsigned copies = 1;
6191 /* Start with a vspltisw. */
6192 if (vspltis_constant (op, step, copies))
6193 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6195 /* Then try with a vspltish. */
6201 if (vspltis_constant (op, step, copies))
6202 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6204 /* And finally a vspltisb. */
6210 if (vspltis_constant (op, step, copies))
6211 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6216 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6217 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6219 Return the number of instructions needed (1 or 2) into the address pointed
6222 Return the constant that is being split via CONSTANT_PTR. */
6225 xxspltib_constant_p (rtx op,
6230 size_t nunits = GET_MODE_NUNITS (mode);
6232 HOST_WIDE_INT value;
6235 /* Set the returned values to out of bound values. */
6236 *num_insns_ptr = -1;
6237 *constant_ptr = 256;
6239 if (!TARGET_P9_VECTOR)
6242 if (mode == VOIDmode)
6243 mode = GET_MODE (op);
6245 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6248 /* Handle (vec_duplicate <constant>). */
6249 if (GET_CODE (op) == VEC_DUPLICATE)
6251 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6252 && mode != V2DImode)
6255 element = XEXP (op, 0);
6256 if (!CONST_INT_P (element))
6259 value = INTVAL (element);
6260 if (!IN_RANGE (value, -128, 127))
6264 /* Handle (const_vector [...]). */
6265 else if (GET_CODE (op) == CONST_VECTOR)
6267 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6268 && mode != V2DImode)
6271 element = CONST_VECTOR_ELT (op, 0);
6272 if (!CONST_INT_P (element))
6275 value = INTVAL (element);
6276 if (!IN_RANGE (value, -128, 127))
6279 for (i = 1; i < nunits; i++)
6281 element = CONST_VECTOR_ELT (op, i);
6282 if (!CONST_INT_P (element))
6285 if (value != INTVAL (element))
6290 /* Handle integer constants being loaded into the upper part of the VSX
6291 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6292 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6293 else if (CONST_INT_P (op))
6295 if (!SCALAR_INT_MODE_P (mode))
6298 value = INTVAL (op);
6299 if (!IN_RANGE (value, -128, 127))
6302 if (!IN_RANGE (value, -1, 0))
6304 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6307 if (EASY_VECTOR_15 (value))
6315 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6316 sign extend. Special case 0/-1 to allow getting any VSX register instead
6317 of an Altivec register. */
6318 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6319 && EASY_VECTOR_15 (value))
6322 /* Return # of instructions and the constant byte for XXSPLTIB. */
6323 if (mode == V16QImode)
6326 else if (IN_RANGE (value, -1, 0))
6332 *constant_ptr = (int) value;
6337 output_vec_const_move (rtx *operands)
6345 mode = GET_MODE (dest);
6349 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6350 int xxspltib_value = 256;
6353 if (zero_constant (vec, mode))
6355 if (TARGET_P9_VECTOR)
6356 return "xxspltib %x0,0";
6358 else if (dest_vmx_p)
6359 return "vspltisw %0,0";
6362 return "xxlxor %x0,%x0,%x0";
6365 if (all_ones_constant (vec, mode))
6367 if (TARGET_P9_VECTOR)
6368 return "xxspltib %x0,255";
6370 else if (dest_vmx_p)
6371 return "vspltisw %0,-1";
6373 else if (TARGET_P8_VECTOR)
6374 return "xxlorc %x0,%x0,%x0";
6380 if (TARGET_P9_VECTOR
6381 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6385 operands[2] = GEN_INT (xxspltib_value & 0xff);
6386 return "xxspltib %x0,%2";
6397 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6398 if (zero_constant (vec, mode))
6399 return "vspltisw %0,0";
6401 if (all_ones_constant (vec, mode))
6402 return "vspltisw %0,-1";
6404 /* Do we need to construct a value using VSLDOI? */
6405 shift = vspltis_shifted (vec);
6409 splat_vec = gen_easy_altivec_constant (vec);
6410 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6411 operands[1] = XEXP (splat_vec, 0);
6412 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6415 switch (GET_MODE (splat_vec))
6418 return "vspltisw %0,%1";
6421 return "vspltish %0,%1";
6424 return "vspltisb %0,%1";
6434 /* Initialize vector TARGET to VALS. */
6437 rs6000_expand_vector_init (rtx target, rtx vals)
6439 machine_mode mode = GET_MODE (target);
6440 machine_mode inner_mode = GET_MODE_INNER (mode);
6441 int n_elts = GET_MODE_NUNITS (mode);
6442 int n_var = 0, one_var = -1;
6443 bool all_same = true, all_const_zero = true;
6447 for (i = 0; i < n_elts; ++i)
6449 x = XVECEXP (vals, 0, i);
6450 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6451 ++n_var, one_var = i;
6452 else if (x != CONST0_RTX (inner_mode))
6453 all_const_zero = false;
6455 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6461 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6462 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6463 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6465 /* Zero register. */
6466 emit_move_insn (target, CONST0_RTX (mode));
6469 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6471 /* Splat immediate. */
6472 emit_insn (gen_rtx_SET (target, const_vec));
6477 /* Load from constant pool. */
6478 emit_move_insn (target, const_vec);
6483 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6484 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6488 size_t num_elements = all_same ? 1 : 2;
6489 for (i = 0; i < num_elements; i++)
6491 op[i] = XVECEXP (vals, 0, i);
6492 /* Just in case there is a SUBREG with a smaller mode, do a
6494 if (GET_MODE (op[i]) != inner_mode)
6496 rtx tmp = gen_reg_rtx (inner_mode);
6497 convert_move (tmp, op[i], 0);
6500 /* Allow load with splat double word. */
6501 else if (MEM_P (op[i]))
6504 op[i] = force_reg (inner_mode, op[i]);
6506 else if (!REG_P (op[i]))
6507 op[i] = force_reg (inner_mode, op[i]);
6512 if (mode == V2DFmode)
6513 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6515 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6519 if (mode == V2DFmode)
6520 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6522 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6527 /* Special case initializing vector int if we are on 64-bit systems with
6528 direct move or we have the ISA 3.0 instructions. */
6529 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6530 && TARGET_DIRECT_MOVE_64BIT)
6534 rtx element0 = XVECEXP (vals, 0, 0);
6535 if (MEM_P (element0))
6536 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6538 element0 = force_reg (SImode, element0);
6540 if (TARGET_P9_VECTOR)
6541 emit_insn (gen_vsx_splat_v4si (target, element0));
6544 rtx tmp = gen_reg_rtx (DImode);
6545 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6546 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6555 for (i = 0; i < 4; i++)
6556 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6558 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6559 elements[2], elements[3]));
6564 /* With single precision floating point on VSX, know that internally single
6565 precision is actually represented as a double, and either make 2 V2DF
6566 vectors, and convert these vectors to single precision, or do one
6567 conversion, and splat the result to the other elements. */
6568 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6572 rtx element0 = XVECEXP (vals, 0, 0);
6574 if (TARGET_P9_VECTOR)
6576 if (MEM_P (element0))
6577 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6579 emit_insn (gen_vsx_splat_v4sf (target, element0));
6584 rtx freg = gen_reg_rtx (V4SFmode);
6585 rtx sreg = force_reg (SFmode, element0);
6586 rtx cvt = (TARGET_XSCVDPSPN
6587 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6588 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6591 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6597 rtx dbl_even = gen_reg_rtx (V2DFmode);
6598 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6599 rtx flt_even = gen_reg_rtx (V4SFmode);
6600 rtx flt_odd = gen_reg_rtx (V4SFmode);
6601 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6602 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6603 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6604 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6606 /* Use VMRGEW if we can instead of doing a permute. */
6607 if (TARGET_P8_VECTOR)
6609 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6610 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6611 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6612 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6613 if (BYTES_BIG_ENDIAN)
6614 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6616 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6620 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6621 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6622 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6623 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6624 rs6000_expand_extract_even (target, flt_even, flt_odd);
6630 /* Special case initializing vector short/char that are splats if we are on
6631 64-bit systems with direct move. */
6632 if (all_same && TARGET_DIRECT_MOVE_64BIT
6633 && (mode == V16QImode || mode == V8HImode))
6635 rtx op0 = XVECEXP (vals, 0, 0);
6636 rtx di_tmp = gen_reg_rtx (DImode);
6639 op0 = force_reg (GET_MODE_INNER (mode), op0);
6641 if (mode == V16QImode)
6643 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6644 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6648 if (mode == V8HImode)
6650 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6651 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6656 /* Store value to stack temp. Load vector element. Splat. However, splat
6657 of 64-bit items is not supported on Altivec. */
6658 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6660 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6661 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6662 XVECEXP (vals, 0, 0));
6663 x = gen_rtx_UNSPEC (VOIDmode,
6664 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6665 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6667 gen_rtx_SET (target, mem),
6669 x = gen_rtx_VEC_SELECT (inner_mode, target,
6670 gen_rtx_PARALLEL (VOIDmode,
6671 gen_rtvec (1, const0_rtx)));
6672 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6676 /* One field is non-constant. Load constant then overwrite
6680 rtx copy = copy_rtx (vals);
6682 /* Load constant part of vector, substitute neighboring value for
6684 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6685 rs6000_expand_vector_init (target, copy);
6687 /* Insert variable. */
6688 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6692 /* Construct the vector in memory one field at a time
6693 and load the whole vector. */
6694 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6695 for (i = 0; i < n_elts; i++)
6696 emit_move_insn (adjust_address_nv (mem, inner_mode,
6697 i * GET_MODE_SIZE (inner_mode)),
6698 XVECEXP (vals, 0, i));
6699 emit_move_insn (target, mem);
6702 /* Set field ELT of TARGET to VAL. */
6705 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6707 machine_mode mode = GET_MODE (target);
6708 machine_mode inner_mode = GET_MODE_INNER (mode);
6709 rtx reg = gen_reg_rtx (mode);
6711 int width = GET_MODE_SIZE (inner_mode);
6714 val = force_reg (GET_MODE (val), val);
6716 if (VECTOR_MEM_VSX_P (mode))
6718 rtx insn = NULL_RTX;
6719 rtx elt_rtx = GEN_INT (elt);
6721 if (mode == V2DFmode)
6722 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6724 else if (mode == V2DImode)
6725 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6727 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6729 if (mode == V4SImode)
6730 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6731 else if (mode == V8HImode)
6732 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6733 else if (mode == V16QImode)
6734 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6735 else if (mode == V4SFmode)
6736 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6746 /* Simplify setting single element vectors like V1TImode. */
6747 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6749 emit_move_insn (target, gen_lowpart (mode, val));
6753 /* Load single variable value. */
6754 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6755 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6756 x = gen_rtx_UNSPEC (VOIDmode,
6757 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6758 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6760 gen_rtx_SET (reg, mem),
6763 /* Linear sequence. */
6764 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6765 for (i = 0; i < 16; ++i)
6766 XVECEXP (mask, 0, i) = GEN_INT (i);
6768 /* Set permute mask to insert element into target. */
6769 for (i = 0; i < width; ++i)
6770 XVECEXP (mask, 0, elt*width + i)
6771 = GEN_INT (i + 0x10);
6772 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6774 if (BYTES_BIG_ENDIAN)
6775 x = gen_rtx_UNSPEC (mode,
6776 gen_rtvec (3, target, reg,
6777 force_reg (V16QImode, x)),
6781 if (TARGET_P9_VECTOR)
6782 x = gen_rtx_UNSPEC (mode,
6783 gen_rtvec (3, reg, target,
6784 force_reg (V16QImode, x)),
6788 /* Invert selector. We prefer to generate VNAND on P8 so
6789 that future fusion opportunities can kick in, but must
6790 generate VNOR elsewhere. */
6791 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6792 rtx iorx = (TARGET_P8_VECTOR
6793 ? gen_rtx_IOR (V16QImode, notx, notx)
6794 : gen_rtx_AND (V16QImode, notx, notx));
6795 rtx tmp = gen_reg_rtx (V16QImode);
6796 emit_insn (gen_rtx_SET (tmp, iorx));
6798 /* Permute with operands reversed and adjusted selector. */
6799 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6804 emit_insn (gen_rtx_SET (target, x));
6807 /* Extract field ELT from VEC into TARGET. */
6810 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6812 machine_mode mode = GET_MODE (vec);
6813 machine_mode inner_mode = GET_MODE_INNER (mode);
6816 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6823 emit_move_insn (target, gen_lowpart (TImode, vec));
6826 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6829 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6832 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6835 if (TARGET_DIRECT_MOVE_64BIT)
6837 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6843 if (TARGET_DIRECT_MOVE_64BIT)
6845 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6851 if (TARGET_DIRECT_MOVE_64BIT)
6853 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6859 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6860 && TARGET_DIRECT_MOVE_64BIT)
6862 if (GET_MODE (elt) != DImode)
6864 rtx tmp = gen_reg_rtx (DImode);
6865 convert_move (tmp, elt, 0);
6868 else if (!REG_P (elt))
6869 elt = force_reg (DImode, elt);
6874 emit_move_insn (target, gen_lowpart (TImode, vec));
6878 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6882 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6886 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6890 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6894 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6898 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6906 /* Allocate mode-sized buffer. */
6907 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6909 emit_move_insn (mem, vec);
6910 if (CONST_INT_P (elt))
6912 int modulo_elt = INTVAL (elt) % GET_MODE_NUNITS (mode);
6914 /* Add offset to field within buffer matching vector element. */
6915 mem = adjust_address_nv (mem, inner_mode,
6916 modulo_elt * GET_MODE_SIZE (inner_mode));
6917 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6921 unsigned int ele_size = GET_MODE_SIZE (inner_mode);
6922 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
6923 rtx new_addr = gen_reg_rtx (Pmode);
6925 elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
6927 elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
6928 new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
6929 new_addr = change_address (mem, inner_mode, new_addr);
6930 emit_move_insn (target, new_addr);
6934 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6935 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6936 temporary (BASE_TMP) to fixup the address. Return the new memory address
6937 that is valid for reads or writes to a given register (SCALAR_REG). */
6940 rs6000_adjust_vec_address (rtx scalar_reg,
6944 machine_mode scalar_mode)
6946 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6947 rtx addr = XEXP (mem, 0);
6952 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6953 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6955 /* Calculate what we need to add to the address to get the element
6957 if (CONST_INT_P (element))
6958 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6961 int byte_shift = exact_log2 (scalar_size);
6962 gcc_assert (byte_shift >= 0);
6964 if (byte_shift == 0)
6965 element_offset = element;
6969 if (TARGET_POWERPC64)
6970 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6972 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6974 element_offset = base_tmp;
6978 /* Create the new address pointing to the element within the vector. If we
6979 are adding 0, we don't have to change the address. */
6980 if (element_offset == const0_rtx)
6983 /* A simple indirect address can be converted into a reg + offset
6985 else if (REG_P (addr) || SUBREG_P (addr))
6986 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
6988 /* Optimize D-FORM addresses with constant offset with a constant element, to
6989 include the element offset in the address directly. */
6990 else if (GET_CODE (addr) == PLUS)
6992 rtx op0 = XEXP (addr, 0);
6993 rtx op1 = XEXP (addr, 1);
6996 gcc_assert (REG_P (op0) || SUBREG_P (op0));
6997 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
6999 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7000 rtx offset_rtx = GEN_INT (offset);
7002 if (IN_RANGE (offset, -32768, 32767)
7003 && (scalar_size < 8 || (offset & 0x3) == 0))
7004 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7007 emit_move_insn (base_tmp, offset_rtx);
7008 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7013 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7014 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7016 /* Note, ADDI requires the register being added to be a base
7017 register. If the register was R0, load it up into the temporary
7020 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7022 insn = gen_add3_insn (base_tmp, op1, element_offset);
7023 gcc_assert (insn != NULL_RTX);
7028 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7030 insn = gen_add3_insn (base_tmp, element_offset, op1);
7031 gcc_assert (insn != NULL_RTX);
7037 emit_move_insn (base_tmp, op1);
7038 emit_insn (gen_add2_insn (base_tmp, element_offset));
7041 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7047 emit_move_insn (base_tmp, addr);
7048 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7051 /* If we have a PLUS, we need to see whether the particular register class
7052 allows for D-FORM or X-FORM addressing. */
7053 if (GET_CODE (new_addr) == PLUS)
7055 rtx op1 = XEXP (new_addr, 1);
7056 addr_mask_type addr_mask;
7057 unsigned int scalar_regno = reg_or_subregno (scalar_reg);
7059 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
7060 if (INT_REGNO_P (scalar_regno))
7061 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7063 else if (FP_REGNO_P (scalar_regno))
7064 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7066 else if (ALTIVEC_REGNO_P (scalar_regno))
7067 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7072 if (REG_P (op1) || SUBREG_P (op1))
7073 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7075 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7078 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7079 valid_addr_p = true;
7082 valid_addr_p = false;
7086 emit_move_insn (base_tmp, new_addr);
7087 new_addr = base_tmp;
7090 return change_address (mem, scalar_mode, new_addr);
7093 /* Split a variable vec_extract operation into the component instructions. */
7096 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7099 machine_mode mode = GET_MODE (src);
7100 machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src));
7101 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7102 int byte_shift = exact_log2 (scalar_size);
7104 gcc_assert (byte_shift >= 0);
7106 /* If we are given a memory address, optimize to load just the element. We
7107 don't have to adjust the vector element number on little endian
7111 int num_elements = GET_MODE_NUNITS (mode);
7112 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7114 emit_insn (gen_anddi3 (element, element, num_ele_m1));
7115 gcc_assert (REG_P (tmp_gpr));
7116 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7117 tmp_gpr, scalar_mode));
7121 else if (REG_P (src) || SUBREG_P (src))
7123 int num_elements = GET_MODE_NUNITS (mode);
7124 int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
7125 int bit_shift = 7 - exact_log2 (num_elements);
7127 unsigned int dest_regno = reg_or_subregno (dest);
7128 unsigned int src_regno = reg_or_subregno (src);
7129 unsigned int element_regno = reg_or_subregno (element);
7131 gcc_assert (REG_P (tmp_gpr));
7133 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7134 a general purpose register. */
7135 if (TARGET_P9_VECTOR
7136 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7137 && INT_REGNO_P (dest_regno)
7138 && ALTIVEC_REGNO_P (src_regno)
7139 && INT_REGNO_P (element_regno))
7141 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7142 rtx element_si = gen_rtx_REG (SImode, element_regno);
7144 if (mode == V16QImode)
7145 emit_insn (BYTES_BIG_ENDIAN
7146 ? gen_vextublx (dest_si, element_si, src)
7147 : gen_vextubrx (dest_si, element_si, src));
7149 else if (mode == V8HImode)
7151 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7152 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7153 emit_insn (BYTES_BIG_ENDIAN
7154 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7155 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7161 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7162 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7163 emit_insn (BYTES_BIG_ENDIAN
7164 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7165 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7172 gcc_assert (REG_P (tmp_altivec));
7174 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7175 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7176 will shift the element into the upper position (adding 3 to convert a
7177 byte shift into a bit shift). */
7178 if (scalar_size == 8)
7180 if (!BYTES_BIG_ENDIAN)
7182 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7188 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7190 emit_insn (gen_rtx_SET (tmp_gpr,
7191 gen_rtx_AND (DImode,
7192 gen_rtx_ASHIFT (DImode,
7199 if (!BYTES_BIG_ENDIAN)
7201 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7203 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7204 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7210 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7213 /* Get the value into the lower byte of the Altivec register where VSLO
7215 if (TARGET_P9_VECTOR)
7216 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7217 else if (can_create_pseudo_p ())
7218 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7221 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7222 emit_move_insn (tmp_di, tmp_gpr);
7223 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7226 /* Do the VSLO to get the value into the final location. */
7230 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7234 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7239 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7240 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7241 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7242 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7245 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7253 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7254 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7255 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7256 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7258 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7259 emit_insn (gen_lshrdi3 (tmp_gpr_di, tmp_gpr_di,
7260 GEN_INT (64 - bits_in_element)));
7274 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7275 selects whether the alignment is abi mandated, optional, or
7276 both abi and optional alignment. */
7279 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7281 if (how != align_opt)
7283 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7287 if (how != align_abi)
7289 if (TREE_CODE (type) == ARRAY_TYPE
7290 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7292 if (align < BITS_PER_WORD)
7293 align = BITS_PER_WORD;
7300 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7301 instructions simply ignore the low bits; VSX memory instructions
7302 are aligned to 4 or 8 bytes. */
7305 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7307 return (STRICT_ALIGNMENT
7308 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7309 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7310 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7311 && (int) align < VECTOR_ALIGN (mode)))));
7314 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7317 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7319 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7321 if (computed != 128)
7324 if (!warned && warn_psabi)
7327 inform (input_location,
7328 "the layout of aggregates containing vectors with"
7329 " %d-byte alignment has changed in GCC 5",
7330 computed / BITS_PER_UNIT);
7333 /* In current GCC there is no special case. */
7340 /* AIX increases natural record alignment to doubleword if the first
7341 field is an FP double while the FP fields remain word aligned. */
7344 rs6000_special_round_type_align (tree type, unsigned int computed,
7345 unsigned int specified)
7347 unsigned int align = MAX (computed, specified);
7348 tree field = TYPE_FIELDS (type);
7350 /* Skip all non field decls */
7351 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7352 field = DECL_CHAIN (field);
7354 if (field != NULL && field != type)
7356 type = TREE_TYPE (field);
7357 while (TREE_CODE (type) == ARRAY_TYPE)
7358 type = TREE_TYPE (type);
7360 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7361 align = MAX (align, 64);
7367 /* Darwin increases record alignment to the natural alignment of
7371 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7372 unsigned int specified)
7374 unsigned int align = MAX (computed, specified);
7376 if (TYPE_PACKED (type))
7379 /* Find the first field, looking down into aggregates. */
7381 tree field = TYPE_FIELDS (type);
7382 /* Skip all non field decls */
7383 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7384 field = DECL_CHAIN (field);
7387 /* A packed field does not contribute any extra alignment. */
7388 if (DECL_PACKED (field))
7390 type = TREE_TYPE (field);
7391 while (TREE_CODE (type) == ARRAY_TYPE)
7392 type = TREE_TYPE (type);
7393 } while (AGGREGATE_TYPE_P (type));
7395 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7396 align = MAX (align, TYPE_ALIGN (type));
7401 /* Return 1 for an operand in small memory on V.4/eabi. */
7404 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7405 machine_mode mode ATTRIBUTE_UNUSED)
7410 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7413 if (DEFAULT_ABI != ABI_V4)
7416 if (SYMBOL_REF_P (op))
7419 else if (GET_CODE (op) != CONST
7420 || GET_CODE (XEXP (op, 0)) != PLUS
7421 || !SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
7422 || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
7427 rtx sum = XEXP (op, 0);
7428 HOST_WIDE_INT summand;
7430 /* We have to be careful here, because it is the referenced address
7431 that must be 32k from _SDA_BASE_, not just the symbol. */
7432 summand = INTVAL (XEXP (sum, 1));
7433 if (summand < 0 || summand > g_switch_value)
7436 sym_ref = XEXP (sum, 0);
7439 return SYMBOL_REF_SMALL_P (sym_ref);
7445 /* Return true if either operand is a general purpose register. */
7448 gpr_or_gpr_p (rtx op0, rtx op1)
7450 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7451 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7454 /* Return true if this is a move direct operation between GPR registers and
7455 floating point/VSX registers. */
7458 direct_move_p (rtx op0, rtx op1)
7460 if (!REG_P (op0) || !REG_P (op1))
7463 if (!TARGET_DIRECT_MOVE)
7466 int regno0 = REGNO (op0);
7467 int regno1 = REGNO (op1);
7468 if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
7471 if (INT_REGNO_P (regno0) && VSX_REGNO_P (regno1))
7474 if (VSX_REGNO_P (regno0) && INT_REGNO_P (regno1))
7480 /* Return true if the OFFSET is valid for the quad address instructions that
7481 use d-form (register + offset) addressing. */
7484 quad_address_offset_p (HOST_WIDE_INT offset)
7486 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7489 /* Return true if the ADDR is an acceptable address for a quad memory
7490 operation of mode MODE (either LQ/STQ for general purpose registers, or
7491 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7492 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7493 3.0 LXV/STXV instruction. */
7496 quad_address_p (rtx addr, machine_mode mode, bool strict)
7500 if (GET_MODE_SIZE (mode) != 16)
7503 if (legitimate_indirect_address_p (addr, strict))
7506 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7509 if (GET_CODE (addr) != PLUS)
7512 op0 = XEXP (addr, 0);
7513 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7516 op1 = XEXP (addr, 1);
7517 if (!CONST_INT_P (op1))
7520 return quad_address_offset_p (INTVAL (op1));
7523 /* Return true if this is a load or store quad operation. This function does
7524 not handle the atomic quad memory instructions. */
7527 quad_load_store_p (rtx op0, rtx op1)
7531 if (!TARGET_QUAD_MEMORY)
7534 else if (REG_P (op0) && MEM_P (op1))
7535 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7536 && quad_memory_operand (op1, GET_MODE (op1))
7537 && !reg_overlap_mentioned_p (op0, op1));
7539 else if (MEM_P (op0) && REG_P (op1))
7540 ret = (quad_memory_operand (op0, GET_MODE (op0))
7541 && quad_int_reg_operand (op1, GET_MODE (op1)));
7546 if (TARGET_DEBUG_ADDR)
7548 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7549 ret ? "true" : "false");
7550 debug_rtx (gen_rtx_SET (op0, op1));
7556 /* Given an address, return a constant offset term if one exists. */
7559 address_offset (rtx op)
7561 if (GET_CODE (op) == PRE_INC
7562 || GET_CODE (op) == PRE_DEC)
7564 else if (GET_CODE (op) == PRE_MODIFY
7565 || GET_CODE (op) == LO_SUM)
7568 if (GET_CODE (op) == CONST)
7571 if (GET_CODE (op) == PLUS)
7574 if (CONST_INT_P (op))
7580 /* Return true if the MEM operand is a memory operand suitable for use
7581 with a (full width, possibly multiple) gpr load/store. On
7582 powerpc64 this means the offset must be divisible by 4.
7583 Implements 'Y' constraint.
7585 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7586 a constraint function we know the operand has satisfied a suitable
7589 Offsetting a lo_sum should not be allowed, except where we know by
7590 alignment that a 32k boundary is not crossed. Note that by
7591 "offsetting" here we mean a further offset to access parts of the
7592 MEM. It's fine to have a lo_sum where the inner address is offset
7593 from a sym, since the same sym+offset will appear in the high part
7594 of the address calculation. */
7597 mem_operand_gpr (rtx op, machine_mode mode)
7599 unsigned HOST_WIDE_INT offset;
7601 rtx addr = XEXP (op, 0);
7603 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7605 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7606 && mode_supports_pre_incdec_p (mode)
7607 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7610 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7611 if (!rs6000_offsettable_memref_p (op, mode, false))
7614 op = address_offset (addr);
7618 offset = INTVAL (op);
7619 if (TARGET_POWERPC64 && (offset & 3) != 0)
7622 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7626 if (GET_CODE (addr) == LO_SUM)
7627 /* For lo_sum addresses, we must allow any offset except one that
7628 causes a wrap, so test only the low 16 bits. */
7629 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7631 return offset + 0x8000 < 0x10000u - extra;
7634 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7635 enforce an offset divisible by 4 even for 32-bit. */
7638 mem_operand_ds_form (rtx op, machine_mode mode)
7640 unsigned HOST_WIDE_INT offset;
7642 rtx addr = XEXP (op, 0);
7644 if (!offsettable_address_p (false, mode, addr))
7647 op = address_offset (addr);
7651 offset = INTVAL (op);
7652 if ((offset & 3) != 0)
7655 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7659 if (GET_CODE (addr) == LO_SUM)
7660 /* For lo_sum addresses, we must allow any offset except one that
7661 causes a wrap, so test only the low 16 bits. */
7662 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7664 return offset + 0x8000 < 0x10000u - extra;
7667 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7670 reg_offset_addressing_ok_p (machine_mode mode)
7684 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7685 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7686 a vector mode, if we want to use the VSX registers to move it around,
7687 we need to restrict ourselves to reg+reg addressing. Similarly for
7688 IEEE 128-bit floating point that is passed in a single vector
7690 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7691 return mode_supports_dq_form (mode);
7695 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7696 addressing for the LFIWZX and STFIWX instructions. */
7697 if (TARGET_NO_SDMODE_STACK)
7709 virtual_stack_registers_memory_p (rtx op)
7714 regnum = REGNO (op);
7716 else if (GET_CODE (op) == PLUS
7717 && REG_P (XEXP (op, 0))
7718 && CONST_INT_P (XEXP (op, 1)))
7719 regnum = REGNO (XEXP (op, 0));
7724 return (regnum >= FIRST_VIRTUAL_REGISTER
7725 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7728 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7729 is known to not straddle a 32k boundary. This function is used
7730 to determine whether -mcmodel=medium code can use TOC pointer
7731 relative addressing for OP. This means the alignment of the TOC
7732 pointer must also be taken into account, and unfortunately that is
7735 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7736 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7740 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7744 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7746 if (!SYMBOL_REF_P (op))
7749 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7751 if (mode_supports_dq_form (mode))
7754 dsize = GET_MODE_SIZE (mode);
7755 decl = SYMBOL_REF_DECL (op);
7761 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7762 replacing memory addresses with an anchor plus offset. We
7763 could find the decl by rummaging around in the block->objects
7764 VEC for the given offset but that seems like too much work. */
7765 dalign = BITS_PER_UNIT;
7766 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7767 && SYMBOL_REF_ANCHOR_P (op)
7768 && SYMBOL_REF_BLOCK (op) != NULL)
7770 struct object_block *block = SYMBOL_REF_BLOCK (op);
7772 dalign = block->alignment;
7773 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7775 else if (CONSTANT_POOL_ADDRESS_P (op))
7777 /* It would be nice to have get_pool_align().. */
7778 machine_mode cmode = get_pool_mode (op);
7780 dalign = GET_MODE_ALIGNMENT (cmode);
7783 else if (DECL_P (decl))
7785 dalign = DECL_ALIGN (decl);
7789 /* Allow BLKmode when the entire object is known to not
7790 cross a 32k boundary. */
7791 if (!DECL_SIZE_UNIT (decl))
7794 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7797 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7801 dalign /= BITS_PER_UNIT;
7802 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7803 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7804 return dalign >= dsize;
7810 /* Find how many bits of the alignment we know for this access. */
7811 dalign /= BITS_PER_UNIT;
7812 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7813 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7815 lsb = offset & -offset;
7819 return dalign >= dsize;
7823 constant_pool_expr_p (rtx op)
7827 split_const (op, &base, &offset);
7828 return (SYMBOL_REF_P (base)
7829 && CONSTANT_POOL_ADDRESS_P (base)
7830 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7833 /* These are only used to pass through from print_operand/print_operand_address
7834 to rs6000_output_addr_const_extra over the intervening function
7835 output_addr_const which is not target code. */
7836 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7838 /* Return true if OP is a toc pointer relative address (the output
7839 of create_TOC_reference). If STRICT, do not match non-split
7840 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7841 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7842 TOCREL_OFFSET_RET respectively. */
7845 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7846 const_rtx *tocrel_offset_ret)
7851 if (TARGET_CMODEL != CMODEL_SMALL)
7853 /* When strict ensure we have everything tidy. */
7855 && !(GET_CODE (op) == LO_SUM
7856 && REG_P (XEXP (op, 0))
7857 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7860 /* When not strict, allow non-split TOC addresses and also allow
7861 (lo_sum (high ..)) TOC addresses created during reload. */
7862 if (GET_CODE (op) == LO_SUM)
7866 const_rtx tocrel_base = op;
7867 const_rtx tocrel_offset = const0_rtx;
7869 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7871 tocrel_base = XEXP (op, 0);
7872 tocrel_offset = XEXP (op, 1);
7875 if (tocrel_base_ret)
7876 *tocrel_base_ret = tocrel_base;
7877 if (tocrel_offset_ret)
7878 *tocrel_offset_ret = tocrel_offset;
7880 return (GET_CODE (tocrel_base) == UNSPEC
7881 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7882 && REG_P (XVECEXP (tocrel_base, 0, 1))
7883 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7886 /* Return true if X is a constant pool address, and also for cmodel=medium
7887 if X is a toc-relative address known to be offsettable within MODE. */
7890 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7893 const_rtx tocrel_base, tocrel_offset;
7894 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7895 && (TARGET_CMODEL != CMODEL_MEDIUM
7896 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7898 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7899 INTVAL (tocrel_offset), mode)));
7903 legitimate_small_data_p (machine_mode mode, rtx x)
7905 return (DEFAULT_ABI == ABI_V4
7906 && !flag_pic && !TARGET_TOC
7907 && (SYMBOL_REF_P (x) || GET_CODE (x) == CONST)
7908 && small_data_operand (x, mode));
7912 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7913 bool strict, bool worst_case)
7915 unsigned HOST_WIDE_INT offset;
7918 if (GET_CODE (x) != PLUS)
7920 if (!REG_P (XEXP (x, 0)))
7922 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7924 if (mode_supports_dq_form (mode))
7925 return quad_address_p (x, mode, strict);
7926 if (!reg_offset_addressing_ok_p (mode))
7927 return virtual_stack_registers_memory_p (x);
7928 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7930 if (!CONST_INT_P (XEXP (x, 1)))
7933 offset = INTVAL (XEXP (x, 1));
7940 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7942 if (VECTOR_MEM_VSX_P (mode))
7947 if (!TARGET_POWERPC64)
7949 else if (offset & 3)
7962 if (!TARGET_POWERPC64)
7964 else if (offset & 3)
7973 return offset < 0x10000 - extra;
7977 legitimate_indexed_address_p (rtx x, int strict)
7981 if (GET_CODE (x) != PLUS)
7987 return (REG_P (op0) && REG_P (op1)
7988 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
7989 && INT_REG_OK_FOR_INDEX_P (op1, strict))
7990 || (INT_REG_OK_FOR_BASE_P (op1, strict)
7991 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
7995 avoiding_indexed_address_p (machine_mode mode)
7997 /* Avoid indexed addressing for modes that have non-indexed
7998 load/store instruction forms. */
7999 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8003 legitimate_indirect_address_p (rtx x, int strict)
8005 return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
8009 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8011 if (!TARGET_MACHO || !flag_pic
8012 || mode != SImode || !MEM_P (x))
8016 if (GET_CODE (x) != LO_SUM)
8018 if (!REG_P (XEXP (x, 0)))
8020 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8024 return CONSTANT_P (x);
8028 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8030 if (GET_CODE (x) != LO_SUM)
8032 if (!REG_P (XEXP (x, 0)))
8034 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8036 /* quad word addresses are restricted, and we can't use LO_SUM. */
8037 if (mode_supports_dq_form (mode))
8041 if (TARGET_ELF || TARGET_MACHO)
8045 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8047 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8048 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8049 recognizes some LO_SUM addresses as valid although this
8050 function says opposite. In most cases, LRA through different
8051 transformations can generate correct code for address reloads.
8052 It cannot manage only some LO_SUM cases. So we need to add
8053 code here saying that some addresses are still valid. */
8054 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8055 && small_toc_ref (x, VOIDmode));
8056 if (TARGET_TOC && ! large_toc_ok)
8058 if (GET_MODE_NUNITS (mode) != 1)
8060 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8061 && !(/* ??? Assume floating point reg based on mode? */
8062 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8065 return CONSTANT_P (x) || large_toc_ok;
8072 /* Try machine-dependent ways of modifying an illegitimate address
8073 to be legitimate. If we find one, return the new, valid address.
8074 This is used from only one place: `memory_address' in explow.c.
8076 OLDX is the address as it was before break_out_memory_refs was
8077 called. In some cases it is useful to look at this to decide what
8080 It is always safe for this function to do nothing. It exists to
8081 recognize opportunities to optimize the output.
8083 On RS/6000, first check for the sum of a register with a constant
8084 integer that is out of range. If so, generate code to add the
8085 constant with the low-order 16 bits masked to the register and force
8086 this result into another register (this can be done with `cau').
8087 Then generate an address of REG+(CONST&0xffff), allowing for the
8088 possibility of bit 16 being a one.
8090 Then check for the sum of a register and something not constant, try to
8091 load the other things into a register and return the sum. */
8094 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8099 if (!reg_offset_addressing_ok_p (mode)
8100 || mode_supports_dq_form (mode))
8102 if (virtual_stack_registers_memory_p (x))
8105 /* In theory we should not be seeing addresses of the form reg+0,
8106 but just in case it is generated, optimize it away. */
8107 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8108 return force_reg (Pmode, XEXP (x, 0));
8110 /* For TImode with load/store quad, restrict addresses to just a single
8111 pointer, so it works with both GPRs and VSX registers. */
8112 /* Make sure both operands are registers. */
8113 else if (GET_CODE (x) == PLUS
8114 && (mode != TImode || !TARGET_VSX))
8115 return gen_rtx_PLUS (Pmode,
8116 force_reg (Pmode, XEXP (x, 0)),
8117 force_reg (Pmode, XEXP (x, 1)));
8119 return force_reg (Pmode, x);
8121 if (SYMBOL_REF_P (x))
8123 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8125 return rs6000_legitimize_tls_address (x, model);
8137 /* As in legitimate_offset_address_p we do not assume
8138 worst-case. The mode here is just a hint as to the registers
8139 used. A TImode is usually in gprs, but may actually be in
8140 fprs. Leave worst-case scenario for reload to handle via
8141 insn constraints. PTImode is only GPRs. */
8148 if (GET_CODE (x) == PLUS
8149 && REG_P (XEXP (x, 0))
8150 && CONST_INT_P (XEXP (x, 1))
8151 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8152 >= 0x10000 - extra))
8154 HOST_WIDE_INT high_int, low_int;
8156 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8157 if (low_int >= 0x8000 - extra)
8159 high_int = INTVAL (XEXP (x, 1)) - low_int;
8160 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8161 GEN_INT (high_int)), 0);
8162 return plus_constant (Pmode, sum, low_int);
8164 else if (GET_CODE (x) == PLUS
8165 && REG_P (XEXP (x, 0))
8166 && !CONST_INT_P (XEXP (x, 1))
8167 && GET_MODE_NUNITS (mode) == 1
8168 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8169 || (/* ??? Assume floating point reg based on mode? */
8170 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8171 && !avoiding_indexed_address_p (mode))
8173 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8174 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8176 else if ((TARGET_ELF
8178 || !MACHO_DYNAMIC_NO_PIC_P
8185 && !CONST_WIDE_INT_P (x)
8186 && !CONST_DOUBLE_P (x)
8188 && GET_MODE_NUNITS (mode) == 1
8189 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8190 || (/* ??? Assume floating point reg based on mode? */
8191 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8193 rtx reg = gen_reg_rtx (Pmode);
8195 emit_insn (gen_elf_high (reg, x));
8197 emit_insn (gen_macho_high (reg, x));
8198 return gen_rtx_LO_SUM (Pmode, reg, x);
8202 && constant_pool_expr_p (x)
8203 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8204 return create_TOC_reference (x, NULL_RTX);
8209 /* Debug version of rs6000_legitimize_address. */
8211 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8217 ret = rs6000_legitimize_address (x, oldx, mode);
8218 insns = get_insns ();
8224 "\nrs6000_legitimize_address: mode %s, old code %s, "
8225 "new code %s, modified\n",
8226 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8227 GET_RTX_NAME (GET_CODE (ret)));
8229 fprintf (stderr, "Original address:\n");
8232 fprintf (stderr, "oldx:\n");
8235 fprintf (stderr, "New address:\n");
8240 fprintf (stderr, "Insns added:\n");
8241 debug_rtx_list (insns, 20);
8247 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8248 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8259 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8260 We need to emit DTP-relative relocations. */
8262 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8264 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8269 fputs ("\t.long\t", file);
8272 fputs (DOUBLE_INT_ASM_OP, file);
8277 output_addr_const (file, x);
8279 fputs ("@dtprel+0x8000", file);
8280 else if (TARGET_XCOFF && SYMBOL_REF_P (x))
8282 switch (SYMBOL_REF_TLS_MODEL (x))
8286 case TLS_MODEL_LOCAL_EXEC:
8287 fputs ("@le", file);
8289 case TLS_MODEL_INITIAL_EXEC:
8290 fputs ("@ie", file);
8292 case TLS_MODEL_GLOBAL_DYNAMIC:
8293 case TLS_MODEL_LOCAL_DYNAMIC:
8302 /* Return true if X is a symbol that refers to real (rather than emulated)
8306 rs6000_real_tls_symbol_ref_p (rtx x)
8308 return (SYMBOL_REF_P (x)
8309 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8312 /* In the name of slightly smaller debug output, and to cater to
8313 general assembler lossage, recognize various UNSPEC sequences
8314 and turn them back into a direct symbol reference. */
8317 rs6000_delegitimize_address (rtx orig_x)
8321 if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
8322 orig_x = XVECEXP (orig_x, 0, 0);
8324 orig_x = delegitimize_mem_from_attrs (orig_x);
8331 if (TARGET_CMODEL != CMODEL_SMALL && GET_CODE (y) == LO_SUM)
8335 if (GET_CODE (y) == PLUS
8336 && GET_MODE (y) == Pmode
8337 && CONST_INT_P (XEXP (y, 1)))
8339 offset = XEXP (y, 1);
8343 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL)
8345 y = XVECEXP (y, 0, 0);
8348 /* Do not associate thread-local symbols with the original
8349 constant pool symbol. */
8352 && CONSTANT_POOL_ADDRESS_P (y)
8353 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8357 if (offset != NULL_RTX)
8358 y = gen_rtx_PLUS (Pmode, y, offset);
8359 if (!MEM_P (orig_x))
8362 return replace_equiv_address_nv (orig_x, y);
8366 && GET_CODE (orig_x) == LO_SUM
8367 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8369 y = XEXP (XEXP (orig_x, 1), 0);
8370 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8371 return XVECEXP (y, 0, 0);
8377 /* Return true if X shouldn't be emitted into the debug info.
8378 The linker doesn't like .toc section references from
8379 .debug_* sections, so reject .toc section symbols. */
8382 rs6000_const_not_ok_for_debug_p (rtx x)
8384 if (GET_CODE (x) == UNSPEC)
8386 if (SYMBOL_REF_P (x)
8387 && CONSTANT_POOL_ADDRESS_P (x))
8389 rtx c = get_pool_constant (x);
8390 machine_mode cmode = get_pool_mode (x);
8391 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8398 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8401 rs6000_legitimate_combined_insn (rtx_insn *insn)
8403 int icode = INSN_CODE (insn);
8405 /* Reject creating doloop insns. Combine should not be allowed
8406 to create these for a number of reasons:
8407 1) In a nested loop, if combine creates one of these in an
8408 outer loop and the register allocator happens to allocate ctr
8409 to the outer loop insn, then the inner loop can't use ctr.
8410 Inner loops ought to be more highly optimized.
8411 2) Combine often wants to create one of these from what was
8412 originally a three insn sequence, first combining the three
8413 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8414 allocated ctr, the splitter takes use back to the three insn
8415 sequence. It's better to stop combine at the two insn
8417 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8418 insns, the register allocator sometimes uses floating point
8419 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8420 jump insn and output reloads are not implemented for jumps,
8421 the ctrsi/ctrdi splitters need to handle all possible cases.
8422 That's a pain, and it gets to be seriously difficult when a
8423 splitter that runs after reload needs memory to transfer from
8424 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8425 for the difficult case. It's better to not create problems
8426 in the first place. */
8427 if (icode != CODE_FOR_nothing
8428 && (icode == CODE_FOR_bdz_si
8429 || icode == CODE_FOR_bdz_di
8430 || icode == CODE_FOR_bdnz_si
8431 || icode == CODE_FOR_bdnz_di
8432 || icode == CODE_FOR_bdztf_si
8433 || icode == CODE_FOR_bdztf_di
8434 || icode == CODE_FOR_bdnztf_si
8435 || icode == CODE_FOR_bdnztf_di))
8441 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8443 static GTY(()) rtx rs6000_tls_symbol;
8445 rs6000_tls_get_addr (void)
8447 if (!rs6000_tls_symbol)
8448 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8450 return rs6000_tls_symbol;
8453 /* Construct the SYMBOL_REF for TLS GOT references. */
8455 static GTY(()) rtx rs6000_got_symbol;
8457 rs6000_got_sym (void)
8459 if (!rs6000_got_symbol)
8461 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8462 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8463 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8466 return rs6000_got_symbol;
8469 /* AIX Thread-Local Address support. */
8472 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8474 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8478 name = XSTR (addr, 0);
8479 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8480 or the symbol will be in TLS private data section. */
8481 if (name[strlen (name) - 1] != ']'
8482 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8483 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8485 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8486 strcpy (tlsname, name);
8488 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8489 tlsaddr = copy_rtx (addr);
8490 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8495 /* Place addr into TOC constant pool. */
8496 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8498 /* Output the TOC entry and create the MEM referencing the value. */
8499 if (constant_pool_expr_p (XEXP (sym, 0))
8500 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8502 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8503 mem = gen_const_mem (Pmode, tocref);
8504 set_mem_alias_set (mem, get_TOC_alias_set ());
8509 /* Use global-dynamic for local-dynamic. */
8510 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8511 || model == TLS_MODEL_LOCAL_DYNAMIC)
8513 /* Create new TOC reference for @m symbol. */
8514 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8515 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8516 strcpy (tlsname, "*LCM");
8517 strcat (tlsname, name + 3);
8518 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8519 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8520 tocref = create_TOC_reference (modaddr, NULL_RTX);
8521 rtx modmem = gen_const_mem (Pmode, tocref);
8522 set_mem_alias_set (modmem, get_TOC_alias_set ());
8524 rtx modreg = gen_reg_rtx (Pmode);
8525 emit_insn (gen_rtx_SET (modreg, modmem));
8527 tmpreg = gen_reg_rtx (Pmode);
8528 emit_insn (gen_rtx_SET (tmpreg, mem));
8530 dest = gen_reg_rtx (Pmode);
8532 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8534 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8537 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8538 else if (TARGET_32BIT)
8540 tlsreg = gen_reg_rtx (SImode);
8541 emit_insn (gen_tls_get_tpointer (tlsreg));
8544 tlsreg = gen_rtx_REG (DImode, 13);
8546 /* Load the TOC value into temporary register. */
8547 tmpreg = gen_reg_rtx (Pmode);
8548 emit_insn (gen_rtx_SET (tmpreg, mem));
8549 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8550 gen_rtx_MINUS (Pmode, addr, tlsreg));
8552 /* Add TOC symbol value to TLS pointer. */
8553 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8558 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8559 __tls_get_addr call. */
8562 rs6000_output_tlsargs (rtx *operands)
8564 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8567 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8568 op[0] = operands[0];
8569 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8570 op[1] = XVECEXP (operands[2], 0, 0);
8571 if (XINT (operands[2], 1) == UNSPEC_TLSGD)
8573 /* The GOT register. */
8574 op[2] = XVECEXP (operands[2], 0, 1);
8575 if (TARGET_CMODEL != CMODEL_SMALL)
8576 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8577 "addi %0,%0,%1@got@tlsgd@l", op);
8579 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op);
8581 else if (XINT (operands[2], 1) == UNSPEC_TLSLD)
8583 if (TARGET_CMODEL != CMODEL_SMALL)
8584 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8585 "addi %0,%0,%&@got@tlsld@l", op);
8587 output_asm_insn ("addi %0,%1,%&@got@tlsld", op);
8593 /* Passes the tls arg value for global dynamic and local dynamic
8594 emit_library_call_value in rs6000_legitimize_tls_address to
8595 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8596 marker relocs put on __tls_get_addr calls. */
8597 static rtx global_tlsarg;
8599 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8600 this (thread-local) address. */
8603 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8608 return rs6000_legitimize_tls_address_aix (addr, model);
8610 dest = gen_reg_rtx (Pmode);
8611 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8617 tlsreg = gen_rtx_REG (Pmode, 13);
8618 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8622 tlsreg = gen_rtx_REG (Pmode, 2);
8623 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8627 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8631 tmp = gen_reg_rtx (Pmode);
8634 tlsreg = gen_rtx_REG (Pmode, 13);
8635 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8639 tlsreg = gen_rtx_REG (Pmode, 2);
8640 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8644 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8646 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8651 rtx got, tga, tmp1, tmp2;
8653 /* We currently use relocations like @got@tlsgd for tls, which
8654 means the linker will handle allocation of tls entries, placing
8655 them in the .got section. So use a pointer to the .got section,
8656 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8657 or to secondary GOT sections used by 32-bit -fPIC. */
8659 got = gen_rtx_REG (Pmode, 2);
8663 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8666 rtx gsym = rs6000_got_sym ();
8667 got = gen_reg_rtx (Pmode);
8669 rs6000_emit_move (got, gsym, Pmode);
8674 tmp1 = gen_reg_rtx (Pmode);
8675 tmp2 = gen_reg_rtx (Pmode);
8676 mem = gen_const_mem (Pmode, tmp1);
8677 lab = gen_label_rtx ();
8678 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8679 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8680 if (TARGET_LINK_STACK)
8681 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8682 emit_move_insn (tmp2, mem);
8683 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8684 set_unique_reg_note (last, REG_EQUAL, gsym);
8689 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8691 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addr, got),
8693 tga = rs6000_tls_get_addr ();
8694 global_tlsarg = arg;
8695 if (TARGET_TLS_MARKERS)
8697 rtx argreg = gen_rtx_REG (Pmode, 3);
8698 emit_insn (gen_rtx_SET (argreg, arg));
8699 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8703 emit_library_call_value (tga, dest, LCT_CONST, Pmode);
8704 global_tlsarg = NULL_RTX;
8706 /* Make a note so that the result of this call can be CSEd. */
8707 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8708 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8709 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8711 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8713 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got), UNSPEC_TLSLD);
8714 tga = rs6000_tls_get_addr ();
8715 tmp1 = gen_reg_rtx (Pmode);
8716 global_tlsarg = arg;
8717 if (TARGET_TLS_MARKERS)
8719 rtx argreg = gen_rtx_REG (Pmode, 3);
8720 emit_insn (gen_rtx_SET (argreg, arg));
8721 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8725 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode);
8726 global_tlsarg = NULL_RTX;
8728 /* Make a note so that the result of this call can be CSEd. */
8729 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8730 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8731 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8733 if (rs6000_tls_size == 16)
8736 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8738 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8740 else if (rs6000_tls_size == 32)
8742 tmp2 = gen_reg_rtx (Pmode);
8744 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8746 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8749 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8751 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8755 tmp2 = gen_reg_rtx (Pmode);
8757 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8759 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8761 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8767 /* IE, or 64-bit offset LE. */
8768 tmp2 = gen_reg_rtx (Pmode);
8770 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8772 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8775 insn = gen_tls_tls_64 (dest, tmp2, addr);
8777 insn = gen_tls_tls_32 (dest, tmp2, addr);
8785 /* Only create the global variable for the stack protect guard if we are using
8786 the global flavor of that guard. */
8788 rs6000_init_stack_protect_guard (void)
8790 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8791 return default_stack_protect_guard ();
8796 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8799 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8801 if (GET_CODE (x) == HIGH
8802 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8805 /* A TLS symbol in the TOC cannot contain a sum. */
8806 if (GET_CODE (x) == CONST
8807 && GET_CODE (XEXP (x, 0)) == PLUS
8808 && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
8809 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8812 /* Do not place an ELF TLS symbol in the constant pool. */
8813 return TARGET_ELF && tls_referenced_p (x);
8816 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8817 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8818 can be addressed relative to the toc pointer. */
8821 use_toc_relative_ref (rtx sym, machine_mode mode)
8823 return ((constant_pool_expr_p (sym)
8824 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8825 get_pool_mode (sym)))
8826 || (TARGET_CMODEL == CMODEL_MEDIUM
8827 && SYMBOL_REF_LOCAL_P (sym)
8828 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8831 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8832 that is a valid memory address for an instruction.
8833 The MODE argument is the machine mode for the MEM expression
8834 that wants to use this address.
8836 On the RS/6000, there are four valid address: a SYMBOL_REF that
8837 refers to a constant pool entry of an address (or the sum of it
8838 plus a constant), a short (16-bit signed) constant plus a register,
8839 the sum of two registers, or a register indirect, possibly with an
8840 auto-increment. For DFmode, DDmode and DImode with a constant plus
8841 register, we must ensure that both words are addressable or PowerPC64
8842 with offset word aligned.
8844 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8845 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8846 because adjacent memory cells are accessed by adding word-sized offsets
8847 during assembly output. */
8849 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
8851 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8852 bool quad_offset_p = mode_supports_dq_form (mode);
8854 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8855 if (VECTOR_MEM_ALTIVEC_P (mode)
8856 && GET_CODE (x) == AND
8857 && CONST_INT_P (XEXP (x, 1))
8858 && INTVAL (XEXP (x, 1)) == -16)
8861 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
8863 if (legitimate_indirect_address_p (x, reg_ok_strict))
8866 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
8867 && mode_supports_pre_incdec_p (mode)
8868 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
8870 /* Handle restricted vector d-form offsets in ISA 3.0. */
8873 if (quad_address_p (x, mode, reg_ok_strict))
8876 else if (virtual_stack_registers_memory_p (x))
8879 else if (reg_offset_p)
8881 if (legitimate_small_data_p (mode, x))
8883 if (legitimate_constant_pool_address_p (x, mode,
8884 reg_ok_strict || lra_in_progress))
8888 /* For TImode, if we have TImode in VSX registers, only allow register
8889 indirect addresses. This will allow the values to go in either GPRs
8890 or VSX registers without reloading. The vector types would tend to
8891 go into VSX registers, so we allow REG+REG, while TImode seems
8892 somewhat split, in that some uses are GPR based, and some VSX based. */
8893 /* FIXME: We could loosen this by changing the following to
8894 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
8895 but currently we cannot allow REG+REG addressing for TImode. See
8896 PR72827 for complete details on how this ends up hoodwinking DSE. */
8897 if (mode == TImode && TARGET_VSX)
8899 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8902 && GET_CODE (x) == PLUS
8903 && REG_P (XEXP (x, 0))
8904 && (XEXP (x, 0) == virtual_stack_vars_rtx
8905 || XEXP (x, 0) == arg_pointer_rtx)
8906 && CONST_INT_P (XEXP (x, 1)))
8908 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
8910 if (!FLOAT128_2REG_P (mode)
8911 && (TARGET_HARD_FLOAT
8913 || (mode != DFmode && mode != DDmode))
8914 && (TARGET_POWERPC64 || mode != DImode)
8915 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
8917 && !avoiding_indexed_address_p (mode)
8918 && legitimate_indexed_address_p (x, reg_ok_strict))
8920 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
8921 && mode_supports_pre_modify_p (mode)
8922 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
8923 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
8924 reg_ok_strict, false)
8925 || (!avoiding_indexed_address_p (mode)
8926 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
8927 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8929 if (reg_offset_p && !quad_offset_p
8930 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
8935 /* Debug version of rs6000_legitimate_address_p. */
8937 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
8940 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
8942 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8943 "strict = %d, reload = %s, code = %s\n",
8944 ret ? "true" : "false",
8945 GET_MODE_NAME (mode),
8947 (reload_completed ? "after" : "before"),
8948 GET_RTX_NAME (GET_CODE (x)));
8954 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8957 rs6000_mode_dependent_address_p (const_rtx addr,
8958 addr_space_t as ATTRIBUTE_UNUSED)
8960 return rs6000_mode_dependent_address_ptr (addr);
8963 /* Go to LABEL if ADDR (a legitimate address expression)
8964 has an effect that depends on the machine mode it is used for.
8966 On the RS/6000 this is true of all integral offsets (since AltiVec
8967 and VSX modes don't allow them) or is a pre-increment or decrement.
8969 ??? Except that due to conceptual problems in offsettable_address_p
8970 we can't really report the problems of integral offsets. So leave
8971 this assuming that the adjustable offset must be valid for the
8972 sub-words of a TFmode operand, which is what we had before. */
8975 rs6000_mode_dependent_address (const_rtx addr)
8977 switch (GET_CODE (addr))
8980 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8981 is considered a legitimate address before reload, so there
8982 are no offset restrictions in that case. Note that this
8983 condition is safe in strict mode because any address involving
8984 virtual_stack_vars_rtx or arg_pointer_rtx would already have
8985 been rejected as illegitimate. */
8986 if (XEXP (addr, 0) != virtual_stack_vars_rtx
8987 && XEXP (addr, 0) != arg_pointer_rtx
8988 && CONST_INT_P (XEXP (addr, 1)))
8990 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
8991 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
8996 /* Anything in the constant pool is sufficiently aligned that
8997 all bytes have the same high part address. */
8998 return !legitimate_constant_pool_address_p (addr, QImode, false);
9000 /* Auto-increment cases are now treated generically in recog.c. */
9002 return TARGET_UPDATE;
9004 /* AND is only allowed in Altivec loads. */
9015 /* Debug version of rs6000_mode_dependent_address. */
9017 rs6000_debug_mode_dependent_address (const_rtx addr)
9019 bool ret = rs6000_mode_dependent_address (addr);
9021 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9022 ret ? "true" : "false");
9028 /* Implement FIND_BASE_TERM. */
9031 rs6000_find_base_term (rtx op)
9036 if (GET_CODE (base) == CONST)
9037 base = XEXP (base, 0);
9038 if (GET_CODE (base) == PLUS)
9039 base = XEXP (base, 0);
9040 if (GET_CODE (base) == UNSPEC)
9041 switch (XINT (base, 1))
9044 case UNSPEC_MACHOPIC_OFFSET:
9045 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9046 for aliasing purposes. */
9047 return XVECEXP (base, 0, 0);
9053 /* More elaborate version of recog's offsettable_memref_p predicate
9054 that works around the ??? note of rs6000_mode_dependent_address.
9055 In particular it accepts
9057 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9059 in 32-bit mode, that the recog predicate rejects. */
9062 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9069 /* First mimic offsettable_memref_p. */
9070 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9073 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9074 the latter predicate knows nothing about the mode of the memory
9075 reference and, therefore, assumes that it is the largest supported
9076 mode (TFmode). As a consequence, legitimate offsettable memory
9077 references are rejected. rs6000_legitimate_offset_address_p contains
9078 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9079 at least with a little bit of help here given that we know the
9080 actual registers used. */
9081 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9082 || GET_MODE_SIZE (reg_mode) == 4);
9083 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9084 strict, worst_case);
9087 /* Determine the reassociation width to be used in reassociate_bb.
9088 This takes into account how many parallel operations we
9089 can actually do of a given type, and also the latency.
9093 vect add/sub/mul 2/cycle
9094 fp add/sub/mul 2/cycle
9099 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9102 switch (rs6000_tune)
9104 case PROCESSOR_POWER8:
9105 case PROCESSOR_POWER9:
9106 case PROCESSOR_FUTURE:
9107 if (DECIMAL_FLOAT_MODE_P (mode))
9109 if (VECTOR_MODE_P (mode))
9111 if (INTEGRAL_MODE_P (mode))
9113 if (FLOAT_MODE_P (mode))
9122 /* Change register usage conditional on target flags. */
9124 rs6000_conditional_register_usage (void)
9128 if (TARGET_DEBUG_TARGET)
9129 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9131 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9133 fixed_regs[13] = call_used_regs[13]
9134 = call_really_used_regs[13] = 1;
9136 /* Conditionally disable FPRs. */
9137 if (TARGET_SOFT_FLOAT)
9138 for (i = 32; i < 64; i++)
9139 fixed_regs[i] = call_used_regs[i]
9140 = call_really_used_regs[i] = 1;
9142 /* The TOC register is not killed across calls in a way that is
9143 visible to the compiler. */
9144 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9145 call_really_used_regs[2] = 0;
9147 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9148 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9150 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9151 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9152 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9153 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9155 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9156 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9157 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9158 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9160 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9161 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9162 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9164 if (!TARGET_ALTIVEC && !TARGET_VSX)
9166 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9167 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9168 call_really_used_regs[VRSAVE_REGNO] = 1;
9171 if (TARGET_ALTIVEC || TARGET_VSX)
9172 global_regs[VSCR_REGNO] = 1;
9174 if (TARGET_ALTIVEC_ABI)
9176 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9177 call_used_regs[i] = call_really_used_regs[i] = 1;
9179 /* AIX reserves VR20:31 in non-extended ABI mode. */
9181 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9182 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9187 /* Output insns to set DEST equal to the constant SOURCE as a series of
9188 lis, ori and shl instructions and return TRUE. */
9191 rs6000_emit_set_const (rtx dest, rtx source)
9193 machine_mode mode = GET_MODE (dest);
9198 gcc_checking_assert (CONST_INT_P (source));
9199 c = INTVAL (source);
9204 emit_insn (gen_rtx_SET (dest, source));
9208 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9210 emit_insn (gen_rtx_SET (copy_rtx (temp),
9211 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9212 emit_insn (gen_rtx_SET (dest,
9213 gen_rtx_IOR (SImode, copy_rtx (temp),
9214 GEN_INT (c & 0xffff))));
9218 if (!TARGET_POWERPC64)
9222 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9224 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9226 emit_move_insn (hi, GEN_INT (c >> 32));
9227 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9228 emit_move_insn (lo, GEN_INT (c));
9231 rs6000_emit_set_long_const (dest, c);
9238 insn = get_last_insn ();
9239 set = single_set (insn);
9240 if (! CONSTANT_P (SET_SRC (set)))
9241 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9246 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9247 Output insns to set DEST equal to the constant C as a series of
9248 lis, ori and shl instructions. */
9251 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9254 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9264 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9265 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9266 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9268 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9269 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9271 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9273 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9274 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9276 emit_move_insn (dest,
9277 gen_rtx_IOR (DImode, copy_rtx (temp),
9280 else if (ud3 == 0 && ud4 == 0)
9282 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9284 gcc_assert (ud2 & 0x8000);
9285 emit_move_insn (copy_rtx (temp),
9286 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9288 emit_move_insn (copy_rtx (temp),
9289 gen_rtx_IOR (DImode, copy_rtx (temp),
9291 emit_move_insn (dest,
9292 gen_rtx_ZERO_EXTEND (DImode,
9293 gen_lowpart (SImode,
9296 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9297 || (ud4 == 0 && ! (ud3 & 0x8000)))
9299 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9301 emit_move_insn (copy_rtx (temp),
9302 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9304 emit_move_insn (copy_rtx (temp),
9305 gen_rtx_IOR (DImode, copy_rtx (temp),
9307 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9308 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9311 emit_move_insn (dest,
9312 gen_rtx_IOR (DImode, copy_rtx (temp),
9317 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9319 emit_move_insn (copy_rtx (temp),
9320 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9322 emit_move_insn (copy_rtx (temp),
9323 gen_rtx_IOR (DImode, copy_rtx (temp),
9326 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9327 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9330 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9331 gen_rtx_IOR (DImode, copy_rtx (temp),
9332 GEN_INT (ud2 << 16)));
9334 emit_move_insn (dest,
9335 gen_rtx_IOR (DImode, copy_rtx (temp),
9340 /* Helper for the following. Get rid of [r+r] memory refs
9341 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9344 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9346 if (MEM_P (operands[0])
9347 && !REG_P (XEXP (operands[0], 0))
9348 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9349 GET_MODE (operands[0]), false))
9351 = replace_equiv_address (operands[0],
9352 copy_addr_to_reg (XEXP (operands[0], 0)));
9354 if (MEM_P (operands[1])
9355 && !REG_P (XEXP (operands[1], 0))
9356 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9357 GET_MODE (operands[1]), false))
9359 = replace_equiv_address (operands[1],
9360 copy_addr_to_reg (XEXP (operands[1], 0)));
9363 /* Generate a vector of constants to permute MODE for a little-endian
9364 storage operation by swapping the two halves of a vector. */
9366 rs6000_const_vec (machine_mode mode)
9394 v = rtvec_alloc (subparts);
9396 for (i = 0; i < subparts / 2; ++i)
9397 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9398 for (i = subparts / 2; i < subparts; ++i)
9399 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9404 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9407 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9409 /* Scalar permutations are easier to express in integer modes rather than
9410 floating-point modes, so cast them here. We use V1TImode instead
9411 of TImode to ensure that the values don't go through GPRs. */
9412 if (FLOAT128_VECTOR_P (mode))
9414 dest = gen_lowpart (V1TImode, dest);
9415 source = gen_lowpart (V1TImode, source);
9419 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9421 if (mode == TImode || mode == V1TImode)
9422 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9426 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9427 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9431 /* Emit a little-endian load from vector memory location SOURCE to VSX
9432 register DEST in mode MODE. The load is done with two permuting
9433 insn's that represent an lxvd2x and xxpermdi. */
9435 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9437 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9439 if (mode == TImode || mode == V1TImode)
9442 dest = gen_lowpart (V2DImode, dest);
9443 source = adjust_address (source, V2DImode, 0);
9446 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9447 rs6000_emit_le_vsx_permute (tmp, source, mode);
9448 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9451 /* Emit a little-endian store to vector memory location DEST from VSX
9452 register SOURCE in mode MODE. The store is done with two permuting
9453 insn's that represent an xxpermdi and an stxvd2x. */
9455 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9457 /* This should never be called during or after LRA, because it does
9458 not re-permute the source register. It is intended only for use
9460 gcc_assert (!lra_in_progress && !reload_completed);
9462 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9464 if (mode == TImode || mode == V1TImode)
9467 dest = adjust_address (dest, V2DImode, 0);
9468 source = gen_lowpart (V2DImode, source);
9471 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9472 rs6000_emit_le_vsx_permute (tmp, source, mode);
9473 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9476 /* Emit a sequence representing a little-endian VSX load or store,
9477 moving data from SOURCE to DEST in mode MODE. This is done
9478 separately from rs6000_emit_move to ensure it is called only
9479 during expand. LE VSX loads and stores introduced later are
9480 handled with a split. The expand-time RTL generation allows
9481 us to optimize away redundant pairs of register-permutes. */
9483 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9485 gcc_assert (!BYTES_BIG_ENDIAN
9486 && VECTOR_MEM_VSX_P (mode)
9487 && !TARGET_P9_VECTOR
9488 && !gpr_or_gpr_p (dest, source)
9489 && (MEM_P (source) ^ MEM_P (dest)));
9493 gcc_assert (REG_P (dest) || SUBREG_P (dest));
9494 rs6000_emit_le_vsx_load (dest, source, mode);
9498 if (!REG_P (source))
9499 source = force_reg (mode, source);
9500 rs6000_emit_le_vsx_store (dest, source, mode);
9504 /* Return whether a SFmode or SImode move can be done without converting one
9505 mode to another. This arrises when we have:
9507 (SUBREG:SF (REG:SI ...))
9508 (SUBREG:SI (REG:SF ...))
9510 and one of the values is in a floating point/vector register, where SFmode
9511 scalars are stored in DFmode format. */
9514 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9516 if (TARGET_ALLOW_SF_SUBREG)
9519 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9522 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9525 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9526 if (SUBREG_P (dest))
9528 rtx dest_subreg = SUBREG_REG (dest);
9529 rtx src_subreg = SUBREG_REG (src);
9530 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9537 /* Helper function to change moves with:
9539 (SUBREG:SF (REG:SI)) and
9540 (SUBREG:SI (REG:SF))
9542 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9543 values are stored as DFmode values in the VSX registers. We need to convert
9544 the bits before we can use a direct move or operate on the bits in the
9545 vector register as an integer type.
9547 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9550 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9552 if (TARGET_DIRECT_MOVE_64BIT && !reload_completed
9553 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9554 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9556 rtx inner_source = SUBREG_REG (source);
9557 machine_mode inner_mode = GET_MODE (inner_source);
9559 if (mode == SImode && inner_mode == SFmode)
9561 emit_insn (gen_movsi_from_sf (dest, inner_source));
9565 if (mode == SFmode && inner_mode == SImode)
9567 emit_insn (gen_movsf_from_si (dest, inner_source));
9575 /* Emit a move from SOURCE to DEST in mode MODE. */
9577 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9581 operands[1] = source;
9583 if (TARGET_DEBUG_ADDR)
9586 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9587 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9588 GET_MODE_NAME (mode),
9591 can_create_pseudo_p ());
9593 fprintf (stderr, "source:\n");
9597 /* Check that we get CONST_WIDE_INT only when we should. */
9598 if (CONST_WIDE_INT_P (operands[1])
9599 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9602 #ifdef HAVE_AS_GNU_ATTRIBUTE
9603 /* If we use a long double type, set the flags in .gnu_attribute that say
9604 what the long double type is. This is to allow the linker's warning
9605 message for the wrong long double to be useful, even if the function does
9606 not do a call (for example, doing a 128-bit add on power9 if the long
9607 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9608 used if they aren't the default long dobule type. */
9609 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9611 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9612 rs6000_passes_float = rs6000_passes_long_double = true;
9614 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9615 rs6000_passes_float = rs6000_passes_long_double = true;
9619 /* See if we need to special case SImode/SFmode SUBREG moves. */
9620 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9621 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9624 /* Check if GCC is setting up a block move that will end up using FP
9625 registers as temporaries. We must make sure this is acceptable. */
9626 if (MEM_P (operands[0])
9627 && MEM_P (operands[1])
9629 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9630 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9631 && ! (rs6000_slow_unaligned_access (SImode,
9632 (MEM_ALIGN (operands[0]) > 32
9633 ? 32 : MEM_ALIGN (operands[0])))
9634 || rs6000_slow_unaligned_access (SImode,
9635 (MEM_ALIGN (operands[1]) > 32
9636 ? 32 : MEM_ALIGN (operands[1]))))
9637 && ! MEM_VOLATILE_P (operands [0])
9638 && ! MEM_VOLATILE_P (operands [1]))
9640 emit_move_insn (adjust_address (operands[0], SImode, 0),
9641 adjust_address (operands[1], SImode, 0));
9642 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9643 adjust_address (copy_rtx (operands[1]), SImode, 4));
9647 if (can_create_pseudo_p () && MEM_P (operands[0])
9648 && !gpc_reg_operand (operands[1], mode))
9649 operands[1] = force_reg (mode, operands[1]);
9651 /* Recognize the case where operand[1] is a reference to thread-local
9652 data and load its address to a register. */
9653 if (tls_referenced_p (operands[1]))
9655 enum tls_model model;
9656 rtx tmp = operands[1];
9659 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9661 addend = XEXP (XEXP (tmp, 0), 1);
9662 tmp = XEXP (XEXP (tmp, 0), 0);
9665 gcc_assert (SYMBOL_REF_P (tmp));
9666 model = SYMBOL_REF_TLS_MODEL (tmp);
9667 gcc_assert (model != 0);
9669 tmp = rs6000_legitimize_tls_address (tmp, model);
9672 tmp = gen_rtx_PLUS (mode, tmp, addend);
9673 tmp = force_operand (tmp, operands[0]);
9678 /* 128-bit constant floating-point values on Darwin should really be loaded
9679 as two parts. However, this premature splitting is a problem when DFmode
9680 values can go into Altivec registers. */
9681 if (TARGET_MACHO && CONST_DOUBLE_P (operands[1]) && FLOAT128_IBM_P (mode)
9682 && !reg_addr[DFmode].scalar_in_vmx_p)
9684 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9685 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9687 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9688 GET_MODE_SIZE (DFmode)),
9689 simplify_gen_subreg (DFmode, operands[1], mode,
9690 GET_MODE_SIZE (DFmode)),
9695 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9696 p1:SD) if p1 is not of floating point class and p0 is spilled as
9697 we can have no analogous movsd_store for this. */
9698 if (lra_in_progress && mode == DDmode
9699 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9700 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9701 && SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))
9702 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9705 int regno = REGNO (SUBREG_REG (operands[1]));
9707 if (!HARD_REGISTER_NUM_P (regno))
9709 cl = reg_preferred_class (regno);
9710 regno = reg_renumber[regno];
9712 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9714 if (regno >= 0 && ! FP_REGNO_P (regno))
9717 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9718 operands[1] = SUBREG_REG (operands[1]);
9723 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9724 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9725 && (REG_P (operands[1])
9726 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))))
9728 int regno = reg_or_subregno (operands[1]);
9731 if (!HARD_REGISTER_NUM_P (regno))
9733 cl = reg_preferred_class (regno);
9734 gcc_assert (cl != NO_REGS);
9735 regno = reg_renumber[regno];
9737 regno = ira_class_hard_regs[cl][0];
9739 if (FP_REGNO_P (regno))
9741 if (GET_MODE (operands[0]) != DDmode)
9742 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
9743 emit_insn (gen_movsd_store (operands[0], operands[1]));
9745 else if (INT_REGNO_P (regno))
9746 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9751 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9752 p:DD)) if p0 is not of floating point class and p1 is spilled as
9753 we can have no analogous movsd_load for this. */
9754 if (lra_in_progress && mode == DDmode
9755 && SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))
9756 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
9757 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9758 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9761 int regno = REGNO (SUBREG_REG (operands[0]));
9763 if (!HARD_REGISTER_NUM_P (regno))
9765 cl = reg_preferred_class (regno);
9766 regno = reg_renumber[regno];
9768 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
9770 if (regno >= 0 && ! FP_REGNO_P (regno))
9773 operands[0] = SUBREG_REG (operands[0]);
9774 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
9779 && (REG_P (operands[0])
9780 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
9781 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9782 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9784 int regno = reg_or_subregno (operands[0]);
9787 if (!HARD_REGISTER_NUM_P (regno))
9789 cl = reg_preferred_class (regno);
9790 gcc_assert (cl != NO_REGS);
9791 regno = reg_renumber[regno];
9793 regno = ira_class_hard_regs[cl][0];
9795 if (FP_REGNO_P (regno))
9797 if (GET_MODE (operands[1]) != DDmode)
9798 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
9799 emit_insn (gen_movsd_load (operands[0], operands[1]));
9801 else if (INT_REGNO_P (regno))
9802 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9808 /* FIXME: In the long term, this switch statement should go away
9809 and be replaced by a sequence of tests based on things like
9815 if (CONSTANT_P (operands[1])
9816 && !CONST_INT_P (operands[1]))
9817 operands[1] = force_const_mem (mode, operands[1]);
9824 if (FLOAT128_2REG_P (mode))
9825 rs6000_eliminate_indexed_memrefs (operands);
9832 if (CONSTANT_P (operands[1])
9833 && ! easy_fp_constant (operands[1], mode))
9834 operands[1] = force_const_mem (mode, operands[1]);
9844 if (CONSTANT_P (operands[1])
9845 && !easy_vector_constant (operands[1], mode))
9846 operands[1] = force_const_mem (mode, operands[1]);
9851 /* Use default pattern for address of ELF small data */
9854 && DEFAULT_ABI == ABI_V4
9855 && (SYMBOL_REF_P (operands[1])
9856 || GET_CODE (operands[1]) == CONST)
9857 && small_data_operand (operands[1], mode))
9859 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9863 if (DEFAULT_ABI == ABI_V4
9864 && mode == Pmode && mode == SImode
9865 && flag_pic == 1 && got_operand (operands[1], mode))
9867 emit_insn (gen_movsi_got (operands[0], operands[1]));
9871 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
9875 && CONSTANT_P (operands[1])
9876 && GET_CODE (operands[1]) != HIGH
9877 && !CONST_INT_P (operands[1]))
9879 rtx target = (!can_create_pseudo_p ()
9881 : gen_reg_rtx (mode));
9883 /* If this is a function address on -mcall-aixdesc,
9884 convert it to the address of the descriptor. */
9885 if (DEFAULT_ABI == ABI_AIX
9886 && SYMBOL_REF_P (operands[1])
9887 && XSTR (operands[1], 0)[0] == '.')
9889 const char *name = XSTR (operands[1], 0);
9891 while (*name == '.')
9893 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
9894 CONSTANT_POOL_ADDRESS_P (new_ref)
9895 = CONSTANT_POOL_ADDRESS_P (operands[1]);
9896 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
9897 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
9898 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
9899 operands[1] = new_ref;
9902 if (DEFAULT_ABI == ABI_DARWIN)
9905 if (MACHO_DYNAMIC_NO_PIC_P)
9907 /* Take care of any required data indirection. */
9908 operands[1] = rs6000_machopic_legitimize_pic_address (
9909 operands[1], mode, operands[0]);
9910 if (operands[0] != operands[1])
9911 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9915 emit_insn (gen_macho_high (target, operands[1]));
9916 emit_insn (gen_macho_low (operands[0], target, operands[1]));
9920 emit_insn (gen_elf_high (target, operands[1]));
9921 emit_insn (gen_elf_low (operands[0], target, operands[1]));
9925 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9926 and we have put it in the TOC, we just need to make a TOC-relative
9929 && SYMBOL_REF_P (operands[1])
9930 && use_toc_relative_ref (operands[1], mode))
9931 operands[1] = create_TOC_reference (operands[1], operands[0]);
9932 else if (mode == Pmode
9933 && CONSTANT_P (operands[1])
9934 && GET_CODE (operands[1]) != HIGH
9935 && ((REG_P (operands[0])
9936 && FP_REGNO_P (REGNO (operands[0])))
9937 || !CONST_INT_P (operands[1])
9938 || (num_insns_constant (operands[1], mode)
9939 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
9940 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
9941 && (TARGET_CMODEL == CMODEL_SMALL
9942 || can_create_pseudo_p ()
9943 || (REG_P (operands[0])
9944 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
9948 /* Darwin uses a special PIC legitimizer. */
9949 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
9952 rs6000_machopic_legitimize_pic_address (operands[1], mode,
9954 if (operands[0] != operands[1])
9955 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9960 /* If we are to limit the number of things we put in the TOC and
9961 this is a symbol plus a constant we can add in one insn,
9962 just put the symbol in the TOC and add the constant. */
9963 if (GET_CODE (operands[1]) == CONST
9964 && TARGET_NO_SUM_IN_TOC
9965 && GET_CODE (XEXP (operands[1], 0)) == PLUS
9966 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
9967 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
9968 || SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
9969 && ! side_effects_p (operands[0]))
9972 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
9973 rtx other = XEXP (XEXP (operands[1], 0), 1);
9975 sym = force_reg (mode, sym);
9976 emit_insn (gen_add3_insn (operands[0], sym, other));
9980 operands[1] = force_const_mem (mode, operands[1]);
9983 && SYMBOL_REF_P (XEXP (operands[1], 0))
9984 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
9986 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
9988 operands[1] = gen_const_mem (mode, tocref);
9989 set_mem_alias_set (operands[1], get_TOC_alias_set ());
9995 if (!VECTOR_MEM_VSX_P (TImode))
9996 rs6000_eliminate_indexed_memrefs (operands);
10000 rs6000_eliminate_indexed_memrefs (operands);
10004 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10007 /* Above, we may have called force_const_mem which may have returned
10008 an invalid address. If we can, fix this up; otherwise, reload will
10009 have to deal with it. */
10010 if (MEM_P (operands[1]))
10011 operands[1] = validize_mem (operands[1]);
10013 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10016 /* Nonzero if we can use a floating-point register to pass this arg. */
10017 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10018 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10019 && (CUM)->fregno <= FP_ARG_MAX_REG \
10020 && TARGET_HARD_FLOAT)
10022 /* Nonzero if we can use an AltiVec register to pass this arg. */
10023 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10024 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10025 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10026 && TARGET_ALTIVEC_ABI \
10029 /* Walk down the type tree of TYPE counting consecutive base elements.
10030 If *MODEP is VOIDmode, then set it to the first valid floating point
10031 or vector type. If a non-floating point or vector type is found, or
10032 if a floating point or vector type that doesn't match a non-VOIDmode
10033 *MODEP is found, then return -1, otherwise return the count in the
10037 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10040 HOST_WIDE_INT size;
10042 switch (TREE_CODE (type))
10045 mode = TYPE_MODE (type);
10046 if (!SCALAR_FLOAT_MODE_P (mode))
10049 if (*modep == VOIDmode)
10052 if (*modep == mode)
10058 mode = TYPE_MODE (TREE_TYPE (type));
10059 if (!SCALAR_FLOAT_MODE_P (mode))
10062 if (*modep == VOIDmode)
10065 if (*modep == mode)
10071 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10074 /* Use V4SImode as representative of all 128-bit vector types. */
10075 size = int_size_in_bytes (type);
10085 if (*modep == VOIDmode)
10088 /* Vector modes are considered to be opaque: two vectors are
10089 equivalent for the purposes of being homogeneous aggregates
10090 if they are the same size. */
10091 if (*modep == mode)
10099 tree index = TYPE_DOMAIN (type);
10101 /* Can't handle incomplete types nor sizes that are not
10103 if (!COMPLETE_TYPE_P (type)
10104 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10107 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10110 || !TYPE_MAX_VALUE (index)
10111 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10112 || !TYPE_MIN_VALUE (index)
10113 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10117 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10118 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10120 /* There must be no padding. */
10121 if (wi::to_wide (TYPE_SIZE (type))
10122 != count * GET_MODE_BITSIZE (*modep))
10134 /* Can't handle incomplete types nor sizes that are not
10136 if (!COMPLETE_TYPE_P (type)
10137 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10140 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10142 if (TREE_CODE (field) != FIELD_DECL)
10145 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10148 count += sub_count;
10151 /* There must be no padding. */
10152 if (wi::to_wide (TYPE_SIZE (type))
10153 != count * GET_MODE_BITSIZE (*modep))
10160 case QUAL_UNION_TYPE:
10162 /* These aren't very interesting except in a degenerate case. */
10167 /* Can't handle incomplete types nor sizes that are not
10169 if (!COMPLETE_TYPE_P (type)
10170 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10173 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10175 if (TREE_CODE (field) != FIELD_DECL)
10178 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10181 count = count > sub_count ? count : sub_count;
10184 /* There must be no padding. */
10185 if (wi::to_wide (TYPE_SIZE (type))
10186 != count * GET_MODE_BITSIZE (*modep))
10199 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10200 float or vector aggregate that shall be passed in FP/vector registers
10201 according to the ELFv2 ABI, return the homogeneous element mode in
10202 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10204 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10207 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10208 machine_mode *elt_mode,
10211 /* Note that we do not accept complex types at the top level as
10212 homogeneous aggregates; these types are handled via the
10213 targetm.calls.split_complex_arg mechanism. Complex types
10214 can be elements of homogeneous aggregates, however. */
10215 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10216 && AGGREGATE_TYPE_P (type))
10218 machine_mode field_mode = VOIDmode;
10219 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10221 if (field_count > 0)
10223 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10224 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10226 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10227 up to AGGR_ARG_NUM_REG registers. */
10228 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10231 *elt_mode = field_mode;
10233 *n_elts = field_count;
10246 /* Return a nonzero value to say to return the function value in
10247 memory, just as large structures are always returned. TYPE will be
10248 the data type of the value, and FNTYPE will be the type of the
10249 function doing the returning, or @code{NULL} for libcalls.
10251 The AIX ABI for the RS/6000 specifies that all structures are
10252 returned in memory. The Darwin ABI does the same.
10254 For the Darwin 64 Bit ABI, a function result can be returned in
10255 registers or in memory, depending on the size of the return data
10256 type. If it is returned in registers, the value occupies the same
10257 registers as it would if it were the first and only function
10258 argument. Otherwise, the function places its result in memory at
10259 the location pointed to by GPR3.
10261 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10262 but a draft put them in memory, and GCC used to implement the draft
10263 instead of the final standard. Therefore, aix_struct_return
10264 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10265 compatibility can change DRAFT_V4_STRUCT_RET to override the
10266 default, and -m switches get the final word. See
10267 rs6000_option_override_internal for more details.
10269 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10270 long double support is enabled. These values are returned in memory.
10272 int_size_in_bytes returns -1 for variable size objects, which go in
10273 memory always. The cast to unsigned makes -1 > 8. */
10276 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10278 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10280 && rs6000_darwin64_abi
10281 && TREE_CODE (type) == RECORD_TYPE
10282 && int_size_in_bytes (type) > 0)
10284 CUMULATIVE_ARGS valcum;
10288 valcum.fregno = FP_ARG_MIN_REG;
10289 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10290 /* Do a trial code generation as if this were going to be passed
10291 as an argument; if any part goes in memory, we return NULL. */
10292 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10295 /* Otherwise fall through to more conventional ABI rules. */
10298 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10299 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10303 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10304 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10305 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10308 if (AGGREGATE_TYPE_P (type)
10309 && (aix_struct_return
10310 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10313 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10314 modes only exist for GCC vector types if -maltivec. */
10315 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10316 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10319 /* Return synthetic vectors in memory. */
10320 if (TREE_CODE (type) == VECTOR_TYPE
10321 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10323 static bool warned_for_return_big_vectors = false;
10324 if (!warned_for_return_big_vectors)
10326 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10327 "non-standard ABI extension with no compatibility "
10329 warned_for_return_big_vectors = true;
10334 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10335 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10341 /* Specify whether values returned in registers should be at the most
10342 significant end of a register. We want aggregates returned by
10343 value to match the way aggregates are passed to functions. */
10346 rs6000_return_in_msb (const_tree valtype)
10348 return (DEFAULT_ABI == ABI_ELFv2
10349 && BYTES_BIG_ENDIAN
10350 && AGGREGATE_TYPE_P (valtype)
10351 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10355 #ifdef HAVE_AS_GNU_ATTRIBUTE
10356 /* Return TRUE if a call to function FNDECL may be one that
10357 potentially affects the function calling ABI of the object file. */
10360 call_ABI_of_interest (tree fndecl)
10362 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10364 struct cgraph_node *c_node;
10366 /* Libcalls are always interesting. */
10367 if (fndecl == NULL_TREE)
10370 /* Any call to an external function is interesting. */
10371 if (DECL_EXTERNAL (fndecl))
10374 /* Interesting functions that we are emitting in this object file. */
10375 c_node = cgraph_node::get (fndecl);
10376 c_node = c_node->ultimate_alias_target ();
10377 return !c_node->only_called_directly_p ();
10383 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10384 for a call to a function whose data type is FNTYPE.
10385 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10387 For incoming args we set the number of arguments in the prototype large
10388 so we never return a PARALLEL. */
10391 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10392 rtx libname ATTRIBUTE_UNUSED, int incoming,
10393 int libcall, int n_named_args,
10395 machine_mode return_mode ATTRIBUTE_UNUSED)
10397 static CUMULATIVE_ARGS zero_cumulative;
10399 *cum = zero_cumulative;
10401 cum->fregno = FP_ARG_MIN_REG;
10402 cum->vregno = ALTIVEC_ARG_MIN_REG;
10403 cum->prototype = (fntype && prototype_p (fntype));
10404 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10405 ? CALL_LIBCALL : CALL_NORMAL);
10406 cum->sysv_gregno = GP_ARG_MIN_REG;
10407 cum->stdarg = stdarg_p (fntype);
10408 cum->libcall = libcall;
10410 cum->nargs_prototype = 0;
10411 if (incoming || cum->prototype)
10412 cum->nargs_prototype = n_named_args;
10414 /* Check for a longcall attribute. */
10415 if ((!fntype && rs6000_default_long_calls)
10417 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10418 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10419 cum->call_cookie |= CALL_LONG;
10420 else if (DEFAULT_ABI != ABI_DARWIN)
10422 bool is_local = (fndecl
10423 && !DECL_EXTERNAL (fndecl)
10424 && !DECL_WEAK (fndecl)
10425 && (*targetm.binds_local_p) (fndecl));
10431 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
10432 cum->call_cookie |= CALL_LONG;
10437 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
10438 cum->call_cookie |= CALL_LONG;
10442 if (TARGET_DEBUG_ARG)
10444 fprintf (stderr, "\ninit_cumulative_args:");
10447 tree ret_type = TREE_TYPE (fntype);
10448 fprintf (stderr, " ret code = %s,",
10449 get_tree_code_name (TREE_CODE (ret_type)));
10452 if (cum->call_cookie & CALL_LONG)
10453 fprintf (stderr, " longcall,");
10455 fprintf (stderr, " proto = %d, nargs = %d\n",
10456 cum->prototype, cum->nargs_prototype);
10459 #ifdef HAVE_AS_GNU_ATTRIBUTE
10460 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10462 cum->escapes = call_ABI_of_interest (fndecl);
10469 return_type = TREE_TYPE (fntype);
10470 return_mode = TYPE_MODE (return_type);
10473 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10475 if (return_type != NULL)
10477 if (TREE_CODE (return_type) == RECORD_TYPE
10478 && TYPE_TRANSPARENT_AGGR (return_type))
10480 return_type = TREE_TYPE (first_field (return_type));
10481 return_mode = TYPE_MODE (return_type);
10483 if (AGGREGATE_TYPE_P (return_type)
10484 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10486 rs6000_returns_struct = true;
10488 if (SCALAR_FLOAT_MODE_P (return_mode))
10490 rs6000_passes_float = true;
10491 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10492 && (FLOAT128_IBM_P (return_mode)
10493 || FLOAT128_IEEE_P (return_mode)
10494 || (return_type != NULL
10495 && (TYPE_MAIN_VARIANT (return_type)
10496 == long_double_type_node))))
10497 rs6000_passes_long_double = true;
10499 /* Note if we passed or return a IEEE 128-bit type. We changed
10500 the mangling for these types, and we may need to make an alias
10501 with the old mangling. */
10502 if (FLOAT128_IEEE_P (return_mode))
10503 rs6000_passes_ieee128 = true;
10505 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10506 rs6000_passes_vector = true;
10513 && TARGET_ALTIVEC_ABI
10514 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10516 error ("cannot return value in vector register because"
10517 " altivec instructions are disabled, use %qs"
10518 " to enable them", "-maltivec");
10522 /* The mode the ABI uses for a word. This is not the same as word_mode
10523 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10525 static scalar_int_mode
10526 rs6000_abi_word_mode (void)
10528 return TARGET_32BIT ? SImode : DImode;
10531 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10533 rs6000_offload_options (void)
10536 return xstrdup ("-foffload-abi=lp64");
10538 return xstrdup ("-foffload-abi=ilp32");
10541 /* On rs6000, function arguments are promoted, as are function return
10544 static machine_mode
10545 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10547 int *punsignedp ATTRIBUTE_UNUSED,
10550 PROMOTE_MODE (mode, *punsignedp, type);
10555 /* Return true if TYPE must be passed on the stack and not in registers. */
10558 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10560 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10561 return must_pass_in_stack_var_size (mode, type);
10563 return must_pass_in_stack_var_size_or_pad (mode, type);
10567 is_complex_IBM_long_double (machine_mode mode)
10569 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10572 /* Whether ABI_V4 passes MODE args to a function in floating point
10576 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10578 if (!TARGET_HARD_FLOAT)
10580 if (mode == DFmode)
10582 if (mode == SFmode && named)
10584 /* ABI_V4 passes complex IBM long double in 8 gprs.
10585 Stupid, but we can't change the ABI now. */
10586 if (is_complex_IBM_long_double (mode))
10588 if (FLOAT128_2REG_P (mode))
10590 if (DECIMAL_FLOAT_MODE_P (mode))
10595 /* Implement TARGET_FUNCTION_ARG_PADDING.
10597 For the AIX ABI structs are always stored left shifted in their
10600 static pad_direction
10601 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10603 #ifndef AGGREGATE_PADDING_FIXED
10604 #define AGGREGATE_PADDING_FIXED 0
10606 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10607 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10610 if (!AGGREGATE_PADDING_FIXED)
10612 /* GCC used to pass structures of the same size as integer types as
10613 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10614 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10615 passed padded downward, except that -mstrict-align further
10616 muddied the water in that multi-component structures of 2 and 4
10617 bytes in size were passed padded upward.
10619 The following arranges for best compatibility with previous
10620 versions of gcc, but removes the -mstrict-align dependency. */
10621 if (BYTES_BIG_ENDIAN)
10623 HOST_WIDE_INT size = 0;
10625 if (mode == BLKmode)
10627 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10628 size = int_size_in_bytes (type);
10631 size = GET_MODE_SIZE (mode);
10633 if (size == 1 || size == 2 || size == 4)
10634 return PAD_DOWNWARD;
10639 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10641 if (type != 0 && AGGREGATE_TYPE_P (type))
10645 /* Fall back to the default. */
10646 return default_function_arg_padding (mode, type);
10649 /* If defined, a C expression that gives the alignment boundary, in bits,
10650 of an argument with the specified mode and type. If it is not defined,
10651 PARM_BOUNDARY is used for all arguments.
10653 V.4 wants long longs and doubles to be double word aligned. Just
10654 testing the mode size is a boneheaded way to do this as it means
10655 that other types such as complex int are also double word aligned.
10656 However, we're stuck with this because changing the ABI might break
10657 existing library interfaces.
10659 Quadword align Altivec/VSX vectors.
10660 Quadword align large synthetic vector types. */
10662 static unsigned int
10663 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10665 machine_mode elt_mode;
10668 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10670 if (DEFAULT_ABI == ABI_V4
10671 && (GET_MODE_SIZE (mode) == 8
10672 || (TARGET_HARD_FLOAT
10673 && !is_complex_IBM_long_double (mode)
10674 && FLOAT128_2REG_P (mode))))
10676 else if (FLOAT128_VECTOR_P (mode))
10678 else if (type && TREE_CODE (type) == VECTOR_TYPE
10679 && int_size_in_bytes (type) >= 8
10680 && int_size_in_bytes (type) < 16)
10682 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10683 || (type && TREE_CODE (type) == VECTOR_TYPE
10684 && int_size_in_bytes (type) >= 16))
10687 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10688 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10689 -mcompat-align-parm is used. */
10690 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10691 || DEFAULT_ABI == ABI_ELFv2)
10692 && type && TYPE_ALIGN (type) > 64)
10694 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10695 or homogeneous float/vector aggregates here. We already handled
10696 vector aggregates above, but still need to check for float here. */
10697 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10698 && !SCALAR_FLOAT_MODE_P (elt_mode));
10700 /* We used to check for BLKmode instead of the above aggregate type
10701 check. Warn when this results in any difference to the ABI. */
10702 if (aggregate_p != (mode == BLKmode))
10704 static bool warned;
10705 if (!warned && warn_psabi)
10708 inform (input_location,
10709 "the ABI of passing aggregates with %d-byte alignment"
10710 " has changed in GCC 5",
10711 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10719 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10720 implement the "aggregate type" check as a BLKmode check here; this
10721 means certain aggregate types are in fact not aligned. */
10722 if (TARGET_MACHO && rs6000_darwin64_abi
10724 && type && TYPE_ALIGN (type) > 64)
10727 return PARM_BOUNDARY;
10730 /* The offset in words to the start of the parameter save area. */
10732 static unsigned int
10733 rs6000_parm_offset (void)
10735 return (DEFAULT_ABI == ABI_V4 ? 2
10736 : DEFAULT_ABI == ABI_ELFv2 ? 4
10740 /* For a function parm of MODE and TYPE, return the starting word in
10741 the parameter area. NWORDS of the parameter area are already used. */
10743 static unsigned int
10744 rs6000_parm_start (machine_mode mode, const_tree type,
10745 unsigned int nwords)
10747 unsigned int align;
10749 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
10750 return nwords + (-(rs6000_parm_offset () + nwords) & align);
10753 /* Compute the size (in words) of a function argument. */
10755 static unsigned long
10756 rs6000_arg_size (machine_mode mode, const_tree type)
10758 unsigned long size;
10760 if (mode != BLKmode)
10761 size = GET_MODE_SIZE (mode);
10763 size = int_size_in_bytes (type);
10766 return (size + 3) >> 2;
10768 return (size + 7) >> 3;
10771 /* Use this to flush pending int fields. */
10774 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
10775 HOST_WIDE_INT bitpos, int final)
10777 unsigned int startbit, endbit;
10778 int intregs, intoffset;
10780 /* Handle the situations where a float is taking up the first half
10781 of the GPR, and the other half is empty (typically due to
10782 alignment restrictions). We can detect this by a 8-byte-aligned
10783 int field, or by seeing that this is the final flush for this
10784 argument. Count the word and continue on. */
10785 if (cum->floats_in_gpr == 1
10786 && (cum->intoffset % 64 == 0
10787 || (cum->intoffset == -1 && final)))
10790 cum->floats_in_gpr = 0;
10793 if (cum->intoffset == -1)
10796 intoffset = cum->intoffset;
10797 cum->intoffset = -1;
10798 cum->floats_in_gpr = 0;
10800 if (intoffset % BITS_PER_WORD != 0)
10802 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
10803 if (!int_mode_for_size (bits, 0).exists ())
10805 /* We couldn't find an appropriate mode, which happens,
10806 e.g., in packed structs when there are 3 bytes to load.
10807 Back intoffset back to the beginning of the word in this
10809 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
10813 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
10814 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
10815 intregs = (endbit - startbit) / BITS_PER_WORD;
10816 cum->words += intregs;
10817 /* words should be unsigned. */
10818 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
10820 int pad = (endbit/BITS_PER_WORD) - cum->words;
10825 /* The darwin64 ABI calls for us to recurse down through structs,
10826 looking for elements passed in registers. Unfortunately, we have
10827 to track int register count here also because of misalignments
10828 in powerpc alignment mode. */
10831 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
10833 HOST_WIDE_INT startbitpos)
10837 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10838 if (TREE_CODE (f) == FIELD_DECL)
10840 HOST_WIDE_INT bitpos = startbitpos;
10841 tree ftype = TREE_TYPE (f);
10843 if (ftype == error_mark_node)
10845 mode = TYPE_MODE (ftype);
10847 if (DECL_SIZE (f) != 0
10848 && tree_fits_uhwi_p (bit_position (f)))
10849 bitpos += int_bit_position (f);
10851 /* ??? FIXME: else assume zero offset. */
10853 if (TREE_CODE (ftype) == RECORD_TYPE)
10854 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
10855 else if (USE_FP_FOR_ARG_P (cum, mode))
10857 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
10858 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10859 cum->fregno += n_fpregs;
10860 /* Single-precision floats present a special problem for
10861 us, because they are smaller than an 8-byte GPR, and so
10862 the structure-packing rules combined with the standard
10863 varargs behavior mean that we want to pack float/float
10864 and float/int combinations into a single register's
10865 space. This is complicated by the arg advance flushing,
10866 which works on arbitrarily large groups of int-type
10868 if (mode == SFmode)
10870 if (cum->floats_in_gpr == 1)
10872 /* Two floats in a word; count the word and reset
10873 the float count. */
10875 cum->floats_in_gpr = 0;
10877 else if (bitpos % 64 == 0)
10879 /* A float at the beginning of an 8-byte word;
10880 count it and put off adjusting cum->words until
10881 we see if a arg advance flush is going to do it
10883 cum->floats_in_gpr++;
10887 /* The float is at the end of a word, preceded
10888 by integer fields, so the arg advance flush
10889 just above has already set cum->words and
10890 everything is taken care of. */
10894 cum->words += n_fpregs;
10896 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10898 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10902 else if (cum->intoffset == -1)
10903 cum->intoffset = bitpos;
10907 /* Check for an item that needs to be considered specially under the darwin 64
10908 bit ABI. These are record types where the mode is BLK or the structure is
10909 8 bytes in size. */
10911 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
10913 return rs6000_darwin64_abi
10914 && ((mode == BLKmode
10915 && TREE_CODE (type) == RECORD_TYPE
10916 && int_size_in_bytes (type) > 0)
10917 || (type && TREE_CODE (type) == RECORD_TYPE
10918 && int_size_in_bytes (type) == 8)) ? 1 : 0;
10921 /* Update the data in CUM to advance over an argument
10922 of mode MODE and data type TYPE.
10923 (TYPE is null for libcalls where that information may not be available.)
10925 Note that for args passed by reference, function_arg will be called
10926 with MODE and TYPE set to that of the pointer to the arg, not the arg
10930 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
10931 const_tree type, bool named, int depth)
10933 machine_mode elt_mode;
10936 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10938 /* Only tick off an argument if we're not recursing. */
10940 cum->nargs_prototype--;
10942 #ifdef HAVE_AS_GNU_ATTRIBUTE
10943 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
10946 if (SCALAR_FLOAT_MODE_P (mode))
10948 rs6000_passes_float = true;
10949 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10950 && (FLOAT128_IBM_P (mode)
10951 || FLOAT128_IEEE_P (mode)
10953 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
10954 rs6000_passes_long_double = true;
10956 /* Note if we passed or return a IEEE 128-bit type. We changed the
10957 mangling for these types, and we may need to make an alias with
10958 the old mangling. */
10959 if (FLOAT128_IEEE_P (mode))
10960 rs6000_passes_ieee128 = true;
10962 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
10963 rs6000_passes_vector = true;
10967 if (TARGET_ALTIVEC_ABI
10968 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10969 || (type && TREE_CODE (type) == VECTOR_TYPE
10970 && int_size_in_bytes (type) == 16)))
10972 bool stack = false;
10974 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10976 cum->vregno += n_elts;
10978 if (!TARGET_ALTIVEC)
10979 error ("cannot pass argument in vector register because"
10980 " altivec instructions are disabled, use %qs"
10981 " to enable them", "-maltivec");
10983 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
10984 even if it is going to be passed in a vector register.
10985 Darwin does the same for variable-argument functions. */
10986 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10988 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
10998 /* Vector parameters must be 16-byte aligned. In 32-bit
10999 mode this means we need to take into account the offset
11000 to the parameter save area. In 64-bit mode, they just
11001 have to start on an even word, since the parameter save
11002 area is 16-byte aligned. */
11004 align = -(rs6000_parm_offset () + cum->words) & 3;
11006 align = cum->words & 1;
11007 cum->words += align + rs6000_arg_size (mode, type);
11009 if (TARGET_DEBUG_ARG)
11011 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11012 cum->words, align);
11013 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11014 cum->nargs_prototype, cum->prototype,
11015 GET_MODE_NAME (mode));
11019 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11021 int size = int_size_in_bytes (type);
11022 /* Variable sized types have size == -1 and are
11023 treated as if consisting entirely of ints.
11024 Pad to 16 byte boundary if needed. */
11025 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11026 && (cum->words % 2) != 0)
11028 /* For varargs, we can just go up by the size of the struct. */
11030 cum->words += (size + 7) / 8;
11033 /* It is tempting to say int register count just goes up by
11034 sizeof(type)/8, but this is wrong in a case such as
11035 { int; double; int; } [powerpc alignment]. We have to
11036 grovel through the fields for these too. */
11037 cum->intoffset = 0;
11038 cum->floats_in_gpr = 0;
11039 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11040 rs6000_darwin64_record_arg_advance_flush (cum,
11041 size * BITS_PER_UNIT, 1);
11043 if (TARGET_DEBUG_ARG)
11045 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11046 cum->words, TYPE_ALIGN (type), size);
11048 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11049 cum->nargs_prototype, cum->prototype,
11050 GET_MODE_NAME (mode));
11053 else if (DEFAULT_ABI == ABI_V4)
11055 if (abi_v4_pass_in_fpr (mode, named))
11057 /* _Decimal128 must use an even/odd register pair. This assumes
11058 that the register number is odd when fregno is odd. */
11059 if (mode == TDmode && (cum->fregno % 2) == 1)
11062 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11063 <= FP_ARG_V4_MAX_REG)
11064 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11067 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11068 if (mode == DFmode || FLOAT128_IBM_P (mode)
11069 || mode == DDmode || mode == TDmode)
11070 cum->words += cum->words & 1;
11071 cum->words += rs6000_arg_size (mode, type);
11076 int n_words = rs6000_arg_size (mode, type);
11077 int gregno = cum->sysv_gregno;
11079 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11080 As does any other 2 word item such as complex int due to a
11081 historical mistake. */
11083 gregno += (1 - gregno) & 1;
11085 /* Multi-reg args are not split between registers and stack. */
11086 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11088 /* Long long is aligned on the stack. So are other 2 word
11089 items such as complex int due to a historical mistake. */
11091 cum->words += cum->words & 1;
11092 cum->words += n_words;
11095 /* Note: continuing to accumulate gregno past when we've started
11096 spilling to the stack indicates the fact that we've started
11097 spilling to the stack to expand_builtin_saveregs. */
11098 cum->sysv_gregno = gregno + n_words;
11101 if (TARGET_DEBUG_ARG)
11103 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11104 cum->words, cum->fregno);
11105 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11106 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11107 fprintf (stderr, "mode = %4s, named = %d\n",
11108 GET_MODE_NAME (mode), named);
11113 int n_words = rs6000_arg_size (mode, type);
11114 int start_words = cum->words;
11115 int align_words = rs6000_parm_start (mode, type, start_words);
11117 cum->words = align_words + n_words;
11119 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11121 /* _Decimal128 must be passed in an even/odd float register pair.
11122 This assumes that the register number is odd when fregno is
11124 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11126 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11129 if (TARGET_DEBUG_ARG)
11131 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11132 cum->words, cum->fregno);
11133 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11134 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11135 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11136 named, align_words - start_words, depth);
11142 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11143 const_tree type, bool named)
11145 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11149 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11150 structure between cum->intoffset and bitpos to integer registers. */
11153 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11154 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11157 unsigned int regno;
11158 unsigned int startbit, endbit;
11159 int this_regno, intregs, intoffset;
11162 if (cum->intoffset == -1)
11165 intoffset = cum->intoffset;
11166 cum->intoffset = -1;
11168 /* If this is the trailing part of a word, try to only load that
11169 much into the register. Otherwise load the whole register. Note
11170 that in the latter case we may pick up unwanted bits. It's not a
11171 problem at the moment but may wish to revisit. */
11173 if (intoffset % BITS_PER_WORD != 0)
11175 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11176 if (!int_mode_for_size (bits, 0).exists (&mode))
11178 /* We couldn't find an appropriate mode, which happens,
11179 e.g., in packed structs when there are 3 bytes to load.
11180 Back intoffset back to the beginning of the word in this
11182 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11189 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11190 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11191 intregs = (endbit - startbit) / BITS_PER_WORD;
11192 this_regno = cum->words + intoffset / BITS_PER_WORD;
11194 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11195 cum->use_stack = 1;
11197 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11201 intoffset /= BITS_PER_UNIT;
11204 regno = GP_ARG_MIN_REG + this_regno;
11205 reg = gen_rtx_REG (mode, regno);
11207 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11210 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11214 while (intregs > 0);
11217 /* Recursive workhorse for the following. */
11220 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11221 HOST_WIDE_INT startbitpos, rtx rvec[],
11226 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11227 if (TREE_CODE (f) == FIELD_DECL)
11229 HOST_WIDE_INT bitpos = startbitpos;
11230 tree ftype = TREE_TYPE (f);
11232 if (ftype == error_mark_node)
11234 mode = TYPE_MODE (ftype);
11236 if (DECL_SIZE (f) != 0
11237 && tree_fits_uhwi_p (bit_position (f)))
11238 bitpos += int_bit_position (f);
11240 /* ??? FIXME: else assume zero offset. */
11242 if (TREE_CODE (ftype) == RECORD_TYPE)
11243 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11244 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11246 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11250 case E_SCmode: mode = SFmode; break;
11251 case E_DCmode: mode = DFmode; break;
11252 case E_TCmode: mode = TFmode; break;
11256 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11257 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11259 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11260 && (mode == TFmode || mode == TDmode));
11261 /* Long double or _Decimal128 split over regs and memory. */
11262 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11266 = gen_rtx_EXPR_LIST (VOIDmode,
11267 gen_rtx_REG (mode, cum->fregno++),
11268 GEN_INT (bitpos / BITS_PER_UNIT));
11269 if (FLOAT128_2REG_P (mode))
11272 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11274 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11276 = gen_rtx_EXPR_LIST (VOIDmode,
11277 gen_rtx_REG (mode, cum->vregno++),
11278 GEN_INT (bitpos / BITS_PER_UNIT));
11280 else if (cum->intoffset == -1)
11281 cum->intoffset = bitpos;
11285 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11286 the register(s) to be used for each field and subfield of a struct
11287 being passed by value, along with the offset of where the
11288 register's value may be found in the block. FP fields go in FP
11289 register, vector fields go in vector registers, and everything
11290 else goes in int registers, packed as in memory.
11292 This code is also used for function return values. RETVAL indicates
11293 whether this is the case.
11295 Much of this is taken from the SPARC V9 port, which has a similar
11296 calling convention. */
11299 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11300 bool named, bool retval)
11302 rtx rvec[FIRST_PSEUDO_REGISTER];
11303 int k = 1, kbase = 1;
11304 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11305 /* This is a copy; modifications are not visible to our caller. */
11306 CUMULATIVE_ARGS copy_cum = *orig_cum;
11307 CUMULATIVE_ARGS *cum = ©_cum;
11309 /* Pad to 16 byte boundary if needed. */
11310 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11311 && (cum->words % 2) != 0)
11314 cum->intoffset = 0;
11315 cum->use_stack = 0;
11316 cum->named = named;
11318 /* Put entries into rvec[] for individual FP and vector fields, and
11319 for the chunks of memory that go in int regs. Note we start at
11320 element 1; 0 is reserved for an indication of using memory, and
11321 may or may not be filled in below. */
11322 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11323 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11325 /* If any part of the struct went on the stack put all of it there.
11326 This hack is because the generic code for
11327 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11328 parts of the struct are not at the beginning. */
11329 if (cum->use_stack)
11332 return NULL_RTX; /* doesn't go in registers at all */
11334 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11336 if (k > 1 || cum->use_stack)
11337 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11342 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11345 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11350 rtx rvec[GP_ARG_NUM_REG + 1];
11352 if (align_words >= GP_ARG_NUM_REG)
11355 n_units = rs6000_arg_size (mode, type);
11357 /* Optimize the simple case where the arg fits in one gpr, except in
11358 the case of BLKmode due to assign_parms assuming that registers are
11359 BITS_PER_WORD wide. */
11361 || (n_units == 1 && mode != BLKmode))
11362 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11365 if (align_words + n_units > GP_ARG_NUM_REG)
11366 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11367 using a magic NULL_RTX component.
11368 This is not strictly correct. Only some of the arg belongs in
11369 memory, not all of it. However, the normal scheme using
11370 function_arg_partial_nregs can result in unusual subregs, eg.
11371 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11372 store the whole arg to memory is often more efficient than code
11373 to store pieces, and we know that space is available in the right
11374 place for the whole arg. */
11375 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11380 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11381 rtx off = GEN_INT (i++ * 4);
11382 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11384 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11386 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11389 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11390 but must also be copied into the parameter save area starting at
11391 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11392 to the GPRs and/or memory. Return the number of elements used. */
11395 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11396 int align_words, rtx *rvec)
11400 if (align_words < GP_ARG_NUM_REG)
11402 int n_words = rs6000_arg_size (mode, type);
11404 if (align_words + n_words > GP_ARG_NUM_REG
11406 || (TARGET_32BIT && TARGET_POWERPC64))
11408 /* If this is partially on the stack, then we only
11409 include the portion actually in registers here. */
11410 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11413 if (align_words + n_words > GP_ARG_NUM_REG)
11415 /* Not all of the arg fits in gprs. Say that it goes in memory
11416 too, using a magic NULL_RTX component. Also see comment in
11417 rs6000_mixed_function_arg for why the normal
11418 function_arg_partial_nregs scheme doesn't work in this case. */
11419 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11424 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11425 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11426 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11428 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11432 /* The whole arg fits in gprs. */
11433 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11434 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11439 /* It's entirely in memory. */
11440 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11446 /* RVEC is a vector of K components of an argument of mode MODE.
11447 Construct the final function_arg return value from it. */
11450 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11452 gcc_assert (k >= 1);
11454 /* Avoid returning a PARALLEL in the trivial cases. */
11457 if (XEXP (rvec[0], 0) == NULL_RTX)
11460 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11461 return XEXP (rvec[0], 0);
11464 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11467 /* Determine where to put an argument to a function.
11468 Value is zero to push the argument on the stack,
11469 or a hard register in which to store the argument.
11471 MODE is the argument's machine mode.
11472 TYPE is the data type of the argument (as a tree).
11473 This is null for libcalls where that information may
11475 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11476 the preceding args and about the function being called. It is
11477 not modified in this routine.
11478 NAMED is nonzero if this argument is a named parameter
11479 (otherwise it is an extra parameter matching an ellipsis).
11481 On RS/6000 the first eight words of non-FP are normally in registers
11482 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11483 Under V.4, the first 8 FP args are in registers.
11485 If this is floating-point and no prototype is specified, we use
11486 both an FP and integer register (or possibly FP reg and stack). Library
11487 functions (when CALL_LIBCALL is set) always have the proper types for args,
11488 so we can pass the FP value just in one register. emit_library_function
11489 doesn't support PARALLEL anyway.
11491 Note that for args passed by reference, function_arg will be called
11492 with MODE and TYPE set to that of the pointer to the arg, not the arg
11496 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11497 const_tree type, bool named)
11499 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11500 enum rs6000_abi abi = DEFAULT_ABI;
11501 machine_mode elt_mode;
11504 /* Return a marker to indicate whether CR1 needs to set or clear the
11505 bit that V.4 uses to say fp args were passed in registers.
11506 Assume that we don't need the marker for software floating point,
11507 or compiler generated library calls. */
11508 if (mode == VOIDmode)
11511 && (cum->call_cookie & CALL_LIBCALL) == 0
11513 || (cum->nargs_prototype < 0
11514 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11515 && TARGET_HARD_FLOAT)
11516 return GEN_INT (cum->call_cookie
11517 | ((cum->fregno == FP_ARG_MIN_REG)
11518 ? CALL_V4_SET_FP_ARGS
11519 : CALL_V4_CLEAR_FP_ARGS));
11521 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11524 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11526 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11528 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11529 if (rslt != NULL_RTX)
11531 /* Else fall through to usual handling. */
11534 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11536 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11540 /* Do we also need to pass this argument in the parameter save area?
11541 Library support functions for IEEE 128-bit are assumed to not need the
11542 value passed both in GPRs and in vector registers. */
11543 if (TARGET_64BIT && !cum->prototype
11544 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11546 int align_words = ROUND_UP (cum->words, 2);
11547 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11550 /* Describe where this argument goes in the vector registers. */
11551 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11553 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11554 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11555 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11558 return rs6000_finish_function_arg (mode, rvec, k);
11560 else if (TARGET_ALTIVEC_ABI
11561 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11562 || (type && TREE_CODE (type) == VECTOR_TYPE
11563 && int_size_in_bytes (type) == 16)))
11565 if (named || abi == ABI_V4)
11569 /* Vector parameters to varargs functions under AIX or Darwin
11570 get passed in memory and possibly also in GPRs. */
11571 int align, align_words, n_words;
11572 machine_mode part_mode;
11574 /* Vector parameters must be 16-byte aligned. In 32-bit
11575 mode this means we need to take into account the offset
11576 to the parameter save area. In 64-bit mode, they just
11577 have to start on an even word, since the parameter save
11578 area is 16-byte aligned. */
11580 align = -(rs6000_parm_offset () + cum->words) & 3;
11582 align = cum->words & 1;
11583 align_words = cum->words + align;
11585 /* Out of registers? Memory, then. */
11586 if (align_words >= GP_ARG_NUM_REG)
11589 if (TARGET_32BIT && TARGET_POWERPC64)
11590 return rs6000_mixed_function_arg (mode, type, align_words);
11592 /* The vector value goes in GPRs. Only the part of the
11593 value in GPRs is reported here. */
11595 n_words = rs6000_arg_size (mode, type);
11596 if (align_words + n_words > GP_ARG_NUM_REG)
11597 /* Fortunately, there are only two possibilities, the value
11598 is either wholly in GPRs or half in GPRs and half not. */
11599 part_mode = DImode;
11601 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11605 else if (abi == ABI_V4)
11607 if (abi_v4_pass_in_fpr (mode, named))
11609 /* _Decimal128 must use an even/odd register pair. This assumes
11610 that the register number is odd when fregno is odd. */
11611 if (mode == TDmode && (cum->fregno % 2) == 1)
11614 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11615 <= FP_ARG_V4_MAX_REG)
11616 return gen_rtx_REG (mode, cum->fregno);
11622 int n_words = rs6000_arg_size (mode, type);
11623 int gregno = cum->sysv_gregno;
11625 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11626 As does any other 2 word item such as complex int due to a
11627 historical mistake. */
11629 gregno += (1 - gregno) & 1;
11631 /* Multi-reg args are not split between registers and stack. */
11632 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11635 if (TARGET_32BIT && TARGET_POWERPC64)
11636 return rs6000_mixed_function_arg (mode, type,
11637 gregno - GP_ARG_MIN_REG);
11638 return gen_rtx_REG (mode, gregno);
11643 int align_words = rs6000_parm_start (mode, type, cum->words);
11645 /* _Decimal128 must be passed in an even/odd float register pair.
11646 This assumes that the register number is odd when fregno is odd. */
11647 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11650 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11651 && !(TARGET_AIX && !TARGET_ELF
11652 && type != NULL && AGGREGATE_TYPE_P (type)))
11654 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11657 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11660 /* Do we also need to pass this argument in the parameter
11662 if (type && (cum->nargs_prototype <= 0
11663 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11664 && TARGET_XL_COMPAT
11665 && align_words >= GP_ARG_NUM_REG)))
11666 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11668 /* Describe where this argument goes in the fprs. */
11669 for (i = 0; i < n_elts
11670 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11672 /* Check if the argument is split over registers and memory.
11673 This can only ever happen for long double or _Decimal128;
11674 complex types are handled via split_complex_arg. */
11675 machine_mode fmode = elt_mode;
11676 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11678 gcc_assert (FLOAT128_2REG_P (fmode));
11679 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11682 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11683 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11684 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11687 /* If there were not enough FPRs to hold the argument, the rest
11688 usually goes into memory. However, if the current position
11689 is still within the register parameter area, a portion may
11690 actually have to go into GPRs.
11692 Note that it may happen that the portion of the argument
11693 passed in the first "half" of the first GPR was already
11694 passed in the last FPR as well.
11696 For unnamed arguments, we already set up GPRs to cover the
11697 whole argument in rs6000_psave_function_arg, so there is
11698 nothing further to do at this point. */
11699 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11700 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11701 && cum->nargs_prototype > 0)
11703 static bool warned;
11705 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11706 int n_words = rs6000_arg_size (mode, type);
11708 align_words += fpr_words;
11709 n_words -= fpr_words;
11713 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11714 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11715 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11717 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11719 if (!warned && warn_psabi)
11722 inform (input_location,
11723 "the ABI of passing homogeneous %<float%> aggregates"
11724 " has changed in GCC 5");
11728 return rs6000_finish_function_arg (mode, rvec, k);
11730 else if (align_words < GP_ARG_NUM_REG)
11732 if (TARGET_32BIT && TARGET_POWERPC64)
11733 return rs6000_mixed_function_arg (mode, type, align_words);
11735 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11742 /* For an arg passed partly in registers and partly in memory, this is
11743 the number of bytes passed in registers. For args passed entirely in
11744 registers or entirely in memory, zero. When an arg is described by a
11745 PARALLEL, perhaps using more than one register type, this function
11746 returns the number of bytes used by the first element of the PARALLEL. */
11749 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11750 tree type, bool named)
11752 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11753 bool passed_in_gprs = true;
11756 machine_mode elt_mode;
11759 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11761 if (DEFAULT_ABI == ABI_V4)
11764 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11766 /* If we are passing this arg in the fixed parameter save area (gprs or
11767 memory) as well as VRs, we do not use the partial bytes mechanism;
11768 instead, rs6000_function_arg will return a PARALLEL including a memory
11769 element as necessary. Library support functions for IEEE 128-bit are
11770 assumed to not need the value passed both in GPRs and in vector
11772 if (TARGET_64BIT && !cum->prototype
11773 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11776 /* Otherwise, we pass in VRs only. Check for partial copies. */
11777 passed_in_gprs = false;
11778 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
11779 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
11782 /* In this complicated case we just disable the partial_nregs code. */
11783 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11786 align_words = rs6000_parm_start (mode, type, cum->words);
11788 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11789 && !(TARGET_AIX && !TARGET_ELF
11790 && type != NULL && AGGREGATE_TYPE_P (type)))
11792 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11794 /* If we are passing this arg in the fixed parameter save area
11795 (gprs or memory) as well as FPRs, we do not use the partial
11796 bytes mechanism; instead, rs6000_function_arg will return a
11797 PARALLEL including a memory element as necessary. */
11799 && (cum->nargs_prototype <= 0
11800 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11801 && TARGET_XL_COMPAT
11802 && align_words >= GP_ARG_NUM_REG)))
11805 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11806 passed_in_gprs = false;
11807 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
11809 /* Compute number of bytes / words passed in FPRs. If there
11810 is still space available in the register parameter area
11811 *after* that amount, a part of the argument will be passed
11812 in GPRs. In that case, the total amount passed in any
11813 registers is equal to the amount that would have been passed
11814 in GPRs if everything were passed there, so we fall back to
11815 the GPR code below to compute the appropriate value. */
11816 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
11817 * MIN (8, GET_MODE_SIZE (elt_mode)));
11818 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
11820 if (align_words + fpr_words < GP_ARG_NUM_REG)
11821 passed_in_gprs = true;
11828 && align_words < GP_ARG_NUM_REG
11829 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
11830 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
11832 if (ret != 0 && TARGET_DEBUG_ARG)
11833 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
11838 /* A C expression that indicates when an argument must be passed by
11839 reference. If nonzero for an argument, a copy of that argument is
11840 made in memory and a pointer to the argument is passed instead of
11841 the argument itself. The pointer is passed in whatever way is
11842 appropriate for passing a pointer to that type.
11844 Under V.4, aggregates and long double are passed by reference.
11846 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11847 reference unless the AltiVec vector extension ABI is in force.
11849 As an extension to all ABIs, variable sized types are passed by
11853 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
11854 machine_mode mode, const_tree type,
11855 bool named ATTRIBUTE_UNUSED)
11860 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11861 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11863 if (TARGET_DEBUG_ARG)
11864 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11868 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
11870 if (TARGET_DEBUG_ARG)
11871 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
11875 if (int_size_in_bytes (type) < 0)
11877 if (TARGET_DEBUG_ARG)
11878 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
11882 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11883 modes only exist for GCC vector types if -maltivec. */
11884 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11886 if (TARGET_DEBUG_ARG)
11887 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
11891 /* Pass synthetic vectors in memory. */
11892 if (TREE_CODE (type) == VECTOR_TYPE
11893 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11895 static bool warned_for_pass_big_vectors = false;
11896 if (TARGET_DEBUG_ARG)
11897 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
11898 if (!warned_for_pass_big_vectors)
11900 warning (OPT_Wpsabi, "GCC vector passed by reference: "
11901 "non-standard ABI extension with no compatibility "
11903 warned_for_pass_big_vectors = true;
11911 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11912 already processes. Return true if the parameter must be passed
11913 (fully or partially) on the stack. */
11916 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
11922 /* Catch errors. */
11923 if (type == NULL || type == error_mark_node)
11926 /* Handle types with no storage requirement. */
11927 if (TYPE_MODE (type) == VOIDmode)
11930 /* Handle complex types. */
11931 if (TREE_CODE (type) == COMPLEX_TYPE)
11932 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
11933 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
11935 /* Handle transparent aggregates. */
11936 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
11937 && TYPE_TRANSPARENT_AGGR (type))
11938 type = TREE_TYPE (first_field (type));
11940 /* See if this arg was passed by invisible reference. */
11941 if (pass_by_reference (get_cumulative_args (args_so_far),
11942 TYPE_MODE (type), type, true))
11943 type = build_pointer_type (type);
11945 /* Find mode as it is passed by the ABI. */
11946 unsignedp = TYPE_UNSIGNED (type);
11947 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
11949 /* If we must pass in stack, we need a stack. */
11950 if (rs6000_must_pass_in_stack (mode, type))
11953 /* If there is no incoming register, we need a stack. */
11954 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
11955 if (entry_parm == NULL)
11958 /* Likewise if we need to pass both in registers and on the stack. */
11959 if (GET_CODE (entry_parm) == PARALLEL
11960 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
11963 /* Also true if we're partially in registers and partially not. */
11964 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
11967 /* Update info on where next arg arrives in registers. */
11968 rs6000_function_arg_advance (args_so_far, mode, type, true);
11972 /* Return true if FUN has no prototype, has a variable argument
11973 list, or passes any parameter in memory. */
11976 rs6000_function_parms_need_stack (tree fun, bool incoming)
11978 tree fntype, result;
11979 CUMULATIVE_ARGS args_so_far_v;
11980 cumulative_args_t args_so_far;
11983 /* Must be a libcall, all of which only use reg parms. */
11988 fntype = TREE_TYPE (fun);
11990 /* Varargs functions need the parameter save area. */
11991 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
11994 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
11995 args_so_far = pack_cumulative_args (&args_so_far_v);
11997 /* When incoming, we will have been passed the function decl.
11998 It is necessary to use the decl to handle K&R style functions,
11999 where TYPE_ARG_TYPES may not be available. */
12002 gcc_assert (DECL_P (fun));
12003 result = DECL_RESULT (fun);
12006 result = TREE_TYPE (fntype);
12008 if (result && aggregate_value_p (result, fntype))
12010 if (!TYPE_P (result))
12011 result = TREE_TYPE (result);
12012 result = build_pointer_type (result);
12013 rs6000_parm_needs_stack (args_so_far, result);
12020 for (parm = DECL_ARGUMENTS (fun);
12021 parm && parm != void_list_node;
12022 parm = TREE_CHAIN (parm))
12023 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12028 function_args_iterator args_iter;
12031 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12032 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12039 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12040 usually a constant depending on the ABI. However, in the ELFv2 ABI
12041 the register parameter area is optional when calling a function that
12042 has a prototype is scope, has no variable argument list, and passes
12043 all parameters in registers. */
12046 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12048 int reg_parm_stack_space;
12050 switch (DEFAULT_ABI)
12053 reg_parm_stack_space = 0;
12058 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12062 /* ??? Recomputing this every time is a bit expensive. Is there
12063 a place to cache this information? */
12064 if (rs6000_function_parms_need_stack (fun, incoming))
12065 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12067 reg_parm_stack_space = 0;
12071 return reg_parm_stack_space;
12075 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12078 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12083 for (i = 0; i < nregs; i++)
12085 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12086 if (reload_completed)
12088 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12091 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12092 i * GET_MODE_SIZE (reg_mode));
12095 tem = replace_equiv_address (tem, XEXP (tem, 0));
12099 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12103 /* Perform any needed actions needed for a function that is receiving a
12104 variable number of arguments.
12108 MODE and TYPE are the mode and type of the current parameter.
12110 PRETEND_SIZE is a variable that should be set to the amount of stack
12111 that must be pushed by the prolog to pretend that our caller pushed
12114 Normally, this macro will push all remaining incoming registers on the
12115 stack and set PRETEND_SIZE to the length of the registers pushed. */
12118 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12119 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12122 CUMULATIVE_ARGS next_cum;
12123 int reg_size = TARGET_32BIT ? 4 : 8;
12124 rtx save_area = NULL_RTX, mem;
12125 int first_reg_offset;
12126 alias_set_type set;
12128 /* Skip the last named argument. */
12129 next_cum = *get_cumulative_args (cum);
12130 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12132 if (DEFAULT_ABI == ABI_V4)
12134 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12138 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12139 HOST_WIDE_INT offset = 0;
12141 /* Try to optimize the size of the varargs save area.
12142 The ABI requires that ap.reg_save_area is doubleword
12143 aligned, but we don't need to allocate space for all
12144 the bytes, only those to which we actually will save
12146 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12147 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12148 if (TARGET_HARD_FLOAT
12149 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12150 && cfun->va_list_fpr_size)
12153 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12154 * UNITS_PER_FP_WORD;
12155 if (cfun->va_list_fpr_size
12156 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12157 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12159 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12160 * UNITS_PER_FP_WORD;
12164 offset = -((first_reg_offset * reg_size) & ~7);
12165 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12167 gpr_reg_num = cfun->va_list_gpr_size;
12168 if (reg_size == 4 && (first_reg_offset & 1))
12171 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12174 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12175 * UNITS_PER_FP_WORD
12176 - (int) (GP_ARG_NUM_REG * reg_size);
12178 if (gpr_size + fpr_size)
12181 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12182 gcc_assert (MEM_P (reg_save_area));
12183 reg_save_area = XEXP (reg_save_area, 0);
12184 if (GET_CODE (reg_save_area) == PLUS)
12186 gcc_assert (XEXP (reg_save_area, 0)
12187 == virtual_stack_vars_rtx);
12188 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
12189 offset += INTVAL (XEXP (reg_save_area, 1));
12192 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12195 cfun->machine->varargs_save_offset = offset;
12196 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12201 first_reg_offset = next_cum.words;
12202 save_area = crtl->args.internal_arg_pointer;
12204 if (targetm.calls.must_pass_in_stack (mode, type))
12205 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12208 set = get_varargs_alias_set ();
12209 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12210 && cfun->va_list_gpr_size)
12212 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12214 if (va_list_gpr_counter_field)
12215 /* V4 va_list_gpr_size counts number of registers needed. */
12216 n_gpr = cfun->va_list_gpr_size;
12218 /* char * va_list instead counts number of bytes needed. */
12219 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12224 mem = gen_rtx_MEM (BLKmode,
12225 plus_constant (Pmode, save_area,
12226 first_reg_offset * reg_size));
12227 MEM_NOTRAP_P (mem) = 1;
12228 set_mem_alias_set (mem, set);
12229 set_mem_align (mem, BITS_PER_WORD);
12231 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12235 /* Save FP registers if needed. */
12236 if (DEFAULT_ABI == ABI_V4
12237 && TARGET_HARD_FLOAT
12239 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12240 && cfun->va_list_fpr_size)
12242 int fregno = next_cum.fregno, nregs;
12243 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12244 rtx lab = gen_label_rtx ();
12245 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12246 * UNITS_PER_FP_WORD);
12249 (gen_rtx_SET (pc_rtx,
12250 gen_rtx_IF_THEN_ELSE (VOIDmode,
12251 gen_rtx_NE (VOIDmode, cr1,
12253 gen_rtx_LABEL_REF (VOIDmode, lab),
12257 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12258 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12260 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12261 plus_constant (Pmode, save_area, off));
12262 MEM_NOTRAP_P (mem) = 1;
12263 set_mem_alias_set (mem, set);
12264 set_mem_align (mem, GET_MODE_ALIGNMENT (
12265 TARGET_HARD_FLOAT ? DFmode : SFmode));
12266 emit_move_insn (mem, gen_rtx_REG (
12267 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12274 /* Create the va_list data type. */
12277 rs6000_build_builtin_va_list (void)
12279 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12281 /* For AIX, prefer 'char *' because that's what the system
12282 header files like. */
12283 if (DEFAULT_ABI != ABI_V4)
12284 return build_pointer_type (char_type_node);
12286 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12287 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12288 get_identifier ("__va_list_tag"), record);
12290 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12291 unsigned_char_type_node);
12292 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12293 unsigned_char_type_node);
12294 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12295 every user file. */
12296 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12297 get_identifier ("reserved"), short_unsigned_type_node);
12298 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12299 get_identifier ("overflow_arg_area"),
12301 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12302 get_identifier ("reg_save_area"),
12305 va_list_gpr_counter_field = f_gpr;
12306 va_list_fpr_counter_field = f_fpr;
12308 DECL_FIELD_CONTEXT (f_gpr) = record;
12309 DECL_FIELD_CONTEXT (f_fpr) = record;
12310 DECL_FIELD_CONTEXT (f_res) = record;
12311 DECL_FIELD_CONTEXT (f_ovf) = record;
12312 DECL_FIELD_CONTEXT (f_sav) = record;
12314 TYPE_STUB_DECL (record) = type_decl;
12315 TYPE_NAME (record) = type_decl;
12316 TYPE_FIELDS (record) = f_gpr;
12317 DECL_CHAIN (f_gpr) = f_fpr;
12318 DECL_CHAIN (f_fpr) = f_res;
12319 DECL_CHAIN (f_res) = f_ovf;
12320 DECL_CHAIN (f_ovf) = f_sav;
12322 layout_type (record);
12324 /* The correct type is an array type of one element. */
12325 return build_array_type (record, build_index_type (size_zero_node));
12328 /* Implement va_start. */
12331 rs6000_va_start (tree valist, rtx nextarg)
12333 HOST_WIDE_INT words, n_gpr, n_fpr;
12334 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12335 tree gpr, fpr, ovf, sav, t;
12337 /* Only SVR4 needs something special. */
12338 if (DEFAULT_ABI != ABI_V4)
12340 std_expand_builtin_va_start (valist, nextarg);
12344 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12345 f_fpr = DECL_CHAIN (f_gpr);
12346 f_res = DECL_CHAIN (f_fpr);
12347 f_ovf = DECL_CHAIN (f_res);
12348 f_sav = DECL_CHAIN (f_ovf);
12350 valist = build_simple_mem_ref (valist);
12351 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12352 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12354 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12356 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12359 /* Count number of gp and fp argument registers used. */
12360 words = crtl->args.info.words;
12361 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12363 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12366 if (TARGET_DEBUG_ARG)
12367 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12368 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12369 words, n_gpr, n_fpr);
12371 if (cfun->va_list_gpr_size)
12373 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12374 build_int_cst (NULL_TREE, n_gpr));
12375 TREE_SIDE_EFFECTS (t) = 1;
12376 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12379 if (cfun->va_list_fpr_size)
12381 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12382 build_int_cst (NULL_TREE, n_fpr));
12383 TREE_SIDE_EFFECTS (t) = 1;
12384 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12386 #ifdef HAVE_AS_GNU_ATTRIBUTE
12387 if (call_ABI_of_interest (cfun->decl))
12388 rs6000_passes_float = true;
12392 /* Find the overflow area. */
12393 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12395 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12396 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12397 TREE_SIDE_EFFECTS (t) = 1;
12398 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12400 /* If there were no va_arg invocations, don't set up the register
12402 if (!cfun->va_list_gpr_size
12403 && !cfun->va_list_fpr_size
12404 && n_gpr < GP_ARG_NUM_REG
12405 && n_fpr < FP_ARG_V4_MAX_REG)
12408 /* Find the register save area. */
12409 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12410 if (cfun->machine->varargs_save_offset)
12411 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12412 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12413 TREE_SIDE_EFFECTS (t) = 1;
12414 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12417 /* Implement va_arg. */
12420 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12421 gimple_seq *post_p)
12423 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12424 tree gpr, fpr, ovf, sav, reg, t, u;
12425 int size, rsize, n_reg, sav_ofs, sav_scale;
12426 tree lab_false, lab_over, addr;
12428 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12432 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12434 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12435 return build_va_arg_indirect_ref (t);
12438 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12439 earlier version of gcc, with the property that it always applied alignment
12440 adjustments to the va-args (even for zero-sized types). The cheapest way
12441 to deal with this is to replicate the effect of the part of
12442 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12444 We don't need to check for pass-by-reference because of the test above.
12445 We can return a simplifed answer, since we know there's no offset to add. */
12448 && rs6000_darwin64_abi)
12449 || DEFAULT_ABI == ABI_ELFv2
12450 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12451 && integer_zerop (TYPE_SIZE (type)))
12453 unsigned HOST_WIDE_INT align, boundary;
12454 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12455 align = PARM_BOUNDARY / BITS_PER_UNIT;
12456 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12457 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12458 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12459 boundary /= BITS_PER_UNIT;
12460 if (boundary > align)
12463 /* This updates arg ptr by the amount that would be necessary
12464 to align the zero-sized (but not zero-alignment) item. */
12465 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12466 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12467 gimplify_and_add (t, pre_p);
12469 t = fold_convert (sizetype, valist_tmp);
12470 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12471 fold_convert (TREE_TYPE (valist),
12472 fold_build2 (BIT_AND_EXPR, sizetype, t,
12473 size_int (-boundary))));
12474 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12475 gimplify_and_add (t, pre_p);
12477 /* Since it is zero-sized there's no increment for the item itself. */
12478 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12479 return build_va_arg_indirect_ref (valist_tmp);
12482 if (DEFAULT_ABI != ABI_V4)
12484 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12486 tree elem_type = TREE_TYPE (type);
12487 machine_mode elem_mode = TYPE_MODE (elem_type);
12488 int elem_size = GET_MODE_SIZE (elem_mode);
12490 if (elem_size < UNITS_PER_WORD)
12492 tree real_part, imag_part;
12493 gimple_seq post = NULL;
12495 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12497 /* Copy the value into a temporary, lest the formal temporary
12498 be reused out from under us. */
12499 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12500 gimple_seq_add_seq (pre_p, post);
12502 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12505 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12509 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12512 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12513 f_fpr = DECL_CHAIN (f_gpr);
12514 f_res = DECL_CHAIN (f_fpr);
12515 f_ovf = DECL_CHAIN (f_res);
12516 f_sav = DECL_CHAIN (f_ovf);
12518 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12519 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12521 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12523 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12526 size = int_size_in_bytes (type);
12527 rsize = (size + 3) / 4;
12528 int pad = 4 * rsize - size;
12531 machine_mode mode = TYPE_MODE (type);
12532 if (abi_v4_pass_in_fpr (mode, false))
12534 /* FP args go in FP registers, if present. */
12536 n_reg = (size + 7) / 8;
12537 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12538 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12539 if (mode != SFmode && mode != SDmode)
12544 /* Otherwise into GP registers. */
12553 /* Pull the value out of the saved registers.... */
12556 addr = create_tmp_var (ptr_type_node, "addr");
12558 /* AltiVec vectors never go in registers when -mabi=altivec. */
12559 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12563 lab_false = create_artificial_label (input_location);
12564 lab_over = create_artificial_label (input_location);
12566 /* Long long is aligned in the registers. As are any other 2 gpr
12567 item such as complex int due to a historical mistake. */
12569 if (n_reg == 2 && reg == gpr)
12572 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12573 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12574 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12575 unshare_expr (reg), u);
12577 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12578 reg number is 0 for f1, so we want to make it odd. */
12579 else if (reg == fpr && mode == TDmode)
12581 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12582 build_int_cst (TREE_TYPE (reg), 1));
12583 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12586 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12587 t = build2 (GE_EXPR, boolean_type_node, u, t);
12588 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12589 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12590 gimplify_and_add (t, pre_p);
12594 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12596 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12597 build_int_cst (TREE_TYPE (reg), n_reg));
12598 u = fold_convert (sizetype, u);
12599 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12600 t = fold_build_pointer_plus (t, u);
12602 /* _Decimal32 varargs are located in the second word of the 64-bit
12603 FP register for 32-bit binaries. */
12604 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12605 t = fold_build_pointer_plus_hwi (t, size);
12607 /* Args are passed right-aligned. */
12608 if (BYTES_BIG_ENDIAN)
12609 t = fold_build_pointer_plus_hwi (t, pad);
12611 gimplify_assign (addr, t, pre_p);
12613 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12615 stmt = gimple_build_label (lab_false);
12616 gimple_seq_add_stmt (pre_p, stmt);
12618 if ((n_reg == 2 && !regalign) || n_reg > 2)
12620 /* Ensure that we don't find any more args in regs.
12621 Alignment has taken care of for special cases. */
12622 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12626 /* ... otherwise out of the overflow area. */
12628 /* Care for on-stack alignment if needed. */
12632 t = fold_build_pointer_plus_hwi (t, align - 1);
12633 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12634 build_int_cst (TREE_TYPE (t), -align));
12637 /* Args are passed right-aligned. */
12638 if (BYTES_BIG_ENDIAN)
12639 t = fold_build_pointer_plus_hwi (t, pad);
12641 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12643 gimplify_assign (unshare_expr (addr), t, pre_p);
12645 t = fold_build_pointer_plus_hwi (t, size);
12646 gimplify_assign (unshare_expr (ovf), t, pre_p);
12650 stmt = gimple_build_label (lab_over);
12651 gimple_seq_add_stmt (pre_p, stmt);
12654 if (STRICT_ALIGNMENT
12655 && (TYPE_ALIGN (type)
12656 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12658 /* The value (of type complex double, for example) may not be
12659 aligned in memory in the saved registers, so copy via a
12660 temporary. (This is the same code as used for SPARC.) */
12661 tree tmp = create_tmp_var (type, "va_arg_tmp");
12662 tree dest_addr = build_fold_addr_expr (tmp);
12664 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12665 3, dest_addr, addr, size_int (rsize * 4));
12666 TREE_ADDRESSABLE (tmp) = 1;
12668 gimplify_and_add (copy, pre_p);
12672 addr = fold_convert (ptrtype, addr);
12673 return build_va_arg_indirect_ref (addr);
12679 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12682 unsigned classify = rs6000_builtin_info[(int)code].attr;
12683 const char *attr_string = "";
12685 gcc_assert (name != NULL);
12686 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12688 if (rs6000_builtin_decls[(int)code])
12689 fatal_error (input_location,
12690 "internal error: builtin function %qs already processed",
12693 rs6000_builtin_decls[(int)code] = t =
12694 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12696 /* Set any special attributes. */
12697 if ((classify & RS6000_BTC_CONST) != 0)
12699 /* const function, function only depends on the inputs. */
12700 TREE_READONLY (t) = 1;
12701 TREE_NOTHROW (t) = 1;
12702 attr_string = ", const";
12704 else if ((classify & RS6000_BTC_PURE) != 0)
12706 /* pure function, function can read global memory, but does not set any
12708 DECL_PURE_P (t) = 1;
12709 TREE_NOTHROW (t) = 1;
12710 attr_string = ", pure";
12712 else if ((classify & RS6000_BTC_FP) != 0)
12714 /* Function is a math function. If rounding mode is on, then treat the
12715 function as not reading global memory, but it can have arbitrary side
12716 effects. If it is off, then assume the function is a const function.
12717 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12718 builtin-attribute.def that is used for the math functions. */
12719 TREE_NOTHROW (t) = 1;
12720 if (flag_rounding_math)
12722 DECL_PURE_P (t) = 1;
12723 DECL_IS_NOVOPS (t) = 1;
12724 attr_string = ", fp, pure";
12728 TREE_READONLY (t) = 1;
12729 attr_string = ", fp, const";
12732 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12733 gcc_unreachable ();
12735 if (TARGET_DEBUG_BUILTIN)
12736 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12737 (int)code, name, attr_string);
12740 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12742 #undef RS6000_BUILTIN_0
12743 #undef RS6000_BUILTIN_1
12744 #undef RS6000_BUILTIN_2
12745 #undef RS6000_BUILTIN_3
12746 #undef RS6000_BUILTIN_A
12747 #undef RS6000_BUILTIN_D
12748 #undef RS6000_BUILTIN_H
12749 #undef RS6000_BUILTIN_P
12750 #undef RS6000_BUILTIN_X
12752 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12753 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12754 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12755 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12756 { MASK, ICODE, NAME, ENUM },
12758 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12759 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12760 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12761 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12762 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12764 static const struct builtin_description bdesc_3arg[] =
12766 #include "rs6000-builtin.def"
12769 /* DST operations: void foo (void *, const int, const char). */
12771 #undef RS6000_BUILTIN_0
12772 #undef RS6000_BUILTIN_1
12773 #undef RS6000_BUILTIN_2
12774 #undef RS6000_BUILTIN_3
12775 #undef RS6000_BUILTIN_A
12776 #undef RS6000_BUILTIN_D
12777 #undef RS6000_BUILTIN_H
12778 #undef RS6000_BUILTIN_P
12779 #undef RS6000_BUILTIN_X
12781 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12782 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12783 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12784 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12785 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12786 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12787 { MASK, ICODE, NAME, ENUM },
12789 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12790 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12791 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12793 static const struct builtin_description bdesc_dst[] =
12795 #include "rs6000-builtin.def"
12798 /* Simple binary operations: VECc = foo (VECa, VECb). */
12800 #undef RS6000_BUILTIN_0
12801 #undef RS6000_BUILTIN_1
12802 #undef RS6000_BUILTIN_2
12803 #undef RS6000_BUILTIN_3
12804 #undef RS6000_BUILTIN_A
12805 #undef RS6000_BUILTIN_D
12806 #undef RS6000_BUILTIN_H
12807 #undef RS6000_BUILTIN_P
12808 #undef RS6000_BUILTIN_X
12810 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12811 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12812 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12813 { MASK, ICODE, NAME, ENUM },
12815 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12816 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12817 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12818 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12819 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12820 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12822 static const struct builtin_description bdesc_2arg[] =
12824 #include "rs6000-builtin.def"
12827 #undef RS6000_BUILTIN_0
12828 #undef RS6000_BUILTIN_1
12829 #undef RS6000_BUILTIN_2
12830 #undef RS6000_BUILTIN_3
12831 #undef RS6000_BUILTIN_A
12832 #undef RS6000_BUILTIN_D
12833 #undef RS6000_BUILTIN_H
12834 #undef RS6000_BUILTIN_P
12835 #undef RS6000_BUILTIN_X
12837 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12838 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12839 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12840 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12841 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12842 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12843 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12844 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12845 { MASK, ICODE, NAME, ENUM },
12847 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12849 /* AltiVec predicates. */
12851 static const struct builtin_description bdesc_altivec_preds[] =
12853 #include "rs6000-builtin.def"
12856 /* ABS* operations. */
12858 #undef RS6000_BUILTIN_0
12859 #undef RS6000_BUILTIN_1
12860 #undef RS6000_BUILTIN_2
12861 #undef RS6000_BUILTIN_3
12862 #undef RS6000_BUILTIN_A
12863 #undef RS6000_BUILTIN_D
12864 #undef RS6000_BUILTIN_H
12865 #undef RS6000_BUILTIN_P
12866 #undef RS6000_BUILTIN_X
12868 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12869 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12870 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12871 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12872 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12873 { MASK, ICODE, NAME, ENUM },
12875 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12876 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12877 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12878 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12880 static const struct builtin_description bdesc_abs[] =
12882 #include "rs6000-builtin.def"
12885 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12888 #undef RS6000_BUILTIN_0
12889 #undef RS6000_BUILTIN_1
12890 #undef RS6000_BUILTIN_2
12891 #undef RS6000_BUILTIN_3
12892 #undef RS6000_BUILTIN_A
12893 #undef RS6000_BUILTIN_D
12894 #undef RS6000_BUILTIN_H
12895 #undef RS6000_BUILTIN_P
12896 #undef RS6000_BUILTIN_X
12898 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12899 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12900 { MASK, ICODE, NAME, ENUM },
12902 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12903 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12904 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12905 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12906 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12907 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12908 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12910 static const struct builtin_description bdesc_1arg[] =
12912 #include "rs6000-builtin.def"
12915 /* Simple no-argument operations: result = __builtin_darn_32 () */
12917 #undef RS6000_BUILTIN_0
12918 #undef RS6000_BUILTIN_1
12919 #undef RS6000_BUILTIN_2
12920 #undef RS6000_BUILTIN_3
12921 #undef RS6000_BUILTIN_A
12922 #undef RS6000_BUILTIN_D
12923 #undef RS6000_BUILTIN_H
12924 #undef RS6000_BUILTIN_P
12925 #undef RS6000_BUILTIN_X
12927 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
12928 { MASK, ICODE, NAME, ENUM },
12930 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12931 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12932 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12933 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12934 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12935 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12936 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12937 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12939 static const struct builtin_description bdesc_0arg[] =
12941 #include "rs6000-builtin.def"
12944 /* HTM builtins. */
12945 #undef RS6000_BUILTIN_0
12946 #undef RS6000_BUILTIN_1
12947 #undef RS6000_BUILTIN_2
12948 #undef RS6000_BUILTIN_3
12949 #undef RS6000_BUILTIN_A
12950 #undef RS6000_BUILTIN_D
12951 #undef RS6000_BUILTIN_H
12952 #undef RS6000_BUILTIN_P
12953 #undef RS6000_BUILTIN_X
12955 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12956 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12957 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12958 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12959 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12960 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12961 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12962 { MASK, ICODE, NAME, ENUM },
12964 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12965 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12967 static const struct builtin_description bdesc_htm[] =
12969 #include "rs6000-builtin.def"
12972 #undef RS6000_BUILTIN_0
12973 #undef RS6000_BUILTIN_1
12974 #undef RS6000_BUILTIN_2
12975 #undef RS6000_BUILTIN_3
12976 #undef RS6000_BUILTIN_A
12977 #undef RS6000_BUILTIN_D
12978 #undef RS6000_BUILTIN_H
12979 #undef RS6000_BUILTIN_P
12981 /* Return true if a builtin function is overloaded. */
12983 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
12985 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
12989 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
12991 return rs6000_builtin_info[(int)fncode].name;
12994 /* Expand an expression EXP that calls a builtin without arguments. */
12996 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
12999 machine_mode tmode = insn_data[icode].operand[0].mode;
13001 if (icode == CODE_FOR_nothing)
13002 /* Builtin not supported on this processor. */
13005 if (icode == CODE_FOR_rs6000_mffsl
13006 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13008 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13013 || GET_MODE (target) != tmode
13014 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13015 target = gen_reg_rtx (tmode);
13017 pat = GEN_FCN (icode) (target);
13027 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13030 tree arg0 = CALL_EXPR_ARG (exp, 0);
13031 tree arg1 = CALL_EXPR_ARG (exp, 1);
13032 rtx op0 = expand_normal (arg0);
13033 rtx op1 = expand_normal (arg1);
13034 machine_mode mode0 = insn_data[icode].operand[0].mode;
13035 machine_mode mode1 = insn_data[icode].operand[1].mode;
13037 if (icode == CODE_FOR_nothing)
13038 /* Builtin not supported on this processor. */
13041 /* If we got invalid arguments bail out before generating bad rtl. */
13042 if (arg0 == error_mark_node || arg1 == error_mark_node)
13045 if (!CONST_INT_P (op0)
13046 || INTVAL (op0) > 255
13047 || INTVAL (op0) < 0)
13049 error ("argument 1 must be an 8-bit field value");
13053 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13054 op0 = copy_to_mode_reg (mode0, op0);
13056 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13057 op1 = copy_to_mode_reg (mode1, op1);
13059 pat = GEN_FCN (icode) (op0, op1);
13068 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13071 tree arg0 = CALL_EXPR_ARG (exp, 0);
13072 rtx op0 = expand_normal (arg0);
13074 if (icode == CODE_FOR_nothing)
13075 /* Builtin not supported on this processor. */
13078 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13080 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13081 "%<-msoft-float%>");
13085 /* If we got invalid arguments bail out before generating bad rtl. */
13086 if (arg0 == error_mark_node)
13089 /* Only allow bit numbers 0 to 31. */
13090 if (!u5bit_cint_operand (op0, VOIDmode))
13092 error ("Argument must be a constant between 0 and 31.");
13096 pat = GEN_FCN (icode) (op0);
13105 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13108 tree arg0 = CALL_EXPR_ARG (exp, 0);
13109 rtx op0 = expand_normal (arg0);
13110 machine_mode mode0 = insn_data[icode].operand[0].mode;
13112 if (icode == CODE_FOR_nothing)
13113 /* Builtin not supported on this processor. */
13116 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13118 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13122 /* If we got invalid arguments bail out before generating bad rtl. */
13123 if (arg0 == error_mark_node)
13126 /* If the argument is a constant, check the range. Argument can only be a
13127 2-bit value. Unfortunately, can't check the range of the value at
13128 compile time if the argument is a variable. The least significant two
13129 bits of the argument, regardless of type, are used to set the rounding
13130 mode. All other bits are ignored. */
13131 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
13133 error ("Argument must be a value between 0 and 3.");
13137 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13138 op0 = copy_to_mode_reg (mode0, op0);
13140 pat = GEN_FCN (icode) (op0);
13148 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13151 tree arg0 = CALL_EXPR_ARG (exp, 0);
13152 rtx op0 = expand_normal (arg0);
13153 machine_mode mode0 = insn_data[icode].operand[0].mode;
13156 /* Builtin not supported in 32-bit mode. */
13157 fatal_error (input_location,
13158 "%<__builtin_set_fpscr_drn%> is not supported "
13161 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13163 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13167 if (icode == CODE_FOR_nothing)
13168 /* Builtin not supported on this processor. */
13171 /* If we got invalid arguments bail out before generating bad rtl. */
13172 if (arg0 == error_mark_node)
13175 /* If the argument is a constant, check the range. Agrument can only be a
13176 3-bit value. Unfortunately, can't check the range of the value at
13177 compile time if the argument is a variable. The least significant two
13178 bits of the argument, regardless of type, are used to set the rounding
13179 mode. All other bits are ignored. */
13180 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
13182 error ("Argument must be a value between 0 and 7.");
13186 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13187 op0 = copy_to_mode_reg (mode0, op0);
13189 pat = GEN_FCN (icode) (op0);
13198 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13201 tree arg0 = CALL_EXPR_ARG (exp, 0);
13202 rtx op0 = expand_normal (arg0);
13203 machine_mode tmode = insn_data[icode].operand[0].mode;
13204 machine_mode mode0 = insn_data[icode].operand[1].mode;
13206 if (icode == CODE_FOR_nothing)
13207 /* Builtin not supported on this processor. */
13210 /* If we got invalid arguments bail out before generating bad rtl. */
13211 if (arg0 == error_mark_node)
13214 if (icode == CODE_FOR_altivec_vspltisb
13215 || icode == CODE_FOR_altivec_vspltish
13216 || icode == CODE_FOR_altivec_vspltisw)
13218 /* Only allow 5-bit *signed* literals. */
13219 if (!CONST_INT_P (op0)
13220 || INTVAL (op0) > 15
13221 || INTVAL (op0) < -16)
13223 error ("argument 1 must be a 5-bit signed literal");
13224 return CONST0_RTX (tmode);
13229 || GET_MODE (target) != tmode
13230 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13231 target = gen_reg_rtx (tmode);
13233 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13234 op0 = copy_to_mode_reg (mode0, op0);
13236 pat = GEN_FCN (icode) (target, op0);
13245 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13247 rtx pat, scratch1, scratch2;
13248 tree arg0 = CALL_EXPR_ARG (exp, 0);
13249 rtx op0 = expand_normal (arg0);
13250 machine_mode tmode = insn_data[icode].operand[0].mode;
13251 machine_mode mode0 = insn_data[icode].operand[1].mode;
13253 /* If we have invalid arguments, bail out before generating bad rtl. */
13254 if (arg0 == error_mark_node)
13258 || GET_MODE (target) != tmode
13259 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13260 target = gen_reg_rtx (tmode);
13262 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13263 op0 = copy_to_mode_reg (mode0, op0);
13265 scratch1 = gen_reg_rtx (mode0);
13266 scratch2 = gen_reg_rtx (mode0);
13268 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13277 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13280 tree arg0 = CALL_EXPR_ARG (exp, 0);
13281 tree arg1 = CALL_EXPR_ARG (exp, 1);
13282 rtx op0 = expand_normal (arg0);
13283 rtx op1 = expand_normal (arg1);
13284 machine_mode tmode = insn_data[icode].operand[0].mode;
13285 machine_mode mode0 = insn_data[icode].operand[1].mode;
13286 machine_mode mode1 = insn_data[icode].operand[2].mode;
13288 if (icode == CODE_FOR_nothing)
13289 /* Builtin not supported on this processor. */
13292 /* If we got invalid arguments bail out before generating bad rtl. */
13293 if (arg0 == error_mark_node || arg1 == error_mark_node)
13296 if (icode == CODE_FOR_unpackv1ti
13297 || icode == CODE_FOR_unpackkf
13298 || icode == CODE_FOR_unpacktf
13299 || icode == CODE_FOR_unpackif
13300 || icode == CODE_FOR_unpacktd)
13302 /* Only allow 1-bit unsigned literals. */
13304 if (TREE_CODE (arg1) != INTEGER_CST
13305 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13307 error ("argument 2 must be a 1-bit unsigned literal");
13308 return CONST0_RTX (tmode);
13311 else if (icode == CODE_FOR_altivec_vspltw)
13313 /* Only allow 2-bit unsigned literals. */
13315 if (TREE_CODE (arg1) != INTEGER_CST
13316 || TREE_INT_CST_LOW (arg1) & ~3)
13318 error ("argument 2 must be a 2-bit unsigned literal");
13319 return CONST0_RTX (tmode);
13322 else if (icode == CODE_FOR_altivec_vsplth)
13324 /* Only allow 3-bit unsigned literals. */
13326 if (TREE_CODE (arg1) != INTEGER_CST
13327 || TREE_INT_CST_LOW (arg1) & ~7)
13329 error ("argument 2 must be a 3-bit unsigned literal");
13330 return CONST0_RTX (tmode);
13333 else if (icode == CODE_FOR_altivec_vspltb)
13335 /* Only allow 4-bit unsigned literals. */
13337 if (TREE_CODE (arg1) != INTEGER_CST
13338 || TREE_INT_CST_LOW (arg1) & ~15)
13340 error ("argument 2 must be a 4-bit unsigned literal");
13341 return CONST0_RTX (tmode);
13344 else if (icode == CODE_FOR_altivec_vcfux
13345 || icode == CODE_FOR_altivec_vcfsx
13346 || icode == CODE_FOR_altivec_vctsxs
13347 || icode == CODE_FOR_altivec_vctuxs)
13349 /* Only allow 5-bit unsigned literals. */
13351 if (TREE_CODE (arg1) != INTEGER_CST
13352 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13354 error ("argument 2 must be a 5-bit unsigned literal");
13355 return CONST0_RTX (tmode);
13358 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13359 || icode == CODE_FOR_dfptstsfi_lt_dd
13360 || icode == CODE_FOR_dfptstsfi_gt_dd
13361 || icode == CODE_FOR_dfptstsfi_unordered_dd
13362 || icode == CODE_FOR_dfptstsfi_eq_td
13363 || icode == CODE_FOR_dfptstsfi_lt_td
13364 || icode == CODE_FOR_dfptstsfi_gt_td
13365 || icode == CODE_FOR_dfptstsfi_unordered_td)
13367 /* Only allow 6-bit unsigned literals. */
13369 if (TREE_CODE (arg0) != INTEGER_CST
13370 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13372 error ("argument 1 must be a 6-bit unsigned literal");
13373 return CONST0_RTX (tmode);
13376 else if (icode == CODE_FOR_xststdcqp_kf
13377 || icode == CODE_FOR_xststdcqp_tf
13378 || icode == CODE_FOR_xststdcdp
13379 || icode == CODE_FOR_xststdcsp
13380 || icode == CODE_FOR_xvtstdcdp
13381 || icode == CODE_FOR_xvtstdcsp)
13383 /* Only allow 7-bit unsigned literals. */
13385 if (TREE_CODE (arg1) != INTEGER_CST
13386 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13388 error ("argument 2 must be a 7-bit unsigned literal");
13389 return CONST0_RTX (tmode);
13394 || GET_MODE (target) != tmode
13395 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13396 target = gen_reg_rtx (tmode);
13398 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13399 op0 = copy_to_mode_reg (mode0, op0);
13400 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13401 op1 = copy_to_mode_reg (mode1, op1);
13403 pat = GEN_FCN (icode) (target, op0, op1);
13412 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13415 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13416 tree arg0 = CALL_EXPR_ARG (exp, 1);
13417 tree arg1 = CALL_EXPR_ARG (exp, 2);
13418 rtx op0 = expand_normal (arg0);
13419 rtx op1 = expand_normal (arg1);
13420 machine_mode tmode = SImode;
13421 machine_mode mode0 = insn_data[icode].operand[1].mode;
13422 machine_mode mode1 = insn_data[icode].operand[2].mode;
13425 if (TREE_CODE (cr6_form) != INTEGER_CST)
13427 error ("argument 1 of %qs must be a constant",
13428 "__builtin_altivec_predicate");
13432 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13434 gcc_assert (mode0 == mode1);
13436 /* If we have invalid arguments, bail out before generating bad rtl. */
13437 if (arg0 == error_mark_node || arg1 == error_mark_node)
13441 || GET_MODE (target) != tmode
13442 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13443 target = gen_reg_rtx (tmode);
13445 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13446 op0 = copy_to_mode_reg (mode0, op0);
13447 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13448 op1 = copy_to_mode_reg (mode1, op1);
13450 /* Note that for many of the relevant operations (e.g. cmpne or
13451 cmpeq) with float or double operands, it makes more sense for the
13452 mode of the allocated scratch register to select a vector of
13453 integer. But the choice to copy the mode of operand 0 was made
13454 long ago and there are no plans to change it. */
13455 scratch = gen_reg_rtx (mode0);
13457 pat = GEN_FCN (icode) (scratch, op0, op1);
13462 /* The vec_any* and vec_all* predicates use the same opcodes for two
13463 different operations, but the bits in CR6 will be different
13464 depending on what information we want. So we have to play tricks
13465 with CR6 to get the right bits out.
13467 If you think this is disgusting, look at the specs for the
13468 AltiVec predicates. */
13470 switch (cr6_form_int)
13473 emit_insn (gen_cr6_test_for_zero (target));
13476 emit_insn (gen_cr6_test_for_zero_reverse (target));
13479 emit_insn (gen_cr6_test_for_lt (target));
13482 emit_insn (gen_cr6_test_for_lt_reverse (target));
13485 error ("argument 1 of %qs is out of range",
13486 "__builtin_altivec_predicate");
13494 swap_endian_selector_for_mode (machine_mode mode)
13496 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13497 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13498 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13499 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13501 unsigned int *swaparray, i;
13521 gcc_unreachable ();
13524 for (i = 0; i < 16; ++i)
13525 perm[i] = GEN_INT (swaparray[i]);
13527 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13528 gen_rtvec_v (16, perm)));
13532 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13535 tree arg0 = CALL_EXPR_ARG (exp, 0);
13536 tree arg1 = CALL_EXPR_ARG (exp, 1);
13537 machine_mode tmode = insn_data[icode].operand[0].mode;
13538 machine_mode mode0 = Pmode;
13539 machine_mode mode1 = Pmode;
13540 rtx op0 = expand_normal (arg0);
13541 rtx op1 = expand_normal (arg1);
13543 if (icode == CODE_FOR_nothing)
13544 /* Builtin not supported on this processor. */
13547 /* If we got invalid arguments bail out before generating bad rtl. */
13548 if (arg0 == error_mark_node || arg1 == error_mark_node)
13552 || GET_MODE (target) != tmode
13553 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13554 target = gen_reg_rtx (tmode);
13556 op1 = copy_to_mode_reg (mode1, op1);
13558 /* For LVX, express the RTL accurately by ANDing the address with -16.
13559 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13560 so the raw address is fine. */
13561 if (icode == CODE_FOR_altivec_lvx_v1ti
13562 || icode == CODE_FOR_altivec_lvx_v2df
13563 || icode == CODE_FOR_altivec_lvx_v2di
13564 || icode == CODE_FOR_altivec_lvx_v4sf
13565 || icode == CODE_FOR_altivec_lvx_v4si
13566 || icode == CODE_FOR_altivec_lvx_v8hi
13567 || icode == CODE_FOR_altivec_lvx_v16qi)
13570 if (op0 == const0_rtx)
13574 op0 = copy_to_mode_reg (mode0, op0);
13575 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13577 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13578 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13580 emit_insn (gen_rtx_SET (target, addr));
13584 if (op0 == const0_rtx)
13585 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13588 op0 = copy_to_mode_reg (mode0, op0);
13589 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13590 gen_rtx_PLUS (Pmode, op1, op0));
13593 pat = GEN_FCN (icode) (target, addr);
13603 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13606 tree arg0 = CALL_EXPR_ARG (exp, 0);
13607 tree arg1 = CALL_EXPR_ARG (exp, 1);
13608 tree arg2 = CALL_EXPR_ARG (exp, 2);
13609 rtx op0 = expand_normal (arg0);
13610 rtx op1 = expand_normal (arg1);
13611 rtx op2 = expand_normal (arg2);
13612 machine_mode mode0 = insn_data[icode].operand[0].mode;
13613 machine_mode mode1 = insn_data[icode].operand[1].mode;
13614 machine_mode mode2 = insn_data[icode].operand[2].mode;
13616 if (icode == CODE_FOR_nothing)
13617 /* Builtin not supported on this processor. */
13620 /* If we got invalid arguments bail out before generating bad rtl. */
13621 if (arg0 == error_mark_node
13622 || arg1 == error_mark_node
13623 || arg2 == error_mark_node)
13626 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13627 op0 = copy_to_mode_reg (mode0, op0);
13628 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13629 op1 = copy_to_mode_reg (mode1, op1);
13630 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13631 op2 = copy_to_mode_reg (mode2, op2);
13633 pat = GEN_FCN (icode) (op0, op1, op2);
13641 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13643 tree arg0 = CALL_EXPR_ARG (exp, 0);
13644 tree arg1 = CALL_EXPR_ARG (exp, 1);
13645 tree arg2 = CALL_EXPR_ARG (exp, 2);
13646 rtx op0 = expand_normal (arg0);
13647 rtx op1 = expand_normal (arg1);
13648 rtx op2 = expand_normal (arg2);
13649 rtx pat, addr, rawaddr;
13650 machine_mode tmode = insn_data[icode].operand[0].mode;
13651 machine_mode smode = insn_data[icode].operand[1].mode;
13652 machine_mode mode1 = Pmode;
13653 machine_mode mode2 = Pmode;
13655 /* Invalid arguments. Bail before doing anything stoopid! */
13656 if (arg0 == error_mark_node
13657 || arg1 == error_mark_node
13658 || arg2 == error_mark_node)
13661 op2 = copy_to_mode_reg (mode2, op2);
13663 /* For STVX, express the RTL accurately by ANDing the address with -16.
13664 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13665 so the raw address is fine. */
13666 if (icode == CODE_FOR_altivec_stvx_v2df
13667 || icode == CODE_FOR_altivec_stvx_v2di
13668 || icode == CODE_FOR_altivec_stvx_v4sf
13669 || icode == CODE_FOR_altivec_stvx_v4si
13670 || icode == CODE_FOR_altivec_stvx_v8hi
13671 || icode == CODE_FOR_altivec_stvx_v16qi)
13673 if (op1 == const0_rtx)
13677 op1 = copy_to_mode_reg (mode1, op1);
13678 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13681 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13682 addr = gen_rtx_MEM (tmode, addr);
13684 op0 = copy_to_mode_reg (tmode, op0);
13686 emit_insn (gen_rtx_SET (addr, op0));
13690 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13691 op0 = copy_to_mode_reg (smode, op0);
13693 if (op1 == const0_rtx)
13694 addr = gen_rtx_MEM (tmode, op2);
13697 op1 = copy_to_mode_reg (mode1, op1);
13698 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13701 pat = GEN_FCN (icode) (addr, op0);
13709 /* Return the appropriate SPR number associated with the given builtin. */
13710 static inline HOST_WIDE_INT
13711 htm_spr_num (enum rs6000_builtins code)
13713 if (code == HTM_BUILTIN_GET_TFHAR
13714 || code == HTM_BUILTIN_SET_TFHAR)
13716 else if (code == HTM_BUILTIN_GET_TFIAR
13717 || code == HTM_BUILTIN_SET_TFIAR)
13719 else if (code == HTM_BUILTIN_GET_TEXASR
13720 || code == HTM_BUILTIN_SET_TEXASR)
13722 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13723 || code == HTM_BUILTIN_SET_TEXASRU);
13724 return TEXASRU_SPR;
13727 /* Return the correct ICODE value depending on whether we are
13728 setting or reading the HTM SPRs. */
13729 static inline enum insn_code
13730 rs6000_htm_spr_icode (bool nonvoid)
13733 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13735 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13738 /* Expand the HTM builtin in EXP and store the result in TARGET.
13739 Store true in *EXPANDEDP if we found a builtin to expand. */
13741 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
13743 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13744 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
13745 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13746 const struct builtin_description *d;
13751 if (!TARGET_POWERPC64
13752 && (fcode == HTM_BUILTIN_TABORTDC
13753 || fcode == HTM_BUILTIN_TABORTDCI))
13755 size_t uns_fcode = (size_t)fcode;
13756 const char *name = rs6000_builtin_info[uns_fcode].name;
13757 error ("builtin %qs is only valid in 64-bit mode", name);
13761 /* Expand the HTM builtins. */
13763 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13764 if (d->code == fcode)
13766 rtx op[MAX_HTM_OPERANDS], pat;
13769 call_expr_arg_iterator iter;
13770 unsigned attr = rs6000_builtin_info[fcode].attr;
13771 enum insn_code icode = d->icode;
13772 const struct insn_operand_data *insn_op;
13773 bool uses_spr = (attr & RS6000_BTC_SPR);
13777 icode = rs6000_htm_spr_icode (nonvoid);
13778 insn_op = &insn_data[icode].operand[0];
13782 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
13784 || GET_MODE (target) != tmode
13785 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
13786 target = gen_reg_rtx (tmode);
13788 op[nopnds++] = target;
13791 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
13793 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
13796 insn_op = &insn_data[icode].operand[nopnds];
13798 op[nopnds] = expand_normal (arg);
13800 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
13802 if (!strcmp (insn_op->constraint, "n"))
13804 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
13805 if (!CONST_INT_P (op[nopnds]))
13806 error ("argument %d must be an unsigned literal", arg_num);
13808 error ("argument %d is an unsigned literal that is "
13809 "out of range", arg_num);
13812 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
13818 /* Handle the builtins for extended mnemonics. These accept
13819 no arguments, but map to builtins that take arguments. */
13822 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
13823 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
13824 op[nopnds++] = GEN_INT (1);
13826 attr |= RS6000_BTC_UNARY;
13828 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
13829 op[nopnds++] = GEN_INT (0);
13831 attr |= RS6000_BTC_UNARY;
13837 /* If this builtin accesses SPRs, then pass in the appropriate
13838 SPR number and SPR regno as the last two operands. */
13841 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
13842 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
13844 /* If this builtin accesses a CR, then pass in a scratch
13845 CR as the last operand. */
13846 else if (attr & RS6000_BTC_CR)
13847 { cr = gen_reg_rtx (CCmode);
13853 int expected_nopnds = 0;
13854 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
13855 expected_nopnds = 1;
13856 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
13857 expected_nopnds = 2;
13858 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
13859 expected_nopnds = 3;
13860 if (!(attr & RS6000_BTC_VOID))
13861 expected_nopnds += 1;
13863 expected_nopnds += 1;
13865 gcc_assert (nopnds == expected_nopnds
13866 && nopnds <= MAX_HTM_OPERANDS);
13872 pat = GEN_FCN (icode) (op[0]);
13875 pat = GEN_FCN (icode) (op[0], op[1]);
13878 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
13881 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
13884 gcc_unreachable ();
13890 if (attr & RS6000_BTC_CR)
13892 if (fcode == HTM_BUILTIN_TBEGIN)
13894 /* Emit code to set TARGET to true or false depending on
13895 whether the tbegin. instruction successfully or failed
13896 to start a transaction. We do this by placing the 1's
13897 complement of CR's EQ bit into TARGET. */
13898 rtx scratch = gen_reg_rtx (SImode);
13899 emit_insn (gen_rtx_SET (scratch,
13900 gen_rtx_EQ (SImode, cr,
13902 emit_insn (gen_rtx_SET (target,
13903 gen_rtx_XOR (SImode, scratch,
13908 /* Emit code to copy the 4-bit condition register field
13909 CR into the least significant end of register TARGET. */
13910 rtx scratch1 = gen_reg_rtx (SImode);
13911 rtx scratch2 = gen_reg_rtx (SImode);
13912 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
13913 emit_insn (gen_movcc (subreg, cr));
13914 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
13915 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
13924 *expandedp = false;
13928 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
13931 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
13934 /* __builtin_cpu_init () is a nop, so expand to nothing. */
13935 if (fcode == RS6000_BUILTIN_CPU_INIT)
13938 if (target == 0 || GET_MODE (target) != SImode)
13939 target = gen_reg_rtx (SImode);
13941 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
13942 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
13943 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
13944 to a STRING_CST. */
13945 if (TREE_CODE (arg) == ARRAY_REF
13946 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
13947 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
13948 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
13949 arg = TREE_OPERAND (arg, 0);
13951 if (TREE_CODE (arg) != STRING_CST)
13953 error ("builtin %qs only accepts a string argument",
13954 rs6000_builtin_info[(size_t) fcode].name);
13958 if (fcode == RS6000_BUILTIN_CPU_IS)
13960 const char *cpu = TREE_STRING_POINTER (arg);
13961 rtx cpuid = NULL_RTX;
13962 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
13963 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
13965 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
13966 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
13969 if (cpuid == NULL_RTX)
13971 /* Invalid CPU argument. */
13972 error ("cpu %qs is an invalid argument to builtin %qs",
13973 cpu, rs6000_builtin_info[(size_t) fcode].name);
13977 rtx platform = gen_reg_rtx (SImode);
13978 rtx tcbmem = gen_const_mem (SImode,
13979 gen_rtx_PLUS (Pmode,
13980 gen_rtx_REG (Pmode, TLS_REGNUM),
13981 GEN_INT (TCB_PLATFORM_OFFSET)));
13982 emit_move_insn (platform, tcbmem);
13983 emit_insn (gen_eqsi3 (target, platform, cpuid));
13985 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
13987 const char *hwcap = TREE_STRING_POINTER (arg);
13988 rtx mask = NULL_RTX;
13990 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
13991 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
13993 mask = GEN_INT (cpu_supports_info[i].mask);
13994 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
13997 if (mask == NULL_RTX)
13999 /* Invalid HWCAP argument. */
14000 error ("%s %qs is an invalid argument to builtin %qs",
14001 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14005 rtx tcb_hwcap = gen_reg_rtx (SImode);
14006 rtx tcbmem = gen_const_mem (SImode,
14007 gen_rtx_PLUS (Pmode,
14008 gen_rtx_REG (Pmode, TLS_REGNUM),
14009 GEN_INT (hwcap_offset)));
14010 emit_move_insn (tcb_hwcap, tcbmem);
14011 rtx scratch1 = gen_reg_rtx (SImode);
14012 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14013 rtx scratch2 = gen_reg_rtx (SImode);
14014 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14015 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14018 gcc_unreachable ();
14020 /* Record that we have expanded a CPU builtin, so that we can later
14021 emit a reference to the special symbol exported by LIBC to ensure we
14022 do not link against an old LIBC that doesn't support this feature. */
14023 cpu_builtin_p = true;
14026 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14027 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14029 /* For old LIBCs, always return FALSE. */
14030 emit_move_insn (target, GEN_INT (0));
14031 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14037 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14040 tree arg0 = CALL_EXPR_ARG (exp, 0);
14041 tree arg1 = CALL_EXPR_ARG (exp, 1);
14042 tree arg2 = CALL_EXPR_ARG (exp, 2);
14043 rtx op0 = expand_normal (arg0);
14044 rtx op1 = expand_normal (arg1);
14045 rtx op2 = expand_normal (arg2);
14046 machine_mode tmode = insn_data[icode].operand[0].mode;
14047 machine_mode mode0 = insn_data[icode].operand[1].mode;
14048 machine_mode mode1 = insn_data[icode].operand[2].mode;
14049 machine_mode mode2 = insn_data[icode].operand[3].mode;
14051 if (icode == CODE_FOR_nothing)
14052 /* Builtin not supported on this processor. */
14055 /* If we got invalid arguments bail out before generating bad rtl. */
14056 if (arg0 == error_mark_node
14057 || arg1 == error_mark_node
14058 || arg2 == error_mark_node)
14061 /* Check and prepare argument depending on the instruction code.
14063 Note that a switch statement instead of the sequence of tests
14064 would be incorrect as many of the CODE_FOR values could be
14065 CODE_FOR_nothing and that would yield multiple alternatives
14066 with identical values. We'd never reach here at runtime in
14068 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14069 || icode == CODE_FOR_altivec_vsldoi_v2df
14070 || icode == CODE_FOR_altivec_vsldoi_v4si
14071 || icode == CODE_FOR_altivec_vsldoi_v8hi
14072 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14074 /* Only allow 4-bit unsigned literals. */
14076 if (TREE_CODE (arg2) != INTEGER_CST
14077 || TREE_INT_CST_LOW (arg2) & ~0xf)
14079 error ("argument 3 must be a 4-bit unsigned literal");
14080 return CONST0_RTX (tmode);
14083 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14084 || icode == CODE_FOR_vsx_xxpermdi_v2di
14085 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14086 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14087 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14088 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14089 || icode == CODE_FOR_vsx_xxpermdi_v4si
14090 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14091 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14092 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14093 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14094 || icode == CODE_FOR_vsx_xxsldwi_v4si
14095 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14096 || icode == CODE_FOR_vsx_xxsldwi_v2di
14097 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14099 /* Only allow 2-bit unsigned literals. */
14101 if (TREE_CODE (arg2) != INTEGER_CST
14102 || TREE_INT_CST_LOW (arg2) & ~0x3)
14104 error ("argument 3 must be a 2-bit unsigned literal");
14105 return CONST0_RTX (tmode);
14108 else if (icode == CODE_FOR_vsx_set_v2df
14109 || icode == CODE_FOR_vsx_set_v2di
14110 || icode == CODE_FOR_bcdadd
14111 || icode == CODE_FOR_bcdadd_lt
14112 || icode == CODE_FOR_bcdadd_eq
14113 || icode == CODE_FOR_bcdadd_gt
14114 || icode == CODE_FOR_bcdsub
14115 || icode == CODE_FOR_bcdsub_lt
14116 || icode == CODE_FOR_bcdsub_eq
14117 || icode == CODE_FOR_bcdsub_gt)
14119 /* Only allow 1-bit unsigned literals. */
14121 if (TREE_CODE (arg2) != INTEGER_CST
14122 || TREE_INT_CST_LOW (arg2) & ~0x1)
14124 error ("argument 3 must be a 1-bit unsigned literal");
14125 return CONST0_RTX (tmode);
14128 else if (icode == CODE_FOR_dfp_ddedpd_dd
14129 || icode == CODE_FOR_dfp_ddedpd_td)
14131 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14133 if (TREE_CODE (arg0) != INTEGER_CST
14134 || TREE_INT_CST_LOW (arg2) & ~0x3)
14136 error ("argument 1 must be 0 or 2");
14137 return CONST0_RTX (tmode);
14140 else if (icode == CODE_FOR_dfp_denbcd_dd
14141 || icode == CODE_FOR_dfp_denbcd_td)
14143 /* Only allow 1-bit unsigned literals. */
14145 if (TREE_CODE (arg0) != INTEGER_CST
14146 || TREE_INT_CST_LOW (arg0) & ~0x1)
14148 error ("argument 1 must be a 1-bit unsigned literal");
14149 return CONST0_RTX (tmode);
14152 else if (icode == CODE_FOR_dfp_dscli_dd
14153 || icode == CODE_FOR_dfp_dscli_td
14154 || icode == CODE_FOR_dfp_dscri_dd
14155 || icode == CODE_FOR_dfp_dscri_td)
14157 /* Only allow 6-bit unsigned literals. */
14159 if (TREE_CODE (arg1) != INTEGER_CST
14160 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14162 error ("argument 2 must be a 6-bit unsigned literal");
14163 return CONST0_RTX (tmode);
14166 else if (icode == CODE_FOR_crypto_vshasigmaw
14167 || icode == CODE_FOR_crypto_vshasigmad)
14169 /* Check whether the 2nd and 3rd arguments are integer constants and in
14170 range and prepare arguments. */
14172 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14174 error ("argument 2 must be 0 or 1");
14175 return CONST0_RTX (tmode);
14179 if (TREE_CODE (arg2) != INTEGER_CST
14180 || wi::geu_p (wi::to_wide (arg2), 16))
14182 error ("argument 3 must be in the range [0, 15]");
14183 return CONST0_RTX (tmode);
14188 || GET_MODE (target) != tmode
14189 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14190 target = gen_reg_rtx (tmode);
14192 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14193 op0 = copy_to_mode_reg (mode0, op0);
14194 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14195 op1 = copy_to_mode_reg (mode1, op1);
14196 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14197 op2 = copy_to_mode_reg (mode2, op2);
14199 pat = GEN_FCN (icode) (target, op0, op1, op2);
14208 /* Expand the dst builtins. */
14210 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14213 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14214 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14215 tree arg0, arg1, arg2;
14216 machine_mode mode0, mode1;
14217 rtx pat, op0, op1, op2;
14218 const struct builtin_description *d;
14221 *expandedp = false;
14223 /* Handle DST variants. */
14225 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14226 if (d->code == fcode)
14228 arg0 = CALL_EXPR_ARG (exp, 0);
14229 arg1 = CALL_EXPR_ARG (exp, 1);
14230 arg2 = CALL_EXPR_ARG (exp, 2);
14231 op0 = expand_normal (arg0);
14232 op1 = expand_normal (arg1);
14233 op2 = expand_normal (arg2);
14234 mode0 = insn_data[d->icode].operand[0].mode;
14235 mode1 = insn_data[d->icode].operand[1].mode;
14237 /* Invalid arguments, bail out before generating bad rtl. */
14238 if (arg0 == error_mark_node
14239 || arg1 == error_mark_node
14240 || arg2 == error_mark_node)
14245 if (TREE_CODE (arg2) != INTEGER_CST
14246 || TREE_INT_CST_LOW (arg2) & ~0x3)
14248 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14252 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14253 op0 = copy_to_mode_reg (Pmode, op0);
14254 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14255 op1 = copy_to_mode_reg (mode1, op1);
14257 pat = GEN_FCN (d->icode) (op0, op1, op2);
14267 /* Expand vec_init builtin. */
14269 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14271 machine_mode tmode = TYPE_MODE (type);
14272 machine_mode inner_mode = GET_MODE_INNER (tmode);
14273 int i, n_elt = GET_MODE_NUNITS (tmode);
14275 gcc_assert (VECTOR_MODE_P (tmode));
14276 gcc_assert (n_elt == call_expr_nargs (exp));
14278 if (!target || !register_operand (target, tmode))
14279 target = gen_reg_rtx (tmode);
14281 /* If we have a vector compromised of a single element, such as V1TImode, do
14282 the initialization directly. */
14283 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14285 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14286 emit_move_insn (target, gen_lowpart (tmode, x));
14290 rtvec v = rtvec_alloc (n_elt);
14292 for (i = 0; i < n_elt; ++i)
14294 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14295 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14298 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14304 /* Return the integer constant in ARG. Constrain it to be in the range
14305 of the subparts of VEC_TYPE; issue an error if not. */
14308 get_element_number (tree vec_type, tree arg)
14310 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14312 if (!tree_fits_uhwi_p (arg)
14313 || (elt = tree_to_uhwi (arg), elt > max))
14315 error ("selector must be an integer constant in the range [0, %wi]", max);
14322 /* Expand vec_set builtin. */
14324 altivec_expand_vec_set_builtin (tree exp)
14326 machine_mode tmode, mode1;
14327 tree arg0, arg1, arg2;
14331 arg0 = CALL_EXPR_ARG (exp, 0);
14332 arg1 = CALL_EXPR_ARG (exp, 1);
14333 arg2 = CALL_EXPR_ARG (exp, 2);
14335 tmode = TYPE_MODE (TREE_TYPE (arg0));
14336 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14337 gcc_assert (VECTOR_MODE_P (tmode));
14339 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14340 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14341 elt = get_element_number (TREE_TYPE (arg0), arg2);
14343 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14344 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14346 op0 = force_reg (tmode, op0);
14347 op1 = force_reg (mode1, op1);
14349 rs6000_expand_vector_set (op0, op1, elt);
14354 /* Expand vec_ext builtin. */
14356 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14358 machine_mode tmode, mode0;
14363 arg0 = CALL_EXPR_ARG (exp, 0);
14364 arg1 = CALL_EXPR_ARG (exp, 1);
14366 op0 = expand_normal (arg0);
14367 op1 = expand_normal (arg1);
14369 if (TREE_CODE (arg1) == INTEGER_CST)
14371 unsigned HOST_WIDE_INT elt;
14372 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
14373 unsigned int truncated_selector;
14374 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14375 returns low-order bits of INTEGER_CST for modulo indexing. */
14376 elt = TREE_INT_CST_LOW (arg1);
14377 truncated_selector = elt % size;
14378 op1 = GEN_INT (truncated_selector);
14381 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14382 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14383 gcc_assert (VECTOR_MODE_P (mode0));
14385 op0 = force_reg (mode0, op0);
14387 if (optimize || !target || !register_operand (target, tmode))
14388 target = gen_reg_rtx (tmode);
14390 rs6000_expand_vector_extract (target, op0, op1);
14395 /* Expand the builtin in EXP and store the result in TARGET. Store
14396 true in *EXPANDEDP if we found a builtin to expand. */
14398 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14400 const struct builtin_description *d;
14402 enum insn_code icode;
14403 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14404 tree arg0, arg1, arg2;
14406 machine_mode tmode, mode0;
14407 enum rs6000_builtins fcode
14408 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14410 if (rs6000_overloaded_builtin_p (fcode))
14413 error ("unresolved overload for Altivec builtin %qF", fndecl);
14415 /* Given it is invalid, just generate a normal call. */
14416 return expand_call (exp, target, false);
14419 target = altivec_expand_dst_builtin (exp, target, expandedp);
14427 case ALTIVEC_BUILTIN_STVX_V2DF:
14428 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14429 case ALTIVEC_BUILTIN_STVX_V2DI:
14430 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14431 case ALTIVEC_BUILTIN_STVX_V4SF:
14432 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14433 case ALTIVEC_BUILTIN_STVX:
14434 case ALTIVEC_BUILTIN_STVX_V4SI:
14435 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14436 case ALTIVEC_BUILTIN_STVX_V8HI:
14437 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14438 case ALTIVEC_BUILTIN_STVX_V16QI:
14439 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14440 case ALTIVEC_BUILTIN_STVEBX:
14441 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14442 case ALTIVEC_BUILTIN_STVEHX:
14443 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14444 case ALTIVEC_BUILTIN_STVEWX:
14445 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14446 case ALTIVEC_BUILTIN_STVXL_V2DF:
14447 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14448 case ALTIVEC_BUILTIN_STVXL_V2DI:
14449 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14450 case ALTIVEC_BUILTIN_STVXL_V4SF:
14451 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14452 case ALTIVEC_BUILTIN_STVXL:
14453 case ALTIVEC_BUILTIN_STVXL_V4SI:
14454 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14455 case ALTIVEC_BUILTIN_STVXL_V8HI:
14456 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14457 case ALTIVEC_BUILTIN_STVXL_V16QI:
14458 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14460 case ALTIVEC_BUILTIN_STVLX:
14461 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14462 case ALTIVEC_BUILTIN_STVLXL:
14463 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14464 case ALTIVEC_BUILTIN_STVRX:
14465 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14466 case ALTIVEC_BUILTIN_STVRXL:
14467 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14469 case P9V_BUILTIN_STXVL:
14470 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14472 case P9V_BUILTIN_XST_LEN_R:
14473 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14475 case VSX_BUILTIN_STXVD2X_V1TI:
14476 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14477 case VSX_BUILTIN_STXVD2X_V2DF:
14478 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14479 case VSX_BUILTIN_STXVD2X_V2DI:
14480 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14481 case VSX_BUILTIN_STXVW4X_V4SF:
14482 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14483 case VSX_BUILTIN_STXVW4X_V4SI:
14484 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14485 case VSX_BUILTIN_STXVW4X_V8HI:
14486 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14487 case VSX_BUILTIN_STXVW4X_V16QI:
14488 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14490 /* For the following on big endian, it's ok to use any appropriate
14491 unaligned-supporting store, so use a generic expander. For
14492 little-endian, the exact element-reversing instruction must
14494 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14496 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14497 : CODE_FOR_vsx_st_elemrev_v1ti);
14498 return altivec_expand_stv_builtin (code, exp);
14500 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14502 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14503 : CODE_FOR_vsx_st_elemrev_v2df);
14504 return altivec_expand_stv_builtin (code, exp);
14506 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14508 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14509 : CODE_FOR_vsx_st_elemrev_v2di);
14510 return altivec_expand_stv_builtin (code, exp);
14512 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14514 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14515 : CODE_FOR_vsx_st_elemrev_v4sf);
14516 return altivec_expand_stv_builtin (code, exp);
14518 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14520 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14521 : CODE_FOR_vsx_st_elemrev_v4si);
14522 return altivec_expand_stv_builtin (code, exp);
14524 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14526 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14527 : CODE_FOR_vsx_st_elemrev_v8hi);
14528 return altivec_expand_stv_builtin (code, exp);
14530 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14532 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14533 : CODE_FOR_vsx_st_elemrev_v16qi);
14534 return altivec_expand_stv_builtin (code, exp);
14537 case ALTIVEC_BUILTIN_MFVSCR:
14538 icode = CODE_FOR_altivec_mfvscr;
14539 tmode = insn_data[icode].operand[0].mode;
14542 || GET_MODE (target) != tmode
14543 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14544 target = gen_reg_rtx (tmode);
14546 pat = GEN_FCN (icode) (target);
14552 case ALTIVEC_BUILTIN_MTVSCR:
14553 icode = CODE_FOR_altivec_mtvscr;
14554 arg0 = CALL_EXPR_ARG (exp, 0);
14555 op0 = expand_normal (arg0);
14556 mode0 = insn_data[icode].operand[0].mode;
14558 /* If we got invalid arguments bail out before generating bad rtl. */
14559 if (arg0 == error_mark_node)
14562 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14563 op0 = copy_to_mode_reg (mode0, op0);
14565 pat = GEN_FCN (icode) (op0);
14570 case ALTIVEC_BUILTIN_DSSALL:
14571 emit_insn (gen_altivec_dssall ());
14574 case ALTIVEC_BUILTIN_DSS:
14575 icode = CODE_FOR_altivec_dss;
14576 arg0 = CALL_EXPR_ARG (exp, 0);
14578 op0 = expand_normal (arg0);
14579 mode0 = insn_data[icode].operand[0].mode;
14581 /* If we got invalid arguments bail out before generating bad rtl. */
14582 if (arg0 == error_mark_node)
14585 if (TREE_CODE (arg0) != INTEGER_CST
14586 || TREE_INT_CST_LOW (arg0) & ~0x3)
14588 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14592 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14593 op0 = copy_to_mode_reg (mode0, op0);
14595 emit_insn (gen_altivec_dss (op0));
14598 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14599 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14600 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14601 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14602 case VSX_BUILTIN_VEC_INIT_V2DF:
14603 case VSX_BUILTIN_VEC_INIT_V2DI:
14604 case VSX_BUILTIN_VEC_INIT_V1TI:
14605 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14607 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14608 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14609 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14610 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14611 case VSX_BUILTIN_VEC_SET_V2DF:
14612 case VSX_BUILTIN_VEC_SET_V2DI:
14613 case VSX_BUILTIN_VEC_SET_V1TI:
14614 return altivec_expand_vec_set_builtin (exp);
14616 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14617 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14618 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14619 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14620 case VSX_BUILTIN_VEC_EXT_V2DF:
14621 case VSX_BUILTIN_VEC_EXT_V2DI:
14622 case VSX_BUILTIN_VEC_EXT_V1TI:
14623 return altivec_expand_vec_ext_builtin (exp, target);
14625 case P9V_BUILTIN_VEC_EXTRACT4B:
14626 arg1 = CALL_EXPR_ARG (exp, 1);
14629 /* Generate a normal call if it is invalid. */
14630 if (arg1 == error_mark_node)
14631 return expand_call (exp, target, false);
14633 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14635 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
14636 return expand_call (exp, target, false);
14640 case P9V_BUILTIN_VEC_INSERT4B:
14641 arg2 = CALL_EXPR_ARG (exp, 2);
14644 /* Generate a normal call if it is invalid. */
14645 if (arg2 == error_mark_node)
14646 return expand_call (exp, target, false);
14648 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14650 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
14651 return expand_call (exp, target, false);
14657 /* Fall through. */
14660 /* Expand abs* operations. */
14662 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14663 if (d->code == fcode)
14664 return altivec_expand_abs_builtin (d->icode, exp, target);
14666 /* Expand the AltiVec predicates. */
14667 d = bdesc_altivec_preds;
14668 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14669 if (d->code == fcode)
14670 return altivec_expand_predicate_builtin (d->icode, exp, target);
14672 /* LV* are funky. We initialized them differently. */
14675 case ALTIVEC_BUILTIN_LVSL:
14676 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14677 exp, target, false);
14678 case ALTIVEC_BUILTIN_LVSR:
14679 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14680 exp, target, false);
14681 case ALTIVEC_BUILTIN_LVEBX:
14682 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14683 exp, target, false);
14684 case ALTIVEC_BUILTIN_LVEHX:
14685 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14686 exp, target, false);
14687 case ALTIVEC_BUILTIN_LVEWX:
14688 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14689 exp, target, false);
14690 case ALTIVEC_BUILTIN_LVXL_V2DF:
14691 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14692 exp, target, false);
14693 case ALTIVEC_BUILTIN_LVXL_V2DI:
14694 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14695 exp, target, false);
14696 case ALTIVEC_BUILTIN_LVXL_V4SF:
14697 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14698 exp, target, false);
14699 case ALTIVEC_BUILTIN_LVXL:
14700 case ALTIVEC_BUILTIN_LVXL_V4SI:
14701 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14702 exp, target, false);
14703 case ALTIVEC_BUILTIN_LVXL_V8HI:
14704 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14705 exp, target, false);
14706 case ALTIVEC_BUILTIN_LVXL_V16QI:
14707 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14708 exp, target, false);
14709 case ALTIVEC_BUILTIN_LVX_V1TI:
14710 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14711 exp, target, false);
14712 case ALTIVEC_BUILTIN_LVX_V2DF:
14713 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14714 exp, target, false);
14715 case ALTIVEC_BUILTIN_LVX_V2DI:
14716 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14717 exp, target, false);
14718 case ALTIVEC_BUILTIN_LVX_V4SF:
14719 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14720 exp, target, false);
14721 case ALTIVEC_BUILTIN_LVX:
14722 case ALTIVEC_BUILTIN_LVX_V4SI:
14723 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14724 exp, target, false);
14725 case ALTIVEC_BUILTIN_LVX_V8HI:
14726 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14727 exp, target, false);
14728 case ALTIVEC_BUILTIN_LVX_V16QI:
14729 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14730 exp, target, false);
14731 case ALTIVEC_BUILTIN_LVLX:
14732 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14733 exp, target, true);
14734 case ALTIVEC_BUILTIN_LVLXL:
14735 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14736 exp, target, true);
14737 case ALTIVEC_BUILTIN_LVRX:
14738 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14739 exp, target, true);
14740 case ALTIVEC_BUILTIN_LVRXL:
14741 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14742 exp, target, true);
14743 case VSX_BUILTIN_LXVD2X_V1TI:
14744 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14745 exp, target, false);
14746 case VSX_BUILTIN_LXVD2X_V2DF:
14747 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
14748 exp, target, false);
14749 case VSX_BUILTIN_LXVD2X_V2DI:
14750 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
14751 exp, target, false);
14752 case VSX_BUILTIN_LXVW4X_V4SF:
14753 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
14754 exp, target, false);
14755 case VSX_BUILTIN_LXVW4X_V4SI:
14756 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
14757 exp, target, false);
14758 case VSX_BUILTIN_LXVW4X_V8HI:
14759 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
14760 exp, target, false);
14761 case VSX_BUILTIN_LXVW4X_V16QI:
14762 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
14763 exp, target, false);
14764 /* For the following on big endian, it's ok to use any appropriate
14765 unaligned-supporting load, so use a generic expander. For
14766 little-endian, the exact element-reversing instruction must
14768 case VSX_BUILTIN_LD_ELEMREV_V2DF:
14770 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
14771 : CODE_FOR_vsx_ld_elemrev_v2df);
14772 return altivec_expand_lv_builtin (code, exp, target, false);
14774 case VSX_BUILTIN_LD_ELEMREV_V1TI:
14776 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
14777 : CODE_FOR_vsx_ld_elemrev_v1ti);
14778 return altivec_expand_lv_builtin (code, exp, target, false);
14780 case VSX_BUILTIN_LD_ELEMREV_V2DI:
14782 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
14783 : CODE_FOR_vsx_ld_elemrev_v2di);
14784 return altivec_expand_lv_builtin (code, exp, target, false);
14786 case VSX_BUILTIN_LD_ELEMREV_V4SF:
14788 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
14789 : CODE_FOR_vsx_ld_elemrev_v4sf);
14790 return altivec_expand_lv_builtin (code, exp, target, false);
14792 case VSX_BUILTIN_LD_ELEMREV_V4SI:
14794 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
14795 : CODE_FOR_vsx_ld_elemrev_v4si);
14796 return altivec_expand_lv_builtin (code, exp, target, false);
14798 case VSX_BUILTIN_LD_ELEMREV_V8HI:
14800 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
14801 : CODE_FOR_vsx_ld_elemrev_v8hi);
14802 return altivec_expand_lv_builtin (code, exp, target, false);
14804 case VSX_BUILTIN_LD_ELEMREV_V16QI:
14806 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
14807 : CODE_FOR_vsx_ld_elemrev_v16qi);
14808 return altivec_expand_lv_builtin (code, exp, target, false);
14813 /* Fall through. */
14816 *expandedp = false;
14820 /* Check whether a builtin function is supported in this target
14823 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
14825 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
14826 if ((fnmask & rs6000_builtin_mask) != fnmask)
14832 /* Raise an error message for a builtin function that is called without the
14833 appropriate target options being set. */
14836 rs6000_invalid_builtin (enum rs6000_builtins fncode)
14838 size_t uns_fncode = (size_t) fncode;
14839 const char *name = rs6000_builtin_info[uns_fncode].name;
14840 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
14842 gcc_assert (name != NULL);
14843 if ((fnmask & RS6000_BTM_CELL) != 0)
14844 error ("builtin function %qs is only valid for the cell processor", name);
14845 else if ((fnmask & RS6000_BTM_VSX) != 0)
14846 error ("builtin function %qs requires the %qs option", name, "-mvsx");
14847 else if ((fnmask & RS6000_BTM_HTM) != 0)
14848 error ("builtin function %qs requires the %qs option", name, "-mhtm");
14849 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
14850 error ("builtin function %qs requires the %qs option", name, "-maltivec");
14851 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14852 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14853 error ("builtin function %qs requires the %qs and %qs options",
14854 name, "-mhard-dfp", "-mpower8-vector");
14855 else if ((fnmask & RS6000_BTM_DFP) != 0)
14856 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
14857 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
14858 error ("builtin function %qs requires the %qs option", name,
14859 "-mpower8-vector");
14860 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14861 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14862 error ("builtin function %qs requires the %qs and %qs options",
14863 name, "-mcpu=power9", "-m64");
14864 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
14865 error ("builtin function %qs requires the %qs option", name,
14867 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14868 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14869 error ("builtin function %qs requires the %qs and %qs options",
14870 name, "-mcpu=power9", "-m64");
14871 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
14872 error ("builtin function %qs requires the %qs option", name,
14874 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
14876 if (!TARGET_HARD_FLOAT)
14877 error ("builtin function %qs requires the %qs option", name,
14880 error ("builtin function %qs requires the %qs option", name,
14881 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
14883 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
14884 error ("builtin function %qs requires the %qs option", name,
14886 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
14887 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
14889 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
14890 error ("builtin function %qs requires the %qs option", name,
14892 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14893 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14894 error ("builtin function %qs requires the %qs (or newer), and "
14895 "%qs or %qs options",
14896 name, "-mcpu=power7", "-m64", "-mpowerpc64");
14898 error ("builtin function %qs is not supported with the current options",
14902 /* Target hook for early folding of built-ins, shamelessly stolen
14906 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
14907 int n_args ATTRIBUTE_UNUSED,
14908 tree *args ATTRIBUTE_UNUSED,
14909 bool ignore ATTRIBUTE_UNUSED)
14911 #ifdef SUBTARGET_FOLD_BUILTIN
14912 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
14918 /* Helper function to sort out which built-ins may be valid without having
14921 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
14925 case ALTIVEC_BUILTIN_STVX_V16QI:
14926 case ALTIVEC_BUILTIN_STVX_V8HI:
14927 case ALTIVEC_BUILTIN_STVX_V4SI:
14928 case ALTIVEC_BUILTIN_STVX_V4SF:
14929 case ALTIVEC_BUILTIN_STVX_V2DI:
14930 case ALTIVEC_BUILTIN_STVX_V2DF:
14931 case VSX_BUILTIN_STXVW4X_V16QI:
14932 case VSX_BUILTIN_STXVW4X_V8HI:
14933 case VSX_BUILTIN_STXVW4X_V4SF:
14934 case VSX_BUILTIN_STXVW4X_V4SI:
14935 case VSX_BUILTIN_STXVD2X_V2DF:
14936 case VSX_BUILTIN_STXVD2X_V2DI:
14943 /* Helper function to handle the gimple folding of a vector compare
14944 operation. This sets up true/false vectors, and uses the
14945 VEC_COND_EXPR operation.
14946 CODE indicates which comparison is to be made. (EQ, GT, ...).
14947 TYPE indicates the type of the result. */
14949 fold_build_vec_cmp (tree_code code, tree type,
14950 tree arg0, tree arg1)
14952 tree cmp_type = build_same_sized_truth_vector_type (type);
14953 tree zero_vec = build_zero_cst (type);
14954 tree minus_one_vec = build_minus_one_cst (type);
14955 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
14956 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
14959 /* Helper function to handle the in-between steps for the
14960 vector compare built-ins. */
14962 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
14964 tree arg0 = gimple_call_arg (stmt, 0);
14965 tree arg1 = gimple_call_arg (stmt, 1);
14966 tree lhs = gimple_call_lhs (stmt);
14967 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
14968 gimple *g = gimple_build_assign (lhs, cmp);
14969 gimple_set_location (g, gimple_location (stmt));
14970 gsi_replace (gsi, g, true);
14973 /* Helper function to map V2DF and V4SF types to their
14974 integral equivalents (V2DI and V4SI). */
14975 tree map_to_integral_tree_type (tree input_tree_type)
14977 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
14978 return input_tree_type;
14981 if (types_compatible_p (TREE_TYPE (input_tree_type),
14982 TREE_TYPE (V2DF_type_node)))
14983 return V2DI_type_node;
14984 else if (types_compatible_p (TREE_TYPE (input_tree_type),
14985 TREE_TYPE (V4SF_type_node)))
14986 return V4SI_type_node;
14988 gcc_unreachable ();
14992 /* Helper function to handle the vector merge[hl] built-ins. The
14993 implementation difference between h and l versions for this code are in
14994 the values used when building of the permute vector for high word versus
14995 low word merge. The variance is keyed off the use_high parameter. */
14997 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
14999 tree arg0 = gimple_call_arg (stmt, 0);
15000 tree arg1 = gimple_call_arg (stmt, 1);
15001 tree lhs = gimple_call_lhs (stmt);
15002 tree lhs_type = TREE_TYPE (lhs);
15003 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15004 int midpoint = n_elts / 2;
15010 /* The permute_type will match the lhs for integral types. For double and
15011 float types, the permute type needs to map to the V2 or V4 type that
15014 permute_type = map_to_integral_tree_type (lhs_type);
15015 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15017 for (int i = 0; i < midpoint; i++)
15019 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15021 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15022 offset + n_elts + i));
15025 tree permute = elts.build ();
15027 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15028 gimple_set_location (g, gimple_location (stmt));
15029 gsi_replace (gsi, g, true);
15032 /* Helper function to handle the vector merge[eo] built-ins. */
15034 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15036 tree arg0 = gimple_call_arg (stmt, 0);
15037 tree arg1 = gimple_call_arg (stmt, 1);
15038 tree lhs = gimple_call_lhs (stmt);
15039 tree lhs_type = TREE_TYPE (lhs);
15040 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15042 /* The permute_type will match the lhs for integral types. For double and
15043 float types, the permute type needs to map to the V2 or V4 type that
15046 permute_type = map_to_integral_tree_type (lhs_type);
15048 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15050 /* Build the permute vector. */
15051 for (int i = 0; i < n_elts / 2; i++)
15053 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15055 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15056 2*i + use_odd + n_elts));
15059 tree permute = elts.build ();
15061 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15062 gimple_set_location (g, gimple_location (stmt));
15063 gsi_replace (gsi, g, true);
15066 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15067 a constant, use rs6000_fold_builtin.) */
15070 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15072 gimple *stmt = gsi_stmt (*gsi);
15073 tree fndecl = gimple_call_fndecl (stmt);
15074 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15075 enum rs6000_builtins fn_code
15076 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15077 tree arg0, arg1, lhs, temp;
15078 enum tree_code bcode;
15081 size_t uns_fncode = (size_t) fn_code;
15082 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15083 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15084 const char *fn_name2 = (icode != CODE_FOR_nothing)
15085 ? get_insn_name ((int) icode)
15088 if (TARGET_DEBUG_BUILTIN)
15089 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15090 fn_code, fn_name1, fn_name2);
15092 if (!rs6000_fold_gimple)
15095 /* Prevent gimple folding for code that does not have a LHS, unless it is
15096 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15097 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15100 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15101 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15102 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15108 /* Flavors of vec_add. We deliberately don't expand
15109 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15110 TImode, resulting in much poorer code generation. */
15111 case ALTIVEC_BUILTIN_VADDUBM:
15112 case ALTIVEC_BUILTIN_VADDUHM:
15113 case ALTIVEC_BUILTIN_VADDUWM:
15114 case P8V_BUILTIN_VADDUDM:
15115 case ALTIVEC_BUILTIN_VADDFP:
15116 case VSX_BUILTIN_XVADDDP:
15119 arg0 = gimple_call_arg (stmt, 0);
15120 arg1 = gimple_call_arg (stmt, 1);
15121 lhs = gimple_call_lhs (stmt);
15122 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
15123 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
15125 /* Ensure the binary operation is performed in a type
15126 that wraps if it is integral type. */
15127 gimple_seq stmts = NULL;
15128 tree type = unsigned_type_for (TREE_TYPE (lhs));
15129 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15131 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15133 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
15134 type, uarg0, uarg1);
15135 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15136 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
15137 build1 (VIEW_CONVERT_EXPR,
15138 TREE_TYPE (lhs), res));
15139 gsi_replace (gsi, g, true);
15142 g = gimple_build_assign (lhs, bcode, arg0, arg1);
15143 gimple_set_location (g, gimple_location (stmt));
15144 gsi_replace (gsi, g, true);
15146 /* Flavors of vec_sub. We deliberately don't expand
15147 P8V_BUILTIN_VSUBUQM. */
15148 case ALTIVEC_BUILTIN_VSUBUBM:
15149 case ALTIVEC_BUILTIN_VSUBUHM:
15150 case ALTIVEC_BUILTIN_VSUBUWM:
15151 case P8V_BUILTIN_VSUBUDM:
15152 case ALTIVEC_BUILTIN_VSUBFP:
15153 case VSX_BUILTIN_XVSUBDP:
15154 bcode = MINUS_EXPR;
15156 case VSX_BUILTIN_XVMULSP:
15157 case VSX_BUILTIN_XVMULDP:
15158 arg0 = gimple_call_arg (stmt, 0);
15159 arg1 = gimple_call_arg (stmt, 1);
15160 lhs = gimple_call_lhs (stmt);
15161 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15162 gimple_set_location (g, gimple_location (stmt));
15163 gsi_replace (gsi, g, true);
15165 /* Even element flavors of vec_mul (signed). */
15166 case ALTIVEC_BUILTIN_VMULESB:
15167 case ALTIVEC_BUILTIN_VMULESH:
15168 case P8V_BUILTIN_VMULESW:
15169 /* Even element flavors of vec_mul (unsigned). */
15170 case ALTIVEC_BUILTIN_VMULEUB:
15171 case ALTIVEC_BUILTIN_VMULEUH:
15172 case P8V_BUILTIN_VMULEUW:
15173 arg0 = gimple_call_arg (stmt, 0);
15174 arg1 = gimple_call_arg (stmt, 1);
15175 lhs = gimple_call_lhs (stmt);
15176 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15177 gimple_set_location (g, gimple_location (stmt));
15178 gsi_replace (gsi, g, true);
15180 /* Odd element flavors of vec_mul (signed). */
15181 case ALTIVEC_BUILTIN_VMULOSB:
15182 case ALTIVEC_BUILTIN_VMULOSH:
15183 case P8V_BUILTIN_VMULOSW:
15184 /* Odd element flavors of vec_mul (unsigned). */
15185 case ALTIVEC_BUILTIN_VMULOUB:
15186 case ALTIVEC_BUILTIN_VMULOUH:
15187 case P8V_BUILTIN_VMULOUW:
15188 arg0 = gimple_call_arg (stmt, 0);
15189 arg1 = gimple_call_arg (stmt, 1);
15190 lhs = gimple_call_lhs (stmt);
15191 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15192 gimple_set_location (g, gimple_location (stmt));
15193 gsi_replace (gsi, g, true);
15195 /* Flavors of vec_div (Integer). */
15196 case VSX_BUILTIN_DIV_V2DI:
15197 case VSX_BUILTIN_UDIV_V2DI:
15198 arg0 = gimple_call_arg (stmt, 0);
15199 arg1 = gimple_call_arg (stmt, 1);
15200 lhs = gimple_call_lhs (stmt);
15201 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15202 gimple_set_location (g, gimple_location (stmt));
15203 gsi_replace (gsi, g, true);
15205 /* Flavors of vec_div (Float). */
15206 case VSX_BUILTIN_XVDIVSP:
15207 case VSX_BUILTIN_XVDIVDP:
15208 arg0 = gimple_call_arg (stmt, 0);
15209 arg1 = gimple_call_arg (stmt, 1);
15210 lhs = gimple_call_lhs (stmt);
15211 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15212 gimple_set_location (g, gimple_location (stmt));
15213 gsi_replace (gsi, g, true);
15215 /* Flavors of vec_and. */
15216 case ALTIVEC_BUILTIN_VAND:
15217 arg0 = gimple_call_arg (stmt, 0);
15218 arg1 = gimple_call_arg (stmt, 1);
15219 lhs = gimple_call_lhs (stmt);
15220 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15221 gimple_set_location (g, gimple_location (stmt));
15222 gsi_replace (gsi, g, true);
15224 /* Flavors of vec_andc. */
15225 case ALTIVEC_BUILTIN_VANDC:
15226 arg0 = gimple_call_arg (stmt, 0);
15227 arg1 = gimple_call_arg (stmt, 1);
15228 lhs = gimple_call_lhs (stmt);
15229 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15230 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15231 gimple_set_location (g, gimple_location (stmt));
15232 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15233 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15234 gimple_set_location (g, gimple_location (stmt));
15235 gsi_replace (gsi, g, true);
15237 /* Flavors of vec_nand. */
15238 case P8V_BUILTIN_VEC_NAND:
15239 case P8V_BUILTIN_NAND_V16QI:
15240 case P8V_BUILTIN_NAND_V8HI:
15241 case P8V_BUILTIN_NAND_V4SI:
15242 case P8V_BUILTIN_NAND_V4SF:
15243 case P8V_BUILTIN_NAND_V2DF:
15244 case P8V_BUILTIN_NAND_V2DI:
15245 arg0 = gimple_call_arg (stmt, 0);
15246 arg1 = gimple_call_arg (stmt, 1);
15247 lhs = gimple_call_lhs (stmt);
15248 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15249 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15250 gimple_set_location (g, gimple_location (stmt));
15251 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15252 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15253 gimple_set_location (g, gimple_location (stmt));
15254 gsi_replace (gsi, g, true);
15256 /* Flavors of vec_or. */
15257 case ALTIVEC_BUILTIN_VOR:
15258 arg0 = gimple_call_arg (stmt, 0);
15259 arg1 = gimple_call_arg (stmt, 1);
15260 lhs = gimple_call_lhs (stmt);
15261 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15262 gimple_set_location (g, gimple_location (stmt));
15263 gsi_replace (gsi, g, true);
15265 /* flavors of vec_orc. */
15266 case P8V_BUILTIN_ORC_V16QI:
15267 case P8V_BUILTIN_ORC_V8HI:
15268 case P8V_BUILTIN_ORC_V4SI:
15269 case P8V_BUILTIN_ORC_V4SF:
15270 case P8V_BUILTIN_ORC_V2DF:
15271 case P8V_BUILTIN_ORC_V2DI:
15272 arg0 = gimple_call_arg (stmt, 0);
15273 arg1 = gimple_call_arg (stmt, 1);
15274 lhs = gimple_call_lhs (stmt);
15275 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15276 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15277 gimple_set_location (g, gimple_location (stmt));
15278 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15279 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15280 gimple_set_location (g, gimple_location (stmt));
15281 gsi_replace (gsi, g, true);
15283 /* Flavors of vec_xor. */
15284 case ALTIVEC_BUILTIN_VXOR:
15285 arg0 = gimple_call_arg (stmt, 0);
15286 arg1 = gimple_call_arg (stmt, 1);
15287 lhs = gimple_call_lhs (stmt);
15288 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15289 gimple_set_location (g, gimple_location (stmt));
15290 gsi_replace (gsi, g, true);
15292 /* Flavors of vec_nor. */
15293 case ALTIVEC_BUILTIN_VNOR:
15294 arg0 = gimple_call_arg (stmt, 0);
15295 arg1 = gimple_call_arg (stmt, 1);
15296 lhs = gimple_call_lhs (stmt);
15297 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15298 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15299 gimple_set_location (g, gimple_location (stmt));
15300 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15301 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15302 gimple_set_location (g, gimple_location (stmt));
15303 gsi_replace (gsi, g, true);
15305 /* flavors of vec_abs. */
15306 case ALTIVEC_BUILTIN_ABS_V16QI:
15307 case ALTIVEC_BUILTIN_ABS_V8HI:
15308 case ALTIVEC_BUILTIN_ABS_V4SI:
15309 case ALTIVEC_BUILTIN_ABS_V4SF:
15310 case P8V_BUILTIN_ABS_V2DI:
15311 case VSX_BUILTIN_XVABSDP:
15312 arg0 = gimple_call_arg (stmt, 0);
15313 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15314 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15316 lhs = gimple_call_lhs (stmt);
15317 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15318 gimple_set_location (g, gimple_location (stmt));
15319 gsi_replace (gsi, g, true);
15321 /* flavors of vec_min. */
15322 case VSX_BUILTIN_XVMINDP:
15323 case P8V_BUILTIN_VMINSD:
15324 case P8V_BUILTIN_VMINUD:
15325 case ALTIVEC_BUILTIN_VMINSB:
15326 case ALTIVEC_BUILTIN_VMINSH:
15327 case ALTIVEC_BUILTIN_VMINSW:
15328 case ALTIVEC_BUILTIN_VMINUB:
15329 case ALTIVEC_BUILTIN_VMINUH:
15330 case ALTIVEC_BUILTIN_VMINUW:
15331 case ALTIVEC_BUILTIN_VMINFP:
15332 arg0 = gimple_call_arg (stmt, 0);
15333 arg1 = gimple_call_arg (stmt, 1);
15334 lhs = gimple_call_lhs (stmt);
15335 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15336 gimple_set_location (g, gimple_location (stmt));
15337 gsi_replace (gsi, g, true);
15339 /* flavors of vec_max. */
15340 case VSX_BUILTIN_XVMAXDP:
15341 case P8V_BUILTIN_VMAXSD:
15342 case P8V_BUILTIN_VMAXUD:
15343 case ALTIVEC_BUILTIN_VMAXSB:
15344 case ALTIVEC_BUILTIN_VMAXSH:
15345 case ALTIVEC_BUILTIN_VMAXSW:
15346 case ALTIVEC_BUILTIN_VMAXUB:
15347 case ALTIVEC_BUILTIN_VMAXUH:
15348 case ALTIVEC_BUILTIN_VMAXUW:
15349 case ALTIVEC_BUILTIN_VMAXFP:
15350 arg0 = gimple_call_arg (stmt, 0);
15351 arg1 = gimple_call_arg (stmt, 1);
15352 lhs = gimple_call_lhs (stmt);
15353 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15354 gimple_set_location (g, gimple_location (stmt));
15355 gsi_replace (gsi, g, true);
15357 /* Flavors of vec_eqv. */
15358 case P8V_BUILTIN_EQV_V16QI:
15359 case P8V_BUILTIN_EQV_V8HI:
15360 case P8V_BUILTIN_EQV_V4SI:
15361 case P8V_BUILTIN_EQV_V4SF:
15362 case P8V_BUILTIN_EQV_V2DF:
15363 case P8V_BUILTIN_EQV_V2DI:
15364 arg0 = gimple_call_arg (stmt, 0);
15365 arg1 = gimple_call_arg (stmt, 1);
15366 lhs = gimple_call_lhs (stmt);
15367 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15368 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15369 gimple_set_location (g, gimple_location (stmt));
15370 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15371 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15372 gimple_set_location (g, gimple_location (stmt));
15373 gsi_replace (gsi, g, true);
15375 /* Flavors of vec_rotate_left. */
15376 case ALTIVEC_BUILTIN_VRLB:
15377 case ALTIVEC_BUILTIN_VRLH:
15378 case ALTIVEC_BUILTIN_VRLW:
15379 case P8V_BUILTIN_VRLD:
15380 arg0 = gimple_call_arg (stmt, 0);
15381 arg1 = gimple_call_arg (stmt, 1);
15382 lhs = gimple_call_lhs (stmt);
15383 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15384 gimple_set_location (g, gimple_location (stmt));
15385 gsi_replace (gsi, g, true);
15387 /* Flavors of vector shift right algebraic.
15388 vec_sra{b,h,w} -> vsra{b,h,w}. */
15389 case ALTIVEC_BUILTIN_VSRAB:
15390 case ALTIVEC_BUILTIN_VSRAH:
15391 case ALTIVEC_BUILTIN_VSRAW:
15392 case P8V_BUILTIN_VSRAD:
15394 arg0 = gimple_call_arg (stmt, 0);
15395 arg1 = gimple_call_arg (stmt, 1);
15396 lhs = gimple_call_lhs (stmt);
15397 tree arg1_type = TREE_TYPE (arg1);
15398 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15399 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15400 location_t loc = gimple_location (stmt);
15401 /* Force arg1 into the range valid matching the arg0 type. */
15402 /* Build a vector consisting of the max valid bit-size values. */
15403 int n_elts = VECTOR_CST_NELTS (arg1);
15404 tree element_size = build_int_cst (unsigned_element_type,
15406 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15407 for (int i = 0; i < n_elts; i++)
15408 elts.safe_push (element_size);
15409 tree modulo_tree = elts.build ();
15410 /* Modulo the provided shift value against that vector. */
15411 gimple_seq stmts = NULL;
15412 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15413 unsigned_arg1_type, arg1);
15414 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15415 unsigned_arg1_type, unsigned_arg1,
15417 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15418 /* And finally, do the shift. */
15419 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
15420 gimple_set_location (g, loc);
15421 gsi_replace (gsi, g, true);
15424 /* Flavors of vector shift left.
15425 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15426 case ALTIVEC_BUILTIN_VSLB:
15427 case ALTIVEC_BUILTIN_VSLH:
15428 case ALTIVEC_BUILTIN_VSLW:
15429 case P8V_BUILTIN_VSLD:
15432 gimple_seq stmts = NULL;
15433 arg0 = gimple_call_arg (stmt, 0);
15434 tree arg0_type = TREE_TYPE (arg0);
15435 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15436 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15438 arg1 = gimple_call_arg (stmt, 1);
15439 tree arg1_type = TREE_TYPE (arg1);
15440 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15441 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15442 loc = gimple_location (stmt);
15443 lhs = gimple_call_lhs (stmt);
15444 /* Force arg1 into the range valid matching the arg0 type. */
15445 /* Build a vector consisting of the max valid bit-size values. */
15446 int n_elts = VECTOR_CST_NELTS (arg1);
15447 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15449 tree element_size = build_int_cst (unsigned_element_type,
15450 tree_size_in_bits / n_elts);
15451 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15452 for (int i = 0; i < n_elts; i++)
15453 elts.safe_push (element_size);
15454 tree modulo_tree = elts.build ();
15455 /* Modulo the provided shift value against that vector. */
15456 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15457 unsigned_arg1_type, arg1);
15458 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15459 unsigned_arg1_type, unsigned_arg1,
15461 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15462 /* And finally, do the shift. */
15463 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15464 gimple_set_location (g, gimple_location (stmt));
15465 gsi_replace (gsi, g, true);
15468 /* Flavors of vector shift right. */
15469 case ALTIVEC_BUILTIN_VSRB:
15470 case ALTIVEC_BUILTIN_VSRH:
15471 case ALTIVEC_BUILTIN_VSRW:
15472 case P8V_BUILTIN_VSRD:
15474 arg0 = gimple_call_arg (stmt, 0);
15475 arg1 = gimple_call_arg (stmt, 1);
15476 lhs = gimple_call_lhs (stmt);
15477 tree arg1_type = TREE_TYPE (arg1);
15478 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15479 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15480 location_t loc = gimple_location (stmt);
15481 gimple_seq stmts = NULL;
15482 /* Convert arg0 to unsigned. */
15484 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15485 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15486 /* Force arg1 into the range valid matching the arg0 type. */
15487 /* Build a vector consisting of the max valid bit-size values. */
15488 int n_elts = VECTOR_CST_NELTS (arg1);
15489 tree element_size = build_int_cst (unsigned_element_type,
15491 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15492 for (int i = 0; i < n_elts; i++)
15493 elts.safe_push (element_size);
15494 tree modulo_tree = elts.build ();
15495 /* Modulo the provided shift value against that vector. */
15496 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15497 unsigned_arg1_type, arg1);
15498 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15499 unsigned_arg1_type, unsigned_arg1,
15501 /* Do the shift. */
15503 = gimple_build (&stmts, RSHIFT_EXPR,
15504 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
15505 /* Convert result back to the lhs type. */
15506 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15507 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15508 update_call_from_tree (gsi, res);
15511 /* Vector loads. */
15512 case ALTIVEC_BUILTIN_LVX_V16QI:
15513 case ALTIVEC_BUILTIN_LVX_V8HI:
15514 case ALTIVEC_BUILTIN_LVX_V4SI:
15515 case ALTIVEC_BUILTIN_LVX_V4SF:
15516 case ALTIVEC_BUILTIN_LVX_V2DI:
15517 case ALTIVEC_BUILTIN_LVX_V2DF:
15518 case ALTIVEC_BUILTIN_LVX_V1TI:
15520 arg0 = gimple_call_arg (stmt, 0); // offset
15521 arg1 = gimple_call_arg (stmt, 1); // address
15522 lhs = gimple_call_lhs (stmt);
15523 location_t loc = gimple_location (stmt);
15524 /* Since arg1 may be cast to a different type, just use ptr_type_node
15525 here instead of trying to enforce TBAA on pointer types. */
15526 tree arg1_type = ptr_type_node;
15527 tree lhs_type = TREE_TYPE (lhs);
15528 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15529 the tree using the value from arg0. The resulting type will match
15530 the type of arg1. */
15531 gimple_seq stmts = NULL;
15532 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15533 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15534 arg1_type, arg1, temp_offset);
15535 /* Mask off any lower bits from the address. */
15536 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15537 arg1_type, temp_addr,
15538 build_int_cst (arg1_type, -16));
15539 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15540 if (!is_gimple_mem_ref_addr (aligned_addr))
15542 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15543 gimple *g = gimple_build_assign (t, aligned_addr);
15544 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15547 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15548 take an offset, but since we've already incorporated the offset
15549 above, here we just pass in a zero. */
15551 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15552 build_int_cst (arg1_type, 0)));
15553 gimple_set_location (g, loc);
15554 gsi_replace (gsi, g, true);
15557 /* Vector stores. */
15558 case ALTIVEC_BUILTIN_STVX_V16QI:
15559 case ALTIVEC_BUILTIN_STVX_V8HI:
15560 case ALTIVEC_BUILTIN_STVX_V4SI:
15561 case ALTIVEC_BUILTIN_STVX_V4SF:
15562 case ALTIVEC_BUILTIN_STVX_V2DI:
15563 case ALTIVEC_BUILTIN_STVX_V2DF:
15565 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15566 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15567 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15568 location_t loc = gimple_location (stmt);
15569 tree arg0_type = TREE_TYPE (arg0);
15570 /* Use ptr_type_node (no TBAA) for the arg2_type.
15571 FIXME: (Richard) "A proper fix would be to transition this type as
15572 seen from the frontend to GIMPLE, for example in a similar way we
15573 do for MEM_REFs by piggy-backing that on an extra argument, a
15574 constant zero pointer of the alias pointer type to use (which would
15575 also serve as a type indicator of the store itself). I'd use a
15576 target specific internal function for this (not sure if we can have
15577 those target specific, but I guess if it's folded away then that's
15578 fine) and get away with the overload set." */
15579 tree arg2_type = ptr_type_node;
15580 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15581 the tree using the value from arg0. The resulting type will match
15582 the type of arg2. */
15583 gimple_seq stmts = NULL;
15584 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15585 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15586 arg2_type, arg2, temp_offset);
15587 /* Mask off any lower bits from the address. */
15588 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15589 arg2_type, temp_addr,
15590 build_int_cst (arg2_type, -16));
15591 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15592 if (!is_gimple_mem_ref_addr (aligned_addr))
15594 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15595 gimple *g = gimple_build_assign (t, aligned_addr);
15596 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15599 /* The desired gimple result should be similar to:
15600 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15602 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15603 build_int_cst (arg2_type, 0)), arg0);
15604 gimple_set_location (g, loc);
15605 gsi_replace (gsi, g, true);
15609 /* unaligned Vector loads. */
15610 case VSX_BUILTIN_LXVW4X_V16QI:
15611 case VSX_BUILTIN_LXVW4X_V8HI:
15612 case VSX_BUILTIN_LXVW4X_V4SF:
15613 case VSX_BUILTIN_LXVW4X_V4SI:
15614 case VSX_BUILTIN_LXVD2X_V2DF:
15615 case VSX_BUILTIN_LXVD2X_V2DI:
15617 arg0 = gimple_call_arg (stmt, 0); // offset
15618 arg1 = gimple_call_arg (stmt, 1); // address
15619 lhs = gimple_call_lhs (stmt);
15620 location_t loc = gimple_location (stmt);
15621 /* Since arg1 may be cast to a different type, just use ptr_type_node
15622 here instead of trying to enforce TBAA on pointer types. */
15623 tree arg1_type = ptr_type_node;
15624 tree lhs_type = TREE_TYPE (lhs);
15625 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15626 required alignment (power) is 4 bytes regardless of data type. */
15627 tree align_ltype = build_aligned_type (lhs_type, 4);
15628 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15629 the tree using the value from arg0. The resulting type will match
15630 the type of arg1. */
15631 gimple_seq stmts = NULL;
15632 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15633 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15634 arg1_type, arg1, temp_offset);
15635 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15636 if (!is_gimple_mem_ref_addr (temp_addr))
15638 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15639 gimple *g = gimple_build_assign (t, temp_addr);
15640 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15643 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15644 take an offset, but since we've already incorporated the offset
15645 above, here we just pass in a zero. */
15647 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15648 build_int_cst (arg1_type, 0)));
15649 gimple_set_location (g, loc);
15650 gsi_replace (gsi, g, true);
15654 /* unaligned Vector stores. */
15655 case VSX_BUILTIN_STXVW4X_V16QI:
15656 case VSX_BUILTIN_STXVW4X_V8HI:
15657 case VSX_BUILTIN_STXVW4X_V4SF:
15658 case VSX_BUILTIN_STXVW4X_V4SI:
15659 case VSX_BUILTIN_STXVD2X_V2DF:
15660 case VSX_BUILTIN_STXVD2X_V2DI:
15662 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15663 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15664 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15665 location_t loc = gimple_location (stmt);
15666 tree arg0_type = TREE_TYPE (arg0);
15667 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15668 tree arg2_type = ptr_type_node;
15669 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15670 required alignment (power) is 4 bytes regardless of data type. */
15671 tree align_stype = build_aligned_type (arg0_type, 4);
15672 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15673 the tree using the value from arg1. */
15674 gimple_seq stmts = NULL;
15675 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15676 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15677 arg2_type, arg2, temp_offset);
15678 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15679 if (!is_gimple_mem_ref_addr (temp_addr))
15681 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15682 gimple *g = gimple_build_assign (t, temp_addr);
15683 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15687 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15688 build_int_cst (arg2_type, 0)), arg0);
15689 gimple_set_location (g, loc);
15690 gsi_replace (gsi, g, true);
15694 /* Vector Fused multiply-add (fma). */
15695 case ALTIVEC_BUILTIN_VMADDFP:
15696 case VSX_BUILTIN_XVMADDDP:
15697 case ALTIVEC_BUILTIN_VMLADDUHM:
15699 arg0 = gimple_call_arg (stmt, 0);
15700 arg1 = gimple_call_arg (stmt, 1);
15701 tree arg2 = gimple_call_arg (stmt, 2);
15702 lhs = gimple_call_lhs (stmt);
15703 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15704 gimple_call_set_lhs (g, lhs);
15705 gimple_call_set_nothrow (g, true);
15706 gimple_set_location (g, gimple_location (stmt));
15707 gsi_replace (gsi, g, true);
15711 /* Vector compares; EQ, NE, GE, GT, LE. */
15712 case ALTIVEC_BUILTIN_VCMPEQUB:
15713 case ALTIVEC_BUILTIN_VCMPEQUH:
15714 case ALTIVEC_BUILTIN_VCMPEQUW:
15715 case P8V_BUILTIN_VCMPEQUD:
15716 fold_compare_helper (gsi, EQ_EXPR, stmt);
15719 case P9V_BUILTIN_CMPNEB:
15720 case P9V_BUILTIN_CMPNEH:
15721 case P9V_BUILTIN_CMPNEW:
15722 fold_compare_helper (gsi, NE_EXPR, stmt);
15725 case VSX_BUILTIN_CMPGE_16QI:
15726 case VSX_BUILTIN_CMPGE_U16QI:
15727 case VSX_BUILTIN_CMPGE_8HI:
15728 case VSX_BUILTIN_CMPGE_U8HI:
15729 case VSX_BUILTIN_CMPGE_4SI:
15730 case VSX_BUILTIN_CMPGE_U4SI:
15731 case VSX_BUILTIN_CMPGE_2DI:
15732 case VSX_BUILTIN_CMPGE_U2DI:
15733 fold_compare_helper (gsi, GE_EXPR, stmt);
15736 case ALTIVEC_BUILTIN_VCMPGTSB:
15737 case ALTIVEC_BUILTIN_VCMPGTUB:
15738 case ALTIVEC_BUILTIN_VCMPGTSH:
15739 case ALTIVEC_BUILTIN_VCMPGTUH:
15740 case ALTIVEC_BUILTIN_VCMPGTSW:
15741 case ALTIVEC_BUILTIN_VCMPGTUW:
15742 case P8V_BUILTIN_VCMPGTUD:
15743 case P8V_BUILTIN_VCMPGTSD:
15744 fold_compare_helper (gsi, GT_EXPR, stmt);
15747 case VSX_BUILTIN_CMPLE_16QI:
15748 case VSX_BUILTIN_CMPLE_U16QI:
15749 case VSX_BUILTIN_CMPLE_8HI:
15750 case VSX_BUILTIN_CMPLE_U8HI:
15751 case VSX_BUILTIN_CMPLE_4SI:
15752 case VSX_BUILTIN_CMPLE_U4SI:
15753 case VSX_BUILTIN_CMPLE_2DI:
15754 case VSX_BUILTIN_CMPLE_U2DI:
15755 fold_compare_helper (gsi, LE_EXPR, stmt);
15758 /* flavors of vec_splat_[us]{8,16,32}. */
15759 case ALTIVEC_BUILTIN_VSPLTISB:
15760 case ALTIVEC_BUILTIN_VSPLTISH:
15761 case ALTIVEC_BUILTIN_VSPLTISW:
15763 arg0 = gimple_call_arg (stmt, 0);
15764 lhs = gimple_call_lhs (stmt);
15766 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15767 5-bit signed constant in range -16 to +15. */
15768 if (TREE_CODE (arg0) != INTEGER_CST
15769 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
15771 gimple_seq stmts = NULL;
15772 location_t loc = gimple_location (stmt);
15773 tree splat_value = gimple_convert (&stmts, loc,
15774 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15775 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15776 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15777 g = gimple_build_assign (lhs, splat_tree);
15778 gimple_set_location (g, gimple_location (stmt));
15779 gsi_replace (gsi, g, true);
15783 /* Flavors of vec_splat. */
15784 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15785 case ALTIVEC_BUILTIN_VSPLTB:
15786 case ALTIVEC_BUILTIN_VSPLTH:
15787 case ALTIVEC_BUILTIN_VSPLTW:
15788 case VSX_BUILTIN_XXSPLTD_V2DI:
15789 case VSX_BUILTIN_XXSPLTD_V2DF:
15791 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15792 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15793 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15794 is a valid index into the arg0 vector. */
15795 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15796 if (TREE_CODE (arg1) != INTEGER_CST
15797 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15799 lhs = gimple_call_lhs (stmt);
15800 tree lhs_type = TREE_TYPE (lhs);
15801 tree arg0_type = TREE_TYPE (arg0);
15803 if (TREE_CODE (arg0) == VECTOR_CST)
15804 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15807 /* Determine (in bits) the length and start location of the
15808 splat value for a call to the tree_vec_extract helper. */
15809 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15810 * BITS_PER_UNIT / n_elts;
15811 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15812 tree len = build_int_cst (bitsizetype, splat_elem_size);
15813 tree start = build_int_cst (bitsizetype, splat_start_bit);
15814 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15817 /* And finally, build the new vector. */
15818 tree splat_tree = build_vector_from_val (lhs_type, splat);
15819 g = gimple_build_assign (lhs, splat_tree);
15820 gimple_set_location (g, gimple_location (stmt));
15821 gsi_replace (gsi, g, true);
15825 /* vec_mergel (integrals). */
15826 case ALTIVEC_BUILTIN_VMRGLH:
15827 case ALTIVEC_BUILTIN_VMRGLW:
15828 case VSX_BUILTIN_XXMRGLW_4SI:
15829 case ALTIVEC_BUILTIN_VMRGLB:
15830 case VSX_BUILTIN_VEC_MERGEL_V2DI:
15831 case VSX_BUILTIN_XXMRGLW_4SF:
15832 case VSX_BUILTIN_VEC_MERGEL_V2DF:
15833 fold_mergehl_helper (gsi, stmt, 1);
15835 /* vec_mergeh (integrals). */
15836 case ALTIVEC_BUILTIN_VMRGHH:
15837 case ALTIVEC_BUILTIN_VMRGHW:
15838 case VSX_BUILTIN_XXMRGHW_4SI:
15839 case ALTIVEC_BUILTIN_VMRGHB:
15840 case VSX_BUILTIN_VEC_MERGEH_V2DI:
15841 case VSX_BUILTIN_XXMRGHW_4SF:
15842 case VSX_BUILTIN_VEC_MERGEH_V2DF:
15843 fold_mergehl_helper (gsi, stmt, 0);
15846 /* Flavors of vec_mergee. */
15847 case P8V_BUILTIN_VMRGEW_V4SI:
15848 case P8V_BUILTIN_VMRGEW_V2DI:
15849 case P8V_BUILTIN_VMRGEW_V4SF:
15850 case P8V_BUILTIN_VMRGEW_V2DF:
15851 fold_mergeeo_helper (gsi, stmt, 0);
15853 /* Flavors of vec_mergeo. */
15854 case P8V_BUILTIN_VMRGOW_V4SI:
15855 case P8V_BUILTIN_VMRGOW_V2DI:
15856 case P8V_BUILTIN_VMRGOW_V4SF:
15857 case P8V_BUILTIN_VMRGOW_V2DF:
15858 fold_mergeeo_helper (gsi, stmt, 1);
15861 /* d = vec_pack (a, b) */
15862 case P8V_BUILTIN_VPKUDUM:
15863 case ALTIVEC_BUILTIN_VPKUHUM:
15864 case ALTIVEC_BUILTIN_VPKUWUM:
15866 arg0 = gimple_call_arg (stmt, 0);
15867 arg1 = gimple_call_arg (stmt, 1);
15868 lhs = gimple_call_lhs (stmt);
15869 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
15870 gimple_set_location (g, gimple_location (stmt));
15871 gsi_replace (gsi, g, true);
15875 /* d = vec_unpackh (a) */
15876 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
15877 in this code is sensitive to endian-ness, and needs to be inverted to
15878 handle both LE and BE targets. */
15879 case ALTIVEC_BUILTIN_VUPKHSB:
15880 case ALTIVEC_BUILTIN_VUPKHSH:
15881 case P8V_BUILTIN_VUPKHSW:
15883 arg0 = gimple_call_arg (stmt, 0);
15884 lhs = gimple_call_lhs (stmt);
15885 if (BYTES_BIG_ENDIAN)
15886 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15888 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15889 gimple_set_location (g, gimple_location (stmt));
15890 gsi_replace (gsi, g, true);
15893 /* d = vec_unpackl (a) */
15894 case ALTIVEC_BUILTIN_VUPKLSB:
15895 case ALTIVEC_BUILTIN_VUPKLSH:
15896 case P8V_BUILTIN_VUPKLSW:
15898 arg0 = gimple_call_arg (stmt, 0);
15899 lhs = gimple_call_lhs (stmt);
15900 if (BYTES_BIG_ENDIAN)
15901 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15903 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15904 gimple_set_location (g, gimple_location (stmt));
15905 gsi_replace (gsi, g, true);
15908 /* There is no gimple type corresponding with pixel, so just return. */
15909 case ALTIVEC_BUILTIN_VUPKHPX:
15910 case ALTIVEC_BUILTIN_VUPKLPX:
15914 case ALTIVEC_BUILTIN_VPERM_16QI:
15915 case ALTIVEC_BUILTIN_VPERM_8HI:
15916 case ALTIVEC_BUILTIN_VPERM_4SI:
15917 case ALTIVEC_BUILTIN_VPERM_2DI:
15918 case ALTIVEC_BUILTIN_VPERM_4SF:
15919 case ALTIVEC_BUILTIN_VPERM_2DF:
15921 arg0 = gimple_call_arg (stmt, 0);
15922 arg1 = gimple_call_arg (stmt, 1);
15923 tree permute = gimple_call_arg (stmt, 2);
15924 lhs = gimple_call_lhs (stmt);
15925 location_t loc = gimple_location (stmt);
15926 gimple_seq stmts = NULL;
15927 // convert arg0 and arg1 to match the type of the permute
15928 // for the VEC_PERM_EXPR operation.
15929 tree permute_type = (TREE_TYPE (permute));
15930 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
15931 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
15932 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
15933 permute_type, arg0_ptype, arg1_ptype,
15935 // Convert the result back to the desired lhs type upon completion.
15936 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
15937 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15938 g = gimple_build_assign (lhs, temp);
15939 gimple_set_location (g, loc);
15940 gsi_replace (gsi, g, true);
15945 if (TARGET_DEBUG_BUILTIN)
15946 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
15947 fn_code, fn_name1, fn_name2);
15954 /* Expand an expression EXP that calls a built-in function,
15955 with result going to TARGET if that's convenient
15956 (and in mode MODE if that's convenient).
15957 SUBTARGET may be used as the target for computing one of EXP's operands.
15958 IGNORE is nonzero if the value is to be ignored. */
15961 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15962 machine_mode mode ATTRIBUTE_UNUSED,
15963 int ignore ATTRIBUTE_UNUSED)
15965 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15966 enum rs6000_builtins fcode
15967 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
15968 size_t uns_fcode = (size_t)fcode;
15969 const struct builtin_description *d;
15973 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
15974 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
15975 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
15977 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
15978 floating point type, depending on whether long double is the IBM extended
15979 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
15980 we only define one variant of the built-in function, and switch the code
15981 when defining it, rather than defining two built-ins and using the
15982 overload table in rs6000-c.c to switch between the two. If we don't have
15983 the proper assembler, don't do this switch because CODE_FOR_*kf* and
15984 CODE_FOR_*tf* will be CODE_FOR_nothing. */
15985 if (FLOAT128_IEEE_P (TFmode))
15991 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
15992 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
15993 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
15994 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
15995 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
15996 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
15997 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
15998 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
15999 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16000 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16001 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16002 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16003 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16006 if (TARGET_DEBUG_BUILTIN)
16008 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16009 const char *name2 = (icode != CODE_FOR_nothing)
16010 ? get_insn_name ((int) icode)
16014 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16016 default: name3 = "unknown"; break;
16017 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16018 case RS6000_BTC_UNARY: name3 = "unary"; break;
16019 case RS6000_BTC_BINARY: name3 = "binary"; break;
16020 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16021 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16022 case RS6000_BTC_ABS: name3 = "abs"; break;
16023 case RS6000_BTC_DST: name3 = "dst"; break;
16028 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16029 (name1) ? name1 : "---", fcode,
16030 (name2) ? name2 : "---", (int) icode,
16032 func_valid_p ? "" : ", not valid");
16037 rs6000_invalid_builtin (fcode);
16039 /* Given it is invalid, just generate a normal call. */
16040 return expand_call (exp, target, ignore);
16045 case RS6000_BUILTIN_RECIP:
16046 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16048 case RS6000_BUILTIN_RECIPF:
16049 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16051 case RS6000_BUILTIN_RSQRTF:
16052 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16054 case RS6000_BUILTIN_RSQRT:
16055 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16057 case POWER7_BUILTIN_BPERMD:
16058 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16059 ? CODE_FOR_bpermd_di
16060 : CODE_FOR_bpermd_si), exp, target);
16062 case RS6000_BUILTIN_GET_TB:
16063 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16066 case RS6000_BUILTIN_MFTB:
16067 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16068 ? CODE_FOR_rs6000_mftb_di
16069 : CODE_FOR_rs6000_mftb_si),
16072 case RS6000_BUILTIN_MFFS:
16073 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16075 case RS6000_BUILTIN_MTFSB0:
16076 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16078 case RS6000_BUILTIN_MTFSB1:
16079 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16081 case RS6000_BUILTIN_SET_FPSCR_RN:
16082 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16085 case RS6000_BUILTIN_SET_FPSCR_DRN:
16087 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16090 case RS6000_BUILTIN_MFFSL:
16091 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16093 case RS6000_BUILTIN_MTFSF:
16094 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16096 case RS6000_BUILTIN_CPU_INIT:
16097 case RS6000_BUILTIN_CPU_IS:
16098 case RS6000_BUILTIN_CPU_SUPPORTS:
16099 return cpu_expand_builtin (fcode, exp, target);
16101 case MISC_BUILTIN_SPEC_BARRIER:
16103 emit_insn (gen_speculation_barrier ());
16107 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16108 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16110 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16111 : (int) CODE_FOR_altivec_lvsl_direct);
16112 machine_mode tmode = insn_data[icode2].operand[0].mode;
16113 machine_mode mode = insn_data[icode2].operand[1].mode;
16117 gcc_assert (TARGET_ALTIVEC);
16119 arg = CALL_EXPR_ARG (exp, 0);
16120 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16121 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16122 addr = memory_address (mode, op);
16123 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16127 /* For the load case need to negate the address. */
16128 op = gen_reg_rtx (GET_MODE (addr));
16129 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16131 op = gen_rtx_MEM (mode, op);
16134 || GET_MODE (target) != tmode
16135 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16136 target = gen_reg_rtx (tmode);
16138 pat = GEN_FCN (icode2) (target, op);
16146 case ALTIVEC_BUILTIN_VCFUX:
16147 case ALTIVEC_BUILTIN_VCFSX:
16148 case ALTIVEC_BUILTIN_VCTUXS:
16149 case ALTIVEC_BUILTIN_VCTSXS:
16150 /* FIXME: There's got to be a nicer way to handle this case than
16151 constructing a new CALL_EXPR. */
16152 if (call_expr_nargs (exp) == 1)
16154 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16155 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16159 /* For the pack and unpack int128 routines, fix up the builtin so it
16160 uses the correct IBM128 type. */
16161 case MISC_BUILTIN_PACK_IF:
16162 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16164 icode = CODE_FOR_packtf;
16165 fcode = MISC_BUILTIN_PACK_TF;
16166 uns_fcode = (size_t)fcode;
16170 case MISC_BUILTIN_UNPACK_IF:
16171 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16173 icode = CODE_FOR_unpacktf;
16174 fcode = MISC_BUILTIN_UNPACK_TF;
16175 uns_fcode = (size_t)fcode;
16183 if (TARGET_ALTIVEC)
16185 ret = altivec_expand_builtin (exp, target, &success);
16192 ret = htm_expand_builtin (exp, target, &success);
16198 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16199 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16200 gcc_assert (attr == RS6000_BTC_UNARY
16201 || attr == RS6000_BTC_BINARY
16202 || attr == RS6000_BTC_TERNARY
16203 || attr == RS6000_BTC_SPECIAL);
16205 /* Handle simple unary operations. */
16207 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16208 if (d->code == fcode)
16209 return rs6000_expand_unop_builtin (icode, exp, target);
16211 /* Handle simple binary operations. */
16213 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16214 if (d->code == fcode)
16215 return rs6000_expand_binop_builtin (icode, exp, target);
16217 /* Handle simple ternary operations. */
16219 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16220 if (d->code == fcode)
16221 return rs6000_expand_ternop_builtin (icode, exp, target);
16223 /* Handle simple no-argument operations. */
16225 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16226 if (d->code == fcode)
16227 return rs6000_expand_zeroop_builtin (icode, target);
16229 gcc_unreachable ();
16232 /* Create a builtin vector type with a name. Taking care not to give
16233 the canonical type a name. */
16236 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16238 tree result = build_vector_type (elt_type, num_elts);
16240 /* Copy so we don't give the canonical type a name. */
16241 result = build_variant_type_copy (result);
16243 add_builtin_type (name, result);
16249 rs6000_init_builtins (void)
16255 if (TARGET_DEBUG_BUILTIN)
16256 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16257 (TARGET_ALTIVEC) ? ", altivec" : "",
16258 (TARGET_VSX) ? ", vsx" : "");
16260 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16261 : "__vector long long",
16262 intDI_type_node, 2);
16263 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16264 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16265 intSI_type_node, 4);
16266 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16267 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16268 intHI_type_node, 8);
16269 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16270 intQI_type_node, 16);
16272 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16273 unsigned_intQI_type_node, 16);
16274 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16275 unsigned_intHI_type_node, 8);
16276 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16277 unsigned_intSI_type_node, 4);
16278 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16279 ? "__vector unsigned long"
16280 : "__vector unsigned long long",
16281 unsigned_intDI_type_node, 2);
16283 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16285 const_str_type_node
16286 = build_pointer_type (build_qualified_type (char_type_node,
16289 /* We use V1TI mode as a special container to hold __int128_t items that
16290 must live in VSX registers. */
16291 if (intTI_type_node)
16293 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16294 intTI_type_node, 1);
16295 unsigned_V1TI_type_node
16296 = rs6000_vector_type ("__vector unsigned __int128",
16297 unsigned_intTI_type_node, 1);
16300 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16301 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16302 'vector unsigned short'. */
16304 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16305 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16306 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16307 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16308 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16310 long_integer_type_internal_node = long_integer_type_node;
16311 long_unsigned_type_internal_node = long_unsigned_type_node;
16312 long_long_integer_type_internal_node = long_long_integer_type_node;
16313 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16314 intQI_type_internal_node = intQI_type_node;
16315 uintQI_type_internal_node = unsigned_intQI_type_node;
16316 intHI_type_internal_node = intHI_type_node;
16317 uintHI_type_internal_node = unsigned_intHI_type_node;
16318 intSI_type_internal_node = intSI_type_node;
16319 uintSI_type_internal_node = unsigned_intSI_type_node;
16320 intDI_type_internal_node = intDI_type_node;
16321 uintDI_type_internal_node = unsigned_intDI_type_node;
16322 intTI_type_internal_node = intTI_type_node;
16323 uintTI_type_internal_node = unsigned_intTI_type_node;
16324 float_type_internal_node = float_type_node;
16325 double_type_internal_node = double_type_node;
16326 long_double_type_internal_node = long_double_type_node;
16327 dfloat64_type_internal_node = dfloat64_type_node;
16328 dfloat128_type_internal_node = dfloat128_type_node;
16329 void_type_internal_node = void_type_node;
16331 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16332 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16333 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16334 format that uses a pair of doubles, depending on the switches and
16337 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16338 floating point, we need make sure the type is non-zero or else self-test
16339 fails during bootstrap.
16341 Always create __ibm128 as a separate type, even if the current long double
16342 format is IBM extended double.
16344 For IEEE 128-bit floating point, always create the type __ieee128. If the
16345 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16347 if (TARGET_FLOAT128_TYPE)
16349 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16350 ibm128_float_type_node = long_double_type_node;
16353 ibm128_float_type_node = make_node (REAL_TYPE);
16354 TYPE_PRECISION (ibm128_float_type_node) = 128;
16355 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16356 layout_type (ibm128_float_type_node);
16359 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16362 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16363 ieee128_float_type_node = long_double_type_node;
16365 ieee128_float_type_node = float128_type_node;
16367 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16372 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16374 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16376 builtin_mode_to_type[QImode][0] = integer_type_node;
16377 builtin_mode_to_type[HImode][0] = integer_type_node;
16378 builtin_mode_to_type[SImode][0] = intSI_type_node;
16379 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16380 builtin_mode_to_type[DImode][0] = intDI_type_node;
16381 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16382 builtin_mode_to_type[TImode][0] = intTI_type_node;
16383 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16384 builtin_mode_to_type[SFmode][0] = float_type_node;
16385 builtin_mode_to_type[DFmode][0] = double_type_node;
16386 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16387 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16388 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16389 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16390 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16391 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16392 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16393 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16394 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16395 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16396 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16397 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16398 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16399 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16400 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16401 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16402 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16404 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16405 TYPE_NAME (bool_char_type_node) = tdecl;
16407 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16408 TYPE_NAME (bool_short_type_node) = tdecl;
16410 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16411 TYPE_NAME (bool_int_type_node) = tdecl;
16413 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16414 TYPE_NAME (pixel_type_node) = tdecl;
16416 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16417 bool_char_type_node, 16);
16418 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16419 bool_short_type_node, 8);
16420 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16421 bool_int_type_node, 4);
16422 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16423 ? "__vector __bool long"
16424 : "__vector __bool long long",
16425 bool_long_long_type_node, 2);
16426 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16427 pixel_type_node, 8);
16429 /* Create Altivec and VSX builtins on machines with at least the
16430 general purpose extensions (970 and newer) to allow the use of
16431 the target attribute. */
16432 if (TARGET_EXTRA_BUILTINS)
16433 altivec_init_builtins ();
16435 htm_init_builtins ();
16437 if (TARGET_EXTRA_BUILTINS)
16438 rs6000_common_init_builtins ();
16440 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16441 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16442 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16444 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16445 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16446 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16448 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16449 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16450 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16452 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16453 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16454 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16456 mode = (TARGET_64BIT) ? DImode : SImode;
16457 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16458 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16459 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16461 ftype = build_function_type_list (unsigned_intDI_type_node,
16463 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16466 ftype = build_function_type_list (unsigned_intDI_type_node,
16469 ftype = build_function_type_list (unsigned_intSI_type_node,
16471 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16473 ftype = build_function_type_list (double_type_node, NULL_TREE);
16474 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16476 ftype = build_function_type_list (double_type_node, NULL_TREE);
16477 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16479 ftype = build_function_type_list (void_type_node,
16482 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16484 ftype = build_function_type_list (void_type_node,
16487 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16489 ftype = build_function_type_list (void_type_node,
16492 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16494 ftype = build_function_type_list (void_type_node,
16497 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16499 ftype = build_function_type_list (void_type_node,
16500 intSI_type_node, double_type_node,
16502 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16504 ftype = build_function_type_list (void_type_node, NULL_TREE);
16505 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16506 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16507 MISC_BUILTIN_SPEC_BARRIER);
16509 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16511 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16512 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16514 /* AIX libm provides clog as __clog. */
16515 if (TARGET_XCOFF &&
16516 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16517 set_user_assembler_name (tdecl, "__clog");
16519 #ifdef SUBTARGET_INIT_BUILTINS
16520 SUBTARGET_INIT_BUILTINS;
16524 /* Returns the rs6000 builtin decl for CODE. */
16527 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16529 HOST_WIDE_INT fnmask;
16531 if (code >= RS6000_BUILTIN_COUNT)
16532 return error_mark_node;
16534 fnmask = rs6000_builtin_info[code].mask;
16535 if ((fnmask & rs6000_builtin_mask) != fnmask)
16537 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16538 return error_mark_node;
16541 return rs6000_builtin_decls[code];
16545 altivec_init_builtins (void)
16547 const struct builtin_description *d;
16551 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16553 tree pvoid_type_node = build_pointer_type (void_type_node);
16555 tree pcvoid_type_node
16556 = build_pointer_type (build_qualified_type (void_type_node,
16559 tree int_ftype_opaque
16560 = build_function_type_list (integer_type_node,
16561 opaque_V4SI_type_node, NULL_TREE);
16562 tree opaque_ftype_opaque
16563 = build_function_type_list (integer_type_node, NULL_TREE);
16564 tree opaque_ftype_opaque_int
16565 = build_function_type_list (opaque_V4SI_type_node,
16566 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16567 tree opaque_ftype_opaque_opaque_int
16568 = build_function_type_list (opaque_V4SI_type_node,
16569 opaque_V4SI_type_node, opaque_V4SI_type_node,
16570 integer_type_node, NULL_TREE);
16571 tree opaque_ftype_opaque_opaque_opaque
16572 = build_function_type_list (opaque_V4SI_type_node,
16573 opaque_V4SI_type_node, opaque_V4SI_type_node,
16574 opaque_V4SI_type_node, NULL_TREE);
16575 tree opaque_ftype_opaque_opaque
16576 = build_function_type_list (opaque_V4SI_type_node,
16577 opaque_V4SI_type_node, opaque_V4SI_type_node,
16579 tree int_ftype_int_opaque_opaque
16580 = build_function_type_list (integer_type_node,
16581 integer_type_node, opaque_V4SI_type_node,
16582 opaque_V4SI_type_node, NULL_TREE);
16583 tree int_ftype_int_v4si_v4si
16584 = build_function_type_list (integer_type_node,
16585 integer_type_node, V4SI_type_node,
16586 V4SI_type_node, NULL_TREE);
16587 tree int_ftype_int_v2di_v2di
16588 = build_function_type_list (integer_type_node,
16589 integer_type_node, V2DI_type_node,
16590 V2DI_type_node, NULL_TREE);
16591 tree void_ftype_v4si
16592 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16593 tree v8hi_ftype_void
16594 = build_function_type_list (V8HI_type_node, NULL_TREE);
16595 tree void_ftype_void
16596 = build_function_type_list (void_type_node, NULL_TREE);
16597 tree void_ftype_int
16598 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16600 tree opaque_ftype_long_pcvoid
16601 = build_function_type_list (opaque_V4SI_type_node,
16602 long_integer_type_node, pcvoid_type_node,
16604 tree v16qi_ftype_long_pcvoid
16605 = build_function_type_list (V16QI_type_node,
16606 long_integer_type_node, pcvoid_type_node,
16608 tree v8hi_ftype_long_pcvoid
16609 = build_function_type_list (V8HI_type_node,
16610 long_integer_type_node, pcvoid_type_node,
16612 tree v4si_ftype_long_pcvoid
16613 = build_function_type_list (V4SI_type_node,
16614 long_integer_type_node, pcvoid_type_node,
16616 tree v4sf_ftype_long_pcvoid
16617 = build_function_type_list (V4SF_type_node,
16618 long_integer_type_node, pcvoid_type_node,
16620 tree v2df_ftype_long_pcvoid
16621 = build_function_type_list (V2DF_type_node,
16622 long_integer_type_node, pcvoid_type_node,
16624 tree v2di_ftype_long_pcvoid
16625 = build_function_type_list (V2DI_type_node,
16626 long_integer_type_node, pcvoid_type_node,
16628 tree v1ti_ftype_long_pcvoid
16629 = build_function_type_list (V1TI_type_node,
16630 long_integer_type_node, pcvoid_type_node,
16633 tree void_ftype_opaque_long_pvoid
16634 = build_function_type_list (void_type_node,
16635 opaque_V4SI_type_node, long_integer_type_node,
16636 pvoid_type_node, NULL_TREE);
16637 tree void_ftype_v4si_long_pvoid
16638 = build_function_type_list (void_type_node,
16639 V4SI_type_node, long_integer_type_node,
16640 pvoid_type_node, NULL_TREE);
16641 tree void_ftype_v16qi_long_pvoid
16642 = build_function_type_list (void_type_node,
16643 V16QI_type_node, long_integer_type_node,
16644 pvoid_type_node, NULL_TREE);
16646 tree void_ftype_v16qi_pvoid_long
16647 = build_function_type_list (void_type_node,
16648 V16QI_type_node, pvoid_type_node,
16649 long_integer_type_node, NULL_TREE);
16651 tree void_ftype_v8hi_long_pvoid
16652 = build_function_type_list (void_type_node,
16653 V8HI_type_node, long_integer_type_node,
16654 pvoid_type_node, NULL_TREE);
16655 tree void_ftype_v4sf_long_pvoid
16656 = build_function_type_list (void_type_node,
16657 V4SF_type_node, long_integer_type_node,
16658 pvoid_type_node, NULL_TREE);
16659 tree void_ftype_v2df_long_pvoid
16660 = build_function_type_list (void_type_node,
16661 V2DF_type_node, long_integer_type_node,
16662 pvoid_type_node, NULL_TREE);
16663 tree void_ftype_v1ti_long_pvoid
16664 = build_function_type_list (void_type_node,
16665 V1TI_type_node, long_integer_type_node,
16666 pvoid_type_node, NULL_TREE);
16667 tree void_ftype_v2di_long_pvoid
16668 = build_function_type_list (void_type_node,
16669 V2DI_type_node, long_integer_type_node,
16670 pvoid_type_node, NULL_TREE);
16671 tree int_ftype_int_v8hi_v8hi
16672 = build_function_type_list (integer_type_node,
16673 integer_type_node, V8HI_type_node,
16674 V8HI_type_node, NULL_TREE);
16675 tree int_ftype_int_v16qi_v16qi
16676 = build_function_type_list (integer_type_node,
16677 integer_type_node, V16QI_type_node,
16678 V16QI_type_node, NULL_TREE);
16679 tree int_ftype_int_v4sf_v4sf
16680 = build_function_type_list (integer_type_node,
16681 integer_type_node, V4SF_type_node,
16682 V4SF_type_node, NULL_TREE);
16683 tree int_ftype_int_v2df_v2df
16684 = build_function_type_list (integer_type_node,
16685 integer_type_node, V2DF_type_node,
16686 V2DF_type_node, NULL_TREE);
16687 tree v2di_ftype_v2di
16688 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16689 tree v4si_ftype_v4si
16690 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16691 tree v8hi_ftype_v8hi
16692 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16693 tree v16qi_ftype_v16qi
16694 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16695 tree v4sf_ftype_v4sf
16696 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16697 tree v2df_ftype_v2df
16698 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16699 tree void_ftype_pcvoid_int_int
16700 = build_function_type_list (void_type_node,
16701 pcvoid_type_node, integer_type_node,
16702 integer_type_node, NULL_TREE);
16704 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16705 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16706 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16707 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16708 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16709 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16710 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16711 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16712 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16713 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16714 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16715 ALTIVEC_BUILTIN_LVXL_V2DF);
16716 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16717 ALTIVEC_BUILTIN_LVXL_V2DI);
16718 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16719 ALTIVEC_BUILTIN_LVXL_V4SF);
16720 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16721 ALTIVEC_BUILTIN_LVXL_V4SI);
16722 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16723 ALTIVEC_BUILTIN_LVXL_V8HI);
16724 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16725 ALTIVEC_BUILTIN_LVXL_V16QI);
16726 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16727 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16728 ALTIVEC_BUILTIN_LVX_V1TI);
16729 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16730 ALTIVEC_BUILTIN_LVX_V2DF);
16731 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16732 ALTIVEC_BUILTIN_LVX_V2DI);
16733 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16734 ALTIVEC_BUILTIN_LVX_V4SF);
16735 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16736 ALTIVEC_BUILTIN_LVX_V4SI);
16737 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16738 ALTIVEC_BUILTIN_LVX_V8HI);
16739 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16740 ALTIVEC_BUILTIN_LVX_V16QI);
16741 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16742 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16743 ALTIVEC_BUILTIN_STVX_V2DF);
16744 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16745 ALTIVEC_BUILTIN_STVX_V2DI);
16746 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16747 ALTIVEC_BUILTIN_STVX_V4SF);
16748 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16749 ALTIVEC_BUILTIN_STVX_V4SI);
16750 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16751 ALTIVEC_BUILTIN_STVX_V8HI);
16752 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16753 ALTIVEC_BUILTIN_STVX_V16QI);
16754 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16755 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16756 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16757 ALTIVEC_BUILTIN_STVXL_V2DF);
16758 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16759 ALTIVEC_BUILTIN_STVXL_V2DI);
16760 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16761 ALTIVEC_BUILTIN_STVXL_V4SF);
16762 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16763 ALTIVEC_BUILTIN_STVXL_V4SI);
16764 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16765 ALTIVEC_BUILTIN_STVXL_V8HI);
16766 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16767 ALTIVEC_BUILTIN_STVXL_V16QI);
16768 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16769 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16770 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16771 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16772 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16773 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16774 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16775 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16776 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16777 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16778 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16779 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16780 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16781 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16782 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16783 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16785 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16786 VSX_BUILTIN_LXVD2X_V2DF);
16787 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16788 VSX_BUILTIN_LXVD2X_V2DI);
16789 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16790 VSX_BUILTIN_LXVW4X_V4SF);
16791 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16792 VSX_BUILTIN_LXVW4X_V4SI);
16793 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16794 VSX_BUILTIN_LXVW4X_V8HI);
16795 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16796 VSX_BUILTIN_LXVW4X_V16QI);
16797 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16798 VSX_BUILTIN_STXVD2X_V2DF);
16799 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16800 VSX_BUILTIN_STXVD2X_V2DI);
16801 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16802 VSX_BUILTIN_STXVW4X_V4SF);
16803 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16804 VSX_BUILTIN_STXVW4X_V4SI);
16805 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16806 VSX_BUILTIN_STXVW4X_V8HI);
16807 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16808 VSX_BUILTIN_STXVW4X_V16QI);
16810 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16811 VSX_BUILTIN_LD_ELEMREV_V2DF);
16812 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16813 VSX_BUILTIN_LD_ELEMREV_V2DI);
16814 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16815 VSX_BUILTIN_LD_ELEMREV_V4SF);
16816 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16817 VSX_BUILTIN_LD_ELEMREV_V4SI);
16818 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16819 VSX_BUILTIN_LD_ELEMREV_V8HI);
16820 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16821 VSX_BUILTIN_LD_ELEMREV_V16QI);
16822 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16823 VSX_BUILTIN_ST_ELEMREV_V2DF);
16824 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16825 VSX_BUILTIN_ST_ELEMREV_V1TI);
16826 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16827 VSX_BUILTIN_ST_ELEMREV_V2DI);
16828 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16829 VSX_BUILTIN_ST_ELEMREV_V4SF);
16830 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16831 VSX_BUILTIN_ST_ELEMREV_V4SI);
16832 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16833 VSX_BUILTIN_ST_ELEMREV_V8HI);
16834 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16835 VSX_BUILTIN_ST_ELEMREV_V16QI);
16837 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16838 VSX_BUILTIN_VEC_LD);
16839 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16840 VSX_BUILTIN_VEC_ST);
16841 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16842 VSX_BUILTIN_VEC_XL);
16843 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16844 VSX_BUILTIN_VEC_XL_BE);
16845 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16846 VSX_BUILTIN_VEC_XST);
16847 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16848 VSX_BUILTIN_VEC_XST_BE);
16850 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16851 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16852 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16854 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16855 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16856 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16857 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16858 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16859 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16860 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16861 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16862 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16863 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16864 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16865 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16867 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16868 ALTIVEC_BUILTIN_VEC_ADDE);
16869 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16870 ALTIVEC_BUILTIN_VEC_ADDEC);
16871 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16872 ALTIVEC_BUILTIN_VEC_CMPNE);
16873 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16874 ALTIVEC_BUILTIN_VEC_MUL);
16875 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16876 ALTIVEC_BUILTIN_VEC_SUBE);
16877 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16878 ALTIVEC_BUILTIN_VEC_SUBEC);
16880 /* Cell builtins. */
16881 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16882 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16883 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16884 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16886 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16887 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16888 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16889 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16891 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16892 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16893 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16894 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16896 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16897 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16898 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16899 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16901 if (TARGET_P9_VECTOR)
16903 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16904 P9V_BUILTIN_STXVL);
16905 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16906 P9V_BUILTIN_XST_LEN_R);
16909 /* Add the DST variants. */
16911 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16913 HOST_WIDE_INT mask = d->mask;
16915 /* It is expected that these dst built-in functions may have
16916 d->icode equal to CODE_FOR_nothing. */
16917 if ((mask & builtin_mask) != mask)
16919 if (TARGET_DEBUG_BUILTIN)
16920 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16924 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16927 /* Initialize the predicates. */
16928 d = bdesc_altivec_preds;
16929 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16931 machine_mode mode1;
16933 HOST_WIDE_INT mask = d->mask;
16935 if ((mask & builtin_mask) != mask)
16937 if (TARGET_DEBUG_BUILTIN)
16938 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16943 if (rs6000_overloaded_builtin_p (d->code))
16947 /* Cannot define builtin if the instruction is disabled. */
16948 gcc_assert (d->icode != CODE_FOR_nothing);
16949 mode1 = insn_data[d->icode].operand[1].mode;
16955 type = int_ftype_int_opaque_opaque;
16958 type = int_ftype_int_v2di_v2di;
16961 type = int_ftype_int_v4si_v4si;
16964 type = int_ftype_int_v8hi_v8hi;
16967 type = int_ftype_int_v16qi_v16qi;
16970 type = int_ftype_int_v4sf_v4sf;
16973 type = int_ftype_int_v2df_v2df;
16976 gcc_unreachable ();
16979 def_builtin (d->name, type, d->code);
16982 /* Initialize the abs* operators. */
16984 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
16986 machine_mode mode0;
16988 HOST_WIDE_INT mask = d->mask;
16990 if ((mask & builtin_mask) != mask)
16992 if (TARGET_DEBUG_BUILTIN)
16993 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
16998 /* Cannot define builtin if the instruction is disabled. */
16999 gcc_assert (d->icode != CODE_FOR_nothing);
17000 mode0 = insn_data[d->icode].operand[0].mode;
17005 type = v2di_ftype_v2di;
17008 type = v4si_ftype_v4si;
17011 type = v8hi_ftype_v8hi;
17014 type = v16qi_ftype_v16qi;
17017 type = v4sf_ftype_v4sf;
17020 type = v2df_ftype_v2df;
17023 gcc_unreachable ();
17026 def_builtin (d->name, type, d->code);
17029 /* Initialize target builtin that implements
17030 targetm.vectorize.builtin_mask_for_load. */
17032 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17033 v16qi_ftype_long_pcvoid,
17034 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17035 BUILT_IN_MD, NULL, NULL_TREE);
17036 TREE_READONLY (decl) = 1;
17037 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17038 altivec_builtin_mask_for_load = decl;
17040 /* Access to the vec_init patterns. */
17041 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17042 integer_type_node, integer_type_node,
17043 integer_type_node, NULL_TREE);
17044 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17046 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17047 short_integer_type_node,
17048 short_integer_type_node,
17049 short_integer_type_node,
17050 short_integer_type_node,
17051 short_integer_type_node,
17052 short_integer_type_node,
17053 short_integer_type_node, NULL_TREE);
17054 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17056 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17057 char_type_node, char_type_node,
17058 char_type_node, char_type_node,
17059 char_type_node, char_type_node,
17060 char_type_node, char_type_node,
17061 char_type_node, char_type_node,
17062 char_type_node, char_type_node,
17063 char_type_node, char_type_node,
17064 char_type_node, NULL_TREE);
17065 def_builtin ("__builtin_vec_init_v16qi", ftype,
17066 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17068 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17069 float_type_node, float_type_node,
17070 float_type_node, NULL_TREE);
17071 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17073 /* VSX builtins. */
17074 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17075 double_type_node, NULL_TREE);
17076 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17078 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17079 intDI_type_node, NULL_TREE);
17080 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17082 /* Access to the vec_set patterns. */
17083 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17085 integer_type_node, NULL_TREE);
17086 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17088 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17090 integer_type_node, NULL_TREE);
17091 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17093 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17095 integer_type_node, NULL_TREE);
17096 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17098 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17100 integer_type_node, NULL_TREE);
17101 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17103 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17105 integer_type_node, NULL_TREE);
17106 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17108 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17110 integer_type_node, NULL_TREE);
17111 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17113 /* Access to the vec_extract patterns. */
17114 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17115 integer_type_node, NULL_TREE);
17116 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17118 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17119 integer_type_node, NULL_TREE);
17120 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17122 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17123 integer_type_node, NULL_TREE);
17124 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17126 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17127 integer_type_node, NULL_TREE);
17128 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17130 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17131 integer_type_node, NULL_TREE);
17132 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17134 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17135 integer_type_node, NULL_TREE);
17136 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17139 if (V1TI_type_node)
17141 tree v1ti_ftype_long_pcvoid
17142 = build_function_type_list (V1TI_type_node,
17143 long_integer_type_node, pcvoid_type_node,
17145 tree void_ftype_v1ti_long_pvoid
17146 = build_function_type_list (void_type_node,
17147 V1TI_type_node, long_integer_type_node,
17148 pvoid_type_node, NULL_TREE);
17149 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17150 VSX_BUILTIN_LD_ELEMREV_V1TI);
17151 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17152 VSX_BUILTIN_LXVD2X_V1TI);
17153 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17154 VSX_BUILTIN_STXVD2X_V1TI);
17155 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17156 NULL_TREE, NULL_TREE);
17157 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17158 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17160 integer_type_node, NULL_TREE);
17161 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17162 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17163 integer_type_node, NULL_TREE);
17164 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17170 htm_init_builtins (void)
17172 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17173 const struct builtin_description *d;
17177 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17179 tree op[MAX_HTM_OPERANDS], type;
17180 HOST_WIDE_INT mask = d->mask;
17181 unsigned attr = rs6000_builtin_info[d->code].attr;
17182 bool void_func = (attr & RS6000_BTC_VOID);
17183 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17185 tree gpr_type_node;
17189 /* It is expected that these htm built-in functions may have
17190 d->icode equal to CODE_FOR_nothing. */
17192 if (TARGET_32BIT && TARGET_POWERPC64)
17193 gpr_type_node = long_long_unsigned_type_node;
17195 gpr_type_node = long_unsigned_type_node;
17197 if (attr & RS6000_BTC_SPR)
17199 rettype = gpr_type_node;
17200 argtype = gpr_type_node;
17202 else if (d->code == HTM_BUILTIN_TABORTDC
17203 || d->code == HTM_BUILTIN_TABORTDCI)
17205 rettype = unsigned_type_node;
17206 argtype = gpr_type_node;
17210 rettype = unsigned_type_node;
17211 argtype = unsigned_type_node;
17214 if ((mask & builtin_mask) != mask)
17216 if (TARGET_DEBUG_BUILTIN)
17217 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17223 if (TARGET_DEBUG_BUILTIN)
17224 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17225 (long unsigned) i);
17229 op[nopnds++] = (void_func) ? void_type_node : rettype;
17231 if (attr_args == RS6000_BTC_UNARY)
17232 op[nopnds++] = argtype;
17233 else if (attr_args == RS6000_BTC_BINARY)
17235 op[nopnds++] = argtype;
17236 op[nopnds++] = argtype;
17238 else if (attr_args == RS6000_BTC_TERNARY)
17240 op[nopnds++] = argtype;
17241 op[nopnds++] = argtype;
17242 op[nopnds++] = argtype;
17248 type = build_function_type_list (op[0], NULL_TREE);
17251 type = build_function_type_list (op[0], op[1], NULL_TREE);
17254 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17257 type = build_function_type_list (op[0], op[1], op[2], op[3],
17261 gcc_unreachable ();
17264 def_builtin (d->name, type, d->code);
17268 /* Hash function for builtin functions with up to 3 arguments and a return
17271 builtin_hasher::hash (builtin_hash_struct *bh)
17276 for (i = 0; i < 4; i++)
17278 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17279 ret = (ret * 2) + bh->uns_p[i];
17285 /* Compare builtin hash entries H1 and H2 for equivalence. */
17287 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17289 return ((p1->mode[0] == p2->mode[0])
17290 && (p1->mode[1] == p2->mode[1])
17291 && (p1->mode[2] == p2->mode[2])
17292 && (p1->mode[3] == p2->mode[3])
17293 && (p1->uns_p[0] == p2->uns_p[0])
17294 && (p1->uns_p[1] == p2->uns_p[1])
17295 && (p1->uns_p[2] == p2->uns_p[2])
17296 && (p1->uns_p[3] == p2->uns_p[3]));
17299 /* Map types for builtin functions with an explicit return type and up to 3
17300 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17301 of the argument. */
17303 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17304 machine_mode mode_arg1, machine_mode mode_arg2,
17305 enum rs6000_builtins builtin, const char *name)
17307 struct builtin_hash_struct h;
17308 struct builtin_hash_struct *h2;
17311 tree ret_type = NULL_TREE;
17312 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17314 /* Create builtin_hash_table. */
17315 if (builtin_hash_table == NULL)
17316 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17318 h.type = NULL_TREE;
17319 h.mode[0] = mode_ret;
17320 h.mode[1] = mode_arg0;
17321 h.mode[2] = mode_arg1;
17322 h.mode[3] = mode_arg2;
17328 /* If the builtin is a type that produces unsigned results or takes unsigned
17329 arguments, and it is returned as a decl for the vectorizer (such as
17330 widening multiplies, permute), make sure the arguments and return value
17331 are type correct. */
17334 /* unsigned 1 argument functions. */
17335 case CRYPTO_BUILTIN_VSBOX:
17336 case CRYPTO_BUILTIN_VSBOX_BE:
17337 case P8V_BUILTIN_VGBBD:
17338 case MISC_BUILTIN_CDTBCD:
17339 case MISC_BUILTIN_CBCDTD:
17344 /* unsigned 2 argument functions. */
17345 case ALTIVEC_BUILTIN_VMULEUB:
17346 case ALTIVEC_BUILTIN_VMULEUH:
17347 case P8V_BUILTIN_VMULEUW:
17348 case ALTIVEC_BUILTIN_VMULOUB:
17349 case ALTIVEC_BUILTIN_VMULOUH:
17350 case P8V_BUILTIN_VMULOUW:
17351 case CRYPTO_BUILTIN_VCIPHER:
17352 case CRYPTO_BUILTIN_VCIPHER_BE:
17353 case CRYPTO_BUILTIN_VCIPHERLAST:
17354 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
17355 case CRYPTO_BUILTIN_VNCIPHER:
17356 case CRYPTO_BUILTIN_VNCIPHER_BE:
17357 case CRYPTO_BUILTIN_VNCIPHERLAST:
17358 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
17359 case CRYPTO_BUILTIN_VPMSUMB:
17360 case CRYPTO_BUILTIN_VPMSUMH:
17361 case CRYPTO_BUILTIN_VPMSUMW:
17362 case CRYPTO_BUILTIN_VPMSUMD:
17363 case CRYPTO_BUILTIN_VPMSUM:
17364 case MISC_BUILTIN_ADDG6S:
17365 case MISC_BUILTIN_DIVWEU:
17366 case MISC_BUILTIN_DIVDEU:
17367 case VSX_BUILTIN_UDIV_V2DI:
17368 case ALTIVEC_BUILTIN_VMAXUB:
17369 case ALTIVEC_BUILTIN_VMINUB:
17370 case ALTIVEC_BUILTIN_VMAXUH:
17371 case ALTIVEC_BUILTIN_VMINUH:
17372 case ALTIVEC_BUILTIN_VMAXUW:
17373 case ALTIVEC_BUILTIN_VMINUW:
17374 case P8V_BUILTIN_VMAXUD:
17375 case P8V_BUILTIN_VMINUD:
17381 /* unsigned 3 argument functions. */
17382 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17383 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17384 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17385 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17386 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17387 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17388 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17389 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17390 case VSX_BUILTIN_VPERM_16QI_UNS:
17391 case VSX_BUILTIN_VPERM_8HI_UNS:
17392 case VSX_BUILTIN_VPERM_4SI_UNS:
17393 case VSX_BUILTIN_VPERM_2DI_UNS:
17394 case VSX_BUILTIN_XXSEL_16QI_UNS:
17395 case VSX_BUILTIN_XXSEL_8HI_UNS:
17396 case VSX_BUILTIN_XXSEL_4SI_UNS:
17397 case VSX_BUILTIN_XXSEL_2DI_UNS:
17398 case CRYPTO_BUILTIN_VPERMXOR:
17399 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17400 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17401 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17402 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17403 case CRYPTO_BUILTIN_VSHASIGMAW:
17404 case CRYPTO_BUILTIN_VSHASIGMAD:
17405 case CRYPTO_BUILTIN_VSHASIGMA:
17412 /* signed permute functions with unsigned char mask. */
17413 case ALTIVEC_BUILTIN_VPERM_16QI:
17414 case ALTIVEC_BUILTIN_VPERM_8HI:
17415 case ALTIVEC_BUILTIN_VPERM_4SI:
17416 case ALTIVEC_BUILTIN_VPERM_4SF:
17417 case ALTIVEC_BUILTIN_VPERM_2DI:
17418 case ALTIVEC_BUILTIN_VPERM_2DF:
17419 case VSX_BUILTIN_VPERM_16QI:
17420 case VSX_BUILTIN_VPERM_8HI:
17421 case VSX_BUILTIN_VPERM_4SI:
17422 case VSX_BUILTIN_VPERM_4SF:
17423 case VSX_BUILTIN_VPERM_2DI:
17424 case VSX_BUILTIN_VPERM_2DF:
17428 /* unsigned args, signed return. */
17429 case VSX_BUILTIN_XVCVUXDSP:
17430 case VSX_BUILTIN_XVCVUXDDP_UNS:
17431 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17435 /* signed args, unsigned return. */
17436 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17437 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17438 case MISC_BUILTIN_UNPACK_TD:
17439 case MISC_BUILTIN_UNPACK_V1TI:
17443 /* unsigned arguments, bool return (compares). */
17444 case ALTIVEC_BUILTIN_VCMPEQUB:
17445 case ALTIVEC_BUILTIN_VCMPEQUH:
17446 case ALTIVEC_BUILTIN_VCMPEQUW:
17447 case P8V_BUILTIN_VCMPEQUD:
17448 case VSX_BUILTIN_CMPGE_U16QI:
17449 case VSX_BUILTIN_CMPGE_U8HI:
17450 case VSX_BUILTIN_CMPGE_U4SI:
17451 case VSX_BUILTIN_CMPGE_U2DI:
17452 case ALTIVEC_BUILTIN_VCMPGTUB:
17453 case ALTIVEC_BUILTIN_VCMPGTUH:
17454 case ALTIVEC_BUILTIN_VCMPGTUW:
17455 case P8V_BUILTIN_VCMPGTUD:
17460 /* unsigned arguments for 128-bit pack instructions. */
17461 case MISC_BUILTIN_PACK_TD:
17462 case MISC_BUILTIN_PACK_V1TI:
17467 /* unsigned second arguments (vector shift right). */
17468 case ALTIVEC_BUILTIN_VSRB:
17469 case ALTIVEC_BUILTIN_VSRH:
17470 case ALTIVEC_BUILTIN_VSRW:
17471 case P8V_BUILTIN_VSRD:
17479 /* Figure out how many args are present. */
17480 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17483 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17484 if (!ret_type && h.uns_p[0])
17485 ret_type = builtin_mode_to_type[h.mode[0]][0];
17488 fatal_error (input_location,
17489 "internal error: builtin function %qs had an unexpected "
17490 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17492 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17493 arg_type[i] = NULL_TREE;
17495 for (i = 0; i < num_args; i++)
17497 int m = (int) h.mode[i+1];
17498 int uns_p = h.uns_p[i+1];
17500 arg_type[i] = builtin_mode_to_type[m][uns_p];
17501 if (!arg_type[i] && uns_p)
17502 arg_type[i] = builtin_mode_to_type[m][0];
17505 fatal_error (input_location,
17506 "internal error: builtin function %qs, argument %d "
17507 "had unexpected argument type %qs", name, i,
17508 GET_MODE_NAME (m));
17511 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17512 if (*found == NULL)
17514 h2 = ggc_alloc<builtin_hash_struct> ();
17518 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17519 arg_type[2], NULL_TREE);
17522 return (*found)->type;
17526 rs6000_common_init_builtins (void)
17528 const struct builtin_description *d;
17531 tree opaque_ftype_opaque = NULL_TREE;
17532 tree opaque_ftype_opaque_opaque = NULL_TREE;
17533 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17534 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17536 /* Create Altivec and VSX builtins on machines with at least the
17537 general purpose extensions (970 and newer) to allow the use of
17538 the target attribute. */
17540 if (TARGET_EXTRA_BUILTINS)
17541 builtin_mask |= RS6000_BTM_COMMON;
17543 /* Add the ternary operators. */
17545 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17548 HOST_WIDE_INT mask = d->mask;
17550 if ((mask & builtin_mask) != mask)
17552 if (TARGET_DEBUG_BUILTIN)
17553 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17557 if (rs6000_overloaded_builtin_p (d->code))
17559 if (! (type = opaque_ftype_opaque_opaque_opaque))
17560 type = opaque_ftype_opaque_opaque_opaque
17561 = build_function_type_list (opaque_V4SI_type_node,
17562 opaque_V4SI_type_node,
17563 opaque_V4SI_type_node,
17564 opaque_V4SI_type_node,
17569 enum insn_code icode = d->icode;
17572 if (TARGET_DEBUG_BUILTIN)
17573 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17579 if (icode == CODE_FOR_nothing)
17581 if (TARGET_DEBUG_BUILTIN)
17582 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17588 type = builtin_function_type (insn_data[icode].operand[0].mode,
17589 insn_data[icode].operand[1].mode,
17590 insn_data[icode].operand[2].mode,
17591 insn_data[icode].operand[3].mode,
17595 def_builtin (d->name, type, d->code);
17598 /* Add the binary operators. */
17600 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17602 machine_mode mode0, mode1, mode2;
17604 HOST_WIDE_INT mask = d->mask;
17606 if ((mask & builtin_mask) != mask)
17608 if (TARGET_DEBUG_BUILTIN)
17609 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17613 if (rs6000_overloaded_builtin_p (d->code))
17615 if (! (type = opaque_ftype_opaque_opaque))
17616 type = opaque_ftype_opaque_opaque
17617 = build_function_type_list (opaque_V4SI_type_node,
17618 opaque_V4SI_type_node,
17619 opaque_V4SI_type_node,
17624 enum insn_code icode = d->icode;
17627 if (TARGET_DEBUG_BUILTIN)
17628 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17634 if (icode == CODE_FOR_nothing)
17636 if (TARGET_DEBUG_BUILTIN)
17637 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17643 mode0 = insn_data[icode].operand[0].mode;
17644 mode1 = insn_data[icode].operand[1].mode;
17645 mode2 = insn_data[icode].operand[2].mode;
17647 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17651 def_builtin (d->name, type, d->code);
17654 /* Add the simple unary operators. */
17656 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17658 machine_mode mode0, mode1;
17660 HOST_WIDE_INT mask = d->mask;
17662 if ((mask & builtin_mask) != mask)
17664 if (TARGET_DEBUG_BUILTIN)
17665 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17669 if (rs6000_overloaded_builtin_p (d->code))
17671 if (! (type = opaque_ftype_opaque))
17672 type = opaque_ftype_opaque
17673 = build_function_type_list (opaque_V4SI_type_node,
17674 opaque_V4SI_type_node,
17679 enum insn_code icode = d->icode;
17682 if (TARGET_DEBUG_BUILTIN)
17683 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17689 if (icode == CODE_FOR_nothing)
17691 if (TARGET_DEBUG_BUILTIN)
17692 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17698 mode0 = insn_data[icode].operand[0].mode;
17699 mode1 = insn_data[icode].operand[1].mode;
17701 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17705 def_builtin (d->name, type, d->code);
17708 /* Add the simple no-argument operators. */
17710 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17712 machine_mode mode0;
17714 HOST_WIDE_INT mask = d->mask;
17716 if ((mask & builtin_mask) != mask)
17718 if (TARGET_DEBUG_BUILTIN)
17719 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17722 if (rs6000_overloaded_builtin_p (d->code))
17724 if (!opaque_ftype_opaque)
17725 opaque_ftype_opaque
17726 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17727 type = opaque_ftype_opaque;
17731 enum insn_code icode = d->icode;
17734 if (TARGET_DEBUG_BUILTIN)
17735 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17736 (long unsigned) i);
17739 if (icode == CODE_FOR_nothing)
17741 if (TARGET_DEBUG_BUILTIN)
17743 "rs6000_builtin, skip no-argument %s (no code)\n",
17747 mode0 = insn_data[icode].operand[0].mode;
17748 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17751 def_builtin (d->name, type, d->code);
17755 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17757 init_float128_ibm (machine_mode mode)
17759 if (!TARGET_XL_COMPAT)
17761 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17762 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17763 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17764 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17766 if (!TARGET_HARD_FLOAT)
17768 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17769 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17770 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17771 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17772 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17773 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17774 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17775 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17777 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17778 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17779 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17780 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17781 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17782 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17783 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17784 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17789 set_optab_libfunc (add_optab, mode, "_xlqadd");
17790 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17791 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17792 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17795 /* Add various conversions for IFmode to use the traditional TFmode
17797 if (mode == IFmode)
17799 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17800 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17801 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17802 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17803 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17804 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17806 if (TARGET_POWERPC64)
17808 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17809 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17810 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17811 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17816 /* Create a decl for either complex long double multiply or complex long double
17817 divide when long double is IEEE 128-bit floating point. We can't use
17818 __multc3 and __divtc3 because the original long double using IBM extended
17819 double used those names. The complex multiply/divide functions are encoded
17820 as builtin functions with a complex result and 4 scalar inputs. */
17823 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17825 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17828 set_builtin_decl (fncode, fndecl, true);
17830 if (TARGET_DEBUG_BUILTIN)
17831 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17836 /* Set up IEEE 128-bit floating point routines. Use different names if the
17837 arguments can be passed in a vector register. The historical PowerPC
17838 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17839 continue to use that if we aren't using vector registers to pass IEEE
17840 128-bit floating point. */
17843 init_float128_ieee (machine_mode mode)
17845 if (FLOAT128_VECTOR_P (mode))
17847 static bool complex_muldiv_init_p = false;
17849 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
17850 we have clone or target attributes, this will be called a second
17851 time. We want to create the built-in function only once. */
17852 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
17854 complex_muldiv_init_p = true;
17855 built_in_function fncode_mul =
17856 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17857 - MIN_MODE_COMPLEX_FLOAT);
17858 built_in_function fncode_div =
17859 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17860 - MIN_MODE_COMPLEX_FLOAT);
17862 tree fntype = build_function_type_list (complex_long_double_type_node,
17863 long_double_type_node,
17864 long_double_type_node,
17865 long_double_type_node,
17866 long_double_type_node,
17869 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17870 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17873 set_optab_libfunc (add_optab, mode, "__addkf3");
17874 set_optab_libfunc (sub_optab, mode, "__subkf3");
17875 set_optab_libfunc (neg_optab, mode, "__negkf2");
17876 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17877 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17878 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17879 set_optab_libfunc (abs_optab, mode, "__abskf2");
17880 set_optab_libfunc (powi_optab, mode, "__powikf2");
17882 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17883 set_optab_libfunc (ne_optab, mode, "__nekf2");
17884 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17885 set_optab_libfunc (ge_optab, mode, "__gekf2");
17886 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17887 set_optab_libfunc (le_optab, mode, "__lekf2");
17888 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17890 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17891 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17892 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17893 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17895 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17896 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17897 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17899 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17900 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17901 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17903 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
17904 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
17905 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
17906 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
17907 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
17908 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
17910 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17911 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17912 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17913 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17915 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17916 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17917 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17918 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17920 if (TARGET_POWERPC64)
17922 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17923 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17924 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17925 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17931 set_optab_libfunc (add_optab, mode, "_q_add");
17932 set_optab_libfunc (sub_optab, mode, "_q_sub");
17933 set_optab_libfunc (neg_optab, mode, "_q_neg");
17934 set_optab_libfunc (smul_optab, mode, "_q_mul");
17935 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17936 if (TARGET_PPC_GPOPT)
17937 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17939 set_optab_libfunc (eq_optab, mode, "_q_feq");
17940 set_optab_libfunc (ne_optab, mode, "_q_fne");
17941 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17942 set_optab_libfunc (ge_optab, mode, "_q_fge");
17943 set_optab_libfunc (lt_optab, mode, "_q_flt");
17944 set_optab_libfunc (le_optab, mode, "_q_fle");
17946 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17947 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17948 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17949 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17950 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17951 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17952 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17953 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17958 rs6000_init_libfuncs (void)
17960 /* __float128 support. */
17961 if (TARGET_FLOAT128_TYPE)
17963 init_float128_ibm (IFmode);
17964 init_float128_ieee (KFmode);
17967 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17968 if (TARGET_LONG_DOUBLE_128)
17970 if (!TARGET_IEEEQUAD)
17971 init_float128_ibm (TFmode);
17973 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
17975 init_float128_ieee (TFmode);
17979 /* Emit a potentially record-form instruction, setting DST from SRC.
17980 If DOT is 0, that is all; otherwise, set CCREG to the result of the
17981 signed comparison of DST with zero. If DOT is 1, the generated RTL
17982 doesn't care about the DST result; if DOT is 2, it does. If CCREG
17983 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
17984 a separate COMPARE. */
17987 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
17991 emit_move_insn (dst, src);
17995 if (cc_reg_not_cr0_operand (ccreg, CCmode))
17997 emit_move_insn (dst, src);
17998 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18002 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18005 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18006 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18010 rtx set = gen_rtx_SET (dst, src);
18011 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18016 /* A validation routine: say whether CODE, a condition code, and MODE
18017 match. The other alternatives either don't make sense or should
18018 never be generated. */
18021 validate_condition_mode (enum rtx_code code, machine_mode mode)
18023 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18024 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18025 && GET_MODE_CLASS (mode) == MODE_CC);
18027 /* These don't make sense. */
18028 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18029 || mode != CCUNSmode);
18031 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18032 || mode == CCUNSmode);
18034 gcc_assert (mode == CCFPmode
18035 || (code != ORDERED && code != UNORDERED
18036 && code != UNEQ && code != LTGT
18037 && code != UNGT && code != UNLT
18038 && code != UNGE && code != UNLE));
18040 /* These should never be generated except for
18041 flag_finite_math_only. */
18042 gcc_assert (mode != CCFPmode
18043 || flag_finite_math_only
18044 || (code != LE && code != GE
18045 && code != UNEQ && code != LTGT
18046 && code != UNGT && code != UNLT));
18048 /* These are invalid; the information is not there. */
18049 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18053 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18054 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18055 not zero, store there the bit offset (counted from the right) where
18056 the single stretch of 1 bits begins; and similarly for B, the bit
18057 offset where it ends. */
18060 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18062 unsigned HOST_WIDE_INT val = INTVAL (mask);
18063 unsigned HOST_WIDE_INT bit;
18065 int n = GET_MODE_PRECISION (mode);
18067 if (mode != DImode && mode != SImode)
18070 if (INTVAL (mask) >= 0)
18073 ne = exact_log2 (bit);
18074 nb = exact_log2 (val + bit);
18076 else if (val + 1 == 0)
18085 nb = exact_log2 (bit);
18086 ne = exact_log2 (val + bit);
18091 ne = exact_log2 (bit);
18092 if (val + bit == 0)
18100 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18111 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18112 or rldicr instruction, to implement an AND with it in mode MODE. */
18115 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18119 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18122 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18124 if (mode == DImode)
18125 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18127 /* For SImode, rlwinm can do everything. */
18128 if (mode == SImode)
18129 return (nb < 32 && ne < 32);
18134 /* Return the instruction template for an AND with mask in mode MODE, with
18135 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18138 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18142 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18143 gcc_unreachable ();
18145 if (mode == DImode && ne == 0)
18147 operands[3] = GEN_INT (63 - nb);
18149 return "rldicl. %0,%1,0,%3";
18150 return "rldicl %0,%1,0,%3";
18153 if (mode == DImode && nb == 63)
18155 operands[3] = GEN_INT (63 - ne);
18157 return "rldicr. %0,%1,0,%3";
18158 return "rldicr %0,%1,0,%3";
18161 if (nb < 32 && ne < 32)
18163 operands[3] = GEN_INT (31 - nb);
18164 operands[4] = GEN_INT (31 - ne);
18166 return "rlwinm. %0,%1,0,%3,%4";
18167 return "rlwinm %0,%1,0,%3,%4";
18170 gcc_unreachable ();
18173 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18174 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18175 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18178 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18182 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18185 int n = GET_MODE_PRECISION (mode);
18188 if (CONST_INT_P (XEXP (shift, 1)))
18190 sh = INTVAL (XEXP (shift, 1));
18191 if (sh < 0 || sh >= n)
18195 rtx_code code = GET_CODE (shift);
18197 /* Convert any shift by 0 to a rotate, to simplify below code. */
18201 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18202 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18204 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18210 /* DImode rotates need rld*. */
18211 if (mode == DImode && code == ROTATE)
18212 return (nb == 63 || ne == 0 || ne == sh);
18214 /* SImode rotates need rlw*. */
18215 if (mode == SImode && code == ROTATE)
18216 return (nb < 32 && ne < 32 && sh < 32);
18218 /* Wrap-around masks are only okay for rotates. */
18222 /* Variable shifts are only okay for rotates. */
18226 /* Don't allow ASHIFT if the mask is wrong for that. */
18227 if (code == ASHIFT && ne < sh)
18230 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18231 if the mask is wrong for that. */
18232 if (nb < 32 && ne < 32 && sh < 32
18233 && !(code == LSHIFTRT && nb >= 32 - sh))
18236 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18237 if the mask is wrong for that. */
18238 if (code == LSHIFTRT)
18240 if (nb == 63 || ne == 0 || ne == sh)
18241 return !(code == LSHIFTRT && nb >= sh);
18246 /* Return the instruction template for a shift with mask in mode MODE, with
18247 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18250 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18254 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18255 gcc_unreachable ();
18257 if (mode == DImode && ne == 0)
18259 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18260 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18261 operands[3] = GEN_INT (63 - nb);
18263 return "rld%I2cl. %0,%1,%2,%3";
18264 return "rld%I2cl %0,%1,%2,%3";
18267 if (mode == DImode && nb == 63)
18269 operands[3] = GEN_INT (63 - ne);
18271 return "rld%I2cr. %0,%1,%2,%3";
18272 return "rld%I2cr %0,%1,%2,%3";
18276 && GET_CODE (operands[4]) != LSHIFTRT
18277 && CONST_INT_P (operands[2])
18278 && ne == INTVAL (operands[2]))
18280 operands[3] = GEN_INT (63 - nb);
18282 return "rld%I2c. %0,%1,%2,%3";
18283 return "rld%I2c %0,%1,%2,%3";
18286 if (nb < 32 && ne < 32)
18288 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18289 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18290 operands[3] = GEN_INT (31 - nb);
18291 operands[4] = GEN_INT (31 - ne);
18292 /* This insn can also be a 64-bit rotate with mask that really makes
18293 it just a shift right (with mask); the %h below are to adjust for
18294 that situation (shift count is >= 32 in that case). */
18296 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18297 return "rlw%I2nm %0,%1,%h2,%3,%4";
18300 gcc_unreachable ();
18303 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18304 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18305 ASHIFT, or LSHIFTRT) in mode MODE. */
18308 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18312 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18315 int n = GET_MODE_PRECISION (mode);
18317 int sh = INTVAL (XEXP (shift, 1));
18318 if (sh < 0 || sh >= n)
18321 rtx_code code = GET_CODE (shift);
18323 /* Convert any shift by 0 to a rotate, to simplify below code. */
18327 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18328 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18330 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18336 /* DImode rotates need rldimi. */
18337 if (mode == DImode && code == ROTATE)
18340 /* SImode rotates need rlwimi. */
18341 if (mode == SImode && code == ROTATE)
18342 return (nb < 32 && ne < 32 && sh < 32);
18344 /* Wrap-around masks are only okay for rotates. */
18348 /* Don't allow ASHIFT if the mask is wrong for that. */
18349 if (code == ASHIFT && ne < sh)
18352 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18353 if the mask is wrong for that. */
18354 if (nb < 32 && ne < 32 && sh < 32
18355 && !(code == LSHIFTRT && nb >= 32 - sh))
18358 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18359 if the mask is wrong for that. */
18360 if (code == LSHIFTRT)
18363 return !(code == LSHIFTRT && nb >= sh);
18368 /* Return the instruction template for an insert with mask in mode MODE, with
18369 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18372 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18376 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18377 gcc_unreachable ();
18379 /* Prefer rldimi because rlwimi is cracked. */
18380 if (TARGET_POWERPC64
18381 && (!dot || mode == DImode)
18382 && GET_CODE (operands[4]) != LSHIFTRT
18383 && ne == INTVAL (operands[2]))
18385 operands[3] = GEN_INT (63 - nb);
18387 return "rldimi. %0,%1,%2,%3";
18388 return "rldimi %0,%1,%2,%3";
18391 if (nb < 32 && ne < 32)
18393 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18394 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18395 operands[3] = GEN_INT (31 - nb);
18396 operands[4] = GEN_INT (31 - ne);
18398 return "rlwimi. %0,%1,%2,%3,%4";
18399 return "rlwimi %0,%1,%2,%3,%4";
18402 gcc_unreachable ();
18405 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18406 using two machine instructions. */
18409 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18411 /* There are two kinds of AND we can handle with two insns:
18412 1) those we can do with two rl* insn;
18415 We do not handle that last case yet. */
18417 /* If there is just one stretch of ones, we can do it. */
18418 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18421 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18422 one insn, we can do the whole thing with two. */
18423 unsigned HOST_WIDE_INT val = INTVAL (c);
18424 unsigned HOST_WIDE_INT bit1 = val & -val;
18425 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18426 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18427 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18428 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18431 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18432 If EXPAND is true, split rotate-and-mask instructions we generate to
18433 their constituent parts as well (this is used during expand); if DOT
18434 is 1, make the last insn a record-form instruction clobbering the
18435 destination GPR and setting the CC reg (from operands[3]); if 2, set
18436 that GPR as well as the CC reg. */
18439 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18441 gcc_assert (!(expand && dot));
18443 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18445 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18446 shift right. This generates better code than doing the masks without
18447 shifts, or shifting first right and then left. */
18449 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18451 gcc_assert (mode == DImode);
18453 int shift = 63 - nb;
18456 rtx tmp1 = gen_reg_rtx (DImode);
18457 rtx tmp2 = gen_reg_rtx (DImode);
18458 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18459 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18460 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18464 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18465 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18466 emit_move_insn (operands[0], tmp);
18467 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18468 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18473 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18474 that does the rest. */
18475 unsigned HOST_WIDE_INT bit1 = val & -val;
18476 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18477 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18478 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18480 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18481 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18483 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18485 /* Two "no-rotate"-and-mask instructions, for SImode. */
18486 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18488 gcc_assert (mode == SImode);
18490 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18491 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18492 emit_move_insn (reg, tmp);
18493 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18494 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18498 gcc_assert (mode == DImode);
18500 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18501 insns; we have to do the first in SImode, because it wraps. */
18502 if (mask2 <= 0xffffffff
18503 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18505 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18506 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18508 rtx reg_low = gen_lowpart (SImode, reg);
18509 emit_move_insn (reg_low, tmp);
18510 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18511 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18515 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18516 at the top end), rotate back and clear the other hole. */
18517 int right = exact_log2 (bit3);
18518 int left = 64 - right;
18520 /* Rotate the mask too. */
18521 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18525 rtx tmp1 = gen_reg_rtx (DImode);
18526 rtx tmp2 = gen_reg_rtx (DImode);
18527 rtx tmp3 = gen_reg_rtx (DImode);
18528 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18529 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18530 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18531 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18535 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18536 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18537 emit_move_insn (operands[0], tmp);
18538 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18539 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18540 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18544 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18545 for lfq and stfq insns iff the registers are hard registers. */
18548 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18550 /* We might have been passed a SUBREG. */
18551 if (!REG_P (reg1) || !REG_P (reg2))
18554 /* We might have been passed non floating point registers. */
18555 if (!FP_REGNO_P (REGNO (reg1))
18556 || !FP_REGNO_P (REGNO (reg2)))
18559 return (REGNO (reg1) == REGNO (reg2) - 1);
18562 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18563 addr1 and addr2 must be in consecutive memory locations
18564 (addr2 == addr1 + 8). */
18567 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18570 unsigned int reg1, reg2;
18571 int offset1, offset2;
18573 /* The mems cannot be volatile. */
18574 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18577 addr1 = XEXP (mem1, 0);
18578 addr2 = XEXP (mem2, 0);
18580 /* Extract an offset (if used) from the first addr. */
18581 if (GET_CODE (addr1) == PLUS)
18583 /* If not a REG, return zero. */
18584 if (!REG_P (XEXP (addr1, 0)))
18588 reg1 = REGNO (XEXP (addr1, 0));
18589 /* The offset must be constant! */
18590 if (!CONST_INT_P (XEXP (addr1, 1)))
18592 offset1 = INTVAL (XEXP (addr1, 1));
18595 else if (!REG_P (addr1))
18599 reg1 = REGNO (addr1);
18600 /* This was a simple (mem (reg)) expression. Offset is 0. */
18604 /* And now for the second addr. */
18605 if (GET_CODE (addr2) == PLUS)
18607 /* If not a REG, return zero. */
18608 if (!REG_P (XEXP (addr2, 0)))
18612 reg2 = REGNO (XEXP (addr2, 0));
18613 /* The offset must be constant. */
18614 if (!CONST_INT_P (XEXP (addr2, 1)))
18616 offset2 = INTVAL (XEXP (addr2, 1));
18619 else if (!REG_P (addr2))
18623 reg2 = REGNO (addr2);
18624 /* This was a simple (mem (reg)) expression. Offset is 0. */
18628 /* Both of these must have the same base register. */
18632 /* The offset for the second addr must be 8 more than the first addr. */
18633 if (offset2 != offset1 + 8)
18636 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18641 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18642 need to use DDmode, in all other cases we can use the same mode. */
18643 static machine_mode
18644 rs6000_secondary_memory_needed_mode (machine_mode mode)
18646 if (lra_in_progress && mode == SDmode)
18651 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18652 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18653 only work on the traditional altivec registers, note if an altivec register
18656 static enum rs6000_reg_type
18657 register_to_reg_type (rtx reg, bool *is_altivec)
18659 HOST_WIDE_INT regno;
18660 enum reg_class rclass;
18662 if (SUBREG_P (reg))
18663 reg = SUBREG_REG (reg);
18666 return NO_REG_TYPE;
18668 regno = REGNO (reg);
18669 if (!HARD_REGISTER_NUM_P (regno))
18671 if (!lra_in_progress && !reload_completed)
18672 return PSEUDO_REG_TYPE;
18674 regno = true_regnum (reg);
18675 if (regno < 0 || !HARD_REGISTER_NUM_P (regno))
18676 return PSEUDO_REG_TYPE;
18679 gcc_assert (regno >= 0);
18681 if (is_altivec && ALTIVEC_REGNO_P (regno))
18682 *is_altivec = true;
18684 rclass = rs6000_regno_regclass[regno];
18685 return reg_class_to_reg_type[(int)rclass];
18688 /* Helper function to return the cost of adding a TOC entry address. */
18691 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18695 if (TARGET_CMODEL != CMODEL_SMALL)
18696 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18699 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18704 /* Helper function for rs6000_secondary_reload to determine whether the memory
18705 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18706 needs reloading. Return negative if the memory is not handled by the memory
18707 helper functions and to try a different reload method, 0 if no additional
18708 instructions are need, and positive to give the extra cost for the
18712 rs6000_secondary_reload_memory (rtx addr,
18713 enum reg_class rclass,
18716 int extra_cost = 0;
18717 rtx reg, and_arg, plus_arg0, plus_arg1;
18718 addr_mask_type addr_mask;
18719 const char *type = NULL;
18720 const char *fail_msg = NULL;
18722 if (GPR_REG_CLASS_P (rclass))
18723 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18725 else if (rclass == FLOAT_REGS)
18726 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18728 else if (rclass == ALTIVEC_REGS)
18729 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18731 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18732 else if (rclass == VSX_REGS)
18733 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18734 & ~RELOAD_REG_AND_M16);
18736 /* If the register allocator hasn't made up its mind yet on the register
18737 class to use, settle on defaults to use. */
18738 else if (rclass == NO_REGS)
18740 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18741 & ~RELOAD_REG_AND_M16);
18743 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18744 addr_mask &= ~(RELOAD_REG_INDEXED
18745 | RELOAD_REG_PRE_INCDEC
18746 | RELOAD_REG_PRE_MODIFY);
18752 /* If the register isn't valid in this register class, just return now. */
18753 if ((addr_mask & RELOAD_REG_VALID) == 0)
18755 if (TARGET_DEBUG_ADDR)
18758 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18759 "not valid in class\n",
18760 GET_MODE_NAME (mode), reg_class_names[rclass]);
18767 switch (GET_CODE (addr))
18769 /* Does the register class supports auto update forms for this mode? We
18770 don't need a scratch register, since the powerpc only supports
18771 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18774 reg = XEXP (addr, 0);
18775 if (!base_reg_operand (addr, GET_MODE (reg)))
18777 fail_msg = "no base register #1";
18781 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18789 reg = XEXP (addr, 0);
18790 plus_arg1 = XEXP (addr, 1);
18791 if (!base_reg_operand (reg, GET_MODE (reg))
18792 || GET_CODE (plus_arg1) != PLUS
18793 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18795 fail_msg = "bad PRE_MODIFY";
18799 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18806 /* Do we need to simulate AND -16 to clear the bottom address bits used
18807 in VMX load/stores? Only allow the AND for vector sizes. */
18809 and_arg = XEXP (addr, 0);
18810 if (GET_MODE_SIZE (mode) != 16
18811 || !CONST_INT_P (XEXP (addr, 1))
18812 || INTVAL (XEXP (addr, 1)) != -16)
18814 fail_msg = "bad Altivec AND #1";
18818 if (rclass != ALTIVEC_REGS)
18820 if (legitimate_indirect_address_p (and_arg, false))
18823 else if (legitimate_indexed_address_p (and_arg, false))
18828 fail_msg = "bad Altivec AND #2";
18836 /* If this is an indirect address, make sure it is a base register. */
18839 if (!legitimate_indirect_address_p (addr, false))
18846 /* If this is an indexed address, make sure the register class can handle
18847 indexed addresses for this mode. */
18849 plus_arg0 = XEXP (addr, 0);
18850 plus_arg1 = XEXP (addr, 1);
18852 /* (plus (plus (reg) (constant)) (constant)) is generated during
18853 push_reload processing, so handle it now. */
18854 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18856 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18863 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18864 push_reload processing, so handle it now. */
18865 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18867 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18870 type = "indexed #2";
18874 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18876 fail_msg = "no base register #2";
18880 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18882 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18883 || !legitimate_indexed_address_p (addr, false))
18890 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18891 && CONST_INT_P (plus_arg1))
18893 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18896 type = "vector d-form offset";
18900 /* Make sure the register class can handle offset addresses. */
18901 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18903 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18906 type = "offset #2";
18912 fail_msg = "bad PLUS";
18919 /* Quad offsets are restricted and can't handle normal addresses. */
18920 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18923 type = "vector d-form lo_sum";
18926 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18928 fail_msg = "bad LO_SUM";
18932 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18939 /* Static addresses need to create a TOC entry. */
18943 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18946 type = "vector d-form lo_sum #2";
18952 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18956 /* TOC references look like offsetable memory. */
18958 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18960 fail_msg = "bad UNSPEC";
18964 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18967 type = "vector d-form lo_sum #3";
18970 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18973 type = "toc reference";
18979 fail_msg = "bad address";
18984 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
18986 if (extra_cost < 0)
18988 "rs6000_secondary_reload_memory error: mode = %s, "
18989 "class = %s, addr_mask = '%s', %s\n",
18990 GET_MODE_NAME (mode),
18991 reg_class_names[rclass],
18992 rs6000_debug_addr_mask (addr_mask, false),
18993 (fail_msg != NULL) ? fail_msg : "<bad address>");
18997 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18998 "addr_mask = '%s', extra cost = %d, %s\n",
18999 GET_MODE_NAME (mode),
19000 reg_class_names[rclass],
19001 rs6000_debug_addr_mask (addr_mask, false),
19003 (type) ? type : "<none>");
19011 /* Helper function for rs6000_secondary_reload to return true if a move to a
19012 different register classe is really a simple move. */
19015 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19016 enum rs6000_reg_type from_type,
19019 int size = GET_MODE_SIZE (mode);
19021 /* Add support for various direct moves available. In this function, we only
19022 look at cases where we don't need any extra registers, and one or more
19023 simple move insns are issued. Originally small integers are not allowed
19024 in FPR/VSX registers. Single precision binary floating is not a simple
19025 move because we need to convert to the single precision memory layout.
19026 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19027 need special direct move handling, which we do not support yet. */
19028 if (TARGET_DIRECT_MOVE
19029 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19030 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19032 if (TARGET_POWERPC64)
19034 /* ISA 2.07: MTVSRD or MVFVSRD. */
19038 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19039 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19043 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19044 if (TARGET_P8_VECTOR)
19046 if (mode == SImode)
19049 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19053 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19054 if (mode == SDmode)
19058 /* Move to/from SPR. */
19059 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19060 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19061 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19067 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19068 special direct moves that involve allocating an extra register, return the
19069 insn code of the helper function if there is such a function or
19070 CODE_FOR_nothing if not. */
19073 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19074 enum rs6000_reg_type from_type,
19076 secondary_reload_info *sri,
19080 enum insn_code icode = CODE_FOR_nothing;
19082 int size = GET_MODE_SIZE (mode);
19084 if (TARGET_POWERPC64 && size == 16)
19086 /* Handle moving 128-bit values from GPRs to VSX point registers on
19087 ISA 2.07 (power8, power9) when running in 64-bit mode using
19088 XXPERMDI to glue the two 64-bit values back together. */
19089 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19091 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19092 icode = reg_addr[mode].reload_vsx_gpr;
19095 /* Handle moving 128-bit values from VSX point registers to GPRs on
19096 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19097 bottom 64-bit value. */
19098 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19100 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19101 icode = reg_addr[mode].reload_gpr_vsx;
19105 else if (TARGET_POWERPC64 && mode == SFmode)
19107 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19109 cost = 3; /* xscvdpspn, mfvsrd, and. */
19110 icode = reg_addr[mode].reload_gpr_vsx;
19113 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19115 cost = 2; /* mtvsrz, xscvspdpn. */
19116 icode = reg_addr[mode].reload_vsx_gpr;
19120 else if (!TARGET_POWERPC64 && size == 8)
19122 /* Handle moving 64-bit values from GPRs to floating point registers on
19123 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19124 32-bit values back together. Altivec register classes must be handled
19125 specially since a different instruction is used, and the secondary
19126 reload support requires a single instruction class in the scratch
19127 register constraint. However, right now TFmode is not allowed in
19128 Altivec registers, so the pattern will never match. */
19129 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19131 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19132 icode = reg_addr[mode].reload_fpr_gpr;
19136 if (icode != CODE_FOR_nothing)
19141 sri->icode = icode;
19142 sri->extra_cost = cost;
19149 /* Return whether a move between two register classes can be done either
19150 directly (simple move) or via a pattern that uses a single extra temporary
19151 (using ISA 2.07's direct move in this case. */
19154 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19155 enum rs6000_reg_type from_type,
19157 secondary_reload_info *sri,
19160 /* Fall back to load/store reloads if either type is not a register. */
19161 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19164 /* If we haven't allocated registers yet, assume the move can be done for the
19165 standard register types. */
19166 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19167 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19168 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19171 /* Moves to the same set of registers is a simple move for non-specialized
19173 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19176 /* Check whether a simple move can be done directly. */
19177 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19181 sri->icode = CODE_FOR_nothing;
19182 sri->extra_cost = 0;
19187 /* Now check if we can do it in a few steps. */
19188 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19192 /* Inform reload about cases where moving X with a mode MODE to a register in
19193 RCLASS requires an extra scratch or immediate register. Return the class
19194 needed for the immediate register.
19196 For VSX and Altivec, we may need a register to convert sp+offset into
19199 For misaligned 64-bit gpr loads and stores we need a register to
19200 convert an offset address to indirect. */
19203 rs6000_secondary_reload (bool in_p,
19205 reg_class_t rclass_i,
19207 secondary_reload_info *sri)
19209 enum reg_class rclass = (enum reg_class) rclass_i;
19210 reg_class_t ret = ALL_REGS;
19211 enum insn_code icode;
19212 bool default_p = false;
19213 bool done_p = false;
19215 /* Allow subreg of memory before/during reload. */
19216 bool memory_p = (MEM_P (x)
19217 || (!reload_completed && SUBREG_P (x)
19218 && MEM_P (SUBREG_REG (x))));
19220 sri->icode = CODE_FOR_nothing;
19221 sri->t_icode = CODE_FOR_nothing;
19222 sri->extra_cost = 0;
19224 ? reg_addr[mode].reload_load
19225 : reg_addr[mode].reload_store);
19227 if (REG_P (x) || register_operand (x, mode))
19229 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19230 bool altivec_p = (rclass == ALTIVEC_REGS);
19231 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19234 std::swap (to_type, from_type);
19236 /* Can we do a direct move of some sort? */
19237 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19240 icode = (enum insn_code)sri->icode;
19247 /* Make sure 0.0 is not reloaded or forced into memory. */
19248 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19255 /* If this is a scalar floating point value and we want to load it into the
19256 traditional Altivec registers, do it via a move via a traditional floating
19257 point register, unless we have D-form addressing. Also make sure that
19258 non-zero constants use a FPR. */
19259 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19260 && !mode_supports_vmx_dform (mode)
19261 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19262 && (memory_p || CONST_DOUBLE_P (x)))
19269 /* Handle reload of load/stores if we have reload helper functions. */
19270 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19272 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19275 if (extra_cost >= 0)
19279 if (extra_cost > 0)
19281 sri->extra_cost = extra_cost;
19282 sri->icode = icode;
19287 /* Handle unaligned loads and stores of integer registers. */
19288 if (!done_p && TARGET_POWERPC64
19289 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19291 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19293 rtx addr = XEXP (x, 0);
19294 rtx off = address_offset (addr);
19296 if (off != NULL_RTX)
19298 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19299 unsigned HOST_WIDE_INT offset = INTVAL (off);
19301 /* We need a secondary reload when our legitimate_address_p
19302 says the address is good (as otherwise the entire address
19303 will be reloaded), and the offset is not a multiple of
19304 four or we have an address wrap. Address wrap will only
19305 occur for LO_SUMs since legitimate_offset_address_p
19306 rejects addresses for 16-byte mems that will wrap. */
19307 if (GET_CODE (addr) == LO_SUM
19308 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19309 && ((offset & 3) != 0
19310 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19311 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19312 && (offset & 3) != 0))
19314 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19316 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19317 : CODE_FOR_reload_di_load);
19319 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19320 : CODE_FOR_reload_di_store);
19321 sri->extra_cost = 2;
19332 if (!done_p && !TARGET_POWERPC64
19333 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19335 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19337 rtx addr = XEXP (x, 0);
19338 rtx off = address_offset (addr);
19340 if (off != NULL_RTX)
19342 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19343 unsigned HOST_WIDE_INT offset = INTVAL (off);
19345 /* We need a secondary reload when our legitimate_address_p
19346 says the address is good (as otherwise the entire address
19347 will be reloaded), and we have a wrap.
19349 legitimate_lo_sum_address_p allows LO_SUM addresses to
19350 have any offset so test for wrap in the low 16 bits.
19352 legitimate_offset_address_p checks for the range
19353 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19354 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19355 [0x7ff4,0x7fff] respectively, so test for the
19356 intersection of these ranges, [0x7ffc,0x7fff] and
19357 [0x7ff4,0x7ff7] respectively.
19359 Note that the address we see here may have been
19360 manipulated by legitimize_reload_address. */
19361 if (GET_CODE (addr) == LO_SUM
19362 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19363 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19366 sri->icode = CODE_FOR_reload_si_load;
19368 sri->icode = CODE_FOR_reload_si_store;
19369 sri->extra_cost = 2;
19384 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19386 gcc_assert (ret != ALL_REGS);
19388 if (TARGET_DEBUG_ADDR)
19391 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19393 reg_class_names[ret],
19394 in_p ? "true" : "false",
19395 reg_class_names[rclass],
19396 GET_MODE_NAME (mode));
19398 if (reload_completed)
19399 fputs (", after reload", stderr);
19402 fputs (", done_p not set", stderr);
19405 fputs (", default secondary reload", stderr);
19407 if (sri->icode != CODE_FOR_nothing)
19408 fprintf (stderr, ", reload func = %s, extra cost = %d",
19409 insn_data[sri->icode].name, sri->extra_cost);
19411 else if (sri->extra_cost > 0)
19412 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19414 fputs ("\n", stderr);
19421 /* Better tracing for rs6000_secondary_reload_inner. */
19424 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19429 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19431 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19432 store_p ? "store" : "load");
19435 set = gen_rtx_SET (mem, reg);
19437 set = gen_rtx_SET (reg, mem);
19439 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19440 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19443 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19444 ATTRIBUTE_NORETURN;
19447 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19450 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19451 gcc_unreachable ();
19454 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19455 reload helper functions. These were identified in
19456 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19457 reload, it calls the insns:
19458 reload_<RELOAD:mode>_<P:mptrsize>_store
19459 reload_<RELOAD:mode>_<P:mptrsize>_load
19461 which in turn calls this function, to do whatever is necessary to create
19462 valid addresses. */
19465 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19467 int regno = true_regnum (reg);
19468 machine_mode mode = GET_MODE (reg);
19469 addr_mask_type addr_mask;
19472 rtx op_reg, op0, op1;
19477 if (regno < 0 || !HARD_REGISTER_NUM_P (regno) || !MEM_P (mem)
19478 || !base_reg_operand (scratch, GET_MODE (scratch)))
19479 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19481 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19482 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19484 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19485 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19487 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19488 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19491 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19493 /* Make sure the mode is valid in this register class. */
19494 if ((addr_mask & RELOAD_REG_VALID) == 0)
19495 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19497 if (TARGET_DEBUG_ADDR)
19498 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19500 new_addr = addr = XEXP (mem, 0);
19501 switch (GET_CODE (addr))
19503 /* Does the register class support auto update forms for this mode? If
19504 not, do the update now. We don't need a scratch register, since the
19505 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19508 op_reg = XEXP (addr, 0);
19509 if (!base_reg_operand (op_reg, Pmode))
19510 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19512 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19514 int delta = GET_MODE_SIZE (mode);
19515 if (GET_CODE (addr) == PRE_DEC)
19517 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19523 op0 = XEXP (addr, 0);
19524 op1 = XEXP (addr, 1);
19525 if (!base_reg_operand (op0, Pmode)
19526 || GET_CODE (op1) != PLUS
19527 || !rtx_equal_p (op0, XEXP (op1, 0)))
19528 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19530 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19532 emit_insn (gen_rtx_SET (op0, op1));
19537 /* Do we need to simulate AND -16 to clear the bottom address bits used
19538 in VMX load/stores? */
19540 op0 = XEXP (addr, 0);
19541 op1 = XEXP (addr, 1);
19542 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19544 if (REG_P (op0) || SUBREG_P (op0))
19547 else if (GET_CODE (op1) == PLUS)
19549 emit_insn (gen_rtx_SET (scratch, op1));
19554 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19556 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19557 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19558 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19559 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19560 new_addr = scratch;
19564 /* If this is an indirect address, make sure it is a base register. */
19567 if (!base_reg_operand (addr, GET_MODE (addr)))
19569 emit_insn (gen_rtx_SET (scratch, addr));
19570 new_addr = scratch;
19574 /* If this is an indexed address, make sure the register class can handle
19575 indexed addresses for this mode. */
19577 op0 = XEXP (addr, 0);
19578 op1 = XEXP (addr, 1);
19579 if (!base_reg_operand (op0, Pmode))
19580 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19582 else if (int_reg_operand (op1, Pmode))
19584 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19586 emit_insn (gen_rtx_SET (scratch, addr));
19587 new_addr = scratch;
19591 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19593 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19594 || !quad_address_p (addr, mode, false))
19596 emit_insn (gen_rtx_SET (scratch, addr));
19597 new_addr = scratch;
19601 /* Make sure the register class can handle offset addresses. */
19602 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19604 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19606 emit_insn (gen_rtx_SET (scratch, addr));
19607 new_addr = scratch;
19612 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19617 op0 = XEXP (addr, 0);
19618 op1 = XEXP (addr, 1);
19619 if (!base_reg_operand (op0, Pmode))
19620 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19622 else if (int_reg_operand (op1, Pmode))
19624 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19626 emit_insn (gen_rtx_SET (scratch, addr));
19627 new_addr = scratch;
19631 /* Quad offsets are restricted and can't handle normal addresses. */
19632 else if (mode_supports_dq_form (mode))
19634 emit_insn (gen_rtx_SET (scratch, addr));
19635 new_addr = scratch;
19638 /* Make sure the register class can handle offset addresses. */
19639 else if (legitimate_lo_sum_address_p (mode, addr, false))
19641 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19643 emit_insn (gen_rtx_SET (scratch, addr));
19644 new_addr = scratch;
19649 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19656 rs6000_emit_move (scratch, addr, Pmode);
19657 new_addr = scratch;
19661 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19664 /* Adjust the address if it changed. */
19665 if (addr != new_addr)
19667 mem = replace_equiv_address_nv (mem, new_addr);
19668 if (TARGET_DEBUG_ADDR)
19669 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19672 /* Now create the move. */
19674 emit_insn (gen_rtx_SET (mem, reg));
19676 emit_insn (gen_rtx_SET (reg, mem));
19681 /* Convert reloads involving 64-bit gprs and misaligned offset
19682 addressing, or multiple 32-bit gprs and offsets that are too large,
19683 to use indirect addressing. */
19686 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19688 int regno = true_regnum (reg);
19689 enum reg_class rclass;
19691 rtx scratch_or_premodify = scratch;
19693 if (TARGET_DEBUG_ADDR)
19695 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19696 store_p ? "store" : "load");
19697 fprintf (stderr, "reg:\n");
19699 fprintf (stderr, "mem:\n");
19701 fprintf (stderr, "scratch:\n");
19702 debug_rtx (scratch);
19705 gcc_assert (regno >= 0 && HARD_REGISTER_NUM_P (regno));
19706 gcc_assert (MEM_P (mem));
19707 rclass = REGNO_REG_CLASS (regno);
19708 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19709 addr = XEXP (mem, 0);
19711 if (GET_CODE (addr) == PRE_MODIFY)
19713 gcc_assert (REG_P (XEXP (addr, 0))
19714 && GET_CODE (XEXP (addr, 1)) == PLUS
19715 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19716 scratch_or_premodify = XEXP (addr, 0);
19717 addr = XEXP (addr, 1);
19719 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19721 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19723 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19725 /* Now create the move. */
19727 emit_insn (gen_rtx_SET (mem, reg));
19729 emit_insn (gen_rtx_SET (reg, mem));
19734 /* Given an rtx X being reloaded into a reg required to be
19735 in class CLASS, return the class of reg to actually use.
19736 In general this is just CLASS; but on some machines
19737 in some cases it is preferable to use a more restrictive class.
19739 On the RS/6000, we have to return NO_REGS when we want to reload a
19740 floating-point CONST_DOUBLE to force it to be copied to memory.
19742 We also don't want to reload integer values into floating-point
19743 registers if we can at all help it. In fact, this can
19744 cause reload to die, if it tries to generate a reload of CTR
19745 into a FP register and discovers it doesn't have the memory location
19748 ??? Would it be a good idea to have reload do the converse, that is
19749 try to reload floating modes into FP registers if possible?
19752 static enum reg_class
19753 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19755 machine_mode mode = GET_MODE (x);
19756 bool is_constant = CONSTANT_P (x);
19758 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19759 reload class for it. */
19760 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19761 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19764 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19765 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19768 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19769 the reloading of address expressions using PLUS into floating point
19771 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19775 /* Zero is always allowed in all VSX registers. */
19776 if (x == CONST0_RTX (mode))
19779 /* If this is a vector constant that can be formed with a few Altivec
19780 instructions, we want altivec registers. */
19781 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19782 return ALTIVEC_REGS;
19784 /* If this is an integer constant that can easily be loaded into
19785 vector registers, allow it. */
19786 if (CONST_INT_P (x))
19788 HOST_WIDE_INT value = INTVAL (x);
19790 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19791 2.06 can generate it in the Altivec registers with
19795 if (TARGET_P8_VECTOR)
19797 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19798 return ALTIVEC_REGS;
19803 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19804 a sign extend in the Altivec registers. */
19805 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19806 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19807 return ALTIVEC_REGS;
19810 /* Force constant to memory. */
19814 /* D-form addressing can easily reload the value. */
19815 if (mode_supports_vmx_dform (mode)
19816 || mode_supports_dq_form (mode))
19819 /* If this is a scalar floating point value and we don't have D-form
19820 addressing, prefer the traditional floating point registers so that we
19821 can use D-form (register+offset) addressing. */
19822 if (rclass == VSX_REGS
19823 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19826 /* Prefer the Altivec registers if Altivec is handling the vector
19827 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19829 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19830 || mode == V1TImode)
19831 return ALTIVEC_REGS;
19836 if (is_constant || GET_CODE (x) == PLUS)
19838 if (reg_class_subset_p (GENERAL_REGS, rclass))
19839 return GENERAL_REGS;
19840 if (reg_class_subset_p (BASE_REGS, rclass))
19845 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
19846 return GENERAL_REGS;
19851 /* Debug version of rs6000_preferred_reload_class. */
19852 static enum reg_class
19853 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19855 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19858 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19860 reg_class_names[ret], reg_class_names[rclass],
19861 GET_MODE_NAME (GET_MODE (x)));
19867 /* If we are copying between FP or AltiVec registers and anything else, we need
19868 a memory location. The exception is when we are targeting ppc64 and the
19869 move to/from fpr to gpr instructions are available. Also, under VSX, you
19870 can copy vector registers from the FP register set to the Altivec register
19871 set and vice versa. */
19874 rs6000_secondary_memory_needed (machine_mode mode,
19875 reg_class_t from_class,
19876 reg_class_t to_class)
19878 enum rs6000_reg_type from_type, to_type;
19879 bool altivec_p = ((from_class == ALTIVEC_REGS)
19880 || (to_class == ALTIVEC_REGS));
19882 /* If a simple/direct move is available, we don't need secondary memory */
19883 from_type = reg_class_to_reg_type[(int)from_class];
19884 to_type = reg_class_to_reg_type[(int)to_class];
19886 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19887 (secondary_reload_info *)0, altivec_p))
19890 /* If we have a floating point or vector register class, we need to use
19891 memory to transfer the data. */
19892 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19898 /* Debug version of rs6000_secondary_memory_needed. */
19900 rs6000_debug_secondary_memory_needed (machine_mode mode,
19901 reg_class_t from_class,
19902 reg_class_t to_class)
19904 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19907 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19908 "to_class = %s, mode = %s\n",
19909 ret ? "true" : "false",
19910 reg_class_names[from_class],
19911 reg_class_names[to_class],
19912 GET_MODE_NAME (mode));
19917 /* Return the register class of a scratch register needed to copy IN into
19918 or out of a register in RCLASS in MODE. If it can be done directly,
19919 NO_REGS is returned. */
19921 static enum reg_class
19922 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19927 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19929 && MACHOPIC_INDIRECT
19933 /* We cannot copy a symbolic operand directly into anything
19934 other than BASE_REGS for TARGET_ELF. So indicate that a
19935 register from BASE_REGS is needed as an intermediate
19938 On Darwin, pic addresses require a load from memory, which
19939 needs a base register. */
19940 if (rclass != BASE_REGS
19941 && (SYMBOL_REF_P (in)
19942 || GET_CODE (in) == HIGH
19943 || GET_CODE (in) == LABEL_REF
19944 || GET_CODE (in) == CONST))
19950 regno = REGNO (in);
19951 if (!HARD_REGISTER_NUM_P (regno))
19953 regno = true_regnum (in);
19954 if (!HARD_REGISTER_NUM_P (regno))
19958 else if (SUBREG_P (in))
19960 regno = true_regnum (in);
19961 if (!HARD_REGISTER_NUM_P (regno))
19967 /* If we have VSX register moves, prefer moving scalar values between
19968 Altivec registers and GPR by going via an FPR (and then via memory)
19969 instead of reloading the secondary memory address for Altivec moves. */
19971 && GET_MODE_SIZE (mode) < 16
19972 && !mode_supports_vmx_dform (mode)
19973 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
19974 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
19975 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19976 && (regno >= 0 && INT_REGNO_P (regno)))))
19979 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
19981 if (rclass == GENERAL_REGS || rclass == BASE_REGS
19982 || (regno >= 0 && INT_REGNO_P (regno)))
19985 /* Constants, memory, and VSX registers can go into VSX registers (both the
19986 traditional floating point and the altivec registers). */
19987 if (rclass == VSX_REGS
19988 && (regno == -1 || VSX_REGNO_P (regno)))
19991 /* Constants, memory, and FP registers can go into FP registers. */
19992 if ((regno == -1 || FP_REGNO_P (regno))
19993 && (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
19994 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
19996 /* Memory, and AltiVec registers can go into AltiVec registers. */
19997 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
19998 && rclass == ALTIVEC_REGS)
20001 /* We can copy among the CR registers. */
20002 if ((rclass == CR_REGS || rclass == CR0_REGS)
20003 && regno >= 0 && CR_REGNO_P (regno))
20006 /* Otherwise, we need GENERAL_REGS. */
20007 return GENERAL_REGS;
20010 /* Debug version of rs6000_secondary_reload_class. */
20011 static enum reg_class
20012 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20013 machine_mode mode, rtx in)
20015 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20017 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20018 "mode = %s, input rtx:\n",
20019 reg_class_names[ret], reg_class_names[rclass],
20020 GET_MODE_NAME (mode));
20026 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20029 rs6000_can_change_mode_class (machine_mode from,
20031 reg_class_t rclass)
20033 unsigned from_size = GET_MODE_SIZE (from);
20034 unsigned to_size = GET_MODE_SIZE (to);
20036 if (from_size != to_size)
20038 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20040 if (reg_classes_intersect_p (xclass, rclass))
20042 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20043 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20044 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20045 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20047 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20048 single register under VSX because the scalar part of the register
20049 is in the upper 64-bits, and not the lower 64-bits. Types like
20050 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20051 IEEE floating point can't overlap, and neither can small
20054 if (to_float128_vector_p && from_float128_vector_p)
20057 else if (to_float128_vector_p || from_float128_vector_p)
20060 /* TDmode in floating-mode registers must always go into a register
20061 pair with the most significant word in the even-numbered register
20062 to match ISA requirements. In little-endian mode, this does not
20063 match subreg numbering, so we cannot allow subregs. */
20064 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20067 if (from_size < 8 || to_size < 8)
20070 if (from_size == 8 && (8 * to_nregs) != to_size)
20073 if (to_size == 8 && (8 * from_nregs) != from_size)
20082 /* Since the VSX register set includes traditional floating point registers
20083 and altivec registers, just check for the size being different instead of
20084 trying to check whether the modes are vector modes. Otherwise it won't
20085 allow say DF and DI to change classes. For types like TFmode and TDmode
20086 that take 2 64-bit registers, rather than a single 128-bit register, don't
20087 allow subregs of those types to other 128 bit types. */
20088 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20090 unsigned num_regs = (from_size + 15) / 16;
20091 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20092 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20095 return (from_size == 8 || from_size == 16);
20098 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20099 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20105 /* Debug version of rs6000_can_change_mode_class. */
20107 rs6000_debug_can_change_mode_class (machine_mode from,
20109 reg_class_t rclass)
20111 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20114 "rs6000_can_change_mode_class, return %s, from = %s, "
20115 "to = %s, rclass = %s\n",
20116 ret ? "true" : "false",
20117 GET_MODE_NAME (from), GET_MODE_NAME (to),
20118 reg_class_names[rclass]);
20123 /* Return a string to do a move operation of 128 bits of data. */
20126 rs6000_output_move_128bit (rtx operands[])
20128 rtx dest = operands[0];
20129 rtx src = operands[1];
20130 machine_mode mode = GET_MODE (dest);
20133 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20134 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20138 dest_regno = REGNO (dest);
20139 dest_gpr_p = INT_REGNO_P (dest_regno);
20140 dest_fp_p = FP_REGNO_P (dest_regno);
20141 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20142 dest_vsx_p = dest_fp_p | dest_vmx_p;
20147 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20152 src_regno = REGNO (src);
20153 src_gpr_p = INT_REGNO_P (src_regno);
20154 src_fp_p = FP_REGNO_P (src_regno);
20155 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20156 src_vsx_p = src_fp_p | src_vmx_p;
20161 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20164 /* Register moves. */
20165 if (dest_regno >= 0 && src_regno >= 0)
20172 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20173 return (WORDS_BIG_ENDIAN
20174 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20175 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20177 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20181 else if (TARGET_VSX && dest_vsx_p)
20184 return "xxlor %x0,%x1,%x1";
20186 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20187 return (WORDS_BIG_ENDIAN
20188 ? "mtvsrdd %x0,%1,%L1"
20189 : "mtvsrdd %x0,%L1,%1");
20191 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20195 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20196 return "vor %0,%1,%1";
20198 else if (dest_fp_p && src_fp_p)
20203 else if (dest_regno >= 0 && MEM_P (src))
20207 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20213 else if (TARGET_ALTIVEC && dest_vmx_p
20214 && altivec_indexed_or_indirect_operand (src, mode))
20215 return "lvx %0,%y1";
20217 else if (TARGET_VSX && dest_vsx_p)
20219 if (mode_supports_dq_form (mode)
20220 && quad_address_p (XEXP (src, 0), mode, true))
20221 return "lxv %x0,%1";
20223 else if (TARGET_P9_VECTOR)
20224 return "lxvx %x0,%y1";
20226 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20227 return "lxvw4x %x0,%y1";
20230 return "lxvd2x %x0,%y1";
20233 else if (TARGET_ALTIVEC && dest_vmx_p)
20234 return "lvx %0,%y1";
20236 else if (dest_fp_p)
20241 else if (src_regno >= 0 && MEM_P (dest))
20245 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20246 return "stq %1,%0";
20251 else if (TARGET_ALTIVEC && src_vmx_p
20252 && altivec_indexed_or_indirect_operand (dest, mode))
20253 return "stvx %1,%y0";
20255 else if (TARGET_VSX && src_vsx_p)
20257 if (mode_supports_dq_form (mode)
20258 && quad_address_p (XEXP (dest, 0), mode, true))
20259 return "stxv %x1,%0";
20261 else if (TARGET_P9_VECTOR)
20262 return "stxvx %x1,%y0";
20264 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20265 return "stxvw4x %x1,%y0";
20268 return "stxvd2x %x1,%y0";
20271 else if (TARGET_ALTIVEC && src_vmx_p)
20272 return "stvx %1,%y0";
20279 else if (dest_regno >= 0
20280 && (CONST_INT_P (src)
20281 || CONST_WIDE_INT_P (src)
20282 || CONST_DOUBLE_P (src)
20283 || GET_CODE (src) == CONST_VECTOR))
20288 else if ((dest_vmx_p && TARGET_ALTIVEC)
20289 || (dest_vsx_p && TARGET_VSX))
20290 return output_vec_const_move (operands);
20293 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20296 /* Validate a 128-bit move. */
20298 rs6000_move_128bit_ok_p (rtx operands[])
20300 machine_mode mode = GET_MODE (operands[0]);
20301 return (gpc_reg_operand (operands[0], mode)
20302 || gpc_reg_operand (operands[1], mode));
20305 /* Return true if a 128-bit move needs to be split. */
20307 rs6000_split_128bit_ok_p (rtx operands[])
20309 if (!reload_completed)
20312 if (!gpr_or_gpr_p (operands[0], operands[1]))
20315 if (quad_load_store_p (operands[0], operands[1]))
20322 /* Given a comparison operation, return the bit number in CCR to test. We
20323 know this is a valid comparison.
20325 SCC_P is 1 if this is for an scc. That means that %D will have been
20326 used instead of %C, so the bits will be in different places.
20328 Return -1 if OP isn't a valid comparison for some reason. */
20331 ccr_bit (rtx op, int scc_p)
20333 enum rtx_code code = GET_CODE (op);
20334 machine_mode cc_mode;
20339 if (!COMPARISON_P (op))
20342 reg = XEXP (op, 0);
20344 if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg)))
20347 cc_mode = GET_MODE (reg);
20348 cc_regnum = REGNO (reg);
20349 base_bit = 4 * (cc_regnum - CR0_REGNO);
20351 validate_condition_mode (code, cc_mode);
20353 /* When generating a sCOND operation, only positive conditions are
20372 return scc_p ? base_bit + 3 : base_bit + 2;
20374 return base_bit + 2;
20375 case GT: case GTU: case UNLE:
20376 return base_bit + 1;
20377 case LT: case LTU: case UNGE:
20379 case ORDERED: case UNORDERED:
20380 return base_bit + 3;
20383 /* If scc, we will have done a cror to put the bit in the
20384 unordered position. So test that bit. For integer, this is ! LT
20385 unless this is an scc insn. */
20386 return scc_p ? base_bit + 3 : base_bit;
20389 return scc_p ? base_bit + 3 : base_bit + 1;
20396 /* Return the GOT register. */
20399 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20401 /* The second flow pass currently (June 1999) can't update
20402 regs_ever_live without disturbing other parts of the compiler, so
20403 update it here to make the prolog/epilogue code happy. */
20404 if (!can_create_pseudo_p ()
20405 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20406 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20408 crtl->uses_pic_offset_table = 1;
20410 return pic_offset_table_rtx;
20413 static rs6000_stack_t stack_info;
20415 /* Function to init struct machine_function.
20416 This will be called, via a pointer variable,
20417 from push_function_context. */
20419 static struct machine_function *
20420 rs6000_init_machine_status (void)
20422 stack_info.reload_completed = 0;
20423 return ggc_cleared_alloc<machine_function> ();
20426 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20428 /* Write out a function code label. */
20431 rs6000_output_function_entry (FILE *file, const char *fname)
20433 if (fname[0] != '.')
20435 switch (DEFAULT_ABI)
20438 gcc_unreachable ();
20444 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20454 RS6000_OUTPUT_BASENAME (file, fname);
20457 /* Print an operand. Recognize special options, documented below. */
20460 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20461 only introduced by the linker, when applying the sda21
20463 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20464 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20466 #define SMALL_DATA_RELOC "sda21"
20467 #define SMALL_DATA_REG 0
20471 print_operand (FILE *file, rtx x, int code)
20474 unsigned HOST_WIDE_INT uval;
20478 /* %a is output_address. */
20480 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20484 /* Like 'J' but get to the GT bit only. */
20485 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20487 output_operand_lossage ("invalid %%D value");
20491 /* Bit 1 is GT bit. */
20492 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20494 /* Add one for shift count in rlinm for scc. */
20495 fprintf (file, "%d", i + 1);
20499 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20502 output_operand_lossage ("invalid %%e value");
20507 if ((uval & 0xffff) == 0 && uval != 0)
20512 /* X is a CR register. Print the number of the EQ bit of the CR */
20513 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20514 output_operand_lossage ("invalid %%E value");
20516 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20520 /* X is a CR register. Print the shift count needed to move it
20521 to the high-order four bits. */
20522 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20523 output_operand_lossage ("invalid %%f value");
20525 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20529 /* Similar, but print the count for the rotate in the opposite
20531 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20532 output_operand_lossage ("invalid %%F value");
20534 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20538 /* X is a constant integer. If it is negative, print "m",
20539 otherwise print "z". This is to make an aze or ame insn. */
20540 if (!CONST_INT_P (x))
20541 output_operand_lossage ("invalid %%G value");
20542 else if (INTVAL (x) >= 0)
20549 /* If constant, output low-order five bits. Otherwise, write
20552 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20554 print_operand (file, x, 0);
20558 /* If constant, output low-order six bits. Otherwise, write
20561 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20563 print_operand (file, x, 0);
20567 /* Print `i' if this is a constant, else nothing. */
20573 /* Write the bit number in CCR for jump. */
20574 i = ccr_bit (x, 0);
20576 output_operand_lossage ("invalid %%j code");
20578 fprintf (file, "%d", i);
20582 /* Similar, but add one for shift count in rlinm for scc and pass
20583 scc flag to `ccr_bit'. */
20584 i = ccr_bit (x, 1);
20586 output_operand_lossage ("invalid %%J code");
20588 /* If we want bit 31, write a shift count of zero, not 32. */
20589 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20593 /* X must be a constant. Write the 1's complement of the
20596 output_operand_lossage ("invalid %%k value");
20598 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20602 /* X must be a symbolic constant on ELF. Write an
20603 expression suitable for an 'addi' that adds in the low 16
20604 bits of the MEM. */
20605 if (GET_CODE (x) == CONST)
20607 if (GET_CODE (XEXP (x, 0)) != PLUS
20608 || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
20609 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20610 || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20611 output_operand_lossage ("invalid %%K value");
20613 print_operand_address (file, x);
20614 fputs ("@l", file);
20617 /* %l is output_asm_label. */
20620 /* Write second word of DImode or DFmode reference. Works on register
20621 or non-indexed memory only. */
20623 fputs (reg_names[REGNO (x) + 1], file);
20624 else if (MEM_P (x))
20626 machine_mode mode = GET_MODE (x);
20627 /* Handle possible auto-increment. Since it is pre-increment and
20628 we have already done it, we can just use an offset of word. */
20629 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20630 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20631 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20633 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20634 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20637 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20641 if (small_data_operand (x, GET_MODE (x)))
20642 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20643 reg_names[SMALL_DATA_REG]);
20647 case 'N': /* Unused */
20648 /* Write the number of elements in the vector times 4. */
20649 if (GET_CODE (x) != PARALLEL)
20650 output_operand_lossage ("invalid %%N value");
20652 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20655 case 'O': /* Unused */
20656 /* Similar, but subtract 1 first. */
20657 if (GET_CODE (x) != PARALLEL)
20658 output_operand_lossage ("invalid %%O value");
20660 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20664 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20667 || (i = exact_log2 (INTVAL (x))) < 0)
20668 output_operand_lossage ("invalid %%p value");
20670 fprintf (file, "%d", i);
20674 /* The operand must be an indirect memory reference. The result
20675 is the register name. */
20676 if (!MEM_P (x) || !REG_P (XEXP (x, 0))
20677 || REGNO (XEXP (x, 0)) >= 32)
20678 output_operand_lossage ("invalid %%P value");
20680 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20684 /* This outputs the logical code corresponding to a boolean
20685 expression. The expression may have one or both operands
20686 negated (if one, only the first one). For condition register
20687 logical operations, it will also treat the negated
20688 CR codes as NOTs, but not handle NOTs of them. */
20690 const char *const *t = 0;
20692 enum rtx_code code = GET_CODE (x);
20693 static const char * const tbl[3][3] = {
20694 { "and", "andc", "nor" },
20695 { "or", "orc", "nand" },
20696 { "xor", "eqv", "xor" } };
20700 else if (code == IOR)
20702 else if (code == XOR)
20705 output_operand_lossage ("invalid %%q value");
20707 if (GET_CODE (XEXP (x, 0)) != NOT)
20711 if (GET_CODE (XEXP (x, 1)) == NOT)
20722 if (! TARGET_MFCRF)
20728 /* X is a CR register. Print the mask for `mtcrf'. */
20729 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20730 output_operand_lossage ("invalid %%R value");
20732 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20736 /* Low 5 bits of 32 - value */
20738 output_operand_lossage ("invalid %%s value");
20740 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20744 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20745 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20747 output_operand_lossage ("invalid %%t value");
20751 /* Bit 3 is OV bit. */
20752 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20754 /* If we want bit 31, write a shift count of zero, not 32. */
20755 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20759 /* Print the symbolic name of a branch target register. */
20760 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20761 x = XVECEXP (x, 0, 0);
20762 if (!REG_P (x) || (REGNO (x) != LR_REGNO
20763 && REGNO (x) != CTR_REGNO))
20764 output_operand_lossage ("invalid %%T value");
20765 else if (REGNO (x) == LR_REGNO)
20766 fputs ("lr", file);
20768 fputs ("ctr", file);
20772 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20773 for use in unsigned operand. */
20776 output_operand_lossage ("invalid %%u value");
20781 if ((uval & 0xffff) == 0)
20784 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20788 /* High-order 16 bits of constant for use in signed operand. */
20790 output_operand_lossage ("invalid %%v value");
20792 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20793 (INTVAL (x) >> 16) & 0xffff);
20797 /* Print `u' if this has an auto-increment or auto-decrement. */
20799 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20800 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20801 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20806 /* Print the trap code for this operand. */
20807 switch (GET_CODE (x))
20810 fputs ("eq", file); /* 4 */
20813 fputs ("ne", file); /* 24 */
20816 fputs ("lt", file); /* 16 */
20819 fputs ("le", file); /* 20 */
20822 fputs ("gt", file); /* 8 */
20825 fputs ("ge", file); /* 12 */
20828 fputs ("llt", file); /* 2 */
20831 fputs ("lle", file); /* 6 */
20834 fputs ("lgt", file); /* 1 */
20837 fputs ("lge", file); /* 5 */
20840 output_operand_lossage ("invalid %%V value");
20845 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20848 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20849 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20851 print_operand (file, x, 0);
20855 /* X is a FPR or Altivec register used in a VSX context. */
20856 if (!REG_P (x) || !VSX_REGNO_P (REGNO (x)))
20857 output_operand_lossage ("invalid %%x value");
20860 int reg = REGNO (x);
20861 int vsx_reg = (FP_REGNO_P (reg)
20863 : reg - FIRST_ALTIVEC_REGNO + 32);
20865 #ifdef TARGET_REGNAMES
20866 if (TARGET_REGNAMES)
20867 fprintf (file, "%%vs%d", vsx_reg);
20870 fprintf (file, "%d", vsx_reg);
20876 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20877 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20878 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20883 /* Like 'L', for third word of TImode/PTImode */
20885 fputs (reg_names[REGNO (x) + 2], file);
20886 else if (MEM_P (x))
20888 machine_mode mode = GET_MODE (x);
20889 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20890 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20891 output_address (mode, plus_constant (Pmode,
20892 XEXP (XEXP (x, 0), 0), 8));
20893 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20894 output_address (mode, plus_constant (Pmode,
20895 XEXP (XEXP (x, 0), 0), 8));
20897 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20898 if (small_data_operand (x, GET_MODE (x)))
20899 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20900 reg_names[SMALL_DATA_REG]);
20905 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20906 x = XVECEXP (x, 0, 1);
20907 /* X is a SYMBOL_REF. Write out the name preceded by a
20908 period and without any trailing data in brackets. Used for function
20909 names. If we are configured for System V (or the embedded ABI) on
20910 the PowerPC, do not emit the period, since those systems do not use
20911 TOCs and the like. */
20912 if (!SYMBOL_REF_P (x))
20914 output_operand_lossage ("invalid %%z value");
20918 /* For macho, check to see if we need a stub. */
20921 const char *name = XSTR (x, 0);
20923 if (darwin_emit_branch_islands
20924 && MACHOPIC_INDIRECT
20925 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20926 name = machopic_indirection_name (x, /*stub_p=*/true);
20928 assemble_name (file, name);
20930 else if (!DOT_SYMBOLS)
20931 assemble_name (file, XSTR (x, 0));
20933 rs6000_output_function_entry (file, XSTR (x, 0));
20937 /* Like 'L', for last word of TImode/PTImode. */
20939 fputs (reg_names[REGNO (x) + 3], file);
20940 else if (MEM_P (x))
20942 machine_mode mode = GET_MODE (x);
20943 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20944 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20945 output_address (mode, plus_constant (Pmode,
20946 XEXP (XEXP (x, 0), 0), 12));
20947 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20948 output_address (mode, plus_constant (Pmode,
20949 XEXP (XEXP (x, 0), 0), 12));
20951 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20952 if (small_data_operand (x, GET_MODE (x)))
20953 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20954 reg_names[SMALL_DATA_REG]);
20958 /* Print AltiVec memory operand. */
20963 gcc_assert (MEM_P (x));
20967 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20968 && GET_CODE (tmp) == AND
20969 && CONST_INT_P (XEXP (tmp, 1))
20970 && INTVAL (XEXP (tmp, 1)) == -16)
20971 tmp = XEXP (tmp, 0);
20972 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20973 && GET_CODE (tmp) == PRE_MODIFY)
20974 tmp = XEXP (tmp, 1);
20976 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
20979 if (GET_CODE (tmp) != PLUS
20980 || !REG_P (XEXP (tmp, 0))
20981 || !REG_P (XEXP (tmp, 1)))
20983 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20987 if (REGNO (XEXP (tmp, 0)) == 0)
20988 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
20989 reg_names[ REGNO (XEXP (tmp, 0)) ]);
20991 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
20992 reg_names[ REGNO (XEXP (tmp, 1)) ]);
20999 fprintf (file, "%s", reg_names[REGNO (x)]);
21000 else if (MEM_P (x))
21002 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21003 know the width from the mode. */
21004 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21005 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21006 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21007 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21008 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21009 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21010 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21011 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21013 output_address (GET_MODE (x), XEXP (x, 0));
21015 else if (toc_relative_expr_p (x, false,
21016 &tocrel_base_oac, &tocrel_offset_oac))
21017 /* This hack along with a corresponding hack in
21018 rs6000_output_addr_const_extra arranges to output addends
21019 where the assembler expects to find them. eg.
21020 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21021 without this hack would be output as "x@toc+4". We
21023 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21024 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
21025 output_addr_const (file, XVECEXP (x, 0, 0));
21026 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
21027 output_addr_const (file, XVECEXP (x, 0, 1));
21029 output_addr_const (file, x);
21033 if (const char *name = get_some_local_dynamic_name ())
21034 assemble_name (file, name);
21036 output_operand_lossage ("'%%&' used without any "
21037 "local dynamic TLS references");
21041 output_operand_lossage ("invalid %%xn code");
21045 /* Print the address of an operand. */
21048 print_operand_address (FILE *file, rtx x)
21051 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21053 /* Is it a pc-relative address? */
21054 else if (pcrel_address (x, Pmode))
21056 HOST_WIDE_INT offset;
21058 if (GET_CODE (x) == CONST)
21061 if (GET_CODE (x) == PLUS)
21063 offset = INTVAL (XEXP (x, 1));
21069 output_addr_const (file, x);
21072 fprintf (file, "%+" PRId64, offset);
21074 fputs ("@pcrel", file);
21076 else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
21077 || GET_CODE (x) == LABEL_REF)
21079 output_addr_const (file, x);
21080 if (small_data_operand (x, GET_MODE (x)))
21081 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21082 reg_names[SMALL_DATA_REG]);
21084 gcc_assert (!TARGET_TOC);
21086 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21087 && REG_P (XEXP (x, 1)))
21089 if (REGNO (XEXP (x, 0)) == 0)
21090 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21091 reg_names[ REGNO (XEXP (x, 0)) ]);
21093 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21094 reg_names[ REGNO (XEXP (x, 1)) ]);
21096 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21097 && CONST_INT_P (XEXP (x, 1)))
21098 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21099 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21101 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21102 && CONSTANT_P (XEXP (x, 1)))
21104 fprintf (file, "lo16(");
21105 output_addr_const (file, XEXP (x, 1));
21106 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21110 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21111 && CONSTANT_P (XEXP (x, 1)))
21113 output_addr_const (file, XEXP (x, 1));
21114 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21117 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21119 /* This hack along with a corresponding hack in
21120 rs6000_output_addr_const_extra arranges to output addends
21121 where the assembler expects to find them. eg.
21123 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21124 without this hack would be output as "x@toc+8@l(9)". We
21125 want "x+8@toc@l(9)". */
21126 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21127 if (GET_CODE (x) == LO_SUM)
21128 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21130 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21133 output_addr_const (file, x);
21136 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21139 rs6000_output_addr_const_extra (FILE *file, rtx x)
21141 if (GET_CODE (x) == UNSPEC)
21142 switch (XINT (x, 1))
21144 case UNSPEC_TOCREL:
21145 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x, 0, 0))
21146 && REG_P (XVECEXP (x, 0, 1))
21147 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21148 output_addr_const (file, XVECEXP (x, 0, 0));
21149 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21151 if (INTVAL (tocrel_offset_oac) >= 0)
21152 fprintf (file, "+");
21153 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21155 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21158 assemble_name (file, toc_label_name);
21161 else if (TARGET_ELF)
21162 fputs ("@toc", file);
21166 case UNSPEC_MACHOPIC_OFFSET:
21167 output_addr_const (file, XVECEXP (x, 0, 0));
21169 machopic_output_function_base_name (file);
21176 /* Target hook for assembling integer objects. The PowerPC version has
21177 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21178 is defined. It also needs to handle DI-mode objects on 64-bit
21182 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21184 #ifdef RELOCATABLE_NEEDS_FIXUP
21185 /* Special handling for SI values. */
21186 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21188 static int recurse = 0;
21190 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21191 the .fixup section. Since the TOC section is already relocated, we
21192 don't need to mark it here. We used to skip the text section, but it
21193 should never be valid for relocated addresses to be placed in the text
21195 if (DEFAULT_ABI == ABI_V4
21196 && (TARGET_RELOCATABLE || flag_pic > 1)
21197 && in_section != toc_section
21199 && !CONST_SCALAR_INT_P (x)
21205 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21207 ASM_OUTPUT_LABEL (asm_out_file, buf);
21208 fprintf (asm_out_file, "\t.long\t(");
21209 output_addr_const (asm_out_file, x);
21210 fprintf (asm_out_file, ")@fixup\n");
21211 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21212 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21213 fprintf (asm_out_file, "\t.long\t");
21214 assemble_name (asm_out_file, buf);
21215 fprintf (asm_out_file, "\n\t.previous\n");
21219 /* Remove initial .'s to turn a -mcall-aixdesc function
21220 address into the address of the descriptor, not the function
21222 else if (SYMBOL_REF_P (x)
21223 && XSTR (x, 0)[0] == '.'
21224 && DEFAULT_ABI == ABI_AIX)
21226 const char *name = XSTR (x, 0);
21227 while (*name == '.')
21230 fprintf (asm_out_file, "\t.long\t%s\n", name);
21234 #endif /* RELOCATABLE_NEEDS_FIXUP */
21235 return default_assemble_integer (x, size, aligned_p);
21238 /* Return a template string for assembly to emit when making an
21239 external call. FUNOP is the call mem argument operand number. */
21241 static const char *
21242 rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
21244 /* -Wformat-overflow workaround, without which gcc thinks that %u
21245 might produce 10 digits. */
21246 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21250 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21252 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21253 sprintf (arg, "(%%%u@tlsgd)", funop + 1);
21254 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21255 sprintf (arg, "(%%&@tlsld)");
21257 gcc_unreachable ();
21260 /* The magic 32768 offset here corresponds to the offset of
21261 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21263 sprintf (z, "%%z%u%s", funop,
21264 (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == 2
21267 static char str[32]; /* 1 spare */
21268 if (rs6000_pcrel_p (cfun))
21269 sprintf (str, "b%s %s@notoc%s", sibcall ? "" : "l", z, arg);
21270 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21271 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21272 sibcall ? "" : "\n\tnop");
21273 else if (DEFAULT_ABI == ABI_V4)
21274 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21275 flag_pic ? "@plt" : "");
21277 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21278 else if (DEFAULT_ABI == ABI_DARWIN)
21280 /* The cookie is in operand func+2. */
21281 gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
21282 int cookie = INTVAL (operands[funop + 2]);
21283 if (cookie & CALL_LONG)
21285 tree funname = get_identifier (XSTR (operands[funop], 0));
21286 tree labelname = get_prev_label (funname);
21287 gcc_checking_assert (labelname && !sibcall);
21289 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21290 instruction will reach 'foo', otherwise link as 'bl L42'".
21291 "L42" should be a 'branch island', that will do a far jump to
21292 'foo'. Branch islands are generated in
21293 macho_branch_islands(). */
21294 sprintf (str, "jbsr %%z%u,%.10s", funop,
21295 IDENTIFIER_POINTER (labelname));
21298 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21300 sprintf (str, "b%s %s%s", sibcall ? "" : "l", z, arg);
21304 gcc_unreachable ();
21309 rs6000_call_template (rtx *operands, unsigned int funop)
21311 return rs6000_call_template_1 (operands, funop, false);
21315 rs6000_sibcall_template (rtx *operands, unsigned int funop)
21317 return rs6000_call_template_1 (operands, funop, true);
21320 /* As above, for indirect calls. */
21322 static const char *
21323 rs6000_indirect_call_template_1 (rtx *operands, unsigned int funop,
21326 /* -Wformat-overflow workaround, without which gcc thinks that %u
21327 might produce 10 digits. Note that -Wformat-overflow will not
21328 currently warn here for str[], so do not rely on a warning to
21329 ensure str[] is correctly sized. */
21330 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21332 /* Currently, funop is either 0 or 1. The maximum string is always
21333 a !speculate 64-bit __tls_get_addr call.
21336 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21337 . 35 .reloc .,R_PPC64_PLTSEQ_NOTOC,%z1\n\t
21339 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21340 . 36 .reloc .,R_PPC64_PLTCALL_NOTOC,%z1\n\t
21347 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21348 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21350 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21351 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21358 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21359 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21361 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21362 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21369 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21370 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21372 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21373 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21377 static char str[160]; /* 8 spare */
21379 const char *ptrload = TARGET_64BIT ? "d" : "wz";
21381 if (DEFAULT_ABI == ABI_AIX)
21384 ptrload, funop + 2);
21386 /* We don't need the extra code to stop indirect call speculation if
21388 bool speculate = (TARGET_MACHO
21389 || rs6000_speculate_indirect_jumps
21390 || (REG_P (operands[funop])
21391 && REGNO (operands[funop]) == LR_REGNO));
21393 if (TARGET_PLTSEQ && GET_CODE (operands[funop]) == UNSPEC)
21395 const char *rel64 = TARGET_64BIT ? "64" : "";
21398 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21400 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21401 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21403 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21404 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21407 gcc_unreachable ();
21410 const char *notoc = rs6000_pcrel_p (cfun) ? "_NOTOC" : "";
21411 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21412 && flag_pic == 2 ? "+32768" : "");
21416 "%s.reloc .,R_PPC%s_PLTSEQ%s,%%z%u%s\n\t",
21417 tls, rel64, notoc, funop, addend);
21418 s += sprintf (s, "crset 2\n\t");
21421 "%s.reloc .,R_PPC%s_PLTCALL%s,%%z%u%s\n\t",
21422 tls, rel64, notoc, funop, addend);
21424 else if (!speculate)
21425 s += sprintf (s, "crset 2\n\t");
21427 if (rs6000_pcrel_p (cfun))
21430 sprintf (s, "b%%T%ul", funop);
21432 sprintf (s, "beq%%T%ul-", funop);
21434 else if (DEFAULT_ABI == ABI_AIX)
21440 funop, ptrload, funop + 3);
21445 funop, ptrload, funop + 3);
21447 else if (DEFAULT_ABI == ABI_ELFv2)
21453 funop, ptrload, funop + 2);
21458 funop, ptrload, funop + 2);
21465 funop, sibcall ? "" : "l");
21469 funop, sibcall ? "" : "l", sibcall ? "\n\tb $" : "");
21475 rs6000_indirect_call_template (rtx *operands, unsigned int funop)
21477 return rs6000_indirect_call_template_1 (operands, funop, false);
21481 rs6000_indirect_sibcall_template (rtx *operands, unsigned int funop)
21483 return rs6000_indirect_call_template_1 (operands, funop, true);
21487 /* Output indirect call insns. WHICH identifies the type of sequence. */
21489 rs6000_pltseq_template (rtx *operands, int which)
21491 const char *rel64 = TARGET_64BIT ? "64" : "";
21494 if (TARGET_TLS_MARKERS && GET_CODE (operands[3]) == UNSPEC)
21496 char off = which == RS6000_PLTSEQ_PLT_PCREL34 ? '8' : '4';
21497 if (XINT (operands[3], 1) == UNSPEC_TLSGD)
21498 sprintf (tls, ".reloc .-%c,R_PPC%s_TLSGD,%%3\n\t",
21500 else if (XINT (operands[3], 1) == UNSPEC_TLSLD)
21501 sprintf (tls, ".reloc .-%c,R_PPC%s_TLSLD,%%&\n\t",
21504 gcc_unreachable ();
21507 gcc_assert (DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4);
21508 static char str[96]; /* 10 spare */
21509 char off = WORDS_BIG_ENDIAN ? '2' : '4';
21510 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21511 && flag_pic == 2 ? "+32768" : "");
21514 case RS6000_PLTSEQ_TOCSAVE:
21517 "%s.reloc .-4,R_PPC%s_PLTSEQ,%%z2",
21518 TARGET_64BIT ? "d 2,24(1)" : "w 2,12(1)",
21521 case RS6000_PLTSEQ_PLT16_HA:
21522 if (DEFAULT_ABI == ABI_V4 && !flag_pic)
21525 "%s.reloc .-%c,R_PPC%s_PLT16_HA,%%z2",
21529 "addis %%0,%%1,0\n\t"
21530 "%s.reloc .-%c,R_PPC%s_PLT16_HA,%%z2%s",
21531 tls, off, rel64, addend);
21533 case RS6000_PLTSEQ_PLT16_LO:
21535 "l%s %%0,0(%%1)\n\t"
21536 "%s.reloc .-%c,R_PPC%s_PLT16_LO%s,%%z2%s",
21537 TARGET_64BIT ? "d" : "wz",
21538 tls, off, rel64, TARGET_64BIT ? "_DS" : "", addend);
21540 case RS6000_PLTSEQ_MTCTR:
21543 "%s.reloc .-4,R_PPC%s_PLTSEQ,%%z2%s",
21544 tls, rel64, addend);
21546 case RS6000_PLTSEQ_PLT_PCREL34:
21548 "pl%s %%0,0(0),1\n\t"
21549 "%s.reloc .-8,R_PPC%s_PLT_PCREL34_NOTOC,%%z2",
21550 TARGET_64BIT ? "d" : "wz",
21554 gcc_unreachable ();
21560 /* Helper function to return whether a MODE can do prefixed loads/stores.
21561 VOIDmode is used when we are loading the pc-relative address into a base
21562 register, but we are not using it as part of a memory operation. As modes
21563 add support for prefixed memory, they will be added here. */
21566 mode_supports_prefixed_address_p (machine_mode mode)
21568 return mode == VOIDmode;
21571 /* Function to return true if ADDR is a valid prefixed memory address that uses
21575 rs6000_prefixed_address (rtx addr, machine_mode mode)
21577 if (!TARGET_PREFIXED_ADDR || !mode_supports_prefixed_address_p (mode))
21580 /* Check for PC-relative addresses. */
21581 if (pcrel_address (addr, Pmode))
21584 /* Check for prefixed memory addresses that have a large numeric offset,
21585 or an offset that can't be used for a DS/DQ-form memory operation. */
21586 if (GET_CODE (addr) == PLUS)
21588 rtx op0 = XEXP (addr, 0);
21589 rtx op1 = XEXP (addr, 1);
21591 if (!base_reg_operand (op0, Pmode) || !CONST_INT_P (op1))
21594 HOST_WIDE_INT value = INTVAL (op1);
21595 if (!SIGNED_34BIT_OFFSET_P (value, 0))
21598 /* Offset larger than 16-bits? */
21599 if (!SIGNED_16BIT_OFFSET_P (value, 0))
21602 /* DQ instruction (bottom 4 bits must be 0) for vectors. */
21603 HOST_WIDE_INT mask;
21604 if (GET_MODE_SIZE (mode) >= 16)
21607 /* DS instruction (bottom 2 bits must be 0). For 32-bit integers, we
21608 need to use DS instructions if we are sign-extending the value with
21609 LWA. For 32-bit floating point, we need DS instructions to load and
21610 store values to the traditional Altivec registers. */
21611 else if (GET_MODE_SIZE (mode) >= 4)
21614 /* QImode/HImode has no restrictions. */
21618 /* Return true if we must use a prefixed instruction. */
21619 return (value & mask) != 0;
21625 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21626 /* Emit an assembler directive to set symbol visibility for DECL to
21627 VISIBILITY_TYPE. */
21630 rs6000_assemble_visibility (tree decl, int vis)
21635 /* Functions need to have their entry point symbol visibility set as
21636 well as their descriptor symbol visibility. */
21637 if (DEFAULT_ABI == ABI_AIX
21639 && TREE_CODE (decl) == FUNCTION_DECL)
21641 static const char * const visibility_types[] = {
21642 NULL, "protected", "hidden", "internal"
21645 const char *name, *type;
21647 name = ((* targetm.strip_name_encoding)
21648 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21649 type = visibility_types[vis];
21651 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21652 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21655 default_assemble_visibility (decl, vis);
21660 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21662 /* Reversal of FP compares takes care -- an ordered compare
21663 becomes an unordered compare and vice versa. */
21664 if (mode == CCFPmode
21665 && (!flag_finite_math_only
21666 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21667 || code == UNEQ || code == LTGT))
21668 return reverse_condition_maybe_unordered (code);
21670 return reverse_condition (code);
21673 /* Generate a compare for CODE. Return a brand-new rtx that
21674 represents the result of the compare. */
21677 rs6000_generate_compare (rtx cmp, machine_mode mode)
21679 machine_mode comp_mode;
21680 rtx compare_result;
21681 enum rtx_code code = GET_CODE (cmp);
21682 rtx op0 = XEXP (cmp, 0);
21683 rtx op1 = XEXP (cmp, 1);
21685 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21686 comp_mode = CCmode;
21687 else if (FLOAT_MODE_P (mode))
21688 comp_mode = CCFPmode;
21689 else if (code == GTU || code == LTU
21690 || code == GEU || code == LEU)
21691 comp_mode = CCUNSmode;
21692 else if ((code == EQ || code == NE)
21693 && unsigned_reg_p (op0)
21694 && (unsigned_reg_p (op1)
21695 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21696 /* These are unsigned values, perhaps there will be a later
21697 ordering compare that can be shared with this one. */
21698 comp_mode = CCUNSmode;
21700 comp_mode = CCmode;
21702 /* If we have an unsigned compare, make sure we don't have a signed value as
21704 if (comp_mode == CCUNSmode && CONST_INT_P (op1)
21705 && INTVAL (op1) < 0)
21707 op0 = copy_rtx_if_shared (op0);
21708 op1 = force_reg (GET_MODE (op0), op1);
21709 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21712 /* First, the compare. */
21713 compare_result = gen_reg_rtx (comp_mode);
21715 /* IEEE 128-bit support in VSX registers when we do not have hardware
21717 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21719 rtx libfunc = NULL_RTX;
21720 bool check_nan = false;
21727 libfunc = optab_libfunc (eq_optab, mode);
21732 libfunc = optab_libfunc (ge_optab, mode);
21737 libfunc = optab_libfunc (le_optab, mode);
21742 libfunc = optab_libfunc (unord_optab, mode);
21743 code = (code == UNORDERED) ? NE : EQ;
21749 libfunc = optab_libfunc (ge_optab, mode);
21750 code = (code == UNGE) ? GE : GT;
21756 libfunc = optab_libfunc (le_optab, mode);
21757 code = (code == UNLE) ? LE : LT;
21763 libfunc = optab_libfunc (eq_optab, mode);
21764 code = (code = UNEQ) ? EQ : NE;
21768 gcc_unreachable ();
21771 gcc_assert (libfunc);
21774 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21775 SImode, op0, mode, op1, mode);
21777 /* The library signals an exception for signalling NaNs, so we need to
21778 handle isgreater, etc. by first checking isordered. */
21781 rtx ne_rtx, normal_dest, unord_dest;
21782 rtx unord_func = optab_libfunc (unord_optab, mode);
21783 rtx join_label = gen_label_rtx ();
21784 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21785 rtx unord_cmp = gen_reg_rtx (comp_mode);
21788 /* Test for either value being a NaN. */
21789 gcc_assert (unord_func);
21790 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21791 SImode, op0, mode, op1, mode);
21793 /* Set value (0) if either value is a NaN, and jump to the join
21795 dest = gen_reg_rtx (SImode);
21796 emit_move_insn (dest, const1_rtx);
21797 emit_insn (gen_rtx_SET (unord_cmp,
21798 gen_rtx_COMPARE (comp_mode, unord_dest,
21801 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21802 emit_jump_insn (gen_rtx_SET (pc_rtx,
21803 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21807 /* Do the normal comparison, knowing that the values are not
21809 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21810 SImode, op0, mode, op1, mode);
21812 emit_insn (gen_cstoresi4 (dest,
21813 gen_rtx_fmt_ee (code, SImode, normal_dest,
21815 normal_dest, const0_rtx));
21817 /* Join NaN and non-Nan paths. Compare dest against 0. */
21818 emit_label (join_label);
21822 emit_insn (gen_rtx_SET (compare_result,
21823 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21828 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21829 CLOBBERs to match cmptf_internal2 pattern. */
21830 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21831 && FLOAT128_IBM_P (GET_MODE (op0))
21832 && TARGET_HARD_FLOAT)
21833 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21835 gen_rtx_SET (compare_result,
21836 gen_rtx_COMPARE (comp_mode, op0, op1)),
21837 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21838 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21839 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21840 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21841 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21842 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21843 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21844 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21845 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21846 else if (GET_CODE (op1) == UNSPEC
21847 && XINT (op1, 1) == UNSPEC_SP_TEST)
21849 rtx op1b = XVECEXP (op1, 0, 0);
21850 comp_mode = CCEQmode;
21851 compare_result = gen_reg_rtx (CCEQmode);
21853 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21855 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21858 emit_insn (gen_rtx_SET (compare_result,
21859 gen_rtx_COMPARE (comp_mode, op0, op1)));
21862 /* Some kinds of FP comparisons need an OR operation;
21863 under flag_finite_math_only we don't bother. */
21864 if (FLOAT_MODE_P (mode)
21865 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21866 && !flag_finite_math_only
21867 && (code == LE || code == GE
21868 || code == UNEQ || code == LTGT
21869 || code == UNGT || code == UNLT))
21871 enum rtx_code or1, or2;
21872 rtx or1_rtx, or2_rtx, compare2_rtx;
21873 rtx or_result = gen_reg_rtx (CCEQmode);
21877 case LE: or1 = LT; or2 = EQ; break;
21878 case GE: or1 = GT; or2 = EQ; break;
21879 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21880 case LTGT: or1 = LT; or2 = GT; break;
21881 case UNGT: or1 = UNORDERED; or2 = GT; break;
21882 case UNLT: or1 = UNORDERED; or2 = LT; break;
21883 default: gcc_unreachable ();
21885 validate_condition_mode (or1, comp_mode);
21886 validate_condition_mode (or2, comp_mode);
21887 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21888 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21889 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21890 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21892 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21894 compare_result = or_result;
21898 validate_condition_mode (code, GET_MODE (compare_result));
21900 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21904 /* Return the diagnostic message string if the binary operation OP is
21905 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21908 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21912 machine_mode mode1 = TYPE_MODE (type1);
21913 machine_mode mode2 = TYPE_MODE (type2);
21915 /* For complex modes, use the inner type. */
21916 if (COMPLEX_MODE_P (mode1))
21917 mode1 = GET_MODE_INNER (mode1);
21919 if (COMPLEX_MODE_P (mode2))
21920 mode2 = GET_MODE_INNER (mode2);
21922 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21923 double to intermix unless -mfloat128-convert. */
21924 if (mode1 == mode2)
21927 if (!TARGET_FLOAT128_CVT)
21929 if ((mode1 == KFmode && mode2 == IFmode)
21930 || (mode1 == IFmode && mode2 == KFmode))
21931 return N_("__float128 and __ibm128 cannot be used in the same "
21934 if (TARGET_IEEEQUAD
21935 && ((mode1 == IFmode && mode2 == TFmode)
21936 || (mode1 == TFmode && mode2 == IFmode)))
21937 return N_("__ibm128 and long double cannot be used in the same "
21940 if (!TARGET_IEEEQUAD
21941 && ((mode1 == KFmode && mode2 == TFmode)
21942 || (mode1 == TFmode && mode2 == KFmode)))
21943 return N_("__float128 and long double cannot be used in the same "
21951 /* Expand floating point conversion to/from __float128 and __ibm128. */
21954 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21956 machine_mode dest_mode = GET_MODE (dest);
21957 machine_mode src_mode = GET_MODE (src);
21958 convert_optab cvt = unknown_optab;
21959 bool do_move = false;
21960 rtx libfunc = NULL_RTX;
21962 typedef rtx (*rtx_2func_t) (rtx, rtx);
21963 rtx_2func_t hw_convert = (rtx_2func_t)0;
21967 rtx_2func_t from_df;
21968 rtx_2func_t from_sf;
21969 rtx_2func_t from_si_sign;
21970 rtx_2func_t from_si_uns;
21971 rtx_2func_t from_di_sign;
21972 rtx_2func_t from_di_uns;
21975 rtx_2func_t to_si_sign;
21976 rtx_2func_t to_si_uns;
21977 rtx_2func_t to_di_sign;
21978 rtx_2func_t to_di_uns;
21979 } hw_conversions[2] = {
21980 /* convertions to/from KFmode */
21982 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21983 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21984 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21985 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21986 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21987 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21988 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21989 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21990 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21991 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21992 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21993 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21996 /* convertions to/from TFmode */
21998 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21999 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22000 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22001 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22002 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22003 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22004 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22005 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22006 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22007 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22008 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22009 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22013 if (dest_mode == src_mode)
22014 gcc_unreachable ();
22016 /* Eliminate memory operations. */
22018 src = force_reg (src_mode, src);
22022 rtx tmp = gen_reg_rtx (dest_mode);
22023 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22024 rs6000_emit_move (dest, tmp, dest_mode);
22028 /* Convert to IEEE 128-bit floating point. */
22029 if (FLOAT128_IEEE_P (dest_mode))
22031 if (dest_mode == KFmode)
22033 else if (dest_mode == TFmode)
22036 gcc_unreachable ();
22042 hw_convert = hw_conversions[kf_or_tf].from_df;
22047 hw_convert = hw_conversions[kf_or_tf].from_sf;
22053 if (FLOAT128_IBM_P (src_mode))
22062 cvt = ufloat_optab;
22063 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22067 cvt = sfloat_optab;
22068 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22075 cvt = ufloat_optab;
22076 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22080 cvt = sfloat_optab;
22081 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22086 gcc_unreachable ();
22090 /* Convert from IEEE 128-bit floating point. */
22091 else if (FLOAT128_IEEE_P (src_mode))
22093 if (src_mode == KFmode)
22095 else if (src_mode == TFmode)
22098 gcc_unreachable ();
22104 hw_convert = hw_conversions[kf_or_tf].to_df;
22109 hw_convert = hw_conversions[kf_or_tf].to_sf;
22115 if (FLOAT128_IBM_P (dest_mode))
22125 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22130 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22138 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22143 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22148 gcc_unreachable ();
22152 /* Both IBM format. */
22153 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22157 gcc_unreachable ();
22159 /* Handle conversion between TFmode/KFmode/IFmode. */
22161 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
22163 /* Handle conversion if we have hardware support. */
22164 else if (TARGET_FLOAT128_HW && hw_convert)
22165 emit_insn ((hw_convert) (dest, src));
22167 /* Call an external function to do the conversion. */
22168 else if (cvt != unknown_optab)
22170 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22171 gcc_assert (libfunc != NULL_RTX);
22173 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22176 gcc_assert (dest2 != NULL_RTX);
22177 if (!rtx_equal_p (dest, dest2))
22178 emit_move_insn (dest, dest2);
22182 gcc_unreachable ();
22188 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22189 can be used as that dest register. Return the dest register. */
22192 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22194 if (op2 == const0_rtx)
22197 if (GET_CODE (scratch) == SCRATCH)
22198 scratch = gen_reg_rtx (mode);
22200 if (logical_operand (op2, mode))
22201 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22203 emit_insn (gen_rtx_SET (scratch,
22204 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22210 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22213 machine_mode op_mode;
22214 enum rtx_code cond_code;
22215 rtx result = operands[0];
22217 condition_rtx = rs6000_generate_compare (operands[1], mode);
22218 cond_code = GET_CODE (condition_rtx);
22220 if (cond_code == NE
22221 || cond_code == GE || cond_code == LE
22222 || cond_code == GEU || cond_code == LEU
22223 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22225 rtx not_result = gen_reg_rtx (CCEQmode);
22226 rtx not_op, rev_cond_rtx;
22227 machine_mode cc_mode;
22229 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22231 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22232 SImode, XEXP (condition_rtx, 0), const0_rtx);
22233 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22234 emit_insn (gen_rtx_SET (not_result, not_op));
22235 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22238 op_mode = GET_MODE (XEXP (operands[1], 0));
22239 if (op_mode == VOIDmode)
22240 op_mode = GET_MODE (XEXP (operands[1], 1));
22242 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22244 PUT_MODE (condition_rtx, DImode);
22245 convert_move (result, condition_rtx, 0);
22249 PUT_MODE (condition_rtx, SImode);
22250 emit_insn (gen_rtx_SET (result, condition_rtx));
22254 /* Emit a branch of kind CODE to location LOC. */
22257 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22259 rtx condition_rtx, loc_ref;
22261 condition_rtx = rs6000_generate_compare (operands[0], mode);
22262 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22263 emit_jump_insn (gen_rtx_SET (pc_rtx,
22264 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22265 loc_ref, pc_rtx)));
22268 /* Return the string to output a conditional branch to LABEL, which is
22269 the operand template of the label, or NULL if the branch is really a
22270 conditional return.
22272 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22273 condition code register and its mode specifies what kind of
22274 comparison we made.
22276 REVERSED is nonzero if we should reverse the sense of the comparison.
22278 INSN is the insn. */
22281 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22283 static char string[64];
22284 enum rtx_code code = GET_CODE (op);
22285 rtx cc_reg = XEXP (op, 0);
22286 machine_mode mode = GET_MODE (cc_reg);
22287 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22288 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22289 int really_reversed = reversed ^ need_longbranch;
22295 validate_condition_mode (code, mode);
22297 /* Work out which way this really branches. We could use
22298 reverse_condition_maybe_unordered here always but this
22299 makes the resulting assembler clearer. */
22300 if (really_reversed)
22302 /* Reversal of FP compares takes care -- an ordered compare
22303 becomes an unordered compare and vice versa. */
22304 if (mode == CCFPmode)
22305 code = reverse_condition_maybe_unordered (code);
22307 code = reverse_condition (code);
22312 /* Not all of these are actually distinct opcodes, but
22313 we distinguish them for clarity of the resulting assembler. */
22314 case NE: case LTGT:
22315 ccode = "ne"; break;
22316 case EQ: case UNEQ:
22317 ccode = "eq"; break;
22319 ccode = "ge"; break;
22320 case GT: case GTU: case UNGT:
22321 ccode = "gt"; break;
22323 ccode = "le"; break;
22324 case LT: case LTU: case UNLT:
22325 ccode = "lt"; break;
22326 case UNORDERED: ccode = "un"; break;
22327 case ORDERED: ccode = "nu"; break;
22328 case UNGE: ccode = "nl"; break;
22329 case UNLE: ccode = "ng"; break;
22331 gcc_unreachable ();
22334 /* Maybe we have a guess as to how likely the branch is. */
22336 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22337 if (note != NULL_RTX)
22339 /* PROB is the difference from 50%. */
22340 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22341 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22343 /* Only hint for highly probable/improbable branches on newer cpus when
22344 we have real profile data, as static prediction overrides processor
22345 dynamic prediction. For older cpus we may as well always hint, but
22346 assume not taken for branches that are very close to 50% as a
22347 mispredicted taken branch is more expensive than a
22348 mispredicted not-taken branch. */
22349 if (rs6000_always_hint
22350 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22351 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22352 && br_prob_note_reliable_p (note)))
22354 if (abs (prob) > REG_BR_PROB_BASE / 20
22355 && ((prob > 0) ^ need_longbranch))
22363 s += sprintf (s, "b%slr%s ", ccode, pred);
22365 s += sprintf (s, "b%s%s ", ccode, pred);
22367 /* We need to escape any '%' characters in the reg_names string.
22368 Assume they'd only be the first character.... */
22369 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22371 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22375 /* If the branch distance was too far, we may have to use an
22376 unconditional branch to go the distance. */
22377 if (need_longbranch)
22378 s += sprintf (s, ",$+8\n\tb %s", label);
22380 s += sprintf (s, ",%s", label);
22386 /* Return insn for VSX or Altivec comparisons. */
22389 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22392 machine_mode mode = GET_MODE (op0);
22400 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22411 mask = gen_reg_rtx (mode);
22412 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22419 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22420 DMODE is expected destination mode. This is a recursive function. */
22423 rs6000_emit_vector_compare (enum rtx_code rcode,
22425 machine_mode dmode)
22428 bool swap_operands = false;
22429 bool try_again = false;
22431 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22432 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22434 /* See if the comparison works as is. */
22435 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22443 swap_operands = true;
22448 swap_operands = true;
22456 /* Invert condition and try again.
22457 e.g., A != B becomes ~(A==B). */
22459 enum rtx_code rev_code;
22460 enum insn_code nor_code;
22463 rev_code = reverse_condition_maybe_unordered (rcode);
22464 if (rev_code == UNKNOWN)
22467 nor_code = optab_handler (one_cmpl_optab, dmode);
22468 if (nor_code == CODE_FOR_nothing)
22471 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22475 mask = gen_reg_rtx (dmode);
22476 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22484 /* Try GT/GTU/LT/LTU OR EQ */
22487 enum insn_code ior_code;
22488 enum rtx_code new_code;
22509 gcc_unreachable ();
22512 ior_code = optab_handler (ior_optab, dmode);
22513 if (ior_code == CODE_FOR_nothing)
22516 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22520 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22524 mask = gen_reg_rtx (dmode);
22525 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22536 std::swap (op0, op1);
22538 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22543 /* You only get two chances. */
22547 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22548 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22549 operands for the relation operation COND. */
22552 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22553 rtx cond, rtx cc_op0, rtx cc_op1)
22555 machine_mode dest_mode = GET_MODE (dest);
22556 machine_mode mask_mode = GET_MODE (cc_op0);
22557 enum rtx_code rcode = GET_CODE (cond);
22558 machine_mode cc_mode = CCmode;
22561 bool invert_move = false;
22563 if (VECTOR_UNIT_NONE_P (dest_mode))
22566 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22567 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22571 /* Swap operands if we can, and fall back to doing the operation as
22572 specified, and doing a NOR to invert the test. */
22578 /* Invert condition and try again.
22579 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22580 invert_move = true;
22581 rcode = reverse_condition_maybe_unordered (rcode);
22582 if (rcode == UNKNOWN)
22588 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22590 /* Invert condition to avoid compound test. */
22591 invert_move = true;
22592 rcode = reverse_condition (rcode);
22600 /* Mark unsigned tests with CCUNSmode. */
22601 cc_mode = CCUNSmode;
22603 /* Invert condition to avoid compound test if necessary. */
22604 if (rcode == GEU || rcode == LEU)
22606 invert_move = true;
22607 rcode = reverse_condition (rcode);
22615 /* Get the vector mask for the given relational operations. */
22616 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22622 std::swap (op_true, op_false);
22624 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22625 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22626 && (GET_CODE (op_true) == CONST_VECTOR
22627 || GET_CODE (op_false) == CONST_VECTOR))
22629 rtx constant_0 = CONST0_RTX (dest_mode);
22630 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22632 if (op_true == constant_m1 && op_false == constant_0)
22634 emit_move_insn (dest, mask);
22638 else if (op_true == constant_0 && op_false == constant_m1)
22640 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22644 /* If we can't use the vector comparison directly, perhaps we can use
22645 the mask for the true or false fields, instead of loading up a
22647 if (op_true == constant_m1)
22650 if (op_false == constant_0)
22654 if (!REG_P (op_true) && !SUBREG_P (op_true))
22655 op_true = force_reg (dest_mode, op_true);
22657 if (!REG_P (op_false) && !SUBREG_P (op_false))
22658 op_false = force_reg (dest_mode, op_false);
22660 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22661 CONST0_RTX (dest_mode));
22662 emit_insn (gen_rtx_SET (dest,
22663 gen_rtx_IF_THEN_ELSE (dest_mode,
22670 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22671 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22672 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22673 hardware has no such operation. */
22676 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22678 enum rtx_code code = GET_CODE (op);
22679 rtx op0 = XEXP (op, 0);
22680 rtx op1 = XEXP (op, 1);
22681 machine_mode compare_mode = GET_MODE (op0);
22682 machine_mode result_mode = GET_MODE (dest);
22683 bool max_p = false;
22685 if (result_mode != compare_mode)
22688 if (code == GE || code == GT)
22690 else if (code == LE || code == LT)
22695 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22698 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22704 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22708 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22709 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22710 operands of the last comparison is nonzero/true, FALSE_COND if it is
22711 zero/false. Return 0 if the hardware has no such operation. */
22714 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22716 enum rtx_code code = GET_CODE (op);
22717 rtx op0 = XEXP (op, 0);
22718 rtx op1 = XEXP (op, 1);
22719 machine_mode result_mode = GET_MODE (dest);
22724 if (!can_create_pseudo_p ())
22737 code = swap_condition (code);
22738 std::swap (op0, op1);
22745 /* Generate: [(parallel [(set (dest)
22746 (if_then_else (op (cmp1) (cmp2))
22749 (clobber (scratch))])]. */
22751 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22752 cmove_rtx = gen_rtx_SET (dest,
22753 gen_rtx_IF_THEN_ELSE (result_mode,
22758 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22759 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22760 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22765 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22766 operands of the last comparison is nonzero/true, FALSE_COND if it
22767 is zero/false. Return 0 if the hardware has no such operation. */
22770 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22772 enum rtx_code code = GET_CODE (op);
22773 rtx op0 = XEXP (op, 0);
22774 rtx op1 = XEXP (op, 1);
22775 machine_mode compare_mode = GET_MODE (op0);
22776 machine_mode result_mode = GET_MODE (dest);
22778 bool is_against_zero;
22780 /* These modes should always match. */
22781 if (GET_MODE (op1) != compare_mode
22782 /* In the isel case however, we can use a compare immediate, so
22783 op1 may be a small constant. */
22784 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22786 if (GET_MODE (true_cond) != result_mode)
22788 if (GET_MODE (false_cond) != result_mode)
22791 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22792 if (TARGET_P9_MINMAX
22793 && (compare_mode == SFmode || compare_mode == DFmode)
22794 && (result_mode == SFmode || result_mode == DFmode))
22796 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22799 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22803 /* Don't allow using floating point comparisons for integer results for
22805 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22808 /* First, work out if the hardware can do this at all, or
22809 if it's too slow.... */
22810 if (!FLOAT_MODE_P (compare_mode))
22813 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22817 is_against_zero = op1 == CONST0_RTX (compare_mode);
22819 /* A floating-point subtract might overflow, underflow, or produce
22820 an inexact result, thus changing the floating-point flags, so it
22821 can't be generated if we care about that. It's safe if one side
22822 of the construct is zero, since then no subtract will be
22824 if (SCALAR_FLOAT_MODE_P (compare_mode)
22825 && flag_trapping_math && ! is_against_zero)
22828 /* Eliminate half of the comparisons by switching operands, this
22829 makes the remaining code simpler. */
22830 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22831 || code == LTGT || code == LT || code == UNLE)
22833 code = reverse_condition_maybe_unordered (code);
22835 true_cond = false_cond;
22839 /* UNEQ and LTGT take four instructions for a comparison with zero,
22840 it'll probably be faster to use a branch here too. */
22841 if (code == UNEQ && HONOR_NANS (compare_mode))
22844 /* We're going to try to implement comparisons by performing
22845 a subtract, then comparing against zero. Unfortunately,
22846 Inf - Inf is NaN which is not zero, and so if we don't
22847 know that the operand is finite and the comparison
22848 would treat EQ different to UNORDERED, we can't do it. */
22849 if (HONOR_INFINITIES (compare_mode)
22850 && code != GT && code != UNGE
22851 && (!CONST_DOUBLE_P (op1)
22852 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22853 /* Constructs of the form (a OP b ? a : b) are safe. */
22854 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22855 || (! rtx_equal_p (op0, true_cond)
22856 && ! rtx_equal_p (op1, true_cond))))
22859 /* At this point we know we can use fsel. */
22861 /* Reduce the comparison to a comparison against zero. */
22862 if (! is_against_zero)
22864 temp = gen_reg_rtx (compare_mode);
22865 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22867 op1 = CONST0_RTX (compare_mode);
22870 /* If we don't care about NaNs we can reduce some of the comparisons
22871 down to faster ones. */
22872 if (! HONOR_NANS (compare_mode))
22878 true_cond = false_cond;
22891 /* Now, reduce everything down to a GE. */
22898 temp = gen_reg_rtx (compare_mode);
22899 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22904 temp = gen_reg_rtx (compare_mode);
22905 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22910 temp = gen_reg_rtx (compare_mode);
22911 emit_insn (gen_rtx_SET (temp,
22912 gen_rtx_NEG (compare_mode,
22913 gen_rtx_ABS (compare_mode, op0))));
22918 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22919 temp = gen_reg_rtx (result_mode);
22920 emit_insn (gen_rtx_SET (temp,
22921 gen_rtx_IF_THEN_ELSE (result_mode,
22922 gen_rtx_GE (VOIDmode,
22924 true_cond, false_cond)));
22925 false_cond = true_cond;
22928 temp = gen_reg_rtx (compare_mode);
22929 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22934 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22935 temp = gen_reg_rtx (result_mode);
22936 emit_insn (gen_rtx_SET (temp,
22937 gen_rtx_IF_THEN_ELSE (result_mode,
22938 gen_rtx_GE (VOIDmode,
22940 true_cond, false_cond)));
22941 true_cond = false_cond;
22944 temp = gen_reg_rtx (compare_mode);
22945 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22950 gcc_unreachable ();
22953 emit_insn (gen_rtx_SET (dest,
22954 gen_rtx_IF_THEN_ELSE (result_mode,
22955 gen_rtx_GE (VOIDmode,
22957 true_cond, false_cond)));
22961 /* Same as above, but for ints (isel). */
22964 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22966 rtx condition_rtx, cr;
22967 machine_mode mode = GET_MODE (dest);
22968 enum rtx_code cond_code;
22969 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22972 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22975 /* We still have to do the compare, because isel doesn't do a
22976 compare, it just looks at the CRx bits set by a previous compare
22978 condition_rtx = rs6000_generate_compare (op, mode);
22979 cond_code = GET_CODE (condition_rtx);
22980 cr = XEXP (condition_rtx, 0);
22981 signedp = GET_MODE (cr) == CCmode;
22983 isel_func = (mode == SImode
22984 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22985 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22989 case LT: case GT: case LTU: case GTU: case EQ:
22990 /* isel handles these directly. */
22994 /* We need to swap the sense of the comparison. */
22996 std::swap (false_cond, true_cond);
22997 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23002 false_cond = force_reg (mode, false_cond);
23003 if (true_cond != const0_rtx)
23004 true_cond = force_reg (mode, true_cond);
23006 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23012 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23014 machine_mode mode = GET_MODE (op0);
23018 /* VSX/altivec have direct min/max insns. */
23019 if ((code == SMAX || code == SMIN)
23020 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23021 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23023 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23027 if (code == SMAX || code == SMIN)
23032 if (code == SMAX || code == UMAX)
23033 target = emit_conditional_move (dest, c, op0, op1, mode,
23034 op0, op1, mode, 0);
23036 target = emit_conditional_move (dest, c, op0, op1, mode,
23037 op1, op0, mode, 0);
23038 gcc_assert (target);
23039 if (target != dest)
23040 emit_move_insn (dest, target);
23043 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23044 COND is true. Mark the jump as unlikely to be taken. */
23047 emit_unlikely_jump (rtx cond, rtx label)
23049 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23050 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23051 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23054 /* A subroutine of the atomic operation splitters. Emit a load-locked
23055 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23056 the zero_extend operation. */
23059 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23061 rtx (*fn) (rtx, rtx) = NULL;
23066 fn = gen_load_lockedqi;
23069 fn = gen_load_lockedhi;
23072 if (GET_MODE (mem) == QImode)
23073 fn = gen_load_lockedqi_si;
23074 else if (GET_MODE (mem) == HImode)
23075 fn = gen_load_lockedhi_si;
23077 fn = gen_load_lockedsi;
23080 fn = gen_load_lockeddi;
23083 fn = gen_load_lockedti;
23086 gcc_unreachable ();
23088 emit_insn (fn (reg, mem));
23091 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23092 instruction in MODE. */
23095 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23097 rtx (*fn) (rtx, rtx, rtx) = NULL;
23102 fn = gen_store_conditionalqi;
23105 fn = gen_store_conditionalhi;
23108 fn = gen_store_conditionalsi;
23111 fn = gen_store_conditionaldi;
23114 fn = gen_store_conditionalti;
23117 gcc_unreachable ();
23120 /* Emit sync before stwcx. to address PPC405 Erratum. */
23121 if (PPC405_ERRATUM77)
23122 emit_insn (gen_hwsync ());
23124 emit_insn (fn (res, mem, val));
23127 /* Expand barriers before and after a load_locked/store_cond sequence. */
23130 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23132 rtx addr = XEXP (mem, 0);
23134 if (!legitimate_indirect_address_p (addr, reload_completed)
23135 && !legitimate_indexed_address_p (addr, reload_completed))
23137 addr = force_reg (Pmode, addr);
23138 mem = replace_equiv_address_nv (mem, addr);
23143 case MEMMODEL_RELAXED:
23144 case MEMMODEL_CONSUME:
23145 case MEMMODEL_ACQUIRE:
23147 case MEMMODEL_RELEASE:
23148 case MEMMODEL_ACQ_REL:
23149 emit_insn (gen_lwsync ());
23151 case MEMMODEL_SEQ_CST:
23152 emit_insn (gen_hwsync ());
23155 gcc_unreachable ();
23161 rs6000_post_atomic_barrier (enum memmodel model)
23165 case MEMMODEL_RELAXED:
23166 case MEMMODEL_CONSUME:
23167 case MEMMODEL_RELEASE:
23169 case MEMMODEL_ACQUIRE:
23170 case MEMMODEL_ACQ_REL:
23171 case MEMMODEL_SEQ_CST:
23172 emit_insn (gen_isync ());
23175 gcc_unreachable ();
23179 /* A subroutine of the various atomic expanders. For sub-word operations,
23180 we must adjust things to operate on SImode. Given the original MEM,
23181 return a new aligned memory. Also build and return the quantities by
23182 which to shift and mask. */
23185 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23187 rtx addr, align, shift, mask, mem;
23188 HOST_WIDE_INT shift_mask;
23189 machine_mode mode = GET_MODE (orig_mem);
23191 /* For smaller modes, we have to implement this via SImode. */
23192 shift_mask = (mode == QImode ? 0x18 : 0x10);
23194 addr = XEXP (orig_mem, 0);
23195 addr = force_reg (GET_MODE (addr), addr);
23197 /* Aligned memory containing subword. Generate a new memory. We
23198 do not want any of the existing MEM_ATTR data, as we're now
23199 accessing memory outside the original object. */
23200 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23201 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23202 mem = gen_rtx_MEM (SImode, align);
23203 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23204 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23205 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23207 /* Shift amount for subword relative to aligned word. */
23208 shift = gen_reg_rtx (SImode);
23209 addr = gen_lowpart (SImode, addr);
23210 rtx tmp = gen_reg_rtx (SImode);
23211 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23212 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23213 if (BYTES_BIG_ENDIAN)
23214 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23215 shift, 1, OPTAB_LIB_WIDEN);
23218 /* Mask for insertion. */
23219 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23220 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23226 /* A subroutine of the various atomic expanders. For sub-word operands,
23227 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23230 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23234 x = gen_reg_rtx (SImode);
23235 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23236 gen_rtx_NOT (SImode, mask),
23239 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23244 /* A subroutine of the various atomic expanders. For sub-word operands,
23245 extract WIDE to NARROW via SHIFT. */
23248 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23250 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23251 wide, 1, OPTAB_LIB_WIDEN);
23252 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23255 /* Expand an atomic compare and swap operation. */
23258 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23260 rtx boolval, retval, mem, oldval, newval, cond;
23261 rtx label1, label2, x, mask, shift;
23262 machine_mode mode, orig_mode;
23263 enum memmodel mod_s, mod_f;
23266 boolval = operands[0];
23267 retval = operands[1];
23269 oldval = operands[3];
23270 newval = operands[4];
23271 is_weak = (INTVAL (operands[5]) != 0);
23272 mod_s = memmodel_base (INTVAL (operands[6]));
23273 mod_f = memmodel_base (INTVAL (operands[7]));
23274 orig_mode = mode = GET_MODE (mem);
23276 mask = shift = NULL_RTX;
23277 if (mode == QImode || mode == HImode)
23279 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23280 lwarx and shift/mask operations. With power8, we need to do the
23281 comparison in SImode, but the store is still done in QI/HImode. */
23282 oldval = convert_modes (SImode, mode, oldval, 1);
23284 if (!TARGET_SYNC_HI_QI)
23286 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23288 /* Shift and mask OLDVAL into position with the word. */
23289 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23290 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23292 /* Shift and mask NEWVAL into position within the word. */
23293 newval = convert_modes (SImode, mode, newval, 1);
23294 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23295 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23298 /* Prepare to adjust the return value. */
23299 retval = gen_reg_rtx (SImode);
23302 else if (reg_overlap_mentioned_p (retval, oldval))
23303 oldval = copy_to_reg (oldval);
23305 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23306 oldval = copy_to_mode_reg (mode, oldval);
23308 if (reg_overlap_mentioned_p (retval, newval))
23309 newval = copy_to_reg (newval);
23311 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23316 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23317 emit_label (XEXP (label1, 0));
23319 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23321 emit_load_locked (mode, retval, mem);
23325 x = expand_simple_binop (SImode, AND, retval, mask,
23326 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23328 cond = gen_reg_rtx (CCmode);
23329 /* If we have TImode, synthesize a comparison. */
23330 if (mode != TImode)
23331 x = gen_rtx_COMPARE (CCmode, x, oldval);
23334 rtx xor1_result = gen_reg_rtx (DImode);
23335 rtx xor2_result = gen_reg_rtx (DImode);
23336 rtx or_result = gen_reg_rtx (DImode);
23337 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23338 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23339 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23340 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23342 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23343 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23344 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23345 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23348 emit_insn (gen_rtx_SET (cond, x));
23350 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23351 emit_unlikely_jump (x, label2);
23355 x = rs6000_mask_atomic_subword (retval, newval, mask);
23357 emit_store_conditional (orig_mode, cond, mem, x);
23361 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23362 emit_unlikely_jump (x, label1);
23365 if (!is_mm_relaxed (mod_f))
23366 emit_label (XEXP (label2, 0));
23368 rs6000_post_atomic_barrier (mod_s);
23370 if (is_mm_relaxed (mod_f))
23371 emit_label (XEXP (label2, 0));
23374 rs6000_finish_atomic_subword (operands[1], retval, shift);
23375 else if (mode != GET_MODE (operands[1]))
23376 convert_move (operands[1], retval, 1);
23378 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23379 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23380 emit_insn (gen_rtx_SET (boolval, x));
23383 /* Expand an atomic exchange operation. */
23386 rs6000_expand_atomic_exchange (rtx operands[])
23388 rtx retval, mem, val, cond;
23390 enum memmodel model;
23391 rtx label, x, mask, shift;
23393 retval = operands[0];
23396 model = memmodel_base (INTVAL (operands[3]));
23397 mode = GET_MODE (mem);
23399 mask = shift = NULL_RTX;
23400 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23402 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23404 /* Shift and mask VAL into position with the word. */
23405 val = convert_modes (SImode, mode, val, 1);
23406 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23407 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23409 /* Prepare to adjust the return value. */
23410 retval = gen_reg_rtx (SImode);
23414 mem = rs6000_pre_atomic_barrier (mem, model);
23416 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23417 emit_label (XEXP (label, 0));
23419 emit_load_locked (mode, retval, mem);
23423 x = rs6000_mask_atomic_subword (retval, val, mask);
23425 cond = gen_reg_rtx (CCmode);
23426 emit_store_conditional (mode, cond, mem, x);
23428 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23429 emit_unlikely_jump (x, label);
23431 rs6000_post_atomic_barrier (model);
23434 rs6000_finish_atomic_subword (operands[0], retval, shift);
23437 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23438 to perform. MEM is the memory on which to operate. VAL is the second
23439 operand of the binary operator. BEFORE and AFTER are optional locations to
23440 return the value of MEM either before of after the operation. MODEL_RTX
23441 is a CONST_INT containing the memory model to use. */
23444 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23445 rtx orig_before, rtx orig_after, rtx model_rtx)
23447 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23448 machine_mode mode = GET_MODE (mem);
23449 machine_mode store_mode = mode;
23450 rtx label, x, cond, mask, shift;
23451 rtx before = orig_before, after = orig_after;
23453 mask = shift = NULL_RTX;
23454 /* On power8, we want to use SImode for the operation. On previous systems,
23455 use the operation in a subword and shift/mask to get the proper byte or
23457 if (mode == QImode || mode == HImode)
23459 if (TARGET_SYNC_HI_QI)
23461 val = convert_modes (SImode, mode, val, 1);
23463 /* Prepare to adjust the return value. */
23464 before = gen_reg_rtx (SImode);
23466 after = gen_reg_rtx (SImode);
23471 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23473 /* Shift and mask VAL into position with the word. */
23474 val = convert_modes (SImode, mode, val, 1);
23475 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23476 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23482 /* We've already zero-extended VAL. That is sufficient to
23483 make certain that it does not affect other bits. */
23488 /* If we make certain that all of the other bits in VAL are
23489 set, that will be sufficient to not affect other bits. */
23490 x = gen_rtx_NOT (SImode, mask);
23491 x = gen_rtx_IOR (SImode, x, val);
23492 emit_insn (gen_rtx_SET (val, x));
23499 /* These will all affect bits outside the field and need
23500 adjustment via MASK within the loop. */
23504 gcc_unreachable ();
23507 /* Prepare to adjust the return value. */
23508 before = gen_reg_rtx (SImode);
23510 after = gen_reg_rtx (SImode);
23511 store_mode = mode = SImode;
23515 mem = rs6000_pre_atomic_barrier (mem, model);
23517 label = gen_label_rtx ();
23518 emit_label (label);
23519 label = gen_rtx_LABEL_REF (VOIDmode, label);
23521 if (before == NULL_RTX)
23522 before = gen_reg_rtx (mode);
23524 emit_load_locked (mode, before, mem);
23528 x = expand_simple_binop (mode, AND, before, val,
23529 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23530 after = expand_simple_unop (mode, NOT, x, after, 1);
23534 after = expand_simple_binop (mode, code, before, val,
23535 after, 1, OPTAB_LIB_WIDEN);
23541 x = expand_simple_binop (SImode, AND, after, mask,
23542 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23543 x = rs6000_mask_atomic_subword (before, x, mask);
23545 else if (store_mode != mode)
23546 x = convert_modes (store_mode, mode, x, 1);
23548 cond = gen_reg_rtx (CCmode);
23549 emit_store_conditional (store_mode, cond, mem, x);
23551 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23552 emit_unlikely_jump (x, label);
23554 rs6000_post_atomic_barrier (model);
23558 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23559 then do the calcuations in a SImode register. */
23561 rs6000_finish_atomic_subword (orig_before, before, shift);
23563 rs6000_finish_atomic_subword (orig_after, after, shift);
23565 else if (store_mode != mode)
23567 /* QImode/HImode on machines with lbarx/lharx where we do the native
23568 operation and then do the calcuations in a SImode register. */
23570 convert_move (orig_before, before, 1);
23572 convert_move (orig_after, after, 1);
23574 else if (orig_after && after != orig_after)
23575 emit_move_insn (orig_after, after);
23578 /* Emit instructions to move SRC to DST. Called by splitters for
23579 multi-register moves. It will emit at most one instruction for
23580 each register that is accessed; that is, it won't emit li/lis pairs
23581 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23585 rs6000_split_multireg_move (rtx dst, rtx src)
23587 /* The register number of the first register being moved. */
23589 /* The mode that is to be moved. */
23591 /* The mode that the move is being done in, and its size. */
23592 machine_mode reg_mode;
23594 /* The number of registers that will be moved. */
23597 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23598 mode = GET_MODE (dst);
23599 nregs = hard_regno_nregs (reg, mode);
23600 if (FP_REGNO_P (reg))
23601 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23602 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23603 else if (ALTIVEC_REGNO_P (reg))
23604 reg_mode = V16QImode;
23606 reg_mode = word_mode;
23607 reg_mode_size = GET_MODE_SIZE (reg_mode);
23609 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23611 /* TDmode residing in FP registers is special, since the ISA requires that
23612 the lower-numbered word of a register pair is always the most significant
23613 word, even in little-endian mode. This does not match the usual subreg
23614 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23615 the appropriate constituent registers "by hand" in little-endian mode.
23617 Note we do not need to check for destructive overlap here since TDmode
23618 can only reside in even/odd register pairs. */
23619 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23624 for (i = 0; i < nregs; i++)
23626 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23627 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23629 p_src = simplify_gen_subreg (reg_mode, src, mode,
23630 i * reg_mode_size);
23632 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23633 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23635 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23636 i * reg_mode_size);
23638 emit_insn (gen_rtx_SET (p_dst, p_src));
23644 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23646 /* Move register range backwards, if we might have destructive
23649 for (i = nregs - 1; i >= 0; i--)
23650 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23651 i * reg_mode_size),
23652 simplify_gen_subreg (reg_mode, src, mode,
23653 i * reg_mode_size)));
23659 bool used_update = false;
23660 rtx restore_basereg = NULL_RTX;
23662 if (MEM_P (src) && INT_REGNO_P (reg))
23666 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23667 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23670 breg = XEXP (XEXP (src, 0), 0);
23671 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23672 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23673 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23674 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23675 src = replace_equiv_address (src, breg);
23677 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23679 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23681 rtx basereg = XEXP (XEXP (src, 0), 0);
23684 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23685 emit_insn (gen_rtx_SET (ndst,
23686 gen_rtx_MEM (reg_mode,
23688 used_update = true;
23691 emit_insn (gen_rtx_SET (basereg,
23692 XEXP (XEXP (src, 0), 1)));
23693 src = replace_equiv_address (src, basereg);
23697 rtx basereg = gen_rtx_REG (Pmode, reg);
23698 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23699 src = replace_equiv_address (src, basereg);
23703 breg = XEXP (src, 0);
23704 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23705 breg = XEXP (breg, 0);
23707 /* If the base register we are using to address memory is
23708 also a destination reg, then change that register last. */
23710 && REGNO (breg) >= REGNO (dst)
23711 && REGNO (breg) < REGNO (dst) + nregs)
23712 j = REGNO (breg) - REGNO (dst);
23714 else if (MEM_P (dst) && INT_REGNO_P (reg))
23718 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23719 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23722 breg = XEXP (XEXP (dst, 0), 0);
23723 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23724 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23725 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23727 /* We have to update the breg before doing the store.
23728 Use store with update, if available. */
23732 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23733 emit_insn (TARGET_32BIT
23734 ? (TARGET_POWERPC64
23735 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23736 : gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
23737 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23738 used_update = true;
23741 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23742 dst = replace_equiv_address (dst, breg);
23744 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23745 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23747 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23749 rtx basereg = XEXP (XEXP (dst, 0), 0);
23752 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23753 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23756 used_update = true;
23759 emit_insn (gen_rtx_SET (basereg,
23760 XEXP (XEXP (dst, 0), 1)));
23761 dst = replace_equiv_address (dst, basereg);
23765 rtx basereg = XEXP (XEXP (dst, 0), 0);
23766 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23767 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23769 && REG_P (offsetreg)
23770 && REGNO (basereg) != REGNO (offsetreg));
23771 if (REGNO (basereg) == 0)
23773 rtx tmp = offsetreg;
23774 offsetreg = basereg;
23777 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23778 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23779 dst = replace_equiv_address (dst, basereg);
23782 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23783 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23786 for (i = 0; i < nregs; i++)
23788 /* Calculate index to next subword. */
23793 /* If compiler already emitted move of first word by
23794 store with update, no need to do anything. */
23795 if (j == 0 && used_update)
23798 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23799 j * reg_mode_size),
23800 simplify_gen_subreg (reg_mode, src, mode,
23801 j * reg_mode_size)));
23803 if (restore_basereg != NULL_RTX)
23804 emit_insn (restore_basereg);
23809 /* This page contains routines that are used to determine what the
23810 function prologue and epilogue code will do and write them out. */
23812 /* Determine whether the REG is really used. */
23815 save_reg_p (int reg)
23817 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23819 /* When calling eh_return, we must return true for all the cases
23820 where conditional_register_usage marks the PIC offset reg
23821 call used or fixed. */
23822 if (crtl->calls_eh_return
23823 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23824 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23825 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23828 /* We need to mark the PIC offset register live for the same
23829 conditions as it is set up in rs6000_emit_prologue, or
23830 otherwise it won't be saved before we clobber it. */
23831 if (TARGET_TOC && TARGET_MINIMAL_TOC
23832 && !constant_pool_empty_p ())
23835 if (DEFAULT_ABI == ABI_V4
23836 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
23837 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
23840 if (DEFAULT_ABI == ABI_DARWIN
23841 && flag_pic && crtl->uses_pic_offset_table)
23845 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23848 /* Return the first fixed-point register that is required to be
23849 saved. 32 if none. */
23852 first_reg_to_save (void)
23856 /* Find lowest numbered live register. */
23857 for (first_reg = 13; first_reg <= 31; first_reg++)
23858 if (save_reg_p (first_reg))
23864 /* Similar, for FP regs. */
23867 first_fp_reg_to_save (void)
23871 /* Find lowest numbered live register. */
23872 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23873 if (save_reg_p (first_reg))
23879 /* Similar, for AltiVec regs. */
23882 first_altivec_reg_to_save (void)
23886 /* Stack frame remains as is unless we are in AltiVec ABI. */
23887 if (! TARGET_ALTIVEC_ABI)
23888 return LAST_ALTIVEC_REGNO + 1;
23890 /* On Darwin, the unwind routines are compiled without
23891 TARGET_ALTIVEC, and use save_world to save/restore the
23892 altivec registers when necessary. */
23893 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23894 && ! TARGET_ALTIVEC)
23895 return FIRST_ALTIVEC_REGNO + 20;
23897 /* Find lowest numbered live register. */
23898 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23899 if (save_reg_p (i))
23905 /* Return a 32-bit mask of the AltiVec registers we need to set in
23906 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23907 the 32-bit word is 0. */
23909 static unsigned int
23910 compute_vrsave_mask (void)
23912 unsigned int i, mask = 0;
23914 /* On Darwin, the unwind routines are compiled without
23915 TARGET_ALTIVEC, and use save_world to save/restore the
23916 call-saved altivec registers when necessary. */
23917 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23918 && ! TARGET_ALTIVEC)
23921 /* First, find out if we use _any_ altivec registers. */
23922 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23923 if (df_regs_ever_live_p (i))
23924 mask |= ALTIVEC_REG_BIT (i);
23929 /* Next, remove the argument registers from the set. These must
23930 be in the VRSAVE mask set by the caller, so we don't need to add
23931 them in again. More importantly, the mask we compute here is
23932 used to generate CLOBBERs in the set_vrsave insn, and we do not
23933 wish the argument registers to die. */
23934 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23935 mask &= ~ALTIVEC_REG_BIT (i);
23937 /* Similarly, remove the return value from the set. */
23940 diddle_return_value (is_altivec_return_reg, &yes);
23942 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23948 /* For a very restricted set of circumstances, we can cut down the
23949 size of prologues/epilogues by calling our own save/restore-the-world
23953 compute_save_world_info (rs6000_stack_t *info)
23955 info->world_save_p = 1;
23957 = (WORLD_SAVE_P (info)
23958 && DEFAULT_ABI == ABI_DARWIN
23959 && !cfun->has_nonlocal_label
23960 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23961 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23962 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23963 && info->cr_save_p);
23965 /* This will not work in conjunction with sibcalls. Make sure there
23966 are none. (This check is expensive, but seldom executed.) */
23967 if (WORLD_SAVE_P (info))
23970 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23971 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23973 info->world_save_p = 0;
23978 if (WORLD_SAVE_P (info))
23980 /* Even if we're not touching VRsave, make sure there's room on the
23981 stack for it, if it looks like we're calling SAVE_WORLD, which
23982 will attempt to save it. */
23983 info->vrsave_size = 4;
23985 /* If we are going to save the world, we need to save the link register too. */
23986 info->lr_save_p = 1;
23988 /* "Save" the VRsave register too if we're saving the world. */
23989 if (info->vrsave_mask == 0)
23990 info->vrsave_mask = compute_vrsave_mask ();
23992 /* Because the Darwin register save/restore routines only handle
23993 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23995 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23996 && (info->first_altivec_reg_save
23997 >= FIRST_SAVED_ALTIVEC_REGNO));
24005 is_altivec_return_reg (rtx reg, void *xyes)
24007 bool *yes = (bool *) xyes;
24008 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24013 /* Return whether REG is a global user reg or has been specifed by
24014 -ffixed-REG. We should not restore these, and so cannot use
24015 lmw or out-of-line restore functions if there are any. We also
24016 can't save them (well, emit frame notes for them), because frame
24017 unwinding during exception handling will restore saved registers. */
24020 fixed_reg_p (int reg)
24022 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24023 backend sets it, overriding anything the user might have given. */
24024 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24025 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24026 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24027 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24030 return fixed_regs[reg];
24033 /* Determine the strategy for savings/restoring registers. */
24036 SAVE_MULTIPLE = 0x1,
24037 SAVE_INLINE_GPRS = 0x2,
24038 SAVE_INLINE_FPRS = 0x4,
24039 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24040 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24041 SAVE_INLINE_VRS = 0x20,
24042 REST_MULTIPLE = 0x100,
24043 REST_INLINE_GPRS = 0x200,
24044 REST_INLINE_FPRS = 0x400,
24045 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24046 REST_INLINE_VRS = 0x1000
24050 rs6000_savres_strategy (rs6000_stack_t *info,
24051 bool using_static_chain_p)
24055 /* Select between in-line and out-of-line save and restore of regs.
24056 First, all the obvious cases where we don't use out-of-line. */
24057 if (crtl->calls_eh_return
24058 || cfun->machine->ra_need_lr)
24059 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24060 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24061 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24063 if (info->first_gp_reg_save == 32)
24064 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24066 if (info->first_fp_reg_save == 64)
24067 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24069 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24070 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24072 /* Define cutoff for using out-of-line functions to save registers. */
24073 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24075 if (!optimize_size)
24077 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24078 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24079 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24083 /* Prefer out-of-line restore if it will exit. */
24084 if (info->first_fp_reg_save > 61)
24085 strategy |= SAVE_INLINE_FPRS;
24086 if (info->first_gp_reg_save > 29)
24088 if (info->first_fp_reg_save == 64)
24089 strategy |= SAVE_INLINE_GPRS;
24091 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24093 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24094 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24097 else if (DEFAULT_ABI == ABI_DARWIN)
24099 if (info->first_fp_reg_save > 60)
24100 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24101 if (info->first_gp_reg_save > 29)
24102 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24103 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24107 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24108 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24109 || info->first_fp_reg_save > 61)
24110 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24111 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24112 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24115 /* Don't bother to try to save things out-of-line if r11 is occupied
24116 by the static chain. It would require too much fiddling and the
24117 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24118 pointer on Darwin, and AIX uses r1 or r12. */
24119 if (using_static_chain_p
24120 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24121 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24123 | SAVE_INLINE_VRS);
24125 /* Don't ever restore fixed regs. That means we can't use the
24126 out-of-line register restore functions if a fixed reg is in the
24127 range of regs restored. */
24128 if (!(strategy & REST_INLINE_FPRS))
24129 for (int i = info->first_fp_reg_save; i < 64; i++)
24132 strategy |= REST_INLINE_FPRS;
24136 /* We can only use the out-of-line routines to restore fprs if we've
24137 saved all the registers from first_fp_reg_save in the prologue.
24138 Otherwise, we risk loading garbage. Of course, if we have saved
24139 out-of-line then we know we haven't skipped any fprs. */
24140 if ((strategy & SAVE_INLINE_FPRS)
24141 && !(strategy & REST_INLINE_FPRS))
24142 for (int i = info->first_fp_reg_save; i < 64; i++)
24143 if (!save_reg_p (i))
24145 strategy |= REST_INLINE_FPRS;
24149 /* Similarly, for altivec regs. */
24150 if (!(strategy & REST_INLINE_VRS))
24151 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24154 strategy |= REST_INLINE_VRS;
24158 if ((strategy & SAVE_INLINE_VRS)
24159 && !(strategy & REST_INLINE_VRS))
24160 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24161 if (!save_reg_p (i))
24163 strategy |= REST_INLINE_VRS;
24167 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24168 saved is an out-of-line save or restore. Set up the value for
24169 the next test (excluding out-of-line gprs). */
24170 bool lr_save_p = (info->lr_save_p
24171 || !(strategy & SAVE_INLINE_FPRS)
24172 || !(strategy & SAVE_INLINE_VRS)
24173 || !(strategy & REST_INLINE_FPRS)
24174 || !(strategy & REST_INLINE_VRS));
24176 if (TARGET_MULTIPLE
24177 && !TARGET_POWERPC64
24178 && info->first_gp_reg_save < 31
24179 && !(flag_shrink_wrap
24180 && flag_shrink_wrap_separate
24181 && optimize_function_for_speed_p (cfun)))
24184 for (int i = info->first_gp_reg_save; i < 32; i++)
24185 if (save_reg_p (i))
24189 /* Don't use store multiple if only one reg needs to be
24190 saved. This can occur for example when the ABI_V4 pic reg
24191 (r30) needs to be saved to make calls, but r31 is not
24193 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24196 /* Prefer store multiple for saves over out-of-line
24197 routines, since the store-multiple instruction will
24198 always be smaller. */
24199 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24201 /* The situation is more complicated with load multiple.
24202 We'd prefer to use the out-of-line routines for restores,
24203 since the "exit" out-of-line routines can handle the
24204 restore of LR and the frame teardown. However if doesn't
24205 make sense to use the out-of-line routine if that is the
24206 only reason we'd need to save LR, and we can't use the
24207 "exit" out-of-line gpr restore if we have saved some
24208 fprs; In those cases it is advantageous to use load
24209 multiple when available. */
24210 if (info->first_fp_reg_save != 64 || !lr_save_p)
24211 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24215 /* Using the "exit" out-of-line routine does not improve code size
24216 if using it would require lr to be saved and if only saving one
24218 else if (!lr_save_p && info->first_gp_reg_save > 29)
24219 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24221 /* Don't ever restore fixed regs. */
24222 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24223 for (int i = info->first_gp_reg_save; i < 32; i++)
24224 if (fixed_reg_p (i))
24226 strategy |= REST_INLINE_GPRS;
24227 strategy &= ~REST_MULTIPLE;
24231 /* We can only use load multiple or the out-of-line routines to
24232 restore gprs if we've saved all the registers from
24233 first_gp_reg_save. Otherwise, we risk loading garbage.
24234 Of course, if we have saved out-of-line or used stmw then we know
24235 we haven't skipped any gprs. */
24236 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24237 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24238 for (int i = info->first_gp_reg_save; i < 32; i++)
24239 if (!save_reg_p (i))
24241 strategy |= REST_INLINE_GPRS;
24242 strategy &= ~REST_MULTIPLE;
24246 if (TARGET_ELF && TARGET_64BIT)
24248 if (!(strategy & SAVE_INLINE_FPRS))
24249 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24250 else if (!(strategy & SAVE_INLINE_GPRS)
24251 && info->first_fp_reg_save == 64)
24252 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24254 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24255 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24257 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24258 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24263 /* Calculate the stack information for the current function. This is
24264 complicated by having two separate calling sequences, the AIX calling
24265 sequence and the V.4 calling sequence.
24267 AIX (and Darwin/Mac OS X) stack frames look like:
24269 SP----> +---------------------------------------+
24270 | back chain to caller | 0 0
24271 +---------------------------------------+
24272 | saved CR | 4 8 (8-11)
24273 +---------------------------------------+
24275 +---------------------------------------+
24276 | reserved for compilers | 12 24
24277 +---------------------------------------+
24278 | reserved for binders | 16 32
24279 +---------------------------------------+
24280 | saved TOC pointer | 20 40
24281 +---------------------------------------+
24282 | Parameter save area (+padding*) (P) | 24 48
24283 +---------------------------------------+
24284 | Alloca space (A) | 24+P etc.
24285 +---------------------------------------+
24286 | Local variable space (L) | 24+P+A
24287 +---------------------------------------+
24288 | Float/int conversion temporary (X) | 24+P+A+L
24289 +---------------------------------------+
24290 | Save area for AltiVec registers (W) | 24+P+A+L+X
24291 +---------------------------------------+
24292 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24293 +---------------------------------------+
24294 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24295 +---------------------------------------+
24296 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24297 +---------------------------------------+
24298 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24299 +---------------------------------------+
24300 old SP->| back chain to caller's caller |
24301 +---------------------------------------+
24303 * If the alloca area is present, the parameter save area is
24304 padded so that the former starts 16-byte aligned.
24306 The required alignment for AIX configurations is two words (i.e., 8
24309 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24311 SP----> +---------------------------------------+
24312 | Back chain to caller | 0
24313 +---------------------------------------+
24314 | Save area for CR | 8
24315 +---------------------------------------+
24317 +---------------------------------------+
24318 | Saved TOC pointer | 24
24319 +---------------------------------------+
24320 | Parameter save area (+padding*) (P) | 32
24321 +---------------------------------------+
24322 | Alloca space (A) | 32+P
24323 +---------------------------------------+
24324 | Local variable space (L) | 32+P+A
24325 +---------------------------------------+
24326 | Save area for AltiVec registers (W) | 32+P+A+L
24327 +---------------------------------------+
24328 | AltiVec alignment padding (Y) | 32+P+A+L+W
24329 +---------------------------------------+
24330 | Save area for GP registers (G) | 32+P+A+L+W+Y
24331 +---------------------------------------+
24332 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24333 +---------------------------------------+
24334 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24335 +---------------------------------------+
24337 * If the alloca area is present, the parameter save area is
24338 padded so that the former starts 16-byte aligned.
24340 V.4 stack frames look like:
24342 SP----> +---------------------------------------+
24343 | back chain to caller | 0
24344 +---------------------------------------+
24345 | caller's saved LR | 4
24346 +---------------------------------------+
24347 | Parameter save area (+padding*) (P) | 8
24348 +---------------------------------------+
24349 | Alloca space (A) | 8+P
24350 +---------------------------------------+
24351 | Varargs save area (V) | 8+P+A
24352 +---------------------------------------+
24353 | Local variable space (L) | 8+P+A+V
24354 +---------------------------------------+
24355 | Float/int conversion temporary (X) | 8+P+A+V+L
24356 +---------------------------------------+
24357 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24358 +---------------------------------------+
24359 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24360 +---------------------------------------+
24361 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24362 +---------------------------------------+
24363 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24364 +---------------------------------------+
24365 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24366 +---------------------------------------+
24367 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24368 +---------------------------------------+
24369 old SP->| back chain to caller's caller |
24370 +---------------------------------------+
24372 * If the alloca area is present and the required alignment is
24373 16 bytes, the parameter save area is padded so that the
24374 alloca area starts 16-byte aligned.
24376 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24377 given. (But note below and in sysv4.h that we require only 8 and
24378 may round up the size of our stack frame anyways. The historical
24379 reason is early versions of powerpc-linux which didn't properly
24380 align the stack at program startup. A happy side-effect is that
24381 -mno-eabi libraries can be used with -meabi programs.)
24383 The EABI configuration defaults to the V.4 layout. However,
24384 the stack alignment requirements may differ. If -mno-eabi is not
24385 given, the required stack alignment is 8 bytes; if -mno-eabi is
24386 given, the required alignment is 16 bytes. (But see V.4 comment
24389 #ifndef ABI_STACK_BOUNDARY
24390 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24393 static rs6000_stack_t *
24394 rs6000_stack_info (void)
24396 /* We should never be called for thunks, we are not set up for that. */
24397 gcc_assert (!cfun->is_thunk);
24399 rs6000_stack_t *info = &stack_info;
24400 int reg_size = TARGET_32BIT ? 4 : 8;
24405 HOST_WIDE_INT non_fixed_size;
24406 bool using_static_chain_p;
24408 if (reload_completed && info->reload_completed)
24411 memset (info, 0, sizeof (*info));
24412 info->reload_completed = reload_completed;
24414 /* Select which calling sequence. */
24415 info->abi = DEFAULT_ABI;
24417 /* Calculate which registers need to be saved & save area size. */
24418 info->first_gp_reg_save = first_reg_to_save ();
24419 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24420 even if it currently looks like we won't. Reload may need it to
24421 get at a constant; if so, it will have already created a constant
24422 pool entry for it. */
24423 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24424 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24425 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24426 && crtl->uses_const_pool
24427 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24428 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24430 first_gp = info->first_gp_reg_save;
24432 info->gp_size = reg_size * (32 - first_gp);
24434 info->first_fp_reg_save = first_fp_reg_to_save ();
24435 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24437 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24438 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24439 - info->first_altivec_reg_save);
24441 /* Does this function call anything? */
24442 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24444 /* Determine if we need to save the condition code registers. */
24445 if (save_reg_p (CR2_REGNO)
24446 || save_reg_p (CR3_REGNO)
24447 || save_reg_p (CR4_REGNO))
24449 info->cr_save_p = 1;
24450 if (DEFAULT_ABI == ABI_V4)
24451 info->cr_size = reg_size;
24454 /* If the current function calls __builtin_eh_return, then we need
24455 to allocate stack space for registers that will hold data for
24456 the exception handler. */
24457 if (crtl->calls_eh_return)
24460 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24463 ehrd_size = i * UNITS_PER_WORD;
24468 /* In the ELFv2 ABI, we also need to allocate space for separate
24469 CR field save areas if the function calls __builtin_eh_return. */
24470 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24472 /* This hard-codes that we have three call-saved CR fields. */
24473 ehcr_size = 3 * reg_size;
24474 /* We do *not* use the regular CR save mechanism. */
24475 info->cr_save_p = 0;
24480 /* Determine various sizes. */
24481 info->reg_size = reg_size;
24482 info->fixed_size = RS6000_SAVE_AREA;
24483 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24484 if (cfun->calls_alloca)
24486 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24487 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24489 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24490 TARGET_ALTIVEC ? 16 : 8);
24491 if (FRAME_GROWS_DOWNWARD)
24493 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24494 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24495 - (info->fixed_size + info->vars_size + info->parm_size);
24497 if (TARGET_ALTIVEC_ABI)
24498 info->vrsave_mask = compute_vrsave_mask ();
24500 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24501 info->vrsave_size = 4;
24503 compute_save_world_info (info);
24505 /* Calculate the offsets. */
24506 switch (DEFAULT_ABI)
24510 gcc_unreachable ();
24515 info->fp_save_offset = -info->fp_size;
24516 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24518 if (TARGET_ALTIVEC_ABI)
24520 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24522 /* Align stack so vector save area is on a quadword boundary.
24523 The padding goes above the vectors. */
24524 if (info->altivec_size != 0)
24525 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24527 info->altivec_save_offset = info->vrsave_save_offset
24528 - info->altivec_padding_size
24529 - info->altivec_size;
24530 gcc_assert (info->altivec_size == 0
24531 || info->altivec_save_offset % 16 == 0);
24533 /* Adjust for AltiVec case. */
24534 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24537 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24539 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24540 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24541 info->lr_save_offset = 2*reg_size;
24545 info->fp_save_offset = -info->fp_size;
24546 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24547 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24549 if (TARGET_ALTIVEC_ABI)
24551 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24553 /* Align stack so vector save area is on a quadword boundary. */
24554 if (info->altivec_size != 0)
24555 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24557 info->altivec_save_offset = info->vrsave_save_offset
24558 - info->altivec_padding_size
24559 - info->altivec_size;
24561 /* Adjust for AltiVec case. */
24562 info->ehrd_offset = info->altivec_save_offset;
24565 info->ehrd_offset = info->cr_save_offset;
24567 info->ehrd_offset -= ehrd_size;
24568 info->lr_save_offset = reg_size;
24571 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24572 info->save_size = RS6000_ALIGN (info->fp_size
24574 + info->altivec_size
24575 + info->altivec_padding_size
24579 + info->vrsave_size,
24582 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24584 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24585 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24587 /* Determine if we need to save the link register. */
24589 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24591 && !TARGET_PROFILE_KERNEL)
24592 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24593 #ifdef TARGET_RELOCATABLE
24594 || (DEFAULT_ABI == ABI_V4
24595 && (TARGET_RELOCATABLE || flag_pic > 1)
24596 && !constant_pool_empty_p ())
24598 || rs6000_ra_ever_killed ())
24599 info->lr_save_p = 1;
24601 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24602 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24603 && call_used_regs[STATIC_CHAIN_REGNUM]);
24604 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24606 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24607 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24608 || !(info->savres_strategy & SAVE_INLINE_VRS)
24609 || !(info->savres_strategy & REST_INLINE_GPRS)
24610 || !(info->savres_strategy & REST_INLINE_FPRS)
24611 || !(info->savres_strategy & REST_INLINE_VRS))
24612 info->lr_save_p = 1;
24614 if (info->lr_save_p)
24615 df_set_regs_ever_live (LR_REGNO, true);
24617 /* Determine if we need to allocate any stack frame:
24619 For AIX we need to push the stack if a frame pointer is needed
24620 (because the stack might be dynamically adjusted), if we are
24621 debugging, if we make calls, or if the sum of fp_save, gp_save,
24622 and local variables are more than the space needed to save all
24623 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24624 + 18*8 = 288 (GPR13 reserved).
24626 For V.4 we don't have the stack cushion that AIX uses, but assume
24627 that the debugger can handle stackless frames. */
24632 else if (DEFAULT_ABI == ABI_V4)
24633 info->push_p = non_fixed_size != 0;
24635 else if (frame_pointer_needed)
24638 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24642 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24648 debug_stack_info (rs6000_stack_t *info)
24650 const char *abi_string;
24653 info = rs6000_stack_info ();
24655 fprintf (stderr, "\nStack information for function %s:\n",
24656 ((current_function_decl && DECL_NAME (current_function_decl))
24657 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24662 default: abi_string = "Unknown"; break;
24663 case ABI_NONE: abi_string = "NONE"; break;
24664 case ABI_AIX: abi_string = "AIX"; break;
24665 case ABI_ELFv2: abi_string = "ELFv2"; break;
24666 case ABI_DARWIN: abi_string = "Darwin"; break;
24667 case ABI_V4: abi_string = "V.4"; break;
24670 fprintf (stderr, "\tABI = %5s\n", abi_string);
24672 if (TARGET_ALTIVEC_ABI)
24673 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24675 if (info->first_gp_reg_save != 32)
24676 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24678 if (info->first_fp_reg_save != 64)
24679 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24681 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24682 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24683 info->first_altivec_reg_save);
24685 if (info->lr_save_p)
24686 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24688 if (info->cr_save_p)
24689 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24691 if (info->vrsave_mask)
24692 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24695 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24698 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24701 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24704 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24706 if (info->altivec_size)
24707 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24708 info->altivec_save_offset);
24710 if (info->vrsave_size)
24711 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24712 info->vrsave_save_offset);
24714 if (info->lr_save_p)
24715 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24717 if (info->cr_save_p)
24718 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24720 if (info->varargs_save_offset)
24721 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24723 if (info->total_size)
24724 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24727 if (info->vars_size)
24728 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24731 if (info->parm_size)
24732 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24734 if (info->fixed_size)
24735 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24738 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24741 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24743 if (info->altivec_size)
24744 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24746 if (info->vrsave_size)
24747 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24749 if (info->altivec_padding_size)
24750 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24751 info->altivec_padding_size);
24754 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24756 if (info->save_size)
24757 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24759 if (info->reg_size != 4)
24760 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24762 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24764 if (info->abi == ABI_DARWIN)
24765 fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
24767 fprintf (stderr, "\n");
24771 rs6000_return_addr (int count, rtx frame)
24773 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24774 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24776 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24778 cfun->machine->ra_needs_full_frame = 1;
24781 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24782 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24783 frame = stack_pointer_rtx;
24784 rtx prev_frame_addr = memory_address (Pmode, frame);
24785 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24786 rtx lr_save_off = plus_constant (Pmode,
24787 prev_frame, RETURN_ADDRESS_OFFSET);
24788 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24789 return gen_rtx_MEM (Pmode, lr_save_addr);
24792 cfun->machine->ra_need_lr = 1;
24793 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24796 /* Helper function for rs6000_function_ok_for_sibcall. */
24799 rs6000_decl_ok_for_sibcall (tree decl)
24801 /* Sibcalls are always fine for the Darwin ABI. */
24802 if (DEFAULT_ABI == ABI_DARWIN)
24805 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24807 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24808 functions, because the callee may have a different TOC pointer to
24809 the caller and there's no way to ensure we restore the TOC when
24811 if (!decl || DECL_EXTERNAL (decl) || DECL_WEAK (decl)
24812 || !(*targetm.binds_local_p) (decl))
24815 /* Similarly, if the caller preserves the TOC pointer and the callee
24816 doesn't (or vice versa), proper TOC setup or restoration will be
24817 missed. For example, suppose A, B, and C are in the same binary
24818 and A -> B -> C. A and B preserve the TOC pointer but C does not,
24819 and B -> C is eligible as a sibcall. A will call B through its
24820 local entry point, so A will not restore its TOC itself. B calls
24821 C with a sibcall, so it will not restore the TOC. C does not
24822 preserve the TOC, so it may clobber r2 with impunity. Returning
24823 from C will result in a corrupted TOC for A. */
24824 else if (rs6000_fndecl_pcrel_p (decl) != rs6000_pcrel_p (cfun))
24831 /* With the secure-plt SYSV ABI we can't make non-local calls when
24832 -fpic/PIC because the plt call stubs use r30. */
24833 if (DEFAULT_ABI != ABI_V4
24834 || (TARGET_SECURE_PLT
24836 && (!decl || !((*targetm.binds_local_p) (decl)))))
24842 /* Say whether a function is a candidate for sibcall handling or not. */
24845 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24849 /* The sibcall epilogue may clobber the static chain register.
24850 ??? We could work harder and avoid that, but it's probably
24851 not worth the hassle in practice. */
24852 if (CALL_EXPR_STATIC_CHAIN (exp))
24856 fntype = TREE_TYPE (decl);
24858 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24860 /* We can't do it if the called function has more vector parameters
24861 than the current function; there's nowhere to put the VRsave code. */
24862 if (TARGET_ALTIVEC_ABI
24863 && TARGET_ALTIVEC_VRSAVE
24864 && !(decl && decl == current_function_decl))
24866 function_args_iterator args_iter;
24870 /* Functions with vector parameters are required to have a
24871 prototype, so the argument type info must be available
24873 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24874 if (TREE_CODE (type) == VECTOR_TYPE
24875 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24878 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24879 if (TREE_CODE (type) == VECTOR_TYPE
24880 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24887 if (rs6000_decl_ok_for_sibcall (decl))
24889 tree attr_list = TYPE_ATTRIBUTES (fntype);
24891 if (!lookup_attribute ("longcall", attr_list)
24892 || lookup_attribute ("shortcall", attr_list))
24900 rs6000_ra_ever_killed (void)
24906 if (cfun->is_thunk)
24909 if (cfun->machine->lr_save_state)
24910 return cfun->machine->lr_save_state - 1;
24912 /* regs_ever_live has LR marked as used if any sibcalls are present,
24913 but this should not force saving and restoring in the
24914 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24915 clobbers LR, so that is inappropriate. */
24917 /* Also, the prologue can generate a store into LR that
24918 doesn't really count, like this:
24921 bcl to set PIC register
24925 When we're called from the epilogue, we need to avoid counting
24926 this as a store. */
24928 push_topmost_sequence ();
24929 top = get_insns ();
24930 pop_topmost_sequence ();
24931 reg = gen_rtx_REG (Pmode, LR_REGNO);
24933 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24939 if (!SIBLING_CALL_P (insn))
24942 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24944 else if (set_of (reg, insn) != NULL_RTX
24945 && !prologue_epilogue_contains (insn))
24952 /* Emit instructions needed to load the TOC register.
24953 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24954 a constant pool; or for SVR4 -fpic. */
24957 rs6000_emit_load_toc_table (int fromprolog)
24960 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24962 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24965 rtx lab, tmp1, tmp2, got;
24967 lab = gen_label_rtx ();
24968 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24969 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24972 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24976 got = rs6000_got_sym ();
24977 tmp1 = tmp2 = dest;
24980 tmp1 = gen_reg_rtx (Pmode);
24981 tmp2 = gen_reg_rtx (Pmode);
24983 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24984 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24985 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24986 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24988 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24990 emit_insn (gen_load_toc_v4_pic_si ());
24991 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24993 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24996 rtx temp0 = (fromprolog
24997 ? gen_rtx_REG (Pmode, 0)
24998 : gen_reg_rtx (Pmode));
25004 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25005 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25007 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25008 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25010 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25011 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25012 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25018 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25020 lab = gen_label_rtx ();
25021 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25022 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25023 if (TARGET_LINK_STACK)
25024 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25025 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25027 emit_insn (gen_addsi3 (dest, temp0, dest));
25029 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25031 /* This is for AIX code running in non-PIC ELF32. */
25032 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25035 emit_insn (gen_elf_high (dest, realsym));
25036 emit_insn (gen_elf_low (dest, dest, realsym));
25040 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25043 emit_insn (gen_load_toc_aix_si (dest));
25045 emit_insn (gen_load_toc_aix_di (dest));
25049 /* Emit instructions to restore the link register after determining where
25050 its value has been stored. */
25053 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25055 rs6000_stack_t *info = rs6000_stack_info ();
25058 operands[0] = source;
25059 operands[1] = scratch;
25061 if (info->lr_save_p)
25063 rtx frame_rtx = stack_pointer_rtx;
25064 HOST_WIDE_INT sp_offset = 0;
25067 if (frame_pointer_needed
25068 || cfun->calls_alloca
25069 || info->total_size > 32767)
25071 tmp = gen_frame_mem (Pmode, frame_rtx);
25072 emit_move_insn (operands[1], tmp);
25073 frame_rtx = operands[1];
25075 else if (info->push_p)
25076 sp_offset = info->total_size;
25078 tmp = plus_constant (Pmode, frame_rtx,
25079 info->lr_save_offset + sp_offset);
25080 tmp = gen_frame_mem (Pmode, tmp);
25081 emit_move_insn (tmp, operands[0]);
25084 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25086 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25087 state of lr_save_p so any change from here on would be a bug. In
25088 particular, stop rs6000_ra_ever_killed from considering the SET
25089 of lr we may have added just above. */
25090 cfun->machine->lr_save_state = info->lr_save_p + 1;
25093 static GTY(()) alias_set_type set = -1;
25096 get_TOC_alias_set (void)
25099 set = new_alias_set ();
25103 /* This returns nonzero if the current function uses the TOC. This is
25104 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25105 is generated by the ABI_V4 load_toc_* patterns.
25106 Return 2 instead of 1 if the load_toc_* pattern is in the function
25107 partition that doesn't start the function. */
25115 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25119 rtx pat = PATTERN (insn);
25122 if (GET_CODE (pat) == PARALLEL)
25123 for (i = 0; i < XVECLEN (pat, 0); i++)
25125 rtx sub = XVECEXP (pat, 0, i);
25126 if (GET_CODE (sub) == USE)
25128 sub = XEXP (sub, 0);
25129 if (GET_CODE (sub) == UNSPEC
25130 && XINT (sub, 1) == UNSPEC_TOC)
25135 else if (crtl->has_bb_partition
25137 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25145 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25147 rtx tocrel, tocreg, hi;
25149 if (TARGET_DEBUG_ADDR)
25151 if (SYMBOL_REF_P (symbol))
25152 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25156 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25157 GET_RTX_NAME (GET_CODE (symbol)));
25158 debug_rtx (symbol);
25162 if (!can_create_pseudo_p ())
25163 df_set_regs_ever_live (TOC_REGISTER, true);
25165 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25166 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25167 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25170 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25171 if (largetoc_reg != NULL)
25173 emit_move_insn (largetoc_reg, hi);
25176 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25179 /* Issue assembly directives that create a reference to the given DWARF
25180 FRAME_TABLE_LABEL from the current function section. */
25182 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25184 fprintf (asm_out_file, "\t.ref %s\n",
25185 (* targetm.strip_name_encoding) (frame_table_label));
25188 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25189 and the change to the stack pointer. */
25192 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25199 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25200 if (hard_frame_needed)
25201 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25202 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25203 || (hard_frame_needed
25204 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25207 p = rtvec_alloc (i);
25210 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25211 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25214 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25217 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25218 and set the appropriate attributes for the generated insn. Return the
25219 first insn which adjusts the stack pointer or the last insn before
25220 the stack adjustment loop.
25222 SIZE_INT is used to create the CFI note for the allocation.
25224 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25225 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25227 ORIG_SP contains the backchain value that must be stored at *sp. */
25230 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25234 rtx size_rtx = GEN_INT (-size_int);
25235 if (size_int > 32767)
25237 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25238 /* Need a note here so that try_split doesn't get confused. */
25239 if (get_last_insn () == NULL_RTX)
25240 emit_note (NOTE_INSN_DELETED);
25241 insn = emit_move_insn (tmp_reg, size_rtx);
25242 try_split (PATTERN (insn), insn, 0);
25243 size_rtx = tmp_reg;
25247 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25252 insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
25256 rtx par = PATTERN (insn);
25257 gcc_assert (GET_CODE (par) == PARALLEL);
25258 rtx set = XVECEXP (par, 0, 0);
25259 gcc_assert (GET_CODE (set) == SET);
25260 rtx mem = SET_DEST (set);
25261 gcc_assert (MEM_P (mem));
25262 MEM_NOTRAP_P (mem) = 1;
25263 set_mem_alias_set (mem, get_frame_alias_set ());
25265 RTX_FRAME_RELATED_P (insn) = 1;
25266 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25267 gen_rtx_SET (stack_pointer_rtx,
25268 gen_rtx_PLUS (Pmode,
25270 GEN_INT (-size_int))));
25272 /* Emit a blockage to ensure the allocation/probing insns are
25273 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25274 note for similar reasons. */
25275 if (flag_stack_clash_protection)
25277 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25278 emit_insn (gen_blockage ());
25284 static HOST_WIDE_INT
25285 get_stack_clash_protection_probe_interval (void)
25287 return (HOST_WIDE_INT_1U
25288 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25291 static HOST_WIDE_INT
25292 get_stack_clash_protection_guard_size (void)
25294 return (HOST_WIDE_INT_1U
25295 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25298 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25299 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25301 COPY_REG, if non-null, should contain a copy of the original
25302 stack pointer at exit from this function.
25304 This is subtly different than the Ada probing in that it tries hard to
25305 prevent attacks that jump the stack guard. Thus it is never allowed to
25306 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25307 space without a suitable probe. */
25309 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25312 rtx orig_sp = copy_reg;
25314 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25316 /* Round the size down to a multiple of PROBE_INTERVAL. */
25317 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25319 /* If explicitly requested,
25320 or the rounded size is not the same as the original size
25321 or the the rounded size is greater than a page,
25322 then we will need a copy of the original stack pointer. */
25323 if (rounded_size != orig_size
25324 || rounded_size > probe_interval
25327 /* If the caller did not request a copy of the incoming stack
25328 pointer, then we use r0 to hold the copy. */
25330 orig_sp = gen_rtx_REG (Pmode, 0);
25331 emit_move_insn (orig_sp, stack_pointer_rtx);
25334 /* There's three cases here.
25336 One is a single probe which is the most common and most efficiently
25337 implemented as it does not have to have a copy of the original
25338 stack pointer if there are no residuals.
25340 Second is unrolled allocation/probes which we use if there's just
25341 a few of them. It needs to save the original stack pointer into a
25342 temporary for use as a source register in the allocation/probe.
25344 Last is a loop. This is the most uncommon case and least efficient. */
25345 rtx_insn *retval = NULL;
25346 if (rounded_size == probe_interval)
25348 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25350 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25352 else if (rounded_size <= 8 * probe_interval)
25354 /* The ABI requires using the store with update insns to allocate
25355 space and store the backchain into the stack
25357 So we save the current stack pointer into a temporary, then
25358 emit the store-with-update insns to store the saved stack pointer
25359 into the right location in each new page. */
25360 for (int i = 0; i < rounded_size; i += probe_interval)
25363 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25365 /* Save the first stack adjustment in RETVAL. */
25370 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25374 /* Compute the ending address. */
25376 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25377 rtx rs = GEN_INT (-rounded_size);
25379 if (add_operand (rs, Pmode))
25380 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25383 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25384 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25385 stack_pointer_rtx));
25386 /* Describe the effect of INSN to the CFI engine. */
25387 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25388 gen_rtx_SET (end_addr,
25389 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25392 RTX_FRAME_RELATED_P (insn) = 1;
25394 /* Emit the loop. */
25396 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25397 stack_pointer_rtx, orig_sp,
25400 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25401 stack_pointer_rtx, orig_sp,
25403 RTX_FRAME_RELATED_P (retval) = 1;
25404 /* Describe the effect of INSN to the CFI engine. */
25405 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25406 gen_rtx_SET (stack_pointer_rtx, end_addr));
25408 /* Emit a blockage to ensure the allocation/probing insns are
25409 not optimized, combined, removed, etc. Other cases handle this
25410 within their call to rs6000_emit_allocate_stack_1. */
25411 emit_insn (gen_blockage ());
25413 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25416 if (orig_size != rounded_size)
25418 /* Allocate (and implicitly probe) any residual space. */
25419 HOST_WIDE_INT residual = orig_size - rounded_size;
25421 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25423 /* If the residual was the only allocation, then we can return the
25424 allocating insn. */
25432 /* Emit the correct code for allocating stack space, as insns.
25433 If COPY_REG, make sure a copy of the old frame is left there.
25434 The generated code may use hard register 0 as a temporary. */
25437 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25440 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25441 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25442 rtx todec = gen_int_mode (-size, Pmode);
25444 if (INTVAL (todec) != -size)
25446 warning (0, "stack frame too large");
25447 emit_insn (gen_trap ());
25451 if (crtl->limit_stack)
25453 if (REG_P (stack_limit_rtx)
25454 && REGNO (stack_limit_rtx) > 1
25455 && REGNO (stack_limit_rtx) <= 31)
25458 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25461 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25463 else if (SYMBOL_REF_P (stack_limit_rtx)
25465 && DEFAULT_ABI == ABI_V4
25468 rtx toload = gen_rtx_CONST (VOIDmode,
25469 gen_rtx_PLUS (Pmode,
25473 emit_insn (gen_elf_high (tmp_reg, toload));
25474 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25475 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25479 warning (0, "stack limit expression is not supported");
25482 if (flag_stack_clash_protection)
25484 if (size < get_stack_clash_protection_guard_size ())
25485 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25488 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25491 /* If we asked for a copy with an offset, then we still need add in
25493 if (copy_reg && copy_off)
25494 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25502 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25504 emit_move_insn (copy_reg, stack_reg);
25507 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25508 it now and set the alias set/attributes. The above gen_*_update
25509 calls will generate a PARALLEL with the MEM set being the first
25511 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25515 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25517 #if PROBE_INTERVAL > 32768
25518 #error Cannot use indexed addressing mode for stack probing
25521 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25522 inclusive. These are offsets from the current stack pointer. */
25525 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25527 /* See if we have a constant small number of probes to generate. If so,
25528 that's the easy case. */
25529 if (first + size <= 32768)
25533 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25534 it exceeds SIZE. If only one probe is needed, this will not
25535 generate any code. Then probe at FIRST + SIZE. */
25536 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25537 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25540 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25544 /* Otherwise, do the same as above, but in a loop. Note that we must be
25545 extra careful with variables wrapping around because we might be at
25546 the very top (or the very bottom) of the address space and we have
25547 to be able to handle this case properly; in particular, we use an
25548 equality test for the loop condition. */
25551 HOST_WIDE_INT rounded_size;
25552 rtx r12 = gen_rtx_REG (Pmode, 12);
25553 rtx r0 = gen_rtx_REG (Pmode, 0);
25555 /* Sanity check for the addressing mode we're going to use. */
25556 gcc_assert (first <= 32768);
25558 /* Step 1: round SIZE to the previous multiple of the interval. */
25560 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25563 /* Step 2: compute initial and final value of the loop counter. */
25565 /* TEST_ADDR = SP + FIRST. */
25566 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25569 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25570 if (rounded_size > 32768)
25572 emit_move_insn (r0, GEN_INT (-rounded_size));
25573 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25576 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25580 /* Step 3: the loop
25584 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25587 while (TEST_ADDR != LAST_ADDR)
25589 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25590 until it is equal to ROUNDED_SIZE. */
25593 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25595 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25598 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25599 that SIZE is equal to ROUNDED_SIZE. */
25601 if (size != rounded_size)
25602 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25606 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25607 addresses, not offsets. */
25609 static const char *
25610 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25612 static int labelno = 0;
25616 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25619 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25621 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25623 xops[1] = GEN_INT (-PROBE_INTERVAL);
25624 output_asm_insn ("addi %0,%0,%1", xops);
25626 /* Probe at TEST_ADDR. */
25627 xops[1] = gen_rtx_REG (Pmode, 0);
25628 output_asm_insn ("stw %1,0(%0)", xops);
25630 /* Test if TEST_ADDR == LAST_ADDR. */
25633 output_asm_insn ("cmpd 0,%0,%1", xops);
25635 output_asm_insn ("cmpw 0,%0,%1", xops);
25638 fputs ("\tbne 0,", asm_out_file);
25639 assemble_name_raw (asm_out_file, loop_lab);
25640 fputc ('\n', asm_out_file);
25645 /* This function is called when rs6000_frame_related is processing
25646 SETs within a PARALLEL, and returns whether the REGNO save ought to
25647 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25648 for out-of-line register save functions, store multiple, and the
25649 Darwin world_save. They may contain registers that don't really
25653 interesting_frame_related_regno (unsigned int regno)
25655 /* Saves apparently of r0 are actually saving LR. It doesn't make
25656 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25657 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25658 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25659 as frame related. */
25662 /* If we see CR2 then we are here on a Darwin world save. Saves of
25663 CR2 signify the whole CR is being saved. This is a long-standing
25664 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25665 that CR needs to be saved. */
25666 if (regno == CR2_REGNO)
25668 /* Omit frame info for any user-defined global regs. If frame info
25669 is supplied for them, frame unwinding will restore a user reg.
25670 Also omit frame info for any reg we don't need to save, as that
25671 bloats frame info and can cause problems with shrink wrapping.
25672 Since global regs won't be seen as needing to be saved, both of
25673 these conditions are covered by save_reg_p. */
25674 return save_reg_p (regno);
25677 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25678 addresses, not offsets.
25680 REG2 contains the backchain that must be stored into *sp at each allocation.
25682 This is subtly different than the Ada probing above in that it tries hard
25683 to prevent attacks that jump the stack guard. Thus, it is never allowed
25684 to allocate more than PROBE_INTERVAL bytes of stack space without a
25687 static const char *
25688 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25690 static int labelno = 0;
25694 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25696 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25698 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25700 /* This allocates and probes. */
25703 xops[2] = GEN_INT (-probe_interval);
25705 output_asm_insn ("stdu %1,%2(%0)", xops);
25707 output_asm_insn ("stwu %1,%2(%0)", xops);
25709 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25713 output_asm_insn ("cmpd 0,%0,%1", xops);
25715 output_asm_insn ("cmpw 0,%0,%1", xops);
25717 fputs ("\tbne 0,", asm_out_file);
25718 assemble_name_raw (asm_out_file, loop_lab);
25719 fputc ('\n', asm_out_file);
25724 /* Wrapper around the output_probe_stack_range routines. */
25726 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25728 if (flag_stack_clash_protection)
25729 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25731 return output_probe_stack_range_1 (reg1, reg3);
25734 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25735 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25736 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25737 deduce these equivalences by itself so it wasn't necessary to hold
25738 its hand so much. Don't be tempted to always supply d2_f_d_e with
25739 the actual cfa register, ie. r31 when we are using a hard frame
25740 pointer. That fails when saving regs off r1, and sched moves the
25741 r31 setup past the reg saves. */
25744 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25745 rtx reg2, rtx repl2)
25749 if (REGNO (reg) == STACK_POINTER_REGNUM)
25751 gcc_checking_assert (val == 0);
25755 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25758 rtx pat = PATTERN (insn);
25759 if (!repl && !reg2)
25761 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25762 if (GET_CODE (pat) == PARALLEL)
25763 for (int i = 0; i < XVECLEN (pat, 0); i++)
25764 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25766 rtx set = XVECEXP (pat, 0, i);
25768 if (!REG_P (SET_SRC (set))
25769 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25770 RTX_FRAME_RELATED_P (set) = 1;
25772 RTX_FRAME_RELATED_P (insn) = 1;
25776 /* We expect that 'pat' is either a SET or a PARALLEL containing
25777 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25778 are important so they all have to be marked RTX_FRAME_RELATED_P.
25779 Call simplify_replace_rtx on the SETs rather than the whole insn
25780 so as to leave the other stuff alone (for example USE of r12). */
25782 set_used_flags (pat);
25783 if (GET_CODE (pat) == SET)
25786 pat = simplify_replace_rtx (pat, reg, repl);
25788 pat = simplify_replace_rtx (pat, reg2, repl2);
25790 else if (GET_CODE (pat) == PARALLEL)
25792 pat = shallow_copy_rtx (pat);
25793 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25795 for (int i = 0; i < XVECLEN (pat, 0); i++)
25796 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25798 rtx set = XVECEXP (pat, 0, i);
25801 set = simplify_replace_rtx (set, reg, repl);
25803 set = simplify_replace_rtx (set, reg2, repl2);
25804 XVECEXP (pat, 0, i) = set;
25806 if (!REG_P (SET_SRC (set))
25807 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25808 RTX_FRAME_RELATED_P (set) = 1;
25812 gcc_unreachable ();
25814 RTX_FRAME_RELATED_P (insn) = 1;
25815 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25820 /* Returns an insn that has a vrsave set operation with the
25821 appropriate CLOBBERs. */
25824 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25827 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25828 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25831 = gen_rtx_SET (vrsave,
25832 gen_rtx_UNSPEC_VOLATILE (SImode,
25833 gen_rtvec (2, reg, vrsave),
25834 UNSPECV_SET_VRSAVE));
25838 /* We need to clobber the registers in the mask so the scheduler
25839 does not move sets to VRSAVE before sets of AltiVec registers.
25841 However, if the function receives nonlocal gotos, reload will set
25842 all call saved registers live. We will end up with:
25844 (set (reg 999) (mem))
25845 (parallel [ (set (reg vrsave) (unspec blah))
25846 (clobber (reg 999))])
25848 The clobber will cause the store into reg 999 to be dead, and
25849 flow will attempt to delete an epilogue insn. In this case, we
25850 need an unspec use/set of the register. */
25852 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25853 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25855 if (!epiloguep || call_used_regs [i])
25856 clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
25859 rtx reg = gen_rtx_REG (V4SImode, i);
25862 = gen_rtx_SET (reg,
25863 gen_rtx_UNSPEC (V4SImode,
25864 gen_rtvec (1, reg), 27));
25868 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25870 for (i = 0; i < nclobs; ++i)
25871 XVECEXP (insn, 0, i) = clobs[i];
25877 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25881 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25882 mem = gen_frame_mem (GET_MODE (reg), addr);
25883 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25887 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25889 return gen_frame_set (reg, frame_reg, offset, false);
25893 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25895 return gen_frame_set (reg, frame_reg, offset, true);
25898 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25899 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25902 emit_frame_save (rtx frame_reg, machine_mode mode,
25903 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25907 /* Some cases that need register indexed addressing. */
25908 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25909 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25911 reg = gen_rtx_REG (mode, regno);
25912 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25913 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25914 NULL_RTX, NULL_RTX);
25917 /* Emit an offset memory reference suitable for a frame store, while
25918 converting to a valid addressing mode. */
25921 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25923 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25926 #ifndef TARGET_FIX_AND_CONTINUE
25927 #define TARGET_FIX_AND_CONTINUE 0
25930 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25931 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25932 #define LAST_SAVRES_REGISTER 31
25933 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25944 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25946 /* Temporary holding space for an out-of-line register save/restore
25948 static char savres_routine_name[30];
25950 /* Return the name for an out-of-line register save/restore routine.
25951 We are saving/restoring GPRs if GPR is true. */
25954 rs6000_savres_routine_name (int regno, int sel)
25956 const char *prefix = "";
25957 const char *suffix = "";
25959 /* Different targets are supposed to define
25960 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25961 routine name could be defined with:
25963 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25965 This is a nice idea in practice, but in reality, things are
25966 complicated in several ways:
25968 - ELF targets have save/restore routines for GPRs.
25970 - PPC64 ELF targets have routines for save/restore of GPRs that
25971 differ in what they do with the link register, so having a set
25972 prefix doesn't work. (We only use one of the save routines at
25973 the moment, though.)
25975 - PPC32 elf targets have "exit" versions of the restore routines
25976 that restore the link register and can save some extra space.
25977 These require an extra suffix. (There are also "tail" versions
25978 of the restore routines and "GOT" versions of the save routines,
25979 but we don't generate those at present. Same problems apply,
25982 We deal with all this by synthesizing our own prefix/suffix and
25983 using that for the simple sprintf call shown above. */
25984 if (DEFAULT_ABI == ABI_V4)
25989 if ((sel & SAVRES_REG) == SAVRES_GPR)
25990 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25991 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25992 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25993 else if ((sel & SAVRES_REG) == SAVRES_VR)
25994 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25998 if ((sel & SAVRES_LR))
26001 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26003 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26004 /* No out-of-line save/restore routines for GPRs on AIX. */
26005 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26009 if ((sel & SAVRES_REG) == SAVRES_GPR)
26010 prefix = ((sel & SAVRES_SAVE)
26011 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26012 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26013 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26015 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26016 if ((sel & SAVRES_LR))
26017 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26021 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26022 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26025 else if ((sel & SAVRES_REG) == SAVRES_VR)
26026 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26031 if (DEFAULT_ABI == ABI_DARWIN)
26033 /* The Darwin approach is (slightly) different, in order to be
26034 compatible with code generated by the system toolchain. There is a
26035 single symbol for the start of save sequence, and the code here
26036 embeds an offset into that code on the basis of the first register
26038 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26039 if ((sel & SAVRES_REG) == SAVRES_GPR)
26040 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26041 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26042 (regno - 13) * 4, prefix, regno);
26043 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26044 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26045 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26046 else if ((sel & SAVRES_REG) == SAVRES_VR)
26047 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26048 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26053 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26055 return savres_routine_name;
26058 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26059 We are saving/restoring GPRs if GPR is true. */
26062 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26064 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26065 ? info->first_gp_reg_save
26066 : (sel & SAVRES_REG) == SAVRES_FPR
26067 ? info->first_fp_reg_save - 32
26068 : (sel & SAVRES_REG) == SAVRES_VR
26069 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26074 /* Don't generate bogus routine names. */
26075 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26076 && regno <= LAST_SAVRES_REGISTER
26077 && select >= 0 && select <= 12);
26079 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26085 name = rs6000_savres_routine_name (regno, sel);
26087 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26088 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26089 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26095 /* Emit a sequence of insns, including a stack tie if needed, for
26096 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26097 reset the stack pointer, but move the base of the frame into
26098 reg UPDT_REGNO for use by out-of-line register restore routines. */
26101 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26102 unsigned updt_regno)
26104 /* If there is nothing to do, don't do anything. */
26105 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26108 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26110 /* This blockage is needed so that sched doesn't decide to move
26111 the sp change before the register restores. */
26112 if (DEFAULT_ABI == ABI_V4)
26113 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26114 GEN_INT (frame_off)));
26116 /* If we are restoring registers out-of-line, we will be using the
26117 "exit" variants of the restore routines, which will reset the
26118 stack for us. But we do need to point updt_reg into the
26119 right place for those routines. */
26120 if (frame_off != 0)
26121 return emit_insn (gen_add3_insn (updt_reg_rtx,
26122 frame_reg_rtx, GEN_INT (frame_off)));
26124 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26129 /* Return the register number used as a pointer by out-of-line
26130 save/restore functions. */
26132 static inline unsigned
26133 ptr_regno_for_savres (int sel)
26135 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26136 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26137 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26140 /* Construct a parallel rtx describing the effect of a call to an
26141 out-of-line register save/restore routine, and emit the insn
26142 or jump_insn as appropriate. */
26145 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26146 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26147 machine_mode reg_mode, int sel)
26150 int offset, start_reg, end_reg, n_regs, use_reg;
26151 int reg_size = GET_MODE_SIZE (reg_mode);
26158 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26159 ? info->first_gp_reg_save
26160 : (sel & SAVRES_REG) == SAVRES_FPR
26161 ? info->first_fp_reg_save
26162 : (sel & SAVRES_REG) == SAVRES_VR
26163 ? info->first_altivec_reg_save
26165 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26167 : (sel & SAVRES_REG) == SAVRES_FPR
26169 : (sel & SAVRES_REG) == SAVRES_VR
26170 ? LAST_ALTIVEC_REGNO + 1
26172 n_regs = end_reg - start_reg;
26173 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26174 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26177 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26178 RTVEC_ELT (p, offset++) = ret_rtx;
26180 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
26182 sym = rs6000_savres_routine_sym (info, sel);
26183 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26185 use_reg = ptr_regno_for_savres (sel);
26186 if ((sel & SAVRES_REG) == SAVRES_VR)
26188 /* Vector regs are saved/restored using [reg+reg] addressing. */
26189 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
26190 RTVEC_ELT (p, offset++)
26191 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26194 RTVEC_ELT (p, offset++)
26195 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26197 for (i = 0; i < end_reg - start_reg; i++)
26198 RTVEC_ELT (p, i + offset)
26199 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26200 frame_reg_rtx, save_area_offset + reg_size * i,
26201 (sel & SAVRES_SAVE) != 0);
26203 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26204 RTVEC_ELT (p, i + offset)
26205 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26207 par = gen_rtx_PARALLEL (VOIDmode, p);
26209 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26211 insn = emit_jump_insn (par);
26212 JUMP_LABEL (insn) = ret_rtx;
26215 insn = emit_insn (par);
26219 /* Emit prologue code to store CR fields that need to be saved into REG. This
26220 function should only be called when moving the non-volatile CRs to REG, it
26221 is not a general purpose routine to move the entire set of CRs to REG.
26222 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26226 rs6000_emit_prologue_move_from_cr (rtx reg)
26228 /* Only the ELFv2 ABI allows storing only selected fields. */
26229 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26231 int i, cr_reg[8], count = 0;
26233 /* Collect CR fields that must be saved. */
26234 for (i = 0; i < 8; i++)
26235 if (save_reg_p (CR0_REGNO + i))
26236 cr_reg[count++] = i;
26238 /* If it's just a single one, use mfcrf. */
26241 rtvec p = rtvec_alloc (1);
26242 rtvec r = rtvec_alloc (2);
26243 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26244 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26246 = gen_rtx_SET (reg,
26247 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26249 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26253 /* ??? It might be better to handle count == 2 / 3 cases here
26254 as well, using logical operations to combine the values. */
26257 emit_insn (gen_prologue_movesi_from_cr (reg));
26260 /* Return whether the split-stack arg pointer (r12) is used. */
26263 split_stack_arg_pointer_used_p (void)
26265 /* If the pseudo holding the arg pointer is no longer a pseudo,
26266 then the arg pointer is used. */
26267 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26268 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26269 || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
26272 /* Unfortunately we also need to do some code scanning, since
26273 r12 may have been substituted for the pseudo. */
26275 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26276 FOR_BB_INSNS (bb, insn)
26277 if (NONDEBUG_INSN_P (insn))
26279 /* A call destroys r12. */
26284 FOR_EACH_INSN_USE (use, insn)
26286 rtx x = DF_REF_REG (use);
26287 if (REG_P (x) && REGNO (x) == 12)
26291 FOR_EACH_INSN_DEF (def, insn)
26293 rtx x = DF_REF_REG (def);
26294 if (REG_P (x) && REGNO (x) == 12)
26298 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26301 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26304 rs6000_global_entry_point_prologue_needed_p (void)
26306 /* Only needed for the ELFv2 ABI. */
26307 if (DEFAULT_ABI != ABI_ELFv2)
26310 /* With -msingle-pic-base, we assume the whole program shares the same
26311 TOC, so no global entry point prologues are needed anywhere. */
26312 if (TARGET_SINGLE_PIC_BASE)
26315 /* PC-relative functions never generate a global entry point prologue. */
26316 if (rs6000_pcrel_p (cfun))
26319 /* Ensure we have a global entry point for thunks. ??? We could
26320 avoid that if the target routine doesn't need a global entry point,
26321 but we do not know whether this is the case at this point. */
26322 if (cfun->is_thunk)
26325 /* For regular functions, rs6000_emit_prologue sets this flag if the
26326 routine ever uses the TOC pointer. */
26327 return cfun->machine->r2_setup_needed;
26330 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26332 rs6000_get_separate_components (void)
26334 rs6000_stack_t *info = rs6000_stack_info ();
26336 if (WORLD_SAVE_P (info))
26339 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26340 && !(info->savres_strategy & REST_MULTIPLE));
26342 /* Component 0 is the save/restore of LR (done via GPR0).
26343 Component 2 is the save of the TOC (GPR2).
26344 Components 13..31 are the save/restore of GPR13..GPR31.
26345 Components 46..63 are the save/restore of FPR14..FPR31. */
26347 cfun->machine->n_components = 64;
26349 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26350 bitmap_clear (components);
26352 int reg_size = TARGET_32BIT ? 4 : 8;
26353 int fp_reg_size = 8;
26355 /* The GPRs we need saved to the frame. */
26356 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26357 && (info->savres_strategy & REST_INLINE_GPRS))
26359 int offset = info->gp_save_offset;
26361 offset += info->total_size;
26363 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26365 if (IN_RANGE (offset, -0x8000, 0x7fff)
26366 && save_reg_p (regno))
26367 bitmap_set_bit (components, regno);
26369 offset += reg_size;
26373 /* Don't mess with the hard frame pointer. */
26374 if (frame_pointer_needed)
26375 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26377 /* Don't mess with the fixed TOC register. */
26378 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26379 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26380 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26381 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26383 /* The FPRs we need saved to the frame. */
26384 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26385 && (info->savres_strategy & REST_INLINE_FPRS))
26387 int offset = info->fp_save_offset;
26389 offset += info->total_size;
26391 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26393 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26394 bitmap_set_bit (components, regno);
26396 offset += fp_reg_size;
26400 /* Optimize LR save and restore if we can. This is component 0. Any
26401 out-of-line register save/restore routines need LR. */
26402 if (info->lr_save_p
26403 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26404 && (info->savres_strategy & SAVE_INLINE_GPRS)
26405 && (info->savres_strategy & REST_INLINE_GPRS)
26406 && (info->savres_strategy & SAVE_INLINE_FPRS)
26407 && (info->savres_strategy & REST_INLINE_FPRS)
26408 && (info->savres_strategy & SAVE_INLINE_VRS)
26409 && (info->savres_strategy & REST_INLINE_VRS))
26411 int offset = info->lr_save_offset;
26413 offset += info->total_size;
26414 if (IN_RANGE (offset, -0x8000, 0x7fff))
26415 bitmap_set_bit (components, 0);
26418 /* Optimize saving the TOC. This is component 2. */
26419 if (cfun->machine->save_toc_in_prologue)
26420 bitmap_set_bit (components, 2);
26425 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26427 rs6000_components_for_bb (basic_block bb)
26429 rs6000_stack_t *info = rs6000_stack_info ();
26431 bitmap in = DF_LIVE_IN (bb);
26432 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26433 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26435 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26436 bitmap_clear (components);
26438 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26441 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26442 if (bitmap_bit_p (in, regno)
26443 || bitmap_bit_p (gen, regno)
26444 || bitmap_bit_p (kill, regno))
26445 bitmap_set_bit (components, regno);
26448 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26449 if (bitmap_bit_p (in, regno)
26450 || bitmap_bit_p (gen, regno)
26451 || bitmap_bit_p (kill, regno))
26452 bitmap_set_bit (components, regno);
26454 /* The link register. */
26455 if (bitmap_bit_p (in, LR_REGNO)
26456 || bitmap_bit_p (gen, LR_REGNO)
26457 || bitmap_bit_p (kill, LR_REGNO))
26458 bitmap_set_bit (components, 0);
26460 /* The TOC save. */
26461 if (bitmap_bit_p (in, TOC_REGNUM)
26462 || bitmap_bit_p (gen, TOC_REGNUM)
26463 || bitmap_bit_p (kill, TOC_REGNUM))
26464 bitmap_set_bit (components, 2);
26469 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26471 rs6000_disqualify_components (sbitmap components, edge e,
26472 sbitmap edge_components, bool /*is_prologue*/)
26474 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26475 live where we want to place that code. */
26476 if (bitmap_bit_p (edge_components, 0)
26477 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26480 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26481 "on entry to bb %d\n", e->dest->index);
26482 bitmap_clear_bit (components, 0);
26486 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26488 rs6000_emit_prologue_components (sbitmap components)
26490 rs6000_stack_t *info = rs6000_stack_info ();
26491 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26492 ? HARD_FRAME_POINTER_REGNUM
26493 : STACK_POINTER_REGNUM);
26495 machine_mode reg_mode = Pmode;
26496 int reg_size = TARGET_32BIT ? 4 : 8;
26497 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26498 int fp_reg_size = 8;
26500 /* Prologue for LR. */
26501 if (bitmap_bit_p (components, 0))
26503 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26504 rtx reg = gen_rtx_REG (reg_mode, 0);
26505 rtx_insn *insn = emit_move_insn (reg, lr);
26506 RTX_FRAME_RELATED_P (insn) = 1;
26507 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26509 int offset = info->lr_save_offset;
26511 offset += info->total_size;
26513 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26514 RTX_FRAME_RELATED_P (insn) = 1;
26515 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26516 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26519 /* Prologue for TOC. */
26520 if (bitmap_bit_p (components, 2))
26522 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26523 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26524 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26527 /* Prologue for the GPRs. */
26528 int offset = info->gp_save_offset;
26530 offset += info->total_size;
26532 for (int i = info->first_gp_reg_save; i < 32; i++)
26534 if (bitmap_bit_p (components, i))
26536 rtx reg = gen_rtx_REG (reg_mode, i);
26537 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26538 RTX_FRAME_RELATED_P (insn) = 1;
26539 rtx set = copy_rtx (single_set (insn));
26540 add_reg_note (insn, REG_CFA_OFFSET, set);
26543 offset += reg_size;
26546 /* Prologue for the FPRs. */
26547 offset = info->fp_save_offset;
26549 offset += info->total_size;
26551 for (int i = info->first_fp_reg_save; i < 64; i++)
26553 if (bitmap_bit_p (components, i))
26555 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26556 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26557 RTX_FRAME_RELATED_P (insn) = 1;
26558 rtx set = copy_rtx (single_set (insn));
26559 add_reg_note (insn, REG_CFA_OFFSET, set);
26562 offset += fp_reg_size;
26566 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26568 rs6000_emit_epilogue_components (sbitmap components)
26570 rs6000_stack_t *info = rs6000_stack_info ();
26571 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26572 ? HARD_FRAME_POINTER_REGNUM
26573 : STACK_POINTER_REGNUM);
26575 machine_mode reg_mode = Pmode;
26576 int reg_size = TARGET_32BIT ? 4 : 8;
26578 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26579 int fp_reg_size = 8;
26581 /* Epilogue for the FPRs. */
26582 int offset = info->fp_save_offset;
26584 offset += info->total_size;
26586 for (int i = info->first_fp_reg_save; i < 64; i++)
26588 if (bitmap_bit_p (components, i))
26590 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26591 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26592 RTX_FRAME_RELATED_P (insn) = 1;
26593 add_reg_note (insn, REG_CFA_RESTORE, reg);
26596 offset += fp_reg_size;
26599 /* Epilogue for the GPRs. */
26600 offset = info->gp_save_offset;
26602 offset += info->total_size;
26604 for (int i = info->first_gp_reg_save; i < 32; i++)
26606 if (bitmap_bit_p (components, i))
26608 rtx reg = gen_rtx_REG (reg_mode, i);
26609 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26610 RTX_FRAME_RELATED_P (insn) = 1;
26611 add_reg_note (insn, REG_CFA_RESTORE, reg);
26614 offset += reg_size;
26617 /* Epilogue for LR. */
26618 if (bitmap_bit_p (components, 0))
26620 int offset = info->lr_save_offset;
26622 offset += info->total_size;
26624 rtx reg = gen_rtx_REG (reg_mode, 0);
26625 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26627 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26628 insn = emit_move_insn (lr, reg);
26629 RTX_FRAME_RELATED_P (insn) = 1;
26630 add_reg_note (insn, REG_CFA_RESTORE, lr);
26634 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26636 rs6000_set_handled_components (sbitmap components)
26638 rs6000_stack_t *info = rs6000_stack_info ();
26640 for (int i = info->first_gp_reg_save; i < 32; i++)
26641 if (bitmap_bit_p (components, i))
26642 cfun->machine->gpr_is_wrapped_separately[i] = true;
26644 for (int i = info->first_fp_reg_save; i < 64; i++)
26645 if (bitmap_bit_p (components, i))
26646 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26648 if (bitmap_bit_p (components, 0))
26649 cfun->machine->lr_is_wrapped_separately = true;
26651 if (bitmap_bit_p (components, 2))
26652 cfun->machine->toc_is_wrapped_separately = true;
26655 /* VRSAVE is a bit vector representing which AltiVec registers
26656 are used. The OS uses this to determine which vector
26657 registers to save on a context switch. We need to save
26658 VRSAVE on the stack frame, add whatever AltiVec registers we
26659 used in this function, and do the corresponding magic in the
26662 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26663 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26665 /* Get VRSAVE into a GPR. */
26666 rtx reg = gen_rtx_REG (SImode, save_regno);
26667 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26669 emit_insn (gen_get_vrsave_internal (reg));
26671 emit_insn (gen_rtx_SET (reg, vrsave));
26674 int offset = info->vrsave_save_offset + frame_off;
26675 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26677 /* Include the registers in the mask. */
26678 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26680 emit_insn (generate_set_vrsave (reg, info, 0));
26683 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26684 called, it left the arg pointer to the old stack in r29. Otherwise, the
26685 arg pointer is the top of the current frame. */
26687 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26688 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26690 cfun->machine->split_stack_argp_used = true;
26694 rtx r12 = gen_rtx_REG (Pmode, 12);
26695 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26696 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26697 emit_insn_before (set_r12, sp_adjust);
26699 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26701 rtx r12 = gen_rtx_REG (Pmode, 12);
26702 if (frame_off == 0)
26703 emit_move_insn (r12, frame_reg_rtx);
26705 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26710 rtx r12 = gen_rtx_REG (Pmode, 12);
26711 rtx r29 = gen_rtx_REG (Pmode, 29);
26712 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26713 rtx not_more = gen_label_rtx ();
26716 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26717 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26718 gen_rtx_LABEL_REF (VOIDmode, not_more),
26720 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26721 JUMP_LABEL (jump) = not_more;
26722 LABEL_NUSES (not_more) += 1;
26723 emit_move_insn (r12, r29);
26724 emit_label (not_more);
26728 /* Emit function prologue as insns. */
26731 rs6000_emit_prologue (void)
26733 rs6000_stack_t *info = rs6000_stack_info ();
26734 machine_mode reg_mode = Pmode;
26735 int reg_size = TARGET_32BIT ? 4 : 8;
26736 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26737 int fp_reg_size = 8;
26738 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26739 rtx frame_reg_rtx = sp_reg_rtx;
26740 unsigned int cr_save_regno;
26741 rtx cr_save_rtx = NULL_RTX;
26744 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26745 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26746 && call_used_regs[STATIC_CHAIN_REGNUM]);
26747 int using_split_stack = (flag_split_stack
26748 && (lookup_attribute ("no_split_stack",
26749 DECL_ATTRIBUTES (cfun->decl))
26752 /* Offset to top of frame for frame_reg and sp respectively. */
26753 HOST_WIDE_INT frame_off = 0;
26754 HOST_WIDE_INT sp_off = 0;
26755 /* sp_adjust is the stack adjusting instruction, tracked so that the
26756 insn setting up the split-stack arg pointer can be emitted just
26757 prior to it, when r12 is not used here for other purposes. */
26758 rtx_insn *sp_adjust = 0;
26761 /* Track and check usage of r0, r11, r12. */
26762 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26763 #define START_USE(R) do \
26765 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26766 reg_inuse |= 1 << (R); \
26768 #define END_USE(R) do \
26770 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26771 reg_inuse &= ~(1 << (R)); \
26773 #define NOT_INUSE(R) do \
26775 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26778 #define START_USE(R) do {} while (0)
26779 #define END_USE(R) do {} while (0)
26780 #define NOT_INUSE(R) do {} while (0)
26783 if (DEFAULT_ABI == ABI_ELFv2
26784 && !TARGET_SINGLE_PIC_BASE)
26786 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26788 /* With -mminimal-toc we may generate an extra use of r2 below. */
26789 if (TARGET_TOC && TARGET_MINIMAL_TOC
26790 && !constant_pool_empty_p ())
26791 cfun->machine->r2_setup_needed = true;
26795 if (flag_stack_usage_info)
26796 current_function_static_stack_size = info->total_size;
26798 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26800 HOST_WIDE_INT size = info->total_size;
26802 if (crtl->is_leaf && !cfun->calls_alloca)
26804 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26805 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26806 size - get_stack_check_protect ());
26809 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26812 if (TARGET_FIX_AND_CONTINUE)
26814 /* gdb on darwin arranges to forward a function from the old
26815 address by modifying the first 5 instructions of the function
26816 to branch to the overriding function. This is necessary to
26817 permit function pointers that point to the old function to
26818 actually forward to the new function. */
26819 emit_insn (gen_nop ());
26820 emit_insn (gen_nop ());
26821 emit_insn (gen_nop ());
26822 emit_insn (gen_nop ());
26823 emit_insn (gen_nop ());
26826 /* Handle world saves specially here. */
26827 if (WORLD_SAVE_P (info))
26834 /* save_world expects lr in r0. */
26835 reg0 = gen_rtx_REG (Pmode, 0);
26836 if (info->lr_save_p)
26838 insn = emit_move_insn (reg0,
26839 gen_rtx_REG (Pmode, LR_REGNO));
26840 RTX_FRAME_RELATED_P (insn) = 1;
26843 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26844 assumptions about the offsets of various bits of the stack
26846 gcc_assert (info->gp_save_offset == -220
26847 && info->fp_save_offset == -144
26848 && info->lr_save_offset == 8
26849 && info->cr_save_offset == 4
26852 && (!crtl->calls_eh_return
26853 || info->ehrd_offset == -432)
26854 && info->vrsave_save_offset == -224
26855 && info->altivec_save_offset == -416);
26857 treg = gen_rtx_REG (SImode, 11);
26858 emit_move_insn (treg, GEN_INT (-info->total_size));
26860 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26861 in R11. It also clobbers R12, so beware! */
26863 /* Preserve CR2 for save_world prologues */
26865 sz += 32 - info->first_gp_reg_save;
26866 sz += 64 - info->first_fp_reg_save;
26867 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26868 p = rtvec_alloc (sz);
26870 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
26871 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26872 gen_rtx_SYMBOL_REF (Pmode,
26874 /* We do floats first so that the instruction pattern matches
26876 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26878 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26879 info->first_fp_reg_save + i),
26881 info->fp_save_offset + frame_off + 8 * i);
26882 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26884 = gen_frame_store (gen_rtx_REG (V4SImode,
26885 info->first_altivec_reg_save + i),
26887 info->altivec_save_offset + frame_off + 16 * i);
26888 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26890 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26892 info->gp_save_offset + frame_off + reg_size * i);
26894 /* CR register traditionally saved as CR2. */
26896 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26897 frame_reg_rtx, info->cr_save_offset + frame_off);
26898 /* Explain about use of R0. */
26899 if (info->lr_save_p)
26901 = gen_frame_store (reg0,
26902 frame_reg_rtx, info->lr_save_offset + frame_off);
26903 /* Explain what happens to the stack pointer. */
26905 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26906 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26909 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26910 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26911 treg, GEN_INT (-info->total_size));
26912 sp_off = frame_off = info->total_size;
26915 strategy = info->savres_strategy;
26917 /* For V.4, update stack before we do any saving and set back pointer. */
26918 if (! WORLD_SAVE_P (info)
26920 && (DEFAULT_ABI == ABI_V4
26921 || crtl->calls_eh_return))
26923 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26924 || !(strategy & SAVE_INLINE_GPRS)
26925 || !(strategy & SAVE_INLINE_VRS));
26926 int ptr_regno = -1;
26927 rtx ptr_reg = NULL_RTX;
26930 if (info->total_size < 32767)
26931 frame_off = info->total_size;
26934 else if (info->cr_save_p
26936 || info->first_fp_reg_save < 64
26937 || info->first_gp_reg_save < 32
26938 || info->altivec_size != 0
26939 || info->vrsave_size != 0
26940 || crtl->calls_eh_return)
26944 /* The prologue won't be saving any regs so there is no need
26945 to set up a frame register to access any frame save area.
26946 We also won't be using frame_off anywhere below, but set
26947 the correct value anyway to protect against future
26948 changes to this function. */
26949 frame_off = info->total_size;
26951 if (ptr_regno != -1)
26953 /* Set up the frame offset to that needed by the first
26954 out-of-line save function. */
26955 START_USE (ptr_regno);
26956 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26957 frame_reg_rtx = ptr_reg;
26958 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26959 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26960 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26961 ptr_off = info->gp_save_offset + info->gp_size;
26962 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26963 ptr_off = info->altivec_save_offset + info->altivec_size;
26964 frame_off = -ptr_off;
26966 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26968 if (REGNO (frame_reg_rtx) == 12)
26970 sp_off = info->total_size;
26971 if (frame_reg_rtx != sp_reg_rtx)
26972 rs6000_emit_stack_tie (frame_reg_rtx, false);
26975 /* If we use the link register, get it into r0. */
26976 if (!WORLD_SAVE_P (info) && info->lr_save_p
26977 && !cfun->machine->lr_is_wrapped_separately)
26979 rtx addr, reg, mem;
26981 reg = gen_rtx_REG (Pmode, 0);
26983 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26984 RTX_FRAME_RELATED_P (insn) = 1;
26986 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26987 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26989 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26990 GEN_INT (info->lr_save_offset + frame_off));
26991 mem = gen_rtx_MEM (Pmode, addr);
26992 /* This should not be of rs6000_sr_alias_set, because of
26993 __builtin_return_address. */
26995 insn = emit_move_insn (mem, reg);
26996 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26997 NULL_RTX, NULL_RTX);
27002 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27003 r12 will be needed by out-of-line gpr save. */
27004 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27005 && !(strategy & (SAVE_INLINE_GPRS
27006 | SAVE_NOINLINE_GPRS_SAVES_LR))
27008 if (!WORLD_SAVE_P (info)
27010 && REGNO (frame_reg_rtx) != cr_save_regno
27011 && !(using_static_chain_p && cr_save_regno == 11)
27012 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27014 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27015 START_USE (cr_save_regno);
27016 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27019 /* Do any required saving of fpr's. If only one or two to save, do
27020 it ourselves. Otherwise, call function. */
27021 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27023 int offset = info->fp_save_offset + frame_off;
27024 for (int i = info->first_fp_reg_save; i < 64; i++)
27027 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27028 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27029 sp_off - frame_off);
27031 offset += fp_reg_size;
27034 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27036 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27037 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27038 unsigned ptr_regno = ptr_regno_for_savres (sel);
27039 rtx ptr_reg = frame_reg_rtx;
27041 if (REGNO (frame_reg_rtx) == ptr_regno)
27042 gcc_checking_assert (frame_off == 0);
27045 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27046 NOT_INUSE (ptr_regno);
27047 emit_insn (gen_add3_insn (ptr_reg,
27048 frame_reg_rtx, GEN_INT (frame_off)));
27050 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27051 info->fp_save_offset,
27052 info->lr_save_offset,
27054 rs6000_frame_related (insn, ptr_reg, sp_off,
27055 NULL_RTX, NULL_RTX);
27060 /* Save GPRs. This is done as a PARALLEL if we are using
27061 the store-multiple instructions. */
27062 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27064 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27065 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27066 unsigned ptr_regno = ptr_regno_for_savres (sel);
27067 rtx ptr_reg = frame_reg_rtx;
27068 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27069 int end_save = info->gp_save_offset + info->gp_size;
27072 if (ptr_regno == 12)
27075 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27077 /* Need to adjust r11 (r12) if we saved any FPRs. */
27078 if (end_save + frame_off != 0)
27080 rtx offset = GEN_INT (end_save + frame_off);
27083 frame_off = -end_save;
27085 NOT_INUSE (ptr_regno);
27086 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27088 else if (!ptr_set_up)
27090 NOT_INUSE (ptr_regno);
27091 emit_move_insn (ptr_reg, frame_reg_rtx);
27093 ptr_off = -end_save;
27094 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27095 info->gp_save_offset + ptr_off,
27096 info->lr_save_offset + ptr_off,
27098 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27099 NULL_RTX, NULL_RTX);
27103 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27107 p = rtvec_alloc (32 - info->first_gp_reg_save);
27108 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27110 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27112 info->gp_save_offset + frame_off + reg_size * i);
27113 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27114 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27115 NULL_RTX, NULL_RTX);
27117 else if (!WORLD_SAVE_P (info))
27119 int offset = info->gp_save_offset + frame_off;
27120 for (int i = info->first_gp_reg_save; i < 32; i++)
27123 && !cfun->machine->gpr_is_wrapped_separately[i])
27124 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27125 sp_off - frame_off);
27127 offset += reg_size;
27131 if (crtl->calls_eh_return)
27138 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27139 if (regno == INVALID_REGNUM)
27143 p = rtvec_alloc (i);
27147 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27148 if (regno == INVALID_REGNUM)
27152 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27154 info->ehrd_offset + sp_off + reg_size * (int) i);
27155 RTVEC_ELT (p, i) = set;
27156 RTX_FRAME_RELATED_P (set) = 1;
27159 insn = emit_insn (gen_blockage ());
27160 RTX_FRAME_RELATED_P (insn) = 1;
27161 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27164 /* In AIX ABI we need to make sure r2 is really saved. */
27165 if (TARGET_AIX && crtl->calls_eh_return)
27167 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27168 rtx join_insn, note;
27169 rtx_insn *save_insn;
27170 long toc_restore_insn;
27172 tmp_reg = gen_rtx_REG (Pmode, 11);
27173 tmp_reg_si = gen_rtx_REG (SImode, 11);
27174 if (using_static_chain_p)
27177 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27181 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27182 /* Peek at instruction to which this function returns. If it's
27183 restoring r2, then we know we've already saved r2. We can't
27184 unconditionally save r2 because the value we have will already
27185 be updated if we arrived at this function via a plt call or
27186 toc adjusting stub. */
27187 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27188 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27189 + RS6000_TOC_SAVE_SLOT);
27190 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27191 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27192 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27193 validate_condition_mode (EQ, CCUNSmode);
27194 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27195 emit_insn (gen_rtx_SET (compare_result,
27196 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27197 toc_save_done = gen_label_rtx ();
27198 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27199 gen_rtx_EQ (VOIDmode, compare_result,
27201 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27203 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27204 JUMP_LABEL (jump) = toc_save_done;
27205 LABEL_NUSES (toc_save_done) += 1;
27207 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27208 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27209 sp_off - frame_off);
27211 emit_label (toc_save_done);
27213 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27214 have a CFG that has different saves along different paths.
27215 Move the note to a dummy blockage insn, which describes that
27216 R2 is unconditionally saved after the label. */
27217 /* ??? An alternate representation might be a special insn pattern
27218 containing both the branch and the store. That might let the
27219 code that minimizes the number of DW_CFA_advance opcodes better
27220 freedom in placing the annotations. */
27221 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27223 remove_note (save_insn, note);
27225 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27226 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27227 RTX_FRAME_RELATED_P (save_insn) = 0;
27229 join_insn = emit_insn (gen_blockage ());
27230 REG_NOTES (join_insn) = note;
27231 RTX_FRAME_RELATED_P (join_insn) = 1;
27233 if (using_static_chain_p)
27235 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27242 /* Save CR if we use any that must be preserved. */
27243 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27245 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27246 GEN_INT (info->cr_save_offset + frame_off));
27247 rtx mem = gen_frame_mem (SImode, addr);
27249 /* If we didn't copy cr before, do so now using r0. */
27250 if (cr_save_rtx == NULL_RTX)
27253 cr_save_rtx = gen_rtx_REG (SImode, 0);
27254 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27257 /* Saving CR requires a two-instruction sequence: one instruction
27258 to move the CR to a general-purpose register, and a second
27259 instruction that stores the GPR to memory.
27261 We do not emit any DWARF CFI records for the first of these,
27262 because we cannot properly represent the fact that CR is saved in
27263 a register. One reason is that we cannot express that multiple
27264 CR fields are saved; another reason is that on 64-bit, the size
27265 of the CR register in DWARF (4 bytes) differs from the size of
27266 a general-purpose register.
27268 This means if any intervening instruction were to clobber one of
27269 the call-saved CR fields, we'd have incorrect CFI. To prevent
27270 this from happening, we mark the store to memory as a use of
27271 those CR fields, which prevents any such instruction from being
27272 scheduled in between the two instructions. */
27277 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27278 for (i = 0; i < 8; i++)
27279 if (save_reg_p (CR0_REGNO + i))
27280 crsave_v[n_crsave++]
27281 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27283 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27284 gen_rtvec_v (n_crsave, crsave_v)));
27285 END_USE (REGNO (cr_save_rtx));
27287 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27288 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27289 so we need to construct a frame expression manually. */
27290 RTX_FRAME_RELATED_P (insn) = 1;
27292 /* Update address to be stack-pointer relative, like
27293 rs6000_frame_related would do. */
27294 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27295 GEN_INT (info->cr_save_offset + sp_off));
27296 mem = gen_frame_mem (SImode, addr);
27298 if (DEFAULT_ABI == ABI_ELFv2)
27300 /* In the ELFv2 ABI we generate separate CFI records for each
27301 CR field that was actually saved. They all point to the
27302 same 32-bit stack slot. */
27306 for (i = 0; i < 8; i++)
27307 if (save_reg_p (CR0_REGNO + i))
27310 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27312 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27316 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27317 gen_rtx_PARALLEL (VOIDmode,
27318 gen_rtvec_v (n_crframe, crframe)));
27322 /* In other ABIs, by convention, we use a single CR regnum to
27323 represent the fact that all call-saved CR fields are saved.
27324 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27325 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27326 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27330 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27331 *separate* slots if the routine calls __builtin_eh_return, so
27332 that they can be independently restored by the unwinder. */
27333 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27335 int i, cr_off = info->ehcr_offset;
27338 /* ??? We might get better performance by using multiple mfocrf
27340 crsave = gen_rtx_REG (SImode, 0);
27341 emit_insn (gen_prologue_movesi_from_cr (crsave));
27343 for (i = 0; i < 8; i++)
27344 if (!call_used_regs[CR0_REGNO + i])
27346 rtvec p = rtvec_alloc (2);
27348 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27350 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27352 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27354 RTX_FRAME_RELATED_P (insn) = 1;
27355 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27356 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27357 sp_reg_rtx, cr_off + sp_off));
27359 cr_off += reg_size;
27363 /* If we are emitting stack probes, but allocate no stack, then
27364 just note that in the dump file. */
27365 if (flag_stack_clash_protection
27368 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27370 /* Update stack and set back pointer unless this is V.4,
27371 for which it was done previously. */
27372 if (!WORLD_SAVE_P (info) && info->push_p
27373 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27375 rtx ptr_reg = NULL;
27378 /* If saving altivec regs we need to be able to address all save
27379 locations using a 16-bit offset. */
27380 if ((strategy & SAVE_INLINE_VRS) == 0
27381 || (info->altivec_size != 0
27382 && (info->altivec_save_offset + info->altivec_size - 16
27383 + info->total_size - frame_off) > 32767)
27384 || (info->vrsave_size != 0
27385 && (info->vrsave_save_offset
27386 + info->total_size - frame_off) > 32767))
27388 int sel = SAVRES_SAVE | SAVRES_VR;
27389 unsigned ptr_regno = ptr_regno_for_savres (sel);
27391 if (using_static_chain_p
27392 && ptr_regno == STATIC_CHAIN_REGNUM)
27394 if (REGNO (frame_reg_rtx) != ptr_regno)
27395 START_USE (ptr_regno);
27396 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27397 frame_reg_rtx = ptr_reg;
27398 ptr_off = info->altivec_save_offset + info->altivec_size;
27399 frame_off = -ptr_off;
27401 else if (REGNO (frame_reg_rtx) == 1)
27402 frame_off = info->total_size;
27403 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27405 if (REGNO (frame_reg_rtx) == 12)
27407 sp_off = info->total_size;
27408 if (frame_reg_rtx != sp_reg_rtx)
27409 rs6000_emit_stack_tie (frame_reg_rtx, false);
27412 /* Set frame pointer, if needed. */
27413 if (frame_pointer_needed)
27415 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27417 RTX_FRAME_RELATED_P (insn) = 1;
27420 /* Save AltiVec registers if needed. Save here because the red zone does
27421 not always include AltiVec registers. */
27422 if (!WORLD_SAVE_P (info)
27423 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27425 int end_save = info->altivec_save_offset + info->altivec_size;
27427 /* Oddly, the vector save/restore functions point r0 at the end
27428 of the save area, then use r11 or r12 to load offsets for
27429 [reg+reg] addressing. */
27430 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27431 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27432 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27434 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27436 if (scratch_regno == 12)
27438 if (end_save + frame_off != 0)
27440 rtx offset = GEN_INT (end_save + frame_off);
27442 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27445 emit_move_insn (ptr_reg, frame_reg_rtx);
27447 ptr_off = -end_save;
27448 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27449 info->altivec_save_offset + ptr_off,
27450 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27451 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27452 NULL_RTX, NULL_RTX);
27453 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27455 /* The oddity mentioned above clobbered our frame reg. */
27456 emit_move_insn (frame_reg_rtx, ptr_reg);
27457 frame_off = ptr_off;
27460 else if (!WORLD_SAVE_P (info)
27461 && info->altivec_size != 0)
27465 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27466 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27468 rtx areg, savereg, mem;
27469 HOST_WIDE_INT offset;
27471 offset = (info->altivec_save_offset + frame_off
27472 + 16 * (i - info->first_altivec_reg_save));
27474 savereg = gen_rtx_REG (V4SImode, i);
27476 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27478 mem = gen_frame_mem (V4SImode,
27479 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27480 GEN_INT (offset)));
27481 insn = emit_insn (gen_rtx_SET (mem, savereg));
27487 areg = gen_rtx_REG (Pmode, 0);
27488 emit_move_insn (areg, GEN_INT (offset));
27490 /* AltiVec addressing mode is [reg+reg]. */
27491 mem = gen_frame_mem (V4SImode,
27492 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27494 /* Rather than emitting a generic move, force use of the stvx
27495 instruction, which we always want on ISA 2.07 (power8) systems.
27496 In particular we don't want xxpermdi/stxvd2x for little
27498 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27501 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27502 areg, GEN_INT (offset));
27506 /* VRSAVE is a bit vector representing which AltiVec registers
27507 are used. The OS uses this to determine which vector
27508 registers to save on a context switch. We need to save
27509 VRSAVE on the stack frame, add whatever AltiVec registers we
27510 used in this function, and do the corresponding magic in the
27513 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27515 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27516 be using r12 as frame_reg_rtx and r11 as the static chain
27517 pointer for nested functions. */
27518 int save_regno = 12;
27519 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27520 && !using_static_chain_p)
27522 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27525 if (using_static_chain_p)
27528 NOT_INUSE (save_regno);
27530 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27533 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27534 if (!TARGET_SINGLE_PIC_BASE
27535 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27536 && !constant_pool_empty_p ())
27537 || (DEFAULT_ABI == ABI_V4
27538 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27539 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27541 /* If emit_load_toc_table will use the link register, we need to save
27542 it. We use R12 for this purpose because emit_load_toc_table
27543 can use register 0. This allows us to use a plain 'blr' to return
27544 from the procedure more often. */
27545 int save_LR_around_toc_setup = (TARGET_ELF
27546 && DEFAULT_ABI == ABI_V4
27548 && ! info->lr_save_p
27549 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27550 if (save_LR_around_toc_setup)
27552 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27553 rtx tmp = gen_rtx_REG (Pmode, 12);
27556 insn = emit_move_insn (tmp, lr);
27557 RTX_FRAME_RELATED_P (insn) = 1;
27559 rs6000_emit_load_toc_table (TRUE);
27561 insn = emit_move_insn (lr, tmp);
27562 add_reg_note (insn, REG_CFA_RESTORE, lr);
27563 RTX_FRAME_RELATED_P (insn) = 1;
27566 rs6000_emit_load_toc_table (TRUE);
27570 if (!TARGET_SINGLE_PIC_BASE
27571 && DEFAULT_ABI == ABI_DARWIN
27572 && flag_pic && crtl->uses_pic_offset_table)
27574 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27575 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27577 /* Save and restore LR locally around this call (in R0). */
27578 if (!info->lr_save_p)
27579 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27581 emit_insn (gen_load_macho_picbase (src));
27583 emit_move_insn (gen_rtx_REG (Pmode,
27584 RS6000_PIC_OFFSET_TABLE_REGNUM),
27587 if (!info->lr_save_p)
27588 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27592 /* If we need to, save the TOC register after doing the stack setup.
27593 Do not emit eh frame info for this save. The unwinder wants info,
27594 conceptually attached to instructions in this function, about
27595 register values in the caller of this function. This R2 may have
27596 already been changed from the value in the caller.
27597 We don't attempt to write accurate DWARF EH frame info for R2
27598 because code emitted by gcc for a (non-pointer) function call
27599 doesn't save and restore R2. Instead, R2 is managed out-of-line
27600 by a linker generated plt call stub when the function resides in
27601 a shared library. This behavior is costly to describe in DWARF,
27602 both in terms of the size of DWARF info and the time taken in the
27603 unwinder to interpret it. R2 changes, apart from the
27604 calls_eh_return case earlier in this function, are handled by
27605 linux-unwind.h frob_update_context. */
27606 if (rs6000_save_toc_in_prologue_p ()
27607 && !cfun->machine->toc_is_wrapped_separately)
27609 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27610 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27613 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27614 if (using_split_stack && split_stack_arg_pointer_used_p ())
27615 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27618 /* Output .extern statements for the save/restore routines we use. */
27621 rs6000_output_savres_externs (FILE *file)
27623 rs6000_stack_t *info = rs6000_stack_info ();
27625 if (TARGET_DEBUG_STACK)
27626 debug_stack_info (info);
27628 /* Write .extern for any function we will call to save and restore
27630 if (info->first_fp_reg_save < 64
27635 int regno = info->first_fp_reg_save - 32;
27637 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27639 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27640 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27641 name = rs6000_savres_routine_name (regno, sel);
27642 fprintf (file, "\t.extern %s\n", name);
27644 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27646 bool lr = (info->savres_strategy
27647 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27648 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27649 name = rs6000_savres_routine_name (regno, sel);
27650 fprintf (file, "\t.extern %s\n", name);
27655 /* Write function prologue. */
27658 rs6000_output_function_prologue (FILE *file)
27660 if (!cfun->is_thunk)
27662 rs6000_output_savres_externs (file);
27663 #ifdef USING_ELFOS_H
27664 const char *curr_machine = rs6000_machine_from_flags ();
27665 if (rs6000_machine != curr_machine)
27667 rs6000_machine = curr_machine;
27668 emit_asm_machine ();
27673 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27674 immediately after the global entry point label. */
27675 if (rs6000_global_entry_point_prologue_needed_p ())
27677 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27678 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27680 if (TARGET_CMODEL != CMODEL_LARGE)
27682 /* In the small and medium code models, we assume the TOC is less
27683 2 GB away from the text section, so it can be computed via the
27684 following two-instruction sequence. */
27687 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27688 fprintf (file, "0:\taddis 2,12,.TOC.-");
27689 assemble_name (file, buf);
27690 fprintf (file, "@ha\n");
27691 fprintf (file, "\taddi 2,2,.TOC.-");
27692 assemble_name (file, buf);
27693 fprintf (file, "@l\n");
27697 /* In the large code model, we allow arbitrary offsets between the
27698 TOC and the text section, so we have to load the offset from
27699 memory. The data field is emitted directly before the global
27700 entry point in rs6000_elf_declare_function_name. */
27703 #ifdef HAVE_AS_ENTRY_MARKERS
27704 /* If supported by the linker, emit a marker relocation. If the
27705 total code size of the final executable or shared library
27706 happens to fit into 2 GB after all, the linker will replace
27707 this code sequence with the sequence for the small or medium
27709 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27711 fprintf (file, "\tld 2,");
27712 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27713 assemble_name (file, buf);
27714 fprintf (file, "-");
27715 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27716 assemble_name (file, buf);
27717 fprintf (file, "(12)\n");
27718 fprintf (file, "\tadd 2,2,12\n");
27721 fputs ("\t.localentry\t", file);
27722 assemble_name (file, name);
27723 fputs (",.-", file);
27724 assemble_name (file, name);
27725 fputs ("\n", file);
27728 else if (rs6000_pcrel_p (cfun))
27730 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27731 /* All functions compiled to use PC-relative addressing will
27732 have a .localentry value of 0 or 1. For now we set it to
27733 1 all the time, indicating that the function may clobber
27734 the TOC register r2. Later we may optimize this by setting
27735 it to 0 if the function is a leaf and does not clobber r2. */
27736 fputs ("\t.localentry\t", file);
27737 assemble_name (file, name);
27738 fputs (",1\n", file);
27741 /* Output -mprofile-kernel code. This needs to be done here instead of
27742 in output_function_profile since it must go after the ELFv2 ABI
27743 local entry point. */
27744 if (TARGET_PROFILE_KERNEL && crtl->profile)
27746 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27747 gcc_assert (!TARGET_32BIT);
27749 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27751 /* In the ELFv2 ABI we have no compiler stack word. It must be
27752 the resposibility of _mcount to preserve the static chain
27753 register if required. */
27754 if (DEFAULT_ABI != ABI_ELFv2
27755 && cfun->static_chain_decl != NULL)
27757 asm_fprintf (file, "\tstd %s,24(%s)\n",
27758 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27759 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27760 asm_fprintf (file, "\tld %s,24(%s)\n",
27761 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27764 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27767 rs6000_pic_labelno++;
27770 /* -mprofile-kernel code calls mcount before the function prolog,
27771 so a profiled leaf function should stay a leaf function. */
27773 rs6000_keep_leaf_when_profiled ()
27775 return TARGET_PROFILE_KERNEL;
27778 /* Non-zero if vmx regs are restored before the frame pop, zero if
27779 we restore after the pop when possible. */
27780 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27782 /* Restoring cr is a two step process: loading a reg from the frame
27783 save, then moving the reg to cr. For ABI_V4 we must let the
27784 unwinder know that the stack location is no longer valid at or
27785 before the stack deallocation, but we can't emit a cfa_restore for
27786 cr at the stack deallocation like we do for other registers.
27787 The trouble is that it is possible for the move to cr to be
27788 scheduled after the stack deallocation. So say exactly where cr
27789 is located on each of the two insns. */
27792 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27794 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27795 rtx reg = gen_rtx_REG (SImode, regno);
27796 rtx_insn *insn = emit_move_insn (reg, mem);
27798 if (!exit_func && DEFAULT_ABI == ABI_V4)
27800 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27801 rtx set = gen_rtx_SET (reg, cr);
27803 add_reg_note (insn, REG_CFA_REGISTER, set);
27804 RTX_FRAME_RELATED_P (insn) = 1;
27809 /* Reload CR from REG. */
27812 restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func)
27817 if (using_mfcr_multiple)
27819 for (i = 0; i < 8; i++)
27820 if (save_reg_p (CR0_REGNO + i))
27822 gcc_assert (count);
27825 if (using_mfcr_multiple && count > 1)
27831 p = rtvec_alloc (count);
27834 for (i = 0; i < 8; i++)
27835 if (save_reg_p (CR0_REGNO + i))
27837 rtvec r = rtvec_alloc (2);
27838 RTVEC_ELT (r, 0) = reg;
27839 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27840 RTVEC_ELT (p, ndx) =
27841 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27842 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27845 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27846 gcc_assert (ndx == count);
27848 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27849 CR field separately. */
27850 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27852 for (i = 0; i < 8; i++)
27853 if (save_reg_p (CR0_REGNO + i))
27854 add_reg_note (insn, REG_CFA_RESTORE,
27855 gen_rtx_REG (SImode, CR0_REGNO + i));
27857 RTX_FRAME_RELATED_P (insn) = 1;
27861 for (i = 0; i < 8; i++)
27862 if (save_reg_p (CR0_REGNO + i))
27864 rtx insn = emit_insn (gen_movsi_to_cr_one
27865 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27867 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27868 CR field separately, attached to the insn that in fact
27869 restores this particular CR field. */
27870 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27872 add_reg_note (insn, REG_CFA_RESTORE,
27873 gen_rtx_REG (SImode, CR0_REGNO + i));
27875 RTX_FRAME_RELATED_P (insn) = 1;
27879 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27880 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27881 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27883 rtx_insn *insn = get_last_insn ();
27884 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27886 add_reg_note (insn, REG_CFA_RESTORE, cr);
27887 RTX_FRAME_RELATED_P (insn) = 1;
27891 /* Like cr, the move to lr instruction can be scheduled after the
27892 stack deallocation, but unlike cr, its stack frame save is still
27893 valid. So we only need to emit the cfa_restore on the correct
27897 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27899 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27900 rtx reg = gen_rtx_REG (Pmode, regno);
27902 emit_move_insn (reg, mem);
27906 restore_saved_lr (int regno, bool exit_func)
27908 rtx reg = gen_rtx_REG (Pmode, regno);
27909 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27910 rtx_insn *insn = emit_move_insn (lr, reg);
27912 if (!exit_func && flag_shrink_wrap)
27914 add_reg_note (insn, REG_CFA_RESTORE, lr);
27915 RTX_FRAME_RELATED_P (insn) = 1;
27920 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27922 if (DEFAULT_ABI == ABI_ELFv2)
27925 for (i = 0; i < 8; i++)
27926 if (save_reg_p (CR0_REGNO + i))
27928 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27929 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27933 else if (info->cr_save_p)
27934 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27935 gen_rtx_REG (SImode, CR2_REGNO),
27938 if (info->lr_save_p)
27939 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27940 gen_rtx_REG (Pmode, LR_REGNO),
27942 return cfa_restores;
27945 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27946 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27947 below stack pointer not cloberred by signals. */
27950 offset_below_red_zone_p (HOST_WIDE_INT offset)
27952 return offset < (DEFAULT_ABI == ABI_V4
27954 : TARGET_32BIT ? -220 : -288);
27957 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27960 emit_cfa_restores (rtx cfa_restores)
27962 rtx_insn *insn = get_last_insn ();
27963 rtx *loc = ®_NOTES (insn);
27966 loc = &XEXP (*loc, 1);
27967 *loc = cfa_restores;
27968 RTX_FRAME_RELATED_P (insn) = 1;
27971 /* Emit function epilogue as insns. */
27974 rs6000_emit_epilogue (enum epilogue_type epilogue_type)
27976 HOST_WIDE_INT frame_off = 0;
27977 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27978 rtx frame_reg_rtx = sp_reg_rtx;
27979 rtx cfa_restores = NULL_RTX;
27981 rtx cr_save_reg = NULL_RTX;
27982 machine_mode reg_mode = Pmode;
27983 int reg_size = TARGET_32BIT ? 4 : 8;
27984 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27985 int fp_reg_size = 8;
27987 unsigned ptr_regno;
27989 rs6000_stack_t *info = rs6000_stack_info ();
27991 if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return)
27992 epilogue_type = EPILOGUE_TYPE_EH_RETURN;
27994 int strategy = info->savres_strategy;
27995 bool using_load_multiple = !!(strategy & REST_MULTIPLE);
27996 bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS);
27997 bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS);
27998 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28000 restoring_GPRs_inline = true;
28001 restoring_FPRs_inline = true;
28004 bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
28005 || rs6000_tune == PROCESSOR_PPC603
28006 || rs6000_tune == PROCESSOR_PPC750
28009 /* Restore via the backchain when we have a large frame, since this
28010 is more efficient than an addis, addi pair. The second condition
28011 here will not trigger at the moment; We don't actually need a
28012 frame pointer for alloca, but the generic parts of the compiler
28013 give us one anyway. */
28014 bool use_backchain_to_restore_sp
28015 = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767
28016 || (cfun->calls_alloca && !frame_pointer_needed));
28018 bool restore_lr = (info->lr_save_p
28019 && (restoring_FPRs_inline
28020 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28021 && (restoring_GPRs_inline
28022 || info->first_fp_reg_save < 64)
28023 && !cfun->machine->lr_is_wrapped_separately);
28026 if (WORLD_SAVE_P (info))
28028 gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL);
28030 /* eh_rest_world_r10 will return to the location saved in the LR
28031 stack slot (which is not likely to be our caller.)
28032 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28033 rest_world is similar, except any R10 parameter is ignored.
28034 The exception-handling stuff that was here in 2.95 is no
28035 longer necessary. */
28039 + 32 - info->first_gp_reg_save
28040 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28041 + 63 + 1 - info->first_fp_reg_save);
28044 switch (epilogue_type)
28046 case EPILOGUE_TYPE_NORMAL:
28047 rname = ggc_strdup ("*rest_world");
28050 case EPILOGUE_TYPE_EH_RETURN:
28051 rname = ggc_strdup ("*eh_rest_world_r10");
28055 gcc_unreachable ();
28059 RTVEC_ELT (p, j++) = ret_rtx;
28061 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname));
28062 /* The instruction pattern requires a clobber here;
28063 it is shared with the restVEC helper. */
28064 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11);
28067 /* CR register traditionally saved as CR2. */
28068 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28070 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28071 if (flag_shrink_wrap)
28073 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28074 gen_rtx_REG (Pmode, LR_REGNO),
28076 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28081 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28083 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28085 = gen_frame_load (reg,
28086 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28087 if (flag_shrink_wrap
28088 && save_reg_p (info->first_gp_reg_save + i))
28089 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28091 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28093 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28095 = gen_frame_load (reg,
28096 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28097 if (flag_shrink_wrap
28098 && save_reg_p (info->first_altivec_reg_save + i))
28099 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28101 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28103 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
28104 info->first_fp_reg_save + i);
28106 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28107 if (flag_shrink_wrap
28108 && save_reg_p (info->first_fp_reg_save + i))
28109 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28111 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0);
28112 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12);
28113 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7);
28114 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8);
28116 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28117 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28119 if (flag_shrink_wrap)
28121 REG_NOTES (insn) = cfa_restores;
28122 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28123 RTX_FRAME_RELATED_P (insn) = 1;
28128 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28130 frame_off = info->total_size;
28132 /* Restore AltiVec registers if we must do so before adjusting the
28134 if (info->altivec_size != 0
28135 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28136 || (DEFAULT_ABI != ABI_V4
28137 && offset_below_red_zone_p (info->altivec_save_offset))))
28140 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28142 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28143 if (use_backchain_to_restore_sp)
28145 int frame_regno = 11;
28147 if ((strategy & REST_INLINE_VRS) == 0)
28149 /* Of r11 and r12, select the one not clobbered by an
28150 out-of-line restore function for the frame register. */
28151 frame_regno = 11 + 12 - scratch_regno;
28153 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28154 emit_move_insn (frame_reg_rtx,
28155 gen_rtx_MEM (Pmode, sp_reg_rtx));
28158 else if (frame_pointer_needed)
28159 frame_reg_rtx = hard_frame_pointer_rtx;
28161 if ((strategy & REST_INLINE_VRS) == 0)
28163 int end_save = info->altivec_save_offset + info->altivec_size;
28165 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28166 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28168 if (end_save + frame_off != 0)
28170 rtx offset = GEN_INT (end_save + frame_off);
28172 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28175 emit_move_insn (ptr_reg, frame_reg_rtx);
28177 ptr_off = -end_save;
28178 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28179 info->altivec_save_offset + ptr_off,
28180 0, V4SImode, SAVRES_VR);
28184 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28185 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28187 rtx addr, areg, mem, insn;
28188 rtx reg = gen_rtx_REG (V4SImode, i);
28189 HOST_WIDE_INT offset
28190 = (info->altivec_save_offset + frame_off
28191 + 16 * (i - info->first_altivec_reg_save));
28193 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28195 mem = gen_frame_mem (V4SImode,
28196 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28197 GEN_INT (offset)));
28198 insn = gen_rtx_SET (reg, mem);
28202 areg = gen_rtx_REG (Pmode, 0);
28203 emit_move_insn (areg, GEN_INT (offset));
28205 /* AltiVec addressing mode is [reg+reg]. */
28206 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28207 mem = gen_frame_mem (V4SImode, addr);
28209 /* Rather than emitting a generic move, force use of the
28210 lvx instruction, which we always want. In particular we
28211 don't want lxvd2x/xxpermdi for little endian. */
28212 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28215 (void) emit_insn (insn);
28219 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28220 if (((strategy & REST_INLINE_VRS) == 0
28221 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28222 && (flag_shrink_wrap
28223 || (offset_below_red_zone_p
28224 (info->altivec_save_offset
28225 + 16 * (i - info->first_altivec_reg_save))))
28228 rtx reg = gen_rtx_REG (V4SImode, i);
28229 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28233 /* Restore VRSAVE if we must do so before adjusting the stack. */
28234 if (info->vrsave_size != 0
28235 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28236 || (DEFAULT_ABI != ABI_V4
28237 && offset_below_red_zone_p (info->vrsave_save_offset))))
28241 if (frame_reg_rtx == sp_reg_rtx)
28243 if (use_backchain_to_restore_sp)
28245 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28246 emit_move_insn (frame_reg_rtx,
28247 gen_rtx_MEM (Pmode, sp_reg_rtx));
28250 else if (frame_pointer_needed)
28251 frame_reg_rtx = hard_frame_pointer_rtx;
28254 reg = gen_rtx_REG (SImode, 12);
28255 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28256 info->vrsave_save_offset + frame_off));
28258 emit_insn (generate_set_vrsave (reg, info, 1));
28262 /* If we have a large stack frame, restore the old stack pointer
28263 using the backchain. */
28264 if (use_backchain_to_restore_sp)
28266 if (frame_reg_rtx == sp_reg_rtx)
28268 /* Under V.4, don't reset the stack pointer until after we're done
28269 loading the saved registers. */
28270 if (DEFAULT_ABI == ABI_V4)
28271 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28273 insn = emit_move_insn (frame_reg_rtx,
28274 gen_rtx_MEM (Pmode, sp_reg_rtx));
28277 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28278 && DEFAULT_ABI == ABI_V4)
28279 /* frame_reg_rtx has been set up by the altivec restore. */
28283 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28284 frame_reg_rtx = sp_reg_rtx;
28287 /* If we have a frame pointer, we can restore the old stack pointer
28289 else if (frame_pointer_needed)
28291 frame_reg_rtx = sp_reg_rtx;
28292 if (DEFAULT_ABI == ABI_V4)
28293 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28294 /* Prevent reordering memory accesses against stack pointer restore. */
28295 else if (cfun->calls_alloca
28296 || offset_below_red_zone_p (-info->total_size))
28297 rs6000_emit_stack_tie (frame_reg_rtx, true);
28299 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28300 GEN_INT (info->total_size)));
28303 else if (info->push_p
28304 && DEFAULT_ABI != ABI_V4
28305 && epilogue_type != EPILOGUE_TYPE_EH_RETURN)
28307 /* Prevent reordering memory accesses against stack pointer restore. */
28308 if (cfun->calls_alloca
28309 || offset_below_red_zone_p (-info->total_size))
28310 rs6000_emit_stack_tie (frame_reg_rtx, false);
28311 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28312 GEN_INT (info->total_size)));
28315 if (insn && frame_reg_rtx == sp_reg_rtx)
28319 REG_NOTES (insn) = cfa_restores;
28320 cfa_restores = NULL_RTX;
28322 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28323 RTX_FRAME_RELATED_P (insn) = 1;
28326 /* Restore AltiVec registers if we have not done so already. */
28327 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28328 && info->altivec_size != 0
28329 && (DEFAULT_ABI == ABI_V4
28330 || !offset_below_red_zone_p (info->altivec_save_offset)))
28334 if ((strategy & REST_INLINE_VRS) == 0)
28336 int end_save = info->altivec_save_offset + info->altivec_size;
28338 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28339 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28340 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28342 if (end_save + frame_off != 0)
28344 rtx offset = GEN_INT (end_save + frame_off);
28346 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28349 emit_move_insn (ptr_reg, frame_reg_rtx);
28351 ptr_off = -end_save;
28352 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28353 info->altivec_save_offset + ptr_off,
28354 0, V4SImode, SAVRES_VR);
28355 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28357 /* Frame reg was clobbered by out-of-line save. Restore it
28358 from ptr_reg, and if we are calling out-of-line gpr or
28359 fpr restore set up the correct pointer and offset. */
28360 unsigned newptr_regno = 1;
28361 if (!restoring_GPRs_inline)
28363 bool lr = info->gp_save_offset + info->gp_size == 0;
28364 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28365 newptr_regno = ptr_regno_for_savres (sel);
28366 end_save = info->gp_save_offset + info->gp_size;
28368 else if (!restoring_FPRs_inline)
28370 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28371 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28372 newptr_regno = ptr_regno_for_savres (sel);
28373 end_save = info->fp_save_offset + info->fp_size;
28376 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28377 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28379 if (end_save + ptr_off != 0)
28381 rtx offset = GEN_INT (end_save + ptr_off);
28383 frame_off = -end_save;
28385 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28388 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28393 frame_off = ptr_off;
28394 emit_move_insn (frame_reg_rtx, ptr_reg);
28400 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28401 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28403 rtx addr, areg, mem, insn;
28404 rtx reg = gen_rtx_REG (V4SImode, i);
28405 HOST_WIDE_INT offset
28406 = (info->altivec_save_offset + frame_off
28407 + 16 * (i - info->first_altivec_reg_save));
28409 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28411 mem = gen_frame_mem (V4SImode,
28412 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28413 GEN_INT (offset)));
28414 insn = gen_rtx_SET (reg, mem);
28418 areg = gen_rtx_REG (Pmode, 0);
28419 emit_move_insn (areg, GEN_INT (offset));
28421 /* AltiVec addressing mode is [reg+reg]. */
28422 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28423 mem = gen_frame_mem (V4SImode, addr);
28425 /* Rather than emitting a generic move, force use of the
28426 lvx instruction, which we always want. In particular we
28427 don't want lxvd2x/xxpermdi for little endian. */
28428 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28431 (void) emit_insn (insn);
28435 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28436 if (((strategy & REST_INLINE_VRS) == 0
28437 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28438 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28441 rtx reg = gen_rtx_REG (V4SImode, i);
28442 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28446 /* Restore VRSAVE if we have not done so already. */
28447 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28448 && info->vrsave_size != 0
28449 && (DEFAULT_ABI == ABI_V4
28450 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28454 reg = gen_rtx_REG (SImode, 12);
28455 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28456 info->vrsave_save_offset + frame_off));
28458 emit_insn (generate_set_vrsave (reg, info, 1));
28461 /* If we exit by an out-of-line restore function on ABI_V4 then that
28462 function will deallocate the stack, so we don't need to worry
28463 about the unwinder restoring cr from an invalid stack frame
28465 bool exit_func = (!restoring_FPRs_inline
28466 || (!restoring_GPRs_inline
28467 && info->first_fp_reg_save == 64));
28469 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28470 *separate* slots if the routine calls __builtin_eh_return, so
28471 that they can be independently restored by the unwinder. */
28472 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28474 int i, cr_off = info->ehcr_offset;
28476 for (i = 0; i < 8; i++)
28477 if (!call_used_regs[CR0_REGNO + i])
28479 rtx reg = gen_rtx_REG (SImode, 0);
28480 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28481 cr_off + frame_off));
28483 insn = emit_insn (gen_movsi_to_cr_one
28484 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28486 if (!exit_func && flag_shrink_wrap)
28488 add_reg_note (insn, REG_CFA_RESTORE,
28489 gen_rtx_REG (SImode, CR0_REGNO + i));
28491 RTX_FRAME_RELATED_P (insn) = 1;
28494 cr_off += reg_size;
28498 /* Get the old lr if we saved it. If we are restoring registers
28499 out-of-line, then the out-of-line routines can do this for us. */
28500 if (restore_lr && restoring_GPRs_inline)
28501 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28503 /* Get the old cr if we saved it. */
28504 if (info->cr_save_p)
28506 unsigned cr_save_regno = 12;
28508 if (!restoring_GPRs_inline)
28510 /* Ensure we don't use the register used by the out-of-line
28511 gpr register restore below. */
28512 bool lr = info->gp_save_offset + info->gp_size == 0;
28513 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28514 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28516 if (gpr_ptr_regno == 12)
28517 cr_save_regno = 11;
28518 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28520 else if (REGNO (frame_reg_rtx) == 12)
28521 cr_save_regno = 11;
28523 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28524 info->cr_save_offset + frame_off,
28528 /* Set LR here to try to overlap restores below. */
28529 if (restore_lr && restoring_GPRs_inline)
28530 restore_saved_lr (0, exit_func);
28532 /* Load exception handler data registers, if needed. */
28533 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28535 unsigned int i, regno;
28539 rtx reg = gen_rtx_REG (reg_mode, 2);
28540 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28541 frame_off + RS6000_TOC_SAVE_SLOT));
28548 regno = EH_RETURN_DATA_REGNO (i);
28549 if (regno == INVALID_REGNUM)
28552 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28553 info->ehrd_offset + frame_off
28554 + reg_size * (int) i);
28556 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28560 /* Restore GPRs. This is done as a PARALLEL if we are using
28561 the load-multiple instructions. */
28562 if (!restoring_GPRs_inline)
28564 /* We are jumping to an out-of-line function. */
28566 int end_save = info->gp_save_offset + info->gp_size;
28567 bool can_use_exit = end_save == 0;
28568 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28571 /* Emit stack reset code if we need it. */
28572 ptr_regno = ptr_regno_for_savres (sel);
28573 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28575 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28576 else if (end_save + frame_off != 0)
28577 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28578 GEN_INT (end_save + frame_off)));
28579 else if (REGNO (frame_reg_rtx) != ptr_regno)
28580 emit_move_insn (ptr_reg, frame_reg_rtx);
28581 if (REGNO (frame_reg_rtx) == ptr_regno)
28582 frame_off = -end_save;
28584 if (can_use_exit && info->cr_save_p)
28585 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28587 ptr_off = -end_save;
28588 rs6000_emit_savres_rtx (info, ptr_reg,
28589 info->gp_save_offset + ptr_off,
28590 info->lr_save_offset + ptr_off,
28593 else if (using_load_multiple)
28596 p = rtvec_alloc (32 - info->first_gp_reg_save);
28597 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28599 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28601 info->gp_save_offset + frame_off + reg_size * i);
28602 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28606 int offset = info->gp_save_offset + frame_off;
28607 for (i = info->first_gp_reg_save; i < 32; i++)
28610 && !cfun->machine->gpr_is_wrapped_separately[i])
28612 rtx reg = gen_rtx_REG (reg_mode, i);
28613 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28616 offset += reg_size;
28620 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28622 /* If the frame pointer was used then we can't delay emitting
28623 a REG_CFA_DEF_CFA note. This must happen on the insn that
28624 restores the frame pointer, r31. We may have already emitted
28625 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28626 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28627 be harmless if emitted. */
28628 if (frame_pointer_needed)
28630 insn = get_last_insn ();
28631 add_reg_note (insn, REG_CFA_DEF_CFA,
28632 plus_constant (Pmode, frame_reg_rtx, frame_off));
28633 RTX_FRAME_RELATED_P (insn) = 1;
28636 /* Set up cfa_restores. We always need these when
28637 shrink-wrapping. If not shrink-wrapping then we only need
28638 the cfa_restore when the stack location is no longer valid.
28639 The cfa_restores must be emitted on or before the insn that
28640 invalidates the stack, and of course must not be emitted
28641 before the insn that actually does the restore. The latter
28642 is why it is a bad idea to emit the cfa_restores as a group
28643 on the last instruction here that actually does a restore:
28644 That insn may be reordered with respect to others doing
28646 if (flag_shrink_wrap
28647 && !restoring_GPRs_inline
28648 && info->first_fp_reg_save == 64)
28649 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28651 for (i = info->first_gp_reg_save; i < 32; i++)
28653 && !cfun->machine->gpr_is_wrapped_separately[i])
28655 rtx reg = gen_rtx_REG (reg_mode, i);
28656 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28660 if (!restoring_GPRs_inline
28661 && info->first_fp_reg_save == 64)
28663 /* We are jumping to an out-of-line function. */
28665 emit_cfa_restores (cfa_restores);
28669 if (restore_lr && !restoring_GPRs_inline)
28671 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28672 restore_saved_lr (0, exit_func);
28675 /* Restore fpr's if we need to do it without calling a function. */
28676 if (restoring_FPRs_inline)
28678 int offset = info->fp_save_offset + frame_off;
28679 for (i = info->first_fp_reg_save; i < 64; i++)
28682 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28684 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28685 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28686 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28687 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28691 offset += fp_reg_size;
28695 /* If we saved cr, restore it here. Just those that were used. */
28696 if (info->cr_save_p)
28697 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28699 /* If this is V.4, unwind the stack pointer after all of the loads
28700 have been done, or set up r11 if we are restoring fp out of line. */
28702 if (!restoring_FPRs_inline)
28704 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28705 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28706 ptr_regno = ptr_regno_for_savres (sel);
28709 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28710 if (REGNO (frame_reg_rtx) == ptr_regno)
28713 if (insn && restoring_FPRs_inline)
28717 REG_NOTES (insn) = cfa_restores;
28718 cfa_restores = NULL_RTX;
28720 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28721 RTX_FRAME_RELATED_P (insn) = 1;
28724 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28726 rtx sa = EH_RETURN_STACKADJ_RTX;
28727 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28730 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline)
28734 /* We can't hang the cfa_restores off a simple return,
28735 since the shrink-wrap code sometimes uses an existing
28736 return. This means there might be a path from
28737 pre-prologue code to this return, and dwarf2cfi code
28738 wants the eh_frame unwinder state to be the same on
28739 all paths to any point. So we need to emit the
28740 cfa_restores before the return. For -m64 we really
28741 don't need epilogue cfa_restores at all, except for
28742 this irritating dwarf2cfi with shrink-wrap
28743 requirement; The stack red-zone means eh_frame info
28744 from the prologue telling the unwinder to restore
28745 from the stack is perfectly good right to the end of
28747 emit_insn (gen_blockage ());
28748 emit_cfa_restores (cfa_restores);
28749 cfa_restores = NULL_RTX;
28752 emit_jump_insn (targetm.gen_simple_return ());
28755 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline)
28757 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28758 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28760 RTVEC_ELT (p, elt++) = ret_rtx;
28762 RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
28764 /* We have to restore more than two FP registers, so branch to the
28765 restore function. It will return to our caller. */
28770 if (flag_shrink_wrap)
28771 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28773 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28774 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28775 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28776 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28778 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28780 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28782 RTVEC_ELT (p, elt++)
28783 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28784 if (flag_shrink_wrap
28785 && save_reg_p (info->first_fp_reg_save + i))
28786 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28789 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28794 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28795 /* Ensure the cfa_restores are hung off an insn that won't
28796 be reordered above other restores. */
28797 emit_insn (gen_blockage ());
28799 emit_cfa_restores (cfa_restores);
28803 /* Write function epilogue. */
28806 rs6000_output_function_epilogue (FILE *file)
28809 macho_branch_islands ();
28812 rtx_insn *insn = get_last_insn ();
28813 rtx_insn *deleted_debug_label = NULL;
28815 /* Mach-O doesn't support labels at the end of objects, so if
28816 it looks like we might want one, take special action.
28818 First, collect any sequence of deleted debug labels. */
28821 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28823 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28824 notes only, instead set their CODE_LABEL_NUMBER to -1,
28825 otherwise there would be code generation differences
28826 in between -g and -g0. */
28827 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28828 deleted_debug_label = insn;
28829 insn = PREV_INSN (insn);
28832 /* Second, if we have:
28835 then this needs to be detected, so skip past the barrier. */
28837 if (insn && BARRIER_P (insn))
28838 insn = PREV_INSN (insn);
28840 /* Up to now we've only seen notes or barriers. */
28845 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28846 /* Trailing label: <barrier>. */
28847 fputs ("\tnop\n", file);
28850 /* Lastly, see if we have a completely empty function body. */
28851 while (insn && ! INSN_P (insn))
28852 insn = PREV_INSN (insn);
28853 /* If we don't find any insns, we've got an empty function body;
28854 I.e. completely empty - without a return or branch. This is
28855 taken as the case where a function body has been removed
28856 because it contains an inline __builtin_unreachable(). GCC
28857 states that reaching __builtin_unreachable() means UB so we're
28858 not obliged to do anything special; however, we want
28859 non-zero-sized function bodies. To meet this, and help the
28860 user out, let's trap the case. */
28862 fputs ("\ttrap\n", file);
28865 else if (deleted_debug_label)
28866 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28867 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28868 CODE_LABEL_NUMBER (insn) = -1;
28872 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28875 We don't output a traceback table if -finhibit-size-directive was
28876 used. The documentation for -finhibit-size-directive reads
28877 ``don't output a @code{.size} assembler directive, or anything
28878 else that would cause trouble if the function is split in the
28879 middle, and the two halves are placed at locations far apart in
28880 memory.'' The traceback table has this property, since it
28881 includes the offset from the start of the function to the
28882 traceback table itself.
28884 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28885 different traceback table. */
28886 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28887 && ! flag_inhibit_size_directive
28888 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28890 const char *fname = NULL;
28891 const char *language_string = lang_hooks.name;
28892 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28894 int optional_tbtab;
28895 rs6000_stack_t *info = rs6000_stack_info ();
28897 if (rs6000_traceback == traceback_full)
28898 optional_tbtab = 1;
28899 else if (rs6000_traceback == traceback_part)
28900 optional_tbtab = 0;
28902 optional_tbtab = !optimize_size && !TARGET_ELF;
28904 if (optional_tbtab)
28906 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28907 while (*fname == '.') /* V.4 encodes . in the name */
28910 /* Need label immediately before tbtab, so we can compute
28911 its offset from the function start. */
28912 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28913 ASM_OUTPUT_LABEL (file, fname);
28916 /* The .tbtab pseudo-op can only be used for the first eight
28917 expressions, since it can't handle the possibly variable
28918 length fields that follow. However, if you omit the optional
28919 fields, the assembler outputs zeros for all optional fields
28920 anyways, giving each variable length field is minimum length
28921 (as defined in sys/debug.h). Thus we cannot use the .tbtab
28922 pseudo-op at all. */
28924 /* An all-zero word flags the start of the tbtab, for debuggers
28925 that have to find it by searching forward from the entry
28926 point or from the current pc. */
28927 fputs ("\t.long 0\n", file);
28929 /* Tbtab format type. Use format type 0. */
28930 fputs ("\t.byte 0,", file);
28932 /* Language type. Unfortunately, there does not seem to be any
28933 official way to discover the language being compiled, so we
28934 use language_string.
28935 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28936 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28937 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28938 numbers either, so for now use 0. */
28940 || ! strcmp (language_string, "GNU GIMPLE")
28941 || ! strcmp (language_string, "GNU Go")
28942 || ! strcmp (language_string, "GNU D")
28943 || ! strcmp (language_string, "libgccjit"))
28945 else if (! strcmp (language_string, "GNU F77")
28946 || lang_GNU_Fortran ())
28948 else if (! strcmp (language_string, "GNU Ada"))
28950 else if (lang_GNU_CXX ()
28951 || ! strcmp (language_string, "GNU Objective-C++"))
28953 else if (! strcmp (language_string, "GNU Java"))
28955 else if (! strcmp (language_string, "GNU Objective-C"))
28958 gcc_unreachable ();
28959 fprintf (file, "%d,", i);
28961 /* 8 single bit fields: global linkage (not set for C extern linkage,
28962 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28963 from start of procedure stored in tbtab, internal function, function
28964 has controlled storage, function has no toc, function uses fp,
28965 function logs/aborts fp operations. */
28966 /* Assume that fp operations are used if any fp reg must be saved. */
28967 fprintf (file, "%d,",
28968 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28970 /* 6 bitfields: function is interrupt handler, name present in
28971 proc table, function calls alloca, on condition directives
28972 (controls stack walks, 3 bits), saves condition reg, saves
28974 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28975 set up as a frame pointer, even when there is no alloca call. */
28976 fprintf (file, "%d,",
28977 ((optional_tbtab << 6)
28978 | ((optional_tbtab & frame_pointer_needed) << 5)
28979 | (info->cr_save_p << 1)
28980 | (info->lr_save_p)));
28982 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28984 fprintf (file, "%d,",
28985 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28987 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28988 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28990 if (optional_tbtab)
28992 /* Compute the parameter info from the function decl argument
28995 int next_parm_info_bit = 31;
28997 for (decl = DECL_ARGUMENTS (current_function_decl);
28998 decl; decl = DECL_CHAIN (decl))
29000 rtx parameter = DECL_INCOMING_RTL (decl);
29001 machine_mode mode = GET_MODE (parameter);
29003 if (REG_P (parameter))
29005 if (SCALAR_FLOAT_MODE_P (mode))
29028 gcc_unreachable ();
29031 /* If only one bit will fit, don't or in this entry. */
29032 if (next_parm_info_bit > 0)
29033 parm_info |= (bits << (next_parm_info_bit - 1));
29034 next_parm_info_bit -= 2;
29038 fixed_parms += ((GET_MODE_SIZE (mode)
29039 + (UNITS_PER_WORD - 1))
29041 next_parm_info_bit -= 1;
29047 /* Number of fixed point parameters. */
29048 /* This is actually the number of words of fixed point parameters; thus
29049 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29050 fprintf (file, "%d,", fixed_parms);
29052 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29054 /* This is actually the number of fp registers that hold parameters;
29055 and thus the maximum value is 13. */
29056 /* Set parameters on stack bit if parameters are not in their original
29057 registers, regardless of whether they are on the stack? Xlc
29058 seems to set the bit when not optimizing. */
29059 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29061 if (optional_tbtab)
29063 /* Optional fields follow. Some are variable length. */
29065 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29066 float, 11 double float. */
29067 /* There is an entry for each parameter in a register, in the order
29068 that they occur in the parameter list. Any intervening arguments
29069 on the stack are ignored. If the list overflows a long (max
29070 possible length 34 bits) then completely leave off all elements
29072 /* Only emit this long if there was at least one parameter. */
29073 if (fixed_parms || float_parms)
29074 fprintf (file, "\t.long %d\n", parm_info);
29076 /* Offset from start of code to tb table. */
29077 fputs ("\t.long ", file);
29078 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29079 RS6000_OUTPUT_BASENAME (file, fname);
29081 rs6000_output_function_entry (file, fname);
29084 /* Interrupt handler mask. */
29085 /* Omit this long, since we never set the interrupt handler bit
29088 /* Number of CTL (controlled storage) anchors. */
29089 /* Omit this long, since the has_ctl bit is never set above. */
29091 /* Displacement into stack of each CTL anchor. */
29092 /* Omit this list of longs, because there are no CTL anchors. */
29094 /* Length of function name. */
29097 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29099 /* Function name. */
29100 assemble_string (fname, strlen (fname));
29102 /* Register for alloca automatic storage; this is always reg 31.
29103 Only emit this if the alloca bit was set above. */
29104 if (frame_pointer_needed)
29105 fputs ("\t.byte 31\n", file);
29107 fputs ("\t.align 2\n", file);
29111 /* Arrange to define .LCTOC1 label, if not already done. */
29115 if (!toc_initialized)
29117 switch_to_section (toc_section);
29118 switch_to_section (current_function_section ());
29123 /* -fsplit-stack support. */
29125 /* A SYMBOL_REF for __morestack. */
29126 static GTY(()) rtx morestack_ref;
29129 gen_add3_const (rtx rt, rtx ra, long c)
29132 return gen_adddi3 (rt, ra, GEN_INT (c));
29134 return gen_addsi3 (rt, ra, GEN_INT (c));
29137 /* Emit -fsplit-stack prologue, which goes before the regular function
29138 prologue (at local entry point in the case of ELFv2). */
29141 rs6000_expand_split_stack_prologue (void)
29143 rs6000_stack_t *info = rs6000_stack_info ();
29144 unsigned HOST_WIDE_INT allocate;
29145 long alloc_hi, alloc_lo;
29146 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29149 gcc_assert (flag_split_stack && reload_completed);
29154 if (global_regs[29])
29156 error ("%qs uses register r29", "%<-fsplit-stack%>");
29157 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29158 "conflicts with %qD", global_regs_decl[29]);
29161 allocate = info->total_size;
29162 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29164 sorry ("Stack frame larger than 2G is not supported for "
29165 "%<-fsplit-stack%>");
29168 if (morestack_ref == NULL_RTX)
29170 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29171 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29172 | SYMBOL_FLAG_FUNCTION);
29175 r0 = gen_rtx_REG (Pmode, 0);
29176 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29177 r12 = gen_rtx_REG (Pmode, 12);
29178 emit_insn (gen_load_split_stack_limit (r0));
29179 /* Always emit two insns here to calculate the requested stack,
29180 so that the linker can edit them when adjusting size for calling
29181 non-split-stack code. */
29182 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29183 alloc_lo = -allocate - alloc_hi;
29186 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29188 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29190 emit_insn (gen_nop ());
29194 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29195 emit_insn (gen_nop ());
29198 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29199 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29200 ok_label = gen_label_rtx ();
29201 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29202 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29203 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29205 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29206 JUMP_LABEL (insn) = ok_label;
29207 /* Mark the jump as very likely to be taken. */
29208 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29210 lr = gen_rtx_REG (Pmode, LR_REGNO);
29211 insn = emit_move_insn (r0, lr);
29212 RTX_FRAME_RELATED_P (insn) = 1;
29213 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29214 RTX_FRAME_RELATED_P (insn) = 1;
29216 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29217 const0_rtx, const0_rtx));
29218 call_fusage = NULL_RTX;
29219 use_reg (&call_fusage, r12);
29220 /* Say the call uses r0, even though it doesn't, to stop regrename
29221 from twiddling with the insns saving lr, trashing args for cfun.
29222 The insns restoring lr are similarly protected by making
29223 split_stack_return use r0. */
29224 use_reg (&call_fusage, r0);
29225 add_function_usage_to (insn, call_fusage);
29226 /* Indicate that this function can't jump to non-local gotos. */
29227 make_reg_eh_region_note_nothrow_nononlocal (insn);
29228 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29229 insn = emit_move_insn (lr, r0);
29230 add_reg_note (insn, REG_CFA_RESTORE, lr);
29231 RTX_FRAME_RELATED_P (insn) = 1;
29232 emit_insn (gen_split_stack_return ());
29234 emit_label (ok_label);
29235 LABEL_NUSES (ok_label) = 1;
29238 /* Return the internal arg pointer used for function incoming
29239 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29240 to copy it to a pseudo in order for it to be preserved over calls
29241 and suchlike. We'd really like to use a pseudo here for the
29242 internal arg pointer but data-flow analysis is not prepared to
29243 accept pseudos as live at the beginning of a function. */
29246 rs6000_internal_arg_pointer (void)
29248 if (flag_split_stack
29249 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29253 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29257 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29258 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29260 /* Put the pseudo initialization right after the note at the
29261 beginning of the function. */
29262 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29263 gen_rtx_REG (Pmode, 12));
29264 push_topmost_sequence ();
29265 emit_insn_after (pat, get_insns ());
29266 pop_topmost_sequence ();
29268 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29269 FIRST_PARM_OFFSET (current_function_decl));
29270 return copy_to_reg (ret);
29272 return virtual_incoming_args_rtx;
29275 /* We may have to tell the dataflow pass that the split stack prologue
29276 is initializing a register. */
29279 rs6000_live_on_entry (bitmap regs)
29281 if (flag_split_stack)
29282 bitmap_set_bit (regs, 12);
29285 /* Emit -fsplit-stack dynamic stack allocation space check. */
29288 rs6000_split_stack_space_check (rtx size, rtx label)
29290 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29291 rtx limit = gen_reg_rtx (Pmode);
29292 rtx requested = gen_reg_rtx (Pmode);
29293 rtx cmp = gen_reg_rtx (CCUNSmode);
29296 emit_insn (gen_load_split_stack_limit (limit));
29297 if (CONST_INT_P (size))
29298 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29301 size = force_reg (Pmode, size);
29302 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29304 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29305 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29306 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29307 gen_rtx_LABEL_REF (VOIDmode, label),
29309 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29310 JUMP_LABEL (jump) = label;
29313 /* A C compound statement that outputs the assembler code for a thunk
29314 function, used to implement C++ virtual function calls with
29315 multiple inheritance. The thunk acts as a wrapper around a virtual
29316 function, adjusting the implicit object parameter before handing
29317 control off to the real function.
29319 First, emit code to add the integer DELTA to the location that
29320 contains the incoming first argument. Assume that this argument
29321 contains a pointer, and is the one used to pass the `this' pointer
29322 in C++. This is the incoming argument *before* the function
29323 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29324 values of all other incoming arguments.
29326 After the addition, emit code to jump to FUNCTION, which is a
29327 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29328 not touch the return address. Hence returning from FUNCTION will
29329 return to whoever called the current `thunk'.
29331 The effect must be as if FUNCTION had been called directly with the
29332 adjusted first argument. This macro is responsible for emitting
29333 all of the code for a thunk function; output_function_prologue()
29334 and output_function_epilogue() are not invoked.
29336 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29337 been extracted from it.) It might possibly be useful on some
29338 targets, but probably not.
29340 If you do not define this macro, the target-independent code in the
29341 C++ frontend will generate a less efficient heavyweight thunk that
29342 calls FUNCTION instead of jumping to it. The generic approach does
29343 not support varargs. */
29346 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29347 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29350 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
29351 rtx this_rtx, funexp;
29354 reload_completed = 1;
29355 epilogue_completed = 1;
29357 /* Mark the end of the (empty) prologue. */
29358 emit_note (NOTE_INSN_PROLOGUE_END);
29360 /* Find the "this" pointer. If the function returns a structure,
29361 the structure return pointer is in r3. */
29362 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29363 this_rtx = gen_rtx_REG (Pmode, 4);
29365 this_rtx = gen_rtx_REG (Pmode, 3);
29367 /* Apply the constant offset, if required. */
29369 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29371 /* Apply the offset from the vtable, if required. */
29374 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29375 rtx tmp = gen_rtx_REG (Pmode, 12);
29377 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29378 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29380 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29381 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29385 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29387 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29389 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29392 /* Generate a tail call to the target function. */
29393 if (!TREE_USED (function))
29395 assemble_external (function);
29396 TREE_USED (function) = 1;
29398 funexp = XEXP (DECL_RTL (function), 0);
29399 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29402 if (MACHOPIC_INDIRECT)
29403 funexp = machopic_indirect_call_target (funexp);
29406 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29407 generate sibcall RTL explicitly. */
29408 insn = emit_call_insn (
29409 gen_rtx_PARALLEL (VOIDmode,
29411 gen_rtx_CALL (VOIDmode,
29412 funexp, const0_rtx),
29413 gen_rtx_USE (VOIDmode, const0_rtx),
29414 simple_return_rtx)));
29415 SIBLING_CALL_P (insn) = 1;
29418 /* Run just enough of rest_of_compilation to get the insns emitted.
29419 There's not really enough bulk here to make other passes such as
29420 instruction scheduling worth while. */
29421 insn = get_insns ();
29422 shorten_branches (insn);
29423 assemble_start_function (thunk_fndecl, fnname);
29424 final_start_function (insn, file, 1);
29425 final (insn, file, 1);
29426 final_end_function ();
29427 assemble_end_function (thunk_fndecl, fnname);
29429 reload_completed = 0;
29430 epilogue_completed = 0;
29433 /* A quick summary of the various types of 'constant-pool tables'
29436 Target Flags Name One table per
29437 AIX (none) AIX TOC object file
29438 AIX -mfull-toc AIX TOC object file
29439 AIX -mminimal-toc AIX minimal TOC translation unit
29440 SVR4/EABI (none) SVR4 SDATA object file
29441 SVR4/EABI -fpic SVR4 pic object file
29442 SVR4/EABI -fPIC SVR4 PIC translation unit
29443 SVR4/EABI -mrelocatable EABI TOC function
29444 SVR4/EABI -maix AIX TOC object file
29445 SVR4/EABI -maix -mminimal-toc
29446 AIX minimal TOC translation unit
29448 Name Reg. Set by entries contains:
29449 made by addrs? fp? sum?
29451 AIX TOC 2 crt0 as Y option option
29452 AIX minimal TOC 30 prolog gcc Y Y option
29453 SVR4 SDATA 13 crt0 gcc N Y N
29454 SVR4 pic 30 prolog ld Y not yet N
29455 SVR4 PIC 30 prolog gcc Y option option
29456 EABI TOC 30 prolog gcc Y option option
29460 /* Hash functions for the hash table. */
29463 rs6000_hash_constant (rtx k)
29465 enum rtx_code code = GET_CODE (k);
29466 machine_mode mode = GET_MODE (k);
29467 unsigned result = (code << 3) ^ mode;
29468 const char *format;
29471 format = GET_RTX_FORMAT (code);
29472 flen = strlen (format);
29478 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29480 case CONST_WIDE_INT:
29483 flen = CONST_WIDE_INT_NUNITS (k);
29484 for (i = 0; i < flen; i++)
29485 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29490 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29500 for (; fidx < flen; fidx++)
29501 switch (format[fidx])
29506 const char *str = XSTR (k, fidx);
29507 len = strlen (str);
29508 result = result * 613 + len;
29509 for (i = 0; i < len; i++)
29510 result = result * 613 + (unsigned) str[i];
29515 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29519 result = result * 613 + (unsigned) XINT (k, fidx);
29522 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29523 result = result * 613 + (unsigned) XWINT (k, fidx);
29527 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29528 result = result * 613 + (unsigned) (XWINT (k, fidx)
29535 gcc_unreachable ();
29542 toc_hasher::hash (toc_hash_struct *thc)
29544 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29547 /* Compare H1 and H2 for equivalence. */
29550 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29555 if (h1->key_mode != h2->key_mode)
29558 return rtx_equal_p (r1, r2);
29561 /* These are the names given by the C++ front-end to vtables, and
29562 vtable-like objects. Ideally, this logic should not be here;
29563 instead, there should be some programmatic way of inquiring as
29564 to whether or not an object is a vtable. */
29566 #define VTABLE_NAME_P(NAME) \
29567 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29568 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29569 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29570 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29571 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29573 #ifdef NO_DOLLAR_IN_LABEL
29574 /* Return a GGC-allocated character string translating dollar signs in
29575 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29578 rs6000_xcoff_strip_dollar (const char *name)
29584 q = (const char *) strchr (name, '$');
29586 if (q == 0 || q == name)
29589 len = strlen (name);
29590 strip = XALLOCAVEC (char, len + 1);
29591 strcpy (strip, name);
29592 p = strip + (q - name);
29596 p = strchr (p + 1, '$');
29599 return ggc_alloc_string (strip, len);
29604 rs6000_output_symbol_ref (FILE *file, rtx x)
29606 const char *name = XSTR (x, 0);
29608 /* Currently C++ toc references to vtables can be emitted before it
29609 is decided whether the vtable is public or private. If this is
29610 the case, then the linker will eventually complain that there is
29611 a reference to an unknown section. Thus, for vtables only,
29612 we emit the TOC reference to reference the identifier and not the
29614 if (VTABLE_NAME_P (name))
29616 RS6000_OUTPUT_BASENAME (file, name);
29619 assemble_name (file, name);
29622 /* Output a TOC entry. We derive the entry name from what is being
29626 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29629 const char *name = buf;
29631 HOST_WIDE_INT offset = 0;
29633 gcc_assert (!TARGET_NO_TOC);
29635 /* When the linker won't eliminate them, don't output duplicate
29636 TOC entries (this happens on AIX if there is any kind of TOC,
29637 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29639 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29641 struct toc_hash_struct *h;
29643 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29644 time because GGC is not initialized at that point. */
29645 if (toc_hash_table == NULL)
29646 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29648 h = ggc_alloc<toc_hash_struct> ();
29650 h->key_mode = mode;
29651 h->labelno = labelno;
29653 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29654 if (*found == NULL)
29656 else /* This is indeed a duplicate.
29657 Set this label equal to that label. */
29659 fputs ("\t.set ", file);
29660 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29661 fprintf (file, "%d,", labelno);
29662 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29663 fprintf (file, "%d\n", ((*found)->labelno));
29666 if (TARGET_XCOFF && SYMBOL_REF_P (x)
29667 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29668 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29670 fputs ("\t.set ", file);
29671 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29672 fprintf (file, "%d,", labelno);
29673 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29674 fprintf (file, "%d\n", ((*found)->labelno));
29681 /* If we're going to put a double constant in the TOC, make sure it's
29682 aligned properly when strict alignment is on. */
29683 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29684 && STRICT_ALIGNMENT
29685 && GET_MODE_BITSIZE (mode) >= 64
29686 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29687 ASM_OUTPUT_ALIGN (file, 3);
29690 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29692 /* Handle FP constants specially. Note that if we have a minimal
29693 TOC, things we put here aren't actually in the TOC, so we can allow
29695 if (CONST_DOUBLE_P (x)
29696 && (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29697 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29701 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29702 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29704 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29708 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29709 fputs (DOUBLE_INT_ASM_OP, file);
29711 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29712 k[0] & 0xffffffff, k[1] & 0xffffffff,
29713 k[2] & 0xffffffff, k[3] & 0xffffffff);
29714 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29715 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29716 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29717 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29718 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29723 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29724 fputs ("\t.long ", file);
29726 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29727 k[0] & 0xffffffff, k[1] & 0xffffffff,
29728 k[2] & 0xffffffff, k[3] & 0xffffffff);
29729 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29730 k[0] & 0xffffffff, k[1] & 0xffffffff,
29731 k[2] & 0xffffffff, k[3] & 0xffffffff);
29735 else if (CONST_DOUBLE_P (x)
29736 && (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29740 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29741 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29743 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29747 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29748 fputs (DOUBLE_INT_ASM_OP, file);
29750 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29751 k[0] & 0xffffffff, k[1] & 0xffffffff);
29752 fprintf (file, "0x%lx%08lx\n",
29753 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29754 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29759 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29760 fputs ("\t.long ", file);
29762 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29763 k[0] & 0xffffffff, k[1] & 0xffffffff);
29764 fprintf (file, "0x%lx,0x%lx\n",
29765 k[0] & 0xffffffff, k[1] & 0xffffffff);
29769 else if (CONST_DOUBLE_P (x)
29770 && (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29774 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29775 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29777 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29781 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29782 fputs (DOUBLE_INT_ASM_OP, file);
29784 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29785 if (WORDS_BIG_ENDIAN)
29786 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29788 fprintf (file, "0x%lx\n", l & 0xffffffff);
29793 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29794 fputs ("\t.long ", file);
29796 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29797 fprintf (file, "0x%lx\n", l & 0xffffffff);
29801 else if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
29803 unsigned HOST_WIDE_INT low;
29804 HOST_WIDE_INT high;
29806 low = INTVAL (x) & 0xffffffff;
29807 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29809 /* TOC entries are always Pmode-sized, so when big-endian
29810 smaller integer constants in the TOC need to be padded.
29811 (This is still a win over putting the constants in
29812 a separate constant pool, because then we'd have
29813 to have both a TOC entry _and_ the actual constant.)
29815 For a 32-bit target, CONST_INT values are loaded and shifted
29816 entirely within `low' and can be stored in one TOC entry. */
29818 /* It would be easy to make this work, but it doesn't now. */
29819 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29821 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29824 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29825 high = (HOST_WIDE_INT) low >> 32;
29831 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29832 fputs (DOUBLE_INT_ASM_OP, file);
29834 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29835 (long) high & 0xffffffff, (long) low & 0xffffffff);
29836 fprintf (file, "0x%lx%08lx\n",
29837 (long) high & 0xffffffff, (long) low & 0xffffffff);
29842 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29844 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29845 fputs ("\t.long ", file);
29847 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29848 (long) high & 0xffffffff, (long) low & 0xffffffff);
29849 fprintf (file, "0x%lx,0x%lx\n",
29850 (long) high & 0xffffffff, (long) low & 0xffffffff);
29854 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29855 fputs ("\t.long ", file);
29857 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29858 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29864 if (GET_CODE (x) == CONST)
29866 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29867 && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
29869 base = XEXP (XEXP (x, 0), 0);
29870 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29873 switch (GET_CODE (base))
29876 name = XSTR (base, 0);
29880 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29881 CODE_LABEL_NUMBER (XEXP (base, 0)));
29885 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29889 gcc_unreachable ();
29892 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29893 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29896 fputs ("\t.tc ", file);
29897 RS6000_OUTPUT_BASENAME (file, name);
29900 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29902 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29904 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29905 after other TOC symbols, reducing overflow of small TOC access
29906 to [TC] symbols. */
29907 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29908 ? "[TE]," : "[TC],", file);
29911 /* Currently C++ toc references to vtables can be emitted before it
29912 is decided whether the vtable is public or private. If this is
29913 the case, then the linker will eventually complain that there is
29914 a TOC reference to an unknown section. Thus, for vtables only,
29915 we emit the TOC reference to reference the symbol and not the
29917 if (VTABLE_NAME_P (name))
29919 RS6000_OUTPUT_BASENAME (file, name);
29921 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29922 else if (offset > 0)
29923 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29926 output_addr_const (file, x);
29929 if (TARGET_XCOFF && SYMBOL_REF_P (base))
29931 switch (SYMBOL_REF_TLS_MODEL (base))
29935 case TLS_MODEL_LOCAL_EXEC:
29936 fputs ("@le", file);
29938 case TLS_MODEL_INITIAL_EXEC:
29939 fputs ("@ie", file);
29941 /* Use global-dynamic for local-dynamic. */
29942 case TLS_MODEL_GLOBAL_DYNAMIC:
29943 case TLS_MODEL_LOCAL_DYNAMIC:
29945 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29946 fputs ("\t.tc .", file);
29947 RS6000_OUTPUT_BASENAME (file, name);
29948 fputs ("[TC],", file);
29949 output_addr_const (file, x);
29950 fputs ("@m", file);
29953 gcc_unreachable ();
29961 /* Output an assembler pseudo-op to write an ASCII string of N characters
29962 starting at P to FILE.
29964 On the RS/6000, we have to do this using the .byte operation and
29965 write out special characters outside the quoted string.
29966 Also, the assembler is broken; very long strings are truncated,
29967 so we must artificially break them up early. */
29970 output_ascii (FILE *file, const char *p, int n)
29973 int i, count_string;
29974 const char *for_string = "\t.byte \"";
29975 const char *for_decimal = "\t.byte ";
29976 const char *to_close = NULL;
29979 for (i = 0; i < n; i++)
29982 if (c >= ' ' && c < 0177)
29985 fputs (for_string, file);
29988 /* Write two quotes to get one. */
29996 for_decimal = "\"\n\t.byte ";
30000 if (count_string >= 512)
30002 fputs (to_close, file);
30004 for_string = "\t.byte \"";
30005 for_decimal = "\t.byte ";
30013 fputs (for_decimal, file);
30014 fprintf (file, "%d", c);
30016 for_string = "\n\t.byte \"";
30017 for_decimal = ", ";
30023 /* Now close the string if we have written one. Then end the line. */
30025 fputs (to_close, file);
30028 /* Generate a unique section name for FILENAME for a section type
30029 represented by SECTION_DESC. Output goes into BUF.
30031 SECTION_DESC can be any string, as long as it is different for each
30032 possible section type.
30034 We name the section in the same manner as xlc. The name begins with an
30035 underscore followed by the filename (after stripping any leading directory
30036 names) with the last period replaced by the string SECTION_DESC. If
30037 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30041 rs6000_gen_section_name (char **buf, const char *filename,
30042 const char *section_desc)
30044 const char *q, *after_last_slash, *last_period = 0;
30048 after_last_slash = filename;
30049 for (q = filename; *q; q++)
30052 after_last_slash = q + 1;
30053 else if (*q == '.')
30057 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30058 *buf = (char *) xmalloc (len);
30063 for (q = after_last_slash; *q; q++)
30065 if (q == last_period)
30067 strcpy (p, section_desc);
30068 p += strlen (section_desc);
30072 else if (ISALNUM (*q))
30076 if (last_period == 0)
30077 strcpy (p, section_desc);
30082 /* Emit profile function. */
30085 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30087 /* Non-standard profiling for kernels, which just saves LR then calls
30088 _mcount without worrying about arg saves. The idea is to change
30089 the function prologue as little as possible as it isn't easy to
30090 account for arg save/restore code added just for _mcount. */
30091 if (TARGET_PROFILE_KERNEL)
30094 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30096 #ifndef NO_PROFILE_COUNTERS
30097 # define NO_PROFILE_COUNTERS 0
30099 if (NO_PROFILE_COUNTERS)
30100 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30101 LCT_NORMAL, VOIDmode);
30105 const char *label_name;
30108 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30109 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30110 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30112 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30113 LCT_NORMAL, VOIDmode, fun, Pmode);
30116 else if (DEFAULT_ABI == ABI_DARWIN)
30118 const char *mcount_name = RS6000_MCOUNT;
30119 int caller_addr_regno = LR_REGNO;
30121 /* Be conservative and always set this, at least for now. */
30122 crtl->uses_pic_offset_table = 1;
30125 /* For PIC code, set up a stub and collect the caller's address
30126 from r0, which is where the prologue puts it. */
30127 if (MACHOPIC_INDIRECT
30128 && crtl->uses_pic_offset_table)
30129 caller_addr_regno = 0;
30131 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30132 LCT_NORMAL, VOIDmode,
30133 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30137 /* Write function profiler code. */
30140 output_function_profiler (FILE *file, int labelno)
30144 switch (DEFAULT_ABI)
30147 gcc_unreachable ();
30152 warning (0, "no profiling of 64-bit code for this ABI");
30155 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30156 fprintf (file, "\tmflr %s\n", reg_names[0]);
30157 if (NO_PROFILE_COUNTERS)
30159 asm_fprintf (file, "\tstw %s,4(%s)\n",
30160 reg_names[0], reg_names[1]);
30162 else if (TARGET_SECURE_PLT && flag_pic)
30164 if (TARGET_LINK_STACK)
30167 get_ppc476_thunk_name (name);
30168 asm_fprintf (file, "\tbl %s\n", name);
30171 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30172 asm_fprintf (file, "\tstw %s,4(%s)\n",
30173 reg_names[0], reg_names[1]);
30174 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30175 asm_fprintf (file, "\taddis %s,%s,",
30176 reg_names[12], reg_names[12]);
30177 assemble_name (file, buf);
30178 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30179 assemble_name (file, buf);
30180 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30182 else if (flag_pic == 1)
30184 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30185 asm_fprintf (file, "\tstw %s,4(%s)\n",
30186 reg_names[0], reg_names[1]);
30187 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30188 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30189 assemble_name (file, buf);
30190 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30192 else if (flag_pic > 1)
30194 asm_fprintf (file, "\tstw %s,4(%s)\n",
30195 reg_names[0], reg_names[1]);
30196 /* Now, we need to get the address of the label. */
30197 if (TARGET_LINK_STACK)
30200 get_ppc476_thunk_name (name);
30201 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30202 assemble_name (file, buf);
30203 fputs ("-.\n1:", file);
30204 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30205 asm_fprintf (file, "\taddi %s,%s,4\n",
30206 reg_names[11], reg_names[11]);
30210 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30211 assemble_name (file, buf);
30212 fputs ("-.\n1:", file);
30213 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30215 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30216 reg_names[0], reg_names[11]);
30217 asm_fprintf (file, "\tadd %s,%s,%s\n",
30218 reg_names[0], reg_names[0], reg_names[11]);
30222 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30223 assemble_name (file, buf);
30224 fputs ("@ha\n", file);
30225 asm_fprintf (file, "\tstw %s,4(%s)\n",
30226 reg_names[0], reg_names[1]);
30227 asm_fprintf (file, "\tla %s,", reg_names[0]);
30228 assemble_name (file, buf);
30229 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30232 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30233 fprintf (file, "\tbl %s%s\n",
30234 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30240 /* Don't do anything, done in output_profile_hook (). */
30247 /* The following variable value is the last issued insn. */
30249 static rtx_insn *last_scheduled_insn;
30251 /* The following variable helps to balance issuing of load and
30252 store instructions */
30254 static int load_store_pendulum;
30256 /* The following variable helps pair divide insns during scheduling. */
30257 static int divide_cnt;
30258 /* The following variable helps pair and alternate vector and vector load
30259 insns during scheduling. */
30260 static int vec_pairing;
30263 /* Power4 load update and store update instructions are cracked into a
30264 load or store and an integer insn which are executed in the same cycle.
30265 Branches have their own dispatch slot which does not count against the
30266 GCC issue rate, but it changes the program flow so there are no other
30267 instructions to issue in this cycle. */
30270 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30272 last_scheduled_insn = insn;
30273 if (GET_CODE (PATTERN (insn)) == USE
30274 || GET_CODE (PATTERN (insn)) == CLOBBER)
30276 cached_can_issue_more = more;
30277 return cached_can_issue_more;
30280 if (insn_terminates_group_p (insn, current_group))
30282 cached_can_issue_more = 0;
30283 return cached_can_issue_more;
30286 /* If no reservation, but reach here */
30287 if (recog_memoized (insn) < 0)
30290 if (rs6000_sched_groups)
30292 if (is_microcoded_insn (insn))
30293 cached_can_issue_more = 0;
30294 else if (is_cracked_insn (insn))
30295 cached_can_issue_more = more > 2 ? more - 2 : 0;
30297 cached_can_issue_more = more - 1;
30299 return cached_can_issue_more;
30302 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30305 cached_can_issue_more = more - 1;
30306 return cached_can_issue_more;
30310 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30312 int r = rs6000_variable_issue_1 (insn, more);
30314 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30318 /* Adjust the cost of a scheduling dependency. Return the new cost of
30319 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30322 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30325 enum attr_type attr_type;
30327 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30334 /* Data dependency; DEP_INSN writes a register that INSN reads
30335 some cycles later. */
30337 /* Separate a load from a narrower, dependent store. */
30338 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
30339 || rs6000_tune == PROCESSOR_FUTURE)
30340 && GET_CODE (PATTERN (insn)) == SET
30341 && GET_CODE (PATTERN (dep_insn)) == SET
30342 && MEM_P (XEXP (PATTERN (insn), 1))
30343 && MEM_P (XEXP (PATTERN (dep_insn), 0))
30344 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30345 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30348 attr_type = get_attr_type (insn);
30353 /* Tell the first scheduling pass about the latency between
30354 a mtctr and bctr (and mtlr and br/blr). The first
30355 scheduling pass will not know about this latency since
30356 the mtctr instruction, which has the latency associated
30357 to it, will be generated by reload. */
30360 /* Leave some extra cycles between a compare and its
30361 dependent branch, to inhibit expensive mispredicts. */
30362 if ((rs6000_tune == PROCESSOR_PPC603
30363 || rs6000_tune == PROCESSOR_PPC604
30364 || rs6000_tune == PROCESSOR_PPC604e
30365 || rs6000_tune == PROCESSOR_PPC620
30366 || rs6000_tune == PROCESSOR_PPC630
30367 || rs6000_tune == PROCESSOR_PPC750
30368 || rs6000_tune == PROCESSOR_PPC7400
30369 || rs6000_tune == PROCESSOR_PPC7450
30370 || rs6000_tune == PROCESSOR_PPCE5500
30371 || rs6000_tune == PROCESSOR_PPCE6500
30372 || rs6000_tune == PROCESSOR_POWER4
30373 || rs6000_tune == PROCESSOR_POWER5
30374 || rs6000_tune == PROCESSOR_POWER7
30375 || rs6000_tune == PROCESSOR_POWER8
30376 || rs6000_tune == PROCESSOR_POWER9
30377 || rs6000_tune == PROCESSOR_FUTURE
30378 || rs6000_tune == PROCESSOR_CELL)
30379 && recog_memoized (dep_insn)
30380 && (INSN_CODE (dep_insn) >= 0))
30382 switch (get_attr_type (dep_insn))
30385 case TYPE_FPCOMPARE:
30386 case TYPE_CR_LOGICAL:
30390 if (get_attr_dot (dep_insn) == DOT_YES)
30395 if (get_attr_dot (dep_insn) == DOT_YES
30396 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30407 if ((rs6000_tune == PROCESSOR_POWER6)
30408 && recog_memoized (dep_insn)
30409 && (INSN_CODE (dep_insn) >= 0))
30412 if (GET_CODE (PATTERN (insn)) != SET)
30413 /* If this happens, we have to extend this to schedule
30414 optimally. Return default for now. */
30417 /* Adjust the cost for the case where the value written
30418 by a fixed point operation is used as the address
30419 gen value on a store. */
30420 switch (get_attr_type (dep_insn))
30425 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30426 return get_attr_sign_extend (dep_insn)
30427 == SIGN_EXTEND_YES ? 6 : 4;
30432 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30433 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30443 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30451 if (get_attr_update (dep_insn) == UPDATE_YES
30452 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30458 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30464 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30465 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30475 if ((rs6000_tune == PROCESSOR_POWER6)
30476 && recog_memoized (dep_insn)
30477 && (INSN_CODE (dep_insn) >= 0))
30480 /* Adjust the cost for the case where the value written
30481 by a fixed point instruction is used within the address
30482 gen portion of a subsequent load(u)(x) */
30483 switch (get_attr_type (dep_insn))
30488 if (set_to_load_agen (dep_insn, insn))
30489 return get_attr_sign_extend (dep_insn)
30490 == SIGN_EXTEND_YES ? 6 : 4;
30495 if (set_to_load_agen (dep_insn, insn))
30496 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30506 if (set_to_load_agen (dep_insn, insn))
30514 if (get_attr_update (dep_insn) == UPDATE_YES
30515 && set_to_load_agen (dep_insn, insn))
30521 if (set_to_load_agen (dep_insn, insn))
30527 if (set_to_load_agen (dep_insn, insn))
30528 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30538 if ((rs6000_tune == PROCESSOR_POWER6)
30539 && get_attr_update (insn) == UPDATE_NO
30540 && recog_memoized (dep_insn)
30541 && (INSN_CODE (dep_insn) >= 0)
30542 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30549 /* Fall out to return default cost. */
30553 case REG_DEP_OUTPUT:
30554 /* Output dependency; DEP_INSN writes a register that INSN writes some
30556 if ((rs6000_tune == PROCESSOR_POWER6)
30557 && recog_memoized (dep_insn)
30558 && (INSN_CODE (dep_insn) >= 0))
30560 attr_type = get_attr_type (insn);
30565 case TYPE_FPSIMPLE:
30566 if (get_attr_type (dep_insn) == TYPE_FP
30567 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30571 if (get_attr_update (insn) == UPDATE_NO
30572 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30579 /* Fall through, no cost for output dependency. */
30583 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30588 gcc_unreachable ();
30594 /* Debug version of rs6000_adjust_cost. */
30597 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30598 int cost, unsigned int dw)
30600 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30608 default: dep = "unknown depencency"; break;
30609 case REG_DEP_TRUE: dep = "data dependency"; break;
30610 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30611 case REG_DEP_ANTI: dep = "anti depencency"; break;
30615 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30616 "%s, insn:\n", ret, cost, dep);
30624 /* The function returns a true if INSN is microcoded.
30625 Return false otherwise. */
30628 is_microcoded_insn (rtx_insn *insn)
30630 if (!insn || !NONDEBUG_INSN_P (insn)
30631 || GET_CODE (PATTERN (insn)) == USE
30632 || GET_CODE (PATTERN (insn)) == CLOBBER)
30635 if (rs6000_tune == PROCESSOR_CELL)
30636 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30638 if (rs6000_sched_groups
30639 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30641 enum attr_type type = get_attr_type (insn);
30642 if ((type == TYPE_LOAD
30643 && get_attr_update (insn) == UPDATE_YES
30644 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30645 || ((type == TYPE_LOAD || type == TYPE_STORE)
30646 && get_attr_update (insn) == UPDATE_YES
30647 && get_attr_indexed (insn) == INDEXED_YES)
30648 || type == TYPE_MFCR)
30655 /* The function returns true if INSN is cracked into 2 instructions
30656 by the processor (and therefore occupies 2 issue slots). */
30659 is_cracked_insn (rtx_insn *insn)
30661 if (!insn || !NONDEBUG_INSN_P (insn)
30662 || GET_CODE (PATTERN (insn)) == USE
30663 || GET_CODE (PATTERN (insn)) == CLOBBER)
30666 if (rs6000_sched_groups
30667 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30669 enum attr_type type = get_attr_type (insn);
30670 if ((type == TYPE_LOAD
30671 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30672 && get_attr_update (insn) == UPDATE_NO)
30673 || (type == TYPE_LOAD
30674 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30675 && get_attr_update (insn) == UPDATE_YES
30676 && get_attr_indexed (insn) == INDEXED_NO)
30677 || (type == TYPE_STORE
30678 && get_attr_update (insn) == UPDATE_YES
30679 && get_attr_indexed (insn) == INDEXED_NO)
30680 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30681 && get_attr_update (insn) == UPDATE_YES)
30682 || (type == TYPE_CR_LOGICAL
30683 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30684 || (type == TYPE_EXTS
30685 && get_attr_dot (insn) == DOT_YES)
30686 || (type == TYPE_SHIFT
30687 && get_attr_dot (insn) == DOT_YES
30688 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30689 || (type == TYPE_MUL
30690 && get_attr_dot (insn) == DOT_YES)
30691 || type == TYPE_DIV
30692 || (type == TYPE_INSERT
30693 && get_attr_size (insn) == SIZE_32))
30700 /* The function returns true if INSN can be issued only from
30701 the branch slot. */
30704 is_branch_slot_insn (rtx_insn *insn)
30706 if (!insn || !NONDEBUG_INSN_P (insn)
30707 || GET_CODE (PATTERN (insn)) == USE
30708 || GET_CODE (PATTERN (insn)) == CLOBBER)
30711 if (rs6000_sched_groups)
30713 enum attr_type type = get_attr_type (insn);
30714 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30722 /* The function returns true if out_inst sets a value that is
30723 used in the address generation computation of in_insn */
30725 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30727 rtx out_set, in_set;
30729 /* For performance reasons, only handle the simple case where
30730 both loads are a single_set. */
30731 out_set = single_set (out_insn);
30734 in_set = single_set (in_insn);
30736 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30742 /* Try to determine base/offset/size parts of the given MEM.
30743 Return true if successful, false if all the values couldn't
30746 This function only looks for REG or REG+CONST address forms.
30747 REG+REG address form will return false. */
30750 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30751 HOST_WIDE_INT *size)
30754 if MEM_SIZE_KNOWN_P (mem)
30755 *size = MEM_SIZE (mem);
30759 addr_rtx = (XEXP (mem, 0));
30760 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30761 addr_rtx = XEXP (addr_rtx, 1);
30764 while (GET_CODE (addr_rtx) == PLUS
30765 && CONST_INT_P (XEXP (addr_rtx, 1)))
30767 *offset += INTVAL (XEXP (addr_rtx, 1));
30768 addr_rtx = XEXP (addr_rtx, 0);
30770 if (!REG_P (addr_rtx))
30777 /* The function returns true if the target storage location of
30778 mem1 is adjacent to the target storage location of mem2 */
30779 /* Return 1 if memory locations are adjacent. */
30782 adjacent_mem_locations (rtx mem1, rtx mem2)
30785 HOST_WIDE_INT off1, size1, off2, size2;
30787 if (get_memref_parts (mem1, ®1, &off1, &size1)
30788 && get_memref_parts (mem2, ®2, &off2, &size2))
30789 return ((REGNO (reg1) == REGNO (reg2))
30790 && ((off1 + size1 == off2)
30791 || (off2 + size2 == off1)));
30796 /* This function returns true if it can be determined that the two MEM
30797 locations overlap by at least 1 byte based on base reg/offset/size. */
30800 mem_locations_overlap (rtx mem1, rtx mem2)
30803 HOST_WIDE_INT off1, size1, off2, size2;
30805 if (get_memref_parts (mem1, ®1, &off1, &size1)
30806 && get_memref_parts (mem2, ®2, &off2, &size2))
30807 return ((REGNO (reg1) == REGNO (reg2))
30808 && (((off1 <= off2) && (off1 + size1 > off2))
30809 || ((off2 <= off1) && (off2 + size2 > off1))));
30814 /* A C statement (sans semicolon) to update the integer scheduling
30815 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30816 INSN earlier, reduce the priority to execute INSN later. Do not
30817 define this macro if you do not need to adjust the scheduling
30818 priorities of insns. */
30821 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30823 rtx load_mem, str_mem;
30824 /* On machines (like the 750) which have asymmetric integer units,
30825 where one integer unit can do multiply and divides and the other
30826 can't, reduce the priority of multiply/divide so it is scheduled
30827 before other integer operations. */
30830 if (! INSN_P (insn))
30833 if (GET_CODE (PATTERN (insn)) == USE)
30836 switch (rs6000_tune) {
30837 case PROCESSOR_PPC750:
30838 switch (get_attr_type (insn))
30845 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30846 priority, priority);
30847 if (priority >= 0 && priority < 0x01000000)
30854 if (insn_must_be_first_in_group (insn)
30855 && reload_completed
30856 && current_sched_info->sched_max_insns_priority
30857 && rs6000_sched_restricted_insns_priority)
30860 /* Prioritize insns that can be dispatched only in the first
30862 if (rs6000_sched_restricted_insns_priority == 1)
30863 /* Attach highest priority to insn. This means that in
30864 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30865 precede 'priority' (critical path) considerations. */
30866 return current_sched_info->sched_max_insns_priority;
30867 else if (rs6000_sched_restricted_insns_priority == 2)
30868 /* Increase priority of insn by a minimal amount. This means that in
30869 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30870 considerations precede dispatch-slot restriction considerations. */
30871 return (priority + 1);
30874 if (rs6000_tune == PROCESSOR_POWER6
30875 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30876 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30877 /* Attach highest priority to insn if the scheduler has just issued two
30878 stores and this instruction is a load, or two loads and this instruction
30879 is a store. Power6 wants loads and stores scheduled alternately
30881 return current_sched_info->sched_max_insns_priority;
30886 /* Return true if the instruction is nonpipelined on the Cell. */
30888 is_nonpipeline_insn (rtx_insn *insn)
30890 enum attr_type type;
30891 if (!insn || !NONDEBUG_INSN_P (insn)
30892 || GET_CODE (PATTERN (insn)) == USE
30893 || GET_CODE (PATTERN (insn)) == CLOBBER)
30896 type = get_attr_type (insn);
30897 if (type == TYPE_MUL
30898 || type == TYPE_DIV
30899 || type == TYPE_SDIV
30900 || type == TYPE_DDIV
30901 || type == TYPE_SSQRT
30902 || type == TYPE_DSQRT
30903 || type == TYPE_MFCR
30904 || type == TYPE_MFCRF
30905 || type == TYPE_MFJMPR)
30913 /* Return how many instructions the machine can issue per cycle. */
30916 rs6000_issue_rate (void)
30918 /* Unless scheduling for register pressure, use issue rate of 1 for
30919 first scheduling pass to decrease degradation. */
30920 if (!reload_completed && !flag_sched_pressure)
30923 switch (rs6000_tune) {
30924 case PROCESSOR_RS64A:
30925 case PROCESSOR_PPC601: /* ? */
30926 case PROCESSOR_PPC7450:
30928 case PROCESSOR_PPC440:
30929 case PROCESSOR_PPC603:
30930 case PROCESSOR_PPC750:
30931 case PROCESSOR_PPC7400:
30932 case PROCESSOR_PPC8540:
30933 case PROCESSOR_PPC8548:
30934 case PROCESSOR_CELL:
30935 case PROCESSOR_PPCE300C2:
30936 case PROCESSOR_PPCE300C3:
30937 case PROCESSOR_PPCE500MC:
30938 case PROCESSOR_PPCE500MC64:
30939 case PROCESSOR_PPCE5500:
30940 case PROCESSOR_PPCE6500:
30941 case PROCESSOR_TITAN:
30943 case PROCESSOR_PPC476:
30944 case PROCESSOR_PPC604:
30945 case PROCESSOR_PPC604e:
30946 case PROCESSOR_PPC620:
30947 case PROCESSOR_PPC630:
30949 case PROCESSOR_POWER4:
30950 case PROCESSOR_POWER5:
30951 case PROCESSOR_POWER6:
30952 case PROCESSOR_POWER7:
30954 case PROCESSOR_POWER8:
30956 case PROCESSOR_POWER9:
30957 case PROCESSOR_FUTURE:
30964 /* Return how many instructions to look ahead for better insn
30968 rs6000_use_sched_lookahead (void)
30970 switch (rs6000_tune)
30972 case PROCESSOR_PPC8540:
30973 case PROCESSOR_PPC8548:
30976 case PROCESSOR_CELL:
30977 return (reload_completed ? 8 : 0);
30984 /* We are choosing insn from the ready queue. Return zero if INSN can be
30987 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30989 if (ready_index == 0)
30992 if (rs6000_tune != PROCESSOR_CELL)
30995 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30997 if (!reload_completed
30998 || is_nonpipeline_insn (insn)
30999 || is_microcoded_insn (insn))
31005 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31006 and return true. */
31009 find_mem_ref (rtx pat, rtx *mem_ref)
31014 /* stack_tie does not produce any real memory traffic. */
31015 if (tie_operand (pat, VOIDmode))
31024 /* Recursively process the pattern. */
31025 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31027 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31031 if (find_mem_ref (XEXP (pat, i), mem_ref))
31034 else if (fmt[i] == 'E')
31035 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31037 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31045 /* Determine if PAT is a PATTERN of a load insn. */
31048 is_load_insn1 (rtx pat, rtx *load_mem)
31050 if (!pat || pat == NULL_RTX)
31053 if (GET_CODE (pat) == SET)
31054 return find_mem_ref (SET_SRC (pat), load_mem);
31056 if (GET_CODE (pat) == PARALLEL)
31060 for (i = 0; i < XVECLEN (pat, 0); i++)
31061 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31068 /* Determine if INSN loads from memory. */
31071 is_load_insn (rtx insn, rtx *load_mem)
31073 if (!insn || !INSN_P (insn))
31079 return is_load_insn1 (PATTERN (insn), load_mem);
31082 /* Determine if PAT is a PATTERN of a store insn. */
31085 is_store_insn1 (rtx pat, rtx *str_mem)
31087 if (!pat || pat == NULL_RTX)
31090 if (GET_CODE (pat) == SET)
31091 return find_mem_ref (SET_DEST (pat), str_mem);
31093 if (GET_CODE (pat) == PARALLEL)
31097 for (i = 0; i < XVECLEN (pat, 0); i++)
31098 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31105 /* Determine if INSN stores to memory. */
31108 is_store_insn (rtx insn, rtx *str_mem)
31110 if (!insn || !INSN_P (insn))
31113 return is_store_insn1 (PATTERN (insn), str_mem);
31116 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31119 is_power9_pairable_vec_type (enum attr_type type)
31123 case TYPE_VECSIMPLE:
31124 case TYPE_VECCOMPLEX:
31128 case TYPE_VECFLOAT:
31130 case TYPE_VECDOUBLE:
31138 /* Returns whether the dependence between INSN and NEXT is considered
31139 costly by the given target. */
31142 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31146 rtx load_mem, str_mem;
31148 /* If the flag is not enabled - no dependence is considered costly;
31149 allow all dependent insns in the same group.
31150 This is the most aggressive option. */
31151 if (rs6000_sched_costly_dep == no_dep_costly)
31154 /* If the flag is set to 1 - a dependence is always considered costly;
31155 do not allow dependent instructions in the same group.
31156 This is the most conservative option. */
31157 if (rs6000_sched_costly_dep == all_deps_costly)
31160 insn = DEP_PRO (dep);
31161 next = DEP_CON (dep);
31163 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31164 && is_load_insn (next, &load_mem)
31165 && is_store_insn (insn, &str_mem))
31166 /* Prevent load after store in the same group. */
31169 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31170 && is_load_insn (next, &load_mem)
31171 && is_store_insn (insn, &str_mem)
31172 && DEP_TYPE (dep) == REG_DEP_TRUE
31173 && mem_locations_overlap(str_mem, load_mem))
31174 /* Prevent load after store in the same group if it is a true
31178 /* The flag is set to X; dependences with latency >= X are considered costly,
31179 and will not be scheduled in the same group. */
31180 if (rs6000_sched_costly_dep <= max_dep_latency
31181 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31187 /* Return the next insn after INSN that is found before TAIL is reached,
31188 skipping any "non-active" insns - insns that will not actually occupy
31189 an issue slot. Return NULL_RTX if such an insn is not found. */
31192 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31194 if (insn == NULL_RTX || insn == tail)
31199 insn = NEXT_INSN (insn);
31200 if (insn == NULL_RTX || insn == tail)
31204 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31205 || (NONJUMP_INSN_P (insn)
31206 && GET_CODE (PATTERN (insn)) != USE
31207 && GET_CODE (PATTERN (insn)) != CLOBBER
31208 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31214 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31217 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31222 enum attr_type type, type2;
31224 type = get_attr_type (last_scheduled_insn);
31226 /* Try to issue fixed point divides back-to-back in pairs so they will be
31227 routed to separate execution units and execute in parallel. */
31228 if (type == TYPE_DIV && divide_cnt == 0)
31230 /* First divide has been scheduled. */
31233 /* Scan the ready list looking for another divide, if found move it
31234 to the end of the list so it is chosen next. */
31238 if (recog_memoized (ready[pos]) >= 0
31239 && get_attr_type (ready[pos]) == TYPE_DIV)
31242 for (i = pos; i < lastpos; i++)
31243 ready[i] = ready[i + 1];
31244 ready[lastpos] = tmp;
31252 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31255 /* The best dispatch throughput for vector and vector load insns can be
31256 achieved by interleaving a vector and vector load such that they'll
31257 dispatch to the same superslice. If this pairing cannot be achieved
31258 then it is best to pair vector insns together and vector load insns
31261 To aid in this pairing, vec_pairing maintains the current state with
31262 the following values:
31264 0 : Initial state, no vecload/vector pairing has been started.
31266 1 : A vecload or vector insn has been issued and a candidate for
31267 pairing has been found and moved to the end of the ready
31269 if (type == TYPE_VECLOAD)
31271 /* Issued a vecload. */
31272 if (vec_pairing == 0)
31274 int vecload_pos = -1;
31275 /* We issued a single vecload, look for a vector insn to pair it
31276 with. If one isn't found, try to pair another vecload. */
31280 if (recog_memoized (ready[pos]) >= 0)
31282 type2 = get_attr_type (ready[pos]);
31283 if (is_power9_pairable_vec_type (type2))
31285 /* Found a vector insn to pair with, move it to the
31286 end of the ready list so it is scheduled next. */
31288 for (i = pos; i < lastpos; i++)
31289 ready[i] = ready[i + 1];
31290 ready[lastpos] = tmp;
31292 return cached_can_issue_more;
31294 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31295 /* Remember position of first vecload seen. */
31300 if (vecload_pos >= 0)
31302 /* Didn't find a vector to pair with but did find a vecload,
31303 move it to the end of the ready list. */
31304 tmp = ready[vecload_pos];
31305 for (i = vecload_pos; i < lastpos; i++)
31306 ready[i] = ready[i + 1];
31307 ready[lastpos] = tmp;
31309 return cached_can_issue_more;
31313 else if (is_power9_pairable_vec_type (type))
31315 /* Issued a vector operation. */
31316 if (vec_pairing == 0)
31319 /* We issued a single vector insn, look for a vecload to pair it
31320 with. If one isn't found, try to pair another vector. */
31324 if (recog_memoized (ready[pos]) >= 0)
31326 type2 = get_attr_type (ready[pos]);
31327 if (type2 == TYPE_VECLOAD)
31329 /* Found a vecload insn to pair with, move it to the
31330 end of the ready list so it is scheduled next. */
31332 for (i = pos; i < lastpos; i++)
31333 ready[i] = ready[i + 1];
31334 ready[lastpos] = tmp;
31336 return cached_can_issue_more;
31338 else if (is_power9_pairable_vec_type (type2)
31340 /* Remember position of first vector insn seen. */
31347 /* Didn't find a vecload to pair with but did find a vector
31348 insn, move it to the end of the ready list. */
31349 tmp = ready[vec_pos];
31350 for (i = vec_pos; i < lastpos; i++)
31351 ready[i] = ready[i + 1];
31352 ready[lastpos] = tmp;
31354 return cached_can_issue_more;
31359 /* We've either finished a vec/vecload pair, couldn't find an insn to
31360 continue the current pair, or the last insn had nothing to do with
31361 with pairing. In any case, reset the state. */
31365 return cached_can_issue_more;
31368 /* We are about to begin issuing insns for this clock cycle. */
31371 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31372 rtx_insn **ready ATTRIBUTE_UNUSED,
31373 int *pn_ready ATTRIBUTE_UNUSED,
31374 int clock_var ATTRIBUTE_UNUSED)
31376 int n_ready = *pn_ready;
31379 fprintf (dump, "// rs6000_sched_reorder :\n");
31381 /* Reorder the ready list, if the second to last ready insn
31382 is a nonepipeline insn. */
31383 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31385 if (is_nonpipeline_insn (ready[n_ready - 1])
31386 && (recog_memoized (ready[n_ready - 2]) > 0))
31387 /* Simply swap first two insns. */
31388 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31391 if (rs6000_tune == PROCESSOR_POWER6)
31392 load_store_pendulum = 0;
31394 return rs6000_issue_rate ();
31397 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31400 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31401 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31404 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31406 /* For Power6, we need to handle some special cases to try and keep the
31407 store queue from overflowing and triggering expensive flushes.
31409 This code monitors how load and store instructions are being issued
31410 and skews the ready list one way or the other to increase the likelihood
31411 that a desired instruction is issued at the proper time.
31413 A couple of things are done. First, we maintain a "load_store_pendulum"
31414 to track the current state of load/store issue.
31416 - If the pendulum is at zero, then no loads or stores have been
31417 issued in the current cycle so we do nothing.
31419 - If the pendulum is 1, then a single load has been issued in this
31420 cycle and we attempt to locate another load in the ready list to
31423 - If the pendulum is -2, then two stores have already been
31424 issued in this cycle, so we increase the priority of the first load
31425 in the ready list to increase it's likelihood of being chosen first
31428 - If the pendulum is -1, then a single store has been issued in this
31429 cycle and we attempt to locate another store in the ready list to
31430 issue with it, preferring a store to an adjacent memory location to
31431 facilitate store pairing in the store queue.
31433 - If the pendulum is 2, then two loads have already been
31434 issued in this cycle, so we increase the priority of the first store
31435 in the ready list to increase it's likelihood of being chosen first
31438 - If the pendulum < -2 or > 2, then do nothing.
31440 Note: This code covers the most common scenarios. There exist non
31441 load/store instructions which make use of the LSU and which
31442 would need to be accounted for to strictly model the behavior
31443 of the machine. Those instructions are currently unaccounted
31444 for to help minimize compile time overhead of this code.
31446 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31451 rtx load_mem, str_mem;
31453 if (is_store_insn (last_scheduled_insn, &str_mem))
31454 /* Issuing a store, swing the load_store_pendulum to the left */
31455 load_store_pendulum--;
31456 else if (is_load_insn (last_scheduled_insn, &load_mem))
31457 /* Issuing a load, swing the load_store_pendulum to the right */
31458 load_store_pendulum++;
31460 return cached_can_issue_more;
31462 /* If the pendulum is balanced, or there is only one instruction on
31463 the ready list, then all is well, so return. */
31464 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31465 return cached_can_issue_more;
31467 if (load_store_pendulum == 1)
31469 /* A load has been issued in this cycle. Scan the ready list
31470 for another load to issue with it */
31475 if (is_load_insn (ready[pos], &load_mem))
31477 /* Found a load. Move it to the head of the ready list,
31478 and adjust it's priority so that it is more likely to
31481 for (i=pos; i<*pn_ready-1; i++)
31482 ready[i] = ready[i + 1];
31483 ready[*pn_ready-1] = tmp;
31485 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31486 INSN_PRIORITY (tmp)++;
31492 else if (load_store_pendulum == -2)
31494 /* Two stores have been issued in this cycle. Increase the
31495 priority of the first load in the ready list to favor it for
31496 issuing in the next cycle. */
31501 if (is_load_insn (ready[pos], &load_mem)
31503 && INSN_PRIORITY_KNOWN (ready[pos]))
31505 INSN_PRIORITY (ready[pos])++;
31507 /* Adjust the pendulum to account for the fact that a load
31508 was found and increased in priority. This is to prevent
31509 increasing the priority of multiple loads */
31510 load_store_pendulum--;
31517 else if (load_store_pendulum == -1)
31519 /* A store has been issued in this cycle. Scan the ready list for
31520 another store to issue with it, preferring a store to an adjacent
31522 int first_store_pos = -1;
31528 if (is_store_insn (ready[pos], &str_mem))
31531 /* Maintain the index of the first store found on the
31533 if (first_store_pos == -1)
31534 first_store_pos = pos;
31536 if (is_store_insn (last_scheduled_insn, &str_mem2)
31537 && adjacent_mem_locations (str_mem, str_mem2))
31539 /* Found an adjacent store. Move it to the head of the
31540 ready list, and adjust it's priority so that it is
31541 more likely to stay there */
31543 for (i=pos; i<*pn_ready-1; i++)
31544 ready[i] = ready[i + 1];
31545 ready[*pn_ready-1] = tmp;
31547 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31548 INSN_PRIORITY (tmp)++;
31550 first_store_pos = -1;
31558 if (first_store_pos >= 0)
31560 /* An adjacent store wasn't found, but a non-adjacent store was,
31561 so move the non-adjacent store to the front of the ready
31562 list, and adjust its priority so that it is more likely to
31564 tmp = ready[first_store_pos];
31565 for (i=first_store_pos; i<*pn_ready-1; i++)
31566 ready[i] = ready[i + 1];
31567 ready[*pn_ready-1] = tmp;
31568 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31569 INSN_PRIORITY (tmp)++;
31572 else if (load_store_pendulum == 2)
31574 /* Two loads have been issued in this cycle. Increase the priority
31575 of the first store in the ready list to favor it for issuing in
31581 if (is_store_insn (ready[pos], &str_mem)
31583 && INSN_PRIORITY_KNOWN (ready[pos]))
31585 INSN_PRIORITY (ready[pos])++;
31587 /* Adjust the pendulum to account for the fact that a store
31588 was found and increased in priority. This is to prevent
31589 increasing the priority of multiple stores */
31590 load_store_pendulum++;
31599 /* Do Power9 dependent reordering if necessary. */
31600 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31601 && recog_memoized (last_scheduled_insn) >= 0)
31602 return power9_sched_reorder2 (ready, *pn_ready - 1);
31604 return cached_can_issue_more;
31607 /* Return whether the presence of INSN causes a dispatch group termination
31608 of group WHICH_GROUP.
31610 If WHICH_GROUP == current_group, this function will return true if INSN
31611 causes the termination of the current group (i.e, the dispatch group to
31612 which INSN belongs). This means that INSN will be the last insn in the
31613 group it belongs to.
31615 If WHICH_GROUP == previous_group, this function will return true if INSN
31616 causes the termination of the previous group (i.e, the dispatch group that
31617 precedes the group to which INSN belongs). This means that INSN will be
31618 the first insn in the group it belongs to). */
31621 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31628 first = insn_must_be_first_in_group (insn);
31629 last = insn_must_be_last_in_group (insn);
31634 if (which_group == current_group)
31636 else if (which_group == previous_group)
31644 insn_must_be_first_in_group (rtx_insn *insn)
31646 enum attr_type type;
31650 || DEBUG_INSN_P (insn)
31651 || GET_CODE (PATTERN (insn)) == USE
31652 || GET_CODE (PATTERN (insn)) == CLOBBER)
31655 switch (rs6000_tune)
31657 case PROCESSOR_POWER5:
31658 if (is_cracked_insn (insn))
31661 case PROCESSOR_POWER4:
31662 if (is_microcoded_insn (insn))
31665 if (!rs6000_sched_groups)
31668 type = get_attr_type (insn);
31675 case TYPE_CR_LOGICAL:
31688 case PROCESSOR_POWER6:
31689 type = get_attr_type (insn);
31698 case TYPE_FPCOMPARE:
31709 if (get_attr_dot (insn) == DOT_NO
31710 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31715 if (get_attr_size (insn) == SIZE_32)
31723 if (get_attr_update (insn) == UPDATE_YES)
31731 case PROCESSOR_POWER7:
31732 type = get_attr_type (insn);
31736 case TYPE_CR_LOGICAL:
31750 if (get_attr_dot (insn) == DOT_YES)
31755 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31756 || get_attr_update (insn) == UPDATE_YES)
31763 if (get_attr_update (insn) == UPDATE_YES)
31771 case PROCESSOR_POWER8:
31772 type = get_attr_type (insn);
31776 case TYPE_CR_LOGICAL:
31784 case TYPE_VECSTORE:
31791 if (get_attr_dot (insn) == DOT_YES)
31796 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31797 || get_attr_update (insn) == UPDATE_YES)
31802 if (get_attr_update (insn) == UPDATE_YES
31803 && get_attr_indexed (insn) == INDEXED_YES)
31819 insn_must_be_last_in_group (rtx_insn *insn)
31821 enum attr_type type;
31825 || DEBUG_INSN_P (insn)
31826 || GET_CODE (PATTERN (insn)) == USE
31827 || GET_CODE (PATTERN (insn)) == CLOBBER)
31830 switch (rs6000_tune) {
31831 case PROCESSOR_POWER4:
31832 case PROCESSOR_POWER5:
31833 if (is_microcoded_insn (insn))
31836 if (is_branch_slot_insn (insn))
31840 case PROCESSOR_POWER6:
31841 type = get_attr_type (insn);
31849 case TYPE_FPCOMPARE:
31860 if (get_attr_dot (insn) == DOT_NO
31861 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31866 if (get_attr_size (insn) == SIZE_32)
31874 case PROCESSOR_POWER7:
31875 type = get_attr_type (insn);
31885 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31886 && get_attr_update (insn) == UPDATE_YES)
31891 if (get_attr_update (insn) == UPDATE_YES
31892 && get_attr_indexed (insn) == INDEXED_YES)
31900 case PROCESSOR_POWER8:
31901 type = get_attr_type (insn);
31913 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31914 && get_attr_update (insn) == UPDATE_YES)
31919 if (get_attr_update (insn) == UPDATE_YES
31920 && get_attr_indexed (insn) == INDEXED_YES)
31935 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31936 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31939 is_costly_group (rtx *group_insns, rtx next_insn)
31942 int issue_rate = rs6000_issue_rate ();
31944 for (i = 0; i < issue_rate; i++)
31946 sd_iterator_def sd_it;
31948 rtx insn = group_insns[i];
31953 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31955 rtx next = DEP_CON (dep);
31957 if (next == next_insn
31958 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31966 /* Utility of the function redefine_groups.
31967 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31968 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31969 to keep it "far" (in a separate group) from GROUP_INSNS, following
31970 one of the following schemes, depending on the value of the flag
31971 -minsert_sched_nops = X:
31972 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31973 in order to force NEXT_INSN into a separate group.
31974 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31975 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31976 insertion (has a group just ended, how many vacant issue slots remain in the
31977 last group, and how many dispatch groups were encountered so far). */
31980 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31981 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31986 int issue_rate = rs6000_issue_rate ();
31987 bool end = *group_end;
31990 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31991 return can_issue_more;
31993 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31994 return can_issue_more;
31996 force = is_costly_group (group_insns, next_insn);
31998 return can_issue_more;
32000 if (sched_verbose > 6)
32001 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32002 *group_count ,can_issue_more);
32004 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32007 can_issue_more = 0;
32009 /* Since only a branch can be issued in the last issue_slot, it is
32010 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32011 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32012 in this case the last nop will start a new group and the branch
32013 will be forced to the new group. */
32014 if (can_issue_more && !is_branch_slot_insn (next_insn))
32017 /* Do we have a special group ending nop? */
32018 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
32019 || rs6000_tune == PROCESSOR_POWER8)
32021 nop = gen_group_ending_nop ();
32022 emit_insn_before (nop, next_insn);
32023 can_issue_more = 0;
32026 while (can_issue_more > 0)
32029 emit_insn_before (nop, next_insn);
32037 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32039 int n_nops = rs6000_sched_insert_nops;
32041 /* Nops can't be issued from the branch slot, so the effective
32042 issue_rate for nops is 'issue_rate - 1'. */
32043 if (can_issue_more == 0)
32044 can_issue_more = issue_rate;
32046 if (can_issue_more == 0)
32048 can_issue_more = issue_rate - 1;
32051 for (i = 0; i < issue_rate; i++)
32053 group_insns[i] = 0;
32060 emit_insn_before (nop, next_insn);
32061 if (can_issue_more == issue_rate - 1) /* new group begins */
32064 if (can_issue_more == 0)
32066 can_issue_more = issue_rate - 1;
32069 for (i = 0; i < issue_rate; i++)
32071 group_insns[i] = 0;
32077 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32080 /* Is next_insn going to start a new group? */
32083 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32084 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32085 || (can_issue_more < issue_rate &&
32086 insn_terminates_group_p (next_insn, previous_group)));
32087 if (*group_end && end)
32090 if (sched_verbose > 6)
32091 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32092 *group_count, can_issue_more);
32093 return can_issue_more;
32096 return can_issue_more;
32099 /* This function tries to synch the dispatch groups that the compiler "sees"
32100 with the dispatch groups that the processor dispatcher is expected to
32101 form in practice. It tries to achieve this synchronization by forcing the
32102 estimated processor grouping on the compiler (as opposed to the function
32103 'pad_goups' which tries to force the scheduler's grouping on the processor).
32105 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32106 examines the (estimated) dispatch groups that will be formed by the processor
32107 dispatcher. It marks these group boundaries to reflect the estimated
32108 processor grouping, overriding the grouping that the scheduler had marked.
32109 Depending on the value of the flag '-minsert-sched-nops' this function can
32110 force certain insns into separate groups or force a certain distance between
32111 them by inserting nops, for example, if there exists a "costly dependence"
32114 The function estimates the group boundaries that the processor will form as
32115 follows: It keeps track of how many vacant issue slots are available after
32116 each insn. A subsequent insn will start a new group if one of the following
32118 - no more vacant issue slots remain in the current dispatch group.
32119 - only the last issue slot, which is the branch slot, is vacant, but the next
32120 insn is not a branch.
32121 - only the last 2 or less issue slots, including the branch slot, are vacant,
32122 which means that a cracked insn (which occupies two issue slots) can't be
32123 issued in this group.
32124 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32125 start a new group. */
32128 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32131 rtx_insn *insn, *next_insn;
32133 int can_issue_more;
32136 int group_count = 0;
32140 issue_rate = rs6000_issue_rate ();
32141 group_insns = XALLOCAVEC (rtx, issue_rate);
32142 for (i = 0; i < issue_rate; i++)
32144 group_insns[i] = 0;
32146 can_issue_more = issue_rate;
32148 insn = get_next_active_insn (prev_head_insn, tail);
32151 while (insn != NULL_RTX)
32153 slot = (issue_rate - can_issue_more);
32154 group_insns[slot] = insn;
32156 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32157 if (insn_terminates_group_p (insn, current_group))
32158 can_issue_more = 0;
32160 next_insn = get_next_active_insn (insn, tail);
32161 if (next_insn == NULL_RTX)
32162 return group_count + 1;
32164 /* Is next_insn going to start a new group? */
32166 = (can_issue_more == 0
32167 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32168 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32169 || (can_issue_more < issue_rate &&
32170 insn_terminates_group_p (next_insn, previous_group)));
32172 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32173 next_insn, &group_end, can_issue_more,
32179 can_issue_more = 0;
32180 for (i = 0; i < issue_rate; i++)
32182 group_insns[i] = 0;
32186 if (GET_MODE (next_insn) == TImode && can_issue_more)
32187 PUT_MODE (next_insn, VOIDmode);
32188 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32189 PUT_MODE (next_insn, TImode);
32192 if (can_issue_more == 0)
32193 can_issue_more = issue_rate;
32196 return group_count;
32199 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32200 dispatch group boundaries that the scheduler had marked. Pad with nops
32201 any dispatch groups which have vacant issue slots, in order to force the
32202 scheduler's grouping on the processor dispatcher. The function
32203 returns the number of dispatch groups found. */
32206 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32209 rtx_insn *insn, *next_insn;
32212 int can_issue_more;
32214 int group_count = 0;
32216 /* Initialize issue_rate. */
32217 issue_rate = rs6000_issue_rate ();
32218 can_issue_more = issue_rate;
32220 insn = get_next_active_insn (prev_head_insn, tail);
32221 next_insn = get_next_active_insn (insn, tail);
32223 while (insn != NULL_RTX)
32226 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32228 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32230 if (next_insn == NULL_RTX)
32235 /* If the scheduler had marked group termination at this location
32236 (between insn and next_insn), and neither insn nor next_insn will
32237 force group termination, pad the group with nops to force group
32240 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32241 && !insn_terminates_group_p (insn, current_group)
32242 && !insn_terminates_group_p (next_insn, previous_group))
32244 if (!is_branch_slot_insn (next_insn))
32247 while (can_issue_more)
32250 emit_insn_before (nop, next_insn);
32255 can_issue_more = issue_rate;
32260 next_insn = get_next_active_insn (insn, tail);
32263 return group_count;
32266 /* We're beginning a new block. Initialize data structures as necessary. */
32269 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32270 int sched_verbose ATTRIBUTE_UNUSED,
32271 int max_ready ATTRIBUTE_UNUSED)
32273 last_scheduled_insn = NULL;
32274 load_store_pendulum = 0;
32279 /* The following function is called at the end of scheduling BB.
32280 After reload, it inserts nops at insn group bundling. */
32283 rs6000_sched_finish (FILE *dump, int sched_verbose)
32288 fprintf (dump, "=== Finishing schedule.\n");
32290 if (reload_completed && rs6000_sched_groups)
32292 /* Do not run sched_finish hook when selective scheduling enabled. */
32293 if (sel_sched_p ())
32296 if (rs6000_sched_insert_nops == sched_finish_none)
32299 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32300 n_groups = pad_groups (dump, sched_verbose,
32301 current_sched_info->prev_head,
32302 current_sched_info->next_tail);
32304 n_groups = redefine_groups (dump, sched_verbose,
32305 current_sched_info->prev_head,
32306 current_sched_info->next_tail);
32308 if (sched_verbose >= 6)
32310 fprintf (dump, "ngroups = %d\n", n_groups);
32311 print_rtl (dump, current_sched_info->prev_head);
32312 fprintf (dump, "Done finish_sched\n");
32317 struct rs6000_sched_context
32319 short cached_can_issue_more;
32320 rtx_insn *last_scheduled_insn;
32321 int load_store_pendulum;
32326 typedef struct rs6000_sched_context rs6000_sched_context_def;
32327 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32329 /* Allocate store for new scheduling context. */
32331 rs6000_alloc_sched_context (void)
32333 return xmalloc (sizeof (rs6000_sched_context_def));
32336 /* If CLEAN_P is true then initializes _SC with clean data,
32337 and from the global context otherwise. */
32339 rs6000_init_sched_context (void *_sc, bool clean_p)
32341 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32345 sc->cached_can_issue_more = 0;
32346 sc->last_scheduled_insn = NULL;
32347 sc->load_store_pendulum = 0;
32348 sc->divide_cnt = 0;
32349 sc->vec_pairing = 0;
32353 sc->cached_can_issue_more = cached_can_issue_more;
32354 sc->last_scheduled_insn = last_scheduled_insn;
32355 sc->load_store_pendulum = load_store_pendulum;
32356 sc->divide_cnt = divide_cnt;
32357 sc->vec_pairing = vec_pairing;
32361 /* Sets the global scheduling context to the one pointed to by _SC. */
32363 rs6000_set_sched_context (void *_sc)
32365 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32367 gcc_assert (sc != NULL);
32369 cached_can_issue_more = sc->cached_can_issue_more;
32370 last_scheduled_insn = sc->last_scheduled_insn;
32371 load_store_pendulum = sc->load_store_pendulum;
32372 divide_cnt = sc->divide_cnt;
32373 vec_pairing = sc->vec_pairing;
32378 rs6000_free_sched_context (void *_sc)
32380 gcc_assert (_sc != NULL);
32386 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32388 switch (get_attr_type (insn))
32403 /* Length in units of the trampoline for entering a nested function. */
32406 rs6000_trampoline_size (void)
32410 switch (DEFAULT_ABI)
32413 gcc_unreachable ();
32416 ret = (TARGET_32BIT) ? 12 : 24;
32420 gcc_assert (!TARGET_32BIT);
32426 ret = (TARGET_32BIT) ? 40 : 48;
32433 /* Emit RTL insns to initialize the variable parts of a trampoline.
32434 FNADDR is an RTX for the address of the function's pure code.
32435 CXT is an RTX for the static chain value for the function. */
32438 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32440 int regsize = (TARGET_32BIT) ? 4 : 8;
32441 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32442 rtx ctx_reg = force_reg (Pmode, cxt);
32443 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32445 switch (DEFAULT_ABI)
32448 gcc_unreachable ();
32450 /* Under AIX, just build the 3 word function descriptor */
32453 rtx fnmem, fn_reg, toc_reg;
32455 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32456 error ("you cannot take the address of a nested function if you use "
32457 "the %qs option", "-mno-pointers-to-nested-functions");
32459 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32460 fn_reg = gen_reg_rtx (Pmode);
32461 toc_reg = gen_reg_rtx (Pmode);
32463 /* Macro to shorten the code expansions below. */
32464 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32466 m_tramp = replace_equiv_address (m_tramp, addr);
32468 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32469 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32470 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32471 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32472 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32478 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32482 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32483 LCT_NORMAL, VOIDmode,
32485 GEN_INT (rs6000_trampoline_size ()), SImode,
32493 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32494 identifier as an argument, so the front end shouldn't look it up. */
32497 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32499 return is_attribute_p ("altivec", attr_id);
32502 /* Handle the "altivec" attribute. The attribute may have
32503 arguments as follows:
32505 __attribute__((altivec(vector__)))
32506 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32507 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32509 and may appear more than once (e.g., 'vector bool char') in a
32510 given declaration. */
32513 rs6000_handle_altivec_attribute (tree *node,
32514 tree name ATTRIBUTE_UNUSED,
32516 int flags ATTRIBUTE_UNUSED,
32517 bool *no_add_attrs)
32519 tree type = *node, result = NULL_TREE;
32523 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32524 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32525 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32528 while (POINTER_TYPE_P (type)
32529 || TREE_CODE (type) == FUNCTION_TYPE
32530 || TREE_CODE (type) == METHOD_TYPE
32531 || TREE_CODE (type) == ARRAY_TYPE)
32532 type = TREE_TYPE (type);
32534 mode = TYPE_MODE (type);
32536 /* Check for invalid AltiVec type qualifiers. */
32537 if (type == long_double_type_node)
32538 error ("use of %<long double%> in AltiVec types is invalid");
32539 else if (type == boolean_type_node)
32540 error ("use of boolean types in AltiVec types is invalid");
32541 else if (TREE_CODE (type) == COMPLEX_TYPE)
32542 error ("use of %<complex%> in AltiVec types is invalid");
32543 else if (DECIMAL_FLOAT_MODE_P (mode))
32544 error ("use of decimal floating point types in AltiVec types is invalid");
32545 else if (!TARGET_VSX)
32547 if (type == long_unsigned_type_node || type == long_integer_type_node)
32550 error ("use of %<long%> in AltiVec types is invalid for "
32551 "64-bit code without %qs", "-mvsx");
32552 else if (rs6000_warn_altivec_long)
32553 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32556 else if (type == long_long_unsigned_type_node
32557 || type == long_long_integer_type_node)
32558 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32560 else if (type == double_type_node)
32561 error ("use of %<double%> in AltiVec types is invalid without %qs",
32565 switch (altivec_type)
32568 unsigned_p = TYPE_UNSIGNED (type);
32572 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32575 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32578 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32581 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32584 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32586 case E_SFmode: result = V4SF_type_node; break;
32587 case E_DFmode: result = V2DF_type_node; break;
32588 /* If the user says 'vector int bool', we may be handed the 'bool'
32589 attribute _before_ the 'vector' attribute, and so select the
32590 proper type in the 'b' case below. */
32591 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32592 case E_V2DImode: case E_V2DFmode:
32600 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32601 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32602 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32603 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32610 case E_V8HImode: result = pixel_V8HI_type_node;
32616 /* Propagate qualifiers attached to the element type
32617 onto the vector type. */
32618 if (result && result != type && TYPE_QUALS (type))
32619 result = build_qualified_type (result, TYPE_QUALS (type));
32621 *no_add_attrs = true; /* No need to hang on to the attribute. */
32624 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32629 /* AltiVec defines five built-in scalar types that serve as vector
32630 elements; we must teach the compiler how to mangle them. The 128-bit
32631 floating point mangling is target-specific as well. */
32633 static const char *
32634 rs6000_mangle_type (const_tree type)
32636 type = TYPE_MAIN_VARIANT (type);
32638 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32639 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32642 if (type == bool_char_type_node) return "U6__boolc";
32643 if (type == bool_short_type_node) return "U6__bools";
32644 if (type == pixel_type_node) return "u7__pixel";
32645 if (type == bool_int_type_node) return "U6__booli";
32646 if (type == bool_long_long_type_node) return "U6__boolx";
32648 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32650 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32651 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32653 /* For all other types, use the default mangling. */
32657 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32658 struct attribute_spec.handler. */
32661 rs6000_handle_longcall_attribute (tree *node, tree name,
32662 tree args ATTRIBUTE_UNUSED,
32663 int flags ATTRIBUTE_UNUSED,
32664 bool *no_add_attrs)
32666 if (TREE_CODE (*node) != FUNCTION_TYPE
32667 && TREE_CODE (*node) != FIELD_DECL
32668 && TREE_CODE (*node) != TYPE_DECL)
32670 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32672 *no_add_attrs = true;
32678 /* Set longcall attributes on all functions declared when
32679 rs6000_default_long_calls is true. */
32681 rs6000_set_default_type_attributes (tree type)
32683 if (rs6000_default_long_calls
32684 && (TREE_CODE (type) == FUNCTION_TYPE
32685 || TREE_CODE (type) == METHOD_TYPE))
32686 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32688 TYPE_ATTRIBUTES (type));
32691 darwin_set_default_type_attributes (type);
32695 /* Return a reference suitable for calling a function with the
32696 longcall attribute. */
32699 rs6000_longcall_ref (rtx call_ref, rtx arg)
32701 /* System V adds '.' to the internal name, so skip them. */
32702 const char *call_name = XSTR (call_ref, 0);
32703 if (*call_name == '.')
32705 while (*call_name == '.')
32708 tree node = get_identifier (call_name);
32709 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32714 rtx base = const0_rtx;
32716 if (rs6000_pcrel_p (cfun))
32718 rtx reg = gen_rtx_REG (Pmode, regno);
32719 rtx u = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32721 emit_insn (gen_rtx_SET (reg, u));
32725 if (DEFAULT_ABI == ABI_ELFv2)
32726 base = gen_rtx_REG (Pmode, TOC_REGISTER);
32730 base = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
32733 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32734 may be used by a function global entry point. For SysV4, r11
32735 is used by __glink_PLTresolve lazy resolver entry. */
32736 rtx reg = gen_rtx_REG (Pmode, regno);
32737 rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32739 rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg),
32741 emit_insn (gen_rtx_SET (reg, hi));
32742 emit_insn (gen_rtx_SET (reg, lo));
32746 return force_reg (Pmode, call_ref);
32749 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32750 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32753 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32754 struct attribute_spec.handler. */
32756 rs6000_handle_struct_attribute (tree *node, tree name,
32757 tree args ATTRIBUTE_UNUSED,
32758 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32761 if (DECL_P (*node))
32763 if (TREE_CODE (*node) == TYPE_DECL)
32764 type = &TREE_TYPE (*node);
32769 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32770 || TREE_CODE (*type) == UNION_TYPE)))
32772 warning (OPT_Wattributes, "%qE attribute ignored", name);
32773 *no_add_attrs = true;
32776 else if ((is_attribute_p ("ms_struct", name)
32777 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32778 || ((is_attribute_p ("gcc_struct", name)
32779 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32781 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32783 *no_add_attrs = true;
32790 rs6000_ms_bitfield_layout_p (const_tree record_type)
32792 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32793 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32794 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32797 #ifdef USING_ELFOS_H
32799 /* A get_unnamed_section callback, used for switching to toc_section. */
32802 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32804 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32805 && TARGET_MINIMAL_TOC)
32807 if (!toc_initialized)
32809 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32810 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32811 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32812 fprintf (asm_out_file, "\t.tc ");
32813 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32814 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32815 fprintf (asm_out_file, "\n");
32817 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32818 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32819 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32820 fprintf (asm_out_file, " = .+32768\n");
32821 toc_initialized = 1;
32824 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32826 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32828 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32829 if (!toc_initialized)
32831 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32832 toc_initialized = 1;
32837 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32838 if (!toc_initialized)
32840 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32841 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32842 fprintf (asm_out_file, " = .+32768\n");
32843 toc_initialized = 1;
32848 /* Implement TARGET_ASM_INIT_SECTIONS. */
32851 rs6000_elf_asm_init_sections (void)
32854 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32857 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32858 SDATA2_SECTION_ASM_OP);
32861 /* Implement TARGET_SELECT_RTX_SECTION. */
32864 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32865 unsigned HOST_WIDE_INT align)
32867 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32868 return toc_section;
32870 return default_elf_select_rtx_section (mode, x, align);
32873 /* For a SYMBOL_REF, set generic flags and then perform some
32874 target-specific processing.
32876 When the AIX ABI is requested on a non-AIX system, replace the
32877 function name with the real name (with a leading .) rather than the
32878 function descriptor name. This saves a lot of overriding code to
32879 read the prefixes. */
32881 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32883 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32885 default_encode_section_info (decl, rtl, first);
32888 && TREE_CODE (decl) == FUNCTION_DECL
32890 && DEFAULT_ABI == ABI_AIX)
32892 rtx sym_ref = XEXP (rtl, 0);
32893 size_t len = strlen (XSTR (sym_ref, 0));
32894 char *str = XALLOCAVEC (char, len + 2);
32896 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32897 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32902 compare_section_name (const char *section, const char *templ)
32906 len = strlen (templ);
32907 return (strncmp (section, templ, len) == 0
32908 && (section[len] == 0 || section[len] == '.'));
32912 rs6000_elf_in_small_data_p (const_tree decl)
32914 if (rs6000_sdata == SDATA_NONE)
32917 /* We want to merge strings, so we never consider them small data. */
32918 if (TREE_CODE (decl) == STRING_CST)
32921 /* Functions are never in the small data area. */
32922 if (TREE_CODE (decl) == FUNCTION_DECL)
32925 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32927 const char *section = DECL_SECTION_NAME (decl);
32928 if (compare_section_name (section, ".sdata")
32929 || compare_section_name (section, ".sdata2")
32930 || compare_section_name (section, ".gnu.linkonce.s")
32931 || compare_section_name (section, ".sbss")
32932 || compare_section_name (section, ".sbss2")
32933 || compare_section_name (section, ".gnu.linkonce.sb")
32934 || strcmp (section, ".PPC.EMB.sdata0") == 0
32935 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32940 /* If we are told not to put readonly data in sdata, then don't. */
32941 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32942 && !rs6000_readonly_in_sdata)
32945 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32948 && size <= g_switch_value
32949 /* If it's not public, and we're not going to reference it there,
32950 there's no need to put it in the small data section. */
32951 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32958 #endif /* USING_ELFOS_H */
32960 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32963 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32965 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32968 /* Do not place thread-local symbols refs in the object blocks. */
32971 rs6000_use_blocks_for_decl_p (const_tree decl)
32973 return !DECL_THREAD_LOCAL_P (decl);
32976 /* Return a REG that occurs in ADDR with coefficient 1.
32977 ADDR can be effectively incremented by incrementing REG.
32979 r0 is special and we must not select it as an address
32980 register by this routine since our caller will try to
32981 increment the returned register via an "la" instruction. */
32984 find_addr_reg (rtx addr)
32986 while (GET_CODE (addr) == PLUS)
32988 if (REG_P (XEXP (addr, 0))
32989 && REGNO (XEXP (addr, 0)) != 0)
32990 addr = XEXP (addr, 0);
32991 else if (REG_P (XEXP (addr, 1))
32992 && REGNO (XEXP (addr, 1)) != 0)
32993 addr = XEXP (addr, 1);
32994 else if (CONSTANT_P (XEXP (addr, 0)))
32995 addr = XEXP (addr, 1);
32996 else if (CONSTANT_P (XEXP (addr, 1)))
32997 addr = XEXP (addr, 0);
32999 gcc_unreachable ();
33001 gcc_assert (REG_P (addr) && REGNO (addr) != 0);
33006 rs6000_fatal_bad_address (rtx op)
33008 fatal_insn ("bad address", op);
33013 typedef struct branch_island_d {
33014 tree function_name;
33020 static vec<branch_island, va_gc> *branch_islands;
33022 /* Remember to generate a branch island for far calls to the given
33026 add_compiler_branch_island (tree label_name, tree function_name,
33029 branch_island bi = {function_name, label_name, line_number};
33030 vec_safe_push (branch_islands, bi);
33033 /* Generate far-jump branch islands for everything recorded in
33034 branch_islands. Invoked immediately after the last instruction of
33035 the epilogue has been emitted; the branch islands must be appended
33036 to, and contiguous with, the function body. Mach-O stubs are
33037 generated in machopic_output_stub(). */
33040 macho_branch_islands (void)
33044 while (!vec_safe_is_empty (branch_islands))
33046 branch_island *bi = &branch_islands->last ();
33047 const char *label = IDENTIFIER_POINTER (bi->label_name);
33048 const char *name = IDENTIFIER_POINTER (bi->function_name);
33049 char name_buf[512];
33050 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33051 if (name[0] == '*' || name[0] == '&')
33052 strcpy (name_buf, name+1);
33056 strcpy (name_buf+1, name);
33058 strcpy (tmp_buf, "\n");
33059 strcat (tmp_buf, label);
33060 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33061 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33062 dbxout_stabd (N_SLINE, bi->line_number);
33063 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33066 if (TARGET_LINK_STACK)
33069 get_ppc476_thunk_name (name);
33070 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33071 strcat (tmp_buf, name);
33072 strcat (tmp_buf, "\n");
33073 strcat (tmp_buf, label);
33074 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33078 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33079 strcat (tmp_buf, label);
33080 strcat (tmp_buf, "_pic\n");
33081 strcat (tmp_buf, label);
33082 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33085 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33086 strcat (tmp_buf, name_buf);
33087 strcat (tmp_buf, " - ");
33088 strcat (tmp_buf, label);
33089 strcat (tmp_buf, "_pic)\n");
33091 strcat (tmp_buf, "\tmtlr r0\n");
33093 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33094 strcat (tmp_buf, name_buf);
33095 strcat (tmp_buf, " - ");
33096 strcat (tmp_buf, label);
33097 strcat (tmp_buf, "_pic)\n");
33099 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33103 strcat (tmp_buf, ":\n\tlis r12,hi16(");
33104 strcat (tmp_buf, name_buf);
33105 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33106 strcat (tmp_buf, name_buf);
33107 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33109 output_asm_insn (tmp_buf, 0);
33110 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33111 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33112 dbxout_stabd (N_SLINE, bi->line_number);
33113 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33114 branch_islands->pop ();
33118 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33119 already there or not. */
33122 no_previous_def (tree function_name)
33127 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33128 if (function_name == bi->function_name)
33133 /* GET_PREV_LABEL gets the label name from the previous definition of
33137 get_prev_label (tree function_name)
33142 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33143 if (function_name == bi->function_name)
33144 return bi->label_name;
33148 /* Generate PIC and indirect symbol stubs. */
33151 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33153 unsigned int length;
33154 char *symbol_name, *lazy_ptr_name;
33155 char *local_label_0;
33156 static unsigned label = 0;
33158 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33159 symb = (*targetm.strip_name_encoding) (symb);
33162 length = strlen (symb);
33163 symbol_name = XALLOCAVEC (char, length + 32);
33164 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33166 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33167 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33170 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33172 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33176 fprintf (file, "\t.align 5\n");
33178 fprintf (file, "%s:\n", stub);
33179 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33182 local_label_0 = XALLOCAVEC (char, 16);
33183 sprintf (local_label_0, "L%u$spb", label);
33185 fprintf (file, "\tmflr r0\n");
33186 if (TARGET_LINK_STACK)
33189 get_ppc476_thunk_name (name);
33190 fprintf (file, "\tbl %s\n", name);
33191 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33195 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33196 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33198 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33199 lazy_ptr_name, local_label_0);
33200 fprintf (file, "\tmtlr r0\n");
33201 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33202 (TARGET_64BIT ? "ldu" : "lwzu"),
33203 lazy_ptr_name, local_label_0);
33204 fprintf (file, "\tmtctr r12\n");
33205 fprintf (file, "\tbctr\n");
33209 fprintf (file, "\t.align 4\n");
33211 fprintf (file, "%s:\n", stub);
33212 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33214 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33215 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33216 (TARGET_64BIT ? "ldu" : "lwzu"),
33218 fprintf (file, "\tmtctr r12\n");
33219 fprintf (file, "\tbctr\n");
33222 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33223 fprintf (file, "%s:\n", lazy_ptr_name);
33224 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33225 fprintf (file, "%sdyld_stub_binding_helper\n",
33226 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33229 /* Legitimize PIC addresses. If the address is already
33230 position-independent, we return ORIG. Newly generated
33231 position-independent addresses go into a reg. This is REG if non
33232 zero, otherwise we allocate register(s) as necessary. */
33234 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33237 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33242 if (reg == NULL && !reload_completed)
33243 reg = gen_reg_rtx (Pmode);
33245 if (GET_CODE (orig) == CONST)
33249 if (GET_CODE (XEXP (orig, 0)) == PLUS
33250 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33253 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33255 /* Use a different reg for the intermediate value, as
33256 it will be marked UNCHANGING. */
33257 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33258 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33261 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33264 if (CONST_INT_P (offset))
33266 if (SMALL_INT (offset))
33267 return plus_constant (Pmode, base, INTVAL (offset));
33268 else if (!reload_completed)
33269 offset = force_reg (Pmode, offset);
33272 rtx mem = force_const_mem (Pmode, orig);
33273 return machopic_legitimize_pic_address (mem, Pmode, reg);
33276 return gen_rtx_PLUS (Pmode, base, offset);
33279 /* Fall back on generic machopic code. */
33280 return machopic_legitimize_pic_address (orig, mode, reg);
33283 /* Output a .machine directive for the Darwin assembler, and call
33284 the generic start_file routine. */
33287 rs6000_darwin_file_start (void)
33289 static const struct
33293 HOST_WIDE_INT if_set;
33295 { "ppc64", "ppc64", MASK_64BIT },
33296 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33297 { "power4", "ppc970", 0 },
33298 { "G5", "ppc970", 0 },
33299 { "7450", "ppc7450", 0 },
33300 { "7400", "ppc7400", MASK_ALTIVEC },
33301 { "G4", "ppc7400", 0 },
33302 { "750", "ppc750", 0 },
33303 { "740", "ppc750", 0 },
33304 { "G3", "ppc750", 0 },
33305 { "604e", "ppc604e", 0 },
33306 { "604", "ppc604", 0 },
33307 { "603e", "ppc603", 0 },
33308 { "603", "ppc603", 0 },
33309 { "601", "ppc601", 0 },
33310 { NULL, "ppc", 0 } };
33311 const char *cpu_id = "";
33314 rs6000_file_start ();
33315 darwin_file_start ();
33317 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33319 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33320 cpu_id = rs6000_default_cpu;
33322 if (global_options_set.x_rs6000_cpu_index)
33323 cpu_id = processor_target_table[rs6000_cpu_index].name;
33325 /* Look through the mapping array. Pick the first name that either
33326 matches the argument, has a bit set in IF_SET that is also set
33327 in the target flags, or has a NULL name. */
33330 while (mapping[i].arg != NULL
33331 && strcmp (mapping[i].arg, cpu_id) != 0
33332 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33335 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33338 #endif /* TARGET_MACHO */
33342 rs6000_elf_reloc_rw_mask (void)
33346 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33352 /* Record an element in the table of global constructors. SYMBOL is
33353 a SYMBOL_REF of the function to be called; PRIORITY is a number
33354 between 0 and MAX_INIT_PRIORITY.
33356 This differs from default_named_section_asm_out_constructor in
33357 that we have special handling for -mrelocatable. */
33359 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33361 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33363 const char *section = ".ctors";
33366 if (priority != DEFAULT_INIT_PRIORITY)
33368 sprintf (buf, ".ctors.%.5u",
33369 /* Invert the numbering so the linker puts us in the proper
33370 order; constructors are run from right to left, and the
33371 linker sorts in increasing order. */
33372 MAX_INIT_PRIORITY - priority);
33376 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33377 assemble_align (POINTER_SIZE);
33379 if (DEFAULT_ABI == ABI_V4
33380 && (TARGET_RELOCATABLE || flag_pic > 1))
33382 fputs ("\t.long (", asm_out_file);
33383 output_addr_const (asm_out_file, symbol);
33384 fputs (")@fixup\n", asm_out_file);
33387 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33390 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33392 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33394 const char *section = ".dtors";
33397 if (priority != DEFAULT_INIT_PRIORITY)
33399 sprintf (buf, ".dtors.%.5u",
33400 /* Invert the numbering so the linker puts us in the proper
33401 order; constructors are run from right to left, and the
33402 linker sorts in increasing order. */
33403 MAX_INIT_PRIORITY - priority);
33407 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33408 assemble_align (POINTER_SIZE);
33410 if (DEFAULT_ABI == ABI_V4
33411 && (TARGET_RELOCATABLE || flag_pic > 1))
33413 fputs ("\t.long (", asm_out_file);
33414 output_addr_const (asm_out_file, symbol);
33415 fputs (")@fixup\n", asm_out_file);
33418 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33422 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33424 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33426 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33427 ASM_OUTPUT_LABEL (file, name);
33428 fputs (DOUBLE_INT_ASM_OP, file);
33429 rs6000_output_function_entry (file, name);
33430 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33433 fputs ("\t.size\t", file);
33434 assemble_name (file, name);
33435 fputs (",24\n\t.type\t.", file);
33436 assemble_name (file, name);
33437 fputs (",@function\n", file);
33438 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33440 fputs ("\t.globl\t.", file);
33441 assemble_name (file, name);
33446 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33447 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33448 rs6000_output_function_entry (file, name);
33449 fputs (":\n", file);
33454 if (DEFAULT_ABI == ABI_V4
33455 && (TARGET_RELOCATABLE || flag_pic > 1)
33456 && !TARGET_SECURE_PLT
33457 && (!constant_pool_empty_p () || crtl->profile)
33458 && (uses_toc = uses_TOC ()))
33463 switch_to_other_text_partition ();
33464 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33466 fprintf (file, "\t.long ");
33467 assemble_name (file, toc_label_name);
33470 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33471 assemble_name (file, buf);
33474 switch_to_other_text_partition ();
33477 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33478 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33480 if (TARGET_CMODEL == CMODEL_LARGE
33481 && rs6000_global_entry_point_prologue_needed_p ())
33485 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33487 fprintf (file, "\t.quad .TOC.-");
33488 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33489 assemble_name (file, buf);
33493 if (DEFAULT_ABI == ABI_AIX)
33495 const char *desc_name, *orig_name;
33497 orig_name = (*targetm.strip_name_encoding) (name);
33498 desc_name = orig_name;
33499 while (*desc_name == '.')
33502 if (TREE_PUBLIC (decl))
33503 fprintf (file, "\t.globl %s\n", desc_name);
33505 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33506 fprintf (file, "%s:\n", desc_name);
33507 fprintf (file, "\t.long %s\n", orig_name);
33508 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33509 fputs ("\t.long 0\n", file);
33510 fprintf (file, "\t.previous\n");
33512 ASM_OUTPUT_LABEL (file, name);
33515 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33517 rs6000_elf_file_end (void)
33519 #ifdef HAVE_AS_GNU_ATTRIBUTE
33520 /* ??? The value emitted depends on options active at file end.
33521 Assume anyone using #pragma or attributes that might change
33522 options knows what they are doing. */
33523 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33524 && rs6000_passes_float)
33528 if (TARGET_HARD_FLOAT)
33532 if (rs6000_passes_long_double)
33534 if (!TARGET_LONG_DOUBLE_128)
33536 else if (TARGET_IEEEQUAD)
33541 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33543 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33545 if (rs6000_passes_vector)
33546 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33547 (TARGET_ALTIVEC_ABI ? 2 : 1));
33548 if (rs6000_returns_struct)
33549 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33550 aix_struct_return ? 2 : 1);
33553 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33554 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33555 file_end_indicate_exec_stack ();
33558 if (flag_split_stack)
33559 file_end_indicate_split_stack ();
33563 /* We have expanded a CPU builtin, so we need to emit a reference to
33564 the special symbol that LIBC uses to declare it supports the
33565 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33566 switch_to_section (data_section);
33567 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33568 fprintf (asm_out_file, "\t%s %s\n",
33569 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33576 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33577 #define HAVE_XCOFF_DWARF_EXTRAS 0
33580 static enum unwind_info_type
33581 rs6000_xcoff_debug_unwind_info (void)
33587 rs6000_xcoff_asm_output_anchor (rtx symbol)
33591 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33592 SYMBOL_REF_BLOCK_OFFSET (symbol));
33593 fprintf (asm_out_file, "%s", SET_ASM_OP);
33594 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33595 fprintf (asm_out_file, ",");
33596 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33597 fprintf (asm_out_file, "\n");
33601 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33603 fputs (GLOBAL_ASM_OP, stream);
33604 RS6000_OUTPUT_BASENAME (stream, name);
33605 putc ('\n', stream);
33608 /* A get_unnamed_decl callback, used for read-only sections. PTR
33609 points to the section string variable. */
33612 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33614 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33615 *(const char *const *) directive,
33616 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33619 /* Likewise for read-write sections. */
33622 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33624 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33625 *(const char *const *) directive,
33626 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33630 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33632 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33633 *(const char *const *) directive,
33634 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33637 /* A get_unnamed_section callback, used for switching to toc_section. */
33640 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33642 if (TARGET_MINIMAL_TOC)
33644 /* toc_section is always selected at least once from
33645 rs6000_xcoff_file_start, so this is guaranteed to
33646 always be defined once and only once in each file. */
33647 if (!toc_initialized)
33649 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33650 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33651 toc_initialized = 1;
33653 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33654 (TARGET_32BIT ? "" : ",3"));
33657 fputs ("\t.toc\n", asm_out_file);
33660 /* Implement TARGET_ASM_INIT_SECTIONS. */
33663 rs6000_xcoff_asm_init_sections (void)
33665 read_only_data_section
33666 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33667 &xcoff_read_only_section_name);
33669 private_data_section
33670 = get_unnamed_section (SECTION_WRITE,
33671 rs6000_xcoff_output_readwrite_section_asm_op,
33672 &xcoff_private_data_section_name);
33674 read_only_private_data_section
33675 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33676 &xcoff_private_rodata_section_name);
33679 = get_unnamed_section (SECTION_TLS,
33680 rs6000_xcoff_output_tls_section_asm_op,
33681 &xcoff_tls_data_section_name);
33683 tls_private_data_section
33684 = get_unnamed_section (SECTION_TLS,
33685 rs6000_xcoff_output_tls_section_asm_op,
33686 &xcoff_private_data_section_name);
33689 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33691 readonly_data_section = read_only_data_section;
33695 rs6000_xcoff_reloc_rw_mask (void)
33701 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33702 tree decl ATTRIBUTE_UNUSED)
33705 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33707 if (flags & SECTION_EXCLUDE)
33709 else if (flags & SECTION_DEBUG)
33711 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33714 else if (flags & SECTION_CODE)
33716 else if (flags & SECTION_TLS)
33718 else if (flags & SECTION_WRITE)
33723 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33724 (flags & SECTION_CODE) ? "." : "",
33725 name, suffix[smclass], flags & SECTION_ENTSIZE);
33728 #define IN_NAMED_SECTION(DECL) \
33729 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33730 && DECL_SECTION_NAME (DECL) != NULL)
33733 rs6000_xcoff_select_section (tree decl, int reloc,
33734 unsigned HOST_WIDE_INT align)
33736 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33738 if (align > BIGGEST_ALIGNMENT)
33740 resolve_unique_section (decl, reloc, true);
33741 if (IN_NAMED_SECTION (decl))
33742 return get_named_section (decl, NULL, reloc);
33745 if (decl_readonly_section (decl, reloc))
33747 if (TREE_PUBLIC (decl))
33748 return read_only_data_section;
33750 return read_only_private_data_section;
33755 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33757 if (TREE_PUBLIC (decl))
33758 return tls_data_section;
33759 else if (bss_initializer_p (decl))
33761 /* Convert to COMMON to emit in BSS. */
33762 DECL_COMMON (decl) = 1;
33763 return tls_comm_section;
33766 return tls_private_data_section;
33770 if (TREE_PUBLIC (decl))
33771 return data_section;
33773 return private_data_section;
33778 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33782 /* Use select_section for private data and uninitialized data with
33783 alignment <= BIGGEST_ALIGNMENT. */
33784 if (!TREE_PUBLIC (decl)
33785 || DECL_COMMON (decl)
33786 || (DECL_INITIAL (decl) == NULL_TREE
33787 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33788 || DECL_INITIAL (decl) == error_mark_node
33789 || (flag_zero_initialized_in_bss
33790 && initializer_zerop (DECL_INITIAL (decl))))
33793 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33794 name = (*targetm.strip_name_encoding) (name);
33795 set_decl_section_name (decl, name);
33798 /* Select section for constant in constant pool.
33800 On RS/6000, all constants are in the private read-only data area.
33801 However, if this is being placed in the TOC it must be output as a
33805 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33806 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33808 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33809 return toc_section;
33811 return read_only_private_data_section;
33814 /* Remove any trailing [DS] or the like from the symbol name. */
33816 static const char *
33817 rs6000_xcoff_strip_name_encoding (const char *name)
33822 len = strlen (name);
33823 if (name[len - 1] == ']')
33824 return ggc_alloc_string (name, len - 4);
33829 /* Section attributes. AIX is always PIC. */
33831 static unsigned int
33832 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33834 unsigned int align;
33835 unsigned int flags = default_section_type_flags (decl, name, reloc);
33837 /* Align to at least UNIT size. */
33838 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33839 align = MIN_UNITS_PER_WORD;
33841 /* Increase alignment of large objects if not already stricter. */
33842 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33843 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33844 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33846 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33849 /* Output at beginning of assembler file.
33851 Initialize the section names for the RS/6000 at this point.
33853 Specify filename, including full path, to assembler.
33855 We want to go into the TOC section so at least one .toc will be emitted.
33856 Also, in order to output proper .bs/.es pairs, we need at least one static
33857 [RW] section emitted.
33859 Finally, declare mcount when profiling to make the assembler happy. */
33862 rs6000_xcoff_file_start (void)
33864 rs6000_gen_section_name (&xcoff_bss_section_name,
33865 main_input_filename, ".bss_");
33866 rs6000_gen_section_name (&xcoff_private_data_section_name,
33867 main_input_filename, ".rw_");
33868 rs6000_gen_section_name (&xcoff_private_rodata_section_name,
33869 main_input_filename, ".rop_");
33870 rs6000_gen_section_name (&xcoff_read_only_section_name,
33871 main_input_filename, ".ro_");
33872 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33873 main_input_filename, ".tls_");
33874 rs6000_gen_section_name (&xcoff_tbss_section_name,
33875 main_input_filename, ".tbss_[UL]");
33877 fputs ("\t.file\t", asm_out_file);
33878 output_quoted_string (asm_out_file, main_input_filename);
33879 fputc ('\n', asm_out_file);
33880 if (write_symbols != NO_DEBUG)
33881 switch_to_section (private_data_section);
33882 switch_to_section (toc_section);
33883 switch_to_section (text_section);
33885 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33886 rs6000_file_start ();
33889 /* Output at end of assembler file.
33890 On the RS/6000, referencing data should automatically pull in text. */
33893 rs6000_xcoff_file_end (void)
33895 switch_to_section (text_section);
33896 fputs ("_section_.text:\n", asm_out_file);
33897 switch_to_section (data_section);
33898 fputs (TARGET_32BIT
33899 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33903 struct declare_alias_data
33906 bool function_descriptor;
33909 /* Declare alias N. A helper function for for_node_and_aliases. */
33912 rs6000_declare_alias (struct symtab_node *n, void *d)
33914 struct declare_alias_data *data = (struct declare_alias_data *)d;
33915 /* Main symbol is output specially, because varasm machinery does part of
33916 the job for us - we do not need to declare .globl/lglobs and such. */
33917 if (!n->alias || n->weakref)
33920 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33923 /* Prevent assemble_alias from trying to use .set pseudo operation
33924 that does not behave as expected by the middle-end. */
33925 TREE_ASM_WRITTEN (n->decl) = true;
33927 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33928 char *buffer = (char *) alloca (strlen (name) + 2);
33930 int dollar_inside = 0;
33932 strcpy (buffer, name);
33933 p = strchr (buffer, '$');
33937 p = strchr (p + 1, '$');
33939 if (TREE_PUBLIC (n->decl))
33941 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33943 if (dollar_inside) {
33944 if (data->function_descriptor)
33945 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33946 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33948 if (data->function_descriptor)
33950 fputs ("\t.globl .", data->file);
33951 RS6000_OUTPUT_BASENAME (data->file, buffer);
33952 putc ('\n', data->file);
33954 fputs ("\t.globl ", data->file);
33955 RS6000_OUTPUT_BASENAME (data->file, buffer);
33956 putc ('\n', data->file);
33958 #ifdef ASM_WEAKEN_DECL
33959 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33960 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33967 if (data->function_descriptor)
33968 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33969 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33971 if (data->function_descriptor)
33973 fputs ("\t.lglobl .", data->file);
33974 RS6000_OUTPUT_BASENAME (data->file, buffer);
33975 putc ('\n', data->file);
33977 fputs ("\t.lglobl ", data->file);
33978 RS6000_OUTPUT_BASENAME (data->file, buffer);
33979 putc ('\n', data->file);
33981 if (data->function_descriptor)
33982 fputs (".", data->file);
33983 RS6000_OUTPUT_BASENAME (data->file, buffer);
33984 fputs (":\n", data->file);
33989 #ifdef HAVE_GAS_HIDDEN
33990 /* Helper function to calculate visibility of a DECL
33991 and return the value as a const string. */
33993 static const char *
33994 rs6000_xcoff_visibility (tree decl)
33996 static const char * const visibility_types[] = {
33997 "", ",protected", ",hidden", ",internal"
34000 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34001 return visibility_types[vis];
34006 /* This macro produces the initial definition of a function name.
34007 On the RS/6000, we need to place an extra '.' in the function name and
34008 output the function descriptor.
34009 Dollar signs are converted to underscores.
34011 The csect for the function will have already been created when
34012 text_section was selected. We do have to go back to that csect, however.
34014 The third and fourth parameters to the .function pseudo-op (16 and 044)
34015 are placeholders which no longer have any use.
34017 Because AIX assembler's .set command has unexpected semantics, we output
34018 all aliases as alternative labels in front of the definition. */
34021 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34023 char *buffer = (char *) alloca (strlen (name) + 1);
34025 int dollar_inside = 0;
34026 struct declare_alias_data data = {file, false};
34028 strcpy (buffer, name);
34029 p = strchr (buffer, '$');
34033 p = strchr (p + 1, '$');
34035 if (TREE_PUBLIC (decl))
34037 if (!RS6000_WEAK || !DECL_WEAK (decl))
34039 if (dollar_inside) {
34040 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34041 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34043 fputs ("\t.globl .", file);
34044 RS6000_OUTPUT_BASENAME (file, buffer);
34045 #ifdef HAVE_GAS_HIDDEN
34046 fputs (rs6000_xcoff_visibility (decl), file);
34053 if (dollar_inside) {
34054 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34055 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34057 fputs ("\t.lglobl .", file);
34058 RS6000_OUTPUT_BASENAME (file, buffer);
34061 fputs ("\t.csect ", file);
34062 RS6000_OUTPUT_BASENAME (file, buffer);
34063 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34064 RS6000_OUTPUT_BASENAME (file, buffer);
34065 fputs (":\n", file);
34066 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34068 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34069 RS6000_OUTPUT_BASENAME (file, buffer);
34070 fputs (", TOC[tc0], 0\n", file);
34072 switch_to_section (function_section (decl));
34074 RS6000_OUTPUT_BASENAME (file, buffer);
34075 fputs (":\n", file);
34076 data.function_descriptor = true;
34077 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34079 if (!DECL_IGNORED_P (decl))
34081 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34082 xcoffout_declare_function (file, decl, buffer);
34083 else if (write_symbols == DWARF2_DEBUG)
34085 name = (*targetm.strip_name_encoding) (name);
34086 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34093 /* Output assembly language to globalize a symbol from a DECL,
34094 possibly with visibility. */
34097 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34099 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34100 fputs (GLOBAL_ASM_OP, stream);
34101 RS6000_OUTPUT_BASENAME (stream, name);
34102 #ifdef HAVE_GAS_HIDDEN
34103 fputs (rs6000_xcoff_visibility (decl), stream);
34105 putc ('\n', stream);
34108 /* Output assembly language to define a symbol as COMMON from a DECL,
34109 possibly with visibility. */
34112 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34113 tree decl ATTRIBUTE_UNUSED,
34115 unsigned HOST_WIDE_INT size,
34116 unsigned HOST_WIDE_INT align)
34118 unsigned HOST_WIDE_INT align2 = 2;
34121 align2 = floor_log2 (align / BITS_PER_UNIT);
34125 fputs (COMMON_ASM_OP, stream);
34126 RS6000_OUTPUT_BASENAME (stream, name);
34129 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34132 #ifdef HAVE_GAS_HIDDEN
34134 fputs (rs6000_xcoff_visibility (decl), stream);
34136 putc ('\n', stream);
34139 /* This macro produces the initial definition of a object (variable) name.
34140 Because AIX assembler's .set command has unexpected semantics, we output
34141 all aliases as alternative labels in front of the definition. */
34144 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34146 struct declare_alias_data data = {file, false};
34147 RS6000_OUTPUT_BASENAME (file, name);
34148 fputs (":\n", file);
34149 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34153 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34156 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34158 fputs (integer_asm_op (size, FALSE), file);
34159 assemble_name (file, label);
34160 fputs ("-$", file);
34163 /* Output a symbol offset relative to the dbase for the current object.
34164 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34167 __gcc_unwind_dbase is embedded in all executables/libraries through
34168 libgcc/config/rs6000/crtdbase.S. */
34171 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34173 fputs (integer_asm_op (size, FALSE), file);
34174 assemble_name (file, label);
34175 fputs("-__gcc_unwind_dbase", file);
34180 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34184 const char *symname;
34186 default_encode_section_info (decl, rtl, first);
34188 /* Careful not to prod global register variables. */
34191 symbol = XEXP (rtl, 0);
34192 if (!SYMBOL_REF_P (symbol))
34195 flags = SYMBOL_REF_FLAGS (symbol);
34197 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34198 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34200 SYMBOL_REF_FLAGS (symbol) = flags;
34202 /* Append mapping class to extern decls. */
34203 symname = XSTR (symbol, 0);
34204 if (decl /* sync condition with assemble_external () */
34205 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34206 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34207 || TREE_CODE (decl) == FUNCTION_DECL)
34208 && symname[strlen (symname) - 1] != ']')
34210 char *newname = (char *) alloca (strlen (symname) + 5);
34211 strcpy (newname, symname);
34212 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34213 ? "[DS]" : "[UA]"));
34214 XSTR (symbol, 0) = ggc_strdup (newname);
34217 #endif /* HAVE_AS_TLS */
34218 #endif /* TARGET_XCOFF */
34221 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34222 const char *name, const char *val)
34224 fputs ("\t.weak\t", stream);
34225 RS6000_OUTPUT_BASENAME (stream, name);
34226 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34227 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34230 fputs ("[DS]", stream);
34231 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34233 fputs (rs6000_xcoff_visibility (decl), stream);
34235 fputs ("\n\t.weak\t.", stream);
34236 RS6000_OUTPUT_BASENAME (stream, name);
34238 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34240 fputs (rs6000_xcoff_visibility (decl), stream);
34242 fputc ('\n', stream);
34245 #ifdef ASM_OUTPUT_DEF
34246 ASM_OUTPUT_DEF (stream, name, val);
34248 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34249 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34251 fputs ("\t.set\t.", stream);
34252 RS6000_OUTPUT_BASENAME (stream, name);
34253 fputs (",.", stream);
34254 RS6000_OUTPUT_BASENAME (stream, val);
34255 fputc ('\n', stream);
34261 /* Return true if INSN should not be copied. */
34264 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34266 return recog_memoized (insn) >= 0
34267 && get_attr_cannot_copy (insn);
34270 /* Compute a (partial) cost for rtx X. Return true if the complete
34271 cost has been computed, and false if subexpressions should be
34272 scanned. In either case, *TOTAL contains the cost result. */
34275 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34276 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34278 int code = GET_CODE (x);
34282 /* On the RS/6000, if it is valid in the insn, it is free. */
34284 if (((outer_code == SET
34285 || outer_code == PLUS
34286 || outer_code == MINUS)
34287 && (satisfies_constraint_I (x)
34288 || satisfies_constraint_L (x)))
34289 || (outer_code == AND
34290 && (satisfies_constraint_K (x)
34292 ? satisfies_constraint_L (x)
34293 : satisfies_constraint_J (x))))
34294 || ((outer_code == IOR || outer_code == XOR)
34295 && (satisfies_constraint_K (x)
34297 ? satisfies_constraint_L (x)
34298 : satisfies_constraint_J (x))))
34299 || outer_code == ASHIFT
34300 || outer_code == ASHIFTRT
34301 || outer_code == LSHIFTRT
34302 || outer_code == ROTATE
34303 || outer_code == ROTATERT
34304 || outer_code == ZERO_EXTRACT
34305 || (outer_code == MULT
34306 && satisfies_constraint_I (x))
34307 || ((outer_code == DIV || outer_code == UDIV
34308 || outer_code == MOD || outer_code == UMOD)
34309 && exact_log2 (INTVAL (x)) >= 0)
34310 || (outer_code == COMPARE
34311 && (satisfies_constraint_I (x)
34312 || satisfies_constraint_K (x)))
34313 || ((outer_code == EQ || outer_code == NE)
34314 && (satisfies_constraint_I (x)
34315 || satisfies_constraint_K (x)
34317 ? satisfies_constraint_L (x)
34318 : satisfies_constraint_J (x))))
34319 || (outer_code == GTU
34320 && satisfies_constraint_I (x))
34321 || (outer_code == LTU
34322 && satisfies_constraint_P (x)))
34327 else if ((outer_code == PLUS
34328 && reg_or_add_cint_operand (x, VOIDmode))
34329 || (outer_code == MINUS
34330 && reg_or_sub_cint_operand (x, VOIDmode))
34331 || ((outer_code == SET
34332 || outer_code == IOR
34333 || outer_code == XOR)
34335 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34337 *total = COSTS_N_INSNS (1);
34343 case CONST_WIDE_INT:
34347 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34351 /* When optimizing for size, MEM should be slightly more expensive
34352 than generating address, e.g., (plus (reg) (const)).
34353 L1 cache latency is about two instructions. */
34354 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34355 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34356 *total += COSTS_N_INSNS (100);
34365 if (FLOAT_MODE_P (mode))
34366 *total = rs6000_cost->fp;
34368 *total = COSTS_N_INSNS (1);
34372 if (CONST_INT_P (XEXP (x, 1))
34373 && satisfies_constraint_I (XEXP (x, 1)))
34375 if (INTVAL (XEXP (x, 1)) >= -256
34376 && INTVAL (XEXP (x, 1)) <= 255)
34377 *total = rs6000_cost->mulsi_const9;
34379 *total = rs6000_cost->mulsi_const;
34381 else if (mode == SFmode)
34382 *total = rs6000_cost->fp;
34383 else if (FLOAT_MODE_P (mode))
34384 *total = rs6000_cost->dmul;
34385 else if (mode == DImode)
34386 *total = rs6000_cost->muldi;
34388 *total = rs6000_cost->mulsi;
34392 if (mode == SFmode)
34393 *total = rs6000_cost->fp;
34395 *total = rs6000_cost->dmul;
34400 if (FLOAT_MODE_P (mode))
34402 *total = mode == DFmode ? rs6000_cost->ddiv
34403 : rs6000_cost->sdiv;
34410 if (CONST_INT_P (XEXP (x, 1))
34411 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34413 if (code == DIV || code == MOD)
34415 *total = COSTS_N_INSNS (2);
34418 *total = COSTS_N_INSNS (1);
34422 if (GET_MODE (XEXP (x, 1)) == DImode)
34423 *total = rs6000_cost->divdi;
34425 *total = rs6000_cost->divsi;
34427 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34428 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34429 *total += COSTS_N_INSNS (2);
34433 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34437 *total = COSTS_N_INSNS (4);
34441 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34445 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34449 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34452 *total = COSTS_N_INSNS (1);
34456 if (CONST_INT_P (XEXP (x, 1)))
34458 rtx left = XEXP (x, 0);
34459 rtx_code left_code = GET_CODE (left);
34461 /* rotate-and-mask: 1 insn. */
34462 if ((left_code == ROTATE
34463 || left_code == ASHIFT
34464 || left_code == LSHIFTRT)
34465 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34467 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34468 if (!CONST_INT_P (XEXP (left, 1)))
34469 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34470 *total += COSTS_N_INSNS (1);
34474 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34475 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34476 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34477 || (val & 0xffff) == val
34478 || (val & 0xffff0000) == val
34479 || ((val & 0xffff) == 0 && mode == SImode))
34481 *total = rtx_cost (left, mode, AND, 0, speed);
34482 *total += COSTS_N_INSNS (1);
34487 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34489 *total = rtx_cost (left, mode, AND, 0, speed);
34490 *total += COSTS_N_INSNS (2);
34495 *total = COSTS_N_INSNS (1);
34500 *total = COSTS_N_INSNS (1);
34506 *total = COSTS_N_INSNS (1);
34510 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34511 the sign extend and shift separately within the insn. */
34512 if (TARGET_EXTSWSLI && mode == DImode
34513 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34514 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34525 /* Handle mul_highpart. */
34526 if (outer_code == TRUNCATE
34527 && GET_CODE (XEXP (x, 0)) == MULT)
34529 if (mode == DImode)
34530 *total = rs6000_cost->muldi;
34532 *total = rs6000_cost->mulsi;
34535 else if (outer_code == AND)
34538 *total = COSTS_N_INSNS (1);
34543 if (MEM_P (XEXP (x, 0)))
34546 *total = COSTS_N_INSNS (1);
34552 if (!FLOAT_MODE_P (mode))
34554 *total = COSTS_N_INSNS (1);
34560 case UNSIGNED_FLOAT:
34563 case FLOAT_TRUNCATE:
34564 *total = rs6000_cost->fp;
34568 if (mode == DFmode)
34569 *total = rs6000_cost->sfdf_convert;
34571 *total = rs6000_cost->fp;
34575 switch (XINT (x, 1))
34578 *total = rs6000_cost->fp;
34590 *total = COSTS_N_INSNS (1);
34593 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34595 *total = rs6000_cost->fp;
34604 /* Carry bit requires mode == Pmode.
34605 NEG or PLUS already counted so only add one. */
34607 && (outer_code == NEG || outer_code == PLUS))
34609 *total = COSTS_N_INSNS (1);
34617 if (outer_code == SET)
34619 if (XEXP (x, 1) == const0_rtx)
34621 *total = COSTS_N_INSNS (2);
34626 *total = COSTS_N_INSNS (3);
34631 if (outer_code == COMPARE)
34645 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34648 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34649 int opno, int *total, bool speed)
34651 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34654 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34655 "opno = %d, total = %d, speed = %s, x:\n",
34656 ret ? "complete" : "scan inner",
34657 GET_MODE_NAME (mode),
34658 GET_RTX_NAME (outer_code),
34661 speed ? "true" : "false");
34669 rs6000_insn_cost (rtx_insn *insn, bool speed)
34671 if (recog_memoized (insn) < 0)
34675 return get_attr_length (insn);
34677 int cost = get_attr_cost (insn);
34681 int n = get_attr_length (insn) / 4;
34682 enum attr_type type = get_attr_type (insn);
34689 cost = COSTS_N_INSNS (n + 1);
34693 switch (get_attr_size (insn))
34696 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34699 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34702 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34705 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34708 gcc_unreachable ();
34712 switch (get_attr_size (insn))
34715 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34718 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34721 gcc_unreachable ();
34726 cost = n * rs6000_cost->fp;
34729 cost = n * rs6000_cost->dmul;
34732 cost = n * rs6000_cost->sdiv;
34735 cost = n * rs6000_cost->ddiv;
34742 cost = COSTS_N_INSNS (n + 2);
34746 cost = COSTS_N_INSNS (n);
34752 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34755 rs6000_debug_address_cost (rtx x, machine_mode mode,
34756 addr_space_t as, bool speed)
34758 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34760 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34761 ret, speed ? "true" : "false");
34768 /* A C expression returning the cost of moving data from a register of class
34769 CLASS1 to one of CLASS2. */
34772 rs6000_register_move_cost (machine_mode mode,
34773 reg_class_t from, reg_class_t to)
34776 reg_class_t rclass;
34778 if (TARGET_DEBUG_COST)
34781 /* If we have VSX, we can easily move between FPR or Altivec registers,
34782 otherwise we can only easily move within classes.
34783 Do this first so we give best-case answers for union classes
34784 containing both gprs and vsx regs. */
34785 HARD_REG_SET to_vsx, from_vsx;
34786 COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
34787 AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
34788 COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
34789 AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
34790 if (!hard_reg_set_empty_p (to_vsx)
34791 && !hard_reg_set_empty_p (from_vsx)
34793 || hard_reg_set_intersect_p (to_vsx, from_vsx)))
34795 int reg = FIRST_FPR_REGNO;
34797 || (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
34798 && TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
34799 reg = FIRST_ALTIVEC_REGNO;
34800 ret = 2 * hard_regno_nregs (reg, mode);
34803 /* Moves from/to GENERAL_REGS. */
34804 else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
34805 || (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
34807 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34809 if (TARGET_DIRECT_MOVE)
34811 /* Keep the cost for direct moves above that for within
34812 a register class even if the actual processor cost is
34813 comparable. We do this because a direct move insn
34814 can't be a nop, whereas with ideal register
34815 allocation a move within the same class might turn
34816 out to be a nop. */
34817 if (rs6000_tune == PROCESSOR_POWER9
34818 || rs6000_tune == PROCESSOR_FUTURE)
34819 ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34821 ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34822 /* SFmode requires a conversion when moving between gprs
34824 if (mode == SFmode)
34828 ret = (rs6000_memory_move_cost (mode, rclass, false)
34829 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34832 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34834 else if (rclass == CR_REGS)
34837 /* For those processors that have slow LR/CTR moves, make them more
34838 expensive than memory in order to bias spills to memory .*/
34839 else if ((rs6000_tune == PROCESSOR_POWER6
34840 || rs6000_tune == PROCESSOR_POWER7
34841 || rs6000_tune == PROCESSOR_POWER8
34842 || rs6000_tune == PROCESSOR_POWER9)
34843 && reg_class_subset_p (rclass, SPECIAL_REGS))
34844 ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34847 /* A move will cost one instruction per GPR moved. */
34848 ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34851 /* Everything else has to go through GENERAL_REGS. */
34853 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34854 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34856 if (TARGET_DEBUG_COST)
34858 if (dbg_cost_ctrl == 1)
34860 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
34861 ret, GET_MODE_NAME (mode), reg_class_names[from],
34862 reg_class_names[to]);
34869 /* A C expressions returning the cost of moving data of MODE from a register to
34873 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34874 bool in ATTRIBUTE_UNUSED)
34878 if (TARGET_DEBUG_COST)
34881 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34882 ret = 4 * hard_regno_nregs (0, mode);
34883 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34884 || reg_classes_intersect_p (rclass, VSX_REGS)))
34885 ret = 4 * hard_regno_nregs (32, mode);
34886 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34887 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34889 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34891 if (TARGET_DEBUG_COST)
34893 if (dbg_cost_ctrl == 1)
34895 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34896 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34903 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
34905 The register allocator chooses GEN_OR_VSX_REGS for the allocno
34906 class if GENERAL_REGS and VSX_REGS cost is lower than the memory
34907 cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
34908 move cost between GENERAL_REGS and VSX_REGS low.
34910 It might seem reasonable to use a union class. After all, if usage
34911 of vsr is low and gpr high, it might make sense to spill gpr to vsr
34912 rather than memory. However, in cases where register pressure of
34913 both is high, like the cactus_adm spec test, allowing
34914 GEN_OR_VSX_REGS as the allocno class results in bad decisions in
34915 the first scheduling pass. This is partly due to an allocno of
34916 GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
34917 class, which gives too high a pressure for GENERAL_REGS and too low
34918 for VSX_REGS. So, force a choice of the subclass here.
34920 The best class is also the union if GENERAL_REGS and VSX_REGS have
34921 the same cost. In that case we do use GEN_OR_VSX_REGS as the
34922 allocno class, since trying to narrow down the class by regno mode
34923 is prone to error. For example, SImode is allowed in VSX regs and
34924 in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
34925 it would be wrong to choose an allocno of GENERAL_REGS based on
34929 rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
34930 reg_class_t allocno_class,
34931 reg_class_t best_class)
34933 switch (allocno_class)
34935 case GEN_OR_VSX_REGS:
34936 /* best_class must be a subset of allocno_class. */
34937 gcc_checking_assert (best_class == GEN_OR_VSX_REGS
34938 || best_class == GEN_OR_FLOAT_REGS
34939 || best_class == VSX_REGS
34940 || best_class == ALTIVEC_REGS
34941 || best_class == FLOAT_REGS
34942 || best_class == GENERAL_REGS
34943 || best_class == BASE_REGS);
34944 /* Use best_class but choose wider classes when copying from the
34945 wider class to best_class is cheap. This mimics IRA choice
34946 of allocno class. */
34947 if (best_class == BASE_REGS)
34948 return GENERAL_REGS;
34950 && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
34958 return allocno_class;
34961 /* Returns a code for a target-specific builtin that implements
34962 reciprocal of the function, or NULL_TREE if not available. */
34965 rs6000_builtin_reciprocal (tree fndecl)
34967 switch (DECL_FUNCTION_CODE (fndecl))
34969 case VSX_BUILTIN_XVSQRTDP:
34970 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34973 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34975 case VSX_BUILTIN_XVSQRTSP:
34976 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34979 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34986 /* Load up a constant. If the mode is a vector mode, splat the value across
34987 all of the vector elements. */
34990 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34994 if (mode == SFmode || mode == DFmode)
34996 rtx d = const_double_from_real_value (dconst, mode);
34997 reg = force_reg (mode, d);
34999 else if (mode == V4SFmode)
35001 rtx d = const_double_from_real_value (dconst, SFmode);
35002 rtvec v = gen_rtvec (4, d, d, d, d);
35003 reg = gen_reg_rtx (mode);
35004 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35006 else if (mode == V2DFmode)
35008 rtx d = const_double_from_real_value (dconst, DFmode);
35009 rtvec v = gen_rtvec (2, d, d);
35010 reg = gen_reg_rtx (mode);
35011 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35014 gcc_unreachable ();
35019 /* Generate an FMA instruction. */
35022 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35024 machine_mode mode = GET_MODE (target);
35027 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35028 gcc_assert (dst != NULL);
35031 emit_move_insn (target, dst);
35034 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35037 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35039 machine_mode mode = GET_MODE (dst);
35042 /* This is a tad more complicated, since the fnma_optab is for
35043 a different expression: fma(-m1, m2, a), which is the same
35044 thing except in the case of signed zeros.
35046 Fortunately we know that if FMA is supported that FNMSUB is
35047 also supported in the ISA. Just expand it directly. */
35049 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35051 r = gen_rtx_NEG (mode, a);
35052 r = gen_rtx_FMA (mode, m1, m2, r);
35053 r = gen_rtx_NEG (mode, r);
35054 emit_insn (gen_rtx_SET (dst, r));
35057 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35058 add a reg_note saying that this was a division. Support both scalar and
35059 vector divide. Assumes no trapping math and finite arguments. */
35062 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35064 machine_mode mode = GET_MODE (dst);
35065 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35068 /* Low precision estimates guarantee 5 bits of accuracy. High
35069 precision estimates guarantee 14 bits of accuracy. SFmode
35070 requires 23 bits of accuracy. DFmode requires 52 bits of
35071 accuracy. Each pass at least doubles the accuracy, leading
35072 to the following. */
35073 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35074 if (mode == DFmode || mode == V2DFmode)
35077 enum insn_code code = optab_handler (smul_optab, mode);
35078 insn_gen_fn gen_mul = GEN_FCN (code);
35080 gcc_assert (code != CODE_FOR_nothing);
35082 one = rs6000_load_constant_and_splat (mode, dconst1);
35084 /* x0 = 1./d estimate */
35085 x0 = gen_reg_rtx (mode);
35086 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35089 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35092 /* e0 = 1. - d * x0 */
35093 e0 = gen_reg_rtx (mode);
35094 rs6000_emit_nmsub (e0, d, x0, one);
35096 /* x1 = x0 + e0 * x0 */
35097 x1 = gen_reg_rtx (mode);
35098 rs6000_emit_madd (x1, e0, x0, x0);
35100 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35101 ++i, xprev = xnext, eprev = enext) {
35103 /* enext = eprev * eprev */
35104 enext = gen_reg_rtx (mode);
35105 emit_insn (gen_mul (enext, eprev, eprev));
35107 /* xnext = xprev + enext * xprev */
35108 xnext = gen_reg_rtx (mode);
35109 rs6000_emit_madd (xnext, enext, xprev, xprev);
35115 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35117 /* u = n * xprev */
35118 u = gen_reg_rtx (mode);
35119 emit_insn (gen_mul (u, n, xprev));
35121 /* v = n - (d * u) */
35122 v = gen_reg_rtx (mode);
35123 rs6000_emit_nmsub (v, d, u, n);
35125 /* dst = (v * xprev) + u */
35126 rs6000_emit_madd (dst, v, xprev, u);
35129 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35132 /* Goldschmidt's Algorithm for single/double-precision floating point
35133 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35136 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35138 machine_mode mode = GET_MODE (src);
35139 rtx e = gen_reg_rtx (mode);
35140 rtx g = gen_reg_rtx (mode);
35141 rtx h = gen_reg_rtx (mode);
35143 /* Low precision estimates guarantee 5 bits of accuracy. High
35144 precision estimates guarantee 14 bits of accuracy. SFmode
35145 requires 23 bits of accuracy. DFmode requires 52 bits of
35146 accuracy. Each pass at least doubles the accuracy, leading
35147 to the following. */
35148 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35149 if (mode == DFmode || mode == V2DFmode)
35154 enum insn_code code = optab_handler (smul_optab, mode);
35155 insn_gen_fn gen_mul = GEN_FCN (code);
35157 gcc_assert (code != CODE_FOR_nothing);
35159 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35161 /* e = rsqrt estimate */
35162 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35165 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35168 rtx zero = force_reg (mode, CONST0_RTX (mode));
35170 if (mode == SFmode)
35172 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35175 emit_move_insn (e, target);
35179 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35180 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35184 /* g = sqrt estimate. */
35185 emit_insn (gen_mul (g, e, src));
35186 /* h = 1/(2*sqrt) estimate. */
35187 emit_insn (gen_mul (h, e, mhalf));
35193 rtx t = gen_reg_rtx (mode);
35194 rs6000_emit_nmsub (t, g, h, mhalf);
35195 /* Apply correction directly to 1/rsqrt estimate. */
35196 rs6000_emit_madd (dst, e, t, e);
35200 for (i = 0; i < passes; i++)
35202 rtx t1 = gen_reg_rtx (mode);
35203 rtx g1 = gen_reg_rtx (mode);
35204 rtx h1 = gen_reg_rtx (mode);
35206 rs6000_emit_nmsub (t1, g, h, mhalf);
35207 rs6000_emit_madd (g1, g, t1, g);
35208 rs6000_emit_madd (h1, h, t1, h);
35213 /* Multiply by 2 for 1/rsqrt. */
35214 emit_insn (gen_add3_insn (dst, h, h));
35219 rtx t = gen_reg_rtx (mode);
35220 rs6000_emit_nmsub (t, g, h, mhalf);
35221 rs6000_emit_madd (dst, g, t, g);
35227 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35228 (Power7) targets. DST is the target, and SRC is the argument operand. */
35231 rs6000_emit_popcount (rtx dst, rtx src)
35233 machine_mode mode = GET_MODE (dst);
35236 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35237 if (TARGET_POPCNTD)
35239 if (mode == SImode)
35240 emit_insn (gen_popcntdsi2 (dst, src));
35242 emit_insn (gen_popcntddi2 (dst, src));
35246 tmp1 = gen_reg_rtx (mode);
35248 if (mode == SImode)
35250 emit_insn (gen_popcntbsi2 (tmp1, src));
35251 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35253 tmp2 = force_reg (SImode, tmp2);
35254 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35258 emit_insn (gen_popcntbdi2 (tmp1, src));
35259 tmp2 = expand_mult (DImode, tmp1,
35260 GEN_INT ((HOST_WIDE_INT)
35261 0x01010101 << 32 | 0x01010101),
35263 tmp2 = force_reg (DImode, tmp2);
35264 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35269 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35270 target, and SRC is the argument operand. */
35273 rs6000_emit_parity (rtx dst, rtx src)
35275 machine_mode mode = GET_MODE (dst);
35278 tmp = gen_reg_rtx (mode);
35280 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35283 if (mode == SImode)
35285 emit_insn (gen_popcntbsi2 (tmp, src));
35286 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35290 emit_insn (gen_popcntbdi2 (tmp, src));
35291 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35296 if (mode == SImode)
35298 /* Is mult+shift >= shift+xor+shift+xor? */
35299 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35301 rtx tmp1, tmp2, tmp3, tmp4;
35303 tmp1 = gen_reg_rtx (SImode);
35304 emit_insn (gen_popcntbsi2 (tmp1, src));
35306 tmp2 = gen_reg_rtx (SImode);
35307 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35308 tmp3 = gen_reg_rtx (SImode);
35309 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35311 tmp4 = gen_reg_rtx (SImode);
35312 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35313 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35316 rs6000_emit_popcount (tmp, src);
35317 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35321 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35322 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35324 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35326 tmp1 = gen_reg_rtx (DImode);
35327 emit_insn (gen_popcntbdi2 (tmp1, src));
35329 tmp2 = gen_reg_rtx (DImode);
35330 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35331 tmp3 = gen_reg_rtx (DImode);
35332 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35334 tmp4 = gen_reg_rtx (DImode);
35335 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35336 tmp5 = gen_reg_rtx (DImode);
35337 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35339 tmp6 = gen_reg_rtx (DImode);
35340 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35341 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35344 rs6000_emit_popcount (tmp, src);
35345 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35349 /* Expand an Altivec constant permutation for little endian mode.
35350 OP0 and OP1 are the input vectors and TARGET is the output vector.
35351 SEL specifies the constant permutation vector.
35353 There are two issues: First, the two input operands must be
35354 swapped so that together they form a double-wide array in LE
35355 order. Second, the vperm instruction has surprising behavior
35356 in LE mode: it interprets the elements of the source vectors
35357 in BE mode ("left to right") and interprets the elements of
35358 the destination vector in LE mode ("right to left"). To
35359 correct for this, we must subtract each element of the permute
35360 control vector from 31.
35362 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35363 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35364 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35365 serve as the permute control vector. Then, in BE mode,
35369 places the desired result in vr9. However, in LE mode the
35370 vector contents will be
35372 vr10 = 00000003 00000002 00000001 00000000
35373 vr11 = 00000007 00000006 00000005 00000004
35375 The result of the vperm using the same permute control vector is
35377 vr9 = 05000000 07000000 01000000 03000000
35379 That is, the leftmost 4 bytes of vr10 are interpreted as the
35380 source for the rightmost 4 bytes of vr9, and so on.
35382 If we change the permute control vector to
35384 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35392 vr9 = 00000006 00000004 00000002 00000000. */
35395 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35396 const vec_perm_indices &sel)
35400 rtx constv, unspec;
35402 /* Unpack and adjust the constant selector. */
35403 for (i = 0; i < 16; ++i)
35405 unsigned int elt = 31 - (sel[i] & 31);
35406 perm[i] = GEN_INT (elt);
35409 /* Expand to a permute, swapping the inputs and using the
35410 adjusted selector. */
35412 op0 = force_reg (V16QImode, op0);
35414 op1 = force_reg (V16QImode, op1);
35416 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35417 constv = force_reg (V16QImode, constv);
35418 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35420 if (!REG_P (target))
35422 rtx tmp = gen_reg_rtx (V16QImode);
35423 emit_move_insn (tmp, unspec);
35427 emit_move_insn (target, unspec);
35430 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35431 permute control vector. But here it's not a constant, so we must
35432 generate a vector NAND or NOR to do the adjustment. */
35435 altivec_expand_vec_perm_le (rtx operands[4])
35437 rtx notx, iorx, unspec;
35438 rtx target = operands[0];
35439 rtx op0 = operands[1];
35440 rtx op1 = operands[2];
35441 rtx sel = operands[3];
35443 rtx norreg = gen_reg_rtx (V16QImode);
35444 machine_mode mode = GET_MODE (target);
35446 /* Get everything in regs so the pattern matches. */
35448 op0 = force_reg (mode, op0);
35450 op1 = force_reg (mode, op1);
35452 sel = force_reg (V16QImode, sel);
35453 if (!REG_P (target))
35454 tmp = gen_reg_rtx (mode);
35456 if (TARGET_P9_VECTOR)
35458 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35463 /* Invert the selector with a VNAND if available, else a VNOR.
35464 The VNAND is preferred for future fusion opportunities. */
35465 notx = gen_rtx_NOT (V16QImode, sel);
35466 iorx = (TARGET_P8_VECTOR
35467 ? gen_rtx_IOR (V16QImode, notx, notx)
35468 : gen_rtx_AND (V16QImode, notx, notx));
35469 emit_insn (gen_rtx_SET (norreg, iorx));
35471 /* Permute with operands reversed and adjusted selector. */
35472 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35476 /* Copy into target, possibly by way of a register. */
35477 if (!REG_P (target))
35479 emit_move_insn (tmp, unspec);
35483 emit_move_insn (target, unspec);
35486 /* Expand an Altivec constant permutation. Return true if we match
35487 an efficient implementation; false to fall back to VPERM.
35489 OP0 and OP1 are the input vectors and TARGET is the output vector.
35490 SEL specifies the constant permutation vector. */
35493 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35494 const vec_perm_indices &sel)
35496 struct altivec_perm_insn {
35497 HOST_WIDE_INT mask;
35498 enum insn_code impl;
35499 unsigned char perm[16];
35501 static const struct altivec_perm_insn patterns[] = {
35502 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35503 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35504 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35505 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35506 { OPTION_MASK_ALTIVEC,
35507 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35508 : CODE_FOR_altivec_vmrglb_direct),
35509 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35510 { OPTION_MASK_ALTIVEC,
35511 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35512 : CODE_FOR_altivec_vmrglh_direct),
35513 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35514 { OPTION_MASK_ALTIVEC,
35515 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35516 : CODE_FOR_altivec_vmrglw_direct),
35517 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35518 { OPTION_MASK_ALTIVEC,
35519 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35520 : CODE_FOR_altivec_vmrghb_direct),
35521 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35522 { OPTION_MASK_ALTIVEC,
35523 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35524 : CODE_FOR_altivec_vmrghh_direct),
35525 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35526 { OPTION_MASK_ALTIVEC,
35527 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35528 : CODE_FOR_altivec_vmrghw_direct),
35529 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35530 { OPTION_MASK_P8_VECTOR,
35531 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35532 : CODE_FOR_p8_vmrgow_v4sf_direct),
35533 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35534 { OPTION_MASK_P8_VECTOR,
35535 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35536 : CODE_FOR_p8_vmrgew_v4sf_direct),
35537 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35540 unsigned int i, j, elt, which;
35541 unsigned char perm[16];
35545 /* Unpack the constant selector. */
35546 for (i = which = 0; i < 16; ++i)
35549 which |= (elt < 16 ? 1 : 2);
35553 /* Simplify the constant selector based on operands. */
35557 gcc_unreachable ();
35561 if (!rtx_equal_p (op0, op1))
35566 for (i = 0; i < 16; ++i)
35578 /* Look for splat patterns. */
35583 for (i = 0; i < 16; ++i)
35584 if (perm[i] != elt)
35588 if (!BYTES_BIG_ENDIAN)
35590 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35596 for (i = 0; i < 16; i += 2)
35597 if (perm[i] != elt || perm[i + 1] != elt + 1)
35601 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35602 x = gen_reg_rtx (V8HImode);
35603 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35605 emit_move_insn (target, gen_lowpart (V16QImode, x));
35612 for (i = 0; i < 16; i += 4)
35614 || perm[i + 1] != elt + 1
35615 || perm[i + 2] != elt + 2
35616 || perm[i + 3] != elt + 3)
35620 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35621 x = gen_reg_rtx (V4SImode);
35622 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35624 emit_move_insn (target, gen_lowpart (V16QImode, x));
35630 /* Look for merge and pack patterns. */
35631 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35635 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35638 elt = patterns[j].perm[0];
35639 if (perm[0] == elt)
35641 else if (perm[0] == elt + 16)
35645 for (i = 1; i < 16; ++i)
35647 elt = patterns[j].perm[i];
35649 elt = (elt >= 16 ? elt - 16 : elt + 16);
35650 else if (one_vec && elt >= 16)
35652 if (perm[i] != elt)
35657 enum insn_code icode = patterns[j].impl;
35658 machine_mode omode = insn_data[icode].operand[0].mode;
35659 machine_mode imode = insn_data[icode].operand[1].mode;
35661 /* For little-endian, don't use vpkuwum and vpkuhum if the
35662 underlying vector type is not V4SI and V8HI, respectively.
35663 For example, using vpkuwum with a V8HI picks up the even
35664 halfwords (BE numbering) when the even halfwords (LE
35665 numbering) are what we need. */
35666 if (!BYTES_BIG_ENDIAN
35667 && icode == CODE_FOR_altivec_vpkuwum_direct
35669 && GET_MODE (op0) != V4SImode)
35671 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35673 if (!BYTES_BIG_ENDIAN
35674 && icode == CODE_FOR_altivec_vpkuhum_direct
35676 && GET_MODE (op0) != V8HImode)
35678 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35681 /* For little-endian, the two input operands must be swapped
35682 (or swapped back) to ensure proper right-to-left numbering
35684 if (swapped ^ !BYTES_BIG_ENDIAN)
35685 std::swap (op0, op1);
35686 if (imode != V16QImode)
35688 op0 = gen_lowpart (imode, op0);
35689 op1 = gen_lowpart (imode, op1);
35691 if (omode == V16QImode)
35694 x = gen_reg_rtx (omode);
35695 emit_insn (GEN_FCN (icode) (x, op0, op1));
35696 if (omode != V16QImode)
35697 emit_move_insn (target, gen_lowpart (V16QImode, x));
35702 if (!BYTES_BIG_ENDIAN)
35704 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35711 /* Expand a VSX Permute Doubleword constant permutation.
35712 Return true if we match an efficient implementation. */
35715 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35716 unsigned char perm0, unsigned char perm1)
35720 /* If both selectors come from the same operand, fold to single op. */
35721 if ((perm0 & 2) == (perm1 & 2))
35728 /* If both operands are equal, fold to simpler permutation. */
35729 if (rtx_equal_p (op0, op1))
35732 perm1 = (perm1 & 1) + 2;
35734 /* If the first selector comes from the second operand, swap. */
35735 else if (perm0 & 2)
35741 std::swap (op0, op1);
35743 /* If the second selector does not come from the second operand, fail. */
35744 else if ((perm1 & 2) == 0)
35748 if (target != NULL)
35750 machine_mode vmode, dmode;
35753 vmode = GET_MODE (target);
35754 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35755 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35756 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35757 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35758 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35759 emit_insn (gen_rtx_SET (target, x));
35764 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35767 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35768 rtx op1, const vec_perm_indices &sel)
35770 bool testing_p = !target;
35772 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35773 if (TARGET_ALTIVEC && testing_p)
35776 /* Check for ps_merge* or xxpermdi insns. */
35777 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35781 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35782 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35784 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35788 if (TARGET_ALTIVEC)
35790 /* Force the target-independent code to lower to V16QImode. */
35791 if (vmode != V16QImode)
35793 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35800 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35801 OP0 and OP1 are the input vectors and TARGET is the output vector.
35802 PERM specifies the constant permutation vector. */
35805 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35806 machine_mode vmode, const vec_perm_builder &perm)
35808 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35810 emit_move_insn (target, x);
35813 /* Expand an extract even operation. */
35816 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35818 machine_mode vmode = GET_MODE (target);
35819 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35820 vec_perm_builder perm (nelt, nelt, 1);
35822 for (i = 0; i < nelt; i++)
35823 perm.quick_push (i * 2);
35825 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35828 /* Expand a vector interleave operation. */
35831 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35833 machine_mode vmode = GET_MODE (target);
35834 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35835 vec_perm_builder perm (nelt, nelt, 1);
35837 high = (highp ? 0 : nelt / 2);
35838 for (i = 0; i < nelt / 2; i++)
35840 perm.quick_push (i + high);
35841 perm.quick_push (i + nelt + high);
35844 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35847 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35849 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35851 HOST_WIDE_INT hwi_scale (scale);
35852 REAL_VALUE_TYPE r_pow;
35853 rtvec v = rtvec_alloc (2);
35855 rtx scale_vec = gen_reg_rtx (V2DFmode);
35856 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35857 elt = const_double_from_real_value (r_pow, DFmode);
35858 RTVEC_ELT (v, 0) = elt;
35859 RTVEC_ELT (v, 1) = elt;
35860 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35861 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35864 /* Return an RTX representing where to find the function value of a
35865 function returning MODE. */
35867 rs6000_complex_function_value (machine_mode mode)
35869 unsigned int regno;
35871 machine_mode inner = GET_MODE_INNER (mode);
35872 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35874 if (TARGET_FLOAT128_TYPE
35876 || (mode == TCmode && TARGET_IEEEQUAD)))
35877 regno = ALTIVEC_ARG_RETURN;
35879 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35880 regno = FP_ARG_RETURN;
35884 regno = GP_ARG_RETURN;
35886 /* 32-bit is OK since it'll go in r3/r4. */
35887 if (TARGET_32BIT && inner_bytes >= 4)
35888 return gen_rtx_REG (mode, regno);
35891 if (inner_bytes >= 8)
35892 return gen_rtx_REG (mode, regno);
35894 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35896 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35897 GEN_INT (inner_bytes));
35898 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35901 /* Return an rtx describing a return value of MODE as a PARALLEL
35902 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35903 stride REG_STRIDE. */
35906 rs6000_parallel_return (machine_mode mode,
35907 int n_elts, machine_mode elt_mode,
35908 unsigned int regno, unsigned int reg_stride)
35910 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35913 for (i = 0; i < n_elts; i++)
35915 rtx r = gen_rtx_REG (elt_mode, regno);
35916 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35917 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35918 regno += reg_stride;
35924 /* Target hook for TARGET_FUNCTION_VALUE.
35926 An integer value is in r3 and a floating-point value is in fp1,
35927 unless -msoft-float. */
35930 rs6000_function_value (const_tree valtype,
35931 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35932 bool outgoing ATTRIBUTE_UNUSED)
35935 unsigned int regno;
35936 machine_mode elt_mode;
35939 /* Special handling for structs in darwin64. */
35941 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35943 CUMULATIVE_ARGS valcum;
35947 valcum.fregno = FP_ARG_MIN_REG;
35948 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35949 /* Do a trial code generation as if this were going to be passed as
35950 an argument; if any part goes in memory, we return NULL. */
35951 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35954 /* Otherwise fall through to standard ABI rules. */
35957 mode = TYPE_MODE (valtype);
35959 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35960 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35962 int first_reg, n_regs;
35964 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35966 /* _Decimal128 must use even/odd register pairs. */
35967 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35968 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35972 first_reg = ALTIVEC_ARG_RETURN;
35976 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35979 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35980 if (TARGET_32BIT && TARGET_POWERPC64)
35989 int count = GET_MODE_SIZE (mode) / 4;
35990 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35993 if ((INTEGRAL_TYPE_P (valtype)
35994 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35995 || POINTER_TYPE_P (valtype))
35996 mode = TARGET_32BIT ? SImode : DImode;
35998 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35999 /* _Decimal128 must use an even/odd register pair. */
36000 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36001 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36002 && !FLOAT128_VECTOR_P (mode))
36003 regno = FP_ARG_RETURN;
36004 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36005 && targetm.calls.split_complex_arg)
36006 return rs6000_complex_function_value (mode);
36007 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36008 return register is used in both cases, and we won't see V2DImode/V2DFmode
36009 for pure altivec, combine the two cases. */
36010 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36011 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36012 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36013 regno = ALTIVEC_ARG_RETURN;
36015 regno = GP_ARG_RETURN;
36017 return gen_rtx_REG (mode, regno);
36020 /* Define how to find the value returned by a library function
36021 assuming the value has mode MODE. */
36023 rs6000_libcall_value (machine_mode mode)
36025 unsigned int regno;
36027 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36028 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36029 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36031 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36032 /* _Decimal128 must use an even/odd register pair. */
36033 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36034 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
36035 regno = FP_ARG_RETURN;
36036 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36037 return register is used in both cases, and we won't see V2DImode/V2DFmode
36038 for pure altivec, combine the two cases. */
36039 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36040 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36041 regno = ALTIVEC_ARG_RETURN;
36042 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36043 return rs6000_complex_function_value (mode);
36045 regno = GP_ARG_RETURN;
36047 return gen_rtx_REG (mode, regno);
36050 /* Compute register pressure classes. We implement the target hook to avoid
36051 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
36052 lead to incorrect estimates of number of available registers and therefor
36053 increased register pressure/spill. */
36055 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36060 pressure_classes[n++] = GENERAL_REGS;
36062 pressure_classes[n++] = VSX_REGS;
36065 if (TARGET_ALTIVEC)
36066 pressure_classes[n++] = ALTIVEC_REGS;
36067 if (TARGET_HARD_FLOAT)
36068 pressure_classes[n++] = FLOAT_REGS;
36070 pressure_classes[n++] = CR_REGS;
36071 pressure_classes[n++] = SPECIAL_REGS;
36076 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36077 Frame pointer elimination is automatically handled.
36079 For the RS/6000, if frame pointer elimination is being done, we would like
36080 to convert ap into fp, not sp.
36082 We need r30 if -mminimal-toc was specified, and there are constant pool
36086 rs6000_can_eliminate (const int from, const int to)
36088 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36089 ? ! frame_pointer_needed
36090 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36091 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36092 || constant_pool_empty_p ()
36096 /* Define the offset between two registers, FROM to be eliminated and its
36097 replacement TO, at the start of a routine. */
36099 rs6000_initial_elimination_offset (int from, int to)
36101 rs6000_stack_t *info = rs6000_stack_info ();
36102 HOST_WIDE_INT offset;
36104 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36105 offset = info->push_p ? 0 : -info->total_size;
36106 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36108 offset = info->push_p ? 0 : -info->total_size;
36109 if (FRAME_GROWS_DOWNWARD)
36110 offset += info->fixed_size + info->vars_size + info->parm_size;
36112 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36113 offset = FRAME_GROWS_DOWNWARD
36114 ? info->fixed_size + info->vars_size + info->parm_size
36116 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36117 offset = info->total_size;
36118 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36119 offset = info->push_p ? info->total_size : 0;
36120 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36123 gcc_unreachable ();
36128 /* Fill in sizes of registers used by unwinder. */
36131 rs6000_init_dwarf_reg_sizes_extra (tree address)
36133 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36136 machine_mode mode = TYPE_MODE (char_type_node);
36137 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36138 rtx mem = gen_rtx_MEM (BLKmode, addr);
36139 rtx value = gen_int_mode (16, mode);
36141 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36142 The unwinder still needs to know the size of Altivec registers. */
36144 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36146 int column = DWARF_REG_TO_UNWIND_COLUMN
36147 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36148 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36150 emit_move_insn (adjust_address (mem, mode, offset), value);
36155 /* Map internal gcc register numbers to debug format register numbers.
36156 FORMAT specifies the type of debug register number to use:
36157 0 -- debug information, except for frame-related sections
36158 1 -- DWARF .debug_frame section
36159 2 -- DWARF .eh_frame section */
36162 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36164 /* On some platforms, we use the standard DWARF register
36165 numbering for .debug_info and .debug_frame. */
36166 if ((format == 0 && write_symbols == DWARF2_DEBUG) || format == 1)
36168 #ifdef RS6000_USE_DWARF_NUMBERING
36171 if (FP_REGNO_P (regno))
36172 return regno - FIRST_FPR_REGNO + 32;
36173 if (ALTIVEC_REGNO_P (regno))
36174 return regno - FIRST_ALTIVEC_REGNO + 1124;
36175 if (regno == LR_REGNO)
36177 if (regno == CTR_REGNO)
36179 if (regno == CA_REGNO)
36180 return 101; /* XER */
36181 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36182 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36183 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36184 to the DWARF reg for CR. */
36185 if (format == 1 && regno == CR2_REGNO)
36187 if (CR_REGNO_P (regno))
36188 return regno - CR0_REGNO + 86;
36189 if (regno == VRSAVE_REGNO)
36191 if (regno == VSCR_REGNO)
36194 /* These do not make much sense. */
36195 if (regno == FRAME_POINTER_REGNUM)
36197 if (regno == ARG_POINTER_REGNUM)
36202 gcc_unreachable ();
36206 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36207 information, and also for .eh_frame. */
36208 /* Translate the regnos to their numbers in GCC 7 (and before). */
36211 if (FP_REGNO_P (regno))
36212 return regno - FIRST_FPR_REGNO + 32;
36213 if (ALTIVEC_REGNO_P (regno))
36214 return regno - FIRST_ALTIVEC_REGNO + 77;
36215 if (regno == LR_REGNO)
36217 if (regno == CTR_REGNO)
36219 if (regno == CA_REGNO)
36220 return 76; /* XER */
36221 if (CR_REGNO_P (regno))
36222 return regno - CR0_REGNO + 68;
36223 if (regno == VRSAVE_REGNO)
36225 if (regno == VSCR_REGNO)
36228 if (regno == FRAME_POINTER_REGNUM)
36230 if (regno == ARG_POINTER_REGNUM)
36235 gcc_unreachable ();
36238 /* target hook eh_return_filter_mode */
36239 static scalar_int_mode
36240 rs6000_eh_return_filter_mode (void)
36242 return TARGET_32BIT ? SImode : word_mode;
36245 /* Target hook for translate_mode_attribute. */
36246 static machine_mode
36247 rs6000_translate_mode_attribute (machine_mode mode)
36249 if ((FLOAT128_IEEE_P (mode)
36250 && ieee128_float_type_node == long_double_type_node)
36251 || (FLOAT128_IBM_P (mode)
36252 && ibm128_float_type_node == long_double_type_node))
36253 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
36257 /* Target hook for scalar_mode_supported_p. */
36259 rs6000_scalar_mode_supported_p (scalar_mode mode)
36261 /* -m32 does not support TImode. This is the default, from
36262 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36263 same ABI as for -m32. But default_scalar_mode_supported_p allows
36264 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36265 for -mpowerpc64. */
36266 if (TARGET_32BIT && mode == TImode)
36269 if (DECIMAL_FLOAT_MODE_P (mode))
36270 return default_decimal_float_supported_p ();
36271 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36274 return default_scalar_mode_supported_p (mode);
36277 /* Target hook for vector_mode_supported_p. */
36279 rs6000_vector_mode_supported_p (machine_mode mode)
36281 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36282 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36284 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36291 /* Target hook for floatn_mode. */
36292 static opt_scalar_float_mode
36293 rs6000_floatn_mode (int n, bool extended)
36303 if (TARGET_FLOAT128_TYPE)
36304 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36306 return opt_scalar_float_mode ();
36309 return opt_scalar_float_mode ();
36312 /* Those are the only valid _FloatNx types. */
36313 gcc_unreachable ();
36327 if (TARGET_FLOAT128_TYPE)
36328 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36330 return opt_scalar_float_mode ();
36333 return opt_scalar_float_mode ();
36339 /* Target hook for c_mode_for_suffix. */
36340 static machine_mode
36341 rs6000_c_mode_for_suffix (char suffix)
36343 if (TARGET_FLOAT128_TYPE)
36345 if (suffix == 'q' || suffix == 'Q')
36346 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36348 /* At the moment, we are not defining a suffix for IBM extended double.
36349 If/when the default for -mabi=ieeelongdouble is changed, and we want
36350 to support __ibm128 constants in legacy library code, we may need to
36351 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36352 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36353 __float80 constants. */
36359 /* Target hook for invalid_arg_for_unprototyped_fn. */
36360 static const char *
36361 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36363 return (!rs6000_darwin64_abi
36365 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36366 && (funcdecl == NULL_TREE
36367 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36368 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36369 ? N_("AltiVec argument passed to unprototyped function")
36373 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36374 setup by using __stack_chk_fail_local hidden function instead of
36375 calling __stack_chk_fail directly. Otherwise it is better to call
36376 __stack_chk_fail directly. */
36378 static tree ATTRIBUTE_UNUSED
36379 rs6000_stack_protect_fail (void)
36381 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36382 ? default_hidden_stack_protect_fail ()
36383 : default_external_stack_protect_fail ();
36386 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36389 static unsigned HOST_WIDE_INT
36390 rs6000_asan_shadow_offset (void)
36392 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36396 /* Mask options that we want to support inside of attribute((target)) and
36397 #pragma GCC target operations. Note, we do not include things like
36398 64/32-bit, endianness, hard/soft floating point, etc. that would have
36399 different calling sequences. */
36401 struct rs6000_opt_mask {
36402 const char *name; /* option name */
36403 HOST_WIDE_INT mask; /* mask to set */
36404 bool invert; /* invert sense of mask */
36405 bool valid_target; /* option is a target option */
36408 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36410 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36411 { "cmpb", OPTION_MASK_CMPB, false, true },
36412 { "crypto", OPTION_MASK_CRYPTO, false, true },
36413 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36414 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36415 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36417 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36418 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36419 { "fprnd", OPTION_MASK_FPRND, false, true },
36420 { "future", OPTION_MASK_FUTURE, false, true },
36421 { "hard-dfp", OPTION_MASK_DFP, false, true },
36422 { "htm", OPTION_MASK_HTM, false, true },
36423 { "isel", OPTION_MASK_ISEL, false, true },
36424 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36425 { "mfpgpr", 0, false, true },
36426 { "modulo", OPTION_MASK_MODULO, false, true },
36427 { "mulhw", OPTION_MASK_MULHW, false, true },
36428 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36429 { "pcrel", OPTION_MASK_PCREL, false, true },
36430 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36431 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36432 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36433 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36434 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36435 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36436 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36437 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36438 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36439 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36440 { "prefixed-addr", OPTION_MASK_PREFIXED_ADDR, false, true },
36441 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36442 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36443 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36444 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36445 { "string", 0, false, true },
36446 { "update", OPTION_MASK_NO_UPDATE, true , true },
36447 { "vsx", OPTION_MASK_VSX, false, true },
36448 #ifdef OPTION_MASK_64BIT
36450 { "aix64", OPTION_MASK_64BIT, false, false },
36451 { "aix32", OPTION_MASK_64BIT, true, false },
36453 { "64", OPTION_MASK_64BIT, false, false },
36454 { "32", OPTION_MASK_64BIT, true, false },
36457 #ifdef OPTION_MASK_EABI
36458 { "eabi", OPTION_MASK_EABI, false, false },
36460 #ifdef OPTION_MASK_LITTLE_ENDIAN
36461 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36462 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36464 #ifdef OPTION_MASK_RELOCATABLE
36465 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36467 #ifdef OPTION_MASK_STRICT_ALIGN
36468 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36470 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36471 { "string", 0, false, false },
36474 /* Builtin mask mapping for printing the flags. */
36475 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36477 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36478 { "vsx", RS6000_BTM_VSX, false, false },
36479 { "fre", RS6000_BTM_FRE, false, false },
36480 { "fres", RS6000_BTM_FRES, false, false },
36481 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36482 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36483 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36484 { "cell", RS6000_BTM_CELL, false, false },
36485 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36486 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36487 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36488 { "crypto", RS6000_BTM_CRYPTO, false, false },
36489 { "htm", RS6000_BTM_HTM, false, false },
36490 { "hard-dfp", RS6000_BTM_DFP, false, false },
36491 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36492 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36493 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36494 { "float128", RS6000_BTM_FLOAT128, false, false },
36495 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36498 /* Option variables that we want to support inside attribute((target)) and
36499 #pragma GCC target operations. */
36501 struct rs6000_opt_var {
36502 const char *name; /* option name */
36503 size_t global_offset; /* offset of the option in global_options. */
36504 size_t target_offset; /* offset of the option in target options. */
36507 static struct rs6000_opt_var const rs6000_opt_vars[] =
36510 offsetof (struct gcc_options, x_TARGET_FRIZ),
36511 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36512 { "avoid-indexed-addresses",
36513 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36514 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36516 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36517 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36518 { "optimize-swaps",
36519 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36520 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36521 { "allow-movmisalign",
36522 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36523 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36525 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36526 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36528 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36529 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36530 { "align-branch-targets",
36531 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36532 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36534 offsetof (struct gcc_options, x_tls_markers),
36535 offsetof (struct cl_target_option, x_tls_markers), },
36537 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36538 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36540 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36541 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36542 { "speculate-indirect-jumps",
36543 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36544 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36547 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36548 parsing. Return true if there were no errors. */
36551 rs6000_inner_target_options (tree args, bool attr_p)
36555 if (args == NULL_TREE)
36558 else if (TREE_CODE (args) == STRING_CST)
36560 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36563 while ((q = strtok (p, ",")) != NULL)
36565 bool error_p = false;
36566 bool not_valid_p = false;
36567 const char *cpu_opt = NULL;
36570 if (strncmp (q, "cpu=", 4) == 0)
36572 int cpu_index = rs6000_cpu_name_lookup (q+4);
36573 if (cpu_index >= 0)
36574 rs6000_cpu_index = cpu_index;
36581 else if (strncmp (q, "tune=", 5) == 0)
36583 int tune_index = rs6000_cpu_name_lookup (q+5);
36584 if (tune_index >= 0)
36585 rs6000_tune_index = tune_index;
36595 bool invert = false;
36599 if (strncmp (r, "no-", 3) == 0)
36605 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36606 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36608 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36610 if (!rs6000_opt_masks[i].valid_target)
36611 not_valid_p = true;
36615 rs6000_isa_flags_explicit |= mask;
36617 /* VSX needs altivec, so -mvsx automagically sets
36618 altivec and disables -mavoid-indexed-addresses. */
36621 if (mask == OPTION_MASK_VSX)
36623 mask |= OPTION_MASK_ALTIVEC;
36624 TARGET_AVOID_XFORM = 0;
36628 if (rs6000_opt_masks[i].invert)
36632 rs6000_isa_flags &= ~mask;
36634 rs6000_isa_flags |= mask;
36639 if (error_p && !not_valid_p)
36641 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36642 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36644 size_t j = rs6000_opt_vars[i].global_offset;
36645 *((int *) ((char *)&global_options + j)) = !invert;
36647 not_valid_p = false;
36655 const char *eprefix, *esuffix;
36660 eprefix = "__attribute__((__target__(";
36665 eprefix = "#pragma GCC target ";
36670 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36672 else if (not_valid_p)
36673 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36675 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36680 else if (TREE_CODE (args) == TREE_LIST)
36684 tree value = TREE_VALUE (args);
36687 bool ret2 = rs6000_inner_target_options (value, attr_p);
36691 args = TREE_CHAIN (args);
36693 while (args != NULL_TREE);
36698 error ("attribute %<target%> argument not a string");
36705 /* Print out the target options as a list for -mdebug=target. */
36708 rs6000_debug_target_options (tree args, const char *prefix)
36710 if (args == NULL_TREE)
36711 fprintf (stderr, "%s<NULL>", prefix);
36713 else if (TREE_CODE (args) == STRING_CST)
36715 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36718 while ((q = strtok (p, ",")) != NULL)
36721 fprintf (stderr, "%s\"%s\"", prefix, q);
36726 else if (TREE_CODE (args) == TREE_LIST)
36730 tree value = TREE_VALUE (args);
36733 rs6000_debug_target_options (value, prefix);
36736 args = TREE_CHAIN (args);
36738 while (args != NULL_TREE);
36742 gcc_unreachable ();
36748 /* Hook to validate attribute((target("..."))). */
36751 rs6000_valid_attribute_p (tree fndecl,
36752 tree ARG_UNUSED (name),
36756 struct cl_target_option cur_target;
36759 tree new_target, new_optimize;
36760 tree func_optimize;
36762 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36764 if (TARGET_DEBUG_TARGET)
36766 tree tname = DECL_NAME (fndecl);
36767 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36769 fprintf (stderr, "function: %.*s\n",
36770 (int) IDENTIFIER_LENGTH (tname),
36771 IDENTIFIER_POINTER (tname));
36773 fprintf (stderr, "function: unknown\n");
36775 fprintf (stderr, "args:");
36776 rs6000_debug_target_options (args, " ");
36777 fprintf (stderr, "\n");
36780 fprintf (stderr, "flags: 0x%x\n", flags);
36782 fprintf (stderr, "--------------------\n");
36785 /* attribute((target("default"))) does nothing, beyond
36786 affecting multi-versioning. */
36787 if (TREE_VALUE (args)
36788 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36789 && TREE_CHAIN (args) == NULL_TREE
36790 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36793 old_optimize = build_optimization_node (&global_options);
36794 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36796 /* If the function changed the optimization levels as well as setting target
36797 options, start with the optimizations specified. */
36798 if (func_optimize && func_optimize != old_optimize)
36799 cl_optimization_restore (&global_options,
36800 TREE_OPTIMIZATION (func_optimize));
36802 /* The target attributes may also change some optimization flags, so update
36803 the optimization options if necessary. */
36804 cl_target_option_save (&cur_target, &global_options);
36805 rs6000_cpu_index = rs6000_tune_index = -1;
36806 ret = rs6000_inner_target_options (args, true);
36808 /* Set up any additional state. */
36811 ret = rs6000_option_override_internal (false);
36812 new_target = build_target_option_node (&global_options);
36817 new_optimize = build_optimization_node (&global_options);
36824 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36826 if (old_optimize != new_optimize)
36827 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36830 cl_target_option_restore (&global_options, &cur_target);
36832 if (old_optimize != new_optimize)
36833 cl_optimization_restore (&global_options,
36834 TREE_OPTIMIZATION (old_optimize));
36840 /* Hook to validate the current #pragma GCC target and set the state, and
36841 update the macros based on what was changed. If ARGS is NULL, then
36842 POP_TARGET is used to reset the options. */
36845 rs6000_pragma_target_parse (tree args, tree pop_target)
36847 tree prev_tree = build_target_option_node (&global_options);
36849 struct cl_target_option *prev_opt, *cur_opt;
36850 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36851 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36853 if (TARGET_DEBUG_TARGET)
36855 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36856 fprintf (stderr, "args:");
36857 rs6000_debug_target_options (args, " ");
36858 fprintf (stderr, "\n");
36862 fprintf (stderr, "pop_target:\n");
36863 debug_tree (pop_target);
36866 fprintf (stderr, "pop_target: <NULL>\n");
36868 fprintf (stderr, "--------------------\n");
36873 cur_tree = ((pop_target)
36875 : target_option_default_node);
36876 cl_target_option_restore (&global_options,
36877 TREE_TARGET_OPTION (cur_tree));
36881 rs6000_cpu_index = rs6000_tune_index = -1;
36882 if (!rs6000_inner_target_options (args, false)
36883 || !rs6000_option_override_internal (false)
36884 || (cur_tree = build_target_option_node (&global_options))
36887 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36888 fprintf (stderr, "invalid pragma\n");
36894 target_option_current_node = cur_tree;
36895 rs6000_activate_target_options (target_option_current_node);
36897 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36898 change the macros that are defined. */
36899 if (rs6000_target_modify_macros_ptr)
36901 prev_opt = TREE_TARGET_OPTION (prev_tree);
36902 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36903 prev_flags = prev_opt->x_rs6000_isa_flags;
36905 cur_opt = TREE_TARGET_OPTION (cur_tree);
36906 cur_flags = cur_opt->x_rs6000_isa_flags;
36907 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36909 diff_bumask = (prev_bumask ^ cur_bumask);
36910 diff_flags = (prev_flags ^ cur_flags);
36912 if ((diff_flags != 0) || (diff_bumask != 0))
36914 /* Delete old macros. */
36915 rs6000_target_modify_macros_ptr (false,
36916 prev_flags & diff_flags,
36917 prev_bumask & diff_bumask);
36919 /* Define new macros. */
36920 rs6000_target_modify_macros_ptr (true,
36921 cur_flags & diff_flags,
36922 cur_bumask & diff_bumask);
36930 /* Remember the last target of rs6000_set_current_function. */
36931 static GTY(()) tree rs6000_previous_fndecl;
36933 /* Restore target's globals from NEW_TREE and invalidate the
36934 rs6000_previous_fndecl cache. */
36937 rs6000_activate_target_options (tree new_tree)
36939 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36940 if (TREE_TARGET_GLOBALS (new_tree))
36941 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36942 else if (new_tree == target_option_default_node)
36943 restore_target_globals (&default_target_globals);
36945 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36946 rs6000_previous_fndecl = NULL_TREE;
36949 /* Establish appropriate back-end context for processing the function
36950 FNDECL. The argument might be NULL to indicate processing at top
36951 level, outside of any function scope. */
36953 rs6000_set_current_function (tree fndecl)
36955 if (TARGET_DEBUG_TARGET)
36957 fprintf (stderr, "\n==================== rs6000_set_current_function");
36960 fprintf (stderr, ", fndecl %s (%p)",
36961 (DECL_NAME (fndecl)
36962 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36963 : "<unknown>"), (void *)fndecl);
36965 if (rs6000_previous_fndecl)
36966 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36968 fprintf (stderr, "\n");
36971 /* Only change the context if the function changes. This hook is called
36972 several times in the course of compiling a function, and we don't want to
36973 slow things down too much or call target_reinit when it isn't safe. */
36974 if (fndecl == rs6000_previous_fndecl)
36978 if (rs6000_previous_fndecl == NULL_TREE)
36979 old_tree = target_option_current_node;
36980 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36981 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36983 old_tree = target_option_default_node;
36986 if (fndecl == NULL_TREE)
36988 if (old_tree != target_option_current_node)
36989 new_tree = target_option_current_node;
36991 new_tree = NULL_TREE;
36995 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36996 if (new_tree == NULL_TREE)
36997 new_tree = target_option_default_node;
37000 if (TARGET_DEBUG_TARGET)
37004 fprintf (stderr, "\nnew fndecl target specific options:\n");
37005 debug_tree (new_tree);
37010 fprintf (stderr, "\nold fndecl target specific options:\n");
37011 debug_tree (old_tree);
37014 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37015 fprintf (stderr, "--------------------\n");
37018 if (new_tree && old_tree != new_tree)
37019 rs6000_activate_target_options (new_tree);
37022 rs6000_previous_fndecl = fndecl;
37026 /* Save the current options */
37029 rs6000_function_specific_save (struct cl_target_option *ptr,
37030 struct gcc_options *opts)
37032 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37033 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37036 /* Restore the current options */
37039 rs6000_function_specific_restore (struct gcc_options *opts,
37040 struct cl_target_option *ptr)
37043 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37044 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37045 (void) rs6000_option_override_internal (false);
37048 /* Print the current options */
37051 rs6000_function_specific_print (FILE *file, int indent,
37052 struct cl_target_option *ptr)
37054 rs6000_print_isa_options (file, indent, "Isa options set",
37055 ptr->x_rs6000_isa_flags);
37057 rs6000_print_isa_options (file, indent, "Isa options explicit",
37058 ptr->x_rs6000_isa_flags_explicit);
37061 /* Helper function to print the current isa or misc options on a line. */
37064 rs6000_print_options_internal (FILE *file,
37066 const char *string,
37067 HOST_WIDE_INT flags,
37068 const char *prefix,
37069 const struct rs6000_opt_mask *opts,
37070 size_t num_elements)
37073 size_t start_column = 0;
37075 size_t max_column = 120;
37076 size_t prefix_len = strlen (prefix);
37077 size_t comma_len = 0;
37078 const char *comma = "";
37081 start_column += fprintf (file, "%*s", indent, "");
37085 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37089 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37091 /* Print the various mask options. */
37092 cur_column = start_column;
37093 for (i = 0; i < num_elements; i++)
37095 bool invert = opts[i].invert;
37096 const char *name = opts[i].name;
37097 const char *no_str = "";
37098 HOST_WIDE_INT mask = opts[i].mask;
37099 size_t len = comma_len + prefix_len + strlen (name);
37103 if ((flags & mask) == 0)
37106 len += sizeof ("no-") - 1;
37114 if ((flags & mask) != 0)
37117 len += sizeof ("no-") - 1;
37124 if (cur_column > max_column)
37126 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37127 cur_column = start_column + len;
37131 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37133 comma_len = sizeof (", ") - 1;
37136 fputs ("\n", file);
37139 /* Helper function to print the current isa options on a line. */
37142 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37143 HOST_WIDE_INT flags)
37145 rs6000_print_options_internal (file, indent, string, flags, "-m",
37146 &rs6000_opt_masks[0],
37147 ARRAY_SIZE (rs6000_opt_masks));
37151 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37152 HOST_WIDE_INT flags)
37154 rs6000_print_options_internal (file, indent, string, flags, "",
37155 &rs6000_builtin_mask_names[0],
37156 ARRAY_SIZE (rs6000_builtin_mask_names));
37159 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37160 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37161 -mupper-regs-df, etc.).
37163 If the user used -mno-power8-vector, we need to turn off all of the implicit
37164 ISA 2.07 and 3.0 options that relate to the vector unit.
37166 If the user used -mno-power9-vector, we need to turn off all of the implicit
37167 ISA 3.0 options that relate to the vector unit.
37169 This function does not handle explicit options such as the user specifying
37170 -mdirect-move. These are handled in rs6000_option_override_internal, and
37171 the appropriate error is given if needed.
37173 We return a mask of all of the implicit options that should not be enabled
37176 static HOST_WIDE_INT
37177 rs6000_disable_incompatible_switches (void)
37179 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37182 static const struct {
37183 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37184 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37185 const char *const name; /* name of the switch. */
37187 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37188 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37189 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37192 for (i = 0; i < ARRAY_SIZE (flags); i++)
37194 HOST_WIDE_INT no_flag = flags[i].no_flag;
37196 if ((rs6000_isa_flags & no_flag) == 0
37197 && (rs6000_isa_flags_explicit & no_flag) != 0)
37199 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37200 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37206 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37207 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37209 set_flags &= ~rs6000_opt_masks[j].mask;
37210 error ("%<-mno-%s%> turns off %<-m%s%>",
37212 rs6000_opt_masks[j].name);
37215 gcc_assert (!set_flags);
37218 rs6000_isa_flags &= ~dep_flags;
37219 ignore_masks |= no_flag | dep_flags;
37223 return ignore_masks;
37227 /* Helper function for printing the function name when debugging. */
37229 static const char *
37230 get_decl_name (tree fn)
37237 name = DECL_NAME (fn);
37239 return "<no-name>";
37241 return IDENTIFIER_POINTER (name);
37244 /* Return the clone id of the target we are compiling code for in a target
37245 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37246 the priority list for the target clones (ordered from lowest to
37250 rs6000_clone_priority (tree fndecl)
37252 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37253 HOST_WIDE_INT isa_masks;
37254 int ret = CLONE_DEFAULT;
37255 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37256 const char *attrs_str = NULL;
37258 attrs = TREE_VALUE (TREE_VALUE (attrs));
37259 attrs_str = TREE_STRING_POINTER (attrs);
37261 /* Return priority zero for default function. Return the ISA needed for the
37262 function if it is not the default. */
37263 if (strcmp (attrs_str, "default") != 0)
37265 if (fn_opts == NULL_TREE)
37266 fn_opts = target_option_default_node;
37268 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37269 isa_masks = rs6000_isa_flags;
37271 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37273 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37274 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37278 if (TARGET_DEBUG_TARGET)
37279 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37280 get_decl_name (fndecl), ret);
37285 /* This compares the priority of target features in function DECL1 and DECL2.
37286 It returns positive value if DECL1 is higher priority, negative value if
37287 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37288 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37291 rs6000_compare_version_priority (tree decl1, tree decl2)
37293 int priority1 = rs6000_clone_priority (decl1);
37294 int priority2 = rs6000_clone_priority (decl2);
37295 int ret = priority1 - priority2;
37297 if (TARGET_DEBUG_TARGET)
37298 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37299 get_decl_name (decl1), get_decl_name (decl2), ret);
37304 /* Make a dispatcher declaration for the multi-versioned function DECL.
37305 Calls to DECL function will be replaced with calls to the dispatcher
37306 by the front-end. Returns the decl of the dispatcher function. */
37309 rs6000_get_function_versions_dispatcher (void *decl)
37311 tree fn = (tree) decl;
37312 struct cgraph_node *node = NULL;
37313 struct cgraph_node *default_node = NULL;
37314 struct cgraph_function_version_info *node_v = NULL;
37315 struct cgraph_function_version_info *first_v = NULL;
37317 tree dispatch_decl = NULL;
37319 struct cgraph_function_version_info *default_version_info = NULL;
37320 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37322 if (TARGET_DEBUG_TARGET)
37323 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37324 get_decl_name (fn));
37326 node = cgraph_node::get (fn);
37327 gcc_assert (node != NULL);
37329 node_v = node->function_version ();
37330 gcc_assert (node_v != NULL);
37332 if (node_v->dispatcher_resolver != NULL)
37333 return node_v->dispatcher_resolver;
37335 /* Find the default version and make it the first node. */
37337 /* Go to the beginning of the chain. */
37338 while (first_v->prev != NULL)
37339 first_v = first_v->prev;
37341 default_version_info = first_v;
37342 while (default_version_info != NULL)
37344 const tree decl2 = default_version_info->this_node->decl;
37345 if (is_function_default_version (decl2))
37347 default_version_info = default_version_info->next;
37350 /* If there is no default node, just return NULL. */
37351 if (default_version_info == NULL)
37354 /* Make default info the first node. */
37355 if (first_v != default_version_info)
37357 default_version_info->prev->next = default_version_info->next;
37358 if (default_version_info->next)
37359 default_version_info->next->prev = default_version_info->prev;
37360 first_v->prev = default_version_info;
37361 default_version_info->next = first_v;
37362 default_version_info->prev = NULL;
37365 default_node = default_version_info->this_node;
37367 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37368 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37369 "%<target_clones%> attribute needs GLIBC (2.23 and newer) that "
37370 "exports hardware capability bits");
37373 if (targetm.has_ifunc_p ())
37375 struct cgraph_function_version_info *it_v = NULL;
37376 struct cgraph_node *dispatcher_node = NULL;
37377 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37379 /* Right now, the dispatching is done via ifunc. */
37380 dispatch_decl = make_dispatcher_decl (default_node->decl);
37382 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37383 gcc_assert (dispatcher_node != NULL);
37384 dispatcher_node->dispatcher_function = 1;
37385 dispatcher_version_info
37386 = dispatcher_node->insert_new_function_version ();
37387 dispatcher_version_info->next = default_version_info;
37388 dispatcher_node->definition = 1;
37390 /* Set the dispatcher for all the versions. */
37391 it_v = default_version_info;
37392 while (it_v != NULL)
37394 it_v->dispatcher_resolver = dispatch_decl;
37400 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37401 "multiversioning needs ifunc which is not supported "
37406 return dispatch_decl;
37409 /* Make the resolver function decl to dispatch the versions of a multi-
37410 versioned function, DEFAULT_DECL. Create an empty basic block in the
37411 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37415 make_resolver_func (const tree default_decl,
37416 const tree dispatch_decl,
37417 basic_block *empty_bb)
37419 /* Make the resolver function static. The resolver function returns
37421 tree decl_name = clone_function_name (default_decl, "resolver");
37422 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37423 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37424 tree decl = build_fn_decl (resolver_name, type);
37425 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37427 DECL_NAME (decl) = decl_name;
37428 TREE_USED (decl) = 1;
37429 DECL_ARTIFICIAL (decl) = 1;
37430 DECL_IGNORED_P (decl) = 0;
37431 TREE_PUBLIC (decl) = 0;
37432 DECL_UNINLINABLE (decl) = 1;
37434 /* Resolver is not external, body is generated. */
37435 DECL_EXTERNAL (decl) = 0;
37436 DECL_EXTERNAL (dispatch_decl) = 0;
37438 DECL_CONTEXT (decl) = NULL_TREE;
37439 DECL_INITIAL (decl) = make_node (BLOCK);
37440 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37442 /* Build result decl and add to function_decl. */
37443 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37444 DECL_CONTEXT (t) = decl;
37445 DECL_ARTIFICIAL (t) = 1;
37446 DECL_IGNORED_P (t) = 1;
37447 DECL_RESULT (decl) = t;
37449 gimplify_function_tree (decl);
37450 push_cfun (DECL_STRUCT_FUNCTION (decl));
37451 *empty_bb = init_lowered_empty_function (decl, false,
37452 profile_count::uninitialized ());
37454 cgraph_node::add_new_function (decl, true);
37455 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37459 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37460 DECL_ATTRIBUTES (dispatch_decl)
37461 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37463 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37468 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37469 return a pointer to VERSION_DECL if we are running on a machine that
37470 supports the index CLONE_ISA hardware architecture bits. This function will
37471 be called during version dispatch to decide which function version to
37472 execute. It returns the basic block at the end, to which more conditions
37476 add_condition_to_bb (tree function_decl, tree version_decl,
37477 int clone_isa, basic_block new_bb)
37479 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37481 gcc_assert (new_bb != NULL);
37482 gimple_seq gseq = bb_seq (new_bb);
37485 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37486 build_fold_addr_expr (version_decl));
37487 tree result_var = create_tmp_var (ptr_type_node);
37488 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37489 gimple *return_stmt = gimple_build_return (result_var);
37491 if (clone_isa == CLONE_DEFAULT)
37493 gimple_seq_add_stmt (&gseq, convert_stmt);
37494 gimple_seq_add_stmt (&gseq, return_stmt);
37495 set_bb_seq (new_bb, gseq);
37496 gimple_set_bb (convert_stmt, new_bb);
37497 gimple_set_bb (return_stmt, new_bb);
37502 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37503 tree cond_var = create_tmp_var (bool_int_type_node);
37504 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37505 const char *arg_str = rs6000_clone_map[clone_isa].name;
37506 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37507 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37508 gimple_call_set_lhs (call_cond_stmt, cond_var);
37510 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37511 gimple_set_bb (call_cond_stmt, new_bb);
37512 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37514 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37515 NULL_TREE, NULL_TREE);
37516 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37517 gimple_set_bb (if_else_stmt, new_bb);
37518 gimple_seq_add_stmt (&gseq, if_else_stmt);
37520 gimple_seq_add_stmt (&gseq, convert_stmt);
37521 gimple_seq_add_stmt (&gseq, return_stmt);
37522 set_bb_seq (new_bb, gseq);
37524 basic_block bb1 = new_bb;
37525 edge e12 = split_block (bb1, if_else_stmt);
37526 basic_block bb2 = e12->dest;
37527 e12->flags &= ~EDGE_FALLTHRU;
37528 e12->flags |= EDGE_TRUE_VALUE;
37530 edge e23 = split_block (bb2, return_stmt);
37531 gimple_set_bb (convert_stmt, bb2);
37532 gimple_set_bb (return_stmt, bb2);
37534 basic_block bb3 = e23->dest;
37535 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37538 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37544 /* This function generates the dispatch function for multi-versioned functions.
37545 DISPATCH_DECL is the function which will contain the dispatch logic.
37546 FNDECLS are the function choices for dispatch, and is a tree chain.
37547 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37548 code is generated. */
37551 dispatch_function_versions (tree dispatch_decl,
37553 basic_block *empty_bb)
37557 vec<tree> *fndecls;
37558 tree clones[CLONE_MAX];
37560 if (TARGET_DEBUG_TARGET)
37561 fputs ("dispatch_function_versions, top\n", stderr);
37563 gcc_assert (dispatch_decl != NULL
37564 && fndecls_p != NULL
37565 && empty_bb != NULL);
37567 /* fndecls_p is actually a vector. */
37568 fndecls = static_cast<vec<tree> *> (fndecls_p);
37570 /* At least one more version other than the default. */
37571 gcc_assert (fndecls->length () >= 2);
37573 /* The first version in the vector is the default decl. */
37574 memset ((void *) clones, '\0', sizeof (clones));
37575 clones[CLONE_DEFAULT] = (*fndecls)[0];
37577 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37578 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37579 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37580 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37581 to insert the code here to do the call. */
37583 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37585 int priority = rs6000_clone_priority (ele);
37586 if (!clones[priority])
37587 clones[priority] = ele;
37590 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37593 if (TARGET_DEBUG_TARGET)
37594 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37595 ix, get_decl_name (clones[ix]));
37597 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37604 /* Generate the dispatching code body to dispatch multi-versioned function
37605 DECL. The target hook is called to process the "target" attributes and
37606 provide the code to dispatch the right function at run-time. NODE points
37607 to the dispatcher decl whose body will be created. */
37610 rs6000_generate_version_dispatcher_body (void *node_p)
37613 basic_block empty_bb;
37614 struct cgraph_node *node = (cgraph_node *) node_p;
37615 struct cgraph_function_version_info *ninfo = node->function_version ();
37617 if (ninfo->dispatcher_resolver)
37618 return ninfo->dispatcher_resolver;
37620 /* node is going to be an alias, so remove the finalized bit. */
37621 node->definition = false;
37623 /* The first version in the chain corresponds to the default version. */
37624 ninfo->dispatcher_resolver = resolver
37625 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37627 if (TARGET_DEBUG_TARGET)
37628 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37629 get_decl_name (resolver));
37631 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37632 auto_vec<tree, 2> fn_ver_vec;
37634 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37636 vinfo = vinfo->next)
37638 struct cgraph_node *version = vinfo->this_node;
37639 /* Check for virtual functions here again, as by this time it should
37640 have been determined if this function needs a vtable index or
37641 not. This happens for methods in derived classes that override
37642 virtual methods in base classes but are not explicitly marked as
37644 if (DECL_VINDEX (version->decl))
37645 sorry ("Virtual function multiversioning not supported");
37647 fn_ver_vec.safe_push (version->decl);
37650 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37651 cgraph_edge::rebuild_edges ();
37657 /* Hook to determine if one function can safely inline another. */
37660 rs6000_can_inline_p (tree caller, tree callee)
37663 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37664 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37666 /* If callee has no option attributes, then it is ok to inline. */
37670 /* If caller has no option attributes, but callee does then it is not ok to
37672 else if (!caller_tree)
37677 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37678 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37680 /* Callee's options should a subset of the caller's, i.e. a vsx function
37681 can inline an altivec function but a non-vsx function can't inline a
37683 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37684 == callee_opts->x_rs6000_isa_flags)
37688 if (TARGET_DEBUG_TARGET)
37689 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37690 get_decl_name (caller), get_decl_name (callee),
37691 (ret ? "can" : "cannot"));
37696 /* Allocate a stack temp and fixup the address so it meets the particular
37697 memory requirements (either offetable or REG+REG addressing). */
37700 rs6000_allocate_stack_temp (machine_mode mode,
37701 bool offsettable_p,
37704 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37705 rtx addr = XEXP (stack, 0);
37706 int strict_p = reload_completed;
37708 if (!legitimate_indirect_address_p (addr, strict_p))
37711 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37712 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37714 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37715 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37721 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37722 convert to such a form to deal with memory reference instructions
37723 like STFIWX and LDBRX that only take reg+reg addressing. */
37726 rs6000_force_indexed_or_indirect_mem (rtx x)
37728 machine_mode mode = GET_MODE (x);
37730 gcc_assert (MEM_P (x));
37731 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37733 rtx addr = XEXP (x, 0);
37734 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37736 rtx reg = XEXP (addr, 0);
37737 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37738 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37739 gcc_assert (REG_P (reg));
37740 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37743 else if (GET_CODE (addr) == PRE_MODIFY)
37745 rtx reg = XEXP (addr, 0);
37746 rtx expr = XEXP (addr, 1);
37747 gcc_assert (REG_P (reg));
37748 gcc_assert (GET_CODE (expr) == PLUS);
37749 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37753 x = replace_equiv_address (x, force_reg (Pmode, addr));
37759 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37761 On the RS/6000, all integer constants are acceptable, most won't be valid
37762 for particular insns, though. Only easy FP constants are acceptable. */
37765 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37767 if (TARGET_ELF && tls_referenced_p (x))
37770 if (CONST_DOUBLE_P (x))
37771 return easy_fp_constant (x, mode);
37773 if (GET_CODE (x) == CONST_VECTOR)
37774 return easy_vector_constant (x, mode);
37780 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37783 chain_already_loaded (rtx_insn *last)
37785 for (; last != NULL; last = PREV_INSN (last))
37787 if (NONJUMP_INSN_P (last))
37789 rtx patt = PATTERN (last);
37791 if (GET_CODE (patt) == SET)
37793 rtx lhs = XEXP (patt, 0);
37795 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37803 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37806 rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37808 rtx func = func_desc;
37809 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37810 rtx toc_load = NULL_RTX;
37811 rtx toc_restore = NULL_RTX;
37813 rtx abi_reg = NULL_RTX;
37817 bool is_pltseq_longcall;
37820 tlsarg = global_tlsarg;
37822 /* Handle longcall attributes. */
37823 is_pltseq_longcall = false;
37824 if ((INTVAL (cookie) & CALL_LONG) != 0
37825 && GET_CODE (func_desc) == SYMBOL_REF)
37827 func = rs6000_longcall_ref (func_desc, tlsarg);
37829 is_pltseq_longcall = true;
37832 /* Handle indirect calls. */
37833 if (!SYMBOL_REF_P (func)
37834 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func)))
37836 if (!rs6000_pcrel_p (cfun))
37838 /* Save the TOC into its reserved slot before the call,
37839 and prepare to restore it after the call. */
37840 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37841 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37842 gen_rtvec (1, stack_toc_offset),
37844 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37846 /* Can we optimize saving the TOC in the prologue or
37847 do we need to do it at every call? */
37848 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37849 cfun->machine->save_toc_in_prologue = true;
37852 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37853 rtx stack_toc_mem = gen_frame_mem (Pmode,
37854 gen_rtx_PLUS (Pmode, stack_ptr,
37855 stack_toc_offset));
37856 MEM_VOLATILE_P (stack_toc_mem) = 1;
37857 if (is_pltseq_longcall)
37859 rtvec v = gen_rtvec (3, toc_reg, func_desc, tlsarg);
37860 rtx mark_toc_reg = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37861 emit_insn (gen_rtx_SET (stack_toc_mem, mark_toc_reg));
37864 emit_move_insn (stack_toc_mem, toc_reg);
37868 if (DEFAULT_ABI == ABI_ELFv2)
37870 /* A function pointer in the ELFv2 ABI is just a plain address, but
37871 the ABI requires it to be loaded into r12 before the call. */
37872 func_addr = gen_rtx_REG (Pmode, 12);
37873 if (!rtx_equal_p (func_addr, func))
37874 emit_move_insn (func_addr, func);
37875 abi_reg = func_addr;
37876 /* Indirect calls via CTR are strongly preferred over indirect
37877 calls via LR, so move the address there. Needed to mark
37878 this insn for linker plt sequence editing too. */
37879 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37880 if (is_pltseq_longcall)
37882 rtvec v = gen_rtvec (3, abi_reg, func_desc, tlsarg);
37883 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37884 emit_insn (gen_rtx_SET (func_addr, mark_func));
37885 v = gen_rtvec (2, func_addr, func_desc);
37886 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37889 emit_move_insn (func_addr, abi_reg);
37893 /* A function pointer under AIX is a pointer to a data area whose
37894 first word contains the actual address of the function, whose
37895 second word contains a pointer to its TOC, and whose third word
37896 contains a value to place in the static chain register (r11).
37897 Note that if we load the static chain, our "trampoline" need
37898 not have any executable code. */
37900 /* Load up address of the actual function. */
37901 func = force_reg (Pmode, func);
37902 func_addr = gen_reg_rtx (Pmode);
37903 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func));
37905 /* Indirect calls via CTR are strongly preferred over indirect
37906 calls via LR, so move the address there. */
37907 rtx ctr_reg = gen_rtx_REG (Pmode, CTR_REGNO);
37908 emit_move_insn (ctr_reg, func_addr);
37909 func_addr = ctr_reg;
37911 /* Prepare to load the TOC of the called function. Note that the
37912 TOC load must happen immediately before the actual call so
37913 that unwinding the TOC registers works correctly. See the
37914 comment in frob_update_context. */
37915 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37916 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37917 gen_rtx_PLUS (Pmode, func,
37919 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37921 /* If we have a static chain, load it up. But, if the call was
37922 originally direct, the 3rd word has not been written since no
37923 trampoline has been built, so we ought not to load it, lest we
37924 override a static chain value. */
37925 if (!(GET_CODE (func_desc) == SYMBOL_REF
37926 && SYMBOL_REF_FUNCTION_P (func_desc))
37927 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37928 && !chain_already_loaded (get_current_sequence ()->next->last))
37930 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37931 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37932 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37933 gen_rtx_PLUS (Pmode, func,
37935 emit_move_insn (sc_reg, func_sc_mem);
37942 /* No TOC register needed for calls from PC-relative callers. */
37943 if (!rs6000_pcrel_p (cfun))
37944 /* Direct calls use the TOC: for local calls, the callee will
37945 assume the TOC register is set; for non-local calls, the
37946 PLT stub needs the TOC register. */
37951 /* Create the call. */
37952 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37953 if (value != NULL_RTX)
37954 call[0] = gen_rtx_SET (value, call[0]);
37958 call[n_call++] = toc_load;
37960 call[n_call++] = toc_restore;
37962 call[n_call++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37964 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37965 insn = emit_call_insn (insn);
37967 /* Mention all registers defined by the ABI to hold information
37968 as uses in CALL_INSN_FUNCTION_USAGE. */
37970 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37973 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37976 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37981 gcc_assert (INTVAL (cookie) == 0);
37984 tlsarg = global_tlsarg;
37986 /* Create the call. */
37987 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), tlsarg);
37988 if (value != NULL_RTX)
37989 call[0] = gen_rtx_SET (value, call[0]);
37991 call[1] = simple_return_rtx;
37993 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37994 insn = emit_call_insn (insn);
37996 /* Note use of the TOC register. */
37997 if (!rs6000_pcrel_p (cfun))
37998 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
37999 gen_rtx_REG (Pmode, TOC_REGNUM));
38002 /* Expand code to perform a call under the SYSV4 ABI. */
38005 rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
38007 rtx func = func_desc;
38011 rtx abi_reg = NULL_RTX;
38015 tlsarg = global_tlsarg;
38017 /* Handle longcall attributes. */
38018 if ((INTVAL (cookie) & CALL_LONG) != 0
38019 && GET_CODE (func_desc) == SYMBOL_REF)
38021 func = rs6000_longcall_ref (func_desc, tlsarg);
38022 /* If the longcall was implemented as an inline PLT call using
38023 PLT unspecs then func will be REG:r11. If not, func will be
38024 a pseudo reg. The inline PLT call sequence supports lazy
38025 linking (and longcalls to functions in dlopen'd libraries).
38026 The other style of longcalls don't. The lazy linking entry
38027 to the dynamic symbol resolver requires r11 be the function
38028 address (as it is for linker generated PLT stubs). Ensure
38029 r11 stays valid to the bctrl by marking r11 used by the call. */
38034 /* Handle indirect calls. */
38035 if (GET_CODE (func) != SYMBOL_REF)
38037 func = force_reg (Pmode, func);
38039 /* Indirect calls via CTR are strongly preferred over indirect
38040 calls via LR, so move the address there. That can't be left
38041 to reload because we want to mark every instruction in an
38042 inline PLT call sequence with a reloc, enabling the linker to
38043 edit the sequence back to a direct call when that makes sense. */
38044 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38047 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
38048 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
38049 emit_insn (gen_rtx_SET (func_addr, mark_func));
38050 v = gen_rtvec (2, func_addr, func_desc);
38051 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
38054 emit_move_insn (func_addr, func);
38059 /* Create the call. */
38060 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38061 if (value != NULL_RTX)
38062 call[0] = gen_rtx_SET (value, call[0]);
38064 call[1] = gen_rtx_USE (VOIDmode, cookie);
38066 if (TARGET_SECURE_PLT
38068 && GET_CODE (func_addr) == SYMBOL_REF
38069 && !SYMBOL_REF_LOCAL_P (func_addr))
38070 call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
38072 call[n++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38074 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n, call));
38075 insn = emit_call_insn (insn);
38077 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38080 /* Expand code to perform a sibling call under the SysV4 ABI. */
38083 rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
38085 rtx func = func_desc;
38089 rtx abi_reg = NULL_RTX;
38092 tlsarg = global_tlsarg;
38094 /* Handle longcall attributes. */
38095 if ((INTVAL (cookie) & CALL_LONG) != 0
38096 && GET_CODE (func_desc) == SYMBOL_REF)
38098 func = rs6000_longcall_ref (func_desc, tlsarg);
38099 /* If the longcall was implemented as an inline PLT call using
38100 PLT unspecs then func will be REG:r11. If not, func will be
38101 a pseudo reg. The inline PLT call sequence supports lazy
38102 linking (and longcalls to functions in dlopen'd libraries).
38103 The other style of longcalls don't. The lazy linking entry
38104 to the dynamic symbol resolver requires r11 be the function
38105 address (as it is for linker generated PLT stubs). Ensure
38106 r11 stays valid to the bctr by marking r11 used by the call. */
38111 /* Handle indirect calls. */
38112 if (GET_CODE (func) != SYMBOL_REF)
38114 func = force_reg (Pmode, func);
38116 /* Indirect sibcalls must go via CTR. That can't be left to
38117 reload because we want to mark every instruction in an inline
38118 PLT call sequence with a reloc, enabling the linker to edit
38119 the sequence back to a direct call when that makes sense. */
38120 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38123 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
38124 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
38125 emit_insn (gen_rtx_SET (func_addr, mark_func));
38126 v = gen_rtvec (2, func_addr, func_desc);
38127 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
38130 emit_move_insn (func_addr, func);
38135 /* Create the call. */
38136 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38137 if (value != NULL_RTX)
38138 call[0] = gen_rtx_SET (value, call[0]);
38140 call[1] = gen_rtx_USE (VOIDmode, cookie);
38141 call[2] = simple_return_rtx;
38143 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38144 insn = emit_call_insn (insn);
38146 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38151 /* Expand code to perform a call under the Darwin ABI.
38152 Modulo handling of mlongcall, this is much the same as sysv.
38153 if/when the longcall optimisation is removed, we could drop this
38154 code and use the sysv case (taking care to avoid the tls stuff).
38156 We can use this for sibcalls too, if needed. */
38159 rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
38160 rtx cookie, bool sibcall)
38162 rtx func = func_desc;
38166 int cookie_val = INTVAL (cookie);
38167 bool make_island = false;
38169 /* Handle longcall attributes, there are two cases for Darwin:
38170 1) Newer linkers are capable of synthesising any branch islands needed.
38171 2) We need a helper branch island synthesised by the compiler.
38172 The second case has mostly been retired and we don't use it for m64.
38173 In fact, it's is an optimisation, we could just indirect as sysv does..
38174 ... however, backwards compatibility for now.
38175 If we're going to use this, then we need to keep the CALL_LONG bit set,
38176 so that we can pick up the special insn form later. */
38177 if ((cookie_val & CALL_LONG) != 0
38178 && GET_CODE (func_desc) == SYMBOL_REF)
38180 if (darwin_emit_branch_islands && TARGET_32BIT)
38181 make_island = true; /* Do nothing yet, retain the CALL_LONG flag. */
38184 /* The linker is capable of doing this, but the user explicitly
38185 asked for -mlongcall, so we'll do the 'normal' version. */
38186 func = rs6000_longcall_ref (func_desc, NULL_RTX);
38187 cookie_val &= ~CALL_LONG; /* Handled, zap it. */
38191 /* Handle indirect calls. */
38192 if (GET_CODE (func) != SYMBOL_REF)
38194 func = force_reg (Pmode, func);
38196 /* Indirect calls via CTR are strongly preferred over indirect
38197 calls via LR, and are required for indirect sibcalls, so move
38198 the address there. */
38199 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38200 emit_move_insn (func_addr, func);
38205 /* Create the call. */
38206 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38207 if (value != NULL_RTX)
38208 call[0] = gen_rtx_SET (value, call[0]);
38210 call[1] = gen_rtx_USE (VOIDmode, GEN_INT (cookie_val));
38213 call[2] = simple_return_rtx;
38215 call[2] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38217 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38218 insn = emit_call_insn (insn);
38219 /* Now we have the debug info in the insn, we can set up the branch island
38220 if we're using one. */
38223 tree funname = get_identifier (XSTR (func_desc, 0));
38225 if (no_previous_def (funname))
38227 rtx label_rtx = gen_label_rtx ();
38228 char *label_buf, temp_buf[256];
38229 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
38230 CODE_LABEL_NUMBER (label_rtx));
38231 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
38232 tree labelname = get_identifier (label_buf);
38233 add_compiler_branch_island (labelname, funname,
38234 insn_line ((const rtx_insn*)insn));
38241 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38242 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38245 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, false);
38253 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38254 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38257 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, true);
38264 /* Return whether we need to always update the saved TOC pointer when we update
38265 the stack pointer. */
38268 rs6000_save_toc_in_prologue_p (void)
38270 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38273 /* Return whether we should generate PC-relative code for FNDECL. */
38275 rs6000_fndecl_pcrel_p (const_tree fndecl)
38277 if (DEFAULT_ABI != ABI_ELFv2)
38280 struct cl_target_option *opts = target_opts_for_fn (fndecl);
38282 return ((opts->x_rs6000_isa_flags & OPTION_MASK_PCREL) != 0
38283 && TARGET_CMODEL == CMODEL_MEDIUM);
38286 /* Return whether we should generate PC-relative code for *FN. */
38288 rs6000_pcrel_p (struct function *fn)
38290 if (DEFAULT_ABI != ABI_ELFv2)
38293 /* Optimize usual case. */
38295 return ((rs6000_isa_flags & OPTION_MASK_PCREL) != 0
38296 && TARGET_CMODEL == CMODEL_MEDIUM);
38298 return rs6000_fndecl_pcrel_p (fn->decl);
38301 #ifdef HAVE_GAS_HIDDEN
38302 # define USE_HIDDEN_LINKONCE 1
38304 # define USE_HIDDEN_LINKONCE 0
38307 /* Fills in the label name that should be used for a 476 link stack thunk. */
38310 get_ppc476_thunk_name (char name[32])
38312 gcc_assert (TARGET_LINK_STACK);
38314 if (USE_HIDDEN_LINKONCE)
38315 sprintf (name, "__ppc476.get_thunk");
38317 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38320 /* This function emits the simple thunk routine that is used to preserve
38321 the link stack on the 476 cpu. */
38323 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38325 rs6000_code_end (void)
38330 if (!TARGET_LINK_STACK)
38333 get_ppc476_thunk_name (name);
38335 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38336 build_function_type_list (void_type_node, NULL_TREE));
38337 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38338 NULL_TREE, void_type_node);
38339 TREE_PUBLIC (decl) = 1;
38340 TREE_STATIC (decl) = 1;
38343 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38345 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38346 targetm.asm_out.unique_section (decl, 0);
38347 switch_to_section (get_named_section (decl, NULL, 0));
38348 DECL_WEAK (decl) = 1;
38349 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38350 targetm.asm_out.globalize_label (asm_out_file, name);
38351 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38352 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38357 switch_to_section (text_section);
38358 ASM_OUTPUT_LABEL (asm_out_file, name);
38361 DECL_INITIAL (decl) = make_node (BLOCK);
38362 current_function_decl = decl;
38363 allocate_struct_function (decl, false);
38364 init_function_start (decl);
38365 first_function_block_is_cold = false;
38366 /* Make sure unwind info is emitted for the thunk if needed. */
38367 final_start_function (emit_barrier (), asm_out_file, 1);
38369 fputs ("\tblr\n", asm_out_file);
38371 final_end_function ();
38372 init_insn_lengths ();
38373 free_after_compilation (cfun);
38375 current_function_decl = NULL;
38378 /* Add r30 to hard reg set if the prologue sets it up and it is not
38379 pic_offset_table_rtx. */
38382 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38384 if (!TARGET_SINGLE_PIC_BASE
38386 && TARGET_MINIMAL_TOC
38387 && !constant_pool_empty_p ())
38388 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38389 if (cfun->machine->split_stack_argp_used)
38390 add_to_hard_reg_set (&set->set, Pmode, 12);
38392 /* Make sure the hard reg set doesn't include r2, which was possibly added
38393 via PIC_OFFSET_TABLE_REGNUM. */
38395 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38399 /* Helper function for rs6000_split_logical to emit a logical instruction after
38400 spliting the operation to single GPR registers.
38402 DEST is the destination register.
38403 OP1 and OP2 are the input source registers.
38404 CODE is the base operation (AND, IOR, XOR, NOT).
38405 MODE is the machine mode.
38406 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38407 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38408 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38411 rs6000_split_logical_inner (rtx dest,
38414 enum rtx_code code,
38416 bool complement_final_p,
38417 bool complement_op1_p,
38418 bool complement_op2_p)
38422 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38423 if (op2 && CONST_INT_P (op2)
38424 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38425 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38427 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38428 HOST_WIDE_INT value = INTVAL (op2) & mask;
38430 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38435 emit_insn (gen_rtx_SET (dest, const0_rtx));
38439 else if (value == mask)
38441 if (!rtx_equal_p (dest, op1))
38442 emit_insn (gen_rtx_SET (dest, op1));
38447 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38448 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38449 else if (code == IOR || code == XOR)
38453 if (!rtx_equal_p (dest, op1))
38454 emit_insn (gen_rtx_SET (dest, op1));
38460 if (code == AND && mode == SImode
38461 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38463 emit_insn (gen_andsi3 (dest, op1, op2));
38467 if (complement_op1_p)
38468 op1 = gen_rtx_NOT (mode, op1);
38470 if (complement_op2_p)
38471 op2 = gen_rtx_NOT (mode, op2);
38473 /* For canonical RTL, if only one arm is inverted it is the first. */
38474 if (!complement_op1_p && complement_op2_p)
38475 std::swap (op1, op2);
38477 bool_rtx = ((code == NOT)
38478 ? gen_rtx_NOT (mode, op1)
38479 : gen_rtx_fmt_ee (code, mode, op1, op2));
38481 if (complement_final_p)
38482 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38484 emit_insn (gen_rtx_SET (dest, bool_rtx));
38487 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38488 operations are split immediately during RTL generation to allow for more
38489 optimizations of the AND/IOR/XOR.
38491 OPERANDS is an array containing the destination and two input operands.
38492 CODE is the base operation (AND, IOR, XOR, NOT).
38493 MODE is the machine mode.
38494 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38495 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38496 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38497 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38498 formation of the AND instructions. */
38501 rs6000_split_logical_di (rtx operands[3],
38502 enum rtx_code code,
38503 bool complement_final_p,
38504 bool complement_op1_p,
38505 bool complement_op2_p)
38507 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38508 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38509 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38510 enum hi_lo { hi = 0, lo = 1 };
38511 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38514 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38515 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38516 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38517 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38520 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38523 if (!CONST_INT_P (operands[2]))
38525 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38526 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38530 HOST_WIDE_INT value = INTVAL (operands[2]);
38531 HOST_WIDE_INT value_hi_lo[2];
38533 gcc_assert (!complement_final_p);
38534 gcc_assert (!complement_op1_p);
38535 gcc_assert (!complement_op2_p);
38537 value_hi_lo[hi] = value >> 32;
38538 value_hi_lo[lo] = value & lower_32bits;
38540 for (i = 0; i < 2; i++)
38542 HOST_WIDE_INT sub_value = value_hi_lo[i];
38544 if (sub_value & sign_bit)
38545 sub_value |= upper_32bits;
38547 op2_hi_lo[i] = GEN_INT (sub_value);
38549 /* If this is an AND instruction, check to see if we need to load
38550 the value in a register. */
38551 if (code == AND && sub_value != -1 && sub_value != 0
38552 && !and_operand (op2_hi_lo[i], SImode))
38553 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38558 for (i = 0; i < 2; i++)
38560 /* Split large IOR/XOR operations. */
38561 if ((code == IOR || code == XOR)
38562 && CONST_INT_P (op2_hi_lo[i])
38563 && !complement_final_p
38564 && !complement_op1_p
38565 && !complement_op2_p
38566 && !logical_const_operand (op2_hi_lo[i], SImode))
38568 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38569 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38570 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38571 rtx tmp = gen_reg_rtx (SImode);
38573 /* Make sure the constant is sign extended. */
38574 if ((hi_16bits & sign_bit) != 0)
38575 hi_16bits |= upper_32bits;
38577 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38578 code, SImode, false, false, false);
38580 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38581 code, SImode, false, false, false);
38584 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38585 code, SImode, complement_final_p,
38586 complement_op1_p, complement_op2_p);
38592 /* Split the insns that make up boolean operations operating on multiple GPR
38593 registers. The boolean MD patterns ensure that the inputs either are
38594 exactly the same as the output registers, or there is no overlap.
38596 OPERANDS is an array containing the destination and two input operands.
38597 CODE is the base operation (AND, IOR, XOR, NOT).
38598 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38599 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38600 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38603 rs6000_split_logical (rtx operands[3],
38604 enum rtx_code code,
38605 bool complement_final_p,
38606 bool complement_op1_p,
38607 bool complement_op2_p)
38609 machine_mode mode = GET_MODE (operands[0]);
38610 machine_mode sub_mode;
38612 int sub_size, regno0, regno1, nregs, i;
38614 /* If this is DImode, use the specialized version that can run before
38615 register allocation. */
38616 if (mode == DImode && !TARGET_POWERPC64)
38618 rs6000_split_logical_di (operands, code, complement_final_p,
38619 complement_op1_p, complement_op2_p);
38625 op2 = (code == NOT) ? NULL_RTX : operands[2];
38626 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38627 sub_size = GET_MODE_SIZE (sub_mode);
38628 regno0 = REGNO (op0);
38629 regno1 = REGNO (op1);
38631 gcc_assert (reload_completed);
38632 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38633 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38635 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38636 gcc_assert (nregs > 1);
38638 if (op2 && REG_P (op2))
38639 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38641 for (i = 0; i < nregs; i++)
38643 int offset = i * sub_size;
38644 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38645 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38646 rtx sub_op2 = ((code == NOT)
38648 : simplify_subreg (sub_mode, op2, mode, offset));
38650 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38651 complement_final_p, complement_op1_p,
38659 /* Return true if the peephole2 can combine a load involving a combination of
38660 an addis instruction and a load with an offset that can be fused together on
38664 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38665 rtx addis_value, /* addis value. */
38666 rtx target, /* target register that is loaded. */
38667 rtx mem) /* bottom part of the memory addr. */
38672 /* Validate arguments. */
38673 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38676 if (!base_reg_operand (target, GET_MODE (target)))
38679 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38682 /* Allow sign/zero extension. */
38683 if (GET_CODE (mem) == ZERO_EXTEND
38684 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38685 mem = XEXP (mem, 0);
38690 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38693 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38694 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38697 /* Validate that the register used to load the high value is either the
38698 register being loaded, or we can safely replace its use.
38700 This function is only called from the peephole2 pass and we assume that
38701 there are 2 instructions in the peephole (addis and load), so we want to
38702 check if the target register was not used in the memory address and the
38703 register to hold the addis result is dead after the peephole. */
38704 if (REGNO (addis_reg) != REGNO (target))
38706 if (reg_mentioned_p (target, mem))
38709 if (!peep2_reg_dead_p (2, addis_reg))
38712 /* If the target register being loaded is the stack pointer, we must
38713 avoid loading any other value into it, even temporarily. */
38714 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38718 base_reg = XEXP (addr, 0);
38719 return REGNO (addis_reg) == REGNO (base_reg);
38722 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38723 sequence. We adjust the addis register to use the target register. If the
38724 load sign extends, we adjust the code to do the zero extending load, and an
38725 explicit sign extension later since the fusion only covers zero extending
38729 operands[0] register set with addis (to be replaced with target)
38730 operands[1] value set via addis
38731 operands[2] target register being loaded
38732 operands[3] D-form memory reference using operands[0]. */
38735 expand_fusion_gpr_load (rtx *operands)
38737 rtx addis_value = operands[1];
38738 rtx target = operands[2];
38739 rtx orig_mem = operands[3];
38740 rtx new_addr, new_mem, orig_addr, offset;
38741 enum rtx_code plus_or_lo_sum;
38742 machine_mode target_mode = GET_MODE (target);
38743 machine_mode extend_mode = target_mode;
38744 machine_mode ptr_mode = Pmode;
38745 enum rtx_code extend = UNKNOWN;
38747 if (GET_CODE (orig_mem) == ZERO_EXTEND
38748 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38750 extend = GET_CODE (orig_mem);
38751 orig_mem = XEXP (orig_mem, 0);
38752 target_mode = GET_MODE (orig_mem);
38755 gcc_assert (MEM_P (orig_mem));
38757 orig_addr = XEXP (orig_mem, 0);
38758 plus_or_lo_sum = GET_CODE (orig_addr);
38759 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38761 offset = XEXP (orig_addr, 1);
38762 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38763 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38765 if (extend != UNKNOWN)
38766 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38768 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38769 UNSPEC_FUSION_GPR);
38770 emit_insn (gen_rtx_SET (target, new_mem));
38772 if (extend == SIGN_EXTEND)
38774 int sub_off = ((BYTES_BIG_ENDIAN)
38775 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38778 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38780 emit_insn (gen_rtx_SET (target,
38781 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38787 /* Emit the addis instruction that will be part of a fused instruction
38791 emit_fusion_addis (rtx target, rtx addis_value)
38794 const char *addis_str = NULL;
38796 /* Emit the addis instruction. */
38797 fuse_ops[0] = target;
38798 if (satisfies_constraint_L (addis_value))
38800 fuse_ops[1] = addis_value;
38801 addis_str = "lis %0,%v1";
38804 else if (GET_CODE (addis_value) == PLUS)
38806 rtx op0 = XEXP (addis_value, 0);
38807 rtx op1 = XEXP (addis_value, 1);
38809 if (REG_P (op0) && CONST_INT_P (op1)
38810 && satisfies_constraint_L (op1))
38814 addis_str = "addis %0,%1,%v2";
38818 else if (GET_CODE (addis_value) == HIGH)
38820 rtx value = XEXP (addis_value, 0);
38821 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38823 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38824 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38826 addis_str = "addis %0,%2,%1@toc@ha";
38828 else if (TARGET_XCOFF)
38829 addis_str = "addis %0,%1@u(%2)";
38832 gcc_unreachable ();
38835 else if (GET_CODE (value) == PLUS)
38837 rtx op0 = XEXP (value, 0);
38838 rtx op1 = XEXP (value, 1);
38840 if (GET_CODE (op0) == UNSPEC
38841 && XINT (op0, 1) == UNSPEC_TOCREL
38842 && CONST_INT_P (op1))
38844 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38845 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38848 addis_str = "addis %0,%2,%1+%3@toc@ha";
38850 else if (TARGET_XCOFF)
38851 addis_str = "addis %0,%1+%3@u(%2)";
38854 gcc_unreachable ();
38858 else if (satisfies_constraint_L (value))
38860 fuse_ops[1] = value;
38861 addis_str = "lis %0,%v1";
38864 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38866 fuse_ops[1] = value;
38867 addis_str = "lis %0,%1@ha";
38872 fatal_insn ("Could not generate addis value for fusion", addis_value);
38874 output_asm_insn (addis_str, fuse_ops);
38877 /* Emit a D-form load or store instruction that is the second instruction
38878 of a fusion sequence. */
38881 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38884 char insn_template[80];
38886 fuse_ops[0] = load_reg;
38887 fuse_ops[1] = addis_reg;
38889 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38891 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38892 fuse_ops[2] = offset;
38893 output_asm_insn (insn_template, fuse_ops);
38896 else if (GET_CODE (offset) == UNSPEC
38897 && XINT (offset, 1) == UNSPEC_TOCREL)
38900 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38902 else if (TARGET_XCOFF)
38903 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38906 gcc_unreachable ();
38908 fuse_ops[2] = XVECEXP (offset, 0, 0);
38909 output_asm_insn (insn_template, fuse_ops);
38912 else if (GET_CODE (offset) == PLUS
38913 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38914 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38915 && CONST_INT_P (XEXP (offset, 1)))
38917 rtx tocrel_unspec = XEXP (offset, 0);
38919 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38921 else if (TARGET_XCOFF)
38922 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38925 gcc_unreachable ();
38927 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38928 fuse_ops[3] = XEXP (offset, 1);
38929 output_asm_insn (insn_template, fuse_ops);
38932 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38934 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38936 fuse_ops[2] = offset;
38937 output_asm_insn (insn_template, fuse_ops);
38941 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38946 /* Given an address, convert it into the addis and load offset parts. Addresses
38947 created during the peephole2 process look like:
38948 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38949 (unspec [(...)] UNSPEC_TOCREL)) */
38952 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38956 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38958 hi = XEXP (addr, 0);
38959 lo = XEXP (addr, 1);
38962 gcc_unreachable ();
38968 /* Return a string to fuse an addis instruction with a gpr load to the same
38969 register that we loaded up the addis instruction. The address that is used
38970 is the logical address that was formed during peephole2:
38971 (lo_sum (high) (low-part))
38973 The code is complicated, so we call output_asm_insn directly, and just
38977 emit_fusion_gpr_load (rtx target, rtx mem)
38982 const char *load_str = NULL;
38985 if (GET_CODE (mem) == ZERO_EXTEND)
38986 mem = XEXP (mem, 0);
38988 gcc_assert (REG_P (target) && MEM_P (mem));
38990 addr = XEXP (mem, 0);
38991 fusion_split_address (addr, &addis_value, &load_offset);
38993 /* Now emit the load instruction to the same register. */
38994 mode = GET_MODE (mem);
39012 gcc_assert (TARGET_POWERPC64);
39017 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
39020 /* Emit the addis instruction. */
39021 emit_fusion_addis (target, addis_value);
39023 /* Emit the D-form load instruction. */
39024 emit_fusion_load (target, target, load_offset, load_str);
39030 #ifdef RS6000_GLIBC_ATOMIC_FENV
39031 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39032 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39035 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39038 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39040 if (!TARGET_HARD_FLOAT)
39042 #ifdef RS6000_GLIBC_ATOMIC_FENV
39043 if (atomic_hold_decl == NULL_TREE)
39046 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39047 get_identifier ("__atomic_feholdexcept"),
39048 build_function_type_list (void_type_node,
39049 double_ptr_type_node,
39051 TREE_PUBLIC (atomic_hold_decl) = 1;
39052 DECL_EXTERNAL (atomic_hold_decl) = 1;
39055 if (atomic_clear_decl == NULL_TREE)
39058 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39059 get_identifier ("__atomic_feclearexcept"),
39060 build_function_type_list (void_type_node,
39062 TREE_PUBLIC (atomic_clear_decl) = 1;
39063 DECL_EXTERNAL (atomic_clear_decl) = 1;
39066 tree const_double = build_qualified_type (double_type_node,
39068 tree const_double_ptr = build_pointer_type (const_double);
39069 if (atomic_update_decl == NULL_TREE)
39072 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39073 get_identifier ("__atomic_feupdateenv"),
39074 build_function_type_list (void_type_node,
39077 TREE_PUBLIC (atomic_update_decl) = 1;
39078 DECL_EXTERNAL (atomic_update_decl) = 1;
39081 tree fenv_var = create_tmp_var_raw (double_type_node);
39082 TREE_ADDRESSABLE (fenv_var) = 1;
39083 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39085 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39086 *clear = build_call_expr (atomic_clear_decl, 0);
39087 *update = build_call_expr (atomic_update_decl, 1,
39088 fold_convert (const_double_ptr, fenv_addr));
39093 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39094 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39095 tree call_mffs = build_call_expr (mffs, 0);
39097 /* Generates the equivalent of feholdexcept (&fenv_var)
39099 *fenv_var = __builtin_mffs ();
39101 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39102 __builtin_mtfsf (0xff, fenv_hold); */
39104 /* Mask to clear everything except for the rounding modes and non-IEEE
39105 arithmetic flag. */
39106 const unsigned HOST_WIDE_INT hold_exception_mask =
39107 HOST_WIDE_INT_C (0xffffffff00000007);
39109 tree fenv_var = create_tmp_var_raw (double_type_node);
39111 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39113 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39114 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39115 build_int_cst (uint64_type_node,
39116 hold_exception_mask));
39118 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39121 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39122 build_int_cst (unsigned_type_node, 0xff),
39125 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39127 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39129 double fenv_clear = __builtin_mffs ();
39130 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39131 __builtin_mtfsf (0xff, fenv_clear); */
39133 /* Mask to clear everything except for the rounding modes and non-IEEE
39134 arithmetic flag. */
39135 const unsigned HOST_WIDE_INT clear_exception_mask =
39136 HOST_WIDE_INT_C (0xffffffff00000000);
39138 tree fenv_clear = create_tmp_var_raw (double_type_node);
39140 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39142 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39143 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39145 build_int_cst (uint64_type_node,
39146 clear_exception_mask));
39148 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39149 fenv_clear_llu_and);
39151 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39152 build_int_cst (unsigned_type_node, 0xff),
39155 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39157 /* Generates the equivalent of feupdateenv (&fenv_var)
39159 double old_fenv = __builtin_mffs ();
39160 double fenv_update;
39161 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39162 (*(uint64_t*)fenv_var 0x1ff80fff);
39163 __builtin_mtfsf (0xff, fenv_update); */
39165 const unsigned HOST_WIDE_INT update_exception_mask =
39166 HOST_WIDE_INT_C (0xffffffff1fffff00);
39167 const unsigned HOST_WIDE_INT new_exception_mask =
39168 HOST_WIDE_INT_C (0x1ff80fff);
39170 tree old_fenv = create_tmp_var_raw (double_type_node);
39171 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39173 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39174 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39175 build_int_cst (uint64_type_node,
39176 update_exception_mask));
39178 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39179 build_int_cst (uint64_type_node,
39180 new_exception_mask));
39182 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39183 old_llu_and, new_llu_and);
39185 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39188 tree update_mtfsf = build_call_expr (mtfsf, 2,
39189 build_int_cst (unsigned_type_node, 0xff),
39190 fenv_update_mtfsf);
39192 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39196 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39198 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39200 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39201 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39203 /* The destination of the vmrgew instruction layout is:
39204 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39205 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39206 vmrgew instruction will be correct. */
39207 if (BYTES_BIG_ENDIAN)
39209 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39211 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39216 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39217 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39220 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39221 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39223 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39224 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39226 if (BYTES_BIG_ENDIAN)
39227 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39229 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39233 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39235 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39237 rtx_tmp0 = gen_reg_rtx (V2DImode);
39238 rtx_tmp1 = gen_reg_rtx (V2DImode);
39240 /* The destination of the vmrgew instruction layout is:
39241 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39242 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39243 vmrgew instruction will be correct. */
39244 if (BYTES_BIG_ENDIAN)
39246 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39247 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39251 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39252 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39255 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39256 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39258 if (signed_convert)
39260 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39261 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39265 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39266 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39269 if (BYTES_BIG_ENDIAN)
39270 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39272 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39276 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39279 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39281 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39282 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39284 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39285 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39287 rtx_tmp2 = gen_reg_rtx (V4SImode);
39288 rtx_tmp3 = gen_reg_rtx (V4SImode);
39290 if (signed_convert)
39292 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39293 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39297 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39298 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39301 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39304 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39307 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39308 optimization_type opt_type)
39313 return (opt_type == OPTIMIZE_FOR_SPEED
39314 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39321 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39323 static HOST_WIDE_INT
39324 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39326 if (TREE_CODE (exp) == STRING_CST
39327 && (STRICT_ALIGNMENT || !optimize_size))
39328 return MAX (align, BITS_PER_WORD);
39332 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39334 static HOST_WIDE_INT
39335 rs6000_starting_frame_offset (void)
39337 if (FRAME_GROWS_DOWNWARD)
39339 return RS6000_STARTING_FRAME_OFFSET;
39343 /* Create an alias for a mangled name where we have changed the mangling (in
39344 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39345 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39347 #if TARGET_ELF && RS6000_WEAK
39349 rs6000_globalize_decl_name (FILE * stream, tree decl)
39351 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
39353 targetm.asm_out.globalize_label (stream, name);
39355 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
39357 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
39358 const char *old_name;
39360 ieee128_mangling_gcc_8_1 = true;
39361 lang_hooks.set_decl_assembler_name (decl);
39362 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
39363 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
39364 ieee128_mangling_gcc_8_1 = false;
39366 if (strcmp (name, old_name) != 0)
39368 fprintf (stream, "\t.weak %s\n", old_name);
39369 fprintf (stream, "\t.set %s,%s\n", old_name, name);
39376 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39377 function names from <foo>l to <foo>f128 if the default long double type is
39378 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39379 include file switches the names on systems that support long double as IEEE
39380 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39381 In the future, glibc will export names like __ieee128_sinf128 and we can
39382 switch to using those instead of using sinf128, which pollutes the user's
39385 This will switch the names for Fortran math functions as well (which doesn't
39386 use math.h). However, Fortran needs other changes to the compiler and
39387 library before you can switch the real*16 type at compile time.
39389 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39390 only do this if the default is that long double is IBM extended double, and
39391 the user asked for IEEE 128-bit. */
39394 rs6000_mangle_decl_assembler_name (tree decl, tree id)
39396 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
39397 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
39399 size_t len = IDENTIFIER_LENGTH (id);
39400 const char *name = IDENTIFIER_POINTER (id);
39402 if (name[len - 1] == 'l')
39404 bool uses_ieee128_p = false;
39405 tree type = TREE_TYPE (decl);
39406 machine_mode ret_mode = TYPE_MODE (type);
39408 /* See if the function returns a IEEE 128-bit floating point type or
39410 if (ret_mode == TFmode || ret_mode == TCmode)
39411 uses_ieee128_p = true;
39414 function_args_iterator args_iter;
39417 /* See if the function passes a IEEE 128-bit floating point type
39418 or complex type. */
39419 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
39421 machine_mode arg_mode = TYPE_MODE (arg);
39422 if (arg_mode == TFmode || arg_mode == TCmode)
39424 uses_ieee128_p = true;
39430 /* If we passed or returned an IEEE 128-bit floating point type,
39431 change the name. */
39432 if (uses_ieee128_p)
39434 char *name2 = (char *) alloca (len + 4);
39435 memcpy (name2, name, len - 1);
39436 strcpy (name2 + len - 1, "f128");
39437 id = get_identifier (name2);
39446 struct gcc_target targetm = TARGET_INITIALIZER;
39448 #include "gt-rs6000.h"