1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float;
228 static bool rs6000_passes_long_double;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
248 static int dbg_cost_ctrl;
250 /* Built in types. */
251 tree rs6000_builtin_types[RS6000_BTI_MAX];
252 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized, need_toc_init;
256 char toc_label_name[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more;
262 static GTY(()) section *read_only_data_section;
263 static GTY(()) section *private_data_section;
264 static GTY(()) section *tls_data_section;
265 static GTY(()) section *tls_private_data_section;
266 static GTY(()) section *read_only_private_data_section;
267 static GTY(()) section *sdata2_section;
268 static GTY(()) section *toc_section;
270 struct builtin_description
272 const HOST_WIDE_INT mask;
273 const enum insn_code icode;
274 const char *const name;
275 const enum rs6000_builtins code;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
280 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align[NUM_MACHINE_MODES];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask {
299 RECIP_SF_DIV = 0x001, /* Use divide estimate */
300 RECIP_DF_DIV = 0x002,
301 RECIP_V4SF_DIV = 0x004,
302 RECIP_V2DF_DIV = 0x008,
304 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT = 0x020,
306 RECIP_V4SF_RSQRT = 0x040,
307 RECIP_V2DF_RSQRT = 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
315 RECIP_HIGH_PRECISION = RECIP_ALL,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
322 /* -mrecip options. */
325 const char *string; /* option name */
326 unsigned int mask; /* mask bits to set */
327 } recip_options[] = {
328 { "all", RECIP_ALL },
329 { "none", RECIP_NONE },
330 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
334 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT) },
336 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
337 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9 },
347 { "power8", PPC_PLATFORM_POWER8 },
348 { "power7", PPC_PLATFORM_POWER7 },
349 { "power6x", PPC_PLATFORM_POWER6X },
350 { "power6", PPC_PLATFORM_POWER6 },
351 { "power5+", PPC_PLATFORM_POWER5_PLUS },
352 { "power5", PPC_PLATFORM_POWER5 },
353 { "ppc970", PPC_PLATFORM_PPC970 },
354 { "power4", PPC_PLATFORM_POWER4 },
355 { "ppca2", PPC_PLATFORM_PPCA2 },
356 { "ppc476", PPC_PLATFORM_PPC476 },
357 { "ppc464", PPC_PLATFORM_PPC464 },
358 { "ppc440", PPC_PLATFORM_PPC440 },
359 { "ppc405", PPC_PLATFORM_PPC405 },
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
376 { "booke", PPC_FEATURE_BOOKE, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
384 { "notb", PPC_FEATURE_NO_TB, 0 },
385 { "pa6t", PPC_FEATURE_PA6T, 0 },
386 { "power4", PPC_FEATURE_POWER4, 0 },
387 { "power5", PPC_FEATURE_POWER5, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
390 { "ppc32", PPC_FEATURE_32, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
392 { "ppc64", PPC_FEATURE_64, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
394 { "smt", PPC_FEATURE_SMT, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
412 { "darn", PPC_FEATURE2_DARN, 1 },
413 { "scv", PPC_FEATURE2_SCV, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT = 0, /* default clone. */
422 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
432 const char *name; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type {
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type {
489 RELOAD_REG_GPR, /* General purpose registers. */
490 RELOAD_REG_FPR, /* Traditional floating point regs. */
491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type {
504 const char *name; /* Register class name. */
505 int reg; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
509 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr {
531 enum insn_code reload_load; /* INSN to reload for loading. */
532 enum insn_code reload_store; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
537 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode)
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode)
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode)
562 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
598 in_set = single_set (in_insn);
601 if (MEM_P (SET_DEST (in_set)))
603 out_set = single_set (out_insn);
606 out_pat = PATTERN (out_insn);
607 if (GET_CODE (out_pat) == PARALLEL)
609 for (i = 0; i < XVECLEN (out_pat, 0); i++)
611 out_exp = XVECEXP (out_pat, 0, i);
612 if ((GET_CODE (out_exp) == CLOBBER)
613 || (GET_CODE (out_exp) == USE))
615 else if (GET_CODE (out_exp) != SET)
624 in_pat = PATTERN (in_insn);
625 if (GET_CODE (in_pat) != PARALLEL)
628 for (i = 0; i < XVECLEN (in_pat, 0); i++)
630 in_exp = XVECEXP (in_pat, 0, i);
631 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
633 else if (GET_CODE (in_exp) != SET)
636 if (MEM_P (SET_DEST (in_exp)))
638 out_set = single_set (out_insn);
641 out_pat = PATTERN (out_insn);
642 if (GET_CODE (out_pat) != PARALLEL)
644 for (j = 0; j < XVECLEN (out_pat, 0); j++)
646 out_exp = XVECEXP (out_pat, 0, j);
647 if ((GET_CODE (out_exp) == CLOBBER)
648 || (GET_CODE (out_exp) == USE))
650 else if (GET_CODE (out_exp) != SET)
657 return store_data_bypass_p (out_insn, in_insn);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs *rs6000_cost;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost = {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost = {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost = {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost = {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost = {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost = {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost = {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost = {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost = {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost = {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost = {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost = {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost = {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost = {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost = {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost = {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost = {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost = {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost = {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost = {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost = {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost = {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost = {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost = {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost = {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost = {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost = {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost = {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost = {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost = {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type {
1307 const enum insn_code icode;
1308 const HOST_WIDE_INT mask;
1309 const unsigned attr;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1332 static struct machine_function * rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1338 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1339 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1340 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1343 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1345 static bool is_microcoded_insn (rtx_insn *);
1346 static bool is_nonpipeline_insn (rtx_insn *);
1347 static bool is_cracked_insn (rtx_insn *);
1348 static bool is_load_insn (rtx, rtx *);
1349 static bool is_store_insn (rtx, rtx *);
1350 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1351 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1352 static bool insn_must_be_first_in_group (rtx_insn *);
1353 static bool insn_must_be_last_in_group (rtx_insn *);
1354 static void altivec_init_builtins (void);
1355 static tree builtin_function_type (machine_mode, machine_mode,
1356 machine_mode, machine_mode,
1357 enum rs6000_builtins, const char *name);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t *rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx, void *);
1362 int easy_vector_constant (rtx, machine_mode);
1363 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1364 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1365 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1368 static void macho_branch_islands (void);
1369 static tree get_prev_label (tree);
1371 static bool rs6000_mode_dependent_address (const_rtx);
1372 static bool rs6000_debug_mode_dependent_address (const_rtx);
1373 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1374 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1376 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1380 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1382 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1385 static bool rs6000_debug_can_change_mode_class (machine_mode,
1388 static bool rs6000_save_toc_in_prologue_p (void);
1389 static rtx rs6000_internal_arg_pointer (void);
1391 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1392 = rs6000_mode_dependent_address;
1394 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1396 = rs6000_secondary_reload_class;
1398 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1399 = rs6000_preferred_reload_class;
1401 const int INSN_NOT_AVAILABLE = -1;
1403 static void rs6000_print_isa_options (FILE *, int, const char *,
1405 static void rs6000_print_builtin_options (FILE *, int, const char *,
1407 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1409 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1410 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1411 enum rs6000_reg_type,
1413 secondary_reload_info *,
1415 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1416 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1417 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1419 /* Hash table stuff for keeping track of TOC entries. */
1421 struct GTY((for_user)) toc_hash_struct
1423 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1424 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1426 machine_mode key_mode;
1430 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1432 static hashval_t hash (toc_hash_struct *);
1433 static bool equal (toc_hash_struct *, toc_hash_struct *);
1436 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1438 /* Hash table to keep track of the argument types for builtin functions. */
1440 struct GTY((for_user)) builtin_hash_struct
1443 machine_mode mode[4]; /* return value + 3 arguments. */
1444 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1447 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1449 static hashval_t hash (builtin_hash_struct *);
1450 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1453 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1456 /* Default register names. */
1457 char rs6000_reg_names[][8] =
1460 "0", "1", "2", "3", "4", "5", "6", "7",
1461 "8", "9", "10", "11", "12", "13", "14", "15",
1462 "16", "17", "18", "19", "20", "21", "22", "23",
1463 "24", "25", "26", "27", "28", "29", "30", "31",
1465 "0", "1", "2", "3", "4", "5", "6", "7",
1466 "8", "9", "10", "11", "12", "13", "14", "15",
1467 "16", "17", "18", "19", "20", "21", "22", "23",
1468 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "lr", "ctr", "ca", "ap",
1477 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* vrsave vscr sfp */
1479 "vrsave", "vscr", "sfp",
1482 #ifdef TARGET_REGNAMES
1483 static const char alt_reg_names[][8] =
1486 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1487 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1488 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1489 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1491 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1492 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1493 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1494 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1496 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1497 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1498 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1499 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1501 "lr", "ctr", "ca", "ap",
1503 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* vrsave vscr sfp */
1505 "vrsave", "vscr", "sfp",
1509 /* Table of valid machine attributes. */
1511 static const struct attribute_spec rs6000_attribute_table[] =
1513 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1514 affects_type_identity, handler, exclude } */
1515 { "altivec", 1, 1, false, true, false, false,
1516 rs6000_handle_altivec_attribute, NULL },
1517 { "longcall", 0, 0, false, true, true, false,
1518 rs6000_handle_longcall_attribute, NULL },
1519 { "shortcall", 0, 0, false, true, true, false,
1520 rs6000_handle_longcall_attribute, NULL },
1521 { "ms_struct", 0, 0, false, false, false, false,
1522 rs6000_handle_struct_attribute, NULL },
1523 { "gcc_struct", 0, 0, false, false, false, false,
1524 rs6000_handle_struct_attribute, NULL },
1525 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1526 SUBTARGET_ATTRIBUTE_TABLE,
1528 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1531 #ifndef TARGET_PROFILE_KERNEL
1532 #define TARGET_PROFILE_KERNEL 0
1535 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1536 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1538 /* Initialize the GCC target structure. */
1539 #undef TARGET_ATTRIBUTE_TABLE
1540 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1541 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1542 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1543 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1544 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1546 #undef TARGET_ASM_ALIGNED_DI_OP
1547 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1549 /* Default unaligned ops are only provided for ELF. Find the ops needed
1550 for non-ELF systems. */
1551 #ifndef OBJECT_FORMAT_ELF
1553 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1555 #undef TARGET_ASM_UNALIGNED_HI_OP
1556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1557 #undef TARGET_ASM_UNALIGNED_SI_OP
1558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1559 #undef TARGET_ASM_UNALIGNED_DI_OP
1560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1569 #undef TARGET_ASM_ALIGNED_DI_OP
1570 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1574 /* This hook deals with fixups for relocatable code and DI-mode objects
1576 #undef TARGET_ASM_INTEGER
1577 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1579 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1580 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1581 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1584 #undef TARGET_SET_UP_BY_PROLOGUE
1585 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1587 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1588 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1589 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1590 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1591 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1592 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1593 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1594 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1595 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1597 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1600 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1601 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1603 #undef TARGET_INTERNAL_ARG_POINTER
1604 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1606 #undef TARGET_HAVE_TLS
1607 #define TARGET_HAVE_TLS HAVE_AS_TLS
1609 #undef TARGET_CANNOT_FORCE_CONST_MEM
1610 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1612 #undef TARGET_DELEGITIMIZE_ADDRESS
1613 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1615 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1616 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1618 #undef TARGET_LEGITIMATE_COMBINED_INSN
1619 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1621 #undef TARGET_ASM_FUNCTION_PROLOGUE
1622 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1623 #undef TARGET_ASM_FUNCTION_EPILOGUE
1624 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1626 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1627 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1629 #undef TARGET_LEGITIMIZE_ADDRESS
1630 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1632 #undef TARGET_SCHED_VARIABLE_ISSUE
1633 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1635 #undef TARGET_SCHED_ISSUE_RATE
1636 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1637 #undef TARGET_SCHED_ADJUST_COST
1638 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1639 #undef TARGET_SCHED_ADJUST_PRIORITY
1640 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1641 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1642 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1643 #undef TARGET_SCHED_INIT
1644 #define TARGET_SCHED_INIT rs6000_sched_init
1645 #undef TARGET_SCHED_FINISH
1646 #define TARGET_SCHED_FINISH rs6000_sched_finish
1647 #undef TARGET_SCHED_REORDER
1648 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1649 #undef TARGET_SCHED_REORDER2
1650 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1652 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1653 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1658 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1659 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1660 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1661 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1662 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1663 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1664 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1665 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1667 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1668 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1670 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1671 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1672 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1673 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1674 rs6000_builtin_support_vector_misalignment
1675 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1676 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1677 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1678 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1679 rs6000_builtin_vectorization_cost
1680 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1681 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1682 rs6000_preferred_simd_mode
1683 #undef TARGET_VECTORIZE_INIT_COST
1684 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1685 #undef TARGET_VECTORIZE_ADD_STMT_COST
1686 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1687 #undef TARGET_VECTORIZE_FINISH_COST
1688 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1689 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1690 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1692 #undef TARGET_INIT_BUILTINS
1693 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1694 #undef TARGET_BUILTIN_DECL
1695 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1697 #undef TARGET_FOLD_BUILTIN
1698 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1699 #undef TARGET_GIMPLE_FOLD_BUILTIN
1700 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1702 #undef TARGET_EXPAND_BUILTIN
1703 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1705 #undef TARGET_MANGLE_TYPE
1706 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1708 #undef TARGET_INIT_LIBFUNCS
1709 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1712 #undef TARGET_BINDS_LOCAL_P
1713 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1716 #undef TARGET_MS_BITFIELD_LAYOUT_P
1717 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1719 #undef TARGET_ASM_OUTPUT_MI_THUNK
1720 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1722 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1723 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1726 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1728 #undef TARGET_REGISTER_MOVE_COST
1729 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1730 #undef TARGET_MEMORY_MOVE_COST
1731 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1732 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1733 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
1734 rs6000_ira_change_pseudo_allocno_class
1735 #undef TARGET_CANNOT_COPY_INSN_P
1736 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1737 #undef TARGET_RTX_COSTS
1738 #define TARGET_RTX_COSTS rs6000_rtx_costs
1739 #undef TARGET_ADDRESS_COST
1740 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1741 #undef TARGET_INSN_COST
1742 #define TARGET_INSN_COST rs6000_insn_cost
1744 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1745 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1747 #undef TARGET_PROMOTE_FUNCTION_MODE
1748 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1750 #undef TARGET_RETURN_IN_MEMORY
1751 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1753 #undef TARGET_RETURN_IN_MSB
1754 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1759 /* Always strict argument naming on rs6000. */
1760 #undef TARGET_STRICT_ARGUMENT_NAMING
1761 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1762 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1763 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_SPLIT_COMPLEX_ARG
1765 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1766 #undef TARGET_MUST_PASS_IN_STACK
1767 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1768 #undef TARGET_PASS_BY_REFERENCE
1769 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1770 #undef TARGET_ARG_PARTIAL_BYTES
1771 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1772 #undef TARGET_FUNCTION_ARG_ADVANCE
1773 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1774 #undef TARGET_FUNCTION_ARG
1775 #define TARGET_FUNCTION_ARG rs6000_function_arg
1776 #undef TARGET_FUNCTION_ARG_PADDING
1777 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1778 #undef TARGET_FUNCTION_ARG_BOUNDARY
1779 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1781 #undef TARGET_BUILD_BUILTIN_VA_LIST
1782 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1784 #undef TARGET_EXPAND_BUILTIN_VA_START
1785 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1788 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1790 #undef TARGET_EH_RETURN_FILTER_MODE
1791 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1793 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1794 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1796 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1797 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1799 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1800 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1802 #undef TARGET_FLOATN_MODE
1803 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1805 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1806 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1808 #undef TARGET_MD_ASM_ADJUST
1809 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1811 #undef TARGET_OPTION_OVERRIDE
1812 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1814 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1815 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1816 rs6000_builtin_vectorized_function
1818 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1820 rs6000_builtin_md_vectorized_function
1822 #undef TARGET_STACK_PROTECT_GUARD
1823 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1826 #undef TARGET_STACK_PROTECT_FAIL
1827 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1831 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1832 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1835 /* Use a 32-bit anchor range. This leads to sequences like:
1837 addis tmp,anchor,high
1840 where tmp itself acts as an anchor, and can be shared between
1841 accesses to the same 64k page. */
1842 #undef TARGET_MIN_ANCHOR_OFFSET
1843 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1844 #undef TARGET_MAX_ANCHOR_OFFSET
1845 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1846 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1847 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1848 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1849 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1851 #undef TARGET_BUILTIN_RECIPROCAL
1852 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1854 #undef TARGET_SECONDARY_RELOAD
1855 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1856 #undef TARGET_SECONDARY_MEMORY_NEEDED
1857 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1859 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1861 #undef TARGET_LEGITIMATE_ADDRESS_P
1862 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1864 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1865 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1867 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1868 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1870 #undef TARGET_CAN_ELIMINATE
1871 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1873 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1874 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1876 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1877 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1879 #undef TARGET_TRAMPOLINE_INIT
1880 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1882 #undef TARGET_FUNCTION_VALUE
1883 #define TARGET_FUNCTION_VALUE rs6000_function_value
1885 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1886 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1888 #undef TARGET_OPTION_SAVE
1889 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1891 #undef TARGET_OPTION_RESTORE
1892 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1894 #undef TARGET_OPTION_PRINT
1895 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1897 #undef TARGET_CAN_INLINE_P
1898 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1900 #undef TARGET_SET_CURRENT_FUNCTION
1901 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1903 #undef TARGET_LEGITIMATE_CONSTANT_P
1904 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1906 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1907 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1909 #undef TARGET_CAN_USE_DOLOOP_P
1910 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1912 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1913 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1916 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1919 #undef TARGET_UNWIND_WORD_MODE
1920 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1922 #undef TARGET_OFFLOAD_OPTIONS
1923 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1925 #undef TARGET_C_MODE_FOR_SUFFIX
1926 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1928 #undef TARGET_INVALID_BINARY_OP
1929 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1931 #undef TARGET_OPTAB_SUPPORTED_P
1932 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1934 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1935 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1937 #undef TARGET_COMPARE_VERSION_PRIORITY
1938 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1940 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1941 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1942 rs6000_generate_version_dispatcher_body
1944 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1945 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1946 rs6000_get_function_versions_dispatcher
1948 #undef TARGET_OPTION_FUNCTION_VERSIONS
1949 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1951 #undef TARGET_HARD_REGNO_NREGS
1952 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1953 #undef TARGET_HARD_REGNO_MODE_OK
1954 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1956 #undef TARGET_MODES_TIEABLE_P
1957 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1959 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1960 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1961 rs6000_hard_regno_call_part_clobbered
1963 #undef TARGET_SLOW_UNALIGNED_ACCESS
1964 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1966 #undef TARGET_CAN_CHANGE_MODE_CLASS
1967 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1969 #undef TARGET_CONSTANT_ALIGNMENT
1970 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1972 #undef TARGET_STARTING_FRAME_OFFSET
1973 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1975 #if TARGET_ELF && RS6000_WEAK
1976 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1977 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1980 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1981 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1983 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1984 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1987 /* Processor table. */
1990 const char *const name; /* Canonical processor name. */
1991 const enum processor_type processor; /* Processor type enum value. */
1992 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1995 static struct rs6000_ptt const processor_target_table[] =
1997 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1998 #include "rs6000-cpus.def"
2002 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2006 rs6000_cpu_name_lookup (const char *name)
2012 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2013 if (! strcmp (name, processor_target_table[i].name))
2021 /* Return number of consecutive hard regs needed starting at reg REGNO
2022 to hold something of mode MODE.
2023 This is ordinarily the length in words of a value of mode MODE
2024 but can be less for certain modes in special long registers.
2026 POWER and PowerPC GPRs hold 32 bits worth;
2027 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2030 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2032 unsigned HOST_WIDE_INT reg_size;
2034 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2035 128-bit floating point that can go in vector registers, which has VSX
2036 memory addressing. */
2037 if (FP_REGNO_P (regno))
2038 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2039 ? UNITS_PER_VSX_WORD
2040 : UNITS_PER_FP_WORD);
2042 else if (ALTIVEC_REGNO_P (regno))
2043 reg_size = UNITS_PER_ALTIVEC_WORD;
2046 reg_size = UNITS_PER_WORD;
2048 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2054 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2056 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2058 if (COMPLEX_MODE_P (mode))
2059 mode = GET_MODE_INNER (mode);
2061 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2062 register combinations, and use PTImode where we need to deal with quad
2063 word memory operations. Don't allow quad words in the argument or frame
2064 pointer registers, just registers 0..31. */
2065 if (mode == PTImode)
2066 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2067 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2068 && ((regno & 1) == 0));
2070 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2071 implementations. Don't allow an item to be split between a FP register
2072 and an Altivec register. Allow TImode in all VSX registers if the user
2074 if (TARGET_VSX && VSX_REGNO_P (regno)
2075 && (VECTOR_MEM_VSX_P (mode)
2076 || FLOAT128_VECTOR_P (mode)
2077 || reg_addr[mode].scalar_in_vmx_p
2079 || (TARGET_VADDUQM && mode == V1TImode)))
2081 if (FP_REGNO_P (regno))
2082 return FP_REGNO_P (last_regno);
2084 if (ALTIVEC_REGNO_P (regno))
2086 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2089 return ALTIVEC_REGNO_P (last_regno);
2093 /* The GPRs can hold any mode, but values bigger than one register
2094 cannot go past R31. */
2095 if (INT_REGNO_P (regno))
2096 return INT_REGNO_P (last_regno);
2098 /* The float registers (except for VSX vector modes) can only hold floating
2099 modes and DImode. */
2100 if (FP_REGNO_P (regno))
2102 if (FLOAT128_VECTOR_P (mode))
2105 if (SCALAR_FLOAT_MODE_P (mode)
2106 && (mode != TDmode || (regno % 2) == 0)
2107 && FP_REGNO_P (last_regno))
2110 if (GET_MODE_CLASS (mode) == MODE_INT)
2112 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2115 if (TARGET_P8_VECTOR && (mode == SImode))
2118 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2194 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2197 rs6000_hard_regno_call_part_clobbered (rtx_insn *insn ATTRIBUTE_UNUSED,
2198 unsigned int regno, machine_mode mode)
2202 && GET_MODE_SIZE (mode) > 4
2203 && INT_REGNO_P (regno))
2207 && FP_REGNO_P (regno)
2208 && GET_MODE_SIZE (mode) > 8
2209 && !FLOAT128_2REG_P (mode))
2215 /* Print interesting facts about registers. */
2217 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2221 for (r = first_regno; r <= last_regno; ++r)
2223 const char *comma = "";
2226 if (first_regno == last_regno)
2227 fprintf (stderr, "%s:\t", reg_name);
2229 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2232 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2233 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2237 fprintf (stderr, ",\n\t");
2242 if (rs6000_hard_regno_nregs[m][r] > 1)
2243 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2244 rs6000_hard_regno_nregs[m][r]);
2246 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2251 if (call_used_regs[r])
2255 fprintf (stderr, ",\n\t");
2260 len += fprintf (stderr, "%s%s", comma, "call-used");
2268 fprintf (stderr, ",\n\t");
2273 len += fprintf (stderr, "%s%s", comma, "fixed");
2279 fprintf (stderr, ",\n\t");
2283 len += fprintf (stderr, "%sreg-class = %s", comma,
2284 reg_class_names[(int)rs6000_regno_regclass[r]]);
2289 fprintf (stderr, ",\n\t");
2293 fprintf (stderr, "%sregno = %d\n", comma, r);
2298 rs6000_debug_vector_unit (enum rs6000_vector v)
2304 case VECTOR_NONE: ret = "none"; break;
2305 case VECTOR_ALTIVEC: ret = "altivec"; break;
2306 case VECTOR_VSX: ret = "vsx"; break;
2307 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2308 default: ret = "unknown"; break;
2314 /* Inner function printing just the address mask for a particular reload
2316 DEBUG_FUNCTION char *
2317 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2322 if ((mask & RELOAD_REG_VALID) != 0)
2324 else if (keep_spaces)
2327 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2329 else if (keep_spaces)
2332 if ((mask & RELOAD_REG_INDEXED) != 0)
2334 else if (keep_spaces)
2337 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2339 else if ((mask & RELOAD_REG_OFFSET) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2346 else if (keep_spaces)
2349 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2351 else if (keep_spaces)
2354 if ((mask & RELOAD_REG_AND_M16) != 0)
2356 else if (keep_spaces)
2364 /* Print the address masks in a human readble fashion. */
2366 rs6000_debug_print_mode (ssize_t m)
2371 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2372 for (rc = 0; rc < N_RELOAD_REG; rc++)
2373 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2374 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2376 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2377 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2379 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2380 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2381 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2385 spaces += sizeof (" Reload=sl") - 1;
2387 if (reg_addr[m].scalar_in_vmx_p)
2389 fprintf (stderr, "%*s Upper=y", spaces, "");
2393 spaces += sizeof (" Upper=y") - 1;
2395 if (rs6000_vector_unit[m] != VECTOR_NONE
2396 || rs6000_vector_mem[m] != VECTOR_NONE)
2398 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2400 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2401 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2404 fputs ("\n", stderr);
2407 #define DEBUG_FMT_ID "%-32s= "
2408 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2409 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2410 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2412 /* Print various interesting information with -mdebug=reg. */
2414 rs6000_debug_reg_global (void)
2416 static const char *const tf[2] = { "false", "true" };
2417 const char *nl = (const char *)0;
2420 char costly_num[20];
2422 char flags_buffer[40];
2423 const char *costly_str;
2424 const char *nop_str;
2425 const char *trace_str;
2426 const char *abi_str;
2427 const char *cmodel_str;
2428 struct cl_target_option cl_opts;
2430 /* Modes we want tieable information on. */
2431 static const machine_mode print_tieable_modes[] = {
2465 /* Virtual regs we are interested in. */
2466 const static struct {
2467 int regno; /* register number. */
2468 const char *name; /* register name. */
2469 } virtual_regs[] = {
2470 { STACK_POINTER_REGNUM, "stack pointer:" },
2471 { TOC_REGNUM, "toc: " },
2472 { STATIC_CHAIN_REGNUM, "static chain: " },
2473 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2474 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2475 { ARG_POINTER_REGNUM, "arg pointer: " },
2476 { FRAME_POINTER_REGNUM, "frame pointer:" },
2477 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2478 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2479 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2480 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2481 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2482 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2483 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2484 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2485 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2488 fputs ("\nHard register information:\n", stderr);
2489 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2490 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2491 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2494 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2495 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2496 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2497 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2498 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2499 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2501 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2502 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2503 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2507 "d reg_class = %s\n"
2508 "f reg_class = %s\n"
2509 "v reg_class = %s\n"
2510 "wa reg_class = %s\n"
2511 "wd reg_class = %s\n"
2512 "we reg_class = %s\n"
2513 "wf reg_class = %s\n"
2514 "wg reg_class = %s\n"
2515 "wi reg_class = %s\n"
2516 "wp reg_class = %s\n"
2517 "wq reg_class = %s\n"
2518 "wr reg_class = %s\n"
2519 "ws reg_class = %s\n"
2520 "wt reg_class = %s\n"
2521 "wv reg_class = %s\n"
2522 "ww reg_class = %s\n"
2523 "wx reg_class = %s\n"
2524 "wz reg_class = %s\n"
2525 "wA reg_class = %s\n"
2527 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2528 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2529 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2530 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2531 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2532 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2533 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2534 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2535 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2536 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2537 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2538 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2539 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2540 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2541 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2542 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2543 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2544 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2545 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
2548 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2549 rs6000_debug_print_mode (m);
2551 fputs ("\n", stderr);
2553 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2555 machine_mode mode1 = print_tieable_modes[m1];
2556 bool first_time = true;
2558 nl = (const char *)0;
2559 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2561 machine_mode mode2 = print_tieable_modes[m2];
2562 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2566 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2571 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2576 fputs ("\n", stderr);
2582 if (rs6000_recip_control)
2584 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2586 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2587 if (rs6000_recip_bits[m])
2590 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2592 (RS6000_RECIP_AUTO_RE_P (m)
2594 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2595 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2597 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2600 fputs ("\n", stderr);
2603 if (rs6000_cpu_index >= 0)
2605 const char *name = processor_target_table[rs6000_cpu_index].name;
2607 = processor_target_table[rs6000_cpu_index].target_enable;
2609 sprintf (flags_buffer, "-mcpu=%s flags", name);
2610 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2613 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2615 if (rs6000_tune_index >= 0)
2617 const char *name = processor_target_table[rs6000_tune_index].name;
2619 = processor_target_table[rs6000_tune_index].target_enable;
2621 sprintf (flags_buffer, "-mtune=%s flags", name);
2622 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2625 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2627 cl_target_option_save (&cl_opts, &global_options);
2628 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2631 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2632 rs6000_isa_flags_explicit);
2634 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2635 rs6000_builtin_mask);
2637 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2639 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2640 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2642 switch (rs6000_sched_costly_dep)
2644 case max_dep_latency:
2645 costly_str = "max_dep_latency";
2649 costly_str = "no_dep_costly";
2652 case all_deps_costly:
2653 costly_str = "all_deps_costly";
2656 case true_store_to_load_dep_costly:
2657 costly_str = "true_store_to_load_dep_costly";
2660 case store_to_load_dep_costly:
2661 costly_str = "store_to_load_dep_costly";
2665 costly_str = costly_num;
2666 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2670 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2672 switch (rs6000_sched_insert_nops)
2674 case sched_finish_regroup_exact:
2675 nop_str = "sched_finish_regroup_exact";
2678 case sched_finish_pad_groups:
2679 nop_str = "sched_finish_pad_groups";
2682 case sched_finish_none:
2683 nop_str = "sched_finish_none";
2688 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2692 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2694 switch (rs6000_sdata)
2701 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2705 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2709 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2714 switch (rs6000_traceback)
2716 case traceback_default: trace_str = "default"; break;
2717 case traceback_none: trace_str = "none"; break;
2718 case traceback_part: trace_str = "part"; break;
2719 case traceback_full: trace_str = "full"; break;
2720 default: trace_str = "unknown"; break;
2723 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2725 switch (rs6000_current_cmodel)
2727 case CMODEL_SMALL: cmodel_str = "small"; break;
2728 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2729 case CMODEL_LARGE: cmodel_str = "large"; break;
2730 default: cmodel_str = "unknown"; break;
2733 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2735 switch (rs6000_current_abi)
2737 case ABI_NONE: abi_str = "none"; break;
2738 case ABI_AIX: abi_str = "aix"; break;
2739 case ABI_ELFv2: abi_str = "ELFv2"; break;
2740 case ABI_V4: abi_str = "V4"; break;
2741 case ABI_DARWIN: abi_str = "darwin"; break;
2742 default: abi_str = "unknown"; break;
2745 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2747 if (rs6000_altivec_abi)
2748 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2750 if (rs6000_darwin64_abi)
2751 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2753 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2754 (TARGET_SOFT_FLOAT ? "true" : "false"));
2756 if (TARGET_LINK_STACK)
2757 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2759 if (TARGET_P8_FUSION)
2763 strcpy (options, "power8");
2764 if (TARGET_P8_FUSION_SIGN)
2765 strcat (options, ", sign");
2767 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2770 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2771 TARGET_SECURE_PLT ? "secure" : "bss");
2772 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2773 aix_struct_return ? "aix" : "sysv");
2774 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2775 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2776 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2777 tf[!!rs6000_align_branch_targets]);
2778 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2779 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2780 rs6000_long_double_type_size);
2781 if (rs6000_long_double_type_size > 64)
2783 fprintf (stderr, DEBUG_FMT_S, "long double type",
2784 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2785 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2786 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2788 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2789 (int)rs6000_sched_restricted_insns_priority);
2790 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2792 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2793 (int)RS6000_BUILTIN_COUNT);
2795 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2796 (int)TARGET_FLOAT128_ENABLE_TYPE);
2799 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2800 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2802 if (TARGET_DIRECT_MOVE_128)
2803 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2804 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2808 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2809 legitimate address support to figure out the appropriate addressing to
2813 rs6000_setup_reg_addr_masks (void)
2815 ssize_t rc, reg, m, nregs;
2816 addr_mask_type any_addr_mask, addr_mask;
2818 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2820 machine_mode m2 = (machine_mode) m;
2821 bool complex_p = false;
2822 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2825 if (COMPLEX_MODE_P (m2))
2828 m2 = GET_MODE_INNER (m2);
2831 msize = GET_MODE_SIZE (m2);
2833 /* SDmode is special in that we want to access it only via REG+REG
2834 addressing on power7 and above, since we want to use the LFIWZX and
2835 STFIWZX instructions to load it. */
2836 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2839 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2842 reg = reload_reg_map[rc].reg;
2844 /* Can mode values go in the GPR/FPR/Altivec registers? */
2845 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2847 bool small_int_vsx_p = (small_int_p
2848 && (rc == RELOAD_REG_FPR
2849 || rc == RELOAD_REG_VMX));
2851 nregs = rs6000_hard_regno_nregs[m][reg];
2852 addr_mask |= RELOAD_REG_VALID;
2854 /* Indicate if the mode takes more than 1 physical register. If
2855 it takes a single register, indicate it can do REG+REG
2856 addressing. Small integers in VSX registers can only do
2857 REG+REG addressing. */
2858 if (small_int_vsx_p)
2859 addr_mask |= RELOAD_REG_INDEXED;
2860 else if (nregs > 1 || m == BLKmode || complex_p)
2861 addr_mask |= RELOAD_REG_MULTIPLE;
2863 addr_mask |= RELOAD_REG_INDEXED;
2865 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2866 addressing. If we allow scalars into Altivec registers,
2867 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2869 For VSX systems, we don't allow update addressing for
2870 DFmode/SFmode if those registers can go in both the
2871 traditional floating point registers and Altivec registers.
2872 The load/store instructions for the Altivec registers do not
2873 have update forms. If we allowed update addressing, it seems
2874 to break IV-OPT code using floating point if the index type is
2875 int instead of long (PR target/81550 and target/84042). */
2878 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2880 && !VECTOR_MODE_P (m2)
2881 && !FLOAT128_VECTOR_P (m2)
2883 && (m != E_DFmode || !TARGET_VSX)
2884 && (m != E_SFmode || !TARGET_P8_VECTOR)
2885 && !small_int_vsx_p)
2887 addr_mask |= RELOAD_REG_PRE_INCDEC;
2889 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2890 we don't allow PRE_MODIFY for some multi-register
2895 addr_mask |= RELOAD_REG_PRE_MODIFY;
2899 if (TARGET_POWERPC64)
2900 addr_mask |= RELOAD_REG_PRE_MODIFY;
2905 if (TARGET_HARD_FLOAT)
2906 addr_mask |= RELOAD_REG_PRE_MODIFY;
2912 /* GPR and FPR registers can do REG+OFFSET addressing, except
2913 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2914 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2915 if ((addr_mask != 0) && !indexed_only_p
2917 && (rc == RELOAD_REG_GPR
2918 || ((msize == 8 || m2 == SFmode)
2919 && (rc == RELOAD_REG_FPR
2920 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2921 addr_mask |= RELOAD_REG_OFFSET;
2923 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2924 instructions are enabled. The offset for 128-bit VSX registers is
2925 only 12-bits. While GPRs can handle the full offset range, VSX
2926 registers can only handle the restricted range. */
2927 else if ((addr_mask != 0) && !indexed_only_p
2928 && msize == 16 && TARGET_P9_VECTOR
2929 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2930 || (m2 == TImode && TARGET_VSX)))
2932 addr_mask |= RELOAD_REG_OFFSET;
2933 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2934 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2937 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2938 addressing on 128-bit types. */
2939 if (rc == RELOAD_REG_VMX && msize == 16
2940 && (addr_mask & RELOAD_REG_VALID) != 0)
2941 addr_mask |= RELOAD_REG_AND_M16;
2943 reg_addr[m].addr_mask[rc] = addr_mask;
2944 any_addr_mask |= addr_mask;
2947 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2952 /* Initialize the various global tables that are based on register size. */
2954 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2960 /* Precalculate REGNO_REG_CLASS. */
2961 rs6000_regno_regclass[0] = GENERAL_REGS;
2962 for (r = 1; r < 32; ++r)
2963 rs6000_regno_regclass[r] = BASE_REGS;
2965 for (r = 32; r < 64; ++r)
2966 rs6000_regno_regclass[r] = FLOAT_REGS;
2968 for (r = 64; HARD_REGISTER_NUM_P (r); ++r)
2969 rs6000_regno_regclass[r] = NO_REGS;
2971 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2972 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2974 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2975 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2976 rs6000_regno_regclass[r] = CR_REGS;
2978 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2979 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2980 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2981 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2982 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2983 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2984 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2986 /* Precalculate register class to simpler reload register class. We don't
2987 need all of the register classes that are combinations of different
2988 classes, just the simple ones that have constraint letters. */
2989 for (c = 0; c < N_REG_CLASSES; c++)
2990 reg_class_to_reg_type[c] = NO_REG_TYPE;
2992 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2993 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
2994 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
2995 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
2996 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
2997 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
2998 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
2999 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3000 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3001 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3005 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3006 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3010 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3011 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3014 /* Precalculate the valid memory formats as well as the vector information,
3015 this must be set up before the rs6000_hard_regno_nregs_internal calls
3017 gcc_assert ((int)VECTOR_NONE == 0);
3018 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3019 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem));
3021 gcc_assert ((int)CODE_FOR_nothing == 0);
3022 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3024 gcc_assert ((int)NO_REGS == 0);
3025 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3027 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3028 believes it can use native alignment or still uses 128-bit alignment. */
3029 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3040 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3041 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3042 if (TARGET_FLOAT128_TYPE)
3044 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3045 rs6000_vector_align[KFmode] = 128;
3047 if (FLOAT128_IEEE_P (TFmode))
3049 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3050 rs6000_vector_align[TFmode] = 128;
3054 /* V2DF mode, VSX only. */
3057 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3058 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3059 rs6000_vector_align[V2DFmode] = align64;
3062 /* V4SF mode, either VSX or Altivec. */
3065 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3066 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3067 rs6000_vector_align[V4SFmode] = align32;
3069 else if (TARGET_ALTIVEC)
3071 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3072 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3073 rs6000_vector_align[V4SFmode] = align32;
3076 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3080 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3081 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3082 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3083 rs6000_vector_align[V4SImode] = align32;
3084 rs6000_vector_align[V8HImode] = align32;
3085 rs6000_vector_align[V16QImode] = align32;
3089 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3090 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3091 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3095 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3096 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3097 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3101 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3102 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3105 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3106 rs6000_vector_unit[V2DImode]
3107 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3108 rs6000_vector_align[V2DImode] = align64;
3110 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3111 rs6000_vector_unit[V1TImode]
3112 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3113 rs6000_vector_align[V1TImode] = 128;
3116 /* DFmode, see if we want to use the VSX unit. Memory is handled
3117 differently, so don't set rs6000_vector_mem. */
3120 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3121 rs6000_vector_align[DFmode] = 64;
3124 /* SFmode, see if we want to use the VSX unit. */
3125 if (TARGET_P8_VECTOR)
3127 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3128 rs6000_vector_align[SFmode] = 32;
3131 /* Allow TImode in VSX register and set the VSX memory macros. */
3134 rs6000_vector_mem[TImode] = VECTOR_VSX;
3135 rs6000_vector_align[TImode] = align64;
3138 /* Register class constraints for the constraints that depend on compile
3139 switches. When the VSX code was added, different constraints were added
3140 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3141 of the VSX registers are used. The register classes for scalar floating
3142 point types is set, based on whether we allow that type into the upper
3143 (Altivec) registers. GCC has register classes to target the Altivec
3144 registers for load/store operations, to select using a VSX memory
3145 operation instead of the traditional floating point operation. The
3148 d - Register class to use with traditional DFmode instructions.
3149 f - Register class to use with traditional SFmode instructions.
3150 v - Altivec register.
3151 wa - Any VSX register.
3152 wc - Reserved to represent individual CR bits (used in LLVM).
3153 wd - Preferred register class for V2DFmode.
3154 wf - Preferred register class for V4SFmode.
3155 wg - Float register for power6x move insns.
3156 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3157 wn - always NO_REGS.
3158 wr - GPR if 64-bit mode is permitted.
3159 ws - Register class to do ISA 2.06 DF operations.
3160 wt - VSX register for TImode in VSX registers.
3161 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3162 ww - Register class to do SF conversions in with VSX operations.
3163 wx - Float register if we can do 32-bit int stores.
3164 wz - Float register if we can do 32-bit unsigned int loads. */
3166 if (TARGET_HARD_FLOAT)
3168 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3169 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3174 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3175 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3176 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3177 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3178 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3179 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3180 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3183 /* Add conditional constraints based on various options, to allow us to
3184 collapse multiple insn patterns. */
3186 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3188 if (TARGET_MFPGPR) /* DFmode */
3189 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3191 if (TARGET_POWERPC64)
3193 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3194 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3197 if (TARGET_P8_VECTOR) /* SFmode */
3198 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3199 else if (TARGET_VSX)
3200 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3203 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3206 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3208 if (TARGET_FLOAT128_TYPE)
3210 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3211 if (FLOAT128_IEEE_P (TFmode))
3212 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3215 /* Support for new direct moves (ISA 3.0 + 64bit). */
3216 if (TARGET_DIRECT_MOVE_128)
3217 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3219 /* Set up the reload helper and direct move functions. */
3220 if (TARGET_VSX || TARGET_ALTIVEC)
3224 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3225 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3226 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3227 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3228 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3229 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3230 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3231 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3232 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3233 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3234 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3235 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3236 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3237 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3238 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3239 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3240 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3241 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3242 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3243 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3245 if (FLOAT128_VECTOR_P (KFmode))
3247 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3248 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3251 if (FLOAT128_VECTOR_P (TFmode))
3253 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3254 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3257 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3259 if (TARGET_NO_SDMODE_STACK)
3261 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3262 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3267 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3268 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3271 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3273 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3274 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3275 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3276 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3277 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3278 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3279 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3280 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3281 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3283 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3284 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3285 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3286 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3287 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3288 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3289 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3290 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3291 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3293 if (FLOAT128_VECTOR_P (KFmode))
3295 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3296 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3299 if (FLOAT128_VECTOR_P (TFmode))
3301 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3302 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3308 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3309 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3310 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3311 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3312 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3313 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3314 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3315 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3316 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3317 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3318 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3319 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3320 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3321 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3322 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3323 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3324 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3325 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3326 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3327 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3329 if (FLOAT128_VECTOR_P (KFmode))
3331 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3332 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3335 if (FLOAT128_IEEE_P (TFmode))
3337 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3338 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3341 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3343 if (TARGET_NO_SDMODE_STACK)
3345 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3346 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3351 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3352 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3355 if (TARGET_DIRECT_MOVE)
3357 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3358 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3359 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3363 reg_addr[DFmode].scalar_in_vmx_p = true;
3364 reg_addr[DImode].scalar_in_vmx_p = true;
3366 if (TARGET_P8_VECTOR)
3368 reg_addr[SFmode].scalar_in_vmx_p = true;
3369 reg_addr[SImode].scalar_in_vmx_p = true;
3371 if (TARGET_P9_VECTOR)
3373 reg_addr[HImode].scalar_in_vmx_p = true;
3374 reg_addr[QImode].scalar_in_vmx_p = true;
3379 /* Precalculate HARD_REGNO_NREGS. */
3380 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3381 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3382 rs6000_hard_regno_nregs[m][r]
3383 = rs6000_hard_regno_nregs_internal (r, (machine_mode) m);
3385 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3386 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3387 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3388 rs6000_hard_regno_mode_ok_p[m][r]
3389 = rs6000_hard_regno_mode_ok_uncached (r, (machine_mode) m);
3391 /* Precalculate CLASS_MAX_NREGS sizes. */
3392 for (c = 0; c < LIM_REG_CLASSES; ++c)
3396 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3397 reg_size = UNITS_PER_VSX_WORD;
3399 else if (c == ALTIVEC_REGS)
3400 reg_size = UNITS_PER_ALTIVEC_WORD;
3402 else if (c == FLOAT_REGS)
3403 reg_size = UNITS_PER_FP_WORD;
3406 reg_size = UNITS_PER_WORD;
3408 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3410 machine_mode m2 = (machine_mode)m;
3411 int reg_size2 = reg_size;
3413 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3415 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3416 reg_size2 = UNITS_PER_FP_WORD;
3418 rs6000_class_max_nregs[m][c]
3419 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3423 /* Calculate which modes to automatically generate code to use a the
3424 reciprocal divide and square root instructions. In the future, possibly
3425 automatically generate the instructions even if the user did not specify
3426 -mrecip. The older machines double precision reciprocal sqrt estimate is
3427 not accurate enough. */
3428 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3430 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3432 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3433 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3434 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3435 if (VECTOR_UNIT_VSX_P (V2DFmode))
3436 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3438 if (TARGET_FRSQRTES)
3439 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3441 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3442 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3443 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3444 if (VECTOR_UNIT_VSX_P (V2DFmode))
3445 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3447 if (rs6000_recip_control)
3449 if (!flag_finite_math_only)
3450 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3452 if (flag_trapping_math)
3453 warning (0, "%qs requires %qs or %qs", "-mrecip",
3454 "-fno-trapping-math", "-ffast-math");
3455 if (!flag_reciprocal_math)
3456 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3458 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3460 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3461 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3462 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3464 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3465 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3466 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3468 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3469 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3470 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3472 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3473 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3474 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3476 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3477 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3478 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3480 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3481 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3482 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3484 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3485 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3486 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3488 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3489 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3490 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3494 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3495 legitimate address support to figure out the appropriate addressing to
3497 rs6000_setup_reg_addr_masks ();
3499 if (global_init_p || TARGET_DEBUG_TARGET)
3501 if (TARGET_DEBUG_REG)
3502 rs6000_debug_reg_global ();
3504 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3506 "SImode variable mult cost = %d\n"
3507 "SImode constant mult cost = %d\n"
3508 "SImode short constant mult cost = %d\n"
3509 "DImode multipliciation cost = %d\n"
3510 "SImode division cost = %d\n"
3511 "DImode division cost = %d\n"
3512 "Simple fp operation cost = %d\n"
3513 "DFmode multiplication cost = %d\n"
3514 "SFmode division cost = %d\n"
3515 "DFmode division cost = %d\n"
3516 "cache line size = %d\n"
3517 "l1 cache size = %d\n"
3518 "l2 cache size = %d\n"
3519 "simultaneous prefetches = %d\n"
3522 rs6000_cost->mulsi_const,
3523 rs6000_cost->mulsi_const9,
3531 rs6000_cost->cache_line_size,
3532 rs6000_cost->l1_cache_size,
3533 rs6000_cost->l2_cache_size,
3534 rs6000_cost->simultaneous_prefetches);
3539 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3542 darwin_rs6000_override_options (void)
3544 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3546 rs6000_altivec_abi = 1;
3547 TARGET_ALTIVEC_VRSAVE = 1;
3548 rs6000_current_abi = ABI_DARWIN;
3550 if (DEFAULT_ABI == ABI_DARWIN
3552 darwin_one_byte_bool = 1;
3554 if (TARGET_64BIT && ! TARGET_POWERPC64)
3556 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3557 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3561 rs6000_default_long_calls = 1;
3562 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3565 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3567 if (!flag_mkernel && !flag_apple_kext
3569 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3570 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3572 /* Unless the user (not the configurer) has explicitly overridden
3573 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3574 G4 unless targeting the kernel. */
3577 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3578 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3579 && ! global_options_set.x_rs6000_cpu_index)
3581 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3586 /* If not otherwise specified by a target, make 'long double' equivalent to
3589 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3590 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3593 /* Return the builtin mask of the various options used that could affect which
3594 builtins were used. In the past we used target_flags, but we've run out of
3595 bits, and some options are no longer in target_flags. */
3598 rs6000_builtin_mask_calculate (void)
3600 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3601 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3602 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3603 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3604 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3605 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3606 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3607 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3608 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3609 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3610 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3611 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3612 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3613 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3614 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3615 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3616 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3617 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3618 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3619 | ((TARGET_LONG_DOUBLE_128
3620 && TARGET_HARD_FLOAT
3621 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3622 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3623 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3626 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3627 to clobber the XER[CA] bit because clobbering that bit without telling
3628 the compiler worked just fine with versions of GCC before GCC 5, and
3629 breaking a lot of older code in ways that are hard to track down is
3630 not such a great idea. */
3633 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3634 vec<const char *> &/*constraints*/,
3635 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3637 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3638 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3642 /* Override command line options.
3644 Combine build-specific configuration information with options
3645 specified on the command line to set various state variables which
3646 influence code generation, optimization, and expansion of built-in
3647 functions. Assure that command-line configuration preferences are
3648 compatible with each other and with the build configuration; issue
3649 warnings while adjusting configuration or error messages while
3650 rejecting configuration.
3652 Upon entry to this function:
3654 This function is called once at the beginning of
3655 compilation, and then again at the start and end of compiling
3656 each section of code that has a different configuration, as
3657 indicated, for example, by adding the
3659 __attribute__((__target__("cpu=power9")))
3661 qualifier to a function definition or, for example, by bracketing
3664 #pragma GCC target("altivec")
3668 #pragma GCC reset_options
3670 directives. Parameter global_init_p is true for the initial
3671 invocation, which initializes global variables, and false for all
3672 subsequent invocations.
3675 Various global state information is assumed to be valid. This
3676 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3677 default CPU specified at build configure time, TARGET_DEFAULT,
3678 representing the default set of option flags for the default
3679 target, and global_options_set.x_rs6000_isa_flags, representing
3680 which options were requested on the command line.
3682 Upon return from this function:
3684 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3685 was set by name on the command line. Additionally, if certain
3686 attributes are automatically enabled or disabled by this function
3687 in order to assure compatibility between options and
3688 configuration, the flags associated with those attributes are
3689 also set. By setting these "explicit bits", we avoid the risk
3690 that other code might accidentally overwrite these particular
3691 attributes with "default values".
3693 The various bits of rs6000_isa_flags are set to indicate the
3694 target options that have been selected for the most current
3695 compilation efforts. This has the effect of also turning on the
3696 associated TARGET_XXX values since these are macros which are
3697 generally defined to test the corresponding bit of the
3698 rs6000_isa_flags variable.
3700 The variable rs6000_builtin_mask is set to represent the target
3701 options for the most current compilation efforts, consistent with
3702 the current contents of rs6000_isa_flags. This variable controls
3703 expansion of built-in functions.
3705 Various other global variables and fields of global structures
3706 (over 50 in all) are initialized to reflect the desired options
3707 for the most current compilation efforts. */
3710 rs6000_option_override_internal (bool global_init_p)
3714 HOST_WIDE_INT set_masks;
3715 HOST_WIDE_INT ignore_masks;
3718 struct cl_target_option *main_target_opt
3719 = ((global_init_p || target_option_default_node == NULL)
3720 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3722 /* Print defaults. */
3723 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3724 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3726 /* Remember the explicit arguments. */
3728 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3730 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3731 library functions, so warn about it. The flag may be useful for
3732 performance studies from time to time though, so don't disable it
3734 if (global_options_set.x_rs6000_alignment_flags
3735 && rs6000_alignment_flags == MASK_ALIGN_POWER
3736 && DEFAULT_ABI == ABI_DARWIN
3738 warning (0, "%qs is not supported for 64-bit Darwin;"
3739 " it is incompatible with the installed C and C++ libraries",
3742 /* Numerous experiment shows that IRA based loop pressure
3743 calculation works better for RTL loop invariant motion on targets
3744 with enough (>= 32) registers. It is an expensive optimization.
3745 So it is on only for peak performance. */
3746 if (optimize >= 3 && global_init_p
3747 && !global_options_set.x_flag_ira_loop_pressure)
3748 flag_ira_loop_pressure = 1;
3750 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3751 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3752 options were already specified. */
3753 if (flag_sanitize & SANITIZE_USER_ADDRESS
3754 && !global_options_set.x_flag_asynchronous_unwind_tables)
3755 flag_asynchronous_unwind_tables = 1;
3757 /* Set the pointer size. */
3760 rs6000_pmode = DImode;
3761 rs6000_pointer_size = 64;
3765 rs6000_pmode = SImode;
3766 rs6000_pointer_size = 32;
3769 /* Some OSs don't support saving the high part of 64-bit registers on context
3770 switch. Other OSs don't support saving Altivec registers. On those OSs,
3771 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3772 if the user wants either, the user must explicitly specify them and we
3773 won't interfere with the user's specification. */
3775 set_masks = POWERPC_MASKS;
3776 #ifdef OS_MISSING_POWERPC64
3777 if (OS_MISSING_POWERPC64)
3778 set_masks &= ~OPTION_MASK_POWERPC64;
3780 #ifdef OS_MISSING_ALTIVEC
3781 if (OS_MISSING_ALTIVEC)
3782 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3783 | OTHER_VSX_VECTOR_MASKS);
3786 /* Don't override by the processor default if given explicitly. */
3787 set_masks &= ~rs6000_isa_flags_explicit;
3789 if (global_init_p && rs6000_dejagnu_cpu_index >= 0)
3790 rs6000_cpu_index = rs6000_dejagnu_cpu_index;
3792 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3793 the cpu in a target attribute or pragma, but did not specify a tuning
3794 option, use the cpu for the tuning option rather than the option specified
3795 with -mtune on the command line. Process a '--with-cpu' configuration
3796 request as an implicit --cpu. */
3797 if (rs6000_cpu_index >= 0)
3798 cpu_index = rs6000_cpu_index;
3799 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3800 cpu_index = main_target_opt->x_rs6000_cpu_index;
3801 else if (OPTION_TARGET_CPU_DEFAULT)
3802 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3804 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3805 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3806 with those from the cpu, except for options that were explicitly set. If
3807 we don't have a cpu, do not override the target bits set in
3811 rs6000_cpu_index = cpu_index;
3812 rs6000_isa_flags &= ~set_masks;
3813 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3818 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3819 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3820 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3821 to using rs6000_isa_flags, we need to do the initialization here.
3823 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3824 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3825 HOST_WIDE_INT flags;
3827 flags = TARGET_DEFAULT;
3830 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3831 const char *default_cpu = (!TARGET_POWERPC64
3836 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3837 flags = processor_target_table[default_cpu_index].target_enable;
3839 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3842 if (rs6000_tune_index >= 0)
3843 tune_index = rs6000_tune_index;
3844 else if (cpu_index >= 0)
3845 rs6000_tune_index = tune_index = cpu_index;
3849 enum processor_type tune_proc
3850 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3853 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3854 if (processor_target_table[i].processor == tune_proc)
3862 rs6000_cpu = processor_target_table[cpu_index].processor;
3864 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3866 gcc_assert (tune_index >= 0);
3867 rs6000_tune = processor_target_table[tune_index].processor;
3869 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3870 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3871 || rs6000_cpu == PROCESSOR_PPCE5500)
3874 error ("AltiVec not supported in this target");
3877 /* If we are optimizing big endian systems for space, use the load/store
3878 multiple instructions. */
3879 if (BYTES_BIG_ENDIAN && optimize_size)
3880 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3882 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3883 because the hardware doesn't support the instructions used in little
3884 endian mode, and causes an alignment trap. The 750 does not cause an
3885 alignment trap (except when the target is unaligned). */
3887 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3889 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3890 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3891 warning (0, "%qs is not supported on little endian systems",
3895 /* If little-endian, default to -mstrict-align on older processors.
3896 Testing for htm matches power8 and later. */
3897 if (!BYTES_BIG_ENDIAN
3898 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3899 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3901 if (!rs6000_fold_gimple)
3903 "gimple folding of rs6000 builtins has been disabled.\n");
3905 /* Add some warnings for VSX. */
3908 const char *msg = NULL;
3909 if (!TARGET_HARD_FLOAT)
3911 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3912 msg = N_("%<-mvsx%> requires hardware floating point");
3915 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3916 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3919 else if (TARGET_AVOID_XFORM > 0)
3920 msg = N_("%<-mvsx%> needs indexed addressing");
3921 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3922 & OPTION_MASK_ALTIVEC))
3924 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3925 msg = N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
3927 msg = N_("%<-mno-altivec%> disables vsx");
3933 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3934 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3938 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3939 the -mcpu setting to enable options that conflict. */
3940 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3941 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3942 | OPTION_MASK_ALTIVEC
3943 | OPTION_MASK_VSX)) != 0)
3944 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3945 | OPTION_MASK_DIRECT_MOVE)
3946 & ~rs6000_isa_flags_explicit);
3948 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3949 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3951 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
3952 off all of the options that depend on those flags. */
3953 ignore_masks = rs6000_disable_incompatible_switches ();
3955 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3956 unless the user explicitly used the -mno-<option> to disable the code. */
3957 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
3958 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3959 else if (TARGET_P9_MINMAX)
3963 if (cpu_index == PROCESSOR_POWER9)
3965 /* legacy behavior: allow -mcpu=power9 with certain
3966 capabilities explicitly disabled. */
3967 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3970 error ("power9 target option is incompatible with %<%s=<xxx>%> "
3971 "for <xxx> less than power9", "-mcpu");
3973 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
3974 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
3975 & rs6000_isa_flags_explicit))
3976 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
3977 were explicitly cleared. */
3978 error ("%qs incompatible with explicitly disabled options",
3981 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
3983 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
3984 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
3985 else if (TARGET_VSX)
3986 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
3987 else if (TARGET_POPCNTD)
3988 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
3989 else if (TARGET_DFP)
3990 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
3991 else if (TARGET_CMPB)
3992 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
3993 else if (TARGET_FPRND)
3994 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
3995 else if (TARGET_POPCNTB)
3996 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
3997 else if (TARGET_ALTIVEC)
3998 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4000 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4002 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4003 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4004 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4007 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4009 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4010 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4011 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4014 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4016 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4017 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4018 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4021 if (TARGET_P8_VECTOR && !TARGET_VSX)
4023 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4024 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4025 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4026 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4028 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4029 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4030 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4034 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4036 rs6000_isa_flags |= OPTION_MASK_VSX;
4037 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4041 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4043 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4044 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4045 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4048 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4049 silently turn off quad memory mode. */
4050 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4052 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4053 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4055 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4056 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4058 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4059 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4062 /* Non-atomic quad memory load/store are disabled for little endian, since
4063 the words are reversed, but atomic operations can still be done by
4064 swapping the words. */
4065 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4067 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4068 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4071 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4074 /* Assume if the user asked for normal quad memory instructions, they want
4075 the atomic versions as well, unless they explicity told us not to use quad
4076 word atomic instructions. */
4077 if (TARGET_QUAD_MEMORY
4078 && !TARGET_QUAD_MEMORY_ATOMIC
4079 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4080 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4082 /* If we can shrink-wrap the TOC register save separately, then use
4083 -msave-toc-indirect unless explicitly disabled. */
4084 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4085 && flag_shrink_wrap_separate
4086 && optimize_function_for_speed_p (cfun))
4087 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4089 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4090 generating power8 instructions. Power9 does not optimize power8 fusion
4092 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4094 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4095 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4097 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4100 /* Setting additional fusion flags turns on base fusion. */
4101 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4103 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4105 if (TARGET_P8_FUSION_SIGN)
4106 error ("%qs requires %qs", "-mpower8-fusion-sign",
4109 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4112 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4115 /* Power8 does not fuse sign extended loads with the addis. If we are
4116 optimizing at high levels for speed, convert a sign extended load into a
4117 zero extending load, and an explicit sign extension. */
4118 if (TARGET_P8_FUSION
4119 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4120 && optimize_function_for_speed_p (cfun)
4122 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4124 /* ISA 3.0 vector instructions include ISA 2.07. */
4125 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4127 /* We prefer to not mention undocumented options in
4128 error messages. However, if users have managed to select
4129 power9-vector without selecting power8-vector, they
4130 already know about undocumented flags. */
4131 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4132 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4133 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4134 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4136 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4137 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4138 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4142 /* OPTION_MASK_P9_VECTOR is explicit and
4143 OPTION_MASK_P8_VECTOR is not explicit. */
4144 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4145 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4149 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4150 support. If we only have ISA 2.06 support, and the user did not specify
4151 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4152 but we don't enable the full vectorization support */
4153 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4154 TARGET_ALLOW_MOVMISALIGN = 1;
4156 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4158 if (TARGET_ALLOW_MOVMISALIGN > 0
4159 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4160 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4162 TARGET_ALLOW_MOVMISALIGN = 0;
4165 /* Determine when unaligned vector accesses are permitted, and when
4166 they are preferred over masked Altivec loads. Note that if
4167 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4168 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4170 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4174 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4175 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4177 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4180 else if (!TARGET_ALLOW_MOVMISALIGN)
4182 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4183 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4184 "-mallow-movmisalign");
4186 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4190 /* Use long double size to select the appropriate long double. We use
4191 TYPE_PRECISION to differentiate the 3 different long double types. We map
4192 128 into the precision used for TFmode. */
4193 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4195 : FLOAT_PRECISION_TFmode);
4197 /* Set long double size before the IEEE 128-bit tests. */
4198 if (!global_options_set.x_rs6000_long_double_type_size)
4200 if (main_target_opt != NULL
4201 && (main_target_opt->x_rs6000_long_double_type_size
4202 != default_long_double_size))
4203 error ("target attribute or pragma changes %<long double%> size");
4205 rs6000_long_double_type_size = default_long_double_size;
4207 else if (rs6000_long_double_type_size == 128)
4208 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4209 else if (global_options_set.x_rs6000_ieeequad)
4211 if (global_options.x_rs6000_ieeequad)
4212 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4214 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4217 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4218 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4219 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4220 those systems will not pick up this default. Warn if the user changes the
4221 default unless -Wno-psabi. */
4222 if (!global_options_set.x_rs6000_ieeequad)
4223 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4227 if (global_options.x_rs6000_ieeequad
4228 && (!TARGET_POPCNTD || !TARGET_VSX))
4229 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4231 if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4233 static bool warned_change_long_double;
4234 if (!warned_change_long_double)
4236 warned_change_long_double = true;
4237 if (TARGET_IEEEQUAD)
4238 warning (OPT_Wpsabi, "Using IEEE extended precision "
4241 warning (OPT_Wpsabi, "Using IBM extended precision "
4247 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4248 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4249 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4250 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4251 the keyword as well as the type. */
4252 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4254 /* IEEE 128-bit floating point requires VSX support. */
4255 if (TARGET_FLOAT128_KEYWORD)
4259 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4260 error ("%qs requires VSX support", "%<-mfloat128%>");
4262 TARGET_FLOAT128_TYPE = 0;
4263 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4264 | OPTION_MASK_FLOAT128_HW);
4266 else if (!TARGET_FLOAT128_TYPE)
4268 TARGET_FLOAT128_TYPE = 1;
4269 warning (0, "The %<-mfloat128%> option may not be fully supported");
4273 /* Enable the __float128 keyword under Linux by default. */
4274 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4275 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4276 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4278 /* If we have are supporting the float128 type and full ISA 3.0 support,
4279 enable -mfloat128-hardware by default. However, don't enable the
4280 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4281 because sometimes the compiler wants to put things in an integer
4282 container, and if we don't have __int128 support, it is impossible. */
4283 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4284 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4285 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4286 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4288 if (TARGET_FLOAT128_HW
4289 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4291 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4292 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4294 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4297 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4299 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4300 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4302 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4305 /* Print the options after updating the defaults. */
4306 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4307 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4309 /* E500mc does "better" if we inline more aggressively. Respect the
4310 user's opinion, though. */
4311 if (rs6000_block_move_inline_limit == 0
4312 && (rs6000_tune == PROCESSOR_PPCE500MC
4313 || rs6000_tune == PROCESSOR_PPCE500MC64
4314 || rs6000_tune == PROCESSOR_PPCE5500
4315 || rs6000_tune == PROCESSOR_PPCE6500))
4316 rs6000_block_move_inline_limit = 128;
4318 /* store_one_arg depends on expand_block_move to handle at least the
4319 size of reg_parm_stack_space. */
4320 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4321 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4325 /* If the appropriate debug option is enabled, replace the target hooks
4326 with debug versions that call the real version and then prints
4327 debugging information. */
4328 if (TARGET_DEBUG_COST)
4330 targetm.rtx_costs = rs6000_debug_rtx_costs;
4331 targetm.address_cost = rs6000_debug_address_cost;
4332 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4335 if (TARGET_DEBUG_ADDR)
4337 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4338 targetm.legitimize_address = rs6000_debug_legitimize_address;
4339 rs6000_secondary_reload_class_ptr
4340 = rs6000_debug_secondary_reload_class;
4341 targetm.secondary_memory_needed
4342 = rs6000_debug_secondary_memory_needed;
4343 targetm.can_change_mode_class
4344 = rs6000_debug_can_change_mode_class;
4345 rs6000_preferred_reload_class_ptr
4346 = rs6000_debug_preferred_reload_class;
4347 rs6000_mode_dependent_address_ptr
4348 = rs6000_debug_mode_dependent_address;
4351 if (rs6000_veclibabi_name)
4353 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4354 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4357 error ("unknown vectorization library ABI type (%qs) for "
4358 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4364 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4365 target attribute or pragma which automatically enables both options,
4366 unless the altivec ABI was set. This is set by default for 64-bit, but
4368 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4370 TARGET_FLOAT128_TYPE = 0;
4371 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4372 | OPTION_MASK_FLOAT128_KEYWORD)
4373 & ~rs6000_isa_flags_explicit);
4376 /* Enable Altivec ABI for AIX -maltivec. */
4377 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4379 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4380 error ("target attribute or pragma changes AltiVec ABI");
4382 rs6000_altivec_abi = 1;
4385 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4386 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4387 be explicitly overridden in either case. */
4390 if (!global_options_set.x_rs6000_altivec_abi
4391 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4393 if (main_target_opt != NULL &&
4394 !main_target_opt->x_rs6000_altivec_abi)
4395 error ("target attribute or pragma changes AltiVec ABI");
4397 rs6000_altivec_abi = 1;
4401 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4402 So far, the only darwin64 targets are also MACH-O. */
4404 && DEFAULT_ABI == ABI_DARWIN
4407 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4408 error ("target attribute or pragma changes darwin64 ABI");
4411 rs6000_darwin64_abi = 1;
4412 /* Default to natural alignment, for better performance. */
4413 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4417 /* Place FP constants in the constant pool instead of TOC
4418 if section anchors enabled. */
4419 if (flag_section_anchors
4420 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4421 TARGET_NO_FP_IN_TOC = 1;
4423 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4424 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4426 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4427 SUBTARGET_OVERRIDE_OPTIONS;
4429 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4430 SUBSUBTARGET_OVERRIDE_OPTIONS;
4432 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4433 SUB3TARGET_OVERRIDE_OPTIONS;
4436 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4437 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4439 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4440 && rs6000_tune != PROCESSOR_POWER5
4441 && rs6000_tune != PROCESSOR_POWER6
4442 && rs6000_tune != PROCESSOR_POWER7
4443 && rs6000_tune != PROCESSOR_POWER8
4444 && rs6000_tune != PROCESSOR_POWER9
4445 && rs6000_tune != PROCESSOR_PPCA2
4446 && rs6000_tune != PROCESSOR_CELL
4447 && rs6000_tune != PROCESSOR_PPC476);
4448 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4449 || rs6000_tune == PROCESSOR_POWER5
4450 || rs6000_tune == PROCESSOR_POWER7
4451 || rs6000_tune == PROCESSOR_POWER8);
4452 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4453 || rs6000_tune == PROCESSOR_POWER5
4454 || rs6000_tune == PROCESSOR_POWER6
4455 || rs6000_tune == PROCESSOR_POWER7
4456 || rs6000_tune == PROCESSOR_POWER8
4457 || rs6000_tune == PROCESSOR_POWER9
4458 || rs6000_tune == PROCESSOR_PPCE500MC
4459 || rs6000_tune == PROCESSOR_PPCE500MC64
4460 || rs6000_tune == PROCESSOR_PPCE5500
4461 || rs6000_tune == PROCESSOR_PPCE6500);
4463 /* Allow debug switches to override the above settings. These are set to -1
4464 in rs6000.opt to indicate the user hasn't directly set the switch. */
4465 if (TARGET_ALWAYS_HINT >= 0)
4466 rs6000_always_hint = TARGET_ALWAYS_HINT;
4468 if (TARGET_SCHED_GROUPS >= 0)
4469 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4471 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4472 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4474 rs6000_sched_restricted_insns_priority
4475 = (rs6000_sched_groups ? 1 : 0);
4477 /* Handle -msched-costly-dep option. */
4478 rs6000_sched_costly_dep
4479 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4481 if (rs6000_sched_costly_dep_str)
4483 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4484 rs6000_sched_costly_dep = no_dep_costly;
4485 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4486 rs6000_sched_costly_dep = all_deps_costly;
4487 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4488 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4489 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4490 rs6000_sched_costly_dep = store_to_load_dep_costly;
4492 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4493 atoi (rs6000_sched_costly_dep_str));
4496 /* Handle -minsert-sched-nops option. */
4497 rs6000_sched_insert_nops
4498 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4500 if (rs6000_sched_insert_nops_str)
4502 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4503 rs6000_sched_insert_nops = sched_finish_none;
4504 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4505 rs6000_sched_insert_nops = sched_finish_pad_groups;
4506 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4507 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4509 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4510 atoi (rs6000_sched_insert_nops_str));
4513 /* Handle stack protector */
4514 if (!global_options_set.x_rs6000_stack_protector_guard)
4515 #ifdef TARGET_THREAD_SSP_OFFSET
4516 rs6000_stack_protector_guard = SSP_TLS;
4518 rs6000_stack_protector_guard = SSP_GLOBAL;
4521 #ifdef TARGET_THREAD_SSP_OFFSET
4522 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4523 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4526 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4529 const char *str = rs6000_stack_protector_guard_offset_str;
4532 long offset = strtol (str, &endp, 0);
4533 if (!*str || *endp || errno)
4534 error ("%qs is not a valid number in %qs", str,
4535 "-mstack-protector-guard-offset=");
4537 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4538 || (TARGET_64BIT && (offset & 3)))
4539 error ("%qs is not a valid offset in %qs", str,
4540 "-mstack-protector-guard-offset=");
4542 rs6000_stack_protector_guard_offset = offset;
4545 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4547 const char *str = rs6000_stack_protector_guard_reg_str;
4548 int reg = decode_reg_name (str);
4550 if (!IN_RANGE (reg, 1, 31))
4551 error ("%qs is not a valid base register in %qs", str,
4552 "-mstack-protector-guard-reg=");
4554 rs6000_stack_protector_guard_reg = reg;
4557 if (rs6000_stack_protector_guard == SSP_TLS
4558 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4559 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4563 #ifdef TARGET_REGNAMES
4564 /* If the user desires alternate register names, copy in the
4565 alternate names now. */
4566 if (TARGET_REGNAMES)
4567 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4570 /* Set aix_struct_return last, after the ABI is determined.
4571 If -maix-struct-return or -msvr4-struct-return was explicitly
4572 used, don't override with the ABI default. */
4573 if (!global_options_set.x_aix_struct_return)
4574 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4577 /* IBM XL compiler defaults to unsigned bitfields. */
4578 if (TARGET_XL_COMPAT)
4579 flag_signed_bitfields = 0;
4582 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4583 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4585 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4587 /* We can only guarantee the availability of DI pseudo-ops when
4588 assembling for 64-bit targets. */
4591 targetm.asm_out.aligned_op.di = NULL;
4592 targetm.asm_out.unaligned_op.di = NULL;
4596 /* Set branch target alignment, if not optimizing for size. */
4599 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4600 aligned 8byte to avoid misprediction by the branch predictor. */
4601 if (rs6000_tune == PROCESSOR_TITAN
4602 || rs6000_tune == PROCESSOR_CELL)
4604 if (flag_align_functions && !str_align_functions)
4605 str_align_functions = "8";
4606 if (flag_align_jumps && !str_align_jumps)
4607 str_align_jumps = "8";
4608 if (flag_align_loops && !str_align_loops)
4609 str_align_loops = "8";
4611 if (rs6000_align_branch_targets)
4613 if (flag_align_functions && !str_align_functions)
4614 str_align_functions = "16";
4615 if (flag_align_jumps && !str_align_jumps)
4616 str_align_jumps = "16";
4617 if (flag_align_loops && !str_align_loops)
4619 can_override_loop_align = 1;
4620 str_align_loops = "16";
4624 if (flag_align_jumps && !str_align_jumps)
4625 str_align_jumps = "16";
4626 if (flag_align_loops && !str_align_loops)
4627 str_align_loops = "16";
4630 /* Arrange to save and restore machine status around nested functions. */
4631 init_machine_status = rs6000_init_machine_status;
4633 /* We should always be splitting complex arguments, but we can't break
4634 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4635 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4636 targetm.calls.split_complex_arg = NULL;
4638 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4639 if (DEFAULT_ABI == ABI_AIX)
4640 targetm.calls.custom_function_descriptors = 0;
4643 /* Initialize rs6000_cost with the appropriate target costs. */
4645 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4647 switch (rs6000_tune)
4649 case PROCESSOR_RS64A:
4650 rs6000_cost = &rs64a_cost;
4653 case PROCESSOR_MPCCORE:
4654 rs6000_cost = &mpccore_cost;
4657 case PROCESSOR_PPC403:
4658 rs6000_cost = &ppc403_cost;
4661 case PROCESSOR_PPC405:
4662 rs6000_cost = &ppc405_cost;
4665 case PROCESSOR_PPC440:
4666 rs6000_cost = &ppc440_cost;
4669 case PROCESSOR_PPC476:
4670 rs6000_cost = &ppc476_cost;
4673 case PROCESSOR_PPC601:
4674 rs6000_cost = &ppc601_cost;
4677 case PROCESSOR_PPC603:
4678 rs6000_cost = &ppc603_cost;
4681 case PROCESSOR_PPC604:
4682 rs6000_cost = &ppc604_cost;
4685 case PROCESSOR_PPC604e:
4686 rs6000_cost = &ppc604e_cost;
4689 case PROCESSOR_PPC620:
4690 rs6000_cost = &ppc620_cost;
4693 case PROCESSOR_PPC630:
4694 rs6000_cost = &ppc630_cost;
4697 case PROCESSOR_CELL:
4698 rs6000_cost = &ppccell_cost;
4701 case PROCESSOR_PPC750:
4702 case PROCESSOR_PPC7400:
4703 rs6000_cost = &ppc750_cost;
4706 case PROCESSOR_PPC7450:
4707 rs6000_cost = &ppc7450_cost;
4710 case PROCESSOR_PPC8540:
4711 case PROCESSOR_PPC8548:
4712 rs6000_cost = &ppc8540_cost;
4715 case PROCESSOR_PPCE300C2:
4716 case PROCESSOR_PPCE300C3:
4717 rs6000_cost = &ppce300c2c3_cost;
4720 case PROCESSOR_PPCE500MC:
4721 rs6000_cost = &ppce500mc_cost;
4724 case PROCESSOR_PPCE500MC64:
4725 rs6000_cost = &ppce500mc64_cost;
4728 case PROCESSOR_PPCE5500:
4729 rs6000_cost = &ppce5500_cost;
4732 case PROCESSOR_PPCE6500:
4733 rs6000_cost = &ppce6500_cost;
4736 case PROCESSOR_TITAN:
4737 rs6000_cost = &titan_cost;
4740 case PROCESSOR_POWER4:
4741 case PROCESSOR_POWER5:
4742 rs6000_cost = &power4_cost;
4745 case PROCESSOR_POWER6:
4746 rs6000_cost = &power6_cost;
4749 case PROCESSOR_POWER7:
4750 rs6000_cost = &power7_cost;
4753 case PROCESSOR_POWER8:
4754 rs6000_cost = &power8_cost;
4757 case PROCESSOR_POWER9:
4758 rs6000_cost = &power9_cost;
4761 case PROCESSOR_PPCA2:
4762 rs6000_cost = &ppca2_cost;
4771 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4772 rs6000_cost->simultaneous_prefetches,
4773 global_options.x_param_values,
4774 global_options_set.x_param_values);
4775 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4776 global_options.x_param_values,
4777 global_options_set.x_param_values);
4778 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4779 rs6000_cost->cache_line_size,
4780 global_options.x_param_values,
4781 global_options_set.x_param_values);
4782 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4783 global_options.x_param_values,
4784 global_options_set.x_param_values);
4786 /* Increase loop peeling limits based on performance analysis. */
4787 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4788 global_options.x_param_values,
4789 global_options_set.x_param_values);
4790 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4791 global_options.x_param_values,
4792 global_options_set.x_param_values);
4794 /* Use the 'model' -fsched-pressure algorithm by default. */
4795 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4796 SCHED_PRESSURE_MODEL,
4797 global_options.x_param_values,
4798 global_options_set.x_param_values);
4800 /* If using typedef char *va_list, signal that
4801 __builtin_va_start (&ap, 0) can be optimized to
4802 ap = __builtin_next_arg (0). */
4803 if (DEFAULT_ABI != ABI_V4)
4804 targetm.expand_builtin_va_start = NULL;
4807 /* If not explicitly specified via option, decide whether to generate indexed
4808 load/store instructions. A value of -1 indicates that the
4809 initial value of this variable has not been overwritten. During
4810 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4811 if (TARGET_AVOID_XFORM == -1)
4812 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4813 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4814 need indexed accesses and the type used is the scalar type of the element
4815 being loaded or stored. */
4816 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4817 && !TARGET_ALTIVEC);
4819 /* Set the -mrecip options. */
4820 if (rs6000_recip_name)
4822 char *p = ASTRDUP (rs6000_recip_name);
4824 unsigned int mask, i;
4827 while ((q = strtok (p, ",")) != NULL)
4838 if (!strcmp (q, "default"))
4839 mask = ((TARGET_RECIP_PRECISION)
4840 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4843 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4844 if (!strcmp (q, recip_options[i].string))
4846 mask = recip_options[i].mask;
4850 if (i == ARRAY_SIZE (recip_options))
4852 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4860 rs6000_recip_control &= ~mask;
4862 rs6000_recip_control |= mask;
4866 /* Set the builtin mask of the various options used that could affect which
4867 builtins were used. In the past we used target_flags, but we've run out
4868 of bits, and some options are no longer in target_flags. */
4869 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4870 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4871 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4872 rs6000_builtin_mask);
4874 /* Initialize all of the registers. */
4875 rs6000_init_hard_regno_mode_ok (global_init_p);
4877 /* Save the initial options in case the user does function specific options */
4879 target_option_default_node = target_option_current_node
4880 = build_target_option_node (&global_options);
4882 /* If not explicitly specified via option, decide whether to generate the
4883 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4884 if (TARGET_LINK_STACK == -1)
4885 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4887 /* Deprecate use of -mno-speculate-indirect-jumps. */
4888 if (!rs6000_speculate_indirect_jumps)
4889 warning (0, "%qs is deprecated and not recommended in any circumstances",
4890 "-mno-speculate-indirect-jumps");
4895 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4896 define the target cpu type. */
4899 rs6000_option_override (void)
4901 (void) rs6000_option_override_internal (true);
4905 /* Implement targetm.vectorize.builtin_mask_for_load. */
4907 rs6000_builtin_mask_for_load (void)
4909 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4910 if ((TARGET_ALTIVEC && !TARGET_VSX)
4911 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4912 return altivec_builtin_mask_for_load;
4917 /* Implement LOOP_ALIGN. */
4919 rs6000_loop_align (rtx label)
4924 /* Don't override loop alignment if -falign-loops was specified. */
4925 if (!can_override_loop_align)
4928 bb = BLOCK_FOR_INSN (label);
4929 ninsns = num_loop_insns(bb->loop_father);
4931 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4932 if (ninsns > 4 && ninsns <= 8
4933 && (rs6000_tune == PROCESSOR_POWER4
4934 || rs6000_tune == PROCESSOR_POWER5
4935 || rs6000_tune == PROCESSOR_POWER6
4936 || rs6000_tune == PROCESSOR_POWER7
4937 || rs6000_tune == PROCESSOR_POWER8))
4938 return align_flags (5);
4943 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4944 after applying N number of iterations. This routine does not determine
4945 how may iterations are required to reach desired alignment. */
4948 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4955 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4958 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4968 /* Assuming that all other types are naturally aligned. CHECKME! */
4973 /* Return true if the vector misalignment factor is supported by the
4976 rs6000_builtin_support_vector_misalignment (machine_mode mode,
4983 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4986 /* Return if movmisalign pattern is not supported for this mode. */
4987 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
4990 if (misalignment == -1)
4992 /* Misalignment factor is unknown at compile time but we know
4993 it's word aligned. */
4994 if (rs6000_vector_alignment_reachable (type, is_packed))
4996 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
4998 if (element_size == 64 || element_size == 32)
5005 /* VSX supports word-aligned vector. */
5006 if (misalignment % 4 == 0)
5012 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5014 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5015 tree vectype, int misalign)
5020 switch (type_of_cost)
5030 case cond_branch_not_taken:
5039 case vec_promote_demote:
5045 case cond_branch_taken:
5048 case unaligned_load:
5049 case vector_gather_load:
5050 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5053 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5055 elements = TYPE_VECTOR_SUBPARTS (vectype);
5057 /* Double word aligned. */
5065 /* Double word aligned. */
5069 /* Unknown misalignment. */
5082 /* Misaligned loads are not supported. */
5087 case unaligned_store:
5088 case vector_scatter_store:
5089 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5092 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5094 elements = TYPE_VECTOR_SUBPARTS (vectype);
5096 /* Double word aligned. */
5104 /* Double word aligned. */
5108 /* Unknown misalignment. */
5121 /* Misaligned stores are not supported. */
5127 /* This is a rough approximation assuming non-constant elements
5128 constructed into a vector via element insertion. FIXME:
5129 vec_construct is not granular enough for uniformly good
5130 decisions. If the initialization is a splat, this is
5131 cheaper than we estimate. Improve this someday. */
5132 elem_type = TREE_TYPE (vectype);
5133 /* 32-bit vectors loaded into registers are stored as double
5134 precision, so we need 2 permutes, 2 converts, and 1 merge
5135 to construct a vector of short floats from them. */
5136 if (SCALAR_FLOAT_TYPE_P (elem_type)
5137 && TYPE_PRECISION (elem_type) == 32)
5139 /* On POWER9, integer vector types are built up in GPRs and then
5140 use a direct move (2 cycles). For POWER8 this is even worse,
5141 as we need two direct moves and a merge, and the direct moves
5143 else if (INTEGRAL_TYPE_P (elem_type))
5145 if (TARGET_P9_VECTOR)
5146 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5148 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5151 /* V2DFmode doesn't need a direct move. */
5159 /* Implement targetm.vectorize.preferred_simd_mode. */
5162 rs6000_preferred_simd_mode (scalar_mode mode)
5171 if (TARGET_ALTIVEC || TARGET_VSX)
5191 typedef struct _rs6000_cost_data
5193 struct loop *loop_info;
5197 /* Test for likely overcommitment of vector hardware resources. If a
5198 loop iteration is relatively large, and too large a percentage of
5199 instructions in the loop are vectorized, the cost model may not
5200 adequately reflect delays from unavailable vector resources.
5201 Penalize the loop body cost for this case. */
5204 rs6000_density_test (rs6000_cost_data *data)
5206 const int DENSITY_PCT_THRESHOLD = 85;
5207 const int DENSITY_SIZE_THRESHOLD = 70;
5208 const int DENSITY_PENALTY = 10;
5209 struct loop *loop = data->loop_info;
5210 basic_block *bbs = get_loop_body (loop);
5211 int nbbs = loop->num_nodes;
5212 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5213 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5216 for (i = 0; i < nbbs; i++)
5218 basic_block bb = bbs[i];
5219 gimple_stmt_iterator gsi;
5221 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5223 gimple *stmt = gsi_stmt (gsi);
5224 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5226 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5227 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5233 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5235 if (density_pct > DENSITY_PCT_THRESHOLD
5236 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5238 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5239 if (dump_enabled_p ())
5240 dump_printf_loc (MSG_NOTE, vect_location,
5241 "density %d%%, cost %d exceeds threshold, penalizing "
5242 "loop body cost by %d%%", density_pct,
5243 vec_cost + not_vec_cost, DENSITY_PENALTY);
5247 /* Implement targetm.vectorize.init_cost. */
5249 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5250 instruction is needed by the vectorization. */
5251 static bool rs6000_vect_nonmem;
5254 rs6000_init_cost (struct loop *loop_info)
5256 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5257 data->loop_info = loop_info;
5258 data->cost[vect_prologue] = 0;
5259 data->cost[vect_body] = 0;
5260 data->cost[vect_epilogue] = 0;
5261 rs6000_vect_nonmem = false;
5265 /* Implement targetm.vectorize.add_stmt_cost. */
5268 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5269 struct _stmt_vec_info *stmt_info, int misalign,
5270 enum vect_cost_model_location where)
5272 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5273 unsigned retval = 0;
5275 if (flag_vect_cost_model)
5277 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5278 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5280 /* Statements in an inner loop relative to the loop being
5281 vectorized are weighted more heavily. The value here is
5282 arbitrary and could potentially be improved with analysis. */
5283 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5284 count *= 50; /* FIXME. */
5286 retval = (unsigned) (count * stmt_cost);
5287 cost_data->cost[where] += retval;
5289 /* Check whether we're doing something other than just a copy loop.
5290 Not all such loops may be profitably vectorized; see
5291 rs6000_finish_cost. */
5292 if ((kind == vec_to_scalar || kind == vec_perm
5293 || kind == vec_promote_demote || kind == vec_construct
5294 || kind == scalar_to_vec)
5295 || (where == vect_body && kind == vector_stmt))
5296 rs6000_vect_nonmem = true;
5302 /* Implement targetm.vectorize.finish_cost. */
5305 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5306 unsigned *body_cost, unsigned *epilogue_cost)
5308 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5310 if (cost_data->loop_info)
5311 rs6000_density_test (cost_data);
5313 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5314 that require versioning for any reason. The vectorization is at
5315 best a wash inside the loop, and the versioning checks make
5316 profitability highly unlikely and potentially quite harmful. */
5317 if (cost_data->loop_info)
5319 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5320 if (!rs6000_vect_nonmem
5321 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5322 && LOOP_REQUIRES_VERSIONING (vec_info))
5323 cost_data->cost[vect_body] += 10000;
5326 *prologue_cost = cost_data->cost[vect_prologue];
5327 *body_cost = cost_data->cost[vect_body];
5328 *epilogue_cost = cost_data->cost[vect_epilogue];
5331 /* Implement targetm.vectorize.destroy_cost_data. */
5334 rs6000_destroy_cost_data (void *data)
5339 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5340 library with vectorized intrinsics. */
5343 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5347 const char *suffix = NULL;
5348 tree fntype, new_fndecl, bdecl = NULL_TREE;
5351 machine_mode el_mode, in_mode;
5354 /* Libmass is suitable for unsafe math only as it does not correctly support
5355 parts of IEEE with the required precision such as denormals. Only support
5356 it if we have VSX to use the simd d2 or f4 functions.
5357 XXX: Add variable length support. */
5358 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5361 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5362 n = TYPE_VECTOR_SUBPARTS (type_out);
5363 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5364 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5365 if (el_mode != in_mode
5401 if (el_mode == DFmode && n == 2)
5403 bdecl = mathfn_built_in (double_type_node, fn);
5404 suffix = "d2"; /* pow -> powd2 */
5406 else if (el_mode == SFmode && n == 4)
5408 bdecl = mathfn_built_in (float_type_node, fn);
5409 suffix = "4"; /* powf -> powf4 */
5421 gcc_assert (suffix != NULL);
5422 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5426 strcpy (name, bname + sizeof ("__builtin_") - 1);
5427 strcat (name, suffix);
5430 fntype = build_function_type_list (type_out, type_in, NULL);
5431 else if (n_args == 2)
5432 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5436 /* Build a function declaration for the vectorized function. */
5437 new_fndecl = build_decl (BUILTINS_LOCATION,
5438 FUNCTION_DECL, get_identifier (name), fntype);
5439 TREE_PUBLIC (new_fndecl) = 1;
5440 DECL_EXTERNAL (new_fndecl) = 1;
5441 DECL_IS_NOVOPS (new_fndecl) = 1;
5442 TREE_READONLY (new_fndecl) = 1;
5447 /* Returns a function decl for a vectorized version of the builtin function
5448 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5449 if it is not available. */
5452 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5455 machine_mode in_mode, out_mode;
5458 if (TARGET_DEBUG_BUILTIN)
5459 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5460 combined_fn_name (combined_fn (fn)),
5461 GET_MODE_NAME (TYPE_MODE (type_out)),
5462 GET_MODE_NAME (TYPE_MODE (type_in)));
5464 if (TREE_CODE (type_out) != VECTOR_TYPE
5465 || TREE_CODE (type_in) != VECTOR_TYPE)
5468 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5469 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5470 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5471 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5476 if (VECTOR_UNIT_VSX_P (V2DFmode)
5477 && out_mode == DFmode && out_n == 2
5478 && in_mode == DFmode && in_n == 2)
5479 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5480 if (VECTOR_UNIT_VSX_P (V4SFmode)
5481 && out_mode == SFmode && out_n == 4
5482 && in_mode == SFmode && in_n == 4)
5483 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5484 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5485 && out_mode == SFmode && out_n == 4
5486 && in_mode == SFmode && in_n == 4)
5487 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5490 if (VECTOR_UNIT_VSX_P (V2DFmode)
5491 && out_mode == DFmode && out_n == 2
5492 && in_mode == DFmode && in_n == 2)
5493 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5494 if (VECTOR_UNIT_VSX_P (V4SFmode)
5495 && out_mode == SFmode && out_n == 4
5496 && in_mode == SFmode && in_n == 4)
5497 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5498 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5499 && out_mode == SFmode && out_n == 4
5500 && in_mode == SFmode && in_n == 4)
5501 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5504 if (VECTOR_UNIT_VSX_P (V2DFmode)
5505 && out_mode == DFmode && out_n == 2
5506 && in_mode == DFmode && in_n == 2)
5507 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5508 if (VECTOR_UNIT_VSX_P (V4SFmode)
5509 && out_mode == SFmode && out_n == 4
5510 && in_mode == SFmode && in_n == 4)
5511 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5512 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5513 && out_mode == SFmode && out_n == 4
5514 && in_mode == SFmode && in_n == 4)
5515 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5518 if (VECTOR_UNIT_VSX_P (V2DFmode)
5519 && out_mode == DFmode && out_n == 2
5520 && in_mode == DFmode && in_n == 2)
5521 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5522 if (VECTOR_UNIT_VSX_P (V4SFmode)
5523 && out_mode == SFmode && out_n == 4
5524 && in_mode == SFmode && in_n == 4)
5525 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5526 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5527 && out_mode == SFmode && out_n == 4
5528 && in_mode == SFmode && in_n == 4)
5529 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5532 if (VECTOR_UNIT_VSX_P (V2DFmode)
5533 && out_mode == DFmode && out_n == 2
5534 && in_mode == DFmode && in_n == 2)
5535 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5536 if (VECTOR_UNIT_VSX_P (V4SFmode)
5537 && out_mode == SFmode && out_n == 4
5538 && in_mode == SFmode && in_n == 4)
5539 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5540 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5541 && out_mode == SFmode && out_n == 4
5542 && in_mode == SFmode && in_n == 4)
5543 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5546 if (VECTOR_UNIT_VSX_P (V2DFmode)
5547 && flag_unsafe_math_optimizations
5548 && out_mode == DFmode && out_n == 2
5549 && in_mode == DFmode && in_n == 2)
5550 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5551 if (VECTOR_UNIT_VSX_P (V4SFmode)
5552 && flag_unsafe_math_optimizations
5553 && out_mode == SFmode && out_n == 4
5554 && in_mode == SFmode && in_n == 4)
5555 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5558 if (VECTOR_UNIT_VSX_P (V2DFmode)
5559 && !flag_trapping_math
5560 && out_mode == DFmode && out_n == 2
5561 && in_mode == DFmode && in_n == 2)
5562 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5563 if (VECTOR_UNIT_VSX_P (V4SFmode)
5564 && !flag_trapping_math
5565 && out_mode == SFmode && out_n == 4
5566 && in_mode == SFmode && in_n == 4)
5567 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5573 /* Generate calls to libmass if appropriate. */
5574 if (rs6000_veclib_handler)
5575 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5580 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5583 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5586 machine_mode in_mode, out_mode;
5589 if (TARGET_DEBUG_BUILTIN)
5590 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5591 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5592 GET_MODE_NAME (TYPE_MODE (type_out)),
5593 GET_MODE_NAME (TYPE_MODE (type_in)));
5595 if (TREE_CODE (type_out) != VECTOR_TYPE
5596 || TREE_CODE (type_in) != VECTOR_TYPE)
5599 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5600 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5601 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5602 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5604 enum rs6000_builtins fn
5605 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5608 case RS6000_BUILTIN_RSQRTF:
5609 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5610 && out_mode == SFmode && out_n == 4
5611 && in_mode == SFmode && in_n == 4)
5612 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5614 case RS6000_BUILTIN_RSQRT:
5615 if (VECTOR_UNIT_VSX_P (V2DFmode)
5616 && out_mode == DFmode && out_n == 2
5617 && in_mode == DFmode && in_n == 2)
5618 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5620 case RS6000_BUILTIN_RECIPF:
5621 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5622 && out_mode == SFmode && out_n == 4
5623 && in_mode == SFmode && in_n == 4)
5624 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5626 case RS6000_BUILTIN_RECIP:
5627 if (VECTOR_UNIT_VSX_P (V2DFmode)
5628 && out_mode == DFmode && out_n == 2
5629 && in_mode == DFmode && in_n == 2)
5630 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5638 /* Default CPU string for rs6000*_file_start functions. */
5639 static const char *rs6000_default_cpu;
5641 /* Do anything needed at the start of the asm file. */
5644 rs6000_file_start (void)
5647 const char *start = buffer;
5648 FILE *file = asm_out_file;
5650 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5652 default_file_start ();
5654 if (flag_verbose_asm)
5656 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5658 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5660 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5664 if (global_options_set.x_rs6000_cpu_index)
5666 fprintf (file, "%s -mcpu=%s", start,
5667 processor_target_table[rs6000_cpu_index].name);
5671 if (global_options_set.x_rs6000_tune_index)
5673 fprintf (file, "%s -mtune=%s", start,
5674 processor_target_table[rs6000_tune_index].name);
5678 if (PPC405_ERRATUM77)
5680 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5684 #ifdef USING_ELFOS_H
5685 switch (rs6000_sdata)
5687 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5688 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5689 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5690 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5693 if (rs6000_sdata && g_switch_value)
5695 fprintf (file, "%s -G %d", start,
5705 #ifdef USING_ELFOS_H
5706 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5707 && !global_options_set.x_rs6000_cpu_index)
5709 fputs ("\t.machine ", asm_out_file);
5710 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
5711 fputs ("power9\n", asm_out_file);
5712 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
5713 fputs ("power8\n", asm_out_file);
5714 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
5715 fputs ("power7\n", asm_out_file);
5716 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
5717 fputs ("power6\n", asm_out_file);
5718 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
5719 fputs ("power5\n", asm_out_file);
5720 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
5721 fputs ("power4\n", asm_out_file);
5722 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5723 fputs ("ppc64\n", asm_out_file);
5725 fputs ("ppc\n", asm_out_file);
5729 if (DEFAULT_ABI == ABI_ELFv2)
5730 fprintf (file, "\t.abiversion 2\n");
5734 /* Return nonzero if this function is known to have a null epilogue. */
5737 direct_return (void)
5739 if (reload_completed)
5741 rs6000_stack_t *info = rs6000_stack_info ();
5743 if (info->first_gp_reg_save == 32
5744 && info->first_fp_reg_save == 64
5745 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5746 && ! info->lr_save_p
5747 && ! info->cr_save_p
5748 && info->vrsave_size == 0
5756 /* Helper for num_insns_constant. Calculate number of instructions to
5757 load VALUE to a single gpr using combinations of addi, addis, ori,
5758 oris and sldi instructions. */
5761 num_insns_constant_gpr (HOST_WIDE_INT value)
5763 /* signed constant loadable with addi */
5764 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5767 /* constant loadable with addis */
5768 else if ((value & 0xffff) == 0
5769 && (value >> 31 == -1 || value >> 31 == 0))
5772 else if (TARGET_POWERPC64)
5774 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5775 HOST_WIDE_INT high = value >> 31;
5777 if (high == 0 || high == -1)
5783 return num_insns_constant_gpr (high) + 1;
5785 return num_insns_constant_gpr (low) + 1;
5787 return (num_insns_constant_gpr (high)
5788 + num_insns_constant_gpr (low) + 1);
5795 /* Helper for num_insns_constant. Allow constants formed by the
5796 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5797 and handle modes that require multiple gprs. */
5800 num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
5802 int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5806 HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
5807 int insns = num_insns_constant_gpr (low);
5809 /* We won't get more than 2 from num_insns_constant_gpr
5810 except when TARGET_POWERPC64 and mode is DImode or
5811 wider, so the register mode must be DImode. */
5812 && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5815 value >>= BITS_PER_WORD;
5820 /* Return the number of instructions it takes to form a constant in as
5821 many gprs are needed for MODE. */
5824 num_insns_constant (rtx op, machine_mode mode)
5828 switch (GET_CODE (op))
5834 case CONST_WIDE_INT:
5837 for (int i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5838 insns += num_insns_constant_multi (CONST_WIDE_INT_ELT (op, i),
5845 const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
5847 if (mode == SFmode || mode == SDmode)
5852 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv, l);
5854 REAL_VALUE_TO_TARGET_SINGLE (*rv, l);
5855 /* See the first define_split in rs6000.md handling a
5856 const_double_operand. */
5860 else if (mode == DFmode || mode == DDmode)
5865 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv, l);
5867 REAL_VALUE_TO_TARGET_DOUBLE (*rv, l);
5869 /* See the second (32-bit) and third (64-bit) define_split
5870 in rs6000.md handling a const_double_operand. */
5871 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 1] << 32;
5872 val |= l[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffffUL;
5875 else if (mode == TFmode || mode == TDmode
5876 || mode == KFmode || mode == IFmode)
5882 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv, l);
5884 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv, l);
5886 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 3] << 32;
5887 val |= l[WORDS_BIG_ENDIAN ? 1 : 2] & 0xffffffffUL;
5888 insns = num_insns_constant_multi (val, DImode);
5889 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 2 : 1] << 32;
5890 val |= l[WORDS_BIG_ENDIAN ? 3 : 0] & 0xffffffffUL;
5891 insns += num_insns_constant_multi (val, DImode);
5903 return num_insns_constant_multi (val, mode);
5906 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5907 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5908 corresponding element of the vector, but for V4SFmode, the
5909 corresponding "float" is interpreted as an SImode integer. */
5912 const_vector_elt_as_int (rtx op, unsigned int elt)
5916 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5917 gcc_assert (GET_MODE (op) != V2DImode
5918 && GET_MODE (op) != V2DFmode);
5920 tmp = CONST_VECTOR_ELT (op, elt);
5921 if (GET_MODE (op) == V4SFmode)
5922 tmp = gen_lowpart (SImode, tmp);
5923 return INTVAL (tmp);
5926 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5927 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5928 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5929 all items are set to the same value and contain COPIES replicas of the
5930 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5931 operand and the others are set to the value of the operand's msb. */
5934 vspltis_constant (rtx op, unsigned step, unsigned copies)
5936 machine_mode mode = GET_MODE (op);
5937 machine_mode inner = GET_MODE_INNER (mode);
5945 HOST_WIDE_INT splat_val;
5946 HOST_WIDE_INT msb_val;
5948 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5951 nunits = GET_MODE_NUNITS (mode);
5952 bitsize = GET_MODE_BITSIZE (inner);
5953 mask = GET_MODE_MASK (inner);
5955 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5957 msb_val = val >= 0 ? 0 : -1;
5959 /* Construct the value to be splatted, if possible. If not, return 0. */
5960 for (i = 2; i <= copies; i *= 2)
5962 HOST_WIDE_INT small_val;
5964 small_val = splat_val >> bitsize;
5966 if (splat_val != ((HOST_WIDE_INT)
5967 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5968 | (small_val & mask)))
5970 splat_val = small_val;
5973 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5974 if (EASY_VECTOR_15 (splat_val))
5977 /* Also check if we can splat, and then add the result to itself. Do so if
5978 the value is positive, of if the splat instruction is using OP's mode;
5979 for splat_val < 0, the splat and the add should use the same mode. */
5980 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
5981 && (splat_val >= 0 || (step == 1 && copies == 1)))
5984 /* Also check if are loading up the most significant bit which can be done by
5985 loading up -1 and shifting the value left by -1. */
5986 else if (EASY_VECTOR_MSB (splat_val, inner))
5992 /* Check if VAL is present in every STEP-th element, and the
5993 other elements are filled with its most significant bit. */
5994 for (i = 1; i < nunits; ++i)
5996 HOST_WIDE_INT desired_val;
5997 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
5998 if ((i & (step - 1)) == 0)
6001 desired_val = msb_val;
6003 if (desired_val != const_vector_elt_as_int (op, elt))
6010 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6011 instruction, filling in the bottom elements with 0 or -1.
6013 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6014 for the number of zeroes to shift in, or negative for the number of 0xff
6017 OP is a CONST_VECTOR. */
6020 vspltis_shifted (rtx op)
6022 machine_mode mode = GET_MODE (op);
6023 machine_mode inner = GET_MODE_INNER (mode);
6031 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6034 /* We need to create pseudo registers to do the shift, so don't recognize
6035 shift vector constants after reload. */
6036 if (!can_create_pseudo_p ())
6039 nunits = GET_MODE_NUNITS (mode);
6040 mask = GET_MODE_MASK (inner);
6042 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6044 /* Check if the value can really be the operand of a vspltis[bhw]. */
6045 if (EASY_VECTOR_15 (val))
6048 /* Also check if we are loading up the most significant bit which can be done
6049 by loading up -1 and shifting the value left by -1. */
6050 else if (EASY_VECTOR_MSB (val, inner))
6056 /* Check if VAL is present in every STEP-th element until we find elements
6057 that are 0 or all 1 bits. */
6058 for (i = 1; i < nunits; ++i)
6060 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6061 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6063 /* If the value isn't the splat value, check for the remaining elements
6069 for (j = i+1; j < nunits; ++j)
6071 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6072 if (const_vector_elt_as_int (op, elt2) != 0)
6076 return (nunits - i) * GET_MODE_SIZE (inner);
6079 else if ((elt_val & mask) == mask)
6081 for (j = i+1; j < nunits; ++j)
6083 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6084 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6088 return -((nunits - i) * GET_MODE_SIZE (inner));
6096 /* If all elements are equal, we don't need to do VLSDOI. */
6101 /* Return true if OP is of the given MODE and can be synthesized
6102 with a vspltisb, vspltish or vspltisw. */
6105 easy_altivec_constant (rtx op, machine_mode mode)
6107 unsigned step, copies;
6109 if (mode == VOIDmode)
6110 mode = GET_MODE (op);
6111 else if (mode != GET_MODE (op))
6114 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6116 if (mode == V2DFmode)
6117 return zero_constant (op, mode);
6119 else if (mode == V2DImode)
6121 if (!CONST_INT_P (CONST_VECTOR_ELT (op, 0))
6122 || !CONST_INT_P (CONST_VECTOR_ELT (op, 1)))
6125 if (zero_constant (op, mode))
6128 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6129 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6135 /* V1TImode is a special container for TImode. Ignore for now. */
6136 else if (mode == V1TImode)
6139 /* Start with a vspltisw. */
6140 step = GET_MODE_NUNITS (mode) / 4;
6143 if (vspltis_constant (op, step, copies))
6146 /* Then try with a vspltish. */
6152 if (vspltis_constant (op, step, copies))
6155 /* And finally a vspltisb. */
6161 if (vspltis_constant (op, step, copies))
6164 if (vspltis_shifted (op) != 0)
6170 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6171 result is OP. Abort if it is not possible. */
6174 gen_easy_altivec_constant (rtx op)
6176 machine_mode mode = GET_MODE (op);
6177 int nunits = GET_MODE_NUNITS (mode);
6178 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6179 unsigned step = nunits / 4;
6180 unsigned copies = 1;
6182 /* Start with a vspltisw. */
6183 if (vspltis_constant (op, step, copies))
6184 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6186 /* Then try with a vspltish. */
6192 if (vspltis_constant (op, step, copies))
6193 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6195 /* And finally a vspltisb. */
6201 if (vspltis_constant (op, step, copies))
6202 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6207 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6208 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6210 Return the number of instructions needed (1 or 2) into the address pointed
6213 Return the constant that is being split via CONSTANT_PTR. */
6216 xxspltib_constant_p (rtx op,
6221 size_t nunits = GET_MODE_NUNITS (mode);
6223 HOST_WIDE_INT value;
6226 /* Set the returned values to out of bound values. */
6227 *num_insns_ptr = -1;
6228 *constant_ptr = 256;
6230 if (!TARGET_P9_VECTOR)
6233 if (mode == VOIDmode)
6234 mode = GET_MODE (op);
6236 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6239 /* Handle (vec_duplicate <constant>). */
6240 if (GET_CODE (op) == VEC_DUPLICATE)
6242 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6243 && mode != V2DImode)
6246 element = XEXP (op, 0);
6247 if (!CONST_INT_P (element))
6250 value = INTVAL (element);
6251 if (!IN_RANGE (value, -128, 127))
6255 /* Handle (const_vector [...]). */
6256 else if (GET_CODE (op) == CONST_VECTOR)
6258 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6259 && mode != V2DImode)
6262 element = CONST_VECTOR_ELT (op, 0);
6263 if (!CONST_INT_P (element))
6266 value = INTVAL (element);
6267 if (!IN_RANGE (value, -128, 127))
6270 for (i = 1; i < nunits; i++)
6272 element = CONST_VECTOR_ELT (op, i);
6273 if (!CONST_INT_P (element))
6276 if (value != INTVAL (element))
6281 /* Handle integer constants being loaded into the upper part of the VSX
6282 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6283 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6284 else if (CONST_INT_P (op))
6286 if (!SCALAR_INT_MODE_P (mode))
6289 value = INTVAL (op);
6290 if (!IN_RANGE (value, -128, 127))
6293 if (!IN_RANGE (value, -1, 0))
6295 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6298 if (EASY_VECTOR_15 (value))
6306 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6307 sign extend. Special case 0/-1 to allow getting any VSX register instead
6308 of an Altivec register. */
6309 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6310 && EASY_VECTOR_15 (value))
6313 /* Return # of instructions and the constant byte for XXSPLTIB. */
6314 if (mode == V16QImode)
6317 else if (IN_RANGE (value, -1, 0))
6323 *constant_ptr = (int) value;
6328 output_vec_const_move (rtx *operands)
6336 mode = GET_MODE (dest);
6340 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6341 int xxspltib_value = 256;
6344 if (zero_constant (vec, mode))
6346 if (TARGET_P9_VECTOR)
6347 return "xxspltib %x0,0";
6349 else if (dest_vmx_p)
6350 return "vspltisw %0,0";
6353 return "xxlxor %x0,%x0,%x0";
6356 if (all_ones_constant (vec, mode))
6358 if (TARGET_P9_VECTOR)
6359 return "xxspltib %x0,255";
6361 else if (dest_vmx_p)
6362 return "vspltisw %0,-1";
6364 else if (TARGET_P8_VECTOR)
6365 return "xxlorc %x0,%x0,%x0";
6371 if (TARGET_P9_VECTOR
6372 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6376 operands[2] = GEN_INT (xxspltib_value & 0xff);
6377 return "xxspltib %x0,%2";
6388 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6389 if (zero_constant (vec, mode))
6390 return "vspltisw %0,0";
6392 if (all_ones_constant (vec, mode))
6393 return "vspltisw %0,-1";
6395 /* Do we need to construct a value using VSLDOI? */
6396 shift = vspltis_shifted (vec);
6400 splat_vec = gen_easy_altivec_constant (vec);
6401 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6402 operands[1] = XEXP (splat_vec, 0);
6403 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6406 switch (GET_MODE (splat_vec))
6409 return "vspltisw %0,%1";
6412 return "vspltish %0,%1";
6415 return "vspltisb %0,%1";
6425 /* Initialize vector TARGET to VALS. */
6428 rs6000_expand_vector_init (rtx target, rtx vals)
6430 machine_mode mode = GET_MODE (target);
6431 machine_mode inner_mode = GET_MODE_INNER (mode);
6432 int n_elts = GET_MODE_NUNITS (mode);
6433 int n_var = 0, one_var = -1;
6434 bool all_same = true, all_const_zero = true;
6438 for (i = 0; i < n_elts; ++i)
6440 x = XVECEXP (vals, 0, i);
6441 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6442 ++n_var, one_var = i;
6443 else if (x != CONST0_RTX (inner_mode))
6444 all_const_zero = false;
6446 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6452 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6453 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6454 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6456 /* Zero register. */
6457 emit_move_insn (target, CONST0_RTX (mode));
6460 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6462 /* Splat immediate. */
6463 emit_insn (gen_rtx_SET (target, const_vec));
6468 /* Load from constant pool. */
6469 emit_move_insn (target, const_vec);
6474 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6475 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6479 size_t num_elements = all_same ? 1 : 2;
6480 for (i = 0; i < num_elements; i++)
6482 op[i] = XVECEXP (vals, 0, i);
6483 /* Just in case there is a SUBREG with a smaller mode, do a
6485 if (GET_MODE (op[i]) != inner_mode)
6487 rtx tmp = gen_reg_rtx (inner_mode);
6488 convert_move (tmp, op[i], 0);
6491 /* Allow load with splat double word. */
6492 else if (MEM_P (op[i]))
6495 op[i] = force_reg (inner_mode, op[i]);
6497 else if (!REG_P (op[i]))
6498 op[i] = force_reg (inner_mode, op[i]);
6503 if (mode == V2DFmode)
6504 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6506 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6510 if (mode == V2DFmode)
6511 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6513 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6518 /* Special case initializing vector int if we are on 64-bit systems with
6519 direct move or we have the ISA 3.0 instructions. */
6520 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6521 && TARGET_DIRECT_MOVE_64BIT)
6525 rtx element0 = XVECEXP (vals, 0, 0);
6526 if (MEM_P (element0))
6527 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6529 element0 = force_reg (SImode, element0);
6531 if (TARGET_P9_VECTOR)
6532 emit_insn (gen_vsx_splat_v4si (target, element0));
6535 rtx tmp = gen_reg_rtx (DImode);
6536 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6537 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6546 for (i = 0; i < 4; i++)
6547 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6549 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6550 elements[2], elements[3]));
6555 /* With single precision floating point on VSX, know that internally single
6556 precision is actually represented as a double, and either make 2 V2DF
6557 vectors, and convert these vectors to single precision, or do one
6558 conversion, and splat the result to the other elements. */
6559 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6563 rtx element0 = XVECEXP (vals, 0, 0);
6565 if (TARGET_P9_VECTOR)
6567 if (MEM_P (element0))
6568 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6570 emit_insn (gen_vsx_splat_v4sf (target, element0));
6575 rtx freg = gen_reg_rtx (V4SFmode);
6576 rtx sreg = force_reg (SFmode, element0);
6577 rtx cvt = (TARGET_XSCVDPSPN
6578 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6579 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6582 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6588 rtx dbl_even = gen_reg_rtx (V2DFmode);
6589 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6590 rtx flt_even = gen_reg_rtx (V4SFmode);
6591 rtx flt_odd = gen_reg_rtx (V4SFmode);
6592 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6593 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6594 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6595 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6597 /* Use VMRGEW if we can instead of doing a permute. */
6598 if (TARGET_P8_VECTOR)
6600 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6601 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6602 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6603 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6604 if (BYTES_BIG_ENDIAN)
6605 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6607 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6611 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6612 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6613 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6614 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6615 rs6000_expand_extract_even (target, flt_even, flt_odd);
6621 /* Special case initializing vector short/char that are splats if we are on
6622 64-bit systems with direct move. */
6623 if (all_same && TARGET_DIRECT_MOVE_64BIT
6624 && (mode == V16QImode || mode == V8HImode))
6626 rtx op0 = XVECEXP (vals, 0, 0);
6627 rtx di_tmp = gen_reg_rtx (DImode);
6630 op0 = force_reg (GET_MODE_INNER (mode), op0);
6632 if (mode == V16QImode)
6634 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6635 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6639 if (mode == V8HImode)
6641 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6642 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6647 /* Store value to stack temp. Load vector element. Splat. However, splat
6648 of 64-bit items is not supported on Altivec. */
6649 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6651 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6652 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6653 XVECEXP (vals, 0, 0));
6654 x = gen_rtx_UNSPEC (VOIDmode,
6655 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6656 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6658 gen_rtx_SET (target, mem),
6660 x = gen_rtx_VEC_SELECT (inner_mode, target,
6661 gen_rtx_PARALLEL (VOIDmode,
6662 gen_rtvec (1, const0_rtx)));
6663 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6667 /* One field is non-constant. Load constant then overwrite
6671 rtx copy = copy_rtx (vals);
6673 /* Load constant part of vector, substitute neighboring value for
6675 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6676 rs6000_expand_vector_init (target, copy);
6678 /* Insert variable. */
6679 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6683 /* Construct the vector in memory one field at a time
6684 and load the whole vector. */
6685 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6686 for (i = 0; i < n_elts; i++)
6687 emit_move_insn (adjust_address_nv (mem, inner_mode,
6688 i * GET_MODE_SIZE (inner_mode)),
6689 XVECEXP (vals, 0, i));
6690 emit_move_insn (target, mem);
6693 /* Set field ELT of TARGET to VAL. */
6696 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6698 machine_mode mode = GET_MODE (target);
6699 machine_mode inner_mode = GET_MODE_INNER (mode);
6700 rtx reg = gen_reg_rtx (mode);
6702 int width = GET_MODE_SIZE (inner_mode);
6705 val = force_reg (GET_MODE (val), val);
6707 if (VECTOR_MEM_VSX_P (mode))
6709 rtx insn = NULL_RTX;
6710 rtx elt_rtx = GEN_INT (elt);
6712 if (mode == V2DFmode)
6713 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6715 else if (mode == V2DImode)
6716 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6718 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6720 if (mode == V4SImode)
6721 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6722 else if (mode == V8HImode)
6723 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6724 else if (mode == V16QImode)
6725 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6726 else if (mode == V4SFmode)
6727 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6737 /* Simplify setting single element vectors like V1TImode. */
6738 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6740 emit_move_insn (target, gen_lowpart (mode, val));
6744 /* Load single variable value. */
6745 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6746 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6747 x = gen_rtx_UNSPEC (VOIDmode,
6748 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6749 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6751 gen_rtx_SET (reg, mem),
6754 /* Linear sequence. */
6755 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6756 for (i = 0; i < 16; ++i)
6757 XVECEXP (mask, 0, i) = GEN_INT (i);
6759 /* Set permute mask to insert element into target. */
6760 for (i = 0; i < width; ++i)
6761 XVECEXP (mask, 0, elt*width + i)
6762 = GEN_INT (i + 0x10);
6763 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6765 if (BYTES_BIG_ENDIAN)
6766 x = gen_rtx_UNSPEC (mode,
6767 gen_rtvec (3, target, reg,
6768 force_reg (V16QImode, x)),
6772 if (TARGET_P9_VECTOR)
6773 x = gen_rtx_UNSPEC (mode,
6774 gen_rtvec (3, reg, target,
6775 force_reg (V16QImode, x)),
6779 /* Invert selector. We prefer to generate VNAND on P8 so
6780 that future fusion opportunities can kick in, but must
6781 generate VNOR elsewhere. */
6782 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6783 rtx iorx = (TARGET_P8_VECTOR
6784 ? gen_rtx_IOR (V16QImode, notx, notx)
6785 : gen_rtx_AND (V16QImode, notx, notx));
6786 rtx tmp = gen_reg_rtx (V16QImode);
6787 emit_insn (gen_rtx_SET (tmp, iorx));
6789 /* Permute with operands reversed and adjusted selector. */
6790 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6795 emit_insn (gen_rtx_SET (target, x));
6798 /* Extract field ELT from VEC into TARGET. */
6801 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6803 machine_mode mode = GET_MODE (vec);
6804 machine_mode inner_mode = GET_MODE_INNER (mode);
6807 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6814 emit_move_insn (target, gen_lowpart (TImode, vec));
6817 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6820 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6823 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6826 if (TARGET_DIRECT_MOVE_64BIT)
6828 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6834 if (TARGET_DIRECT_MOVE_64BIT)
6836 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6842 if (TARGET_DIRECT_MOVE_64BIT)
6844 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6850 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6851 && TARGET_DIRECT_MOVE_64BIT)
6853 if (GET_MODE (elt) != DImode)
6855 rtx tmp = gen_reg_rtx (DImode);
6856 convert_move (tmp, elt, 0);
6859 else if (!REG_P (elt))
6860 elt = force_reg (DImode, elt);
6865 emit_move_insn (target, gen_lowpart (TImode, vec));
6869 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6873 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6877 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6881 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6885 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6889 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6897 /* Allocate mode-sized buffer. */
6898 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6900 emit_move_insn (mem, vec);
6901 if (CONST_INT_P (elt))
6903 int modulo_elt = INTVAL (elt) % GET_MODE_NUNITS (mode);
6905 /* Add offset to field within buffer matching vector element. */
6906 mem = adjust_address_nv (mem, inner_mode,
6907 modulo_elt * GET_MODE_SIZE (inner_mode));
6908 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6912 unsigned int ele_size = GET_MODE_SIZE (inner_mode);
6913 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
6914 rtx new_addr = gen_reg_rtx (Pmode);
6916 elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
6918 elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
6919 new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
6920 new_addr = change_address (mem, inner_mode, new_addr);
6921 emit_move_insn (target, new_addr);
6925 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6926 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6927 temporary (BASE_TMP) to fixup the address. Return the new memory address
6928 that is valid for reads or writes to a given register (SCALAR_REG). */
6931 rs6000_adjust_vec_address (rtx scalar_reg,
6935 machine_mode scalar_mode)
6937 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6938 rtx addr = XEXP (mem, 0);
6943 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6944 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6946 /* Calculate what we need to add to the address to get the element
6948 if (CONST_INT_P (element))
6949 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6952 int byte_shift = exact_log2 (scalar_size);
6953 gcc_assert (byte_shift >= 0);
6955 if (byte_shift == 0)
6956 element_offset = element;
6960 if (TARGET_POWERPC64)
6961 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6963 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6965 element_offset = base_tmp;
6969 /* Create the new address pointing to the element within the vector. If we
6970 are adding 0, we don't have to change the address. */
6971 if (element_offset == const0_rtx)
6974 /* A simple indirect address can be converted into a reg + offset
6976 else if (REG_P (addr) || SUBREG_P (addr))
6977 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
6979 /* Optimize D-FORM addresses with constant offset with a constant element, to
6980 include the element offset in the address directly. */
6981 else if (GET_CODE (addr) == PLUS)
6983 rtx op0 = XEXP (addr, 0);
6984 rtx op1 = XEXP (addr, 1);
6987 gcc_assert (REG_P (op0) || SUBREG_P (op0));
6988 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
6990 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
6991 rtx offset_rtx = GEN_INT (offset);
6993 if (IN_RANGE (offset, -32768, 32767)
6994 && (scalar_size < 8 || (offset & 0x3) == 0))
6995 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
6998 emit_move_insn (base_tmp, offset_rtx);
6999 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7004 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7005 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7007 /* Note, ADDI requires the register being added to be a base
7008 register. If the register was R0, load it up into the temporary
7011 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7013 insn = gen_add3_insn (base_tmp, op1, element_offset);
7014 gcc_assert (insn != NULL_RTX);
7019 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7021 insn = gen_add3_insn (base_tmp, element_offset, op1);
7022 gcc_assert (insn != NULL_RTX);
7028 emit_move_insn (base_tmp, op1);
7029 emit_insn (gen_add2_insn (base_tmp, element_offset));
7032 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7038 emit_move_insn (base_tmp, addr);
7039 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7042 /* If we have a PLUS, we need to see whether the particular register class
7043 allows for D-FORM or X-FORM addressing. */
7044 if (GET_CODE (new_addr) == PLUS)
7046 rtx op1 = XEXP (new_addr, 1);
7047 addr_mask_type addr_mask;
7048 unsigned int scalar_regno = reg_or_subregno (scalar_reg);
7050 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
7051 if (INT_REGNO_P (scalar_regno))
7052 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7054 else if (FP_REGNO_P (scalar_regno))
7055 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7057 else if (ALTIVEC_REGNO_P (scalar_regno))
7058 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7063 if (REG_P (op1) || SUBREG_P (op1))
7064 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7066 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7069 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7070 valid_addr_p = true;
7073 valid_addr_p = false;
7077 emit_move_insn (base_tmp, new_addr);
7078 new_addr = base_tmp;
7081 return change_address (mem, scalar_mode, new_addr);
7084 /* Split a variable vec_extract operation into the component instructions. */
7087 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7090 machine_mode mode = GET_MODE (src);
7091 machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src));
7092 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7093 int byte_shift = exact_log2 (scalar_size);
7095 gcc_assert (byte_shift >= 0);
7097 /* If we are given a memory address, optimize to load just the element. We
7098 don't have to adjust the vector element number on little endian
7102 int num_elements = GET_MODE_NUNITS (mode);
7103 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7105 emit_insn (gen_anddi3 (element, element, num_ele_m1));
7106 gcc_assert (REG_P (tmp_gpr));
7107 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7108 tmp_gpr, scalar_mode));
7112 else if (REG_P (src) || SUBREG_P (src))
7114 int num_elements = GET_MODE_NUNITS (mode);
7115 int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
7116 int bit_shift = 7 - exact_log2 (num_elements);
7118 unsigned int dest_regno = reg_or_subregno (dest);
7119 unsigned int src_regno = reg_or_subregno (src);
7120 unsigned int element_regno = reg_or_subregno (element);
7122 gcc_assert (REG_P (tmp_gpr));
7124 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7125 a general purpose register. */
7126 if (TARGET_P9_VECTOR
7127 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7128 && INT_REGNO_P (dest_regno)
7129 && ALTIVEC_REGNO_P (src_regno)
7130 && INT_REGNO_P (element_regno))
7132 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7133 rtx element_si = gen_rtx_REG (SImode, element_regno);
7135 if (mode == V16QImode)
7136 emit_insn (BYTES_BIG_ENDIAN
7137 ? gen_vextublx (dest_si, element_si, src)
7138 : gen_vextubrx (dest_si, element_si, src));
7140 else if (mode == V8HImode)
7142 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7143 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7144 emit_insn (BYTES_BIG_ENDIAN
7145 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7146 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7152 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7153 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7154 emit_insn (BYTES_BIG_ENDIAN
7155 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7156 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7163 gcc_assert (REG_P (tmp_altivec));
7165 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7166 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7167 will shift the element into the upper position (adding 3 to convert a
7168 byte shift into a bit shift). */
7169 if (scalar_size == 8)
7171 if (!BYTES_BIG_ENDIAN)
7173 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7179 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7181 emit_insn (gen_rtx_SET (tmp_gpr,
7182 gen_rtx_AND (DImode,
7183 gen_rtx_ASHIFT (DImode,
7190 if (!BYTES_BIG_ENDIAN)
7192 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7194 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7195 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7201 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7204 /* Get the value into the lower byte of the Altivec register where VSLO
7206 if (TARGET_P9_VECTOR)
7207 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7208 else if (can_create_pseudo_p ())
7209 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7212 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7213 emit_move_insn (tmp_di, tmp_gpr);
7214 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7217 /* Do the VSLO to get the value into the final location. */
7221 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7225 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7230 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7231 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7232 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7233 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7236 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7244 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7245 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7246 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7247 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7249 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7250 emit_insn (gen_lshrdi3 (tmp_gpr_di, tmp_gpr_di,
7251 GEN_INT (64 - bits_in_element)));
7265 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7266 selects whether the alignment is abi mandated, optional, or
7267 both abi and optional alignment. */
7270 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7272 if (how != align_opt)
7274 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7278 if (how != align_abi)
7280 if (TREE_CODE (type) == ARRAY_TYPE
7281 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7283 if (align < BITS_PER_WORD)
7284 align = BITS_PER_WORD;
7291 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7292 instructions simply ignore the low bits; VSX memory instructions
7293 are aligned to 4 or 8 bytes. */
7296 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7298 return (STRICT_ALIGNMENT
7299 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7300 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7301 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7302 && (int) align < VECTOR_ALIGN (mode)))));
7305 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7308 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7310 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7312 if (computed != 128)
7315 if (!warned && warn_psabi)
7318 inform (input_location,
7319 "the layout of aggregates containing vectors with"
7320 " %d-byte alignment has changed in GCC 5",
7321 computed / BITS_PER_UNIT);
7324 /* In current GCC there is no special case. */
7331 /* AIX increases natural record alignment to doubleword if the first
7332 field is an FP double while the FP fields remain word aligned. */
7335 rs6000_special_round_type_align (tree type, unsigned int computed,
7336 unsigned int specified)
7338 unsigned int align = MAX (computed, specified);
7339 tree field = TYPE_FIELDS (type);
7341 /* Skip all non field decls */
7342 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7343 field = DECL_CHAIN (field);
7345 if (field != NULL && field != type)
7347 type = TREE_TYPE (field);
7348 while (TREE_CODE (type) == ARRAY_TYPE)
7349 type = TREE_TYPE (type);
7351 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7352 align = MAX (align, 64);
7358 /* Darwin increases record alignment to the natural alignment of
7362 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7363 unsigned int specified)
7365 unsigned int align = MAX (computed, specified);
7367 if (TYPE_PACKED (type))
7370 /* Find the first field, looking down into aggregates. */
7372 tree field = TYPE_FIELDS (type);
7373 /* Skip all non field decls */
7374 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7375 field = DECL_CHAIN (field);
7378 /* A packed field does not contribute any extra alignment. */
7379 if (DECL_PACKED (field))
7381 type = TREE_TYPE (field);
7382 while (TREE_CODE (type) == ARRAY_TYPE)
7383 type = TREE_TYPE (type);
7384 } while (AGGREGATE_TYPE_P (type));
7386 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7387 align = MAX (align, TYPE_ALIGN (type));
7392 /* Return 1 for an operand in small memory on V.4/eabi. */
7395 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7396 machine_mode mode ATTRIBUTE_UNUSED)
7401 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7404 if (DEFAULT_ABI != ABI_V4)
7407 if (SYMBOL_REF_P (op))
7410 else if (GET_CODE (op) != CONST
7411 || GET_CODE (XEXP (op, 0)) != PLUS
7412 || !SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
7413 || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
7418 rtx sum = XEXP (op, 0);
7419 HOST_WIDE_INT summand;
7421 /* We have to be careful here, because it is the referenced address
7422 that must be 32k from _SDA_BASE_, not just the symbol. */
7423 summand = INTVAL (XEXP (sum, 1));
7424 if (summand < 0 || summand > g_switch_value)
7427 sym_ref = XEXP (sum, 0);
7430 return SYMBOL_REF_SMALL_P (sym_ref);
7436 /* Return true if either operand is a general purpose register. */
7439 gpr_or_gpr_p (rtx op0, rtx op1)
7441 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7442 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7445 /* Return true if this is a move direct operation between GPR registers and
7446 floating point/VSX registers. */
7449 direct_move_p (rtx op0, rtx op1)
7453 if (!REG_P (op0) || !REG_P (op1))
7456 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7459 regno0 = REGNO (op0);
7460 regno1 = REGNO (op1);
7461 if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
7464 if (INT_REGNO_P (regno0))
7465 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7467 else if (INT_REGNO_P (regno1))
7469 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7472 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7479 /* Return true if the OFFSET is valid for the quad address instructions that
7480 use d-form (register + offset) addressing. */
7483 quad_address_offset_p (HOST_WIDE_INT offset)
7485 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7488 /* Return true if the ADDR is an acceptable address for a quad memory
7489 operation of mode MODE (either LQ/STQ for general purpose registers, or
7490 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7491 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7492 3.0 LXV/STXV instruction. */
7495 quad_address_p (rtx addr, machine_mode mode, bool strict)
7499 if (GET_MODE_SIZE (mode) != 16)
7502 if (legitimate_indirect_address_p (addr, strict))
7505 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7508 if (GET_CODE (addr) != PLUS)
7511 op0 = XEXP (addr, 0);
7512 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7515 op1 = XEXP (addr, 1);
7516 if (!CONST_INT_P (op1))
7519 return quad_address_offset_p (INTVAL (op1));
7522 /* Return true if this is a load or store quad operation. This function does
7523 not handle the atomic quad memory instructions. */
7526 quad_load_store_p (rtx op0, rtx op1)
7530 if (!TARGET_QUAD_MEMORY)
7533 else if (REG_P (op0) && MEM_P (op1))
7534 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7535 && quad_memory_operand (op1, GET_MODE (op1))
7536 && !reg_overlap_mentioned_p (op0, op1));
7538 else if (MEM_P (op0) && REG_P (op1))
7539 ret = (quad_memory_operand (op0, GET_MODE (op0))
7540 && quad_int_reg_operand (op1, GET_MODE (op1)));
7545 if (TARGET_DEBUG_ADDR)
7547 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7548 ret ? "true" : "false");
7549 debug_rtx (gen_rtx_SET (op0, op1));
7555 /* Given an address, return a constant offset term if one exists. */
7558 address_offset (rtx op)
7560 if (GET_CODE (op) == PRE_INC
7561 || GET_CODE (op) == PRE_DEC)
7563 else if (GET_CODE (op) == PRE_MODIFY
7564 || GET_CODE (op) == LO_SUM)
7567 if (GET_CODE (op) == CONST)
7570 if (GET_CODE (op) == PLUS)
7573 if (CONST_INT_P (op))
7579 /* Return true if the MEM operand is a memory operand suitable for use
7580 with a (full width, possibly multiple) gpr load/store. On
7581 powerpc64 this means the offset must be divisible by 4.
7582 Implements 'Y' constraint.
7584 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7585 a constraint function we know the operand has satisfied a suitable
7588 Offsetting a lo_sum should not be allowed, except where we know by
7589 alignment that a 32k boundary is not crossed. Note that by
7590 "offsetting" here we mean a further offset to access parts of the
7591 MEM. It's fine to have a lo_sum where the inner address is offset
7592 from a sym, since the same sym+offset will appear in the high part
7593 of the address calculation. */
7596 mem_operand_gpr (rtx op, machine_mode mode)
7598 unsigned HOST_WIDE_INT offset;
7600 rtx addr = XEXP (op, 0);
7602 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7604 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7605 && mode_supports_pre_incdec_p (mode)
7606 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7609 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7610 if (!rs6000_offsettable_memref_p (op, mode, false))
7613 op = address_offset (addr);
7617 offset = INTVAL (op);
7618 if (TARGET_POWERPC64 && (offset & 3) != 0)
7621 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7625 if (GET_CODE (addr) == LO_SUM)
7626 /* For lo_sum addresses, we must allow any offset except one that
7627 causes a wrap, so test only the low 16 bits. */
7628 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7630 return offset + 0x8000 < 0x10000u - extra;
7633 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7634 enforce an offset divisible by 4 even for 32-bit. */
7637 mem_operand_ds_form (rtx op, machine_mode mode)
7639 unsigned HOST_WIDE_INT offset;
7641 rtx addr = XEXP (op, 0);
7643 if (!offsettable_address_p (false, mode, addr))
7646 op = address_offset (addr);
7650 offset = INTVAL (op);
7651 if ((offset & 3) != 0)
7654 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7658 if (GET_CODE (addr) == LO_SUM)
7659 /* For lo_sum addresses, we must allow any offset except one that
7660 causes a wrap, so test only the low 16 bits. */
7661 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7663 return offset + 0x8000 < 0x10000u - extra;
7666 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7669 reg_offset_addressing_ok_p (machine_mode mode)
7683 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7684 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7685 a vector mode, if we want to use the VSX registers to move it around,
7686 we need to restrict ourselves to reg+reg addressing. Similarly for
7687 IEEE 128-bit floating point that is passed in a single vector
7689 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7690 return mode_supports_dq_form (mode);
7694 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7695 addressing for the LFIWZX and STFIWX instructions. */
7696 if (TARGET_NO_SDMODE_STACK)
7708 virtual_stack_registers_memory_p (rtx op)
7713 regnum = REGNO (op);
7715 else if (GET_CODE (op) == PLUS
7716 && REG_P (XEXP (op, 0))
7717 && CONST_INT_P (XEXP (op, 1)))
7718 regnum = REGNO (XEXP (op, 0));
7723 return (regnum >= FIRST_VIRTUAL_REGISTER
7724 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7727 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7728 is known to not straddle a 32k boundary. This function is used
7729 to determine whether -mcmodel=medium code can use TOC pointer
7730 relative addressing for OP. This means the alignment of the TOC
7731 pointer must also be taken into account, and unfortunately that is
7734 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7735 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7739 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7743 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7745 if (!SYMBOL_REF_P (op))
7748 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7750 if (mode_supports_dq_form (mode))
7753 dsize = GET_MODE_SIZE (mode);
7754 decl = SYMBOL_REF_DECL (op);
7760 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7761 replacing memory addresses with an anchor plus offset. We
7762 could find the decl by rummaging around in the block->objects
7763 VEC for the given offset but that seems like too much work. */
7764 dalign = BITS_PER_UNIT;
7765 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7766 && SYMBOL_REF_ANCHOR_P (op)
7767 && SYMBOL_REF_BLOCK (op) != NULL)
7769 struct object_block *block = SYMBOL_REF_BLOCK (op);
7771 dalign = block->alignment;
7772 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7774 else if (CONSTANT_POOL_ADDRESS_P (op))
7776 /* It would be nice to have get_pool_align().. */
7777 machine_mode cmode = get_pool_mode (op);
7779 dalign = GET_MODE_ALIGNMENT (cmode);
7782 else if (DECL_P (decl))
7784 dalign = DECL_ALIGN (decl);
7788 /* Allow BLKmode when the entire object is known to not
7789 cross a 32k boundary. */
7790 if (!DECL_SIZE_UNIT (decl))
7793 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7796 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7800 dalign /= BITS_PER_UNIT;
7801 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7802 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7803 return dalign >= dsize;
7809 /* Find how many bits of the alignment we know for this access. */
7810 dalign /= BITS_PER_UNIT;
7811 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7812 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7814 lsb = offset & -offset;
7818 return dalign >= dsize;
7822 constant_pool_expr_p (rtx op)
7826 split_const (op, &base, &offset);
7827 return (SYMBOL_REF_P (base)
7828 && CONSTANT_POOL_ADDRESS_P (base)
7829 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7832 /* These are only used to pass through from print_operand/print_operand_address
7833 to rs6000_output_addr_const_extra over the intervening function
7834 output_addr_const which is not target code. */
7835 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7837 /* Return true if OP is a toc pointer relative address (the output
7838 of create_TOC_reference). If STRICT, do not match non-split
7839 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7840 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7841 TOCREL_OFFSET_RET respectively. */
7844 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7845 const_rtx *tocrel_offset_ret)
7850 if (TARGET_CMODEL != CMODEL_SMALL)
7852 /* When strict ensure we have everything tidy. */
7854 && !(GET_CODE (op) == LO_SUM
7855 && REG_P (XEXP (op, 0))
7856 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7859 /* When not strict, allow non-split TOC addresses and also allow
7860 (lo_sum (high ..)) TOC addresses created during reload. */
7861 if (GET_CODE (op) == LO_SUM)
7865 const_rtx tocrel_base = op;
7866 const_rtx tocrel_offset = const0_rtx;
7868 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7870 tocrel_base = XEXP (op, 0);
7871 tocrel_offset = XEXP (op, 1);
7874 if (tocrel_base_ret)
7875 *tocrel_base_ret = tocrel_base;
7876 if (tocrel_offset_ret)
7877 *tocrel_offset_ret = tocrel_offset;
7879 return (GET_CODE (tocrel_base) == UNSPEC
7880 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7881 && REG_P (XVECEXP (tocrel_base, 0, 1))
7882 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7885 /* Return true if X is a constant pool address, and also for cmodel=medium
7886 if X is a toc-relative address known to be offsettable within MODE. */
7889 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7892 const_rtx tocrel_base, tocrel_offset;
7893 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7894 && (TARGET_CMODEL != CMODEL_MEDIUM
7895 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7897 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7898 INTVAL (tocrel_offset), mode)));
7902 legitimate_small_data_p (machine_mode mode, rtx x)
7904 return (DEFAULT_ABI == ABI_V4
7905 && !flag_pic && !TARGET_TOC
7906 && (SYMBOL_REF_P (x) || GET_CODE (x) == CONST)
7907 && small_data_operand (x, mode));
7911 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7912 bool strict, bool worst_case)
7914 unsigned HOST_WIDE_INT offset;
7917 if (GET_CODE (x) != PLUS)
7919 if (!REG_P (XEXP (x, 0)))
7921 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7923 if (mode_supports_dq_form (mode))
7924 return quad_address_p (x, mode, strict);
7925 if (!reg_offset_addressing_ok_p (mode))
7926 return virtual_stack_registers_memory_p (x);
7927 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7929 if (!CONST_INT_P (XEXP (x, 1)))
7932 offset = INTVAL (XEXP (x, 1));
7939 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7941 if (VECTOR_MEM_VSX_P (mode))
7946 if (!TARGET_POWERPC64)
7948 else if (offset & 3)
7961 if (!TARGET_POWERPC64)
7963 else if (offset & 3)
7972 return offset < 0x10000 - extra;
7976 legitimate_indexed_address_p (rtx x, int strict)
7980 if (GET_CODE (x) != PLUS)
7986 return (REG_P (op0) && REG_P (op1)
7987 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
7988 && INT_REG_OK_FOR_INDEX_P (op1, strict))
7989 || (INT_REG_OK_FOR_BASE_P (op1, strict)
7990 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
7994 avoiding_indexed_address_p (machine_mode mode)
7996 /* Avoid indexed addressing for modes that have non-indexed
7997 load/store instruction forms. */
7998 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8002 legitimate_indirect_address_p (rtx x, int strict)
8004 return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
8008 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8010 if (!TARGET_MACHO || !flag_pic
8011 || mode != SImode || !MEM_P (x))
8015 if (GET_CODE (x) != LO_SUM)
8017 if (!REG_P (XEXP (x, 0)))
8019 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8023 return CONSTANT_P (x);
8027 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8029 if (GET_CODE (x) != LO_SUM)
8031 if (!REG_P (XEXP (x, 0)))
8033 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8035 /* quad word addresses are restricted, and we can't use LO_SUM. */
8036 if (mode_supports_dq_form (mode))
8040 if (TARGET_ELF || TARGET_MACHO)
8044 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8046 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8047 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8048 recognizes some LO_SUM addresses as valid although this
8049 function says opposite. In most cases, LRA through different
8050 transformations can generate correct code for address reloads.
8051 It cannot manage only some LO_SUM cases. So we need to add
8052 code here saying that some addresses are still valid. */
8053 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8054 && small_toc_ref (x, VOIDmode));
8055 if (TARGET_TOC && ! large_toc_ok)
8057 if (GET_MODE_NUNITS (mode) != 1)
8059 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8060 && !(/* ??? Assume floating point reg based on mode? */
8061 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8064 return CONSTANT_P (x) || large_toc_ok;
8071 /* Try machine-dependent ways of modifying an illegitimate address
8072 to be legitimate. If we find one, return the new, valid address.
8073 This is used from only one place: `memory_address' in explow.c.
8075 OLDX is the address as it was before break_out_memory_refs was
8076 called. In some cases it is useful to look at this to decide what
8079 It is always safe for this function to do nothing. It exists to
8080 recognize opportunities to optimize the output.
8082 On RS/6000, first check for the sum of a register with a constant
8083 integer that is out of range. If so, generate code to add the
8084 constant with the low-order 16 bits masked to the register and force
8085 this result into another register (this can be done with `cau').
8086 Then generate an address of REG+(CONST&0xffff), allowing for the
8087 possibility of bit 16 being a one.
8089 Then check for the sum of a register and something not constant, try to
8090 load the other things into a register and return the sum. */
8093 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8098 if (!reg_offset_addressing_ok_p (mode)
8099 || mode_supports_dq_form (mode))
8101 if (virtual_stack_registers_memory_p (x))
8104 /* In theory we should not be seeing addresses of the form reg+0,
8105 but just in case it is generated, optimize it away. */
8106 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8107 return force_reg (Pmode, XEXP (x, 0));
8109 /* For TImode with load/store quad, restrict addresses to just a single
8110 pointer, so it works with both GPRs and VSX registers. */
8111 /* Make sure both operands are registers. */
8112 else if (GET_CODE (x) == PLUS
8113 && (mode != TImode || !TARGET_VSX))
8114 return gen_rtx_PLUS (Pmode,
8115 force_reg (Pmode, XEXP (x, 0)),
8116 force_reg (Pmode, XEXP (x, 1)));
8118 return force_reg (Pmode, x);
8120 if (SYMBOL_REF_P (x))
8122 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8124 return rs6000_legitimize_tls_address (x, model);
8136 /* As in legitimate_offset_address_p we do not assume
8137 worst-case. The mode here is just a hint as to the registers
8138 used. A TImode is usually in gprs, but may actually be in
8139 fprs. Leave worst-case scenario for reload to handle via
8140 insn constraints. PTImode is only GPRs. */
8147 if (GET_CODE (x) == PLUS
8148 && REG_P (XEXP (x, 0))
8149 && CONST_INT_P (XEXP (x, 1))
8150 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8151 >= 0x10000 - extra))
8153 HOST_WIDE_INT high_int, low_int;
8155 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8156 if (low_int >= 0x8000 - extra)
8158 high_int = INTVAL (XEXP (x, 1)) - low_int;
8159 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8160 GEN_INT (high_int)), 0);
8161 return plus_constant (Pmode, sum, low_int);
8163 else if (GET_CODE (x) == PLUS
8164 && REG_P (XEXP (x, 0))
8165 && !CONST_INT_P (XEXP (x, 1))
8166 && GET_MODE_NUNITS (mode) == 1
8167 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8168 || (/* ??? Assume floating point reg based on mode? */
8169 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8170 && !avoiding_indexed_address_p (mode))
8172 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8173 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8175 else if ((TARGET_ELF
8177 || !MACHO_DYNAMIC_NO_PIC_P
8184 && !CONST_WIDE_INT_P (x)
8185 && !CONST_DOUBLE_P (x)
8187 && GET_MODE_NUNITS (mode) == 1
8188 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8189 || (/* ??? Assume floating point reg based on mode? */
8190 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8192 rtx reg = gen_reg_rtx (Pmode);
8194 emit_insn (gen_elf_high (reg, x));
8196 emit_insn (gen_macho_high (reg, x));
8197 return gen_rtx_LO_SUM (Pmode, reg, x);
8201 && constant_pool_expr_p (x)
8202 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8203 return create_TOC_reference (x, NULL_RTX);
8208 /* Debug version of rs6000_legitimize_address. */
8210 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8216 ret = rs6000_legitimize_address (x, oldx, mode);
8217 insns = get_insns ();
8223 "\nrs6000_legitimize_address: mode %s, old code %s, "
8224 "new code %s, modified\n",
8225 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8226 GET_RTX_NAME (GET_CODE (ret)));
8228 fprintf (stderr, "Original address:\n");
8231 fprintf (stderr, "oldx:\n");
8234 fprintf (stderr, "New address:\n");
8239 fprintf (stderr, "Insns added:\n");
8240 debug_rtx_list (insns, 20);
8246 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8247 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8258 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8259 We need to emit DTP-relative relocations. */
8261 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8263 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8268 fputs ("\t.long\t", file);
8271 fputs (DOUBLE_INT_ASM_OP, file);
8276 output_addr_const (file, x);
8278 fputs ("@dtprel+0x8000", file);
8279 else if (TARGET_XCOFF && SYMBOL_REF_P (x))
8281 switch (SYMBOL_REF_TLS_MODEL (x))
8285 case TLS_MODEL_LOCAL_EXEC:
8286 fputs ("@le", file);
8288 case TLS_MODEL_INITIAL_EXEC:
8289 fputs ("@ie", file);
8291 case TLS_MODEL_GLOBAL_DYNAMIC:
8292 case TLS_MODEL_LOCAL_DYNAMIC:
8301 /* Return true if X is a symbol that refers to real (rather than emulated)
8305 rs6000_real_tls_symbol_ref_p (rtx x)
8307 return (SYMBOL_REF_P (x)
8308 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8311 /* In the name of slightly smaller debug output, and to cater to
8312 general assembler lossage, recognize various UNSPEC sequences
8313 and turn them back into a direct symbol reference. */
8316 rs6000_delegitimize_address (rtx orig_x)
8320 if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
8321 orig_x = XVECEXP (orig_x, 0, 0);
8323 orig_x = delegitimize_mem_from_attrs (orig_x);
8330 if (TARGET_CMODEL != CMODEL_SMALL && GET_CODE (y) == LO_SUM)
8334 if (GET_CODE (y) == PLUS
8335 && GET_MODE (y) == Pmode
8336 && CONST_INT_P (XEXP (y, 1)))
8338 offset = XEXP (y, 1);
8342 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL)
8344 y = XVECEXP (y, 0, 0);
8347 /* Do not associate thread-local symbols with the original
8348 constant pool symbol. */
8351 && CONSTANT_POOL_ADDRESS_P (y)
8352 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8356 if (offset != NULL_RTX)
8357 y = gen_rtx_PLUS (Pmode, y, offset);
8358 if (!MEM_P (orig_x))
8361 return replace_equiv_address_nv (orig_x, y);
8365 && GET_CODE (orig_x) == LO_SUM
8366 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8368 y = XEXP (XEXP (orig_x, 1), 0);
8369 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8370 return XVECEXP (y, 0, 0);
8376 /* Return true if X shouldn't be emitted into the debug info.
8377 The linker doesn't like .toc section references from
8378 .debug_* sections, so reject .toc section symbols. */
8381 rs6000_const_not_ok_for_debug_p (rtx x)
8383 if (GET_CODE (x) == UNSPEC)
8385 if (SYMBOL_REF_P (x)
8386 && CONSTANT_POOL_ADDRESS_P (x))
8388 rtx c = get_pool_constant (x);
8389 machine_mode cmode = get_pool_mode (x);
8390 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8397 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8400 rs6000_legitimate_combined_insn (rtx_insn *insn)
8402 int icode = INSN_CODE (insn);
8404 /* Reject creating doloop insns. Combine should not be allowed
8405 to create these for a number of reasons:
8406 1) In a nested loop, if combine creates one of these in an
8407 outer loop and the register allocator happens to allocate ctr
8408 to the outer loop insn, then the inner loop can't use ctr.
8409 Inner loops ought to be more highly optimized.
8410 2) Combine often wants to create one of these from what was
8411 originally a three insn sequence, first combining the three
8412 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8413 allocated ctr, the splitter takes use back to the three insn
8414 sequence. It's better to stop combine at the two insn
8416 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8417 insns, the register allocator sometimes uses floating point
8418 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8419 jump insn and output reloads are not implemented for jumps,
8420 the ctrsi/ctrdi splitters need to handle all possible cases.
8421 That's a pain, and it gets to be seriously difficult when a
8422 splitter that runs after reload needs memory to transfer from
8423 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8424 for the difficult case. It's better to not create problems
8425 in the first place. */
8426 if (icode != CODE_FOR_nothing
8427 && (icode == CODE_FOR_bdz_si
8428 || icode == CODE_FOR_bdz_di
8429 || icode == CODE_FOR_bdnz_si
8430 || icode == CODE_FOR_bdnz_di
8431 || icode == CODE_FOR_bdztf_si
8432 || icode == CODE_FOR_bdztf_di
8433 || icode == CODE_FOR_bdnztf_si
8434 || icode == CODE_FOR_bdnztf_di))
8440 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8442 static GTY(()) rtx rs6000_tls_symbol;
8444 rs6000_tls_get_addr (void)
8446 if (!rs6000_tls_symbol)
8447 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8449 return rs6000_tls_symbol;
8452 /* Construct the SYMBOL_REF for TLS GOT references. */
8454 static GTY(()) rtx rs6000_got_symbol;
8456 rs6000_got_sym (void)
8458 if (!rs6000_got_symbol)
8460 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8461 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8462 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8465 return rs6000_got_symbol;
8468 /* AIX Thread-Local Address support. */
8471 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8473 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8477 name = XSTR (addr, 0);
8478 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8479 or the symbol will be in TLS private data section. */
8480 if (name[strlen (name) - 1] != ']'
8481 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8482 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8484 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8485 strcpy (tlsname, name);
8487 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8488 tlsaddr = copy_rtx (addr);
8489 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8494 /* Place addr into TOC constant pool. */
8495 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8497 /* Output the TOC entry and create the MEM referencing the value. */
8498 if (constant_pool_expr_p (XEXP (sym, 0))
8499 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8501 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8502 mem = gen_const_mem (Pmode, tocref);
8503 set_mem_alias_set (mem, get_TOC_alias_set ());
8508 /* Use global-dynamic for local-dynamic. */
8509 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8510 || model == TLS_MODEL_LOCAL_DYNAMIC)
8512 /* Create new TOC reference for @m symbol. */
8513 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8514 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8515 strcpy (tlsname, "*LCM");
8516 strcat (tlsname, name + 3);
8517 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8518 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8519 tocref = create_TOC_reference (modaddr, NULL_RTX);
8520 rtx modmem = gen_const_mem (Pmode, tocref);
8521 set_mem_alias_set (modmem, get_TOC_alias_set ());
8523 rtx modreg = gen_reg_rtx (Pmode);
8524 emit_insn (gen_rtx_SET (modreg, modmem));
8526 tmpreg = gen_reg_rtx (Pmode);
8527 emit_insn (gen_rtx_SET (tmpreg, mem));
8529 dest = gen_reg_rtx (Pmode);
8531 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8533 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8536 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8537 else if (TARGET_32BIT)
8539 tlsreg = gen_reg_rtx (SImode);
8540 emit_insn (gen_tls_get_tpointer (tlsreg));
8543 tlsreg = gen_rtx_REG (DImode, 13);
8545 /* Load the TOC value into temporary register. */
8546 tmpreg = gen_reg_rtx (Pmode);
8547 emit_insn (gen_rtx_SET (tmpreg, mem));
8548 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8549 gen_rtx_MINUS (Pmode, addr, tlsreg));
8551 /* Add TOC symbol value to TLS pointer. */
8552 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8557 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8558 __tls_get_addr call. */
8561 rs6000_output_tlsargs (rtx *operands)
8563 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8566 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8567 op[0] = operands[0];
8568 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8569 op[1] = XVECEXP (operands[2], 0, 0);
8570 if (XINT (operands[2], 1) == UNSPEC_TLSGD)
8572 /* The GOT register. */
8573 op[2] = XVECEXP (operands[2], 0, 1);
8574 if (TARGET_CMODEL != CMODEL_SMALL)
8575 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8576 "addi %0,%0,%1@got@tlsgd@l", op);
8578 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op);
8580 else if (XINT (operands[2], 1) == UNSPEC_TLSLD)
8582 if (TARGET_CMODEL != CMODEL_SMALL)
8583 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8584 "addi %0,%0,%&@got@tlsld@l", op);
8586 output_asm_insn ("addi %0,%1,%&@got@tlsld", op);
8592 /* Passes the tls arg value for global dynamic and local dynamic
8593 emit_library_call_value in rs6000_legitimize_tls_address to
8594 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8595 marker relocs put on __tls_get_addr calls. */
8596 static rtx global_tlsarg;
8598 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8599 this (thread-local) address. */
8602 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8607 return rs6000_legitimize_tls_address_aix (addr, model);
8609 dest = gen_reg_rtx (Pmode);
8610 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8616 tlsreg = gen_rtx_REG (Pmode, 13);
8617 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8621 tlsreg = gen_rtx_REG (Pmode, 2);
8622 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8626 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8630 tmp = gen_reg_rtx (Pmode);
8633 tlsreg = gen_rtx_REG (Pmode, 13);
8634 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8638 tlsreg = gen_rtx_REG (Pmode, 2);
8639 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8643 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8645 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8650 rtx got, tga, tmp1, tmp2;
8652 /* We currently use relocations like @got@tlsgd for tls, which
8653 means the linker will handle allocation of tls entries, placing
8654 them in the .got section. So use a pointer to the .got section,
8655 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8656 or to secondary GOT sections used by 32-bit -fPIC. */
8658 got = gen_rtx_REG (Pmode, 2);
8662 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8665 rtx gsym = rs6000_got_sym ();
8666 got = gen_reg_rtx (Pmode);
8668 rs6000_emit_move (got, gsym, Pmode);
8673 tmp1 = gen_reg_rtx (Pmode);
8674 tmp2 = gen_reg_rtx (Pmode);
8675 mem = gen_const_mem (Pmode, tmp1);
8676 lab = gen_label_rtx ();
8677 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8678 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8679 if (TARGET_LINK_STACK)
8680 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8681 emit_move_insn (tmp2, mem);
8682 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8683 set_unique_reg_note (last, REG_EQUAL, gsym);
8688 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8690 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addr, got),
8692 tga = rs6000_tls_get_addr ();
8693 global_tlsarg = arg;
8694 if (TARGET_TLS_MARKERS)
8696 rtx argreg = gen_rtx_REG (Pmode, 3);
8697 emit_insn (gen_rtx_SET (argreg, arg));
8698 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8702 emit_library_call_value (tga, dest, LCT_CONST, Pmode);
8703 global_tlsarg = NULL_RTX;
8705 /* Make a note so that the result of this call can be CSEd. */
8706 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8707 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8708 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8710 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8712 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got), UNSPEC_TLSLD);
8713 tga = rs6000_tls_get_addr ();
8714 tmp1 = gen_reg_rtx (Pmode);
8715 global_tlsarg = arg;
8716 if (TARGET_TLS_MARKERS)
8718 rtx argreg = gen_rtx_REG (Pmode, 3);
8719 emit_insn (gen_rtx_SET (argreg, arg));
8720 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8724 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode);
8725 global_tlsarg = NULL_RTX;
8727 /* Make a note so that the result of this call can be CSEd. */
8728 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8729 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8730 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8732 if (rs6000_tls_size == 16)
8735 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8737 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8739 else if (rs6000_tls_size == 32)
8741 tmp2 = gen_reg_rtx (Pmode);
8743 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8745 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8748 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8750 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8754 tmp2 = gen_reg_rtx (Pmode);
8756 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8758 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8760 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8766 /* IE, or 64-bit offset LE. */
8767 tmp2 = gen_reg_rtx (Pmode);
8769 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8771 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8774 insn = gen_tls_tls_64 (dest, tmp2, addr);
8776 insn = gen_tls_tls_32 (dest, tmp2, addr);
8784 /* Only create the global variable for the stack protect guard if we are using
8785 the global flavor of that guard. */
8787 rs6000_init_stack_protect_guard (void)
8789 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8790 return default_stack_protect_guard ();
8795 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8798 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8800 if (GET_CODE (x) == HIGH
8801 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8804 /* A TLS symbol in the TOC cannot contain a sum. */
8805 if (GET_CODE (x) == CONST
8806 && GET_CODE (XEXP (x, 0)) == PLUS
8807 && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
8808 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8811 /* Do not place an ELF TLS symbol in the constant pool. */
8812 return TARGET_ELF && tls_referenced_p (x);
8815 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8816 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8817 can be addressed relative to the toc pointer. */
8820 use_toc_relative_ref (rtx sym, machine_mode mode)
8822 return ((constant_pool_expr_p (sym)
8823 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8824 get_pool_mode (sym)))
8825 || (TARGET_CMODEL == CMODEL_MEDIUM
8826 && SYMBOL_REF_LOCAL_P (sym)
8827 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8830 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8831 that is a valid memory address for an instruction.
8832 The MODE argument is the machine mode for the MEM expression
8833 that wants to use this address.
8835 On the RS/6000, there are four valid address: a SYMBOL_REF that
8836 refers to a constant pool entry of an address (or the sum of it
8837 plus a constant), a short (16-bit signed) constant plus a register,
8838 the sum of two registers, or a register indirect, possibly with an
8839 auto-increment. For DFmode, DDmode and DImode with a constant plus
8840 register, we must ensure that both words are addressable or PowerPC64
8841 with offset word aligned.
8843 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8844 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8845 because adjacent memory cells are accessed by adding word-sized offsets
8846 during assembly output. */
8848 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
8850 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8851 bool quad_offset_p = mode_supports_dq_form (mode);
8853 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8854 if (VECTOR_MEM_ALTIVEC_P (mode)
8855 && GET_CODE (x) == AND
8856 && CONST_INT_P (XEXP (x, 1))
8857 && INTVAL (XEXP (x, 1)) == -16)
8860 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
8862 if (legitimate_indirect_address_p (x, reg_ok_strict))
8865 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
8866 && mode_supports_pre_incdec_p (mode)
8867 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
8869 /* Handle restricted vector d-form offsets in ISA 3.0. */
8872 if (quad_address_p (x, mode, reg_ok_strict))
8875 else if (virtual_stack_registers_memory_p (x))
8878 else if (reg_offset_p)
8880 if (legitimate_small_data_p (mode, x))
8882 if (legitimate_constant_pool_address_p (x, mode,
8883 reg_ok_strict || lra_in_progress))
8887 /* For TImode, if we have TImode in VSX registers, only allow register
8888 indirect addresses. This will allow the values to go in either GPRs
8889 or VSX registers without reloading. The vector types would tend to
8890 go into VSX registers, so we allow REG+REG, while TImode seems
8891 somewhat split, in that some uses are GPR based, and some VSX based. */
8892 /* FIXME: We could loosen this by changing the following to
8893 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
8894 but currently we cannot allow REG+REG addressing for TImode. See
8895 PR72827 for complete details on how this ends up hoodwinking DSE. */
8896 if (mode == TImode && TARGET_VSX)
8898 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8901 && GET_CODE (x) == PLUS
8902 && REG_P (XEXP (x, 0))
8903 && (XEXP (x, 0) == virtual_stack_vars_rtx
8904 || XEXP (x, 0) == arg_pointer_rtx)
8905 && CONST_INT_P (XEXP (x, 1)))
8907 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
8909 if (!FLOAT128_2REG_P (mode)
8910 && (TARGET_HARD_FLOAT
8912 || (mode != DFmode && mode != DDmode))
8913 && (TARGET_POWERPC64 || mode != DImode)
8914 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
8916 && !avoiding_indexed_address_p (mode)
8917 && legitimate_indexed_address_p (x, reg_ok_strict))
8919 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
8920 && mode_supports_pre_modify_p (mode)
8921 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
8922 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
8923 reg_ok_strict, false)
8924 || (!avoiding_indexed_address_p (mode)
8925 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
8926 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8928 if (reg_offset_p && !quad_offset_p
8929 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
8934 /* Debug version of rs6000_legitimate_address_p. */
8936 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
8939 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
8941 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8942 "strict = %d, reload = %s, code = %s\n",
8943 ret ? "true" : "false",
8944 GET_MODE_NAME (mode),
8946 (reload_completed ? "after" : "before"),
8947 GET_RTX_NAME (GET_CODE (x)));
8953 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8956 rs6000_mode_dependent_address_p (const_rtx addr,
8957 addr_space_t as ATTRIBUTE_UNUSED)
8959 return rs6000_mode_dependent_address_ptr (addr);
8962 /* Go to LABEL if ADDR (a legitimate address expression)
8963 has an effect that depends on the machine mode it is used for.
8965 On the RS/6000 this is true of all integral offsets (since AltiVec
8966 and VSX modes don't allow them) or is a pre-increment or decrement.
8968 ??? Except that due to conceptual problems in offsettable_address_p
8969 we can't really report the problems of integral offsets. So leave
8970 this assuming that the adjustable offset must be valid for the
8971 sub-words of a TFmode operand, which is what we had before. */
8974 rs6000_mode_dependent_address (const_rtx addr)
8976 switch (GET_CODE (addr))
8979 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8980 is considered a legitimate address before reload, so there
8981 are no offset restrictions in that case. Note that this
8982 condition is safe in strict mode because any address involving
8983 virtual_stack_vars_rtx or arg_pointer_rtx would already have
8984 been rejected as illegitimate. */
8985 if (XEXP (addr, 0) != virtual_stack_vars_rtx
8986 && XEXP (addr, 0) != arg_pointer_rtx
8987 && CONST_INT_P (XEXP (addr, 1)))
8989 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
8990 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
8995 /* Anything in the constant pool is sufficiently aligned that
8996 all bytes have the same high part address. */
8997 return !legitimate_constant_pool_address_p (addr, QImode, false);
8999 /* Auto-increment cases are now treated generically in recog.c. */
9001 return TARGET_UPDATE;
9003 /* AND is only allowed in Altivec loads. */
9014 /* Debug version of rs6000_mode_dependent_address. */
9016 rs6000_debug_mode_dependent_address (const_rtx addr)
9018 bool ret = rs6000_mode_dependent_address (addr);
9020 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9021 ret ? "true" : "false");
9027 /* Implement FIND_BASE_TERM. */
9030 rs6000_find_base_term (rtx op)
9035 if (GET_CODE (base) == CONST)
9036 base = XEXP (base, 0);
9037 if (GET_CODE (base) == PLUS)
9038 base = XEXP (base, 0);
9039 if (GET_CODE (base) == UNSPEC)
9040 switch (XINT (base, 1))
9043 case UNSPEC_MACHOPIC_OFFSET:
9044 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9045 for aliasing purposes. */
9046 return XVECEXP (base, 0, 0);
9052 /* More elaborate version of recog's offsettable_memref_p predicate
9053 that works around the ??? note of rs6000_mode_dependent_address.
9054 In particular it accepts
9056 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9058 in 32-bit mode, that the recog predicate rejects. */
9061 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9068 /* First mimic offsettable_memref_p. */
9069 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9072 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9073 the latter predicate knows nothing about the mode of the memory
9074 reference and, therefore, assumes that it is the largest supported
9075 mode (TFmode). As a consequence, legitimate offsettable memory
9076 references are rejected. rs6000_legitimate_offset_address_p contains
9077 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9078 at least with a little bit of help here given that we know the
9079 actual registers used. */
9080 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9081 || GET_MODE_SIZE (reg_mode) == 4);
9082 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9083 strict, worst_case);
9086 /* Determine the reassociation width to be used in reassociate_bb.
9087 This takes into account how many parallel operations we
9088 can actually do of a given type, and also the latency.
9092 vect add/sub/mul 2/cycle
9093 fp add/sub/mul 2/cycle
9098 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9101 switch (rs6000_tune)
9103 case PROCESSOR_POWER8:
9104 case PROCESSOR_POWER9:
9105 if (DECIMAL_FLOAT_MODE_P (mode))
9107 if (VECTOR_MODE_P (mode))
9109 if (INTEGRAL_MODE_P (mode))
9111 if (FLOAT_MODE_P (mode))
9120 /* Change register usage conditional on target flags. */
9122 rs6000_conditional_register_usage (void)
9126 if (TARGET_DEBUG_TARGET)
9127 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9129 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9131 fixed_regs[13] = call_used_regs[13]
9132 = call_really_used_regs[13] = 1;
9134 /* Conditionally disable FPRs. */
9135 if (TARGET_SOFT_FLOAT)
9136 for (i = 32; i < 64; i++)
9137 fixed_regs[i] = call_used_regs[i]
9138 = call_really_used_regs[i] = 1;
9140 /* The TOC register is not killed across calls in a way that is
9141 visible to the compiler. */
9142 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9143 call_really_used_regs[2] = 0;
9145 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9146 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9148 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9149 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9150 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9151 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9153 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9154 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9155 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9156 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9158 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9159 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9160 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9162 if (!TARGET_ALTIVEC && !TARGET_VSX)
9164 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9165 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9166 call_really_used_regs[VRSAVE_REGNO] = 1;
9169 if (TARGET_ALTIVEC || TARGET_VSX)
9170 global_regs[VSCR_REGNO] = 1;
9172 if (TARGET_ALTIVEC_ABI)
9174 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9175 call_used_regs[i] = call_really_used_regs[i] = 1;
9177 /* AIX reserves VR20:31 in non-extended ABI mode. */
9179 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9180 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9185 /* Output insns to set DEST equal to the constant SOURCE as a series of
9186 lis, ori and shl instructions and return TRUE. */
9189 rs6000_emit_set_const (rtx dest, rtx source)
9191 machine_mode mode = GET_MODE (dest);
9196 gcc_checking_assert (CONST_INT_P (source));
9197 c = INTVAL (source);
9202 emit_insn (gen_rtx_SET (dest, source));
9206 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9208 emit_insn (gen_rtx_SET (copy_rtx (temp),
9209 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9210 emit_insn (gen_rtx_SET (dest,
9211 gen_rtx_IOR (SImode, copy_rtx (temp),
9212 GEN_INT (c & 0xffff))));
9216 if (!TARGET_POWERPC64)
9220 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9222 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9224 emit_move_insn (hi, GEN_INT (c >> 32));
9225 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9226 emit_move_insn (lo, GEN_INT (c));
9229 rs6000_emit_set_long_const (dest, c);
9236 insn = get_last_insn ();
9237 set = single_set (insn);
9238 if (! CONSTANT_P (SET_SRC (set)))
9239 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9244 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9245 Output insns to set DEST equal to the constant C as a series of
9246 lis, ori and shl instructions. */
9249 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9252 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9262 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9263 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9264 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9266 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9267 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9269 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9271 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9272 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9274 emit_move_insn (dest,
9275 gen_rtx_IOR (DImode, copy_rtx (temp),
9278 else if (ud3 == 0 && ud4 == 0)
9280 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9282 gcc_assert (ud2 & 0x8000);
9283 emit_move_insn (copy_rtx (temp),
9284 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9286 emit_move_insn (copy_rtx (temp),
9287 gen_rtx_IOR (DImode, copy_rtx (temp),
9289 emit_move_insn (dest,
9290 gen_rtx_ZERO_EXTEND (DImode,
9291 gen_lowpart (SImode,
9294 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9295 || (ud4 == 0 && ! (ud3 & 0x8000)))
9297 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9299 emit_move_insn (copy_rtx (temp),
9300 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9302 emit_move_insn (copy_rtx (temp),
9303 gen_rtx_IOR (DImode, copy_rtx (temp),
9305 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9306 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9309 emit_move_insn (dest,
9310 gen_rtx_IOR (DImode, copy_rtx (temp),
9315 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9317 emit_move_insn (copy_rtx (temp),
9318 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9320 emit_move_insn (copy_rtx (temp),
9321 gen_rtx_IOR (DImode, copy_rtx (temp),
9324 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9325 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9328 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9329 gen_rtx_IOR (DImode, copy_rtx (temp),
9330 GEN_INT (ud2 << 16)));
9332 emit_move_insn (dest,
9333 gen_rtx_IOR (DImode, copy_rtx (temp),
9338 /* Helper for the following. Get rid of [r+r] memory refs
9339 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9342 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9344 if (MEM_P (operands[0])
9345 && !REG_P (XEXP (operands[0], 0))
9346 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9347 GET_MODE (operands[0]), false))
9349 = replace_equiv_address (operands[0],
9350 copy_addr_to_reg (XEXP (operands[0], 0)));
9352 if (MEM_P (operands[1])
9353 && !REG_P (XEXP (operands[1], 0))
9354 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9355 GET_MODE (operands[1]), false))
9357 = replace_equiv_address (operands[1],
9358 copy_addr_to_reg (XEXP (operands[1], 0)));
9361 /* Generate a vector of constants to permute MODE for a little-endian
9362 storage operation by swapping the two halves of a vector. */
9364 rs6000_const_vec (machine_mode mode)
9392 v = rtvec_alloc (subparts);
9394 for (i = 0; i < subparts / 2; ++i)
9395 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9396 for (i = subparts / 2; i < subparts; ++i)
9397 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9402 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9405 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9407 /* Scalar permutations are easier to express in integer modes rather than
9408 floating-point modes, so cast them here. We use V1TImode instead
9409 of TImode to ensure that the values don't go through GPRs. */
9410 if (FLOAT128_VECTOR_P (mode))
9412 dest = gen_lowpart (V1TImode, dest);
9413 source = gen_lowpart (V1TImode, source);
9417 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9419 if (mode == TImode || mode == V1TImode)
9420 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9424 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9425 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9429 /* Emit a little-endian load from vector memory location SOURCE to VSX
9430 register DEST in mode MODE. The load is done with two permuting
9431 insn's that represent an lxvd2x and xxpermdi. */
9433 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9435 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9437 if (mode == TImode || mode == V1TImode)
9440 dest = gen_lowpart (V2DImode, dest);
9441 source = adjust_address (source, V2DImode, 0);
9444 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9445 rs6000_emit_le_vsx_permute (tmp, source, mode);
9446 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9449 /* Emit a little-endian store to vector memory location DEST from VSX
9450 register SOURCE in mode MODE. The store is done with two permuting
9451 insn's that represent an xxpermdi and an stxvd2x. */
9453 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9455 /* This should never be called during or after LRA, because it does
9456 not re-permute the source register. It is intended only for use
9458 gcc_assert (!lra_in_progress && !reload_completed);
9460 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9462 if (mode == TImode || mode == V1TImode)
9465 dest = adjust_address (dest, V2DImode, 0);
9466 source = gen_lowpart (V2DImode, source);
9469 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9470 rs6000_emit_le_vsx_permute (tmp, source, mode);
9471 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9474 /* Emit a sequence representing a little-endian VSX load or store,
9475 moving data from SOURCE to DEST in mode MODE. This is done
9476 separately from rs6000_emit_move to ensure it is called only
9477 during expand. LE VSX loads and stores introduced later are
9478 handled with a split. The expand-time RTL generation allows
9479 us to optimize away redundant pairs of register-permutes. */
9481 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9483 gcc_assert (!BYTES_BIG_ENDIAN
9484 && VECTOR_MEM_VSX_P (mode)
9485 && !TARGET_P9_VECTOR
9486 && !gpr_or_gpr_p (dest, source)
9487 && (MEM_P (source) ^ MEM_P (dest)));
9491 gcc_assert (REG_P (dest) || SUBREG_P (dest));
9492 rs6000_emit_le_vsx_load (dest, source, mode);
9496 if (!REG_P (source))
9497 source = force_reg (mode, source);
9498 rs6000_emit_le_vsx_store (dest, source, mode);
9502 /* Return whether a SFmode or SImode move can be done without converting one
9503 mode to another. This arrises when we have:
9505 (SUBREG:SF (REG:SI ...))
9506 (SUBREG:SI (REG:SF ...))
9508 and one of the values is in a floating point/vector register, where SFmode
9509 scalars are stored in DFmode format. */
9512 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9514 if (TARGET_ALLOW_SF_SUBREG)
9517 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9520 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9523 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9524 if (SUBREG_P (dest))
9526 rtx dest_subreg = SUBREG_REG (dest);
9527 rtx src_subreg = SUBREG_REG (src);
9528 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9535 /* Helper function to change moves with:
9537 (SUBREG:SF (REG:SI)) and
9538 (SUBREG:SI (REG:SF))
9540 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9541 values are stored as DFmode values in the VSX registers. We need to convert
9542 the bits before we can use a direct move or operate on the bits in the
9543 vector register as an integer type.
9545 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9548 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9550 if (TARGET_DIRECT_MOVE_64BIT && !reload_completed
9551 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9552 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9554 rtx inner_source = SUBREG_REG (source);
9555 machine_mode inner_mode = GET_MODE (inner_source);
9557 if (mode == SImode && inner_mode == SFmode)
9559 emit_insn (gen_movsi_from_sf (dest, inner_source));
9563 if (mode == SFmode && inner_mode == SImode)
9565 emit_insn (gen_movsf_from_si (dest, inner_source));
9573 /* Emit a move from SOURCE to DEST in mode MODE. */
9575 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9579 operands[1] = source;
9581 if (TARGET_DEBUG_ADDR)
9584 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9585 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9586 GET_MODE_NAME (mode),
9589 can_create_pseudo_p ());
9591 fprintf (stderr, "source:\n");
9595 /* Check that we get CONST_WIDE_INT only when we should. */
9596 if (CONST_WIDE_INT_P (operands[1])
9597 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9600 #ifdef HAVE_AS_GNU_ATTRIBUTE
9601 /* If we use a long double type, set the flags in .gnu_attribute that say
9602 what the long double type is. This is to allow the linker's warning
9603 message for the wrong long double to be useful, even if the function does
9604 not do a call (for example, doing a 128-bit add on power9 if the long
9605 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9606 used if they aren't the default long dobule type. */
9607 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9609 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9610 rs6000_passes_float = rs6000_passes_long_double = true;
9612 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9613 rs6000_passes_float = rs6000_passes_long_double = true;
9617 /* See if we need to special case SImode/SFmode SUBREG moves. */
9618 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9619 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9622 /* Check if GCC is setting up a block move that will end up using FP
9623 registers as temporaries. We must make sure this is acceptable. */
9624 if (MEM_P (operands[0])
9625 && MEM_P (operands[1])
9627 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9628 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9629 && ! (rs6000_slow_unaligned_access (SImode,
9630 (MEM_ALIGN (operands[0]) > 32
9631 ? 32 : MEM_ALIGN (operands[0])))
9632 || rs6000_slow_unaligned_access (SImode,
9633 (MEM_ALIGN (operands[1]) > 32
9634 ? 32 : MEM_ALIGN (operands[1]))))
9635 && ! MEM_VOLATILE_P (operands [0])
9636 && ! MEM_VOLATILE_P (operands [1]))
9638 emit_move_insn (adjust_address (operands[0], SImode, 0),
9639 adjust_address (operands[1], SImode, 0));
9640 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9641 adjust_address (copy_rtx (operands[1]), SImode, 4));
9645 if (can_create_pseudo_p () && MEM_P (operands[0])
9646 && !gpc_reg_operand (operands[1], mode))
9647 operands[1] = force_reg (mode, operands[1]);
9649 /* Recognize the case where operand[1] is a reference to thread-local
9650 data and load its address to a register. */
9651 if (tls_referenced_p (operands[1]))
9653 enum tls_model model;
9654 rtx tmp = operands[1];
9657 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9659 addend = XEXP (XEXP (tmp, 0), 1);
9660 tmp = XEXP (XEXP (tmp, 0), 0);
9663 gcc_assert (SYMBOL_REF_P (tmp));
9664 model = SYMBOL_REF_TLS_MODEL (tmp);
9665 gcc_assert (model != 0);
9667 tmp = rs6000_legitimize_tls_address (tmp, model);
9670 tmp = gen_rtx_PLUS (mode, tmp, addend);
9671 tmp = force_operand (tmp, operands[0]);
9676 /* 128-bit constant floating-point values on Darwin should really be loaded
9677 as two parts. However, this premature splitting is a problem when DFmode
9678 values can go into Altivec registers. */
9679 if (TARGET_MACHO && CONST_DOUBLE_P (operands[1]) && FLOAT128_IBM_P (mode)
9680 && !reg_addr[DFmode].scalar_in_vmx_p)
9682 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9683 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9685 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9686 GET_MODE_SIZE (DFmode)),
9687 simplify_gen_subreg (DFmode, operands[1], mode,
9688 GET_MODE_SIZE (DFmode)),
9693 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9694 p1:SD) if p1 is not of floating point class and p0 is spilled as
9695 we can have no analogous movsd_store for this. */
9696 if (lra_in_progress && mode == DDmode
9697 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9698 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9699 && SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))
9700 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9703 int regno = REGNO (SUBREG_REG (operands[1]));
9705 if (!HARD_REGISTER_NUM_P (regno))
9707 cl = reg_preferred_class (regno);
9708 regno = reg_renumber[regno];
9710 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9712 if (regno >= 0 && ! FP_REGNO_P (regno))
9715 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9716 operands[1] = SUBREG_REG (operands[1]);
9721 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9722 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9723 && (REG_P (operands[1])
9724 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))))
9726 int regno = reg_or_subregno (operands[1]);
9729 if (!HARD_REGISTER_NUM_P (regno))
9731 cl = reg_preferred_class (regno);
9732 gcc_assert (cl != NO_REGS);
9733 regno = reg_renumber[regno];
9735 regno = ira_class_hard_regs[cl][0];
9737 if (FP_REGNO_P (regno))
9739 if (GET_MODE (operands[0]) != DDmode)
9740 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
9741 emit_insn (gen_movsd_store (operands[0], operands[1]));
9743 else if (INT_REGNO_P (regno))
9744 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9749 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9750 p:DD)) if p0 is not of floating point class and p1 is spilled as
9751 we can have no analogous movsd_load for this. */
9752 if (lra_in_progress && mode == DDmode
9753 && SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))
9754 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
9755 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9756 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9759 int regno = REGNO (SUBREG_REG (operands[0]));
9761 if (!HARD_REGISTER_NUM_P (regno))
9763 cl = reg_preferred_class (regno);
9764 regno = reg_renumber[regno];
9766 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
9768 if (regno >= 0 && ! FP_REGNO_P (regno))
9771 operands[0] = SUBREG_REG (operands[0]);
9772 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
9777 && (REG_P (operands[0])
9778 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
9779 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9780 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9782 int regno = reg_or_subregno (operands[0]);
9785 if (!HARD_REGISTER_NUM_P (regno))
9787 cl = reg_preferred_class (regno);
9788 gcc_assert (cl != NO_REGS);
9789 regno = reg_renumber[regno];
9791 regno = ira_class_hard_regs[cl][0];
9793 if (FP_REGNO_P (regno))
9795 if (GET_MODE (operands[1]) != DDmode)
9796 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
9797 emit_insn (gen_movsd_load (operands[0], operands[1]));
9799 else if (INT_REGNO_P (regno))
9800 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9806 /* FIXME: In the long term, this switch statement should go away
9807 and be replaced by a sequence of tests based on things like
9813 if (CONSTANT_P (operands[1])
9814 && !CONST_INT_P (operands[1]))
9815 operands[1] = force_const_mem (mode, operands[1]);
9822 if (FLOAT128_2REG_P (mode))
9823 rs6000_eliminate_indexed_memrefs (operands);
9830 if (CONSTANT_P (operands[1])
9831 && ! easy_fp_constant (operands[1], mode))
9832 operands[1] = force_const_mem (mode, operands[1]);
9842 if (CONSTANT_P (operands[1])
9843 && !easy_vector_constant (operands[1], mode))
9844 operands[1] = force_const_mem (mode, operands[1]);
9849 /* Use default pattern for address of ELF small data */
9852 && DEFAULT_ABI == ABI_V4
9853 && (SYMBOL_REF_P (operands[1])
9854 || GET_CODE (operands[1]) == CONST)
9855 && small_data_operand (operands[1], mode))
9857 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9861 if (DEFAULT_ABI == ABI_V4
9862 && mode == Pmode && mode == SImode
9863 && flag_pic == 1 && got_operand (operands[1], mode))
9865 emit_insn (gen_movsi_got (operands[0], operands[1]));
9869 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
9873 && CONSTANT_P (operands[1])
9874 && GET_CODE (operands[1]) != HIGH
9875 && !CONST_INT_P (operands[1]))
9877 rtx target = (!can_create_pseudo_p ()
9879 : gen_reg_rtx (mode));
9881 /* If this is a function address on -mcall-aixdesc,
9882 convert it to the address of the descriptor. */
9883 if (DEFAULT_ABI == ABI_AIX
9884 && SYMBOL_REF_P (operands[1])
9885 && XSTR (operands[1], 0)[0] == '.')
9887 const char *name = XSTR (operands[1], 0);
9889 while (*name == '.')
9891 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
9892 CONSTANT_POOL_ADDRESS_P (new_ref)
9893 = CONSTANT_POOL_ADDRESS_P (operands[1]);
9894 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
9895 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
9896 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
9897 operands[1] = new_ref;
9900 if (DEFAULT_ABI == ABI_DARWIN)
9903 if (MACHO_DYNAMIC_NO_PIC_P)
9905 /* Take care of any required data indirection. */
9906 operands[1] = rs6000_machopic_legitimize_pic_address (
9907 operands[1], mode, operands[0]);
9908 if (operands[0] != operands[1])
9909 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9913 emit_insn (gen_macho_high (target, operands[1]));
9914 emit_insn (gen_macho_low (operands[0], target, operands[1]));
9918 emit_insn (gen_elf_high (target, operands[1]));
9919 emit_insn (gen_elf_low (operands[0], target, operands[1]));
9923 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9924 and we have put it in the TOC, we just need to make a TOC-relative
9927 && SYMBOL_REF_P (operands[1])
9928 && use_toc_relative_ref (operands[1], mode))
9929 operands[1] = create_TOC_reference (operands[1], operands[0]);
9930 else if (mode == Pmode
9931 && CONSTANT_P (operands[1])
9932 && GET_CODE (operands[1]) != HIGH
9933 && ((REG_P (operands[0])
9934 && FP_REGNO_P (REGNO (operands[0])))
9935 || !CONST_INT_P (operands[1])
9936 || (num_insns_constant (operands[1], mode)
9937 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
9938 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
9939 && (TARGET_CMODEL == CMODEL_SMALL
9940 || can_create_pseudo_p ()
9941 || (REG_P (operands[0])
9942 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
9946 /* Darwin uses a special PIC legitimizer. */
9947 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
9950 rs6000_machopic_legitimize_pic_address (operands[1], mode,
9952 if (operands[0] != operands[1])
9953 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9958 /* If we are to limit the number of things we put in the TOC and
9959 this is a symbol plus a constant we can add in one insn,
9960 just put the symbol in the TOC and add the constant. */
9961 if (GET_CODE (operands[1]) == CONST
9962 && TARGET_NO_SUM_IN_TOC
9963 && GET_CODE (XEXP (operands[1], 0)) == PLUS
9964 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
9965 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
9966 || SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
9967 && ! side_effects_p (operands[0]))
9970 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
9971 rtx other = XEXP (XEXP (operands[1], 0), 1);
9973 sym = force_reg (mode, sym);
9974 emit_insn (gen_add3_insn (operands[0], sym, other));
9978 operands[1] = force_const_mem (mode, operands[1]);
9981 && SYMBOL_REF_P (XEXP (operands[1], 0))
9982 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
9984 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
9986 operands[1] = gen_const_mem (mode, tocref);
9987 set_mem_alias_set (operands[1], get_TOC_alias_set ());
9993 if (!VECTOR_MEM_VSX_P (TImode))
9994 rs6000_eliminate_indexed_memrefs (operands);
9998 rs6000_eliminate_indexed_memrefs (operands);
10002 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10005 /* Above, we may have called force_const_mem which may have returned
10006 an invalid address. If we can, fix this up; otherwise, reload will
10007 have to deal with it. */
10008 if (MEM_P (operands[1]))
10009 operands[1] = validize_mem (operands[1]);
10011 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10014 /* Nonzero if we can use a floating-point register to pass this arg. */
10015 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10016 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10017 && (CUM)->fregno <= FP_ARG_MAX_REG \
10018 && TARGET_HARD_FLOAT)
10020 /* Nonzero if we can use an AltiVec register to pass this arg. */
10021 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10022 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10023 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10024 && TARGET_ALTIVEC_ABI \
10027 /* Walk down the type tree of TYPE counting consecutive base elements.
10028 If *MODEP is VOIDmode, then set it to the first valid floating point
10029 or vector type. If a non-floating point or vector type is found, or
10030 if a floating point or vector type that doesn't match a non-VOIDmode
10031 *MODEP is found, then return -1, otherwise return the count in the
10035 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10038 HOST_WIDE_INT size;
10040 switch (TREE_CODE (type))
10043 mode = TYPE_MODE (type);
10044 if (!SCALAR_FLOAT_MODE_P (mode))
10047 if (*modep == VOIDmode)
10050 if (*modep == mode)
10056 mode = TYPE_MODE (TREE_TYPE (type));
10057 if (!SCALAR_FLOAT_MODE_P (mode))
10060 if (*modep == VOIDmode)
10063 if (*modep == mode)
10069 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10072 /* Use V4SImode as representative of all 128-bit vector types. */
10073 size = int_size_in_bytes (type);
10083 if (*modep == VOIDmode)
10086 /* Vector modes are considered to be opaque: two vectors are
10087 equivalent for the purposes of being homogeneous aggregates
10088 if they are the same size. */
10089 if (*modep == mode)
10097 tree index = TYPE_DOMAIN (type);
10099 /* Can't handle incomplete types nor sizes that are not
10101 if (!COMPLETE_TYPE_P (type)
10102 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10105 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10108 || !TYPE_MAX_VALUE (index)
10109 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10110 || !TYPE_MIN_VALUE (index)
10111 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10115 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10116 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10118 /* There must be no padding. */
10119 if (wi::to_wide (TYPE_SIZE (type))
10120 != count * GET_MODE_BITSIZE (*modep))
10132 /* Can't handle incomplete types nor sizes that are not
10134 if (!COMPLETE_TYPE_P (type)
10135 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10138 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10140 if (TREE_CODE (field) != FIELD_DECL)
10143 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10146 count += sub_count;
10149 /* There must be no padding. */
10150 if (wi::to_wide (TYPE_SIZE (type))
10151 != count * GET_MODE_BITSIZE (*modep))
10158 case QUAL_UNION_TYPE:
10160 /* These aren't very interesting except in a degenerate case. */
10165 /* Can't handle incomplete types nor sizes that are not
10167 if (!COMPLETE_TYPE_P (type)
10168 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10171 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10173 if (TREE_CODE (field) != FIELD_DECL)
10176 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10179 count = count > sub_count ? count : sub_count;
10182 /* There must be no padding. */
10183 if (wi::to_wide (TYPE_SIZE (type))
10184 != count * GET_MODE_BITSIZE (*modep))
10197 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10198 float or vector aggregate that shall be passed in FP/vector registers
10199 according to the ELFv2 ABI, return the homogeneous element mode in
10200 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10202 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10205 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10206 machine_mode *elt_mode,
10209 /* Note that we do not accept complex types at the top level as
10210 homogeneous aggregates; these types are handled via the
10211 targetm.calls.split_complex_arg mechanism. Complex types
10212 can be elements of homogeneous aggregates, however. */
10213 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10214 && AGGREGATE_TYPE_P (type))
10216 machine_mode field_mode = VOIDmode;
10217 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10219 if (field_count > 0)
10221 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10222 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10224 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10225 up to AGGR_ARG_NUM_REG registers. */
10226 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10229 *elt_mode = field_mode;
10231 *n_elts = field_count;
10244 /* Return a nonzero value to say to return the function value in
10245 memory, just as large structures are always returned. TYPE will be
10246 the data type of the value, and FNTYPE will be the type of the
10247 function doing the returning, or @code{NULL} for libcalls.
10249 The AIX ABI for the RS/6000 specifies that all structures are
10250 returned in memory. The Darwin ABI does the same.
10252 For the Darwin 64 Bit ABI, a function result can be returned in
10253 registers or in memory, depending on the size of the return data
10254 type. If it is returned in registers, the value occupies the same
10255 registers as it would if it were the first and only function
10256 argument. Otherwise, the function places its result in memory at
10257 the location pointed to by GPR3.
10259 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10260 but a draft put them in memory, and GCC used to implement the draft
10261 instead of the final standard. Therefore, aix_struct_return
10262 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10263 compatibility can change DRAFT_V4_STRUCT_RET to override the
10264 default, and -m switches get the final word. See
10265 rs6000_option_override_internal for more details.
10267 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10268 long double support is enabled. These values are returned in memory.
10270 int_size_in_bytes returns -1 for variable size objects, which go in
10271 memory always. The cast to unsigned makes -1 > 8. */
10274 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10276 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10278 && rs6000_darwin64_abi
10279 && TREE_CODE (type) == RECORD_TYPE
10280 && int_size_in_bytes (type) > 0)
10282 CUMULATIVE_ARGS valcum;
10286 valcum.fregno = FP_ARG_MIN_REG;
10287 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10288 /* Do a trial code generation as if this were going to be passed
10289 as an argument; if any part goes in memory, we return NULL. */
10290 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10293 /* Otherwise fall through to more conventional ABI rules. */
10296 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10297 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10301 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10302 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10303 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10306 if (AGGREGATE_TYPE_P (type)
10307 && (aix_struct_return
10308 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10311 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10312 modes only exist for GCC vector types if -maltivec. */
10313 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10314 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10317 /* Return synthetic vectors in memory. */
10318 if (TREE_CODE (type) == VECTOR_TYPE
10319 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10321 static bool warned_for_return_big_vectors = false;
10322 if (!warned_for_return_big_vectors)
10324 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10325 "non-standard ABI extension with no compatibility "
10327 warned_for_return_big_vectors = true;
10332 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10333 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10339 /* Specify whether values returned in registers should be at the most
10340 significant end of a register. We want aggregates returned by
10341 value to match the way aggregates are passed to functions. */
10344 rs6000_return_in_msb (const_tree valtype)
10346 return (DEFAULT_ABI == ABI_ELFv2
10347 && BYTES_BIG_ENDIAN
10348 && AGGREGATE_TYPE_P (valtype)
10349 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10353 #ifdef HAVE_AS_GNU_ATTRIBUTE
10354 /* Return TRUE if a call to function FNDECL may be one that
10355 potentially affects the function calling ABI of the object file. */
10358 call_ABI_of_interest (tree fndecl)
10360 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10362 struct cgraph_node *c_node;
10364 /* Libcalls are always interesting. */
10365 if (fndecl == NULL_TREE)
10368 /* Any call to an external function is interesting. */
10369 if (DECL_EXTERNAL (fndecl))
10372 /* Interesting functions that we are emitting in this object file. */
10373 c_node = cgraph_node::get (fndecl);
10374 c_node = c_node->ultimate_alias_target ();
10375 return !c_node->only_called_directly_p ();
10381 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10382 for a call to a function whose data type is FNTYPE.
10383 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10385 For incoming args we set the number of arguments in the prototype large
10386 so we never return a PARALLEL. */
10389 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10390 rtx libname ATTRIBUTE_UNUSED, int incoming,
10391 int libcall, int n_named_args,
10393 machine_mode return_mode ATTRIBUTE_UNUSED)
10395 static CUMULATIVE_ARGS zero_cumulative;
10397 *cum = zero_cumulative;
10399 cum->fregno = FP_ARG_MIN_REG;
10400 cum->vregno = ALTIVEC_ARG_MIN_REG;
10401 cum->prototype = (fntype && prototype_p (fntype));
10402 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10403 ? CALL_LIBCALL : CALL_NORMAL);
10404 cum->sysv_gregno = GP_ARG_MIN_REG;
10405 cum->stdarg = stdarg_p (fntype);
10406 cum->libcall = libcall;
10408 cum->nargs_prototype = 0;
10409 if (incoming || cum->prototype)
10410 cum->nargs_prototype = n_named_args;
10412 /* Check for a longcall attribute. */
10413 if ((!fntype && rs6000_default_long_calls)
10415 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10416 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10417 cum->call_cookie |= CALL_LONG;
10418 else if (DEFAULT_ABI != ABI_DARWIN)
10420 bool is_local = (fndecl
10421 && !DECL_EXTERNAL (fndecl)
10422 && !DECL_WEAK (fndecl)
10423 && (*targetm.binds_local_p) (fndecl));
10429 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
10430 cum->call_cookie |= CALL_LONG;
10435 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
10436 cum->call_cookie |= CALL_LONG;
10440 if (TARGET_DEBUG_ARG)
10442 fprintf (stderr, "\ninit_cumulative_args:");
10445 tree ret_type = TREE_TYPE (fntype);
10446 fprintf (stderr, " ret code = %s,",
10447 get_tree_code_name (TREE_CODE (ret_type)));
10450 if (cum->call_cookie & CALL_LONG)
10451 fprintf (stderr, " longcall,");
10453 fprintf (stderr, " proto = %d, nargs = %d\n",
10454 cum->prototype, cum->nargs_prototype);
10457 #ifdef HAVE_AS_GNU_ATTRIBUTE
10458 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10460 cum->escapes = call_ABI_of_interest (fndecl);
10467 return_type = TREE_TYPE (fntype);
10468 return_mode = TYPE_MODE (return_type);
10471 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10473 if (return_type != NULL)
10475 if (TREE_CODE (return_type) == RECORD_TYPE
10476 && TYPE_TRANSPARENT_AGGR (return_type))
10478 return_type = TREE_TYPE (first_field (return_type));
10479 return_mode = TYPE_MODE (return_type);
10481 if (AGGREGATE_TYPE_P (return_type)
10482 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10484 rs6000_returns_struct = true;
10486 if (SCALAR_FLOAT_MODE_P (return_mode))
10488 rs6000_passes_float = true;
10489 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10490 && (FLOAT128_IBM_P (return_mode)
10491 || FLOAT128_IEEE_P (return_mode)
10492 || (return_type != NULL
10493 && (TYPE_MAIN_VARIANT (return_type)
10494 == long_double_type_node))))
10495 rs6000_passes_long_double = true;
10497 /* Note if we passed or return a IEEE 128-bit type. We changed
10498 the mangling for these types, and we may need to make an alias
10499 with the old mangling. */
10500 if (FLOAT128_IEEE_P (return_mode))
10501 rs6000_passes_ieee128 = true;
10503 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10504 rs6000_passes_vector = true;
10511 && TARGET_ALTIVEC_ABI
10512 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10514 error ("cannot return value in vector register because"
10515 " altivec instructions are disabled, use %qs"
10516 " to enable them", "-maltivec");
10520 /* The mode the ABI uses for a word. This is not the same as word_mode
10521 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10523 static scalar_int_mode
10524 rs6000_abi_word_mode (void)
10526 return TARGET_32BIT ? SImode : DImode;
10529 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10531 rs6000_offload_options (void)
10534 return xstrdup ("-foffload-abi=lp64");
10536 return xstrdup ("-foffload-abi=ilp32");
10539 /* On rs6000, function arguments are promoted, as are function return
10542 static machine_mode
10543 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10545 int *punsignedp ATTRIBUTE_UNUSED,
10548 PROMOTE_MODE (mode, *punsignedp, type);
10553 /* Return true if TYPE must be passed on the stack and not in registers. */
10556 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10558 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10559 return must_pass_in_stack_var_size (mode, type);
10561 return must_pass_in_stack_var_size_or_pad (mode, type);
10565 is_complex_IBM_long_double (machine_mode mode)
10567 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10570 /* Whether ABI_V4 passes MODE args to a function in floating point
10574 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10576 if (!TARGET_HARD_FLOAT)
10578 if (mode == DFmode)
10580 if (mode == SFmode && named)
10582 /* ABI_V4 passes complex IBM long double in 8 gprs.
10583 Stupid, but we can't change the ABI now. */
10584 if (is_complex_IBM_long_double (mode))
10586 if (FLOAT128_2REG_P (mode))
10588 if (DECIMAL_FLOAT_MODE_P (mode))
10593 /* Implement TARGET_FUNCTION_ARG_PADDING.
10595 For the AIX ABI structs are always stored left shifted in their
10598 static pad_direction
10599 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10601 #ifndef AGGREGATE_PADDING_FIXED
10602 #define AGGREGATE_PADDING_FIXED 0
10604 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10605 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10608 if (!AGGREGATE_PADDING_FIXED)
10610 /* GCC used to pass structures of the same size as integer types as
10611 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10612 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10613 passed padded downward, except that -mstrict-align further
10614 muddied the water in that multi-component structures of 2 and 4
10615 bytes in size were passed padded upward.
10617 The following arranges for best compatibility with previous
10618 versions of gcc, but removes the -mstrict-align dependency. */
10619 if (BYTES_BIG_ENDIAN)
10621 HOST_WIDE_INT size = 0;
10623 if (mode == BLKmode)
10625 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10626 size = int_size_in_bytes (type);
10629 size = GET_MODE_SIZE (mode);
10631 if (size == 1 || size == 2 || size == 4)
10632 return PAD_DOWNWARD;
10637 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10639 if (type != 0 && AGGREGATE_TYPE_P (type))
10643 /* Fall back to the default. */
10644 return default_function_arg_padding (mode, type);
10647 /* If defined, a C expression that gives the alignment boundary, in bits,
10648 of an argument with the specified mode and type. If it is not defined,
10649 PARM_BOUNDARY is used for all arguments.
10651 V.4 wants long longs and doubles to be double word aligned. Just
10652 testing the mode size is a boneheaded way to do this as it means
10653 that other types such as complex int are also double word aligned.
10654 However, we're stuck with this because changing the ABI might break
10655 existing library interfaces.
10657 Quadword align Altivec/VSX vectors.
10658 Quadword align large synthetic vector types. */
10660 static unsigned int
10661 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10663 machine_mode elt_mode;
10666 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10668 if (DEFAULT_ABI == ABI_V4
10669 && (GET_MODE_SIZE (mode) == 8
10670 || (TARGET_HARD_FLOAT
10671 && !is_complex_IBM_long_double (mode)
10672 && FLOAT128_2REG_P (mode))))
10674 else if (FLOAT128_VECTOR_P (mode))
10676 else if (type && TREE_CODE (type) == VECTOR_TYPE
10677 && int_size_in_bytes (type) >= 8
10678 && int_size_in_bytes (type) < 16)
10680 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10681 || (type && TREE_CODE (type) == VECTOR_TYPE
10682 && int_size_in_bytes (type) >= 16))
10685 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10686 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10687 -mcompat-align-parm is used. */
10688 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10689 || DEFAULT_ABI == ABI_ELFv2)
10690 && type && TYPE_ALIGN (type) > 64)
10692 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10693 or homogeneous float/vector aggregates here. We already handled
10694 vector aggregates above, but still need to check for float here. */
10695 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10696 && !SCALAR_FLOAT_MODE_P (elt_mode));
10698 /* We used to check for BLKmode instead of the above aggregate type
10699 check. Warn when this results in any difference to the ABI. */
10700 if (aggregate_p != (mode == BLKmode))
10702 static bool warned;
10703 if (!warned && warn_psabi)
10706 inform (input_location,
10707 "the ABI of passing aggregates with %d-byte alignment"
10708 " has changed in GCC 5",
10709 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10717 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10718 implement the "aggregate type" check as a BLKmode check here; this
10719 means certain aggregate types are in fact not aligned. */
10720 if (TARGET_MACHO && rs6000_darwin64_abi
10722 && type && TYPE_ALIGN (type) > 64)
10725 return PARM_BOUNDARY;
10728 /* The offset in words to the start of the parameter save area. */
10730 static unsigned int
10731 rs6000_parm_offset (void)
10733 return (DEFAULT_ABI == ABI_V4 ? 2
10734 : DEFAULT_ABI == ABI_ELFv2 ? 4
10738 /* For a function parm of MODE and TYPE, return the starting word in
10739 the parameter area. NWORDS of the parameter area are already used. */
10741 static unsigned int
10742 rs6000_parm_start (machine_mode mode, const_tree type,
10743 unsigned int nwords)
10745 unsigned int align;
10747 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
10748 return nwords + (-(rs6000_parm_offset () + nwords) & align);
10751 /* Compute the size (in words) of a function argument. */
10753 static unsigned long
10754 rs6000_arg_size (machine_mode mode, const_tree type)
10756 unsigned long size;
10758 if (mode != BLKmode)
10759 size = GET_MODE_SIZE (mode);
10761 size = int_size_in_bytes (type);
10764 return (size + 3) >> 2;
10766 return (size + 7) >> 3;
10769 /* Use this to flush pending int fields. */
10772 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
10773 HOST_WIDE_INT bitpos, int final)
10775 unsigned int startbit, endbit;
10776 int intregs, intoffset;
10778 /* Handle the situations where a float is taking up the first half
10779 of the GPR, and the other half is empty (typically due to
10780 alignment restrictions). We can detect this by a 8-byte-aligned
10781 int field, or by seeing that this is the final flush for this
10782 argument. Count the word and continue on. */
10783 if (cum->floats_in_gpr == 1
10784 && (cum->intoffset % 64 == 0
10785 || (cum->intoffset == -1 && final)))
10788 cum->floats_in_gpr = 0;
10791 if (cum->intoffset == -1)
10794 intoffset = cum->intoffset;
10795 cum->intoffset = -1;
10796 cum->floats_in_gpr = 0;
10798 if (intoffset % BITS_PER_WORD != 0)
10800 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
10801 if (!int_mode_for_size (bits, 0).exists ())
10803 /* We couldn't find an appropriate mode, which happens,
10804 e.g., in packed structs when there are 3 bytes to load.
10805 Back intoffset back to the beginning of the word in this
10807 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
10811 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
10812 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
10813 intregs = (endbit - startbit) / BITS_PER_WORD;
10814 cum->words += intregs;
10815 /* words should be unsigned. */
10816 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
10818 int pad = (endbit/BITS_PER_WORD) - cum->words;
10823 /* The darwin64 ABI calls for us to recurse down through structs,
10824 looking for elements passed in registers. Unfortunately, we have
10825 to track int register count here also because of misalignments
10826 in powerpc alignment mode. */
10829 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
10831 HOST_WIDE_INT startbitpos)
10835 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10836 if (TREE_CODE (f) == FIELD_DECL)
10838 HOST_WIDE_INT bitpos = startbitpos;
10839 tree ftype = TREE_TYPE (f);
10841 if (ftype == error_mark_node)
10843 mode = TYPE_MODE (ftype);
10845 if (DECL_SIZE (f) != 0
10846 && tree_fits_uhwi_p (bit_position (f)))
10847 bitpos += int_bit_position (f);
10849 /* ??? FIXME: else assume zero offset. */
10851 if (TREE_CODE (ftype) == RECORD_TYPE)
10852 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
10853 else if (USE_FP_FOR_ARG_P (cum, mode))
10855 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
10856 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10857 cum->fregno += n_fpregs;
10858 /* Single-precision floats present a special problem for
10859 us, because they are smaller than an 8-byte GPR, and so
10860 the structure-packing rules combined with the standard
10861 varargs behavior mean that we want to pack float/float
10862 and float/int combinations into a single register's
10863 space. This is complicated by the arg advance flushing,
10864 which works on arbitrarily large groups of int-type
10866 if (mode == SFmode)
10868 if (cum->floats_in_gpr == 1)
10870 /* Two floats in a word; count the word and reset
10871 the float count. */
10873 cum->floats_in_gpr = 0;
10875 else if (bitpos % 64 == 0)
10877 /* A float at the beginning of an 8-byte word;
10878 count it and put off adjusting cum->words until
10879 we see if a arg advance flush is going to do it
10881 cum->floats_in_gpr++;
10885 /* The float is at the end of a word, preceded
10886 by integer fields, so the arg advance flush
10887 just above has already set cum->words and
10888 everything is taken care of. */
10892 cum->words += n_fpregs;
10894 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10896 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10900 else if (cum->intoffset == -1)
10901 cum->intoffset = bitpos;
10905 /* Check for an item that needs to be considered specially under the darwin 64
10906 bit ABI. These are record types where the mode is BLK or the structure is
10907 8 bytes in size. */
10909 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
10911 return rs6000_darwin64_abi
10912 && ((mode == BLKmode
10913 && TREE_CODE (type) == RECORD_TYPE
10914 && int_size_in_bytes (type) > 0)
10915 || (type && TREE_CODE (type) == RECORD_TYPE
10916 && int_size_in_bytes (type) == 8)) ? 1 : 0;
10919 /* Update the data in CUM to advance over an argument
10920 of mode MODE and data type TYPE.
10921 (TYPE is null for libcalls where that information may not be available.)
10923 Note that for args passed by reference, function_arg will be called
10924 with MODE and TYPE set to that of the pointer to the arg, not the arg
10928 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
10929 const_tree type, bool named, int depth)
10931 machine_mode elt_mode;
10934 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10936 /* Only tick off an argument if we're not recursing. */
10938 cum->nargs_prototype--;
10940 #ifdef HAVE_AS_GNU_ATTRIBUTE
10941 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
10944 if (SCALAR_FLOAT_MODE_P (mode))
10946 rs6000_passes_float = true;
10947 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10948 && (FLOAT128_IBM_P (mode)
10949 || FLOAT128_IEEE_P (mode)
10951 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
10952 rs6000_passes_long_double = true;
10954 /* Note if we passed or return a IEEE 128-bit type. We changed the
10955 mangling for these types, and we may need to make an alias with
10956 the old mangling. */
10957 if (FLOAT128_IEEE_P (mode))
10958 rs6000_passes_ieee128 = true;
10960 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
10961 rs6000_passes_vector = true;
10965 if (TARGET_ALTIVEC_ABI
10966 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10967 || (type && TREE_CODE (type) == VECTOR_TYPE
10968 && int_size_in_bytes (type) == 16)))
10970 bool stack = false;
10972 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10974 cum->vregno += n_elts;
10976 if (!TARGET_ALTIVEC)
10977 error ("cannot pass argument in vector register because"
10978 " altivec instructions are disabled, use %qs"
10979 " to enable them", "-maltivec");
10981 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
10982 even if it is going to be passed in a vector register.
10983 Darwin does the same for variable-argument functions. */
10984 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10986 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
10996 /* Vector parameters must be 16-byte aligned. In 32-bit
10997 mode this means we need to take into account the offset
10998 to the parameter save area. In 64-bit mode, they just
10999 have to start on an even word, since the parameter save
11000 area is 16-byte aligned. */
11002 align = -(rs6000_parm_offset () + cum->words) & 3;
11004 align = cum->words & 1;
11005 cum->words += align + rs6000_arg_size (mode, type);
11007 if (TARGET_DEBUG_ARG)
11009 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11010 cum->words, align);
11011 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11012 cum->nargs_prototype, cum->prototype,
11013 GET_MODE_NAME (mode));
11017 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11019 int size = int_size_in_bytes (type);
11020 /* Variable sized types have size == -1 and are
11021 treated as if consisting entirely of ints.
11022 Pad to 16 byte boundary if needed. */
11023 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11024 && (cum->words % 2) != 0)
11026 /* For varargs, we can just go up by the size of the struct. */
11028 cum->words += (size + 7) / 8;
11031 /* It is tempting to say int register count just goes up by
11032 sizeof(type)/8, but this is wrong in a case such as
11033 { int; double; int; } [powerpc alignment]. We have to
11034 grovel through the fields for these too. */
11035 cum->intoffset = 0;
11036 cum->floats_in_gpr = 0;
11037 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11038 rs6000_darwin64_record_arg_advance_flush (cum,
11039 size * BITS_PER_UNIT, 1);
11041 if (TARGET_DEBUG_ARG)
11043 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11044 cum->words, TYPE_ALIGN (type), size);
11046 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11047 cum->nargs_prototype, cum->prototype,
11048 GET_MODE_NAME (mode));
11051 else if (DEFAULT_ABI == ABI_V4)
11053 if (abi_v4_pass_in_fpr (mode, named))
11055 /* _Decimal128 must use an even/odd register pair. This assumes
11056 that the register number is odd when fregno is odd. */
11057 if (mode == TDmode && (cum->fregno % 2) == 1)
11060 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11061 <= FP_ARG_V4_MAX_REG)
11062 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11065 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11066 if (mode == DFmode || FLOAT128_IBM_P (mode)
11067 || mode == DDmode || mode == TDmode)
11068 cum->words += cum->words & 1;
11069 cum->words += rs6000_arg_size (mode, type);
11074 int n_words = rs6000_arg_size (mode, type);
11075 int gregno = cum->sysv_gregno;
11077 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11078 As does any other 2 word item such as complex int due to a
11079 historical mistake. */
11081 gregno += (1 - gregno) & 1;
11083 /* Multi-reg args are not split between registers and stack. */
11084 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11086 /* Long long is aligned on the stack. So are other 2 word
11087 items such as complex int due to a historical mistake. */
11089 cum->words += cum->words & 1;
11090 cum->words += n_words;
11093 /* Note: continuing to accumulate gregno past when we've started
11094 spilling to the stack indicates the fact that we've started
11095 spilling to the stack to expand_builtin_saveregs. */
11096 cum->sysv_gregno = gregno + n_words;
11099 if (TARGET_DEBUG_ARG)
11101 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11102 cum->words, cum->fregno);
11103 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11104 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11105 fprintf (stderr, "mode = %4s, named = %d\n",
11106 GET_MODE_NAME (mode), named);
11111 int n_words = rs6000_arg_size (mode, type);
11112 int start_words = cum->words;
11113 int align_words = rs6000_parm_start (mode, type, start_words);
11115 cum->words = align_words + n_words;
11117 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11119 /* _Decimal128 must be passed in an even/odd float register pair.
11120 This assumes that the register number is odd when fregno is
11122 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11124 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11127 if (TARGET_DEBUG_ARG)
11129 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11130 cum->words, cum->fregno);
11131 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11132 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11133 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11134 named, align_words - start_words, depth);
11140 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11141 const_tree type, bool named)
11143 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11147 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11148 structure between cum->intoffset and bitpos to integer registers. */
11151 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11152 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11155 unsigned int regno;
11156 unsigned int startbit, endbit;
11157 int this_regno, intregs, intoffset;
11160 if (cum->intoffset == -1)
11163 intoffset = cum->intoffset;
11164 cum->intoffset = -1;
11166 /* If this is the trailing part of a word, try to only load that
11167 much into the register. Otherwise load the whole register. Note
11168 that in the latter case we may pick up unwanted bits. It's not a
11169 problem at the moment but may wish to revisit. */
11171 if (intoffset % BITS_PER_WORD != 0)
11173 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11174 if (!int_mode_for_size (bits, 0).exists (&mode))
11176 /* We couldn't find an appropriate mode, which happens,
11177 e.g., in packed structs when there are 3 bytes to load.
11178 Back intoffset back to the beginning of the word in this
11180 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11187 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11188 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11189 intregs = (endbit - startbit) / BITS_PER_WORD;
11190 this_regno = cum->words + intoffset / BITS_PER_WORD;
11192 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11193 cum->use_stack = 1;
11195 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11199 intoffset /= BITS_PER_UNIT;
11202 regno = GP_ARG_MIN_REG + this_regno;
11203 reg = gen_rtx_REG (mode, regno);
11205 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11208 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11212 while (intregs > 0);
11215 /* Recursive workhorse for the following. */
11218 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11219 HOST_WIDE_INT startbitpos, rtx rvec[],
11224 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11225 if (TREE_CODE (f) == FIELD_DECL)
11227 HOST_WIDE_INT bitpos = startbitpos;
11228 tree ftype = TREE_TYPE (f);
11230 if (ftype == error_mark_node)
11232 mode = TYPE_MODE (ftype);
11234 if (DECL_SIZE (f) != 0
11235 && tree_fits_uhwi_p (bit_position (f)))
11236 bitpos += int_bit_position (f);
11238 /* ??? FIXME: else assume zero offset. */
11240 if (TREE_CODE (ftype) == RECORD_TYPE)
11241 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11242 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11244 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11248 case E_SCmode: mode = SFmode; break;
11249 case E_DCmode: mode = DFmode; break;
11250 case E_TCmode: mode = TFmode; break;
11254 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11255 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11257 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11258 && (mode == TFmode || mode == TDmode));
11259 /* Long double or _Decimal128 split over regs and memory. */
11260 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11264 = gen_rtx_EXPR_LIST (VOIDmode,
11265 gen_rtx_REG (mode, cum->fregno++),
11266 GEN_INT (bitpos / BITS_PER_UNIT));
11267 if (FLOAT128_2REG_P (mode))
11270 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11272 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11274 = gen_rtx_EXPR_LIST (VOIDmode,
11275 gen_rtx_REG (mode, cum->vregno++),
11276 GEN_INT (bitpos / BITS_PER_UNIT));
11278 else if (cum->intoffset == -1)
11279 cum->intoffset = bitpos;
11283 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11284 the register(s) to be used for each field and subfield of a struct
11285 being passed by value, along with the offset of where the
11286 register's value may be found in the block. FP fields go in FP
11287 register, vector fields go in vector registers, and everything
11288 else goes in int registers, packed as in memory.
11290 This code is also used for function return values. RETVAL indicates
11291 whether this is the case.
11293 Much of this is taken from the SPARC V9 port, which has a similar
11294 calling convention. */
11297 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11298 bool named, bool retval)
11300 rtx rvec[FIRST_PSEUDO_REGISTER];
11301 int k = 1, kbase = 1;
11302 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11303 /* This is a copy; modifications are not visible to our caller. */
11304 CUMULATIVE_ARGS copy_cum = *orig_cum;
11305 CUMULATIVE_ARGS *cum = ©_cum;
11307 /* Pad to 16 byte boundary if needed. */
11308 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11309 && (cum->words % 2) != 0)
11312 cum->intoffset = 0;
11313 cum->use_stack = 0;
11314 cum->named = named;
11316 /* Put entries into rvec[] for individual FP and vector fields, and
11317 for the chunks of memory that go in int regs. Note we start at
11318 element 1; 0 is reserved for an indication of using memory, and
11319 may or may not be filled in below. */
11320 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11321 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11323 /* If any part of the struct went on the stack put all of it there.
11324 This hack is because the generic code for
11325 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11326 parts of the struct are not at the beginning. */
11327 if (cum->use_stack)
11330 return NULL_RTX; /* doesn't go in registers at all */
11332 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11334 if (k > 1 || cum->use_stack)
11335 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11340 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11343 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11348 rtx rvec[GP_ARG_NUM_REG + 1];
11350 if (align_words >= GP_ARG_NUM_REG)
11353 n_units = rs6000_arg_size (mode, type);
11355 /* Optimize the simple case where the arg fits in one gpr, except in
11356 the case of BLKmode due to assign_parms assuming that registers are
11357 BITS_PER_WORD wide. */
11359 || (n_units == 1 && mode != BLKmode))
11360 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11363 if (align_words + n_units > GP_ARG_NUM_REG)
11364 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11365 using a magic NULL_RTX component.
11366 This is not strictly correct. Only some of the arg belongs in
11367 memory, not all of it. However, the normal scheme using
11368 function_arg_partial_nregs can result in unusual subregs, eg.
11369 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11370 store the whole arg to memory is often more efficient than code
11371 to store pieces, and we know that space is available in the right
11372 place for the whole arg. */
11373 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11378 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11379 rtx off = GEN_INT (i++ * 4);
11380 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11382 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11384 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11387 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11388 but must also be copied into the parameter save area starting at
11389 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11390 to the GPRs and/or memory. Return the number of elements used. */
11393 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11394 int align_words, rtx *rvec)
11398 if (align_words < GP_ARG_NUM_REG)
11400 int n_words = rs6000_arg_size (mode, type);
11402 if (align_words + n_words > GP_ARG_NUM_REG
11404 || (TARGET_32BIT && TARGET_POWERPC64))
11406 /* If this is partially on the stack, then we only
11407 include the portion actually in registers here. */
11408 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11411 if (align_words + n_words > GP_ARG_NUM_REG)
11413 /* Not all of the arg fits in gprs. Say that it goes in memory
11414 too, using a magic NULL_RTX component. Also see comment in
11415 rs6000_mixed_function_arg for why the normal
11416 function_arg_partial_nregs scheme doesn't work in this case. */
11417 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11422 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11423 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11424 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11426 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11430 /* The whole arg fits in gprs. */
11431 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11432 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11437 /* It's entirely in memory. */
11438 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11444 /* RVEC is a vector of K components of an argument of mode MODE.
11445 Construct the final function_arg return value from it. */
11448 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11450 gcc_assert (k >= 1);
11452 /* Avoid returning a PARALLEL in the trivial cases. */
11455 if (XEXP (rvec[0], 0) == NULL_RTX)
11458 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11459 return XEXP (rvec[0], 0);
11462 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11465 /* Determine where to put an argument to a function.
11466 Value is zero to push the argument on the stack,
11467 or a hard register in which to store the argument.
11469 MODE is the argument's machine mode.
11470 TYPE is the data type of the argument (as a tree).
11471 This is null for libcalls where that information may
11473 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11474 the preceding args and about the function being called. It is
11475 not modified in this routine.
11476 NAMED is nonzero if this argument is a named parameter
11477 (otherwise it is an extra parameter matching an ellipsis).
11479 On RS/6000 the first eight words of non-FP are normally in registers
11480 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11481 Under V.4, the first 8 FP args are in registers.
11483 If this is floating-point and no prototype is specified, we use
11484 both an FP and integer register (or possibly FP reg and stack). Library
11485 functions (when CALL_LIBCALL is set) always have the proper types for args,
11486 so we can pass the FP value just in one register. emit_library_function
11487 doesn't support PARALLEL anyway.
11489 Note that for args passed by reference, function_arg will be called
11490 with MODE and TYPE set to that of the pointer to the arg, not the arg
11494 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11495 const_tree type, bool named)
11497 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11498 enum rs6000_abi abi = DEFAULT_ABI;
11499 machine_mode elt_mode;
11502 /* Return a marker to indicate whether CR1 needs to set or clear the
11503 bit that V.4 uses to say fp args were passed in registers.
11504 Assume that we don't need the marker for software floating point,
11505 or compiler generated library calls. */
11506 if (mode == VOIDmode)
11509 && (cum->call_cookie & CALL_LIBCALL) == 0
11511 || (cum->nargs_prototype < 0
11512 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11513 && TARGET_HARD_FLOAT)
11514 return GEN_INT (cum->call_cookie
11515 | ((cum->fregno == FP_ARG_MIN_REG)
11516 ? CALL_V4_SET_FP_ARGS
11517 : CALL_V4_CLEAR_FP_ARGS));
11519 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11522 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11524 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11526 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11527 if (rslt != NULL_RTX)
11529 /* Else fall through to usual handling. */
11532 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11534 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11538 /* Do we also need to pass this argument in the parameter save area?
11539 Library support functions for IEEE 128-bit are assumed to not need the
11540 value passed both in GPRs and in vector registers. */
11541 if (TARGET_64BIT && !cum->prototype
11542 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11544 int align_words = ROUND_UP (cum->words, 2);
11545 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11548 /* Describe where this argument goes in the vector registers. */
11549 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11551 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11552 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11553 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11556 return rs6000_finish_function_arg (mode, rvec, k);
11558 else if (TARGET_ALTIVEC_ABI
11559 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11560 || (type && TREE_CODE (type) == VECTOR_TYPE
11561 && int_size_in_bytes (type) == 16)))
11563 if (named || abi == ABI_V4)
11567 /* Vector parameters to varargs functions under AIX or Darwin
11568 get passed in memory and possibly also in GPRs. */
11569 int align, align_words, n_words;
11570 machine_mode part_mode;
11572 /* Vector parameters must be 16-byte aligned. In 32-bit
11573 mode this means we need to take into account the offset
11574 to the parameter save area. In 64-bit mode, they just
11575 have to start on an even word, since the parameter save
11576 area is 16-byte aligned. */
11578 align = -(rs6000_parm_offset () + cum->words) & 3;
11580 align = cum->words & 1;
11581 align_words = cum->words + align;
11583 /* Out of registers? Memory, then. */
11584 if (align_words >= GP_ARG_NUM_REG)
11587 if (TARGET_32BIT && TARGET_POWERPC64)
11588 return rs6000_mixed_function_arg (mode, type, align_words);
11590 /* The vector value goes in GPRs. Only the part of the
11591 value in GPRs is reported here. */
11593 n_words = rs6000_arg_size (mode, type);
11594 if (align_words + n_words > GP_ARG_NUM_REG)
11595 /* Fortunately, there are only two possibilities, the value
11596 is either wholly in GPRs or half in GPRs and half not. */
11597 part_mode = DImode;
11599 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11603 else if (abi == ABI_V4)
11605 if (abi_v4_pass_in_fpr (mode, named))
11607 /* _Decimal128 must use an even/odd register pair. This assumes
11608 that the register number is odd when fregno is odd. */
11609 if (mode == TDmode && (cum->fregno % 2) == 1)
11612 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11613 <= FP_ARG_V4_MAX_REG)
11614 return gen_rtx_REG (mode, cum->fregno);
11620 int n_words = rs6000_arg_size (mode, type);
11621 int gregno = cum->sysv_gregno;
11623 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11624 As does any other 2 word item such as complex int due to a
11625 historical mistake. */
11627 gregno += (1 - gregno) & 1;
11629 /* Multi-reg args are not split between registers and stack. */
11630 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11633 if (TARGET_32BIT && TARGET_POWERPC64)
11634 return rs6000_mixed_function_arg (mode, type,
11635 gregno - GP_ARG_MIN_REG);
11636 return gen_rtx_REG (mode, gregno);
11641 int align_words = rs6000_parm_start (mode, type, cum->words);
11643 /* _Decimal128 must be passed in an even/odd float register pair.
11644 This assumes that the register number is odd when fregno is odd. */
11645 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11648 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11649 && !(TARGET_AIX && !TARGET_ELF
11650 && type != NULL && AGGREGATE_TYPE_P (type)))
11652 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11655 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11658 /* Do we also need to pass this argument in the parameter
11660 if (type && (cum->nargs_prototype <= 0
11661 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11662 && TARGET_XL_COMPAT
11663 && align_words >= GP_ARG_NUM_REG)))
11664 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11666 /* Describe where this argument goes in the fprs. */
11667 for (i = 0; i < n_elts
11668 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11670 /* Check if the argument is split over registers and memory.
11671 This can only ever happen for long double or _Decimal128;
11672 complex types are handled via split_complex_arg. */
11673 machine_mode fmode = elt_mode;
11674 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11676 gcc_assert (FLOAT128_2REG_P (fmode));
11677 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11680 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11681 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11682 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11685 /* If there were not enough FPRs to hold the argument, the rest
11686 usually goes into memory. However, if the current position
11687 is still within the register parameter area, a portion may
11688 actually have to go into GPRs.
11690 Note that it may happen that the portion of the argument
11691 passed in the first "half" of the first GPR was already
11692 passed in the last FPR as well.
11694 For unnamed arguments, we already set up GPRs to cover the
11695 whole argument in rs6000_psave_function_arg, so there is
11696 nothing further to do at this point. */
11697 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11698 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11699 && cum->nargs_prototype > 0)
11701 static bool warned;
11703 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11704 int n_words = rs6000_arg_size (mode, type);
11706 align_words += fpr_words;
11707 n_words -= fpr_words;
11711 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11712 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11713 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11715 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11717 if (!warned && warn_psabi)
11720 inform (input_location,
11721 "the ABI of passing homogeneous %<float%> aggregates"
11722 " has changed in GCC 5");
11726 return rs6000_finish_function_arg (mode, rvec, k);
11728 else if (align_words < GP_ARG_NUM_REG)
11730 if (TARGET_32BIT && TARGET_POWERPC64)
11731 return rs6000_mixed_function_arg (mode, type, align_words);
11733 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11740 /* For an arg passed partly in registers and partly in memory, this is
11741 the number of bytes passed in registers. For args passed entirely in
11742 registers or entirely in memory, zero. When an arg is described by a
11743 PARALLEL, perhaps using more than one register type, this function
11744 returns the number of bytes used by the first element of the PARALLEL. */
11747 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11748 tree type, bool named)
11750 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11751 bool passed_in_gprs = true;
11754 machine_mode elt_mode;
11757 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11759 if (DEFAULT_ABI == ABI_V4)
11762 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11764 /* If we are passing this arg in the fixed parameter save area (gprs or
11765 memory) as well as VRs, we do not use the partial bytes mechanism;
11766 instead, rs6000_function_arg will return a PARALLEL including a memory
11767 element as necessary. Library support functions for IEEE 128-bit are
11768 assumed to not need the value passed both in GPRs and in vector
11770 if (TARGET_64BIT && !cum->prototype
11771 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11774 /* Otherwise, we pass in VRs only. Check for partial copies. */
11775 passed_in_gprs = false;
11776 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
11777 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
11780 /* In this complicated case we just disable the partial_nregs code. */
11781 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11784 align_words = rs6000_parm_start (mode, type, cum->words);
11786 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11787 && !(TARGET_AIX && !TARGET_ELF
11788 && type != NULL && AGGREGATE_TYPE_P (type)))
11790 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11792 /* If we are passing this arg in the fixed parameter save area
11793 (gprs or memory) as well as FPRs, we do not use the partial
11794 bytes mechanism; instead, rs6000_function_arg will return a
11795 PARALLEL including a memory element as necessary. */
11797 && (cum->nargs_prototype <= 0
11798 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11799 && TARGET_XL_COMPAT
11800 && align_words >= GP_ARG_NUM_REG)))
11803 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11804 passed_in_gprs = false;
11805 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
11807 /* Compute number of bytes / words passed in FPRs. If there
11808 is still space available in the register parameter area
11809 *after* that amount, a part of the argument will be passed
11810 in GPRs. In that case, the total amount passed in any
11811 registers is equal to the amount that would have been passed
11812 in GPRs if everything were passed there, so we fall back to
11813 the GPR code below to compute the appropriate value. */
11814 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
11815 * MIN (8, GET_MODE_SIZE (elt_mode)));
11816 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
11818 if (align_words + fpr_words < GP_ARG_NUM_REG)
11819 passed_in_gprs = true;
11826 && align_words < GP_ARG_NUM_REG
11827 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
11828 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
11830 if (ret != 0 && TARGET_DEBUG_ARG)
11831 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
11836 /* A C expression that indicates when an argument must be passed by
11837 reference. If nonzero for an argument, a copy of that argument is
11838 made in memory and a pointer to the argument is passed instead of
11839 the argument itself. The pointer is passed in whatever way is
11840 appropriate for passing a pointer to that type.
11842 Under V.4, aggregates and long double are passed by reference.
11844 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11845 reference unless the AltiVec vector extension ABI is in force.
11847 As an extension to all ABIs, variable sized types are passed by
11851 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
11852 machine_mode mode, const_tree type,
11853 bool named ATTRIBUTE_UNUSED)
11858 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11859 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11861 if (TARGET_DEBUG_ARG)
11862 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11866 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
11868 if (TARGET_DEBUG_ARG)
11869 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
11873 if (int_size_in_bytes (type) < 0)
11875 if (TARGET_DEBUG_ARG)
11876 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
11880 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11881 modes only exist for GCC vector types if -maltivec. */
11882 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11884 if (TARGET_DEBUG_ARG)
11885 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
11889 /* Pass synthetic vectors in memory. */
11890 if (TREE_CODE (type) == VECTOR_TYPE
11891 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11893 static bool warned_for_pass_big_vectors = false;
11894 if (TARGET_DEBUG_ARG)
11895 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
11896 if (!warned_for_pass_big_vectors)
11898 warning (OPT_Wpsabi, "GCC vector passed by reference: "
11899 "non-standard ABI extension with no compatibility "
11901 warned_for_pass_big_vectors = true;
11909 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11910 already processes. Return true if the parameter must be passed
11911 (fully or partially) on the stack. */
11914 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
11920 /* Catch errors. */
11921 if (type == NULL || type == error_mark_node)
11924 /* Handle types with no storage requirement. */
11925 if (TYPE_MODE (type) == VOIDmode)
11928 /* Handle complex types. */
11929 if (TREE_CODE (type) == COMPLEX_TYPE)
11930 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
11931 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
11933 /* Handle transparent aggregates. */
11934 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
11935 && TYPE_TRANSPARENT_AGGR (type))
11936 type = TREE_TYPE (first_field (type));
11938 /* See if this arg was passed by invisible reference. */
11939 if (pass_by_reference (get_cumulative_args (args_so_far),
11940 TYPE_MODE (type), type, true))
11941 type = build_pointer_type (type);
11943 /* Find mode as it is passed by the ABI. */
11944 unsignedp = TYPE_UNSIGNED (type);
11945 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
11947 /* If we must pass in stack, we need a stack. */
11948 if (rs6000_must_pass_in_stack (mode, type))
11951 /* If there is no incoming register, we need a stack. */
11952 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
11953 if (entry_parm == NULL)
11956 /* Likewise if we need to pass both in registers and on the stack. */
11957 if (GET_CODE (entry_parm) == PARALLEL
11958 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
11961 /* Also true if we're partially in registers and partially not. */
11962 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
11965 /* Update info on where next arg arrives in registers. */
11966 rs6000_function_arg_advance (args_so_far, mode, type, true);
11970 /* Return true if FUN has no prototype, has a variable argument
11971 list, or passes any parameter in memory. */
11974 rs6000_function_parms_need_stack (tree fun, bool incoming)
11976 tree fntype, result;
11977 CUMULATIVE_ARGS args_so_far_v;
11978 cumulative_args_t args_so_far;
11981 /* Must be a libcall, all of which only use reg parms. */
11986 fntype = TREE_TYPE (fun);
11988 /* Varargs functions need the parameter save area. */
11989 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
11992 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
11993 args_so_far = pack_cumulative_args (&args_so_far_v);
11995 /* When incoming, we will have been passed the function decl.
11996 It is necessary to use the decl to handle K&R style functions,
11997 where TYPE_ARG_TYPES may not be available. */
12000 gcc_assert (DECL_P (fun));
12001 result = DECL_RESULT (fun);
12004 result = TREE_TYPE (fntype);
12006 if (result && aggregate_value_p (result, fntype))
12008 if (!TYPE_P (result))
12009 result = TREE_TYPE (result);
12010 result = build_pointer_type (result);
12011 rs6000_parm_needs_stack (args_so_far, result);
12018 for (parm = DECL_ARGUMENTS (fun);
12019 parm && parm != void_list_node;
12020 parm = TREE_CHAIN (parm))
12021 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12026 function_args_iterator args_iter;
12029 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12030 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12037 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12038 usually a constant depending on the ABI. However, in the ELFv2 ABI
12039 the register parameter area is optional when calling a function that
12040 has a prototype is scope, has no variable argument list, and passes
12041 all parameters in registers. */
12044 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12046 int reg_parm_stack_space;
12048 switch (DEFAULT_ABI)
12051 reg_parm_stack_space = 0;
12056 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12060 /* ??? Recomputing this every time is a bit expensive. Is there
12061 a place to cache this information? */
12062 if (rs6000_function_parms_need_stack (fun, incoming))
12063 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12065 reg_parm_stack_space = 0;
12069 return reg_parm_stack_space;
12073 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12076 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12081 for (i = 0; i < nregs; i++)
12083 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12084 if (reload_completed)
12086 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12089 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12090 i * GET_MODE_SIZE (reg_mode));
12093 tem = replace_equiv_address (tem, XEXP (tem, 0));
12097 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12101 /* Perform any needed actions needed for a function that is receiving a
12102 variable number of arguments.
12106 MODE and TYPE are the mode and type of the current parameter.
12108 PRETEND_SIZE is a variable that should be set to the amount of stack
12109 that must be pushed by the prolog to pretend that our caller pushed
12112 Normally, this macro will push all remaining incoming registers on the
12113 stack and set PRETEND_SIZE to the length of the registers pushed. */
12116 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12117 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12120 CUMULATIVE_ARGS next_cum;
12121 int reg_size = TARGET_32BIT ? 4 : 8;
12122 rtx save_area = NULL_RTX, mem;
12123 int first_reg_offset;
12124 alias_set_type set;
12126 /* Skip the last named argument. */
12127 next_cum = *get_cumulative_args (cum);
12128 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12130 if (DEFAULT_ABI == ABI_V4)
12132 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12136 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12137 HOST_WIDE_INT offset = 0;
12139 /* Try to optimize the size of the varargs save area.
12140 The ABI requires that ap.reg_save_area is doubleword
12141 aligned, but we don't need to allocate space for all
12142 the bytes, only those to which we actually will save
12144 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12145 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12146 if (TARGET_HARD_FLOAT
12147 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12148 && cfun->va_list_fpr_size)
12151 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12152 * UNITS_PER_FP_WORD;
12153 if (cfun->va_list_fpr_size
12154 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12155 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12157 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12158 * UNITS_PER_FP_WORD;
12162 offset = -((first_reg_offset * reg_size) & ~7);
12163 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12165 gpr_reg_num = cfun->va_list_gpr_size;
12166 if (reg_size == 4 && (first_reg_offset & 1))
12169 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12172 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12173 * UNITS_PER_FP_WORD
12174 - (int) (GP_ARG_NUM_REG * reg_size);
12176 if (gpr_size + fpr_size)
12179 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12180 gcc_assert (MEM_P (reg_save_area));
12181 reg_save_area = XEXP (reg_save_area, 0);
12182 if (GET_CODE (reg_save_area) == PLUS)
12184 gcc_assert (XEXP (reg_save_area, 0)
12185 == virtual_stack_vars_rtx);
12186 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
12187 offset += INTVAL (XEXP (reg_save_area, 1));
12190 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12193 cfun->machine->varargs_save_offset = offset;
12194 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12199 first_reg_offset = next_cum.words;
12200 save_area = crtl->args.internal_arg_pointer;
12202 if (targetm.calls.must_pass_in_stack (mode, type))
12203 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12206 set = get_varargs_alias_set ();
12207 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12208 && cfun->va_list_gpr_size)
12210 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12212 if (va_list_gpr_counter_field)
12213 /* V4 va_list_gpr_size counts number of registers needed. */
12214 n_gpr = cfun->va_list_gpr_size;
12216 /* char * va_list instead counts number of bytes needed. */
12217 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12222 mem = gen_rtx_MEM (BLKmode,
12223 plus_constant (Pmode, save_area,
12224 first_reg_offset * reg_size));
12225 MEM_NOTRAP_P (mem) = 1;
12226 set_mem_alias_set (mem, set);
12227 set_mem_align (mem, BITS_PER_WORD);
12229 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12233 /* Save FP registers if needed. */
12234 if (DEFAULT_ABI == ABI_V4
12235 && TARGET_HARD_FLOAT
12237 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12238 && cfun->va_list_fpr_size)
12240 int fregno = next_cum.fregno, nregs;
12241 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12242 rtx lab = gen_label_rtx ();
12243 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12244 * UNITS_PER_FP_WORD);
12247 (gen_rtx_SET (pc_rtx,
12248 gen_rtx_IF_THEN_ELSE (VOIDmode,
12249 gen_rtx_NE (VOIDmode, cr1,
12251 gen_rtx_LABEL_REF (VOIDmode, lab),
12255 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12256 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12258 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12259 plus_constant (Pmode, save_area, off));
12260 MEM_NOTRAP_P (mem) = 1;
12261 set_mem_alias_set (mem, set);
12262 set_mem_align (mem, GET_MODE_ALIGNMENT (
12263 TARGET_HARD_FLOAT ? DFmode : SFmode));
12264 emit_move_insn (mem, gen_rtx_REG (
12265 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12272 /* Create the va_list data type. */
12275 rs6000_build_builtin_va_list (void)
12277 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12279 /* For AIX, prefer 'char *' because that's what the system
12280 header files like. */
12281 if (DEFAULT_ABI != ABI_V4)
12282 return build_pointer_type (char_type_node);
12284 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12285 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12286 get_identifier ("__va_list_tag"), record);
12288 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12289 unsigned_char_type_node);
12290 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12291 unsigned_char_type_node);
12292 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12293 every user file. */
12294 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12295 get_identifier ("reserved"), short_unsigned_type_node);
12296 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12297 get_identifier ("overflow_arg_area"),
12299 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12300 get_identifier ("reg_save_area"),
12303 va_list_gpr_counter_field = f_gpr;
12304 va_list_fpr_counter_field = f_fpr;
12306 DECL_FIELD_CONTEXT (f_gpr) = record;
12307 DECL_FIELD_CONTEXT (f_fpr) = record;
12308 DECL_FIELD_CONTEXT (f_res) = record;
12309 DECL_FIELD_CONTEXT (f_ovf) = record;
12310 DECL_FIELD_CONTEXT (f_sav) = record;
12312 TYPE_STUB_DECL (record) = type_decl;
12313 TYPE_NAME (record) = type_decl;
12314 TYPE_FIELDS (record) = f_gpr;
12315 DECL_CHAIN (f_gpr) = f_fpr;
12316 DECL_CHAIN (f_fpr) = f_res;
12317 DECL_CHAIN (f_res) = f_ovf;
12318 DECL_CHAIN (f_ovf) = f_sav;
12320 layout_type (record);
12322 /* The correct type is an array type of one element. */
12323 return build_array_type (record, build_index_type (size_zero_node));
12326 /* Implement va_start. */
12329 rs6000_va_start (tree valist, rtx nextarg)
12331 HOST_WIDE_INT words, n_gpr, n_fpr;
12332 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12333 tree gpr, fpr, ovf, sav, t;
12335 /* Only SVR4 needs something special. */
12336 if (DEFAULT_ABI != ABI_V4)
12338 std_expand_builtin_va_start (valist, nextarg);
12342 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12343 f_fpr = DECL_CHAIN (f_gpr);
12344 f_res = DECL_CHAIN (f_fpr);
12345 f_ovf = DECL_CHAIN (f_res);
12346 f_sav = DECL_CHAIN (f_ovf);
12348 valist = build_simple_mem_ref (valist);
12349 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12350 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12352 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12354 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12357 /* Count number of gp and fp argument registers used. */
12358 words = crtl->args.info.words;
12359 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12361 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12364 if (TARGET_DEBUG_ARG)
12365 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12366 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12367 words, n_gpr, n_fpr);
12369 if (cfun->va_list_gpr_size)
12371 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12372 build_int_cst (NULL_TREE, n_gpr));
12373 TREE_SIDE_EFFECTS (t) = 1;
12374 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12377 if (cfun->va_list_fpr_size)
12379 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12380 build_int_cst (NULL_TREE, n_fpr));
12381 TREE_SIDE_EFFECTS (t) = 1;
12382 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12384 #ifdef HAVE_AS_GNU_ATTRIBUTE
12385 if (call_ABI_of_interest (cfun->decl))
12386 rs6000_passes_float = true;
12390 /* Find the overflow area. */
12391 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12393 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12394 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12395 TREE_SIDE_EFFECTS (t) = 1;
12396 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12398 /* If there were no va_arg invocations, don't set up the register
12400 if (!cfun->va_list_gpr_size
12401 && !cfun->va_list_fpr_size
12402 && n_gpr < GP_ARG_NUM_REG
12403 && n_fpr < FP_ARG_V4_MAX_REG)
12406 /* Find the register save area. */
12407 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12408 if (cfun->machine->varargs_save_offset)
12409 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12410 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12411 TREE_SIDE_EFFECTS (t) = 1;
12412 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12415 /* Implement va_arg. */
12418 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12419 gimple_seq *post_p)
12421 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12422 tree gpr, fpr, ovf, sav, reg, t, u;
12423 int size, rsize, n_reg, sav_ofs, sav_scale;
12424 tree lab_false, lab_over, addr;
12426 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12430 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12432 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12433 return build_va_arg_indirect_ref (t);
12436 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12437 earlier version of gcc, with the property that it always applied alignment
12438 adjustments to the va-args (even for zero-sized types). The cheapest way
12439 to deal with this is to replicate the effect of the part of
12440 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12442 We don't need to check for pass-by-reference because of the test above.
12443 We can return a simplifed answer, since we know there's no offset to add. */
12446 && rs6000_darwin64_abi)
12447 || DEFAULT_ABI == ABI_ELFv2
12448 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12449 && integer_zerop (TYPE_SIZE (type)))
12451 unsigned HOST_WIDE_INT align, boundary;
12452 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12453 align = PARM_BOUNDARY / BITS_PER_UNIT;
12454 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12455 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12456 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12457 boundary /= BITS_PER_UNIT;
12458 if (boundary > align)
12461 /* This updates arg ptr by the amount that would be necessary
12462 to align the zero-sized (but not zero-alignment) item. */
12463 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12464 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12465 gimplify_and_add (t, pre_p);
12467 t = fold_convert (sizetype, valist_tmp);
12468 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12469 fold_convert (TREE_TYPE (valist),
12470 fold_build2 (BIT_AND_EXPR, sizetype, t,
12471 size_int (-boundary))));
12472 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12473 gimplify_and_add (t, pre_p);
12475 /* Since it is zero-sized there's no increment for the item itself. */
12476 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12477 return build_va_arg_indirect_ref (valist_tmp);
12480 if (DEFAULT_ABI != ABI_V4)
12482 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12484 tree elem_type = TREE_TYPE (type);
12485 machine_mode elem_mode = TYPE_MODE (elem_type);
12486 int elem_size = GET_MODE_SIZE (elem_mode);
12488 if (elem_size < UNITS_PER_WORD)
12490 tree real_part, imag_part;
12491 gimple_seq post = NULL;
12493 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12495 /* Copy the value into a temporary, lest the formal temporary
12496 be reused out from under us. */
12497 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12498 gimple_seq_add_seq (pre_p, post);
12500 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12503 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12507 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12510 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12511 f_fpr = DECL_CHAIN (f_gpr);
12512 f_res = DECL_CHAIN (f_fpr);
12513 f_ovf = DECL_CHAIN (f_res);
12514 f_sav = DECL_CHAIN (f_ovf);
12516 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12517 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12519 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12521 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12524 size = int_size_in_bytes (type);
12525 rsize = (size + 3) / 4;
12526 int pad = 4 * rsize - size;
12529 machine_mode mode = TYPE_MODE (type);
12530 if (abi_v4_pass_in_fpr (mode, false))
12532 /* FP args go in FP registers, if present. */
12534 n_reg = (size + 7) / 8;
12535 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12536 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12537 if (mode != SFmode && mode != SDmode)
12542 /* Otherwise into GP registers. */
12551 /* Pull the value out of the saved registers.... */
12554 addr = create_tmp_var (ptr_type_node, "addr");
12556 /* AltiVec vectors never go in registers when -mabi=altivec. */
12557 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12561 lab_false = create_artificial_label (input_location);
12562 lab_over = create_artificial_label (input_location);
12564 /* Long long is aligned in the registers. As are any other 2 gpr
12565 item such as complex int due to a historical mistake. */
12567 if (n_reg == 2 && reg == gpr)
12570 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12571 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12572 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12573 unshare_expr (reg), u);
12575 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12576 reg number is 0 for f1, so we want to make it odd. */
12577 else if (reg == fpr && mode == TDmode)
12579 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12580 build_int_cst (TREE_TYPE (reg), 1));
12581 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12584 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12585 t = build2 (GE_EXPR, boolean_type_node, u, t);
12586 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12587 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12588 gimplify_and_add (t, pre_p);
12592 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12594 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12595 build_int_cst (TREE_TYPE (reg), n_reg));
12596 u = fold_convert (sizetype, u);
12597 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12598 t = fold_build_pointer_plus (t, u);
12600 /* _Decimal32 varargs are located in the second word of the 64-bit
12601 FP register for 32-bit binaries. */
12602 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12603 t = fold_build_pointer_plus_hwi (t, size);
12605 /* Args are passed right-aligned. */
12606 if (BYTES_BIG_ENDIAN)
12607 t = fold_build_pointer_plus_hwi (t, pad);
12609 gimplify_assign (addr, t, pre_p);
12611 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12613 stmt = gimple_build_label (lab_false);
12614 gimple_seq_add_stmt (pre_p, stmt);
12616 if ((n_reg == 2 && !regalign) || n_reg > 2)
12618 /* Ensure that we don't find any more args in regs.
12619 Alignment has taken care of for special cases. */
12620 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12624 /* ... otherwise out of the overflow area. */
12626 /* Care for on-stack alignment if needed. */
12630 t = fold_build_pointer_plus_hwi (t, align - 1);
12631 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12632 build_int_cst (TREE_TYPE (t), -align));
12635 /* Args are passed right-aligned. */
12636 if (BYTES_BIG_ENDIAN)
12637 t = fold_build_pointer_plus_hwi (t, pad);
12639 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12641 gimplify_assign (unshare_expr (addr), t, pre_p);
12643 t = fold_build_pointer_plus_hwi (t, size);
12644 gimplify_assign (unshare_expr (ovf), t, pre_p);
12648 stmt = gimple_build_label (lab_over);
12649 gimple_seq_add_stmt (pre_p, stmt);
12652 if (STRICT_ALIGNMENT
12653 && (TYPE_ALIGN (type)
12654 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12656 /* The value (of type complex double, for example) may not be
12657 aligned in memory in the saved registers, so copy via a
12658 temporary. (This is the same code as used for SPARC.) */
12659 tree tmp = create_tmp_var (type, "va_arg_tmp");
12660 tree dest_addr = build_fold_addr_expr (tmp);
12662 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12663 3, dest_addr, addr, size_int (rsize * 4));
12664 TREE_ADDRESSABLE (tmp) = 1;
12666 gimplify_and_add (copy, pre_p);
12670 addr = fold_convert (ptrtype, addr);
12671 return build_va_arg_indirect_ref (addr);
12677 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12680 unsigned classify = rs6000_builtin_info[(int)code].attr;
12681 const char *attr_string = "";
12683 gcc_assert (name != NULL);
12684 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12686 if (rs6000_builtin_decls[(int)code])
12687 fatal_error (input_location,
12688 "internal error: builtin function %qs already processed",
12691 rs6000_builtin_decls[(int)code] = t =
12692 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12694 /* Set any special attributes. */
12695 if ((classify & RS6000_BTC_CONST) != 0)
12697 /* const function, function only depends on the inputs. */
12698 TREE_READONLY (t) = 1;
12699 TREE_NOTHROW (t) = 1;
12700 attr_string = ", const";
12702 else if ((classify & RS6000_BTC_PURE) != 0)
12704 /* pure function, function can read global memory, but does not set any
12706 DECL_PURE_P (t) = 1;
12707 TREE_NOTHROW (t) = 1;
12708 attr_string = ", pure";
12710 else if ((classify & RS6000_BTC_FP) != 0)
12712 /* Function is a math function. If rounding mode is on, then treat the
12713 function as not reading global memory, but it can have arbitrary side
12714 effects. If it is off, then assume the function is a const function.
12715 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12716 builtin-attribute.def that is used for the math functions. */
12717 TREE_NOTHROW (t) = 1;
12718 if (flag_rounding_math)
12720 DECL_PURE_P (t) = 1;
12721 DECL_IS_NOVOPS (t) = 1;
12722 attr_string = ", fp, pure";
12726 TREE_READONLY (t) = 1;
12727 attr_string = ", fp, const";
12730 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12731 gcc_unreachable ();
12733 if (TARGET_DEBUG_BUILTIN)
12734 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12735 (int)code, name, attr_string);
12738 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12740 #undef RS6000_BUILTIN_0
12741 #undef RS6000_BUILTIN_1
12742 #undef RS6000_BUILTIN_2
12743 #undef RS6000_BUILTIN_3
12744 #undef RS6000_BUILTIN_A
12745 #undef RS6000_BUILTIN_D
12746 #undef RS6000_BUILTIN_H
12747 #undef RS6000_BUILTIN_P
12748 #undef RS6000_BUILTIN_X
12750 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12751 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12752 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12753 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12754 { MASK, ICODE, NAME, ENUM },
12756 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12757 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12758 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12759 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12760 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12762 static const struct builtin_description bdesc_3arg[] =
12764 #include "rs6000-builtin.def"
12767 /* DST operations: void foo (void *, const int, const char). */
12769 #undef RS6000_BUILTIN_0
12770 #undef RS6000_BUILTIN_1
12771 #undef RS6000_BUILTIN_2
12772 #undef RS6000_BUILTIN_3
12773 #undef RS6000_BUILTIN_A
12774 #undef RS6000_BUILTIN_D
12775 #undef RS6000_BUILTIN_H
12776 #undef RS6000_BUILTIN_P
12777 #undef RS6000_BUILTIN_X
12779 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12780 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12781 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12782 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12783 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12784 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12785 { MASK, ICODE, NAME, ENUM },
12787 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12788 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12789 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12791 static const struct builtin_description bdesc_dst[] =
12793 #include "rs6000-builtin.def"
12796 /* Simple binary operations: VECc = foo (VECa, VECb). */
12798 #undef RS6000_BUILTIN_0
12799 #undef RS6000_BUILTIN_1
12800 #undef RS6000_BUILTIN_2
12801 #undef RS6000_BUILTIN_3
12802 #undef RS6000_BUILTIN_A
12803 #undef RS6000_BUILTIN_D
12804 #undef RS6000_BUILTIN_H
12805 #undef RS6000_BUILTIN_P
12806 #undef RS6000_BUILTIN_X
12808 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12809 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12810 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12811 { MASK, ICODE, NAME, ENUM },
12813 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12814 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12815 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12816 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12817 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12818 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12820 static const struct builtin_description bdesc_2arg[] =
12822 #include "rs6000-builtin.def"
12825 #undef RS6000_BUILTIN_0
12826 #undef RS6000_BUILTIN_1
12827 #undef RS6000_BUILTIN_2
12828 #undef RS6000_BUILTIN_3
12829 #undef RS6000_BUILTIN_A
12830 #undef RS6000_BUILTIN_D
12831 #undef RS6000_BUILTIN_H
12832 #undef RS6000_BUILTIN_P
12833 #undef RS6000_BUILTIN_X
12835 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12836 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12837 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12838 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12839 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12840 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12841 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12842 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12843 { MASK, ICODE, NAME, ENUM },
12845 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12847 /* AltiVec predicates. */
12849 static const struct builtin_description bdesc_altivec_preds[] =
12851 #include "rs6000-builtin.def"
12854 /* ABS* operations. */
12856 #undef RS6000_BUILTIN_0
12857 #undef RS6000_BUILTIN_1
12858 #undef RS6000_BUILTIN_2
12859 #undef RS6000_BUILTIN_3
12860 #undef RS6000_BUILTIN_A
12861 #undef RS6000_BUILTIN_D
12862 #undef RS6000_BUILTIN_H
12863 #undef RS6000_BUILTIN_P
12864 #undef RS6000_BUILTIN_X
12866 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12867 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12868 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12869 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12870 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12871 { MASK, ICODE, NAME, ENUM },
12873 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12874 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12875 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12876 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12878 static const struct builtin_description bdesc_abs[] =
12880 #include "rs6000-builtin.def"
12883 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12886 #undef RS6000_BUILTIN_0
12887 #undef RS6000_BUILTIN_1
12888 #undef RS6000_BUILTIN_2
12889 #undef RS6000_BUILTIN_3
12890 #undef RS6000_BUILTIN_A
12891 #undef RS6000_BUILTIN_D
12892 #undef RS6000_BUILTIN_H
12893 #undef RS6000_BUILTIN_P
12894 #undef RS6000_BUILTIN_X
12896 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12897 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12898 { MASK, ICODE, NAME, ENUM },
12900 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12901 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12902 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12903 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12904 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12905 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12906 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12908 static const struct builtin_description bdesc_1arg[] =
12910 #include "rs6000-builtin.def"
12913 /* Simple no-argument operations: result = __builtin_darn_32 () */
12915 #undef RS6000_BUILTIN_0
12916 #undef RS6000_BUILTIN_1
12917 #undef RS6000_BUILTIN_2
12918 #undef RS6000_BUILTIN_3
12919 #undef RS6000_BUILTIN_A
12920 #undef RS6000_BUILTIN_D
12921 #undef RS6000_BUILTIN_H
12922 #undef RS6000_BUILTIN_P
12923 #undef RS6000_BUILTIN_X
12925 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
12926 { MASK, ICODE, NAME, ENUM },
12928 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12929 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12930 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12931 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12932 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12933 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12934 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12935 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12937 static const struct builtin_description bdesc_0arg[] =
12939 #include "rs6000-builtin.def"
12942 /* HTM builtins. */
12943 #undef RS6000_BUILTIN_0
12944 #undef RS6000_BUILTIN_1
12945 #undef RS6000_BUILTIN_2
12946 #undef RS6000_BUILTIN_3
12947 #undef RS6000_BUILTIN_A
12948 #undef RS6000_BUILTIN_D
12949 #undef RS6000_BUILTIN_H
12950 #undef RS6000_BUILTIN_P
12951 #undef RS6000_BUILTIN_X
12953 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12954 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12955 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12956 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12957 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12958 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12959 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12960 { MASK, ICODE, NAME, ENUM },
12962 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12963 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12965 static const struct builtin_description bdesc_htm[] =
12967 #include "rs6000-builtin.def"
12970 #undef RS6000_BUILTIN_0
12971 #undef RS6000_BUILTIN_1
12972 #undef RS6000_BUILTIN_2
12973 #undef RS6000_BUILTIN_3
12974 #undef RS6000_BUILTIN_A
12975 #undef RS6000_BUILTIN_D
12976 #undef RS6000_BUILTIN_H
12977 #undef RS6000_BUILTIN_P
12979 /* Return true if a builtin function is overloaded. */
12981 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
12983 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
12987 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
12989 return rs6000_builtin_info[(int)fncode].name;
12992 /* Expand an expression EXP that calls a builtin without arguments. */
12994 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
12997 machine_mode tmode = insn_data[icode].operand[0].mode;
12999 if (icode == CODE_FOR_nothing)
13000 /* Builtin not supported on this processor. */
13003 if (icode == CODE_FOR_rs6000_mffsl
13004 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13006 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13011 || GET_MODE (target) != tmode
13012 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13013 target = gen_reg_rtx (tmode);
13015 pat = GEN_FCN (icode) (target);
13025 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13028 tree arg0 = CALL_EXPR_ARG (exp, 0);
13029 tree arg1 = CALL_EXPR_ARG (exp, 1);
13030 rtx op0 = expand_normal (arg0);
13031 rtx op1 = expand_normal (arg1);
13032 machine_mode mode0 = insn_data[icode].operand[0].mode;
13033 machine_mode mode1 = insn_data[icode].operand[1].mode;
13035 if (icode == CODE_FOR_nothing)
13036 /* Builtin not supported on this processor. */
13039 /* If we got invalid arguments bail out before generating bad rtl. */
13040 if (arg0 == error_mark_node || arg1 == error_mark_node)
13043 if (!CONST_INT_P (op0)
13044 || INTVAL (op0) > 255
13045 || INTVAL (op0) < 0)
13047 error ("argument 1 must be an 8-bit field value");
13051 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13052 op0 = copy_to_mode_reg (mode0, op0);
13054 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13055 op1 = copy_to_mode_reg (mode1, op1);
13057 pat = GEN_FCN (icode) (op0, op1);
13066 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13069 tree arg0 = CALL_EXPR_ARG (exp, 0);
13070 rtx op0 = expand_normal (arg0);
13072 if (icode == CODE_FOR_nothing)
13073 /* Builtin not supported on this processor. */
13076 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13078 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13079 "%<-msoft-float%>");
13083 /* If we got invalid arguments bail out before generating bad rtl. */
13084 if (arg0 == error_mark_node)
13087 /* Only allow bit numbers 0 to 31. */
13088 if (!u5bit_cint_operand (op0, VOIDmode))
13090 error ("Argument must be a constant between 0 and 31.");
13094 pat = GEN_FCN (icode) (op0);
13103 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13106 tree arg0 = CALL_EXPR_ARG (exp, 0);
13107 rtx op0 = expand_normal (arg0);
13108 machine_mode mode0 = insn_data[icode].operand[0].mode;
13110 if (icode == CODE_FOR_nothing)
13111 /* Builtin not supported on this processor. */
13114 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13116 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13120 /* If we got invalid arguments bail out before generating bad rtl. */
13121 if (arg0 == error_mark_node)
13124 /* If the argument is a constant, check the range. Argument can only be a
13125 2-bit value. Unfortunately, can't check the range of the value at
13126 compile time if the argument is a variable. The least significant two
13127 bits of the argument, regardless of type, are used to set the rounding
13128 mode. All other bits are ignored. */
13129 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
13131 error ("Argument must be a value between 0 and 3.");
13135 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13136 op0 = copy_to_mode_reg (mode0, op0);
13138 pat = GEN_FCN (icode) (op0);
13146 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13149 tree arg0 = CALL_EXPR_ARG (exp, 0);
13150 rtx op0 = expand_normal (arg0);
13151 machine_mode mode0 = insn_data[icode].operand[0].mode;
13154 /* Builtin not supported in 32-bit mode. */
13155 fatal_error (input_location,
13156 "%<__builtin_set_fpscr_drn%> is not supported "
13159 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13161 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13165 if (icode == CODE_FOR_nothing)
13166 /* Builtin not supported on this processor. */
13169 /* If we got invalid arguments bail out before generating bad rtl. */
13170 if (arg0 == error_mark_node)
13173 /* If the argument is a constant, check the range. Agrument can only be a
13174 3-bit value. Unfortunately, can't check the range of the value at
13175 compile time if the argument is a variable. The least significant two
13176 bits of the argument, regardless of type, are used to set the rounding
13177 mode. All other bits are ignored. */
13178 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
13180 error ("Argument must be a value between 0 and 7.");
13184 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13185 op0 = copy_to_mode_reg (mode0, op0);
13187 pat = GEN_FCN (icode) (op0);
13196 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13199 tree arg0 = CALL_EXPR_ARG (exp, 0);
13200 rtx op0 = expand_normal (arg0);
13201 machine_mode tmode = insn_data[icode].operand[0].mode;
13202 machine_mode mode0 = insn_data[icode].operand[1].mode;
13204 if (icode == CODE_FOR_nothing)
13205 /* Builtin not supported on this processor. */
13208 /* If we got invalid arguments bail out before generating bad rtl. */
13209 if (arg0 == error_mark_node)
13212 if (icode == CODE_FOR_altivec_vspltisb
13213 || icode == CODE_FOR_altivec_vspltish
13214 || icode == CODE_FOR_altivec_vspltisw)
13216 /* Only allow 5-bit *signed* literals. */
13217 if (!CONST_INT_P (op0)
13218 || INTVAL (op0) > 15
13219 || INTVAL (op0) < -16)
13221 error ("argument 1 must be a 5-bit signed literal");
13222 return CONST0_RTX (tmode);
13227 || GET_MODE (target) != tmode
13228 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13229 target = gen_reg_rtx (tmode);
13231 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13232 op0 = copy_to_mode_reg (mode0, op0);
13234 pat = GEN_FCN (icode) (target, op0);
13243 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13245 rtx pat, scratch1, scratch2;
13246 tree arg0 = CALL_EXPR_ARG (exp, 0);
13247 rtx op0 = expand_normal (arg0);
13248 machine_mode tmode = insn_data[icode].operand[0].mode;
13249 machine_mode mode0 = insn_data[icode].operand[1].mode;
13251 /* If we have invalid arguments, bail out before generating bad rtl. */
13252 if (arg0 == error_mark_node)
13256 || GET_MODE (target) != tmode
13257 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13258 target = gen_reg_rtx (tmode);
13260 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13261 op0 = copy_to_mode_reg (mode0, op0);
13263 scratch1 = gen_reg_rtx (mode0);
13264 scratch2 = gen_reg_rtx (mode0);
13266 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13275 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13278 tree arg0 = CALL_EXPR_ARG (exp, 0);
13279 tree arg1 = CALL_EXPR_ARG (exp, 1);
13280 rtx op0 = expand_normal (arg0);
13281 rtx op1 = expand_normal (arg1);
13282 machine_mode tmode = insn_data[icode].operand[0].mode;
13283 machine_mode mode0 = insn_data[icode].operand[1].mode;
13284 machine_mode mode1 = insn_data[icode].operand[2].mode;
13286 if (icode == CODE_FOR_nothing)
13287 /* Builtin not supported on this processor. */
13290 /* If we got invalid arguments bail out before generating bad rtl. */
13291 if (arg0 == error_mark_node || arg1 == error_mark_node)
13294 if (icode == CODE_FOR_unpackv1ti
13295 || icode == CODE_FOR_unpackkf
13296 || icode == CODE_FOR_unpacktf
13297 || icode == CODE_FOR_unpackif
13298 || icode == CODE_FOR_unpacktd)
13300 /* Only allow 1-bit unsigned literals. */
13302 if (TREE_CODE (arg1) != INTEGER_CST
13303 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13305 error ("argument 2 must be a 1-bit unsigned literal");
13306 return CONST0_RTX (tmode);
13309 else if (icode == CODE_FOR_altivec_vspltw)
13311 /* Only allow 2-bit unsigned literals. */
13313 if (TREE_CODE (arg1) != INTEGER_CST
13314 || TREE_INT_CST_LOW (arg1) & ~3)
13316 error ("argument 2 must be a 2-bit unsigned literal");
13317 return CONST0_RTX (tmode);
13320 else if (icode == CODE_FOR_altivec_vsplth)
13322 /* Only allow 3-bit unsigned literals. */
13324 if (TREE_CODE (arg1) != INTEGER_CST
13325 || TREE_INT_CST_LOW (arg1) & ~7)
13327 error ("argument 2 must be a 3-bit unsigned literal");
13328 return CONST0_RTX (tmode);
13331 else if (icode == CODE_FOR_altivec_vspltb)
13333 /* Only allow 4-bit unsigned literals. */
13335 if (TREE_CODE (arg1) != INTEGER_CST
13336 || TREE_INT_CST_LOW (arg1) & ~15)
13338 error ("argument 2 must be a 4-bit unsigned literal");
13339 return CONST0_RTX (tmode);
13342 else if (icode == CODE_FOR_altivec_vcfux
13343 || icode == CODE_FOR_altivec_vcfsx
13344 || icode == CODE_FOR_altivec_vctsxs
13345 || icode == CODE_FOR_altivec_vctuxs)
13347 /* Only allow 5-bit unsigned literals. */
13349 if (TREE_CODE (arg1) != INTEGER_CST
13350 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13352 error ("argument 2 must be a 5-bit unsigned literal");
13353 return CONST0_RTX (tmode);
13356 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13357 || icode == CODE_FOR_dfptstsfi_lt_dd
13358 || icode == CODE_FOR_dfptstsfi_gt_dd
13359 || icode == CODE_FOR_dfptstsfi_unordered_dd
13360 || icode == CODE_FOR_dfptstsfi_eq_td
13361 || icode == CODE_FOR_dfptstsfi_lt_td
13362 || icode == CODE_FOR_dfptstsfi_gt_td
13363 || icode == CODE_FOR_dfptstsfi_unordered_td)
13365 /* Only allow 6-bit unsigned literals. */
13367 if (TREE_CODE (arg0) != INTEGER_CST
13368 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13370 error ("argument 1 must be a 6-bit unsigned literal");
13371 return CONST0_RTX (tmode);
13374 else if (icode == CODE_FOR_xststdcqp_kf
13375 || icode == CODE_FOR_xststdcqp_tf
13376 || icode == CODE_FOR_xststdcdp
13377 || icode == CODE_FOR_xststdcsp
13378 || icode == CODE_FOR_xvtstdcdp
13379 || icode == CODE_FOR_xvtstdcsp)
13381 /* Only allow 7-bit unsigned literals. */
13383 if (TREE_CODE (arg1) != INTEGER_CST
13384 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13386 error ("argument 2 must be a 7-bit unsigned literal");
13387 return CONST0_RTX (tmode);
13392 || GET_MODE (target) != tmode
13393 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13394 target = gen_reg_rtx (tmode);
13396 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13397 op0 = copy_to_mode_reg (mode0, op0);
13398 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13399 op1 = copy_to_mode_reg (mode1, op1);
13401 pat = GEN_FCN (icode) (target, op0, op1);
13410 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13413 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13414 tree arg0 = CALL_EXPR_ARG (exp, 1);
13415 tree arg1 = CALL_EXPR_ARG (exp, 2);
13416 rtx op0 = expand_normal (arg0);
13417 rtx op1 = expand_normal (arg1);
13418 machine_mode tmode = SImode;
13419 machine_mode mode0 = insn_data[icode].operand[1].mode;
13420 machine_mode mode1 = insn_data[icode].operand[2].mode;
13423 if (TREE_CODE (cr6_form) != INTEGER_CST)
13425 error ("argument 1 of %qs must be a constant",
13426 "__builtin_altivec_predicate");
13430 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13432 gcc_assert (mode0 == mode1);
13434 /* If we have invalid arguments, bail out before generating bad rtl. */
13435 if (arg0 == error_mark_node || arg1 == error_mark_node)
13439 || GET_MODE (target) != tmode
13440 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13441 target = gen_reg_rtx (tmode);
13443 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13444 op0 = copy_to_mode_reg (mode0, op0);
13445 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13446 op1 = copy_to_mode_reg (mode1, op1);
13448 /* Note that for many of the relevant operations (e.g. cmpne or
13449 cmpeq) with float or double operands, it makes more sense for the
13450 mode of the allocated scratch register to select a vector of
13451 integer. But the choice to copy the mode of operand 0 was made
13452 long ago and there are no plans to change it. */
13453 scratch = gen_reg_rtx (mode0);
13455 pat = GEN_FCN (icode) (scratch, op0, op1);
13460 /* The vec_any* and vec_all* predicates use the same opcodes for two
13461 different operations, but the bits in CR6 will be different
13462 depending on what information we want. So we have to play tricks
13463 with CR6 to get the right bits out.
13465 If you think this is disgusting, look at the specs for the
13466 AltiVec predicates. */
13468 switch (cr6_form_int)
13471 emit_insn (gen_cr6_test_for_zero (target));
13474 emit_insn (gen_cr6_test_for_zero_reverse (target));
13477 emit_insn (gen_cr6_test_for_lt (target));
13480 emit_insn (gen_cr6_test_for_lt_reverse (target));
13483 error ("argument 1 of %qs is out of range",
13484 "__builtin_altivec_predicate");
13492 swap_endian_selector_for_mode (machine_mode mode)
13494 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13495 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13496 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13497 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13499 unsigned int *swaparray, i;
13519 gcc_unreachable ();
13522 for (i = 0; i < 16; ++i)
13523 perm[i] = GEN_INT (swaparray[i]);
13525 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13526 gen_rtvec_v (16, perm)));
13530 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13533 tree arg0 = CALL_EXPR_ARG (exp, 0);
13534 tree arg1 = CALL_EXPR_ARG (exp, 1);
13535 machine_mode tmode = insn_data[icode].operand[0].mode;
13536 machine_mode mode0 = Pmode;
13537 machine_mode mode1 = Pmode;
13538 rtx op0 = expand_normal (arg0);
13539 rtx op1 = expand_normal (arg1);
13541 if (icode == CODE_FOR_nothing)
13542 /* Builtin not supported on this processor. */
13545 /* If we got invalid arguments bail out before generating bad rtl. */
13546 if (arg0 == error_mark_node || arg1 == error_mark_node)
13550 || GET_MODE (target) != tmode
13551 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13552 target = gen_reg_rtx (tmode);
13554 op1 = copy_to_mode_reg (mode1, op1);
13556 /* For LVX, express the RTL accurately by ANDing the address with -16.
13557 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13558 so the raw address is fine. */
13559 if (icode == CODE_FOR_altivec_lvx_v1ti
13560 || icode == CODE_FOR_altivec_lvx_v2df
13561 || icode == CODE_FOR_altivec_lvx_v2di
13562 || icode == CODE_FOR_altivec_lvx_v4sf
13563 || icode == CODE_FOR_altivec_lvx_v4si
13564 || icode == CODE_FOR_altivec_lvx_v8hi
13565 || icode == CODE_FOR_altivec_lvx_v16qi)
13568 if (op0 == const0_rtx)
13572 op0 = copy_to_mode_reg (mode0, op0);
13573 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13575 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13576 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13578 emit_insn (gen_rtx_SET (target, addr));
13582 if (op0 == const0_rtx)
13583 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13586 op0 = copy_to_mode_reg (mode0, op0);
13587 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13588 gen_rtx_PLUS (Pmode, op1, op0));
13591 pat = GEN_FCN (icode) (target, addr);
13601 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13604 tree arg0 = CALL_EXPR_ARG (exp, 0);
13605 tree arg1 = CALL_EXPR_ARG (exp, 1);
13606 tree arg2 = CALL_EXPR_ARG (exp, 2);
13607 rtx op0 = expand_normal (arg0);
13608 rtx op1 = expand_normal (arg1);
13609 rtx op2 = expand_normal (arg2);
13610 machine_mode mode0 = insn_data[icode].operand[0].mode;
13611 machine_mode mode1 = insn_data[icode].operand[1].mode;
13612 machine_mode mode2 = insn_data[icode].operand[2].mode;
13614 if (icode == CODE_FOR_nothing)
13615 /* Builtin not supported on this processor. */
13618 /* If we got invalid arguments bail out before generating bad rtl. */
13619 if (arg0 == error_mark_node
13620 || arg1 == error_mark_node
13621 || arg2 == error_mark_node)
13624 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13625 op0 = copy_to_mode_reg (mode0, op0);
13626 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13627 op1 = copy_to_mode_reg (mode1, op1);
13628 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13629 op2 = copy_to_mode_reg (mode2, op2);
13631 pat = GEN_FCN (icode) (op0, op1, op2);
13639 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13641 tree arg0 = CALL_EXPR_ARG (exp, 0);
13642 tree arg1 = CALL_EXPR_ARG (exp, 1);
13643 tree arg2 = CALL_EXPR_ARG (exp, 2);
13644 rtx op0 = expand_normal (arg0);
13645 rtx op1 = expand_normal (arg1);
13646 rtx op2 = expand_normal (arg2);
13647 rtx pat, addr, rawaddr;
13648 machine_mode tmode = insn_data[icode].operand[0].mode;
13649 machine_mode smode = insn_data[icode].operand[1].mode;
13650 machine_mode mode1 = Pmode;
13651 machine_mode mode2 = Pmode;
13653 /* Invalid arguments. Bail before doing anything stoopid! */
13654 if (arg0 == error_mark_node
13655 || arg1 == error_mark_node
13656 || arg2 == error_mark_node)
13659 op2 = copy_to_mode_reg (mode2, op2);
13661 /* For STVX, express the RTL accurately by ANDing the address with -16.
13662 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13663 so the raw address is fine. */
13664 if (icode == CODE_FOR_altivec_stvx_v2df
13665 || icode == CODE_FOR_altivec_stvx_v2di
13666 || icode == CODE_FOR_altivec_stvx_v4sf
13667 || icode == CODE_FOR_altivec_stvx_v4si
13668 || icode == CODE_FOR_altivec_stvx_v8hi
13669 || icode == CODE_FOR_altivec_stvx_v16qi)
13671 if (op1 == const0_rtx)
13675 op1 = copy_to_mode_reg (mode1, op1);
13676 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13679 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13680 addr = gen_rtx_MEM (tmode, addr);
13682 op0 = copy_to_mode_reg (tmode, op0);
13684 emit_insn (gen_rtx_SET (addr, op0));
13688 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13689 op0 = copy_to_mode_reg (smode, op0);
13691 if (op1 == const0_rtx)
13692 addr = gen_rtx_MEM (tmode, op2);
13695 op1 = copy_to_mode_reg (mode1, op1);
13696 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13699 pat = GEN_FCN (icode) (addr, op0);
13707 /* Return the appropriate SPR number associated with the given builtin. */
13708 static inline HOST_WIDE_INT
13709 htm_spr_num (enum rs6000_builtins code)
13711 if (code == HTM_BUILTIN_GET_TFHAR
13712 || code == HTM_BUILTIN_SET_TFHAR)
13714 else if (code == HTM_BUILTIN_GET_TFIAR
13715 || code == HTM_BUILTIN_SET_TFIAR)
13717 else if (code == HTM_BUILTIN_GET_TEXASR
13718 || code == HTM_BUILTIN_SET_TEXASR)
13720 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13721 || code == HTM_BUILTIN_SET_TEXASRU);
13722 return TEXASRU_SPR;
13725 /* Return the correct ICODE value depending on whether we are
13726 setting or reading the HTM SPRs. */
13727 static inline enum insn_code
13728 rs6000_htm_spr_icode (bool nonvoid)
13731 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13733 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13736 /* Expand the HTM builtin in EXP and store the result in TARGET.
13737 Store true in *EXPANDEDP if we found a builtin to expand. */
13739 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
13741 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13742 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
13743 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13744 const struct builtin_description *d;
13749 if (!TARGET_POWERPC64
13750 && (fcode == HTM_BUILTIN_TABORTDC
13751 || fcode == HTM_BUILTIN_TABORTDCI))
13753 size_t uns_fcode = (size_t)fcode;
13754 const char *name = rs6000_builtin_info[uns_fcode].name;
13755 error ("builtin %qs is only valid in 64-bit mode", name);
13759 /* Expand the HTM builtins. */
13761 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13762 if (d->code == fcode)
13764 rtx op[MAX_HTM_OPERANDS], pat;
13767 call_expr_arg_iterator iter;
13768 unsigned attr = rs6000_builtin_info[fcode].attr;
13769 enum insn_code icode = d->icode;
13770 const struct insn_operand_data *insn_op;
13771 bool uses_spr = (attr & RS6000_BTC_SPR);
13775 icode = rs6000_htm_spr_icode (nonvoid);
13776 insn_op = &insn_data[icode].operand[0];
13780 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
13782 || GET_MODE (target) != tmode
13783 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
13784 target = gen_reg_rtx (tmode);
13786 op[nopnds++] = target;
13789 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
13791 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
13794 insn_op = &insn_data[icode].operand[nopnds];
13796 op[nopnds] = expand_normal (arg);
13798 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
13800 if (!strcmp (insn_op->constraint, "n"))
13802 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
13803 if (!CONST_INT_P (op[nopnds]))
13804 error ("argument %d must be an unsigned literal", arg_num);
13806 error ("argument %d is an unsigned literal that is "
13807 "out of range", arg_num);
13810 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
13816 /* Handle the builtins for extended mnemonics. These accept
13817 no arguments, but map to builtins that take arguments. */
13820 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
13821 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
13822 op[nopnds++] = GEN_INT (1);
13824 attr |= RS6000_BTC_UNARY;
13826 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
13827 op[nopnds++] = GEN_INT (0);
13829 attr |= RS6000_BTC_UNARY;
13835 /* If this builtin accesses SPRs, then pass in the appropriate
13836 SPR number and SPR regno as the last two operands. */
13839 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
13840 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
13842 /* If this builtin accesses a CR, then pass in a scratch
13843 CR as the last operand. */
13844 else if (attr & RS6000_BTC_CR)
13845 { cr = gen_reg_rtx (CCmode);
13851 int expected_nopnds = 0;
13852 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
13853 expected_nopnds = 1;
13854 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
13855 expected_nopnds = 2;
13856 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
13857 expected_nopnds = 3;
13858 if (!(attr & RS6000_BTC_VOID))
13859 expected_nopnds += 1;
13861 expected_nopnds += 1;
13863 gcc_assert (nopnds == expected_nopnds
13864 && nopnds <= MAX_HTM_OPERANDS);
13870 pat = GEN_FCN (icode) (op[0]);
13873 pat = GEN_FCN (icode) (op[0], op[1]);
13876 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
13879 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
13882 gcc_unreachable ();
13888 if (attr & RS6000_BTC_CR)
13890 if (fcode == HTM_BUILTIN_TBEGIN)
13892 /* Emit code to set TARGET to true or false depending on
13893 whether the tbegin. instruction successfully or failed
13894 to start a transaction. We do this by placing the 1's
13895 complement of CR's EQ bit into TARGET. */
13896 rtx scratch = gen_reg_rtx (SImode);
13897 emit_insn (gen_rtx_SET (scratch,
13898 gen_rtx_EQ (SImode, cr,
13900 emit_insn (gen_rtx_SET (target,
13901 gen_rtx_XOR (SImode, scratch,
13906 /* Emit code to copy the 4-bit condition register field
13907 CR into the least significant end of register TARGET. */
13908 rtx scratch1 = gen_reg_rtx (SImode);
13909 rtx scratch2 = gen_reg_rtx (SImode);
13910 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
13911 emit_insn (gen_movcc (subreg, cr));
13912 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
13913 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
13922 *expandedp = false;
13926 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
13929 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
13932 /* __builtin_cpu_init () is a nop, so expand to nothing. */
13933 if (fcode == RS6000_BUILTIN_CPU_INIT)
13936 if (target == 0 || GET_MODE (target) != SImode)
13937 target = gen_reg_rtx (SImode);
13939 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
13940 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
13941 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
13942 to a STRING_CST. */
13943 if (TREE_CODE (arg) == ARRAY_REF
13944 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
13945 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
13946 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
13947 arg = TREE_OPERAND (arg, 0);
13949 if (TREE_CODE (arg) != STRING_CST)
13951 error ("builtin %qs only accepts a string argument",
13952 rs6000_builtin_info[(size_t) fcode].name);
13956 if (fcode == RS6000_BUILTIN_CPU_IS)
13958 const char *cpu = TREE_STRING_POINTER (arg);
13959 rtx cpuid = NULL_RTX;
13960 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
13961 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
13963 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
13964 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
13967 if (cpuid == NULL_RTX)
13969 /* Invalid CPU argument. */
13970 error ("cpu %qs is an invalid argument to builtin %qs",
13971 cpu, rs6000_builtin_info[(size_t) fcode].name);
13975 rtx platform = gen_reg_rtx (SImode);
13976 rtx tcbmem = gen_const_mem (SImode,
13977 gen_rtx_PLUS (Pmode,
13978 gen_rtx_REG (Pmode, TLS_REGNUM),
13979 GEN_INT (TCB_PLATFORM_OFFSET)));
13980 emit_move_insn (platform, tcbmem);
13981 emit_insn (gen_eqsi3 (target, platform, cpuid));
13983 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
13985 const char *hwcap = TREE_STRING_POINTER (arg);
13986 rtx mask = NULL_RTX;
13988 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
13989 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
13991 mask = GEN_INT (cpu_supports_info[i].mask);
13992 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
13995 if (mask == NULL_RTX)
13997 /* Invalid HWCAP argument. */
13998 error ("%s %qs is an invalid argument to builtin %qs",
13999 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14003 rtx tcb_hwcap = gen_reg_rtx (SImode);
14004 rtx tcbmem = gen_const_mem (SImode,
14005 gen_rtx_PLUS (Pmode,
14006 gen_rtx_REG (Pmode, TLS_REGNUM),
14007 GEN_INT (hwcap_offset)));
14008 emit_move_insn (tcb_hwcap, tcbmem);
14009 rtx scratch1 = gen_reg_rtx (SImode);
14010 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14011 rtx scratch2 = gen_reg_rtx (SImode);
14012 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14013 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14016 gcc_unreachable ();
14018 /* Record that we have expanded a CPU builtin, so that we can later
14019 emit a reference to the special symbol exported by LIBC to ensure we
14020 do not link against an old LIBC that doesn't support this feature. */
14021 cpu_builtin_p = true;
14024 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14025 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14027 /* For old LIBCs, always return FALSE. */
14028 emit_move_insn (target, GEN_INT (0));
14029 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14035 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14038 tree arg0 = CALL_EXPR_ARG (exp, 0);
14039 tree arg1 = CALL_EXPR_ARG (exp, 1);
14040 tree arg2 = CALL_EXPR_ARG (exp, 2);
14041 rtx op0 = expand_normal (arg0);
14042 rtx op1 = expand_normal (arg1);
14043 rtx op2 = expand_normal (arg2);
14044 machine_mode tmode = insn_data[icode].operand[0].mode;
14045 machine_mode mode0 = insn_data[icode].operand[1].mode;
14046 machine_mode mode1 = insn_data[icode].operand[2].mode;
14047 machine_mode mode2 = insn_data[icode].operand[3].mode;
14049 if (icode == CODE_FOR_nothing)
14050 /* Builtin not supported on this processor. */
14053 /* If we got invalid arguments bail out before generating bad rtl. */
14054 if (arg0 == error_mark_node
14055 || arg1 == error_mark_node
14056 || arg2 == error_mark_node)
14059 /* Check and prepare argument depending on the instruction code.
14061 Note that a switch statement instead of the sequence of tests
14062 would be incorrect as many of the CODE_FOR values could be
14063 CODE_FOR_nothing and that would yield multiple alternatives
14064 with identical values. We'd never reach here at runtime in
14066 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14067 || icode == CODE_FOR_altivec_vsldoi_v2df
14068 || icode == CODE_FOR_altivec_vsldoi_v4si
14069 || icode == CODE_FOR_altivec_vsldoi_v8hi
14070 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14072 /* Only allow 4-bit unsigned literals. */
14074 if (TREE_CODE (arg2) != INTEGER_CST
14075 || TREE_INT_CST_LOW (arg2) & ~0xf)
14077 error ("argument 3 must be a 4-bit unsigned literal");
14078 return CONST0_RTX (tmode);
14081 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14082 || icode == CODE_FOR_vsx_xxpermdi_v2di
14083 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14084 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14085 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14086 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14087 || icode == CODE_FOR_vsx_xxpermdi_v4si
14088 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14089 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14090 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14091 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14092 || icode == CODE_FOR_vsx_xxsldwi_v4si
14093 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14094 || icode == CODE_FOR_vsx_xxsldwi_v2di
14095 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14097 /* Only allow 2-bit unsigned literals. */
14099 if (TREE_CODE (arg2) != INTEGER_CST
14100 || TREE_INT_CST_LOW (arg2) & ~0x3)
14102 error ("argument 3 must be a 2-bit unsigned literal");
14103 return CONST0_RTX (tmode);
14106 else if (icode == CODE_FOR_vsx_set_v2df
14107 || icode == CODE_FOR_vsx_set_v2di
14108 || icode == CODE_FOR_bcdadd
14109 || icode == CODE_FOR_bcdadd_lt
14110 || icode == CODE_FOR_bcdadd_eq
14111 || icode == CODE_FOR_bcdadd_gt
14112 || icode == CODE_FOR_bcdsub
14113 || icode == CODE_FOR_bcdsub_lt
14114 || icode == CODE_FOR_bcdsub_eq
14115 || icode == CODE_FOR_bcdsub_gt)
14117 /* Only allow 1-bit unsigned literals. */
14119 if (TREE_CODE (arg2) != INTEGER_CST
14120 || TREE_INT_CST_LOW (arg2) & ~0x1)
14122 error ("argument 3 must be a 1-bit unsigned literal");
14123 return CONST0_RTX (tmode);
14126 else if (icode == CODE_FOR_dfp_ddedpd_dd
14127 || icode == CODE_FOR_dfp_ddedpd_td)
14129 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14131 if (TREE_CODE (arg0) != INTEGER_CST
14132 || TREE_INT_CST_LOW (arg2) & ~0x3)
14134 error ("argument 1 must be 0 or 2");
14135 return CONST0_RTX (tmode);
14138 else if (icode == CODE_FOR_dfp_denbcd_dd
14139 || icode == CODE_FOR_dfp_denbcd_td)
14141 /* Only allow 1-bit unsigned literals. */
14143 if (TREE_CODE (arg0) != INTEGER_CST
14144 || TREE_INT_CST_LOW (arg0) & ~0x1)
14146 error ("argument 1 must be a 1-bit unsigned literal");
14147 return CONST0_RTX (tmode);
14150 else if (icode == CODE_FOR_dfp_dscli_dd
14151 || icode == CODE_FOR_dfp_dscli_td
14152 || icode == CODE_FOR_dfp_dscri_dd
14153 || icode == CODE_FOR_dfp_dscri_td)
14155 /* Only allow 6-bit unsigned literals. */
14157 if (TREE_CODE (arg1) != INTEGER_CST
14158 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14160 error ("argument 2 must be a 6-bit unsigned literal");
14161 return CONST0_RTX (tmode);
14164 else if (icode == CODE_FOR_crypto_vshasigmaw
14165 || icode == CODE_FOR_crypto_vshasigmad)
14167 /* Check whether the 2nd and 3rd arguments are integer constants and in
14168 range and prepare arguments. */
14170 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14172 error ("argument 2 must be 0 or 1");
14173 return CONST0_RTX (tmode);
14177 if (TREE_CODE (arg2) != INTEGER_CST
14178 || wi::geu_p (wi::to_wide (arg2), 16))
14180 error ("argument 3 must be in the range [0, 15]");
14181 return CONST0_RTX (tmode);
14186 || GET_MODE (target) != tmode
14187 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14188 target = gen_reg_rtx (tmode);
14190 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14191 op0 = copy_to_mode_reg (mode0, op0);
14192 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14193 op1 = copy_to_mode_reg (mode1, op1);
14194 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14195 op2 = copy_to_mode_reg (mode2, op2);
14197 pat = GEN_FCN (icode) (target, op0, op1, op2);
14206 /* Expand the dst builtins. */
14208 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14211 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14212 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14213 tree arg0, arg1, arg2;
14214 machine_mode mode0, mode1;
14215 rtx pat, op0, op1, op2;
14216 const struct builtin_description *d;
14219 *expandedp = false;
14221 /* Handle DST variants. */
14223 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14224 if (d->code == fcode)
14226 arg0 = CALL_EXPR_ARG (exp, 0);
14227 arg1 = CALL_EXPR_ARG (exp, 1);
14228 arg2 = CALL_EXPR_ARG (exp, 2);
14229 op0 = expand_normal (arg0);
14230 op1 = expand_normal (arg1);
14231 op2 = expand_normal (arg2);
14232 mode0 = insn_data[d->icode].operand[0].mode;
14233 mode1 = insn_data[d->icode].operand[1].mode;
14235 /* Invalid arguments, bail out before generating bad rtl. */
14236 if (arg0 == error_mark_node
14237 || arg1 == error_mark_node
14238 || arg2 == error_mark_node)
14243 if (TREE_CODE (arg2) != INTEGER_CST
14244 || TREE_INT_CST_LOW (arg2) & ~0x3)
14246 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14250 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14251 op0 = copy_to_mode_reg (Pmode, op0);
14252 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14253 op1 = copy_to_mode_reg (mode1, op1);
14255 pat = GEN_FCN (d->icode) (op0, op1, op2);
14265 /* Expand vec_init builtin. */
14267 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14269 machine_mode tmode = TYPE_MODE (type);
14270 machine_mode inner_mode = GET_MODE_INNER (tmode);
14271 int i, n_elt = GET_MODE_NUNITS (tmode);
14273 gcc_assert (VECTOR_MODE_P (tmode));
14274 gcc_assert (n_elt == call_expr_nargs (exp));
14276 if (!target || !register_operand (target, tmode))
14277 target = gen_reg_rtx (tmode);
14279 /* If we have a vector compromised of a single element, such as V1TImode, do
14280 the initialization directly. */
14281 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14283 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14284 emit_move_insn (target, gen_lowpart (tmode, x));
14288 rtvec v = rtvec_alloc (n_elt);
14290 for (i = 0; i < n_elt; ++i)
14292 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14293 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14296 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14302 /* Return the integer constant in ARG. Constrain it to be in the range
14303 of the subparts of VEC_TYPE; issue an error if not. */
14306 get_element_number (tree vec_type, tree arg)
14308 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14310 if (!tree_fits_uhwi_p (arg)
14311 || (elt = tree_to_uhwi (arg), elt > max))
14313 error ("selector must be an integer constant in the range [0, %wi]", max);
14320 /* Expand vec_set builtin. */
14322 altivec_expand_vec_set_builtin (tree exp)
14324 machine_mode tmode, mode1;
14325 tree arg0, arg1, arg2;
14329 arg0 = CALL_EXPR_ARG (exp, 0);
14330 arg1 = CALL_EXPR_ARG (exp, 1);
14331 arg2 = CALL_EXPR_ARG (exp, 2);
14333 tmode = TYPE_MODE (TREE_TYPE (arg0));
14334 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14335 gcc_assert (VECTOR_MODE_P (tmode));
14337 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14338 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14339 elt = get_element_number (TREE_TYPE (arg0), arg2);
14341 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14342 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14344 op0 = force_reg (tmode, op0);
14345 op1 = force_reg (mode1, op1);
14347 rs6000_expand_vector_set (op0, op1, elt);
14352 /* Expand vec_ext builtin. */
14354 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14356 machine_mode tmode, mode0;
14361 arg0 = CALL_EXPR_ARG (exp, 0);
14362 arg1 = CALL_EXPR_ARG (exp, 1);
14364 op0 = expand_normal (arg0);
14365 op1 = expand_normal (arg1);
14367 if (TREE_CODE (arg1) == INTEGER_CST)
14369 unsigned HOST_WIDE_INT elt;
14370 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
14371 unsigned int truncated_selector;
14372 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14373 returns low-order bits of INTEGER_CST for modulo indexing. */
14374 elt = TREE_INT_CST_LOW (arg1);
14375 truncated_selector = elt % size;
14376 op1 = GEN_INT (truncated_selector);
14379 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14380 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14381 gcc_assert (VECTOR_MODE_P (mode0));
14383 op0 = force_reg (mode0, op0);
14385 if (optimize || !target || !register_operand (target, tmode))
14386 target = gen_reg_rtx (tmode);
14388 rs6000_expand_vector_extract (target, op0, op1);
14393 /* Expand the builtin in EXP and store the result in TARGET. Store
14394 true in *EXPANDEDP if we found a builtin to expand. */
14396 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14398 const struct builtin_description *d;
14400 enum insn_code icode;
14401 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14402 tree arg0, arg1, arg2;
14404 machine_mode tmode, mode0;
14405 enum rs6000_builtins fcode
14406 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14408 if (rs6000_overloaded_builtin_p (fcode))
14411 error ("unresolved overload for Altivec builtin %qF", fndecl);
14413 /* Given it is invalid, just generate a normal call. */
14414 return expand_call (exp, target, false);
14417 target = altivec_expand_dst_builtin (exp, target, expandedp);
14425 case ALTIVEC_BUILTIN_STVX_V2DF:
14426 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14427 case ALTIVEC_BUILTIN_STVX_V2DI:
14428 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14429 case ALTIVEC_BUILTIN_STVX_V4SF:
14430 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14431 case ALTIVEC_BUILTIN_STVX:
14432 case ALTIVEC_BUILTIN_STVX_V4SI:
14433 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14434 case ALTIVEC_BUILTIN_STVX_V8HI:
14435 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14436 case ALTIVEC_BUILTIN_STVX_V16QI:
14437 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14438 case ALTIVEC_BUILTIN_STVEBX:
14439 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14440 case ALTIVEC_BUILTIN_STVEHX:
14441 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14442 case ALTIVEC_BUILTIN_STVEWX:
14443 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14444 case ALTIVEC_BUILTIN_STVXL_V2DF:
14445 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14446 case ALTIVEC_BUILTIN_STVXL_V2DI:
14447 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14448 case ALTIVEC_BUILTIN_STVXL_V4SF:
14449 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14450 case ALTIVEC_BUILTIN_STVXL:
14451 case ALTIVEC_BUILTIN_STVXL_V4SI:
14452 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14453 case ALTIVEC_BUILTIN_STVXL_V8HI:
14454 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14455 case ALTIVEC_BUILTIN_STVXL_V16QI:
14456 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14458 case ALTIVEC_BUILTIN_STVLX:
14459 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14460 case ALTIVEC_BUILTIN_STVLXL:
14461 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14462 case ALTIVEC_BUILTIN_STVRX:
14463 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14464 case ALTIVEC_BUILTIN_STVRXL:
14465 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14467 case P9V_BUILTIN_STXVL:
14468 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14470 case P9V_BUILTIN_XST_LEN_R:
14471 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14473 case VSX_BUILTIN_STXVD2X_V1TI:
14474 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14475 case VSX_BUILTIN_STXVD2X_V2DF:
14476 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14477 case VSX_BUILTIN_STXVD2X_V2DI:
14478 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14479 case VSX_BUILTIN_STXVW4X_V4SF:
14480 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14481 case VSX_BUILTIN_STXVW4X_V4SI:
14482 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14483 case VSX_BUILTIN_STXVW4X_V8HI:
14484 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14485 case VSX_BUILTIN_STXVW4X_V16QI:
14486 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14488 /* For the following on big endian, it's ok to use any appropriate
14489 unaligned-supporting store, so use a generic expander. For
14490 little-endian, the exact element-reversing instruction must
14492 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14494 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14495 : CODE_FOR_vsx_st_elemrev_v1ti);
14496 return altivec_expand_stv_builtin (code, exp);
14498 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14500 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14501 : CODE_FOR_vsx_st_elemrev_v2df);
14502 return altivec_expand_stv_builtin (code, exp);
14504 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14506 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14507 : CODE_FOR_vsx_st_elemrev_v2di);
14508 return altivec_expand_stv_builtin (code, exp);
14510 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14512 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14513 : CODE_FOR_vsx_st_elemrev_v4sf);
14514 return altivec_expand_stv_builtin (code, exp);
14516 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14518 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14519 : CODE_FOR_vsx_st_elemrev_v4si);
14520 return altivec_expand_stv_builtin (code, exp);
14522 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14524 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14525 : CODE_FOR_vsx_st_elemrev_v8hi);
14526 return altivec_expand_stv_builtin (code, exp);
14528 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14530 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14531 : CODE_FOR_vsx_st_elemrev_v16qi);
14532 return altivec_expand_stv_builtin (code, exp);
14535 case ALTIVEC_BUILTIN_MFVSCR:
14536 icode = CODE_FOR_altivec_mfvscr;
14537 tmode = insn_data[icode].operand[0].mode;
14540 || GET_MODE (target) != tmode
14541 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14542 target = gen_reg_rtx (tmode);
14544 pat = GEN_FCN (icode) (target);
14550 case ALTIVEC_BUILTIN_MTVSCR:
14551 icode = CODE_FOR_altivec_mtvscr;
14552 arg0 = CALL_EXPR_ARG (exp, 0);
14553 op0 = expand_normal (arg0);
14554 mode0 = insn_data[icode].operand[0].mode;
14556 /* If we got invalid arguments bail out before generating bad rtl. */
14557 if (arg0 == error_mark_node)
14560 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14561 op0 = copy_to_mode_reg (mode0, op0);
14563 pat = GEN_FCN (icode) (op0);
14568 case ALTIVEC_BUILTIN_DSSALL:
14569 emit_insn (gen_altivec_dssall ());
14572 case ALTIVEC_BUILTIN_DSS:
14573 icode = CODE_FOR_altivec_dss;
14574 arg0 = CALL_EXPR_ARG (exp, 0);
14576 op0 = expand_normal (arg0);
14577 mode0 = insn_data[icode].operand[0].mode;
14579 /* If we got invalid arguments bail out before generating bad rtl. */
14580 if (arg0 == error_mark_node)
14583 if (TREE_CODE (arg0) != INTEGER_CST
14584 || TREE_INT_CST_LOW (arg0) & ~0x3)
14586 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14590 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14591 op0 = copy_to_mode_reg (mode0, op0);
14593 emit_insn (gen_altivec_dss (op0));
14596 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14597 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14598 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14599 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14600 case VSX_BUILTIN_VEC_INIT_V2DF:
14601 case VSX_BUILTIN_VEC_INIT_V2DI:
14602 case VSX_BUILTIN_VEC_INIT_V1TI:
14603 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14605 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14606 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14607 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14608 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14609 case VSX_BUILTIN_VEC_SET_V2DF:
14610 case VSX_BUILTIN_VEC_SET_V2DI:
14611 case VSX_BUILTIN_VEC_SET_V1TI:
14612 return altivec_expand_vec_set_builtin (exp);
14614 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14615 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14616 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14617 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14618 case VSX_BUILTIN_VEC_EXT_V2DF:
14619 case VSX_BUILTIN_VEC_EXT_V2DI:
14620 case VSX_BUILTIN_VEC_EXT_V1TI:
14621 return altivec_expand_vec_ext_builtin (exp, target);
14623 case P9V_BUILTIN_VEC_EXTRACT4B:
14624 arg1 = CALL_EXPR_ARG (exp, 1);
14627 /* Generate a normal call if it is invalid. */
14628 if (arg1 == error_mark_node)
14629 return expand_call (exp, target, false);
14631 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14633 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
14634 return expand_call (exp, target, false);
14638 case P9V_BUILTIN_VEC_INSERT4B:
14639 arg2 = CALL_EXPR_ARG (exp, 2);
14642 /* Generate a normal call if it is invalid. */
14643 if (arg2 == error_mark_node)
14644 return expand_call (exp, target, false);
14646 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14648 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
14649 return expand_call (exp, target, false);
14655 /* Fall through. */
14658 /* Expand abs* operations. */
14660 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14661 if (d->code == fcode)
14662 return altivec_expand_abs_builtin (d->icode, exp, target);
14664 /* Expand the AltiVec predicates. */
14665 d = bdesc_altivec_preds;
14666 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14667 if (d->code == fcode)
14668 return altivec_expand_predicate_builtin (d->icode, exp, target);
14670 /* LV* are funky. We initialized them differently. */
14673 case ALTIVEC_BUILTIN_LVSL:
14674 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14675 exp, target, false);
14676 case ALTIVEC_BUILTIN_LVSR:
14677 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14678 exp, target, false);
14679 case ALTIVEC_BUILTIN_LVEBX:
14680 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14681 exp, target, false);
14682 case ALTIVEC_BUILTIN_LVEHX:
14683 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14684 exp, target, false);
14685 case ALTIVEC_BUILTIN_LVEWX:
14686 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14687 exp, target, false);
14688 case ALTIVEC_BUILTIN_LVXL_V2DF:
14689 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14690 exp, target, false);
14691 case ALTIVEC_BUILTIN_LVXL_V2DI:
14692 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14693 exp, target, false);
14694 case ALTIVEC_BUILTIN_LVXL_V4SF:
14695 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14696 exp, target, false);
14697 case ALTIVEC_BUILTIN_LVXL:
14698 case ALTIVEC_BUILTIN_LVXL_V4SI:
14699 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14700 exp, target, false);
14701 case ALTIVEC_BUILTIN_LVXL_V8HI:
14702 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14703 exp, target, false);
14704 case ALTIVEC_BUILTIN_LVXL_V16QI:
14705 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14706 exp, target, false);
14707 case ALTIVEC_BUILTIN_LVX_V1TI:
14708 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14709 exp, target, false);
14710 case ALTIVEC_BUILTIN_LVX_V2DF:
14711 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14712 exp, target, false);
14713 case ALTIVEC_BUILTIN_LVX_V2DI:
14714 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14715 exp, target, false);
14716 case ALTIVEC_BUILTIN_LVX_V4SF:
14717 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14718 exp, target, false);
14719 case ALTIVEC_BUILTIN_LVX:
14720 case ALTIVEC_BUILTIN_LVX_V4SI:
14721 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14722 exp, target, false);
14723 case ALTIVEC_BUILTIN_LVX_V8HI:
14724 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14725 exp, target, false);
14726 case ALTIVEC_BUILTIN_LVX_V16QI:
14727 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14728 exp, target, false);
14729 case ALTIVEC_BUILTIN_LVLX:
14730 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14731 exp, target, true);
14732 case ALTIVEC_BUILTIN_LVLXL:
14733 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14734 exp, target, true);
14735 case ALTIVEC_BUILTIN_LVRX:
14736 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14737 exp, target, true);
14738 case ALTIVEC_BUILTIN_LVRXL:
14739 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14740 exp, target, true);
14741 case VSX_BUILTIN_LXVD2X_V1TI:
14742 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14743 exp, target, false);
14744 case VSX_BUILTIN_LXVD2X_V2DF:
14745 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
14746 exp, target, false);
14747 case VSX_BUILTIN_LXVD2X_V2DI:
14748 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
14749 exp, target, false);
14750 case VSX_BUILTIN_LXVW4X_V4SF:
14751 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
14752 exp, target, false);
14753 case VSX_BUILTIN_LXVW4X_V4SI:
14754 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
14755 exp, target, false);
14756 case VSX_BUILTIN_LXVW4X_V8HI:
14757 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
14758 exp, target, false);
14759 case VSX_BUILTIN_LXVW4X_V16QI:
14760 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
14761 exp, target, false);
14762 /* For the following on big endian, it's ok to use any appropriate
14763 unaligned-supporting load, so use a generic expander. For
14764 little-endian, the exact element-reversing instruction must
14766 case VSX_BUILTIN_LD_ELEMREV_V2DF:
14768 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
14769 : CODE_FOR_vsx_ld_elemrev_v2df);
14770 return altivec_expand_lv_builtin (code, exp, target, false);
14772 case VSX_BUILTIN_LD_ELEMREV_V1TI:
14774 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
14775 : CODE_FOR_vsx_ld_elemrev_v1ti);
14776 return altivec_expand_lv_builtin (code, exp, target, false);
14778 case VSX_BUILTIN_LD_ELEMREV_V2DI:
14780 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
14781 : CODE_FOR_vsx_ld_elemrev_v2di);
14782 return altivec_expand_lv_builtin (code, exp, target, false);
14784 case VSX_BUILTIN_LD_ELEMREV_V4SF:
14786 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
14787 : CODE_FOR_vsx_ld_elemrev_v4sf);
14788 return altivec_expand_lv_builtin (code, exp, target, false);
14790 case VSX_BUILTIN_LD_ELEMREV_V4SI:
14792 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
14793 : CODE_FOR_vsx_ld_elemrev_v4si);
14794 return altivec_expand_lv_builtin (code, exp, target, false);
14796 case VSX_BUILTIN_LD_ELEMREV_V8HI:
14798 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
14799 : CODE_FOR_vsx_ld_elemrev_v8hi);
14800 return altivec_expand_lv_builtin (code, exp, target, false);
14802 case VSX_BUILTIN_LD_ELEMREV_V16QI:
14804 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
14805 : CODE_FOR_vsx_ld_elemrev_v16qi);
14806 return altivec_expand_lv_builtin (code, exp, target, false);
14811 /* Fall through. */
14814 *expandedp = false;
14818 /* Check whether a builtin function is supported in this target
14821 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
14823 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
14824 if ((fnmask & rs6000_builtin_mask) != fnmask)
14830 /* Raise an error message for a builtin function that is called without the
14831 appropriate target options being set. */
14834 rs6000_invalid_builtin (enum rs6000_builtins fncode)
14836 size_t uns_fncode = (size_t) fncode;
14837 const char *name = rs6000_builtin_info[uns_fncode].name;
14838 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
14840 gcc_assert (name != NULL);
14841 if ((fnmask & RS6000_BTM_CELL) != 0)
14842 error ("builtin function %qs is only valid for the cell processor", name);
14843 else if ((fnmask & RS6000_BTM_VSX) != 0)
14844 error ("builtin function %qs requires the %qs option", name, "-mvsx");
14845 else if ((fnmask & RS6000_BTM_HTM) != 0)
14846 error ("builtin function %qs requires the %qs option", name, "-mhtm");
14847 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
14848 error ("builtin function %qs requires the %qs option", name, "-maltivec");
14849 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14850 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14851 error ("builtin function %qs requires the %qs and %qs options",
14852 name, "-mhard-dfp", "-mpower8-vector");
14853 else if ((fnmask & RS6000_BTM_DFP) != 0)
14854 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
14855 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
14856 error ("builtin function %qs requires the %qs option", name,
14857 "-mpower8-vector");
14858 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14859 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14860 error ("builtin function %qs requires the %qs and %qs options",
14861 name, "-mcpu=power9", "-m64");
14862 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
14863 error ("builtin function %qs requires the %qs option", name,
14865 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14866 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14867 error ("builtin function %qs requires the %qs and %qs options",
14868 name, "-mcpu=power9", "-m64");
14869 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
14870 error ("builtin function %qs requires the %qs option", name,
14872 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
14874 if (!TARGET_HARD_FLOAT)
14875 error ("builtin function %qs requires the %qs option", name,
14878 error ("builtin function %qs requires the %qs option", name,
14879 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
14881 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
14882 error ("builtin function %qs requires the %qs option", name,
14884 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
14885 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
14887 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
14888 error ("builtin function %qs requires the %qs option", name,
14890 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14891 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14892 error ("builtin function %qs requires the %qs (or newer), and "
14893 "%qs or %qs options",
14894 name, "-mcpu=power7", "-m64", "-mpowerpc64");
14896 error ("builtin function %qs is not supported with the current options",
14900 /* Target hook for early folding of built-ins, shamelessly stolen
14904 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
14905 int n_args ATTRIBUTE_UNUSED,
14906 tree *args ATTRIBUTE_UNUSED,
14907 bool ignore ATTRIBUTE_UNUSED)
14909 #ifdef SUBTARGET_FOLD_BUILTIN
14910 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
14916 /* Helper function to sort out which built-ins may be valid without having
14919 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
14923 case ALTIVEC_BUILTIN_STVX_V16QI:
14924 case ALTIVEC_BUILTIN_STVX_V8HI:
14925 case ALTIVEC_BUILTIN_STVX_V4SI:
14926 case ALTIVEC_BUILTIN_STVX_V4SF:
14927 case ALTIVEC_BUILTIN_STVX_V2DI:
14928 case ALTIVEC_BUILTIN_STVX_V2DF:
14929 case VSX_BUILTIN_STXVW4X_V16QI:
14930 case VSX_BUILTIN_STXVW4X_V8HI:
14931 case VSX_BUILTIN_STXVW4X_V4SF:
14932 case VSX_BUILTIN_STXVW4X_V4SI:
14933 case VSX_BUILTIN_STXVD2X_V2DF:
14934 case VSX_BUILTIN_STXVD2X_V2DI:
14941 /* Helper function to handle the gimple folding of a vector compare
14942 operation. This sets up true/false vectors, and uses the
14943 VEC_COND_EXPR operation.
14944 CODE indicates which comparison is to be made. (EQ, GT, ...).
14945 TYPE indicates the type of the result. */
14947 fold_build_vec_cmp (tree_code code, tree type,
14948 tree arg0, tree arg1)
14950 tree cmp_type = build_same_sized_truth_vector_type (type);
14951 tree zero_vec = build_zero_cst (type);
14952 tree minus_one_vec = build_minus_one_cst (type);
14953 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
14954 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
14957 /* Helper function to handle the in-between steps for the
14958 vector compare built-ins. */
14960 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
14962 tree arg0 = gimple_call_arg (stmt, 0);
14963 tree arg1 = gimple_call_arg (stmt, 1);
14964 tree lhs = gimple_call_lhs (stmt);
14965 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
14966 gimple *g = gimple_build_assign (lhs, cmp);
14967 gimple_set_location (g, gimple_location (stmt));
14968 gsi_replace (gsi, g, true);
14971 /* Helper function to map V2DF and V4SF types to their
14972 integral equivalents (V2DI and V4SI). */
14973 tree map_to_integral_tree_type (tree input_tree_type)
14975 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
14976 return input_tree_type;
14979 if (types_compatible_p (TREE_TYPE (input_tree_type),
14980 TREE_TYPE (V2DF_type_node)))
14981 return V2DI_type_node;
14982 else if (types_compatible_p (TREE_TYPE (input_tree_type),
14983 TREE_TYPE (V4SF_type_node)))
14984 return V4SI_type_node;
14986 gcc_unreachable ();
14990 /* Helper function to handle the vector merge[hl] built-ins. The
14991 implementation difference between h and l versions for this code are in
14992 the values used when building of the permute vector for high word versus
14993 low word merge. The variance is keyed off the use_high parameter. */
14995 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
14997 tree arg0 = gimple_call_arg (stmt, 0);
14998 tree arg1 = gimple_call_arg (stmt, 1);
14999 tree lhs = gimple_call_lhs (stmt);
15000 tree lhs_type = TREE_TYPE (lhs);
15001 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15002 int midpoint = n_elts / 2;
15008 /* The permute_type will match the lhs for integral types. For double and
15009 float types, the permute type needs to map to the V2 or V4 type that
15012 permute_type = map_to_integral_tree_type (lhs_type);
15013 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15015 for (int i = 0; i < midpoint; i++)
15017 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15019 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15020 offset + n_elts + i));
15023 tree permute = elts.build ();
15025 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15026 gimple_set_location (g, gimple_location (stmt));
15027 gsi_replace (gsi, g, true);
15030 /* Helper function to handle the vector merge[eo] built-ins. */
15032 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15034 tree arg0 = gimple_call_arg (stmt, 0);
15035 tree arg1 = gimple_call_arg (stmt, 1);
15036 tree lhs = gimple_call_lhs (stmt);
15037 tree lhs_type = TREE_TYPE (lhs);
15038 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15040 /* The permute_type will match the lhs for integral types. For double and
15041 float types, the permute type needs to map to the V2 or V4 type that
15044 permute_type = map_to_integral_tree_type (lhs_type);
15046 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15048 /* Build the permute vector. */
15049 for (int i = 0; i < n_elts / 2; i++)
15051 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15053 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15054 2*i + use_odd + n_elts));
15057 tree permute = elts.build ();
15059 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15060 gimple_set_location (g, gimple_location (stmt));
15061 gsi_replace (gsi, g, true);
15064 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15065 a constant, use rs6000_fold_builtin.) */
15068 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15070 gimple *stmt = gsi_stmt (*gsi);
15071 tree fndecl = gimple_call_fndecl (stmt);
15072 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15073 enum rs6000_builtins fn_code
15074 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15075 tree arg0, arg1, lhs, temp;
15076 enum tree_code bcode;
15079 size_t uns_fncode = (size_t) fn_code;
15080 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15081 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15082 const char *fn_name2 = (icode != CODE_FOR_nothing)
15083 ? get_insn_name ((int) icode)
15086 if (TARGET_DEBUG_BUILTIN)
15087 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15088 fn_code, fn_name1, fn_name2);
15090 if (!rs6000_fold_gimple)
15093 /* Prevent gimple folding for code that does not have a LHS, unless it is
15094 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15095 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15098 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15099 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15100 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15106 /* Flavors of vec_add. We deliberately don't expand
15107 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15108 TImode, resulting in much poorer code generation. */
15109 case ALTIVEC_BUILTIN_VADDUBM:
15110 case ALTIVEC_BUILTIN_VADDUHM:
15111 case ALTIVEC_BUILTIN_VADDUWM:
15112 case P8V_BUILTIN_VADDUDM:
15113 case ALTIVEC_BUILTIN_VADDFP:
15114 case VSX_BUILTIN_XVADDDP:
15117 arg0 = gimple_call_arg (stmt, 0);
15118 arg1 = gimple_call_arg (stmt, 1);
15119 lhs = gimple_call_lhs (stmt);
15120 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
15121 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
15123 /* Ensure the binary operation is performed in a type
15124 that wraps if it is integral type. */
15125 gimple_seq stmts = NULL;
15126 tree type = unsigned_type_for (TREE_TYPE (lhs));
15127 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15129 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15131 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
15132 type, uarg0, uarg1);
15133 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15134 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
15135 build1 (VIEW_CONVERT_EXPR,
15136 TREE_TYPE (lhs), res));
15137 gsi_replace (gsi, g, true);
15140 g = gimple_build_assign (lhs, bcode, arg0, arg1);
15141 gimple_set_location (g, gimple_location (stmt));
15142 gsi_replace (gsi, g, true);
15144 /* Flavors of vec_sub. We deliberately don't expand
15145 P8V_BUILTIN_VSUBUQM. */
15146 case ALTIVEC_BUILTIN_VSUBUBM:
15147 case ALTIVEC_BUILTIN_VSUBUHM:
15148 case ALTIVEC_BUILTIN_VSUBUWM:
15149 case P8V_BUILTIN_VSUBUDM:
15150 case ALTIVEC_BUILTIN_VSUBFP:
15151 case VSX_BUILTIN_XVSUBDP:
15152 bcode = MINUS_EXPR;
15154 case VSX_BUILTIN_XVMULSP:
15155 case VSX_BUILTIN_XVMULDP:
15156 arg0 = gimple_call_arg (stmt, 0);
15157 arg1 = gimple_call_arg (stmt, 1);
15158 lhs = gimple_call_lhs (stmt);
15159 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15160 gimple_set_location (g, gimple_location (stmt));
15161 gsi_replace (gsi, g, true);
15163 /* Even element flavors of vec_mul (signed). */
15164 case ALTIVEC_BUILTIN_VMULESB:
15165 case ALTIVEC_BUILTIN_VMULESH:
15166 case P8V_BUILTIN_VMULESW:
15167 /* Even element flavors of vec_mul (unsigned). */
15168 case ALTIVEC_BUILTIN_VMULEUB:
15169 case ALTIVEC_BUILTIN_VMULEUH:
15170 case P8V_BUILTIN_VMULEUW:
15171 arg0 = gimple_call_arg (stmt, 0);
15172 arg1 = gimple_call_arg (stmt, 1);
15173 lhs = gimple_call_lhs (stmt);
15174 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15175 gimple_set_location (g, gimple_location (stmt));
15176 gsi_replace (gsi, g, true);
15178 /* Odd element flavors of vec_mul (signed). */
15179 case ALTIVEC_BUILTIN_VMULOSB:
15180 case ALTIVEC_BUILTIN_VMULOSH:
15181 case P8V_BUILTIN_VMULOSW:
15182 /* Odd element flavors of vec_mul (unsigned). */
15183 case ALTIVEC_BUILTIN_VMULOUB:
15184 case ALTIVEC_BUILTIN_VMULOUH:
15185 case P8V_BUILTIN_VMULOUW:
15186 arg0 = gimple_call_arg (stmt, 0);
15187 arg1 = gimple_call_arg (stmt, 1);
15188 lhs = gimple_call_lhs (stmt);
15189 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15190 gimple_set_location (g, gimple_location (stmt));
15191 gsi_replace (gsi, g, true);
15193 /* Flavors of vec_div (Integer). */
15194 case VSX_BUILTIN_DIV_V2DI:
15195 case VSX_BUILTIN_UDIV_V2DI:
15196 arg0 = gimple_call_arg (stmt, 0);
15197 arg1 = gimple_call_arg (stmt, 1);
15198 lhs = gimple_call_lhs (stmt);
15199 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15200 gimple_set_location (g, gimple_location (stmt));
15201 gsi_replace (gsi, g, true);
15203 /* Flavors of vec_div (Float). */
15204 case VSX_BUILTIN_XVDIVSP:
15205 case VSX_BUILTIN_XVDIVDP:
15206 arg0 = gimple_call_arg (stmt, 0);
15207 arg1 = gimple_call_arg (stmt, 1);
15208 lhs = gimple_call_lhs (stmt);
15209 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15210 gimple_set_location (g, gimple_location (stmt));
15211 gsi_replace (gsi, g, true);
15213 /* Flavors of vec_and. */
15214 case ALTIVEC_BUILTIN_VAND:
15215 arg0 = gimple_call_arg (stmt, 0);
15216 arg1 = gimple_call_arg (stmt, 1);
15217 lhs = gimple_call_lhs (stmt);
15218 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15219 gimple_set_location (g, gimple_location (stmt));
15220 gsi_replace (gsi, g, true);
15222 /* Flavors of vec_andc. */
15223 case ALTIVEC_BUILTIN_VANDC:
15224 arg0 = gimple_call_arg (stmt, 0);
15225 arg1 = gimple_call_arg (stmt, 1);
15226 lhs = gimple_call_lhs (stmt);
15227 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15228 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15229 gimple_set_location (g, gimple_location (stmt));
15230 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15231 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15232 gimple_set_location (g, gimple_location (stmt));
15233 gsi_replace (gsi, g, true);
15235 /* Flavors of vec_nand. */
15236 case P8V_BUILTIN_VEC_NAND:
15237 case P8V_BUILTIN_NAND_V16QI:
15238 case P8V_BUILTIN_NAND_V8HI:
15239 case P8V_BUILTIN_NAND_V4SI:
15240 case P8V_BUILTIN_NAND_V4SF:
15241 case P8V_BUILTIN_NAND_V2DF:
15242 case P8V_BUILTIN_NAND_V2DI:
15243 arg0 = gimple_call_arg (stmt, 0);
15244 arg1 = gimple_call_arg (stmt, 1);
15245 lhs = gimple_call_lhs (stmt);
15246 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15247 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15248 gimple_set_location (g, gimple_location (stmt));
15249 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15250 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15251 gimple_set_location (g, gimple_location (stmt));
15252 gsi_replace (gsi, g, true);
15254 /* Flavors of vec_or. */
15255 case ALTIVEC_BUILTIN_VOR:
15256 arg0 = gimple_call_arg (stmt, 0);
15257 arg1 = gimple_call_arg (stmt, 1);
15258 lhs = gimple_call_lhs (stmt);
15259 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15260 gimple_set_location (g, gimple_location (stmt));
15261 gsi_replace (gsi, g, true);
15263 /* flavors of vec_orc. */
15264 case P8V_BUILTIN_ORC_V16QI:
15265 case P8V_BUILTIN_ORC_V8HI:
15266 case P8V_BUILTIN_ORC_V4SI:
15267 case P8V_BUILTIN_ORC_V4SF:
15268 case P8V_BUILTIN_ORC_V2DF:
15269 case P8V_BUILTIN_ORC_V2DI:
15270 arg0 = gimple_call_arg (stmt, 0);
15271 arg1 = gimple_call_arg (stmt, 1);
15272 lhs = gimple_call_lhs (stmt);
15273 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15274 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15275 gimple_set_location (g, gimple_location (stmt));
15276 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15277 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15278 gimple_set_location (g, gimple_location (stmt));
15279 gsi_replace (gsi, g, true);
15281 /* Flavors of vec_xor. */
15282 case ALTIVEC_BUILTIN_VXOR:
15283 arg0 = gimple_call_arg (stmt, 0);
15284 arg1 = gimple_call_arg (stmt, 1);
15285 lhs = gimple_call_lhs (stmt);
15286 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15287 gimple_set_location (g, gimple_location (stmt));
15288 gsi_replace (gsi, g, true);
15290 /* Flavors of vec_nor. */
15291 case ALTIVEC_BUILTIN_VNOR:
15292 arg0 = gimple_call_arg (stmt, 0);
15293 arg1 = gimple_call_arg (stmt, 1);
15294 lhs = gimple_call_lhs (stmt);
15295 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15296 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15297 gimple_set_location (g, gimple_location (stmt));
15298 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15299 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15300 gimple_set_location (g, gimple_location (stmt));
15301 gsi_replace (gsi, g, true);
15303 /* flavors of vec_abs. */
15304 case ALTIVEC_BUILTIN_ABS_V16QI:
15305 case ALTIVEC_BUILTIN_ABS_V8HI:
15306 case ALTIVEC_BUILTIN_ABS_V4SI:
15307 case ALTIVEC_BUILTIN_ABS_V4SF:
15308 case P8V_BUILTIN_ABS_V2DI:
15309 case VSX_BUILTIN_XVABSDP:
15310 arg0 = gimple_call_arg (stmt, 0);
15311 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15312 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15314 lhs = gimple_call_lhs (stmt);
15315 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15316 gimple_set_location (g, gimple_location (stmt));
15317 gsi_replace (gsi, g, true);
15319 /* flavors of vec_min. */
15320 case VSX_BUILTIN_XVMINDP:
15321 case P8V_BUILTIN_VMINSD:
15322 case P8V_BUILTIN_VMINUD:
15323 case ALTIVEC_BUILTIN_VMINSB:
15324 case ALTIVEC_BUILTIN_VMINSH:
15325 case ALTIVEC_BUILTIN_VMINSW:
15326 case ALTIVEC_BUILTIN_VMINUB:
15327 case ALTIVEC_BUILTIN_VMINUH:
15328 case ALTIVEC_BUILTIN_VMINUW:
15329 case ALTIVEC_BUILTIN_VMINFP:
15330 arg0 = gimple_call_arg (stmt, 0);
15331 arg1 = gimple_call_arg (stmt, 1);
15332 lhs = gimple_call_lhs (stmt);
15333 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15334 gimple_set_location (g, gimple_location (stmt));
15335 gsi_replace (gsi, g, true);
15337 /* flavors of vec_max. */
15338 case VSX_BUILTIN_XVMAXDP:
15339 case P8V_BUILTIN_VMAXSD:
15340 case P8V_BUILTIN_VMAXUD:
15341 case ALTIVEC_BUILTIN_VMAXSB:
15342 case ALTIVEC_BUILTIN_VMAXSH:
15343 case ALTIVEC_BUILTIN_VMAXSW:
15344 case ALTIVEC_BUILTIN_VMAXUB:
15345 case ALTIVEC_BUILTIN_VMAXUH:
15346 case ALTIVEC_BUILTIN_VMAXUW:
15347 case ALTIVEC_BUILTIN_VMAXFP:
15348 arg0 = gimple_call_arg (stmt, 0);
15349 arg1 = gimple_call_arg (stmt, 1);
15350 lhs = gimple_call_lhs (stmt);
15351 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15352 gimple_set_location (g, gimple_location (stmt));
15353 gsi_replace (gsi, g, true);
15355 /* Flavors of vec_eqv. */
15356 case P8V_BUILTIN_EQV_V16QI:
15357 case P8V_BUILTIN_EQV_V8HI:
15358 case P8V_BUILTIN_EQV_V4SI:
15359 case P8V_BUILTIN_EQV_V4SF:
15360 case P8V_BUILTIN_EQV_V2DF:
15361 case P8V_BUILTIN_EQV_V2DI:
15362 arg0 = gimple_call_arg (stmt, 0);
15363 arg1 = gimple_call_arg (stmt, 1);
15364 lhs = gimple_call_lhs (stmt);
15365 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15366 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15367 gimple_set_location (g, gimple_location (stmt));
15368 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15369 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15370 gimple_set_location (g, gimple_location (stmt));
15371 gsi_replace (gsi, g, true);
15373 /* Flavors of vec_rotate_left. */
15374 case ALTIVEC_BUILTIN_VRLB:
15375 case ALTIVEC_BUILTIN_VRLH:
15376 case ALTIVEC_BUILTIN_VRLW:
15377 case P8V_BUILTIN_VRLD:
15378 arg0 = gimple_call_arg (stmt, 0);
15379 arg1 = gimple_call_arg (stmt, 1);
15380 lhs = gimple_call_lhs (stmt);
15381 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15382 gimple_set_location (g, gimple_location (stmt));
15383 gsi_replace (gsi, g, true);
15385 /* Flavors of vector shift right algebraic.
15386 vec_sra{b,h,w} -> vsra{b,h,w}. */
15387 case ALTIVEC_BUILTIN_VSRAB:
15388 case ALTIVEC_BUILTIN_VSRAH:
15389 case ALTIVEC_BUILTIN_VSRAW:
15390 case P8V_BUILTIN_VSRAD:
15392 arg0 = gimple_call_arg (stmt, 0);
15393 arg1 = gimple_call_arg (stmt, 1);
15394 lhs = gimple_call_lhs (stmt);
15395 tree arg1_type = TREE_TYPE (arg1);
15396 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15397 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15398 location_t loc = gimple_location (stmt);
15399 /* Force arg1 into the range valid matching the arg0 type. */
15400 /* Build a vector consisting of the max valid bit-size values. */
15401 int n_elts = VECTOR_CST_NELTS (arg1);
15402 tree element_size = build_int_cst (unsigned_element_type,
15404 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15405 for (int i = 0; i < n_elts; i++)
15406 elts.safe_push (element_size);
15407 tree modulo_tree = elts.build ();
15408 /* Modulo the provided shift value against that vector. */
15409 gimple_seq stmts = NULL;
15410 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15411 unsigned_arg1_type, arg1);
15412 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15413 unsigned_arg1_type, unsigned_arg1,
15415 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15416 /* And finally, do the shift. */
15417 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
15418 gimple_set_location (g, loc);
15419 gsi_replace (gsi, g, true);
15422 /* Flavors of vector shift left.
15423 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15424 case ALTIVEC_BUILTIN_VSLB:
15425 case ALTIVEC_BUILTIN_VSLH:
15426 case ALTIVEC_BUILTIN_VSLW:
15427 case P8V_BUILTIN_VSLD:
15430 gimple_seq stmts = NULL;
15431 arg0 = gimple_call_arg (stmt, 0);
15432 tree arg0_type = TREE_TYPE (arg0);
15433 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15434 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15436 arg1 = gimple_call_arg (stmt, 1);
15437 tree arg1_type = TREE_TYPE (arg1);
15438 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15439 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15440 loc = gimple_location (stmt);
15441 lhs = gimple_call_lhs (stmt);
15442 /* Force arg1 into the range valid matching the arg0 type. */
15443 /* Build a vector consisting of the max valid bit-size values. */
15444 int n_elts = VECTOR_CST_NELTS (arg1);
15445 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15447 tree element_size = build_int_cst (unsigned_element_type,
15448 tree_size_in_bits / n_elts);
15449 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15450 for (int i = 0; i < n_elts; i++)
15451 elts.safe_push (element_size);
15452 tree modulo_tree = elts.build ();
15453 /* Modulo the provided shift value against that vector. */
15454 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15455 unsigned_arg1_type, arg1);
15456 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15457 unsigned_arg1_type, unsigned_arg1,
15459 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15460 /* And finally, do the shift. */
15461 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15462 gimple_set_location (g, gimple_location (stmt));
15463 gsi_replace (gsi, g, true);
15466 /* Flavors of vector shift right. */
15467 case ALTIVEC_BUILTIN_VSRB:
15468 case ALTIVEC_BUILTIN_VSRH:
15469 case ALTIVEC_BUILTIN_VSRW:
15470 case P8V_BUILTIN_VSRD:
15472 arg0 = gimple_call_arg (stmt, 0);
15473 arg1 = gimple_call_arg (stmt, 1);
15474 lhs = gimple_call_lhs (stmt);
15475 tree arg1_type = TREE_TYPE (arg1);
15476 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15477 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15478 location_t loc = gimple_location (stmt);
15479 gimple_seq stmts = NULL;
15480 /* Convert arg0 to unsigned. */
15482 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15483 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15484 /* Force arg1 into the range valid matching the arg0 type. */
15485 /* Build a vector consisting of the max valid bit-size values. */
15486 int n_elts = VECTOR_CST_NELTS (arg1);
15487 tree element_size = build_int_cst (unsigned_element_type,
15489 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15490 for (int i = 0; i < n_elts; i++)
15491 elts.safe_push (element_size);
15492 tree modulo_tree = elts.build ();
15493 /* Modulo the provided shift value against that vector. */
15494 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15495 unsigned_arg1_type, arg1);
15496 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15497 unsigned_arg1_type, unsigned_arg1,
15499 /* Do the shift. */
15501 = gimple_build (&stmts, RSHIFT_EXPR,
15502 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
15503 /* Convert result back to the lhs type. */
15504 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15505 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15506 update_call_from_tree (gsi, res);
15509 /* Vector loads. */
15510 case ALTIVEC_BUILTIN_LVX_V16QI:
15511 case ALTIVEC_BUILTIN_LVX_V8HI:
15512 case ALTIVEC_BUILTIN_LVX_V4SI:
15513 case ALTIVEC_BUILTIN_LVX_V4SF:
15514 case ALTIVEC_BUILTIN_LVX_V2DI:
15515 case ALTIVEC_BUILTIN_LVX_V2DF:
15516 case ALTIVEC_BUILTIN_LVX_V1TI:
15518 arg0 = gimple_call_arg (stmt, 0); // offset
15519 arg1 = gimple_call_arg (stmt, 1); // address
15520 lhs = gimple_call_lhs (stmt);
15521 location_t loc = gimple_location (stmt);
15522 /* Since arg1 may be cast to a different type, just use ptr_type_node
15523 here instead of trying to enforce TBAA on pointer types. */
15524 tree arg1_type = ptr_type_node;
15525 tree lhs_type = TREE_TYPE (lhs);
15526 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15527 the tree using the value from arg0. The resulting type will match
15528 the type of arg1. */
15529 gimple_seq stmts = NULL;
15530 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15531 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15532 arg1_type, arg1, temp_offset);
15533 /* Mask off any lower bits from the address. */
15534 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15535 arg1_type, temp_addr,
15536 build_int_cst (arg1_type, -16));
15537 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15538 if (!is_gimple_mem_ref_addr (aligned_addr))
15540 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15541 gimple *g = gimple_build_assign (t, aligned_addr);
15542 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15545 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15546 take an offset, but since we've already incorporated the offset
15547 above, here we just pass in a zero. */
15549 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15550 build_int_cst (arg1_type, 0)));
15551 gimple_set_location (g, loc);
15552 gsi_replace (gsi, g, true);
15555 /* Vector stores. */
15556 case ALTIVEC_BUILTIN_STVX_V16QI:
15557 case ALTIVEC_BUILTIN_STVX_V8HI:
15558 case ALTIVEC_BUILTIN_STVX_V4SI:
15559 case ALTIVEC_BUILTIN_STVX_V4SF:
15560 case ALTIVEC_BUILTIN_STVX_V2DI:
15561 case ALTIVEC_BUILTIN_STVX_V2DF:
15563 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15564 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15565 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15566 location_t loc = gimple_location (stmt);
15567 tree arg0_type = TREE_TYPE (arg0);
15568 /* Use ptr_type_node (no TBAA) for the arg2_type.
15569 FIXME: (Richard) "A proper fix would be to transition this type as
15570 seen from the frontend to GIMPLE, for example in a similar way we
15571 do for MEM_REFs by piggy-backing that on an extra argument, a
15572 constant zero pointer of the alias pointer type to use (which would
15573 also serve as a type indicator of the store itself). I'd use a
15574 target specific internal function for this (not sure if we can have
15575 those target specific, but I guess if it's folded away then that's
15576 fine) and get away with the overload set." */
15577 tree arg2_type = ptr_type_node;
15578 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15579 the tree using the value from arg0. The resulting type will match
15580 the type of arg2. */
15581 gimple_seq stmts = NULL;
15582 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15583 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15584 arg2_type, arg2, temp_offset);
15585 /* Mask off any lower bits from the address. */
15586 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15587 arg2_type, temp_addr,
15588 build_int_cst (arg2_type, -16));
15589 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15590 if (!is_gimple_mem_ref_addr (aligned_addr))
15592 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15593 gimple *g = gimple_build_assign (t, aligned_addr);
15594 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15597 /* The desired gimple result should be similar to:
15598 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15600 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15601 build_int_cst (arg2_type, 0)), arg0);
15602 gimple_set_location (g, loc);
15603 gsi_replace (gsi, g, true);
15607 /* unaligned Vector loads. */
15608 case VSX_BUILTIN_LXVW4X_V16QI:
15609 case VSX_BUILTIN_LXVW4X_V8HI:
15610 case VSX_BUILTIN_LXVW4X_V4SF:
15611 case VSX_BUILTIN_LXVW4X_V4SI:
15612 case VSX_BUILTIN_LXVD2X_V2DF:
15613 case VSX_BUILTIN_LXVD2X_V2DI:
15615 arg0 = gimple_call_arg (stmt, 0); // offset
15616 arg1 = gimple_call_arg (stmt, 1); // address
15617 lhs = gimple_call_lhs (stmt);
15618 location_t loc = gimple_location (stmt);
15619 /* Since arg1 may be cast to a different type, just use ptr_type_node
15620 here instead of trying to enforce TBAA on pointer types. */
15621 tree arg1_type = ptr_type_node;
15622 tree lhs_type = TREE_TYPE (lhs);
15623 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15624 required alignment (power) is 4 bytes regardless of data type. */
15625 tree align_ltype = build_aligned_type (lhs_type, 4);
15626 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15627 the tree using the value from arg0. The resulting type will match
15628 the type of arg1. */
15629 gimple_seq stmts = NULL;
15630 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15631 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15632 arg1_type, arg1, temp_offset);
15633 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15634 if (!is_gimple_mem_ref_addr (temp_addr))
15636 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15637 gimple *g = gimple_build_assign (t, temp_addr);
15638 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15641 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15642 take an offset, but since we've already incorporated the offset
15643 above, here we just pass in a zero. */
15645 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15646 build_int_cst (arg1_type, 0)));
15647 gimple_set_location (g, loc);
15648 gsi_replace (gsi, g, true);
15652 /* unaligned Vector stores. */
15653 case VSX_BUILTIN_STXVW4X_V16QI:
15654 case VSX_BUILTIN_STXVW4X_V8HI:
15655 case VSX_BUILTIN_STXVW4X_V4SF:
15656 case VSX_BUILTIN_STXVW4X_V4SI:
15657 case VSX_BUILTIN_STXVD2X_V2DF:
15658 case VSX_BUILTIN_STXVD2X_V2DI:
15660 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15661 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15662 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15663 location_t loc = gimple_location (stmt);
15664 tree arg0_type = TREE_TYPE (arg0);
15665 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15666 tree arg2_type = ptr_type_node;
15667 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15668 required alignment (power) is 4 bytes regardless of data type. */
15669 tree align_stype = build_aligned_type (arg0_type, 4);
15670 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15671 the tree using the value from arg1. */
15672 gimple_seq stmts = NULL;
15673 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15674 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15675 arg2_type, arg2, temp_offset);
15676 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15677 if (!is_gimple_mem_ref_addr (temp_addr))
15679 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15680 gimple *g = gimple_build_assign (t, temp_addr);
15681 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15685 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15686 build_int_cst (arg2_type, 0)), arg0);
15687 gimple_set_location (g, loc);
15688 gsi_replace (gsi, g, true);
15692 /* Vector Fused multiply-add (fma). */
15693 case ALTIVEC_BUILTIN_VMADDFP:
15694 case VSX_BUILTIN_XVMADDDP:
15695 case ALTIVEC_BUILTIN_VMLADDUHM:
15697 arg0 = gimple_call_arg (stmt, 0);
15698 arg1 = gimple_call_arg (stmt, 1);
15699 tree arg2 = gimple_call_arg (stmt, 2);
15700 lhs = gimple_call_lhs (stmt);
15701 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15702 gimple_call_set_lhs (g, lhs);
15703 gimple_call_set_nothrow (g, true);
15704 gimple_set_location (g, gimple_location (stmt));
15705 gsi_replace (gsi, g, true);
15709 /* Vector compares; EQ, NE, GE, GT, LE. */
15710 case ALTIVEC_BUILTIN_VCMPEQUB:
15711 case ALTIVEC_BUILTIN_VCMPEQUH:
15712 case ALTIVEC_BUILTIN_VCMPEQUW:
15713 case P8V_BUILTIN_VCMPEQUD:
15714 fold_compare_helper (gsi, EQ_EXPR, stmt);
15717 case P9V_BUILTIN_CMPNEB:
15718 case P9V_BUILTIN_CMPNEH:
15719 case P9V_BUILTIN_CMPNEW:
15720 fold_compare_helper (gsi, NE_EXPR, stmt);
15723 case VSX_BUILTIN_CMPGE_16QI:
15724 case VSX_BUILTIN_CMPGE_U16QI:
15725 case VSX_BUILTIN_CMPGE_8HI:
15726 case VSX_BUILTIN_CMPGE_U8HI:
15727 case VSX_BUILTIN_CMPGE_4SI:
15728 case VSX_BUILTIN_CMPGE_U4SI:
15729 case VSX_BUILTIN_CMPGE_2DI:
15730 case VSX_BUILTIN_CMPGE_U2DI:
15731 fold_compare_helper (gsi, GE_EXPR, stmt);
15734 case ALTIVEC_BUILTIN_VCMPGTSB:
15735 case ALTIVEC_BUILTIN_VCMPGTUB:
15736 case ALTIVEC_BUILTIN_VCMPGTSH:
15737 case ALTIVEC_BUILTIN_VCMPGTUH:
15738 case ALTIVEC_BUILTIN_VCMPGTSW:
15739 case ALTIVEC_BUILTIN_VCMPGTUW:
15740 case P8V_BUILTIN_VCMPGTUD:
15741 case P8V_BUILTIN_VCMPGTSD:
15742 fold_compare_helper (gsi, GT_EXPR, stmt);
15745 case VSX_BUILTIN_CMPLE_16QI:
15746 case VSX_BUILTIN_CMPLE_U16QI:
15747 case VSX_BUILTIN_CMPLE_8HI:
15748 case VSX_BUILTIN_CMPLE_U8HI:
15749 case VSX_BUILTIN_CMPLE_4SI:
15750 case VSX_BUILTIN_CMPLE_U4SI:
15751 case VSX_BUILTIN_CMPLE_2DI:
15752 case VSX_BUILTIN_CMPLE_U2DI:
15753 fold_compare_helper (gsi, LE_EXPR, stmt);
15756 /* flavors of vec_splat_[us]{8,16,32}. */
15757 case ALTIVEC_BUILTIN_VSPLTISB:
15758 case ALTIVEC_BUILTIN_VSPLTISH:
15759 case ALTIVEC_BUILTIN_VSPLTISW:
15761 arg0 = gimple_call_arg (stmt, 0);
15762 lhs = gimple_call_lhs (stmt);
15764 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15765 5-bit signed constant in range -16 to +15. */
15766 if (TREE_CODE (arg0) != INTEGER_CST
15767 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
15769 gimple_seq stmts = NULL;
15770 location_t loc = gimple_location (stmt);
15771 tree splat_value = gimple_convert (&stmts, loc,
15772 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15773 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15774 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15775 g = gimple_build_assign (lhs, splat_tree);
15776 gimple_set_location (g, gimple_location (stmt));
15777 gsi_replace (gsi, g, true);
15781 /* Flavors of vec_splat. */
15782 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15783 case ALTIVEC_BUILTIN_VSPLTB:
15784 case ALTIVEC_BUILTIN_VSPLTH:
15785 case ALTIVEC_BUILTIN_VSPLTW:
15786 case VSX_BUILTIN_XXSPLTD_V2DI:
15787 case VSX_BUILTIN_XXSPLTD_V2DF:
15789 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15790 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15791 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15792 is a valid index into the arg0 vector. */
15793 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15794 if (TREE_CODE (arg1) != INTEGER_CST
15795 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15797 lhs = gimple_call_lhs (stmt);
15798 tree lhs_type = TREE_TYPE (lhs);
15799 tree arg0_type = TREE_TYPE (arg0);
15801 if (TREE_CODE (arg0) == VECTOR_CST)
15802 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15805 /* Determine (in bits) the length and start location of the
15806 splat value for a call to the tree_vec_extract helper. */
15807 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15808 * BITS_PER_UNIT / n_elts;
15809 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15810 tree len = build_int_cst (bitsizetype, splat_elem_size);
15811 tree start = build_int_cst (bitsizetype, splat_start_bit);
15812 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15815 /* And finally, build the new vector. */
15816 tree splat_tree = build_vector_from_val (lhs_type, splat);
15817 g = gimple_build_assign (lhs, splat_tree);
15818 gimple_set_location (g, gimple_location (stmt));
15819 gsi_replace (gsi, g, true);
15823 /* vec_mergel (integrals). */
15824 case ALTIVEC_BUILTIN_VMRGLH:
15825 case ALTIVEC_BUILTIN_VMRGLW:
15826 case VSX_BUILTIN_XXMRGLW_4SI:
15827 case ALTIVEC_BUILTIN_VMRGLB:
15828 case VSX_BUILTIN_VEC_MERGEL_V2DI:
15829 case VSX_BUILTIN_XXMRGLW_4SF:
15830 case VSX_BUILTIN_VEC_MERGEL_V2DF:
15831 fold_mergehl_helper (gsi, stmt, 1);
15833 /* vec_mergeh (integrals). */
15834 case ALTIVEC_BUILTIN_VMRGHH:
15835 case ALTIVEC_BUILTIN_VMRGHW:
15836 case VSX_BUILTIN_XXMRGHW_4SI:
15837 case ALTIVEC_BUILTIN_VMRGHB:
15838 case VSX_BUILTIN_VEC_MERGEH_V2DI:
15839 case VSX_BUILTIN_XXMRGHW_4SF:
15840 case VSX_BUILTIN_VEC_MERGEH_V2DF:
15841 fold_mergehl_helper (gsi, stmt, 0);
15844 /* Flavors of vec_mergee. */
15845 case P8V_BUILTIN_VMRGEW_V4SI:
15846 case P8V_BUILTIN_VMRGEW_V2DI:
15847 case P8V_BUILTIN_VMRGEW_V4SF:
15848 case P8V_BUILTIN_VMRGEW_V2DF:
15849 fold_mergeeo_helper (gsi, stmt, 0);
15851 /* Flavors of vec_mergeo. */
15852 case P8V_BUILTIN_VMRGOW_V4SI:
15853 case P8V_BUILTIN_VMRGOW_V2DI:
15854 case P8V_BUILTIN_VMRGOW_V4SF:
15855 case P8V_BUILTIN_VMRGOW_V2DF:
15856 fold_mergeeo_helper (gsi, stmt, 1);
15859 /* d = vec_pack (a, b) */
15860 case P8V_BUILTIN_VPKUDUM:
15861 case ALTIVEC_BUILTIN_VPKUHUM:
15862 case ALTIVEC_BUILTIN_VPKUWUM:
15864 arg0 = gimple_call_arg (stmt, 0);
15865 arg1 = gimple_call_arg (stmt, 1);
15866 lhs = gimple_call_lhs (stmt);
15867 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
15868 gimple_set_location (g, gimple_location (stmt));
15869 gsi_replace (gsi, g, true);
15873 /* d = vec_unpackh (a) */
15874 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
15875 in this code is sensitive to endian-ness, and needs to be inverted to
15876 handle both LE and BE targets. */
15877 case ALTIVEC_BUILTIN_VUPKHSB:
15878 case ALTIVEC_BUILTIN_VUPKHSH:
15879 case P8V_BUILTIN_VUPKHSW:
15881 arg0 = gimple_call_arg (stmt, 0);
15882 lhs = gimple_call_lhs (stmt);
15883 if (BYTES_BIG_ENDIAN)
15884 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15886 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15887 gimple_set_location (g, gimple_location (stmt));
15888 gsi_replace (gsi, g, true);
15891 /* d = vec_unpackl (a) */
15892 case ALTIVEC_BUILTIN_VUPKLSB:
15893 case ALTIVEC_BUILTIN_VUPKLSH:
15894 case P8V_BUILTIN_VUPKLSW:
15896 arg0 = gimple_call_arg (stmt, 0);
15897 lhs = gimple_call_lhs (stmt);
15898 if (BYTES_BIG_ENDIAN)
15899 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15901 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15902 gimple_set_location (g, gimple_location (stmt));
15903 gsi_replace (gsi, g, true);
15906 /* There is no gimple type corresponding with pixel, so just return. */
15907 case ALTIVEC_BUILTIN_VUPKHPX:
15908 case ALTIVEC_BUILTIN_VUPKLPX:
15912 case ALTIVEC_BUILTIN_VPERM_16QI:
15913 case ALTIVEC_BUILTIN_VPERM_8HI:
15914 case ALTIVEC_BUILTIN_VPERM_4SI:
15915 case ALTIVEC_BUILTIN_VPERM_2DI:
15916 case ALTIVEC_BUILTIN_VPERM_4SF:
15917 case ALTIVEC_BUILTIN_VPERM_2DF:
15919 arg0 = gimple_call_arg (stmt, 0);
15920 arg1 = gimple_call_arg (stmt, 1);
15921 tree permute = gimple_call_arg (stmt, 2);
15922 lhs = gimple_call_lhs (stmt);
15923 location_t loc = gimple_location (stmt);
15924 gimple_seq stmts = NULL;
15925 // convert arg0 and arg1 to match the type of the permute
15926 // for the VEC_PERM_EXPR operation.
15927 tree permute_type = (TREE_TYPE (permute));
15928 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
15929 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
15930 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
15931 permute_type, arg0_ptype, arg1_ptype,
15933 // Convert the result back to the desired lhs type upon completion.
15934 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
15935 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15936 g = gimple_build_assign (lhs, temp);
15937 gimple_set_location (g, loc);
15938 gsi_replace (gsi, g, true);
15943 if (TARGET_DEBUG_BUILTIN)
15944 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
15945 fn_code, fn_name1, fn_name2);
15952 /* Expand an expression EXP that calls a built-in function,
15953 with result going to TARGET if that's convenient
15954 (and in mode MODE if that's convenient).
15955 SUBTARGET may be used as the target for computing one of EXP's operands.
15956 IGNORE is nonzero if the value is to be ignored. */
15959 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15960 machine_mode mode ATTRIBUTE_UNUSED,
15961 int ignore ATTRIBUTE_UNUSED)
15963 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15964 enum rs6000_builtins fcode
15965 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
15966 size_t uns_fcode = (size_t)fcode;
15967 const struct builtin_description *d;
15971 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
15972 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
15973 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
15975 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
15976 floating point type, depending on whether long double is the IBM extended
15977 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
15978 we only define one variant of the built-in function, and switch the code
15979 when defining it, rather than defining two built-ins and using the
15980 overload table in rs6000-c.c to switch between the two. If we don't have
15981 the proper assembler, don't do this switch because CODE_FOR_*kf* and
15982 CODE_FOR_*tf* will be CODE_FOR_nothing. */
15983 if (FLOAT128_IEEE_P (TFmode))
15989 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
15990 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
15991 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
15992 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
15993 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
15994 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
15995 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
15996 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
15997 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
15998 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
15999 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16000 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16001 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16004 if (TARGET_DEBUG_BUILTIN)
16006 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16007 const char *name2 = (icode != CODE_FOR_nothing)
16008 ? get_insn_name ((int) icode)
16012 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16014 default: name3 = "unknown"; break;
16015 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16016 case RS6000_BTC_UNARY: name3 = "unary"; break;
16017 case RS6000_BTC_BINARY: name3 = "binary"; break;
16018 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16019 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16020 case RS6000_BTC_ABS: name3 = "abs"; break;
16021 case RS6000_BTC_DST: name3 = "dst"; break;
16026 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16027 (name1) ? name1 : "---", fcode,
16028 (name2) ? name2 : "---", (int) icode,
16030 func_valid_p ? "" : ", not valid");
16035 rs6000_invalid_builtin (fcode);
16037 /* Given it is invalid, just generate a normal call. */
16038 return expand_call (exp, target, ignore);
16043 case RS6000_BUILTIN_RECIP:
16044 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16046 case RS6000_BUILTIN_RECIPF:
16047 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16049 case RS6000_BUILTIN_RSQRTF:
16050 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16052 case RS6000_BUILTIN_RSQRT:
16053 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16055 case POWER7_BUILTIN_BPERMD:
16056 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16057 ? CODE_FOR_bpermd_di
16058 : CODE_FOR_bpermd_si), exp, target);
16060 case RS6000_BUILTIN_GET_TB:
16061 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16064 case RS6000_BUILTIN_MFTB:
16065 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16066 ? CODE_FOR_rs6000_mftb_di
16067 : CODE_FOR_rs6000_mftb_si),
16070 case RS6000_BUILTIN_MFFS:
16071 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16073 case RS6000_BUILTIN_MTFSB0:
16074 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16076 case RS6000_BUILTIN_MTFSB1:
16077 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16079 case RS6000_BUILTIN_SET_FPSCR_RN:
16080 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16083 case RS6000_BUILTIN_SET_FPSCR_DRN:
16085 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16088 case RS6000_BUILTIN_MFFSL:
16089 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16091 case RS6000_BUILTIN_MTFSF:
16092 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16094 case RS6000_BUILTIN_CPU_INIT:
16095 case RS6000_BUILTIN_CPU_IS:
16096 case RS6000_BUILTIN_CPU_SUPPORTS:
16097 return cpu_expand_builtin (fcode, exp, target);
16099 case MISC_BUILTIN_SPEC_BARRIER:
16101 emit_insn (gen_speculation_barrier ());
16105 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16106 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16108 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16109 : (int) CODE_FOR_altivec_lvsl_direct);
16110 machine_mode tmode = insn_data[icode2].operand[0].mode;
16111 machine_mode mode = insn_data[icode2].operand[1].mode;
16115 gcc_assert (TARGET_ALTIVEC);
16117 arg = CALL_EXPR_ARG (exp, 0);
16118 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16119 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16120 addr = memory_address (mode, op);
16121 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16125 /* For the load case need to negate the address. */
16126 op = gen_reg_rtx (GET_MODE (addr));
16127 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16129 op = gen_rtx_MEM (mode, op);
16132 || GET_MODE (target) != tmode
16133 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16134 target = gen_reg_rtx (tmode);
16136 pat = GEN_FCN (icode2) (target, op);
16144 case ALTIVEC_BUILTIN_VCFUX:
16145 case ALTIVEC_BUILTIN_VCFSX:
16146 case ALTIVEC_BUILTIN_VCTUXS:
16147 case ALTIVEC_BUILTIN_VCTSXS:
16148 /* FIXME: There's got to be a nicer way to handle this case than
16149 constructing a new CALL_EXPR. */
16150 if (call_expr_nargs (exp) == 1)
16152 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16153 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16157 /* For the pack and unpack int128 routines, fix up the builtin so it
16158 uses the correct IBM128 type. */
16159 case MISC_BUILTIN_PACK_IF:
16160 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16162 icode = CODE_FOR_packtf;
16163 fcode = MISC_BUILTIN_PACK_TF;
16164 uns_fcode = (size_t)fcode;
16168 case MISC_BUILTIN_UNPACK_IF:
16169 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16171 icode = CODE_FOR_unpacktf;
16172 fcode = MISC_BUILTIN_UNPACK_TF;
16173 uns_fcode = (size_t)fcode;
16181 if (TARGET_ALTIVEC)
16183 ret = altivec_expand_builtin (exp, target, &success);
16190 ret = htm_expand_builtin (exp, target, &success);
16196 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16197 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16198 gcc_assert (attr == RS6000_BTC_UNARY
16199 || attr == RS6000_BTC_BINARY
16200 || attr == RS6000_BTC_TERNARY
16201 || attr == RS6000_BTC_SPECIAL);
16203 /* Handle simple unary operations. */
16205 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16206 if (d->code == fcode)
16207 return rs6000_expand_unop_builtin (icode, exp, target);
16209 /* Handle simple binary operations. */
16211 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16212 if (d->code == fcode)
16213 return rs6000_expand_binop_builtin (icode, exp, target);
16215 /* Handle simple ternary operations. */
16217 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16218 if (d->code == fcode)
16219 return rs6000_expand_ternop_builtin (icode, exp, target);
16221 /* Handle simple no-argument operations. */
16223 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16224 if (d->code == fcode)
16225 return rs6000_expand_zeroop_builtin (icode, target);
16227 gcc_unreachable ();
16230 /* Create a builtin vector type with a name. Taking care not to give
16231 the canonical type a name. */
16234 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16236 tree result = build_vector_type (elt_type, num_elts);
16238 /* Copy so we don't give the canonical type a name. */
16239 result = build_variant_type_copy (result);
16241 add_builtin_type (name, result);
16247 rs6000_init_builtins (void)
16253 if (TARGET_DEBUG_BUILTIN)
16254 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16255 (TARGET_ALTIVEC) ? ", altivec" : "",
16256 (TARGET_VSX) ? ", vsx" : "");
16258 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16259 : "__vector long long",
16260 intDI_type_node, 2);
16261 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16262 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16263 intSI_type_node, 4);
16264 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16265 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16266 intHI_type_node, 8);
16267 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16268 intQI_type_node, 16);
16270 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16271 unsigned_intQI_type_node, 16);
16272 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16273 unsigned_intHI_type_node, 8);
16274 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16275 unsigned_intSI_type_node, 4);
16276 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16277 ? "__vector unsigned long"
16278 : "__vector unsigned long long",
16279 unsigned_intDI_type_node, 2);
16281 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16283 const_str_type_node
16284 = build_pointer_type (build_qualified_type (char_type_node,
16287 /* We use V1TI mode as a special container to hold __int128_t items that
16288 must live in VSX registers. */
16289 if (intTI_type_node)
16291 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16292 intTI_type_node, 1);
16293 unsigned_V1TI_type_node
16294 = rs6000_vector_type ("__vector unsigned __int128",
16295 unsigned_intTI_type_node, 1);
16298 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16299 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16300 'vector unsigned short'. */
16302 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16303 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16304 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16305 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16306 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16308 long_integer_type_internal_node = long_integer_type_node;
16309 long_unsigned_type_internal_node = long_unsigned_type_node;
16310 long_long_integer_type_internal_node = long_long_integer_type_node;
16311 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16312 intQI_type_internal_node = intQI_type_node;
16313 uintQI_type_internal_node = unsigned_intQI_type_node;
16314 intHI_type_internal_node = intHI_type_node;
16315 uintHI_type_internal_node = unsigned_intHI_type_node;
16316 intSI_type_internal_node = intSI_type_node;
16317 uintSI_type_internal_node = unsigned_intSI_type_node;
16318 intDI_type_internal_node = intDI_type_node;
16319 uintDI_type_internal_node = unsigned_intDI_type_node;
16320 intTI_type_internal_node = intTI_type_node;
16321 uintTI_type_internal_node = unsigned_intTI_type_node;
16322 float_type_internal_node = float_type_node;
16323 double_type_internal_node = double_type_node;
16324 long_double_type_internal_node = long_double_type_node;
16325 dfloat64_type_internal_node = dfloat64_type_node;
16326 dfloat128_type_internal_node = dfloat128_type_node;
16327 void_type_internal_node = void_type_node;
16329 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16330 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16331 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16332 format that uses a pair of doubles, depending on the switches and
16335 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16336 floating point, we need make sure the type is non-zero or else self-test
16337 fails during bootstrap.
16339 Always create __ibm128 as a separate type, even if the current long double
16340 format is IBM extended double.
16342 For IEEE 128-bit floating point, always create the type __ieee128. If the
16343 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16345 if (TARGET_FLOAT128_TYPE)
16347 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16348 ibm128_float_type_node = long_double_type_node;
16351 ibm128_float_type_node = make_node (REAL_TYPE);
16352 TYPE_PRECISION (ibm128_float_type_node) = 128;
16353 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16354 layout_type (ibm128_float_type_node);
16357 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16360 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16361 ieee128_float_type_node = long_double_type_node;
16363 ieee128_float_type_node = float128_type_node;
16365 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16370 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16372 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16374 builtin_mode_to_type[QImode][0] = integer_type_node;
16375 builtin_mode_to_type[HImode][0] = integer_type_node;
16376 builtin_mode_to_type[SImode][0] = intSI_type_node;
16377 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16378 builtin_mode_to_type[DImode][0] = intDI_type_node;
16379 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16380 builtin_mode_to_type[TImode][0] = intTI_type_node;
16381 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16382 builtin_mode_to_type[SFmode][0] = float_type_node;
16383 builtin_mode_to_type[DFmode][0] = double_type_node;
16384 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16385 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16386 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16387 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16388 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16389 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16390 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16391 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16392 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16393 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16394 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16395 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16396 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16397 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16398 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16399 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16400 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16402 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16403 TYPE_NAME (bool_char_type_node) = tdecl;
16405 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16406 TYPE_NAME (bool_short_type_node) = tdecl;
16408 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16409 TYPE_NAME (bool_int_type_node) = tdecl;
16411 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16412 TYPE_NAME (pixel_type_node) = tdecl;
16414 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16415 bool_char_type_node, 16);
16416 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16417 bool_short_type_node, 8);
16418 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16419 bool_int_type_node, 4);
16420 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16421 ? "__vector __bool long"
16422 : "__vector __bool long long",
16423 bool_long_long_type_node, 2);
16424 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16425 pixel_type_node, 8);
16427 /* Create Altivec and VSX builtins on machines with at least the
16428 general purpose extensions (970 and newer) to allow the use of
16429 the target attribute. */
16430 if (TARGET_EXTRA_BUILTINS)
16431 altivec_init_builtins ();
16433 htm_init_builtins ();
16435 if (TARGET_EXTRA_BUILTINS)
16436 rs6000_common_init_builtins ();
16438 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16439 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16440 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16442 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16443 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16444 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16446 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16447 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16448 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16450 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16451 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16452 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16454 mode = (TARGET_64BIT) ? DImode : SImode;
16455 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16456 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16457 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16459 ftype = build_function_type_list (unsigned_intDI_type_node,
16461 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16464 ftype = build_function_type_list (unsigned_intDI_type_node,
16467 ftype = build_function_type_list (unsigned_intSI_type_node,
16469 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16471 ftype = build_function_type_list (double_type_node, NULL_TREE);
16472 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16474 ftype = build_function_type_list (double_type_node, NULL_TREE);
16475 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16477 ftype = build_function_type_list (void_type_node,
16480 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16482 ftype = build_function_type_list (void_type_node,
16485 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16487 ftype = build_function_type_list (void_type_node,
16490 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16492 ftype = build_function_type_list (void_type_node,
16495 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16497 ftype = build_function_type_list (void_type_node,
16498 intSI_type_node, double_type_node,
16500 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16502 ftype = build_function_type_list (void_type_node, NULL_TREE);
16503 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16504 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16505 MISC_BUILTIN_SPEC_BARRIER);
16507 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16509 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16510 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16512 /* AIX libm provides clog as __clog. */
16513 if (TARGET_XCOFF &&
16514 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16515 set_user_assembler_name (tdecl, "__clog");
16517 #ifdef SUBTARGET_INIT_BUILTINS
16518 SUBTARGET_INIT_BUILTINS;
16522 /* Returns the rs6000 builtin decl for CODE. */
16525 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16527 HOST_WIDE_INT fnmask;
16529 if (code >= RS6000_BUILTIN_COUNT)
16530 return error_mark_node;
16532 fnmask = rs6000_builtin_info[code].mask;
16533 if ((fnmask & rs6000_builtin_mask) != fnmask)
16535 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16536 return error_mark_node;
16539 return rs6000_builtin_decls[code];
16543 altivec_init_builtins (void)
16545 const struct builtin_description *d;
16549 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16551 tree pvoid_type_node = build_pointer_type (void_type_node);
16553 tree pcvoid_type_node
16554 = build_pointer_type (build_qualified_type (void_type_node,
16557 tree int_ftype_opaque
16558 = build_function_type_list (integer_type_node,
16559 opaque_V4SI_type_node, NULL_TREE);
16560 tree opaque_ftype_opaque
16561 = build_function_type_list (integer_type_node, NULL_TREE);
16562 tree opaque_ftype_opaque_int
16563 = build_function_type_list (opaque_V4SI_type_node,
16564 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16565 tree opaque_ftype_opaque_opaque_int
16566 = build_function_type_list (opaque_V4SI_type_node,
16567 opaque_V4SI_type_node, opaque_V4SI_type_node,
16568 integer_type_node, NULL_TREE);
16569 tree opaque_ftype_opaque_opaque_opaque
16570 = build_function_type_list (opaque_V4SI_type_node,
16571 opaque_V4SI_type_node, opaque_V4SI_type_node,
16572 opaque_V4SI_type_node, NULL_TREE);
16573 tree opaque_ftype_opaque_opaque
16574 = build_function_type_list (opaque_V4SI_type_node,
16575 opaque_V4SI_type_node, opaque_V4SI_type_node,
16577 tree int_ftype_int_opaque_opaque
16578 = build_function_type_list (integer_type_node,
16579 integer_type_node, opaque_V4SI_type_node,
16580 opaque_V4SI_type_node, NULL_TREE);
16581 tree int_ftype_int_v4si_v4si
16582 = build_function_type_list (integer_type_node,
16583 integer_type_node, V4SI_type_node,
16584 V4SI_type_node, NULL_TREE);
16585 tree int_ftype_int_v2di_v2di
16586 = build_function_type_list (integer_type_node,
16587 integer_type_node, V2DI_type_node,
16588 V2DI_type_node, NULL_TREE);
16589 tree void_ftype_v4si
16590 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16591 tree v8hi_ftype_void
16592 = build_function_type_list (V8HI_type_node, NULL_TREE);
16593 tree void_ftype_void
16594 = build_function_type_list (void_type_node, NULL_TREE);
16595 tree void_ftype_int
16596 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16598 tree opaque_ftype_long_pcvoid
16599 = build_function_type_list (opaque_V4SI_type_node,
16600 long_integer_type_node, pcvoid_type_node,
16602 tree v16qi_ftype_long_pcvoid
16603 = build_function_type_list (V16QI_type_node,
16604 long_integer_type_node, pcvoid_type_node,
16606 tree v8hi_ftype_long_pcvoid
16607 = build_function_type_list (V8HI_type_node,
16608 long_integer_type_node, pcvoid_type_node,
16610 tree v4si_ftype_long_pcvoid
16611 = build_function_type_list (V4SI_type_node,
16612 long_integer_type_node, pcvoid_type_node,
16614 tree v4sf_ftype_long_pcvoid
16615 = build_function_type_list (V4SF_type_node,
16616 long_integer_type_node, pcvoid_type_node,
16618 tree v2df_ftype_long_pcvoid
16619 = build_function_type_list (V2DF_type_node,
16620 long_integer_type_node, pcvoid_type_node,
16622 tree v2di_ftype_long_pcvoid
16623 = build_function_type_list (V2DI_type_node,
16624 long_integer_type_node, pcvoid_type_node,
16626 tree v1ti_ftype_long_pcvoid
16627 = build_function_type_list (V1TI_type_node,
16628 long_integer_type_node, pcvoid_type_node,
16631 tree void_ftype_opaque_long_pvoid
16632 = build_function_type_list (void_type_node,
16633 opaque_V4SI_type_node, long_integer_type_node,
16634 pvoid_type_node, NULL_TREE);
16635 tree void_ftype_v4si_long_pvoid
16636 = build_function_type_list (void_type_node,
16637 V4SI_type_node, long_integer_type_node,
16638 pvoid_type_node, NULL_TREE);
16639 tree void_ftype_v16qi_long_pvoid
16640 = build_function_type_list (void_type_node,
16641 V16QI_type_node, long_integer_type_node,
16642 pvoid_type_node, NULL_TREE);
16644 tree void_ftype_v16qi_pvoid_long
16645 = build_function_type_list (void_type_node,
16646 V16QI_type_node, pvoid_type_node,
16647 long_integer_type_node, NULL_TREE);
16649 tree void_ftype_v8hi_long_pvoid
16650 = build_function_type_list (void_type_node,
16651 V8HI_type_node, long_integer_type_node,
16652 pvoid_type_node, NULL_TREE);
16653 tree void_ftype_v4sf_long_pvoid
16654 = build_function_type_list (void_type_node,
16655 V4SF_type_node, long_integer_type_node,
16656 pvoid_type_node, NULL_TREE);
16657 tree void_ftype_v2df_long_pvoid
16658 = build_function_type_list (void_type_node,
16659 V2DF_type_node, long_integer_type_node,
16660 pvoid_type_node, NULL_TREE);
16661 tree void_ftype_v1ti_long_pvoid
16662 = build_function_type_list (void_type_node,
16663 V1TI_type_node, long_integer_type_node,
16664 pvoid_type_node, NULL_TREE);
16665 tree void_ftype_v2di_long_pvoid
16666 = build_function_type_list (void_type_node,
16667 V2DI_type_node, long_integer_type_node,
16668 pvoid_type_node, NULL_TREE);
16669 tree int_ftype_int_v8hi_v8hi
16670 = build_function_type_list (integer_type_node,
16671 integer_type_node, V8HI_type_node,
16672 V8HI_type_node, NULL_TREE);
16673 tree int_ftype_int_v16qi_v16qi
16674 = build_function_type_list (integer_type_node,
16675 integer_type_node, V16QI_type_node,
16676 V16QI_type_node, NULL_TREE);
16677 tree int_ftype_int_v4sf_v4sf
16678 = build_function_type_list (integer_type_node,
16679 integer_type_node, V4SF_type_node,
16680 V4SF_type_node, NULL_TREE);
16681 tree int_ftype_int_v2df_v2df
16682 = build_function_type_list (integer_type_node,
16683 integer_type_node, V2DF_type_node,
16684 V2DF_type_node, NULL_TREE);
16685 tree v2di_ftype_v2di
16686 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16687 tree v4si_ftype_v4si
16688 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16689 tree v8hi_ftype_v8hi
16690 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16691 tree v16qi_ftype_v16qi
16692 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16693 tree v4sf_ftype_v4sf
16694 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16695 tree v2df_ftype_v2df
16696 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16697 tree void_ftype_pcvoid_int_int
16698 = build_function_type_list (void_type_node,
16699 pcvoid_type_node, integer_type_node,
16700 integer_type_node, NULL_TREE);
16702 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16703 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16704 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16705 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16706 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16707 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16708 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16709 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16710 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16711 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16712 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16713 ALTIVEC_BUILTIN_LVXL_V2DF);
16714 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16715 ALTIVEC_BUILTIN_LVXL_V2DI);
16716 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16717 ALTIVEC_BUILTIN_LVXL_V4SF);
16718 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16719 ALTIVEC_BUILTIN_LVXL_V4SI);
16720 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16721 ALTIVEC_BUILTIN_LVXL_V8HI);
16722 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16723 ALTIVEC_BUILTIN_LVXL_V16QI);
16724 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16725 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16726 ALTIVEC_BUILTIN_LVX_V1TI);
16727 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16728 ALTIVEC_BUILTIN_LVX_V2DF);
16729 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16730 ALTIVEC_BUILTIN_LVX_V2DI);
16731 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16732 ALTIVEC_BUILTIN_LVX_V4SF);
16733 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16734 ALTIVEC_BUILTIN_LVX_V4SI);
16735 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16736 ALTIVEC_BUILTIN_LVX_V8HI);
16737 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16738 ALTIVEC_BUILTIN_LVX_V16QI);
16739 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16740 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16741 ALTIVEC_BUILTIN_STVX_V2DF);
16742 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16743 ALTIVEC_BUILTIN_STVX_V2DI);
16744 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16745 ALTIVEC_BUILTIN_STVX_V4SF);
16746 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16747 ALTIVEC_BUILTIN_STVX_V4SI);
16748 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16749 ALTIVEC_BUILTIN_STVX_V8HI);
16750 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16751 ALTIVEC_BUILTIN_STVX_V16QI);
16752 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16753 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16754 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16755 ALTIVEC_BUILTIN_STVXL_V2DF);
16756 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16757 ALTIVEC_BUILTIN_STVXL_V2DI);
16758 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16759 ALTIVEC_BUILTIN_STVXL_V4SF);
16760 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16761 ALTIVEC_BUILTIN_STVXL_V4SI);
16762 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16763 ALTIVEC_BUILTIN_STVXL_V8HI);
16764 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16765 ALTIVEC_BUILTIN_STVXL_V16QI);
16766 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16767 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16768 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16769 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16770 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16771 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16772 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16773 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16774 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16775 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16776 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16777 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16778 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16779 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16780 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16781 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16783 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16784 VSX_BUILTIN_LXVD2X_V2DF);
16785 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16786 VSX_BUILTIN_LXVD2X_V2DI);
16787 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16788 VSX_BUILTIN_LXVW4X_V4SF);
16789 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16790 VSX_BUILTIN_LXVW4X_V4SI);
16791 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16792 VSX_BUILTIN_LXVW4X_V8HI);
16793 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16794 VSX_BUILTIN_LXVW4X_V16QI);
16795 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16796 VSX_BUILTIN_STXVD2X_V2DF);
16797 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16798 VSX_BUILTIN_STXVD2X_V2DI);
16799 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16800 VSX_BUILTIN_STXVW4X_V4SF);
16801 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16802 VSX_BUILTIN_STXVW4X_V4SI);
16803 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16804 VSX_BUILTIN_STXVW4X_V8HI);
16805 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16806 VSX_BUILTIN_STXVW4X_V16QI);
16808 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16809 VSX_BUILTIN_LD_ELEMREV_V2DF);
16810 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16811 VSX_BUILTIN_LD_ELEMREV_V2DI);
16812 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16813 VSX_BUILTIN_LD_ELEMREV_V4SF);
16814 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16815 VSX_BUILTIN_LD_ELEMREV_V4SI);
16816 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16817 VSX_BUILTIN_LD_ELEMREV_V8HI);
16818 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16819 VSX_BUILTIN_LD_ELEMREV_V16QI);
16820 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16821 VSX_BUILTIN_ST_ELEMREV_V2DF);
16822 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16823 VSX_BUILTIN_ST_ELEMREV_V1TI);
16824 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16825 VSX_BUILTIN_ST_ELEMREV_V2DI);
16826 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16827 VSX_BUILTIN_ST_ELEMREV_V4SF);
16828 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16829 VSX_BUILTIN_ST_ELEMREV_V4SI);
16830 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16831 VSX_BUILTIN_ST_ELEMREV_V8HI);
16832 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16833 VSX_BUILTIN_ST_ELEMREV_V16QI);
16835 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16836 VSX_BUILTIN_VEC_LD);
16837 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16838 VSX_BUILTIN_VEC_ST);
16839 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16840 VSX_BUILTIN_VEC_XL);
16841 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16842 VSX_BUILTIN_VEC_XL_BE);
16843 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16844 VSX_BUILTIN_VEC_XST);
16845 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16846 VSX_BUILTIN_VEC_XST_BE);
16848 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16849 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16850 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16852 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16853 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16854 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16855 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16856 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16857 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16858 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16859 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16860 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16861 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16862 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16863 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16865 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16866 ALTIVEC_BUILTIN_VEC_ADDE);
16867 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16868 ALTIVEC_BUILTIN_VEC_ADDEC);
16869 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16870 ALTIVEC_BUILTIN_VEC_CMPNE);
16871 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16872 ALTIVEC_BUILTIN_VEC_MUL);
16873 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16874 ALTIVEC_BUILTIN_VEC_SUBE);
16875 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16876 ALTIVEC_BUILTIN_VEC_SUBEC);
16878 /* Cell builtins. */
16879 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16880 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16881 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16882 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16884 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16885 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16886 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16887 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16889 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16890 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16891 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16892 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16894 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16895 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16896 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16897 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16899 if (TARGET_P9_VECTOR)
16901 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16902 P9V_BUILTIN_STXVL);
16903 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16904 P9V_BUILTIN_XST_LEN_R);
16907 /* Add the DST variants. */
16909 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16911 HOST_WIDE_INT mask = d->mask;
16913 /* It is expected that these dst built-in functions may have
16914 d->icode equal to CODE_FOR_nothing. */
16915 if ((mask & builtin_mask) != mask)
16917 if (TARGET_DEBUG_BUILTIN)
16918 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16922 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16925 /* Initialize the predicates. */
16926 d = bdesc_altivec_preds;
16927 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16929 machine_mode mode1;
16931 HOST_WIDE_INT mask = d->mask;
16933 if ((mask & builtin_mask) != mask)
16935 if (TARGET_DEBUG_BUILTIN)
16936 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16941 if (rs6000_overloaded_builtin_p (d->code))
16945 /* Cannot define builtin if the instruction is disabled. */
16946 gcc_assert (d->icode != CODE_FOR_nothing);
16947 mode1 = insn_data[d->icode].operand[1].mode;
16953 type = int_ftype_int_opaque_opaque;
16956 type = int_ftype_int_v2di_v2di;
16959 type = int_ftype_int_v4si_v4si;
16962 type = int_ftype_int_v8hi_v8hi;
16965 type = int_ftype_int_v16qi_v16qi;
16968 type = int_ftype_int_v4sf_v4sf;
16971 type = int_ftype_int_v2df_v2df;
16974 gcc_unreachable ();
16977 def_builtin (d->name, type, d->code);
16980 /* Initialize the abs* operators. */
16982 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
16984 machine_mode mode0;
16986 HOST_WIDE_INT mask = d->mask;
16988 if ((mask & builtin_mask) != mask)
16990 if (TARGET_DEBUG_BUILTIN)
16991 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
16996 /* Cannot define builtin if the instruction is disabled. */
16997 gcc_assert (d->icode != CODE_FOR_nothing);
16998 mode0 = insn_data[d->icode].operand[0].mode;
17003 type = v2di_ftype_v2di;
17006 type = v4si_ftype_v4si;
17009 type = v8hi_ftype_v8hi;
17012 type = v16qi_ftype_v16qi;
17015 type = v4sf_ftype_v4sf;
17018 type = v2df_ftype_v2df;
17021 gcc_unreachable ();
17024 def_builtin (d->name, type, d->code);
17027 /* Initialize target builtin that implements
17028 targetm.vectorize.builtin_mask_for_load. */
17030 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17031 v16qi_ftype_long_pcvoid,
17032 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17033 BUILT_IN_MD, NULL, NULL_TREE);
17034 TREE_READONLY (decl) = 1;
17035 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17036 altivec_builtin_mask_for_load = decl;
17038 /* Access to the vec_init patterns. */
17039 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17040 integer_type_node, integer_type_node,
17041 integer_type_node, NULL_TREE);
17042 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17044 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17045 short_integer_type_node,
17046 short_integer_type_node,
17047 short_integer_type_node,
17048 short_integer_type_node,
17049 short_integer_type_node,
17050 short_integer_type_node,
17051 short_integer_type_node, NULL_TREE);
17052 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17054 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17055 char_type_node, char_type_node,
17056 char_type_node, char_type_node,
17057 char_type_node, char_type_node,
17058 char_type_node, char_type_node,
17059 char_type_node, char_type_node,
17060 char_type_node, char_type_node,
17061 char_type_node, char_type_node,
17062 char_type_node, NULL_TREE);
17063 def_builtin ("__builtin_vec_init_v16qi", ftype,
17064 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17066 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17067 float_type_node, float_type_node,
17068 float_type_node, NULL_TREE);
17069 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17071 /* VSX builtins. */
17072 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17073 double_type_node, NULL_TREE);
17074 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17076 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17077 intDI_type_node, NULL_TREE);
17078 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17080 /* Access to the vec_set patterns. */
17081 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17083 integer_type_node, NULL_TREE);
17084 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17086 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17088 integer_type_node, NULL_TREE);
17089 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17091 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17093 integer_type_node, NULL_TREE);
17094 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17096 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17098 integer_type_node, NULL_TREE);
17099 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17101 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17103 integer_type_node, NULL_TREE);
17104 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17106 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17108 integer_type_node, NULL_TREE);
17109 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17111 /* Access to the vec_extract patterns. */
17112 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17113 integer_type_node, NULL_TREE);
17114 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17116 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17117 integer_type_node, NULL_TREE);
17118 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17120 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17121 integer_type_node, NULL_TREE);
17122 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17124 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17125 integer_type_node, NULL_TREE);
17126 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17128 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17129 integer_type_node, NULL_TREE);
17130 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17132 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17133 integer_type_node, NULL_TREE);
17134 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17137 if (V1TI_type_node)
17139 tree v1ti_ftype_long_pcvoid
17140 = build_function_type_list (V1TI_type_node,
17141 long_integer_type_node, pcvoid_type_node,
17143 tree void_ftype_v1ti_long_pvoid
17144 = build_function_type_list (void_type_node,
17145 V1TI_type_node, long_integer_type_node,
17146 pvoid_type_node, NULL_TREE);
17147 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17148 VSX_BUILTIN_LD_ELEMREV_V1TI);
17149 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17150 VSX_BUILTIN_LXVD2X_V1TI);
17151 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17152 VSX_BUILTIN_STXVD2X_V1TI);
17153 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17154 NULL_TREE, NULL_TREE);
17155 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17156 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17158 integer_type_node, NULL_TREE);
17159 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17160 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17161 integer_type_node, NULL_TREE);
17162 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17168 htm_init_builtins (void)
17170 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17171 const struct builtin_description *d;
17175 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17177 tree op[MAX_HTM_OPERANDS], type;
17178 HOST_WIDE_INT mask = d->mask;
17179 unsigned attr = rs6000_builtin_info[d->code].attr;
17180 bool void_func = (attr & RS6000_BTC_VOID);
17181 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17183 tree gpr_type_node;
17187 /* It is expected that these htm built-in functions may have
17188 d->icode equal to CODE_FOR_nothing. */
17190 if (TARGET_32BIT && TARGET_POWERPC64)
17191 gpr_type_node = long_long_unsigned_type_node;
17193 gpr_type_node = long_unsigned_type_node;
17195 if (attr & RS6000_BTC_SPR)
17197 rettype = gpr_type_node;
17198 argtype = gpr_type_node;
17200 else if (d->code == HTM_BUILTIN_TABORTDC
17201 || d->code == HTM_BUILTIN_TABORTDCI)
17203 rettype = unsigned_type_node;
17204 argtype = gpr_type_node;
17208 rettype = unsigned_type_node;
17209 argtype = unsigned_type_node;
17212 if ((mask & builtin_mask) != mask)
17214 if (TARGET_DEBUG_BUILTIN)
17215 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17221 if (TARGET_DEBUG_BUILTIN)
17222 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17223 (long unsigned) i);
17227 op[nopnds++] = (void_func) ? void_type_node : rettype;
17229 if (attr_args == RS6000_BTC_UNARY)
17230 op[nopnds++] = argtype;
17231 else if (attr_args == RS6000_BTC_BINARY)
17233 op[nopnds++] = argtype;
17234 op[nopnds++] = argtype;
17236 else if (attr_args == RS6000_BTC_TERNARY)
17238 op[nopnds++] = argtype;
17239 op[nopnds++] = argtype;
17240 op[nopnds++] = argtype;
17246 type = build_function_type_list (op[0], NULL_TREE);
17249 type = build_function_type_list (op[0], op[1], NULL_TREE);
17252 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17255 type = build_function_type_list (op[0], op[1], op[2], op[3],
17259 gcc_unreachable ();
17262 def_builtin (d->name, type, d->code);
17266 /* Hash function for builtin functions with up to 3 arguments and a return
17269 builtin_hasher::hash (builtin_hash_struct *bh)
17274 for (i = 0; i < 4; i++)
17276 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17277 ret = (ret * 2) + bh->uns_p[i];
17283 /* Compare builtin hash entries H1 and H2 for equivalence. */
17285 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17287 return ((p1->mode[0] == p2->mode[0])
17288 && (p1->mode[1] == p2->mode[1])
17289 && (p1->mode[2] == p2->mode[2])
17290 && (p1->mode[3] == p2->mode[3])
17291 && (p1->uns_p[0] == p2->uns_p[0])
17292 && (p1->uns_p[1] == p2->uns_p[1])
17293 && (p1->uns_p[2] == p2->uns_p[2])
17294 && (p1->uns_p[3] == p2->uns_p[3]));
17297 /* Map types for builtin functions with an explicit return type and up to 3
17298 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17299 of the argument. */
17301 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17302 machine_mode mode_arg1, machine_mode mode_arg2,
17303 enum rs6000_builtins builtin, const char *name)
17305 struct builtin_hash_struct h;
17306 struct builtin_hash_struct *h2;
17309 tree ret_type = NULL_TREE;
17310 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17312 /* Create builtin_hash_table. */
17313 if (builtin_hash_table == NULL)
17314 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17316 h.type = NULL_TREE;
17317 h.mode[0] = mode_ret;
17318 h.mode[1] = mode_arg0;
17319 h.mode[2] = mode_arg1;
17320 h.mode[3] = mode_arg2;
17326 /* If the builtin is a type that produces unsigned results or takes unsigned
17327 arguments, and it is returned as a decl for the vectorizer (such as
17328 widening multiplies, permute), make sure the arguments and return value
17329 are type correct. */
17332 /* unsigned 1 argument functions. */
17333 case CRYPTO_BUILTIN_VSBOX:
17334 case CRYPTO_BUILTIN_VSBOX_BE:
17335 case P8V_BUILTIN_VGBBD:
17336 case MISC_BUILTIN_CDTBCD:
17337 case MISC_BUILTIN_CBCDTD:
17342 /* unsigned 2 argument functions. */
17343 case ALTIVEC_BUILTIN_VMULEUB:
17344 case ALTIVEC_BUILTIN_VMULEUH:
17345 case P8V_BUILTIN_VMULEUW:
17346 case ALTIVEC_BUILTIN_VMULOUB:
17347 case ALTIVEC_BUILTIN_VMULOUH:
17348 case P8V_BUILTIN_VMULOUW:
17349 case CRYPTO_BUILTIN_VCIPHER:
17350 case CRYPTO_BUILTIN_VCIPHER_BE:
17351 case CRYPTO_BUILTIN_VCIPHERLAST:
17352 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
17353 case CRYPTO_BUILTIN_VNCIPHER:
17354 case CRYPTO_BUILTIN_VNCIPHER_BE:
17355 case CRYPTO_BUILTIN_VNCIPHERLAST:
17356 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
17357 case CRYPTO_BUILTIN_VPMSUMB:
17358 case CRYPTO_BUILTIN_VPMSUMH:
17359 case CRYPTO_BUILTIN_VPMSUMW:
17360 case CRYPTO_BUILTIN_VPMSUMD:
17361 case CRYPTO_BUILTIN_VPMSUM:
17362 case MISC_BUILTIN_ADDG6S:
17363 case MISC_BUILTIN_DIVWEU:
17364 case MISC_BUILTIN_DIVDEU:
17365 case VSX_BUILTIN_UDIV_V2DI:
17366 case ALTIVEC_BUILTIN_VMAXUB:
17367 case ALTIVEC_BUILTIN_VMINUB:
17368 case ALTIVEC_BUILTIN_VMAXUH:
17369 case ALTIVEC_BUILTIN_VMINUH:
17370 case ALTIVEC_BUILTIN_VMAXUW:
17371 case ALTIVEC_BUILTIN_VMINUW:
17372 case P8V_BUILTIN_VMAXUD:
17373 case P8V_BUILTIN_VMINUD:
17379 /* unsigned 3 argument functions. */
17380 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17381 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17382 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17383 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17384 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17385 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17386 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17387 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17388 case VSX_BUILTIN_VPERM_16QI_UNS:
17389 case VSX_BUILTIN_VPERM_8HI_UNS:
17390 case VSX_BUILTIN_VPERM_4SI_UNS:
17391 case VSX_BUILTIN_VPERM_2DI_UNS:
17392 case VSX_BUILTIN_XXSEL_16QI_UNS:
17393 case VSX_BUILTIN_XXSEL_8HI_UNS:
17394 case VSX_BUILTIN_XXSEL_4SI_UNS:
17395 case VSX_BUILTIN_XXSEL_2DI_UNS:
17396 case CRYPTO_BUILTIN_VPERMXOR:
17397 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17398 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17399 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17400 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17401 case CRYPTO_BUILTIN_VSHASIGMAW:
17402 case CRYPTO_BUILTIN_VSHASIGMAD:
17403 case CRYPTO_BUILTIN_VSHASIGMA:
17410 /* signed permute functions with unsigned char mask. */
17411 case ALTIVEC_BUILTIN_VPERM_16QI:
17412 case ALTIVEC_BUILTIN_VPERM_8HI:
17413 case ALTIVEC_BUILTIN_VPERM_4SI:
17414 case ALTIVEC_BUILTIN_VPERM_4SF:
17415 case ALTIVEC_BUILTIN_VPERM_2DI:
17416 case ALTIVEC_BUILTIN_VPERM_2DF:
17417 case VSX_BUILTIN_VPERM_16QI:
17418 case VSX_BUILTIN_VPERM_8HI:
17419 case VSX_BUILTIN_VPERM_4SI:
17420 case VSX_BUILTIN_VPERM_4SF:
17421 case VSX_BUILTIN_VPERM_2DI:
17422 case VSX_BUILTIN_VPERM_2DF:
17426 /* unsigned args, signed return. */
17427 case VSX_BUILTIN_XVCVUXDSP:
17428 case VSX_BUILTIN_XVCVUXDDP_UNS:
17429 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17433 /* signed args, unsigned return. */
17434 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17435 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17436 case MISC_BUILTIN_UNPACK_TD:
17437 case MISC_BUILTIN_UNPACK_V1TI:
17441 /* unsigned arguments, bool return (compares). */
17442 case ALTIVEC_BUILTIN_VCMPEQUB:
17443 case ALTIVEC_BUILTIN_VCMPEQUH:
17444 case ALTIVEC_BUILTIN_VCMPEQUW:
17445 case P8V_BUILTIN_VCMPEQUD:
17446 case VSX_BUILTIN_CMPGE_U16QI:
17447 case VSX_BUILTIN_CMPGE_U8HI:
17448 case VSX_BUILTIN_CMPGE_U4SI:
17449 case VSX_BUILTIN_CMPGE_U2DI:
17450 case ALTIVEC_BUILTIN_VCMPGTUB:
17451 case ALTIVEC_BUILTIN_VCMPGTUH:
17452 case ALTIVEC_BUILTIN_VCMPGTUW:
17453 case P8V_BUILTIN_VCMPGTUD:
17458 /* unsigned arguments for 128-bit pack instructions. */
17459 case MISC_BUILTIN_PACK_TD:
17460 case MISC_BUILTIN_PACK_V1TI:
17465 /* unsigned second arguments (vector shift right). */
17466 case ALTIVEC_BUILTIN_VSRB:
17467 case ALTIVEC_BUILTIN_VSRH:
17468 case ALTIVEC_BUILTIN_VSRW:
17469 case P8V_BUILTIN_VSRD:
17477 /* Figure out how many args are present. */
17478 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17481 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17482 if (!ret_type && h.uns_p[0])
17483 ret_type = builtin_mode_to_type[h.mode[0]][0];
17486 fatal_error (input_location,
17487 "internal error: builtin function %qs had an unexpected "
17488 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17490 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17491 arg_type[i] = NULL_TREE;
17493 for (i = 0; i < num_args; i++)
17495 int m = (int) h.mode[i+1];
17496 int uns_p = h.uns_p[i+1];
17498 arg_type[i] = builtin_mode_to_type[m][uns_p];
17499 if (!arg_type[i] && uns_p)
17500 arg_type[i] = builtin_mode_to_type[m][0];
17503 fatal_error (input_location,
17504 "internal error: builtin function %qs, argument %d "
17505 "had unexpected argument type %qs", name, i,
17506 GET_MODE_NAME (m));
17509 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17510 if (*found == NULL)
17512 h2 = ggc_alloc<builtin_hash_struct> ();
17516 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17517 arg_type[2], NULL_TREE);
17520 return (*found)->type;
17524 rs6000_common_init_builtins (void)
17526 const struct builtin_description *d;
17529 tree opaque_ftype_opaque = NULL_TREE;
17530 tree opaque_ftype_opaque_opaque = NULL_TREE;
17531 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17532 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17534 /* Create Altivec and VSX builtins on machines with at least the
17535 general purpose extensions (970 and newer) to allow the use of
17536 the target attribute. */
17538 if (TARGET_EXTRA_BUILTINS)
17539 builtin_mask |= RS6000_BTM_COMMON;
17541 /* Add the ternary operators. */
17543 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17546 HOST_WIDE_INT mask = d->mask;
17548 if ((mask & builtin_mask) != mask)
17550 if (TARGET_DEBUG_BUILTIN)
17551 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17555 if (rs6000_overloaded_builtin_p (d->code))
17557 if (! (type = opaque_ftype_opaque_opaque_opaque))
17558 type = opaque_ftype_opaque_opaque_opaque
17559 = build_function_type_list (opaque_V4SI_type_node,
17560 opaque_V4SI_type_node,
17561 opaque_V4SI_type_node,
17562 opaque_V4SI_type_node,
17567 enum insn_code icode = d->icode;
17570 if (TARGET_DEBUG_BUILTIN)
17571 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17577 if (icode == CODE_FOR_nothing)
17579 if (TARGET_DEBUG_BUILTIN)
17580 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17586 type = builtin_function_type (insn_data[icode].operand[0].mode,
17587 insn_data[icode].operand[1].mode,
17588 insn_data[icode].operand[2].mode,
17589 insn_data[icode].operand[3].mode,
17593 def_builtin (d->name, type, d->code);
17596 /* Add the binary operators. */
17598 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17600 machine_mode mode0, mode1, mode2;
17602 HOST_WIDE_INT mask = d->mask;
17604 if ((mask & builtin_mask) != mask)
17606 if (TARGET_DEBUG_BUILTIN)
17607 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17611 if (rs6000_overloaded_builtin_p (d->code))
17613 if (! (type = opaque_ftype_opaque_opaque))
17614 type = opaque_ftype_opaque_opaque
17615 = build_function_type_list (opaque_V4SI_type_node,
17616 opaque_V4SI_type_node,
17617 opaque_V4SI_type_node,
17622 enum insn_code icode = d->icode;
17625 if (TARGET_DEBUG_BUILTIN)
17626 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17632 if (icode == CODE_FOR_nothing)
17634 if (TARGET_DEBUG_BUILTIN)
17635 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17641 mode0 = insn_data[icode].operand[0].mode;
17642 mode1 = insn_data[icode].operand[1].mode;
17643 mode2 = insn_data[icode].operand[2].mode;
17645 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17649 def_builtin (d->name, type, d->code);
17652 /* Add the simple unary operators. */
17654 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17656 machine_mode mode0, mode1;
17658 HOST_WIDE_INT mask = d->mask;
17660 if ((mask & builtin_mask) != mask)
17662 if (TARGET_DEBUG_BUILTIN)
17663 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17667 if (rs6000_overloaded_builtin_p (d->code))
17669 if (! (type = opaque_ftype_opaque))
17670 type = opaque_ftype_opaque
17671 = build_function_type_list (opaque_V4SI_type_node,
17672 opaque_V4SI_type_node,
17677 enum insn_code icode = d->icode;
17680 if (TARGET_DEBUG_BUILTIN)
17681 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17687 if (icode == CODE_FOR_nothing)
17689 if (TARGET_DEBUG_BUILTIN)
17690 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17696 mode0 = insn_data[icode].operand[0].mode;
17697 mode1 = insn_data[icode].operand[1].mode;
17699 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17703 def_builtin (d->name, type, d->code);
17706 /* Add the simple no-argument operators. */
17708 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17710 machine_mode mode0;
17712 HOST_WIDE_INT mask = d->mask;
17714 if ((mask & builtin_mask) != mask)
17716 if (TARGET_DEBUG_BUILTIN)
17717 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17720 if (rs6000_overloaded_builtin_p (d->code))
17722 if (!opaque_ftype_opaque)
17723 opaque_ftype_opaque
17724 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17725 type = opaque_ftype_opaque;
17729 enum insn_code icode = d->icode;
17732 if (TARGET_DEBUG_BUILTIN)
17733 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17734 (long unsigned) i);
17737 if (icode == CODE_FOR_nothing)
17739 if (TARGET_DEBUG_BUILTIN)
17741 "rs6000_builtin, skip no-argument %s (no code)\n",
17745 mode0 = insn_data[icode].operand[0].mode;
17746 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17749 def_builtin (d->name, type, d->code);
17753 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17755 init_float128_ibm (machine_mode mode)
17757 if (!TARGET_XL_COMPAT)
17759 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17760 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17761 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17762 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17764 if (!TARGET_HARD_FLOAT)
17766 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17767 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17768 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17769 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17770 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17771 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17772 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17773 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17775 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17776 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17777 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17778 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17779 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17780 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17781 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17782 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17787 set_optab_libfunc (add_optab, mode, "_xlqadd");
17788 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17789 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17790 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17793 /* Add various conversions for IFmode to use the traditional TFmode
17795 if (mode == IFmode)
17797 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17798 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17799 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17800 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17801 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17802 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17804 if (TARGET_POWERPC64)
17806 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17807 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17808 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17809 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17814 /* Create a decl for either complex long double multiply or complex long double
17815 divide when long double is IEEE 128-bit floating point. We can't use
17816 __multc3 and __divtc3 because the original long double using IBM extended
17817 double used those names. The complex multiply/divide functions are encoded
17818 as builtin functions with a complex result and 4 scalar inputs. */
17821 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17823 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17826 set_builtin_decl (fncode, fndecl, true);
17828 if (TARGET_DEBUG_BUILTIN)
17829 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17834 /* Set up IEEE 128-bit floating point routines. Use different names if the
17835 arguments can be passed in a vector register. The historical PowerPC
17836 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17837 continue to use that if we aren't using vector registers to pass IEEE
17838 128-bit floating point. */
17841 init_float128_ieee (machine_mode mode)
17843 if (FLOAT128_VECTOR_P (mode))
17845 static bool complex_muldiv_init_p = false;
17847 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
17848 we have clone or target attributes, this will be called a second
17849 time. We want to create the built-in function only once. */
17850 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
17852 complex_muldiv_init_p = true;
17853 built_in_function fncode_mul =
17854 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17855 - MIN_MODE_COMPLEX_FLOAT);
17856 built_in_function fncode_div =
17857 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17858 - MIN_MODE_COMPLEX_FLOAT);
17860 tree fntype = build_function_type_list (complex_long_double_type_node,
17861 long_double_type_node,
17862 long_double_type_node,
17863 long_double_type_node,
17864 long_double_type_node,
17867 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17868 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17871 set_optab_libfunc (add_optab, mode, "__addkf3");
17872 set_optab_libfunc (sub_optab, mode, "__subkf3");
17873 set_optab_libfunc (neg_optab, mode, "__negkf2");
17874 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17875 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17876 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17877 set_optab_libfunc (abs_optab, mode, "__abskf2");
17878 set_optab_libfunc (powi_optab, mode, "__powikf2");
17880 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17881 set_optab_libfunc (ne_optab, mode, "__nekf2");
17882 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17883 set_optab_libfunc (ge_optab, mode, "__gekf2");
17884 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17885 set_optab_libfunc (le_optab, mode, "__lekf2");
17886 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17888 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17889 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17890 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17891 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17893 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17894 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17895 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17897 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17898 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17899 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17901 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
17902 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
17903 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
17904 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
17905 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
17906 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
17908 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17909 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17910 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17911 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17913 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17914 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17915 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17916 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17918 if (TARGET_POWERPC64)
17920 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17921 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17922 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17923 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17929 set_optab_libfunc (add_optab, mode, "_q_add");
17930 set_optab_libfunc (sub_optab, mode, "_q_sub");
17931 set_optab_libfunc (neg_optab, mode, "_q_neg");
17932 set_optab_libfunc (smul_optab, mode, "_q_mul");
17933 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17934 if (TARGET_PPC_GPOPT)
17935 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17937 set_optab_libfunc (eq_optab, mode, "_q_feq");
17938 set_optab_libfunc (ne_optab, mode, "_q_fne");
17939 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17940 set_optab_libfunc (ge_optab, mode, "_q_fge");
17941 set_optab_libfunc (lt_optab, mode, "_q_flt");
17942 set_optab_libfunc (le_optab, mode, "_q_fle");
17944 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17945 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17946 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17947 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17948 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17949 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17950 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17951 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17956 rs6000_init_libfuncs (void)
17958 /* __float128 support. */
17959 if (TARGET_FLOAT128_TYPE)
17961 init_float128_ibm (IFmode);
17962 init_float128_ieee (KFmode);
17965 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17966 if (TARGET_LONG_DOUBLE_128)
17968 if (!TARGET_IEEEQUAD)
17969 init_float128_ibm (TFmode);
17971 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
17973 init_float128_ieee (TFmode);
17977 /* Emit a potentially record-form instruction, setting DST from SRC.
17978 If DOT is 0, that is all; otherwise, set CCREG to the result of the
17979 signed comparison of DST with zero. If DOT is 1, the generated RTL
17980 doesn't care about the DST result; if DOT is 2, it does. If CCREG
17981 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
17982 a separate COMPARE. */
17985 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
17989 emit_move_insn (dst, src);
17993 if (cc_reg_not_cr0_operand (ccreg, CCmode))
17995 emit_move_insn (dst, src);
17996 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18000 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18003 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18004 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18008 rtx set = gen_rtx_SET (dst, src);
18009 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18014 /* A validation routine: say whether CODE, a condition code, and MODE
18015 match. The other alternatives either don't make sense or should
18016 never be generated. */
18019 validate_condition_mode (enum rtx_code code, machine_mode mode)
18021 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18022 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18023 && GET_MODE_CLASS (mode) == MODE_CC);
18025 /* These don't make sense. */
18026 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18027 || mode != CCUNSmode);
18029 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18030 || mode == CCUNSmode);
18032 gcc_assert (mode == CCFPmode
18033 || (code != ORDERED && code != UNORDERED
18034 && code != UNEQ && code != LTGT
18035 && code != UNGT && code != UNLT
18036 && code != UNGE && code != UNLE));
18038 /* These should never be generated except for
18039 flag_finite_math_only. */
18040 gcc_assert (mode != CCFPmode
18041 || flag_finite_math_only
18042 || (code != LE && code != GE
18043 && code != UNEQ && code != LTGT
18044 && code != UNGT && code != UNLT));
18046 /* These are invalid; the information is not there. */
18047 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18051 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18052 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18053 not zero, store there the bit offset (counted from the right) where
18054 the single stretch of 1 bits begins; and similarly for B, the bit
18055 offset where it ends. */
18058 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18060 unsigned HOST_WIDE_INT val = INTVAL (mask);
18061 unsigned HOST_WIDE_INT bit;
18063 int n = GET_MODE_PRECISION (mode);
18065 if (mode != DImode && mode != SImode)
18068 if (INTVAL (mask) >= 0)
18071 ne = exact_log2 (bit);
18072 nb = exact_log2 (val + bit);
18074 else if (val + 1 == 0)
18083 nb = exact_log2 (bit);
18084 ne = exact_log2 (val + bit);
18089 ne = exact_log2 (bit);
18090 if (val + bit == 0)
18098 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18109 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18110 or rldicr instruction, to implement an AND with it in mode MODE. */
18113 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18117 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18120 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18122 if (mode == DImode)
18123 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18125 /* For SImode, rlwinm can do everything. */
18126 if (mode == SImode)
18127 return (nb < 32 && ne < 32);
18132 /* Return the instruction template for an AND with mask in mode MODE, with
18133 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18136 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18140 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18141 gcc_unreachable ();
18143 if (mode == DImode && ne == 0)
18145 operands[3] = GEN_INT (63 - nb);
18147 return "rldicl. %0,%1,0,%3";
18148 return "rldicl %0,%1,0,%3";
18151 if (mode == DImode && nb == 63)
18153 operands[3] = GEN_INT (63 - ne);
18155 return "rldicr. %0,%1,0,%3";
18156 return "rldicr %0,%1,0,%3";
18159 if (nb < 32 && ne < 32)
18161 operands[3] = GEN_INT (31 - nb);
18162 operands[4] = GEN_INT (31 - ne);
18164 return "rlwinm. %0,%1,0,%3,%4";
18165 return "rlwinm %0,%1,0,%3,%4";
18168 gcc_unreachable ();
18171 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18172 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18173 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18176 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18180 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18183 int n = GET_MODE_PRECISION (mode);
18186 if (CONST_INT_P (XEXP (shift, 1)))
18188 sh = INTVAL (XEXP (shift, 1));
18189 if (sh < 0 || sh >= n)
18193 rtx_code code = GET_CODE (shift);
18195 /* Convert any shift by 0 to a rotate, to simplify below code. */
18199 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18200 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18202 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18208 /* DImode rotates need rld*. */
18209 if (mode == DImode && code == ROTATE)
18210 return (nb == 63 || ne == 0 || ne == sh);
18212 /* SImode rotates need rlw*. */
18213 if (mode == SImode && code == ROTATE)
18214 return (nb < 32 && ne < 32 && sh < 32);
18216 /* Wrap-around masks are only okay for rotates. */
18220 /* Variable shifts are only okay for rotates. */
18224 /* Don't allow ASHIFT if the mask is wrong for that. */
18225 if (code == ASHIFT && ne < sh)
18228 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18229 if the mask is wrong for that. */
18230 if (nb < 32 && ne < 32 && sh < 32
18231 && !(code == LSHIFTRT && nb >= 32 - sh))
18234 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18235 if the mask is wrong for that. */
18236 if (code == LSHIFTRT)
18238 if (nb == 63 || ne == 0 || ne == sh)
18239 return !(code == LSHIFTRT && nb >= sh);
18244 /* Return the instruction template for a shift with mask in mode MODE, with
18245 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18248 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18252 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18253 gcc_unreachable ();
18255 if (mode == DImode && ne == 0)
18257 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18258 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18259 operands[3] = GEN_INT (63 - nb);
18261 return "rld%I2cl. %0,%1,%2,%3";
18262 return "rld%I2cl %0,%1,%2,%3";
18265 if (mode == DImode && nb == 63)
18267 operands[3] = GEN_INT (63 - ne);
18269 return "rld%I2cr. %0,%1,%2,%3";
18270 return "rld%I2cr %0,%1,%2,%3";
18274 && GET_CODE (operands[4]) != LSHIFTRT
18275 && CONST_INT_P (operands[2])
18276 && ne == INTVAL (operands[2]))
18278 operands[3] = GEN_INT (63 - nb);
18280 return "rld%I2c. %0,%1,%2,%3";
18281 return "rld%I2c %0,%1,%2,%3";
18284 if (nb < 32 && ne < 32)
18286 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18287 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18288 operands[3] = GEN_INT (31 - nb);
18289 operands[4] = GEN_INT (31 - ne);
18290 /* This insn can also be a 64-bit rotate with mask that really makes
18291 it just a shift right (with mask); the %h below are to adjust for
18292 that situation (shift count is >= 32 in that case). */
18294 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18295 return "rlw%I2nm %0,%1,%h2,%3,%4";
18298 gcc_unreachable ();
18301 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18302 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18303 ASHIFT, or LSHIFTRT) in mode MODE. */
18306 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18310 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18313 int n = GET_MODE_PRECISION (mode);
18315 int sh = INTVAL (XEXP (shift, 1));
18316 if (sh < 0 || sh >= n)
18319 rtx_code code = GET_CODE (shift);
18321 /* Convert any shift by 0 to a rotate, to simplify below code. */
18325 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18326 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18328 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18334 /* DImode rotates need rldimi. */
18335 if (mode == DImode && code == ROTATE)
18338 /* SImode rotates need rlwimi. */
18339 if (mode == SImode && code == ROTATE)
18340 return (nb < 32 && ne < 32 && sh < 32);
18342 /* Wrap-around masks are only okay for rotates. */
18346 /* Don't allow ASHIFT if the mask is wrong for that. */
18347 if (code == ASHIFT && ne < sh)
18350 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18351 if the mask is wrong for that. */
18352 if (nb < 32 && ne < 32 && sh < 32
18353 && !(code == LSHIFTRT && nb >= 32 - sh))
18356 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18357 if the mask is wrong for that. */
18358 if (code == LSHIFTRT)
18361 return !(code == LSHIFTRT && nb >= sh);
18366 /* Return the instruction template for an insert with mask in mode MODE, with
18367 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18370 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18374 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18375 gcc_unreachable ();
18377 /* Prefer rldimi because rlwimi is cracked. */
18378 if (TARGET_POWERPC64
18379 && (!dot || mode == DImode)
18380 && GET_CODE (operands[4]) != LSHIFTRT
18381 && ne == INTVAL (operands[2]))
18383 operands[3] = GEN_INT (63 - nb);
18385 return "rldimi. %0,%1,%2,%3";
18386 return "rldimi %0,%1,%2,%3";
18389 if (nb < 32 && ne < 32)
18391 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18392 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18393 operands[3] = GEN_INT (31 - nb);
18394 operands[4] = GEN_INT (31 - ne);
18396 return "rlwimi. %0,%1,%2,%3,%4";
18397 return "rlwimi %0,%1,%2,%3,%4";
18400 gcc_unreachable ();
18403 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18404 using two machine instructions. */
18407 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18409 /* There are two kinds of AND we can handle with two insns:
18410 1) those we can do with two rl* insn;
18413 We do not handle that last case yet. */
18415 /* If there is just one stretch of ones, we can do it. */
18416 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18419 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18420 one insn, we can do the whole thing with two. */
18421 unsigned HOST_WIDE_INT val = INTVAL (c);
18422 unsigned HOST_WIDE_INT bit1 = val & -val;
18423 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18424 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18425 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18426 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18429 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18430 If EXPAND is true, split rotate-and-mask instructions we generate to
18431 their constituent parts as well (this is used during expand); if DOT
18432 is 1, make the last insn a record-form instruction clobbering the
18433 destination GPR and setting the CC reg (from operands[3]); if 2, set
18434 that GPR as well as the CC reg. */
18437 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18439 gcc_assert (!(expand && dot));
18441 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18443 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18444 shift right. This generates better code than doing the masks without
18445 shifts, or shifting first right and then left. */
18447 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18449 gcc_assert (mode == DImode);
18451 int shift = 63 - nb;
18454 rtx tmp1 = gen_reg_rtx (DImode);
18455 rtx tmp2 = gen_reg_rtx (DImode);
18456 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18457 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18458 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18462 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18463 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18464 emit_move_insn (operands[0], tmp);
18465 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18466 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18471 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18472 that does the rest. */
18473 unsigned HOST_WIDE_INT bit1 = val & -val;
18474 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18475 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18476 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18478 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18479 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18481 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18483 /* Two "no-rotate"-and-mask instructions, for SImode. */
18484 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18486 gcc_assert (mode == SImode);
18488 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18489 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18490 emit_move_insn (reg, tmp);
18491 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18492 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18496 gcc_assert (mode == DImode);
18498 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18499 insns; we have to do the first in SImode, because it wraps. */
18500 if (mask2 <= 0xffffffff
18501 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18503 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18504 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18506 rtx reg_low = gen_lowpart (SImode, reg);
18507 emit_move_insn (reg_low, tmp);
18508 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18509 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18513 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18514 at the top end), rotate back and clear the other hole. */
18515 int right = exact_log2 (bit3);
18516 int left = 64 - right;
18518 /* Rotate the mask too. */
18519 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18523 rtx tmp1 = gen_reg_rtx (DImode);
18524 rtx tmp2 = gen_reg_rtx (DImode);
18525 rtx tmp3 = gen_reg_rtx (DImode);
18526 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18527 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18528 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18529 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18533 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18534 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18535 emit_move_insn (operands[0], tmp);
18536 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18537 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18538 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18542 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18543 for lfq and stfq insns iff the registers are hard registers. */
18546 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18548 /* We might have been passed a SUBREG. */
18549 if (!REG_P (reg1) || !REG_P (reg2))
18552 /* We might have been passed non floating point registers. */
18553 if (!FP_REGNO_P (REGNO (reg1))
18554 || !FP_REGNO_P (REGNO (reg2)))
18557 return (REGNO (reg1) == REGNO (reg2) - 1);
18560 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18561 addr1 and addr2 must be in consecutive memory locations
18562 (addr2 == addr1 + 8). */
18565 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18568 unsigned int reg1, reg2;
18569 int offset1, offset2;
18571 /* The mems cannot be volatile. */
18572 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18575 addr1 = XEXP (mem1, 0);
18576 addr2 = XEXP (mem2, 0);
18578 /* Extract an offset (if used) from the first addr. */
18579 if (GET_CODE (addr1) == PLUS)
18581 /* If not a REG, return zero. */
18582 if (!REG_P (XEXP (addr1, 0)))
18586 reg1 = REGNO (XEXP (addr1, 0));
18587 /* The offset must be constant! */
18588 if (!CONST_INT_P (XEXP (addr1, 1)))
18590 offset1 = INTVAL (XEXP (addr1, 1));
18593 else if (!REG_P (addr1))
18597 reg1 = REGNO (addr1);
18598 /* This was a simple (mem (reg)) expression. Offset is 0. */
18602 /* And now for the second addr. */
18603 if (GET_CODE (addr2) == PLUS)
18605 /* If not a REG, return zero. */
18606 if (!REG_P (XEXP (addr2, 0)))
18610 reg2 = REGNO (XEXP (addr2, 0));
18611 /* The offset must be constant. */
18612 if (!CONST_INT_P (XEXP (addr2, 1)))
18614 offset2 = INTVAL (XEXP (addr2, 1));
18617 else if (!REG_P (addr2))
18621 reg2 = REGNO (addr2);
18622 /* This was a simple (mem (reg)) expression. Offset is 0. */
18626 /* Both of these must have the same base register. */
18630 /* The offset for the second addr must be 8 more than the first addr. */
18631 if (offset2 != offset1 + 8)
18634 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18639 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18640 need to use DDmode, in all other cases we can use the same mode. */
18641 static machine_mode
18642 rs6000_secondary_memory_needed_mode (machine_mode mode)
18644 if (lra_in_progress && mode == SDmode)
18649 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18650 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18651 only work on the traditional altivec registers, note if an altivec register
18654 static enum rs6000_reg_type
18655 register_to_reg_type (rtx reg, bool *is_altivec)
18657 HOST_WIDE_INT regno;
18658 enum reg_class rclass;
18660 if (SUBREG_P (reg))
18661 reg = SUBREG_REG (reg);
18664 return NO_REG_TYPE;
18666 regno = REGNO (reg);
18667 if (!HARD_REGISTER_NUM_P (regno))
18669 if (!lra_in_progress && !reload_completed)
18670 return PSEUDO_REG_TYPE;
18672 regno = true_regnum (reg);
18673 if (regno < 0 || !HARD_REGISTER_NUM_P (regno))
18674 return PSEUDO_REG_TYPE;
18677 gcc_assert (regno >= 0);
18679 if (is_altivec && ALTIVEC_REGNO_P (regno))
18680 *is_altivec = true;
18682 rclass = rs6000_regno_regclass[regno];
18683 return reg_class_to_reg_type[(int)rclass];
18686 /* Helper function to return the cost of adding a TOC entry address. */
18689 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18693 if (TARGET_CMODEL != CMODEL_SMALL)
18694 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18697 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18702 /* Helper function for rs6000_secondary_reload to determine whether the memory
18703 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18704 needs reloading. Return negative if the memory is not handled by the memory
18705 helper functions and to try a different reload method, 0 if no additional
18706 instructions are need, and positive to give the extra cost for the
18710 rs6000_secondary_reload_memory (rtx addr,
18711 enum reg_class rclass,
18714 int extra_cost = 0;
18715 rtx reg, and_arg, plus_arg0, plus_arg1;
18716 addr_mask_type addr_mask;
18717 const char *type = NULL;
18718 const char *fail_msg = NULL;
18720 if (GPR_REG_CLASS_P (rclass))
18721 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18723 else if (rclass == FLOAT_REGS)
18724 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18726 else if (rclass == ALTIVEC_REGS)
18727 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18729 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18730 else if (rclass == VSX_REGS)
18731 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18732 & ~RELOAD_REG_AND_M16);
18734 /* If the register allocator hasn't made up its mind yet on the register
18735 class to use, settle on defaults to use. */
18736 else if (rclass == NO_REGS)
18738 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18739 & ~RELOAD_REG_AND_M16);
18741 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18742 addr_mask &= ~(RELOAD_REG_INDEXED
18743 | RELOAD_REG_PRE_INCDEC
18744 | RELOAD_REG_PRE_MODIFY);
18750 /* If the register isn't valid in this register class, just return now. */
18751 if ((addr_mask & RELOAD_REG_VALID) == 0)
18753 if (TARGET_DEBUG_ADDR)
18756 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18757 "not valid in class\n",
18758 GET_MODE_NAME (mode), reg_class_names[rclass]);
18765 switch (GET_CODE (addr))
18767 /* Does the register class supports auto update forms for this mode? We
18768 don't need a scratch register, since the powerpc only supports
18769 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18772 reg = XEXP (addr, 0);
18773 if (!base_reg_operand (addr, GET_MODE (reg)))
18775 fail_msg = "no base register #1";
18779 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18787 reg = XEXP (addr, 0);
18788 plus_arg1 = XEXP (addr, 1);
18789 if (!base_reg_operand (reg, GET_MODE (reg))
18790 || GET_CODE (plus_arg1) != PLUS
18791 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18793 fail_msg = "bad PRE_MODIFY";
18797 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18804 /* Do we need to simulate AND -16 to clear the bottom address bits used
18805 in VMX load/stores? Only allow the AND for vector sizes. */
18807 and_arg = XEXP (addr, 0);
18808 if (GET_MODE_SIZE (mode) != 16
18809 || !CONST_INT_P (XEXP (addr, 1))
18810 || INTVAL (XEXP (addr, 1)) != -16)
18812 fail_msg = "bad Altivec AND #1";
18816 if (rclass != ALTIVEC_REGS)
18818 if (legitimate_indirect_address_p (and_arg, false))
18821 else if (legitimate_indexed_address_p (and_arg, false))
18826 fail_msg = "bad Altivec AND #2";
18834 /* If this is an indirect address, make sure it is a base register. */
18837 if (!legitimate_indirect_address_p (addr, false))
18844 /* If this is an indexed address, make sure the register class can handle
18845 indexed addresses for this mode. */
18847 plus_arg0 = XEXP (addr, 0);
18848 plus_arg1 = XEXP (addr, 1);
18850 /* (plus (plus (reg) (constant)) (constant)) is generated during
18851 push_reload processing, so handle it now. */
18852 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18854 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18861 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18862 push_reload processing, so handle it now. */
18863 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18865 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18868 type = "indexed #2";
18872 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18874 fail_msg = "no base register #2";
18878 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18880 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18881 || !legitimate_indexed_address_p (addr, false))
18888 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18889 && CONST_INT_P (plus_arg1))
18891 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18894 type = "vector d-form offset";
18898 /* Make sure the register class can handle offset addresses. */
18899 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18901 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18904 type = "offset #2";
18910 fail_msg = "bad PLUS";
18917 /* Quad offsets are restricted and can't handle normal addresses. */
18918 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18921 type = "vector d-form lo_sum";
18924 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18926 fail_msg = "bad LO_SUM";
18930 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18937 /* Static addresses need to create a TOC entry. */
18941 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18944 type = "vector d-form lo_sum #2";
18950 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18954 /* TOC references look like offsetable memory. */
18956 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18958 fail_msg = "bad UNSPEC";
18962 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18965 type = "vector d-form lo_sum #3";
18968 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18971 type = "toc reference";
18977 fail_msg = "bad address";
18982 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
18984 if (extra_cost < 0)
18986 "rs6000_secondary_reload_memory error: mode = %s, "
18987 "class = %s, addr_mask = '%s', %s\n",
18988 GET_MODE_NAME (mode),
18989 reg_class_names[rclass],
18990 rs6000_debug_addr_mask (addr_mask, false),
18991 (fail_msg != NULL) ? fail_msg : "<bad address>");
18995 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18996 "addr_mask = '%s', extra cost = %d, %s\n",
18997 GET_MODE_NAME (mode),
18998 reg_class_names[rclass],
18999 rs6000_debug_addr_mask (addr_mask, false),
19001 (type) ? type : "<none>");
19009 /* Helper function for rs6000_secondary_reload to return true if a move to a
19010 different register classe is really a simple move. */
19013 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19014 enum rs6000_reg_type from_type,
19017 int size = GET_MODE_SIZE (mode);
19019 /* Add support for various direct moves available. In this function, we only
19020 look at cases where we don't need any extra registers, and one or more
19021 simple move insns are issued. Originally small integers are not allowed
19022 in FPR/VSX registers. Single precision binary floating is not a simple
19023 move because we need to convert to the single precision memory layout.
19024 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19025 need special direct move handling, which we do not support yet. */
19026 if (TARGET_DIRECT_MOVE
19027 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19028 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19030 if (TARGET_POWERPC64)
19032 /* ISA 2.07: MTVSRD or MVFVSRD. */
19036 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19037 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19041 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19042 if (TARGET_P8_VECTOR)
19044 if (mode == SImode)
19047 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19051 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19052 if (mode == SDmode)
19056 /* Power6+: MFTGPR or MFFGPR. */
19057 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19058 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19059 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19062 /* Move to/from SPR. */
19063 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19064 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19065 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19071 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19072 special direct moves that involve allocating an extra register, return the
19073 insn code of the helper function if there is such a function or
19074 CODE_FOR_nothing if not. */
19077 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19078 enum rs6000_reg_type from_type,
19080 secondary_reload_info *sri,
19084 enum insn_code icode = CODE_FOR_nothing;
19086 int size = GET_MODE_SIZE (mode);
19088 if (TARGET_POWERPC64 && size == 16)
19090 /* Handle moving 128-bit values from GPRs to VSX point registers on
19091 ISA 2.07 (power8, power9) when running in 64-bit mode using
19092 XXPERMDI to glue the two 64-bit values back together. */
19093 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19095 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19096 icode = reg_addr[mode].reload_vsx_gpr;
19099 /* Handle moving 128-bit values from VSX point registers to GPRs on
19100 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19101 bottom 64-bit value. */
19102 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19104 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19105 icode = reg_addr[mode].reload_gpr_vsx;
19109 else if (TARGET_POWERPC64 && mode == SFmode)
19111 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19113 cost = 3; /* xscvdpspn, mfvsrd, and. */
19114 icode = reg_addr[mode].reload_gpr_vsx;
19117 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19119 cost = 2; /* mtvsrz, xscvspdpn. */
19120 icode = reg_addr[mode].reload_vsx_gpr;
19124 else if (!TARGET_POWERPC64 && size == 8)
19126 /* Handle moving 64-bit values from GPRs to floating point registers on
19127 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19128 32-bit values back together. Altivec register classes must be handled
19129 specially since a different instruction is used, and the secondary
19130 reload support requires a single instruction class in the scratch
19131 register constraint. However, right now TFmode is not allowed in
19132 Altivec registers, so the pattern will never match. */
19133 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19135 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19136 icode = reg_addr[mode].reload_fpr_gpr;
19140 if (icode != CODE_FOR_nothing)
19145 sri->icode = icode;
19146 sri->extra_cost = cost;
19153 /* Return whether a move between two register classes can be done either
19154 directly (simple move) or via a pattern that uses a single extra temporary
19155 (using ISA 2.07's direct move in this case. */
19158 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19159 enum rs6000_reg_type from_type,
19161 secondary_reload_info *sri,
19164 /* Fall back to load/store reloads if either type is not a register. */
19165 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19168 /* If we haven't allocated registers yet, assume the move can be done for the
19169 standard register types. */
19170 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19171 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19172 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19175 /* Moves to the same set of registers is a simple move for non-specialized
19177 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19180 /* Check whether a simple move can be done directly. */
19181 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19185 sri->icode = CODE_FOR_nothing;
19186 sri->extra_cost = 0;
19191 /* Now check if we can do it in a few steps. */
19192 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19196 /* Inform reload about cases where moving X with a mode MODE to a register in
19197 RCLASS requires an extra scratch or immediate register. Return the class
19198 needed for the immediate register.
19200 For VSX and Altivec, we may need a register to convert sp+offset into
19203 For misaligned 64-bit gpr loads and stores we need a register to
19204 convert an offset address to indirect. */
19207 rs6000_secondary_reload (bool in_p,
19209 reg_class_t rclass_i,
19211 secondary_reload_info *sri)
19213 enum reg_class rclass = (enum reg_class) rclass_i;
19214 reg_class_t ret = ALL_REGS;
19215 enum insn_code icode;
19216 bool default_p = false;
19217 bool done_p = false;
19219 /* Allow subreg of memory before/during reload. */
19220 bool memory_p = (MEM_P (x)
19221 || (!reload_completed && SUBREG_P (x)
19222 && MEM_P (SUBREG_REG (x))));
19224 sri->icode = CODE_FOR_nothing;
19225 sri->t_icode = CODE_FOR_nothing;
19226 sri->extra_cost = 0;
19228 ? reg_addr[mode].reload_load
19229 : reg_addr[mode].reload_store);
19231 if (REG_P (x) || register_operand (x, mode))
19233 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19234 bool altivec_p = (rclass == ALTIVEC_REGS);
19235 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19238 std::swap (to_type, from_type);
19240 /* Can we do a direct move of some sort? */
19241 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19244 icode = (enum insn_code)sri->icode;
19251 /* Make sure 0.0 is not reloaded or forced into memory. */
19252 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19259 /* If this is a scalar floating point value and we want to load it into the
19260 traditional Altivec registers, do it via a move via a traditional floating
19261 point register, unless we have D-form addressing. Also make sure that
19262 non-zero constants use a FPR. */
19263 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19264 && !mode_supports_vmx_dform (mode)
19265 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19266 && (memory_p || CONST_DOUBLE_P (x)))
19273 /* Handle reload of load/stores if we have reload helper functions. */
19274 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19276 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19279 if (extra_cost >= 0)
19283 if (extra_cost > 0)
19285 sri->extra_cost = extra_cost;
19286 sri->icode = icode;
19291 /* Handle unaligned loads and stores of integer registers. */
19292 if (!done_p && TARGET_POWERPC64
19293 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19295 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19297 rtx addr = XEXP (x, 0);
19298 rtx off = address_offset (addr);
19300 if (off != NULL_RTX)
19302 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19303 unsigned HOST_WIDE_INT offset = INTVAL (off);
19305 /* We need a secondary reload when our legitimate_address_p
19306 says the address is good (as otherwise the entire address
19307 will be reloaded), and the offset is not a multiple of
19308 four or we have an address wrap. Address wrap will only
19309 occur for LO_SUMs since legitimate_offset_address_p
19310 rejects addresses for 16-byte mems that will wrap. */
19311 if (GET_CODE (addr) == LO_SUM
19312 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19313 && ((offset & 3) != 0
19314 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19315 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19316 && (offset & 3) != 0))
19318 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19320 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19321 : CODE_FOR_reload_di_load);
19323 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19324 : CODE_FOR_reload_di_store);
19325 sri->extra_cost = 2;
19336 if (!done_p && !TARGET_POWERPC64
19337 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19339 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19341 rtx addr = XEXP (x, 0);
19342 rtx off = address_offset (addr);
19344 if (off != NULL_RTX)
19346 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19347 unsigned HOST_WIDE_INT offset = INTVAL (off);
19349 /* We need a secondary reload when our legitimate_address_p
19350 says the address is good (as otherwise the entire address
19351 will be reloaded), and we have a wrap.
19353 legitimate_lo_sum_address_p allows LO_SUM addresses to
19354 have any offset so test for wrap in the low 16 bits.
19356 legitimate_offset_address_p checks for the range
19357 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19358 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19359 [0x7ff4,0x7fff] respectively, so test for the
19360 intersection of these ranges, [0x7ffc,0x7fff] and
19361 [0x7ff4,0x7ff7] respectively.
19363 Note that the address we see here may have been
19364 manipulated by legitimize_reload_address. */
19365 if (GET_CODE (addr) == LO_SUM
19366 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19367 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19370 sri->icode = CODE_FOR_reload_si_load;
19372 sri->icode = CODE_FOR_reload_si_store;
19373 sri->extra_cost = 2;
19388 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19390 gcc_assert (ret != ALL_REGS);
19392 if (TARGET_DEBUG_ADDR)
19395 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19397 reg_class_names[ret],
19398 in_p ? "true" : "false",
19399 reg_class_names[rclass],
19400 GET_MODE_NAME (mode));
19402 if (reload_completed)
19403 fputs (", after reload", stderr);
19406 fputs (", done_p not set", stderr);
19409 fputs (", default secondary reload", stderr);
19411 if (sri->icode != CODE_FOR_nothing)
19412 fprintf (stderr, ", reload func = %s, extra cost = %d",
19413 insn_data[sri->icode].name, sri->extra_cost);
19415 else if (sri->extra_cost > 0)
19416 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19418 fputs ("\n", stderr);
19425 /* Better tracing for rs6000_secondary_reload_inner. */
19428 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19433 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19435 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19436 store_p ? "store" : "load");
19439 set = gen_rtx_SET (mem, reg);
19441 set = gen_rtx_SET (reg, mem);
19443 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19444 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19447 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19448 ATTRIBUTE_NORETURN;
19451 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19454 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19455 gcc_unreachable ();
19458 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19459 reload helper functions. These were identified in
19460 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19461 reload, it calls the insns:
19462 reload_<RELOAD:mode>_<P:mptrsize>_store
19463 reload_<RELOAD:mode>_<P:mptrsize>_load
19465 which in turn calls this function, to do whatever is necessary to create
19466 valid addresses. */
19469 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19471 int regno = true_regnum (reg);
19472 machine_mode mode = GET_MODE (reg);
19473 addr_mask_type addr_mask;
19476 rtx op_reg, op0, op1;
19481 if (regno < 0 || !HARD_REGISTER_NUM_P (regno) || !MEM_P (mem)
19482 || !base_reg_operand (scratch, GET_MODE (scratch)))
19483 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19485 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19486 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19488 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19489 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19491 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19492 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19495 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19497 /* Make sure the mode is valid in this register class. */
19498 if ((addr_mask & RELOAD_REG_VALID) == 0)
19499 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19501 if (TARGET_DEBUG_ADDR)
19502 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19504 new_addr = addr = XEXP (mem, 0);
19505 switch (GET_CODE (addr))
19507 /* Does the register class support auto update forms for this mode? If
19508 not, do the update now. We don't need a scratch register, since the
19509 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19512 op_reg = XEXP (addr, 0);
19513 if (!base_reg_operand (op_reg, Pmode))
19514 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19516 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19518 int delta = GET_MODE_SIZE (mode);
19519 if (GET_CODE (addr) == PRE_DEC)
19521 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19527 op0 = XEXP (addr, 0);
19528 op1 = XEXP (addr, 1);
19529 if (!base_reg_operand (op0, Pmode)
19530 || GET_CODE (op1) != PLUS
19531 || !rtx_equal_p (op0, XEXP (op1, 0)))
19532 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19534 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19536 emit_insn (gen_rtx_SET (op0, op1));
19541 /* Do we need to simulate AND -16 to clear the bottom address bits used
19542 in VMX load/stores? */
19544 op0 = XEXP (addr, 0);
19545 op1 = XEXP (addr, 1);
19546 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19548 if (REG_P (op0) || SUBREG_P (op0))
19551 else if (GET_CODE (op1) == PLUS)
19553 emit_insn (gen_rtx_SET (scratch, op1));
19558 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19560 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19561 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19562 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19563 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19564 new_addr = scratch;
19568 /* If this is an indirect address, make sure it is a base register. */
19571 if (!base_reg_operand (addr, GET_MODE (addr)))
19573 emit_insn (gen_rtx_SET (scratch, addr));
19574 new_addr = scratch;
19578 /* If this is an indexed address, make sure the register class can handle
19579 indexed addresses for this mode. */
19581 op0 = XEXP (addr, 0);
19582 op1 = XEXP (addr, 1);
19583 if (!base_reg_operand (op0, Pmode))
19584 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19586 else if (int_reg_operand (op1, Pmode))
19588 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19590 emit_insn (gen_rtx_SET (scratch, addr));
19591 new_addr = scratch;
19595 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19597 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19598 || !quad_address_p (addr, mode, false))
19600 emit_insn (gen_rtx_SET (scratch, addr));
19601 new_addr = scratch;
19605 /* Make sure the register class can handle offset addresses. */
19606 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19608 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19610 emit_insn (gen_rtx_SET (scratch, addr));
19611 new_addr = scratch;
19616 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19621 op0 = XEXP (addr, 0);
19622 op1 = XEXP (addr, 1);
19623 if (!base_reg_operand (op0, Pmode))
19624 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19626 else if (int_reg_operand (op1, Pmode))
19628 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19630 emit_insn (gen_rtx_SET (scratch, addr));
19631 new_addr = scratch;
19635 /* Quad offsets are restricted and can't handle normal addresses. */
19636 else if (mode_supports_dq_form (mode))
19638 emit_insn (gen_rtx_SET (scratch, addr));
19639 new_addr = scratch;
19642 /* Make sure the register class can handle offset addresses. */
19643 else if (legitimate_lo_sum_address_p (mode, addr, false))
19645 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19647 emit_insn (gen_rtx_SET (scratch, addr));
19648 new_addr = scratch;
19653 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19660 rs6000_emit_move (scratch, addr, Pmode);
19661 new_addr = scratch;
19665 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19668 /* Adjust the address if it changed. */
19669 if (addr != new_addr)
19671 mem = replace_equiv_address_nv (mem, new_addr);
19672 if (TARGET_DEBUG_ADDR)
19673 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19676 /* Now create the move. */
19678 emit_insn (gen_rtx_SET (mem, reg));
19680 emit_insn (gen_rtx_SET (reg, mem));
19685 /* Convert reloads involving 64-bit gprs and misaligned offset
19686 addressing, or multiple 32-bit gprs and offsets that are too large,
19687 to use indirect addressing. */
19690 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19692 int regno = true_regnum (reg);
19693 enum reg_class rclass;
19695 rtx scratch_or_premodify = scratch;
19697 if (TARGET_DEBUG_ADDR)
19699 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19700 store_p ? "store" : "load");
19701 fprintf (stderr, "reg:\n");
19703 fprintf (stderr, "mem:\n");
19705 fprintf (stderr, "scratch:\n");
19706 debug_rtx (scratch);
19709 gcc_assert (regno >= 0 && HARD_REGISTER_NUM_P (regno));
19710 gcc_assert (MEM_P (mem));
19711 rclass = REGNO_REG_CLASS (regno);
19712 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19713 addr = XEXP (mem, 0);
19715 if (GET_CODE (addr) == PRE_MODIFY)
19717 gcc_assert (REG_P (XEXP (addr, 0))
19718 && GET_CODE (XEXP (addr, 1)) == PLUS
19719 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19720 scratch_or_premodify = XEXP (addr, 0);
19721 addr = XEXP (addr, 1);
19723 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19725 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19727 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19729 /* Now create the move. */
19731 emit_insn (gen_rtx_SET (mem, reg));
19733 emit_insn (gen_rtx_SET (reg, mem));
19738 /* Given an rtx X being reloaded into a reg required to be
19739 in class CLASS, return the class of reg to actually use.
19740 In general this is just CLASS; but on some machines
19741 in some cases it is preferable to use a more restrictive class.
19743 On the RS/6000, we have to return NO_REGS when we want to reload a
19744 floating-point CONST_DOUBLE to force it to be copied to memory.
19746 We also don't want to reload integer values into floating-point
19747 registers if we can at all help it. In fact, this can
19748 cause reload to die, if it tries to generate a reload of CTR
19749 into a FP register and discovers it doesn't have the memory location
19752 ??? Would it be a good idea to have reload do the converse, that is
19753 try to reload floating modes into FP registers if possible?
19756 static enum reg_class
19757 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19759 machine_mode mode = GET_MODE (x);
19760 bool is_constant = CONSTANT_P (x);
19762 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19763 reload class for it. */
19764 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19765 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19768 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19769 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19772 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19773 the reloading of address expressions using PLUS into floating point
19775 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19779 /* Zero is always allowed in all VSX registers. */
19780 if (x == CONST0_RTX (mode))
19783 /* If this is a vector constant that can be formed with a few Altivec
19784 instructions, we want altivec registers. */
19785 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19786 return ALTIVEC_REGS;
19788 /* If this is an integer constant that can easily be loaded into
19789 vector registers, allow it. */
19790 if (CONST_INT_P (x))
19792 HOST_WIDE_INT value = INTVAL (x);
19794 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19795 2.06 can generate it in the Altivec registers with
19799 if (TARGET_P8_VECTOR)
19801 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19802 return ALTIVEC_REGS;
19807 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19808 a sign extend in the Altivec registers. */
19809 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19810 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19811 return ALTIVEC_REGS;
19814 /* Force constant to memory. */
19818 /* D-form addressing can easily reload the value. */
19819 if (mode_supports_vmx_dform (mode)
19820 || mode_supports_dq_form (mode))
19823 /* If this is a scalar floating point value and we don't have D-form
19824 addressing, prefer the traditional floating point registers so that we
19825 can use D-form (register+offset) addressing. */
19826 if (rclass == VSX_REGS
19827 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19830 /* Prefer the Altivec registers if Altivec is handling the vector
19831 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19833 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19834 || mode == V1TImode)
19835 return ALTIVEC_REGS;
19840 if (is_constant || GET_CODE (x) == PLUS)
19842 if (reg_class_subset_p (GENERAL_REGS, rclass))
19843 return GENERAL_REGS;
19844 if (reg_class_subset_p (BASE_REGS, rclass))
19849 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
19850 return GENERAL_REGS;
19855 /* Debug version of rs6000_preferred_reload_class. */
19856 static enum reg_class
19857 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19859 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19862 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19864 reg_class_names[ret], reg_class_names[rclass],
19865 GET_MODE_NAME (GET_MODE (x)));
19871 /* If we are copying between FP or AltiVec registers and anything else, we need
19872 a memory location. The exception is when we are targeting ppc64 and the
19873 move to/from fpr to gpr instructions are available. Also, under VSX, you
19874 can copy vector registers from the FP register set to the Altivec register
19875 set and vice versa. */
19878 rs6000_secondary_memory_needed (machine_mode mode,
19879 reg_class_t from_class,
19880 reg_class_t to_class)
19882 enum rs6000_reg_type from_type, to_type;
19883 bool altivec_p = ((from_class == ALTIVEC_REGS)
19884 || (to_class == ALTIVEC_REGS));
19886 /* If a simple/direct move is available, we don't need secondary memory */
19887 from_type = reg_class_to_reg_type[(int)from_class];
19888 to_type = reg_class_to_reg_type[(int)to_class];
19890 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19891 (secondary_reload_info *)0, altivec_p))
19894 /* If we have a floating point or vector register class, we need to use
19895 memory to transfer the data. */
19896 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19902 /* Debug version of rs6000_secondary_memory_needed. */
19904 rs6000_debug_secondary_memory_needed (machine_mode mode,
19905 reg_class_t from_class,
19906 reg_class_t to_class)
19908 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19911 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19912 "to_class = %s, mode = %s\n",
19913 ret ? "true" : "false",
19914 reg_class_names[from_class],
19915 reg_class_names[to_class],
19916 GET_MODE_NAME (mode));
19921 /* Return the register class of a scratch register needed to copy IN into
19922 or out of a register in RCLASS in MODE. If it can be done directly,
19923 NO_REGS is returned. */
19925 static enum reg_class
19926 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19931 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19933 && MACHOPIC_INDIRECT
19937 /* We cannot copy a symbolic operand directly into anything
19938 other than BASE_REGS for TARGET_ELF. So indicate that a
19939 register from BASE_REGS is needed as an intermediate
19942 On Darwin, pic addresses require a load from memory, which
19943 needs a base register. */
19944 if (rclass != BASE_REGS
19945 && (SYMBOL_REF_P (in)
19946 || GET_CODE (in) == HIGH
19947 || GET_CODE (in) == LABEL_REF
19948 || GET_CODE (in) == CONST))
19954 regno = REGNO (in);
19955 if (!HARD_REGISTER_NUM_P (regno))
19957 regno = true_regnum (in);
19958 if (!HARD_REGISTER_NUM_P (regno))
19962 else if (SUBREG_P (in))
19964 regno = true_regnum (in);
19965 if (!HARD_REGISTER_NUM_P (regno))
19971 /* If we have VSX register moves, prefer moving scalar values between
19972 Altivec registers and GPR by going via an FPR (and then via memory)
19973 instead of reloading the secondary memory address for Altivec moves. */
19975 && GET_MODE_SIZE (mode) < 16
19976 && !mode_supports_vmx_dform (mode)
19977 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
19978 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
19979 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19980 && (regno >= 0 && INT_REGNO_P (regno)))))
19983 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
19985 if (rclass == GENERAL_REGS || rclass == BASE_REGS
19986 || (regno >= 0 && INT_REGNO_P (regno)))
19989 /* Constants, memory, and VSX registers can go into VSX registers (both the
19990 traditional floating point and the altivec registers). */
19991 if (rclass == VSX_REGS
19992 && (regno == -1 || VSX_REGNO_P (regno)))
19995 /* Constants, memory, and FP registers can go into FP registers. */
19996 if ((regno == -1 || FP_REGNO_P (regno))
19997 && (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
19998 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20000 /* Memory, and AltiVec registers can go into AltiVec registers. */
20001 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20002 && rclass == ALTIVEC_REGS)
20005 /* We can copy among the CR registers. */
20006 if ((rclass == CR_REGS || rclass == CR0_REGS)
20007 && regno >= 0 && CR_REGNO_P (regno))
20010 /* Otherwise, we need GENERAL_REGS. */
20011 return GENERAL_REGS;
20014 /* Debug version of rs6000_secondary_reload_class. */
20015 static enum reg_class
20016 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20017 machine_mode mode, rtx in)
20019 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20021 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20022 "mode = %s, input rtx:\n",
20023 reg_class_names[ret], reg_class_names[rclass],
20024 GET_MODE_NAME (mode));
20030 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20033 rs6000_can_change_mode_class (machine_mode from,
20035 reg_class_t rclass)
20037 unsigned from_size = GET_MODE_SIZE (from);
20038 unsigned to_size = GET_MODE_SIZE (to);
20040 if (from_size != to_size)
20042 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20044 if (reg_classes_intersect_p (xclass, rclass))
20046 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20047 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20048 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20049 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20051 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20052 single register under VSX because the scalar part of the register
20053 is in the upper 64-bits, and not the lower 64-bits. Types like
20054 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20055 IEEE floating point can't overlap, and neither can small
20058 if (to_float128_vector_p && from_float128_vector_p)
20061 else if (to_float128_vector_p || from_float128_vector_p)
20064 /* TDmode in floating-mode registers must always go into a register
20065 pair with the most significant word in the even-numbered register
20066 to match ISA requirements. In little-endian mode, this does not
20067 match subreg numbering, so we cannot allow subregs. */
20068 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20071 if (from_size < 8 || to_size < 8)
20074 if (from_size == 8 && (8 * to_nregs) != to_size)
20077 if (to_size == 8 && (8 * from_nregs) != from_size)
20086 /* Since the VSX register set includes traditional floating point registers
20087 and altivec registers, just check for the size being different instead of
20088 trying to check whether the modes are vector modes. Otherwise it won't
20089 allow say DF and DI to change classes. For types like TFmode and TDmode
20090 that take 2 64-bit registers, rather than a single 128-bit register, don't
20091 allow subregs of those types to other 128 bit types. */
20092 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20094 unsigned num_regs = (from_size + 15) / 16;
20095 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20096 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20099 return (from_size == 8 || from_size == 16);
20102 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20103 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20109 /* Debug version of rs6000_can_change_mode_class. */
20111 rs6000_debug_can_change_mode_class (machine_mode from,
20113 reg_class_t rclass)
20115 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20118 "rs6000_can_change_mode_class, return %s, from = %s, "
20119 "to = %s, rclass = %s\n",
20120 ret ? "true" : "false",
20121 GET_MODE_NAME (from), GET_MODE_NAME (to),
20122 reg_class_names[rclass]);
20127 /* Return a string to do a move operation of 128 bits of data. */
20130 rs6000_output_move_128bit (rtx operands[])
20132 rtx dest = operands[0];
20133 rtx src = operands[1];
20134 machine_mode mode = GET_MODE (dest);
20137 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20138 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20142 dest_regno = REGNO (dest);
20143 dest_gpr_p = INT_REGNO_P (dest_regno);
20144 dest_fp_p = FP_REGNO_P (dest_regno);
20145 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20146 dest_vsx_p = dest_fp_p | dest_vmx_p;
20151 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20156 src_regno = REGNO (src);
20157 src_gpr_p = INT_REGNO_P (src_regno);
20158 src_fp_p = FP_REGNO_P (src_regno);
20159 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20160 src_vsx_p = src_fp_p | src_vmx_p;
20165 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20168 /* Register moves. */
20169 if (dest_regno >= 0 && src_regno >= 0)
20176 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20177 return (WORDS_BIG_ENDIAN
20178 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20179 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20181 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20185 else if (TARGET_VSX && dest_vsx_p)
20188 return "xxlor %x0,%x1,%x1";
20190 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20191 return (WORDS_BIG_ENDIAN
20192 ? "mtvsrdd %x0,%1,%L1"
20193 : "mtvsrdd %x0,%L1,%1");
20195 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20199 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20200 return "vor %0,%1,%1";
20202 else if (dest_fp_p && src_fp_p)
20207 else if (dest_regno >= 0 && MEM_P (src))
20211 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20217 else if (TARGET_ALTIVEC && dest_vmx_p
20218 && altivec_indexed_or_indirect_operand (src, mode))
20219 return "lvx %0,%y1";
20221 else if (TARGET_VSX && dest_vsx_p)
20223 if (mode_supports_dq_form (mode)
20224 && quad_address_p (XEXP (src, 0), mode, true))
20225 return "lxv %x0,%1";
20227 else if (TARGET_P9_VECTOR)
20228 return "lxvx %x0,%y1";
20230 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20231 return "lxvw4x %x0,%y1";
20234 return "lxvd2x %x0,%y1";
20237 else if (TARGET_ALTIVEC && dest_vmx_p)
20238 return "lvx %0,%y1";
20240 else if (dest_fp_p)
20245 else if (src_regno >= 0 && MEM_P (dest))
20249 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20250 return "stq %1,%0";
20255 else if (TARGET_ALTIVEC && src_vmx_p
20256 && altivec_indexed_or_indirect_operand (dest, mode))
20257 return "stvx %1,%y0";
20259 else if (TARGET_VSX && src_vsx_p)
20261 if (mode_supports_dq_form (mode)
20262 && quad_address_p (XEXP (dest, 0), mode, true))
20263 return "stxv %x1,%0";
20265 else if (TARGET_P9_VECTOR)
20266 return "stxvx %x1,%y0";
20268 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20269 return "stxvw4x %x1,%y0";
20272 return "stxvd2x %x1,%y0";
20275 else if (TARGET_ALTIVEC && src_vmx_p)
20276 return "stvx %1,%y0";
20283 else if (dest_regno >= 0
20284 && (CONST_INT_P (src)
20285 || CONST_WIDE_INT_P (src)
20286 || CONST_DOUBLE_P (src)
20287 || GET_CODE (src) == CONST_VECTOR))
20292 else if ((dest_vmx_p && TARGET_ALTIVEC)
20293 || (dest_vsx_p && TARGET_VSX))
20294 return output_vec_const_move (operands);
20297 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20300 /* Validate a 128-bit move. */
20302 rs6000_move_128bit_ok_p (rtx operands[])
20304 machine_mode mode = GET_MODE (operands[0]);
20305 return (gpc_reg_operand (operands[0], mode)
20306 || gpc_reg_operand (operands[1], mode));
20309 /* Return true if a 128-bit move needs to be split. */
20311 rs6000_split_128bit_ok_p (rtx operands[])
20313 if (!reload_completed)
20316 if (!gpr_or_gpr_p (operands[0], operands[1]))
20319 if (quad_load_store_p (operands[0], operands[1]))
20326 /* Given a comparison operation, return the bit number in CCR to test. We
20327 know this is a valid comparison.
20329 SCC_P is 1 if this is for an scc. That means that %D will have been
20330 used instead of %C, so the bits will be in different places.
20332 Return -1 if OP isn't a valid comparison for some reason. */
20335 ccr_bit (rtx op, int scc_p)
20337 enum rtx_code code = GET_CODE (op);
20338 machine_mode cc_mode;
20343 if (!COMPARISON_P (op))
20346 reg = XEXP (op, 0);
20348 if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg)))
20351 cc_mode = GET_MODE (reg);
20352 cc_regnum = REGNO (reg);
20353 base_bit = 4 * (cc_regnum - CR0_REGNO);
20355 validate_condition_mode (code, cc_mode);
20357 /* When generating a sCOND operation, only positive conditions are
20376 return scc_p ? base_bit + 3 : base_bit + 2;
20378 return base_bit + 2;
20379 case GT: case GTU: case UNLE:
20380 return base_bit + 1;
20381 case LT: case LTU: case UNGE:
20383 case ORDERED: case UNORDERED:
20384 return base_bit + 3;
20387 /* If scc, we will have done a cror to put the bit in the
20388 unordered position. So test that bit. For integer, this is ! LT
20389 unless this is an scc insn. */
20390 return scc_p ? base_bit + 3 : base_bit;
20393 return scc_p ? base_bit + 3 : base_bit + 1;
20400 /* Return the GOT register. */
20403 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20405 /* The second flow pass currently (June 1999) can't update
20406 regs_ever_live without disturbing other parts of the compiler, so
20407 update it here to make the prolog/epilogue code happy. */
20408 if (!can_create_pseudo_p ()
20409 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20410 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20412 crtl->uses_pic_offset_table = 1;
20414 return pic_offset_table_rtx;
20417 static rs6000_stack_t stack_info;
20419 /* Function to init struct machine_function.
20420 This will be called, via a pointer variable,
20421 from push_function_context. */
20423 static struct machine_function *
20424 rs6000_init_machine_status (void)
20426 stack_info.reload_completed = 0;
20427 return ggc_cleared_alloc<machine_function> ();
20430 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20432 /* Write out a function code label. */
20435 rs6000_output_function_entry (FILE *file, const char *fname)
20437 if (fname[0] != '.')
20439 switch (DEFAULT_ABI)
20442 gcc_unreachable ();
20448 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20458 RS6000_OUTPUT_BASENAME (file, fname);
20461 /* Print an operand. Recognize special options, documented below. */
20464 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20465 only introduced by the linker, when applying the sda21
20467 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20468 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20470 #define SMALL_DATA_RELOC "sda21"
20471 #define SMALL_DATA_REG 0
20475 print_operand (FILE *file, rtx x, int code)
20478 unsigned HOST_WIDE_INT uval;
20482 /* %a is output_address. */
20484 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20488 /* Like 'J' but get to the GT bit only. */
20489 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20491 output_operand_lossage ("invalid %%D value");
20495 /* Bit 1 is GT bit. */
20496 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20498 /* Add one for shift count in rlinm for scc. */
20499 fprintf (file, "%d", i + 1);
20503 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20506 output_operand_lossage ("invalid %%e value");
20511 if ((uval & 0xffff) == 0 && uval != 0)
20516 /* X is a CR register. Print the number of the EQ bit of the CR */
20517 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20518 output_operand_lossage ("invalid %%E value");
20520 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20524 /* X is a CR register. Print the shift count needed to move it
20525 to the high-order four bits. */
20526 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20527 output_operand_lossage ("invalid %%f value");
20529 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20533 /* Similar, but print the count for the rotate in the opposite
20535 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20536 output_operand_lossage ("invalid %%F value");
20538 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20542 /* X is a constant integer. If it is negative, print "m",
20543 otherwise print "z". This is to make an aze or ame insn. */
20544 if (!CONST_INT_P (x))
20545 output_operand_lossage ("invalid %%G value");
20546 else if (INTVAL (x) >= 0)
20553 /* If constant, output low-order five bits. Otherwise, write
20556 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20558 print_operand (file, x, 0);
20562 /* If constant, output low-order six bits. Otherwise, write
20565 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20567 print_operand (file, x, 0);
20571 /* Print `i' if this is a constant, else nothing. */
20577 /* Write the bit number in CCR for jump. */
20578 i = ccr_bit (x, 0);
20580 output_operand_lossage ("invalid %%j code");
20582 fprintf (file, "%d", i);
20586 /* Similar, but add one for shift count in rlinm for scc and pass
20587 scc flag to `ccr_bit'. */
20588 i = ccr_bit (x, 1);
20590 output_operand_lossage ("invalid %%J code");
20592 /* If we want bit 31, write a shift count of zero, not 32. */
20593 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20597 /* X must be a constant. Write the 1's complement of the
20600 output_operand_lossage ("invalid %%k value");
20602 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20606 /* X must be a symbolic constant on ELF. Write an
20607 expression suitable for an 'addi' that adds in the low 16
20608 bits of the MEM. */
20609 if (GET_CODE (x) == CONST)
20611 if (GET_CODE (XEXP (x, 0)) != PLUS
20612 || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
20613 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20614 || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20615 output_operand_lossage ("invalid %%K value");
20617 print_operand_address (file, x);
20618 fputs ("@l", file);
20621 /* %l is output_asm_label. */
20624 /* Write second word of DImode or DFmode reference. Works on register
20625 or non-indexed memory only. */
20627 fputs (reg_names[REGNO (x) + 1], file);
20628 else if (MEM_P (x))
20630 machine_mode mode = GET_MODE (x);
20631 /* Handle possible auto-increment. Since it is pre-increment and
20632 we have already done it, we can just use an offset of word. */
20633 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20634 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20635 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20637 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20638 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20641 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20645 if (small_data_operand (x, GET_MODE (x)))
20646 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20647 reg_names[SMALL_DATA_REG]);
20651 case 'N': /* Unused */
20652 /* Write the number of elements in the vector times 4. */
20653 if (GET_CODE (x) != PARALLEL)
20654 output_operand_lossage ("invalid %%N value");
20656 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20659 case 'O': /* Unused */
20660 /* Similar, but subtract 1 first. */
20661 if (GET_CODE (x) != PARALLEL)
20662 output_operand_lossage ("invalid %%O value");
20664 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20668 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20671 || (i = exact_log2 (INTVAL (x))) < 0)
20672 output_operand_lossage ("invalid %%p value");
20674 fprintf (file, "%d", i);
20678 /* The operand must be an indirect memory reference. The result
20679 is the register name. */
20680 if (!MEM_P (x) || !REG_P (XEXP (x, 0))
20681 || REGNO (XEXP (x, 0)) >= 32)
20682 output_operand_lossage ("invalid %%P value");
20684 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20688 /* This outputs the logical code corresponding to a boolean
20689 expression. The expression may have one or both operands
20690 negated (if one, only the first one). For condition register
20691 logical operations, it will also treat the negated
20692 CR codes as NOTs, but not handle NOTs of them. */
20694 const char *const *t = 0;
20696 enum rtx_code code = GET_CODE (x);
20697 static const char * const tbl[3][3] = {
20698 { "and", "andc", "nor" },
20699 { "or", "orc", "nand" },
20700 { "xor", "eqv", "xor" } };
20704 else if (code == IOR)
20706 else if (code == XOR)
20709 output_operand_lossage ("invalid %%q value");
20711 if (GET_CODE (XEXP (x, 0)) != NOT)
20715 if (GET_CODE (XEXP (x, 1)) == NOT)
20726 if (! TARGET_MFCRF)
20732 /* X is a CR register. Print the mask for `mtcrf'. */
20733 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20734 output_operand_lossage ("invalid %%R value");
20736 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20740 /* Low 5 bits of 32 - value */
20742 output_operand_lossage ("invalid %%s value");
20744 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20748 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20749 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20751 output_operand_lossage ("invalid %%t value");
20755 /* Bit 3 is OV bit. */
20756 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20758 /* If we want bit 31, write a shift count of zero, not 32. */
20759 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20763 /* Print the symbolic name of a branch target register. */
20764 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20765 x = XVECEXP (x, 0, 0);
20766 if (!REG_P (x) || (REGNO (x) != LR_REGNO
20767 && REGNO (x) != CTR_REGNO))
20768 output_operand_lossage ("invalid %%T value");
20769 else if (REGNO (x) == LR_REGNO)
20770 fputs ("lr", file);
20772 fputs ("ctr", file);
20776 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20777 for use in unsigned operand. */
20780 output_operand_lossage ("invalid %%u value");
20785 if ((uval & 0xffff) == 0)
20788 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20792 /* High-order 16 bits of constant for use in signed operand. */
20794 output_operand_lossage ("invalid %%v value");
20796 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20797 (INTVAL (x) >> 16) & 0xffff);
20801 /* Print `u' if this has an auto-increment or auto-decrement. */
20803 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20804 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20805 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20810 /* Print the trap code for this operand. */
20811 switch (GET_CODE (x))
20814 fputs ("eq", file); /* 4 */
20817 fputs ("ne", file); /* 24 */
20820 fputs ("lt", file); /* 16 */
20823 fputs ("le", file); /* 20 */
20826 fputs ("gt", file); /* 8 */
20829 fputs ("ge", file); /* 12 */
20832 fputs ("llt", file); /* 2 */
20835 fputs ("lle", file); /* 6 */
20838 fputs ("lgt", file); /* 1 */
20841 fputs ("lge", file); /* 5 */
20844 output_operand_lossage ("invalid %%V value");
20849 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20852 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20853 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20855 print_operand (file, x, 0);
20859 /* X is a FPR or Altivec register used in a VSX context. */
20860 if (!REG_P (x) || !VSX_REGNO_P (REGNO (x)))
20861 output_operand_lossage ("invalid %%x value");
20864 int reg = REGNO (x);
20865 int vsx_reg = (FP_REGNO_P (reg)
20867 : reg - FIRST_ALTIVEC_REGNO + 32);
20869 #ifdef TARGET_REGNAMES
20870 if (TARGET_REGNAMES)
20871 fprintf (file, "%%vs%d", vsx_reg);
20874 fprintf (file, "%d", vsx_reg);
20880 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20881 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20882 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20887 /* Like 'L', for third word of TImode/PTImode */
20889 fputs (reg_names[REGNO (x) + 2], file);
20890 else if (MEM_P (x))
20892 machine_mode mode = GET_MODE (x);
20893 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20894 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20895 output_address (mode, plus_constant (Pmode,
20896 XEXP (XEXP (x, 0), 0), 8));
20897 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20898 output_address (mode, plus_constant (Pmode,
20899 XEXP (XEXP (x, 0), 0), 8));
20901 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20902 if (small_data_operand (x, GET_MODE (x)))
20903 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20904 reg_names[SMALL_DATA_REG]);
20909 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20910 x = XVECEXP (x, 0, 1);
20911 /* X is a SYMBOL_REF. Write out the name preceded by a
20912 period and without any trailing data in brackets. Used for function
20913 names. If we are configured for System V (or the embedded ABI) on
20914 the PowerPC, do not emit the period, since those systems do not use
20915 TOCs and the like. */
20916 if (!SYMBOL_REF_P (x))
20918 output_operand_lossage ("invalid %%z value");
20922 /* For macho, check to see if we need a stub. */
20925 const char *name = XSTR (x, 0);
20927 if (darwin_emit_branch_islands
20928 && MACHOPIC_INDIRECT
20929 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20930 name = machopic_indirection_name (x, /*stub_p=*/true);
20932 assemble_name (file, name);
20934 else if (!DOT_SYMBOLS)
20935 assemble_name (file, XSTR (x, 0));
20937 rs6000_output_function_entry (file, XSTR (x, 0));
20941 /* Like 'L', for last word of TImode/PTImode. */
20943 fputs (reg_names[REGNO (x) + 3], file);
20944 else if (MEM_P (x))
20946 machine_mode mode = GET_MODE (x);
20947 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20948 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20949 output_address (mode, plus_constant (Pmode,
20950 XEXP (XEXP (x, 0), 0), 12));
20951 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20952 output_address (mode, plus_constant (Pmode,
20953 XEXP (XEXP (x, 0), 0), 12));
20955 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20956 if (small_data_operand (x, GET_MODE (x)))
20957 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20958 reg_names[SMALL_DATA_REG]);
20962 /* Print AltiVec memory operand. */
20967 gcc_assert (MEM_P (x));
20971 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20972 && GET_CODE (tmp) == AND
20973 && CONST_INT_P (XEXP (tmp, 1))
20974 && INTVAL (XEXP (tmp, 1)) == -16)
20975 tmp = XEXP (tmp, 0);
20976 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20977 && GET_CODE (tmp) == PRE_MODIFY)
20978 tmp = XEXP (tmp, 1);
20980 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
20983 if (GET_CODE (tmp) != PLUS
20984 || !REG_P (XEXP (tmp, 0))
20985 || !REG_P (XEXP (tmp, 1)))
20987 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20991 if (REGNO (XEXP (tmp, 0)) == 0)
20992 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
20993 reg_names[ REGNO (XEXP (tmp, 0)) ]);
20995 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
20996 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21003 fprintf (file, "%s", reg_names[REGNO (x)]);
21004 else if (MEM_P (x))
21006 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21007 know the width from the mode. */
21008 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21009 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21010 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21011 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21012 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21013 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21014 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21015 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21017 output_address (GET_MODE (x), XEXP (x, 0));
21019 else if (toc_relative_expr_p (x, false,
21020 &tocrel_base_oac, &tocrel_offset_oac))
21021 /* This hack along with a corresponding hack in
21022 rs6000_output_addr_const_extra arranges to output addends
21023 where the assembler expects to find them. eg.
21024 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21025 without this hack would be output as "x@toc+4". We
21027 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21028 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
21029 output_addr_const (file, XVECEXP (x, 0, 0));
21030 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
21031 output_addr_const (file, XVECEXP (x, 0, 1));
21033 output_addr_const (file, x);
21037 if (const char *name = get_some_local_dynamic_name ())
21038 assemble_name (file, name);
21040 output_operand_lossage ("'%%&' used without any "
21041 "local dynamic TLS references");
21045 output_operand_lossage ("invalid %%xn code");
21049 /* Print the address of an operand. */
21052 print_operand_address (FILE *file, rtx x)
21055 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21056 else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
21057 || GET_CODE (x) == LABEL_REF)
21059 output_addr_const (file, x);
21060 if (small_data_operand (x, GET_MODE (x)))
21061 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21062 reg_names[SMALL_DATA_REG]);
21064 gcc_assert (!TARGET_TOC);
21066 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21067 && REG_P (XEXP (x, 1)))
21069 if (REGNO (XEXP (x, 0)) == 0)
21070 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21071 reg_names[ REGNO (XEXP (x, 0)) ]);
21073 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21074 reg_names[ REGNO (XEXP (x, 1)) ]);
21076 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21077 && CONST_INT_P (XEXP (x, 1)))
21078 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21079 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21081 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21082 && CONSTANT_P (XEXP (x, 1)))
21084 fprintf (file, "lo16(");
21085 output_addr_const (file, XEXP (x, 1));
21086 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21090 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21091 && CONSTANT_P (XEXP (x, 1)))
21093 output_addr_const (file, XEXP (x, 1));
21094 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21097 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21099 /* This hack along with a corresponding hack in
21100 rs6000_output_addr_const_extra arranges to output addends
21101 where the assembler expects to find them. eg.
21103 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21104 without this hack would be output as "x@toc+8@l(9)". We
21105 want "x+8@toc@l(9)". */
21106 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21107 if (GET_CODE (x) == LO_SUM)
21108 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21110 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21113 output_addr_const (file, x);
21116 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21119 rs6000_output_addr_const_extra (FILE *file, rtx x)
21121 if (GET_CODE (x) == UNSPEC)
21122 switch (XINT (x, 1))
21124 case UNSPEC_TOCREL:
21125 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x, 0, 0))
21126 && REG_P (XVECEXP (x, 0, 1))
21127 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21128 output_addr_const (file, XVECEXP (x, 0, 0));
21129 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21131 if (INTVAL (tocrel_offset_oac) >= 0)
21132 fprintf (file, "+");
21133 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21135 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21138 assemble_name (file, toc_label_name);
21141 else if (TARGET_ELF)
21142 fputs ("@toc", file);
21146 case UNSPEC_MACHOPIC_OFFSET:
21147 output_addr_const (file, XVECEXP (x, 0, 0));
21149 machopic_output_function_base_name (file);
21156 /* Target hook for assembling integer objects. The PowerPC version has
21157 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21158 is defined. It also needs to handle DI-mode objects on 64-bit
21162 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21164 #ifdef RELOCATABLE_NEEDS_FIXUP
21165 /* Special handling for SI values. */
21166 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21168 static int recurse = 0;
21170 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21171 the .fixup section. Since the TOC section is already relocated, we
21172 don't need to mark it here. We used to skip the text section, but it
21173 should never be valid for relocated addresses to be placed in the text
21175 if (DEFAULT_ABI == ABI_V4
21176 && (TARGET_RELOCATABLE || flag_pic > 1)
21177 && in_section != toc_section
21179 && !CONST_SCALAR_INT_P (x)
21185 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21187 ASM_OUTPUT_LABEL (asm_out_file, buf);
21188 fprintf (asm_out_file, "\t.long\t(");
21189 output_addr_const (asm_out_file, x);
21190 fprintf (asm_out_file, ")@fixup\n");
21191 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21192 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21193 fprintf (asm_out_file, "\t.long\t");
21194 assemble_name (asm_out_file, buf);
21195 fprintf (asm_out_file, "\n\t.previous\n");
21199 /* Remove initial .'s to turn a -mcall-aixdesc function
21200 address into the address of the descriptor, not the function
21202 else if (SYMBOL_REF_P (x)
21203 && XSTR (x, 0)[0] == '.'
21204 && DEFAULT_ABI == ABI_AIX)
21206 const char *name = XSTR (x, 0);
21207 while (*name == '.')
21210 fprintf (asm_out_file, "\t.long\t%s\n", name);
21214 #endif /* RELOCATABLE_NEEDS_FIXUP */
21215 return default_assemble_integer (x, size, aligned_p);
21218 /* Return a template string for assembly to emit when making an
21219 external call. FUNOP is the call mem argument operand number. */
21221 static const char *
21222 rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
21224 /* -Wformat-overflow workaround, without which gcc thinks that %u
21225 might produce 10 digits. */
21226 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21230 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21232 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21233 sprintf (arg, "(%%%u@tlsgd)", funop + 1);
21234 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21235 sprintf (arg, "(%%&@tlsld)");
21237 gcc_unreachable ();
21240 /* The magic 32768 offset here corresponds to the offset of
21241 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21243 sprintf (z, "%%z%u%s", funop,
21244 (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == 2
21247 static char str[32]; /* 2 spare */
21248 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21249 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21250 sibcall ? "" : "\n\tnop");
21251 else if (DEFAULT_ABI == ABI_V4)
21252 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21253 flag_pic ? "@plt" : "");
21255 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21256 else if (DEFAULT_ABI == ABI_DARWIN)
21258 /* The cookie is in operand func+2. */
21259 gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
21260 int cookie = INTVAL (operands[funop + 2]);
21261 if (cookie & CALL_LONG)
21263 tree funname = get_identifier (XSTR (operands[funop], 0));
21264 tree labelname = get_prev_label (funname);
21265 gcc_checking_assert (labelname && !sibcall);
21267 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21268 instruction will reach 'foo', otherwise link as 'bl L42'".
21269 "L42" should be a 'branch island', that will do a far jump to
21270 'foo'. Branch islands are generated in
21271 macho_branch_islands(). */
21272 sprintf (str, "jbsr %%z%u,%.10s", funop,
21273 IDENTIFIER_POINTER (labelname));
21276 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21278 sprintf (str, "b%s %s%s", sibcall ? "" : "l", z, arg);
21282 gcc_unreachable ();
21287 rs6000_call_template (rtx *operands, unsigned int funop)
21289 return rs6000_call_template_1 (operands, funop, false);
21293 rs6000_sibcall_template (rtx *operands, unsigned int funop)
21295 return rs6000_call_template_1 (operands, funop, true);
21298 /* As above, for indirect calls. */
21300 static const char *
21301 rs6000_indirect_call_template_1 (rtx *operands, unsigned int funop,
21304 /* -Wformat-overflow workaround, without which gcc thinks that %u
21305 might produce 10 digits. Note that -Wformat-overflow will not
21306 currently warn here for str[], so do not rely on a warning to
21307 ensure str[] is correctly sized. */
21308 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21310 /* Currently, funop is either 0 or 1. The maximum string is always
21311 a !speculate 64-bit __tls_get_addr call.
21315 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21316 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21318 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21319 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21326 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21327 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21329 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21330 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21337 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21338 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21340 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21341 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21345 static char str[160]; /* 8 spare */
21347 const char *ptrload = TARGET_64BIT ? "d" : "wz";
21349 if (DEFAULT_ABI == ABI_AIX)
21352 ptrload, funop + 2);
21354 /* We don't need the extra code to stop indirect call speculation if
21356 bool speculate = (TARGET_MACHO
21357 || rs6000_speculate_indirect_jumps
21358 || (REG_P (operands[funop])
21359 && REGNO (operands[funop]) == LR_REGNO));
21361 if (TARGET_PLTSEQ && GET_CODE (operands[funop]) == UNSPEC)
21363 const char *rel64 = TARGET_64BIT ? "64" : "";
21366 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21368 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21369 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21371 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21372 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21375 gcc_unreachable ();
21378 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21379 && flag_pic == 2 ? "+32768" : "");
21383 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21384 tls, rel64, funop, addend);
21385 s += sprintf (s, "crset 2\n\t");
21388 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21389 tls, rel64, funop, addend);
21391 else if (!speculate)
21392 s += sprintf (s, "crset 2\n\t");
21394 if (DEFAULT_ABI == ABI_AIX)
21400 funop, ptrload, funop + 3);
21405 funop, ptrload, funop + 3);
21407 else if (DEFAULT_ABI == ABI_ELFv2)
21413 funop, ptrload, funop + 2);
21418 funop, ptrload, funop + 2);
21425 funop, sibcall ? "" : "l");
21429 funop, sibcall ? "" : "l", sibcall ? "\n\tb $" : "");
21435 rs6000_indirect_call_template (rtx *operands, unsigned int funop)
21437 return rs6000_indirect_call_template_1 (operands, funop, false);
21441 rs6000_indirect_sibcall_template (rtx *operands, unsigned int funop)
21443 return rs6000_indirect_call_template_1 (operands, funop, true);
21447 /* Output indirect call insns.
21448 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21450 rs6000_pltseq_template (rtx *operands, int which)
21452 const char *rel64 = TARGET_64BIT ? "64" : "";
21455 if (TARGET_TLS_MARKERS && GET_CODE (operands[3]) == UNSPEC)
21457 if (XINT (operands[3], 1) == UNSPEC_TLSGD)
21458 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21460 else if (XINT (operands[3], 1) == UNSPEC_TLSLD)
21461 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21464 gcc_unreachable ();
21467 gcc_assert (DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4);
21468 static char str[96]; /* 15 spare */
21469 const char *off = WORDS_BIG_ENDIAN ? "+2" : "";
21470 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21471 && flag_pic == 2 ? "+32768" : "");
21476 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21478 tls, rel64, TARGET_64BIT ? "d 2,24(1)" : "w 2,12(1)");
21481 if (DEFAULT_ABI == ABI_V4 && !flag_pic)
21483 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21488 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21490 tls, off, rel64, addend);
21494 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21496 tls, off, rel64, TARGET_64BIT ? "_DS" : "", addend,
21497 TARGET_64BIT ? "d" : "wz");
21501 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21503 tls, rel64, addend);
21506 gcc_unreachable ();
21512 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21513 /* Emit an assembler directive to set symbol visibility for DECL to
21514 VISIBILITY_TYPE. */
21517 rs6000_assemble_visibility (tree decl, int vis)
21522 /* Functions need to have their entry point symbol visibility set as
21523 well as their descriptor symbol visibility. */
21524 if (DEFAULT_ABI == ABI_AIX
21526 && TREE_CODE (decl) == FUNCTION_DECL)
21528 static const char * const visibility_types[] = {
21529 NULL, "protected", "hidden", "internal"
21532 const char *name, *type;
21534 name = ((* targetm.strip_name_encoding)
21535 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21536 type = visibility_types[vis];
21538 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21539 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21542 default_assemble_visibility (decl, vis);
21547 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21549 /* Reversal of FP compares takes care -- an ordered compare
21550 becomes an unordered compare and vice versa. */
21551 if (mode == CCFPmode
21552 && (!flag_finite_math_only
21553 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21554 || code == UNEQ || code == LTGT))
21555 return reverse_condition_maybe_unordered (code);
21557 return reverse_condition (code);
21560 /* Generate a compare for CODE. Return a brand-new rtx that
21561 represents the result of the compare. */
21564 rs6000_generate_compare (rtx cmp, machine_mode mode)
21566 machine_mode comp_mode;
21567 rtx compare_result;
21568 enum rtx_code code = GET_CODE (cmp);
21569 rtx op0 = XEXP (cmp, 0);
21570 rtx op1 = XEXP (cmp, 1);
21572 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21573 comp_mode = CCmode;
21574 else if (FLOAT_MODE_P (mode))
21575 comp_mode = CCFPmode;
21576 else if (code == GTU || code == LTU
21577 || code == GEU || code == LEU)
21578 comp_mode = CCUNSmode;
21579 else if ((code == EQ || code == NE)
21580 && unsigned_reg_p (op0)
21581 && (unsigned_reg_p (op1)
21582 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21583 /* These are unsigned values, perhaps there will be a later
21584 ordering compare that can be shared with this one. */
21585 comp_mode = CCUNSmode;
21587 comp_mode = CCmode;
21589 /* If we have an unsigned compare, make sure we don't have a signed value as
21591 if (comp_mode == CCUNSmode && CONST_INT_P (op1)
21592 && INTVAL (op1) < 0)
21594 op0 = copy_rtx_if_shared (op0);
21595 op1 = force_reg (GET_MODE (op0), op1);
21596 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21599 /* First, the compare. */
21600 compare_result = gen_reg_rtx (comp_mode);
21602 /* IEEE 128-bit support in VSX registers when we do not have hardware
21604 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21606 rtx libfunc = NULL_RTX;
21607 bool check_nan = false;
21614 libfunc = optab_libfunc (eq_optab, mode);
21619 libfunc = optab_libfunc (ge_optab, mode);
21624 libfunc = optab_libfunc (le_optab, mode);
21629 libfunc = optab_libfunc (unord_optab, mode);
21630 code = (code == UNORDERED) ? NE : EQ;
21636 libfunc = optab_libfunc (ge_optab, mode);
21637 code = (code == UNGE) ? GE : GT;
21643 libfunc = optab_libfunc (le_optab, mode);
21644 code = (code == UNLE) ? LE : LT;
21650 libfunc = optab_libfunc (eq_optab, mode);
21651 code = (code = UNEQ) ? EQ : NE;
21655 gcc_unreachable ();
21658 gcc_assert (libfunc);
21661 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21662 SImode, op0, mode, op1, mode);
21664 /* The library signals an exception for signalling NaNs, so we need to
21665 handle isgreater, etc. by first checking isordered. */
21668 rtx ne_rtx, normal_dest, unord_dest;
21669 rtx unord_func = optab_libfunc (unord_optab, mode);
21670 rtx join_label = gen_label_rtx ();
21671 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21672 rtx unord_cmp = gen_reg_rtx (comp_mode);
21675 /* Test for either value being a NaN. */
21676 gcc_assert (unord_func);
21677 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21678 SImode, op0, mode, op1, mode);
21680 /* Set value (0) if either value is a NaN, and jump to the join
21682 dest = gen_reg_rtx (SImode);
21683 emit_move_insn (dest, const1_rtx);
21684 emit_insn (gen_rtx_SET (unord_cmp,
21685 gen_rtx_COMPARE (comp_mode, unord_dest,
21688 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21689 emit_jump_insn (gen_rtx_SET (pc_rtx,
21690 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21694 /* Do the normal comparison, knowing that the values are not
21696 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21697 SImode, op0, mode, op1, mode);
21699 emit_insn (gen_cstoresi4 (dest,
21700 gen_rtx_fmt_ee (code, SImode, normal_dest,
21702 normal_dest, const0_rtx));
21704 /* Join NaN and non-Nan paths. Compare dest against 0. */
21705 emit_label (join_label);
21709 emit_insn (gen_rtx_SET (compare_result,
21710 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21715 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21716 CLOBBERs to match cmptf_internal2 pattern. */
21717 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21718 && FLOAT128_IBM_P (GET_MODE (op0))
21719 && TARGET_HARD_FLOAT)
21720 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21722 gen_rtx_SET (compare_result,
21723 gen_rtx_COMPARE (comp_mode, op0, op1)),
21724 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21725 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21726 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21727 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21728 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21729 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21730 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21731 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21732 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21733 else if (GET_CODE (op1) == UNSPEC
21734 && XINT (op1, 1) == UNSPEC_SP_TEST)
21736 rtx op1b = XVECEXP (op1, 0, 0);
21737 comp_mode = CCEQmode;
21738 compare_result = gen_reg_rtx (CCEQmode);
21740 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21742 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21745 emit_insn (gen_rtx_SET (compare_result,
21746 gen_rtx_COMPARE (comp_mode, op0, op1)));
21749 /* Some kinds of FP comparisons need an OR operation;
21750 under flag_finite_math_only we don't bother. */
21751 if (FLOAT_MODE_P (mode)
21752 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21753 && !flag_finite_math_only
21754 && (code == LE || code == GE
21755 || code == UNEQ || code == LTGT
21756 || code == UNGT || code == UNLT))
21758 enum rtx_code or1, or2;
21759 rtx or1_rtx, or2_rtx, compare2_rtx;
21760 rtx or_result = gen_reg_rtx (CCEQmode);
21764 case LE: or1 = LT; or2 = EQ; break;
21765 case GE: or1 = GT; or2 = EQ; break;
21766 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21767 case LTGT: or1 = LT; or2 = GT; break;
21768 case UNGT: or1 = UNORDERED; or2 = GT; break;
21769 case UNLT: or1 = UNORDERED; or2 = LT; break;
21770 default: gcc_unreachable ();
21772 validate_condition_mode (or1, comp_mode);
21773 validate_condition_mode (or2, comp_mode);
21774 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21775 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21776 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21777 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21779 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21781 compare_result = or_result;
21785 validate_condition_mode (code, GET_MODE (compare_result));
21787 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21791 /* Return the diagnostic message string if the binary operation OP is
21792 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21795 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21799 machine_mode mode1 = TYPE_MODE (type1);
21800 machine_mode mode2 = TYPE_MODE (type2);
21802 /* For complex modes, use the inner type. */
21803 if (COMPLEX_MODE_P (mode1))
21804 mode1 = GET_MODE_INNER (mode1);
21806 if (COMPLEX_MODE_P (mode2))
21807 mode2 = GET_MODE_INNER (mode2);
21809 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21810 double to intermix unless -mfloat128-convert. */
21811 if (mode1 == mode2)
21814 if (!TARGET_FLOAT128_CVT)
21816 if ((mode1 == KFmode && mode2 == IFmode)
21817 || (mode1 == IFmode && mode2 == KFmode))
21818 return N_("__float128 and __ibm128 cannot be used in the same "
21821 if (TARGET_IEEEQUAD
21822 && ((mode1 == IFmode && mode2 == TFmode)
21823 || (mode1 == TFmode && mode2 == IFmode)))
21824 return N_("__ibm128 and long double cannot be used in the same "
21827 if (!TARGET_IEEEQUAD
21828 && ((mode1 == KFmode && mode2 == TFmode)
21829 || (mode1 == TFmode && mode2 == KFmode)))
21830 return N_("__float128 and long double cannot be used in the same "
21838 /* Expand floating point conversion to/from __float128 and __ibm128. */
21841 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21843 machine_mode dest_mode = GET_MODE (dest);
21844 machine_mode src_mode = GET_MODE (src);
21845 convert_optab cvt = unknown_optab;
21846 bool do_move = false;
21847 rtx libfunc = NULL_RTX;
21849 typedef rtx (*rtx_2func_t) (rtx, rtx);
21850 rtx_2func_t hw_convert = (rtx_2func_t)0;
21854 rtx_2func_t from_df;
21855 rtx_2func_t from_sf;
21856 rtx_2func_t from_si_sign;
21857 rtx_2func_t from_si_uns;
21858 rtx_2func_t from_di_sign;
21859 rtx_2func_t from_di_uns;
21862 rtx_2func_t to_si_sign;
21863 rtx_2func_t to_si_uns;
21864 rtx_2func_t to_di_sign;
21865 rtx_2func_t to_di_uns;
21866 } hw_conversions[2] = {
21867 /* convertions to/from KFmode */
21869 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21870 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21871 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21872 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21873 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21874 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21875 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21876 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21877 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21878 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21879 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21880 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21883 /* convertions to/from TFmode */
21885 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21886 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21887 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21888 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21889 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21890 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21891 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21892 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21893 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21894 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21895 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21896 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21900 if (dest_mode == src_mode)
21901 gcc_unreachable ();
21903 /* Eliminate memory operations. */
21905 src = force_reg (src_mode, src);
21909 rtx tmp = gen_reg_rtx (dest_mode);
21910 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21911 rs6000_emit_move (dest, tmp, dest_mode);
21915 /* Convert to IEEE 128-bit floating point. */
21916 if (FLOAT128_IEEE_P (dest_mode))
21918 if (dest_mode == KFmode)
21920 else if (dest_mode == TFmode)
21923 gcc_unreachable ();
21929 hw_convert = hw_conversions[kf_or_tf].from_df;
21934 hw_convert = hw_conversions[kf_or_tf].from_sf;
21940 if (FLOAT128_IBM_P (src_mode))
21949 cvt = ufloat_optab;
21950 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21954 cvt = sfloat_optab;
21955 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21962 cvt = ufloat_optab;
21963 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21967 cvt = sfloat_optab;
21968 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21973 gcc_unreachable ();
21977 /* Convert from IEEE 128-bit floating point. */
21978 else if (FLOAT128_IEEE_P (src_mode))
21980 if (src_mode == KFmode)
21982 else if (src_mode == TFmode)
21985 gcc_unreachable ();
21991 hw_convert = hw_conversions[kf_or_tf].to_df;
21996 hw_convert = hw_conversions[kf_or_tf].to_sf;
22002 if (FLOAT128_IBM_P (dest_mode))
22012 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22017 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22025 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22030 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22035 gcc_unreachable ();
22039 /* Both IBM format. */
22040 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22044 gcc_unreachable ();
22046 /* Handle conversion between TFmode/KFmode/IFmode. */
22048 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
22050 /* Handle conversion if we have hardware support. */
22051 else if (TARGET_FLOAT128_HW && hw_convert)
22052 emit_insn ((hw_convert) (dest, src));
22054 /* Call an external function to do the conversion. */
22055 else if (cvt != unknown_optab)
22057 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22058 gcc_assert (libfunc != NULL_RTX);
22060 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22063 gcc_assert (dest2 != NULL_RTX);
22064 if (!rtx_equal_p (dest, dest2))
22065 emit_move_insn (dest, dest2);
22069 gcc_unreachable ();
22075 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22076 can be used as that dest register. Return the dest register. */
22079 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22081 if (op2 == const0_rtx)
22084 if (GET_CODE (scratch) == SCRATCH)
22085 scratch = gen_reg_rtx (mode);
22087 if (logical_operand (op2, mode))
22088 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22090 emit_insn (gen_rtx_SET (scratch,
22091 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22097 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22100 machine_mode op_mode;
22101 enum rtx_code cond_code;
22102 rtx result = operands[0];
22104 condition_rtx = rs6000_generate_compare (operands[1], mode);
22105 cond_code = GET_CODE (condition_rtx);
22107 if (cond_code == NE
22108 || cond_code == GE || cond_code == LE
22109 || cond_code == GEU || cond_code == LEU
22110 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22112 rtx not_result = gen_reg_rtx (CCEQmode);
22113 rtx not_op, rev_cond_rtx;
22114 machine_mode cc_mode;
22116 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22118 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22119 SImode, XEXP (condition_rtx, 0), const0_rtx);
22120 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22121 emit_insn (gen_rtx_SET (not_result, not_op));
22122 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22125 op_mode = GET_MODE (XEXP (operands[1], 0));
22126 if (op_mode == VOIDmode)
22127 op_mode = GET_MODE (XEXP (operands[1], 1));
22129 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22131 PUT_MODE (condition_rtx, DImode);
22132 convert_move (result, condition_rtx, 0);
22136 PUT_MODE (condition_rtx, SImode);
22137 emit_insn (gen_rtx_SET (result, condition_rtx));
22141 /* Emit a branch of kind CODE to location LOC. */
22144 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22146 rtx condition_rtx, loc_ref;
22148 condition_rtx = rs6000_generate_compare (operands[0], mode);
22149 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22150 emit_jump_insn (gen_rtx_SET (pc_rtx,
22151 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22152 loc_ref, pc_rtx)));
22155 /* Return the string to output a conditional branch to LABEL, which is
22156 the operand template of the label, or NULL if the branch is really a
22157 conditional return.
22159 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22160 condition code register and its mode specifies what kind of
22161 comparison we made.
22163 REVERSED is nonzero if we should reverse the sense of the comparison.
22165 INSN is the insn. */
22168 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22170 static char string[64];
22171 enum rtx_code code = GET_CODE (op);
22172 rtx cc_reg = XEXP (op, 0);
22173 machine_mode mode = GET_MODE (cc_reg);
22174 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22175 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22176 int really_reversed = reversed ^ need_longbranch;
22182 validate_condition_mode (code, mode);
22184 /* Work out which way this really branches. We could use
22185 reverse_condition_maybe_unordered here always but this
22186 makes the resulting assembler clearer. */
22187 if (really_reversed)
22189 /* Reversal of FP compares takes care -- an ordered compare
22190 becomes an unordered compare and vice versa. */
22191 if (mode == CCFPmode)
22192 code = reverse_condition_maybe_unordered (code);
22194 code = reverse_condition (code);
22199 /* Not all of these are actually distinct opcodes, but
22200 we distinguish them for clarity of the resulting assembler. */
22201 case NE: case LTGT:
22202 ccode = "ne"; break;
22203 case EQ: case UNEQ:
22204 ccode = "eq"; break;
22206 ccode = "ge"; break;
22207 case GT: case GTU: case UNGT:
22208 ccode = "gt"; break;
22210 ccode = "le"; break;
22211 case LT: case LTU: case UNLT:
22212 ccode = "lt"; break;
22213 case UNORDERED: ccode = "un"; break;
22214 case ORDERED: ccode = "nu"; break;
22215 case UNGE: ccode = "nl"; break;
22216 case UNLE: ccode = "ng"; break;
22218 gcc_unreachable ();
22221 /* Maybe we have a guess as to how likely the branch is. */
22223 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22224 if (note != NULL_RTX)
22226 /* PROB is the difference from 50%. */
22227 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22228 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22230 /* Only hint for highly probable/improbable branches on newer cpus when
22231 we have real profile data, as static prediction overrides processor
22232 dynamic prediction. For older cpus we may as well always hint, but
22233 assume not taken for branches that are very close to 50% as a
22234 mispredicted taken branch is more expensive than a
22235 mispredicted not-taken branch. */
22236 if (rs6000_always_hint
22237 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22238 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22239 && br_prob_note_reliable_p (note)))
22241 if (abs (prob) > REG_BR_PROB_BASE / 20
22242 && ((prob > 0) ^ need_longbranch))
22250 s += sprintf (s, "b%slr%s ", ccode, pred);
22252 s += sprintf (s, "b%s%s ", ccode, pred);
22254 /* We need to escape any '%' characters in the reg_names string.
22255 Assume they'd only be the first character.... */
22256 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22258 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22262 /* If the branch distance was too far, we may have to use an
22263 unconditional branch to go the distance. */
22264 if (need_longbranch)
22265 s += sprintf (s, ",$+8\n\tb %s", label);
22267 s += sprintf (s, ",%s", label);
22273 /* Return insn for VSX or Altivec comparisons. */
22276 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22279 machine_mode mode = GET_MODE (op0);
22287 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22298 mask = gen_reg_rtx (mode);
22299 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22306 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22307 DMODE is expected destination mode. This is a recursive function. */
22310 rs6000_emit_vector_compare (enum rtx_code rcode,
22312 machine_mode dmode)
22315 bool swap_operands = false;
22316 bool try_again = false;
22318 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22319 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22321 /* See if the comparison works as is. */
22322 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22330 swap_operands = true;
22335 swap_operands = true;
22343 /* Invert condition and try again.
22344 e.g., A != B becomes ~(A==B). */
22346 enum rtx_code rev_code;
22347 enum insn_code nor_code;
22350 rev_code = reverse_condition_maybe_unordered (rcode);
22351 if (rev_code == UNKNOWN)
22354 nor_code = optab_handler (one_cmpl_optab, dmode);
22355 if (nor_code == CODE_FOR_nothing)
22358 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22362 mask = gen_reg_rtx (dmode);
22363 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22371 /* Try GT/GTU/LT/LTU OR EQ */
22374 enum insn_code ior_code;
22375 enum rtx_code new_code;
22396 gcc_unreachable ();
22399 ior_code = optab_handler (ior_optab, dmode);
22400 if (ior_code == CODE_FOR_nothing)
22403 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22407 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22411 mask = gen_reg_rtx (dmode);
22412 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22423 std::swap (op0, op1);
22425 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22430 /* You only get two chances. */
22434 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22435 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22436 operands for the relation operation COND. */
22439 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22440 rtx cond, rtx cc_op0, rtx cc_op1)
22442 machine_mode dest_mode = GET_MODE (dest);
22443 machine_mode mask_mode = GET_MODE (cc_op0);
22444 enum rtx_code rcode = GET_CODE (cond);
22445 machine_mode cc_mode = CCmode;
22448 bool invert_move = false;
22450 if (VECTOR_UNIT_NONE_P (dest_mode))
22453 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22454 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22458 /* Swap operands if we can, and fall back to doing the operation as
22459 specified, and doing a NOR to invert the test. */
22465 /* Invert condition and try again.
22466 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22467 invert_move = true;
22468 rcode = reverse_condition_maybe_unordered (rcode);
22469 if (rcode == UNKNOWN)
22475 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22477 /* Invert condition to avoid compound test. */
22478 invert_move = true;
22479 rcode = reverse_condition (rcode);
22487 /* Mark unsigned tests with CCUNSmode. */
22488 cc_mode = CCUNSmode;
22490 /* Invert condition to avoid compound test if necessary. */
22491 if (rcode == GEU || rcode == LEU)
22493 invert_move = true;
22494 rcode = reverse_condition (rcode);
22502 /* Get the vector mask for the given relational operations. */
22503 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22509 std::swap (op_true, op_false);
22511 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22512 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22513 && (GET_CODE (op_true) == CONST_VECTOR
22514 || GET_CODE (op_false) == CONST_VECTOR))
22516 rtx constant_0 = CONST0_RTX (dest_mode);
22517 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22519 if (op_true == constant_m1 && op_false == constant_0)
22521 emit_move_insn (dest, mask);
22525 else if (op_true == constant_0 && op_false == constant_m1)
22527 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22531 /* If we can't use the vector comparison directly, perhaps we can use
22532 the mask for the true or false fields, instead of loading up a
22534 if (op_true == constant_m1)
22537 if (op_false == constant_0)
22541 if (!REG_P (op_true) && !SUBREG_P (op_true))
22542 op_true = force_reg (dest_mode, op_true);
22544 if (!REG_P (op_false) && !SUBREG_P (op_false))
22545 op_false = force_reg (dest_mode, op_false);
22547 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22548 CONST0_RTX (dest_mode));
22549 emit_insn (gen_rtx_SET (dest,
22550 gen_rtx_IF_THEN_ELSE (dest_mode,
22557 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22558 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22559 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22560 hardware has no such operation. */
22563 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22565 enum rtx_code code = GET_CODE (op);
22566 rtx op0 = XEXP (op, 0);
22567 rtx op1 = XEXP (op, 1);
22568 machine_mode compare_mode = GET_MODE (op0);
22569 machine_mode result_mode = GET_MODE (dest);
22570 bool max_p = false;
22572 if (result_mode != compare_mode)
22575 if (code == GE || code == GT)
22577 else if (code == LE || code == LT)
22582 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22585 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22591 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22595 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22596 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22597 operands of the last comparison is nonzero/true, FALSE_COND if it is
22598 zero/false. Return 0 if the hardware has no such operation. */
22601 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22603 enum rtx_code code = GET_CODE (op);
22604 rtx op0 = XEXP (op, 0);
22605 rtx op1 = XEXP (op, 1);
22606 machine_mode result_mode = GET_MODE (dest);
22611 if (!can_create_pseudo_p ())
22624 code = swap_condition (code);
22625 std::swap (op0, op1);
22632 /* Generate: [(parallel [(set (dest)
22633 (if_then_else (op (cmp1) (cmp2))
22636 (clobber (scratch))])]. */
22638 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22639 cmove_rtx = gen_rtx_SET (dest,
22640 gen_rtx_IF_THEN_ELSE (result_mode,
22645 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22646 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22647 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22652 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22653 operands of the last comparison is nonzero/true, FALSE_COND if it
22654 is zero/false. Return 0 if the hardware has no such operation. */
22657 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22659 enum rtx_code code = GET_CODE (op);
22660 rtx op0 = XEXP (op, 0);
22661 rtx op1 = XEXP (op, 1);
22662 machine_mode compare_mode = GET_MODE (op0);
22663 machine_mode result_mode = GET_MODE (dest);
22665 bool is_against_zero;
22667 /* These modes should always match. */
22668 if (GET_MODE (op1) != compare_mode
22669 /* In the isel case however, we can use a compare immediate, so
22670 op1 may be a small constant. */
22671 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22673 if (GET_MODE (true_cond) != result_mode)
22675 if (GET_MODE (false_cond) != result_mode)
22678 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22679 if (TARGET_P9_MINMAX
22680 && (compare_mode == SFmode || compare_mode == DFmode)
22681 && (result_mode == SFmode || result_mode == DFmode))
22683 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22686 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22690 /* Don't allow using floating point comparisons for integer results for
22692 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22695 /* First, work out if the hardware can do this at all, or
22696 if it's too slow.... */
22697 if (!FLOAT_MODE_P (compare_mode))
22700 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22704 is_against_zero = op1 == CONST0_RTX (compare_mode);
22706 /* A floating-point subtract might overflow, underflow, or produce
22707 an inexact result, thus changing the floating-point flags, so it
22708 can't be generated if we care about that. It's safe if one side
22709 of the construct is zero, since then no subtract will be
22711 if (SCALAR_FLOAT_MODE_P (compare_mode)
22712 && flag_trapping_math && ! is_against_zero)
22715 /* Eliminate half of the comparisons by switching operands, this
22716 makes the remaining code simpler. */
22717 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22718 || code == LTGT || code == LT || code == UNLE)
22720 code = reverse_condition_maybe_unordered (code);
22722 true_cond = false_cond;
22726 /* UNEQ and LTGT take four instructions for a comparison with zero,
22727 it'll probably be faster to use a branch here too. */
22728 if (code == UNEQ && HONOR_NANS (compare_mode))
22731 /* We're going to try to implement comparisons by performing
22732 a subtract, then comparing against zero. Unfortunately,
22733 Inf - Inf is NaN which is not zero, and so if we don't
22734 know that the operand is finite and the comparison
22735 would treat EQ different to UNORDERED, we can't do it. */
22736 if (HONOR_INFINITIES (compare_mode)
22737 && code != GT && code != UNGE
22738 && (!CONST_DOUBLE_P (op1)
22739 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22740 /* Constructs of the form (a OP b ? a : b) are safe. */
22741 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22742 || (! rtx_equal_p (op0, true_cond)
22743 && ! rtx_equal_p (op1, true_cond))))
22746 /* At this point we know we can use fsel. */
22748 /* Reduce the comparison to a comparison against zero. */
22749 if (! is_against_zero)
22751 temp = gen_reg_rtx (compare_mode);
22752 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22754 op1 = CONST0_RTX (compare_mode);
22757 /* If we don't care about NaNs we can reduce some of the comparisons
22758 down to faster ones. */
22759 if (! HONOR_NANS (compare_mode))
22765 true_cond = false_cond;
22778 /* Now, reduce everything down to a GE. */
22785 temp = gen_reg_rtx (compare_mode);
22786 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22791 temp = gen_reg_rtx (compare_mode);
22792 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22797 temp = gen_reg_rtx (compare_mode);
22798 emit_insn (gen_rtx_SET (temp,
22799 gen_rtx_NEG (compare_mode,
22800 gen_rtx_ABS (compare_mode, op0))));
22805 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22806 temp = gen_reg_rtx (result_mode);
22807 emit_insn (gen_rtx_SET (temp,
22808 gen_rtx_IF_THEN_ELSE (result_mode,
22809 gen_rtx_GE (VOIDmode,
22811 true_cond, false_cond)));
22812 false_cond = true_cond;
22815 temp = gen_reg_rtx (compare_mode);
22816 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22821 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22822 temp = gen_reg_rtx (result_mode);
22823 emit_insn (gen_rtx_SET (temp,
22824 gen_rtx_IF_THEN_ELSE (result_mode,
22825 gen_rtx_GE (VOIDmode,
22827 true_cond, false_cond)));
22828 true_cond = false_cond;
22831 temp = gen_reg_rtx (compare_mode);
22832 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22837 gcc_unreachable ();
22840 emit_insn (gen_rtx_SET (dest,
22841 gen_rtx_IF_THEN_ELSE (result_mode,
22842 gen_rtx_GE (VOIDmode,
22844 true_cond, false_cond)));
22848 /* Same as above, but for ints (isel). */
22851 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22853 rtx condition_rtx, cr;
22854 machine_mode mode = GET_MODE (dest);
22855 enum rtx_code cond_code;
22856 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22859 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22862 /* We still have to do the compare, because isel doesn't do a
22863 compare, it just looks at the CRx bits set by a previous compare
22865 condition_rtx = rs6000_generate_compare (op, mode);
22866 cond_code = GET_CODE (condition_rtx);
22867 cr = XEXP (condition_rtx, 0);
22868 signedp = GET_MODE (cr) == CCmode;
22870 isel_func = (mode == SImode
22871 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22872 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22876 case LT: case GT: case LTU: case GTU: case EQ:
22877 /* isel handles these directly. */
22881 /* We need to swap the sense of the comparison. */
22883 std::swap (false_cond, true_cond);
22884 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22889 false_cond = force_reg (mode, false_cond);
22890 if (true_cond != const0_rtx)
22891 true_cond = force_reg (mode, true_cond);
22893 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22899 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22901 machine_mode mode = GET_MODE (op0);
22905 /* VSX/altivec have direct min/max insns. */
22906 if ((code == SMAX || code == SMIN)
22907 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22908 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22910 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22914 if (code == SMAX || code == SMIN)
22919 if (code == SMAX || code == UMAX)
22920 target = emit_conditional_move (dest, c, op0, op1, mode,
22921 op0, op1, mode, 0);
22923 target = emit_conditional_move (dest, c, op0, op1, mode,
22924 op1, op0, mode, 0);
22925 gcc_assert (target);
22926 if (target != dest)
22927 emit_move_insn (dest, target);
22930 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22931 COND is true. Mark the jump as unlikely to be taken. */
22934 emit_unlikely_jump (rtx cond, rtx label)
22936 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22937 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22938 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22941 /* A subroutine of the atomic operation splitters. Emit a load-locked
22942 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22943 the zero_extend operation. */
22946 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22948 rtx (*fn) (rtx, rtx) = NULL;
22953 fn = gen_load_lockedqi;
22956 fn = gen_load_lockedhi;
22959 if (GET_MODE (mem) == QImode)
22960 fn = gen_load_lockedqi_si;
22961 else if (GET_MODE (mem) == HImode)
22962 fn = gen_load_lockedhi_si;
22964 fn = gen_load_lockedsi;
22967 fn = gen_load_lockeddi;
22970 fn = gen_load_lockedti;
22973 gcc_unreachable ();
22975 emit_insn (fn (reg, mem));
22978 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22979 instruction in MODE. */
22982 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
22984 rtx (*fn) (rtx, rtx, rtx) = NULL;
22989 fn = gen_store_conditionalqi;
22992 fn = gen_store_conditionalhi;
22995 fn = gen_store_conditionalsi;
22998 fn = gen_store_conditionaldi;
23001 fn = gen_store_conditionalti;
23004 gcc_unreachable ();
23007 /* Emit sync before stwcx. to address PPC405 Erratum. */
23008 if (PPC405_ERRATUM77)
23009 emit_insn (gen_hwsync ());
23011 emit_insn (fn (res, mem, val));
23014 /* Expand barriers before and after a load_locked/store_cond sequence. */
23017 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23019 rtx addr = XEXP (mem, 0);
23021 if (!legitimate_indirect_address_p (addr, reload_completed)
23022 && !legitimate_indexed_address_p (addr, reload_completed))
23024 addr = force_reg (Pmode, addr);
23025 mem = replace_equiv_address_nv (mem, addr);
23030 case MEMMODEL_RELAXED:
23031 case MEMMODEL_CONSUME:
23032 case MEMMODEL_ACQUIRE:
23034 case MEMMODEL_RELEASE:
23035 case MEMMODEL_ACQ_REL:
23036 emit_insn (gen_lwsync ());
23038 case MEMMODEL_SEQ_CST:
23039 emit_insn (gen_hwsync ());
23042 gcc_unreachable ();
23048 rs6000_post_atomic_barrier (enum memmodel model)
23052 case MEMMODEL_RELAXED:
23053 case MEMMODEL_CONSUME:
23054 case MEMMODEL_RELEASE:
23056 case MEMMODEL_ACQUIRE:
23057 case MEMMODEL_ACQ_REL:
23058 case MEMMODEL_SEQ_CST:
23059 emit_insn (gen_isync ());
23062 gcc_unreachable ();
23066 /* A subroutine of the various atomic expanders. For sub-word operations,
23067 we must adjust things to operate on SImode. Given the original MEM,
23068 return a new aligned memory. Also build and return the quantities by
23069 which to shift and mask. */
23072 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23074 rtx addr, align, shift, mask, mem;
23075 HOST_WIDE_INT shift_mask;
23076 machine_mode mode = GET_MODE (orig_mem);
23078 /* For smaller modes, we have to implement this via SImode. */
23079 shift_mask = (mode == QImode ? 0x18 : 0x10);
23081 addr = XEXP (orig_mem, 0);
23082 addr = force_reg (GET_MODE (addr), addr);
23084 /* Aligned memory containing subword. Generate a new memory. We
23085 do not want any of the existing MEM_ATTR data, as we're now
23086 accessing memory outside the original object. */
23087 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23088 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23089 mem = gen_rtx_MEM (SImode, align);
23090 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23091 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23092 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23094 /* Shift amount for subword relative to aligned word. */
23095 shift = gen_reg_rtx (SImode);
23096 addr = gen_lowpart (SImode, addr);
23097 rtx tmp = gen_reg_rtx (SImode);
23098 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23099 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23100 if (BYTES_BIG_ENDIAN)
23101 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23102 shift, 1, OPTAB_LIB_WIDEN);
23105 /* Mask for insertion. */
23106 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23107 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23113 /* A subroutine of the various atomic expanders. For sub-word operands,
23114 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23117 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23121 x = gen_reg_rtx (SImode);
23122 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23123 gen_rtx_NOT (SImode, mask),
23126 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23131 /* A subroutine of the various atomic expanders. For sub-word operands,
23132 extract WIDE to NARROW via SHIFT. */
23135 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23137 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23138 wide, 1, OPTAB_LIB_WIDEN);
23139 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23142 /* Expand an atomic compare and swap operation. */
23145 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23147 rtx boolval, retval, mem, oldval, newval, cond;
23148 rtx label1, label2, x, mask, shift;
23149 machine_mode mode, orig_mode;
23150 enum memmodel mod_s, mod_f;
23153 boolval = operands[0];
23154 retval = operands[1];
23156 oldval = operands[3];
23157 newval = operands[4];
23158 is_weak = (INTVAL (operands[5]) != 0);
23159 mod_s = memmodel_base (INTVAL (operands[6]));
23160 mod_f = memmodel_base (INTVAL (operands[7]));
23161 orig_mode = mode = GET_MODE (mem);
23163 mask = shift = NULL_RTX;
23164 if (mode == QImode || mode == HImode)
23166 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23167 lwarx and shift/mask operations. With power8, we need to do the
23168 comparison in SImode, but the store is still done in QI/HImode. */
23169 oldval = convert_modes (SImode, mode, oldval, 1);
23171 if (!TARGET_SYNC_HI_QI)
23173 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23175 /* Shift and mask OLDVAL into position with the word. */
23176 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23177 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23179 /* Shift and mask NEWVAL into position within the word. */
23180 newval = convert_modes (SImode, mode, newval, 1);
23181 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23182 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23185 /* Prepare to adjust the return value. */
23186 retval = gen_reg_rtx (SImode);
23189 else if (reg_overlap_mentioned_p (retval, oldval))
23190 oldval = copy_to_reg (oldval);
23192 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23193 oldval = copy_to_mode_reg (mode, oldval);
23195 if (reg_overlap_mentioned_p (retval, newval))
23196 newval = copy_to_reg (newval);
23198 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23203 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23204 emit_label (XEXP (label1, 0));
23206 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23208 emit_load_locked (mode, retval, mem);
23212 x = expand_simple_binop (SImode, AND, retval, mask,
23213 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23215 cond = gen_reg_rtx (CCmode);
23216 /* If we have TImode, synthesize a comparison. */
23217 if (mode != TImode)
23218 x = gen_rtx_COMPARE (CCmode, x, oldval);
23221 rtx xor1_result = gen_reg_rtx (DImode);
23222 rtx xor2_result = gen_reg_rtx (DImode);
23223 rtx or_result = gen_reg_rtx (DImode);
23224 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23225 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23226 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23227 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23229 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23230 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23231 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23232 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23235 emit_insn (gen_rtx_SET (cond, x));
23237 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23238 emit_unlikely_jump (x, label2);
23242 x = rs6000_mask_atomic_subword (retval, newval, mask);
23244 emit_store_conditional (orig_mode, cond, mem, x);
23248 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23249 emit_unlikely_jump (x, label1);
23252 if (!is_mm_relaxed (mod_f))
23253 emit_label (XEXP (label2, 0));
23255 rs6000_post_atomic_barrier (mod_s);
23257 if (is_mm_relaxed (mod_f))
23258 emit_label (XEXP (label2, 0));
23261 rs6000_finish_atomic_subword (operands[1], retval, shift);
23262 else if (mode != GET_MODE (operands[1]))
23263 convert_move (operands[1], retval, 1);
23265 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23266 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23267 emit_insn (gen_rtx_SET (boolval, x));
23270 /* Expand an atomic exchange operation. */
23273 rs6000_expand_atomic_exchange (rtx operands[])
23275 rtx retval, mem, val, cond;
23277 enum memmodel model;
23278 rtx label, x, mask, shift;
23280 retval = operands[0];
23283 model = memmodel_base (INTVAL (operands[3]));
23284 mode = GET_MODE (mem);
23286 mask = shift = NULL_RTX;
23287 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23289 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23291 /* Shift and mask VAL into position with the word. */
23292 val = convert_modes (SImode, mode, val, 1);
23293 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23294 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23296 /* Prepare to adjust the return value. */
23297 retval = gen_reg_rtx (SImode);
23301 mem = rs6000_pre_atomic_barrier (mem, model);
23303 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23304 emit_label (XEXP (label, 0));
23306 emit_load_locked (mode, retval, mem);
23310 x = rs6000_mask_atomic_subword (retval, val, mask);
23312 cond = gen_reg_rtx (CCmode);
23313 emit_store_conditional (mode, cond, mem, x);
23315 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23316 emit_unlikely_jump (x, label);
23318 rs6000_post_atomic_barrier (model);
23321 rs6000_finish_atomic_subword (operands[0], retval, shift);
23324 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23325 to perform. MEM is the memory on which to operate. VAL is the second
23326 operand of the binary operator. BEFORE and AFTER are optional locations to
23327 return the value of MEM either before of after the operation. MODEL_RTX
23328 is a CONST_INT containing the memory model to use. */
23331 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23332 rtx orig_before, rtx orig_after, rtx model_rtx)
23334 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23335 machine_mode mode = GET_MODE (mem);
23336 machine_mode store_mode = mode;
23337 rtx label, x, cond, mask, shift;
23338 rtx before = orig_before, after = orig_after;
23340 mask = shift = NULL_RTX;
23341 /* On power8, we want to use SImode for the operation. On previous systems,
23342 use the operation in a subword and shift/mask to get the proper byte or
23344 if (mode == QImode || mode == HImode)
23346 if (TARGET_SYNC_HI_QI)
23348 val = convert_modes (SImode, mode, val, 1);
23350 /* Prepare to adjust the return value. */
23351 before = gen_reg_rtx (SImode);
23353 after = gen_reg_rtx (SImode);
23358 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23360 /* Shift and mask VAL into position with the word. */
23361 val = convert_modes (SImode, mode, val, 1);
23362 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23363 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23369 /* We've already zero-extended VAL. That is sufficient to
23370 make certain that it does not affect other bits. */
23375 /* If we make certain that all of the other bits in VAL are
23376 set, that will be sufficient to not affect other bits. */
23377 x = gen_rtx_NOT (SImode, mask);
23378 x = gen_rtx_IOR (SImode, x, val);
23379 emit_insn (gen_rtx_SET (val, x));
23386 /* These will all affect bits outside the field and need
23387 adjustment via MASK within the loop. */
23391 gcc_unreachable ();
23394 /* Prepare to adjust the return value. */
23395 before = gen_reg_rtx (SImode);
23397 after = gen_reg_rtx (SImode);
23398 store_mode = mode = SImode;
23402 mem = rs6000_pre_atomic_barrier (mem, model);
23404 label = gen_label_rtx ();
23405 emit_label (label);
23406 label = gen_rtx_LABEL_REF (VOIDmode, label);
23408 if (before == NULL_RTX)
23409 before = gen_reg_rtx (mode);
23411 emit_load_locked (mode, before, mem);
23415 x = expand_simple_binop (mode, AND, before, val,
23416 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23417 after = expand_simple_unop (mode, NOT, x, after, 1);
23421 after = expand_simple_binop (mode, code, before, val,
23422 after, 1, OPTAB_LIB_WIDEN);
23428 x = expand_simple_binop (SImode, AND, after, mask,
23429 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23430 x = rs6000_mask_atomic_subword (before, x, mask);
23432 else if (store_mode != mode)
23433 x = convert_modes (store_mode, mode, x, 1);
23435 cond = gen_reg_rtx (CCmode);
23436 emit_store_conditional (store_mode, cond, mem, x);
23438 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23439 emit_unlikely_jump (x, label);
23441 rs6000_post_atomic_barrier (model);
23445 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23446 then do the calcuations in a SImode register. */
23448 rs6000_finish_atomic_subword (orig_before, before, shift);
23450 rs6000_finish_atomic_subword (orig_after, after, shift);
23452 else if (store_mode != mode)
23454 /* QImode/HImode on machines with lbarx/lharx where we do the native
23455 operation and then do the calcuations in a SImode register. */
23457 convert_move (orig_before, before, 1);
23459 convert_move (orig_after, after, 1);
23461 else if (orig_after && after != orig_after)
23462 emit_move_insn (orig_after, after);
23465 /* Emit instructions to move SRC to DST. Called by splitters for
23466 multi-register moves. It will emit at most one instruction for
23467 each register that is accessed; that is, it won't emit li/lis pairs
23468 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23472 rs6000_split_multireg_move (rtx dst, rtx src)
23474 /* The register number of the first register being moved. */
23476 /* The mode that is to be moved. */
23478 /* The mode that the move is being done in, and its size. */
23479 machine_mode reg_mode;
23481 /* The number of registers that will be moved. */
23484 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23485 mode = GET_MODE (dst);
23486 nregs = hard_regno_nregs (reg, mode);
23487 if (FP_REGNO_P (reg))
23488 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23489 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23490 else if (ALTIVEC_REGNO_P (reg))
23491 reg_mode = V16QImode;
23493 reg_mode = word_mode;
23494 reg_mode_size = GET_MODE_SIZE (reg_mode);
23496 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23498 /* TDmode residing in FP registers is special, since the ISA requires that
23499 the lower-numbered word of a register pair is always the most significant
23500 word, even in little-endian mode. This does not match the usual subreg
23501 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23502 the appropriate constituent registers "by hand" in little-endian mode.
23504 Note we do not need to check for destructive overlap here since TDmode
23505 can only reside in even/odd register pairs. */
23506 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23511 for (i = 0; i < nregs; i++)
23513 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23514 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23516 p_src = simplify_gen_subreg (reg_mode, src, mode,
23517 i * reg_mode_size);
23519 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23520 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23522 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23523 i * reg_mode_size);
23525 emit_insn (gen_rtx_SET (p_dst, p_src));
23531 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23533 /* Move register range backwards, if we might have destructive
23536 for (i = nregs - 1; i >= 0; i--)
23537 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23538 i * reg_mode_size),
23539 simplify_gen_subreg (reg_mode, src, mode,
23540 i * reg_mode_size)));
23546 bool used_update = false;
23547 rtx restore_basereg = NULL_RTX;
23549 if (MEM_P (src) && INT_REGNO_P (reg))
23553 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23554 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23557 breg = XEXP (XEXP (src, 0), 0);
23558 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23559 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23560 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23561 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23562 src = replace_equiv_address (src, breg);
23564 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23566 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23568 rtx basereg = XEXP (XEXP (src, 0), 0);
23571 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23572 emit_insn (gen_rtx_SET (ndst,
23573 gen_rtx_MEM (reg_mode,
23575 used_update = true;
23578 emit_insn (gen_rtx_SET (basereg,
23579 XEXP (XEXP (src, 0), 1)));
23580 src = replace_equiv_address (src, basereg);
23584 rtx basereg = gen_rtx_REG (Pmode, reg);
23585 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23586 src = replace_equiv_address (src, basereg);
23590 breg = XEXP (src, 0);
23591 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23592 breg = XEXP (breg, 0);
23594 /* If the base register we are using to address memory is
23595 also a destination reg, then change that register last. */
23597 && REGNO (breg) >= REGNO (dst)
23598 && REGNO (breg) < REGNO (dst) + nregs)
23599 j = REGNO (breg) - REGNO (dst);
23601 else if (MEM_P (dst) && INT_REGNO_P (reg))
23605 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23606 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23609 breg = XEXP (XEXP (dst, 0), 0);
23610 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23611 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23612 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23614 /* We have to update the breg before doing the store.
23615 Use store with update, if available. */
23619 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23620 emit_insn (TARGET_32BIT
23621 ? (TARGET_POWERPC64
23622 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23623 : gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
23624 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23625 used_update = true;
23628 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23629 dst = replace_equiv_address (dst, breg);
23631 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23632 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23634 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23636 rtx basereg = XEXP (XEXP (dst, 0), 0);
23639 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23640 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23643 used_update = true;
23646 emit_insn (gen_rtx_SET (basereg,
23647 XEXP (XEXP (dst, 0), 1)));
23648 dst = replace_equiv_address (dst, basereg);
23652 rtx basereg = XEXP (XEXP (dst, 0), 0);
23653 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23654 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23656 && REG_P (offsetreg)
23657 && REGNO (basereg) != REGNO (offsetreg));
23658 if (REGNO (basereg) == 0)
23660 rtx tmp = offsetreg;
23661 offsetreg = basereg;
23664 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23665 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23666 dst = replace_equiv_address (dst, basereg);
23669 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23670 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23673 for (i = 0; i < nregs; i++)
23675 /* Calculate index to next subword. */
23680 /* If compiler already emitted move of first word by
23681 store with update, no need to do anything. */
23682 if (j == 0 && used_update)
23685 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23686 j * reg_mode_size),
23687 simplify_gen_subreg (reg_mode, src, mode,
23688 j * reg_mode_size)));
23690 if (restore_basereg != NULL_RTX)
23691 emit_insn (restore_basereg);
23696 /* This page contains routines that are used to determine what the
23697 function prologue and epilogue code will do and write them out. */
23699 /* Determine whether the REG is really used. */
23702 save_reg_p (int reg)
23704 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23706 /* When calling eh_return, we must return true for all the cases
23707 where conditional_register_usage marks the PIC offset reg
23708 call used or fixed. */
23709 if (crtl->calls_eh_return
23710 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23711 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23712 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23715 /* We need to mark the PIC offset register live for the same
23716 conditions as it is set up in rs6000_emit_prologue, or
23717 otherwise it won't be saved before we clobber it. */
23718 if (TARGET_TOC && TARGET_MINIMAL_TOC
23719 && !constant_pool_empty_p ())
23722 if (DEFAULT_ABI == ABI_V4
23723 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
23724 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
23727 if (DEFAULT_ABI == ABI_DARWIN
23728 && flag_pic && crtl->uses_pic_offset_table)
23732 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23735 /* Return the first fixed-point register that is required to be
23736 saved. 32 if none. */
23739 first_reg_to_save (void)
23743 /* Find lowest numbered live register. */
23744 for (first_reg = 13; first_reg <= 31; first_reg++)
23745 if (save_reg_p (first_reg))
23751 /* Similar, for FP regs. */
23754 first_fp_reg_to_save (void)
23758 /* Find lowest numbered live register. */
23759 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23760 if (save_reg_p (first_reg))
23766 /* Similar, for AltiVec regs. */
23769 first_altivec_reg_to_save (void)
23773 /* Stack frame remains as is unless we are in AltiVec ABI. */
23774 if (! TARGET_ALTIVEC_ABI)
23775 return LAST_ALTIVEC_REGNO + 1;
23777 /* On Darwin, the unwind routines are compiled without
23778 TARGET_ALTIVEC, and use save_world to save/restore the
23779 altivec registers when necessary. */
23780 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23781 && ! TARGET_ALTIVEC)
23782 return FIRST_ALTIVEC_REGNO + 20;
23784 /* Find lowest numbered live register. */
23785 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23786 if (save_reg_p (i))
23792 /* Return a 32-bit mask of the AltiVec registers we need to set in
23793 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23794 the 32-bit word is 0. */
23796 static unsigned int
23797 compute_vrsave_mask (void)
23799 unsigned int i, mask = 0;
23801 /* On Darwin, the unwind routines are compiled without
23802 TARGET_ALTIVEC, and use save_world to save/restore the
23803 call-saved altivec registers when necessary. */
23804 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23805 && ! TARGET_ALTIVEC)
23808 /* First, find out if we use _any_ altivec registers. */
23809 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23810 if (df_regs_ever_live_p (i))
23811 mask |= ALTIVEC_REG_BIT (i);
23816 /* Next, remove the argument registers from the set. These must
23817 be in the VRSAVE mask set by the caller, so we don't need to add
23818 them in again. More importantly, the mask we compute here is
23819 used to generate CLOBBERs in the set_vrsave insn, and we do not
23820 wish the argument registers to die. */
23821 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23822 mask &= ~ALTIVEC_REG_BIT (i);
23824 /* Similarly, remove the return value from the set. */
23827 diddle_return_value (is_altivec_return_reg, &yes);
23829 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23835 /* For a very restricted set of circumstances, we can cut down the
23836 size of prologues/epilogues by calling our own save/restore-the-world
23840 compute_save_world_info (rs6000_stack_t *info)
23842 info->world_save_p = 1;
23844 = (WORLD_SAVE_P (info)
23845 && DEFAULT_ABI == ABI_DARWIN
23846 && !cfun->has_nonlocal_label
23847 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23848 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23849 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23850 && info->cr_save_p);
23852 /* This will not work in conjunction with sibcalls. Make sure there
23853 are none. (This check is expensive, but seldom executed.) */
23854 if (WORLD_SAVE_P (info))
23857 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23858 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23860 info->world_save_p = 0;
23865 if (WORLD_SAVE_P (info))
23867 /* Even if we're not touching VRsave, make sure there's room on the
23868 stack for it, if it looks like we're calling SAVE_WORLD, which
23869 will attempt to save it. */
23870 info->vrsave_size = 4;
23872 /* If we are going to save the world, we need to save the link register too. */
23873 info->lr_save_p = 1;
23875 /* "Save" the VRsave register too if we're saving the world. */
23876 if (info->vrsave_mask == 0)
23877 info->vrsave_mask = compute_vrsave_mask ();
23879 /* Because the Darwin register save/restore routines only handle
23880 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23882 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23883 && (info->first_altivec_reg_save
23884 >= FIRST_SAVED_ALTIVEC_REGNO));
23892 is_altivec_return_reg (rtx reg, void *xyes)
23894 bool *yes = (bool *) xyes;
23895 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23900 /* Return whether REG is a global user reg or has been specifed by
23901 -ffixed-REG. We should not restore these, and so cannot use
23902 lmw or out-of-line restore functions if there are any. We also
23903 can't save them (well, emit frame notes for them), because frame
23904 unwinding during exception handling will restore saved registers. */
23907 fixed_reg_p (int reg)
23909 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23910 backend sets it, overriding anything the user might have given. */
23911 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23912 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23913 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23914 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23917 return fixed_regs[reg];
23920 /* Determine the strategy for savings/restoring registers. */
23923 SAVE_MULTIPLE = 0x1,
23924 SAVE_INLINE_GPRS = 0x2,
23925 SAVE_INLINE_FPRS = 0x4,
23926 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23927 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23928 SAVE_INLINE_VRS = 0x20,
23929 REST_MULTIPLE = 0x100,
23930 REST_INLINE_GPRS = 0x200,
23931 REST_INLINE_FPRS = 0x400,
23932 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23933 REST_INLINE_VRS = 0x1000
23937 rs6000_savres_strategy (rs6000_stack_t *info,
23938 bool using_static_chain_p)
23942 /* Select between in-line and out-of-line save and restore of regs.
23943 First, all the obvious cases where we don't use out-of-line. */
23944 if (crtl->calls_eh_return
23945 || cfun->machine->ra_need_lr)
23946 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23947 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23948 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23950 if (info->first_gp_reg_save == 32)
23951 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23953 if (info->first_fp_reg_save == 64)
23954 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23956 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23957 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23959 /* Define cutoff for using out-of-line functions to save registers. */
23960 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23962 if (!optimize_size)
23964 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23965 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23966 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23970 /* Prefer out-of-line restore if it will exit. */
23971 if (info->first_fp_reg_save > 61)
23972 strategy |= SAVE_INLINE_FPRS;
23973 if (info->first_gp_reg_save > 29)
23975 if (info->first_fp_reg_save == 64)
23976 strategy |= SAVE_INLINE_GPRS;
23978 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23980 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
23981 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23984 else if (DEFAULT_ABI == ABI_DARWIN)
23986 if (info->first_fp_reg_save > 60)
23987 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23988 if (info->first_gp_reg_save > 29)
23989 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23990 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23994 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
23995 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
23996 || info->first_fp_reg_save > 61)
23997 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23998 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23999 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24002 /* Don't bother to try to save things out-of-line if r11 is occupied
24003 by the static chain. It would require too much fiddling and the
24004 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24005 pointer on Darwin, and AIX uses r1 or r12. */
24006 if (using_static_chain_p
24007 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24008 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24010 | SAVE_INLINE_VRS);
24012 /* Don't ever restore fixed regs. That means we can't use the
24013 out-of-line register restore functions if a fixed reg is in the
24014 range of regs restored. */
24015 if (!(strategy & REST_INLINE_FPRS))
24016 for (int i = info->first_fp_reg_save; i < 64; i++)
24019 strategy |= REST_INLINE_FPRS;
24023 /* We can only use the out-of-line routines to restore fprs if we've
24024 saved all the registers from first_fp_reg_save in the prologue.
24025 Otherwise, we risk loading garbage. Of course, if we have saved
24026 out-of-line then we know we haven't skipped any fprs. */
24027 if ((strategy & SAVE_INLINE_FPRS)
24028 && !(strategy & REST_INLINE_FPRS))
24029 for (int i = info->first_fp_reg_save; i < 64; i++)
24030 if (!save_reg_p (i))
24032 strategy |= REST_INLINE_FPRS;
24036 /* Similarly, for altivec regs. */
24037 if (!(strategy & REST_INLINE_VRS))
24038 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24041 strategy |= REST_INLINE_VRS;
24045 if ((strategy & SAVE_INLINE_VRS)
24046 && !(strategy & REST_INLINE_VRS))
24047 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24048 if (!save_reg_p (i))
24050 strategy |= REST_INLINE_VRS;
24054 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24055 saved is an out-of-line save or restore. Set up the value for
24056 the next test (excluding out-of-line gprs). */
24057 bool lr_save_p = (info->lr_save_p
24058 || !(strategy & SAVE_INLINE_FPRS)
24059 || !(strategy & SAVE_INLINE_VRS)
24060 || !(strategy & REST_INLINE_FPRS)
24061 || !(strategy & REST_INLINE_VRS));
24063 if (TARGET_MULTIPLE
24064 && !TARGET_POWERPC64
24065 && info->first_gp_reg_save < 31
24066 && !(flag_shrink_wrap
24067 && flag_shrink_wrap_separate
24068 && optimize_function_for_speed_p (cfun)))
24071 for (int i = info->first_gp_reg_save; i < 32; i++)
24072 if (save_reg_p (i))
24076 /* Don't use store multiple if only one reg needs to be
24077 saved. This can occur for example when the ABI_V4 pic reg
24078 (r30) needs to be saved to make calls, but r31 is not
24080 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24083 /* Prefer store multiple for saves over out-of-line
24084 routines, since the store-multiple instruction will
24085 always be smaller. */
24086 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24088 /* The situation is more complicated with load multiple.
24089 We'd prefer to use the out-of-line routines for restores,
24090 since the "exit" out-of-line routines can handle the
24091 restore of LR and the frame teardown. However if doesn't
24092 make sense to use the out-of-line routine if that is the
24093 only reason we'd need to save LR, and we can't use the
24094 "exit" out-of-line gpr restore if we have saved some
24095 fprs; In those cases it is advantageous to use load
24096 multiple when available. */
24097 if (info->first_fp_reg_save != 64 || !lr_save_p)
24098 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24102 /* Using the "exit" out-of-line routine does not improve code size
24103 if using it would require lr to be saved and if only saving one
24105 else if (!lr_save_p && info->first_gp_reg_save > 29)
24106 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24108 /* Don't ever restore fixed regs. */
24109 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24110 for (int i = info->first_gp_reg_save; i < 32; i++)
24111 if (fixed_reg_p (i))
24113 strategy |= REST_INLINE_GPRS;
24114 strategy &= ~REST_MULTIPLE;
24118 /* We can only use load multiple or the out-of-line routines to
24119 restore gprs if we've saved all the registers from
24120 first_gp_reg_save. Otherwise, we risk loading garbage.
24121 Of course, if we have saved out-of-line or used stmw then we know
24122 we haven't skipped any gprs. */
24123 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24124 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24125 for (int i = info->first_gp_reg_save; i < 32; i++)
24126 if (!save_reg_p (i))
24128 strategy |= REST_INLINE_GPRS;
24129 strategy &= ~REST_MULTIPLE;
24133 if (TARGET_ELF && TARGET_64BIT)
24135 if (!(strategy & SAVE_INLINE_FPRS))
24136 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24137 else if (!(strategy & SAVE_INLINE_GPRS)
24138 && info->first_fp_reg_save == 64)
24139 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24141 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24142 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24144 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24145 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24150 /* Calculate the stack information for the current function. This is
24151 complicated by having two separate calling sequences, the AIX calling
24152 sequence and the V.4 calling sequence.
24154 AIX (and Darwin/Mac OS X) stack frames look like:
24156 SP----> +---------------------------------------+
24157 | back chain to caller | 0 0
24158 +---------------------------------------+
24159 | saved CR | 4 8 (8-11)
24160 +---------------------------------------+
24162 +---------------------------------------+
24163 | reserved for compilers | 12 24
24164 +---------------------------------------+
24165 | reserved for binders | 16 32
24166 +---------------------------------------+
24167 | saved TOC pointer | 20 40
24168 +---------------------------------------+
24169 | Parameter save area (+padding*) (P) | 24 48
24170 +---------------------------------------+
24171 | Alloca space (A) | 24+P etc.
24172 +---------------------------------------+
24173 | Local variable space (L) | 24+P+A
24174 +---------------------------------------+
24175 | Float/int conversion temporary (X) | 24+P+A+L
24176 +---------------------------------------+
24177 | Save area for AltiVec registers (W) | 24+P+A+L+X
24178 +---------------------------------------+
24179 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24180 +---------------------------------------+
24181 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24182 +---------------------------------------+
24183 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24184 +---------------------------------------+
24185 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24186 +---------------------------------------+
24187 old SP->| back chain to caller's caller |
24188 +---------------------------------------+
24190 * If the alloca area is present, the parameter save area is
24191 padded so that the former starts 16-byte aligned.
24193 The required alignment for AIX configurations is two words (i.e., 8
24196 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24198 SP----> +---------------------------------------+
24199 | Back chain to caller | 0
24200 +---------------------------------------+
24201 | Save area for CR | 8
24202 +---------------------------------------+
24204 +---------------------------------------+
24205 | Saved TOC pointer | 24
24206 +---------------------------------------+
24207 | Parameter save area (+padding*) (P) | 32
24208 +---------------------------------------+
24209 | Alloca space (A) | 32+P
24210 +---------------------------------------+
24211 | Local variable space (L) | 32+P+A
24212 +---------------------------------------+
24213 | Save area for AltiVec registers (W) | 32+P+A+L
24214 +---------------------------------------+
24215 | AltiVec alignment padding (Y) | 32+P+A+L+W
24216 +---------------------------------------+
24217 | Save area for GP registers (G) | 32+P+A+L+W+Y
24218 +---------------------------------------+
24219 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24220 +---------------------------------------+
24221 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24222 +---------------------------------------+
24224 * If the alloca area is present, the parameter save area is
24225 padded so that the former starts 16-byte aligned.
24227 V.4 stack frames look like:
24229 SP----> +---------------------------------------+
24230 | back chain to caller | 0
24231 +---------------------------------------+
24232 | caller's saved LR | 4
24233 +---------------------------------------+
24234 | Parameter save area (+padding*) (P) | 8
24235 +---------------------------------------+
24236 | Alloca space (A) | 8+P
24237 +---------------------------------------+
24238 | Varargs save area (V) | 8+P+A
24239 +---------------------------------------+
24240 | Local variable space (L) | 8+P+A+V
24241 +---------------------------------------+
24242 | Float/int conversion temporary (X) | 8+P+A+V+L
24243 +---------------------------------------+
24244 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24245 +---------------------------------------+
24246 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24247 +---------------------------------------+
24248 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24249 +---------------------------------------+
24250 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24251 +---------------------------------------+
24252 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24253 +---------------------------------------+
24254 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24255 +---------------------------------------+
24256 old SP->| back chain to caller's caller |
24257 +---------------------------------------+
24259 * If the alloca area is present and the required alignment is
24260 16 bytes, the parameter save area is padded so that the
24261 alloca area starts 16-byte aligned.
24263 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24264 given. (But note below and in sysv4.h that we require only 8 and
24265 may round up the size of our stack frame anyways. The historical
24266 reason is early versions of powerpc-linux which didn't properly
24267 align the stack at program startup. A happy side-effect is that
24268 -mno-eabi libraries can be used with -meabi programs.)
24270 The EABI configuration defaults to the V.4 layout. However,
24271 the stack alignment requirements may differ. If -mno-eabi is not
24272 given, the required stack alignment is 8 bytes; if -mno-eabi is
24273 given, the required alignment is 16 bytes. (But see V.4 comment
24276 #ifndef ABI_STACK_BOUNDARY
24277 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24280 static rs6000_stack_t *
24281 rs6000_stack_info (void)
24283 /* We should never be called for thunks, we are not set up for that. */
24284 gcc_assert (!cfun->is_thunk);
24286 rs6000_stack_t *info = &stack_info;
24287 int reg_size = TARGET_32BIT ? 4 : 8;
24292 HOST_WIDE_INT non_fixed_size;
24293 bool using_static_chain_p;
24295 if (reload_completed && info->reload_completed)
24298 memset (info, 0, sizeof (*info));
24299 info->reload_completed = reload_completed;
24301 /* Select which calling sequence. */
24302 info->abi = DEFAULT_ABI;
24304 /* Calculate which registers need to be saved & save area size. */
24305 info->first_gp_reg_save = first_reg_to_save ();
24306 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24307 even if it currently looks like we won't. Reload may need it to
24308 get at a constant; if so, it will have already created a constant
24309 pool entry for it. */
24310 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24311 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24312 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24313 && crtl->uses_const_pool
24314 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24315 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24317 first_gp = info->first_gp_reg_save;
24319 info->gp_size = reg_size * (32 - first_gp);
24321 info->first_fp_reg_save = first_fp_reg_to_save ();
24322 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24324 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24325 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24326 - info->first_altivec_reg_save);
24328 /* Does this function call anything? */
24329 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24331 /* Determine if we need to save the condition code registers. */
24332 if (save_reg_p (CR2_REGNO)
24333 || save_reg_p (CR3_REGNO)
24334 || save_reg_p (CR4_REGNO))
24336 info->cr_save_p = 1;
24337 if (DEFAULT_ABI == ABI_V4)
24338 info->cr_size = reg_size;
24341 /* If the current function calls __builtin_eh_return, then we need
24342 to allocate stack space for registers that will hold data for
24343 the exception handler. */
24344 if (crtl->calls_eh_return)
24347 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24350 ehrd_size = i * UNITS_PER_WORD;
24355 /* In the ELFv2 ABI, we also need to allocate space for separate
24356 CR field save areas if the function calls __builtin_eh_return. */
24357 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24359 /* This hard-codes that we have three call-saved CR fields. */
24360 ehcr_size = 3 * reg_size;
24361 /* We do *not* use the regular CR save mechanism. */
24362 info->cr_save_p = 0;
24367 /* Determine various sizes. */
24368 info->reg_size = reg_size;
24369 info->fixed_size = RS6000_SAVE_AREA;
24370 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24371 if (cfun->calls_alloca)
24373 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24374 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24376 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24377 TARGET_ALTIVEC ? 16 : 8);
24378 if (FRAME_GROWS_DOWNWARD)
24380 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24381 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24382 - (info->fixed_size + info->vars_size + info->parm_size);
24384 if (TARGET_ALTIVEC_ABI)
24385 info->vrsave_mask = compute_vrsave_mask ();
24387 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24388 info->vrsave_size = 4;
24390 compute_save_world_info (info);
24392 /* Calculate the offsets. */
24393 switch (DEFAULT_ABI)
24397 gcc_unreachable ();
24402 info->fp_save_offset = -info->fp_size;
24403 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24405 if (TARGET_ALTIVEC_ABI)
24407 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24409 /* Align stack so vector save area is on a quadword boundary.
24410 The padding goes above the vectors. */
24411 if (info->altivec_size != 0)
24412 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24414 info->altivec_save_offset = info->vrsave_save_offset
24415 - info->altivec_padding_size
24416 - info->altivec_size;
24417 gcc_assert (info->altivec_size == 0
24418 || info->altivec_save_offset % 16 == 0);
24420 /* Adjust for AltiVec case. */
24421 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24424 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24426 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24427 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24428 info->lr_save_offset = 2*reg_size;
24432 info->fp_save_offset = -info->fp_size;
24433 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24434 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24436 if (TARGET_ALTIVEC_ABI)
24438 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24440 /* Align stack so vector save area is on a quadword boundary. */
24441 if (info->altivec_size != 0)
24442 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24444 info->altivec_save_offset = info->vrsave_save_offset
24445 - info->altivec_padding_size
24446 - info->altivec_size;
24448 /* Adjust for AltiVec case. */
24449 info->ehrd_offset = info->altivec_save_offset;
24452 info->ehrd_offset = info->cr_save_offset;
24454 info->ehrd_offset -= ehrd_size;
24455 info->lr_save_offset = reg_size;
24458 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24459 info->save_size = RS6000_ALIGN (info->fp_size
24461 + info->altivec_size
24462 + info->altivec_padding_size
24466 + info->vrsave_size,
24469 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24471 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24472 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24474 /* Determine if we need to save the link register. */
24476 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24478 && !TARGET_PROFILE_KERNEL)
24479 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24480 #ifdef TARGET_RELOCATABLE
24481 || (DEFAULT_ABI == ABI_V4
24482 && (TARGET_RELOCATABLE || flag_pic > 1)
24483 && !constant_pool_empty_p ())
24485 || rs6000_ra_ever_killed ())
24486 info->lr_save_p = 1;
24488 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24489 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24490 && call_used_regs[STATIC_CHAIN_REGNUM]);
24491 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24493 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24494 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24495 || !(info->savres_strategy & SAVE_INLINE_VRS)
24496 || !(info->savres_strategy & REST_INLINE_GPRS)
24497 || !(info->savres_strategy & REST_INLINE_FPRS)
24498 || !(info->savres_strategy & REST_INLINE_VRS))
24499 info->lr_save_p = 1;
24501 if (info->lr_save_p)
24502 df_set_regs_ever_live (LR_REGNO, true);
24504 /* Determine if we need to allocate any stack frame:
24506 For AIX we need to push the stack if a frame pointer is needed
24507 (because the stack might be dynamically adjusted), if we are
24508 debugging, if we make calls, or if the sum of fp_save, gp_save,
24509 and local variables are more than the space needed to save all
24510 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24511 + 18*8 = 288 (GPR13 reserved).
24513 For V.4 we don't have the stack cushion that AIX uses, but assume
24514 that the debugger can handle stackless frames. */
24519 else if (DEFAULT_ABI == ABI_V4)
24520 info->push_p = non_fixed_size != 0;
24522 else if (frame_pointer_needed)
24525 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24529 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24535 debug_stack_info (rs6000_stack_t *info)
24537 const char *abi_string;
24540 info = rs6000_stack_info ();
24542 fprintf (stderr, "\nStack information for function %s:\n",
24543 ((current_function_decl && DECL_NAME (current_function_decl))
24544 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24549 default: abi_string = "Unknown"; break;
24550 case ABI_NONE: abi_string = "NONE"; break;
24551 case ABI_AIX: abi_string = "AIX"; break;
24552 case ABI_ELFv2: abi_string = "ELFv2"; break;
24553 case ABI_DARWIN: abi_string = "Darwin"; break;
24554 case ABI_V4: abi_string = "V.4"; break;
24557 fprintf (stderr, "\tABI = %5s\n", abi_string);
24559 if (TARGET_ALTIVEC_ABI)
24560 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24562 if (info->first_gp_reg_save != 32)
24563 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24565 if (info->first_fp_reg_save != 64)
24566 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24568 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24569 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24570 info->first_altivec_reg_save);
24572 if (info->lr_save_p)
24573 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24575 if (info->cr_save_p)
24576 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24578 if (info->vrsave_mask)
24579 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24582 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24585 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24588 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24591 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24593 if (info->altivec_size)
24594 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24595 info->altivec_save_offset);
24597 if (info->vrsave_size)
24598 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24599 info->vrsave_save_offset);
24601 if (info->lr_save_p)
24602 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24604 if (info->cr_save_p)
24605 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24607 if (info->varargs_save_offset)
24608 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24610 if (info->total_size)
24611 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24614 if (info->vars_size)
24615 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24618 if (info->parm_size)
24619 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24621 if (info->fixed_size)
24622 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24625 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24628 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24630 if (info->altivec_size)
24631 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24633 if (info->vrsave_size)
24634 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24636 if (info->altivec_padding_size)
24637 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24638 info->altivec_padding_size);
24641 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24643 if (info->save_size)
24644 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24646 if (info->reg_size != 4)
24647 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24649 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24651 if (info->abi == ABI_DARWIN)
24652 fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
24654 fprintf (stderr, "\n");
24658 rs6000_return_addr (int count, rtx frame)
24660 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24661 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24663 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24665 cfun->machine->ra_needs_full_frame = 1;
24668 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24669 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24670 frame = stack_pointer_rtx;
24671 rtx prev_frame_addr = memory_address (Pmode, frame);
24672 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24673 rtx lr_save_off = plus_constant (Pmode,
24674 prev_frame, RETURN_ADDRESS_OFFSET);
24675 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24676 return gen_rtx_MEM (Pmode, lr_save_addr);
24679 cfun->machine->ra_need_lr = 1;
24680 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24683 /* Say whether a function is a candidate for sibcall handling or not. */
24686 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24690 /* The sibcall epilogue may clobber the static chain register.
24691 ??? We could work harder and avoid that, but it's probably
24692 not worth the hassle in practice. */
24693 if (CALL_EXPR_STATIC_CHAIN (exp))
24697 fntype = TREE_TYPE (decl);
24699 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24701 /* We can't do it if the called function has more vector parameters
24702 than the current function; there's nowhere to put the VRsave code. */
24703 if (TARGET_ALTIVEC_ABI
24704 && TARGET_ALTIVEC_VRSAVE
24705 && !(decl && decl == current_function_decl))
24707 function_args_iterator args_iter;
24711 /* Functions with vector parameters are required to have a
24712 prototype, so the argument type info must be available
24714 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24715 if (TREE_CODE (type) == VECTOR_TYPE
24716 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24719 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24720 if (TREE_CODE (type) == VECTOR_TYPE
24721 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24728 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24729 functions, because the callee may have a different TOC pointer to
24730 the caller and there's no way to ensure we restore the TOC when
24731 we return. With the secure-plt SYSV ABI we can't make non-local
24732 calls when -fpic/PIC because the plt call stubs use r30. */
24733 if (DEFAULT_ABI == ABI_DARWIN
24734 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24736 && !DECL_EXTERNAL (decl)
24737 && !DECL_WEAK (decl)
24738 && (*targetm.binds_local_p) (decl))
24739 || (DEFAULT_ABI == ABI_V4
24740 && (!TARGET_SECURE_PLT
24743 && (*targetm.binds_local_p) (decl)))))
24745 tree attr_list = TYPE_ATTRIBUTES (fntype);
24747 if (!lookup_attribute ("longcall", attr_list)
24748 || lookup_attribute ("shortcall", attr_list))
24756 rs6000_ra_ever_killed (void)
24762 if (cfun->is_thunk)
24765 if (cfun->machine->lr_save_state)
24766 return cfun->machine->lr_save_state - 1;
24768 /* regs_ever_live has LR marked as used if any sibcalls are present,
24769 but this should not force saving and restoring in the
24770 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24771 clobbers LR, so that is inappropriate. */
24773 /* Also, the prologue can generate a store into LR that
24774 doesn't really count, like this:
24777 bcl to set PIC register
24781 When we're called from the epilogue, we need to avoid counting
24782 this as a store. */
24784 push_topmost_sequence ();
24785 top = get_insns ();
24786 pop_topmost_sequence ();
24787 reg = gen_rtx_REG (Pmode, LR_REGNO);
24789 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24795 if (!SIBLING_CALL_P (insn))
24798 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24800 else if (set_of (reg, insn) != NULL_RTX
24801 && !prologue_epilogue_contains (insn))
24808 /* Emit instructions needed to load the TOC register.
24809 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24810 a constant pool; or for SVR4 -fpic. */
24813 rs6000_emit_load_toc_table (int fromprolog)
24816 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24818 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24821 rtx lab, tmp1, tmp2, got;
24823 lab = gen_label_rtx ();
24824 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24825 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24828 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24832 got = rs6000_got_sym ();
24833 tmp1 = tmp2 = dest;
24836 tmp1 = gen_reg_rtx (Pmode);
24837 tmp2 = gen_reg_rtx (Pmode);
24839 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24840 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24841 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24842 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24844 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24846 emit_insn (gen_load_toc_v4_pic_si ());
24847 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24849 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24852 rtx temp0 = (fromprolog
24853 ? gen_rtx_REG (Pmode, 0)
24854 : gen_reg_rtx (Pmode));
24860 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24861 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24863 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24864 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24866 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24867 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24868 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24874 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24876 lab = gen_label_rtx ();
24877 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24878 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24879 if (TARGET_LINK_STACK)
24880 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24881 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24883 emit_insn (gen_addsi3 (dest, temp0, dest));
24885 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24887 /* This is for AIX code running in non-PIC ELF32. */
24888 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24891 emit_insn (gen_elf_high (dest, realsym));
24892 emit_insn (gen_elf_low (dest, dest, realsym));
24896 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24899 emit_insn (gen_load_toc_aix_si (dest));
24901 emit_insn (gen_load_toc_aix_di (dest));
24905 /* Emit instructions to restore the link register after determining where
24906 its value has been stored. */
24909 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24911 rs6000_stack_t *info = rs6000_stack_info ();
24914 operands[0] = source;
24915 operands[1] = scratch;
24917 if (info->lr_save_p)
24919 rtx frame_rtx = stack_pointer_rtx;
24920 HOST_WIDE_INT sp_offset = 0;
24923 if (frame_pointer_needed
24924 || cfun->calls_alloca
24925 || info->total_size > 32767)
24927 tmp = gen_frame_mem (Pmode, frame_rtx);
24928 emit_move_insn (operands[1], tmp);
24929 frame_rtx = operands[1];
24931 else if (info->push_p)
24932 sp_offset = info->total_size;
24934 tmp = plus_constant (Pmode, frame_rtx,
24935 info->lr_save_offset + sp_offset);
24936 tmp = gen_frame_mem (Pmode, tmp);
24937 emit_move_insn (tmp, operands[0]);
24940 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24942 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24943 state of lr_save_p so any change from here on would be a bug. In
24944 particular, stop rs6000_ra_ever_killed from considering the SET
24945 of lr we may have added just above. */
24946 cfun->machine->lr_save_state = info->lr_save_p + 1;
24949 static GTY(()) alias_set_type set = -1;
24952 get_TOC_alias_set (void)
24955 set = new_alias_set ();
24959 /* This returns nonzero if the current function uses the TOC. This is
24960 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24961 is generated by the ABI_V4 load_toc_* patterns.
24962 Return 2 instead of 1 if the load_toc_* pattern is in the function
24963 partition that doesn't start the function. */
24971 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24975 rtx pat = PATTERN (insn);
24978 if (GET_CODE (pat) == PARALLEL)
24979 for (i = 0; i < XVECLEN (pat, 0); i++)
24981 rtx sub = XVECEXP (pat, 0, i);
24982 if (GET_CODE (sub) == USE)
24984 sub = XEXP (sub, 0);
24985 if (GET_CODE (sub) == UNSPEC
24986 && XINT (sub, 1) == UNSPEC_TOC)
24991 else if (crtl->has_bb_partition
24993 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25001 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25003 rtx tocrel, tocreg, hi;
25005 if (TARGET_DEBUG_ADDR)
25007 if (SYMBOL_REF_P (symbol))
25008 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25012 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25013 GET_RTX_NAME (GET_CODE (symbol)));
25014 debug_rtx (symbol);
25018 if (!can_create_pseudo_p ())
25019 df_set_regs_ever_live (TOC_REGISTER, true);
25021 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25022 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25023 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25026 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25027 if (largetoc_reg != NULL)
25029 emit_move_insn (largetoc_reg, hi);
25032 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25035 /* Issue assembly directives that create a reference to the given DWARF
25036 FRAME_TABLE_LABEL from the current function section. */
25038 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25040 fprintf (asm_out_file, "\t.ref %s\n",
25041 (* targetm.strip_name_encoding) (frame_table_label));
25044 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25045 and the change to the stack pointer. */
25048 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25055 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25056 if (hard_frame_needed)
25057 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25058 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25059 || (hard_frame_needed
25060 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25063 p = rtvec_alloc (i);
25066 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25067 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25070 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25073 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25074 and set the appropriate attributes for the generated insn. Return the
25075 first insn which adjusts the stack pointer or the last insn before
25076 the stack adjustment loop.
25078 SIZE_INT is used to create the CFI note for the allocation.
25080 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25081 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25083 ORIG_SP contains the backchain value that must be stored at *sp. */
25086 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25090 rtx size_rtx = GEN_INT (-size_int);
25091 if (size_int > 32767)
25093 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25094 /* Need a note here so that try_split doesn't get confused. */
25095 if (get_last_insn () == NULL_RTX)
25096 emit_note (NOTE_INSN_DELETED);
25097 insn = emit_move_insn (tmp_reg, size_rtx);
25098 try_split (PATTERN (insn), insn, 0);
25099 size_rtx = tmp_reg;
25103 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25108 insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
25112 rtx par = PATTERN (insn);
25113 gcc_assert (GET_CODE (par) == PARALLEL);
25114 rtx set = XVECEXP (par, 0, 0);
25115 gcc_assert (GET_CODE (set) == SET);
25116 rtx mem = SET_DEST (set);
25117 gcc_assert (MEM_P (mem));
25118 MEM_NOTRAP_P (mem) = 1;
25119 set_mem_alias_set (mem, get_frame_alias_set ());
25121 RTX_FRAME_RELATED_P (insn) = 1;
25122 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25123 gen_rtx_SET (stack_pointer_rtx,
25124 gen_rtx_PLUS (Pmode,
25126 GEN_INT (-size_int))));
25128 /* Emit a blockage to ensure the allocation/probing insns are
25129 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25130 note for similar reasons. */
25131 if (flag_stack_clash_protection)
25133 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25134 emit_insn (gen_blockage ());
25140 static HOST_WIDE_INT
25141 get_stack_clash_protection_probe_interval (void)
25143 return (HOST_WIDE_INT_1U
25144 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25147 static HOST_WIDE_INT
25148 get_stack_clash_protection_guard_size (void)
25150 return (HOST_WIDE_INT_1U
25151 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25154 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25155 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25157 COPY_REG, if non-null, should contain a copy of the original
25158 stack pointer at exit from this function.
25160 This is subtly different than the Ada probing in that it tries hard to
25161 prevent attacks that jump the stack guard. Thus it is never allowed to
25162 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25163 space without a suitable probe. */
25165 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25168 rtx orig_sp = copy_reg;
25170 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25172 /* Round the size down to a multiple of PROBE_INTERVAL. */
25173 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25175 /* If explicitly requested,
25176 or the rounded size is not the same as the original size
25177 or the the rounded size is greater than a page,
25178 then we will need a copy of the original stack pointer. */
25179 if (rounded_size != orig_size
25180 || rounded_size > probe_interval
25183 /* If the caller did not request a copy of the incoming stack
25184 pointer, then we use r0 to hold the copy. */
25186 orig_sp = gen_rtx_REG (Pmode, 0);
25187 emit_move_insn (orig_sp, stack_pointer_rtx);
25190 /* There's three cases here.
25192 One is a single probe which is the most common and most efficiently
25193 implemented as it does not have to have a copy of the original
25194 stack pointer if there are no residuals.
25196 Second is unrolled allocation/probes which we use if there's just
25197 a few of them. It needs to save the original stack pointer into a
25198 temporary for use as a source register in the allocation/probe.
25200 Last is a loop. This is the most uncommon case and least efficient. */
25201 rtx_insn *retval = NULL;
25202 if (rounded_size == probe_interval)
25204 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25206 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25208 else if (rounded_size <= 8 * probe_interval)
25210 /* The ABI requires using the store with update insns to allocate
25211 space and store the backchain into the stack
25213 So we save the current stack pointer into a temporary, then
25214 emit the store-with-update insns to store the saved stack pointer
25215 into the right location in each new page. */
25216 for (int i = 0; i < rounded_size; i += probe_interval)
25219 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25221 /* Save the first stack adjustment in RETVAL. */
25226 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25230 /* Compute the ending address. */
25232 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25233 rtx rs = GEN_INT (-rounded_size);
25235 if (add_operand (rs, Pmode))
25236 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25239 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25240 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25241 stack_pointer_rtx));
25242 /* Describe the effect of INSN to the CFI engine. */
25243 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25244 gen_rtx_SET (end_addr,
25245 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25248 RTX_FRAME_RELATED_P (insn) = 1;
25250 /* Emit the loop. */
25252 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25253 stack_pointer_rtx, orig_sp,
25256 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25257 stack_pointer_rtx, orig_sp,
25259 RTX_FRAME_RELATED_P (retval) = 1;
25260 /* Describe the effect of INSN to the CFI engine. */
25261 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25262 gen_rtx_SET (stack_pointer_rtx, end_addr));
25264 /* Emit a blockage to ensure the allocation/probing insns are
25265 not optimized, combined, removed, etc. Other cases handle this
25266 within their call to rs6000_emit_allocate_stack_1. */
25267 emit_insn (gen_blockage ());
25269 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25272 if (orig_size != rounded_size)
25274 /* Allocate (and implicitly probe) any residual space. */
25275 HOST_WIDE_INT residual = orig_size - rounded_size;
25277 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25279 /* If the residual was the only allocation, then we can return the
25280 allocating insn. */
25288 /* Emit the correct code for allocating stack space, as insns.
25289 If COPY_REG, make sure a copy of the old frame is left there.
25290 The generated code may use hard register 0 as a temporary. */
25293 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25296 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25297 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25298 rtx todec = gen_int_mode (-size, Pmode);
25300 if (INTVAL (todec) != -size)
25302 warning (0, "stack frame too large");
25303 emit_insn (gen_trap ());
25307 if (crtl->limit_stack)
25309 if (REG_P (stack_limit_rtx)
25310 && REGNO (stack_limit_rtx) > 1
25311 && REGNO (stack_limit_rtx) <= 31)
25314 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25317 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25319 else if (SYMBOL_REF_P (stack_limit_rtx)
25321 && DEFAULT_ABI == ABI_V4
25324 rtx toload = gen_rtx_CONST (VOIDmode,
25325 gen_rtx_PLUS (Pmode,
25329 emit_insn (gen_elf_high (tmp_reg, toload));
25330 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25331 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25335 warning (0, "stack limit expression is not supported");
25338 if (flag_stack_clash_protection)
25340 if (size < get_stack_clash_protection_guard_size ())
25341 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25344 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25347 /* If we asked for a copy with an offset, then we still need add in
25349 if (copy_reg && copy_off)
25350 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25358 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25360 emit_move_insn (copy_reg, stack_reg);
25363 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25364 it now and set the alias set/attributes. The above gen_*_update
25365 calls will generate a PARALLEL with the MEM set being the first
25367 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25371 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25373 #if PROBE_INTERVAL > 32768
25374 #error Cannot use indexed addressing mode for stack probing
25377 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25378 inclusive. These are offsets from the current stack pointer. */
25381 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25383 /* See if we have a constant small number of probes to generate. If so,
25384 that's the easy case. */
25385 if (first + size <= 32768)
25389 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25390 it exceeds SIZE. If only one probe is needed, this will not
25391 generate any code. Then probe at FIRST + SIZE. */
25392 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25393 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25396 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25400 /* Otherwise, do the same as above, but in a loop. Note that we must be
25401 extra careful with variables wrapping around because we might be at
25402 the very top (or the very bottom) of the address space and we have
25403 to be able to handle this case properly; in particular, we use an
25404 equality test for the loop condition. */
25407 HOST_WIDE_INT rounded_size;
25408 rtx r12 = gen_rtx_REG (Pmode, 12);
25409 rtx r0 = gen_rtx_REG (Pmode, 0);
25411 /* Sanity check for the addressing mode we're going to use. */
25412 gcc_assert (first <= 32768);
25414 /* Step 1: round SIZE to the previous multiple of the interval. */
25416 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25419 /* Step 2: compute initial and final value of the loop counter. */
25421 /* TEST_ADDR = SP + FIRST. */
25422 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25425 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25426 if (rounded_size > 32768)
25428 emit_move_insn (r0, GEN_INT (-rounded_size));
25429 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25432 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25436 /* Step 3: the loop
25440 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25443 while (TEST_ADDR != LAST_ADDR)
25445 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25446 until it is equal to ROUNDED_SIZE. */
25449 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25451 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25454 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25455 that SIZE is equal to ROUNDED_SIZE. */
25457 if (size != rounded_size)
25458 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25462 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25463 addresses, not offsets. */
25465 static const char *
25466 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25468 static int labelno = 0;
25472 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25475 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25477 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25479 xops[1] = GEN_INT (-PROBE_INTERVAL);
25480 output_asm_insn ("addi %0,%0,%1", xops);
25482 /* Probe at TEST_ADDR. */
25483 xops[1] = gen_rtx_REG (Pmode, 0);
25484 output_asm_insn ("stw %1,0(%0)", xops);
25486 /* Test if TEST_ADDR == LAST_ADDR. */
25489 output_asm_insn ("cmpd 0,%0,%1", xops);
25491 output_asm_insn ("cmpw 0,%0,%1", xops);
25494 fputs ("\tbne 0,", asm_out_file);
25495 assemble_name_raw (asm_out_file, loop_lab);
25496 fputc ('\n', asm_out_file);
25501 /* This function is called when rs6000_frame_related is processing
25502 SETs within a PARALLEL, and returns whether the REGNO save ought to
25503 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25504 for out-of-line register save functions, store multiple, and the
25505 Darwin world_save. They may contain registers that don't really
25509 interesting_frame_related_regno (unsigned int regno)
25511 /* Saves apparently of r0 are actually saving LR. It doesn't make
25512 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25513 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25514 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25515 as frame related. */
25518 /* If we see CR2 then we are here on a Darwin world save. Saves of
25519 CR2 signify the whole CR is being saved. This is a long-standing
25520 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25521 that CR needs to be saved. */
25522 if (regno == CR2_REGNO)
25524 /* Omit frame info for any user-defined global regs. If frame info
25525 is supplied for them, frame unwinding will restore a user reg.
25526 Also omit frame info for any reg we don't need to save, as that
25527 bloats frame info and can cause problems with shrink wrapping.
25528 Since global regs won't be seen as needing to be saved, both of
25529 these conditions are covered by save_reg_p. */
25530 return save_reg_p (regno);
25533 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25534 addresses, not offsets.
25536 REG2 contains the backchain that must be stored into *sp at each allocation.
25538 This is subtly different than the Ada probing above in that it tries hard
25539 to prevent attacks that jump the stack guard. Thus, it is never allowed
25540 to allocate more than PROBE_INTERVAL bytes of stack space without a
25543 static const char *
25544 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25546 static int labelno = 0;
25550 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25552 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25554 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25556 /* This allocates and probes. */
25559 xops[2] = GEN_INT (-probe_interval);
25561 output_asm_insn ("stdu %1,%2(%0)", xops);
25563 output_asm_insn ("stwu %1,%2(%0)", xops);
25565 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25569 output_asm_insn ("cmpd 0,%0,%1", xops);
25571 output_asm_insn ("cmpw 0,%0,%1", xops);
25573 fputs ("\tbne 0,", asm_out_file);
25574 assemble_name_raw (asm_out_file, loop_lab);
25575 fputc ('\n', asm_out_file);
25580 /* Wrapper around the output_probe_stack_range routines. */
25582 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25584 if (flag_stack_clash_protection)
25585 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25587 return output_probe_stack_range_1 (reg1, reg3);
25590 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25591 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25592 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25593 deduce these equivalences by itself so it wasn't necessary to hold
25594 its hand so much. Don't be tempted to always supply d2_f_d_e with
25595 the actual cfa register, ie. r31 when we are using a hard frame
25596 pointer. That fails when saving regs off r1, and sched moves the
25597 r31 setup past the reg saves. */
25600 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25601 rtx reg2, rtx repl2)
25605 if (REGNO (reg) == STACK_POINTER_REGNUM)
25607 gcc_checking_assert (val == 0);
25611 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25614 rtx pat = PATTERN (insn);
25615 if (!repl && !reg2)
25617 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25618 if (GET_CODE (pat) == PARALLEL)
25619 for (int i = 0; i < XVECLEN (pat, 0); i++)
25620 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25622 rtx set = XVECEXP (pat, 0, i);
25624 if (!REG_P (SET_SRC (set))
25625 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25626 RTX_FRAME_RELATED_P (set) = 1;
25628 RTX_FRAME_RELATED_P (insn) = 1;
25632 /* We expect that 'pat' is either a SET or a PARALLEL containing
25633 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25634 are important so they all have to be marked RTX_FRAME_RELATED_P.
25635 Call simplify_replace_rtx on the SETs rather than the whole insn
25636 so as to leave the other stuff alone (for example USE of r12). */
25638 set_used_flags (pat);
25639 if (GET_CODE (pat) == SET)
25642 pat = simplify_replace_rtx (pat, reg, repl);
25644 pat = simplify_replace_rtx (pat, reg2, repl2);
25646 else if (GET_CODE (pat) == PARALLEL)
25648 pat = shallow_copy_rtx (pat);
25649 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25651 for (int i = 0; i < XVECLEN (pat, 0); i++)
25652 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25654 rtx set = XVECEXP (pat, 0, i);
25657 set = simplify_replace_rtx (set, reg, repl);
25659 set = simplify_replace_rtx (set, reg2, repl2);
25660 XVECEXP (pat, 0, i) = set;
25662 if (!REG_P (SET_SRC (set))
25663 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25664 RTX_FRAME_RELATED_P (set) = 1;
25668 gcc_unreachable ();
25670 RTX_FRAME_RELATED_P (insn) = 1;
25671 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25676 /* Returns an insn that has a vrsave set operation with the
25677 appropriate CLOBBERs. */
25680 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25683 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25684 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25687 = gen_rtx_SET (vrsave,
25688 gen_rtx_UNSPEC_VOLATILE (SImode,
25689 gen_rtvec (2, reg, vrsave),
25690 UNSPECV_SET_VRSAVE));
25694 /* We need to clobber the registers in the mask so the scheduler
25695 does not move sets to VRSAVE before sets of AltiVec registers.
25697 However, if the function receives nonlocal gotos, reload will set
25698 all call saved registers live. We will end up with:
25700 (set (reg 999) (mem))
25701 (parallel [ (set (reg vrsave) (unspec blah))
25702 (clobber (reg 999))])
25704 The clobber will cause the store into reg 999 to be dead, and
25705 flow will attempt to delete an epilogue insn. In this case, we
25706 need an unspec use/set of the register. */
25708 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25709 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25711 if (!epiloguep || call_used_regs [i])
25712 clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
25715 rtx reg = gen_rtx_REG (V4SImode, i);
25718 = gen_rtx_SET (reg,
25719 gen_rtx_UNSPEC (V4SImode,
25720 gen_rtvec (1, reg), 27));
25724 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25726 for (i = 0; i < nclobs; ++i)
25727 XVECEXP (insn, 0, i) = clobs[i];
25733 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25737 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25738 mem = gen_frame_mem (GET_MODE (reg), addr);
25739 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25743 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25745 return gen_frame_set (reg, frame_reg, offset, false);
25749 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25751 return gen_frame_set (reg, frame_reg, offset, true);
25754 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25755 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25758 emit_frame_save (rtx frame_reg, machine_mode mode,
25759 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25763 /* Some cases that need register indexed addressing. */
25764 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25765 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25767 reg = gen_rtx_REG (mode, regno);
25768 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25769 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25770 NULL_RTX, NULL_RTX);
25773 /* Emit an offset memory reference suitable for a frame store, while
25774 converting to a valid addressing mode. */
25777 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25779 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25782 #ifndef TARGET_FIX_AND_CONTINUE
25783 #define TARGET_FIX_AND_CONTINUE 0
25786 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25787 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25788 #define LAST_SAVRES_REGISTER 31
25789 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25800 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25802 /* Temporary holding space for an out-of-line register save/restore
25804 static char savres_routine_name[30];
25806 /* Return the name for an out-of-line register save/restore routine.
25807 We are saving/restoring GPRs if GPR is true. */
25810 rs6000_savres_routine_name (int regno, int sel)
25812 const char *prefix = "";
25813 const char *suffix = "";
25815 /* Different targets are supposed to define
25816 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25817 routine name could be defined with:
25819 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25821 This is a nice idea in practice, but in reality, things are
25822 complicated in several ways:
25824 - ELF targets have save/restore routines for GPRs.
25826 - PPC64 ELF targets have routines for save/restore of GPRs that
25827 differ in what they do with the link register, so having a set
25828 prefix doesn't work. (We only use one of the save routines at
25829 the moment, though.)
25831 - PPC32 elf targets have "exit" versions of the restore routines
25832 that restore the link register and can save some extra space.
25833 These require an extra suffix. (There are also "tail" versions
25834 of the restore routines and "GOT" versions of the save routines,
25835 but we don't generate those at present. Same problems apply,
25838 We deal with all this by synthesizing our own prefix/suffix and
25839 using that for the simple sprintf call shown above. */
25840 if (DEFAULT_ABI == ABI_V4)
25845 if ((sel & SAVRES_REG) == SAVRES_GPR)
25846 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25847 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25848 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25849 else if ((sel & SAVRES_REG) == SAVRES_VR)
25850 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25854 if ((sel & SAVRES_LR))
25857 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25859 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25860 /* No out-of-line save/restore routines for GPRs on AIX. */
25861 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25865 if ((sel & SAVRES_REG) == SAVRES_GPR)
25866 prefix = ((sel & SAVRES_SAVE)
25867 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25868 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25869 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25871 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25872 if ((sel & SAVRES_LR))
25873 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25877 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25878 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25881 else if ((sel & SAVRES_REG) == SAVRES_VR)
25882 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25887 if (DEFAULT_ABI == ABI_DARWIN)
25889 /* The Darwin approach is (slightly) different, in order to be
25890 compatible with code generated by the system toolchain. There is a
25891 single symbol for the start of save sequence, and the code here
25892 embeds an offset into that code on the basis of the first register
25894 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25895 if ((sel & SAVRES_REG) == SAVRES_GPR)
25896 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25897 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25898 (regno - 13) * 4, prefix, regno);
25899 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25900 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25901 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25902 else if ((sel & SAVRES_REG) == SAVRES_VR)
25903 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25904 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25909 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25911 return savres_routine_name;
25914 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25915 We are saving/restoring GPRs if GPR is true. */
25918 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25920 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25921 ? info->first_gp_reg_save
25922 : (sel & SAVRES_REG) == SAVRES_FPR
25923 ? info->first_fp_reg_save - 32
25924 : (sel & SAVRES_REG) == SAVRES_VR
25925 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25930 /* Don't generate bogus routine names. */
25931 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25932 && regno <= LAST_SAVRES_REGISTER
25933 && select >= 0 && select <= 12);
25935 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25941 name = rs6000_savres_routine_name (regno, sel);
25943 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25944 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25945 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25951 /* Emit a sequence of insns, including a stack tie if needed, for
25952 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25953 reset the stack pointer, but move the base of the frame into
25954 reg UPDT_REGNO for use by out-of-line register restore routines. */
25957 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25958 unsigned updt_regno)
25960 /* If there is nothing to do, don't do anything. */
25961 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25964 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25966 /* This blockage is needed so that sched doesn't decide to move
25967 the sp change before the register restores. */
25968 if (DEFAULT_ABI == ABI_V4)
25969 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25970 GEN_INT (frame_off)));
25972 /* If we are restoring registers out-of-line, we will be using the
25973 "exit" variants of the restore routines, which will reset the
25974 stack for us. But we do need to point updt_reg into the
25975 right place for those routines. */
25976 if (frame_off != 0)
25977 return emit_insn (gen_add3_insn (updt_reg_rtx,
25978 frame_reg_rtx, GEN_INT (frame_off)));
25980 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
25985 /* Return the register number used as a pointer by out-of-line
25986 save/restore functions. */
25988 static inline unsigned
25989 ptr_regno_for_savres (int sel)
25991 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25992 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
25993 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
25996 /* Construct a parallel rtx describing the effect of a call to an
25997 out-of-line register save/restore routine, and emit the insn
25998 or jump_insn as appropriate. */
26001 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26002 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26003 machine_mode reg_mode, int sel)
26006 int offset, start_reg, end_reg, n_regs, use_reg;
26007 int reg_size = GET_MODE_SIZE (reg_mode);
26014 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26015 ? info->first_gp_reg_save
26016 : (sel & SAVRES_REG) == SAVRES_FPR
26017 ? info->first_fp_reg_save
26018 : (sel & SAVRES_REG) == SAVRES_VR
26019 ? info->first_altivec_reg_save
26021 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26023 : (sel & SAVRES_REG) == SAVRES_FPR
26025 : (sel & SAVRES_REG) == SAVRES_VR
26026 ? LAST_ALTIVEC_REGNO + 1
26028 n_regs = end_reg - start_reg;
26029 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26030 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26033 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26034 RTVEC_ELT (p, offset++) = ret_rtx;
26036 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
26038 sym = rs6000_savres_routine_sym (info, sel);
26039 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26041 use_reg = ptr_regno_for_savres (sel);
26042 if ((sel & SAVRES_REG) == SAVRES_VR)
26044 /* Vector regs are saved/restored using [reg+reg] addressing. */
26045 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
26046 RTVEC_ELT (p, offset++)
26047 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26050 RTVEC_ELT (p, offset++)
26051 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26053 for (i = 0; i < end_reg - start_reg; i++)
26054 RTVEC_ELT (p, i + offset)
26055 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26056 frame_reg_rtx, save_area_offset + reg_size * i,
26057 (sel & SAVRES_SAVE) != 0);
26059 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26060 RTVEC_ELT (p, i + offset)
26061 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26063 par = gen_rtx_PARALLEL (VOIDmode, p);
26065 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26067 insn = emit_jump_insn (par);
26068 JUMP_LABEL (insn) = ret_rtx;
26071 insn = emit_insn (par);
26075 /* Emit prologue code to store CR fields that need to be saved into REG. This
26076 function should only be called when moving the non-volatile CRs to REG, it
26077 is not a general purpose routine to move the entire set of CRs to REG.
26078 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26082 rs6000_emit_prologue_move_from_cr (rtx reg)
26084 /* Only the ELFv2 ABI allows storing only selected fields. */
26085 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26087 int i, cr_reg[8], count = 0;
26089 /* Collect CR fields that must be saved. */
26090 for (i = 0; i < 8; i++)
26091 if (save_reg_p (CR0_REGNO + i))
26092 cr_reg[count++] = i;
26094 /* If it's just a single one, use mfcrf. */
26097 rtvec p = rtvec_alloc (1);
26098 rtvec r = rtvec_alloc (2);
26099 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26100 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26102 = gen_rtx_SET (reg,
26103 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26105 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26109 /* ??? It might be better to handle count == 2 / 3 cases here
26110 as well, using logical operations to combine the values. */
26113 emit_insn (gen_prologue_movesi_from_cr (reg));
26116 /* Return whether the split-stack arg pointer (r12) is used. */
26119 split_stack_arg_pointer_used_p (void)
26121 /* If the pseudo holding the arg pointer is no longer a pseudo,
26122 then the arg pointer is used. */
26123 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26124 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26125 || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
26128 /* Unfortunately we also need to do some code scanning, since
26129 r12 may have been substituted for the pseudo. */
26131 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26132 FOR_BB_INSNS (bb, insn)
26133 if (NONDEBUG_INSN_P (insn))
26135 /* A call destroys r12. */
26140 FOR_EACH_INSN_USE (use, insn)
26142 rtx x = DF_REF_REG (use);
26143 if (REG_P (x) && REGNO (x) == 12)
26147 FOR_EACH_INSN_DEF (def, insn)
26149 rtx x = DF_REF_REG (def);
26150 if (REG_P (x) && REGNO (x) == 12)
26154 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26157 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26160 rs6000_global_entry_point_needed_p (void)
26162 /* Only needed for the ELFv2 ABI. */
26163 if (DEFAULT_ABI != ABI_ELFv2)
26166 /* With -msingle-pic-base, we assume the whole program shares the same
26167 TOC, so no global entry point prologues are needed anywhere. */
26168 if (TARGET_SINGLE_PIC_BASE)
26171 /* Ensure we have a global entry point for thunks. ??? We could
26172 avoid that if the target routine doesn't need a global entry point,
26173 but we do not know whether this is the case at this point. */
26174 if (cfun->is_thunk)
26177 /* For regular functions, rs6000_emit_prologue sets this flag if the
26178 routine ever uses the TOC pointer. */
26179 return cfun->machine->r2_setup_needed;
26182 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26184 rs6000_get_separate_components (void)
26186 rs6000_stack_t *info = rs6000_stack_info ();
26188 if (WORLD_SAVE_P (info))
26191 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26192 && !(info->savres_strategy & REST_MULTIPLE));
26194 /* Component 0 is the save/restore of LR (done via GPR0).
26195 Component 2 is the save of the TOC (GPR2).
26196 Components 13..31 are the save/restore of GPR13..GPR31.
26197 Components 46..63 are the save/restore of FPR14..FPR31. */
26199 cfun->machine->n_components = 64;
26201 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26202 bitmap_clear (components);
26204 int reg_size = TARGET_32BIT ? 4 : 8;
26205 int fp_reg_size = 8;
26207 /* The GPRs we need saved to the frame. */
26208 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26209 && (info->savres_strategy & REST_INLINE_GPRS))
26211 int offset = info->gp_save_offset;
26213 offset += info->total_size;
26215 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26217 if (IN_RANGE (offset, -0x8000, 0x7fff)
26218 && save_reg_p (regno))
26219 bitmap_set_bit (components, regno);
26221 offset += reg_size;
26225 /* Don't mess with the hard frame pointer. */
26226 if (frame_pointer_needed)
26227 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26229 /* Don't mess with the fixed TOC register. */
26230 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26231 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26232 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26233 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26235 /* The FPRs we need saved to the frame. */
26236 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26237 && (info->savres_strategy & REST_INLINE_FPRS))
26239 int offset = info->fp_save_offset;
26241 offset += info->total_size;
26243 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26245 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26246 bitmap_set_bit (components, regno);
26248 offset += fp_reg_size;
26252 /* Optimize LR save and restore if we can. This is component 0. Any
26253 out-of-line register save/restore routines need LR. */
26254 if (info->lr_save_p
26255 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26256 && (info->savres_strategy & SAVE_INLINE_GPRS)
26257 && (info->savres_strategy & REST_INLINE_GPRS)
26258 && (info->savres_strategy & SAVE_INLINE_FPRS)
26259 && (info->savres_strategy & REST_INLINE_FPRS)
26260 && (info->savres_strategy & SAVE_INLINE_VRS)
26261 && (info->savres_strategy & REST_INLINE_VRS))
26263 int offset = info->lr_save_offset;
26265 offset += info->total_size;
26266 if (IN_RANGE (offset, -0x8000, 0x7fff))
26267 bitmap_set_bit (components, 0);
26270 /* Optimize saving the TOC. This is component 2. */
26271 if (cfun->machine->save_toc_in_prologue)
26272 bitmap_set_bit (components, 2);
26277 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26279 rs6000_components_for_bb (basic_block bb)
26281 rs6000_stack_t *info = rs6000_stack_info ();
26283 bitmap in = DF_LIVE_IN (bb);
26284 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26285 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26287 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26288 bitmap_clear (components);
26290 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26293 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26294 if (bitmap_bit_p (in, regno)
26295 || bitmap_bit_p (gen, regno)
26296 || bitmap_bit_p (kill, regno))
26297 bitmap_set_bit (components, regno);
26300 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26301 if (bitmap_bit_p (in, regno)
26302 || bitmap_bit_p (gen, regno)
26303 || bitmap_bit_p (kill, regno))
26304 bitmap_set_bit (components, regno);
26306 /* The link register. */
26307 if (bitmap_bit_p (in, LR_REGNO)
26308 || bitmap_bit_p (gen, LR_REGNO)
26309 || bitmap_bit_p (kill, LR_REGNO))
26310 bitmap_set_bit (components, 0);
26312 /* The TOC save. */
26313 if (bitmap_bit_p (in, TOC_REGNUM)
26314 || bitmap_bit_p (gen, TOC_REGNUM)
26315 || bitmap_bit_p (kill, TOC_REGNUM))
26316 bitmap_set_bit (components, 2);
26321 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26323 rs6000_disqualify_components (sbitmap components, edge e,
26324 sbitmap edge_components, bool /*is_prologue*/)
26326 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26327 live where we want to place that code. */
26328 if (bitmap_bit_p (edge_components, 0)
26329 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26332 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26333 "on entry to bb %d\n", e->dest->index);
26334 bitmap_clear_bit (components, 0);
26338 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26340 rs6000_emit_prologue_components (sbitmap components)
26342 rs6000_stack_t *info = rs6000_stack_info ();
26343 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26344 ? HARD_FRAME_POINTER_REGNUM
26345 : STACK_POINTER_REGNUM);
26347 machine_mode reg_mode = Pmode;
26348 int reg_size = TARGET_32BIT ? 4 : 8;
26349 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26350 int fp_reg_size = 8;
26352 /* Prologue for LR. */
26353 if (bitmap_bit_p (components, 0))
26355 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26356 rtx reg = gen_rtx_REG (reg_mode, 0);
26357 rtx_insn *insn = emit_move_insn (reg, lr);
26358 RTX_FRAME_RELATED_P (insn) = 1;
26359 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26361 int offset = info->lr_save_offset;
26363 offset += info->total_size;
26365 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26366 RTX_FRAME_RELATED_P (insn) = 1;
26367 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26368 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26371 /* Prologue for TOC. */
26372 if (bitmap_bit_p (components, 2))
26374 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26375 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26376 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26379 /* Prologue for the GPRs. */
26380 int offset = info->gp_save_offset;
26382 offset += info->total_size;
26384 for (int i = info->first_gp_reg_save; i < 32; i++)
26386 if (bitmap_bit_p (components, i))
26388 rtx reg = gen_rtx_REG (reg_mode, i);
26389 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26390 RTX_FRAME_RELATED_P (insn) = 1;
26391 rtx set = copy_rtx (single_set (insn));
26392 add_reg_note (insn, REG_CFA_OFFSET, set);
26395 offset += reg_size;
26398 /* Prologue for the FPRs. */
26399 offset = info->fp_save_offset;
26401 offset += info->total_size;
26403 for (int i = info->first_fp_reg_save; i < 64; i++)
26405 if (bitmap_bit_p (components, i))
26407 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26408 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26409 RTX_FRAME_RELATED_P (insn) = 1;
26410 rtx set = copy_rtx (single_set (insn));
26411 add_reg_note (insn, REG_CFA_OFFSET, set);
26414 offset += fp_reg_size;
26418 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26420 rs6000_emit_epilogue_components (sbitmap components)
26422 rs6000_stack_t *info = rs6000_stack_info ();
26423 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26424 ? HARD_FRAME_POINTER_REGNUM
26425 : STACK_POINTER_REGNUM);
26427 machine_mode reg_mode = Pmode;
26428 int reg_size = TARGET_32BIT ? 4 : 8;
26430 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26431 int fp_reg_size = 8;
26433 /* Epilogue for the FPRs. */
26434 int offset = info->fp_save_offset;
26436 offset += info->total_size;
26438 for (int i = info->first_fp_reg_save; i < 64; i++)
26440 if (bitmap_bit_p (components, i))
26442 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26443 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26444 RTX_FRAME_RELATED_P (insn) = 1;
26445 add_reg_note (insn, REG_CFA_RESTORE, reg);
26448 offset += fp_reg_size;
26451 /* Epilogue for the GPRs. */
26452 offset = info->gp_save_offset;
26454 offset += info->total_size;
26456 for (int i = info->first_gp_reg_save; i < 32; i++)
26458 if (bitmap_bit_p (components, i))
26460 rtx reg = gen_rtx_REG (reg_mode, i);
26461 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26462 RTX_FRAME_RELATED_P (insn) = 1;
26463 add_reg_note (insn, REG_CFA_RESTORE, reg);
26466 offset += reg_size;
26469 /* Epilogue for LR. */
26470 if (bitmap_bit_p (components, 0))
26472 int offset = info->lr_save_offset;
26474 offset += info->total_size;
26476 rtx reg = gen_rtx_REG (reg_mode, 0);
26477 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26479 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26480 insn = emit_move_insn (lr, reg);
26481 RTX_FRAME_RELATED_P (insn) = 1;
26482 add_reg_note (insn, REG_CFA_RESTORE, lr);
26486 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26488 rs6000_set_handled_components (sbitmap components)
26490 rs6000_stack_t *info = rs6000_stack_info ();
26492 for (int i = info->first_gp_reg_save; i < 32; i++)
26493 if (bitmap_bit_p (components, i))
26494 cfun->machine->gpr_is_wrapped_separately[i] = true;
26496 for (int i = info->first_fp_reg_save; i < 64; i++)
26497 if (bitmap_bit_p (components, i))
26498 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26500 if (bitmap_bit_p (components, 0))
26501 cfun->machine->lr_is_wrapped_separately = true;
26503 if (bitmap_bit_p (components, 2))
26504 cfun->machine->toc_is_wrapped_separately = true;
26507 /* VRSAVE is a bit vector representing which AltiVec registers
26508 are used. The OS uses this to determine which vector
26509 registers to save on a context switch. We need to save
26510 VRSAVE on the stack frame, add whatever AltiVec registers we
26511 used in this function, and do the corresponding magic in the
26514 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26515 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26517 /* Get VRSAVE into a GPR. */
26518 rtx reg = gen_rtx_REG (SImode, save_regno);
26519 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26521 emit_insn (gen_get_vrsave_internal (reg));
26523 emit_insn (gen_rtx_SET (reg, vrsave));
26526 int offset = info->vrsave_save_offset + frame_off;
26527 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26529 /* Include the registers in the mask. */
26530 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26532 emit_insn (generate_set_vrsave (reg, info, 0));
26535 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26536 called, it left the arg pointer to the old stack in r29. Otherwise, the
26537 arg pointer is the top of the current frame. */
26539 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26540 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26542 cfun->machine->split_stack_argp_used = true;
26546 rtx r12 = gen_rtx_REG (Pmode, 12);
26547 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26548 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26549 emit_insn_before (set_r12, sp_adjust);
26551 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26553 rtx r12 = gen_rtx_REG (Pmode, 12);
26554 if (frame_off == 0)
26555 emit_move_insn (r12, frame_reg_rtx);
26557 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26562 rtx r12 = gen_rtx_REG (Pmode, 12);
26563 rtx r29 = gen_rtx_REG (Pmode, 29);
26564 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26565 rtx not_more = gen_label_rtx ();
26568 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26569 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26570 gen_rtx_LABEL_REF (VOIDmode, not_more),
26572 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26573 JUMP_LABEL (jump) = not_more;
26574 LABEL_NUSES (not_more) += 1;
26575 emit_move_insn (r12, r29);
26576 emit_label (not_more);
26580 /* Emit function prologue as insns. */
26583 rs6000_emit_prologue (void)
26585 rs6000_stack_t *info = rs6000_stack_info ();
26586 machine_mode reg_mode = Pmode;
26587 int reg_size = TARGET_32BIT ? 4 : 8;
26588 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26589 int fp_reg_size = 8;
26590 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26591 rtx frame_reg_rtx = sp_reg_rtx;
26592 unsigned int cr_save_regno;
26593 rtx cr_save_rtx = NULL_RTX;
26596 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26597 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26598 && call_used_regs[STATIC_CHAIN_REGNUM]);
26599 int using_split_stack = (flag_split_stack
26600 && (lookup_attribute ("no_split_stack",
26601 DECL_ATTRIBUTES (cfun->decl))
26604 /* Offset to top of frame for frame_reg and sp respectively. */
26605 HOST_WIDE_INT frame_off = 0;
26606 HOST_WIDE_INT sp_off = 0;
26607 /* sp_adjust is the stack adjusting instruction, tracked so that the
26608 insn setting up the split-stack arg pointer can be emitted just
26609 prior to it, when r12 is not used here for other purposes. */
26610 rtx_insn *sp_adjust = 0;
26613 /* Track and check usage of r0, r11, r12. */
26614 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26615 #define START_USE(R) do \
26617 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26618 reg_inuse |= 1 << (R); \
26620 #define END_USE(R) do \
26622 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26623 reg_inuse &= ~(1 << (R)); \
26625 #define NOT_INUSE(R) do \
26627 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26630 #define START_USE(R) do {} while (0)
26631 #define END_USE(R) do {} while (0)
26632 #define NOT_INUSE(R) do {} while (0)
26635 if (DEFAULT_ABI == ABI_ELFv2
26636 && !TARGET_SINGLE_PIC_BASE)
26638 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26640 /* With -mminimal-toc we may generate an extra use of r2 below. */
26641 if (TARGET_TOC && TARGET_MINIMAL_TOC
26642 && !constant_pool_empty_p ())
26643 cfun->machine->r2_setup_needed = true;
26647 if (flag_stack_usage_info)
26648 current_function_static_stack_size = info->total_size;
26650 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26652 HOST_WIDE_INT size = info->total_size;
26654 if (crtl->is_leaf && !cfun->calls_alloca)
26656 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26657 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26658 size - get_stack_check_protect ());
26661 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26664 if (TARGET_FIX_AND_CONTINUE)
26666 /* gdb on darwin arranges to forward a function from the old
26667 address by modifying the first 5 instructions of the function
26668 to branch to the overriding function. This is necessary to
26669 permit function pointers that point to the old function to
26670 actually forward to the new function. */
26671 emit_insn (gen_nop ());
26672 emit_insn (gen_nop ());
26673 emit_insn (gen_nop ());
26674 emit_insn (gen_nop ());
26675 emit_insn (gen_nop ());
26678 /* Handle world saves specially here. */
26679 if (WORLD_SAVE_P (info))
26686 /* save_world expects lr in r0. */
26687 reg0 = gen_rtx_REG (Pmode, 0);
26688 if (info->lr_save_p)
26690 insn = emit_move_insn (reg0,
26691 gen_rtx_REG (Pmode, LR_REGNO));
26692 RTX_FRAME_RELATED_P (insn) = 1;
26695 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26696 assumptions about the offsets of various bits of the stack
26698 gcc_assert (info->gp_save_offset == -220
26699 && info->fp_save_offset == -144
26700 && info->lr_save_offset == 8
26701 && info->cr_save_offset == 4
26704 && (!crtl->calls_eh_return
26705 || info->ehrd_offset == -432)
26706 && info->vrsave_save_offset == -224
26707 && info->altivec_save_offset == -416);
26709 treg = gen_rtx_REG (SImode, 11);
26710 emit_move_insn (treg, GEN_INT (-info->total_size));
26712 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26713 in R11. It also clobbers R12, so beware! */
26715 /* Preserve CR2 for save_world prologues */
26717 sz += 32 - info->first_gp_reg_save;
26718 sz += 64 - info->first_fp_reg_save;
26719 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26720 p = rtvec_alloc (sz);
26722 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
26723 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26724 gen_rtx_SYMBOL_REF (Pmode,
26726 /* We do floats first so that the instruction pattern matches
26728 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26730 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26731 info->first_fp_reg_save + i),
26733 info->fp_save_offset + frame_off + 8 * i);
26734 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26736 = gen_frame_store (gen_rtx_REG (V4SImode,
26737 info->first_altivec_reg_save + i),
26739 info->altivec_save_offset + frame_off + 16 * i);
26740 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26742 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26744 info->gp_save_offset + frame_off + reg_size * i);
26746 /* CR register traditionally saved as CR2. */
26748 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26749 frame_reg_rtx, info->cr_save_offset + frame_off);
26750 /* Explain about use of R0. */
26751 if (info->lr_save_p)
26753 = gen_frame_store (reg0,
26754 frame_reg_rtx, info->lr_save_offset + frame_off);
26755 /* Explain what happens to the stack pointer. */
26757 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26758 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26761 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26762 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26763 treg, GEN_INT (-info->total_size));
26764 sp_off = frame_off = info->total_size;
26767 strategy = info->savres_strategy;
26769 /* For V.4, update stack before we do any saving and set back pointer. */
26770 if (! WORLD_SAVE_P (info)
26772 && (DEFAULT_ABI == ABI_V4
26773 || crtl->calls_eh_return))
26775 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26776 || !(strategy & SAVE_INLINE_GPRS)
26777 || !(strategy & SAVE_INLINE_VRS));
26778 int ptr_regno = -1;
26779 rtx ptr_reg = NULL_RTX;
26782 if (info->total_size < 32767)
26783 frame_off = info->total_size;
26786 else if (info->cr_save_p
26788 || info->first_fp_reg_save < 64
26789 || info->first_gp_reg_save < 32
26790 || info->altivec_size != 0
26791 || info->vrsave_size != 0
26792 || crtl->calls_eh_return)
26796 /* The prologue won't be saving any regs so there is no need
26797 to set up a frame register to access any frame save area.
26798 We also won't be using frame_off anywhere below, but set
26799 the correct value anyway to protect against future
26800 changes to this function. */
26801 frame_off = info->total_size;
26803 if (ptr_regno != -1)
26805 /* Set up the frame offset to that needed by the first
26806 out-of-line save function. */
26807 START_USE (ptr_regno);
26808 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26809 frame_reg_rtx = ptr_reg;
26810 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26811 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26812 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26813 ptr_off = info->gp_save_offset + info->gp_size;
26814 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26815 ptr_off = info->altivec_save_offset + info->altivec_size;
26816 frame_off = -ptr_off;
26818 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26820 if (REGNO (frame_reg_rtx) == 12)
26822 sp_off = info->total_size;
26823 if (frame_reg_rtx != sp_reg_rtx)
26824 rs6000_emit_stack_tie (frame_reg_rtx, false);
26827 /* If we use the link register, get it into r0. */
26828 if (!WORLD_SAVE_P (info) && info->lr_save_p
26829 && !cfun->machine->lr_is_wrapped_separately)
26831 rtx addr, reg, mem;
26833 reg = gen_rtx_REG (Pmode, 0);
26835 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26836 RTX_FRAME_RELATED_P (insn) = 1;
26838 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26839 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26841 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26842 GEN_INT (info->lr_save_offset + frame_off));
26843 mem = gen_rtx_MEM (Pmode, addr);
26844 /* This should not be of rs6000_sr_alias_set, because of
26845 __builtin_return_address. */
26847 insn = emit_move_insn (mem, reg);
26848 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26849 NULL_RTX, NULL_RTX);
26854 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26855 r12 will be needed by out-of-line gpr save. */
26856 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26857 && !(strategy & (SAVE_INLINE_GPRS
26858 | SAVE_NOINLINE_GPRS_SAVES_LR))
26860 if (!WORLD_SAVE_P (info)
26862 && REGNO (frame_reg_rtx) != cr_save_regno
26863 && !(using_static_chain_p && cr_save_regno == 11)
26864 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26866 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26867 START_USE (cr_save_regno);
26868 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26871 /* Do any required saving of fpr's. If only one or two to save, do
26872 it ourselves. Otherwise, call function. */
26873 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26875 int offset = info->fp_save_offset + frame_off;
26876 for (int i = info->first_fp_reg_save; i < 64; i++)
26879 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26880 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26881 sp_off - frame_off);
26883 offset += fp_reg_size;
26886 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26888 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26889 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26890 unsigned ptr_regno = ptr_regno_for_savres (sel);
26891 rtx ptr_reg = frame_reg_rtx;
26893 if (REGNO (frame_reg_rtx) == ptr_regno)
26894 gcc_checking_assert (frame_off == 0);
26897 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26898 NOT_INUSE (ptr_regno);
26899 emit_insn (gen_add3_insn (ptr_reg,
26900 frame_reg_rtx, GEN_INT (frame_off)));
26902 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26903 info->fp_save_offset,
26904 info->lr_save_offset,
26906 rs6000_frame_related (insn, ptr_reg, sp_off,
26907 NULL_RTX, NULL_RTX);
26912 /* Save GPRs. This is done as a PARALLEL if we are using
26913 the store-multiple instructions. */
26914 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26916 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26917 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26918 unsigned ptr_regno = ptr_regno_for_savres (sel);
26919 rtx ptr_reg = frame_reg_rtx;
26920 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26921 int end_save = info->gp_save_offset + info->gp_size;
26924 if (ptr_regno == 12)
26927 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26929 /* Need to adjust r11 (r12) if we saved any FPRs. */
26930 if (end_save + frame_off != 0)
26932 rtx offset = GEN_INT (end_save + frame_off);
26935 frame_off = -end_save;
26937 NOT_INUSE (ptr_regno);
26938 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26940 else if (!ptr_set_up)
26942 NOT_INUSE (ptr_regno);
26943 emit_move_insn (ptr_reg, frame_reg_rtx);
26945 ptr_off = -end_save;
26946 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26947 info->gp_save_offset + ptr_off,
26948 info->lr_save_offset + ptr_off,
26950 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26951 NULL_RTX, NULL_RTX);
26955 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26959 p = rtvec_alloc (32 - info->first_gp_reg_save);
26960 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26962 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26964 info->gp_save_offset + frame_off + reg_size * i);
26965 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26966 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26967 NULL_RTX, NULL_RTX);
26969 else if (!WORLD_SAVE_P (info))
26971 int offset = info->gp_save_offset + frame_off;
26972 for (int i = info->first_gp_reg_save; i < 32; i++)
26975 && !cfun->machine->gpr_is_wrapped_separately[i])
26976 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26977 sp_off - frame_off);
26979 offset += reg_size;
26983 if (crtl->calls_eh_return)
26990 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26991 if (regno == INVALID_REGNUM)
26995 p = rtvec_alloc (i);
26999 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27000 if (regno == INVALID_REGNUM)
27004 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27006 info->ehrd_offset + sp_off + reg_size * (int) i);
27007 RTVEC_ELT (p, i) = set;
27008 RTX_FRAME_RELATED_P (set) = 1;
27011 insn = emit_insn (gen_blockage ());
27012 RTX_FRAME_RELATED_P (insn) = 1;
27013 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27016 /* In AIX ABI we need to make sure r2 is really saved. */
27017 if (TARGET_AIX && crtl->calls_eh_return)
27019 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27020 rtx join_insn, note;
27021 rtx_insn *save_insn;
27022 long toc_restore_insn;
27024 tmp_reg = gen_rtx_REG (Pmode, 11);
27025 tmp_reg_si = gen_rtx_REG (SImode, 11);
27026 if (using_static_chain_p)
27029 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27033 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27034 /* Peek at instruction to which this function returns. If it's
27035 restoring r2, then we know we've already saved r2. We can't
27036 unconditionally save r2 because the value we have will already
27037 be updated if we arrived at this function via a plt call or
27038 toc adjusting stub. */
27039 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27040 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27041 + RS6000_TOC_SAVE_SLOT);
27042 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27043 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27044 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27045 validate_condition_mode (EQ, CCUNSmode);
27046 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27047 emit_insn (gen_rtx_SET (compare_result,
27048 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27049 toc_save_done = gen_label_rtx ();
27050 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27051 gen_rtx_EQ (VOIDmode, compare_result,
27053 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27055 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27056 JUMP_LABEL (jump) = toc_save_done;
27057 LABEL_NUSES (toc_save_done) += 1;
27059 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27060 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27061 sp_off - frame_off);
27063 emit_label (toc_save_done);
27065 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27066 have a CFG that has different saves along different paths.
27067 Move the note to a dummy blockage insn, which describes that
27068 R2 is unconditionally saved after the label. */
27069 /* ??? An alternate representation might be a special insn pattern
27070 containing both the branch and the store. That might let the
27071 code that minimizes the number of DW_CFA_advance opcodes better
27072 freedom in placing the annotations. */
27073 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27075 remove_note (save_insn, note);
27077 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27078 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27079 RTX_FRAME_RELATED_P (save_insn) = 0;
27081 join_insn = emit_insn (gen_blockage ());
27082 REG_NOTES (join_insn) = note;
27083 RTX_FRAME_RELATED_P (join_insn) = 1;
27085 if (using_static_chain_p)
27087 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27094 /* Save CR if we use any that must be preserved. */
27095 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27097 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27098 GEN_INT (info->cr_save_offset + frame_off));
27099 rtx mem = gen_frame_mem (SImode, addr);
27101 /* If we didn't copy cr before, do so now using r0. */
27102 if (cr_save_rtx == NULL_RTX)
27105 cr_save_rtx = gen_rtx_REG (SImode, 0);
27106 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27109 /* Saving CR requires a two-instruction sequence: one instruction
27110 to move the CR to a general-purpose register, and a second
27111 instruction that stores the GPR to memory.
27113 We do not emit any DWARF CFI records for the first of these,
27114 because we cannot properly represent the fact that CR is saved in
27115 a register. One reason is that we cannot express that multiple
27116 CR fields are saved; another reason is that on 64-bit, the size
27117 of the CR register in DWARF (4 bytes) differs from the size of
27118 a general-purpose register.
27120 This means if any intervening instruction were to clobber one of
27121 the call-saved CR fields, we'd have incorrect CFI. To prevent
27122 this from happening, we mark the store to memory as a use of
27123 those CR fields, which prevents any such instruction from being
27124 scheduled in between the two instructions. */
27129 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27130 for (i = 0; i < 8; i++)
27131 if (save_reg_p (CR0_REGNO + i))
27132 crsave_v[n_crsave++]
27133 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27135 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27136 gen_rtvec_v (n_crsave, crsave_v)));
27137 END_USE (REGNO (cr_save_rtx));
27139 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27140 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27141 so we need to construct a frame expression manually. */
27142 RTX_FRAME_RELATED_P (insn) = 1;
27144 /* Update address to be stack-pointer relative, like
27145 rs6000_frame_related would do. */
27146 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27147 GEN_INT (info->cr_save_offset + sp_off));
27148 mem = gen_frame_mem (SImode, addr);
27150 if (DEFAULT_ABI == ABI_ELFv2)
27152 /* In the ELFv2 ABI we generate separate CFI records for each
27153 CR field that was actually saved. They all point to the
27154 same 32-bit stack slot. */
27158 for (i = 0; i < 8; i++)
27159 if (save_reg_p (CR0_REGNO + i))
27162 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27164 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27168 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27169 gen_rtx_PARALLEL (VOIDmode,
27170 gen_rtvec_v (n_crframe, crframe)));
27174 /* In other ABIs, by convention, we use a single CR regnum to
27175 represent the fact that all call-saved CR fields are saved.
27176 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27177 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27178 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27182 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27183 *separate* slots if the routine calls __builtin_eh_return, so
27184 that they can be independently restored by the unwinder. */
27185 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27187 int i, cr_off = info->ehcr_offset;
27190 /* ??? We might get better performance by using multiple mfocrf
27192 crsave = gen_rtx_REG (SImode, 0);
27193 emit_insn (gen_prologue_movesi_from_cr (crsave));
27195 for (i = 0; i < 8; i++)
27196 if (!call_used_regs[CR0_REGNO + i])
27198 rtvec p = rtvec_alloc (2);
27200 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27202 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27204 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27206 RTX_FRAME_RELATED_P (insn) = 1;
27207 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27208 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27209 sp_reg_rtx, cr_off + sp_off));
27211 cr_off += reg_size;
27215 /* If we are emitting stack probes, but allocate no stack, then
27216 just note that in the dump file. */
27217 if (flag_stack_clash_protection
27220 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27222 /* Update stack and set back pointer unless this is V.4,
27223 for which it was done previously. */
27224 if (!WORLD_SAVE_P (info) && info->push_p
27225 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27227 rtx ptr_reg = NULL;
27230 /* If saving altivec regs we need to be able to address all save
27231 locations using a 16-bit offset. */
27232 if ((strategy & SAVE_INLINE_VRS) == 0
27233 || (info->altivec_size != 0
27234 && (info->altivec_save_offset + info->altivec_size - 16
27235 + info->total_size - frame_off) > 32767)
27236 || (info->vrsave_size != 0
27237 && (info->vrsave_save_offset
27238 + info->total_size - frame_off) > 32767))
27240 int sel = SAVRES_SAVE | SAVRES_VR;
27241 unsigned ptr_regno = ptr_regno_for_savres (sel);
27243 if (using_static_chain_p
27244 && ptr_regno == STATIC_CHAIN_REGNUM)
27246 if (REGNO (frame_reg_rtx) != ptr_regno)
27247 START_USE (ptr_regno);
27248 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27249 frame_reg_rtx = ptr_reg;
27250 ptr_off = info->altivec_save_offset + info->altivec_size;
27251 frame_off = -ptr_off;
27253 else if (REGNO (frame_reg_rtx) == 1)
27254 frame_off = info->total_size;
27255 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27257 if (REGNO (frame_reg_rtx) == 12)
27259 sp_off = info->total_size;
27260 if (frame_reg_rtx != sp_reg_rtx)
27261 rs6000_emit_stack_tie (frame_reg_rtx, false);
27264 /* Set frame pointer, if needed. */
27265 if (frame_pointer_needed)
27267 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27269 RTX_FRAME_RELATED_P (insn) = 1;
27272 /* Save AltiVec registers if needed. Save here because the red zone does
27273 not always include AltiVec registers. */
27274 if (!WORLD_SAVE_P (info)
27275 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27277 int end_save = info->altivec_save_offset + info->altivec_size;
27279 /* Oddly, the vector save/restore functions point r0 at the end
27280 of the save area, then use r11 or r12 to load offsets for
27281 [reg+reg] addressing. */
27282 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27283 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27284 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27286 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27288 if (scratch_regno == 12)
27290 if (end_save + frame_off != 0)
27292 rtx offset = GEN_INT (end_save + frame_off);
27294 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27297 emit_move_insn (ptr_reg, frame_reg_rtx);
27299 ptr_off = -end_save;
27300 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27301 info->altivec_save_offset + ptr_off,
27302 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27303 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27304 NULL_RTX, NULL_RTX);
27305 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27307 /* The oddity mentioned above clobbered our frame reg. */
27308 emit_move_insn (frame_reg_rtx, ptr_reg);
27309 frame_off = ptr_off;
27312 else if (!WORLD_SAVE_P (info)
27313 && info->altivec_size != 0)
27317 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27318 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27320 rtx areg, savereg, mem;
27321 HOST_WIDE_INT offset;
27323 offset = (info->altivec_save_offset + frame_off
27324 + 16 * (i - info->first_altivec_reg_save));
27326 savereg = gen_rtx_REG (V4SImode, i);
27328 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27330 mem = gen_frame_mem (V4SImode,
27331 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27332 GEN_INT (offset)));
27333 insn = emit_insn (gen_rtx_SET (mem, savereg));
27339 areg = gen_rtx_REG (Pmode, 0);
27340 emit_move_insn (areg, GEN_INT (offset));
27342 /* AltiVec addressing mode is [reg+reg]. */
27343 mem = gen_frame_mem (V4SImode,
27344 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27346 /* Rather than emitting a generic move, force use of the stvx
27347 instruction, which we always want on ISA 2.07 (power8) systems.
27348 In particular we don't want xxpermdi/stxvd2x for little
27350 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27353 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27354 areg, GEN_INT (offset));
27358 /* VRSAVE is a bit vector representing which AltiVec registers
27359 are used. The OS uses this to determine which vector
27360 registers to save on a context switch. We need to save
27361 VRSAVE on the stack frame, add whatever AltiVec registers we
27362 used in this function, and do the corresponding magic in the
27365 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27367 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27368 be using r12 as frame_reg_rtx and r11 as the static chain
27369 pointer for nested functions. */
27370 int save_regno = 12;
27371 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27372 && !using_static_chain_p)
27374 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27377 if (using_static_chain_p)
27380 NOT_INUSE (save_regno);
27382 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27385 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27386 if (!TARGET_SINGLE_PIC_BASE
27387 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27388 && !constant_pool_empty_p ())
27389 || (DEFAULT_ABI == ABI_V4
27390 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27391 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27393 /* If emit_load_toc_table will use the link register, we need to save
27394 it. We use R12 for this purpose because emit_load_toc_table
27395 can use register 0. This allows us to use a plain 'blr' to return
27396 from the procedure more often. */
27397 int save_LR_around_toc_setup = (TARGET_ELF
27398 && DEFAULT_ABI == ABI_V4
27400 && ! info->lr_save_p
27401 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27402 if (save_LR_around_toc_setup)
27404 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27405 rtx tmp = gen_rtx_REG (Pmode, 12);
27408 insn = emit_move_insn (tmp, lr);
27409 RTX_FRAME_RELATED_P (insn) = 1;
27411 rs6000_emit_load_toc_table (TRUE);
27413 insn = emit_move_insn (lr, tmp);
27414 add_reg_note (insn, REG_CFA_RESTORE, lr);
27415 RTX_FRAME_RELATED_P (insn) = 1;
27418 rs6000_emit_load_toc_table (TRUE);
27422 if (!TARGET_SINGLE_PIC_BASE
27423 && DEFAULT_ABI == ABI_DARWIN
27424 && flag_pic && crtl->uses_pic_offset_table)
27426 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27427 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27429 /* Save and restore LR locally around this call (in R0). */
27430 if (!info->lr_save_p)
27431 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27433 emit_insn (gen_load_macho_picbase (src));
27435 emit_move_insn (gen_rtx_REG (Pmode,
27436 RS6000_PIC_OFFSET_TABLE_REGNUM),
27439 if (!info->lr_save_p)
27440 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27444 /* If we need to, save the TOC register after doing the stack setup.
27445 Do not emit eh frame info for this save. The unwinder wants info,
27446 conceptually attached to instructions in this function, about
27447 register values in the caller of this function. This R2 may have
27448 already been changed from the value in the caller.
27449 We don't attempt to write accurate DWARF EH frame info for R2
27450 because code emitted by gcc for a (non-pointer) function call
27451 doesn't save and restore R2. Instead, R2 is managed out-of-line
27452 by a linker generated plt call stub when the function resides in
27453 a shared library. This behavior is costly to describe in DWARF,
27454 both in terms of the size of DWARF info and the time taken in the
27455 unwinder to interpret it. R2 changes, apart from the
27456 calls_eh_return case earlier in this function, are handled by
27457 linux-unwind.h frob_update_context. */
27458 if (rs6000_save_toc_in_prologue_p ()
27459 && !cfun->machine->toc_is_wrapped_separately)
27461 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27462 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27465 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27466 if (using_split_stack && split_stack_arg_pointer_used_p ())
27467 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27470 /* Output .extern statements for the save/restore routines we use. */
27473 rs6000_output_savres_externs (FILE *file)
27475 rs6000_stack_t *info = rs6000_stack_info ();
27477 if (TARGET_DEBUG_STACK)
27478 debug_stack_info (info);
27480 /* Write .extern for any function we will call to save and restore
27482 if (info->first_fp_reg_save < 64
27487 int regno = info->first_fp_reg_save - 32;
27489 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27491 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27492 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27493 name = rs6000_savres_routine_name (regno, sel);
27494 fprintf (file, "\t.extern %s\n", name);
27496 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27498 bool lr = (info->savres_strategy
27499 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27500 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27501 name = rs6000_savres_routine_name (regno, sel);
27502 fprintf (file, "\t.extern %s\n", name);
27507 /* Write function prologue. */
27510 rs6000_output_function_prologue (FILE *file)
27512 if (!cfun->is_thunk)
27513 rs6000_output_savres_externs (file);
27515 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27516 immediately after the global entry point label. */
27517 if (rs6000_global_entry_point_needed_p ())
27519 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27521 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27523 if (TARGET_CMODEL != CMODEL_LARGE)
27525 /* In the small and medium code models, we assume the TOC is less
27526 2 GB away from the text section, so it can be computed via the
27527 following two-instruction sequence. */
27530 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27531 fprintf (file, "0:\taddis 2,12,.TOC.-");
27532 assemble_name (file, buf);
27533 fprintf (file, "@ha\n");
27534 fprintf (file, "\taddi 2,2,.TOC.-");
27535 assemble_name (file, buf);
27536 fprintf (file, "@l\n");
27540 /* In the large code model, we allow arbitrary offsets between the
27541 TOC and the text section, so we have to load the offset from
27542 memory. The data field is emitted directly before the global
27543 entry point in rs6000_elf_declare_function_name. */
27546 #ifdef HAVE_AS_ENTRY_MARKERS
27547 /* If supported by the linker, emit a marker relocation. If the
27548 total code size of the final executable or shared library
27549 happens to fit into 2 GB after all, the linker will replace
27550 this code sequence with the sequence for the small or medium
27552 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27554 fprintf (file, "\tld 2,");
27555 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27556 assemble_name (file, buf);
27557 fprintf (file, "-");
27558 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27559 assemble_name (file, buf);
27560 fprintf (file, "(12)\n");
27561 fprintf (file, "\tadd 2,2,12\n");
27564 fputs ("\t.localentry\t", file);
27565 assemble_name (file, name);
27566 fputs (",.-", file);
27567 assemble_name (file, name);
27568 fputs ("\n", file);
27571 /* Output -mprofile-kernel code. This needs to be done here instead of
27572 in output_function_profile since it must go after the ELFv2 ABI
27573 local entry point. */
27574 if (TARGET_PROFILE_KERNEL && crtl->profile)
27576 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27577 gcc_assert (!TARGET_32BIT);
27579 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27581 /* In the ELFv2 ABI we have no compiler stack word. It must be
27582 the resposibility of _mcount to preserve the static chain
27583 register if required. */
27584 if (DEFAULT_ABI != ABI_ELFv2
27585 && cfun->static_chain_decl != NULL)
27587 asm_fprintf (file, "\tstd %s,24(%s)\n",
27588 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27589 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27590 asm_fprintf (file, "\tld %s,24(%s)\n",
27591 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27594 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27597 rs6000_pic_labelno++;
27600 /* -mprofile-kernel code calls mcount before the function prolog,
27601 so a profiled leaf function should stay a leaf function. */
27603 rs6000_keep_leaf_when_profiled ()
27605 return TARGET_PROFILE_KERNEL;
27608 /* Non-zero if vmx regs are restored before the frame pop, zero if
27609 we restore after the pop when possible. */
27610 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27612 /* Restoring cr is a two step process: loading a reg from the frame
27613 save, then moving the reg to cr. For ABI_V4 we must let the
27614 unwinder know that the stack location is no longer valid at or
27615 before the stack deallocation, but we can't emit a cfa_restore for
27616 cr at the stack deallocation like we do for other registers.
27617 The trouble is that it is possible for the move to cr to be
27618 scheduled after the stack deallocation. So say exactly where cr
27619 is located on each of the two insns. */
27622 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27624 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27625 rtx reg = gen_rtx_REG (SImode, regno);
27626 rtx_insn *insn = emit_move_insn (reg, mem);
27628 if (!exit_func && DEFAULT_ABI == ABI_V4)
27630 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27631 rtx set = gen_rtx_SET (reg, cr);
27633 add_reg_note (insn, REG_CFA_REGISTER, set);
27634 RTX_FRAME_RELATED_P (insn) = 1;
27639 /* Reload CR from REG. */
27642 restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func)
27647 if (using_mfcr_multiple)
27649 for (i = 0; i < 8; i++)
27650 if (save_reg_p (CR0_REGNO + i))
27652 gcc_assert (count);
27655 if (using_mfcr_multiple && count > 1)
27661 p = rtvec_alloc (count);
27664 for (i = 0; i < 8; i++)
27665 if (save_reg_p (CR0_REGNO + i))
27667 rtvec r = rtvec_alloc (2);
27668 RTVEC_ELT (r, 0) = reg;
27669 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27670 RTVEC_ELT (p, ndx) =
27671 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27672 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27675 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27676 gcc_assert (ndx == count);
27678 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27679 CR field separately. */
27680 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27682 for (i = 0; i < 8; i++)
27683 if (save_reg_p (CR0_REGNO + i))
27684 add_reg_note (insn, REG_CFA_RESTORE,
27685 gen_rtx_REG (SImode, CR0_REGNO + i));
27687 RTX_FRAME_RELATED_P (insn) = 1;
27691 for (i = 0; i < 8; i++)
27692 if (save_reg_p (CR0_REGNO + i))
27694 rtx insn = emit_insn (gen_movsi_to_cr_one
27695 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27697 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27698 CR field separately, attached to the insn that in fact
27699 restores this particular CR field. */
27700 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27702 add_reg_note (insn, REG_CFA_RESTORE,
27703 gen_rtx_REG (SImode, CR0_REGNO + i));
27705 RTX_FRAME_RELATED_P (insn) = 1;
27709 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27710 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27711 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27713 rtx_insn *insn = get_last_insn ();
27714 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27716 add_reg_note (insn, REG_CFA_RESTORE, cr);
27717 RTX_FRAME_RELATED_P (insn) = 1;
27721 /* Like cr, the move to lr instruction can be scheduled after the
27722 stack deallocation, but unlike cr, its stack frame save is still
27723 valid. So we only need to emit the cfa_restore on the correct
27727 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27729 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27730 rtx reg = gen_rtx_REG (Pmode, regno);
27732 emit_move_insn (reg, mem);
27736 restore_saved_lr (int regno, bool exit_func)
27738 rtx reg = gen_rtx_REG (Pmode, regno);
27739 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27740 rtx_insn *insn = emit_move_insn (lr, reg);
27742 if (!exit_func && flag_shrink_wrap)
27744 add_reg_note (insn, REG_CFA_RESTORE, lr);
27745 RTX_FRAME_RELATED_P (insn) = 1;
27750 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27752 if (DEFAULT_ABI == ABI_ELFv2)
27755 for (i = 0; i < 8; i++)
27756 if (save_reg_p (CR0_REGNO + i))
27758 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27759 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27763 else if (info->cr_save_p)
27764 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27765 gen_rtx_REG (SImode, CR2_REGNO),
27768 if (info->lr_save_p)
27769 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27770 gen_rtx_REG (Pmode, LR_REGNO),
27772 return cfa_restores;
27775 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27776 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27777 below stack pointer not cloberred by signals. */
27780 offset_below_red_zone_p (HOST_WIDE_INT offset)
27782 return offset < (DEFAULT_ABI == ABI_V4
27784 : TARGET_32BIT ? -220 : -288);
27787 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27790 emit_cfa_restores (rtx cfa_restores)
27792 rtx_insn *insn = get_last_insn ();
27793 rtx *loc = ®_NOTES (insn);
27796 loc = &XEXP (*loc, 1);
27797 *loc = cfa_restores;
27798 RTX_FRAME_RELATED_P (insn) = 1;
27801 /* Emit function epilogue as insns. */
27804 rs6000_emit_epilogue (enum epilogue_type epilogue_type)
27806 HOST_WIDE_INT frame_off = 0;
27807 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27808 rtx frame_reg_rtx = sp_reg_rtx;
27809 rtx cfa_restores = NULL_RTX;
27811 rtx cr_save_reg = NULL_RTX;
27812 machine_mode reg_mode = Pmode;
27813 int reg_size = TARGET_32BIT ? 4 : 8;
27814 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27815 int fp_reg_size = 8;
27817 unsigned ptr_regno;
27819 rs6000_stack_t *info = rs6000_stack_info ();
27821 if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return)
27822 epilogue_type = EPILOGUE_TYPE_EH_RETURN;
27824 int strategy = info->savres_strategy;
27825 bool using_load_multiple = !!(strategy & REST_MULTIPLE);
27826 bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS);
27827 bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS);
27828 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
27830 restoring_GPRs_inline = true;
27831 restoring_FPRs_inline = true;
27834 bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27835 || rs6000_tune == PROCESSOR_PPC603
27836 || rs6000_tune == PROCESSOR_PPC750
27839 /* Restore via the backchain when we have a large frame, since this
27840 is more efficient than an addis, addi pair. The second condition
27841 here will not trigger at the moment; We don't actually need a
27842 frame pointer for alloca, but the generic parts of the compiler
27843 give us one anyway. */
27844 bool use_backchain_to_restore_sp
27845 = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767
27846 || (cfun->calls_alloca && !frame_pointer_needed));
27848 bool restore_lr = (info->lr_save_p
27849 && (restoring_FPRs_inline
27850 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27851 && (restoring_GPRs_inline
27852 || info->first_fp_reg_save < 64)
27853 && !cfun->machine->lr_is_wrapped_separately);
27856 if (WORLD_SAVE_P (info))
27858 gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL);
27860 /* eh_rest_world_r10 will return to the location saved in the LR
27861 stack slot (which is not likely to be our caller.)
27862 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27863 rest_world is similar, except any R10 parameter is ignored.
27864 The exception-handling stuff that was here in 2.95 is no
27865 longer necessary. */
27869 + 32 - info->first_gp_reg_save
27870 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27871 + 63 + 1 - info->first_fp_reg_save);
27874 switch (epilogue_type)
27876 case EPILOGUE_TYPE_NORMAL:
27877 rname = ggc_strdup ("*rest_world");
27880 case EPILOGUE_TYPE_EH_RETURN:
27881 rname = ggc_strdup ("*eh_rest_world_r10");
27885 gcc_unreachable ();
27889 RTVEC_ELT (p, j++) = ret_rtx;
27891 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname));
27892 /* The instruction pattern requires a clobber here;
27893 it is shared with the restVEC helper. */
27894 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11);
27897 /* CR register traditionally saved as CR2. */
27898 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27900 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27901 if (flag_shrink_wrap)
27903 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27904 gen_rtx_REG (Pmode, LR_REGNO),
27906 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27911 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27913 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27915 = gen_frame_load (reg,
27916 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27917 if (flag_shrink_wrap
27918 && save_reg_p (info->first_gp_reg_save + i))
27919 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27921 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27923 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27925 = gen_frame_load (reg,
27926 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27927 if (flag_shrink_wrap
27928 && save_reg_p (info->first_altivec_reg_save + i))
27929 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27931 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27933 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27934 info->first_fp_reg_save + i);
27936 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27937 if (flag_shrink_wrap
27938 && save_reg_p (info->first_fp_reg_save + i))
27939 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27941 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0);
27942 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12);
27943 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7);
27944 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8);
27946 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27947 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27949 if (flag_shrink_wrap)
27951 REG_NOTES (insn) = cfa_restores;
27952 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27953 RTX_FRAME_RELATED_P (insn) = 1;
27958 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27960 frame_off = info->total_size;
27962 /* Restore AltiVec registers if we must do so before adjusting the
27964 if (info->altivec_size != 0
27965 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27966 || (DEFAULT_ABI != ABI_V4
27967 && offset_below_red_zone_p (info->altivec_save_offset))))
27970 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27972 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27973 if (use_backchain_to_restore_sp)
27975 int frame_regno = 11;
27977 if ((strategy & REST_INLINE_VRS) == 0)
27979 /* Of r11 and r12, select the one not clobbered by an
27980 out-of-line restore function for the frame register. */
27981 frame_regno = 11 + 12 - scratch_regno;
27983 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
27984 emit_move_insn (frame_reg_rtx,
27985 gen_rtx_MEM (Pmode, sp_reg_rtx));
27988 else if (frame_pointer_needed)
27989 frame_reg_rtx = hard_frame_pointer_rtx;
27991 if ((strategy & REST_INLINE_VRS) == 0)
27993 int end_save = info->altivec_save_offset + info->altivec_size;
27995 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27996 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27998 if (end_save + frame_off != 0)
28000 rtx offset = GEN_INT (end_save + frame_off);
28002 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28005 emit_move_insn (ptr_reg, frame_reg_rtx);
28007 ptr_off = -end_save;
28008 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28009 info->altivec_save_offset + ptr_off,
28010 0, V4SImode, SAVRES_VR);
28014 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28015 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28017 rtx addr, areg, mem, insn;
28018 rtx reg = gen_rtx_REG (V4SImode, i);
28019 HOST_WIDE_INT offset
28020 = (info->altivec_save_offset + frame_off
28021 + 16 * (i - info->first_altivec_reg_save));
28023 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28025 mem = gen_frame_mem (V4SImode,
28026 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28027 GEN_INT (offset)));
28028 insn = gen_rtx_SET (reg, mem);
28032 areg = gen_rtx_REG (Pmode, 0);
28033 emit_move_insn (areg, GEN_INT (offset));
28035 /* AltiVec addressing mode is [reg+reg]. */
28036 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28037 mem = gen_frame_mem (V4SImode, addr);
28039 /* Rather than emitting a generic move, force use of the
28040 lvx instruction, which we always want. In particular we
28041 don't want lxvd2x/xxpermdi for little endian. */
28042 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28045 (void) emit_insn (insn);
28049 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28050 if (((strategy & REST_INLINE_VRS) == 0
28051 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28052 && (flag_shrink_wrap
28053 || (offset_below_red_zone_p
28054 (info->altivec_save_offset
28055 + 16 * (i - info->first_altivec_reg_save))))
28058 rtx reg = gen_rtx_REG (V4SImode, i);
28059 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28063 /* Restore VRSAVE if we must do so before adjusting the stack. */
28064 if (info->vrsave_size != 0
28065 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28066 || (DEFAULT_ABI != ABI_V4
28067 && offset_below_red_zone_p (info->vrsave_save_offset))))
28071 if (frame_reg_rtx == sp_reg_rtx)
28073 if (use_backchain_to_restore_sp)
28075 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28076 emit_move_insn (frame_reg_rtx,
28077 gen_rtx_MEM (Pmode, sp_reg_rtx));
28080 else if (frame_pointer_needed)
28081 frame_reg_rtx = hard_frame_pointer_rtx;
28084 reg = gen_rtx_REG (SImode, 12);
28085 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28086 info->vrsave_save_offset + frame_off));
28088 emit_insn (generate_set_vrsave (reg, info, 1));
28092 /* If we have a large stack frame, restore the old stack pointer
28093 using the backchain. */
28094 if (use_backchain_to_restore_sp)
28096 if (frame_reg_rtx == sp_reg_rtx)
28098 /* Under V.4, don't reset the stack pointer until after we're done
28099 loading the saved registers. */
28100 if (DEFAULT_ABI == ABI_V4)
28101 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28103 insn = emit_move_insn (frame_reg_rtx,
28104 gen_rtx_MEM (Pmode, sp_reg_rtx));
28107 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28108 && DEFAULT_ABI == ABI_V4)
28109 /* frame_reg_rtx has been set up by the altivec restore. */
28113 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28114 frame_reg_rtx = sp_reg_rtx;
28117 /* If we have a frame pointer, we can restore the old stack pointer
28119 else if (frame_pointer_needed)
28121 frame_reg_rtx = sp_reg_rtx;
28122 if (DEFAULT_ABI == ABI_V4)
28123 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28124 /* Prevent reordering memory accesses against stack pointer restore. */
28125 else if (cfun->calls_alloca
28126 || offset_below_red_zone_p (-info->total_size))
28127 rs6000_emit_stack_tie (frame_reg_rtx, true);
28129 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28130 GEN_INT (info->total_size)));
28133 else if (info->push_p
28134 && DEFAULT_ABI != ABI_V4
28135 && epilogue_type != EPILOGUE_TYPE_EH_RETURN)
28137 /* Prevent reordering memory accesses against stack pointer restore. */
28138 if (cfun->calls_alloca
28139 || offset_below_red_zone_p (-info->total_size))
28140 rs6000_emit_stack_tie (frame_reg_rtx, false);
28141 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28142 GEN_INT (info->total_size)));
28145 if (insn && frame_reg_rtx == sp_reg_rtx)
28149 REG_NOTES (insn) = cfa_restores;
28150 cfa_restores = NULL_RTX;
28152 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28153 RTX_FRAME_RELATED_P (insn) = 1;
28156 /* Restore AltiVec registers if we have not done so already. */
28157 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28158 && info->altivec_size != 0
28159 && (DEFAULT_ABI == ABI_V4
28160 || !offset_below_red_zone_p (info->altivec_save_offset)))
28164 if ((strategy & REST_INLINE_VRS) == 0)
28166 int end_save = info->altivec_save_offset + info->altivec_size;
28168 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28169 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28170 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28172 if (end_save + frame_off != 0)
28174 rtx offset = GEN_INT (end_save + frame_off);
28176 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28179 emit_move_insn (ptr_reg, frame_reg_rtx);
28181 ptr_off = -end_save;
28182 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28183 info->altivec_save_offset + ptr_off,
28184 0, V4SImode, SAVRES_VR);
28185 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28187 /* Frame reg was clobbered by out-of-line save. Restore it
28188 from ptr_reg, and if we are calling out-of-line gpr or
28189 fpr restore set up the correct pointer and offset. */
28190 unsigned newptr_regno = 1;
28191 if (!restoring_GPRs_inline)
28193 bool lr = info->gp_save_offset + info->gp_size == 0;
28194 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28195 newptr_regno = ptr_regno_for_savres (sel);
28196 end_save = info->gp_save_offset + info->gp_size;
28198 else if (!restoring_FPRs_inline)
28200 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28201 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28202 newptr_regno = ptr_regno_for_savres (sel);
28203 end_save = info->fp_save_offset + info->fp_size;
28206 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28207 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28209 if (end_save + ptr_off != 0)
28211 rtx offset = GEN_INT (end_save + ptr_off);
28213 frame_off = -end_save;
28215 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28218 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28223 frame_off = ptr_off;
28224 emit_move_insn (frame_reg_rtx, ptr_reg);
28230 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28231 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28233 rtx addr, areg, mem, insn;
28234 rtx reg = gen_rtx_REG (V4SImode, i);
28235 HOST_WIDE_INT offset
28236 = (info->altivec_save_offset + frame_off
28237 + 16 * (i - info->first_altivec_reg_save));
28239 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28241 mem = gen_frame_mem (V4SImode,
28242 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28243 GEN_INT (offset)));
28244 insn = gen_rtx_SET (reg, mem);
28248 areg = gen_rtx_REG (Pmode, 0);
28249 emit_move_insn (areg, GEN_INT (offset));
28251 /* AltiVec addressing mode is [reg+reg]. */
28252 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28253 mem = gen_frame_mem (V4SImode, addr);
28255 /* Rather than emitting a generic move, force use of the
28256 lvx instruction, which we always want. In particular we
28257 don't want lxvd2x/xxpermdi for little endian. */
28258 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28261 (void) emit_insn (insn);
28265 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28266 if (((strategy & REST_INLINE_VRS) == 0
28267 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28268 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28271 rtx reg = gen_rtx_REG (V4SImode, i);
28272 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28276 /* Restore VRSAVE if we have not done so already. */
28277 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28278 && info->vrsave_size != 0
28279 && (DEFAULT_ABI == ABI_V4
28280 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28284 reg = gen_rtx_REG (SImode, 12);
28285 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28286 info->vrsave_save_offset + frame_off));
28288 emit_insn (generate_set_vrsave (reg, info, 1));
28291 /* If we exit by an out-of-line restore function on ABI_V4 then that
28292 function will deallocate the stack, so we don't need to worry
28293 about the unwinder restoring cr from an invalid stack frame
28295 bool exit_func = (!restoring_FPRs_inline
28296 || (!restoring_GPRs_inline
28297 && info->first_fp_reg_save == 64));
28299 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28300 *separate* slots if the routine calls __builtin_eh_return, so
28301 that they can be independently restored by the unwinder. */
28302 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28304 int i, cr_off = info->ehcr_offset;
28306 for (i = 0; i < 8; i++)
28307 if (!call_used_regs[CR0_REGNO + i])
28309 rtx reg = gen_rtx_REG (SImode, 0);
28310 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28311 cr_off + frame_off));
28313 insn = emit_insn (gen_movsi_to_cr_one
28314 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28316 if (!exit_func && flag_shrink_wrap)
28318 add_reg_note (insn, REG_CFA_RESTORE,
28319 gen_rtx_REG (SImode, CR0_REGNO + i));
28321 RTX_FRAME_RELATED_P (insn) = 1;
28324 cr_off += reg_size;
28328 /* Get the old lr if we saved it. If we are restoring registers
28329 out-of-line, then the out-of-line routines can do this for us. */
28330 if (restore_lr && restoring_GPRs_inline)
28331 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28333 /* Get the old cr if we saved it. */
28334 if (info->cr_save_p)
28336 unsigned cr_save_regno = 12;
28338 if (!restoring_GPRs_inline)
28340 /* Ensure we don't use the register used by the out-of-line
28341 gpr register restore below. */
28342 bool lr = info->gp_save_offset + info->gp_size == 0;
28343 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28344 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28346 if (gpr_ptr_regno == 12)
28347 cr_save_regno = 11;
28348 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28350 else if (REGNO (frame_reg_rtx) == 12)
28351 cr_save_regno = 11;
28353 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28354 info->cr_save_offset + frame_off,
28358 /* Set LR here to try to overlap restores below. */
28359 if (restore_lr && restoring_GPRs_inline)
28360 restore_saved_lr (0, exit_func);
28362 /* Load exception handler data registers, if needed. */
28363 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28365 unsigned int i, regno;
28369 rtx reg = gen_rtx_REG (reg_mode, 2);
28370 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28371 frame_off + RS6000_TOC_SAVE_SLOT));
28378 regno = EH_RETURN_DATA_REGNO (i);
28379 if (regno == INVALID_REGNUM)
28382 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28383 info->ehrd_offset + frame_off
28384 + reg_size * (int) i);
28386 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28390 /* Restore GPRs. This is done as a PARALLEL if we are using
28391 the load-multiple instructions. */
28392 if (!restoring_GPRs_inline)
28394 /* We are jumping to an out-of-line function. */
28396 int end_save = info->gp_save_offset + info->gp_size;
28397 bool can_use_exit = end_save == 0;
28398 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28401 /* Emit stack reset code if we need it. */
28402 ptr_regno = ptr_regno_for_savres (sel);
28403 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28405 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28406 else if (end_save + frame_off != 0)
28407 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28408 GEN_INT (end_save + frame_off)));
28409 else if (REGNO (frame_reg_rtx) != ptr_regno)
28410 emit_move_insn (ptr_reg, frame_reg_rtx);
28411 if (REGNO (frame_reg_rtx) == ptr_regno)
28412 frame_off = -end_save;
28414 if (can_use_exit && info->cr_save_p)
28415 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28417 ptr_off = -end_save;
28418 rs6000_emit_savres_rtx (info, ptr_reg,
28419 info->gp_save_offset + ptr_off,
28420 info->lr_save_offset + ptr_off,
28423 else if (using_load_multiple)
28426 p = rtvec_alloc (32 - info->first_gp_reg_save);
28427 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28429 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28431 info->gp_save_offset + frame_off + reg_size * i);
28432 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28436 int offset = info->gp_save_offset + frame_off;
28437 for (i = info->first_gp_reg_save; i < 32; i++)
28440 && !cfun->machine->gpr_is_wrapped_separately[i])
28442 rtx reg = gen_rtx_REG (reg_mode, i);
28443 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28446 offset += reg_size;
28450 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28452 /* If the frame pointer was used then we can't delay emitting
28453 a REG_CFA_DEF_CFA note. This must happen on the insn that
28454 restores the frame pointer, r31. We may have already emitted
28455 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28456 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28457 be harmless if emitted. */
28458 if (frame_pointer_needed)
28460 insn = get_last_insn ();
28461 add_reg_note (insn, REG_CFA_DEF_CFA,
28462 plus_constant (Pmode, frame_reg_rtx, frame_off));
28463 RTX_FRAME_RELATED_P (insn) = 1;
28466 /* Set up cfa_restores. We always need these when
28467 shrink-wrapping. If not shrink-wrapping then we only need
28468 the cfa_restore when the stack location is no longer valid.
28469 The cfa_restores must be emitted on or before the insn that
28470 invalidates the stack, and of course must not be emitted
28471 before the insn that actually does the restore. The latter
28472 is why it is a bad idea to emit the cfa_restores as a group
28473 on the last instruction here that actually does a restore:
28474 That insn may be reordered with respect to others doing
28476 if (flag_shrink_wrap
28477 && !restoring_GPRs_inline
28478 && info->first_fp_reg_save == 64)
28479 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28481 for (i = info->first_gp_reg_save; i < 32; i++)
28483 && !cfun->machine->gpr_is_wrapped_separately[i])
28485 rtx reg = gen_rtx_REG (reg_mode, i);
28486 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28490 if (!restoring_GPRs_inline
28491 && info->first_fp_reg_save == 64)
28493 /* We are jumping to an out-of-line function. */
28495 emit_cfa_restores (cfa_restores);
28499 if (restore_lr && !restoring_GPRs_inline)
28501 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28502 restore_saved_lr (0, exit_func);
28505 /* Restore fpr's if we need to do it without calling a function. */
28506 if (restoring_FPRs_inline)
28508 int offset = info->fp_save_offset + frame_off;
28509 for (i = info->first_fp_reg_save; i < 64; i++)
28512 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28514 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28515 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28516 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28517 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28521 offset += fp_reg_size;
28525 /* If we saved cr, restore it here. Just those that were used. */
28526 if (info->cr_save_p)
28527 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28529 /* If this is V.4, unwind the stack pointer after all of the loads
28530 have been done, or set up r11 if we are restoring fp out of line. */
28532 if (!restoring_FPRs_inline)
28534 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28535 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28536 ptr_regno = ptr_regno_for_savres (sel);
28539 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28540 if (REGNO (frame_reg_rtx) == ptr_regno)
28543 if (insn && restoring_FPRs_inline)
28547 REG_NOTES (insn) = cfa_restores;
28548 cfa_restores = NULL_RTX;
28550 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28551 RTX_FRAME_RELATED_P (insn) = 1;
28554 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28556 rtx sa = EH_RETURN_STACKADJ_RTX;
28557 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28560 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline)
28564 /* We can't hang the cfa_restores off a simple return,
28565 since the shrink-wrap code sometimes uses an existing
28566 return. This means there might be a path from
28567 pre-prologue code to this return, and dwarf2cfi code
28568 wants the eh_frame unwinder state to be the same on
28569 all paths to any point. So we need to emit the
28570 cfa_restores before the return. For -m64 we really
28571 don't need epilogue cfa_restores at all, except for
28572 this irritating dwarf2cfi with shrink-wrap
28573 requirement; The stack red-zone means eh_frame info
28574 from the prologue telling the unwinder to restore
28575 from the stack is perfectly good right to the end of
28577 emit_insn (gen_blockage ());
28578 emit_cfa_restores (cfa_restores);
28579 cfa_restores = NULL_RTX;
28582 emit_jump_insn (targetm.gen_simple_return ());
28585 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline)
28587 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28588 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28590 RTVEC_ELT (p, elt++) = ret_rtx;
28592 RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
28594 /* We have to restore more than two FP registers, so branch to the
28595 restore function. It will return to our caller. */
28600 if (flag_shrink_wrap)
28601 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28603 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28604 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28605 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28606 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28608 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28610 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28612 RTVEC_ELT (p, elt++)
28613 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28614 if (flag_shrink_wrap
28615 && save_reg_p (info->first_fp_reg_save + i))
28616 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28619 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28624 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28625 /* Ensure the cfa_restores are hung off an insn that won't
28626 be reordered above other restores. */
28627 emit_insn (gen_blockage ());
28629 emit_cfa_restores (cfa_restores);
28633 /* Write function epilogue. */
28636 rs6000_output_function_epilogue (FILE *file)
28639 macho_branch_islands ();
28642 rtx_insn *insn = get_last_insn ();
28643 rtx_insn *deleted_debug_label = NULL;
28645 /* Mach-O doesn't support labels at the end of objects, so if
28646 it looks like we might want one, take special action.
28648 First, collect any sequence of deleted debug labels. */
28651 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28653 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28654 notes only, instead set their CODE_LABEL_NUMBER to -1,
28655 otherwise there would be code generation differences
28656 in between -g and -g0. */
28657 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28658 deleted_debug_label = insn;
28659 insn = PREV_INSN (insn);
28662 /* Second, if we have:
28665 then this needs to be detected, so skip past the barrier. */
28667 if (insn && BARRIER_P (insn))
28668 insn = PREV_INSN (insn);
28670 /* Up to now we've only seen notes or barriers. */
28675 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28676 /* Trailing label: <barrier>. */
28677 fputs ("\tnop\n", file);
28680 /* Lastly, see if we have a completely empty function body. */
28681 while (insn && ! INSN_P (insn))
28682 insn = PREV_INSN (insn);
28683 /* If we don't find any insns, we've got an empty function body;
28684 I.e. completely empty - without a return or branch. This is
28685 taken as the case where a function body has been removed
28686 because it contains an inline __builtin_unreachable(). GCC
28687 states that reaching __builtin_unreachable() means UB so we're
28688 not obliged to do anything special; however, we want
28689 non-zero-sized function bodies. To meet this, and help the
28690 user out, let's trap the case. */
28692 fputs ("\ttrap\n", file);
28695 else if (deleted_debug_label)
28696 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28697 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28698 CODE_LABEL_NUMBER (insn) = -1;
28702 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28705 We don't output a traceback table if -finhibit-size-directive was
28706 used. The documentation for -finhibit-size-directive reads
28707 ``don't output a @code{.size} assembler directive, or anything
28708 else that would cause trouble if the function is split in the
28709 middle, and the two halves are placed at locations far apart in
28710 memory.'' The traceback table has this property, since it
28711 includes the offset from the start of the function to the
28712 traceback table itself.
28714 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28715 different traceback table. */
28716 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28717 && ! flag_inhibit_size_directive
28718 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28720 const char *fname = NULL;
28721 const char *language_string = lang_hooks.name;
28722 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28724 int optional_tbtab;
28725 rs6000_stack_t *info = rs6000_stack_info ();
28727 if (rs6000_traceback == traceback_full)
28728 optional_tbtab = 1;
28729 else if (rs6000_traceback == traceback_part)
28730 optional_tbtab = 0;
28732 optional_tbtab = !optimize_size && !TARGET_ELF;
28734 if (optional_tbtab)
28736 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28737 while (*fname == '.') /* V.4 encodes . in the name */
28740 /* Need label immediately before tbtab, so we can compute
28741 its offset from the function start. */
28742 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28743 ASM_OUTPUT_LABEL (file, fname);
28746 /* The .tbtab pseudo-op can only be used for the first eight
28747 expressions, since it can't handle the possibly variable
28748 length fields that follow. However, if you omit the optional
28749 fields, the assembler outputs zeros for all optional fields
28750 anyways, giving each variable length field is minimum length
28751 (as defined in sys/debug.h). Thus we cannot use the .tbtab
28752 pseudo-op at all. */
28754 /* An all-zero word flags the start of the tbtab, for debuggers
28755 that have to find it by searching forward from the entry
28756 point or from the current pc. */
28757 fputs ("\t.long 0\n", file);
28759 /* Tbtab format type. Use format type 0. */
28760 fputs ("\t.byte 0,", file);
28762 /* Language type. Unfortunately, there does not seem to be any
28763 official way to discover the language being compiled, so we
28764 use language_string.
28765 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28766 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28767 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28768 numbers either, so for now use 0. */
28770 || ! strcmp (language_string, "GNU GIMPLE")
28771 || ! strcmp (language_string, "GNU Go")
28772 || ! strcmp (language_string, "GNU D")
28773 || ! strcmp (language_string, "libgccjit"))
28775 else if (! strcmp (language_string, "GNU F77")
28776 || lang_GNU_Fortran ())
28778 else if (! strcmp (language_string, "GNU Ada"))
28780 else if (lang_GNU_CXX ()
28781 || ! strcmp (language_string, "GNU Objective-C++"))
28783 else if (! strcmp (language_string, "GNU Java"))
28785 else if (! strcmp (language_string, "GNU Objective-C"))
28788 gcc_unreachable ();
28789 fprintf (file, "%d,", i);
28791 /* 8 single bit fields: global linkage (not set for C extern linkage,
28792 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28793 from start of procedure stored in tbtab, internal function, function
28794 has controlled storage, function has no toc, function uses fp,
28795 function logs/aborts fp operations. */
28796 /* Assume that fp operations are used if any fp reg must be saved. */
28797 fprintf (file, "%d,",
28798 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28800 /* 6 bitfields: function is interrupt handler, name present in
28801 proc table, function calls alloca, on condition directives
28802 (controls stack walks, 3 bits), saves condition reg, saves
28804 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28805 set up as a frame pointer, even when there is no alloca call. */
28806 fprintf (file, "%d,",
28807 ((optional_tbtab << 6)
28808 | ((optional_tbtab & frame_pointer_needed) << 5)
28809 | (info->cr_save_p << 1)
28810 | (info->lr_save_p)));
28812 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28814 fprintf (file, "%d,",
28815 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28817 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28818 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28820 if (optional_tbtab)
28822 /* Compute the parameter info from the function decl argument
28825 int next_parm_info_bit = 31;
28827 for (decl = DECL_ARGUMENTS (current_function_decl);
28828 decl; decl = DECL_CHAIN (decl))
28830 rtx parameter = DECL_INCOMING_RTL (decl);
28831 machine_mode mode = GET_MODE (parameter);
28833 if (REG_P (parameter))
28835 if (SCALAR_FLOAT_MODE_P (mode))
28858 gcc_unreachable ();
28861 /* If only one bit will fit, don't or in this entry. */
28862 if (next_parm_info_bit > 0)
28863 parm_info |= (bits << (next_parm_info_bit - 1));
28864 next_parm_info_bit -= 2;
28868 fixed_parms += ((GET_MODE_SIZE (mode)
28869 + (UNITS_PER_WORD - 1))
28871 next_parm_info_bit -= 1;
28877 /* Number of fixed point parameters. */
28878 /* This is actually the number of words of fixed point parameters; thus
28879 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28880 fprintf (file, "%d,", fixed_parms);
28882 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28884 /* This is actually the number of fp registers that hold parameters;
28885 and thus the maximum value is 13. */
28886 /* Set parameters on stack bit if parameters are not in their original
28887 registers, regardless of whether they are on the stack? Xlc
28888 seems to set the bit when not optimizing. */
28889 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28891 if (optional_tbtab)
28893 /* Optional fields follow. Some are variable length. */
28895 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28896 float, 11 double float. */
28897 /* There is an entry for each parameter in a register, in the order
28898 that they occur in the parameter list. Any intervening arguments
28899 on the stack are ignored. If the list overflows a long (max
28900 possible length 34 bits) then completely leave off all elements
28902 /* Only emit this long if there was at least one parameter. */
28903 if (fixed_parms || float_parms)
28904 fprintf (file, "\t.long %d\n", parm_info);
28906 /* Offset from start of code to tb table. */
28907 fputs ("\t.long ", file);
28908 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28909 RS6000_OUTPUT_BASENAME (file, fname);
28911 rs6000_output_function_entry (file, fname);
28914 /* Interrupt handler mask. */
28915 /* Omit this long, since we never set the interrupt handler bit
28918 /* Number of CTL (controlled storage) anchors. */
28919 /* Omit this long, since the has_ctl bit is never set above. */
28921 /* Displacement into stack of each CTL anchor. */
28922 /* Omit this list of longs, because there are no CTL anchors. */
28924 /* Length of function name. */
28927 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28929 /* Function name. */
28930 assemble_string (fname, strlen (fname));
28932 /* Register for alloca automatic storage; this is always reg 31.
28933 Only emit this if the alloca bit was set above. */
28934 if (frame_pointer_needed)
28935 fputs ("\t.byte 31\n", file);
28937 fputs ("\t.align 2\n", file);
28941 /* Arrange to define .LCTOC1 label, if not already done. */
28945 if (!toc_initialized)
28947 switch_to_section (toc_section);
28948 switch_to_section (current_function_section ());
28953 /* -fsplit-stack support. */
28955 /* A SYMBOL_REF for __morestack. */
28956 static GTY(()) rtx morestack_ref;
28959 gen_add3_const (rtx rt, rtx ra, long c)
28962 return gen_adddi3 (rt, ra, GEN_INT (c));
28964 return gen_addsi3 (rt, ra, GEN_INT (c));
28967 /* Emit -fsplit-stack prologue, which goes before the regular function
28968 prologue (at local entry point in the case of ELFv2). */
28971 rs6000_expand_split_stack_prologue (void)
28973 rs6000_stack_t *info = rs6000_stack_info ();
28974 unsigned HOST_WIDE_INT allocate;
28975 long alloc_hi, alloc_lo;
28976 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28979 gcc_assert (flag_split_stack && reload_completed);
28984 if (global_regs[29])
28986 error ("%qs uses register r29", "%<-fsplit-stack%>");
28987 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
28988 "conflicts with %qD", global_regs_decl[29]);
28991 allocate = info->total_size;
28992 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
28994 sorry ("Stack frame larger than 2G is not supported for "
28995 "%<-fsplit-stack%>");
28998 if (morestack_ref == NULL_RTX)
29000 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29001 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29002 | SYMBOL_FLAG_FUNCTION);
29005 r0 = gen_rtx_REG (Pmode, 0);
29006 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29007 r12 = gen_rtx_REG (Pmode, 12);
29008 emit_insn (gen_load_split_stack_limit (r0));
29009 /* Always emit two insns here to calculate the requested stack,
29010 so that the linker can edit them when adjusting size for calling
29011 non-split-stack code. */
29012 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29013 alloc_lo = -allocate - alloc_hi;
29016 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29018 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29020 emit_insn (gen_nop ());
29024 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29025 emit_insn (gen_nop ());
29028 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29029 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29030 ok_label = gen_label_rtx ();
29031 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29032 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29033 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29035 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29036 JUMP_LABEL (insn) = ok_label;
29037 /* Mark the jump as very likely to be taken. */
29038 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29040 lr = gen_rtx_REG (Pmode, LR_REGNO);
29041 insn = emit_move_insn (r0, lr);
29042 RTX_FRAME_RELATED_P (insn) = 1;
29043 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29044 RTX_FRAME_RELATED_P (insn) = 1;
29046 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29047 const0_rtx, const0_rtx));
29048 call_fusage = NULL_RTX;
29049 use_reg (&call_fusage, r12);
29050 /* Say the call uses r0, even though it doesn't, to stop regrename
29051 from twiddling with the insns saving lr, trashing args for cfun.
29052 The insns restoring lr are similarly protected by making
29053 split_stack_return use r0. */
29054 use_reg (&call_fusage, r0);
29055 add_function_usage_to (insn, call_fusage);
29056 /* Indicate that this function can't jump to non-local gotos. */
29057 make_reg_eh_region_note_nothrow_nononlocal (insn);
29058 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29059 insn = emit_move_insn (lr, r0);
29060 add_reg_note (insn, REG_CFA_RESTORE, lr);
29061 RTX_FRAME_RELATED_P (insn) = 1;
29062 emit_insn (gen_split_stack_return ());
29064 emit_label (ok_label);
29065 LABEL_NUSES (ok_label) = 1;
29068 /* Return the internal arg pointer used for function incoming
29069 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29070 to copy it to a pseudo in order for it to be preserved over calls
29071 and suchlike. We'd really like to use a pseudo here for the
29072 internal arg pointer but data-flow analysis is not prepared to
29073 accept pseudos as live at the beginning of a function. */
29076 rs6000_internal_arg_pointer (void)
29078 if (flag_split_stack
29079 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29083 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29087 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29088 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29090 /* Put the pseudo initialization right after the note at the
29091 beginning of the function. */
29092 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29093 gen_rtx_REG (Pmode, 12));
29094 push_topmost_sequence ();
29095 emit_insn_after (pat, get_insns ());
29096 pop_topmost_sequence ();
29098 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29099 FIRST_PARM_OFFSET (current_function_decl));
29100 return copy_to_reg (ret);
29102 return virtual_incoming_args_rtx;
29105 /* We may have to tell the dataflow pass that the split stack prologue
29106 is initializing a register. */
29109 rs6000_live_on_entry (bitmap regs)
29111 if (flag_split_stack)
29112 bitmap_set_bit (regs, 12);
29115 /* Emit -fsplit-stack dynamic stack allocation space check. */
29118 rs6000_split_stack_space_check (rtx size, rtx label)
29120 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29121 rtx limit = gen_reg_rtx (Pmode);
29122 rtx requested = gen_reg_rtx (Pmode);
29123 rtx cmp = gen_reg_rtx (CCUNSmode);
29126 emit_insn (gen_load_split_stack_limit (limit));
29127 if (CONST_INT_P (size))
29128 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29131 size = force_reg (Pmode, size);
29132 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29134 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29135 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29136 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29137 gen_rtx_LABEL_REF (VOIDmode, label),
29139 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29140 JUMP_LABEL (jump) = label;
29143 /* A C compound statement that outputs the assembler code for a thunk
29144 function, used to implement C++ virtual function calls with
29145 multiple inheritance. The thunk acts as a wrapper around a virtual
29146 function, adjusting the implicit object parameter before handing
29147 control off to the real function.
29149 First, emit code to add the integer DELTA to the location that
29150 contains the incoming first argument. Assume that this argument
29151 contains a pointer, and is the one used to pass the `this' pointer
29152 in C++. This is the incoming argument *before* the function
29153 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29154 values of all other incoming arguments.
29156 After the addition, emit code to jump to FUNCTION, which is a
29157 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29158 not touch the return address. Hence returning from FUNCTION will
29159 return to whoever called the current `thunk'.
29161 The effect must be as if FUNCTION had been called directly with the
29162 adjusted first argument. This macro is responsible for emitting
29163 all of the code for a thunk function; output_function_prologue()
29164 and output_function_epilogue() are not invoked.
29166 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29167 been extracted from it.) It might possibly be useful on some
29168 targets, but probably not.
29170 If you do not define this macro, the target-independent code in the
29171 C++ frontend will generate a less efficient heavyweight thunk that
29172 calls FUNCTION instead of jumping to it. The generic approach does
29173 not support varargs. */
29176 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29177 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29180 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
29181 rtx this_rtx, funexp;
29184 reload_completed = 1;
29185 epilogue_completed = 1;
29187 /* Mark the end of the (empty) prologue. */
29188 emit_note (NOTE_INSN_PROLOGUE_END);
29190 /* Find the "this" pointer. If the function returns a structure,
29191 the structure return pointer is in r3. */
29192 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29193 this_rtx = gen_rtx_REG (Pmode, 4);
29195 this_rtx = gen_rtx_REG (Pmode, 3);
29197 /* Apply the constant offset, if required. */
29199 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29201 /* Apply the offset from the vtable, if required. */
29204 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29205 rtx tmp = gen_rtx_REG (Pmode, 12);
29207 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29208 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29210 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29211 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29215 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29217 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29219 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29222 /* Generate a tail call to the target function. */
29223 if (!TREE_USED (function))
29225 assemble_external (function);
29226 TREE_USED (function) = 1;
29228 funexp = XEXP (DECL_RTL (function), 0);
29229 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29232 if (MACHOPIC_INDIRECT)
29233 funexp = machopic_indirect_call_target (funexp);
29236 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29237 generate sibcall RTL explicitly. */
29238 insn = emit_call_insn (
29239 gen_rtx_PARALLEL (VOIDmode,
29241 gen_rtx_CALL (VOIDmode,
29242 funexp, const0_rtx),
29243 gen_rtx_USE (VOIDmode, const0_rtx),
29244 simple_return_rtx)));
29245 SIBLING_CALL_P (insn) = 1;
29248 /* Run just enough of rest_of_compilation to get the insns emitted.
29249 There's not really enough bulk here to make other passes such as
29250 instruction scheduling worth while. Note that use_thunk calls
29251 assemble_start_function and assemble_end_function. */
29252 insn = get_insns ();
29253 shorten_branches (insn);
29254 assemble_start_function (thunk_fndecl, fnname);
29255 final_start_function (insn, file, 1);
29256 final (insn, file, 1);
29257 final_end_function ();
29258 assemble_end_function (thunk_fndecl, fnname);
29260 reload_completed = 0;
29261 epilogue_completed = 0;
29264 /* A quick summary of the various types of 'constant-pool tables'
29267 Target Flags Name One table per
29268 AIX (none) AIX TOC object file
29269 AIX -mfull-toc AIX TOC object file
29270 AIX -mminimal-toc AIX minimal TOC translation unit
29271 SVR4/EABI (none) SVR4 SDATA object file
29272 SVR4/EABI -fpic SVR4 pic object file
29273 SVR4/EABI -fPIC SVR4 PIC translation unit
29274 SVR4/EABI -mrelocatable EABI TOC function
29275 SVR4/EABI -maix AIX TOC object file
29276 SVR4/EABI -maix -mminimal-toc
29277 AIX minimal TOC translation unit
29279 Name Reg. Set by entries contains:
29280 made by addrs? fp? sum?
29282 AIX TOC 2 crt0 as Y option option
29283 AIX minimal TOC 30 prolog gcc Y Y option
29284 SVR4 SDATA 13 crt0 gcc N Y N
29285 SVR4 pic 30 prolog ld Y not yet N
29286 SVR4 PIC 30 prolog gcc Y option option
29287 EABI TOC 30 prolog gcc Y option option
29291 /* Hash functions for the hash table. */
29294 rs6000_hash_constant (rtx k)
29296 enum rtx_code code = GET_CODE (k);
29297 machine_mode mode = GET_MODE (k);
29298 unsigned result = (code << 3) ^ mode;
29299 const char *format;
29302 format = GET_RTX_FORMAT (code);
29303 flen = strlen (format);
29309 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29311 case CONST_WIDE_INT:
29314 flen = CONST_WIDE_INT_NUNITS (k);
29315 for (i = 0; i < flen; i++)
29316 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29321 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29331 for (; fidx < flen; fidx++)
29332 switch (format[fidx])
29337 const char *str = XSTR (k, fidx);
29338 len = strlen (str);
29339 result = result * 613 + len;
29340 for (i = 0; i < len; i++)
29341 result = result * 613 + (unsigned) str[i];
29346 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29350 result = result * 613 + (unsigned) XINT (k, fidx);
29353 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29354 result = result * 613 + (unsigned) XWINT (k, fidx);
29358 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29359 result = result * 613 + (unsigned) (XWINT (k, fidx)
29366 gcc_unreachable ();
29373 toc_hasher::hash (toc_hash_struct *thc)
29375 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29378 /* Compare H1 and H2 for equivalence. */
29381 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29386 if (h1->key_mode != h2->key_mode)
29389 return rtx_equal_p (r1, r2);
29392 /* These are the names given by the C++ front-end to vtables, and
29393 vtable-like objects. Ideally, this logic should not be here;
29394 instead, there should be some programmatic way of inquiring as
29395 to whether or not an object is a vtable. */
29397 #define VTABLE_NAME_P(NAME) \
29398 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29399 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29400 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29401 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29402 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29404 #ifdef NO_DOLLAR_IN_LABEL
29405 /* Return a GGC-allocated character string translating dollar signs in
29406 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29409 rs6000_xcoff_strip_dollar (const char *name)
29415 q = (const char *) strchr (name, '$');
29417 if (q == 0 || q == name)
29420 len = strlen (name);
29421 strip = XALLOCAVEC (char, len + 1);
29422 strcpy (strip, name);
29423 p = strip + (q - name);
29427 p = strchr (p + 1, '$');
29430 return ggc_alloc_string (strip, len);
29435 rs6000_output_symbol_ref (FILE *file, rtx x)
29437 const char *name = XSTR (x, 0);
29439 /* Currently C++ toc references to vtables can be emitted before it
29440 is decided whether the vtable is public or private. If this is
29441 the case, then the linker will eventually complain that there is
29442 a reference to an unknown section. Thus, for vtables only,
29443 we emit the TOC reference to reference the identifier and not the
29445 if (VTABLE_NAME_P (name))
29447 RS6000_OUTPUT_BASENAME (file, name);
29450 assemble_name (file, name);
29453 /* Output a TOC entry. We derive the entry name from what is being
29457 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29460 const char *name = buf;
29462 HOST_WIDE_INT offset = 0;
29464 gcc_assert (!TARGET_NO_TOC);
29466 /* When the linker won't eliminate them, don't output duplicate
29467 TOC entries (this happens on AIX if there is any kind of TOC,
29468 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29470 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29472 struct toc_hash_struct *h;
29474 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29475 time because GGC is not initialized at that point. */
29476 if (toc_hash_table == NULL)
29477 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29479 h = ggc_alloc<toc_hash_struct> ();
29481 h->key_mode = mode;
29482 h->labelno = labelno;
29484 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29485 if (*found == NULL)
29487 else /* This is indeed a duplicate.
29488 Set this label equal to that label. */
29490 fputs ("\t.set ", file);
29491 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29492 fprintf (file, "%d,", labelno);
29493 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29494 fprintf (file, "%d\n", ((*found)->labelno));
29497 if (TARGET_XCOFF && SYMBOL_REF_P (x)
29498 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29499 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29501 fputs ("\t.set ", file);
29502 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29503 fprintf (file, "%d,", labelno);
29504 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29505 fprintf (file, "%d\n", ((*found)->labelno));
29512 /* If we're going to put a double constant in the TOC, make sure it's
29513 aligned properly when strict alignment is on. */
29514 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29515 && STRICT_ALIGNMENT
29516 && GET_MODE_BITSIZE (mode) >= 64
29517 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29518 ASM_OUTPUT_ALIGN (file, 3);
29521 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29523 /* Handle FP constants specially. Note that if we have a minimal
29524 TOC, things we put here aren't actually in the TOC, so we can allow
29526 if (CONST_DOUBLE_P (x)
29527 && (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29528 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29532 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29533 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29535 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29539 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29540 fputs (DOUBLE_INT_ASM_OP, file);
29542 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29543 k[0] & 0xffffffff, k[1] & 0xffffffff,
29544 k[2] & 0xffffffff, k[3] & 0xffffffff);
29545 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29546 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29547 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29548 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29549 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29554 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29555 fputs ("\t.long ", file);
29557 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29558 k[0] & 0xffffffff, k[1] & 0xffffffff,
29559 k[2] & 0xffffffff, k[3] & 0xffffffff);
29560 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29561 k[0] & 0xffffffff, k[1] & 0xffffffff,
29562 k[2] & 0xffffffff, k[3] & 0xffffffff);
29566 else if (CONST_DOUBLE_P (x)
29567 && (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29571 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29572 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29574 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29578 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29579 fputs (DOUBLE_INT_ASM_OP, file);
29581 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29582 k[0] & 0xffffffff, k[1] & 0xffffffff);
29583 fprintf (file, "0x%lx%08lx\n",
29584 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29585 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29590 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29591 fputs ("\t.long ", file);
29593 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29594 k[0] & 0xffffffff, k[1] & 0xffffffff);
29595 fprintf (file, "0x%lx,0x%lx\n",
29596 k[0] & 0xffffffff, k[1] & 0xffffffff);
29600 else if (CONST_DOUBLE_P (x)
29601 && (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29605 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29606 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29608 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29612 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29613 fputs (DOUBLE_INT_ASM_OP, file);
29615 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29616 if (WORDS_BIG_ENDIAN)
29617 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29619 fprintf (file, "0x%lx\n", l & 0xffffffff);
29624 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29625 fputs ("\t.long ", file);
29627 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29628 fprintf (file, "0x%lx\n", l & 0xffffffff);
29632 else if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
29634 unsigned HOST_WIDE_INT low;
29635 HOST_WIDE_INT high;
29637 low = INTVAL (x) & 0xffffffff;
29638 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29640 /* TOC entries are always Pmode-sized, so when big-endian
29641 smaller integer constants in the TOC need to be padded.
29642 (This is still a win over putting the constants in
29643 a separate constant pool, because then we'd have
29644 to have both a TOC entry _and_ the actual constant.)
29646 For a 32-bit target, CONST_INT values are loaded and shifted
29647 entirely within `low' and can be stored in one TOC entry. */
29649 /* It would be easy to make this work, but it doesn't now. */
29650 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29652 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29655 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29656 high = (HOST_WIDE_INT) low >> 32;
29662 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29663 fputs (DOUBLE_INT_ASM_OP, file);
29665 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29666 (long) high & 0xffffffff, (long) low & 0xffffffff);
29667 fprintf (file, "0x%lx%08lx\n",
29668 (long) high & 0xffffffff, (long) low & 0xffffffff);
29673 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29675 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29676 fputs ("\t.long ", file);
29678 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29679 (long) high & 0xffffffff, (long) low & 0xffffffff);
29680 fprintf (file, "0x%lx,0x%lx\n",
29681 (long) high & 0xffffffff, (long) low & 0xffffffff);
29685 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29686 fputs ("\t.long ", file);
29688 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29689 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29695 if (GET_CODE (x) == CONST)
29697 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29698 && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
29700 base = XEXP (XEXP (x, 0), 0);
29701 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29704 switch (GET_CODE (base))
29707 name = XSTR (base, 0);
29711 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29712 CODE_LABEL_NUMBER (XEXP (base, 0)));
29716 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29720 gcc_unreachable ();
29723 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29724 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29727 fputs ("\t.tc ", file);
29728 RS6000_OUTPUT_BASENAME (file, name);
29731 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29733 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29735 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29736 after other TOC symbols, reducing overflow of small TOC access
29737 to [TC] symbols. */
29738 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29739 ? "[TE]," : "[TC],", file);
29742 /* Currently C++ toc references to vtables can be emitted before it
29743 is decided whether the vtable is public or private. If this is
29744 the case, then the linker will eventually complain that there is
29745 a TOC reference to an unknown section. Thus, for vtables only,
29746 we emit the TOC reference to reference the symbol and not the
29748 if (VTABLE_NAME_P (name))
29750 RS6000_OUTPUT_BASENAME (file, name);
29752 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29753 else if (offset > 0)
29754 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29757 output_addr_const (file, x);
29760 if (TARGET_XCOFF && SYMBOL_REF_P (base))
29762 switch (SYMBOL_REF_TLS_MODEL (base))
29766 case TLS_MODEL_LOCAL_EXEC:
29767 fputs ("@le", file);
29769 case TLS_MODEL_INITIAL_EXEC:
29770 fputs ("@ie", file);
29772 /* Use global-dynamic for local-dynamic. */
29773 case TLS_MODEL_GLOBAL_DYNAMIC:
29774 case TLS_MODEL_LOCAL_DYNAMIC:
29776 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29777 fputs ("\t.tc .", file);
29778 RS6000_OUTPUT_BASENAME (file, name);
29779 fputs ("[TC],", file);
29780 output_addr_const (file, x);
29781 fputs ("@m", file);
29784 gcc_unreachable ();
29792 /* Output an assembler pseudo-op to write an ASCII string of N characters
29793 starting at P to FILE.
29795 On the RS/6000, we have to do this using the .byte operation and
29796 write out special characters outside the quoted string.
29797 Also, the assembler is broken; very long strings are truncated,
29798 so we must artificially break them up early. */
29801 output_ascii (FILE *file, const char *p, int n)
29804 int i, count_string;
29805 const char *for_string = "\t.byte \"";
29806 const char *for_decimal = "\t.byte ";
29807 const char *to_close = NULL;
29810 for (i = 0; i < n; i++)
29813 if (c >= ' ' && c < 0177)
29816 fputs (for_string, file);
29819 /* Write two quotes to get one. */
29827 for_decimal = "\"\n\t.byte ";
29831 if (count_string >= 512)
29833 fputs (to_close, file);
29835 for_string = "\t.byte \"";
29836 for_decimal = "\t.byte ";
29844 fputs (for_decimal, file);
29845 fprintf (file, "%d", c);
29847 for_string = "\n\t.byte \"";
29848 for_decimal = ", ";
29854 /* Now close the string if we have written one. Then end the line. */
29856 fputs (to_close, file);
29859 /* Generate a unique section name for FILENAME for a section type
29860 represented by SECTION_DESC. Output goes into BUF.
29862 SECTION_DESC can be any string, as long as it is different for each
29863 possible section type.
29865 We name the section in the same manner as xlc. The name begins with an
29866 underscore followed by the filename (after stripping any leading directory
29867 names) with the last period replaced by the string SECTION_DESC. If
29868 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29872 rs6000_gen_section_name (char **buf, const char *filename,
29873 const char *section_desc)
29875 const char *q, *after_last_slash, *last_period = 0;
29879 after_last_slash = filename;
29880 for (q = filename; *q; q++)
29883 after_last_slash = q + 1;
29884 else if (*q == '.')
29888 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29889 *buf = (char *) xmalloc (len);
29894 for (q = after_last_slash; *q; q++)
29896 if (q == last_period)
29898 strcpy (p, section_desc);
29899 p += strlen (section_desc);
29903 else if (ISALNUM (*q))
29907 if (last_period == 0)
29908 strcpy (p, section_desc);
29913 /* Emit profile function. */
29916 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29918 /* Non-standard profiling for kernels, which just saves LR then calls
29919 _mcount without worrying about arg saves. The idea is to change
29920 the function prologue as little as possible as it isn't easy to
29921 account for arg save/restore code added just for _mcount. */
29922 if (TARGET_PROFILE_KERNEL)
29925 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29927 #ifndef NO_PROFILE_COUNTERS
29928 # define NO_PROFILE_COUNTERS 0
29930 if (NO_PROFILE_COUNTERS)
29931 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29932 LCT_NORMAL, VOIDmode);
29936 const char *label_name;
29939 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29940 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29941 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29943 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29944 LCT_NORMAL, VOIDmode, fun, Pmode);
29947 else if (DEFAULT_ABI == ABI_DARWIN)
29949 const char *mcount_name = RS6000_MCOUNT;
29950 int caller_addr_regno = LR_REGNO;
29952 /* Be conservative and always set this, at least for now. */
29953 crtl->uses_pic_offset_table = 1;
29956 /* For PIC code, set up a stub and collect the caller's address
29957 from r0, which is where the prologue puts it. */
29958 if (MACHOPIC_INDIRECT
29959 && crtl->uses_pic_offset_table)
29960 caller_addr_regno = 0;
29962 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29963 LCT_NORMAL, VOIDmode,
29964 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29968 /* Write function profiler code. */
29971 output_function_profiler (FILE *file, int labelno)
29975 switch (DEFAULT_ABI)
29978 gcc_unreachable ();
29983 warning (0, "no profiling of 64-bit code for this ABI");
29986 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29987 fprintf (file, "\tmflr %s\n", reg_names[0]);
29988 if (NO_PROFILE_COUNTERS)
29990 asm_fprintf (file, "\tstw %s,4(%s)\n",
29991 reg_names[0], reg_names[1]);
29993 else if (TARGET_SECURE_PLT && flag_pic)
29995 if (TARGET_LINK_STACK)
29998 get_ppc476_thunk_name (name);
29999 asm_fprintf (file, "\tbl %s\n", name);
30002 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30003 asm_fprintf (file, "\tstw %s,4(%s)\n",
30004 reg_names[0], reg_names[1]);
30005 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30006 asm_fprintf (file, "\taddis %s,%s,",
30007 reg_names[12], reg_names[12]);
30008 assemble_name (file, buf);
30009 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30010 assemble_name (file, buf);
30011 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30013 else if (flag_pic == 1)
30015 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30016 asm_fprintf (file, "\tstw %s,4(%s)\n",
30017 reg_names[0], reg_names[1]);
30018 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30019 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30020 assemble_name (file, buf);
30021 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30023 else if (flag_pic > 1)
30025 asm_fprintf (file, "\tstw %s,4(%s)\n",
30026 reg_names[0], reg_names[1]);
30027 /* Now, we need to get the address of the label. */
30028 if (TARGET_LINK_STACK)
30031 get_ppc476_thunk_name (name);
30032 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30033 assemble_name (file, buf);
30034 fputs ("-.\n1:", file);
30035 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30036 asm_fprintf (file, "\taddi %s,%s,4\n",
30037 reg_names[11], reg_names[11]);
30041 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30042 assemble_name (file, buf);
30043 fputs ("-.\n1:", file);
30044 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30046 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30047 reg_names[0], reg_names[11]);
30048 asm_fprintf (file, "\tadd %s,%s,%s\n",
30049 reg_names[0], reg_names[0], reg_names[11]);
30053 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30054 assemble_name (file, buf);
30055 fputs ("@ha\n", file);
30056 asm_fprintf (file, "\tstw %s,4(%s)\n",
30057 reg_names[0], reg_names[1]);
30058 asm_fprintf (file, "\tla %s,", reg_names[0]);
30059 assemble_name (file, buf);
30060 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30063 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30064 fprintf (file, "\tbl %s%s\n",
30065 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30071 /* Don't do anything, done in output_profile_hook (). */
30078 /* The following variable value is the last issued insn. */
30080 static rtx_insn *last_scheduled_insn;
30082 /* The following variable helps to balance issuing of load and
30083 store instructions */
30085 static int load_store_pendulum;
30087 /* The following variable helps pair divide insns during scheduling. */
30088 static int divide_cnt;
30089 /* The following variable helps pair and alternate vector and vector load
30090 insns during scheduling. */
30091 static int vec_pairing;
30094 /* Power4 load update and store update instructions are cracked into a
30095 load or store and an integer insn which are executed in the same cycle.
30096 Branches have their own dispatch slot which does not count against the
30097 GCC issue rate, but it changes the program flow so there are no other
30098 instructions to issue in this cycle. */
30101 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30103 last_scheduled_insn = insn;
30104 if (GET_CODE (PATTERN (insn)) == USE
30105 || GET_CODE (PATTERN (insn)) == CLOBBER)
30107 cached_can_issue_more = more;
30108 return cached_can_issue_more;
30111 if (insn_terminates_group_p (insn, current_group))
30113 cached_can_issue_more = 0;
30114 return cached_can_issue_more;
30117 /* If no reservation, but reach here */
30118 if (recog_memoized (insn) < 0)
30121 if (rs6000_sched_groups)
30123 if (is_microcoded_insn (insn))
30124 cached_can_issue_more = 0;
30125 else if (is_cracked_insn (insn))
30126 cached_can_issue_more = more > 2 ? more - 2 : 0;
30128 cached_can_issue_more = more - 1;
30130 return cached_can_issue_more;
30133 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30136 cached_can_issue_more = more - 1;
30137 return cached_can_issue_more;
30141 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30143 int r = rs6000_variable_issue_1 (insn, more);
30145 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30149 /* Adjust the cost of a scheduling dependency. Return the new cost of
30150 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30153 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30156 enum attr_type attr_type;
30158 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30165 /* Data dependency; DEP_INSN writes a register that INSN reads
30166 some cycles later. */
30168 /* Separate a load from a narrower, dependent store. */
30169 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30170 && GET_CODE (PATTERN (insn)) == SET
30171 && GET_CODE (PATTERN (dep_insn)) == SET
30172 && MEM_P (XEXP (PATTERN (insn), 1))
30173 && MEM_P (XEXP (PATTERN (dep_insn), 0))
30174 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30175 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30178 attr_type = get_attr_type (insn);
30183 /* Tell the first scheduling pass about the latency between
30184 a mtctr and bctr (and mtlr and br/blr). The first
30185 scheduling pass will not know about this latency since
30186 the mtctr instruction, which has the latency associated
30187 to it, will be generated by reload. */
30190 /* Leave some extra cycles between a compare and its
30191 dependent branch, to inhibit expensive mispredicts. */
30192 if ((rs6000_tune == PROCESSOR_PPC603
30193 || rs6000_tune == PROCESSOR_PPC604
30194 || rs6000_tune == PROCESSOR_PPC604e
30195 || rs6000_tune == PROCESSOR_PPC620
30196 || rs6000_tune == PROCESSOR_PPC630
30197 || rs6000_tune == PROCESSOR_PPC750
30198 || rs6000_tune == PROCESSOR_PPC7400
30199 || rs6000_tune == PROCESSOR_PPC7450
30200 || rs6000_tune == PROCESSOR_PPCE5500
30201 || rs6000_tune == PROCESSOR_PPCE6500
30202 || rs6000_tune == PROCESSOR_POWER4
30203 || rs6000_tune == PROCESSOR_POWER5
30204 || rs6000_tune == PROCESSOR_POWER7
30205 || rs6000_tune == PROCESSOR_POWER8
30206 || rs6000_tune == PROCESSOR_POWER9
30207 || rs6000_tune == PROCESSOR_CELL)
30208 && recog_memoized (dep_insn)
30209 && (INSN_CODE (dep_insn) >= 0))
30211 switch (get_attr_type (dep_insn))
30214 case TYPE_FPCOMPARE:
30215 case TYPE_CR_LOGICAL:
30219 if (get_attr_dot (dep_insn) == DOT_YES)
30224 if (get_attr_dot (dep_insn) == DOT_YES
30225 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30236 if ((rs6000_tune == PROCESSOR_POWER6)
30237 && recog_memoized (dep_insn)
30238 && (INSN_CODE (dep_insn) >= 0))
30241 if (GET_CODE (PATTERN (insn)) != SET)
30242 /* If this happens, we have to extend this to schedule
30243 optimally. Return default for now. */
30246 /* Adjust the cost for the case where the value written
30247 by a fixed point operation is used as the address
30248 gen value on a store. */
30249 switch (get_attr_type (dep_insn))
30254 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30255 return get_attr_sign_extend (dep_insn)
30256 == SIGN_EXTEND_YES ? 6 : 4;
30261 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30262 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30272 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30280 if (get_attr_update (dep_insn) == UPDATE_YES
30281 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30287 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30293 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30294 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30304 if ((rs6000_tune == PROCESSOR_POWER6)
30305 && recog_memoized (dep_insn)
30306 && (INSN_CODE (dep_insn) >= 0))
30309 /* Adjust the cost for the case where the value written
30310 by a fixed point instruction is used within the address
30311 gen portion of a subsequent load(u)(x) */
30312 switch (get_attr_type (dep_insn))
30317 if (set_to_load_agen (dep_insn, insn))
30318 return get_attr_sign_extend (dep_insn)
30319 == SIGN_EXTEND_YES ? 6 : 4;
30324 if (set_to_load_agen (dep_insn, insn))
30325 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30335 if (set_to_load_agen (dep_insn, insn))
30343 if (get_attr_update (dep_insn) == UPDATE_YES
30344 && set_to_load_agen (dep_insn, insn))
30350 if (set_to_load_agen (dep_insn, insn))
30356 if (set_to_load_agen (dep_insn, insn))
30357 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30367 if ((rs6000_tune == PROCESSOR_POWER6)
30368 && get_attr_update (insn) == UPDATE_NO
30369 && recog_memoized (dep_insn)
30370 && (INSN_CODE (dep_insn) >= 0)
30371 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30378 /* Fall out to return default cost. */
30382 case REG_DEP_OUTPUT:
30383 /* Output dependency; DEP_INSN writes a register that INSN writes some
30385 if ((rs6000_tune == PROCESSOR_POWER6)
30386 && recog_memoized (dep_insn)
30387 && (INSN_CODE (dep_insn) >= 0))
30389 attr_type = get_attr_type (insn);
30394 case TYPE_FPSIMPLE:
30395 if (get_attr_type (dep_insn) == TYPE_FP
30396 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30400 if (get_attr_update (insn) == UPDATE_NO
30401 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30408 /* Fall through, no cost for output dependency. */
30412 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30417 gcc_unreachable ();
30423 /* Debug version of rs6000_adjust_cost. */
30426 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30427 int cost, unsigned int dw)
30429 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30437 default: dep = "unknown depencency"; break;
30438 case REG_DEP_TRUE: dep = "data dependency"; break;
30439 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30440 case REG_DEP_ANTI: dep = "anti depencency"; break;
30444 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30445 "%s, insn:\n", ret, cost, dep);
30453 /* The function returns a true if INSN is microcoded.
30454 Return false otherwise. */
30457 is_microcoded_insn (rtx_insn *insn)
30459 if (!insn || !NONDEBUG_INSN_P (insn)
30460 || GET_CODE (PATTERN (insn)) == USE
30461 || GET_CODE (PATTERN (insn)) == CLOBBER)
30464 if (rs6000_tune == PROCESSOR_CELL)
30465 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30467 if (rs6000_sched_groups
30468 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30470 enum attr_type type = get_attr_type (insn);
30471 if ((type == TYPE_LOAD
30472 && get_attr_update (insn) == UPDATE_YES
30473 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30474 || ((type == TYPE_LOAD || type == TYPE_STORE)
30475 && get_attr_update (insn) == UPDATE_YES
30476 && get_attr_indexed (insn) == INDEXED_YES)
30477 || type == TYPE_MFCR)
30484 /* The function returns true if INSN is cracked into 2 instructions
30485 by the processor (and therefore occupies 2 issue slots). */
30488 is_cracked_insn (rtx_insn *insn)
30490 if (!insn || !NONDEBUG_INSN_P (insn)
30491 || GET_CODE (PATTERN (insn)) == USE
30492 || GET_CODE (PATTERN (insn)) == CLOBBER)
30495 if (rs6000_sched_groups
30496 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30498 enum attr_type type = get_attr_type (insn);
30499 if ((type == TYPE_LOAD
30500 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30501 && get_attr_update (insn) == UPDATE_NO)
30502 || (type == TYPE_LOAD
30503 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30504 && get_attr_update (insn) == UPDATE_YES
30505 && get_attr_indexed (insn) == INDEXED_NO)
30506 || (type == TYPE_STORE
30507 && get_attr_update (insn) == UPDATE_YES
30508 && get_attr_indexed (insn) == INDEXED_NO)
30509 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30510 && get_attr_update (insn) == UPDATE_YES)
30511 || (type == TYPE_CR_LOGICAL
30512 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30513 || (type == TYPE_EXTS
30514 && get_attr_dot (insn) == DOT_YES)
30515 || (type == TYPE_SHIFT
30516 && get_attr_dot (insn) == DOT_YES
30517 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30518 || (type == TYPE_MUL
30519 && get_attr_dot (insn) == DOT_YES)
30520 || type == TYPE_DIV
30521 || (type == TYPE_INSERT
30522 && get_attr_size (insn) == SIZE_32))
30529 /* The function returns true if INSN can be issued only from
30530 the branch slot. */
30533 is_branch_slot_insn (rtx_insn *insn)
30535 if (!insn || !NONDEBUG_INSN_P (insn)
30536 || GET_CODE (PATTERN (insn)) == USE
30537 || GET_CODE (PATTERN (insn)) == CLOBBER)
30540 if (rs6000_sched_groups)
30542 enum attr_type type = get_attr_type (insn);
30543 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30551 /* The function returns true if out_inst sets a value that is
30552 used in the address generation computation of in_insn */
30554 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30556 rtx out_set, in_set;
30558 /* For performance reasons, only handle the simple case where
30559 both loads are a single_set. */
30560 out_set = single_set (out_insn);
30563 in_set = single_set (in_insn);
30565 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30571 /* Try to determine base/offset/size parts of the given MEM.
30572 Return true if successful, false if all the values couldn't
30575 This function only looks for REG or REG+CONST address forms.
30576 REG+REG address form will return false. */
30579 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30580 HOST_WIDE_INT *size)
30583 if MEM_SIZE_KNOWN_P (mem)
30584 *size = MEM_SIZE (mem);
30588 addr_rtx = (XEXP (mem, 0));
30589 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30590 addr_rtx = XEXP (addr_rtx, 1);
30593 while (GET_CODE (addr_rtx) == PLUS
30594 && CONST_INT_P (XEXP (addr_rtx, 1)))
30596 *offset += INTVAL (XEXP (addr_rtx, 1));
30597 addr_rtx = XEXP (addr_rtx, 0);
30599 if (!REG_P (addr_rtx))
30606 /* The function returns true if the target storage location of
30607 mem1 is adjacent to the target storage location of mem2 */
30608 /* Return 1 if memory locations are adjacent. */
30611 adjacent_mem_locations (rtx mem1, rtx mem2)
30614 HOST_WIDE_INT off1, size1, off2, size2;
30616 if (get_memref_parts (mem1, ®1, &off1, &size1)
30617 && get_memref_parts (mem2, ®2, &off2, &size2))
30618 return ((REGNO (reg1) == REGNO (reg2))
30619 && ((off1 + size1 == off2)
30620 || (off2 + size2 == off1)));
30625 /* This function returns true if it can be determined that the two MEM
30626 locations overlap by at least 1 byte based on base reg/offset/size. */
30629 mem_locations_overlap (rtx mem1, rtx mem2)
30632 HOST_WIDE_INT off1, size1, off2, size2;
30634 if (get_memref_parts (mem1, ®1, &off1, &size1)
30635 && get_memref_parts (mem2, ®2, &off2, &size2))
30636 return ((REGNO (reg1) == REGNO (reg2))
30637 && (((off1 <= off2) && (off1 + size1 > off2))
30638 || ((off2 <= off1) && (off2 + size2 > off1))));
30643 /* A C statement (sans semicolon) to update the integer scheduling
30644 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30645 INSN earlier, reduce the priority to execute INSN later. Do not
30646 define this macro if you do not need to adjust the scheduling
30647 priorities of insns. */
30650 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30652 rtx load_mem, str_mem;
30653 /* On machines (like the 750) which have asymmetric integer units,
30654 where one integer unit can do multiply and divides and the other
30655 can't, reduce the priority of multiply/divide so it is scheduled
30656 before other integer operations. */
30659 if (! INSN_P (insn))
30662 if (GET_CODE (PATTERN (insn)) == USE)
30665 switch (rs6000_tune) {
30666 case PROCESSOR_PPC750:
30667 switch (get_attr_type (insn))
30674 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30675 priority, priority);
30676 if (priority >= 0 && priority < 0x01000000)
30683 if (insn_must_be_first_in_group (insn)
30684 && reload_completed
30685 && current_sched_info->sched_max_insns_priority
30686 && rs6000_sched_restricted_insns_priority)
30689 /* Prioritize insns that can be dispatched only in the first
30691 if (rs6000_sched_restricted_insns_priority == 1)
30692 /* Attach highest priority to insn. This means that in
30693 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30694 precede 'priority' (critical path) considerations. */
30695 return current_sched_info->sched_max_insns_priority;
30696 else if (rs6000_sched_restricted_insns_priority == 2)
30697 /* Increase priority of insn by a minimal amount. This means that in
30698 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30699 considerations precede dispatch-slot restriction considerations. */
30700 return (priority + 1);
30703 if (rs6000_tune == PROCESSOR_POWER6
30704 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30705 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30706 /* Attach highest priority to insn if the scheduler has just issued two
30707 stores and this instruction is a load, or two loads and this instruction
30708 is a store. Power6 wants loads and stores scheduled alternately
30710 return current_sched_info->sched_max_insns_priority;
30715 /* Return true if the instruction is nonpipelined on the Cell. */
30717 is_nonpipeline_insn (rtx_insn *insn)
30719 enum attr_type type;
30720 if (!insn || !NONDEBUG_INSN_P (insn)
30721 || GET_CODE (PATTERN (insn)) == USE
30722 || GET_CODE (PATTERN (insn)) == CLOBBER)
30725 type = get_attr_type (insn);
30726 if (type == TYPE_MUL
30727 || type == TYPE_DIV
30728 || type == TYPE_SDIV
30729 || type == TYPE_DDIV
30730 || type == TYPE_SSQRT
30731 || type == TYPE_DSQRT
30732 || type == TYPE_MFCR
30733 || type == TYPE_MFCRF
30734 || type == TYPE_MFJMPR)
30742 /* Return how many instructions the machine can issue per cycle. */
30745 rs6000_issue_rate (void)
30747 /* Unless scheduling for register pressure, use issue rate of 1 for
30748 first scheduling pass to decrease degradation. */
30749 if (!reload_completed && !flag_sched_pressure)
30752 switch (rs6000_tune) {
30753 case PROCESSOR_RS64A:
30754 case PROCESSOR_PPC601: /* ? */
30755 case PROCESSOR_PPC7450:
30757 case PROCESSOR_PPC440:
30758 case PROCESSOR_PPC603:
30759 case PROCESSOR_PPC750:
30760 case PROCESSOR_PPC7400:
30761 case PROCESSOR_PPC8540:
30762 case PROCESSOR_PPC8548:
30763 case PROCESSOR_CELL:
30764 case PROCESSOR_PPCE300C2:
30765 case PROCESSOR_PPCE300C3:
30766 case PROCESSOR_PPCE500MC:
30767 case PROCESSOR_PPCE500MC64:
30768 case PROCESSOR_PPCE5500:
30769 case PROCESSOR_PPCE6500:
30770 case PROCESSOR_TITAN:
30772 case PROCESSOR_PPC476:
30773 case PROCESSOR_PPC604:
30774 case PROCESSOR_PPC604e:
30775 case PROCESSOR_PPC620:
30776 case PROCESSOR_PPC630:
30778 case PROCESSOR_POWER4:
30779 case PROCESSOR_POWER5:
30780 case PROCESSOR_POWER6:
30781 case PROCESSOR_POWER7:
30783 case PROCESSOR_POWER8:
30785 case PROCESSOR_POWER9:
30792 /* Return how many instructions to look ahead for better insn
30796 rs6000_use_sched_lookahead (void)
30798 switch (rs6000_tune)
30800 case PROCESSOR_PPC8540:
30801 case PROCESSOR_PPC8548:
30804 case PROCESSOR_CELL:
30805 return (reload_completed ? 8 : 0);
30812 /* We are choosing insn from the ready queue. Return zero if INSN can be
30815 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30817 if (ready_index == 0)
30820 if (rs6000_tune != PROCESSOR_CELL)
30823 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30825 if (!reload_completed
30826 || is_nonpipeline_insn (insn)
30827 || is_microcoded_insn (insn))
30833 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30834 and return true. */
30837 find_mem_ref (rtx pat, rtx *mem_ref)
30842 /* stack_tie does not produce any real memory traffic. */
30843 if (tie_operand (pat, VOIDmode))
30852 /* Recursively process the pattern. */
30853 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30855 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30859 if (find_mem_ref (XEXP (pat, i), mem_ref))
30862 else if (fmt[i] == 'E')
30863 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30865 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30873 /* Determine if PAT is a PATTERN of a load insn. */
30876 is_load_insn1 (rtx pat, rtx *load_mem)
30878 if (!pat || pat == NULL_RTX)
30881 if (GET_CODE (pat) == SET)
30882 return find_mem_ref (SET_SRC (pat), load_mem);
30884 if (GET_CODE (pat) == PARALLEL)
30888 for (i = 0; i < XVECLEN (pat, 0); i++)
30889 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30896 /* Determine if INSN loads from memory. */
30899 is_load_insn (rtx insn, rtx *load_mem)
30901 if (!insn || !INSN_P (insn))
30907 return is_load_insn1 (PATTERN (insn), load_mem);
30910 /* Determine if PAT is a PATTERN of a store insn. */
30913 is_store_insn1 (rtx pat, rtx *str_mem)
30915 if (!pat || pat == NULL_RTX)
30918 if (GET_CODE (pat) == SET)
30919 return find_mem_ref (SET_DEST (pat), str_mem);
30921 if (GET_CODE (pat) == PARALLEL)
30925 for (i = 0; i < XVECLEN (pat, 0); i++)
30926 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30933 /* Determine if INSN stores to memory. */
30936 is_store_insn (rtx insn, rtx *str_mem)
30938 if (!insn || !INSN_P (insn))
30941 return is_store_insn1 (PATTERN (insn), str_mem);
30944 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30947 is_power9_pairable_vec_type (enum attr_type type)
30951 case TYPE_VECSIMPLE:
30952 case TYPE_VECCOMPLEX:
30956 case TYPE_VECFLOAT:
30958 case TYPE_VECDOUBLE:
30966 /* Returns whether the dependence between INSN and NEXT is considered
30967 costly by the given target. */
30970 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30974 rtx load_mem, str_mem;
30976 /* If the flag is not enabled - no dependence is considered costly;
30977 allow all dependent insns in the same group.
30978 This is the most aggressive option. */
30979 if (rs6000_sched_costly_dep == no_dep_costly)
30982 /* If the flag is set to 1 - a dependence is always considered costly;
30983 do not allow dependent instructions in the same group.
30984 This is the most conservative option. */
30985 if (rs6000_sched_costly_dep == all_deps_costly)
30988 insn = DEP_PRO (dep);
30989 next = DEP_CON (dep);
30991 if (rs6000_sched_costly_dep == store_to_load_dep_costly
30992 && is_load_insn (next, &load_mem)
30993 && is_store_insn (insn, &str_mem))
30994 /* Prevent load after store in the same group. */
30997 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
30998 && is_load_insn (next, &load_mem)
30999 && is_store_insn (insn, &str_mem)
31000 && DEP_TYPE (dep) == REG_DEP_TRUE
31001 && mem_locations_overlap(str_mem, load_mem))
31002 /* Prevent load after store in the same group if it is a true
31006 /* The flag is set to X; dependences with latency >= X are considered costly,
31007 and will not be scheduled in the same group. */
31008 if (rs6000_sched_costly_dep <= max_dep_latency
31009 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31015 /* Return the next insn after INSN that is found before TAIL is reached,
31016 skipping any "non-active" insns - insns that will not actually occupy
31017 an issue slot. Return NULL_RTX if such an insn is not found. */
31020 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31022 if (insn == NULL_RTX || insn == tail)
31027 insn = NEXT_INSN (insn);
31028 if (insn == NULL_RTX || insn == tail)
31032 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31033 || (NONJUMP_INSN_P (insn)
31034 && GET_CODE (PATTERN (insn)) != USE
31035 && GET_CODE (PATTERN (insn)) != CLOBBER
31036 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31042 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31045 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31050 enum attr_type type, type2;
31052 type = get_attr_type (last_scheduled_insn);
31054 /* Try to issue fixed point divides back-to-back in pairs so they will be
31055 routed to separate execution units and execute in parallel. */
31056 if (type == TYPE_DIV && divide_cnt == 0)
31058 /* First divide has been scheduled. */
31061 /* Scan the ready list looking for another divide, if found move it
31062 to the end of the list so it is chosen next. */
31066 if (recog_memoized (ready[pos]) >= 0
31067 && get_attr_type (ready[pos]) == TYPE_DIV)
31070 for (i = pos; i < lastpos; i++)
31071 ready[i] = ready[i + 1];
31072 ready[lastpos] = tmp;
31080 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31083 /* The best dispatch throughput for vector and vector load insns can be
31084 achieved by interleaving a vector and vector load such that they'll
31085 dispatch to the same superslice. If this pairing cannot be achieved
31086 then it is best to pair vector insns together and vector load insns
31089 To aid in this pairing, vec_pairing maintains the current state with
31090 the following values:
31092 0 : Initial state, no vecload/vector pairing has been started.
31094 1 : A vecload or vector insn has been issued and a candidate for
31095 pairing has been found and moved to the end of the ready
31097 if (type == TYPE_VECLOAD)
31099 /* Issued a vecload. */
31100 if (vec_pairing == 0)
31102 int vecload_pos = -1;
31103 /* We issued a single vecload, look for a vector insn to pair it
31104 with. If one isn't found, try to pair another vecload. */
31108 if (recog_memoized (ready[pos]) >= 0)
31110 type2 = get_attr_type (ready[pos]);
31111 if (is_power9_pairable_vec_type (type2))
31113 /* Found a vector insn to pair with, move it to the
31114 end of the ready list so it is scheduled next. */
31116 for (i = pos; i < lastpos; i++)
31117 ready[i] = ready[i + 1];
31118 ready[lastpos] = tmp;
31120 return cached_can_issue_more;
31122 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31123 /* Remember position of first vecload seen. */
31128 if (vecload_pos >= 0)
31130 /* Didn't find a vector to pair with but did find a vecload,
31131 move it to the end of the ready list. */
31132 tmp = ready[vecload_pos];
31133 for (i = vecload_pos; i < lastpos; i++)
31134 ready[i] = ready[i + 1];
31135 ready[lastpos] = tmp;
31137 return cached_can_issue_more;
31141 else if (is_power9_pairable_vec_type (type))
31143 /* Issued a vector operation. */
31144 if (vec_pairing == 0)
31147 /* We issued a single vector insn, look for a vecload to pair it
31148 with. If one isn't found, try to pair another vector. */
31152 if (recog_memoized (ready[pos]) >= 0)
31154 type2 = get_attr_type (ready[pos]);
31155 if (type2 == TYPE_VECLOAD)
31157 /* Found a vecload insn to pair with, move it to the
31158 end of the ready list so it is scheduled next. */
31160 for (i = pos; i < lastpos; i++)
31161 ready[i] = ready[i + 1];
31162 ready[lastpos] = tmp;
31164 return cached_can_issue_more;
31166 else if (is_power9_pairable_vec_type (type2)
31168 /* Remember position of first vector insn seen. */
31175 /* Didn't find a vecload to pair with but did find a vector
31176 insn, move it to the end of the ready list. */
31177 tmp = ready[vec_pos];
31178 for (i = vec_pos; i < lastpos; i++)
31179 ready[i] = ready[i + 1];
31180 ready[lastpos] = tmp;
31182 return cached_can_issue_more;
31187 /* We've either finished a vec/vecload pair, couldn't find an insn to
31188 continue the current pair, or the last insn had nothing to do with
31189 with pairing. In any case, reset the state. */
31193 return cached_can_issue_more;
31196 /* We are about to begin issuing insns for this clock cycle. */
31199 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31200 rtx_insn **ready ATTRIBUTE_UNUSED,
31201 int *pn_ready ATTRIBUTE_UNUSED,
31202 int clock_var ATTRIBUTE_UNUSED)
31204 int n_ready = *pn_ready;
31207 fprintf (dump, "// rs6000_sched_reorder :\n");
31209 /* Reorder the ready list, if the second to last ready insn
31210 is a nonepipeline insn. */
31211 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31213 if (is_nonpipeline_insn (ready[n_ready - 1])
31214 && (recog_memoized (ready[n_ready - 2]) > 0))
31215 /* Simply swap first two insns. */
31216 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31219 if (rs6000_tune == PROCESSOR_POWER6)
31220 load_store_pendulum = 0;
31222 return rs6000_issue_rate ();
31225 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31228 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31229 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31232 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31234 /* For Power6, we need to handle some special cases to try and keep the
31235 store queue from overflowing and triggering expensive flushes.
31237 This code monitors how load and store instructions are being issued
31238 and skews the ready list one way or the other to increase the likelihood
31239 that a desired instruction is issued at the proper time.
31241 A couple of things are done. First, we maintain a "load_store_pendulum"
31242 to track the current state of load/store issue.
31244 - If the pendulum is at zero, then no loads or stores have been
31245 issued in the current cycle so we do nothing.
31247 - If the pendulum is 1, then a single load has been issued in this
31248 cycle and we attempt to locate another load in the ready list to
31251 - If the pendulum is -2, then two stores have already been
31252 issued in this cycle, so we increase the priority of the first load
31253 in the ready list to increase it's likelihood of being chosen first
31256 - If the pendulum is -1, then a single store has been issued in this
31257 cycle and we attempt to locate another store in the ready list to
31258 issue with it, preferring a store to an adjacent memory location to
31259 facilitate store pairing in the store queue.
31261 - If the pendulum is 2, then two loads have already been
31262 issued in this cycle, so we increase the priority of the first store
31263 in the ready list to increase it's likelihood of being chosen first
31266 - If the pendulum < -2 or > 2, then do nothing.
31268 Note: This code covers the most common scenarios. There exist non
31269 load/store instructions which make use of the LSU and which
31270 would need to be accounted for to strictly model the behavior
31271 of the machine. Those instructions are currently unaccounted
31272 for to help minimize compile time overhead of this code.
31274 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31279 rtx load_mem, str_mem;
31281 if (is_store_insn (last_scheduled_insn, &str_mem))
31282 /* Issuing a store, swing the load_store_pendulum to the left */
31283 load_store_pendulum--;
31284 else if (is_load_insn (last_scheduled_insn, &load_mem))
31285 /* Issuing a load, swing the load_store_pendulum to the right */
31286 load_store_pendulum++;
31288 return cached_can_issue_more;
31290 /* If the pendulum is balanced, or there is only one instruction on
31291 the ready list, then all is well, so return. */
31292 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31293 return cached_can_issue_more;
31295 if (load_store_pendulum == 1)
31297 /* A load has been issued in this cycle. Scan the ready list
31298 for another load to issue with it */
31303 if (is_load_insn (ready[pos], &load_mem))
31305 /* Found a load. Move it to the head of the ready list,
31306 and adjust it's priority so that it is more likely to
31309 for (i=pos; i<*pn_ready-1; i++)
31310 ready[i] = ready[i + 1];
31311 ready[*pn_ready-1] = tmp;
31313 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31314 INSN_PRIORITY (tmp)++;
31320 else if (load_store_pendulum == -2)
31322 /* Two stores have been issued in this cycle. Increase the
31323 priority of the first load in the ready list to favor it for
31324 issuing in the next cycle. */
31329 if (is_load_insn (ready[pos], &load_mem)
31331 && INSN_PRIORITY_KNOWN (ready[pos]))
31333 INSN_PRIORITY (ready[pos])++;
31335 /* Adjust the pendulum to account for the fact that a load
31336 was found and increased in priority. This is to prevent
31337 increasing the priority of multiple loads */
31338 load_store_pendulum--;
31345 else if (load_store_pendulum == -1)
31347 /* A store has been issued in this cycle. Scan the ready list for
31348 another store to issue with it, preferring a store to an adjacent
31350 int first_store_pos = -1;
31356 if (is_store_insn (ready[pos], &str_mem))
31359 /* Maintain the index of the first store found on the
31361 if (first_store_pos == -1)
31362 first_store_pos = pos;
31364 if (is_store_insn (last_scheduled_insn, &str_mem2)
31365 && adjacent_mem_locations (str_mem, str_mem2))
31367 /* Found an adjacent store. Move it to the head of the
31368 ready list, and adjust it's priority so that it is
31369 more likely to stay there */
31371 for (i=pos; i<*pn_ready-1; i++)
31372 ready[i] = ready[i + 1];
31373 ready[*pn_ready-1] = tmp;
31375 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31376 INSN_PRIORITY (tmp)++;
31378 first_store_pos = -1;
31386 if (first_store_pos >= 0)
31388 /* An adjacent store wasn't found, but a non-adjacent store was,
31389 so move the non-adjacent store to the front of the ready
31390 list, and adjust its priority so that it is more likely to
31392 tmp = ready[first_store_pos];
31393 for (i=first_store_pos; i<*pn_ready-1; i++)
31394 ready[i] = ready[i + 1];
31395 ready[*pn_ready-1] = tmp;
31396 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31397 INSN_PRIORITY (tmp)++;
31400 else if (load_store_pendulum == 2)
31402 /* Two loads have been issued in this cycle. Increase the priority
31403 of the first store in the ready list to favor it for issuing in
31409 if (is_store_insn (ready[pos], &str_mem)
31411 && INSN_PRIORITY_KNOWN (ready[pos]))
31413 INSN_PRIORITY (ready[pos])++;
31415 /* Adjust the pendulum to account for the fact that a store
31416 was found and increased in priority. This is to prevent
31417 increasing the priority of multiple stores */
31418 load_store_pendulum++;
31427 /* Do Power9 dependent reordering if necessary. */
31428 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31429 && recog_memoized (last_scheduled_insn) >= 0)
31430 return power9_sched_reorder2 (ready, *pn_ready - 1);
31432 return cached_can_issue_more;
31435 /* Return whether the presence of INSN causes a dispatch group termination
31436 of group WHICH_GROUP.
31438 If WHICH_GROUP == current_group, this function will return true if INSN
31439 causes the termination of the current group (i.e, the dispatch group to
31440 which INSN belongs). This means that INSN will be the last insn in the
31441 group it belongs to.
31443 If WHICH_GROUP == previous_group, this function will return true if INSN
31444 causes the termination of the previous group (i.e, the dispatch group that
31445 precedes the group to which INSN belongs). This means that INSN will be
31446 the first insn in the group it belongs to). */
31449 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31456 first = insn_must_be_first_in_group (insn);
31457 last = insn_must_be_last_in_group (insn);
31462 if (which_group == current_group)
31464 else if (which_group == previous_group)
31472 insn_must_be_first_in_group (rtx_insn *insn)
31474 enum attr_type type;
31478 || DEBUG_INSN_P (insn)
31479 || GET_CODE (PATTERN (insn)) == USE
31480 || GET_CODE (PATTERN (insn)) == CLOBBER)
31483 switch (rs6000_tune)
31485 case PROCESSOR_POWER5:
31486 if (is_cracked_insn (insn))
31489 case PROCESSOR_POWER4:
31490 if (is_microcoded_insn (insn))
31493 if (!rs6000_sched_groups)
31496 type = get_attr_type (insn);
31503 case TYPE_CR_LOGICAL:
31516 case PROCESSOR_POWER6:
31517 type = get_attr_type (insn);
31526 case TYPE_FPCOMPARE:
31537 if (get_attr_dot (insn) == DOT_NO
31538 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31543 if (get_attr_size (insn) == SIZE_32)
31551 if (get_attr_update (insn) == UPDATE_YES)
31559 case PROCESSOR_POWER7:
31560 type = get_attr_type (insn);
31564 case TYPE_CR_LOGICAL:
31578 if (get_attr_dot (insn) == DOT_YES)
31583 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31584 || get_attr_update (insn) == UPDATE_YES)
31591 if (get_attr_update (insn) == UPDATE_YES)
31599 case PROCESSOR_POWER8:
31600 type = get_attr_type (insn);
31604 case TYPE_CR_LOGICAL:
31612 case TYPE_VECSTORE:
31619 if (get_attr_dot (insn) == DOT_YES)
31624 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31625 || get_attr_update (insn) == UPDATE_YES)
31630 if (get_attr_update (insn) == UPDATE_YES
31631 && get_attr_indexed (insn) == INDEXED_YES)
31647 insn_must_be_last_in_group (rtx_insn *insn)
31649 enum attr_type type;
31653 || DEBUG_INSN_P (insn)
31654 || GET_CODE (PATTERN (insn)) == USE
31655 || GET_CODE (PATTERN (insn)) == CLOBBER)
31658 switch (rs6000_tune) {
31659 case PROCESSOR_POWER4:
31660 case PROCESSOR_POWER5:
31661 if (is_microcoded_insn (insn))
31664 if (is_branch_slot_insn (insn))
31668 case PROCESSOR_POWER6:
31669 type = get_attr_type (insn);
31677 case TYPE_FPCOMPARE:
31688 if (get_attr_dot (insn) == DOT_NO
31689 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31694 if (get_attr_size (insn) == SIZE_32)
31702 case PROCESSOR_POWER7:
31703 type = get_attr_type (insn);
31713 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31714 && get_attr_update (insn) == UPDATE_YES)
31719 if (get_attr_update (insn) == UPDATE_YES
31720 && get_attr_indexed (insn) == INDEXED_YES)
31728 case PROCESSOR_POWER8:
31729 type = get_attr_type (insn);
31741 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31742 && get_attr_update (insn) == UPDATE_YES)
31747 if (get_attr_update (insn) == UPDATE_YES
31748 && get_attr_indexed (insn) == INDEXED_YES)
31763 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31764 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31767 is_costly_group (rtx *group_insns, rtx next_insn)
31770 int issue_rate = rs6000_issue_rate ();
31772 for (i = 0; i < issue_rate; i++)
31774 sd_iterator_def sd_it;
31776 rtx insn = group_insns[i];
31781 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31783 rtx next = DEP_CON (dep);
31785 if (next == next_insn
31786 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31794 /* Utility of the function redefine_groups.
31795 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31796 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31797 to keep it "far" (in a separate group) from GROUP_INSNS, following
31798 one of the following schemes, depending on the value of the flag
31799 -minsert_sched_nops = X:
31800 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31801 in order to force NEXT_INSN into a separate group.
31802 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31803 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31804 insertion (has a group just ended, how many vacant issue slots remain in the
31805 last group, and how many dispatch groups were encountered so far). */
31808 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31809 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31814 int issue_rate = rs6000_issue_rate ();
31815 bool end = *group_end;
31818 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31819 return can_issue_more;
31821 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31822 return can_issue_more;
31824 force = is_costly_group (group_insns, next_insn);
31826 return can_issue_more;
31828 if (sched_verbose > 6)
31829 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31830 *group_count ,can_issue_more);
31832 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31835 can_issue_more = 0;
31837 /* Since only a branch can be issued in the last issue_slot, it is
31838 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31839 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31840 in this case the last nop will start a new group and the branch
31841 will be forced to the new group. */
31842 if (can_issue_more && !is_branch_slot_insn (next_insn))
31845 /* Do we have a special group ending nop? */
31846 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31847 || rs6000_tune == PROCESSOR_POWER8)
31849 nop = gen_group_ending_nop ();
31850 emit_insn_before (nop, next_insn);
31851 can_issue_more = 0;
31854 while (can_issue_more > 0)
31857 emit_insn_before (nop, next_insn);
31865 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31867 int n_nops = rs6000_sched_insert_nops;
31869 /* Nops can't be issued from the branch slot, so the effective
31870 issue_rate for nops is 'issue_rate - 1'. */
31871 if (can_issue_more == 0)
31872 can_issue_more = issue_rate;
31874 if (can_issue_more == 0)
31876 can_issue_more = issue_rate - 1;
31879 for (i = 0; i < issue_rate; i++)
31881 group_insns[i] = 0;
31888 emit_insn_before (nop, next_insn);
31889 if (can_issue_more == issue_rate - 1) /* new group begins */
31892 if (can_issue_more == 0)
31894 can_issue_more = issue_rate - 1;
31897 for (i = 0; i < issue_rate; i++)
31899 group_insns[i] = 0;
31905 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31908 /* Is next_insn going to start a new group? */
31911 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31912 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31913 || (can_issue_more < issue_rate &&
31914 insn_terminates_group_p (next_insn, previous_group)));
31915 if (*group_end && end)
31918 if (sched_verbose > 6)
31919 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31920 *group_count, can_issue_more);
31921 return can_issue_more;
31924 return can_issue_more;
31927 /* This function tries to synch the dispatch groups that the compiler "sees"
31928 with the dispatch groups that the processor dispatcher is expected to
31929 form in practice. It tries to achieve this synchronization by forcing the
31930 estimated processor grouping on the compiler (as opposed to the function
31931 'pad_goups' which tries to force the scheduler's grouping on the processor).
31933 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31934 examines the (estimated) dispatch groups that will be formed by the processor
31935 dispatcher. It marks these group boundaries to reflect the estimated
31936 processor grouping, overriding the grouping that the scheduler had marked.
31937 Depending on the value of the flag '-minsert-sched-nops' this function can
31938 force certain insns into separate groups or force a certain distance between
31939 them by inserting nops, for example, if there exists a "costly dependence"
31942 The function estimates the group boundaries that the processor will form as
31943 follows: It keeps track of how many vacant issue slots are available after
31944 each insn. A subsequent insn will start a new group if one of the following
31946 - no more vacant issue slots remain in the current dispatch group.
31947 - only the last issue slot, which is the branch slot, is vacant, but the next
31948 insn is not a branch.
31949 - only the last 2 or less issue slots, including the branch slot, are vacant,
31950 which means that a cracked insn (which occupies two issue slots) can't be
31951 issued in this group.
31952 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31953 start a new group. */
31956 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31959 rtx_insn *insn, *next_insn;
31961 int can_issue_more;
31964 int group_count = 0;
31968 issue_rate = rs6000_issue_rate ();
31969 group_insns = XALLOCAVEC (rtx, issue_rate);
31970 for (i = 0; i < issue_rate; i++)
31972 group_insns[i] = 0;
31974 can_issue_more = issue_rate;
31976 insn = get_next_active_insn (prev_head_insn, tail);
31979 while (insn != NULL_RTX)
31981 slot = (issue_rate - can_issue_more);
31982 group_insns[slot] = insn;
31984 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31985 if (insn_terminates_group_p (insn, current_group))
31986 can_issue_more = 0;
31988 next_insn = get_next_active_insn (insn, tail);
31989 if (next_insn == NULL_RTX)
31990 return group_count + 1;
31992 /* Is next_insn going to start a new group? */
31994 = (can_issue_more == 0
31995 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31996 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31997 || (can_issue_more < issue_rate &&
31998 insn_terminates_group_p (next_insn, previous_group)));
32000 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32001 next_insn, &group_end, can_issue_more,
32007 can_issue_more = 0;
32008 for (i = 0; i < issue_rate; i++)
32010 group_insns[i] = 0;
32014 if (GET_MODE (next_insn) == TImode && can_issue_more)
32015 PUT_MODE (next_insn, VOIDmode);
32016 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32017 PUT_MODE (next_insn, TImode);
32020 if (can_issue_more == 0)
32021 can_issue_more = issue_rate;
32024 return group_count;
32027 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32028 dispatch group boundaries that the scheduler had marked. Pad with nops
32029 any dispatch groups which have vacant issue slots, in order to force the
32030 scheduler's grouping on the processor dispatcher. The function
32031 returns the number of dispatch groups found. */
32034 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32037 rtx_insn *insn, *next_insn;
32040 int can_issue_more;
32042 int group_count = 0;
32044 /* Initialize issue_rate. */
32045 issue_rate = rs6000_issue_rate ();
32046 can_issue_more = issue_rate;
32048 insn = get_next_active_insn (prev_head_insn, tail);
32049 next_insn = get_next_active_insn (insn, tail);
32051 while (insn != NULL_RTX)
32054 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32056 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32058 if (next_insn == NULL_RTX)
32063 /* If the scheduler had marked group termination at this location
32064 (between insn and next_insn), and neither insn nor next_insn will
32065 force group termination, pad the group with nops to force group
32068 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32069 && !insn_terminates_group_p (insn, current_group)
32070 && !insn_terminates_group_p (next_insn, previous_group))
32072 if (!is_branch_slot_insn (next_insn))
32075 while (can_issue_more)
32078 emit_insn_before (nop, next_insn);
32083 can_issue_more = issue_rate;
32088 next_insn = get_next_active_insn (insn, tail);
32091 return group_count;
32094 /* We're beginning a new block. Initialize data structures as necessary. */
32097 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32098 int sched_verbose ATTRIBUTE_UNUSED,
32099 int max_ready ATTRIBUTE_UNUSED)
32101 last_scheduled_insn = NULL;
32102 load_store_pendulum = 0;
32107 /* The following function is called at the end of scheduling BB.
32108 After reload, it inserts nops at insn group bundling. */
32111 rs6000_sched_finish (FILE *dump, int sched_verbose)
32116 fprintf (dump, "=== Finishing schedule.\n");
32118 if (reload_completed && rs6000_sched_groups)
32120 /* Do not run sched_finish hook when selective scheduling enabled. */
32121 if (sel_sched_p ())
32124 if (rs6000_sched_insert_nops == sched_finish_none)
32127 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32128 n_groups = pad_groups (dump, sched_verbose,
32129 current_sched_info->prev_head,
32130 current_sched_info->next_tail);
32132 n_groups = redefine_groups (dump, sched_verbose,
32133 current_sched_info->prev_head,
32134 current_sched_info->next_tail);
32136 if (sched_verbose >= 6)
32138 fprintf (dump, "ngroups = %d\n", n_groups);
32139 print_rtl (dump, current_sched_info->prev_head);
32140 fprintf (dump, "Done finish_sched\n");
32145 struct rs6000_sched_context
32147 short cached_can_issue_more;
32148 rtx_insn *last_scheduled_insn;
32149 int load_store_pendulum;
32154 typedef struct rs6000_sched_context rs6000_sched_context_def;
32155 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32157 /* Allocate store for new scheduling context. */
32159 rs6000_alloc_sched_context (void)
32161 return xmalloc (sizeof (rs6000_sched_context_def));
32164 /* If CLEAN_P is true then initializes _SC with clean data,
32165 and from the global context otherwise. */
32167 rs6000_init_sched_context (void *_sc, bool clean_p)
32169 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32173 sc->cached_can_issue_more = 0;
32174 sc->last_scheduled_insn = NULL;
32175 sc->load_store_pendulum = 0;
32176 sc->divide_cnt = 0;
32177 sc->vec_pairing = 0;
32181 sc->cached_can_issue_more = cached_can_issue_more;
32182 sc->last_scheduled_insn = last_scheduled_insn;
32183 sc->load_store_pendulum = load_store_pendulum;
32184 sc->divide_cnt = divide_cnt;
32185 sc->vec_pairing = vec_pairing;
32189 /* Sets the global scheduling context to the one pointed to by _SC. */
32191 rs6000_set_sched_context (void *_sc)
32193 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32195 gcc_assert (sc != NULL);
32197 cached_can_issue_more = sc->cached_can_issue_more;
32198 last_scheduled_insn = sc->last_scheduled_insn;
32199 load_store_pendulum = sc->load_store_pendulum;
32200 divide_cnt = sc->divide_cnt;
32201 vec_pairing = sc->vec_pairing;
32206 rs6000_free_sched_context (void *_sc)
32208 gcc_assert (_sc != NULL);
32214 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32216 switch (get_attr_type (insn))
32231 /* Length in units of the trampoline for entering a nested function. */
32234 rs6000_trampoline_size (void)
32238 switch (DEFAULT_ABI)
32241 gcc_unreachable ();
32244 ret = (TARGET_32BIT) ? 12 : 24;
32248 gcc_assert (!TARGET_32BIT);
32254 ret = (TARGET_32BIT) ? 40 : 48;
32261 /* Emit RTL insns to initialize the variable parts of a trampoline.
32262 FNADDR is an RTX for the address of the function's pure code.
32263 CXT is an RTX for the static chain value for the function. */
32266 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32268 int regsize = (TARGET_32BIT) ? 4 : 8;
32269 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32270 rtx ctx_reg = force_reg (Pmode, cxt);
32271 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32273 switch (DEFAULT_ABI)
32276 gcc_unreachable ();
32278 /* Under AIX, just build the 3 word function descriptor */
32281 rtx fnmem, fn_reg, toc_reg;
32283 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32284 error ("you cannot take the address of a nested function if you use "
32285 "the %qs option", "-mno-pointers-to-nested-functions");
32287 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32288 fn_reg = gen_reg_rtx (Pmode);
32289 toc_reg = gen_reg_rtx (Pmode);
32291 /* Macro to shorten the code expansions below. */
32292 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32294 m_tramp = replace_equiv_address (m_tramp, addr);
32296 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32297 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32298 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32299 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32300 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32306 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32310 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32311 LCT_NORMAL, VOIDmode,
32313 GEN_INT (rs6000_trampoline_size ()), SImode,
32321 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32322 identifier as an argument, so the front end shouldn't look it up. */
32325 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32327 return is_attribute_p ("altivec", attr_id);
32330 /* Handle the "altivec" attribute. The attribute may have
32331 arguments as follows:
32333 __attribute__((altivec(vector__)))
32334 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32335 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32337 and may appear more than once (e.g., 'vector bool char') in a
32338 given declaration. */
32341 rs6000_handle_altivec_attribute (tree *node,
32342 tree name ATTRIBUTE_UNUSED,
32344 int flags ATTRIBUTE_UNUSED,
32345 bool *no_add_attrs)
32347 tree type = *node, result = NULL_TREE;
32351 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32352 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32353 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32356 while (POINTER_TYPE_P (type)
32357 || TREE_CODE (type) == FUNCTION_TYPE
32358 || TREE_CODE (type) == METHOD_TYPE
32359 || TREE_CODE (type) == ARRAY_TYPE)
32360 type = TREE_TYPE (type);
32362 mode = TYPE_MODE (type);
32364 /* Check for invalid AltiVec type qualifiers. */
32365 if (type == long_double_type_node)
32366 error ("use of %<long double%> in AltiVec types is invalid");
32367 else if (type == boolean_type_node)
32368 error ("use of boolean types in AltiVec types is invalid");
32369 else if (TREE_CODE (type) == COMPLEX_TYPE)
32370 error ("use of %<complex%> in AltiVec types is invalid");
32371 else if (DECIMAL_FLOAT_MODE_P (mode))
32372 error ("use of decimal floating point types in AltiVec types is invalid");
32373 else if (!TARGET_VSX)
32375 if (type == long_unsigned_type_node || type == long_integer_type_node)
32378 error ("use of %<long%> in AltiVec types is invalid for "
32379 "64-bit code without %qs", "-mvsx");
32380 else if (rs6000_warn_altivec_long)
32381 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32384 else if (type == long_long_unsigned_type_node
32385 || type == long_long_integer_type_node)
32386 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32388 else if (type == double_type_node)
32389 error ("use of %<double%> in AltiVec types is invalid without %qs",
32393 switch (altivec_type)
32396 unsigned_p = TYPE_UNSIGNED (type);
32400 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32403 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32406 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32409 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32412 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32414 case E_SFmode: result = V4SF_type_node; break;
32415 case E_DFmode: result = V2DF_type_node; break;
32416 /* If the user says 'vector int bool', we may be handed the 'bool'
32417 attribute _before_ the 'vector' attribute, and so select the
32418 proper type in the 'b' case below. */
32419 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32420 case E_V2DImode: case E_V2DFmode:
32428 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32429 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32430 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32431 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32438 case E_V8HImode: result = pixel_V8HI_type_node;
32444 /* Propagate qualifiers attached to the element type
32445 onto the vector type. */
32446 if (result && result != type && TYPE_QUALS (type))
32447 result = build_qualified_type (result, TYPE_QUALS (type));
32449 *no_add_attrs = true; /* No need to hang on to the attribute. */
32452 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32457 /* AltiVec defines five built-in scalar types that serve as vector
32458 elements; we must teach the compiler how to mangle them. The 128-bit
32459 floating point mangling is target-specific as well. */
32461 static const char *
32462 rs6000_mangle_type (const_tree type)
32464 type = TYPE_MAIN_VARIANT (type);
32466 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32467 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32470 if (type == bool_char_type_node) return "U6__boolc";
32471 if (type == bool_short_type_node) return "U6__bools";
32472 if (type == pixel_type_node) return "u7__pixel";
32473 if (type == bool_int_type_node) return "U6__booli";
32474 if (type == bool_long_long_type_node) return "U6__boolx";
32476 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32478 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32479 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32481 /* For all other types, use the default mangling. */
32485 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32486 struct attribute_spec.handler. */
32489 rs6000_handle_longcall_attribute (tree *node, tree name,
32490 tree args ATTRIBUTE_UNUSED,
32491 int flags ATTRIBUTE_UNUSED,
32492 bool *no_add_attrs)
32494 if (TREE_CODE (*node) != FUNCTION_TYPE
32495 && TREE_CODE (*node) != FIELD_DECL
32496 && TREE_CODE (*node) != TYPE_DECL)
32498 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32500 *no_add_attrs = true;
32506 /* Set longcall attributes on all functions declared when
32507 rs6000_default_long_calls is true. */
32509 rs6000_set_default_type_attributes (tree type)
32511 if (rs6000_default_long_calls
32512 && (TREE_CODE (type) == FUNCTION_TYPE
32513 || TREE_CODE (type) == METHOD_TYPE))
32514 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32516 TYPE_ATTRIBUTES (type));
32519 darwin_set_default_type_attributes (type);
32523 /* Return a reference suitable for calling a function with the
32524 longcall attribute. */
32527 rs6000_longcall_ref (rtx call_ref, rtx arg)
32529 /* System V adds '.' to the internal name, so skip them. */
32530 const char *call_name = XSTR (call_ref, 0);
32531 if (*call_name == '.')
32533 while (*call_name == '.')
32536 tree node = get_identifier (call_name);
32537 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32542 rtx base = const0_rtx;
32544 if (DEFAULT_ABI == ABI_ELFv2)
32546 base = gen_rtx_REG (Pmode, TOC_REGISTER);
32552 base = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
32555 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32556 may be used by a function global entry point. For SysV4, r11
32557 is used by __glink_PLTresolve lazy resolver entry. */
32558 rtx reg = gen_rtx_REG (Pmode, regno);
32559 rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32561 rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg),
32563 emit_insn (gen_rtx_SET (reg, hi));
32564 emit_insn (gen_rtx_SET (reg, lo));
32568 return force_reg (Pmode, call_ref);
32571 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32572 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32575 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32576 struct attribute_spec.handler. */
32578 rs6000_handle_struct_attribute (tree *node, tree name,
32579 tree args ATTRIBUTE_UNUSED,
32580 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32583 if (DECL_P (*node))
32585 if (TREE_CODE (*node) == TYPE_DECL)
32586 type = &TREE_TYPE (*node);
32591 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32592 || TREE_CODE (*type) == UNION_TYPE)))
32594 warning (OPT_Wattributes, "%qE attribute ignored", name);
32595 *no_add_attrs = true;
32598 else if ((is_attribute_p ("ms_struct", name)
32599 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32600 || ((is_attribute_p ("gcc_struct", name)
32601 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32603 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32605 *no_add_attrs = true;
32612 rs6000_ms_bitfield_layout_p (const_tree record_type)
32614 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32615 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32616 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32619 #ifdef USING_ELFOS_H
32621 /* A get_unnamed_section callback, used for switching to toc_section. */
32624 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32626 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32627 && TARGET_MINIMAL_TOC)
32629 if (!toc_initialized)
32631 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32632 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32633 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32634 fprintf (asm_out_file, "\t.tc ");
32635 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32636 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32637 fprintf (asm_out_file, "\n");
32639 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32640 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32641 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32642 fprintf (asm_out_file, " = .+32768\n");
32643 toc_initialized = 1;
32646 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32648 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32650 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32651 if (!toc_initialized)
32653 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32654 toc_initialized = 1;
32659 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32660 if (!toc_initialized)
32662 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32663 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32664 fprintf (asm_out_file, " = .+32768\n");
32665 toc_initialized = 1;
32670 /* Implement TARGET_ASM_INIT_SECTIONS. */
32673 rs6000_elf_asm_init_sections (void)
32676 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32679 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32680 SDATA2_SECTION_ASM_OP);
32683 /* Implement TARGET_SELECT_RTX_SECTION. */
32686 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32687 unsigned HOST_WIDE_INT align)
32689 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32690 return toc_section;
32692 return default_elf_select_rtx_section (mode, x, align);
32695 /* For a SYMBOL_REF, set generic flags and then perform some
32696 target-specific processing.
32698 When the AIX ABI is requested on a non-AIX system, replace the
32699 function name with the real name (with a leading .) rather than the
32700 function descriptor name. This saves a lot of overriding code to
32701 read the prefixes. */
32703 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32705 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32707 default_encode_section_info (decl, rtl, first);
32710 && TREE_CODE (decl) == FUNCTION_DECL
32712 && DEFAULT_ABI == ABI_AIX)
32714 rtx sym_ref = XEXP (rtl, 0);
32715 size_t len = strlen (XSTR (sym_ref, 0));
32716 char *str = XALLOCAVEC (char, len + 2);
32718 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32719 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32724 compare_section_name (const char *section, const char *templ)
32728 len = strlen (templ);
32729 return (strncmp (section, templ, len) == 0
32730 && (section[len] == 0 || section[len] == '.'));
32734 rs6000_elf_in_small_data_p (const_tree decl)
32736 if (rs6000_sdata == SDATA_NONE)
32739 /* We want to merge strings, so we never consider them small data. */
32740 if (TREE_CODE (decl) == STRING_CST)
32743 /* Functions are never in the small data area. */
32744 if (TREE_CODE (decl) == FUNCTION_DECL)
32747 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32749 const char *section = DECL_SECTION_NAME (decl);
32750 if (compare_section_name (section, ".sdata")
32751 || compare_section_name (section, ".sdata2")
32752 || compare_section_name (section, ".gnu.linkonce.s")
32753 || compare_section_name (section, ".sbss")
32754 || compare_section_name (section, ".sbss2")
32755 || compare_section_name (section, ".gnu.linkonce.sb")
32756 || strcmp (section, ".PPC.EMB.sdata0") == 0
32757 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32762 /* If we are told not to put readonly data in sdata, then don't. */
32763 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32764 && !rs6000_readonly_in_sdata)
32767 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32770 && size <= g_switch_value
32771 /* If it's not public, and we're not going to reference it there,
32772 there's no need to put it in the small data section. */
32773 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32780 #endif /* USING_ELFOS_H */
32782 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32785 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32787 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32790 /* Do not place thread-local symbols refs in the object blocks. */
32793 rs6000_use_blocks_for_decl_p (const_tree decl)
32795 return !DECL_THREAD_LOCAL_P (decl);
32798 /* Return a REG that occurs in ADDR with coefficient 1.
32799 ADDR can be effectively incremented by incrementing REG.
32801 r0 is special and we must not select it as an address
32802 register by this routine since our caller will try to
32803 increment the returned register via an "la" instruction. */
32806 find_addr_reg (rtx addr)
32808 while (GET_CODE (addr) == PLUS)
32810 if (REG_P (XEXP (addr, 0))
32811 && REGNO (XEXP (addr, 0)) != 0)
32812 addr = XEXP (addr, 0);
32813 else if (REG_P (XEXP (addr, 1))
32814 && REGNO (XEXP (addr, 1)) != 0)
32815 addr = XEXP (addr, 1);
32816 else if (CONSTANT_P (XEXP (addr, 0)))
32817 addr = XEXP (addr, 1);
32818 else if (CONSTANT_P (XEXP (addr, 1)))
32819 addr = XEXP (addr, 0);
32821 gcc_unreachable ();
32823 gcc_assert (REG_P (addr) && REGNO (addr) != 0);
32828 rs6000_fatal_bad_address (rtx op)
32830 fatal_insn ("bad address", op);
32835 typedef struct branch_island_d {
32836 tree function_name;
32842 static vec<branch_island, va_gc> *branch_islands;
32844 /* Remember to generate a branch island for far calls to the given
32848 add_compiler_branch_island (tree label_name, tree function_name,
32851 branch_island bi = {function_name, label_name, line_number};
32852 vec_safe_push (branch_islands, bi);
32855 /* Generate far-jump branch islands for everything recorded in
32856 branch_islands. Invoked immediately after the last instruction of
32857 the epilogue has been emitted; the branch islands must be appended
32858 to, and contiguous with, the function body. Mach-O stubs are
32859 generated in machopic_output_stub(). */
32862 macho_branch_islands (void)
32866 while (!vec_safe_is_empty (branch_islands))
32868 branch_island *bi = &branch_islands->last ();
32869 const char *label = IDENTIFIER_POINTER (bi->label_name);
32870 const char *name = IDENTIFIER_POINTER (bi->function_name);
32871 char name_buf[512];
32872 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32873 if (name[0] == '*' || name[0] == '&')
32874 strcpy (name_buf, name+1);
32878 strcpy (name_buf+1, name);
32880 strcpy (tmp_buf, "\n");
32881 strcat (tmp_buf, label);
32882 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32883 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32884 dbxout_stabd (N_SLINE, bi->line_number);
32885 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32888 if (TARGET_LINK_STACK)
32891 get_ppc476_thunk_name (name);
32892 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32893 strcat (tmp_buf, name);
32894 strcat (tmp_buf, "\n");
32895 strcat (tmp_buf, label);
32896 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32900 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32901 strcat (tmp_buf, label);
32902 strcat (tmp_buf, "_pic\n");
32903 strcat (tmp_buf, label);
32904 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32907 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32908 strcat (tmp_buf, name_buf);
32909 strcat (tmp_buf, " - ");
32910 strcat (tmp_buf, label);
32911 strcat (tmp_buf, "_pic)\n");
32913 strcat (tmp_buf, "\tmtlr r0\n");
32915 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32916 strcat (tmp_buf, name_buf);
32917 strcat (tmp_buf, " - ");
32918 strcat (tmp_buf, label);
32919 strcat (tmp_buf, "_pic)\n");
32921 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32925 strcat (tmp_buf, ":\n\tlis r12,hi16(");
32926 strcat (tmp_buf, name_buf);
32927 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32928 strcat (tmp_buf, name_buf);
32929 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32931 output_asm_insn (tmp_buf, 0);
32932 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32933 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32934 dbxout_stabd (N_SLINE, bi->line_number);
32935 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32936 branch_islands->pop ();
32940 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32941 already there or not. */
32944 no_previous_def (tree function_name)
32949 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32950 if (function_name == bi->function_name)
32955 /* GET_PREV_LABEL gets the label name from the previous definition of
32959 get_prev_label (tree function_name)
32964 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32965 if (function_name == bi->function_name)
32966 return bi->label_name;
32970 /* Generate PIC and indirect symbol stubs. */
32973 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32975 unsigned int length;
32976 char *symbol_name, *lazy_ptr_name;
32977 char *local_label_0;
32978 static unsigned label = 0;
32980 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32981 symb = (*targetm.strip_name_encoding) (symb);
32984 length = strlen (symb);
32985 symbol_name = XALLOCAVEC (char, length + 32);
32986 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
32988 lazy_ptr_name = XALLOCAVEC (char, length + 32);
32989 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
32992 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
32994 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
32998 fprintf (file, "\t.align 5\n");
33000 fprintf (file, "%s:\n", stub);
33001 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33004 local_label_0 = XALLOCAVEC (char, 16);
33005 sprintf (local_label_0, "L%u$spb", label);
33007 fprintf (file, "\tmflr r0\n");
33008 if (TARGET_LINK_STACK)
33011 get_ppc476_thunk_name (name);
33012 fprintf (file, "\tbl %s\n", name);
33013 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33017 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33018 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33020 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33021 lazy_ptr_name, local_label_0);
33022 fprintf (file, "\tmtlr r0\n");
33023 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33024 (TARGET_64BIT ? "ldu" : "lwzu"),
33025 lazy_ptr_name, local_label_0);
33026 fprintf (file, "\tmtctr r12\n");
33027 fprintf (file, "\tbctr\n");
33031 fprintf (file, "\t.align 4\n");
33033 fprintf (file, "%s:\n", stub);
33034 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33036 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33037 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33038 (TARGET_64BIT ? "ldu" : "lwzu"),
33040 fprintf (file, "\tmtctr r12\n");
33041 fprintf (file, "\tbctr\n");
33044 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33045 fprintf (file, "%s:\n", lazy_ptr_name);
33046 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33047 fprintf (file, "%sdyld_stub_binding_helper\n",
33048 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33051 /* Legitimize PIC addresses. If the address is already
33052 position-independent, we return ORIG. Newly generated
33053 position-independent addresses go into a reg. This is REG if non
33054 zero, otherwise we allocate register(s) as necessary. */
33056 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33059 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33064 if (reg == NULL && !reload_completed)
33065 reg = gen_reg_rtx (Pmode);
33067 if (GET_CODE (orig) == CONST)
33071 if (GET_CODE (XEXP (orig, 0)) == PLUS
33072 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33075 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33077 /* Use a different reg for the intermediate value, as
33078 it will be marked UNCHANGING. */
33079 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33080 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33083 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33086 if (CONST_INT_P (offset))
33088 if (SMALL_INT (offset))
33089 return plus_constant (Pmode, base, INTVAL (offset));
33090 else if (!reload_completed)
33091 offset = force_reg (Pmode, offset);
33094 rtx mem = force_const_mem (Pmode, orig);
33095 return machopic_legitimize_pic_address (mem, Pmode, reg);
33098 return gen_rtx_PLUS (Pmode, base, offset);
33101 /* Fall back on generic machopic code. */
33102 return machopic_legitimize_pic_address (orig, mode, reg);
33105 /* Output a .machine directive for the Darwin assembler, and call
33106 the generic start_file routine. */
33109 rs6000_darwin_file_start (void)
33111 static const struct
33115 HOST_WIDE_INT if_set;
33117 { "ppc64", "ppc64", MASK_64BIT },
33118 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33119 { "power4", "ppc970", 0 },
33120 { "G5", "ppc970", 0 },
33121 { "7450", "ppc7450", 0 },
33122 { "7400", "ppc7400", MASK_ALTIVEC },
33123 { "G4", "ppc7400", 0 },
33124 { "750", "ppc750", 0 },
33125 { "740", "ppc750", 0 },
33126 { "G3", "ppc750", 0 },
33127 { "604e", "ppc604e", 0 },
33128 { "604", "ppc604", 0 },
33129 { "603e", "ppc603", 0 },
33130 { "603", "ppc603", 0 },
33131 { "601", "ppc601", 0 },
33132 { NULL, "ppc", 0 } };
33133 const char *cpu_id = "";
33136 rs6000_file_start ();
33137 darwin_file_start ();
33139 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33141 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33142 cpu_id = rs6000_default_cpu;
33144 if (global_options_set.x_rs6000_cpu_index)
33145 cpu_id = processor_target_table[rs6000_cpu_index].name;
33147 /* Look through the mapping array. Pick the first name that either
33148 matches the argument, has a bit set in IF_SET that is also set
33149 in the target flags, or has a NULL name. */
33152 while (mapping[i].arg != NULL
33153 && strcmp (mapping[i].arg, cpu_id) != 0
33154 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33157 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33160 #endif /* TARGET_MACHO */
33164 rs6000_elf_reloc_rw_mask (void)
33168 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33174 /* Record an element in the table of global constructors. SYMBOL is
33175 a SYMBOL_REF of the function to be called; PRIORITY is a number
33176 between 0 and MAX_INIT_PRIORITY.
33178 This differs from default_named_section_asm_out_constructor in
33179 that we have special handling for -mrelocatable. */
33181 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33183 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33185 const char *section = ".ctors";
33188 if (priority != DEFAULT_INIT_PRIORITY)
33190 sprintf (buf, ".ctors.%.5u",
33191 /* Invert the numbering so the linker puts us in the proper
33192 order; constructors are run from right to left, and the
33193 linker sorts in increasing order. */
33194 MAX_INIT_PRIORITY - priority);
33198 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33199 assemble_align (POINTER_SIZE);
33201 if (DEFAULT_ABI == ABI_V4
33202 && (TARGET_RELOCATABLE || flag_pic > 1))
33204 fputs ("\t.long (", asm_out_file);
33205 output_addr_const (asm_out_file, symbol);
33206 fputs (")@fixup\n", asm_out_file);
33209 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33212 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33214 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33216 const char *section = ".dtors";
33219 if (priority != DEFAULT_INIT_PRIORITY)
33221 sprintf (buf, ".dtors.%.5u",
33222 /* Invert the numbering so the linker puts us in the proper
33223 order; constructors are run from right to left, and the
33224 linker sorts in increasing order. */
33225 MAX_INIT_PRIORITY - priority);
33229 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33230 assemble_align (POINTER_SIZE);
33232 if (DEFAULT_ABI == ABI_V4
33233 && (TARGET_RELOCATABLE || flag_pic > 1))
33235 fputs ("\t.long (", asm_out_file);
33236 output_addr_const (asm_out_file, symbol);
33237 fputs (")@fixup\n", asm_out_file);
33240 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33244 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33246 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33248 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33249 ASM_OUTPUT_LABEL (file, name);
33250 fputs (DOUBLE_INT_ASM_OP, file);
33251 rs6000_output_function_entry (file, name);
33252 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33255 fputs ("\t.size\t", file);
33256 assemble_name (file, name);
33257 fputs (",24\n\t.type\t.", file);
33258 assemble_name (file, name);
33259 fputs (",@function\n", file);
33260 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33262 fputs ("\t.globl\t.", file);
33263 assemble_name (file, name);
33268 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33269 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33270 rs6000_output_function_entry (file, name);
33271 fputs (":\n", file);
33276 if (DEFAULT_ABI == ABI_V4
33277 && (TARGET_RELOCATABLE || flag_pic > 1)
33278 && !TARGET_SECURE_PLT
33279 && (!constant_pool_empty_p () || crtl->profile)
33280 && (uses_toc = uses_TOC ()))
33285 switch_to_other_text_partition ();
33286 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33288 fprintf (file, "\t.long ");
33289 assemble_name (file, toc_label_name);
33292 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33293 assemble_name (file, buf);
33296 switch_to_other_text_partition ();
33299 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33300 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33302 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33306 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33308 fprintf (file, "\t.quad .TOC.-");
33309 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33310 assemble_name (file, buf);
33314 if (DEFAULT_ABI == ABI_AIX)
33316 const char *desc_name, *orig_name;
33318 orig_name = (*targetm.strip_name_encoding) (name);
33319 desc_name = orig_name;
33320 while (*desc_name == '.')
33323 if (TREE_PUBLIC (decl))
33324 fprintf (file, "\t.globl %s\n", desc_name);
33326 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33327 fprintf (file, "%s:\n", desc_name);
33328 fprintf (file, "\t.long %s\n", orig_name);
33329 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33330 fputs ("\t.long 0\n", file);
33331 fprintf (file, "\t.previous\n");
33333 ASM_OUTPUT_LABEL (file, name);
33336 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33338 rs6000_elf_file_end (void)
33340 #ifdef HAVE_AS_GNU_ATTRIBUTE
33341 /* ??? The value emitted depends on options active at file end.
33342 Assume anyone using #pragma or attributes that might change
33343 options knows what they are doing. */
33344 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33345 && rs6000_passes_float)
33349 if (TARGET_HARD_FLOAT)
33353 if (rs6000_passes_long_double)
33355 if (!TARGET_LONG_DOUBLE_128)
33357 else if (TARGET_IEEEQUAD)
33362 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33364 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33366 if (rs6000_passes_vector)
33367 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33368 (TARGET_ALTIVEC_ABI ? 2 : 1));
33369 if (rs6000_returns_struct)
33370 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33371 aix_struct_return ? 2 : 1);
33374 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33375 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33376 file_end_indicate_exec_stack ();
33379 if (flag_split_stack)
33380 file_end_indicate_split_stack ();
33384 /* We have expanded a CPU builtin, so we need to emit a reference to
33385 the special symbol that LIBC uses to declare it supports the
33386 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33387 switch_to_section (data_section);
33388 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33389 fprintf (asm_out_file, "\t%s %s\n",
33390 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33397 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33398 #define HAVE_XCOFF_DWARF_EXTRAS 0
33401 static enum unwind_info_type
33402 rs6000_xcoff_debug_unwind_info (void)
33408 rs6000_xcoff_asm_output_anchor (rtx symbol)
33412 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33413 SYMBOL_REF_BLOCK_OFFSET (symbol));
33414 fprintf (asm_out_file, "%s", SET_ASM_OP);
33415 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33416 fprintf (asm_out_file, ",");
33417 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33418 fprintf (asm_out_file, "\n");
33422 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33424 fputs (GLOBAL_ASM_OP, stream);
33425 RS6000_OUTPUT_BASENAME (stream, name);
33426 putc ('\n', stream);
33429 /* A get_unnamed_decl callback, used for read-only sections. PTR
33430 points to the section string variable. */
33433 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33435 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33436 *(const char *const *) directive,
33437 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33440 /* Likewise for read-write sections. */
33443 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33445 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33446 *(const char *const *) directive,
33447 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33451 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33453 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33454 *(const char *const *) directive,
33455 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33458 /* A get_unnamed_section callback, used for switching to toc_section. */
33461 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33463 if (TARGET_MINIMAL_TOC)
33465 /* toc_section is always selected at least once from
33466 rs6000_xcoff_file_start, so this is guaranteed to
33467 always be defined once and only once in each file. */
33468 if (!toc_initialized)
33470 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33471 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33472 toc_initialized = 1;
33474 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33475 (TARGET_32BIT ? "" : ",3"));
33478 fputs ("\t.toc\n", asm_out_file);
33481 /* Implement TARGET_ASM_INIT_SECTIONS. */
33484 rs6000_xcoff_asm_init_sections (void)
33486 read_only_data_section
33487 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33488 &xcoff_read_only_section_name);
33490 private_data_section
33491 = get_unnamed_section (SECTION_WRITE,
33492 rs6000_xcoff_output_readwrite_section_asm_op,
33493 &xcoff_private_data_section_name);
33495 read_only_private_data_section
33496 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33497 &xcoff_private_rodata_section_name);
33500 = get_unnamed_section (SECTION_TLS,
33501 rs6000_xcoff_output_tls_section_asm_op,
33502 &xcoff_tls_data_section_name);
33504 tls_private_data_section
33505 = get_unnamed_section (SECTION_TLS,
33506 rs6000_xcoff_output_tls_section_asm_op,
33507 &xcoff_private_data_section_name);
33510 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33512 readonly_data_section = read_only_data_section;
33516 rs6000_xcoff_reloc_rw_mask (void)
33522 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33523 tree decl ATTRIBUTE_UNUSED)
33526 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33528 if (flags & SECTION_EXCLUDE)
33530 else if (flags & SECTION_DEBUG)
33532 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33535 else if (flags & SECTION_CODE)
33537 else if (flags & SECTION_TLS)
33539 else if (flags & SECTION_WRITE)
33544 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33545 (flags & SECTION_CODE) ? "." : "",
33546 name, suffix[smclass], flags & SECTION_ENTSIZE);
33549 #define IN_NAMED_SECTION(DECL) \
33550 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33551 && DECL_SECTION_NAME (DECL) != NULL)
33554 rs6000_xcoff_select_section (tree decl, int reloc,
33555 unsigned HOST_WIDE_INT align)
33557 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33559 if (align > BIGGEST_ALIGNMENT)
33561 resolve_unique_section (decl, reloc, true);
33562 if (IN_NAMED_SECTION (decl))
33563 return get_named_section (decl, NULL, reloc);
33566 if (decl_readonly_section (decl, reloc))
33568 if (TREE_PUBLIC (decl))
33569 return read_only_data_section;
33571 return read_only_private_data_section;
33576 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33578 if (TREE_PUBLIC (decl))
33579 return tls_data_section;
33580 else if (bss_initializer_p (decl))
33582 /* Convert to COMMON to emit in BSS. */
33583 DECL_COMMON (decl) = 1;
33584 return tls_comm_section;
33587 return tls_private_data_section;
33591 if (TREE_PUBLIC (decl))
33592 return data_section;
33594 return private_data_section;
33599 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33603 /* Use select_section for private data and uninitialized data with
33604 alignment <= BIGGEST_ALIGNMENT. */
33605 if (!TREE_PUBLIC (decl)
33606 || DECL_COMMON (decl)
33607 || (DECL_INITIAL (decl) == NULL_TREE
33608 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33609 || DECL_INITIAL (decl) == error_mark_node
33610 || (flag_zero_initialized_in_bss
33611 && initializer_zerop (DECL_INITIAL (decl))))
33614 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33615 name = (*targetm.strip_name_encoding) (name);
33616 set_decl_section_name (decl, name);
33619 /* Select section for constant in constant pool.
33621 On RS/6000, all constants are in the private read-only data area.
33622 However, if this is being placed in the TOC it must be output as a
33626 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33627 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33629 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33630 return toc_section;
33632 return read_only_private_data_section;
33635 /* Remove any trailing [DS] or the like from the symbol name. */
33637 static const char *
33638 rs6000_xcoff_strip_name_encoding (const char *name)
33643 len = strlen (name);
33644 if (name[len - 1] == ']')
33645 return ggc_alloc_string (name, len - 4);
33650 /* Section attributes. AIX is always PIC. */
33652 static unsigned int
33653 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33655 unsigned int align;
33656 unsigned int flags = default_section_type_flags (decl, name, reloc);
33658 /* Align to at least UNIT size. */
33659 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33660 align = MIN_UNITS_PER_WORD;
33662 /* Increase alignment of large objects if not already stricter. */
33663 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33664 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33665 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33667 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33670 /* Output at beginning of assembler file.
33672 Initialize the section names for the RS/6000 at this point.
33674 Specify filename, including full path, to assembler.
33676 We want to go into the TOC section so at least one .toc will be emitted.
33677 Also, in order to output proper .bs/.es pairs, we need at least one static
33678 [RW] section emitted.
33680 Finally, declare mcount when profiling to make the assembler happy. */
33683 rs6000_xcoff_file_start (void)
33685 rs6000_gen_section_name (&xcoff_bss_section_name,
33686 main_input_filename, ".bss_");
33687 rs6000_gen_section_name (&xcoff_private_data_section_name,
33688 main_input_filename, ".rw_");
33689 rs6000_gen_section_name (&xcoff_private_rodata_section_name,
33690 main_input_filename, ".rop_");
33691 rs6000_gen_section_name (&xcoff_read_only_section_name,
33692 main_input_filename, ".ro_");
33693 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33694 main_input_filename, ".tls_");
33695 rs6000_gen_section_name (&xcoff_tbss_section_name,
33696 main_input_filename, ".tbss_[UL]");
33698 fputs ("\t.file\t", asm_out_file);
33699 output_quoted_string (asm_out_file, main_input_filename);
33700 fputc ('\n', asm_out_file);
33701 if (write_symbols != NO_DEBUG)
33702 switch_to_section (private_data_section);
33703 switch_to_section (toc_section);
33704 switch_to_section (text_section);
33706 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33707 rs6000_file_start ();
33710 /* Output at end of assembler file.
33711 On the RS/6000, referencing data should automatically pull in text. */
33714 rs6000_xcoff_file_end (void)
33716 switch_to_section (text_section);
33717 fputs ("_section_.text:\n", asm_out_file);
33718 switch_to_section (data_section);
33719 fputs (TARGET_32BIT
33720 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33724 struct declare_alias_data
33727 bool function_descriptor;
33730 /* Declare alias N. A helper function for for_node_and_aliases. */
33733 rs6000_declare_alias (struct symtab_node *n, void *d)
33735 struct declare_alias_data *data = (struct declare_alias_data *)d;
33736 /* Main symbol is output specially, because varasm machinery does part of
33737 the job for us - we do not need to declare .globl/lglobs and such. */
33738 if (!n->alias || n->weakref)
33741 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33744 /* Prevent assemble_alias from trying to use .set pseudo operation
33745 that does not behave as expected by the middle-end. */
33746 TREE_ASM_WRITTEN (n->decl) = true;
33748 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33749 char *buffer = (char *) alloca (strlen (name) + 2);
33751 int dollar_inside = 0;
33753 strcpy (buffer, name);
33754 p = strchr (buffer, '$');
33758 p = strchr (p + 1, '$');
33760 if (TREE_PUBLIC (n->decl))
33762 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33764 if (dollar_inside) {
33765 if (data->function_descriptor)
33766 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33767 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33769 if (data->function_descriptor)
33771 fputs ("\t.globl .", data->file);
33772 RS6000_OUTPUT_BASENAME (data->file, buffer);
33773 putc ('\n', data->file);
33775 fputs ("\t.globl ", data->file);
33776 RS6000_OUTPUT_BASENAME (data->file, buffer);
33777 putc ('\n', data->file);
33779 #ifdef ASM_WEAKEN_DECL
33780 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33781 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33788 if (data->function_descriptor)
33789 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33790 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33792 if (data->function_descriptor)
33794 fputs ("\t.lglobl .", data->file);
33795 RS6000_OUTPUT_BASENAME (data->file, buffer);
33796 putc ('\n', data->file);
33798 fputs ("\t.lglobl ", data->file);
33799 RS6000_OUTPUT_BASENAME (data->file, buffer);
33800 putc ('\n', data->file);
33802 if (data->function_descriptor)
33803 fputs (".", data->file);
33804 RS6000_OUTPUT_BASENAME (data->file, buffer);
33805 fputs (":\n", data->file);
33810 #ifdef HAVE_GAS_HIDDEN
33811 /* Helper function to calculate visibility of a DECL
33812 and return the value as a const string. */
33814 static const char *
33815 rs6000_xcoff_visibility (tree decl)
33817 static const char * const visibility_types[] = {
33818 "", ",protected", ",hidden", ",internal"
33821 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33822 return visibility_types[vis];
33827 /* This macro produces the initial definition of a function name.
33828 On the RS/6000, we need to place an extra '.' in the function name and
33829 output the function descriptor.
33830 Dollar signs are converted to underscores.
33832 The csect for the function will have already been created when
33833 text_section was selected. We do have to go back to that csect, however.
33835 The third and fourth parameters to the .function pseudo-op (16 and 044)
33836 are placeholders which no longer have any use.
33838 Because AIX assembler's .set command has unexpected semantics, we output
33839 all aliases as alternative labels in front of the definition. */
33842 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33844 char *buffer = (char *) alloca (strlen (name) + 1);
33846 int dollar_inside = 0;
33847 struct declare_alias_data data = {file, false};
33849 strcpy (buffer, name);
33850 p = strchr (buffer, '$');
33854 p = strchr (p + 1, '$');
33856 if (TREE_PUBLIC (decl))
33858 if (!RS6000_WEAK || !DECL_WEAK (decl))
33860 if (dollar_inside) {
33861 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33862 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33864 fputs ("\t.globl .", file);
33865 RS6000_OUTPUT_BASENAME (file, buffer);
33866 #ifdef HAVE_GAS_HIDDEN
33867 fputs (rs6000_xcoff_visibility (decl), file);
33874 if (dollar_inside) {
33875 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33876 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33878 fputs ("\t.lglobl .", file);
33879 RS6000_OUTPUT_BASENAME (file, buffer);
33882 fputs ("\t.csect ", file);
33883 RS6000_OUTPUT_BASENAME (file, buffer);
33884 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33885 RS6000_OUTPUT_BASENAME (file, buffer);
33886 fputs (":\n", file);
33887 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33889 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33890 RS6000_OUTPUT_BASENAME (file, buffer);
33891 fputs (", TOC[tc0], 0\n", file);
33893 switch_to_section (function_section (decl));
33895 RS6000_OUTPUT_BASENAME (file, buffer);
33896 fputs (":\n", file);
33897 data.function_descriptor = true;
33898 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33900 if (!DECL_IGNORED_P (decl))
33902 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33903 xcoffout_declare_function (file, decl, buffer);
33904 else if (write_symbols == DWARF2_DEBUG)
33906 name = (*targetm.strip_name_encoding) (name);
33907 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33914 /* Output assembly language to globalize a symbol from a DECL,
33915 possibly with visibility. */
33918 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33920 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33921 fputs (GLOBAL_ASM_OP, stream);
33922 RS6000_OUTPUT_BASENAME (stream, name);
33923 #ifdef HAVE_GAS_HIDDEN
33924 fputs (rs6000_xcoff_visibility (decl), stream);
33926 putc ('\n', stream);
33929 /* Output assembly language to define a symbol as COMMON from a DECL,
33930 possibly with visibility. */
33933 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33934 tree decl ATTRIBUTE_UNUSED,
33936 unsigned HOST_WIDE_INT size,
33937 unsigned HOST_WIDE_INT align)
33939 unsigned HOST_WIDE_INT align2 = 2;
33942 align2 = floor_log2 (align / BITS_PER_UNIT);
33946 fputs (COMMON_ASM_OP, stream);
33947 RS6000_OUTPUT_BASENAME (stream, name);
33950 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33953 #ifdef HAVE_GAS_HIDDEN
33955 fputs (rs6000_xcoff_visibility (decl), stream);
33957 putc ('\n', stream);
33960 /* This macro produces the initial definition of a object (variable) name.
33961 Because AIX assembler's .set command has unexpected semantics, we output
33962 all aliases as alternative labels in front of the definition. */
33965 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33967 struct declare_alias_data data = {file, false};
33968 RS6000_OUTPUT_BASENAME (file, name);
33969 fputs (":\n", file);
33970 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33974 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33977 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33979 fputs (integer_asm_op (size, FALSE), file);
33980 assemble_name (file, label);
33981 fputs ("-$", file);
33984 /* Output a symbol offset relative to the dbase for the current object.
33985 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
33988 __gcc_unwind_dbase is embedded in all executables/libraries through
33989 libgcc/config/rs6000/crtdbase.S. */
33992 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
33994 fputs (integer_asm_op (size, FALSE), file);
33995 assemble_name (file, label);
33996 fputs("-__gcc_unwind_dbase", file);
34001 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34005 const char *symname;
34007 default_encode_section_info (decl, rtl, first);
34009 /* Careful not to prod global register variables. */
34012 symbol = XEXP (rtl, 0);
34013 if (!SYMBOL_REF_P (symbol))
34016 flags = SYMBOL_REF_FLAGS (symbol);
34018 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34019 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34021 SYMBOL_REF_FLAGS (symbol) = flags;
34023 /* Append mapping class to extern decls. */
34024 symname = XSTR (symbol, 0);
34025 if (decl /* sync condition with assemble_external () */
34026 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34027 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34028 || TREE_CODE (decl) == FUNCTION_DECL)
34029 && symname[strlen (symname) - 1] != ']')
34031 char *newname = (char *) alloca (strlen (symname) + 5);
34032 strcpy (newname, symname);
34033 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34034 ? "[DS]" : "[UA]"));
34035 XSTR (symbol, 0) = ggc_strdup (newname);
34038 #endif /* HAVE_AS_TLS */
34039 #endif /* TARGET_XCOFF */
34042 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34043 const char *name, const char *val)
34045 fputs ("\t.weak\t", stream);
34046 RS6000_OUTPUT_BASENAME (stream, name);
34047 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34048 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34051 fputs ("[DS]", stream);
34052 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34054 fputs (rs6000_xcoff_visibility (decl), stream);
34056 fputs ("\n\t.weak\t.", stream);
34057 RS6000_OUTPUT_BASENAME (stream, name);
34059 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34061 fputs (rs6000_xcoff_visibility (decl), stream);
34063 fputc ('\n', stream);
34066 #ifdef ASM_OUTPUT_DEF
34067 ASM_OUTPUT_DEF (stream, name, val);
34069 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34070 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34072 fputs ("\t.set\t.", stream);
34073 RS6000_OUTPUT_BASENAME (stream, name);
34074 fputs (",.", stream);
34075 RS6000_OUTPUT_BASENAME (stream, val);
34076 fputc ('\n', stream);
34082 /* Return true if INSN should not be copied. */
34085 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34087 return recog_memoized (insn) >= 0
34088 && get_attr_cannot_copy (insn);
34091 /* Compute a (partial) cost for rtx X. Return true if the complete
34092 cost has been computed, and false if subexpressions should be
34093 scanned. In either case, *TOTAL contains the cost result. */
34096 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34097 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34099 int code = GET_CODE (x);
34103 /* On the RS/6000, if it is valid in the insn, it is free. */
34105 if (((outer_code == SET
34106 || outer_code == PLUS
34107 || outer_code == MINUS)
34108 && (satisfies_constraint_I (x)
34109 || satisfies_constraint_L (x)))
34110 || (outer_code == AND
34111 && (satisfies_constraint_K (x)
34113 ? satisfies_constraint_L (x)
34114 : satisfies_constraint_J (x))))
34115 || ((outer_code == IOR || outer_code == XOR)
34116 && (satisfies_constraint_K (x)
34118 ? satisfies_constraint_L (x)
34119 : satisfies_constraint_J (x))))
34120 || outer_code == ASHIFT
34121 || outer_code == ASHIFTRT
34122 || outer_code == LSHIFTRT
34123 || outer_code == ROTATE
34124 || outer_code == ROTATERT
34125 || outer_code == ZERO_EXTRACT
34126 || (outer_code == MULT
34127 && satisfies_constraint_I (x))
34128 || ((outer_code == DIV || outer_code == UDIV
34129 || outer_code == MOD || outer_code == UMOD)
34130 && exact_log2 (INTVAL (x)) >= 0)
34131 || (outer_code == COMPARE
34132 && (satisfies_constraint_I (x)
34133 || satisfies_constraint_K (x)))
34134 || ((outer_code == EQ || outer_code == NE)
34135 && (satisfies_constraint_I (x)
34136 || satisfies_constraint_K (x)
34138 ? satisfies_constraint_L (x)
34139 : satisfies_constraint_J (x))))
34140 || (outer_code == GTU
34141 && satisfies_constraint_I (x))
34142 || (outer_code == LTU
34143 && satisfies_constraint_P (x)))
34148 else if ((outer_code == PLUS
34149 && reg_or_add_cint_operand (x, VOIDmode))
34150 || (outer_code == MINUS
34151 && reg_or_sub_cint_operand (x, VOIDmode))
34152 || ((outer_code == SET
34153 || outer_code == IOR
34154 || outer_code == XOR)
34156 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34158 *total = COSTS_N_INSNS (1);
34164 case CONST_WIDE_INT:
34168 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34172 /* When optimizing for size, MEM should be slightly more expensive
34173 than generating address, e.g., (plus (reg) (const)).
34174 L1 cache latency is about two instructions. */
34175 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34176 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34177 *total += COSTS_N_INSNS (100);
34186 if (FLOAT_MODE_P (mode))
34187 *total = rs6000_cost->fp;
34189 *total = COSTS_N_INSNS (1);
34193 if (CONST_INT_P (XEXP (x, 1))
34194 && satisfies_constraint_I (XEXP (x, 1)))
34196 if (INTVAL (XEXP (x, 1)) >= -256
34197 && INTVAL (XEXP (x, 1)) <= 255)
34198 *total = rs6000_cost->mulsi_const9;
34200 *total = rs6000_cost->mulsi_const;
34202 else if (mode == SFmode)
34203 *total = rs6000_cost->fp;
34204 else if (FLOAT_MODE_P (mode))
34205 *total = rs6000_cost->dmul;
34206 else if (mode == DImode)
34207 *total = rs6000_cost->muldi;
34209 *total = rs6000_cost->mulsi;
34213 if (mode == SFmode)
34214 *total = rs6000_cost->fp;
34216 *total = rs6000_cost->dmul;
34221 if (FLOAT_MODE_P (mode))
34223 *total = mode == DFmode ? rs6000_cost->ddiv
34224 : rs6000_cost->sdiv;
34231 if (CONST_INT_P (XEXP (x, 1))
34232 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34234 if (code == DIV || code == MOD)
34236 *total = COSTS_N_INSNS (2);
34239 *total = COSTS_N_INSNS (1);
34243 if (GET_MODE (XEXP (x, 1)) == DImode)
34244 *total = rs6000_cost->divdi;
34246 *total = rs6000_cost->divsi;
34248 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34249 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34250 *total += COSTS_N_INSNS (2);
34254 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34258 *total = COSTS_N_INSNS (4);
34262 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34266 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34270 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34273 *total = COSTS_N_INSNS (1);
34277 if (CONST_INT_P (XEXP (x, 1)))
34279 rtx left = XEXP (x, 0);
34280 rtx_code left_code = GET_CODE (left);
34282 /* rotate-and-mask: 1 insn. */
34283 if ((left_code == ROTATE
34284 || left_code == ASHIFT
34285 || left_code == LSHIFTRT)
34286 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34288 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34289 if (!CONST_INT_P (XEXP (left, 1)))
34290 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34291 *total += COSTS_N_INSNS (1);
34295 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34296 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34297 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34298 || (val & 0xffff) == val
34299 || (val & 0xffff0000) == val
34300 || ((val & 0xffff) == 0 && mode == SImode))
34302 *total = rtx_cost (left, mode, AND, 0, speed);
34303 *total += COSTS_N_INSNS (1);
34308 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34310 *total = rtx_cost (left, mode, AND, 0, speed);
34311 *total += COSTS_N_INSNS (2);
34316 *total = COSTS_N_INSNS (1);
34321 *total = COSTS_N_INSNS (1);
34327 *total = COSTS_N_INSNS (1);
34331 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34332 the sign extend and shift separately within the insn. */
34333 if (TARGET_EXTSWSLI && mode == DImode
34334 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34335 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34346 /* Handle mul_highpart. */
34347 if (outer_code == TRUNCATE
34348 && GET_CODE (XEXP (x, 0)) == MULT)
34350 if (mode == DImode)
34351 *total = rs6000_cost->muldi;
34353 *total = rs6000_cost->mulsi;
34356 else if (outer_code == AND)
34359 *total = COSTS_N_INSNS (1);
34364 if (MEM_P (XEXP (x, 0)))
34367 *total = COSTS_N_INSNS (1);
34373 if (!FLOAT_MODE_P (mode))
34375 *total = COSTS_N_INSNS (1);
34381 case UNSIGNED_FLOAT:
34384 case FLOAT_TRUNCATE:
34385 *total = rs6000_cost->fp;
34389 if (mode == DFmode)
34390 *total = rs6000_cost->sfdf_convert;
34392 *total = rs6000_cost->fp;
34396 switch (XINT (x, 1))
34399 *total = rs6000_cost->fp;
34411 *total = COSTS_N_INSNS (1);
34414 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34416 *total = rs6000_cost->fp;
34425 /* Carry bit requires mode == Pmode.
34426 NEG or PLUS already counted so only add one. */
34428 && (outer_code == NEG || outer_code == PLUS))
34430 *total = COSTS_N_INSNS (1);
34438 if (outer_code == SET)
34440 if (XEXP (x, 1) == const0_rtx)
34442 *total = COSTS_N_INSNS (2);
34447 *total = COSTS_N_INSNS (3);
34452 if (outer_code == COMPARE)
34466 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34469 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34470 int opno, int *total, bool speed)
34472 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34475 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34476 "opno = %d, total = %d, speed = %s, x:\n",
34477 ret ? "complete" : "scan inner",
34478 GET_MODE_NAME (mode),
34479 GET_RTX_NAME (outer_code),
34482 speed ? "true" : "false");
34490 rs6000_insn_cost (rtx_insn *insn, bool speed)
34492 if (recog_memoized (insn) < 0)
34496 return get_attr_length (insn);
34498 int cost = get_attr_cost (insn);
34502 int n = get_attr_length (insn) / 4;
34503 enum attr_type type = get_attr_type (insn);
34510 cost = COSTS_N_INSNS (n + 1);
34514 switch (get_attr_size (insn))
34517 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34520 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34523 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34526 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34529 gcc_unreachable ();
34533 switch (get_attr_size (insn))
34536 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34539 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34542 gcc_unreachable ();
34547 cost = n * rs6000_cost->fp;
34550 cost = n * rs6000_cost->dmul;
34553 cost = n * rs6000_cost->sdiv;
34556 cost = n * rs6000_cost->ddiv;
34563 cost = COSTS_N_INSNS (n + 2);
34567 cost = COSTS_N_INSNS (n);
34573 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34576 rs6000_debug_address_cost (rtx x, machine_mode mode,
34577 addr_space_t as, bool speed)
34579 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34581 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34582 ret, speed ? "true" : "false");
34589 /* A C expression returning the cost of moving data from a register of class
34590 CLASS1 to one of CLASS2. */
34593 rs6000_register_move_cost (machine_mode mode,
34594 reg_class_t from, reg_class_t to)
34597 reg_class_t rclass;
34599 if (TARGET_DEBUG_COST)
34602 /* If we have VSX, we can easily move between FPR or Altivec registers,
34603 otherwise we can only easily move within classes.
34604 Do this first so we give best-case answers for union classes
34605 containing both gprs and vsx regs. */
34606 HARD_REG_SET to_vsx, from_vsx;
34607 COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
34608 AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
34609 COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
34610 AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
34611 if (!hard_reg_set_empty_p (to_vsx)
34612 && !hard_reg_set_empty_p (from_vsx)
34614 || hard_reg_set_intersect_p (to_vsx, from_vsx)))
34616 int reg = FIRST_FPR_REGNO;
34618 || (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
34619 && TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
34620 reg = FIRST_ALTIVEC_REGNO;
34621 ret = 2 * hard_regno_nregs (reg, mode);
34624 /* Moves from/to GENERAL_REGS. */
34625 else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
34626 || (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
34628 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34630 if (TARGET_DIRECT_MOVE)
34632 /* Keep the cost for direct moves above that for within
34633 a register class even if the actual processor cost is
34634 comparable. We do this because a direct move insn
34635 can't be a nop, whereas with ideal register
34636 allocation a move within the same class might turn
34637 out to be a nop. */
34638 if (rs6000_tune == PROCESSOR_POWER9)
34639 ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34641 ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34642 /* SFmode requires a conversion when moving between gprs
34644 if (mode == SFmode)
34648 ret = (rs6000_memory_move_cost (mode, rclass, false)
34649 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34652 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34654 else if (rclass == CR_REGS)
34657 /* For those processors that have slow LR/CTR moves, make them more
34658 expensive than memory in order to bias spills to memory .*/
34659 else if ((rs6000_tune == PROCESSOR_POWER6
34660 || rs6000_tune == PROCESSOR_POWER7
34661 || rs6000_tune == PROCESSOR_POWER8
34662 || rs6000_tune == PROCESSOR_POWER9)
34663 && reg_class_subset_p (rclass, SPECIAL_REGS))
34664 ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34667 /* A move will cost one instruction per GPR moved. */
34668 ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34671 /* Everything else has to go through GENERAL_REGS. */
34673 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34674 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34676 if (TARGET_DEBUG_COST)
34678 if (dbg_cost_ctrl == 1)
34680 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
34681 ret, GET_MODE_NAME (mode), reg_class_names[from],
34682 reg_class_names[to]);
34689 /* A C expressions returning the cost of moving data of MODE from a register to
34693 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34694 bool in ATTRIBUTE_UNUSED)
34698 if (TARGET_DEBUG_COST)
34701 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34702 ret = 4 * hard_regno_nregs (0, mode);
34703 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34704 || reg_classes_intersect_p (rclass, VSX_REGS)))
34705 ret = 4 * hard_regno_nregs (32, mode);
34706 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34707 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34709 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34711 if (TARGET_DEBUG_COST)
34713 if (dbg_cost_ctrl == 1)
34715 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34716 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34723 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
34725 The register allocator chooses GEN_OR_VSX_REGS for the allocno
34726 class if GENERAL_REGS and VSX_REGS cost is lower than the memory
34727 cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
34728 move cost between GENERAL_REGS and VSX_REGS low.
34730 It might seem reasonable to use a union class. After all, if usage
34731 of vsr is low and gpr high, it might make sense to spill gpr to vsr
34732 rather than memory. However, in cases where register pressure of
34733 both is high, like the cactus_adm spec test, allowing
34734 GEN_OR_VSX_REGS as the allocno class results in bad decisions in
34735 the first scheduling pass. This is partly due to an allocno of
34736 GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
34737 class, which gives too high a pressure for GENERAL_REGS and too low
34738 for VSX_REGS. So, force a choice of the subclass here.
34740 The best class is also the union if GENERAL_REGS and VSX_REGS have
34741 the same cost. In that case we do use GEN_OR_VSX_REGS as the
34742 allocno class, since trying to narrow down the class by regno mode
34743 is prone to error. For example, SImode is allowed in VSX regs and
34744 in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
34745 it would be wrong to choose an allocno of GENERAL_REGS based on
34749 rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
34750 reg_class_t allocno_class,
34751 reg_class_t best_class)
34753 switch (allocno_class)
34755 case GEN_OR_VSX_REGS:
34756 /* best_class must be a subset of allocno_class. */
34757 gcc_checking_assert (best_class == GEN_OR_VSX_REGS
34758 || best_class == GEN_OR_FLOAT_REGS
34759 || best_class == VSX_REGS
34760 || best_class == ALTIVEC_REGS
34761 || best_class == FLOAT_REGS
34762 || best_class == GENERAL_REGS
34763 || best_class == BASE_REGS);
34764 /* Use best_class but choose wider classes when copying from the
34765 wider class to best_class is cheap. This mimics IRA choice
34766 of allocno class. */
34767 if (best_class == BASE_REGS)
34768 return GENERAL_REGS;
34770 && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
34778 return allocno_class;
34781 /* Returns a code for a target-specific builtin that implements
34782 reciprocal of the function, or NULL_TREE if not available. */
34785 rs6000_builtin_reciprocal (tree fndecl)
34787 switch (DECL_FUNCTION_CODE (fndecl))
34789 case VSX_BUILTIN_XVSQRTDP:
34790 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34793 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34795 case VSX_BUILTIN_XVSQRTSP:
34796 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34799 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34806 /* Load up a constant. If the mode is a vector mode, splat the value across
34807 all of the vector elements. */
34810 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34814 if (mode == SFmode || mode == DFmode)
34816 rtx d = const_double_from_real_value (dconst, mode);
34817 reg = force_reg (mode, d);
34819 else if (mode == V4SFmode)
34821 rtx d = const_double_from_real_value (dconst, SFmode);
34822 rtvec v = gen_rtvec (4, d, d, d, d);
34823 reg = gen_reg_rtx (mode);
34824 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34826 else if (mode == V2DFmode)
34828 rtx d = const_double_from_real_value (dconst, DFmode);
34829 rtvec v = gen_rtvec (2, d, d);
34830 reg = gen_reg_rtx (mode);
34831 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34834 gcc_unreachable ();
34839 /* Generate an FMA instruction. */
34842 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34844 machine_mode mode = GET_MODE (target);
34847 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34848 gcc_assert (dst != NULL);
34851 emit_move_insn (target, dst);
34854 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34857 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34859 machine_mode mode = GET_MODE (dst);
34862 /* This is a tad more complicated, since the fnma_optab is for
34863 a different expression: fma(-m1, m2, a), which is the same
34864 thing except in the case of signed zeros.
34866 Fortunately we know that if FMA is supported that FNMSUB is
34867 also supported in the ISA. Just expand it directly. */
34869 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34871 r = gen_rtx_NEG (mode, a);
34872 r = gen_rtx_FMA (mode, m1, m2, r);
34873 r = gen_rtx_NEG (mode, r);
34874 emit_insn (gen_rtx_SET (dst, r));
34877 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34878 add a reg_note saying that this was a division. Support both scalar and
34879 vector divide. Assumes no trapping math and finite arguments. */
34882 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34884 machine_mode mode = GET_MODE (dst);
34885 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34888 /* Low precision estimates guarantee 5 bits of accuracy. High
34889 precision estimates guarantee 14 bits of accuracy. SFmode
34890 requires 23 bits of accuracy. DFmode requires 52 bits of
34891 accuracy. Each pass at least doubles the accuracy, leading
34892 to the following. */
34893 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34894 if (mode == DFmode || mode == V2DFmode)
34897 enum insn_code code = optab_handler (smul_optab, mode);
34898 insn_gen_fn gen_mul = GEN_FCN (code);
34900 gcc_assert (code != CODE_FOR_nothing);
34902 one = rs6000_load_constant_and_splat (mode, dconst1);
34904 /* x0 = 1./d estimate */
34905 x0 = gen_reg_rtx (mode);
34906 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34909 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34912 /* e0 = 1. - d * x0 */
34913 e0 = gen_reg_rtx (mode);
34914 rs6000_emit_nmsub (e0, d, x0, one);
34916 /* x1 = x0 + e0 * x0 */
34917 x1 = gen_reg_rtx (mode);
34918 rs6000_emit_madd (x1, e0, x0, x0);
34920 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34921 ++i, xprev = xnext, eprev = enext) {
34923 /* enext = eprev * eprev */
34924 enext = gen_reg_rtx (mode);
34925 emit_insn (gen_mul (enext, eprev, eprev));
34927 /* xnext = xprev + enext * xprev */
34928 xnext = gen_reg_rtx (mode);
34929 rs6000_emit_madd (xnext, enext, xprev, xprev);
34935 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34937 /* u = n * xprev */
34938 u = gen_reg_rtx (mode);
34939 emit_insn (gen_mul (u, n, xprev));
34941 /* v = n - (d * u) */
34942 v = gen_reg_rtx (mode);
34943 rs6000_emit_nmsub (v, d, u, n);
34945 /* dst = (v * xprev) + u */
34946 rs6000_emit_madd (dst, v, xprev, u);
34949 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34952 /* Goldschmidt's Algorithm for single/double-precision floating point
34953 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34956 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34958 machine_mode mode = GET_MODE (src);
34959 rtx e = gen_reg_rtx (mode);
34960 rtx g = gen_reg_rtx (mode);
34961 rtx h = gen_reg_rtx (mode);
34963 /* Low precision estimates guarantee 5 bits of accuracy. High
34964 precision estimates guarantee 14 bits of accuracy. SFmode
34965 requires 23 bits of accuracy. DFmode requires 52 bits of
34966 accuracy. Each pass at least doubles the accuracy, leading
34967 to the following. */
34968 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34969 if (mode == DFmode || mode == V2DFmode)
34974 enum insn_code code = optab_handler (smul_optab, mode);
34975 insn_gen_fn gen_mul = GEN_FCN (code);
34977 gcc_assert (code != CODE_FOR_nothing);
34979 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
34981 /* e = rsqrt estimate */
34982 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
34985 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34988 rtx zero = force_reg (mode, CONST0_RTX (mode));
34990 if (mode == SFmode)
34992 rtx target = emit_conditional_move (e, GT, src, zero, mode,
34995 emit_move_insn (e, target);
34999 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35000 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35004 /* g = sqrt estimate. */
35005 emit_insn (gen_mul (g, e, src));
35006 /* h = 1/(2*sqrt) estimate. */
35007 emit_insn (gen_mul (h, e, mhalf));
35013 rtx t = gen_reg_rtx (mode);
35014 rs6000_emit_nmsub (t, g, h, mhalf);
35015 /* Apply correction directly to 1/rsqrt estimate. */
35016 rs6000_emit_madd (dst, e, t, e);
35020 for (i = 0; i < passes; i++)
35022 rtx t1 = gen_reg_rtx (mode);
35023 rtx g1 = gen_reg_rtx (mode);
35024 rtx h1 = gen_reg_rtx (mode);
35026 rs6000_emit_nmsub (t1, g, h, mhalf);
35027 rs6000_emit_madd (g1, g, t1, g);
35028 rs6000_emit_madd (h1, h, t1, h);
35033 /* Multiply by 2 for 1/rsqrt. */
35034 emit_insn (gen_add3_insn (dst, h, h));
35039 rtx t = gen_reg_rtx (mode);
35040 rs6000_emit_nmsub (t, g, h, mhalf);
35041 rs6000_emit_madd (dst, g, t, g);
35047 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35048 (Power7) targets. DST is the target, and SRC is the argument operand. */
35051 rs6000_emit_popcount (rtx dst, rtx src)
35053 machine_mode mode = GET_MODE (dst);
35056 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35057 if (TARGET_POPCNTD)
35059 if (mode == SImode)
35060 emit_insn (gen_popcntdsi2 (dst, src));
35062 emit_insn (gen_popcntddi2 (dst, src));
35066 tmp1 = gen_reg_rtx (mode);
35068 if (mode == SImode)
35070 emit_insn (gen_popcntbsi2 (tmp1, src));
35071 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35073 tmp2 = force_reg (SImode, tmp2);
35074 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35078 emit_insn (gen_popcntbdi2 (tmp1, src));
35079 tmp2 = expand_mult (DImode, tmp1,
35080 GEN_INT ((HOST_WIDE_INT)
35081 0x01010101 << 32 | 0x01010101),
35083 tmp2 = force_reg (DImode, tmp2);
35084 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35089 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35090 target, and SRC is the argument operand. */
35093 rs6000_emit_parity (rtx dst, rtx src)
35095 machine_mode mode = GET_MODE (dst);
35098 tmp = gen_reg_rtx (mode);
35100 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35103 if (mode == SImode)
35105 emit_insn (gen_popcntbsi2 (tmp, src));
35106 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35110 emit_insn (gen_popcntbdi2 (tmp, src));
35111 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35116 if (mode == SImode)
35118 /* Is mult+shift >= shift+xor+shift+xor? */
35119 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35121 rtx tmp1, tmp2, tmp3, tmp4;
35123 tmp1 = gen_reg_rtx (SImode);
35124 emit_insn (gen_popcntbsi2 (tmp1, src));
35126 tmp2 = gen_reg_rtx (SImode);
35127 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35128 tmp3 = gen_reg_rtx (SImode);
35129 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35131 tmp4 = gen_reg_rtx (SImode);
35132 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35133 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35136 rs6000_emit_popcount (tmp, src);
35137 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35141 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35142 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35144 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35146 tmp1 = gen_reg_rtx (DImode);
35147 emit_insn (gen_popcntbdi2 (tmp1, src));
35149 tmp2 = gen_reg_rtx (DImode);
35150 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35151 tmp3 = gen_reg_rtx (DImode);
35152 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35154 tmp4 = gen_reg_rtx (DImode);
35155 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35156 tmp5 = gen_reg_rtx (DImode);
35157 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35159 tmp6 = gen_reg_rtx (DImode);
35160 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35161 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35164 rs6000_emit_popcount (tmp, src);
35165 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35169 /* Expand an Altivec constant permutation for little endian mode.
35170 OP0 and OP1 are the input vectors and TARGET is the output vector.
35171 SEL specifies the constant permutation vector.
35173 There are two issues: First, the two input operands must be
35174 swapped so that together they form a double-wide array in LE
35175 order. Second, the vperm instruction has surprising behavior
35176 in LE mode: it interprets the elements of the source vectors
35177 in BE mode ("left to right") and interprets the elements of
35178 the destination vector in LE mode ("right to left"). To
35179 correct for this, we must subtract each element of the permute
35180 control vector from 31.
35182 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35183 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35184 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35185 serve as the permute control vector. Then, in BE mode,
35189 places the desired result in vr9. However, in LE mode the
35190 vector contents will be
35192 vr10 = 00000003 00000002 00000001 00000000
35193 vr11 = 00000007 00000006 00000005 00000004
35195 The result of the vperm using the same permute control vector is
35197 vr9 = 05000000 07000000 01000000 03000000
35199 That is, the leftmost 4 bytes of vr10 are interpreted as the
35200 source for the rightmost 4 bytes of vr9, and so on.
35202 If we change the permute control vector to
35204 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35212 vr9 = 00000006 00000004 00000002 00000000. */
35215 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35216 const vec_perm_indices &sel)
35220 rtx constv, unspec;
35222 /* Unpack and adjust the constant selector. */
35223 for (i = 0; i < 16; ++i)
35225 unsigned int elt = 31 - (sel[i] & 31);
35226 perm[i] = GEN_INT (elt);
35229 /* Expand to a permute, swapping the inputs and using the
35230 adjusted selector. */
35232 op0 = force_reg (V16QImode, op0);
35234 op1 = force_reg (V16QImode, op1);
35236 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35237 constv = force_reg (V16QImode, constv);
35238 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35240 if (!REG_P (target))
35242 rtx tmp = gen_reg_rtx (V16QImode);
35243 emit_move_insn (tmp, unspec);
35247 emit_move_insn (target, unspec);
35250 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35251 permute control vector. But here it's not a constant, so we must
35252 generate a vector NAND or NOR to do the adjustment. */
35255 altivec_expand_vec_perm_le (rtx operands[4])
35257 rtx notx, iorx, unspec;
35258 rtx target = operands[0];
35259 rtx op0 = operands[1];
35260 rtx op1 = operands[2];
35261 rtx sel = operands[3];
35263 rtx norreg = gen_reg_rtx (V16QImode);
35264 machine_mode mode = GET_MODE (target);
35266 /* Get everything in regs so the pattern matches. */
35268 op0 = force_reg (mode, op0);
35270 op1 = force_reg (mode, op1);
35272 sel = force_reg (V16QImode, sel);
35273 if (!REG_P (target))
35274 tmp = gen_reg_rtx (mode);
35276 if (TARGET_P9_VECTOR)
35278 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35283 /* Invert the selector with a VNAND if available, else a VNOR.
35284 The VNAND is preferred for future fusion opportunities. */
35285 notx = gen_rtx_NOT (V16QImode, sel);
35286 iorx = (TARGET_P8_VECTOR
35287 ? gen_rtx_IOR (V16QImode, notx, notx)
35288 : gen_rtx_AND (V16QImode, notx, notx));
35289 emit_insn (gen_rtx_SET (norreg, iorx));
35291 /* Permute with operands reversed and adjusted selector. */
35292 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35296 /* Copy into target, possibly by way of a register. */
35297 if (!REG_P (target))
35299 emit_move_insn (tmp, unspec);
35303 emit_move_insn (target, unspec);
35306 /* Expand an Altivec constant permutation. Return true if we match
35307 an efficient implementation; false to fall back to VPERM.
35309 OP0 and OP1 are the input vectors and TARGET is the output vector.
35310 SEL specifies the constant permutation vector. */
35313 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35314 const vec_perm_indices &sel)
35316 struct altivec_perm_insn {
35317 HOST_WIDE_INT mask;
35318 enum insn_code impl;
35319 unsigned char perm[16];
35321 static const struct altivec_perm_insn patterns[] = {
35322 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35323 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35324 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35325 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35326 { OPTION_MASK_ALTIVEC,
35327 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35328 : CODE_FOR_altivec_vmrglb_direct),
35329 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35330 { OPTION_MASK_ALTIVEC,
35331 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35332 : CODE_FOR_altivec_vmrglh_direct),
35333 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35334 { OPTION_MASK_ALTIVEC,
35335 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35336 : CODE_FOR_altivec_vmrglw_direct),
35337 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35338 { OPTION_MASK_ALTIVEC,
35339 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35340 : CODE_FOR_altivec_vmrghb_direct),
35341 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35342 { OPTION_MASK_ALTIVEC,
35343 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35344 : CODE_FOR_altivec_vmrghh_direct),
35345 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35346 { OPTION_MASK_ALTIVEC,
35347 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35348 : CODE_FOR_altivec_vmrghw_direct),
35349 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35350 { OPTION_MASK_P8_VECTOR,
35351 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35352 : CODE_FOR_p8_vmrgow_v4sf_direct),
35353 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35354 { OPTION_MASK_P8_VECTOR,
35355 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35356 : CODE_FOR_p8_vmrgew_v4sf_direct),
35357 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35360 unsigned int i, j, elt, which;
35361 unsigned char perm[16];
35365 /* Unpack the constant selector. */
35366 for (i = which = 0; i < 16; ++i)
35369 which |= (elt < 16 ? 1 : 2);
35373 /* Simplify the constant selector based on operands. */
35377 gcc_unreachable ();
35381 if (!rtx_equal_p (op0, op1))
35386 for (i = 0; i < 16; ++i)
35398 /* Look for splat patterns. */
35403 for (i = 0; i < 16; ++i)
35404 if (perm[i] != elt)
35408 if (!BYTES_BIG_ENDIAN)
35410 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35416 for (i = 0; i < 16; i += 2)
35417 if (perm[i] != elt || perm[i + 1] != elt + 1)
35421 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35422 x = gen_reg_rtx (V8HImode);
35423 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35425 emit_move_insn (target, gen_lowpart (V16QImode, x));
35432 for (i = 0; i < 16; i += 4)
35434 || perm[i + 1] != elt + 1
35435 || perm[i + 2] != elt + 2
35436 || perm[i + 3] != elt + 3)
35440 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35441 x = gen_reg_rtx (V4SImode);
35442 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35444 emit_move_insn (target, gen_lowpart (V16QImode, x));
35450 /* Look for merge and pack patterns. */
35451 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35455 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35458 elt = patterns[j].perm[0];
35459 if (perm[0] == elt)
35461 else if (perm[0] == elt + 16)
35465 for (i = 1; i < 16; ++i)
35467 elt = patterns[j].perm[i];
35469 elt = (elt >= 16 ? elt - 16 : elt + 16);
35470 else if (one_vec && elt >= 16)
35472 if (perm[i] != elt)
35477 enum insn_code icode = patterns[j].impl;
35478 machine_mode omode = insn_data[icode].operand[0].mode;
35479 machine_mode imode = insn_data[icode].operand[1].mode;
35481 /* For little-endian, don't use vpkuwum and vpkuhum if the
35482 underlying vector type is not V4SI and V8HI, respectively.
35483 For example, using vpkuwum with a V8HI picks up the even
35484 halfwords (BE numbering) when the even halfwords (LE
35485 numbering) are what we need. */
35486 if (!BYTES_BIG_ENDIAN
35487 && icode == CODE_FOR_altivec_vpkuwum_direct
35489 && GET_MODE (op0) != V4SImode)
35491 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35493 if (!BYTES_BIG_ENDIAN
35494 && icode == CODE_FOR_altivec_vpkuhum_direct
35496 && GET_MODE (op0) != V8HImode)
35498 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35501 /* For little-endian, the two input operands must be swapped
35502 (or swapped back) to ensure proper right-to-left numbering
35504 if (swapped ^ !BYTES_BIG_ENDIAN)
35505 std::swap (op0, op1);
35506 if (imode != V16QImode)
35508 op0 = gen_lowpart (imode, op0);
35509 op1 = gen_lowpart (imode, op1);
35511 if (omode == V16QImode)
35514 x = gen_reg_rtx (omode);
35515 emit_insn (GEN_FCN (icode) (x, op0, op1));
35516 if (omode != V16QImode)
35517 emit_move_insn (target, gen_lowpart (V16QImode, x));
35522 if (!BYTES_BIG_ENDIAN)
35524 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35531 /* Expand a VSX Permute Doubleword constant permutation.
35532 Return true if we match an efficient implementation. */
35535 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35536 unsigned char perm0, unsigned char perm1)
35540 /* If both selectors come from the same operand, fold to single op. */
35541 if ((perm0 & 2) == (perm1 & 2))
35548 /* If both operands are equal, fold to simpler permutation. */
35549 if (rtx_equal_p (op0, op1))
35552 perm1 = (perm1 & 1) + 2;
35554 /* If the first selector comes from the second operand, swap. */
35555 else if (perm0 & 2)
35561 std::swap (op0, op1);
35563 /* If the second selector does not come from the second operand, fail. */
35564 else if ((perm1 & 2) == 0)
35568 if (target != NULL)
35570 machine_mode vmode, dmode;
35573 vmode = GET_MODE (target);
35574 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35575 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35576 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35577 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35578 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35579 emit_insn (gen_rtx_SET (target, x));
35584 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35587 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35588 rtx op1, const vec_perm_indices &sel)
35590 bool testing_p = !target;
35592 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35593 if (TARGET_ALTIVEC && testing_p)
35596 /* Check for ps_merge* or xxpermdi insns. */
35597 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35601 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35602 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35604 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35608 if (TARGET_ALTIVEC)
35610 /* Force the target-independent code to lower to V16QImode. */
35611 if (vmode != V16QImode)
35613 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35620 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35621 OP0 and OP1 are the input vectors and TARGET is the output vector.
35622 PERM specifies the constant permutation vector. */
35625 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35626 machine_mode vmode, const vec_perm_builder &perm)
35628 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35630 emit_move_insn (target, x);
35633 /* Expand an extract even operation. */
35636 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35638 machine_mode vmode = GET_MODE (target);
35639 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35640 vec_perm_builder perm (nelt, nelt, 1);
35642 for (i = 0; i < nelt; i++)
35643 perm.quick_push (i * 2);
35645 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35648 /* Expand a vector interleave operation. */
35651 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35653 machine_mode vmode = GET_MODE (target);
35654 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35655 vec_perm_builder perm (nelt, nelt, 1);
35657 high = (highp ? 0 : nelt / 2);
35658 for (i = 0; i < nelt / 2; i++)
35660 perm.quick_push (i + high);
35661 perm.quick_push (i + nelt + high);
35664 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35667 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35669 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35671 HOST_WIDE_INT hwi_scale (scale);
35672 REAL_VALUE_TYPE r_pow;
35673 rtvec v = rtvec_alloc (2);
35675 rtx scale_vec = gen_reg_rtx (V2DFmode);
35676 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35677 elt = const_double_from_real_value (r_pow, DFmode);
35678 RTVEC_ELT (v, 0) = elt;
35679 RTVEC_ELT (v, 1) = elt;
35680 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35681 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35684 /* Return an RTX representing where to find the function value of a
35685 function returning MODE. */
35687 rs6000_complex_function_value (machine_mode mode)
35689 unsigned int regno;
35691 machine_mode inner = GET_MODE_INNER (mode);
35692 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35694 if (TARGET_FLOAT128_TYPE
35696 || (mode == TCmode && TARGET_IEEEQUAD)))
35697 regno = ALTIVEC_ARG_RETURN;
35699 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35700 regno = FP_ARG_RETURN;
35704 regno = GP_ARG_RETURN;
35706 /* 32-bit is OK since it'll go in r3/r4. */
35707 if (TARGET_32BIT && inner_bytes >= 4)
35708 return gen_rtx_REG (mode, regno);
35711 if (inner_bytes >= 8)
35712 return gen_rtx_REG (mode, regno);
35714 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35716 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35717 GEN_INT (inner_bytes));
35718 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35721 /* Return an rtx describing a return value of MODE as a PARALLEL
35722 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35723 stride REG_STRIDE. */
35726 rs6000_parallel_return (machine_mode mode,
35727 int n_elts, machine_mode elt_mode,
35728 unsigned int regno, unsigned int reg_stride)
35730 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35733 for (i = 0; i < n_elts; i++)
35735 rtx r = gen_rtx_REG (elt_mode, regno);
35736 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35737 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35738 regno += reg_stride;
35744 /* Target hook for TARGET_FUNCTION_VALUE.
35746 An integer value is in r3 and a floating-point value is in fp1,
35747 unless -msoft-float. */
35750 rs6000_function_value (const_tree valtype,
35751 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35752 bool outgoing ATTRIBUTE_UNUSED)
35755 unsigned int regno;
35756 machine_mode elt_mode;
35759 /* Special handling for structs in darwin64. */
35761 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35763 CUMULATIVE_ARGS valcum;
35767 valcum.fregno = FP_ARG_MIN_REG;
35768 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35769 /* Do a trial code generation as if this were going to be passed as
35770 an argument; if any part goes in memory, we return NULL. */
35771 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35774 /* Otherwise fall through to standard ABI rules. */
35777 mode = TYPE_MODE (valtype);
35779 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35780 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35782 int first_reg, n_regs;
35784 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35786 /* _Decimal128 must use even/odd register pairs. */
35787 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35788 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35792 first_reg = ALTIVEC_ARG_RETURN;
35796 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35799 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35800 if (TARGET_32BIT && TARGET_POWERPC64)
35809 int count = GET_MODE_SIZE (mode) / 4;
35810 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35813 if ((INTEGRAL_TYPE_P (valtype)
35814 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35815 || POINTER_TYPE_P (valtype))
35816 mode = TARGET_32BIT ? SImode : DImode;
35818 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35819 /* _Decimal128 must use an even/odd register pair. */
35820 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35821 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35822 && !FLOAT128_VECTOR_P (mode))
35823 regno = FP_ARG_RETURN;
35824 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35825 && targetm.calls.split_complex_arg)
35826 return rs6000_complex_function_value (mode);
35827 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35828 return register is used in both cases, and we won't see V2DImode/V2DFmode
35829 for pure altivec, combine the two cases. */
35830 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35831 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35832 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35833 regno = ALTIVEC_ARG_RETURN;
35835 regno = GP_ARG_RETURN;
35837 return gen_rtx_REG (mode, regno);
35840 /* Define how to find the value returned by a library function
35841 assuming the value has mode MODE. */
35843 rs6000_libcall_value (machine_mode mode)
35845 unsigned int regno;
35847 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35848 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35849 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35851 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35852 /* _Decimal128 must use an even/odd register pair. */
35853 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35854 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35855 regno = FP_ARG_RETURN;
35856 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35857 return register is used in both cases, and we won't see V2DImode/V2DFmode
35858 for pure altivec, combine the two cases. */
35859 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35860 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35861 regno = ALTIVEC_ARG_RETURN;
35862 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35863 return rs6000_complex_function_value (mode);
35865 regno = GP_ARG_RETURN;
35867 return gen_rtx_REG (mode, regno);
35870 /* Compute register pressure classes. We implement the target hook to avoid
35871 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
35872 lead to incorrect estimates of number of available registers and therefor
35873 increased register pressure/spill. */
35875 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35880 pressure_classes[n++] = GENERAL_REGS;
35882 pressure_classes[n++] = VSX_REGS;
35885 if (TARGET_ALTIVEC)
35886 pressure_classes[n++] = ALTIVEC_REGS;
35887 if (TARGET_HARD_FLOAT)
35888 pressure_classes[n++] = FLOAT_REGS;
35890 pressure_classes[n++] = CR_REGS;
35891 pressure_classes[n++] = SPECIAL_REGS;
35896 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35897 Frame pointer elimination is automatically handled.
35899 For the RS/6000, if frame pointer elimination is being done, we would like
35900 to convert ap into fp, not sp.
35902 We need r30 if -mminimal-toc was specified, and there are constant pool
35906 rs6000_can_eliminate (const int from, const int to)
35908 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35909 ? ! frame_pointer_needed
35910 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35911 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35912 || constant_pool_empty_p ()
35916 /* Define the offset between two registers, FROM to be eliminated and its
35917 replacement TO, at the start of a routine. */
35919 rs6000_initial_elimination_offset (int from, int to)
35921 rs6000_stack_t *info = rs6000_stack_info ();
35922 HOST_WIDE_INT offset;
35924 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35925 offset = info->push_p ? 0 : -info->total_size;
35926 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35928 offset = info->push_p ? 0 : -info->total_size;
35929 if (FRAME_GROWS_DOWNWARD)
35930 offset += info->fixed_size + info->vars_size + info->parm_size;
35932 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35933 offset = FRAME_GROWS_DOWNWARD
35934 ? info->fixed_size + info->vars_size + info->parm_size
35936 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35937 offset = info->total_size;
35938 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35939 offset = info->push_p ? info->total_size : 0;
35940 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35943 gcc_unreachable ();
35948 /* Fill in sizes of registers used by unwinder. */
35951 rs6000_init_dwarf_reg_sizes_extra (tree address)
35953 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35956 machine_mode mode = TYPE_MODE (char_type_node);
35957 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35958 rtx mem = gen_rtx_MEM (BLKmode, addr);
35959 rtx value = gen_int_mode (16, mode);
35961 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35962 The unwinder still needs to know the size of Altivec registers. */
35964 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35966 int column = DWARF_REG_TO_UNWIND_COLUMN
35967 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35968 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35970 emit_move_insn (adjust_address (mem, mode, offset), value);
35975 /* Map internal gcc register numbers to debug format register numbers.
35976 FORMAT specifies the type of debug register number to use:
35977 0 -- debug information, except for frame-related sections
35978 1 -- DWARF .debug_frame section
35979 2 -- DWARF .eh_frame section */
35982 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
35984 /* On some platforms, we use the standard DWARF register
35985 numbering for .debug_info and .debug_frame. */
35986 if ((format == 0 && write_symbols == DWARF2_DEBUG) || format == 1)
35988 #ifdef RS6000_USE_DWARF_NUMBERING
35991 if (FP_REGNO_P (regno))
35992 return regno - FIRST_FPR_REGNO + 32;
35993 if (ALTIVEC_REGNO_P (regno))
35994 return regno - FIRST_ALTIVEC_REGNO + 1124;
35995 if (regno == LR_REGNO)
35997 if (regno == CTR_REGNO)
35999 if (regno == CA_REGNO)
36000 return 101; /* XER */
36001 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36002 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36003 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36004 to the DWARF reg for CR. */
36005 if (format == 1 && regno == CR2_REGNO)
36007 if (CR_REGNO_P (regno))
36008 return regno - CR0_REGNO + 86;
36009 if (regno == VRSAVE_REGNO)
36011 if (regno == VSCR_REGNO)
36014 /* These do not make much sense. */
36015 if (regno == FRAME_POINTER_REGNUM)
36017 if (regno == ARG_POINTER_REGNUM)
36022 gcc_unreachable ();
36026 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36027 information, and also for .eh_frame. */
36028 /* Translate the regnos to their numbers in GCC 7 (and before). */
36031 if (FP_REGNO_P (regno))
36032 return regno - FIRST_FPR_REGNO + 32;
36033 if (ALTIVEC_REGNO_P (regno))
36034 return regno - FIRST_ALTIVEC_REGNO + 77;
36035 if (regno == LR_REGNO)
36037 if (regno == CTR_REGNO)
36039 if (regno == CA_REGNO)
36040 return 76; /* XER */
36041 if (CR_REGNO_P (regno))
36042 return regno - CR0_REGNO + 68;
36043 if (regno == VRSAVE_REGNO)
36045 if (regno == VSCR_REGNO)
36048 if (regno == FRAME_POINTER_REGNUM)
36050 if (regno == ARG_POINTER_REGNUM)
36055 gcc_unreachable ();
36058 /* target hook eh_return_filter_mode */
36059 static scalar_int_mode
36060 rs6000_eh_return_filter_mode (void)
36062 return TARGET_32BIT ? SImode : word_mode;
36065 /* Target hook for translate_mode_attribute. */
36066 static machine_mode
36067 rs6000_translate_mode_attribute (machine_mode mode)
36069 if ((FLOAT128_IEEE_P (mode)
36070 && ieee128_float_type_node == long_double_type_node)
36071 || (FLOAT128_IBM_P (mode)
36072 && ibm128_float_type_node == long_double_type_node))
36073 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
36077 /* Target hook for scalar_mode_supported_p. */
36079 rs6000_scalar_mode_supported_p (scalar_mode mode)
36081 /* -m32 does not support TImode. This is the default, from
36082 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36083 same ABI as for -m32. But default_scalar_mode_supported_p allows
36084 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36085 for -mpowerpc64. */
36086 if (TARGET_32BIT && mode == TImode)
36089 if (DECIMAL_FLOAT_MODE_P (mode))
36090 return default_decimal_float_supported_p ();
36091 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36094 return default_scalar_mode_supported_p (mode);
36097 /* Target hook for vector_mode_supported_p. */
36099 rs6000_vector_mode_supported_p (machine_mode mode)
36101 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36102 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36104 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36111 /* Target hook for floatn_mode. */
36112 static opt_scalar_float_mode
36113 rs6000_floatn_mode (int n, bool extended)
36123 if (TARGET_FLOAT128_TYPE)
36124 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36126 return opt_scalar_float_mode ();
36129 return opt_scalar_float_mode ();
36132 /* Those are the only valid _FloatNx types. */
36133 gcc_unreachable ();
36147 if (TARGET_FLOAT128_TYPE)
36148 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36150 return opt_scalar_float_mode ();
36153 return opt_scalar_float_mode ();
36159 /* Target hook for c_mode_for_suffix. */
36160 static machine_mode
36161 rs6000_c_mode_for_suffix (char suffix)
36163 if (TARGET_FLOAT128_TYPE)
36165 if (suffix == 'q' || suffix == 'Q')
36166 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36168 /* At the moment, we are not defining a suffix for IBM extended double.
36169 If/when the default for -mabi=ieeelongdouble is changed, and we want
36170 to support __ibm128 constants in legacy library code, we may need to
36171 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36172 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36173 __float80 constants. */
36179 /* Target hook for invalid_arg_for_unprototyped_fn. */
36180 static const char *
36181 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36183 return (!rs6000_darwin64_abi
36185 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36186 && (funcdecl == NULL_TREE
36187 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36188 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36189 ? N_("AltiVec argument passed to unprototyped function")
36193 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36194 setup by using __stack_chk_fail_local hidden function instead of
36195 calling __stack_chk_fail directly. Otherwise it is better to call
36196 __stack_chk_fail directly. */
36198 static tree ATTRIBUTE_UNUSED
36199 rs6000_stack_protect_fail (void)
36201 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36202 ? default_hidden_stack_protect_fail ()
36203 : default_external_stack_protect_fail ();
36206 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36209 static unsigned HOST_WIDE_INT
36210 rs6000_asan_shadow_offset (void)
36212 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36216 /* Mask options that we want to support inside of attribute((target)) and
36217 #pragma GCC target operations. Note, we do not include things like
36218 64/32-bit, endianness, hard/soft floating point, etc. that would have
36219 different calling sequences. */
36221 struct rs6000_opt_mask {
36222 const char *name; /* option name */
36223 HOST_WIDE_INT mask; /* mask to set */
36224 bool invert; /* invert sense of mask */
36225 bool valid_target; /* option is a target option */
36228 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36230 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36231 { "cmpb", OPTION_MASK_CMPB, false, true },
36232 { "crypto", OPTION_MASK_CRYPTO, false, true },
36233 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36234 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36235 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36237 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36238 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36239 { "fprnd", OPTION_MASK_FPRND, false, true },
36240 { "hard-dfp", OPTION_MASK_DFP, false, true },
36241 { "htm", OPTION_MASK_HTM, false, true },
36242 { "isel", OPTION_MASK_ISEL, false, true },
36243 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36244 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36245 { "modulo", OPTION_MASK_MODULO, false, true },
36246 { "mulhw", OPTION_MASK_MULHW, false, true },
36247 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36248 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36249 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36250 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36251 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36252 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36253 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36254 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36255 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36256 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36257 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36258 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36259 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36260 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36261 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36262 { "string", 0, false, true },
36263 { "update", OPTION_MASK_NO_UPDATE, true , true },
36264 { "vsx", OPTION_MASK_VSX, false, true },
36265 #ifdef OPTION_MASK_64BIT
36267 { "aix64", OPTION_MASK_64BIT, false, false },
36268 { "aix32", OPTION_MASK_64BIT, true, false },
36270 { "64", OPTION_MASK_64BIT, false, false },
36271 { "32", OPTION_MASK_64BIT, true, false },
36274 #ifdef OPTION_MASK_EABI
36275 { "eabi", OPTION_MASK_EABI, false, false },
36277 #ifdef OPTION_MASK_LITTLE_ENDIAN
36278 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36279 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36281 #ifdef OPTION_MASK_RELOCATABLE
36282 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36284 #ifdef OPTION_MASK_STRICT_ALIGN
36285 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36287 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36288 { "string", 0, false, false },
36291 /* Builtin mask mapping for printing the flags. */
36292 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36294 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36295 { "vsx", RS6000_BTM_VSX, false, false },
36296 { "fre", RS6000_BTM_FRE, false, false },
36297 { "fres", RS6000_BTM_FRES, false, false },
36298 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36299 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36300 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36301 { "cell", RS6000_BTM_CELL, false, false },
36302 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36303 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36304 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36305 { "crypto", RS6000_BTM_CRYPTO, false, false },
36306 { "htm", RS6000_BTM_HTM, false, false },
36307 { "hard-dfp", RS6000_BTM_DFP, false, false },
36308 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36309 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36310 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36311 { "float128", RS6000_BTM_FLOAT128, false, false },
36312 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36315 /* Option variables that we want to support inside attribute((target)) and
36316 #pragma GCC target operations. */
36318 struct rs6000_opt_var {
36319 const char *name; /* option name */
36320 size_t global_offset; /* offset of the option in global_options. */
36321 size_t target_offset; /* offset of the option in target options. */
36324 static struct rs6000_opt_var const rs6000_opt_vars[] =
36327 offsetof (struct gcc_options, x_TARGET_FRIZ),
36328 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36329 { "avoid-indexed-addresses",
36330 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36331 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36333 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36334 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36335 { "optimize-swaps",
36336 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36337 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36338 { "allow-movmisalign",
36339 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36340 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36342 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36343 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36345 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36346 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36347 { "align-branch-targets",
36348 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36349 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36351 offsetof (struct gcc_options, x_tls_markers),
36352 offsetof (struct cl_target_option, x_tls_markers), },
36354 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36355 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36357 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36358 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36359 { "speculate-indirect-jumps",
36360 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36361 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36364 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36365 parsing. Return true if there were no errors. */
36368 rs6000_inner_target_options (tree args, bool attr_p)
36372 if (args == NULL_TREE)
36375 else if (TREE_CODE (args) == STRING_CST)
36377 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36380 while ((q = strtok (p, ",")) != NULL)
36382 bool error_p = false;
36383 bool not_valid_p = false;
36384 const char *cpu_opt = NULL;
36387 if (strncmp (q, "cpu=", 4) == 0)
36389 int cpu_index = rs6000_cpu_name_lookup (q+4);
36390 if (cpu_index >= 0)
36391 rs6000_cpu_index = cpu_index;
36398 else if (strncmp (q, "tune=", 5) == 0)
36400 int tune_index = rs6000_cpu_name_lookup (q+5);
36401 if (tune_index >= 0)
36402 rs6000_tune_index = tune_index;
36412 bool invert = false;
36416 if (strncmp (r, "no-", 3) == 0)
36422 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36423 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36425 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36427 if (!rs6000_opt_masks[i].valid_target)
36428 not_valid_p = true;
36432 rs6000_isa_flags_explicit |= mask;
36434 /* VSX needs altivec, so -mvsx automagically sets
36435 altivec and disables -mavoid-indexed-addresses. */
36438 if (mask == OPTION_MASK_VSX)
36440 mask |= OPTION_MASK_ALTIVEC;
36441 TARGET_AVOID_XFORM = 0;
36445 if (rs6000_opt_masks[i].invert)
36449 rs6000_isa_flags &= ~mask;
36451 rs6000_isa_flags |= mask;
36456 if (error_p && !not_valid_p)
36458 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36459 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36461 size_t j = rs6000_opt_vars[i].global_offset;
36462 *((int *) ((char *)&global_options + j)) = !invert;
36464 not_valid_p = false;
36472 const char *eprefix, *esuffix;
36477 eprefix = "__attribute__((__target__(";
36482 eprefix = "#pragma GCC target ";
36487 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36489 else if (not_valid_p)
36490 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36492 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36497 else if (TREE_CODE (args) == TREE_LIST)
36501 tree value = TREE_VALUE (args);
36504 bool ret2 = rs6000_inner_target_options (value, attr_p);
36508 args = TREE_CHAIN (args);
36510 while (args != NULL_TREE);
36515 error ("attribute %<target%> argument not a string");
36522 /* Print out the target options as a list for -mdebug=target. */
36525 rs6000_debug_target_options (tree args, const char *prefix)
36527 if (args == NULL_TREE)
36528 fprintf (stderr, "%s<NULL>", prefix);
36530 else if (TREE_CODE (args) == STRING_CST)
36532 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36535 while ((q = strtok (p, ",")) != NULL)
36538 fprintf (stderr, "%s\"%s\"", prefix, q);
36543 else if (TREE_CODE (args) == TREE_LIST)
36547 tree value = TREE_VALUE (args);
36550 rs6000_debug_target_options (value, prefix);
36553 args = TREE_CHAIN (args);
36555 while (args != NULL_TREE);
36559 gcc_unreachable ();
36565 /* Hook to validate attribute((target("..."))). */
36568 rs6000_valid_attribute_p (tree fndecl,
36569 tree ARG_UNUSED (name),
36573 struct cl_target_option cur_target;
36576 tree new_target, new_optimize;
36577 tree func_optimize;
36579 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36581 if (TARGET_DEBUG_TARGET)
36583 tree tname = DECL_NAME (fndecl);
36584 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36586 fprintf (stderr, "function: %.*s\n",
36587 (int) IDENTIFIER_LENGTH (tname),
36588 IDENTIFIER_POINTER (tname));
36590 fprintf (stderr, "function: unknown\n");
36592 fprintf (stderr, "args:");
36593 rs6000_debug_target_options (args, " ");
36594 fprintf (stderr, "\n");
36597 fprintf (stderr, "flags: 0x%x\n", flags);
36599 fprintf (stderr, "--------------------\n");
36602 /* attribute((target("default"))) does nothing, beyond
36603 affecting multi-versioning. */
36604 if (TREE_VALUE (args)
36605 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36606 && TREE_CHAIN (args) == NULL_TREE
36607 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36610 old_optimize = build_optimization_node (&global_options);
36611 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36613 /* If the function changed the optimization levels as well as setting target
36614 options, start with the optimizations specified. */
36615 if (func_optimize && func_optimize != old_optimize)
36616 cl_optimization_restore (&global_options,
36617 TREE_OPTIMIZATION (func_optimize));
36619 /* The target attributes may also change some optimization flags, so update
36620 the optimization options if necessary. */
36621 cl_target_option_save (&cur_target, &global_options);
36622 rs6000_cpu_index = rs6000_tune_index = -1;
36623 ret = rs6000_inner_target_options (args, true);
36625 /* Set up any additional state. */
36628 ret = rs6000_option_override_internal (false);
36629 new_target = build_target_option_node (&global_options);
36634 new_optimize = build_optimization_node (&global_options);
36641 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36643 if (old_optimize != new_optimize)
36644 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36647 cl_target_option_restore (&global_options, &cur_target);
36649 if (old_optimize != new_optimize)
36650 cl_optimization_restore (&global_options,
36651 TREE_OPTIMIZATION (old_optimize));
36657 /* Hook to validate the current #pragma GCC target and set the state, and
36658 update the macros based on what was changed. If ARGS is NULL, then
36659 POP_TARGET is used to reset the options. */
36662 rs6000_pragma_target_parse (tree args, tree pop_target)
36664 tree prev_tree = build_target_option_node (&global_options);
36666 struct cl_target_option *prev_opt, *cur_opt;
36667 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36668 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36670 if (TARGET_DEBUG_TARGET)
36672 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36673 fprintf (stderr, "args:");
36674 rs6000_debug_target_options (args, " ");
36675 fprintf (stderr, "\n");
36679 fprintf (stderr, "pop_target:\n");
36680 debug_tree (pop_target);
36683 fprintf (stderr, "pop_target: <NULL>\n");
36685 fprintf (stderr, "--------------------\n");
36690 cur_tree = ((pop_target)
36692 : target_option_default_node);
36693 cl_target_option_restore (&global_options,
36694 TREE_TARGET_OPTION (cur_tree));
36698 rs6000_cpu_index = rs6000_tune_index = -1;
36699 if (!rs6000_inner_target_options (args, false)
36700 || !rs6000_option_override_internal (false)
36701 || (cur_tree = build_target_option_node (&global_options))
36704 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36705 fprintf (stderr, "invalid pragma\n");
36711 target_option_current_node = cur_tree;
36712 rs6000_activate_target_options (target_option_current_node);
36714 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36715 change the macros that are defined. */
36716 if (rs6000_target_modify_macros_ptr)
36718 prev_opt = TREE_TARGET_OPTION (prev_tree);
36719 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36720 prev_flags = prev_opt->x_rs6000_isa_flags;
36722 cur_opt = TREE_TARGET_OPTION (cur_tree);
36723 cur_flags = cur_opt->x_rs6000_isa_flags;
36724 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36726 diff_bumask = (prev_bumask ^ cur_bumask);
36727 diff_flags = (prev_flags ^ cur_flags);
36729 if ((diff_flags != 0) || (diff_bumask != 0))
36731 /* Delete old macros. */
36732 rs6000_target_modify_macros_ptr (false,
36733 prev_flags & diff_flags,
36734 prev_bumask & diff_bumask);
36736 /* Define new macros. */
36737 rs6000_target_modify_macros_ptr (true,
36738 cur_flags & diff_flags,
36739 cur_bumask & diff_bumask);
36747 /* Remember the last target of rs6000_set_current_function. */
36748 static GTY(()) tree rs6000_previous_fndecl;
36750 /* Restore target's globals from NEW_TREE and invalidate the
36751 rs6000_previous_fndecl cache. */
36754 rs6000_activate_target_options (tree new_tree)
36756 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36757 if (TREE_TARGET_GLOBALS (new_tree))
36758 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36759 else if (new_tree == target_option_default_node)
36760 restore_target_globals (&default_target_globals);
36762 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36763 rs6000_previous_fndecl = NULL_TREE;
36766 /* Establish appropriate back-end context for processing the function
36767 FNDECL. The argument might be NULL to indicate processing at top
36768 level, outside of any function scope. */
36770 rs6000_set_current_function (tree fndecl)
36772 if (TARGET_DEBUG_TARGET)
36774 fprintf (stderr, "\n==================== rs6000_set_current_function");
36777 fprintf (stderr, ", fndecl %s (%p)",
36778 (DECL_NAME (fndecl)
36779 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36780 : "<unknown>"), (void *)fndecl);
36782 if (rs6000_previous_fndecl)
36783 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36785 fprintf (stderr, "\n");
36788 /* Only change the context if the function changes. This hook is called
36789 several times in the course of compiling a function, and we don't want to
36790 slow things down too much or call target_reinit when it isn't safe. */
36791 if (fndecl == rs6000_previous_fndecl)
36795 if (rs6000_previous_fndecl == NULL_TREE)
36796 old_tree = target_option_current_node;
36797 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36798 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36800 old_tree = target_option_default_node;
36803 if (fndecl == NULL_TREE)
36805 if (old_tree != target_option_current_node)
36806 new_tree = target_option_current_node;
36808 new_tree = NULL_TREE;
36812 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36813 if (new_tree == NULL_TREE)
36814 new_tree = target_option_default_node;
36817 if (TARGET_DEBUG_TARGET)
36821 fprintf (stderr, "\nnew fndecl target specific options:\n");
36822 debug_tree (new_tree);
36827 fprintf (stderr, "\nold fndecl target specific options:\n");
36828 debug_tree (old_tree);
36831 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36832 fprintf (stderr, "--------------------\n");
36835 if (new_tree && old_tree != new_tree)
36836 rs6000_activate_target_options (new_tree);
36839 rs6000_previous_fndecl = fndecl;
36843 /* Save the current options */
36846 rs6000_function_specific_save (struct cl_target_option *ptr,
36847 struct gcc_options *opts)
36849 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36850 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36853 /* Restore the current options */
36856 rs6000_function_specific_restore (struct gcc_options *opts,
36857 struct cl_target_option *ptr)
36860 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36861 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36862 (void) rs6000_option_override_internal (false);
36865 /* Print the current options */
36868 rs6000_function_specific_print (FILE *file, int indent,
36869 struct cl_target_option *ptr)
36871 rs6000_print_isa_options (file, indent, "Isa options set",
36872 ptr->x_rs6000_isa_flags);
36874 rs6000_print_isa_options (file, indent, "Isa options explicit",
36875 ptr->x_rs6000_isa_flags_explicit);
36878 /* Helper function to print the current isa or misc options on a line. */
36881 rs6000_print_options_internal (FILE *file,
36883 const char *string,
36884 HOST_WIDE_INT flags,
36885 const char *prefix,
36886 const struct rs6000_opt_mask *opts,
36887 size_t num_elements)
36890 size_t start_column = 0;
36892 size_t max_column = 120;
36893 size_t prefix_len = strlen (prefix);
36894 size_t comma_len = 0;
36895 const char *comma = "";
36898 start_column += fprintf (file, "%*s", indent, "");
36902 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36906 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36908 /* Print the various mask options. */
36909 cur_column = start_column;
36910 for (i = 0; i < num_elements; i++)
36912 bool invert = opts[i].invert;
36913 const char *name = opts[i].name;
36914 const char *no_str = "";
36915 HOST_WIDE_INT mask = opts[i].mask;
36916 size_t len = comma_len + prefix_len + strlen (name);
36920 if ((flags & mask) == 0)
36923 len += sizeof ("no-") - 1;
36931 if ((flags & mask) != 0)
36934 len += sizeof ("no-") - 1;
36941 if (cur_column > max_column)
36943 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36944 cur_column = start_column + len;
36948 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36950 comma_len = sizeof (", ") - 1;
36953 fputs ("\n", file);
36956 /* Helper function to print the current isa options on a line. */
36959 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36960 HOST_WIDE_INT flags)
36962 rs6000_print_options_internal (file, indent, string, flags, "-m",
36963 &rs6000_opt_masks[0],
36964 ARRAY_SIZE (rs6000_opt_masks));
36968 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36969 HOST_WIDE_INT flags)
36971 rs6000_print_options_internal (file, indent, string, flags, "",
36972 &rs6000_builtin_mask_names[0],
36973 ARRAY_SIZE (rs6000_builtin_mask_names));
36976 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36977 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36978 -mupper-regs-df, etc.).
36980 If the user used -mno-power8-vector, we need to turn off all of the implicit
36981 ISA 2.07 and 3.0 options that relate to the vector unit.
36983 If the user used -mno-power9-vector, we need to turn off all of the implicit
36984 ISA 3.0 options that relate to the vector unit.
36986 This function does not handle explicit options such as the user specifying
36987 -mdirect-move. These are handled in rs6000_option_override_internal, and
36988 the appropriate error is given if needed.
36990 We return a mask of all of the implicit options that should not be enabled
36993 static HOST_WIDE_INT
36994 rs6000_disable_incompatible_switches (void)
36996 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
36999 static const struct {
37000 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37001 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37002 const char *const name; /* name of the switch. */
37004 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37005 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37006 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37009 for (i = 0; i < ARRAY_SIZE (flags); i++)
37011 HOST_WIDE_INT no_flag = flags[i].no_flag;
37013 if ((rs6000_isa_flags & no_flag) == 0
37014 && (rs6000_isa_flags_explicit & no_flag) != 0)
37016 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37017 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37023 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37024 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37026 set_flags &= ~rs6000_opt_masks[j].mask;
37027 error ("%<-mno-%s%> turns off %<-m%s%>",
37029 rs6000_opt_masks[j].name);
37032 gcc_assert (!set_flags);
37035 rs6000_isa_flags &= ~dep_flags;
37036 ignore_masks |= no_flag | dep_flags;
37040 return ignore_masks;
37044 /* Helper function for printing the function name when debugging. */
37046 static const char *
37047 get_decl_name (tree fn)
37054 name = DECL_NAME (fn);
37056 return "<no-name>";
37058 return IDENTIFIER_POINTER (name);
37061 /* Return the clone id of the target we are compiling code for in a target
37062 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37063 the priority list for the target clones (ordered from lowest to
37067 rs6000_clone_priority (tree fndecl)
37069 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37070 HOST_WIDE_INT isa_masks;
37071 int ret = CLONE_DEFAULT;
37072 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37073 const char *attrs_str = NULL;
37075 attrs = TREE_VALUE (TREE_VALUE (attrs));
37076 attrs_str = TREE_STRING_POINTER (attrs);
37078 /* Return priority zero for default function. Return the ISA needed for the
37079 function if it is not the default. */
37080 if (strcmp (attrs_str, "default") != 0)
37082 if (fn_opts == NULL_TREE)
37083 fn_opts = target_option_default_node;
37085 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37086 isa_masks = rs6000_isa_flags;
37088 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37090 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37091 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37095 if (TARGET_DEBUG_TARGET)
37096 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37097 get_decl_name (fndecl), ret);
37102 /* This compares the priority of target features in function DECL1 and DECL2.
37103 It returns positive value if DECL1 is higher priority, negative value if
37104 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37105 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37108 rs6000_compare_version_priority (tree decl1, tree decl2)
37110 int priority1 = rs6000_clone_priority (decl1);
37111 int priority2 = rs6000_clone_priority (decl2);
37112 int ret = priority1 - priority2;
37114 if (TARGET_DEBUG_TARGET)
37115 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37116 get_decl_name (decl1), get_decl_name (decl2), ret);
37121 /* Make a dispatcher declaration for the multi-versioned function DECL.
37122 Calls to DECL function will be replaced with calls to the dispatcher
37123 by the front-end. Returns the decl of the dispatcher function. */
37126 rs6000_get_function_versions_dispatcher (void *decl)
37128 tree fn = (tree) decl;
37129 struct cgraph_node *node = NULL;
37130 struct cgraph_node *default_node = NULL;
37131 struct cgraph_function_version_info *node_v = NULL;
37132 struct cgraph_function_version_info *first_v = NULL;
37134 tree dispatch_decl = NULL;
37136 struct cgraph_function_version_info *default_version_info = NULL;
37137 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37139 if (TARGET_DEBUG_TARGET)
37140 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37141 get_decl_name (fn));
37143 node = cgraph_node::get (fn);
37144 gcc_assert (node != NULL);
37146 node_v = node->function_version ();
37147 gcc_assert (node_v != NULL);
37149 if (node_v->dispatcher_resolver != NULL)
37150 return node_v->dispatcher_resolver;
37152 /* Find the default version and make it the first node. */
37154 /* Go to the beginning of the chain. */
37155 while (first_v->prev != NULL)
37156 first_v = first_v->prev;
37158 default_version_info = first_v;
37159 while (default_version_info != NULL)
37161 const tree decl2 = default_version_info->this_node->decl;
37162 if (is_function_default_version (decl2))
37164 default_version_info = default_version_info->next;
37167 /* If there is no default node, just return NULL. */
37168 if (default_version_info == NULL)
37171 /* Make default info the first node. */
37172 if (first_v != default_version_info)
37174 default_version_info->prev->next = default_version_info->next;
37175 if (default_version_info->next)
37176 default_version_info->next->prev = default_version_info->prev;
37177 first_v->prev = default_version_info;
37178 default_version_info->next = first_v;
37179 default_version_info->prev = NULL;
37182 default_node = default_version_info->this_node;
37184 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37185 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37186 "%<target_clones%> attribute needs GLIBC (2.23 and newer) that "
37187 "exports hardware capability bits");
37190 if (targetm.has_ifunc_p ())
37192 struct cgraph_function_version_info *it_v = NULL;
37193 struct cgraph_node *dispatcher_node = NULL;
37194 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37196 /* Right now, the dispatching is done via ifunc. */
37197 dispatch_decl = make_dispatcher_decl (default_node->decl);
37199 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37200 gcc_assert (dispatcher_node != NULL);
37201 dispatcher_node->dispatcher_function = 1;
37202 dispatcher_version_info
37203 = dispatcher_node->insert_new_function_version ();
37204 dispatcher_version_info->next = default_version_info;
37205 dispatcher_node->definition = 1;
37207 /* Set the dispatcher for all the versions. */
37208 it_v = default_version_info;
37209 while (it_v != NULL)
37211 it_v->dispatcher_resolver = dispatch_decl;
37217 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37218 "multiversioning needs ifunc which is not supported "
37223 return dispatch_decl;
37226 /* Make the resolver function decl to dispatch the versions of a multi-
37227 versioned function, DEFAULT_DECL. Create an empty basic block in the
37228 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37232 make_resolver_func (const tree default_decl,
37233 const tree dispatch_decl,
37234 basic_block *empty_bb)
37236 /* Make the resolver function static. The resolver function returns
37238 tree decl_name = clone_function_name (default_decl, "resolver");
37239 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37240 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37241 tree decl = build_fn_decl (resolver_name, type);
37242 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37244 DECL_NAME (decl) = decl_name;
37245 TREE_USED (decl) = 1;
37246 DECL_ARTIFICIAL (decl) = 1;
37247 DECL_IGNORED_P (decl) = 0;
37248 TREE_PUBLIC (decl) = 0;
37249 DECL_UNINLINABLE (decl) = 1;
37251 /* Resolver is not external, body is generated. */
37252 DECL_EXTERNAL (decl) = 0;
37253 DECL_EXTERNAL (dispatch_decl) = 0;
37255 DECL_CONTEXT (decl) = NULL_TREE;
37256 DECL_INITIAL (decl) = make_node (BLOCK);
37257 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37259 /* Build result decl and add to function_decl. */
37260 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37261 DECL_CONTEXT (t) = decl;
37262 DECL_ARTIFICIAL (t) = 1;
37263 DECL_IGNORED_P (t) = 1;
37264 DECL_RESULT (decl) = t;
37266 gimplify_function_tree (decl);
37267 push_cfun (DECL_STRUCT_FUNCTION (decl));
37268 *empty_bb = init_lowered_empty_function (decl, false,
37269 profile_count::uninitialized ());
37271 cgraph_node::add_new_function (decl, true);
37272 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37276 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37277 DECL_ATTRIBUTES (dispatch_decl)
37278 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37280 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37285 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37286 return a pointer to VERSION_DECL if we are running on a machine that
37287 supports the index CLONE_ISA hardware architecture bits. This function will
37288 be called during version dispatch to decide which function version to
37289 execute. It returns the basic block at the end, to which more conditions
37293 add_condition_to_bb (tree function_decl, tree version_decl,
37294 int clone_isa, basic_block new_bb)
37296 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37298 gcc_assert (new_bb != NULL);
37299 gimple_seq gseq = bb_seq (new_bb);
37302 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37303 build_fold_addr_expr (version_decl));
37304 tree result_var = create_tmp_var (ptr_type_node);
37305 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37306 gimple *return_stmt = gimple_build_return (result_var);
37308 if (clone_isa == CLONE_DEFAULT)
37310 gimple_seq_add_stmt (&gseq, convert_stmt);
37311 gimple_seq_add_stmt (&gseq, return_stmt);
37312 set_bb_seq (new_bb, gseq);
37313 gimple_set_bb (convert_stmt, new_bb);
37314 gimple_set_bb (return_stmt, new_bb);
37319 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37320 tree cond_var = create_tmp_var (bool_int_type_node);
37321 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37322 const char *arg_str = rs6000_clone_map[clone_isa].name;
37323 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37324 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37325 gimple_call_set_lhs (call_cond_stmt, cond_var);
37327 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37328 gimple_set_bb (call_cond_stmt, new_bb);
37329 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37331 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37332 NULL_TREE, NULL_TREE);
37333 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37334 gimple_set_bb (if_else_stmt, new_bb);
37335 gimple_seq_add_stmt (&gseq, if_else_stmt);
37337 gimple_seq_add_stmt (&gseq, convert_stmt);
37338 gimple_seq_add_stmt (&gseq, return_stmt);
37339 set_bb_seq (new_bb, gseq);
37341 basic_block bb1 = new_bb;
37342 edge e12 = split_block (bb1, if_else_stmt);
37343 basic_block bb2 = e12->dest;
37344 e12->flags &= ~EDGE_FALLTHRU;
37345 e12->flags |= EDGE_TRUE_VALUE;
37347 edge e23 = split_block (bb2, return_stmt);
37348 gimple_set_bb (convert_stmt, bb2);
37349 gimple_set_bb (return_stmt, bb2);
37351 basic_block bb3 = e23->dest;
37352 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37355 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37361 /* This function generates the dispatch function for multi-versioned functions.
37362 DISPATCH_DECL is the function which will contain the dispatch logic.
37363 FNDECLS are the function choices for dispatch, and is a tree chain.
37364 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37365 code is generated. */
37368 dispatch_function_versions (tree dispatch_decl,
37370 basic_block *empty_bb)
37374 vec<tree> *fndecls;
37375 tree clones[CLONE_MAX];
37377 if (TARGET_DEBUG_TARGET)
37378 fputs ("dispatch_function_versions, top\n", stderr);
37380 gcc_assert (dispatch_decl != NULL
37381 && fndecls_p != NULL
37382 && empty_bb != NULL);
37384 /* fndecls_p is actually a vector. */
37385 fndecls = static_cast<vec<tree> *> (fndecls_p);
37387 /* At least one more version other than the default. */
37388 gcc_assert (fndecls->length () >= 2);
37390 /* The first version in the vector is the default decl. */
37391 memset ((void *) clones, '\0', sizeof (clones));
37392 clones[CLONE_DEFAULT] = (*fndecls)[0];
37394 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37395 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37396 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37397 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37398 to insert the code here to do the call. */
37400 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37402 int priority = rs6000_clone_priority (ele);
37403 if (!clones[priority])
37404 clones[priority] = ele;
37407 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37410 if (TARGET_DEBUG_TARGET)
37411 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37412 ix, get_decl_name (clones[ix]));
37414 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37421 /* Generate the dispatching code body to dispatch multi-versioned function
37422 DECL. The target hook is called to process the "target" attributes and
37423 provide the code to dispatch the right function at run-time. NODE points
37424 to the dispatcher decl whose body will be created. */
37427 rs6000_generate_version_dispatcher_body (void *node_p)
37430 basic_block empty_bb;
37431 struct cgraph_node *node = (cgraph_node *) node_p;
37432 struct cgraph_function_version_info *ninfo = node->function_version ();
37434 if (ninfo->dispatcher_resolver)
37435 return ninfo->dispatcher_resolver;
37437 /* node is going to be an alias, so remove the finalized bit. */
37438 node->definition = false;
37440 /* The first version in the chain corresponds to the default version. */
37441 ninfo->dispatcher_resolver = resolver
37442 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37444 if (TARGET_DEBUG_TARGET)
37445 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37446 get_decl_name (resolver));
37448 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37449 auto_vec<tree, 2> fn_ver_vec;
37451 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37453 vinfo = vinfo->next)
37455 struct cgraph_node *version = vinfo->this_node;
37456 /* Check for virtual functions here again, as by this time it should
37457 have been determined if this function needs a vtable index or
37458 not. This happens for methods in derived classes that override
37459 virtual methods in base classes but are not explicitly marked as
37461 if (DECL_VINDEX (version->decl))
37462 sorry ("Virtual function multiversioning not supported");
37464 fn_ver_vec.safe_push (version->decl);
37467 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37468 cgraph_edge::rebuild_edges ();
37474 /* Hook to determine if one function can safely inline another. */
37477 rs6000_can_inline_p (tree caller, tree callee)
37480 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37481 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37483 /* If callee has no option attributes, then it is ok to inline. */
37487 /* If caller has no option attributes, but callee does then it is not ok to
37489 else if (!caller_tree)
37494 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37495 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37497 /* Callee's options should a subset of the caller's, i.e. a vsx function
37498 can inline an altivec function but a non-vsx function can't inline a
37500 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37501 == callee_opts->x_rs6000_isa_flags)
37505 if (TARGET_DEBUG_TARGET)
37506 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37507 get_decl_name (caller), get_decl_name (callee),
37508 (ret ? "can" : "cannot"));
37513 /* Allocate a stack temp and fixup the address so it meets the particular
37514 memory requirements (either offetable or REG+REG addressing). */
37517 rs6000_allocate_stack_temp (machine_mode mode,
37518 bool offsettable_p,
37521 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37522 rtx addr = XEXP (stack, 0);
37523 int strict_p = reload_completed;
37525 if (!legitimate_indirect_address_p (addr, strict_p))
37528 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37529 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37531 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37532 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37538 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37539 convert to such a form to deal with memory reference instructions
37540 like STFIWX and LDBRX that only take reg+reg addressing. */
37543 rs6000_force_indexed_or_indirect_mem (rtx x)
37545 machine_mode mode = GET_MODE (x);
37547 gcc_assert (MEM_P (x));
37548 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37550 rtx addr = XEXP (x, 0);
37551 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37553 rtx reg = XEXP (addr, 0);
37554 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37555 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37556 gcc_assert (REG_P (reg));
37557 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37560 else if (GET_CODE (addr) == PRE_MODIFY)
37562 rtx reg = XEXP (addr, 0);
37563 rtx expr = XEXP (addr, 1);
37564 gcc_assert (REG_P (reg));
37565 gcc_assert (GET_CODE (expr) == PLUS);
37566 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37570 x = replace_equiv_address (x, force_reg (Pmode, addr));
37576 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37578 On the RS/6000, all integer constants are acceptable, most won't be valid
37579 for particular insns, though. Only easy FP constants are acceptable. */
37582 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37584 if (TARGET_ELF && tls_referenced_p (x))
37587 if (CONST_DOUBLE_P (x))
37588 return easy_fp_constant (x, mode);
37590 if (GET_CODE (x) == CONST_VECTOR)
37591 return easy_vector_constant (x, mode);
37597 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37600 chain_already_loaded (rtx_insn *last)
37602 for (; last != NULL; last = PREV_INSN (last))
37604 if (NONJUMP_INSN_P (last))
37606 rtx patt = PATTERN (last);
37608 if (GET_CODE (patt) == SET)
37610 rtx lhs = XEXP (patt, 0);
37612 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37620 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37623 rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37625 rtx func = func_desc;
37626 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37627 rtx toc_load = NULL_RTX;
37628 rtx toc_restore = NULL_RTX;
37630 rtx abi_reg = NULL_RTX;
37634 bool is_pltseq_longcall;
37637 tlsarg = global_tlsarg;
37639 /* Handle longcall attributes. */
37640 is_pltseq_longcall = false;
37641 if ((INTVAL (cookie) & CALL_LONG) != 0
37642 && GET_CODE (func_desc) == SYMBOL_REF)
37644 func = rs6000_longcall_ref (func_desc, tlsarg);
37646 is_pltseq_longcall = true;
37649 /* Handle indirect calls. */
37650 if (!SYMBOL_REF_P (func)
37651 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func)))
37653 /* Save the TOC into its reserved slot before the call,
37654 and prepare to restore it after the call. */
37655 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37656 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37657 gen_rtvec (1, stack_toc_offset),
37659 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37661 /* Can we optimize saving the TOC in the prologue or
37662 do we need to do it at every call? */
37663 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37664 cfun->machine->save_toc_in_prologue = true;
37667 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37668 rtx stack_toc_mem = gen_frame_mem (Pmode,
37669 gen_rtx_PLUS (Pmode, stack_ptr,
37670 stack_toc_offset));
37671 MEM_VOLATILE_P (stack_toc_mem) = 1;
37672 if (is_pltseq_longcall)
37674 /* Use USPEC_PLTSEQ here to emit every instruction in an
37675 inline PLT call sequence with a reloc, enabling the
37676 linker to edit the sequence back to a direct call
37677 when that makes sense. */
37678 rtvec v = gen_rtvec (3, toc_reg, func_desc, tlsarg);
37679 rtx mark_toc_reg = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37680 emit_insn (gen_rtx_SET (stack_toc_mem, mark_toc_reg));
37683 emit_move_insn (stack_toc_mem, toc_reg);
37686 if (DEFAULT_ABI == ABI_ELFv2)
37688 /* A function pointer in the ELFv2 ABI is just a plain address, but
37689 the ABI requires it to be loaded into r12 before the call. */
37690 func_addr = gen_rtx_REG (Pmode, 12);
37691 if (!rtx_equal_p (func_addr, func))
37692 emit_move_insn (func_addr, func);
37693 abi_reg = func_addr;
37694 /* Indirect calls via CTR are strongly preferred over indirect
37695 calls via LR, so move the address there. Needed to mark
37696 this insn for linker plt sequence editing too. */
37697 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37698 if (is_pltseq_longcall)
37700 rtvec v = gen_rtvec (3, abi_reg, func_desc, tlsarg);
37701 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37702 emit_insn (gen_rtx_SET (func_addr, mark_func));
37703 v = gen_rtvec (2, func_addr, func_desc);
37704 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37707 emit_move_insn (func_addr, abi_reg);
37711 /* A function pointer under AIX is a pointer to a data area whose
37712 first word contains the actual address of the function, whose
37713 second word contains a pointer to its TOC, and whose third word
37714 contains a value to place in the static chain register (r11).
37715 Note that if we load the static chain, our "trampoline" need
37716 not have any executable code. */
37718 /* Load up address of the actual function. */
37719 func = force_reg (Pmode, func);
37720 func_addr = gen_reg_rtx (Pmode);
37721 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func));
37723 /* Indirect calls via CTR are strongly preferred over indirect
37724 calls via LR, so move the address there. */
37725 rtx ctr_reg = gen_rtx_REG (Pmode, CTR_REGNO);
37726 emit_move_insn (ctr_reg, func_addr);
37727 func_addr = ctr_reg;
37729 /* Prepare to load the TOC of the called function. Note that the
37730 TOC load must happen immediately before the actual call so
37731 that unwinding the TOC registers works correctly. See the
37732 comment in frob_update_context. */
37733 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37734 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37735 gen_rtx_PLUS (Pmode, func,
37737 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37739 /* If we have a static chain, load it up. But, if the call was
37740 originally direct, the 3rd word has not been written since no
37741 trampoline has been built, so we ought not to load it, lest we
37742 override a static chain value. */
37743 if (!(GET_CODE (func_desc) == SYMBOL_REF
37744 && SYMBOL_REF_FUNCTION_P (func_desc))
37745 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37746 && !chain_already_loaded (get_current_sequence ()->next->last))
37748 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37749 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37750 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37751 gen_rtx_PLUS (Pmode, func,
37753 emit_move_insn (sc_reg, func_sc_mem);
37760 /* Direct calls use the TOC: for local calls, the callee will
37761 assume the TOC register is set; for non-local calls, the
37762 PLT stub needs the TOC register. */
37767 /* Create the call. */
37768 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37769 if (value != NULL_RTX)
37770 call[0] = gen_rtx_SET (value, call[0]);
37774 call[n_call++] = toc_load;
37776 call[n_call++] = toc_restore;
37778 call[n_call++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37780 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37781 insn = emit_call_insn (insn);
37783 /* Mention all registers defined by the ABI to hold information
37784 as uses in CALL_INSN_FUNCTION_USAGE. */
37786 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37789 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37792 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37797 gcc_assert (INTVAL (cookie) == 0);
37800 tlsarg = global_tlsarg;
37802 /* Create the call. */
37803 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), tlsarg);
37804 if (value != NULL_RTX)
37805 call[0] = gen_rtx_SET (value, call[0]);
37807 call[1] = simple_return_rtx;
37809 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37810 insn = emit_call_insn (insn);
37812 /* Note use of the TOC register. */
37813 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37816 /* Expand code to perform a call under the SYSV4 ABI. */
37819 rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37821 rtx func = func_desc;
37825 rtx abi_reg = NULL_RTX;
37829 tlsarg = global_tlsarg;
37831 /* Handle longcall attributes. */
37832 if ((INTVAL (cookie) & CALL_LONG) != 0
37833 && GET_CODE (func_desc) == SYMBOL_REF)
37835 func = rs6000_longcall_ref (func_desc, tlsarg);
37836 /* If the longcall was implemented as an inline PLT call using
37837 PLT unspecs then func will be REG:r11. If not, func will be
37838 a pseudo reg. The inline PLT call sequence supports lazy
37839 linking (and longcalls to functions in dlopen'd libraries).
37840 The other style of longcalls don't. The lazy linking entry
37841 to the dynamic symbol resolver requires r11 be the function
37842 address (as it is for linker generated PLT stubs). Ensure
37843 r11 stays valid to the bctrl by marking r11 used by the call. */
37848 /* Handle indirect calls. */
37849 if (GET_CODE (func) != SYMBOL_REF)
37851 func = force_reg (Pmode, func);
37853 /* Indirect calls via CTR are strongly preferred over indirect
37854 calls via LR, so move the address there. That can't be left
37855 to reload because we want to mark every instruction in an
37856 inline PLT call sequence with a reloc, enabling the linker to
37857 edit the sequence back to a direct call when that makes sense. */
37858 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37861 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37862 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37863 emit_insn (gen_rtx_SET (func_addr, mark_func));
37864 v = gen_rtvec (2, func_addr, func_desc);
37865 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37868 emit_move_insn (func_addr, func);
37873 /* Create the call. */
37874 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37875 if (value != NULL_RTX)
37876 call[0] = gen_rtx_SET (value, call[0]);
37878 call[1] = gen_rtx_USE (VOIDmode, cookie);
37880 if (TARGET_SECURE_PLT
37882 && GET_CODE (func_addr) == SYMBOL_REF
37883 && !SYMBOL_REF_LOCAL_P (func_addr))
37884 call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
37886 call[n++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37888 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n, call));
37889 insn = emit_call_insn (insn);
37891 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37894 /* Expand code to perform a sibling call under the SysV4 ABI. */
37897 rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37899 rtx func = func_desc;
37903 rtx abi_reg = NULL_RTX;
37906 tlsarg = global_tlsarg;
37908 /* Handle longcall attributes. */
37909 if ((INTVAL (cookie) & CALL_LONG) != 0
37910 && GET_CODE (func_desc) == SYMBOL_REF)
37912 func = rs6000_longcall_ref (func_desc, tlsarg);
37913 /* If the longcall was implemented as an inline PLT call using
37914 PLT unspecs then func will be REG:r11. If not, func will be
37915 a pseudo reg. The inline PLT call sequence supports lazy
37916 linking (and longcalls to functions in dlopen'd libraries).
37917 The other style of longcalls don't. The lazy linking entry
37918 to the dynamic symbol resolver requires r11 be the function
37919 address (as it is for linker generated PLT stubs). Ensure
37920 r11 stays valid to the bctr by marking r11 used by the call. */
37925 /* Handle indirect calls. */
37926 if (GET_CODE (func) != SYMBOL_REF)
37928 func = force_reg (Pmode, func);
37930 /* Indirect sibcalls must go via CTR. That can't be left to
37931 reload because we want to mark every instruction in an inline
37932 PLT call sequence with a reloc, enabling the linker to edit
37933 the sequence back to a direct call when that makes sense. */
37934 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37937 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37938 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37939 emit_insn (gen_rtx_SET (func_addr, mark_func));
37940 v = gen_rtvec (2, func_addr, func_desc);
37941 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37944 emit_move_insn (func_addr, func);
37949 /* Create the call. */
37950 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37951 if (value != NULL_RTX)
37952 call[0] = gen_rtx_SET (value, call[0]);
37954 call[1] = gen_rtx_USE (VOIDmode, cookie);
37955 call[2] = simple_return_rtx;
37957 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
37958 insn = emit_call_insn (insn);
37960 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37965 /* Expand code to perform a call under the Darwin ABI.
37966 Modulo handling of mlongcall, this is much the same as sysv.
37967 if/when the longcall optimisation is removed, we could drop this
37968 code and use the sysv case (taking care to avoid the tls stuff).
37970 We can use this for sibcalls too, if needed. */
37973 rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
37974 rtx cookie, bool sibcall)
37976 rtx func = func_desc;
37980 int cookie_val = INTVAL (cookie);
37981 bool make_island = false;
37983 /* Handle longcall attributes, there are two cases for Darwin:
37984 1) Newer linkers are capable of synthesising any branch islands needed.
37985 2) We need a helper branch island synthesised by the compiler.
37986 The second case has mostly been retired and we don't use it for m64.
37987 In fact, it's is an optimisation, we could just indirect as sysv does..
37988 ... however, backwards compatibility for now.
37989 If we're going to use this, then we need to keep the CALL_LONG bit set,
37990 so that we can pick up the special insn form later. */
37991 if ((cookie_val & CALL_LONG) != 0
37992 && GET_CODE (func_desc) == SYMBOL_REF)
37994 if (darwin_emit_branch_islands && TARGET_32BIT)
37995 make_island = true; /* Do nothing yet, retain the CALL_LONG flag. */
37998 /* The linker is capable of doing this, but the user explicitly
37999 asked for -mlongcall, so we'll do the 'normal' version. */
38000 func = rs6000_longcall_ref (func_desc, NULL_RTX);
38001 cookie_val &= ~CALL_LONG; /* Handled, zap it. */
38005 /* Handle indirect calls. */
38006 if (GET_CODE (func) != SYMBOL_REF)
38008 func = force_reg (Pmode, func);
38010 /* Indirect calls via CTR are strongly preferred over indirect
38011 calls via LR, and are required for indirect sibcalls, so move
38012 the address there. */
38013 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38014 emit_move_insn (func_addr, func);
38019 /* Create the call. */
38020 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38021 if (value != NULL_RTX)
38022 call[0] = gen_rtx_SET (value, call[0]);
38024 call[1] = gen_rtx_USE (VOIDmode, GEN_INT (cookie_val));
38027 call[2] = simple_return_rtx;
38029 call[2] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38031 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38032 insn = emit_call_insn (insn);
38033 /* Now we have the debug info in the insn, we can set up the branch island
38034 if we're using one. */
38037 tree funname = get_identifier (XSTR (func_desc, 0));
38039 if (no_previous_def (funname))
38041 rtx label_rtx = gen_label_rtx ();
38042 char *label_buf, temp_buf[256];
38043 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
38044 CODE_LABEL_NUMBER (label_rtx));
38045 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
38046 tree labelname = get_identifier (label_buf);
38047 add_compiler_branch_island (labelname, funname,
38048 insn_line ((const rtx_insn*)insn));
38055 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38056 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38059 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, false);
38067 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38068 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38071 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, true);
38078 /* Return whether we need to always update the saved TOC pointer when we update
38079 the stack pointer. */
38082 rs6000_save_toc_in_prologue_p (void)
38084 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38087 #ifdef HAVE_GAS_HIDDEN
38088 # define USE_HIDDEN_LINKONCE 1
38090 # define USE_HIDDEN_LINKONCE 0
38093 /* Fills in the label name that should be used for a 476 link stack thunk. */
38096 get_ppc476_thunk_name (char name[32])
38098 gcc_assert (TARGET_LINK_STACK);
38100 if (USE_HIDDEN_LINKONCE)
38101 sprintf (name, "__ppc476.get_thunk");
38103 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38106 /* This function emits the simple thunk routine that is used to preserve
38107 the link stack on the 476 cpu. */
38109 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38111 rs6000_code_end (void)
38116 if (!TARGET_LINK_STACK)
38119 get_ppc476_thunk_name (name);
38121 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38122 build_function_type_list (void_type_node, NULL_TREE));
38123 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38124 NULL_TREE, void_type_node);
38125 TREE_PUBLIC (decl) = 1;
38126 TREE_STATIC (decl) = 1;
38129 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38131 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38132 targetm.asm_out.unique_section (decl, 0);
38133 switch_to_section (get_named_section (decl, NULL, 0));
38134 DECL_WEAK (decl) = 1;
38135 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38136 targetm.asm_out.globalize_label (asm_out_file, name);
38137 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38138 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38143 switch_to_section (text_section);
38144 ASM_OUTPUT_LABEL (asm_out_file, name);
38147 DECL_INITIAL (decl) = make_node (BLOCK);
38148 current_function_decl = decl;
38149 allocate_struct_function (decl, false);
38150 init_function_start (decl);
38151 first_function_block_is_cold = false;
38152 /* Make sure unwind info is emitted for the thunk if needed. */
38153 final_start_function (emit_barrier (), asm_out_file, 1);
38155 fputs ("\tblr\n", asm_out_file);
38157 final_end_function ();
38158 init_insn_lengths ();
38159 free_after_compilation (cfun);
38161 current_function_decl = NULL;
38164 /* Add r30 to hard reg set if the prologue sets it up and it is not
38165 pic_offset_table_rtx. */
38168 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38170 if (!TARGET_SINGLE_PIC_BASE
38172 && TARGET_MINIMAL_TOC
38173 && !constant_pool_empty_p ())
38174 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38175 if (cfun->machine->split_stack_argp_used)
38176 add_to_hard_reg_set (&set->set, Pmode, 12);
38178 /* Make sure the hard reg set doesn't include r2, which was possibly added
38179 via PIC_OFFSET_TABLE_REGNUM. */
38181 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38185 /* Helper function for rs6000_split_logical to emit a logical instruction after
38186 spliting the operation to single GPR registers.
38188 DEST is the destination register.
38189 OP1 and OP2 are the input source registers.
38190 CODE is the base operation (AND, IOR, XOR, NOT).
38191 MODE is the machine mode.
38192 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38193 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38194 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38197 rs6000_split_logical_inner (rtx dest,
38200 enum rtx_code code,
38202 bool complement_final_p,
38203 bool complement_op1_p,
38204 bool complement_op2_p)
38208 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38209 if (op2 && CONST_INT_P (op2)
38210 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38211 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38213 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38214 HOST_WIDE_INT value = INTVAL (op2) & mask;
38216 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38221 emit_insn (gen_rtx_SET (dest, const0_rtx));
38225 else if (value == mask)
38227 if (!rtx_equal_p (dest, op1))
38228 emit_insn (gen_rtx_SET (dest, op1));
38233 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38234 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38235 else if (code == IOR || code == XOR)
38239 if (!rtx_equal_p (dest, op1))
38240 emit_insn (gen_rtx_SET (dest, op1));
38246 if (code == AND && mode == SImode
38247 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38249 emit_insn (gen_andsi3 (dest, op1, op2));
38253 if (complement_op1_p)
38254 op1 = gen_rtx_NOT (mode, op1);
38256 if (complement_op2_p)
38257 op2 = gen_rtx_NOT (mode, op2);
38259 /* For canonical RTL, if only one arm is inverted it is the first. */
38260 if (!complement_op1_p && complement_op2_p)
38261 std::swap (op1, op2);
38263 bool_rtx = ((code == NOT)
38264 ? gen_rtx_NOT (mode, op1)
38265 : gen_rtx_fmt_ee (code, mode, op1, op2));
38267 if (complement_final_p)
38268 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38270 emit_insn (gen_rtx_SET (dest, bool_rtx));
38273 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38274 operations are split immediately during RTL generation to allow for more
38275 optimizations of the AND/IOR/XOR.
38277 OPERANDS is an array containing the destination and two input operands.
38278 CODE is the base operation (AND, IOR, XOR, NOT).
38279 MODE is the machine mode.
38280 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38281 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38282 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38283 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38284 formation of the AND instructions. */
38287 rs6000_split_logical_di (rtx operands[3],
38288 enum rtx_code code,
38289 bool complement_final_p,
38290 bool complement_op1_p,
38291 bool complement_op2_p)
38293 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38294 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38295 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38296 enum hi_lo { hi = 0, lo = 1 };
38297 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38300 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38301 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38302 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38303 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38306 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38309 if (!CONST_INT_P (operands[2]))
38311 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38312 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38316 HOST_WIDE_INT value = INTVAL (operands[2]);
38317 HOST_WIDE_INT value_hi_lo[2];
38319 gcc_assert (!complement_final_p);
38320 gcc_assert (!complement_op1_p);
38321 gcc_assert (!complement_op2_p);
38323 value_hi_lo[hi] = value >> 32;
38324 value_hi_lo[lo] = value & lower_32bits;
38326 for (i = 0; i < 2; i++)
38328 HOST_WIDE_INT sub_value = value_hi_lo[i];
38330 if (sub_value & sign_bit)
38331 sub_value |= upper_32bits;
38333 op2_hi_lo[i] = GEN_INT (sub_value);
38335 /* If this is an AND instruction, check to see if we need to load
38336 the value in a register. */
38337 if (code == AND && sub_value != -1 && sub_value != 0
38338 && !and_operand (op2_hi_lo[i], SImode))
38339 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38344 for (i = 0; i < 2; i++)
38346 /* Split large IOR/XOR operations. */
38347 if ((code == IOR || code == XOR)
38348 && CONST_INT_P (op2_hi_lo[i])
38349 && !complement_final_p
38350 && !complement_op1_p
38351 && !complement_op2_p
38352 && !logical_const_operand (op2_hi_lo[i], SImode))
38354 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38355 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38356 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38357 rtx tmp = gen_reg_rtx (SImode);
38359 /* Make sure the constant is sign extended. */
38360 if ((hi_16bits & sign_bit) != 0)
38361 hi_16bits |= upper_32bits;
38363 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38364 code, SImode, false, false, false);
38366 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38367 code, SImode, false, false, false);
38370 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38371 code, SImode, complement_final_p,
38372 complement_op1_p, complement_op2_p);
38378 /* Split the insns that make up boolean operations operating on multiple GPR
38379 registers. The boolean MD patterns ensure that the inputs either are
38380 exactly the same as the output registers, or there is no overlap.
38382 OPERANDS is an array containing the destination and two input operands.
38383 CODE is the base operation (AND, IOR, XOR, NOT).
38384 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38385 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38386 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38389 rs6000_split_logical (rtx operands[3],
38390 enum rtx_code code,
38391 bool complement_final_p,
38392 bool complement_op1_p,
38393 bool complement_op2_p)
38395 machine_mode mode = GET_MODE (operands[0]);
38396 machine_mode sub_mode;
38398 int sub_size, regno0, regno1, nregs, i;
38400 /* If this is DImode, use the specialized version that can run before
38401 register allocation. */
38402 if (mode == DImode && !TARGET_POWERPC64)
38404 rs6000_split_logical_di (operands, code, complement_final_p,
38405 complement_op1_p, complement_op2_p);
38411 op2 = (code == NOT) ? NULL_RTX : operands[2];
38412 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38413 sub_size = GET_MODE_SIZE (sub_mode);
38414 regno0 = REGNO (op0);
38415 regno1 = REGNO (op1);
38417 gcc_assert (reload_completed);
38418 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38419 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38421 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38422 gcc_assert (nregs > 1);
38424 if (op2 && REG_P (op2))
38425 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38427 for (i = 0; i < nregs; i++)
38429 int offset = i * sub_size;
38430 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38431 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38432 rtx sub_op2 = ((code == NOT)
38434 : simplify_subreg (sub_mode, op2, mode, offset));
38436 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38437 complement_final_p, complement_op1_p,
38445 /* Return true if the peephole2 can combine a load involving a combination of
38446 an addis instruction and a load with an offset that can be fused together on
38450 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38451 rtx addis_value, /* addis value. */
38452 rtx target, /* target register that is loaded. */
38453 rtx mem) /* bottom part of the memory addr. */
38458 /* Validate arguments. */
38459 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38462 if (!base_reg_operand (target, GET_MODE (target)))
38465 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38468 /* Allow sign/zero extension. */
38469 if (GET_CODE (mem) == ZERO_EXTEND
38470 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38471 mem = XEXP (mem, 0);
38476 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38479 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38480 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38483 /* Validate that the register used to load the high value is either the
38484 register being loaded, or we can safely replace its use.
38486 This function is only called from the peephole2 pass and we assume that
38487 there are 2 instructions in the peephole (addis and load), so we want to
38488 check if the target register was not used in the memory address and the
38489 register to hold the addis result is dead after the peephole. */
38490 if (REGNO (addis_reg) != REGNO (target))
38492 if (reg_mentioned_p (target, mem))
38495 if (!peep2_reg_dead_p (2, addis_reg))
38498 /* If the target register being loaded is the stack pointer, we must
38499 avoid loading any other value into it, even temporarily. */
38500 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38504 base_reg = XEXP (addr, 0);
38505 return REGNO (addis_reg) == REGNO (base_reg);
38508 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38509 sequence. We adjust the addis register to use the target register. If the
38510 load sign extends, we adjust the code to do the zero extending load, and an
38511 explicit sign extension later since the fusion only covers zero extending
38515 operands[0] register set with addis (to be replaced with target)
38516 operands[1] value set via addis
38517 operands[2] target register being loaded
38518 operands[3] D-form memory reference using operands[0]. */
38521 expand_fusion_gpr_load (rtx *operands)
38523 rtx addis_value = operands[1];
38524 rtx target = operands[2];
38525 rtx orig_mem = operands[3];
38526 rtx new_addr, new_mem, orig_addr, offset;
38527 enum rtx_code plus_or_lo_sum;
38528 machine_mode target_mode = GET_MODE (target);
38529 machine_mode extend_mode = target_mode;
38530 machine_mode ptr_mode = Pmode;
38531 enum rtx_code extend = UNKNOWN;
38533 if (GET_CODE (orig_mem) == ZERO_EXTEND
38534 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38536 extend = GET_CODE (orig_mem);
38537 orig_mem = XEXP (orig_mem, 0);
38538 target_mode = GET_MODE (orig_mem);
38541 gcc_assert (MEM_P (orig_mem));
38543 orig_addr = XEXP (orig_mem, 0);
38544 plus_or_lo_sum = GET_CODE (orig_addr);
38545 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38547 offset = XEXP (orig_addr, 1);
38548 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38549 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38551 if (extend != UNKNOWN)
38552 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38554 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38555 UNSPEC_FUSION_GPR);
38556 emit_insn (gen_rtx_SET (target, new_mem));
38558 if (extend == SIGN_EXTEND)
38560 int sub_off = ((BYTES_BIG_ENDIAN)
38561 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38564 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38566 emit_insn (gen_rtx_SET (target,
38567 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38573 /* Emit the addis instruction that will be part of a fused instruction
38577 emit_fusion_addis (rtx target, rtx addis_value)
38580 const char *addis_str = NULL;
38582 /* Emit the addis instruction. */
38583 fuse_ops[0] = target;
38584 if (satisfies_constraint_L (addis_value))
38586 fuse_ops[1] = addis_value;
38587 addis_str = "lis %0,%v1";
38590 else if (GET_CODE (addis_value) == PLUS)
38592 rtx op0 = XEXP (addis_value, 0);
38593 rtx op1 = XEXP (addis_value, 1);
38595 if (REG_P (op0) && CONST_INT_P (op1)
38596 && satisfies_constraint_L (op1))
38600 addis_str = "addis %0,%1,%v2";
38604 else if (GET_CODE (addis_value) == HIGH)
38606 rtx value = XEXP (addis_value, 0);
38607 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38609 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38610 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38612 addis_str = "addis %0,%2,%1@toc@ha";
38614 else if (TARGET_XCOFF)
38615 addis_str = "addis %0,%1@u(%2)";
38618 gcc_unreachable ();
38621 else if (GET_CODE (value) == PLUS)
38623 rtx op0 = XEXP (value, 0);
38624 rtx op1 = XEXP (value, 1);
38626 if (GET_CODE (op0) == UNSPEC
38627 && XINT (op0, 1) == UNSPEC_TOCREL
38628 && CONST_INT_P (op1))
38630 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38631 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38634 addis_str = "addis %0,%2,%1+%3@toc@ha";
38636 else if (TARGET_XCOFF)
38637 addis_str = "addis %0,%1+%3@u(%2)";
38640 gcc_unreachable ();
38644 else if (satisfies_constraint_L (value))
38646 fuse_ops[1] = value;
38647 addis_str = "lis %0,%v1";
38650 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38652 fuse_ops[1] = value;
38653 addis_str = "lis %0,%1@ha";
38658 fatal_insn ("Could not generate addis value for fusion", addis_value);
38660 output_asm_insn (addis_str, fuse_ops);
38663 /* Emit a D-form load or store instruction that is the second instruction
38664 of a fusion sequence. */
38667 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38670 char insn_template[80];
38672 fuse_ops[0] = load_reg;
38673 fuse_ops[1] = addis_reg;
38675 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38677 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38678 fuse_ops[2] = offset;
38679 output_asm_insn (insn_template, fuse_ops);
38682 else if (GET_CODE (offset) == UNSPEC
38683 && XINT (offset, 1) == UNSPEC_TOCREL)
38686 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38688 else if (TARGET_XCOFF)
38689 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38692 gcc_unreachable ();
38694 fuse_ops[2] = XVECEXP (offset, 0, 0);
38695 output_asm_insn (insn_template, fuse_ops);
38698 else if (GET_CODE (offset) == PLUS
38699 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38700 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38701 && CONST_INT_P (XEXP (offset, 1)))
38703 rtx tocrel_unspec = XEXP (offset, 0);
38705 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38707 else if (TARGET_XCOFF)
38708 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38711 gcc_unreachable ();
38713 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38714 fuse_ops[3] = XEXP (offset, 1);
38715 output_asm_insn (insn_template, fuse_ops);
38718 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38720 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38722 fuse_ops[2] = offset;
38723 output_asm_insn (insn_template, fuse_ops);
38727 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38732 /* Given an address, convert it into the addis and load offset parts. Addresses
38733 created during the peephole2 process look like:
38734 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38735 (unspec [(...)] UNSPEC_TOCREL)) */
38738 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38742 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38744 hi = XEXP (addr, 0);
38745 lo = XEXP (addr, 1);
38748 gcc_unreachable ();
38754 /* Return a string to fuse an addis instruction with a gpr load to the same
38755 register that we loaded up the addis instruction. The address that is used
38756 is the logical address that was formed during peephole2:
38757 (lo_sum (high) (low-part))
38759 The code is complicated, so we call output_asm_insn directly, and just
38763 emit_fusion_gpr_load (rtx target, rtx mem)
38768 const char *load_str = NULL;
38771 if (GET_CODE (mem) == ZERO_EXTEND)
38772 mem = XEXP (mem, 0);
38774 gcc_assert (REG_P (target) && MEM_P (mem));
38776 addr = XEXP (mem, 0);
38777 fusion_split_address (addr, &addis_value, &load_offset);
38779 /* Now emit the load instruction to the same register. */
38780 mode = GET_MODE (mem);
38798 gcc_assert (TARGET_POWERPC64);
38803 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38806 /* Emit the addis instruction. */
38807 emit_fusion_addis (target, addis_value);
38809 /* Emit the D-form load instruction. */
38810 emit_fusion_load (target, target, load_offset, load_str);
38816 #ifdef RS6000_GLIBC_ATOMIC_FENV
38817 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38818 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38821 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38824 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38826 if (!TARGET_HARD_FLOAT)
38828 #ifdef RS6000_GLIBC_ATOMIC_FENV
38829 if (atomic_hold_decl == NULL_TREE)
38832 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38833 get_identifier ("__atomic_feholdexcept"),
38834 build_function_type_list (void_type_node,
38835 double_ptr_type_node,
38837 TREE_PUBLIC (atomic_hold_decl) = 1;
38838 DECL_EXTERNAL (atomic_hold_decl) = 1;
38841 if (atomic_clear_decl == NULL_TREE)
38844 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38845 get_identifier ("__atomic_feclearexcept"),
38846 build_function_type_list (void_type_node,
38848 TREE_PUBLIC (atomic_clear_decl) = 1;
38849 DECL_EXTERNAL (atomic_clear_decl) = 1;
38852 tree const_double = build_qualified_type (double_type_node,
38854 tree const_double_ptr = build_pointer_type (const_double);
38855 if (atomic_update_decl == NULL_TREE)
38858 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38859 get_identifier ("__atomic_feupdateenv"),
38860 build_function_type_list (void_type_node,
38863 TREE_PUBLIC (atomic_update_decl) = 1;
38864 DECL_EXTERNAL (atomic_update_decl) = 1;
38867 tree fenv_var = create_tmp_var_raw (double_type_node);
38868 TREE_ADDRESSABLE (fenv_var) = 1;
38869 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38871 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38872 *clear = build_call_expr (atomic_clear_decl, 0);
38873 *update = build_call_expr (atomic_update_decl, 1,
38874 fold_convert (const_double_ptr, fenv_addr));
38879 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38880 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38881 tree call_mffs = build_call_expr (mffs, 0);
38883 /* Generates the equivalent of feholdexcept (&fenv_var)
38885 *fenv_var = __builtin_mffs ();
38887 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38888 __builtin_mtfsf (0xff, fenv_hold); */
38890 /* Mask to clear everything except for the rounding modes and non-IEEE
38891 arithmetic flag. */
38892 const unsigned HOST_WIDE_INT hold_exception_mask =
38893 HOST_WIDE_INT_C (0xffffffff00000007);
38895 tree fenv_var = create_tmp_var_raw (double_type_node);
38897 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38899 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38900 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38901 build_int_cst (uint64_type_node,
38902 hold_exception_mask));
38904 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38907 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38908 build_int_cst (unsigned_type_node, 0xff),
38911 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38913 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38915 double fenv_clear = __builtin_mffs ();
38916 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38917 __builtin_mtfsf (0xff, fenv_clear); */
38919 /* Mask to clear everything except for the rounding modes and non-IEEE
38920 arithmetic flag. */
38921 const unsigned HOST_WIDE_INT clear_exception_mask =
38922 HOST_WIDE_INT_C (0xffffffff00000000);
38924 tree fenv_clear = create_tmp_var_raw (double_type_node);
38926 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38928 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38929 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38931 build_int_cst (uint64_type_node,
38932 clear_exception_mask));
38934 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38935 fenv_clear_llu_and);
38937 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38938 build_int_cst (unsigned_type_node, 0xff),
38941 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38943 /* Generates the equivalent of feupdateenv (&fenv_var)
38945 double old_fenv = __builtin_mffs ();
38946 double fenv_update;
38947 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38948 (*(uint64_t*)fenv_var 0x1ff80fff);
38949 __builtin_mtfsf (0xff, fenv_update); */
38951 const unsigned HOST_WIDE_INT update_exception_mask =
38952 HOST_WIDE_INT_C (0xffffffff1fffff00);
38953 const unsigned HOST_WIDE_INT new_exception_mask =
38954 HOST_WIDE_INT_C (0x1ff80fff);
38956 tree old_fenv = create_tmp_var_raw (double_type_node);
38957 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38959 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38960 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38961 build_int_cst (uint64_type_node,
38962 update_exception_mask));
38964 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38965 build_int_cst (uint64_type_node,
38966 new_exception_mask));
38968 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38969 old_llu_and, new_llu_and);
38971 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38974 tree update_mtfsf = build_call_expr (mtfsf, 2,
38975 build_int_cst (unsigned_type_node, 0xff),
38976 fenv_update_mtfsf);
38978 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
38982 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
38984 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38986 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38987 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38989 /* The destination of the vmrgew instruction layout is:
38990 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38991 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38992 vmrgew instruction will be correct. */
38993 if (BYTES_BIG_ENDIAN)
38995 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
38997 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39002 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39003 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39006 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39007 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39009 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39010 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39012 if (BYTES_BIG_ENDIAN)
39013 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39015 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39019 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39021 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39023 rtx_tmp0 = gen_reg_rtx (V2DImode);
39024 rtx_tmp1 = gen_reg_rtx (V2DImode);
39026 /* The destination of the vmrgew instruction layout is:
39027 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39028 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39029 vmrgew instruction will be correct. */
39030 if (BYTES_BIG_ENDIAN)
39032 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39033 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39037 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39038 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39041 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39042 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39044 if (signed_convert)
39046 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39047 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39051 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39052 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39055 if (BYTES_BIG_ENDIAN)
39056 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39058 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39062 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39065 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39067 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39068 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39070 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39071 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39073 rtx_tmp2 = gen_reg_rtx (V4SImode);
39074 rtx_tmp3 = gen_reg_rtx (V4SImode);
39076 if (signed_convert)
39078 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39079 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39083 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39084 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39087 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39090 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39093 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39094 optimization_type opt_type)
39099 return (opt_type == OPTIMIZE_FOR_SPEED
39100 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39107 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39109 static HOST_WIDE_INT
39110 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39112 if (TREE_CODE (exp) == STRING_CST
39113 && (STRICT_ALIGNMENT || !optimize_size))
39114 return MAX (align, BITS_PER_WORD);
39118 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39120 static HOST_WIDE_INT
39121 rs6000_starting_frame_offset (void)
39123 if (FRAME_GROWS_DOWNWARD)
39125 return RS6000_STARTING_FRAME_OFFSET;
39129 /* Create an alias for a mangled name where we have changed the mangling (in
39130 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39131 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39133 #if TARGET_ELF && RS6000_WEAK
39135 rs6000_globalize_decl_name (FILE * stream, tree decl)
39137 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
39139 targetm.asm_out.globalize_label (stream, name);
39141 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
39143 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
39144 const char *old_name;
39146 ieee128_mangling_gcc_8_1 = true;
39147 lang_hooks.set_decl_assembler_name (decl);
39148 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
39149 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
39150 ieee128_mangling_gcc_8_1 = false;
39152 if (strcmp (name, old_name) != 0)
39154 fprintf (stream, "\t.weak %s\n", old_name);
39155 fprintf (stream, "\t.set %s,%s\n", old_name, name);
39162 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39163 function names from <foo>l to <foo>f128 if the default long double type is
39164 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39165 include file switches the names on systems that support long double as IEEE
39166 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39167 In the future, glibc will export names like __ieee128_sinf128 and we can
39168 switch to using those instead of using sinf128, which pollutes the user's
39171 This will switch the names for Fortran math functions as well (which doesn't
39172 use math.h). However, Fortran needs other changes to the compiler and
39173 library before you can switch the real*16 type at compile time.
39175 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39176 only do this if the default is that long double is IBM extended double, and
39177 the user asked for IEEE 128-bit. */
39180 rs6000_mangle_decl_assembler_name (tree decl, tree id)
39182 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
39183 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
39185 size_t len = IDENTIFIER_LENGTH (id);
39186 const char *name = IDENTIFIER_POINTER (id);
39188 if (name[len - 1] == 'l')
39190 bool uses_ieee128_p = false;
39191 tree type = TREE_TYPE (decl);
39192 machine_mode ret_mode = TYPE_MODE (type);
39194 /* See if the function returns a IEEE 128-bit floating point type or
39196 if (ret_mode == TFmode || ret_mode == TCmode)
39197 uses_ieee128_p = true;
39200 function_args_iterator args_iter;
39203 /* See if the function passes a IEEE 128-bit floating point type
39204 or complex type. */
39205 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
39207 machine_mode arg_mode = TYPE_MODE (arg);
39208 if (arg_mode == TFmode || arg_mode == TCmode)
39210 uses_ieee128_p = true;
39216 /* If we passed or returned an IEEE 128-bit floating point type,
39217 change the name. */
39218 if (uses_ieee128_p)
39220 char *name2 = (char *) alloca (len + 4);
39221 memcpy (name2, name, len - 1);
39222 strcpy (name2 + len - 1, "f128");
39223 id = get_identifier (name2);
39232 struct gcc_target targetm = TARGET_INITIALIZER;
39234 #include "gt-rs6000.h"