1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
45 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "langhooks.h"
55 #include "cfglayout.h"
57 #include "sched-int.h"
59 #include "tree-flow.h"
62 #include "tm-constrs.h"
65 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
68 #include "gstab.h" /* for N_SLINE */
71 #ifndef TARGET_NO_PROTOTYPE
72 #define TARGET_NO_PROTOTYPE 0
75 #define min(A,B) ((A) < (B) ? (A) : (B))
76 #define max(A,B) ((A) > (B) ? (A) : (B))
78 /* Structure used to define the rs6000 stack */
79 typedef struct rs6000_stack {
80 int reload_completed; /* stack info won't change from here on */
81 int first_gp_reg_save; /* first callee saved GP register used */
82 int first_fp_reg_save; /* first callee saved FP register used */
83 int first_altivec_reg_save; /* first callee saved AltiVec register used */
84 int lr_save_p; /* true if the link reg needs to be saved */
85 int cr_save_p; /* true if the CR reg needs to be saved */
86 unsigned int vrsave_mask; /* mask of vec registers to save */
87 int push_p; /* true if we need to allocate stack space */
88 int calls_p; /* true if the function makes any calls */
89 int world_save_p; /* true if we're saving *everything*:
90 r13-r31, cr, f14-f31, vrsave, v20-v31 */
91 enum rs6000_abi abi; /* which ABI to use */
92 int gp_save_offset; /* offset to save GP regs from initial SP */
93 int fp_save_offset; /* offset to save FP regs from initial SP */
94 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
95 int lr_save_offset; /* offset to save LR from initial SP */
96 int cr_save_offset; /* offset to save CR from initial SP */
97 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
98 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
99 int varargs_save_offset; /* offset to save the varargs registers */
100 int ehrd_offset; /* offset to EH return data */
101 int reg_size; /* register size (4 or 8) */
102 HOST_WIDE_INT vars_size; /* variable save area size */
103 int parm_size; /* outgoing parameter size */
104 int save_size; /* save area size */
105 int fixed_size; /* fixed size of stack frame */
106 int gp_size; /* size of saved GP registers */
107 int fp_size; /* size of saved FP registers */
108 int altivec_size; /* size of saved AltiVec registers */
109 int cr_size; /* size to hold CR if not in save_size */
110 int vrsave_size; /* size to hold VRSAVE if not in save_size */
111 int altivec_padding_size; /* size of altivec alignment padding if
113 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
114 int spe_padding_size;
115 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
116 int spe_64bit_regs_used;
120 /* A C structure for machine-specific, per-function data.
121 This is added to the cfun structure. */
122 typedef struct GTY(()) machine_function
124 /* Some local-dynamic symbol. */
125 const char *some_ld_name;
126 /* Whether the instruction chain has been scanned already. */
127 int insn_chain_scanned_p;
128 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
129 int ra_needs_full_frame;
130 /* Flags if __builtin_return_address (0) was used. */
132 /* Cache lr_save_p after expansion of builtin_eh_return. */
134 /* Whether we need to save the TOC to the reserved stack location in the
135 function prologue. */
136 bool save_toc_in_prologue;
137 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
138 varargs save area. */
139 HOST_WIDE_INT varargs_save_offset;
140 /* Temporary stack slot to use for SDmode copies. This slot is
141 64-bits wide and is allocated early enough so that the offset
142 does not overflow the 16-bit load/store offset field. */
143 rtx sdmode_stack_slot;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load;
149 /* Set to nonzero once AIX common-mode calls have been defined. */
150 static GTY(()) int common_mode_defined;
152 /* Label number of label created for -mrelocatable, to call to so we can
153 get the address of the GOT section */
154 static int rs6000_pic_labelno;
157 /* Counter for labels which are to be placed in .fixup. */
158 int fixuplabelno = 0;
161 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
164 /* Specify the machine mode that pointers have. After generation of rtl, the
165 compiler makes no further distinction between pointers and any other objects
166 of this machine mode. The type is unsigned since not all things that
167 include rs6000.h also include machmode.h. */
168 unsigned rs6000_pmode;
170 /* Width in bits of a pointer. */
171 unsigned rs6000_pointer_size;
173 #ifdef HAVE_AS_GNU_ATTRIBUTE
174 /* Flag whether floating point values have been passed/returned. */
175 static bool rs6000_passes_float;
176 /* Flag whether vector values have been passed/returned. */
177 static bool rs6000_passes_vector;
178 /* Flag whether small (<= 8 byte) structures have been returned. */
179 static bool rs6000_returns_struct;
182 /* Value is TRUE if register/mode pair is acceptable. */
183 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
185 /* Maximum number of registers needed for a given register class and mode. */
186 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
188 /* How many registers are needed for a given register and mode. */
189 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
191 /* Map register number to register class. */
192 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
194 /* Reload functions based on the type and the vector unit. */
195 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
197 static int dbg_cost_ctrl;
199 /* Built in types. */
200 tree rs6000_builtin_types[RS6000_BTI_MAX];
201 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
203 /* Flag to say the TOC is initialized */
205 char toc_label_name[10];
207 /* Cached value of rs6000_variable_issue. This is cached in
208 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
209 static short cached_can_issue_more;
211 static GTY(()) section *read_only_data_section;
212 static GTY(()) section *private_data_section;
213 static GTY(()) section *read_only_private_data_section;
214 static GTY(()) section *sdata2_section;
215 static GTY(()) section *toc_section;
217 struct builtin_description
219 const unsigned int mask;
220 const enum insn_code icode;
221 const char *const name;
222 const enum rs6000_builtins code;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
227 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align[NUM_MACHINE_MODES];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask {
246 RECIP_SF_DIV = 0x001, /* Use divide estimate */
247 RECIP_DF_DIV = 0x002,
248 RECIP_V4SF_DIV = 0x004,
249 RECIP_V2DF_DIV = 0x008,
251 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT = 0x020,
253 RECIP_V4SF_RSQRT = 0x040,
254 RECIP_V2DF_RSQRT = 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
262 RECIP_HIGH_PRECISION = RECIP_ALL,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
269 /* -mrecip options. */
272 const char *string; /* option name */
273 unsigned int mask; /* mask bits to set */
274 } recip_options[] = {
275 { "all", RECIP_ALL },
276 { "none", RECIP_NONE },
277 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
280 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
281 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT) },
283 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
284 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
296 /* Target cpu costs. */
298 struct processor_costs {
299 const int mulsi; /* cost of SImode multiplication. */
300 const int mulsi_const; /* cost of SImode multiplication by constant. */
301 const int mulsi_const9; /* cost of SImode mult by short constant. */
302 const int muldi; /* cost of DImode multiplication. */
303 const int divsi; /* cost of SImode division. */
304 const int divdi; /* cost of DImode division. */
305 const int fp; /* cost of simple SFmode and DFmode insns. */
306 const int dmul; /* cost of DFmode multiplication (and fmadd). */
307 const int sdiv; /* cost of SFmode division (fdivs). */
308 const int ddiv; /* cost of DFmode division (fdiv). */
309 const int cache_line_size; /* cache line size in bytes. */
310 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
311 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
312 const int simultaneous_prefetches; /* number of parallel prefetch
316 const struct processor_costs *rs6000_cost;
318 /* Processor costs (relative to an add) */
320 /* Instruction size costs on 32bit processors. */
322 struct processor_costs size32_cost = {
323 COSTS_N_INSNS (1), /* mulsi */
324 COSTS_N_INSNS (1), /* mulsi_const */
325 COSTS_N_INSNS (1), /* mulsi_const9 */
326 COSTS_N_INSNS (1), /* muldi */
327 COSTS_N_INSNS (1), /* divsi */
328 COSTS_N_INSNS (1), /* divdi */
329 COSTS_N_INSNS (1), /* fp */
330 COSTS_N_INSNS (1), /* dmul */
331 COSTS_N_INSNS (1), /* sdiv */
332 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction size costs on 64bit processors. */
341 struct processor_costs size64_cost = {
342 COSTS_N_INSNS (1), /* mulsi */
343 COSTS_N_INSNS (1), /* mulsi_const */
344 COSTS_N_INSNS (1), /* mulsi_const9 */
345 COSTS_N_INSNS (1), /* muldi */
346 COSTS_N_INSNS (1), /* divsi */
347 COSTS_N_INSNS (1), /* divdi */
348 COSTS_N_INSNS (1), /* fp */
349 COSTS_N_INSNS (1), /* dmul */
350 COSTS_N_INSNS (1), /* sdiv */
351 COSTS_N_INSNS (1), /* ddiv */
358 /* Instruction costs on RIOS1 processors. */
360 struct processor_costs rios1_cost = {
361 COSTS_N_INSNS (5), /* mulsi */
362 COSTS_N_INSNS (4), /* mulsi_const */
363 COSTS_N_INSNS (3), /* mulsi_const9 */
364 COSTS_N_INSNS (5), /* muldi */
365 COSTS_N_INSNS (19), /* divsi */
366 COSTS_N_INSNS (19), /* divdi */
367 COSTS_N_INSNS (2), /* fp */
368 COSTS_N_INSNS (2), /* dmul */
369 COSTS_N_INSNS (19), /* sdiv */
370 COSTS_N_INSNS (19), /* ddiv */
371 128, /* cache line size */
377 /* Instruction costs on RIOS2 processors. */
379 struct processor_costs rios2_cost = {
380 COSTS_N_INSNS (2), /* mulsi */
381 COSTS_N_INSNS (2), /* mulsi_const */
382 COSTS_N_INSNS (2), /* mulsi_const9 */
383 COSTS_N_INSNS (2), /* muldi */
384 COSTS_N_INSNS (13), /* divsi */
385 COSTS_N_INSNS (13), /* divdi */
386 COSTS_N_INSNS (2), /* fp */
387 COSTS_N_INSNS (2), /* dmul */
388 COSTS_N_INSNS (17), /* sdiv */
389 COSTS_N_INSNS (17), /* ddiv */
390 256, /* cache line size */
396 /* Instruction costs on RS64A processors. */
398 struct processor_costs rs64a_cost = {
399 COSTS_N_INSNS (20), /* mulsi */
400 COSTS_N_INSNS (12), /* mulsi_const */
401 COSTS_N_INSNS (8), /* mulsi_const9 */
402 COSTS_N_INSNS (34), /* muldi */
403 COSTS_N_INSNS (65), /* divsi */
404 COSTS_N_INSNS (67), /* divdi */
405 COSTS_N_INSNS (4), /* fp */
406 COSTS_N_INSNS (4), /* dmul */
407 COSTS_N_INSNS (31), /* sdiv */
408 COSTS_N_INSNS (31), /* ddiv */
409 128, /* cache line size */
415 /* Instruction costs on MPCCORE processors. */
417 struct processor_costs mpccore_cost = {
418 COSTS_N_INSNS (2), /* mulsi */
419 COSTS_N_INSNS (2), /* mulsi_const */
420 COSTS_N_INSNS (2), /* mulsi_const9 */
421 COSTS_N_INSNS (2), /* muldi */
422 COSTS_N_INSNS (6), /* divsi */
423 COSTS_N_INSNS (6), /* divdi */
424 COSTS_N_INSNS (4), /* fp */
425 COSTS_N_INSNS (5), /* dmul */
426 COSTS_N_INSNS (10), /* sdiv */
427 COSTS_N_INSNS (17), /* ddiv */
428 32, /* cache line size */
434 /* Instruction costs on PPC403 processors. */
436 struct processor_costs ppc403_cost = {
437 COSTS_N_INSNS (4), /* mulsi */
438 COSTS_N_INSNS (4), /* mulsi_const */
439 COSTS_N_INSNS (4), /* mulsi_const9 */
440 COSTS_N_INSNS (4), /* muldi */
441 COSTS_N_INSNS (33), /* divsi */
442 COSTS_N_INSNS (33), /* divdi */
443 COSTS_N_INSNS (11), /* fp */
444 COSTS_N_INSNS (11), /* dmul */
445 COSTS_N_INSNS (11), /* sdiv */
446 COSTS_N_INSNS (11), /* ddiv */
447 32, /* cache line size */
453 /* Instruction costs on PPC405 processors. */
455 struct processor_costs ppc405_cost = {
456 COSTS_N_INSNS (5), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (3), /* mulsi_const9 */
459 COSTS_N_INSNS (5), /* muldi */
460 COSTS_N_INSNS (35), /* divsi */
461 COSTS_N_INSNS (35), /* divdi */
462 COSTS_N_INSNS (11), /* fp */
463 COSTS_N_INSNS (11), /* dmul */
464 COSTS_N_INSNS (11), /* sdiv */
465 COSTS_N_INSNS (11), /* ddiv */
466 32, /* cache line size */
472 /* Instruction costs on PPC440 processors. */
474 struct processor_costs ppc440_cost = {
475 COSTS_N_INSNS (3), /* mulsi */
476 COSTS_N_INSNS (2), /* mulsi_const */
477 COSTS_N_INSNS (2), /* mulsi_const9 */
478 COSTS_N_INSNS (3), /* muldi */
479 COSTS_N_INSNS (34), /* divsi */
480 COSTS_N_INSNS (34), /* divdi */
481 COSTS_N_INSNS (5), /* fp */
482 COSTS_N_INSNS (5), /* dmul */
483 COSTS_N_INSNS (19), /* sdiv */
484 COSTS_N_INSNS (33), /* ddiv */
485 32, /* cache line size */
491 /* Instruction costs on PPC476 processors. */
493 struct processor_costs ppc476_cost = {
494 COSTS_N_INSNS (4), /* mulsi */
495 COSTS_N_INSNS (4), /* mulsi_const */
496 COSTS_N_INSNS (4), /* mulsi_const9 */
497 COSTS_N_INSNS (4), /* muldi */
498 COSTS_N_INSNS (11), /* divsi */
499 COSTS_N_INSNS (11), /* divdi */
500 COSTS_N_INSNS (6), /* fp */
501 COSTS_N_INSNS (6), /* dmul */
502 COSTS_N_INSNS (19), /* sdiv */
503 COSTS_N_INSNS (33), /* ddiv */
504 32, /* l1 cache line size */
510 /* Instruction costs on PPC601 processors. */
512 struct processor_costs ppc601_cost = {
513 COSTS_N_INSNS (5), /* mulsi */
514 COSTS_N_INSNS (5), /* mulsi_const */
515 COSTS_N_INSNS (5), /* mulsi_const9 */
516 COSTS_N_INSNS (5), /* muldi */
517 COSTS_N_INSNS (36), /* divsi */
518 COSTS_N_INSNS (36), /* divdi */
519 COSTS_N_INSNS (4), /* fp */
520 COSTS_N_INSNS (5), /* dmul */
521 COSTS_N_INSNS (17), /* sdiv */
522 COSTS_N_INSNS (31), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC603 processors. */
531 struct processor_costs ppc603_cost = {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (3), /* mulsi_const */
534 COSTS_N_INSNS (2), /* mulsi_const9 */
535 COSTS_N_INSNS (5), /* muldi */
536 COSTS_N_INSNS (37), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (4), /* dmul */
540 COSTS_N_INSNS (18), /* sdiv */
541 COSTS_N_INSNS (33), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC604 processors. */
550 struct processor_costs ppc604_cost = {
551 COSTS_N_INSNS (4), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (4), /* mulsi_const9 */
554 COSTS_N_INSNS (4), /* muldi */
555 COSTS_N_INSNS (20), /* divsi */
556 COSTS_N_INSNS (20), /* divdi */
557 COSTS_N_INSNS (3), /* fp */
558 COSTS_N_INSNS (3), /* dmul */
559 COSTS_N_INSNS (18), /* sdiv */
560 COSTS_N_INSNS (32), /* ddiv */
561 32, /* cache line size */
567 /* Instruction costs on PPC604e processors. */
569 struct processor_costs ppc604e_cost = {
570 COSTS_N_INSNS (2), /* mulsi */
571 COSTS_N_INSNS (2), /* mulsi_const */
572 COSTS_N_INSNS (2), /* mulsi_const9 */
573 COSTS_N_INSNS (2), /* muldi */
574 COSTS_N_INSNS (20), /* divsi */
575 COSTS_N_INSNS (20), /* divdi */
576 COSTS_N_INSNS (3), /* fp */
577 COSTS_N_INSNS (3), /* dmul */
578 COSTS_N_INSNS (18), /* sdiv */
579 COSTS_N_INSNS (32), /* ddiv */
580 32, /* cache line size */
586 /* Instruction costs on PPC620 processors. */
588 struct processor_costs ppc620_cost = {
589 COSTS_N_INSNS (5), /* mulsi */
590 COSTS_N_INSNS (4), /* mulsi_const */
591 COSTS_N_INSNS (3), /* mulsi_const9 */
592 COSTS_N_INSNS (7), /* muldi */
593 COSTS_N_INSNS (21), /* divsi */
594 COSTS_N_INSNS (37), /* divdi */
595 COSTS_N_INSNS (3), /* fp */
596 COSTS_N_INSNS (3), /* dmul */
597 COSTS_N_INSNS (18), /* sdiv */
598 COSTS_N_INSNS (32), /* ddiv */
599 128, /* cache line size */
605 /* Instruction costs on PPC630 processors. */
607 struct processor_costs ppc630_cost = {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (4), /* mulsi_const */
610 COSTS_N_INSNS (3), /* mulsi_const9 */
611 COSTS_N_INSNS (7), /* muldi */
612 COSTS_N_INSNS (21), /* divsi */
613 COSTS_N_INSNS (37), /* divdi */
614 COSTS_N_INSNS (3), /* fp */
615 COSTS_N_INSNS (3), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (21), /* ddiv */
618 128, /* cache line size */
624 /* Instruction costs on Cell processor. */
625 /* COSTS_N_INSNS (1) ~ one add. */
627 struct processor_costs ppccell_cost = {
628 COSTS_N_INSNS (9/2)+2, /* mulsi */
629 COSTS_N_INSNS (6/2), /* mulsi_const */
630 COSTS_N_INSNS (6/2), /* mulsi_const9 */
631 COSTS_N_INSNS (15/2)+2, /* muldi */
632 COSTS_N_INSNS (38/2), /* divsi */
633 COSTS_N_INSNS (70/2), /* divdi */
634 COSTS_N_INSNS (10/2), /* fp */
635 COSTS_N_INSNS (10/2), /* dmul */
636 COSTS_N_INSNS (74/2), /* sdiv */
637 COSTS_N_INSNS (74/2), /* ddiv */
638 128, /* cache line size */
644 /* Instruction costs on PPC750 and PPC7400 processors. */
646 struct processor_costs ppc750_cost = {
647 COSTS_N_INSNS (5), /* mulsi */
648 COSTS_N_INSNS (3), /* mulsi_const */
649 COSTS_N_INSNS (2), /* mulsi_const9 */
650 COSTS_N_INSNS (5), /* muldi */
651 COSTS_N_INSNS (17), /* divsi */
652 COSTS_N_INSNS (17), /* divdi */
653 COSTS_N_INSNS (3), /* fp */
654 COSTS_N_INSNS (3), /* dmul */
655 COSTS_N_INSNS (17), /* sdiv */
656 COSTS_N_INSNS (31), /* ddiv */
657 32, /* cache line size */
663 /* Instruction costs on PPC7450 processors. */
665 struct processor_costs ppc7450_cost = {
666 COSTS_N_INSNS (4), /* mulsi */
667 COSTS_N_INSNS (3), /* mulsi_const */
668 COSTS_N_INSNS (3), /* mulsi_const9 */
669 COSTS_N_INSNS (4), /* muldi */
670 COSTS_N_INSNS (23), /* divsi */
671 COSTS_N_INSNS (23), /* divdi */
672 COSTS_N_INSNS (5), /* fp */
673 COSTS_N_INSNS (5), /* dmul */
674 COSTS_N_INSNS (21), /* sdiv */
675 COSTS_N_INSNS (35), /* ddiv */
676 32, /* cache line size */
682 /* Instruction costs on PPC8540 processors. */
684 struct processor_costs ppc8540_cost = {
685 COSTS_N_INSNS (4), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (4), /* mulsi_const9 */
688 COSTS_N_INSNS (4), /* muldi */
689 COSTS_N_INSNS (19), /* divsi */
690 COSTS_N_INSNS (19), /* divdi */
691 COSTS_N_INSNS (4), /* fp */
692 COSTS_N_INSNS (4), /* dmul */
693 COSTS_N_INSNS (29), /* sdiv */
694 COSTS_N_INSNS (29), /* ddiv */
695 32, /* cache line size */
698 1, /* prefetch streams /*/
701 /* Instruction costs on E300C2 and E300C3 cores. */
703 struct processor_costs ppce300c2c3_cost = {
704 COSTS_N_INSNS (4), /* mulsi */
705 COSTS_N_INSNS (4), /* mulsi_const */
706 COSTS_N_INSNS (4), /* mulsi_const9 */
707 COSTS_N_INSNS (4), /* muldi */
708 COSTS_N_INSNS (19), /* divsi */
709 COSTS_N_INSNS (19), /* divdi */
710 COSTS_N_INSNS (3), /* fp */
711 COSTS_N_INSNS (4), /* dmul */
712 COSTS_N_INSNS (18), /* sdiv */
713 COSTS_N_INSNS (33), /* ddiv */
717 1, /* prefetch streams /*/
720 /* Instruction costs on PPCE500MC processors. */
722 struct processor_costs ppce500mc_cost = {
723 COSTS_N_INSNS (4), /* mulsi */
724 COSTS_N_INSNS (4), /* mulsi_const */
725 COSTS_N_INSNS (4), /* mulsi_const9 */
726 COSTS_N_INSNS (4), /* muldi */
727 COSTS_N_INSNS (14), /* divsi */
728 COSTS_N_INSNS (14), /* divdi */
729 COSTS_N_INSNS (8), /* fp */
730 COSTS_N_INSNS (10), /* dmul */
731 COSTS_N_INSNS (36), /* sdiv */
732 COSTS_N_INSNS (66), /* ddiv */
733 64, /* cache line size */
736 1, /* prefetch streams /*/
739 /* Instruction costs on PPCE500MC64 processors. */
741 struct processor_costs ppce500mc64_cost = {
742 COSTS_N_INSNS (4), /* mulsi */
743 COSTS_N_INSNS (4), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (4), /* muldi */
746 COSTS_N_INSNS (14), /* divsi */
747 COSTS_N_INSNS (14), /* divdi */
748 COSTS_N_INSNS (4), /* fp */
749 COSTS_N_INSNS (10), /* dmul */
750 COSTS_N_INSNS (36), /* sdiv */
751 COSTS_N_INSNS (66), /* ddiv */
752 64, /* cache line size */
755 1, /* prefetch streams /*/
758 /* Instruction costs on AppliedMicro Titan processors. */
760 struct processor_costs titan_cost = {
761 COSTS_N_INSNS (5), /* mulsi */
762 COSTS_N_INSNS (5), /* mulsi_const */
763 COSTS_N_INSNS (5), /* mulsi_const9 */
764 COSTS_N_INSNS (5), /* muldi */
765 COSTS_N_INSNS (18), /* divsi */
766 COSTS_N_INSNS (18), /* divdi */
767 COSTS_N_INSNS (10), /* fp */
768 COSTS_N_INSNS (10), /* dmul */
769 COSTS_N_INSNS (46), /* sdiv */
770 COSTS_N_INSNS (72), /* ddiv */
771 32, /* cache line size */
774 1, /* prefetch streams /*/
777 /* Instruction costs on POWER4 and POWER5 processors. */
779 struct processor_costs power4_cost = {
780 COSTS_N_INSNS (3), /* mulsi */
781 COSTS_N_INSNS (2), /* mulsi_const */
782 COSTS_N_INSNS (2), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (18), /* divsi */
785 COSTS_N_INSNS (34), /* divdi */
786 COSTS_N_INSNS (3), /* fp */
787 COSTS_N_INSNS (3), /* dmul */
788 COSTS_N_INSNS (17), /* sdiv */
789 COSTS_N_INSNS (17), /* ddiv */
790 128, /* cache line size */
793 8, /* prefetch streams /*/
796 /* Instruction costs on POWER6 processors. */
798 struct processor_costs power6_cost = {
799 COSTS_N_INSNS (8), /* mulsi */
800 COSTS_N_INSNS (8), /* mulsi_const */
801 COSTS_N_INSNS (8), /* mulsi_const9 */
802 COSTS_N_INSNS (8), /* muldi */
803 COSTS_N_INSNS (22), /* divsi */
804 COSTS_N_INSNS (28), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (3), /* dmul */
807 COSTS_N_INSNS (13), /* sdiv */
808 COSTS_N_INSNS (16), /* ddiv */
809 128, /* cache line size */
812 16, /* prefetch streams */
815 /* Instruction costs on POWER7 processors. */
817 struct processor_costs power7_cost = {
818 COSTS_N_INSNS (2), /* mulsi */
819 COSTS_N_INSNS (2), /* mulsi_const */
820 COSTS_N_INSNS (2), /* mulsi_const9 */
821 COSTS_N_INSNS (2), /* muldi */
822 COSTS_N_INSNS (18), /* divsi */
823 COSTS_N_INSNS (34), /* divdi */
824 COSTS_N_INSNS (3), /* fp */
825 COSTS_N_INSNS (3), /* dmul */
826 COSTS_N_INSNS (13), /* sdiv */
827 COSTS_N_INSNS (16), /* ddiv */
828 128, /* cache line size */
831 12, /* prefetch streams */
834 /* Instruction costs on POWER A2 processors. */
836 struct processor_costs ppca2_cost = {
837 COSTS_N_INSNS (16), /* mulsi */
838 COSTS_N_INSNS (16), /* mulsi_const */
839 COSTS_N_INSNS (16), /* mulsi_const9 */
840 COSTS_N_INSNS (16), /* muldi */
841 COSTS_N_INSNS (22), /* divsi */
842 COSTS_N_INSNS (28), /* divdi */
843 COSTS_N_INSNS (3), /* fp */
844 COSTS_N_INSNS (3), /* dmul */
845 COSTS_N_INSNS (59), /* sdiv */
846 COSTS_N_INSNS (72), /* ddiv */
850 16, /* prefetch streams */
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867 { NAME, ICODE, MASK, ATTR },
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
870 { NAME, ICODE, MASK, ATTR },
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
873 { NAME, ICODE, MASK, ATTR },
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
876 { NAME, ICODE, MASK, ATTR },
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
879 { NAME, ICODE, MASK, ATTR },
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
882 { NAME, ICODE, MASK, ATTR },
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
885 { NAME, ICODE, MASK, ATTR },
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
888 { NAME, ICODE, MASK, ATTR },
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
891 { NAME, ICODE, MASK, ATTR },
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
894 { NAME, ICODE, MASK, ATTR },
896 struct rs6000_builtin_info_type {
898 const enum insn_code icode;
903 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
905 #include "rs6000-builtin.def"
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
920 static tree (*rs6000_veclib_handler) (tree, tree, tree);
923 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
924 static bool spe_func_has_64bit_regs_p (void);
925 static struct machine_function * rs6000_init_machine_status (void);
926 static int rs6000_ra_ever_killed (void);
927 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
928 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
929 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
930 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
931 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
932 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
933 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
934 static int rs6000_debug_address_cost (rtx, bool);
935 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
936 static bool is_microcoded_insn (rtx);
937 static bool is_nonpipeline_insn (rtx);
938 static bool is_cracked_insn (rtx);
939 static bool is_load_insn (rtx);
940 static rtx get_store_dest (rtx pat);
941 static bool is_store_insn (rtx);
942 static bool set_to_load_agen (rtx,rtx);
943 static bool insn_terminates_group_p (rtx , enum group_termination);
944 static bool insn_must_be_first_in_group (rtx);
945 static bool insn_must_be_last_in_group (rtx);
946 static void altivec_init_builtins (void);
947 static tree builtin_function_type (enum machine_mode, enum machine_mode,
948 enum machine_mode, enum machine_mode,
949 enum rs6000_builtins, const char *name);
950 static void rs6000_common_init_builtins (void);
951 static void paired_init_builtins (void);
952 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
953 static void spe_init_builtins (void);
954 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
955 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
956 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
957 static rs6000_stack_t *rs6000_stack_info (void);
958 static void is_altivec_return_reg (rtx, void *);
959 int easy_vector_constant (rtx, enum machine_mode);
960 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
961 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
962 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
963 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
964 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
967 static void macho_branch_islands (void);
969 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
971 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
973 static bool rs6000_mode_dependent_address (const_rtx);
974 static bool rs6000_debug_mode_dependent_address (const_rtx);
975 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
976 enum machine_mode, rtx);
977 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
980 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
981 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
983 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
985 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
988 static bool rs6000_cannot_change_mode_class (enum machine_mode,
991 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
994 static bool rs6000_save_toc_in_prologue_p (void);
996 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
998 = rs6000_legitimize_reload_address;
1000 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1001 = rs6000_mode_dependent_address;
1003 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1004 enum machine_mode, rtx)
1005 = rs6000_secondary_reload_class;
1007 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1008 = rs6000_preferred_reload_class;
1010 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1012 = rs6000_secondary_memory_needed;
1014 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1017 = rs6000_cannot_change_mode_class;
1019 const int INSN_NOT_AVAILABLE = -1;
1021 /* Hash table stuff for keeping track of TOC entries. */
1023 struct GTY(()) toc_hash_struct
1025 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1026 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1028 enum machine_mode key_mode;
1032 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1034 /* Hash table to keep track of the argument types for builtin functions. */
1036 struct GTY(()) builtin_hash_struct
1039 enum machine_mode mode[4]; /* return value + 3 arguments. */
1040 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1043 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1046 /* Default register names. */
1047 char rs6000_reg_names[][8] =
1049 "0", "1", "2", "3", "4", "5", "6", "7",
1050 "8", "9", "10", "11", "12", "13", "14", "15",
1051 "16", "17", "18", "19", "20", "21", "22", "23",
1052 "24", "25", "26", "27", "28", "29", "30", "31",
1053 "0", "1", "2", "3", "4", "5", "6", "7",
1054 "8", "9", "10", "11", "12", "13", "14", "15",
1055 "16", "17", "18", "19", "20", "21", "22", "23",
1056 "24", "25", "26", "27", "28", "29", "30", "31",
1057 "mq", "lr", "ctr","ap",
1058 "0", "1", "2", "3", "4", "5", "6", "7",
1060 /* AltiVec registers. */
1061 "0", "1", "2", "3", "4", "5", "6", "7",
1062 "8", "9", "10", "11", "12", "13", "14", "15",
1063 "16", "17", "18", "19", "20", "21", "22", "23",
1064 "24", "25", "26", "27", "28", "29", "30", "31",
1066 /* SPE registers. */
1067 "spe_acc", "spefscr",
1068 /* Soft frame pointer. */
1072 #ifdef TARGET_REGNAMES
1073 static const char alt_reg_names[][8] =
1075 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1076 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1077 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1078 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1079 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1080 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1081 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1082 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1083 "mq", "lr", "ctr", "ap",
1084 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1086 /* AltiVec registers. */
1087 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1088 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1089 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1090 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1092 /* SPE registers. */
1093 "spe_acc", "spefscr",
1094 /* Soft frame pointer. */
1099 /* Table of valid machine attributes. */
1101 static const struct attribute_spec rs6000_attribute_table[] =
1103 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1104 affects_type_identity } */
1105 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1107 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1109 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1111 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1113 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1115 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1116 SUBTARGET_ATTRIBUTE_TABLE,
1118 { NULL, 0, 0, false, false, false, NULL, false }
1121 #ifndef MASK_STRICT_ALIGN
1122 #define MASK_STRICT_ALIGN 0
1124 #ifndef TARGET_PROFILE_KERNEL
1125 #define TARGET_PROFILE_KERNEL 0
1128 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1129 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1131 /* Initialize the GCC target structure. */
1132 #undef TARGET_ATTRIBUTE_TABLE
1133 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1134 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1135 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1136 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1137 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1139 #undef TARGET_ASM_ALIGNED_DI_OP
1140 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1142 /* Default unaligned ops are only provided for ELF. Find the ops needed
1143 for non-ELF systems. */
1144 #ifndef OBJECT_FORMAT_ELF
1146 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1148 #undef TARGET_ASM_UNALIGNED_HI_OP
1149 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1150 #undef TARGET_ASM_UNALIGNED_SI_OP
1151 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1152 #undef TARGET_ASM_UNALIGNED_DI_OP
1153 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1156 #undef TARGET_ASM_UNALIGNED_HI_OP
1157 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1158 #undef TARGET_ASM_UNALIGNED_SI_OP
1159 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1160 #undef TARGET_ASM_UNALIGNED_DI_OP
1161 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1162 #undef TARGET_ASM_ALIGNED_DI_OP
1163 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1167 /* This hook deals with fixups for relocatable code and DI-mode objects
1169 #undef TARGET_ASM_INTEGER
1170 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1172 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1173 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1174 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1177 #undef TARGET_SET_UP_BY_PROLOGUE
1178 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1180 #undef TARGET_HAVE_TLS
1181 #define TARGET_HAVE_TLS HAVE_AS_TLS
1183 #undef TARGET_CANNOT_FORCE_CONST_MEM
1184 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1186 #undef TARGET_DELEGITIMIZE_ADDRESS
1187 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1189 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1190 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1192 #undef TARGET_ASM_FUNCTION_PROLOGUE
1193 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1194 #undef TARGET_ASM_FUNCTION_EPILOGUE
1195 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1197 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1198 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1200 #undef TARGET_LEGITIMIZE_ADDRESS
1201 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1203 #undef TARGET_SCHED_VARIABLE_ISSUE
1204 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1206 #undef TARGET_SCHED_ISSUE_RATE
1207 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1208 #undef TARGET_SCHED_ADJUST_COST
1209 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1210 #undef TARGET_SCHED_ADJUST_PRIORITY
1211 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1212 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1213 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1214 #undef TARGET_SCHED_INIT
1215 #define TARGET_SCHED_INIT rs6000_sched_init
1216 #undef TARGET_SCHED_FINISH
1217 #define TARGET_SCHED_FINISH rs6000_sched_finish
1218 #undef TARGET_SCHED_REORDER
1219 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1220 #undef TARGET_SCHED_REORDER2
1221 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1223 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1224 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1226 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1227 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1229 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1230 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1231 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1232 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1233 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1234 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1235 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1236 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1238 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1239 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1240 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1241 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1242 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1243 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1244 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1245 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1246 rs6000_builtin_support_vector_misalignment
1247 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1248 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1249 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1250 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1251 rs6000_builtin_vectorization_cost
1252 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1253 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1254 rs6000_preferred_simd_mode
1256 #undef TARGET_INIT_BUILTINS
1257 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1258 #undef TARGET_BUILTIN_DECL
1259 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1261 #undef TARGET_EXPAND_BUILTIN
1262 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1264 #undef TARGET_MANGLE_TYPE
1265 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1267 #undef TARGET_INIT_LIBFUNCS
1268 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1271 #undef TARGET_BINDS_LOCAL_P
1272 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1275 #undef TARGET_MS_BITFIELD_LAYOUT_P
1276 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1278 #undef TARGET_ASM_OUTPUT_MI_THUNK
1279 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1281 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1282 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1284 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1285 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1287 #undef TARGET_INVALID_WITHIN_DOLOOP
1288 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1290 #undef TARGET_REGISTER_MOVE_COST
1291 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1292 #undef TARGET_MEMORY_MOVE_COST
1293 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1294 #undef TARGET_RTX_COSTS
1295 #define TARGET_RTX_COSTS rs6000_rtx_costs
1296 #undef TARGET_ADDRESS_COST
1297 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1299 #undef TARGET_DWARF_REGISTER_SPAN
1300 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1302 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1303 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1305 /* On rs6000, function arguments are promoted, as are function return
1307 #undef TARGET_PROMOTE_FUNCTION_MODE
1308 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1310 #undef TARGET_RETURN_IN_MEMORY
1311 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1313 #undef TARGET_SETUP_INCOMING_VARARGS
1314 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1316 /* Always strict argument naming on rs6000. */
1317 #undef TARGET_STRICT_ARGUMENT_NAMING
1318 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1319 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1320 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1321 #undef TARGET_SPLIT_COMPLEX_ARG
1322 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1323 #undef TARGET_MUST_PASS_IN_STACK
1324 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1325 #undef TARGET_PASS_BY_REFERENCE
1326 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1327 #undef TARGET_ARG_PARTIAL_BYTES
1328 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1329 #undef TARGET_FUNCTION_ARG_ADVANCE
1330 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1331 #undef TARGET_FUNCTION_ARG
1332 #define TARGET_FUNCTION_ARG rs6000_function_arg
1333 #undef TARGET_FUNCTION_ARG_BOUNDARY
1334 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1336 #undef TARGET_BUILD_BUILTIN_VA_LIST
1337 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1339 #undef TARGET_EXPAND_BUILTIN_VA_START
1340 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1342 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1343 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1345 #undef TARGET_EH_RETURN_FILTER_MODE
1346 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1348 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1349 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1351 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1352 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1354 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1355 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1357 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1358 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1360 #undef TARGET_OPTION_OVERRIDE
1361 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1363 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1364 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1365 rs6000_builtin_vectorized_function
1368 #undef TARGET_STACK_PROTECT_FAIL
1369 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1372 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1373 The PowerPC architecture requires only weak consistency among
1374 processors--that is, memory accesses between processors need not be
1375 sequentially consistent and memory accesses among processors can occur
1376 in any order. The ability to order memory accesses weakly provides
1377 opportunities for more efficient use of the system bus. Unless a
1378 dependency exists, the 604e allows read operations to precede store
1380 #undef TARGET_RELAXED_ORDERING
1381 #define TARGET_RELAXED_ORDERING true
1384 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1385 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1388 /* Use a 32-bit anchor range. This leads to sequences like:
1390 addis tmp,anchor,high
1393 where tmp itself acts as an anchor, and can be shared between
1394 accesses to the same 64k page. */
1395 #undef TARGET_MIN_ANCHOR_OFFSET
1396 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1397 #undef TARGET_MAX_ANCHOR_OFFSET
1398 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1399 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1400 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1402 #undef TARGET_BUILTIN_RECIPROCAL
1403 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1405 #undef TARGET_EXPAND_TO_RTL_HOOK
1406 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1408 #undef TARGET_INSTANTIATE_DECLS
1409 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1411 #undef TARGET_SECONDARY_RELOAD
1412 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1414 #undef TARGET_LEGITIMATE_ADDRESS_P
1415 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1417 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1418 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1420 #undef TARGET_CAN_ELIMINATE
1421 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1423 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1424 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1426 #undef TARGET_TRAMPOLINE_INIT
1427 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1429 #undef TARGET_FUNCTION_VALUE
1430 #define TARGET_FUNCTION_VALUE rs6000_function_value
1432 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1433 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1435 #undef TARGET_OPTION_SAVE
1436 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1438 #undef TARGET_OPTION_RESTORE
1439 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1441 #undef TARGET_OPTION_PRINT
1442 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1444 #undef TARGET_CAN_INLINE_P
1445 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1447 #undef TARGET_SET_CURRENT_FUNCTION
1448 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1450 #undef TARGET_LEGITIMATE_CONSTANT_P
1451 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1453 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1454 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1457 /* Simplifications for entries below. */
1460 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1461 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1464 /* Some OSs don't support saving the high part of 64-bit registers on context
1465 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1466 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1467 either, the user must explicitly specify them and we won't interfere with
1468 the user's specification. */
1471 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1472 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1473 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1474 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1475 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
1476 | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
1477 | MASK_RECIP_PRECISION)
1480 /* Masks for instructions set at various powerpc ISAs. */
1482 ISA_2_1_MASKS = MASK_MFCRF,
1483 ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
1484 ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
1486 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1487 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1488 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1489 server and embedded. */
1490 ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
1491 | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
1492 ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
1494 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1495 altivec is a win so enable it. */
1496 ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
1497 ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
1503 const char *const name; /* Canonical processor name. */
1504 const enum processor_type processor; /* Processor type enum value. */
1505 const int target_enable; /* Target flags to enable. */
1508 static struct rs6000_ptt const processor_target_table[] =
1510 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1511 #include "rs6000-cpus.def"
1515 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1519 rs6000_cpu_name_lookup (const char *name)
1525 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1526 if (! strcmp (name, processor_target_table[i].name))
1534 /* Return number of consecutive hard regs needed starting at reg REGNO
1535 to hold something of mode MODE.
1536 This is ordinarily the length in words of a value of mode MODE
1537 but can be less for certain modes in special long registers.
1539 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1540 scalar instructions. The upper 32 bits are only available to the
1543 POWER and PowerPC GPRs hold 32 bits worth;
1544 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1547 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1549 unsigned HOST_WIDE_INT reg_size;
1551 if (FP_REGNO_P (regno))
1552 reg_size = (VECTOR_MEM_VSX_P (mode)
1553 ? UNITS_PER_VSX_WORD
1554 : UNITS_PER_FP_WORD);
1556 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1557 reg_size = UNITS_PER_SPE_WORD;
1559 else if (ALTIVEC_REGNO_P (regno))
1560 reg_size = UNITS_PER_ALTIVEC_WORD;
1562 /* The value returned for SCmode in the E500 double case is 2 for
1563 ABI compatibility; storing an SCmode value in a single register
1564 would require function_arg and rs6000_spe_function_arg to handle
1565 SCmode so as to pass the value correctly in a pair of
1567 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1568 && !DECIMAL_FLOAT_MODE_P (mode))
1569 reg_size = UNITS_PER_FP_WORD;
1572 reg_size = UNITS_PER_WORD;
1574 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1577 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1580 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1582 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1584 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1585 implementations. Don't allow an item to be split between a FP register
1586 and an Altivec register. */
1587 if (VECTOR_MEM_VSX_P (mode))
1589 if (FP_REGNO_P (regno))
1590 return FP_REGNO_P (last_regno);
1592 if (ALTIVEC_REGNO_P (regno))
1593 return ALTIVEC_REGNO_P (last_regno);
1596 /* The GPRs can hold any mode, but values bigger than one register
1597 cannot go past R31. */
1598 if (INT_REGNO_P (regno))
1599 return INT_REGNO_P (last_regno);
1601 /* The float registers (except for VSX vector modes) can only hold floating
1602 modes and DImode. This excludes the 32-bit decimal float mode for
1604 if (FP_REGNO_P (regno))
1606 if (SCALAR_FLOAT_MODE_P (mode)
1607 && (mode != TDmode || (regno % 2) == 0)
1608 && FP_REGNO_P (last_regno))
1611 if (GET_MODE_CLASS (mode) == MODE_INT
1612 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1615 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1616 && PAIRED_VECTOR_MODE (mode))
1622 /* The CR register can only hold CC modes. */
1623 if (CR_REGNO_P (regno))
1624 return GET_MODE_CLASS (mode) == MODE_CC;
1626 if (CA_REGNO_P (regno))
1627 return mode == BImode;
1629 /* AltiVec only in AldyVec registers. */
1630 if (ALTIVEC_REGNO_P (regno))
1631 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1633 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1634 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1637 /* We cannot put TImode anywhere except general register and it must be able
1638 to fit within the register set. In the future, allow TImode in the
1639 Altivec or VSX registers. */
1641 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1644 /* Print interesting facts about registers. */
1646 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1650 for (r = first_regno; r <= last_regno; ++r)
1652 const char *comma = "";
1655 if (first_regno == last_regno)
1656 fprintf (stderr, "%s:\t", reg_name);
1658 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1661 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1662 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1666 fprintf (stderr, ",\n\t");
1671 if (rs6000_hard_regno_nregs[m][r] > 1)
1672 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1673 rs6000_hard_regno_nregs[m][r]);
1675 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1680 if (call_used_regs[r])
1684 fprintf (stderr, ",\n\t");
1689 len += fprintf (stderr, "%s%s", comma, "call-used");
1697 fprintf (stderr, ",\n\t");
1702 len += fprintf (stderr, "%s%s", comma, "fixed");
1708 fprintf (stderr, ",\n\t");
1712 fprintf (stderr, "%sregno = %d\n", comma, r);
1716 #define DEBUG_FMT_D "%-32s= %d\n"
1717 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1718 #define DEBUG_FMT_S "%-32s= %s\n"
1720 /* Print various interesting information with -mdebug=reg. */
1722 rs6000_debug_reg_global (void)
1724 static const char *const tf[2] = { "false", "true" };
1725 const char *nl = (const char *)0;
1727 char costly_num[20];
1729 const char *costly_str;
1730 const char *nop_str;
1731 const char *trace_str;
1732 const char *abi_str;
1733 const char *cmodel_str;
1735 /* Map enum rs6000_vector to string. */
1736 static const char *rs6000_debug_vector_unit[] = {
1745 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1746 LAST_VIRTUAL_REGISTER);
1747 rs6000_debug_reg_print (0, 31, "gr");
1748 rs6000_debug_reg_print (32, 63, "fp");
1749 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1752 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1753 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1754 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1755 rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
1756 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1757 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1758 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1759 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1760 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1764 "d reg_class = %s\n"
1765 "f reg_class = %s\n"
1766 "v reg_class = %s\n"
1767 "wa reg_class = %s\n"
1768 "wd reg_class = %s\n"
1769 "wf reg_class = %s\n"
1770 "ws reg_class = %s\n\n",
1771 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1772 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1773 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1774 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1775 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1776 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1777 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1779 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1780 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1783 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1785 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1786 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
1792 if (rs6000_recip_control)
1794 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
1796 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1797 if (rs6000_recip_bits[m])
1800 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1802 (RS6000_RECIP_AUTO_RE_P (m)
1804 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
1805 (RS6000_RECIP_AUTO_RSQRTE_P (m)
1807 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
1810 fputs ("\n", stderr);
1813 if (rs6000_cpu_index >= 0)
1814 fprintf (stderr, DEBUG_FMT_S, "cpu",
1815 processor_target_table[rs6000_cpu_index].name);
1817 if (rs6000_tune_index >= 0)
1818 fprintf (stderr, DEBUG_FMT_S, "tune",
1819 processor_target_table[rs6000_tune_index].name);
1821 switch (rs6000_sched_costly_dep)
1823 case max_dep_latency:
1824 costly_str = "max_dep_latency";
1828 costly_str = "no_dep_costly";
1831 case all_deps_costly:
1832 costly_str = "all_deps_costly";
1835 case true_store_to_load_dep_costly:
1836 costly_str = "true_store_to_load_dep_costly";
1839 case store_to_load_dep_costly:
1840 costly_str = "store_to_load_dep_costly";
1844 costly_str = costly_num;
1845 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
1849 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
1851 switch (rs6000_sched_insert_nops)
1853 case sched_finish_regroup_exact:
1854 nop_str = "sched_finish_regroup_exact";
1857 case sched_finish_pad_groups:
1858 nop_str = "sched_finish_pad_groups";
1861 case sched_finish_none:
1862 nop_str = "sched_finish_none";
1867 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
1871 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
1873 switch (rs6000_sdata)
1880 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
1884 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
1888 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
1893 switch (rs6000_traceback)
1895 case traceback_default: trace_str = "default"; break;
1896 case traceback_none: trace_str = "none"; break;
1897 case traceback_part: trace_str = "part"; break;
1898 case traceback_full: trace_str = "full"; break;
1899 default: trace_str = "unknown"; break;
1902 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
1904 switch (rs6000_current_cmodel)
1906 case CMODEL_SMALL: cmodel_str = "small"; break;
1907 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
1908 case CMODEL_LARGE: cmodel_str = "large"; break;
1909 default: cmodel_str = "unknown"; break;
1912 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
1914 switch (rs6000_current_abi)
1916 case ABI_NONE: abi_str = "none"; break;
1917 case ABI_AIX: abi_str = "aix"; break;
1918 case ABI_V4: abi_str = "V4"; break;
1919 case ABI_DARWIN: abi_str = "darwin"; break;
1920 default: abi_str = "unknown"; break;
1923 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
1925 if (rs6000_altivec_abi)
1926 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
1929 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
1931 if (rs6000_darwin64_abi)
1932 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
1934 if (rs6000_float_gprs)
1935 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
1937 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
1938 fprintf (stderr, DEBUG_FMT_S, "align_branch",
1939 tf[!!rs6000_align_branch_targets]);
1940 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
1941 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
1942 rs6000_long_double_type_size);
1943 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
1944 (int)rs6000_sched_restricted_insns_priority);
1945 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
1947 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
1948 (int)RS6000_BUILTIN_COUNT);
1949 fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
1952 /* Initialize the various global tables that are based on register size. */
1954 rs6000_init_hard_regno_mode_ok (bool global_init_p)
1960 /* Precalculate REGNO_REG_CLASS. */
1961 rs6000_regno_regclass[0] = GENERAL_REGS;
1962 for (r = 1; r < 32; ++r)
1963 rs6000_regno_regclass[r] = BASE_REGS;
1965 for (r = 32; r < 64; ++r)
1966 rs6000_regno_regclass[r] = FLOAT_REGS;
1968 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
1969 rs6000_regno_regclass[r] = NO_REGS;
1971 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
1972 rs6000_regno_regclass[r] = ALTIVEC_REGS;
1974 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
1975 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
1976 rs6000_regno_regclass[r] = CR_REGS;
1978 rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
1979 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
1980 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
1981 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
1982 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
1983 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
1984 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
1985 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
1986 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
1987 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
1989 /* Precalculate vector information, this must be set up before the
1990 rs6000_hard_regno_nregs_internal below. */
1991 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1993 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
1994 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
1995 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
1998 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
1999 rs6000_constraints[c] = NO_REGS;
2001 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2002 believes it can use native alignment or still uses 128-bit alignment. */
2003 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2014 /* V2DF mode, VSX only. */
2017 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2018 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2019 rs6000_vector_align[V2DFmode] = align64;
2022 /* V4SF mode, either VSX or Altivec. */
2025 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2026 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2027 rs6000_vector_align[V4SFmode] = align32;
2029 else if (TARGET_ALTIVEC)
2031 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2032 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2033 rs6000_vector_align[V4SFmode] = align32;
2036 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2040 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2041 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2042 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2043 rs6000_vector_align[V4SImode] = align32;
2044 rs6000_vector_align[V8HImode] = align32;
2045 rs6000_vector_align[V16QImode] = align32;
2049 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2050 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2051 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2055 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2056 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2057 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2061 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2062 Altivec doesn't have 64-bit support. */
2065 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2066 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2067 rs6000_vector_align[V2DImode] = align64;
2070 /* DFmode, see if we want to use the VSX unit. */
2071 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2073 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2074 rs6000_vector_mem[DFmode]
2075 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2076 rs6000_vector_align[DFmode] = align64;
2079 /* TODO add SPE and paired floating point vector support. */
2081 /* Register class constaints for the constraints that depend on compile
2083 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2084 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2086 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2087 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2091 /* At present, we just use VSX_REGS, but we have different constraints
2092 based on the use, in case we want to fine tune the default register
2093 class used. wa = any VSX register, wf = register class to use for
2094 V4SF, wd = register class to use for V2DF, and ws = register classs to
2095 use for DF scalars. */
2096 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2097 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2098 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2099 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2105 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2107 /* Set up the reload helper functions. */
2108 if (TARGET_VSX || TARGET_ALTIVEC)
2112 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2113 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2114 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2115 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2116 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2117 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2118 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2119 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2120 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2121 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2122 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2123 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2124 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2126 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
2127 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
2132 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2133 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2134 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2135 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2136 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2137 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2138 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2139 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2140 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2141 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2142 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2143 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2144 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2146 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
2147 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
2152 /* Precalculate HARD_REGNO_NREGS. */
2153 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2154 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2155 rs6000_hard_regno_nregs[m][r]
2156 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2158 /* Precalculate HARD_REGNO_MODE_OK. */
2159 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2160 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2161 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2162 rs6000_hard_regno_mode_ok_p[m][r] = true;
2164 /* Precalculate CLASS_MAX_NREGS sizes. */
2165 for (c = 0; c < LIM_REG_CLASSES; ++c)
2169 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2170 reg_size = UNITS_PER_VSX_WORD;
2172 else if (c == ALTIVEC_REGS)
2173 reg_size = UNITS_PER_ALTIVEC_WORD;
2175 else if (c == FLOAT_REGS)
2176 reg_size = UNITS_PER_FP_WORD;
2179 reg_size = UNITS_PER_WORD;
2181 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2182 rs6000_class_max_nregs[m][c]
2183 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2186 if (TARGET_E500_DOUBLE)
2187 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2189 /* Calculate which modes to automatically generate code to use a the
2190 reciprocal divide and square root instructions. In the future, possibly
2191 automatically generate the instructions even if the user did not specify
2192 -mrecip. The older machines double precision reciprocal sqrt estimate is
2193 not accurate enough. */
2194 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2196 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2198 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2199 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2200 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2201 if (VECTOR_UNIT_VSX_P (V2DFmode))
2202 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2204 if (TARGET_FRSQRTES)
2205 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2207 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2208 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2209 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2210 if (VECTOR_UNIT_VSX_P (V2DFmode))
2211 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2213 if (rs6000_recip_control)
2215 if (!flag_finite_math_only)
2216 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2217 if (flag_trapping_math)
2218 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2219 if (!flag_reciprocal_math)
2220 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2221 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2223 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2224 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2225 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2227 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2228 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2229 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2231 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2232 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2233 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2235 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2236 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2237 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2239 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2240 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2241 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2243 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2244 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2245 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2247 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2248 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2249 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2251 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2252 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2253 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2257 if (global_init_p || TARGET_DEBUG_TARGET)
2259 if (TARGET_DEBUG_REG)
2260 rs6000_debug_reg_global ();
2262 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2264 "SImode variable mult cost = %d\n"
2265 "SImode constant mult cost = %d\n"
2266 "SImode short constant mult cost = %d\n"
2267 "DImode multipliciation cost = %d\n"
2268 "SImode division cost = %d\n"
2269 "DImode division cost = %d\n"
2270 "Simple fp operation cost = %d\n"
2271 "DFmode multiplication cost = %d\n"
2272 "SFmode division cost = %d\n"
2273 "DFmode division cost = %d\n"
2274 "cache line size = %d\n"
2275 "l1 cache size = %d\n"
2276 "l2 cache size = %d\n"
2277 "simultaneous prefetches = %d\n"
2280 rs6000_cost->mulsi_const,
2281 rs6000_cost->mulsi_const9,
2289 rs6000_cost->cache_line_size,
2290 rs6000_cost->l1_cache_size,
2291 rs6000_cost->l2_cache_size,
2292 rs6000_cost->simultaneous_prefetches);
2297 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2300 darwin_rs6000_override_options (void)
2302 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2304 rs6000_altivec_abi = 1;
2305 TARGET_ALTIVEC_VRSAVE = 1;
2306 rs6000_current_abi = ABI_DARWIN;
2308 if (DEFAULT_ABI == ABI_DARWIN
2310 darwin_one_byte_bool = 1;
2312 if (TARGET_64BIT && ! TARGET_POWERPC64)
2314 target_flags |= MASK_POWERPC64;
2315 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2319 rs6000_default_long_calls = 1;
2320 target_flags |= MASK_SOFT_FLOAT;
2323 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2325 if (!flag_mkernel && !flag_apple_kext
2327 && ! (target_flags_explicit & MASK_ALTIVEC))
2328 target_flags |= MASK_ALTIVEC;
2330 /* Unless the user (not the configurer) has explicitly overridden
2331 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2332 G4 unless targetting the kernel. */
2335 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2336 && ! (target_flags_explicit & MASK_ALTIVEC)
2337 && ! global_options_set.x_rs6000_cpu_index)
2339 target_flags |= MASK_ALTIVEC;
2344 /* If not otherwise specified by a target, make 'long double' equivalent to
2347 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2348 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2351 /* Return the builtin mask of the various options used that could affect which
2352 builtins were used. In the past we used target_flags, but we've run out of
2353 bits, and some options like SPE and PAIRED are no longer in
2357 rs6000_builtin_mask_calculate (void)
2359 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2360 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2361 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2362 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2363 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2364 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2365 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2366 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2367 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2368 | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0)
2369 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2372 /* Override command line options. Mostly we process the processor type and
2373 sometimes adjust other TARGET_ options. */
2376 rs6000_option_override_internal (bool global_init_p)
2379 bool have_cpu = false;
2381 /* The default cpu requested at configure time, if any. */
2382 const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
2387 struct cl_target_option *main_target_opt
2388 = ((global_init_p || target_option_default_node == NULL)
2389 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2391 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2392 library functions, so warn about it. The flag may be useful for
2393 performance studies from time to time though, so don't disable it
2395 if (global_options_set.x_rs6000_alignment_flags
2396 && rs6000_alignment_flags == MASK_ALIGN_POWER
2397 && DEFAULT_ABI == ABI_DARWIN
2399 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2400 " it is incompatible with the installed C and C++ libraries");
2402 /* Numerous experiment shows that IRA based loop pressure
2403 calculation works better for RTL loop invariant motion on targets
2404 with enough (>= 32) registers. It is an expensive optimization.
2405 So it is on only for peak performance. */
2406 if (optimize >= 3 && global_init_p)
2407 flag_ira_loop_pressure = 1;
2409 /* Set the pointer size. */
2412 rs6000_pmode = (int)DImode;
2413 rs6000_pointer_size = 64;
2417 rs6000_pmode = (int)SImode;
2418 rs6000_pointer_size = 32;
2421 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
2422 #ifdef OS_MISSING_POWERPC64
2423 if (OS_MISSING_POWERPC64)
2424 set_masks &= ~MASK_POWERPC64;
2426 #ifdef OS_MISSING_ALTIVEC
2427 if (OS_MISSING_ALTIVEC)
2428 set_masks &= ~MASK_ALTIVEC;
2431 /* Don't override by the processor default if given explicitly. */
2432 set_masks &= ~target_flags_explicit;
2434 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2435 the cpu in a target attribute or pragma, but did not specify a tuning
2436 option, use the cpu for the tuning option rather than the option specified
2437 with -mtune on the command line. Process a '--with-cpu' configuration
2438 request as an implicit --cpu. */
2439 if (rs6000_cpu_index >= 0)
2441 cpu_index = rs6000_cpu_index;
2444 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
2446 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2451 const char *default_cpu =
2452 (implicit_cpu ? implicit_cpu
2453 : (TARGET_POWERPC64 ? "powerpc64" : "powerpc"));
2455 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2456 have_cpu = implicit_cpu != 0;
2459 gcc_assert (cpu_index >= 0);
2461 target_flags &= ~set_masks;
2462 target_flags |= (processor_target_table[cpu_index].target_enable
2465 if (rs6000_tune_index >= 0)
2466 tune_index = rs6000_tune_index;
2468 rs6000_tune_index = tune_index = cpu_index;
2472 enum processor_type tune_proc
2473 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
2476 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2477 if (processor_target_table[i].processor == tune_proc)
2479 rs6000_tune_index = tune_index = i;
2484 gcc_assert (tune_index >= 0);
2485 rs6000_cpu = processor_target_table[tune_index].processor;
2487 /* Pick defaults for SPE related control flags. Do this early to make sure
2488 that the TARGET_ macros are representative ASAP. */
2490 int spe_capable_cpu =
2491 (rs6000_cpu == PROCESSOR_PPC8540
2492 || rs6000_cpu == PROCESSOR_PPC8548);
2494 if (!global_options_set.x_rs6000_spe_abi)
2495 rs6000_spe_abi = spe_capable_cpu;
2497 if (!global_options_set.x_rs6000_spe)
2498 rs6000_spe = spe_capable_cpu;
2500 if (!global_options_set.x_rs6000_float_gprs)
2502 (rs6000_cpu == PROCESSOR_PPC8540 ? 1
2503 : rs6000_cpu == PROCESSOR_PPC8548 ? 2
2507 if (global_options_set.x_rs6000_spe_abi
2510 error ("not configured for SPE ABI");
2512 if (global_options_set.x_rs6000_spe
2515 error ("not configured for SPE instruction set");
2517 if (main_target_opt != NULL
2518 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2519 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2520 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2521 error ("target attribute or pragma changes SPE ABI");
2523 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2524 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
2527 error ("AltiVec not supported in this target");
2529 error ("SPE not supported in this target");
2532 /* Disable Cell microcode if we are optimizing for the Cell
2533 and not optimizing for size. */
2534 if (rs6000_gen_cell_microcode == -1)
2535 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2538 /* If we are optimizing big endian systems for space and it's OK to
2539 use instructions that would be microcoded on the Cell, use the
2540 load/store multiple and string instructions. */
2541 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2542 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
2544 /* Don't allow -mmultiple or -mstring on little endian systems
2545 unless the cpu is a 750, because the hardware doesn't support the
2546 instructions used in little endian mode, and causes an alignment
2547 trap. The 750 does not cause an alignment trap (except when the
2548 target is unaligned). */
2550 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2552 if (TARGET_MULTIPLE)
2554 target_flags &= ~MASK_MULTIPLE;
2555 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
2556 warning (0, "-mmultiple is not supported on little endian systems");
2561 target_flags &= ~MASK_STRING;
2562 if ((target_flags_explicit & MASK_STRING) != 0)
2563 warning (0, "-mstring is not supported on little endian systems");
2567 /* Add some warnings for VSX. */
2570 const char *msg = NULL;
2571 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2572 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2574 if (target_flags_explicit & MASK_VSX)
2575 msg = N_("-mvsx requires hardware floating point");
2577 target_flags &= ~ MASK_VSX;
2579 else if (TARGET_PAIRED_FLOAT)
2580 msg = N_("-mvsx and -mpaired are incompatible");
2581 /* The hardware will allow VSX and little endian, but until we make sure
2582 things like vector select, etc. work don't allow VSX on little endian
2583 systems at this point. */
2584 else if (!BYTES_BIG_ENDIAN)
2585 msg = N_("-mvsx used with little endian code");
2586 else if (TARGET_AVOID_XFORM > 0)
2587 msg = N_("-mvsx needs indexed addressing");
2588 else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
2590 if (target_flags_explicit & MASK_VSX)
2591 msg = N_("-mvsx and -mno-altivec are incompatible");
2593 msg = N_("-mno-altivec disables vsx");
2599 target_flags &= ~ MASK_VSX;
2600 target_flags_explicit |= MASK_VSX;
2604 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2605 unless the user explicitly used the -mno-<option> to disable the code. */
2607 target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
2608 else if (TARGET_POPCNTD)
2609 target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
2610 else if (TARGET_DFP)
2611 target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
2612 else if (TARGET_CMPB)
2613 target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
2614 else if (TARGET_FPRND)
2615 target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
2616 else if (TARGET_POPCNTB)
2617 target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
2618 else if (TARGET_ALTIVEC)
2619 target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
2621 /* E500mc does "better" if we inline more aggressively. Respect the
2622 user's opinion, though. */
2623 if (rs6000_block_move_inline_limit == 0
2624 && (rs6000_cpu == PROCESSOR_PPCE500MC
2625 || rs6000_cpu == PROCESSOR_PPCE500MC64))
2626 rs6000_block_move_inline_limit = 128;
2628 /* store_one_arg depends on expand_block_move to handle at least the
2629 size of reg_parm_stack_space. */
2630 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2631 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2635 /* If the appropriate debug option is enabled, replace the target hooks
2636 with debug versions that call the real version and then prints
2637 debugging information. */
2638 if (TARGET_DEBUG_COST)
2640 targetm.rtx_costs = rs6000_debug_rtx_costs;
2641 targetm.address_cost = rs6000_debug_address_cost;
2642 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2645 if (TARGET_DEBUG_ADDR)
2647 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2648 targetm.legitimize_address = rs6000_debug_legitimize_address;
2649 rs6000_secondary_reload_class_ptr
2650 = rs6000_debug_secondary_reload_class;
2651 rs6000_secondary_memory_needed_ptr
2652 = rs6000_debug_secondary_memory_needed;
2653 rs6000_cannot_change_mode_class_ptr
2654 = rs6000_debug_cannot_change_mode_class;
2655 rs6000_preferred_reload_class_ptr
2656 = rs6000_debug_preferred_reload_class;
2657 rs6000_legitimize_reload_address_ptr
2658 = rs6000_debug_legitimize_reload_address;
2659 rs6000_mode_dependent_address_ptr
2660 = rs6000_debug_mode_dependent_address;
2663 if (rs6000_veclibabi_name)
2665 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2666 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2669 error ("unknown vectorization library ABI type (%s) for "
2670 "-mveclibabi= switch", rs6000_veclibabi_name);
2676 if (!global_options_set.x_rs6000_long_double_type_size)
2678 if (main_target_opt != NULL
2679 && (main_target_opt->x_rs6000_long_double_type_size
2680 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2681 error ("target attribute or pragma changes long double size");
2683 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2686 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2687 if (!global_options_set.x_rs6000_ieeequad)
2688 rs6000_ieeequad = 1;
2691 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2692 target attribute or pragma which automatically enables both options,
2693 unless the altivec ABI was set. This is set by default for 64-bit, but
2695 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2696 target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
2698 /* Enable Altivec ABI for AIX -maltivec. */
2699 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2701 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2702 error ("target attribute or pragma changes AltiVec ABI");
2704 rs6000_altivec_abi = 1;
2707 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2708 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2709 be explicitly overridden in either case. */
2712 if (!global_options_set.x_rs6000_altivec_abi
2713 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2715 if (main_target_opt != NULL &&
2716 !main_target_opt->x_rs6000_altivec_abi)
2717 error ("target attribute or pragma changes AltiVec ABI");
2719 rs6000_altivec_abi = 1;
2722 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2723 if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE)
2724 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
2727 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2728 So far, the only darwin64 targets are also MACH-O. */
2730 && DEFAULT_ABI == ABI_DARWIN
2733 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2734 error ("target attribute or pragma changes darwin64 ABI");
2737 rs6000_darwin64_abi = 1;
2738 /* Default to natural alignment, for better performance. */
2739 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2743 /* Place FP constants in the constant pool instead of TOC
2744 if section anchors enabled. */
2745 if (flag_section_anchors)
2746 TARGET_NO_FP_IN_TOC = 1;
2748 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2749 SUBTARGET_OVERRIDE_OPTIONS;
2751 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2752 SUBSUBTARGET_OVERRIDE_OPTIONS;
2754 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2755 SUB3TARGET_OVERRIDE_OPTIONS;
2758 /* For the E500 family of cores, reset the single/double FP flags to let us
2759 check that they remain constant across attributes or pragmas. Also,
2760 clear a possible request for string instructions, not supported and which
2761 we might have silently queried above for -Os.
2763 For other families, clear ISEL in case it was set implicitly.
2768 case PROCESSOR_PPC8540:
2769 case PROCESSOR_PPC8548:
2770 case PROCESSOR_PPCE500MC:
2771 case PROCESSOR_PPCE500MC64:
2773 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
2774 rs6000_double_float = TARGET_E500_DOUBLE;
2776 target_flags &= ~MASK_STRING;
2782 if (have_cpu && !(target_flags_explicit & MASK_ISEL))
2783 target_flags &= ~MASK_ISEL;
2788 if (main_target_opt)
2790 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
2791 error ("target attribute or pragma changes single precision floating "
2793 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
2794 error ("target attribute or pragma changes double precision floating "
2798 /* Detect invalid option combinations with E500. */
2801 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2802 && rs6000_cpu != PROCESSOR_POWER5
2803 && rs6000_cpu != PROCESSOR_POWER6
2804 && rs6000_cpu != PROCESSOR_POWER7
2805 && rs6000_cpu != PROCESSOR_PPCA2
2806 && rs6000_cpu != PROCESSOR_CELL
2807 && rs6000_cpu != PROCESSOR_PPC476);
2808 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2809 || rs6000_cpu == PROCESSOR_POWER5
2810 || rs6000_cpu == PROCESSOR_POWER7);
2811 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2812 || rs6000_cpu == PROCESSOR_POWER5
2813 || rs6000_cpu == PROCESSOR_POWER6
2814 || rs6000_cpu == PROCESSOR_POWER7
2815 || rs6000_cpu == PROCESSOR_PPCE500MC
2816 || rs6000_cpu == PROCESSOR_PPCE500MC64);
2818 /* Allow debug switches to override the above settings. These are set to -1
2819 in rs6000.opt to indicate the user hasn't directly set the switch. */
2820 if (TARGET_ALWAYS_HINT >= 0)
2821 rs6000_always_hint = TARGET_ALWAYS_HINT;
2823 if (TARGET_SCHED_GROUPS >= 0)
2824 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2826 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2827 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2829 rs6000_sched_restricted_insns_priority
2830 = (rs6000_sched_groups ? 1 : 0);
2832 /* Handle -msched-costly-dep option. */
2833 rs6000_sched_costly_dep
2834 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
2836 if (rs6000_sched_costly_dep_str)
2838 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2839 rs6000_sched_costly_dep = no_dep_costly;
2840 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2841 rs6000_sched_costly_dep = all_deps_costly;
2842 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2843 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2844 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2845 rs6000_sched_costly_dep = store_to_load_dep_costly;
2847 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2848 atoi (rs6000_sched_costly_dep_str));
2851 /* Handle -minsert-sched-nops option. */
2852 rs6000_sched_insert_nops
2853 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2855 if (rs6000_sched_insert_nops_str)
2857 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2858 rs6000_sched_insert_nops = sched_finish_none;
2859 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
2860 rs6000_sched_insert_nops = sched_finish_pad_groups;
2861 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
2862 rs6000_sched_insert_nops = sched_finish_regroup_exact;
2864 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
2865 atoi (rs6000_sched_insert_nops_str));
2870 #ifdef TARGET_REGNAMES
2871 /* If the user desires alternate register names, copy in the
2872 alternate names now. */
2873 if (TARGET_REGNAMES)
2874 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
2877 /* Set aix_struct_return last, after the ABI is determined.
2878 If -maix-struct-return or -msvr4-struct-return was explicitly
2879 used, don't override with the ABI default. */
2880 if (!global_options_set.x_aix_struct_return)
2881 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
2884 /* IBM XL compiler defaults to unsigned bitfields. */
2885 if (TARGET_XL_COMPAT)
2886 flag_signed_bitfields = 0;
2889 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
2890 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
2893 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
2895 /* We can only guarantee the availability of DI pseudo-ops when
2896 assembling for 64-bit targets. */
2899 targetm.asm_out.aligned_op.di = NULL;
2900 targetm.asm_out.unaligned_op.di = NULL;
2904 /* Set branch target alignment, if not optimizing for size. */
2907 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
2908 aligned 8byte to avoid misprediction by the branch predictor. */
2909 if (rs6000_cpu == PROCESSOR_TITAN
2910 || rs6000_cpu == PROCESSOR_CELL)
2912 if (align_functions <= 0)
2913 align_functions = 8;
2914 if (align_jumps <= 0)
2916 if (align_loops <= 0)
2919 if (rs6000_align_branch_targets)
2921 if (align_functions <= 0)
2922 align_functions = 16;
2923 if (align_jumps <= 0)
2925 if (align_loops <= 0)
2927 can_override_loop_align = 1;
2931 if (align_jumps_max_skip <= 0)
2932 align_jumps_max_skip = 15;
2933 if (align_loops_max_skip <= 0)
2934 align_loops_max_skip = 15;
2937 /* Arrange to save and restore machine status around nested functions. */
2938 init_machine_status = rs6000_init_machine_status;
2940 /* We should always be splitting complex arguments, but we can't break
2941 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
2942 if (DEFAULT_ABI != ABI_AIX)
2943 targetm.calls.split_complex_arg = NULL;
2946 /* Initialize rs6000_cost with the appropriate target costs. */
2948 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
2952 case PROCESSOR_RIOS1:
2953 rs6000_cost = &rios1_cost;
2956 case PROCESSOR_RIOS2:
2957 rs6000_cost = &rios2_cost;
2960 case PROCESSOR_RS64A:
2961 rs6000_cost = &rs64a_cost;
2964 case PROCESSOR_MPCCORE:
2965 rs6000_cost = &mpccore_cost;
2968 case PROCESSOR_PPC403:
2969 rs6000_cost = &ppc403_cost;
2972 case PROCESSOR_PPC405:
2973 rs6000_cost = &ppc405_cost;
2976 case PROCESSOR_PPC440:
2977 rs6000_cost = &ppc440_cost;
2980 case PROCESSOR_PPC476:
2981 rs6000_cost = &ppc476_cost;
2984 case PROCESSOR_PPC601:
2985 rs6000_cost = &ppc601_cost;
2988 case PROCESSOR_PPC603:
2989 rs6000_cost = &ppc603_cost;
2992 case PROCESSOR_PPC604:
2993 rs6000_cost = &ppc604_cost;
2996 case PROCESSOR_PPC604e:
2997 rs6000_cost = &ppc604e_cost;
3000 case PROCESSOR_PPC620:
3001 rs6000_cost = &ppc620_cost;
3004 case PROCESSOR_PPC630:
3005 rs6000_cost = &ppc630_cost;
3008 case PROCESSOR_CELL:
3009 rs6000_cost = &ppccell_cost;
3012 case PROCESSOR_PPC750:
3013 case PROCESSOR_PPC7400:
3014 rs6000_cost = &ppc750_cost;
3017 case PROCESSOR_PPC7450:
3018 rs6000_cost = &ppc7450_cost;
3021 case PROCESSOR_PPC8540:
3022 case PROCESSOR_PPC8548:
3023 rs6000_cost = &ppc8540_cost;
3026 case PROCESSOR_PPCE300C2:
3027 case PROCESSOR_PPCE300C3:
3028 rs6000_cost = &ppce300c2c3_cost;
3031 case PROCESSOR_PPCE500MC:
3032 rs6000_cost = &ppce500mc_cost;
3035 case PROCESSOR_PPCE500MC64:
3036 rs6000_cost = &ppce500mc64_cost;
3039 case PROCESSOR_TITAN:
3040 rs6000_cost = &titan_cost;
3043 case PROCESSOR_POWER4:
3044 case PROCESSOR_POWER5:
3045 rs6000_cost = &power4_cost;
3048 case PROCESSOR_POWER6:
3049 rs6000_cost = &power6_cost;
3052 case PROCESSOR_POWER7:
3053 rs6000_cost = &power7_cost;
3056 case PROCESSOR_PPCA2:
3057 rs6000_cost = &ppca2_cost;
3066 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3067 rs6000_cost->simultaneous_prefetches,
3068 global_options.x_param_values,
3069 global_options_set.x_param_values);
3070 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3071 global_options.x_param_values,
3072 global_options_set.x_param_values);
3073 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3074 rs6000_cost->cache_line_size,
3075 global_options.x_param_values,
3076 global_options_set.x_param_values);
3077 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3078 global_options.x_param_values,
3079 global_options_set.x_param_values);
3081 /* If using typedef char *va_list, signal that
3082 __builtin_va_start (&ap, 0) can be optimized to
3083 ap = __builtin_next_arg (0). */
3084 if (DEFAULT_ABI != ABI_V4)
3085 targetm.expand_builtin_va_start = NULL;
3088 /* Set up single/double float flags.
3089 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3090 then set both flags. */
3091 if (TARGET_HARD_FLOAT && TARGET_FPRS
3092 && rs6000_single_float == 0 && rs6000_double_float == 0)
3093 rs6000_single_float = rs6000_double_float = 1;
3095 /* If not explicitly specified via option, decide whether to generate indexed
3096 load/store instructions. */
3097 if (TARGET_AVOID_XFORM == -1)
3098 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3099 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3100 need indexed accesses and the type used is the scalar type of the element
3101 being loaded or stored. */
3102 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3103 && !TARGET_ALTIVEC);
3105 /* Set the -mrecip options. */
3106 if (rs6000_recip_name)
3108 char *p = ASTRDUP (rs6000_recip_name);
3110 unsigned int mask, i;
3113 while ((q = strtok (p, ",")) != NULL)
3124 if (!strcmp (q, "default"))
3125 mask = ((TARGET_RECIP_PRECISION)
3126 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3129 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3130 if (!strcmp (q, recip_options[i].string))
3132 mask = recip_options[i].mask;
3136 if (i == ARRAY_SIZE (recip_options))
3138 error ("unknown option for -mrecip=%s", q);
3146 rs6000_recip_control &= ~mask;
3148 rs6000_recip_control |= mask;
3152 /* Set the builtin mask of the various options used that could affect which
3153 builtins were used. In the past we used target_flags, but we've run out
3154 of bits, and some options like SPE and PAIRED are no longer in
3156 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3157 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3158 fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
3159 (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
3160 (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "",
3161 (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "",
3162 (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : "");
3164 /* Initialize all of the registers. */
3165 rs6000_init_hard_regno_mode_ok (global_init_p);
3167 /* Save the initial options in case the user does function specific options */
3169 target_option_default_node = target_option_current_node
3170 = build_target_option_node ();
3172 /* If not explicitly specified via option, decide whether to generate the
3173 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3174 if (TARGET_LINK_STACK == -1)
3175 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3180 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3181 define the target cpu type. */
3184 rs6000_option_override (void)
3186 (void) rs6000_option_override_internal (true);
3190 /* Implement targetm.vectorize.builtin_mask_for_load. */
3192 rs6000_builtin_mask_for_load (void)
3194 if (TARGET_ALTIVEC || TARGET_VSX)
3195 return altivec_builtin_mask_for_load;
3200 /* Implement LOOP_ALIGN. */
3202 rs6000_loop_align (rtx label)
3207 /* Don't override loop alignment if -falign-loops was specified. */
3208 if (!can_override_loop_align)
3209 return align_loops_log;
3211 bb = BLOCK_FOR_INSN (label);
3212 ninsns = num_loop_insns(bb->loop_father);
3214 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3215 if (ninsns > 4 && ninsns <= 8
3216 && (rs6000_cpu == PROCESSOR_POWER4
3217 || rs6000_cpu == PROCESSOR_POWER5
3218 || rs6000_cpu == PROCESSOR_POWER6
3219 || rs6000_cpu == PROCESSOR_POWER7))
3222 return align_loops_log;
3225 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3227 rs6000_loop_align_max_skip (rtx label)
3229 return (1 << rs6000_loop_align (label)) - 1;
3232 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3234 rs6000_builtin_mul_widen_even (tree type)
3236 if (!TARGET_ALTIVEC)
3239 switch (TYPE_MODE (type))
3242 return TYPE_UNSIGNED (type)
3243 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
3244 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
3247 return TYPE_UNSIGNED (type)
3248 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
3249 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
3255 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3257 rs6000_builtin_mul_widen_odd (tree type)
3259 if (!TARGET_ALTIVEC)
3262 switch (TYPE_MODE (type))
3265 return TYPE_UNSIGNED (type)
3266 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
3267 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
3270 return TYPE_UNSIGNED (type)
3271 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
3272 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
3279 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3280 after applying N number of iterations. This routine does not determine
3281 how may iterations are required to reach desired alignment. */
3284 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3291 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3294 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3304 /* Assuming that all other types are naturally aligned. CHECKME! */
3309 /* Return true if the vector misalignment factor is supported by the
3312 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3319 /* Return if movmisalign pattern is not supported for this mode. */
3320 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3323 if (misalignment == -1)
3325 /* Misalignment factor is unknown at compile time but we know
3326 it's word aligned. */
3327 if (rs6000_vector_alignment_reachable (type, is_packed))
3329 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3331 if (element_size == 64 || element_size == 32)
3338 /* VSX supports word-aligned vector. */
3339 if (misalignment % 4 == 0)
3345 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3347 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3348 tree vectype, int misalign)
3352 switch (type_of_cost)
3362 case cond_branch_not_taken:
3371 case vec_promote_demote:
3377 case cond_branch_taken:
3380 case unaligned_load:
3381 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3383 elements = TYPE_VECTOR_SUBPARTS (vectype);
3385 /* Double word aligned. */
3393 /* Double word aligned. */
3397 /* Unknown misalignment. */
3410 /* Misaligned loads are not supported. */
3415 case unaligned_store:
3416 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3418 elements = TYPE_VECTOR_SUBPARTS (vectype);
3420 /* Double word aligned. */
3428 /* Double word aligned. */
3432 /* Unknown misalignment. */
3445 /* Misaligned stores are not supported. */
3455 /* Implement targetm.vectorize.preferred_simd_mode. */
3457 static enum machine_mode
3458 rs6000_preferred_simd_mode (enum machine_mode mode)
3467 if (TARGET_ALTIVEC || TARGET_VSX)
3491 if (TARGET_PAIRED_FLOAT
3497 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3498 library with vectorized intrinsics. */
3501 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3504 const char *suffix = NULL;
3505 tree fntype, new_fndecl, bdecl = NULL_TREE;
3508 enum machine_mode el_mode, in_mode;
3511 /* Libmass is suitable for unsafe math only as it does not correctly support
3512 parts of IEEE with the required precision such as denormals. Only support
3513 it if we have VSX to use the simd d2 or f4 functions.
3514 XXX: Add variable length support. */
3515 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3518 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3519 n = TYPE_VECTOR_SUBPARTS (type_out);
3520 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3521 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3522 if (el_mode != in_mode
3526 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3528 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3531 case BUILT_IN_ATAN2:
3532 case BUILT_IN_HYPOT:
3538 case BUILT_IN_ACOSH:
3540 case BUILT_IN_ASINH:
3542 case BUILT_IN_ATANH:
3550 case BUILT_IN_EXPM1:
3551 case BUILT_IN_LGAMMA:
3552 case BUILT_IN_LOG10:
3553 case BUILT_IN_LOG1P:
3561 bdecl = builtin_decl_implicit (fn);
3562 suffix = "d2"; /* pow -> powd2 */
3563 if (el_mode != DFmode
3568 case BUILT_IN_ATAN2F:
3569 case BUILT_IN_HYPOTF:
3574 case BUILT_IN_ACOSF:
3575 case BUILT_IN_ACOSHF:
3576 case BUILT_IN_ASINF:
3577 case BUILT_IN_ASINHF:
3578 case BUILT_IN_ATANF:
3579 case BUILT_IN_ATANHF:
3580 case BUILT_IN_CBRTF:
3582 case BUILT_IN_COSHF:
3584 case BUILT_IN_ERFCF:
3585 case BUILT_IN_EXP2F:
3587 case BUILT_IN_EXPM1F:
3588 case BUILT_IN_LGAMMAF:
3589 case BUILT_IN_LOG10F:
3590 case BUILT_IN_LOG1PF:
3591 case BUILT_IN_LOG2F:
3594 case BUILT_IN_SINHF:
3595 case BUILT_IN_SQRTF:
3597 case BUILT_IN_TANHF:
3598 bdecl = builtin_decl_implicit (fn);
3599 suffix = "4"; /* powf -> powf4 */
3600 if (el_mode != SFmode
3612 gcc_assert (suffix != NULL);
3613 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3614 strcpy (name, bname + sizeof ("__builtin_") - 1);
3615 strcat (name, suffix);
3618 fntype = build_function_type_list (type_out, type_in, NULL);
3619 else if (n_args == 2)
3620 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3624 /* Build a function declaration for the vectorized function. */
3625 new_fndecl = build_decl (BUILTINS_LOCATION,
3626 FUNCTION_DECL, get_identifier (name), fntype);
3627 TREE_PUBLIC (new_fndecl) = 1;
3628 DECL_EXTERNAL (new_fndecl) = 1;
3629 DECL_IS_NOVOPS (new_fndecl) = 1;
3630 TREE_READONLY (new_fndecl) = 1;
3635 /* Returns a function decl for a vectorized version of the builtin function
3636 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3637 if it is not available. */
3640 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3643 enum machine_mode in_mode, out_mode;
3646 if (TARGET_DEBUG_BUILTIN)
3647 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3648 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3649 GET_MODE_NAME (TYPE_MODE (type_out)),
3650 GET_MODE_NAME (TYPE_MODE (type_in)));
3652 if (TREE_CODE (type_out) != VECTOR_TYPE
3653 || TREE_CODE (type_in) != VECTOR_TYPE
3654 || !TARGET_VECTORIZE_BUILTINS)
3657 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3658 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3659 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3660 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3662 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3664 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3667 case BUILT_IN_COPYSIGN:
3668 if (VECTOR_UNIT_VSX_P (V2DFmode)
3669 && out_mode == DFmode && out_n == 2
3670 && in_mode == DFmode && in_n == 2)
3671 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3673 case BUILT_IN_COPYSIGNF:
3674 if (out_mode != SFmode || out_n != 4
3675 || in_mode != SFmode || in_n != 4)
3677 if (VECTOR_UNIT_VSX_P (V4SFmode))
3678 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3679 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3680 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3683 if (VECTOR_UNIT_VSX_P (V2DFmode)
3684 && out_mode == DFmode && out_n == 2
3685 && in_mode == DFmode && in_n == 2)
3686 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3688 case BUILT_IN_SQRTF:
3689 if (VECTOR_UNIT_VSX_P (V4SFmode)
3690 && out_mode == SFmode && out_n == 4
3691 && in_mode == SFmode && in_n == 4)
3692 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3695 if (VECTOR_UNIT_VSX_P (V2DFmode)
3696 && out_mode == DFmode && out_n == 2
3697 && in_mode == DFmode && in_n == 2)
3698 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3700 case BUILT_IN_CEILF:
3701 if (out_mode != SFmode || out_n != 4
3702 || in_mode != SFmode || in_n != 4)
3704 if (VECTOR_UNIT_VSX_P (V4SFmode))
3705 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3706 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3707 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3709 case BUILT_IN_FLOOR:
3710 if (VECTOR_UNIT_VSX_P (V2DFmode)
3711 && out_mode == DFmode && out_n == 2
3712 && in_mode == DFmode && in_n == 2)
3713 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3715 case BUILT_IN_FLOORF:
3716 if (out_mode != SFmode || out_n != 4
3717 || in_mode != SFmode || in_n != 4)
3719 if (VECTOR_UNIT_VSX_P (V4SFmode))
3720 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3721 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3722 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3725 if (VECTOR_UNIT_VSX_P (V2DFmode)
3726 && out_mode == DFmode && out_n == 2
3727 && in_mode == DFmode && in_n == 2)
3728 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3731 if (VECTOR_UNIT_VSX_P (V4SFmode)
3732 && out_mode == SFmode && out_n == 4
3733 && in_mode == SFmode && in_n == 4)
3734 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3735 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3736 && out_mode == SFmode && out_n == 4
3737 && in_mode == SFmode && in_n == 4)
3738 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3740 case BUILT_IN_TRUNC:
3741 if (VECTOR_UNIT_VSX_P (V2DFmode)
3742 && out_mode == DFmode && out_n == 2
3743 && in_mode == DFmode && in_n == 2)
3744 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3746 case BUILT_IN_TRUNCF:
3747 if (out_mode != SFmode || out_n != 4
3748 || in_mode != SFmode || in_n != 4)
3750 if (VECTOR_UNIT_VSX_P (V4SFmode))
3751 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3752 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3753 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3755 case BUILT_IN_NEARBYINT:
3756 if (VECTOR_UNIT_VSX_P (V2DFmode)
3757 && flag_unsafe_math_optimizations
3758 && out_mode == DFmode && out_n == 2
3759 && in_mode == DFmode && in_n == 2)
3760 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3762 case BUILT_IN_NEARBYINTF:
3763 if (VECTOR_UNIT_VSX_P (V4SFmode)
3764 && flag_unsafe_math_optimizations
3765 && out_mode == SFmode && out_n == 4
3766 && in_mode == SFmode && in_n == 4)
3767 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3770 if (VECTOR_UNIT_VSX_P (V2DFmode)
3771 && !flag_trapping_math
3772 && out_mode == DFmode && out_n == 2
3773 && in_mode == DFmode && in_n == 2)
3774 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3776 case BUILT_IN_RINTF:
3777 if (VECTOR_UNIT_VSX_P (V4SFmode)
3778 && !flag_trapping_math
3779 && out_mode == SFmode && out_n == 4
3780 && in_mode == SFmode && in_n == 4)
3781 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3788 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3790 enum rs6000_builtins fn
3791 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3794 case RS6000_BUILTIN_RSQRTF:
3795 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3796 && out_mode == SFmode && out_n == 4
3797 && in_mode == SFmode && in_n == 4)
3798 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3800 case RS6000_BUILTIN_RSQRT:
3801 if (VECTOR_UNIT_VSX_P (V2DFmode)
3802 && out_mode == DFmode && out_n == 2
3803 && in_mode == DFmode && in_n == 2)
3804 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3806 case RS6000_BUILTIN_RECIPF:
3807 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3808 && out_mode == SFmode && out_n == 4
3809 && in_mode == SFmode && in_n == 4)
3810 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3812 case RS6000_BUILTIN_RECIP:
3813 if (VECTOR_UNIT_VSX_P (V2DFmode)
3814 && out_mode == DFmode && out_n == 2
3815 && in_mode == DFmode && in_n == 2)
3816 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3823 /* Generate calls to libmass if appropriate. */
3824 if (rs6000_veclib_handler)
3825 return rs6000_veclib_handler (fndecl, type_out, type_in);
3830 /* Default CPU string for rs6000*_file_start functions. */
3831 static const char *rs6000_default_cpu;
3833 /* Do anything needed at the start of the asm file. */
3836 rs6000_file_start (void)
3839 const char *start = buffer;
3840 FILE *file = asm_out_file;
3842 rs6000_default_cpu = TARGET_CPU_DEFAULT;
3844 default_file_start ();
3846 if (flag_verbose_asm)
3848 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
3850 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
3852 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
3856 if (global_options_set.x_rs6000_cpu_index)
3858 fprintf (file, "%s -mcpu=%s", start,
3859 processor_target_table[rs6000_cpu_index].name);
3863 if (global_options_set.x_rs6000_tune_index)
3865 fprintf (file, "%s -mtune=%s", start,
3866 processor_target_table[rs6000_tune_index].name);
3870 if (PPC405_ERRATUM77)
3872 fprintf (file, "%s PPC405CR_ERRATUM77", start);
3876 #ifdef USING_ELFOS_H
3877 switch (rs6000_sdata)
3879 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
3880 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
3881 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
3882 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
3885 if (rs6000_sdata && g_switch_value)
3887 fprintf (file, "%s -G %d", start,
3897 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
3899 switch_to_section (toc_section);
3900 switch_to_section (text_section);
3905 /* Return nonzero if this function is known to have a null epilogue. */
3908 direct_return (void)
3910 if (reload_completed)
3912 rs6000_stack_t *info = rs6000_stack_info ();
3914 if (info->first_gp_reg_save == 32
3915 && info->first_fp_reg_save == 64
3916 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
3917 && ! info->lr_save_p
3918 && ! info->cr_save_p
3919 && info->vrsave_mask == 0
3927 /* Return the number of instructions it takes to form a constant in an
3928 integer register. */
3931 num_insns_constant_wide (HOST_WIDE_INT value)
3933 /* signed constant loadable with {cal|addi} */
3934 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
3937 /* constant loadable with {cau|addis} */
3938 else if ((value & 0xffff) == 0
3939 && (value >> 31 == -1 || value >> 31 == 0))
3942 #if HOST_BITS_PER_WIDE_INT == 64
3943 else if (TARGET_POWERPC64)
3945 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
3946 HOST_WIDE_INT high = value >> 31;
3948 if (high == 0 || high == -1)
3954 return num_insns_constant_wide (high) + 1;
3956 return num_insns_constant_wide (low) + 1;
3958 return (num_insns_constant_wide (high)
3959 + num_insns_constant_wide (low) + 1);
3968 num_insns_constant (rtx op, enum machine_mode mode)
3970 HOST_WIDE_INT low, high;
3972 switch (GET_CODE (op))
3975 #if HOST_BITS_PER_WIDE_INT == 64
3976 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
3977 && mask64_operand (op, mode))
3981 return num_insns_constant_wide (INTVAL (op));
3984 if (mode == SFmode || mode == SDmode)
3989 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3990 if (DECIMAL_FLOAT_MODE_P (mode))
3991 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
3993 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3994 return num_insns_constant_wide ((HOST_WIDE_INT) l);
3997 if (mode == VOIDmode || mode == DImode)
3999 high = CONST_DOUBLE_HIGH (op);
4000 low = CONST_DOUBLE_LOW (op);
4007 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4008 if (DECIMAL_FLOAT_MODE_P (mode))
4009 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4011 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4012 high = l[WORDS_BIG_ENDIAN == 0];
4013 low = l[WORDS_BIG_ENDIAN != 0];
4017 return (num_insns_constant_wide (low)
4018 + num_insns_constant_wide (high));
4021 if ((high == 0 && low >= 0)
4022 || (high == -1 && low < 0))
4023 return num_insns_constant_wide (low);
4025 else if (mask64_operand (op, mode))
4029 return num_insns_constant_wide (high) + 1;
4032 return (num_insns_constant_wide (high)
4033 + num_insns_constant_wide (low) + 1);
4041 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4042 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4043 corresponding element of the vector, but for V4SFmode and V2SFmode,
4044 the corresponding "float" is interpreted as an SImode integer. */
4047 const_vector_elt_as_int (rtx op, unsigned int elt)
4051 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4052 gcc_assert (GET_MODE (op) != V2DImode
4053 && GET_MODE (op) != V2DFmode);
4055 tmp = CONST_VECTOR_ELT (op, elt);
4056 if (GET_MODE (op) == V4SFmode
4057 || GET_MODE (op) == V2SFmode)
4058 tmp = gen_lowpart (SImode, tmp);
4059 return INTVAL (tmp);
4062 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4063 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4064 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4065 all items are set to the same value and contain COPIES replicas of the
4066 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4067 operand and the others are set to the value of the operand's msb. */
4070 vspltis_constant (rtx op, unsigned step, unsigned copies)
4072 enum machine_mode mode = GET_MODE (op);
4073 enum machine_mode inner = GET_MODE_INNER (mode);
4081 HOST_WIDE_INT splat_val;
4082 HOST_WIDE_INT msb_val;
4084 if (mode == V2DImode || mode == V2DFmode)
4087 nunits = GET_MODE_NUNITS (mode);
4088 bitsize = GET_MODE_BITSIZE (inner);
4089 mask = GET_MODE_MASK (inner);
4091 val = const_vector_elt_as_int (op, nunits - 1);
4093 msb_val = val > 0 ? 0 : -1;
4095 /* Construct the value to be splatted, if possible. If not, return 0. */
4096 for (i = 2; i <= copies; i *= 2)
4098 HOST_WIDE_INT small_val;
4100 small_val = splat_val >> bitsize;
4102 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4104 splat_val = small_val;
4107 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4108 if (EASY_VECTOR_15 (splat_val))
4111 /* Also check if we can splat, and then add the result to itself. Do so if
4112 the value is positive, of if the splat instruction is using OP's mode;
4113 for splat_val < 0, the splat and the add should use the same mode. */
4114 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4115 && (splat_val >= 0 || (step == 1 && copies == 1)))
4118 /* Also check if are loading up the most significant bit which can be done by
4119 loading up -1 and shifting the value left by -1. */
4120 else if (EASY_VECTOR_MSB (splat_val, inner))
4126 /* Check if VAL is present in every STEP-th element, and the
4127 other elements are filled with its most significant bit. */
4128 for (i = 0; i < nunits - 1; ++i)
4130 HOST_WIDE_INT desired_val;
4131 if (((i + 1) & (step - 1)) == 0)
4134 desired_val = msb_val;
4136 if (desired_val != const_vector_elt_as_int (op, i))
4144 /* Return true if OP is of the given MODE and can be synthesized
4145 with a vspltisb, vspltish or vspltisw. */
4148 easy_altivec_constant (rtx op, enum machine_mode mode)
4150 unsigned step, copies;
4152 if (mode == VOIDmode)
4153 mode = GET_MODE (op);
4154 else if (mode != GET_MODE (op))
4157 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4159 if (mode == V2DFmode)
4160 return zero_constant (op, mode);
4162 if (mode == V2DImode)
4164 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4166 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4167 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4170 if (zero_constant (op, mode))
4173 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4174 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4180 /* Start with a vspltisw. */
4181 step = GET_MODE_NUNITS (mode) / 4;
4184 if (vspltis_constant (op, step, copies))
4187 /* Then try with a vspltish. */
4193 if (vspltis_constant (op, step, copies))
4196 /* And finally a vspltisb. */
4202 if (vspltis_constant (op, step, copies))
4208 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4209 result is OP. Abort if it is not possible. */
4212 gen_easy_altivec_constant (rtx op)
4214 enum machine_mode mode = GET_MODE (op);
4215 int nunits = GET_MODE_NUNITS (mode);
4216 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4217 unsigned step = nunits / 4;
4218 unsigned copies = 1;
4220 /* Start with a vspltisw. */
4221 if (vspltis_constant (op, step, copies))
4222 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4224 /* Then try with a vspltish. */
4230 if (vspltis_constant (op, step, copies))
4231 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4233 /* And finally a vspltisb. */
4239 if (vspltis_constant (op, step, copies))
4240 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4246 output_vec_const_move (rtx *operands)
4249 enum machine_mode mode;
4254 mode = GET_MODE (dest);
4258 if (zero_constant (vec, mode))
4259 return "xxlxor %x0,%x0,%x0";
4261 if (mode == V2DImode
4262 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4263 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4264 return "vspltisw %0,-1";
4270 if (zero_constant (vec, mode))
4271 return "vxor %0,%0,%0";
4273 splat_vec = gen_easy_altivec_constant (vec);
4274 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4275 operands[1] = XEXP (splat_vec, 0);
4276 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4279 switch (GET_MODE (splat_vec))
4282 return "vspltisw %0,%1";
4285 return "vspltish %0,%1";
4288 return "vspltisb %0,%1";
4295 gcc_assert (TARGET_SPE);
4297 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4298 pattern of V1DI, V4HI, and V2SF.
4300 FIXME: We should probably return # and add post reload
4301 splitters for these, but this way is so easy ;-). */
4302 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4303 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4304 operands[1] = CONST_VECTOR_ELT (vec, 0);
4305 operands[2] = CONST_VECTOR_ELT (vec, 1);
4307 return "li %0,%1\n\tevmergelo %0,%0,%0";
4309 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4312 /* Initialize TARGET of vector PAIRED to VALS. */
4315 paired_expand_vector_init (rtx target, rtx vals)
4317 enum machine_mode mode = GET_MODE (target);
4318 int n_elts = GET_MODE_NUNITS (mode);
4320 rtx x, new_rtx, tmp, constant_op, op1, op2;
4323 for (i = 0; i < n_elts; ++i)
4325 x = XVECEXP (vals, 0, i);
4326 if (!(CONST_INT_P (x)
4327 || GET_CODE (x) == CONST_DOUBLE
4328 || GET_CODE (x) == CONST_FIXED))
4333 /* Load from constant pool. */
4334 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4340 /* The vector is initialized only with non-constants. */
4341 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4342 XVECEXP (vals, 0, 1));
4344 emit_move_insn (target, new_rtx);
4348 /* One field is non-constant and the other one is a constant. Load the
4349 constant from the constant pool and use ps_merge instruction to
4350 construct the whole vector. */
4351 op1 = XVECEXP (vals, 0, 0);
4352 op2 = XVECEXP (vals, 0, 1);
4354 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4356 tmp = gen_reg_rtx (GET_MODE (constant_op));
4357 emit_move_insn (tmp, constant_op);
4359 if (CONSTANT_P (op1))
4360 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4362 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4364 emit_move_insn (target, new_rtx);
4368 paired_expand_vector_move (rtx operands[])
4370 rtx op0 = operands[0], op1 = operands[1];
4372 emit_move_insn (op0, op1);
4375 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4376 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4377 operands for the relation operation COND. This is a recursive
4381 paired_emit_vector_compare (enum rtx_code rcode,
4382 rtx dest, rtx op0, rtx op1,
4383 rtx cc_op0, rtx cc_op1)
4385 rtx tmp = gen_reg_rtx (V2SFmode);
4388 gcc_assert (TARGET_PAIRED_FLOAT);
4389 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4395 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4399 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4400 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4404 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4407 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4410 tmp1 = gen_reg_rtx (V2SFmode);
4411 max = gen_reg_rtx (V2SFmode);
4412 min = gen_reg_rtx (V2SFmode);
4413 gen_reg_rtx (V2SFmode);
4415 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4416 emit_insn (gen_selv2sf4
4417 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4418 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4419 emit_insn (gen_selv2sf4
4420 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4421 emit_insn (gen_subv2sf3 (tmp1, min, max));
4422 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4425 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4428 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4431 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4434 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4437 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4446 /* Emit vector conditional expression.
4447 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4448 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4451 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4452 rtx cond, rtx cc_op0, rtx cc_op1)
4454 enum rtx_code rcode = GET_CODE (cond);
4456 if (!TARGET_PAIRED_FLOAT)
4459 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4464 /* Initialize vector TARGET to VALS. */
4467 rs6000_expand_vector_init (rtx target, rtx vals)
4469 enum machine_mode mode = GET_MODE (target);
4470 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4471 int n_elts = GET_MODE_NUNITS (mode);
4472 int n_var = 0, one_var = -1;
4473 bool all_same = true, all_const_zero = true;
4477 for (i = 0; i < n_elts; ++i)
4479 x = XVECEXP (vals, 0, i);
4480 if (!(CONST_INT_P (x)
4481 || GET_CODE (x) == CONST_DOUBLE
4482 || GET_CODE (x) == CONST_FIXED))
4483 ++n_var, one_var = i;
4484 else if (x != CONST0_RTX (inner_mode))
4485 all_const_zero = false;
4487 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4493 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4494 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4495 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4497 /* Zero register. */
4498 emit_insn (gen_rtx_SET (VOIDmode, target,
4499 gen_rtx_XOR (mode, target, target)));
4502 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4504 /* Splat immediate. */
4505 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4510 /* Load from constant pool. */
4511 emit_move_insn (target, const_vec);
4516 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4517 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4519 rtx op0 = XVECEXP (vals, 0, 0);
4520 rtx op1 = XVECEXP (vals, 0, 1);
4523 if (!MEM_P (op0) && !REG_P (op0))
4524 op0 = force_reg (inner_mode, op0);
4525 if (mode == V2DFmode)
4526 emit_insn (gen_vsx_splat_v2df (target, op0));
4528 emit_insn (gen_vsx_splat_v2di (target, op0));
4532 op0 = force_reg (inner_mode, op0);
4533 op1 = force_reg (inner_mode, op1);
4534 if (mode == V2DFmode)
4535 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4537 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4542 /* With single precision floating point on VSX, know that internally single
4543 precision is actually represented as a double, and either make 2 V2DF
4544 vectors, and convert these vectors to single precision, or do one
4545 conversion, and splat the result to the other elements. */
4546 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4550 rtx freg = gen_reg_rtx (V4SFmode);
4551 rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
4553 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4554 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4558 rtx dbl_even = gen_reg_rtx (V2DFmode);
4559 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4560 rtx flt_even = gen_reg_rtx (V4SFmode);
4561 rtx flt_odd = gen_reg_rtx (V4SFmode);
4562 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
4563 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
4564 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
4565 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
4567 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
4568 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
4569 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4570 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4571 rs6000_expand_extract_even (target, flt_even, flt_odd);
4576 /* Store value to stack temp. Load vector element. Splat. However, splat
4577 of 64-bit items is not supported on Altivec. */
4578 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4580 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4581 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4582 XVECEXP (vals, 0, 0));
4583 x = gen_rtx_UNSPEC (VOIDmode,
4584 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4585 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4587 gen_rtx_SET (VOIDmode,
4590 x = gen_rtx_VEC_SELECT (inner_mode, target,
4591 gen_rtx_PARALLEL (VOIDmode,
4592 gen_rtvec (1, const0_rtx)));
4593 emit_insn (gen_rtx_SET (VOIDmode, target,
4594 gen_rtx_VEC_DUPLICATE (mode, x)));
4598 /* One field is non-constant. Load constant then overwrite
4602 rtx copy = copy_rtx (vals);
4604 /* Load constant part of vector, substitute neighboring value for
4606 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4607 rs6000_expand_vector_init (target, copy);
4609 /* Insert variable. */
4610 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4614 /* Construct the vector in memory one field at a time
4615 and load the whole vector. */
4616 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4617 for (i = 0; i < n_elts; i++)
4618 emit_move_insn (adjust_address_nv (mem, inner_mode,
4619 i * GET_MODE_SIZE (inner_mode)),
4620 XVECEXP (vals, 0, i));
4621 emit_move_insn (target, mem);
4624 /* Set field ELT of TARGET to VAL. */
4627 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4629 enum machine_mode mode = GET_MODE (target);
4630 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4631 rtx reg = gen_reg_rtx (mode);
4633 int width = GET_MODE_SIZE (inner_mode);
4636 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4638 rtx (*set_func) (rtx, rtx, rtx, rtx)
4639 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4640 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4644 /* Load single variable value. */
4645 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4646 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4647 x = gen_rtx_UNSPEC (VOIDmode,
4648 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4649 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4651 gen_rtx_SET (VOIDmode,
4655 /* Linear sequence. */
4656 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4657 for (i = 0; i < 16; ++i)
4658 XVECEXP (mask, 0, i) = GEN_INT (i);
4660 /* Set permute mask to insert element into target. */
4661 for (i = 0; i < width; ++i)
4662 XVECEXP (mask, 0, elt*width + i)
4663 = GEN_INT (i + 0x10);
4664 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4665 x = gen_rtx_UNSPEC (mode,
4666 gen_rtvec (3, target, reg,
4667 force_reg (V16QImode, x)),
4669 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4672 /* Extract field ELT from VEC into TARGET. */
4675 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4677 enum machine_mode mode = GET_MODE (vec);
4678 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4681 if (VECTOR_MEM_VSX_P (mode))
4688 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4691 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4694 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4699 /* Allocate mode-sized buffer. */
4700 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4702 emit_move_insn (mem, vec);
4704 /* Add offset to field within buffer matching vector element. */
4705 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4707 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4710 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4711 implement ANDing by the mask IN. */
4713 build_mask64_2_operands (rtx in, rtx *out)
4715 #if HOST_BITS_PER_WIDE_INT >= 64
4716 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4719 gcc_assert (GET_CODE (in) == CONST_INT);
4724 /* Assume c initially something like 0x00fff000000fffff. The idea
4725 is to rotate the word so that the middle ^^^^^^ group of zeros
4726 is at the MS end and can be cleared with an rldicl mask. We then
4727 rotate back and clear off the MS ^^ group of zeros with a
4729 c = ~c; /* c == 0xff000ffffff00000 */
4730 lsb = c & -c; /* lsb == 0x0000000000100000 */
4731 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4732 c = ~c; /* c == 0x00fff000000fffff */
4733 c &= -lsb; /* c == 0x00fff00000000000 */
4734 lsb = c & -c; /* lsb == 0x0000100000000000 */
4735 c = ~c; /* c == 0xff000fffffffffff */
4736 c &= -lsb; /* c == 0xff00000000000000 */
4738 while ((lsb >>= 1) != 0)
4739 shift++; /* shift == 44 on exit from loop */
4740 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4741 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4742 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4746 /* Assume c initially something like 0xff000f0000000000. The idea
4747 is to rotate the word so that the ^^^ middle group of zeros
4748 is at the LS end and can be cleared with an rldicr mask. We then
4749 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4751 lsb = c & -c; /* lsb == 0x0000010000000000 */
4752 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4753 c = ~c; /* c == 0x00fff0ffffffffff */
4754 c &= -lsb; /* c == 0x00fff00000000000 */
4755 lsb = c & -c; /* lsb == 0x0000100000000000 */
4756 c = ~c; /* c == 0xff000fffffffffff */
4757 c &= -lsb; /* c == 0xff00000000000000 */
4759 while ((lsb >>= 1) != 0)
4760 shift++; /* shift == 44 on exit from loop */
4761 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4762 m1 >>= shift; /* m1 == 0x0000000000000fff */
4763 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4766 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4767 masks will be all 1's. We are guaranteed more than one transition. */
4768 out[0] = GEN_INT (64 - shift);
4769 out[1] = GEN_INT (m1);
4770 out[2] = GEN_INT (shift);
4771 out[3] = GEN_INT (m2);
4779 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4782 invalid_e500_subreg (rtx op, enum machine_mode mode)
4784 if (TARGET_E500_DOUBLE)
4786 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4787 subreg:TI and reg:TF. Decimal float modes are like integer
4788 modes (only low part of each register used) for this
4790 if (GET_CODE (op) == SUBREG
4791 && (mode == SImode || mode == DImode || mode == TImode
4792 || mode == DDmode || mode == TDmode)
4793 && REG_P (SUBREG_REG (op))
4794 && (GET_MODE (SUBREG_REG (op)) == DFmode
4795 || GET_MODE (SUBREG_REG (op)) == TFmode))
4798 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4800 if (GET_CODE (op) == SUBREG
4801 && (mode == DFmode || mode == TFmode)
4802 && REG_P (SUBREG_REG (op))
4803 && (GET_MODE (SUBREG_REG (op)) == DImode
4804 || GET_MODE (SUBREG_REG (op)) == TImode
4805 || GET_MODE (SUBREG_REG (op)) == DDmode
4806 || GET_MODE (SUBREG_REG (op)) == TDmode))
4811 && GET_CODE (op) == SUBREG
4813 && REG_P (SUBREG_REG (op))
4814 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4820 /* AIX increases natural record alignment to doubleword if the first
4821 field is an FP double while the FP fields remain word aligned. */
4824 rs6000_special_round_type_align (tree type, unsigned int computed,
4825 unsigned int specified)
4827 unsigned int align = MAX (computed, specified);
4828 tree field = TYPE_FIELDS (type);
4830 /* Skip all non field decls */
4831 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4832 field = DECL_CHAIN (field);
4834 if (field != NULL && field != type)
4836 type = TREE_TYPE (field);
4837 while (TREE_CODE (type) == ARRAY_TYPE)
4838 type = TREE_TYPE (type);
4840 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4841 align = MAX (align, 64);
4847 /* Darwin increases record alignment to the natural alignment of
4851 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
4852 unsigned int specified)
4854 unsigned int align = MAX (computed, specified);
4856 if (TYPE_PACKED (type))
4859 /* Find the first field, looking down into aggregates. */
4861 tree field = TYPE_FIELDS (type);
4862 /* Skip all non field decls */
4863 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4864 field = DECL_CHAIN (field);
4867 /* A packed field does not contribute any extra alignment. */
4868 if (DECL_PACKED (field))
4870 type = TREE_TYPE (field);
4871 while (TREE_CODE (type) == ARRAY_TYPE)
4872 type = TREE_TYPE (type);
4873 } while (AGGREGATE_TYPE_P (type));
4875 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
4876 align = MAX (align, TYPE_ALIGN (type));
4881 /* Return 1 for an operand in small memory on V.4/eabi. */
4884 small_data_operand (rtx op ATTRIBUTE_UNUSED,
4885 enum machine_mode mode ATTRIBUTE_UNUSED)
4890 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
4893 if (DEFAULT_ABI != ABI_V4)
4896 /* Vector and float memory instructions have a limited offset on the
4897 SPE, so using a vector or float variable directly as an operand is
4900 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
4903 if (GET_CODE (op) == SYMBOL_REF)
4906 else if (GET_CODE (op) != CONST
4907 || GET_CODE (XEXP (op, 0)) != PLUS
4908 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
4909 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
4914 rtx sum = XEXP (op, 0);
4915 HOST_WIDE_INT summand;
4917 /* We have to be careful here, because it is the referenced address
4918 that must be 32k from _SDA_BASE_, not just the symbol. */
4919 summand = INTVAL (XEXP (sum, 1));
4920 if (summand < 0 || summand > g_switch_value)
4923 sym_ref = XEXP (sum, 0);
4926 return SYMBOL_REF_SMALL_P (sym_ref);
4932 /* Return true if either operand is a general purpose register. */
4935 gpr_or_gpr_p (rtx op0, rtx op1)
4937 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
4938 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
4942 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
4945 reg_offset_addressing_ok_p (enum machine_mode mode)
4955 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
4956 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
4964 /* Paired vector modes. Only reg+reg addressing is valid. */
4965 if (TARGET_PAIRED_FLOAT)
4977 virtual_stack_registers_memory_p (rtx op)
4981 if (GET_CODE (op) == REG)
4982 regnum = REGNO (op);
4984 else if (GET_CODE (op) == PLUS
4985 && GET_CODE (XEXP (op, 0)) == REG
4986 && GET_CODE (XEXP (op, 1)) == CONST_INT)
4987 regnum = REGNO (XEXP (op, 0));
4992 return (regnum >= FIRST_VIRTUAL_REGISTER
4993 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
4996 /* Return true if memory accesses to OP are known to never straddle
5000 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5001 enum machine_mode mode)
5004 unsigned HOST_WIDE_INT dsize, dalign;
5006 if (GET_CODE (op) != SYMBOL_REF)
5009 decl = SYMBOL_REF_DECL (op);
5012 if (GET_MODE_SIZE (mode) == 0)
5015 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5016 replacing memory addresses with an anchor plus offset. We
5017 could find the decl by rummaging around in the block->objects
5018 VEC for the given offset but that seems like too much work. */
5020 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5021 && SYMBOL_REF_ANCHOR_P (op)
5022 && SYMBOL_REF_BLOCK (op) != NULL)
5024 struct object_block *block = SYMBOL_REF_BLOCK (op);
5025 HOST_WIDE_INT lsb, mask;
5027 /* Given the alignment of the block.. */
5028 dalign = block->alignment;
5029 mask = dalign / BITS_PER_UNIT - 1;
5031 /* ..and the combined offset of the anchor and any offset
5032 to this block object.. */
5033 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5034 lsb = offset & -offset;
5036 /* ..find how many bits of the alignment we know for the
5041 return dalign >= GET_MODE_SIZE (mode);
5046 if (TREE_CODE (decl) == FUNCTION_DECL)
5049 if (!DECL_SIZE_UNIT (decl))
5052 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5055 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5059 dalign = DECL_ALIGN_UNIT (decl);
5060 return dalign >= dsize;
5063 type = TREE_TYPE (decl);
5065 if (TREE_CODE (decl) == STRING_CST)
5066 dsize = TREE_STRING_LENGTH (decl);
5067 else if (TYPE_SIZE_UNIT (type)
5068 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5069 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5075 dalign = TYPE_ALIGN (type);
5076 if (CONSTANT_CLASS_P (decl))
5077 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5079 dalign = DATA_ALIGNMENT (decl, dalign);
5080 dalign /= BITS_PER_UNIT;
5081 return dalign >= dsize;
5085 constant_pool_expr_p (rtx op)
5089 split_const (op, &base, &offset);
5090 return (GET_CODE (base) == SYMBOL_REF
5091 && CONSTANT_POOL_ADDRESS_P (base)
5092 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5095 static const_rtx tocrel_base, tocrel_offset;
5097 /* Return true if OP is a toc pointer relative address (the output
5098 of create_TOC_reference). If STRICT, do not match high part or
5099 non-split -mcmodel=large/medium toc pointer relative addresses. */
5102 toc_relative_expr_p (const_rtx op, bool strict)
5107 if (TARGET_CMODEL != CMODEL_SMALL)
5109 /* Only match the low part. */
5110 if (GET_CODE (op) == LO_SUM
5111 && REG_P (XEXP (op, 0))
5112 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict))
5119 tocrel_offset = const0_rtx;
5120 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
5122 tocrel_base = XEXP (op, 0);
5123 tocrel_offset = XEXP (op, 1);
5126 return (GET_CODE (tocrel_base) == UNSPEC
5127 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5130 /* Return true if X is a constant pool address, and also for cmodel=medium
5131 if X is a toc-relative address known to be offsettable within MODE. */
5134 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5137 return (toc_relative_expr_p (x, strict)
5138 && (TARGET_CMODEL != CMODEL_MEDIUM
5139 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5141 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5142 INTVAL (tocrel_offset), mode)));
5146 legitimate_small_data_p (enum machine_mode mode, rtx x)
5148 return (DEFAULT_ABI == ABI_V4
5149 && !flag_pic && !TARGET_TOC
5150 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5151 && small_data_operand (x, mode));
5154 /* SPE offset addressing is limited to 5-bits worth of double words. */
5155 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5158 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
5160 unsigned HOST_WIDE_INT offset, extra;
5162 if (GET_CODE (x) != PLUS)
5164 if (GET_CODE (XEXP (x, 0)) != REG)
5166 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5168 if (!reg_offset_addressing_ok_p (mode))
5169 return virtual_stack_registers_memory_p (x);
5170 if (legitimate_constant_pool_address_p (x, mode, strict))
5172 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5175 offset = INTVAL (XEXP (x, 1));
5183 /* SPE vector modes. */
5184 return SPE_CONST_OFFSET_OK (offset);
5187 if (TARGET_E500_DOUBLE)
5188 return SPE_CONST_OFFSET_OK (offset);
5190 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5192 if (VECTOR_MEM_VSX_P (DFmode))
5197 /* On e500v2, we may have:
5199 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5201 Which gets addressed with evldd instructions. */
5202 if (TARGET_E500_DOUBLE)
5203 return SPE_CONST_OFFSET_OK (offset);
5205 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
5207 else if (offset & 3)
5212 if (TARGET_E500_DOUBLE)
5213 return (SPE_CONST_OFFSET_OK (offset)
5214 && SPE_CONST_OFFSET_OK (offset + 8));
5218 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
5220 else if (offset & 3)
5231 return offset < 0x10000 - extra;
5235 legitimate_indexed_address_p (rtx x, int strict)
5239 if (GET_CODE (x) != PLUS)
5245 /* Recognize the rtl generated by reload which we know will later be
5246 replaced with proper base and index regs. */
5248 && reload_in_progress
5249 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5253 return (REG_P (op0) && REG_P (op1)
5254 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5255 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5256 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5257 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5261 avoiding_indexed_address_p (enum machine_mode mode)
5263 /* Avoid indexed addressing for modes that have non-indexed
5264 load/store instruction forms. */
5265 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5269 legitimate_indirect_address_p (rtx x, int strict)
5271 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5275 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5277 if (!TARGET_MACHO || !flag_pic
5278 || mode != SImode || GET_CODE (x) != MEM)
5282 if (GET_CODE (x) != LO_SUM)
5284 if (GET_CODE (XEXP (x, 0)) != REG)
5286 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5290 return CONSTANT_P (x);
5294 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5296 if (GET_CODE (x) != LO_SUM)
5298 if (GET_CODE (XEXP (x, 0)) != REG)
5300 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5302 /* Restrict addressing for DI because of our SUBREG hackery. */
5303 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5304 || mode == DDmode || mode == TDmode
5309 if (TARGET_ELF || TARGET_MACHO)
5311 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5315 if (GET_MODE_NUNITS (mode) != 1)
5317 if (GET_MODE_BITSIZE (mode) > 64
5318 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
5319 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5320 && (mode == DFmode || mode == DDmode))))
5323 return CONSTANT_P (x);
5330 /* Try machine-dependent ways of modifying an illegitimate address
5331 to be legitimate. If we find one, return the new, valid address.
5332 This is used from only one place: `memory_address' in explow.c.
5334 OLDX is the address as it was before break_out_memory_refs was
5335 called. In some cases it is useful to look at this to decide what
5338 It is always safe for this function to do nothing. It exists to
5339 recognize opportunities to optimize the output.
5341 On RS/6000, first check for the sum of a register with a constant
5342 integer that is out of range. If so, generate code to add the
5343 constant with the low-order 16 bits masked to the register and force
5344 this result into another register (this can be done with `cau').
5345 Then generate an address of REG+(CONST&0xffff), allowing for the
5346 possibility of bit 16 being a one.
5348 Then check for the sum of a register and something not constant, try to
5349 load the other things into a register and return the sum. */
5352 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5353 enum machine_mode mode)
5355 unsigned int extra = 0;
5357 if (!reg_offset_addressing_ok_p (mode))
5359 if (virtual_stack_registers_memory_p (x))
5362 /* In theory we should not be seeing addresses of the form reg+0,
5363 but just in case it is generated, optimize it away. */
5364 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5365 return force_reg (Pmode, XEXP (x, 0));
5367 /* Make sure both operands are registers. */
5368 else if (GET_CODE (x) == PLUS)
5369 return gen_rtx_PLUS (Pmode,
5370 force_reg (Pmode, XEXP (x, 0)),
5371 force_reg (Pmode, XEXP (x, 1)));
5373 return force_reg (Pmode, x);
5375 if (GET_CODE (x) == SYMBOL_REF)
5377 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5379 return rs6000_legitimize_tls_address (x, model);
5389 if (!TARGET_POWERPC64)
5397 extra = TARGET_POWERPC64 ? 8 : 12;
5403 if (GET_CODE (x) == PLUS
5404 && GET_CODE (XEXP (x, 0)) == REG
5405 && GET_CODE (XEXP (x, 1)) == CONST_INT
5406 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5408 && !((TARGET_POWERPC64
5409 && (mode == DImode || mode == TImode)
5410 && (INTVAL (XEXP (x, 1)) & 3) != 0)
5411 || SPE_VECTOR_MODE (mode)
5412 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5413 || mode == DImode || mode == DDmode
5414 || mode == TDmode))))
5416 HOST_WIDE_INT high_int, low_int;
5418 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5419 if (low_int >= 0x8000 - extra)
5421 high_int = INTVAL (XEXP (x, 1)) - low_int;
5422 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5423 GEN_INT (high_int)), 0);
5424 return plus_constant (Pmode, sum, low_int);
5426 else if (GET_CODE (x) == PLUS
5427 && GET_CODE (XEXP (x, 0)) == REG
5428 && GET_CODE (XEXP (x, 1)) != CONST_INT
5429 && GET_MODE_NUNITS (mode) == 1
5430 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5432 || ((mode != DImode && mode != DFmode && mode != DDmode)
5433 || (TARGET_E500_DOUBLE && mode != DDmode)))
5434 && (TARGET_POWERPC64 || mode != DImode)
5435 && !avoiding_indexed_address_p (mode)
5440 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5441 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5443 else if (SPE_VECTOR_MODE (mode)
5444 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5445 || mode == DDmode || mode == TDmode
5446 || mode == DImode)))
5450 /* We accept [reg + reg] and [reg + OFFSET]. */
5452 if (GET_CODE (x) == PLUS)
5454 rtx op1 = XEXP (x, 0);
5455 rtx op2 = XEXP (x, 1);
5458 op1 = force_reg (Pmode, op1);
5460 if (GET_CODE (op2) != REG
5461 && (GET_CODE (op2) != CONST_INT
5462 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5463 || (GET_MODE_SIZE (mode) > 8
5464 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5465 op2 = force_reg (Pmode, op2);
5467 /* We can't always do [reg + reg] for these, because [reg +
5468 reg + offset] is not a legitimate addressing mode. */
5469 y = gen_rtx_PLUS (Pmode, op1, op2);
5471 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5472 return force_reg (Pmode, y);
5477 return force_reg (Pmode, x);
5483 && GET_CODE (x) != CONST_INT
5484 && GET_CODE (x) != CONST_DOUBLE
5486 && GET_MODE_NUNITS (mode) == 1
5487 && (GET_MODE_BITSIZE (mode) <= 32
5488 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5489 && (mode == DFmode || mode == DDmode))))
5491 rtx reg = gen_reg_rtx (Pmode);
5492 emit_insn (gen_elf_high (reg, x));
5493 return gen_rtx_LO_SUM (Pmode, reg, x);
5495 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
5498 && ! MACHO_DYNAMIC_NO_PIC_P
5500 && GET_CODE (x) != CONST_INT
5501 && GET_CODE (x) != CONST_DOUBLE
5503 && GET_MODE_NUNITS (mode) == 1
5504 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5505 || (mode != DFmode && mode != DDmode))
5509 rtx reg = gen_reg_rtx (Pmode);
5510 emit_insn (gen_macho_high (reg, x));
5511 return gen_rtx_LO_SUM (Pmode, reg, x);
5514 && GET_CODE (x) == SYMBOL_REF
5515 && constant_pool_expr_p (x)
5516 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5517 return create_TOC_reference (x, NULL_RTX);
5522 /* Debug version of rs6000_legitimize_address. */
5524 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5530 ret = rs6000_legitimize_address (x, oldx, mode);
5531 insns = get_insns ();
5537 "\nrs6000_legitimize_address: mode %s, old code %s, "
5538 "new code %s, modified\n",
5539 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5540 GET_RTX_NAME (GET_CODE (ret)));
5542 fprintf (stderr, "Original address:\n");
5545 fprintf (stderr, "oldx:\n");
5548 fprintf (stderr, "New address:\n");
5553 fprintf (stderr, "Insns added:\n");
5554 debug_rtx_list (insns, 20);
5560 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5561 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5572 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5573 We need to emit DTP-relative relocations. */
5575 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5577 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5582 fputs ("\t.long\t", file);
5585 fputs (DOUBLE_INT_ASM_OP, file);
5590 output_addr_const (file, x);
5591 fputs ("@dtprel+0x8000", file);
5594 /* In the name of slightly smaller debug output, and to cater to
5595 general assembler lossage, recognize various UNSPEC sequences
5596 and turn them back into a direct symbol reference. */
5599 rs6000_delegitimize_address (rtx orig_x)
5603 orig_x = delegitimize_mem_from_attrs (orig_x);
5609 if (TARGET_CMODEL != CMODEL_SMALL
5610 && GET_CODE (y) == LO_SUM)
5614 if (GET_CODE (y) == PLUS
5615 && GET_MODE (y) == Pmode
5616 && CONST_INT_P (XEXP (y, 1)))
5618 offset = XEXP (y, 1);
5622 if (GET_CODE (y) == UNSPEC
5623 && XINT (y, 1) == UNSPEC_TOCREL)
5625 #ifdef ENABLE_CHECKING
5626 if (REG_P (XVECEXP (y, 0, 1))
5627 && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
5631 else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
5633 /* Weirdness alert. df_note_compute can replace r2 with a
5634 debug_expr when this unspec is in a debug_insn.
5635 Seen in gcc.dg/pr51957-1.c */
5643 y = XVECEXP (y, 0, 0);
5644 if (offset != NULL_RTX)
5645 y = gen_rtx_PLUS (Pmode, y, offset);
5646 if (!MEM_P (orig_x))
5649 return replace_equiv_address_nv (orig_x, y);
5653 && GET_CODE (orig_x) == LO_SUM
5654 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5656 y = XEXP (XEXP (orig_x, 1), 0);
5657 if (GET_CODE (y) == UNSPEC
5658 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5659 return XVECEXP (y, 0, 0);
5665 /* Return true if X shouldn't be emitted into the debug info.
5666 The linker doesn't like .toc section references from
5667 .debug_* sections, so reject .toc section symbols. */
5670 rs6000_const_not_ok_for_debug_p (rtx x)
5672 if (GET_CODE (x) == SYMBOL_REF
5673 && CONSTANT_POOL_ADDRESS_P (x))
5675 rtx c = get_pool_constant (x);
5676 enum machine_mode cmode = get_pool_mode (x);
5677 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
5684 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5686 static GTY(()) rtx rs6000_tls_symbol;
5688 rs6000_tls_get_addr (void)
5690 if (!rs6000_tls_symbol)
5691 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5693 return rs6000_tls_symbol;
5696 /* Construct the SYMBOL_REF for TLS GOT references. */
5698 static GTY(()) rtx rs6000_got_symbol;
5700 rs6000_got_sym (void)
5702 if (!rs6000_got_symbol)
5704 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5705 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5706 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5709 return rs6000_got_symbol;
5712 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5713 this (thread-local) address. */
5716 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5720 dest = gen_reg_rtx (Pmode);
5721 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5727 tlsreg = gen_rtx_REG (Pmode, 13);
5728 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5732 tlsreg = gen_rtx_REG (Pmode, 2);
5733 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5737 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5741 tmp = gen_reg_rtx (Pmode);
5744 tlsreg = gen_rtx_REG (Pmode, 13);
5745 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5749 tlsreg = gen_rtx_REG (Pmode, 2);
5750 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
5754 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
5756 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
5761 rtx r3, got, tga, tmp1, tmp2, call_insn;
5763 /* We currently use relocations like @got@tlsgd for tls, which
5764 means the linker will handle allocation of tls entries, placing
5765 them in the .got section. So use a pointer to the .got section,
5766 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5767 or to secondary GOT sections used by 32-bit -fPIC. */
5769 got = gen_rtx_REG (Pmode, 2);
5773 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
5776 rtx gsym = rs6000_got_sym ();
5777 got = gen_reg_rtx (Pmode);
5779 rs6000_emit_move (got, gsym, Pmode);
5784 tmp1 = gen_reg_rtx (Pmode);
5785 tmp2 = gen_reg_rtx (Pmode);
5786 mem = gen_const_mem (Pmode, tmp1);
5787 lab = gen_label_rtx ();
5788 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
5789 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
5790 if (TARGET_LINK_STACK)
5791 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
5792 emit_move_insn (tmp2, mem);
5793 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
5794 set_unique_reg_note (last, REG_EQUAL, gsym);
5799 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
5801 tga = rs6000_tls_get_addr ();
5802 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
5803 1, const0_rtx, Pmode);
5805 r3 = gen_rtx_REG (Pmode, 3);
5806 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5807 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
5808 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5809 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
5810 else if (DEFAULT_ABI == ABI_V4)
5811 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
5814 call_insn = last_call_insn ();
5815 PATTERN (call_insn) = insn;
5816 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5817 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5818 pic_offset_table_rtx);
5820 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
5822 tga = rs6000_tls_get_addr ();
5823 tmp1 = gen_reg_rtx (Pmode);
5824 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
5825 1, const0_rtx, Pmode);
5827 r3 = gen_rtx_REG (Pmode, 3);
5828 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5829 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
5830 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5831 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
5832 else if (DEFAULT_ABI == ABI_V4)
5833 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
5836 call_insn = last_call_insn ();
5837 PATTERN (call_insn) = insn;
5838 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5839 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5840 pic_offset_table_rtx);
5842 if (rs6000_tls_size == 16)
5845 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
5847 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
5849 else if (rs6000_tls_size == 32)
5851 tmp2 = gen_reg_rtx (Pmode);
5853 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
5855 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
5858 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
5860 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
5864 tmp2 = gen_reg_rtx (Pmode);
5866 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
5868 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
5870 insn = gen_rtx_SET (Pmode, dest,
5871 gen_rtx_PLUS (Pmode, tmp2, tmp1));
5877 /* IE, or 64-bit offset LE. */
5878 tmp2 = gen_reg_rtx (Pmode);
5880 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
5882 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
5885 insn = gen_tls_tls_64 (dest, tmp2, addr);
5887 insn = gen_tls_tls_32 (dest, tmp2, addr);
5895 /* Return 1 if X contains a thread-local symbol. */
5898 rs6000_tls_referenced_p (rtx x)
5900 if (! TARGET_HAVE_TLS)
5903 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
5906 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
5909 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5911 if (GET_CODE (x) == HIGH
5912 && GET_CODE (XEXP (x, 0)) == UNSPEC)
5915 return rs6000_tls_referenced_p (x);
5918 /* Return 1 if *X is a thread-local symbol. This is the same as
5919 rs6000_tls_symbol_ref except for the type of the unused argument. */
5922 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
5924 return RS6000_SYMBOL_REF_TLS_P (*x);
5927 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
5928 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
5929 can be addressed relative to the toc pointer. */
5932 use_toc_relative_ref (rtx sym)
5934 return ((constant_pool_expr_p (sym)
5935 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
5936 get_pool_mode (sym)))
5937 || (TARGET_CMODEL == CMODEL_MEDIUM
5938 && !CONSTANT_POOL_ADDRESS_P (sym)
5939 && SYMBOL_REF_LOCAL_P (sym)));
5942 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
5943 replace the input X, or the original X if no replacement is called for.
5944 The output parameter *WIN is 1 if the calling macro should goto WIN,
5947 For RS/6000, we wish to handle large displacements off a base
5948 register by splitting the addend across an addiu/addis and the mem insn.
5949 This cuts number of extra insns needed from 3 to 1.
5951 On Darwin, we use this to generate code for floating point constants.
5952 A movsf_low is generated so we wind up with 2 instructions rather than 3.
5953 The Darwin code is inside #if TARGET_MACHO because only then are the
5954 machopic_* functions defined. */
5956 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
5957 int opnum, int type,
5958 int ind_levels ATTRIBUTE_UNUSED, int *win)
5960 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
5962 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
5963 DFmode/DImode MEM. */
5966 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
5967 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
5968 reg_offset_p = false;
5970 /* We must recognize output that we have already generated ourselves. */
5971 if (GET_CODE (x) == PLUS
5972 && GET_CODE (XEXP (x, 0)) == PLUS
5973 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5974 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5975 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5977 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
5978 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
5979 opnum, (enum reload_type) type);
5984 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
5985 if (GET_CODE (x) == LO_SUM
5986 && GET_CODE (XEXP (x, 0)) == HIGH)
5988 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
5989 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
5990 opnum, (enum reload_type) type);
5996 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
5997 && GET_CODE (x) == LO_SUM
5998 && GET_CODE (XEXP (x, 0)) == PLUS
5999 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6000 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6001 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6002 && machopic_operand_p (XEXP (x, 1)))
6004 /* Result of previous invocation of this function on Darwin
6005 floating point constant. */
6006 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6007 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6008 opnum, (enum reload_type) type);
6014 if (TARGET_CMODEL != CMODEL_SMALL
6016 && small_toc_ref (x, VOIDmode))
6018 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
6019 x = gen_rtx_LO_SUM (Pmode, hi, x);
6020 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6021 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6022 opnum, (enum reload_type) type);
6027 /* Force ld/std non-word aligned offset into base register by wrapping
6029 if (GET_CODE (x) == PLUS
6030 && GET_CODE (XEXP (x, 0)) == REG
6031 && REGNO (XEXP (x, 0)) < 32
6032 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6033 && GET_CODE (XEXP (x, 1)) == CONST_INT
6035 && (INTVAL (XEXP (x, 1)) & 3) != 0
6036 && VECTOR_MEM_NONE_P (mode)
6037 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
6038 && TARGET_POWERPC64)
6040 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
6041 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6042 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6043 opnum, (enum reload_type) type);
6048 if (GET_CODE (x) == PLUS
6049 && GET_CODE (XEXP (x, 0)) == REG
6050 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6051 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6052 && GET_CODE (XEXP (x, 1)) == CONST_INT
6054 && !SPE_VECTOR_MODE (mode)
6055 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6056 || mode == DDmode || mode == TDmode
6058 && VECTOR_MEM_NONE_P (mode))
6060 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6061 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6063 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6065 /* Check for 32-bit overflow. */
6066 if (high + low != val)
6072 /* Reload the high part into a base reg; leave the low part
6073 in the mem directly. */
6075 x = gen_rtx_PLUS (GET_MODE (x),
6076 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6080 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6081 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6082 opnum, (enum reload_type) type);
6087 if (GET_CODE (x) == SYMBOL_REF
6089 && VECTOR_MEM_NONE_P (mode)
6090 && !SPE_VECTOR_MODE (mode)
6092 && DEFAULT_ABI == ABI_DARWIN
6093 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6094 && machopic_symbol_defined_p (x)
6096 && DEFAULT_ABI == ABI_V4
6099 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6100 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6104 && (mode != DImode || TARGET_POWERPC64)
6105 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6106 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6111 rtx offset = machopic_gen_offset (x);
6112 x = gen_rtx_LO_SUM (GET_MODE (x),
6113 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6114 gen_rtx_HIGH (Pmode, offset)), offset);
6118 x = gen_rtx_LO_SUM (GET_MODE (x),
6119 gen_rtx_HIGH (Pmode, x), x);
6121 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6122 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6123 opnum, (enum reload_type) type);
6128 /* Reload an offset address wrapped by an AND that represents the
6129 masking of the lower bits. Strip the outer AND and let reload
6130 convert the offset address into an indirect address. For VSX,
6131 force reload to create the address with an AND in a separate
6132 register, because we can't guarantee an altivec register will
6134 if (VECTOR_MEM_ALTIVEC_P (mode)
6135 && GET_CODE (x) == AND
6136 && GET_CODE (XEXP (x, 0)) == PLUS
6137 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6138 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6139 && GET_CODE (XEXP (x, 1)) == CONST_INT
6140 && INTVAL (XEXP (x, 1)) == -16)
6149 && GET_CODE (x) == SYMBOL_REF
6150 && use_toc_relative_ref (x))
6152 x = create_TOC_reference (x, NULL_RTX);
6153 if (TARGET_CMODEL != CMODEL_SMALL)
6154 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6155 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6156 opnum, (enum reload_type) type);
6164 /* Debug version of rs6000_legitimize_reload_address. */
6166 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6167 int opnum, int type,
6168 int ind_levels, int *win)
6170 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6173 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6174 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6175 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6179 fprintf (stderr, "Same address returned\n");
6181 fprintf (stderr, "NULL returned\n");
6184 fprintf (stderr, "New address:\n");
6191 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6192 that is a valid memory address for an instruction.
6193 The MODE argument is the machine mode for the MEM expression
6194 that wants to use this address.
6196 On the RS/6000, there are four valid address: a SYMBOL_REF that
6197 refers to a constant pool entry of an address (or the sum of it
6198 plus a constant), a short (16-bit signed) constant plus a register,
6199 the sum of two registers, or a register indirect, possibly with an
6200 auto-increment. For DFmode, DDmode and DImode with a constant plus
6201 register, we must ensure that both words are addressable or PowerPC64
6202 with offset word aligned.
6204 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6205 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6206 because adjacent memory cells are accessed by adding word-sized offsets
6207 during assembly output. */
6209 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6211 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6213 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6214 if (VECTOR_MEM_ALTIVEC_P (mode)
6215 && GET_CODE (x) == AND
6216 && GET_CODE (XEXP (x, 1)) == CONST_INT
6217 && INTVAL (XEXP (x, 1)) == -16)
6220 if (RS6000_SYMBOL_REF_TLS_P (x))
6222 if (legitimate_indirect_address_p (x, reg_ok_strict))
6224 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6225 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6226 && !SPE_VECTOR_MODE (mode)
6229 /* Restrict addressing for DI because of our SUBREG hackery. */
6230 && !(TARGET_E500_DOUBLE
6231 && (mode == DFmode || mode == DDmode || mode == DImode))
6233 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6235 if (virtual_stack_registers_memory_p (x))
6237 if (reg_offset_p && legitimate_small_data_p (mode, x))
6240 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6242 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6245 && GET_CODE (x) == PLUS
6246 && GET_CODE (XEXP (x, 0)) == REG
6247 && (XEXP (x, 0) == virtual_stack_vars_rtx
6248 || XEXP (x, 0) == arg_pointer_rtx)
6249 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6251 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
6256 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6258 || (mode != DFmode && mode != DDmode)
6259 || (TARGET_E500_DOUBLE && mode != DDmode))
6260 && (TARGET_POWERPC64 || mode != DImode)
6261 && !avoiding_indexed_address_p (mode)
6262 && legitimate_indexed_address_p (x, reg_ok_strict))
6264 if (GET_CODE (x) == PRE_MODIFY
6268 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6270 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6271 && (TARGET_POWERPC64 || mode != DImode)
6272 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6273 && !SPE_VECTOR_MODE (mode)
6274 /* Restrict addressing for DI because of our SUBREG hackery. */
6275 && !(TARGET_E500_DOUBLE
6276 && (mode == DFmode || mode == DDmode || mode == DImode))
6278 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6279 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
6280 || (!avoiding_indexed_address_p (mode)
6281 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6282 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6284 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6289 /* Debug version of rs6000_legitimate_address_p. */
6291 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6294 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6296 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6297 "strict = %d, code = %s\n",
6298 ret ? "true" : "false",
6299 GET_MODE_NAME (mode),
6301 GET_RTX_NAME (GET_CODE (x)));
6307 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6310 rs6000_mode_dependent_address_p (const_rtx addr)
6312 return rs6000_mode_dependent_address_ptr (addr);
6315 /* Go to LABEL if ADDR (a legitimate address expression)
6316 has an effect that depends on the machine mode it is used for.
6318 On the RS/6000 this is true of all integral offsets (since AltiVec
6319 and VSX modes don't allow them) or is a pre-increment or decrement.
6321 ??? Except that due to conceptual problems in offsettable_address_p
6322 we can't really report the problems of integral offsets. So leave
6323 this assuming that the adjustable offset must be valid for the
6324 sub-words of a TFmode operand, which is what we had before. */
6327 rs6000_mode_dependent_address (const_rtx addr)
6329 switch (GET_CODE (addr))
6332 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6333 is considered a legitimate address before reload, so there
6334 are no offset restrictions in that case. Note that this
6335 condition is safe in strict mode because any address involving
6336 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6337 been rejected as illegitimate. */
6338 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6339 && XEXP (addr, 0) != arg_pointer_rtx
6340 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6342 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6343 return val + 12 + 0x8000 >= 0x10000;
6348 /* Anything in the constant pool is sufficiently aligned that
6349 all bytes have the same high part address. */
6350 return !legitimate_constant_pool_address_p (addr, QImode, false);
6352 /* Auto-increment cases are now treated generically in recog.c. */
6354 return TARGET_UPDATE;
6356 /* AND is only allowed in Altivec loads. */
6367 /* Debug version of rs6000_mode_dependent_address. */
6369 rs6000_debug_mode_dependent_address (const_rtx addr)
6371 bool ret = rs6000_mode_dependent_address (addr);
6373 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6374 ret ? "true" : "false");
6380 /* Implement FIND_BASE_TERM. */
6383 rs6000_find_base_term (rtx op)
6388 if (GET_CODE (base) == CONST)
6389 base = XEXP (base, 0);
6390 if (GET_CODE (base) == PLUS)
6391 base = XEXP (base, 0);
6392 if (GET_CODE (base) == UNSPEC)
6393 switch (XINT (base, 1))
6396 case UNSPEC_MACHOPIC_OFFSET:
6397 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6398 for aliasing purposes. */
6399 return XVECEXP (base, 0, 0);
6405 /* More elaborate version of recog's offsettable_memref_p predicate
6406 that works around the ??? note of rs6000_mode_dependent_address.
6407 In particular it accepts
6409 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6411 in 32-bit mode, that the recog predicate rejects. */
6414 rs6000_offsettable_memref_p (rtx op)
6419 /* First mimic offsettable_memref_p. */
6420 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
6423 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6424 the latter predicate knows nothing about the mode of the memory
6425 reference and, therefore, assumes that it is the largest supported
6426 mode (TFmode). As a consequence, legitimate offsettable memory
6427 references are rejected. rs6000_legitimate_offset_address_p contains
6428 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6429 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
6432 /* Change register usage conditional on target flags. */
6434 rs6000_conditional_register_usage (void)
6438 if (TARGET_DEBUG_TARGET)
6439 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6441 /* Set MQ register fixed (already call_used) if not POWER
6442 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6447 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6449 fixed_regs[13] = call_used_regs[13]
6450 = call_really_used_regs[13] = 1;
6452 /* Conditionally disable FPRs. */
6453 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6454 for (i = 32; i < 64; i++)
6455 fixed_regs[i] = call_used_regs[i]
6456 = call_really_used_regs[i] = 1;
6458 /* The TOC register is not killed across calls in a way that is
6459 visible to the compiler. */
6460 if (DEFAULT_ABI == ABI_AIX)
6461 call_really_used_regs[2] = 0;
6463 if (DEFAULT_ABI == ABI_V4
6464 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6466 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6468 if (DEFAULT_ABI == ABI_V4
6469 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6471 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6472 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6473 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6475 if (DEFAULT_ABI == ABI_DARWIN
6476 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6477 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6478 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6479 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6481 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6482 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6483 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6487 global_regs[SPEFSCR_REGNO] = 1;
6488 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6489 registers in prologues and epilogues. We no longer use r14
6490 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6491 pool for link-compatibility with older versions of GCC. Once
6492 "old" code has died out, we can return r14 to the allocation
6495 = call_used_regs[14]
6496 = call_really_used_regs[14] = 1;
6499 if (!TARGET_ALTIVEC && !TARGET_VSX)
6501 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6502 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6503 call_really_used_regs[VRSAVE_REGNO] = 1;
6506 if (TARGET_ALTIVEC || TARGET_VSX)
6507 global_regs[VSCR_REGNO] = 1;
6509 if (TARGET_ALTIVEC_ABI)
6511 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6512 call_used_regs[i] = call_really_used_regs[i] = 1;
6514 /* AIX reserves VR20:31 in non-extended ABI mode. */
6516 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6517 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6521 /* Try to output insns to set TARGET equal to the constant C if it can
6522 be done in less than N insns. Do all computations in MODE.
6523 Returns the place where the output has been placed if it can be
6524 done and the insns have been emitted. If it would take more than N
6525 insns, zero is returned and no insns and emitted. */
6528 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6529 rtx source, int n ATTRIBUTE_UNUSED)
6531 rtx result, insn, set;
6532 HOST_WIDE_INT c0, c1;
6539 dest = gen_reg_rtx (mode);
6540 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6544 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6546 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6547 GEN_INT (INTVAL (source)
6548 & (~ (HOST_WIDE_INT) 0xffff))));
6549 emit_insn (gen_rtx_SET (VOIDmode, dest,
6550 gen_rtx_IOR (SImode, copy_rtx (result),
6551 GEN_INT (INTVAL (source) & 0xffff))));
6556 switch (GET_CODE (source))
6559 c0 = INTVAL (source);
6564 #if HOST_BITS_PER_WIDE_INT >= 64
6565 c0 = CONST_DOUBLE_LOW (source);
6568 c0 = CONST_DOUBLE_LOW (source);
6569 c1 = CONST_DOUBLE_HIGH (source);
6577 result = rs6000_emit_set_long_const (dest, c0, c1);
6584 insn = get_last_insn ();
6585 set = single_set (insn);
6586 if (! CONSTANT_P (SET_SRC (set)))
6587 set_unique_reg_note (insn, REG_EQUAL, source);
6592 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6593 fall back to a straight forward decomposition. We do this to avoid
6594 exponential run times encountered when looking for longer sequences
6595 with rs6000_emit_set_const. */
6597 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6599 if (!TARGET_POWERPC64)
6601 rtx operand1, operand2;
6603 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6605 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6607 emit_move_insn (operand1, GEN_INT (c1));
6608 emit_move_insn (operand2, GEN_INT (c2));
6612 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6615 ud2 = (c1 & 0xffff0000) >> 16;
6616 #if HOST_BITS_PER_WIDE_INT >= 64
6620 ud4 = (c2 & 0xffff0000) >> 16;
6622 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6623 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6626 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6628 emit_move_insn (dest, GEN_INT (ud1));
6631 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6632 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6635 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6638 emit_move_insn (dest, GEN_INT (ud2 << 16));
6640 emit_move_insn (copy_rtx (dest),
6641 gen_rtx_IOR (DImode, copy_rtx (dest),
6644 else if (ud3 == 0 && ud4 == 0)
6646 gcc_assert (ud2 & 0x8000);
6647 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6650 emit_move_insn (copy_rtx (dest),
6651 gen_rtx_IOR (DImode, copy_rtx (dest),
6653 emit_move_insn (copy_rtx (dest),
6654 gen_rtx_ZERO_EXTEND (DImode,
6655 gen_lowpart (SImode,
6658 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6659 || (ud4 == 0 && ! (ud3 & 0x8000)))
6662 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6665 emit_move_insn (dest, GEN_INT (ud3 << 16));
6668 emit_move_insn (copy_rtx (dest),
6669 gen_rtx_IOR (DImode, copy_rtx (dest),
6671 emit_move_insn (copy_rtx (dest),
6672 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6675 emit_move_insn (copy_rtx (dest),
6676 gen_rtx_IOR (DImode, copy_rtx (dest),
6682 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6685 emit_move_insn (dest, GEN_INT (ud4 << 16));
6688 emit_move_insn (copy_rtx (dest),
6689 gen_rtx_IOR (DImode, copy_rtx (dest),
6692 emit_move_insn (copy_rtx (dest),
6693 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6696 emit_move_insn (copy_rtx (dest),
6697 gen_rtx_IOR (DImode, copy_rtx (dest),
6698 GEN_INT (ud2 << 16)));
6700 emit_move_insn (copy_rtx (dest),
6701 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6707 /* Helper for the following. Get rid of [r+r] memory refs
6708 in cases where it won't work (TImode, TFmode, TDmode). */
6711 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6713 if (reload_in_progress)
6716 if (GET_CODE (operands[0]) == MEM
6717 && GET_CODE (XEXP (operands[0], 0)) != REG
6718 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6719 GET_MODE (operands[0]), false))
6721 = replace_equiv_address (operands[0],
6722 copy_addr_to_reg (XEXP (operands[0], 0)));
6724 if (GET_CODE (operands[1]) == MEM
6725 && GET_CODE (XEXP (operands[1], 0)) != REG
6726 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6727 GET_MODE (operands[1]), false))
6729 = replace_equiv_address (operands[1],
6730 copy_addr_to_reg (XEXP (operands[1], 0)));
6733 /* Emit a move from SOURCE to DEST in mode MODE. */
6735 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6739 operands[1] = source;
6741 if (TARGET_DEBUG_ADDR)
6744 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6745 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6746 GET_MODE_NAME (mode),
6749 can_create_pseudo_p ());
6751 fprintf (stderr, "source:\n");
6755 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6756 if (GET_CODE (operands[1]) == CONST_DOUBLE
6757 && ! FLOAT_MODE_P (mode)
6758 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6760 /* FIXME. This should never happen. */
6761 /* Since it seems that it does, do the safe thing and convert
6763 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
6765 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
6766 || FLOAT_MODE_P (mode)
6767 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
6768 || CONST_DOUBLE_LOW (operands[1]) < 0)
6769 && (CONST_DOUBLE_HIGH (operands[1]) != -1
6770 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
6772 /* Check if GCC is setting up a block move that will end up using FP
6773 registers as temporaries. We must make sure this is acceptable. */
6774 if (GET_CODE (operands[0]) == MEM
6775 && GET_CODE (operands[1]) == MEM
6777 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
6778 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
6779 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
6780 ? 32 : MEM_ALIGN (operands[0])))
6781 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
6783 : MEM_ALIGN (operands[1]))))
6784 && ! MEM_VOLATILE_P (operands [0])
6785 && ! MEM_VOLATILE_P (operands [1]))
6787 emit_move_insn (adjust_address (operands[0], SImode, 0),
6788 adjust_address (operands[1], SImode, 0));
6789 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
6790 adjust_address (copy_rtx (operands[1]), SImode, 4));
6794 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
6795 && !gpc_reg_operand (operands[1], mode))
6796 operands[1] = force_reg (mode, operands[1]);
6798 if (mode == SFmode && ! TARGET_POWERPC
6799 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6800 && GET_CODE (operands[0]) == MEM)
6804 if (reload_in_progress || reload_completed)
6805 regnum = true_regnum (operands[1]);
6806 else if (GET_CODE (operands[1]) == REG)
6807 regnum = REGNO (operands[1]);
6811 /* If operands[1] is a register, on POWER it may have
6812 double-precision data in it, so truncate it to single
6814 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
6817 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
6818 : gen_reg_rtx (mode));
6819 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6820 operands[1] = newreg;
6824 /* Recognize the case where operand[1] is a reference to thread-local
6825 data and load its address to a register. */
6826 if (rs6000_tls_referenced_p (operands[1]))
6828 enum tls_model model;
6829 rtx tmp = operands[1];
6832 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
6834 addend = XEXP (XEXP (tmp, 0), 1);
6835 tmp = XEXP (XEXP (tmp, 0), 0);
6838 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
6839 model = SYMBOL_REF_TLS_MODEL (tmp);
6840 gcc_assert (model != 0);
6842 tmp = rs6000_legitimize_tls_address (tmp, model);
6845 tmp = gen_rtx_PLUS (mode, tmp, addend);
6846 tmp = force_operand (tmp, operands[0]);
6851 /* Handle the case where reload calls us with an invalid address. */
6852 if (reload_in_progress && mode == Pmode
6853 && (! general_operand (operands[1], mode)
6854 || ! nonimmediate_operand (operands[0], mode)))
6857 /* 128-bit constant floating-point values on Darwin should really be
6858 loaded as two parts. */
6859 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6860 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
6862 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
6863 simplify_gen_subreg (DFmode, operands[1], mode, 0),
6865 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
6866 GET_MODE_SIZE (DFmode)),
6867 simplify_gen_subreg (DFmode, operands[1], mode,
6868 GET_MODE_SIZE (DFmode)),
6873 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
6874 cfun->machine->sdmode_stack_slot =
6875 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
6877 if (reload_in_progress
6879 && MEM_P (operands[0])
6880 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
6881 && REG_P (operands[1]))
6883 if (FP_REGNO_P (REGNO (operands[1])))
6885 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
6886 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6887 emit_insn (gen_movsd_store (mem, operands[1]));
6889 else if (INT_REGNO_P (REGNO (operands[1])))
6891 rtx mem = adjust_address_nv (operands[0], mode, 4);
6892 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6893 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
6899 if (reload_in_progress
6901 && REG_P (operands[0])
6902 && MEM_P (operands[1])
6903 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
6905 if (FP_REGNO_P (REGNO (operands[0])))
6907 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
6908 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6909 emit_insn (gen_movsd_load (operands[0], mem));
6911 else if (INT_REGNO_P (REGNO (operands[0])))
6913 rtx mem = adjust_address_nv (operands[1], mode, 4);
6914 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6915 emit_insn (gen_movsd_hardfloat (operands[0], mem));
6922 /* FIXME: In the long term, this switch statement should go away
6923 and be replaced by a sequence of tests based on things like
6929 if (CONSTANT_P (operands[1])
6930 && GET_CODE (operands[1]) != CONST_INT)
6931 operands[1] = force_const_mem (mode, operands[1]);
6936 rs6000_eliminate_indexed_memrefs (operands);
6943 if (CONSTANT_P (operands[1])
6944 && ! easy_fp_constant (operands[1], mode))
6945 operands[1] = force_const_mem (mode, operands[1]);
6958 if (CONSTANT_P (operands[1])
6959 && !easy_vector_constant (operands[1], mode))
6960 operands[1] = force_const_mem (mode, operands[1]);
6965 /* Use default pattern for address of ELF small data */
6968 && DEFAULT_ABI == ABI_V4
6969 && (GET_CODE (operands[1]) == SYMBOL_REF
6970 || GET_CODE (operands[1]) == CONST)
6971 && small_data_operand (operands[1], mode))
6973 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
6977 if (DEFAULT_ABI == ABI_V4
6978 && mode == Pmode && mode == SImode
6979 && flag_pic == 1 && got_operand (operands[1], mode))
6981 emit_insn (gen_movsi_got (operands[0], operands[1]));
6985 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
6989 && CONSTANT_P (operands[1])
6990 && GET_CODE (operands[1]) != HIGH
6991 && GET_CODE (operands[1]) != CONST_INT)
6993 rtx target = (!can_create_pseudo_p ()
6995 : gen_reg_rtx (mode));
6997 /* If this is a function address on -mcall-aixdesc,
6998 convert it to the address of the descriptor. */
6999 if (DEFAULT_ABI == ABI_AIX
7000 && GET_CODE (operands[1]) == SYMBOL_REF
7001 && XSTR (operands[1], 0)[0] == '.')
7003 const char *name = XSTR (operands[1], 0);
7005 while (*name == '.')
7007 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7008 CONSTANT_POOL_ADDRESS_P (new_ref)
7009 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7010 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7011 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7012 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7013 operands[1] = new_ref;
7016 if (DEFAULT_ABI == ABI_DARWIN)
7019 if (MACHO_DYNAMIC_NO_PIC_P)
7021 /* Take care of any required data indirection. */
7022 operands[1] = rs6000_machopic_legitimize_pic_address (
7023 operands[1], mode, operands[0]);
7024 if (operands[0] != operands[1])
7025 emit_insn (gen_rtx_SET (VOIDmode,
7026 operands[0], operands[1]));
7030 emit_insn (gen_macho_high (target, operands[1]));
7031 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7035 emit_insn (gen_elf_high (target, operands[1]));
7036 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7040 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7041 and we have put it in the TOC, we just need to make a TOC-relative
7044 && GET_CODE (operands[1]) == SYMBOL_REF
7045 && use_toc_relative_ref (operands[1]))
7046 operands[1] = create_TOC_reference (operands[1], operands[0]);
7047 else if (mode == Pmode
7048 && CONSTANT_P (operands[1])
7049 && GET_CODE (operands[1]) != HIGH
7050 && ((GET_CODE (operands[1]) != CONST_INT
7051 && ! easy_fp_constant (operands[1], mode))
7052 || (GET_CODE (operands[1]) == CONST_INT
7053 && (num_insns_constant (operands[1], mode)
7054 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7055 || (GET_CODE (operands[0]) == REG
7056 && FP_REGNO_P (REGNO (operands[0]))))
7057 && !toc_relative_expr_p (operands[1], false)
7058 && (TARGET_CMODEL == CMODEL_SMALL
7059 || can_create_pseudo_p ()
7060 || (REG_P (operands[0])
7061 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7065 /* Darwin uses a special PIC legitimizer. */
7066 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7069 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7071 if (operands[0] != operands[1])
7072 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7077 /* If we are to limit the number of things we put in the TOC and
7078 this is a symbol plus a constant we can add in one insn,
7079 just put the symbol in the TOC and add the constant. Don't do
7080 this if reload is in progress. */
7081 if (GET_CODE (operands[1]) == CONST
7082 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7083 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7084 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7085 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7086 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7087 && ! side_effects_p (operands[0]))
7090 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7091 rtx other = XEXP (XEXP (operands[1], 0), 1);
7093 sym = force_reg (mode, sym);
7094 emit_insn (gen_add3_insn (operands[0], sym, other));
7098 operands[1] = force_const_mem (mode, operands[1]);
7101 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7102 && constant_pool_expr_p (XEXP (operands[1], 0))
7103 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7104 get_pool_constant (XEXP (operands[1], 0)),
7105 get_pool_mode (XEXP (operands[1], 0))))
7107 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
7109 operands[1] = gen_const_mem (mode, tocref);
7110 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7116 rs6000_eliminate_indexed_memrefs (operands);
7120 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7122 gen_rtx_SET (VOIDmode,
7123 operands[0], operands[1]),
7124 gen_rtx_CLOBBER (VOIDmode,
7125 gen_rtx_SCRATCH (SImode)))));
7131 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7134 /* Above, we may have called force_const_mem which may have returned
7135 an invalid address. If we can, fix this up; otherwise, reload will
7136 have to deal with it. */
7137 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7138 operands[1] = validize_mem (operands[1]);
7141 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7144 /* Nonzero if we can use a floating-point register to pass this arg. */
7145 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7146 (SCALAR_FLOAT_MODE_P (MODE) \
7147 && (CUM)->fregno <= FP_ARG_MAX_REG \
7148 && TARGET_HARD_FLOAT && TARGET_FPRS)
7150 /* Nonzero if we can use an AltiVec register to pass this arg. */
7151 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7152 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7153 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7154 && TARGET_ALTIVEC_ABI \
7157 /* Return a nonzero value to say to return the function value in
7158 memory, just as large structures are always returned. TYPE will be
7159 the data type of the value, and FNTYPE will be the type of the
7160 function doing the returning, or @code{NULL} for libcalls.
7162 The AIX ABI for the RS/6000 specifies that all structures are
7163 returned in memory. The Darwin ABI does the same.
7165 For the Darwin 64 Bit ABI, a function result can be returned in
7166 registers or in memory, depending on the size of the return data
7167 type. If it is returned in registers, the value occupies the same
7168 registers as it would if it were the first and only function
7169 argument. Otherwise, the function places its result in memory at
7170 the location pointed to by GPR3.
7172 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7173 but a draft put them in memory, and GCC used to implement the draft
7174 instead of the final standard. Therefore, aix_struct_return
7175 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7176 compatibility can change DRAFT_V4_STRUCT_RET to override the
7177 default, and -m switches get the final word. See
7178 rs6000_option_override_internal for more details.
7180 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7181 long double support is enabled. These values are returned in memory.
7183 int_size_in_bytes returns -1 for variable size objects, which go in
7184 memory always. The cast to unsigned makes -1 > 8. */
7187 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7189 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7191 && rs6000_darwin64_abi
7192 && TREE_CODE (type) == RECORD_TYPE
7193 && int_size_in_bytes (type) > 0)
7195 CUMULATIVE_ARGS valcum;
7199 valcum.fregno = FP_ARG_MIN_REG;
7200 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7201 /* Do a trial code generation as if this were going to be passed
7202 as an argument; if any part goes in memory, we return NULL. */
7203 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7206 /* Otherwise fall through to more conventional ABI rules. */
7209 if (AGGREGATE_TYPE_P (type)
7210 && (aix_struct_return
7211 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7214 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7215 modes only exist for GCC vector types if -maltivec. */
7216 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7217 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7220 /* Return synthetic vectors in memory. */
7221 if (TREE_CODE (type) == VECTOR_TYPE
7222 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7224 static bool warned_for_return_big_vectors = false;
7225 if (!warned_for_return_big_vectors)
7227 warning (0, "GCC vector returned by reference: "
7228 "non-standard ABI extension with no compatibility guarantee");
7229 warned_for_return_big_vectors = true;
7234 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7240 #ifdef HAVE_AS_GNU_ATTRIBUTE
7241 /* Return TRUE if a call to function FNDECL may be one that
7242 potentially affects the function calling ABI of the object file. */
7245 call_ABI_of_interest (tree fndecl)
7247 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7249 struct cgraph_node *c_node;
7251 /* Libcalls are always interesting. */
7252 if (fndecl == NULL_TREE)
7255 /* Any call to an external function is interesting. */
7256 if (DECL_EXTERNAL (fndecl))
7259 /* Interesting functions that we are emitting in this object file. */
7260 c_node = cgraph_get_node (fndecl);
7261 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7262 return !cgraph_only_called_directly_p (c_node);
7268 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7269 for a call to a function whose data type is FNTYPE.
7270 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7272 For incoming args we set the number of arguments in the prototype large
7273 so we never return a PARALLEL. */
7276 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7277 rtx libname ATTRIBUTE_UNUSED, int incoming,
7278 int libcall, int n_named_args,
7279 tree fndecl ATTRIBUTE_UNUSED,
7280 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7282 static CUMULATIVE_ARGS zero_cumulative;
7284 *cum = zero_cumulative;
7286 cum->fregno = FP_ARG_MIN_REG;
7287 cum->vregno = ALTIVEC_ARG_MIN_REG;
7288 cum->prototype = (fntype && prototype_p (fntype));
7289 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7290 ? CALL_LIBCALL : CALL_NORMAL);
7291 cum->sysv_gregno = GP_ARG_MIN_REG;
7292 cum->stdarg = stdarg_p (fntype);
7294 cum->nargs_prototype = 0;
7295 if (incoming || cum->prototype)
7296 cum->nargs_prototype = n_named_args;
7298 /* Check for a longcall attribute. */
7299 if ((!fntype && rs6000_default_long_calls)
7301 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7302 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7303 cum->call_cookie |= CALL_LONG;
7305 if (TARGET_DEBUG_ARG)
7307 fprintf (stderr, "\ninit_cumulative_args:");
7310 tree ret_type = TREE_TYPE (fntype);
7311 fprintf (stderr, " ret code = %s,",
7312 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7315 if (cum->call_cookie & CALL_LONG)
7316 fprintf (stderr, " longcall,");
7318 fprintf (stderr, " proto = %d, nargs = %d\n",
7319 cum->prototype, cum->nargs_prototype);
7322 #ifdef HAVE_AS_GNU_ATTRIBUTE
7323 if (DEFAULT_ABI == ABI_V4)
7325 cum->escapes = call_ABI_of_interest (fndecl);
7332 return_type = TREE_TYPE (fntype);
7333 return_mode = TYPE_MODE (return_type);
7336 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7338 if (return_type != NULL)
7340 if (TREE_CODE (return_type) == RECORD_TYPE
7341 && TYPE_TRANSPARENT_AGGR (return_type))
7343 return_type = TREE_TYPE (first_field (return_type));
7344 return_mode = TYPE_MODE (return_type);
7346 if (AGGREGATE_TYPE_P (return_type)
7347 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7349 rs6000_returns_struct = true;
7351 if (SCALAR_FLOAT_MODE_P (return_mode))
7352 rs6000_passes_float = true;
7353 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7354 || SPE_VECTOR_MODE (return_mode))
7355 rs6000_passes_vector = true;
7362 && TARGET_ALTIVEC_ABI
7363 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7365 error ("cannot return value in vector register because"
7366 " altivec instructions are disabled, use -maltivec"
7371 /* Return true if TYPE must be passed on the stack and not in registers. */
7374 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7376 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7377 return must_pass_in_stack_var_size (mode, type);
7379 return must_pass_in_stack_var_size_or_pad (mode, type);
7382 /* If defined, a C expression which determines whether, and in which
7383 direction, to pad out an argument with extra space. The value
7384 should be of type `enum direction': either `upward' to pad above
7385 the argument, `downward' to pad below, or `none' to inhibit
7388 For the AIX ABI structs are always stored left shifted in their
7392 function_arg_padding (enum machine_mode mode, const_tree type)
7394 #ifndef AGGREGATE_PADDING_FIXED
7395 #define AGGREGATE_PADDING_FIXED 0
7397 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7398 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7401 if (!AGGREGATE_PADDING_FIXED)
7403 /* GCC used to pass structures of the same size as integer types as
7404 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7405 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7406 passed padded downward, except that -mstrict-align further
7407 muddied the water in that multi-component structures of 2 and 4
7408 bytes in size were passed padded upward.
7410 The following arranges for best compatibility with previous
7411 versions of gcc, but removes the -mstrict-align dependency. */
7412 if (BYTES_BIG_ENDIAN)
7414 HOST_WIDE_INT size = 0;
7416 if (mode == BLKmode)
7418 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7419 size = int_size_in_bytes (type);
7422 size = GET_MODE_SIZE (mode);
7424 if (size == 1 || size == 2 || size == 4)
7430 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7432 if (type != 0 && AGGREGATE_TYPE_P (type))
7436 /* Fall back to the default. */
7437 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7440 /* If defined, a C expression that gives the alignment boundary, in bits,
7441 of an argument with the specified mode and type. If it is not defined,
7442 PARM_BOUNDARY is used for all arguments.
7444 V.4 wants long longs and doubles to be double word aligned. Just
7445 testing the mode size is a boneheaded way to do this as it means
7446 that other types such as complex int are also double word aligned.
7447 However, we're stuck with this because changing the ABI might break
7448 existing library interfaces.
7450 Doubleword align SPE vectors.
7451 Quadword align Altivec/VSX vectors.
7452 Quadword align large synthetic vector types. */
7455 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7457 if (DEFAULT_ABI == ABI_V4
7458 && (GET_MODE_SIZE (mode) == 8
7459 || (TARGET_HARD_FLOAT
7461 && (mode == TFmode || mode == TDmode))))
7463 else if (SPE_VECTOR_MODE (mode)
7464 || (type && TREE_CODE (type) == VECTOR_TYPE
7465 && int_size_in_bytes (type) >= 8
7466 && int_size_in_bytes (type) < 16))
7468 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7469 || (type && TREE_CODE (type) == VECTOR_TYPE
7470 && int_size_in_bytes (type) >= 16))
7472 else if (TARGET_MACHO
7473 && rs6000_darwin64_abi
7475 && type && TYPE_ALIGN (type) > 64)
7478 return PARM_BOUNDARY;
7481 /* For a function parm of MODE and TYPE, return the starting word in
7482 the parameter area. NWORDS of the parameter area are already used. */
7485 rs6000_parm_start (enum machine_mode mode, const_tree type,
7486 unsigned int nwords)
7489 unsigned int parm_offset;
7491 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7492 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7493 return nwords + (-(parm_offset + nwords) & align);
7496 /* Compute the size (in words) of a function argument. */
7498 static unsigned long
7499 rs6000_arg_size (enum machine_mode mode, const_tree type)
7503 if (mode != BLKmode)
7504 size = GET_MODE_SIZE (mode);
7506 size = int_size_in_bytes (type);
7509 return (size + 3) >> 2;
7511 return (size + 7) >> 3;
7514 /* Use this to flush pending int fields. */
7517 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7518 HOST_WIDE_INT bitpos, int final)
7520 unsigned int startbit, endbit;
7521 int intregs, intoffset;
7522 enum machine_mode mode;
7524 /* Handle the situations where a float is taking up the first half
7525 of the GPR, and the other half is empty (typically due to
7526 alignment restrictions). We can detect this by a 8-byte-aligned
7527 int field, or by seeing that this is the final flush for this
7528 argument. Count the word and continue on. */
7529 if (cum->floats_in_gpr == 1
7530 && (cum->intoffset % 64 == 0
7531 || (cum->intoffset == -1 && final)))
7534 cum->floats_in_gpr = 0;
7537 if (cum->intoffset == -1)
7540 intoffset = cum->intoffset;
7541 cum->intoffset = -1;
7542 cum->floats_in_gpr = 0;
7544 if (intoffset % BITS_PER_WORD != 0)
7546 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7548 if (mode == BLKmode)
7550 /* We couldn't find an appropriate mode, which happens,
7551 e.g., in packed structs when there are 3 bytes to load.
7552 Back intoffset back to the beginning of the word in this
7554 intoffset = intoffset & -BITS_PER_WORD;
7558 startbit = intoffset & -BITS_PER_WORD;
7559 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7560 intregs = (endbit - startbit) / BITS_PER_WORD;
7561 cum->words += intregs;
7562 /* words should be unsigned. */
7563 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7565 int pad = (endbit/BITS_PER_WORD) - cum->words;
7570 /* The darwin64 ABI calls for us to recurse down through structs,
7571 looking for elements passed in registers. Unfortunately, we have
7572 to track int register count here also because of misalignments
7573 in powerpc alignment mode. */
7576 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7578 HOST_WIDE_INT startbitpos)
7582 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7583 if (TREE_CODE (f) == FIELD_DECL)
7585 HOST_WIDE_INT bitpos = startbitpos;
7586 tree ftype = TREE_TYPE (f);
7587 enum machine_mode mode;
7588 if (ftype == error_mark_node)
7590 mode = TYPE_MODE (ftype);
7592 if (DECL_SIZE (f) != 0
7593 && host_integerp (bit_position (f), 1))
7594 bitpos += int_bit_position (f);
7596 /* ??? FIXME: else assume zero offset. */
7598 if (TREE_CODE (ftype) == RECORD_TYPE)
7599 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7600 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7602 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7603 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7604 cum->fregno += n_fpregs;
7605 /* Single-precision floats present a special problem for
7606 us, because they are smaller than an 8-byte GPR, and so
7607 the structure-packing rules combined with the standard
7608 varargs behavior mean that we want to pack float/float
7609 and float/int combinations into a single register's
7610 space. This is complicated by the arg advance flushing,
7611 which works on arbitrarily large groups of int-type
7615 if (cum->floats_in_gpr == 1)
7617 /* Two floats in a word; count the word and reset
7620 cum->floats_in_gpr = 0;
7622 else if (bitpos % 64 == 0)
7624 /* A float at the beginning of an 8-byte word;
7625 count it and put off adjusting cum->words until
7626 we see if a arg advance flush is going to do it
7628 cum->floats_in_gpr++;
7632 /* The float is at the end of a word, preceded
7633 by integer fields, so the arg advance flush
7634 just above has already set cum->words and
7635 everything is taken care of. */
7639 cum->words += n_fpregs;
7641 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7643 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7647 else if (cum->intoffset == -1)
7648 cum->intoffset = bitpos;
7652 /* Check for an item that needs to be considered specially under the darwin 64
7653 bit ABI. These are record types where the mode is BLK or the structure is
7656 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7658 return rs6000_darwin64_abi
7659 && ((mode == BLKmode
7660 && TREE_CODE (type) == RECORD_TYPE
7661 && int_size_in_bytes (type) > 0)
7662 || (type && TREE_CODE (type) == RECORD_TYPE
7663 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7666 /* Update the data in CUM to advance over an argument
7667 of mode MODE and data type TYPE.
7668 (TYPE is null for libcalls where that information may not be available.)
7670 Note that for args passed by reference, function_arg will be called
7671 with MODE and TYPE set to that of the pointer to the arg, not the arg
7675 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7676 const_tree type, bool named, int depth)
7678 /* Only tick off an argument if we're not recursing. */
7680 cum->nargs_prototype--;
7682 #ifdef HAVE_AS_GNU_ATTRIBUTE
7683 if (DEFAULT_ABI == ABI_V4
7686 if (SCALAR_FLOAT_MODE_P (mode))
7687 rs6000_passes_float = true;
7688 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7689 rs6000_passes_vector = true;
7690 else if (SPE_VECTOR_MODE (mode)
7692 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7693 rs6000_passes_vector = true;
7697 if (TARGET_ALTIVEC_ABI
7698 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7699 || (type && TREE_CODE (type) == VECTOR_TYPE
7700 && int_size_in_bytes (type) == 16)))
7704 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7707 if (!TARGET_ALTIVEC)
7708 error ("cannot pass argument in vector register because"
7709 " altivec instructions are disabled, use -maltivec"
7712 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7713 even if it is going to be passed in a vector register.
7714 Darwin does the same for variable-argument functions. */
7715 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7716 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7726 /* Vector parameters must be 16-byte aligned. This places
7727 them at 2 mod 4 in terms of words in 32-bit mode, since
7728 the parameter save area starts at offset 24 from the
7729 stack. In 64-bit mode, they just have to start on an
7730 even word, since the parameter save area is 16-byte
7731 aligned. Space for GPRs is reserved even if the argument
7732 will be passed in memory. */
7734 align = (2 - cum->words) & 3;
7736 align = cum->words & 1;
7737 cum->words += align + rs6000_arg_size (mode, type);
7739 if (TARGET_DEBUG_ARG)
7741 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7743 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7744 cum->nargs_prototype, cum->prototype,
7745 GET_MODE_NAME (mode));
7749 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7751 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7754 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7756 int size = int_size_in_bytes (type);
7757 /* Variable sized types have size == -1 and are
7758 treated as if consisting entirely of ints.
7759 Pad to 16 byte boundary if needed. */
7760 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7761 && (cum->words % 2) != 0)
7763 /* For varargs, we can just go up by the size of the struct. */
7765 cum->words += (size + 7) / 8;
7768 /* It is tempting to say int register count just goes up by
7769 sizeof(type)/8, but this is wrong in a case such as
7770 { int; double; int; } [powerpc alignment]. We have to
7771 grovel through the fields for these too. */
7773 cum->floats_in_gpr = 0;
7774 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7775 rs6000_darwin64_record_arg_advance_flush (cum,
7776 size * BITS_PER_UNIT, 1);
7778 if (TARGET_DEBUG_ARG)
7780 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7781 cum->words, TYPE_ALIGN (type), size);
7783 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7784 cum->nargs_prototype, cum->prototype,
7785 GET_MODE_NAME (mode));
7788 else if (DEFAULT_ABI == ABI_V4)
7790 if (TARGET_HARD_FLOAT && TARGET_FPRS
7791 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
7792 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
7793 || (mode == TFmode && !TARGET_IEEEQUAD)
7794 || mode == SDmode || mode == DDmode || mode == TDmode))
7796 /* _Decimal128 must use an even/odd register pair. This assumes
7797 that the register number is odd when fregno is odd. */
7798 if (mode == TDmode && (cum->fregno % 2) == 1)
7801 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
7802 <= FP_ARG_V4_MAX_REG)
7803 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7806 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7807 if (mode == DFmode || mode == TFmode
7808 || mode == DDmode || mode == TDmode)
7809 cum->words += cum->words & 1;
7810 cum->words += rs6000_arg_size (mode, type);
7815 int n_words = rs6000_arg_size (mode, type);
7816 int gregno = cum->sysv_gregno;
7818 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
7819 (r7,r8) or (r9,r10). As does any other 2 word item such
7820 as complex int due to a historical mistake. */
7822 gregno += (1 - gregno) & 1;
7824 /* Multi-reg args are not split between registers and stack. */
7825 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7827 /* Long long and SPE vectors are aligned on the stack.
7828 So are other 2 word items such as complex int due to
7829 a historical mistake. */
7831 cum->words += cum->words & 1;
7832 cum->words += n_words;
7835 /* Note: continuing to accumulate gregno past when we've started
7836 spilling to the stack indicates the fact that we've started
7837 spilling to the stack to expand_builtin_saveregs. */
7838 cum->sysv_gregno = gregno + n_words;
7841 if (TARGET_DEBUG_ARG)
7843 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7844 cum->words, cum->fregno);
7845 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7846 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7847 fprintf (stderr, "mode = %4s, named = %d\n",
7848 GET_MODE_NAME (mode), named);
7853 int n_words = rs6000_arg_size (mode, type);
7854 int start_words = cum->words;
7855 int align_words = rs6000_parm_start (mode, type, start_words);
7857 cum->words = align_words + n_words;
7859 if (SCALAR_FLOAT_MODE_P (mode)
7860 && TARGET_HARD_FLOAT && TARGET_FPRS)
7862 /* _Decimal128 must be passed in an even/odd float register pair.
7863 This assumes that the register number is odd when fregno is
7865 if (mode == TDmode && (cum->fregno % 2) == 1)
7867 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7870 if (TARGET_DEBUG_ARG)
7872 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7873 cum->words, cum->fregno);
7874 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
7875 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
7876 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
7877 named, align_words - start_words, depth);
7883 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
7884 const_tree type, bool named)
7886 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
7891 spe_build_register_parallel (enum machine_mode mode, int gregno)
7898 r1 = gen_rtx_REG (DImode, gregno);
7899 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7900 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
7904 r1 = gen_rtx_REG (DImode, gregno);
7905 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7906 r3 = gen_rtx_REG (DImode, gregno + 2);
7907 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
7908 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
7911 r1 = gen_rtx_REG (DImode, gregno);
7912 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
7913 r3 = gen_rtx_REG (DImode, gregno + 2);
7914 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
7915 r5 = gen_rtx_REG (DImode, gregno + 4);
7916 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
7917 r7 = gen_rtx_REG (DImode, gregno + 6);
7918 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
7919 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
7926 /* Determine where to put a SIMD argument on the SPE. */
7928 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7931 int gregno = cum->sysv_gregno;
7933 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
7934 are passed and returned in a pair of GPRs for ABI compatibility. */
7935 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
7936 || mode == DCmode || mode == TCmode))
7938 int n_words = rs6000_arg_size (mode, type);
7940 /* Doubles go in an odd/even register pair (r5/r6, etc). */
7942 gregno += (1 - gregno) & 1;
7944 /* Multi-reg args are not split between registers and stack. */
7945 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7948 return spe_build_register_parallel (mode, gregno);
7952 int n_words = rs6000_arg_size (mode, type);
7954 /* SPE vectors are put in odd registers. */
7955 if (n_words == 2 && (gregno & 1) == 0)
7958 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
7961 enum machine_mode m = SImode;
7963 r1 = gen_rtx_REG (m, gregno);
7964 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
7965 r2 = gen_rtx_REG (m, gregno + 1);
7966 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
7967 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
7974 if (gregno <= GP_ARG_MAX_REG)
7975 return gen_rtx_REG (mode, gregno);
7981 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
7982 structure between cum->intoffset and bitpos to integer registers. */
7985 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
7986 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
7988 enum machine_mode mode;
7990 unsigned int startbit, endbit;
7991 int this_regno, intregs, intoffset;
7994 if (cum->intoffset == -1)
7997 intoffset = cum->intoffset;
7998 cum->intoffset = -1;
8000 /* If this is the trailing part of a word, try to only load that
8001 much into the register. Otherwise load the whole register. Note
8002 that in the latter case we may pick up unwanted bits. It's not a
8003 problem at the moment but may wish to revisit. */
8005 if (intoffset % BITS_PER_WORD != 0)
8007 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8009 if (mode == BLKmode)
8011 /* We couldn't find an appropriate mode, which happens,
8012 e.g., in packed structs when there are 3 bytes to load.
8013 Back intoffset back to the beginning of the word in this
8015 intoffset = intoffset & -BITS_PER_WORD;
8022 startbit = intoffset & -BITS_PER_WORD;
8023 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8024 intregs = (endbit - startbit) / BITS_PER_WORD;
8025 this_regno = cum->words + intoffset / BITS_PER_WORD;
8027 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8030 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8034 intoffset /= BITS_PER_UNIT;
8037 regno = GP_ARG_MIN_REG + this_regno;
8038 reg = gen_rtx_REG (mode, regno);
8040 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8043 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8047 while (intregs > 0);
8050 /* Recursive workhorse for the following. */
8053 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8054 HOST_WIDE_INT startbitpos, rtx rvec[],
8059 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8060 if (TREE_CODE (f) == FIELD_DECL)
8062 HOST_WIDE_INT bitpos = startbitpos;
8063 tree ftype = TREE_TYPE (f);
8064 enum machine_mode mode;
8065 if (ftype == error_mark_node)
8067 mode = TYPE_MODE (ftype);
8069 if (DECL_SIZE (f) != 0
8070 && host_integerp (bit_position (f), 1))
8071 bitpos += int_bit_position (f);
8073 /* ??? FIXME: else assume zero offset. */
8075 if (TREE_CODE (ftype) == RECORD_TYPE)
8076 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8077 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8079 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8083 case SCmode: mode = SFmode; break;
8084 case DCmode: mode = DFmode; break;
8085 case TCmode: mode = TFmode; break;
8089 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8090 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8092 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8093 && (mode == TFmode || mode == TDmode));
8094 /* Long double or _Decimal128 split over regs and memory. */
8095 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8099 = gen_rtx_EXPR_LIST (VOIDmode,
8100 gen_rtx_REG (mode, cum->fregno++),
8101 GEN_INT (bitpos / BITS_PER_UNIT));
8102 if (mode == TFmode || mode == TDmode)
8105 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8107 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8109 = gen_rtx_EXPR_LIST (VOIDmode,
8110 gen_rtx_REG (mode, cum->vregno++),
8111 GEN_INT (bitpos / BITS_PER_UNIT));
8113 else if (cum->intoffset == -1)
8114 cum->intoffset = bitpos;
8118 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8119 the register(s) to be used for each field and subfield of a struct
8120 being passed by value, along with the offset of where the
8121 register's value may be found in the block. FP fields go in FP
8122 register, vector fields go in vector registers, and everything
8123 else goes in int registers, packed as in memory.
8125 This code is also used for function return values. RETVAL indicates
8126 whether this is the case.
8128 Much of this is taken from the SPARC V9 port, which has a similar
8129 calling convention. */
8132 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8133 bool named, bool retval)
8135 rtx rvec[FIRST_PSEUDO_REGISTER];
8136 int k = 1, kbase = 1;
8137 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8138 /* This is a copy; modifications are not visible to our caller. */
8139 CUMULATIVE_ARGS copy_cum = *orig_cum;
8140 CUMULATIVE_ARGS *cum = ©_cum;
8142 /* Pad to 16 byte boundary if needed. */
8143 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8144 && (cum->words % 2) != 0)
8151 /* Put entries into rvec[] for individual FP and vector fields, and
8152 for the chunks of memory that go in int regs. Note we start at
8153 element 1; 0 is reserved for an indication of using memory, and
8154 may or may not be filled in below. */
8155 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8156 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8158 /* If any part of the struct went on the stack put all of it there.
8159 This hack is because the generic code for
8160 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8161 parts of the struct are not at the beginning. */
8165 return NULL_RTX; /* doesn't go in registers at all */
8167 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8169 if (k > 1 || cum->use_stack)
8170 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8175 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8178 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8183 rtx rvec[GP_ARG_NUM_REG + 1];
8185 if (align_words >= GP_ARG_NUM_REG)
8188 n_units = rs6000_arg_size (mode, type);
8190 /* Optimize the simple case where the arg fits in one gpr, except in
8191 the case of BLKmode due to assign_parms assuming that registers are
8192 BITS_PER_WORD wide. */
8194 || (n_units == 1 && mode != BLKmode))
8195 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8198 if (align_words + n_units > GP_ARG_NUM_REG)
8199 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8200 using a magic NULL_RTX component.
8201 This is not strictly correct. Only some of the arg belongs in
8202 memory, not all of it. However, the normal scheme using
8203 function_arg_partial_nregs can result in unusual subregs, eg.
8204 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8205 store the whole arg to memory is often more efficient than code
8206 to store pieces, and we know that space is available in the right
8207 place for the whole arg. */
8208 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8213 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8214 rtx off = GEN_INT (i++ * 4);
8215 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8217 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8219 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8222 /* Determine where to put an argument to a function.
8223 Value is zero to push the argument on the stack,
8224 or a hard register in which to store the argument.
8226 MODE is the argument's machine mode.
8227 TYPE is the data type of the argument (as a tree).
8228 This is null for libcalls where that information may
8230 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8231 the preceding args and about the function being called. It is
8232 not modified in this routine.
8233 NAMED is nonzero if this argument is a named parameter
8234 (otherwise it is an extra parameter matching an ellipsis).
8236 On RS/6000 the first eight words of non-FP are normally in registers
8237 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8238 Under V.4, the first 8 FP args are in registers.
8240 If this is floating-point and no prototype is specified, we use
8241 both an FP and integer register (or possibly FP reg and stack). Library
8242 functions (when CALL_LIBCALL is set) always have the proper types for args,
8243 so we can pass the FP value just in one register. emit_library_function
8244 doesn't support PARALLEL anyway.
8246 Note that for args passed by reference, function_arg will be called
8247 with MODE and TYPE set to that of the pointer to the arg, not the arg
8251 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8252 const_tree type, bool named)
8254 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8255 enum rs6000_abi abi = DEFAULT_ABI;
8257 /* Return a marker to indicate whether CR1 needs to set or clear the
8258 bit that V.4 uses to say fp args were passed in registers.
8259 Assume that we don't need the marker for software floating point,
8260 or compiler generated library calls. */
8261 if (mode == VOIDmode)
8264 && (cum->call_cookie & CALL_LIBCALL) == 0
8266 || (cum->nargs_prototype < 0
8267 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8269 /* For the SPE, we need to crxor CR6 always. */
8271 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8272 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8273 return GEN_INT (cum->call_cookie
8274 | ((cum->fregno == FP_ARG_MIN_REG)
8275 ? CALL_V4_SET_FP_ARGS
8276 : CALL_V4_CLEAR_FP_ARGS));
8279 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8282 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8284 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8285 if (rslt != NULL_RTX)
8287 /* Else fall through to usual handling. */
8290 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8291 if (TARGET_64BIT && ! cum->prototype)
8293 /* Vector parameters get passed in vector register
8294 and also in GPRs or memory, in absence of prototype. */
8297 align_words = (cum->words + 1) & ~1;
8299 if (align_words >= GP_ARG_NUM_REG)
8305 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8307 return gen_rtx_PARALLEL (mode,
8309 gen_rtx_EXPR_LIST (VOIDmode,
8311 gen_rtx_EXPR_LIST (VOIDmode,
8312 gen_rtx_REG (mode, cum->vregno),
8316 return gen_rtx_REG (mode, cum->vregno);
8317 else if (TARGET_ALTIVEC_ABI
8318 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8319 || (type && TREE_CODE (type) == VECTOR_TYPE
8320 && int_size_in_bytes (type) == 16)))
8322 if (named || abi == ABI_V4)
8326 /* Vector parameters to varargs functions under AIX or Darwin
8327 get passed in memory and possibly also in GPRs. */
8328 int align, align_words, n_words;
8329 enum machine_mode part_mode;
8331 /* Vector parameters must be 16-byte aligned. This places them at
8332 2 mod 4 in terms of words in 32-bit mode, since the parameter
8333 save area starts at offset 24 from the stack. In 64-bit mode,
8334 they just have to start on an even word, since the parameter
8335 save area is 16-byte aligned. */
8337 align = (2 - cum->words) & 3;
8339 align = cum->words & 1;
8340 align_words = cum->words + align;
8342 /* Out of registers? Memory, then. */
8343 if (align_words >= GP_ARG_NUM_REG)
8346 if (TARGET_32BIT && TARGET_POWERPC64)
8347 return rs6000_mixed_function_arg (mode, type, align_words);
8349 /* The vector value goes in GPRs. Only the part of the
8350 value in GPRs is reported here. */
8352 n_words = rs6000_arg_size (mode, type);
8353 if (align_words + n_words > GP_ARG_NUM_REG)
8354 /* Fortunately, there are only two possibilities, the value
8355 is either wholly in GPRs or half in GPRs and half not. */
8358 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8361 else if (TARGET_SPE_ABI && TARGET_SPE
8362 && (SPE_VECTOR_MODE (mode)
8363 || (TARGET_E500_DOUBLE && (mode == DFmode
8366 || mode == TCmode))))
8367 return rs6000_spe_function_arg (cum, mode, type);
8369 else if (abi == ABI_V4)
8371 if (TARGET_HARD_FLOAT && TARGET_FPRS
8372 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8373 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8374 || (mode == TFmode && !TARGET_IEEEQUAD)
8375 || mode == SDmode || mode == DDmode || mode == TDmode))
8377 /* _Decimal128 must use an even/odd register pair. This assumes
8378 that the register number is odd when fregno is odd. */
8379 if (mode == TDmode && (cum->fregno % 2) == 1)
8382 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8383 <= FP_ARG_V4_MAX_REG)
8384 return gen_rtx_REG (mode, cum->fregno);
8390 int n_words = rs6000_arg_size (mode, type);
8391 int gregno = cum->sysv_gregno;
8393 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8394 (r7,r8) or (r9,r10). As does any other 2 word item such
8395 as complex int due to a historical mistake. */
8397 gregno += (1 - gregno) & 1;
8399 /* Multi-reg args are not split between registers and stack. */
8400 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8403 if (TARGET_32BIT && TARGET_POWERPC64)
8404 return rs6000_mixed_function_arg (mode, type,
8405 gregno - GP_ARG_MIN_REG);
8406 return gen_rtx_REG (mode, gregno);
8411 int align_words = rs6000_parm_start (mode, type, cum->words);
8413 /* _Decimal128 must be passed in an even/odd float register pair.
8414 This assumes that the register number is odd when fregno is odd. */
8415 if (mode == TDmode && (cum->fregno % 2) == 1)
8418 if (USE_FP_FOR_ARG_P (cum, mode, type))
8420 rtx rvec[GP_ARG_NUM_REG + 1];
8424 enum machine_mode fmode = mode;
8425 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8427 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8429 /* Currently, we only ever need one reg here because complex
8430 doubles are split. */
8431 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8432 && (fmode == TFmode || fmode == TDmode));
8434 /* Long double or _Decimal128 split over regs and memory. */
8435 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8438 /* Do we also need to pass this arg in the parameter save
8441 && (cum->nargs_prototype <= 0
8442 || (DEFAULT_ABI == ABI_AIX
8444 && align_words >= GP_ARG_NUM_REG)));
8446 if (!needs_psave && mode == fmode)
8447 return gen_rtx_REG (fmode, cum->fregno);
8452 /* Describe the part that goes in gprs or the stack.
8453 This piece must come first, before the fprs. */
8454 if (align_words < GP_ARG_NUM_REG)
8456 unsigned long n_words = rs6000_arg_size (mode, type);
8458 if (align_words + n_words > GP_ARG_NUM_REG
8459 || (TARGET_32BIT && TARGET_POWERPC64))
8461 /* If this is partially on the stack, then we only
8462 include the portion actually in registers here. */
8463 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8466 if (align_words + n_words > GP_ARG_NUM_REG)
8467 /* Not all of the arg fits in gprs. Say that it
8468 goes in memory too, using a magic NULL_RTX
8469 component. Also see comment in
8470 rs6000_mixed_function_arg for why the normal
8471 function_arg_partial_nregs scheme doesn't work
8473 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8477 r = gen_rtx_REG (rmode,
8478 GP_ARG_MIN_REG + align_words);
8479 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8480 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8482 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8486 /* The whole arg fits in gprs. */
8487 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8488 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8492 /* It's entirely in memory. */
8493 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8496 /* Describe where this piece goes in the fprs. */
8497 r = gen_rtx_REG (fmode, cum->fregno);
8498 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8500 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8502 else if (align_words < GP_ARG_NUM_REG)
8504 if (TARGET_32BIT && TARGET_POWERPC64)
8505 return rs6000_mixed_function_arg (mode, type, align_words);
8507 if (mode == BLKmode)
8510 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8517 /* For an arg passed partly in registers and partly in memory, this is
8518 the number of bytes passed in registers. For args passed entirely in
8519 registers or entirely in memory, zero. When an arg is described by a
8520 PARALLEL, perhaps using more than one register type, this function
8521 returns the number of bytes used by the first element of the PARALLEL. */
8524 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8525 tree type, bool named)
8527 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8531 if (DEFAULT_ABI == ABI_V4)
8534 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8535 && cum->nargs_prototype >= 0)
8538 /* In this complicated case we just disable the partial_nregs code. */
8539 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8542 align_words = rs6000_parm_start (mode, type, cum->words);
8544 if (USE_FP_FOR_ARG_P (cum, mode, type))
8546 /* If we are passing this arg in the fixed parameter save area
8547 (gprs or memory) as well as fprs, then this function should
8548 return the number of partial bytes passed in the parameter
8549 save area rather than partial bytes passed in fprs. */
8551 && (cum->nargs_prototype <= 0
8552 || (DEFAULT_ABI == ABI_AIX
8554 && align_words >= GP_ARG_NUM_REG)))
8556 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8557 > FP_ARG_MAX_REG + 1)
8558 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8559 else if (cum->nargs_prototype >= 0)
8563 if (align_words < GP_ARG_NUM_REG
8564 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8565 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8567 if (ret != 0 && TARGET_DEBUG_ARG)
8568 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8573 /* A C expression that indicates when an argument must be passed by
8574 reference. If nonzero for an argument, a copy of that argument is
8575 made in memory and a pointer to the argument is passed instead of
8576 the argument itself. The pointer is passed in whatever way is
8577 appropriate for passing a pointer to that type.
8579 Under V.4, aggregates and long double are passed by reference.
8581 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8582 reference unless the AltiVec vector extension ABI is in force.
8584 As an extension to all ABIs, variable sized types are passed by
8588 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8589 enum machine_mode mode, const_tree type,
8590 bool named ATTRIBUTE_UNUSED)
8592 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8594 if (TARGET_DEBUG_ARG)
8595 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8602 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8604 if (TARGET_DEBUG_ARG)
8605 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8609 if (int_size_in_bytes (type) < 0)
8611 if (TARGET_DEBUG_ARG)
8612 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8616 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8617 modes only exist for GCC vector types if -maltivec. */
8618 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8620 if (TARGET_DEBUG_ARG)
8621 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8625 /* Pass synthetic vectors in memory. */
8626 if (TREE_CODE (type) == VECTOR_TYPE
8627 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8629 static bool warned_for_pass_big_vectors = false;
8630 if (TARGET_DEBUG_ARG)
8631 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8632 if (!warned_for_pass_big_vectors)
8634 warning (0, "GCC vector passed by reference: "
8635 "non-standard ABI extension with no compatibility guarantee");
8636 warned_for_pass_big_vectors = true;
8645 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8648 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8653 for (i = 0; i < nregs; i++)
8655 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8656 if (reload_completed)
8658 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8661 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8662 i * GET_MODE_SIZE (reg_mode));
8665 tem = replace_equiv_address (tem, XEXP (tem, 0));
8669 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8673 /* Perform any needed actions needed for a function that is receiving a
8674 variable number of arguments.
8678 MODE and TYPE are the mode and type of the current parameter.
8680 PRETEND_SIZE is a variable that should be set to the amount of stack
8681 that must be pushed by the prolog to pretend that our caller pushed
8684 Normally, this macro will push all remaining incoming registers on the
8685 stack and set PRETEND_SIZE to the length of the registers pushed. */
8688 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8689 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8692 CUMULATIVE_ARGS next_cum;
8693 int reg_size = TARGET_32BIT ? 4 : 8;
8694 rtx save_area = NULL_RTX, mem;
8695 int first_reg_offset;
8698 /* Skip the last named argument. */
8699 next_cum = *get_cumulative_args (cum);
8700 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8702 if (DEFAULT_ABI == ABI_V4)
8704 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8708 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8709 HOST_WIDE_INT offset = 0;
8711 /* Try to optimize the size of the varargs save area.
8712 The ABI requires that ap.reg_save_area is doubleword
8713 aligned, but we don't need to allocate space for all
8714 the bytes, only those to which we actually will save
8716 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8717 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8718 if (TARGET_HARD_FLOAT && TARGET_FPRS
8719 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8720 && cfun->va_list_fpr_size)
8723 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8724 * UNITS_PER_FP_WORD;
8725 if (cfun->va_list_fpr_size
8726 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8727 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8729 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8730 * UNITS_PER_FP_WORD;
8734 offset = -((first_reg_offset * reg_size) & ~7);
8735 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8737 gpr_reg_num = cfun->va_list_gpr_size;
8738 if (reg_size == 4 && (first_reg_offset & 1))
8741 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8744 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8746 - (int) (GP_ARG_NUM_REG * reg_size);
8748 if (gpr_size + fpr_size)
8751 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8752 gcc_assert (GET_CODE (reg_save_area) == MEM);
8753 reg_save_area = XEXP (reg_save_area, 0);
8754 if (GET_CODE (reg_save_area) == PLUS)
8756 gcc_assert (XEXP (reg_save_area, 0)
8757 == virtual_stack_vars_rtx);
8758 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
8759 offset += INTVAL (XEXP (reg_save_area, 1));
8762 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8765 cfun->machine->varargs_save_offset = offset;
8766 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
8771 first_reg_offset = next_cum.words;
8772 save_area = virtual_incoming_args_rtx;
8774 if (targetm.calls.must_pass_in_stack (mode, type))
8775 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
8778 set = get_varargs_alias_set ();
8779 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8780 && cfun->va_list_gpr_size)
8782 int nregs = GP_ARG_NUM_REG - first_reg_offset;
8784 if (va_list_gpr_counter_field)
8786 /* V4 va_list_gpr_size counts number of registers needed. */
8787 if (nregs > cfun->va_list_gpr_size)
8788 nregs = cfun->va_list_gpr_size;
8792 /* char * va_list instead counts number of bytes needed. */
8793 if (nregs > cfun->va_list_gpr_size / reg_size)
8794 nregs = cfun->va_list_gpr_size / reg_size;
8797 mem = gen_rtx_MEM (BLKmode,
8798 plus_constant (Pmode, save_area,
8799 first_reg_offset * reg_size));
8800 MEM_NOTRAP_P (mem) = 1;
8801 set_mem_alias_set (mem, set);
8802 set_mem_align (mem, BITS_PER_WORD);
8804 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8808 /* Save FP registers if needed. */
8809 if (DEFAULT_ABI == ABI_V4
8810 && TARGET_HARD_FLOAT && TARGET_FPRS
8812 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8813 && cfun->va_list_fpr_size)
8815 int fregno = next_cum.fregno, nregs;
8816 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8817 rtx lab = gen_label_rtx ();
8818 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8819 * UNITS_PER_FP_WORD);
8822 (gen_rtx_SET (VOIDmode,
8824 gen_rtx_IF_THEN_ELSE (VOIDmode,
8825 gen_rtx_NE (VOIDmode, cr1,
8827 gen_rtx_LABEL_REF (VOIDmode, lab),
8831 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8832 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8834 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8836 plus_constant (Pmode, save_area, off));
8837 MEM_NOTRAP_P (mem) = 1;
8838 set_mem_alias_set (mem, set);
8839 set_mem_align (mem, GET_MODE_ALIGNMENT (
8840 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8841 ? DFmode : SFmode));
8842 emit_move_insn (mem, gen_rtx_REG (
8843 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8844 ? DFmode : SFmode, fregno));
8851 /* Create the va_list data type. */
8854 rs6000_build_builtin_va_list (void)
8856 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8858 /* For AIX, prefer 'char *' because that's what the system
8859 header files like. */
8860 if (DEFAULT_ABI != ABI_V4)
8861 return build_pointer_type (char_type_node);
8863 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
8864 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
8865 get_identifier ("__va_list_tag"), record);
8867 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
8868 unsigned_char_type_node);
8869 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
8870 unsigned_char_type_node);
8871 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
8873 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8874 get_identifier ("reserved"), short_unsigned_type_node);
8875 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8876 get_identifier ("overflow_arg_area"),
8878 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8879 get_identifier ("reg_save_area"),
8882 va_list_gpr_counter_field = f_gpr;
8883 va_list_fpr_counter_field = f_fpr;
8885 DECL_FIELD_CONTEXT (f_gpr) = record;
8886 DECL_FIELD_CONTEXT (f_fpr) = record;
8887 DECL_FIELD_CONTEXT (f_res) = record;
8888 DECL_FIELD_CONTEXT (f_ovf) = record;
8889 DECL_FIELD_CONTEXT (f_sav) = record;
8891 TYPE_STUB_DECL (record) = type_decl;
8892 TYPE_NAME (record) = type_decl;
8893 TYPE_FIELDS (record) = f_gpr;
8894 DECL_CHAIN (f_gpr) = f_fpr;
8895 DECL_CHAIN (f_fpr) = f_res;
8896 DECL_CHAIN (f_res) = f_ovf;
8897 DECL_CHAIN (f_ovf) = f_sav;
8899 layout_type (record);
8901 /* The correct type is an array type of one element. */
8902 return build_array_type (record, build_index_type (size_zero_node));
8905 /* Implement va_start. */
8908 rs6000_va_start (tree valist, rtx nextarg)
8910 HOST_WIDE_INT words, n_gpr, n_fpr;
8911 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8912 tree gpr, fpr, ovf, sav, t;
8914 /* Only SVR4 needs something special. */
8915 if (DEFAULT_ABI != ABI_V4)
8917 std_expand_builtin_va_start (valist, nextarg);
8921 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8922 f_fpr = DECL_CHAIN (f_gpr);
8923 f_res = DECL_CHAIN (f_fpr);
8924 f_ovf = DECL_CHAIN (f_res);
8925 f_sav = DECL_CHAIN (f_ovf);
8927 valist = build_simple_mem_ref (valist);
8928 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8929 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8931 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8933 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8936 /* Count number of gp and fp argument registers used. */
8937 words = crtl->args.info.words;
8938 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
8940 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
8943 if (TARGET_DEBUG_ARG)
8944 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
8945 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
8946 words, n_gpr, n_fpr);
8948 if (cfun->va_list_gpr_size)
8950 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8951 build_int_cst (NULL_TREE, n_gpr));
8952 TREE_SIDE_EFFECTS (t) = 1;
8953 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8956 if (cfun->va_list_fpr_size)
8958 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8959 build_int_cst (NULL_TREE, n_fpr));
8960 TREE_SIDE_EFFECTS (t) = 1;
8961 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8963 #ifdef HAVE_AS_GNU_ATTRIBUTE
8964 if (call_ABI_of_interest (cfun->decl))
8965 rs6000_passes_float = true;
8969 /* Find the overflow area. */
8970 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8972 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
8973 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8974 TREE_SIDE_EFFECTS (t) = 1;
8975 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8977 /* If there were no va_arg invocations, don't set up the register
8979 if (!cfun->va_list_gpr_size
8980 && !cfun->va_list_fpr_size
8981 && n_gpr < GP_ARG_NUM_REG
8982 && n_fpr < FP_ARG_V4_MAX_REG)
8985 /* Find the register save area. */
8986 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
8987 if (cfun->machine->varargs_save_offset)
8988 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
8989 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8990 TREE_SIDE_EFFECTS (t) = 1;
8991 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8994 /* Implement va_arg. */
8997 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9000 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9001 tree gpr, fpr, ovf, sav, reg, t, u;
9002 int size, rsize, n_reg, sav_ofs, sav_scale;
9003 tree lab_false, lab_over, addr;
9005 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9009 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9011 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9012 return build_va_arg_indirect_ref (t);
9015 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9016 earlier version of gcc, with the property that it always applied alignment
9017 adjustments to the va-args (even for zero-sized types). The cheapest way
9018 to deal with this is to replicate the effect of the part of
9019 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9021 We don't need to check for pass-by-reference because of the test above.
9022 We can return a simplifed answer, since we know there's no offset to add. */
9025 && rs6000_darwin64_abi
9026 && integer_zerop (TYPE_SIZE (type)))
9028 unsigned HOST_WIDE_INT align, boundary;
9029 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9030 align = PARM_BOUNDARY / BITS_PER_UNIT;
9031 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9032 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9033 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9034 boundary /= BITS_PER_UNIT;
9035 if (boundary > align)
9038 /* This updates arg ptr by the amount that would be necessary
9039 to align the zero-sized (but not zero-alignment) item. */
9040 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9041 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9042 gimplify_and_add (t, pre_p);
9044 t = fold_convert (sizetype, valist_tmp);
9045 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9046 fold_convert (TREE_TYPE (valist),
9047 fold_build2 (BIT_AND_EXPR, sizetype, t,
9048 size_int (-boundary))));
9049 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9050 gimplify_and_add (t, pre_p);
9052 /* Since it is zero-sized there's no increment for the item itself. */
9053 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9054 return build_va_arg_indirect_ref (valist_tmp);
9057 if (DEFAULT_ABI != ABI_V4)
9059 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9061 tree elem_type = TREE_TYPE (type);
9062 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9063 int elem_size = GET_MODE_SIZE (elem_mode);
9065 if (elem_size < UNITS_PER_WORD)
9067 tree real_part, imag_part;
9068 gimple_seq post = NULL;
9070 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9072 /* Copy the value into a temporary, lest the formal temporary
9073 be reused out from under us. */
9074 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9075 gimple_seq_add_seq (pre_p, post);
9077 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9080 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9084 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9087 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9088 f_fpr = DECL_CHAIN (f_gpr);
9089 f_res = DECL_CHAIN (f_fpr);
9090 f_ovf = DECL_CHAIN (f_res);
9091 f_sav = DECL_CHAIN (f_ovf);
9093 valist = build_va_arg_indirect_ref (valist);
9094 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9095 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9097 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9099 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9102 size = int_size_in_bytes (type);
9103 rsize = (size + 3) / 4;
9106 if (TARGET_HARD_FLOAT && TARGET_FPRS
9107 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9108 || (TARGET_DOUBLE_FLOAT
9109 && (TYPE_MODE (type) == DFmode
9110 || TYPE_MODE (type) == TFmode
9111 || TYPE_MODE (type) == SDmode
9112 || TYPE_MODE (type) == DDmode
9113 || TYPE_MODE (type) == TDmode))))
9115 /* FP args go in FP registers, if present. */
9117 n_reg = (size + 7) / 8;
9118 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9119 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9120 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9125 /* Otherwise into GP registers. */
9134 /* Pull the value out of the saved registers.... */
9137 addr = create_tmp_var (ptr_type_node, "addr");
9139 /* AltiVec vectors never go in registers when -mabi=altivec. */
9140 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9144 lab_false = create_artificial_label (input_location);
9145 lab_over = create_artificial_label (input_location);
9147 /* Long long and SPE vectors are aligned in the registers.
9148 As are any other 2 gpr item such as complex int due to a
9149 historical mistake. */
9151 if (n_reg == 2 && reg == gpr)
9154 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9155 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9156 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9157 unshare_expr (reg), u);
9159 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9160 reg number is 0 for f1, so we want to make it odd. */
9161 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9163 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9164 build_int_cst (TREE_TYPE (reg), 1));
9165 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9168 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9169 t = build2 (GE_EXPR, boolean_type_node, u, t);
9170 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9171 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9172 gimplify_and_add (t, pre_p);
9176 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9178 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9179 build_int_cst (TREE_TYPE (reg), n_reg));
9180 u = fold_convert (sizetype, u);
9181 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9182 t = fold_build_pointer_plus (t, u);
9184 /* _Decimal32 varargs are located in the second word of the 64-bit
9185 FP register for 32-bit binaries. */
9186 if (!TARGET_POWERPC64
9187 && TARGET_HARD_FLOAT && TARGET_FPRS
9188 && TYPE_MODE (type) == SDmode)
9189 t = fold_build_pointer_plus_hwi (t, size);
9191 gimplify_assign (addr, t, pre_p);
9193 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9195 stmt = gimple_build_label (lab_false);
9196 gimple_seq_add_stmt (pre_p, stmt);
9198 if ((n_reg == 2 && !regalign) || n_reg > 2)
9200 /* Ensure that we don't find any more args in regs.
9201 Alignment has taken care of for special cases. */
9202 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9206 /* ... otherwise out of the overflow area. */
9208 /* Care for on-stack alignment if needed. */
9212 t = fold_build_pointer_plus_hwi (t, align - 1);
9213 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9214 build_int_cst (TREE_TYPE (t), -align));
9216 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9218 gimplify_assign (unshare_expr (addr), t, pre_p);
9220 t = fold_build_pointer_plus_hwi (t, size);
9221 gimplify_assign (unshare_expr (ovf), t, pre_p);
9225 stmt = gimple_build_label (lab_over);
9226 gimple_seq_add_stmt (pre_p, stmt);
9229 if (STRICT_ALIGNMENT
9230 && (TYPE_ALIGN (type)
9231 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9233 /* The value (of type complex double, for example) may not be
9234 aligned in memory in the saved registers, so copy via a
9235 temporary. (This is the same code as used for SPARC.) */
9236 tree tmp = create_tmp_var (type, "va_arg_tmp");
9237 tree dest_addr = build_fold_addr_expr (tmp);
9239 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9240 3, dest_addr, addr, size_int (rsize * 4));
9242 gimplify_and_add (copy, pre_p);
9246 addr = fold_convert (ptrtype, addr);
9247 return build_va_arg_indirect_ref (addr);
9253 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9256 unsigned classify = rs6000_builtin_info[(int)code].attr;
9257 const char *attr_string = "";
9259 gcc_assert (name != NULL);
9260 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9262 if (rs6000_builtin_decls[(int)code])
9263 fatal_error ("internal error: builtin function %s already processed", name);
9265 rs6000_builtin_decls[(int)code] = t =
9266 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9268 /* Set any special attributes. */
9269 if ((classify & RS6000_BTC_CONST) != 0)
9271 /* const function, function only depends on the inputs. */
9272 TREE_READONLY (t) = 1;
9273 TREE_NOTHROW (t) = 1;
9274 attr_string = ", pure";
9276 else if ((classify & RS6000_BTC_PURE) != 0)
9278 /* pure function, function can read global memory, but does not set any
9280 DECL_PURE_P (t) = 1;
9281 TREE_NOTHROW (t) = 1;
9282 attr_string = ", const";
9284 else if ((classify & RS6000_BTC_FP) != 0)
9286 /* Function is a math function. If rounding mode is on, then treat the
9287 function as not reading global memory, but it can have arbitrary side
9288 effects. If it is off, then assume the function is a const function.
9289 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9290 builtin-attribute.def that is used for the math functions. */
9291 TREE_NOTHROW (t) = 1;
9292 if (flag_rounding_math)
9294 DECL_PURE_P (t) = 1;
9295 DECL_IS_NOVOPS (t) = 1;
9296 attr_string = ", fp, pure";
9300 TREE_READONLY (t) = 1;
9301 attr_string = ", fp, const";
9304 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9307 if (TARGET_DEBUG_BUILTIN)
9308 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9309 (int)code, name, attr_string);
9312 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9314 #undef RS6000_BUILTIN_1
9315 #undef RS6000_BUILTIN_2
9316 #undef RS6000_BUILTIN_3
9317 #undef RS6000_BUILTIN_A
9318 #undef RS6000_BUILTIN_D
9319 #undef RS6000_BUILTIN_E
9320 #undef RS6000_BUILTIN_P
9321 #undef RS6000_BUILTIN_Q
9322 #undef RS6000_BUILTIN_S
9323 #undef RS6000_BUILTIN_X
9325 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9326 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9327 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9328 { MASK, ICODE, NAME, ENUM },
9330 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9331 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9332 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9333 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9334 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9335 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9336 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9338 static const struct builtin_description bdesc_3arg[] =
9340 #include "rs6000-builtin.def"
9343 /* DST operations: void foo (void *, const int, const char). */
9345 #undef RS6000_BUILTIN_1
9346 #undef RS6000_BUILTIN_2
9347 #undef RS6000_BUILTIN_3
9348 #undef RS6000_BUILTIN_A
9349 #undef RS6000_BUILTIN_D
9350 #undef RS6000_BUILTIN_E
9351 #undef RS6000_BUILTIN_P
9352 #undef RS6000_BUILTIN_Q
9353 #undef RS6000_BUILTIN_S
9354 #undef RS6000_BUILTIN_X
9356 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9357 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9358 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9359 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9360 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9361 { MASK, ICODE, NAME, ENUM },
9363 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9364 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9365 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9366 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9367 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9369 static const struct builtin_description bdesc_dst[] =
9371 #include "rs6000-builtin.def"
9374 /* Simple binary operations: VECc = foo (VECa, VECb). */
9376 #undef RS6000_BUILTIN_1
9377 #undef RS6000_BUILTIN_2
9378 #undef RS6000_BUILTIN_3
9379 #undef RS6000_BUILTIN_A
9380 #undef RS6000_BUILTIN_D
9381 #undef RS6000_BUILTIN_E
9382 #undef RS6000_BUILTIN_P
9383 #undef RS6000_BUILTIN_Q
9384 #undef RS6000_BUILTIN_S
9385 #undef RS6000_BUILTIN_X
9387 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9388 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9389 { MASK, ICODE, NAME, ENUM },
9391 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9392 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9393 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9394 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9395 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9396 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9397 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9398 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9400 static const struct builtin_description bdesc_2arg[] =
9402 #include "rs6000-builtin.def"
9405 #undef RS6000_BUILTIN_1
9406 #undef RS6000_BUILTIN_2
9407 #undef RS6000_BUILTIN_3
9408 #undef RS6000_BUILTIN_A
9409 #undef RS6000_BUILTIN_D
9410 #undef RS6000_BUILTIN_E
9411 #undef RS6000_BUILTIN_P
9412 #undef RS6000_BUILTIN_Q
9413 #undef RS6000_BUILTIN_S
9414 #undef RS6000_BUILTIN_X
9416 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9417 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9418 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9419 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9420 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9421 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9422 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9423 { MASK, ICODE, NAME, ENUM },
9425 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9426 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9427 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9429 /* AltiVec predicates. */
9431 static const struct builtin_description bdesc_altivec_preds[] =
9433 #include "rs6000-builtin.def"
9436 /* SPE predicates. */
9437 #undef RS6000_BUILTIN_1
9438 #undef RS6000_BUILTIN_2
9439 #undef RS6000_BUILTIN_3
9440 #undef RS6000_BUILTIN_A
9441 #undef RS6000_BUILTIN_D
9442 #undef RS6000_BUILTIN_E
9443 #undef RS6000_BUILTIN_P
9444 #undef RS6000_BUILTIN_Q
9445 #undef RS6000_BUILTIN_S
9446 #undef RS6000_BUILTIN_X
9448 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9449 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9450 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9451 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9452 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9453 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9454 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9455 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9456 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9457 { MASK, ICODE, NAME, ENUM },
9459 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9461 static const struct builtin_description bdesc_spe_predicates[] =
9463 #include "rs6000-builtin.def"
9466 /* SPE evsel predicates. */
9467 #undef RS6000_BUILTIN_1
9468 #undef RS6000_BUILTIN_2
9469 #undef RS6000_BUILTIN_3
9470 #undef RS6000_BUILTIN_A
9471 #undef RS6000_BUILTIN_D
9472 #undef RS6000_BUILTIN_E
9473 #undef RS6000_BUILTIN_P
9474 #undef RS6000_BUILTIN_Q
9475 #undef RS6000_BUILTIN_S
9476 #undef RS6000_BUILTIN_X
9478 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9479 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9480 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9481 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9482 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9483 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9484 { MASK, ICODE, NAME, ENUM },
9486 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9487 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9488 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9489 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9491 static const struct builtin_description bdesc_spe_evsel[] =
9493 #include "rs6000-builtin.def"
9496 /* PAIRED predicates. */
9497 #undef RS6000_BUILTIN_1
9498 #undef RS6000_BUILTIN_2
9499 #undef RS6000_BUILTIN_3
9500 #undef RS6000_BUILTIN_A
9501 #undef RS6000_BUILTIN_D
9502 #undef RS6000_BUILTIN_E
9503 #undef RS6000_BUILTIN_P
9504 #undef RS6000_BUILTIN_Q
9505 #undef RS6000_BUILTIN_S
9506 #undef RS6000_BUILTIN_X
9508 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9509 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9510 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9511 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9512 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9513 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9514 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9515 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9516 { MASK, ICODE, NAME, ENUM },
9518 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9519 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9521 static const struct builtin_description bdesc_paired_preds[] =
9523 #include "rs6000-builtin.def"
9526 /* ABS* operations. */
9528 #undef RS6000_BUILTIN_1
9529 #undef RS6000_BUILTIN_2
9530 #undef RS6000_BUILTIN_3
9531 #undef RS6000_BUILTIN_A
9532 #undef RS6000_BUILTIN_D
9533 #undef RS6000_BUILTIN_E
9534 #undef RS6000_BUILTIN_P
9535 #undef RS6000_BUILTIN_Q
9536 #undef RS6000_BUILTIN_S
9537 #undef RS6000_BUILTIN_X
9539 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9540 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9541 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9542 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9543 { MASK, ICODE, NAME, ENUM },
9545 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9546 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9547 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9548 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9549 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9550 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9552 static const struct builtin_description bdesc_abs[] =
9554 #include "rs6000-builtin.def"
9557 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9560 #undef RS6000_BUILTIN_1
9561 #undef RS6000_BUILTIN_2
9562 #undef RS6000_BUILTIN_3
9563 #undef RS6000_BUILTIN_A
9564 #undef RS6000_BUILTIN_E
9565 #undef RS6000_BUILTIN_D
9566 #undef RS6000_BUILTIN_P
9567 #undef RS6000_BUILTIN_Q
9568 #undef RS6000_BUILTIN_S
9569 #undef RS6000_BUILTIN_X
9571 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9572 { MASK, ICODE, NAME, ENUM },
9574 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9575 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9576 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9577 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9578 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9579 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9580 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9581 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9582 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9584 static const struct builtin_description bdesc_1arg[] =
9586 #include "rs6000-builtin.def"
9589 #undef RS6000_BUILTIN_1
9590 #undef RS6000_BUILTIN_2
9591 #undef RS6000_BUILTIN_3
9592 #undef RS6000_BUILTIN_A
9593 #undef RS6000_BUILTIN_D
9594 #undef RS6000_BUILTIN_E
9595 #undef RS6000_BUILTIN_P
9596 #undef RS6000_BUILTIN_Q
9597 #undef RS6000_BUILTIN_S
9598 #undef RS6000_BUILTIN_X
9600 /* Return true if a builtin function is overloaded. */
9602 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9604 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9609 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9612 tree arg0 = CALL_EXPR_ARG (exp, 0);
9613 rtx op0 = expand_normal (arg0);
9614 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9615 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9617 if (icode == CODE_FOR_nothing)
9618 /* Builtin not supported on this processor. */
9621 /* If we got invalid arguments bail out before generating bad rtl. */
9622 if (arg0 == error_mark_node)
9625 if (icode == CODE_FOR_altivec_vspltisb
9626 || icode == CODE_FOR_altivec_vspltish
9627 || icode == CODE_FOR_altivec_vspltisw
9628 || icode == CODE_FOR_spe_evsplatfi
9629 || icode == CODE_FOR_spe_evsplati)
9631 /* Only allow 5-bit *signed* literals. */
9632 if (GET_CODE (op0) != CONST_INT
9633 || INTVAL (op0) > 15
9634 || INTVAL (op0) < -16)
9636 error ("argument 1 must be a 5-bit signed literal");
9642 || GET_MODE (target) != tmode
9643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9644 target = gen_reg_rtx (tmode);
9646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9647 op0 = copy_to_mode_reg (mode0, op0);
9649 pat = GEN_FCN (icode) (target, op0);
9658 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9660 rtx pat, scratch1, scratch2;
9661 tree arg0 = CALL_EXPR_ARG (exp, 0);
9662 rtx op0 = expand_normal (arg0);
9663 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9664 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9666 /* If we have invalid arguments, bail out before generating bad rtl. */
9667 if (arg0 == error_mark_node)
9671 || GET_MODE (target) != tmode
9672 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9673 target = gen_reg_rtx (tmode);
9675 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9676 op0 = copy_to_mode_reg (mode0, op0);
9678 scratch1 = gen_reg_rtx (mode0);
9679 scratch2 = gen_reg_rtx (mode0);
9681 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9690 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9693 tree arg0 = CALL_EXPR_ARG (exp, 0);
9694 tree arg1 = CALL_EXPR_ARG (exp, 1);
9695 rtx op0 = expand_normal (arg0);
9696 rtx op1 = expand_normal (arg1);
9697 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9698 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9699 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9701 if (icode == CODE_FOR_nothing)
9702 /* Builtin not supported on this processor. */
9705 /* If we got invalid arguments bail out before generating bad rtl. */
9706 if (arg0 == error_mark_node || arg1 == error_mark_node)
9709 if (icode == CODE_FOR_altivec_vcfux
9710 || icode == CODE_FOR_altivec_vcfsx
9711 || icode == CODE_FOR_altivec_vctsxs
9712 || icode == CODE_FOR_altivec_vctuxs
9713 || icode == CODE_FOR_altivec_vspltb
9714 || icode == CODE_FOR_altivec_vsplth
9715 || icode == CODE_FOR_altivec_vspltw
9716 || icode == CODE_FOR_spe_evaddiw
9717 || icode == CODE_FOR_spe_evldd
9718 || icode == CODE_FOR_spe_evldh
9719 || icode == CODE_FOR_spe_evldw
9720 || icode == CODE_FOR_spe_evlhhesplat
9721 || icode == CODE_FOR_spe_evlhhossplat
9722 || icode == CODE_FOR_spe_evlhhousplat
9723 || icode == CODE_FOR_spe_evlwhe
9724 || icode == CODE_FOR_spe_evlwhos
9725 || icode == CODE_FOR_spe_evlwhou
9726 || icode == CODE_FOR_spe_evlwhsplat
9727 || icode == CODE_FOR_spe_evlwwsplat
9728 || icode == CODE_FOR_spe_evrlwi
9729 || icode == CODE_FOR_spe_evslwi
9730 || icode == CODE_FOR_spe_evsrwis
9731 || icode == CODE_FOR_spe_evsubifw
9732 || icode == CODE_FOR_spe_evsrwiu)
9734 /* Only allow 5-bit unsigned literals. */
9736 if (TREE_CODE (arg1) != INTEGER_CST
9737 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9739 error ("argument 2 must be a 5-bit unsigned literal");
9745 || GET_MODE (target) != tmode
9746 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9747 target = gen_reg_rtx (tmode);
9749 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9750 op0 = copy_to_mode_reg (mode0, op0);
9751 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9752 op1 = copy_to_mode_reg (mode1, op1);
9754 pat = GEN_FCN (icode) (target, op0, op1);
9763 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9766 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9767 tree arg0 = CALL_EXPR_ARG (exp, 1);
9768 tree arg1 = CALL_EXPR_ARG (exp, 2);
9769 rtx op0 = expand_normal (arg0);
9770 rtx op1 = expand_normal (arg1);
9771 enum machine_mode tmode = SImode;
9772 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9773 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9776 if (TREE_CODE (cr6_form) != INTEGER_CST)
9778 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9782 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9784 gcc_assert (mode0 == mode1);
9786 /* If we have invalid arguments, bail out before generating bad rtl. */
9787 if (arg0 == error_mark_node || arg1 == error_mark_node)
9791 || GET_MODE (target) != tmode
9792 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9793 target = gen_reg_rtx (tmode);
9795 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9796 op0 = copy_to_mode_reg (mode0, op0);
9797 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9798 op1 = copy_to_mode_reg (mode1, op1);
9800 scratch = gen_reg_rtx (mode0);
9802 pat = GEN_FCN (icode) (scratch, op0, op1);
9807 /* The vec_any* and vec_all* predicates use the same opcodes for two
9808 different operations, but the bits in CR6 will be different
9809 depending on what information we want. So we have to play tricks
9810 with CR6 to get the right bits out.
9812 If you think this is disgusting, look at the specs for the
9813 AltiVec predicates. */
9815 switch (cr6_form_int)
9818 emit_insn (gen_cr6_test_for_zero (target));
9821 emit_insn (gen_cr6_test_for_zero_reverse (target));
9824 emit_insn (gen_cr6_test_for_lt (target));
9827 emit_insn (gen_cr6_test_for_lt_reverse (target));
9830 error ("argument 1 of __builtin_altivec_predicate is out of range");
9838 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
9841 tree arg0 = CALL_EXPR_ARG (exp, 0);
9842 tree arg1 = CALL_EXPR_ARG (exp, 1);
9843 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9844 enum machine_mode mode0 = Pmode;
9845 enum machine_mode mode1 = Pmode;
9846 rtx op0 = expand_normal (arg0);
9847 rtx op1 = expand_normal (arg1);
9849 if (icode == CODE_FOR_nothing)
9850 /* Builtin not supported on this processor. */
9853 /* If we got invalid arguments bail out before generating bad rtl. */
9854 if (arg0 == error_mark_node || arg1 == error_mark_node)
9858 || GET_MODE (target) != tmode
9859 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9860 target = gen_reg_rtx (tmode);
9862 op1 = copy_to_mode_reg (mode1, op1);
9864 if (op0 == const0_rtx)
9866 addr = gen_rtx_MEM (tmode, op1);
9870 op0 = copy_to_mode_reg (mode0, op0);
9871 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
9874 pat = GEN_FCN (icode) (target, addr);
9884 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9887 tree arg0 = CALL_EXPR_ARG (exp, 0);
9888 tree arg1 = CALL_EXPR_ARG (exp, 1);
9889 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9890 enum machine_mode mode0 = Pmode;
9891 enum machine_mode mode1 = Pmode;
9892 rtx op0 = expand_normal (arg0);
9893 rtx op1 = expand_normal (arg1);
9895 if (icode == CODE_FOR_nothing)
9896 /* Builtin not supported on this processor. */
9899 /* If we got invalid arguments bail out before generating bad rtl. */
9900 if (arg0 == error_mark_node || arg1 == error_mark_node)
9904 || GET_MODE (target) != tmode
9905 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9906 target = gen_reg_rtx (tmode);
9908 op1 = copy_to_mode_reg (mode1, op1);
9910 if (op0 == const0_rtx)
9912 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9916 op0 = copy_to_mode_reg (mode0, op0);
9917 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
9920 pat = GEN_FCN (icode) (target, addr);
9930 spe_expand_stv_builtin (enum insn_code icode, tree exp)
9932 tree arg0 = CALL_EXPR_ARG (exp, 0);
9933 tree arg1 = CALL_EXPR_ARG (exp, 1);
9934 tree arg2 = CALL_EXPR_ARG (exp, 2);
9935 rtx op0 = expand_normal (arg0);
9936 rtx op1 = expand_normal (arg1);
9937 rtx op2 = expand_normal (arg2);
9939 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9940 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
9941 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
9943 /* Invalid arguments. Bail before doing anything stoopid! */
9944 if (arg0 == error_mark_node
9945 || arg1 == error_mark_node
9946 || arg2 == error_mark_node)
9949 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
9950 op0 = copy_to_mode_reg (mode2, op0);
9951 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
9952 op1 = copy_to_mode_reg (mode0, op1);
9953 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
9954 op2 = copy_to_mode_reg (mode1, op2);
9956 pat = GEN_FCN (icode) (op1, op2, op0);
9963 paired_expand_stv_builtin (enum insn_code icode, tree exp)
9965 tree arg0 = CALL_EXPR_ARG (exp, 0);
9966 tree arg1 = CALL_EXPR_ARG (exp, 1);
9967 tree arg2 = CALL_EXPR_ARG (exp, 2);
9968 rtx op0 = expand_normal (arg0);
9969 rtx op1 = expand_normal (arg1);
9970 rtx op2 = expand_normal (arg2);
9972 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9973 enum machine_mode mode1 = Pmode;
9974 enum machine_mode mode2 = Pmode;
9976 /* Invalid arguments. Bail before doing anything stoopid! */
9977 if (arg0 == error_mark_node
9978 || arg1 == error_mark_node
9979 || arg2 == error_mark_node)
9982 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
9983 op0 = copy_to_mode_reg (tmode, op0);
9985 op2 = copy_to_mode_reg (mode2, op2);
9987 if (op1 == const0_rtx)
9989 addr = gen_rtx_MEM (tmode, op2);
9993 op1 = copy_to_mode_reg (mode1, op1);
9994 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
9997 pat = GEN_FCN (icode) (addr, op0);
10004 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10006 tree arg0 = CALL_EXPR_ARG (exp, 0);
10007 tree arg1 = CALL_EXPR_ARG (exp, 1);
10008 tree arg2 = CALL_EXPR_ARG (exp, 2);
10009 rtx op0 = expand_normal (arg0);
10010 rtx op1 = expand_normal (arg1);
10011 rtx op2 = expand_normal (arg2);
10013 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10014 enum machine_mode smode = insn_data[icode].operand[1].mode;
10015 enum machine_mode mode1 = Pmode;
10016 enum machine_mode mode2 = Pmode;
10018 /* Invalid arguments. Bail before doing anything stoopid! */
10019 if (arg0 == error_mark_node
10020 || arg1 == error_mark_node
10021 || arg2 == error_mark_node)
10024 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10025 op0 = copy_to_mode_reg (smode, op0);
10027 op2 = copy_to_mode_reg (mode2, op2);
10029 if (op1 == const0_rtx)
10031 addr = gen_rtx_MEM (tmode, op2);
10035 op1 = copy_to_mode_reg (mode1, op1);
10036 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10039 pat = GEN_FCN (icode) (addr, op0);
10046 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10049 tree arg0 = CALL_EXPR_ARG (exp, 0);
10050 tree arg1 = CALL_EXPR_ARG (exp, 1);
10051 tree arg2 = CALL_EXPR_ARG (exp, 2);
10052 rtx op0 = expand_normal (arg0);
10053 rtx op1 = expand_normal (arg1);
10054 rtx op2 = expand_normal (arg2);
10055 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10056 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10057 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10058 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10060 if (icode == CODE_FOR_nothing)
10061 /* Builtin not supported on this processor. */
10064 /* If we got invalid arguments bail out before generating bad rtl. */
10065 if (arg0 == error_mark_node
10066 || arg1 == error_mark_node
10067 || arg2 == error_mark_node)
10070 /* Check and prepare argument depending on the instruction code.
10072 Note that a switch statement instead of the sequence of tests
10073 would be incorrect as many of the CODE_FOR values could be
10074 CODE_FOR_nothing and that would yield multiple alternatives
10075 with identical values. We'd never reach here at runtime in
10077 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10078 || icode == CODE_FOR_altivec_vsldoi_v4si
10079 || icode == CODE_FOR_altivec_vsldoi_v8hi
10080 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10082 /* Only allow 4-bit unsigned literals. */
10084 if (TREE_CODE (arg2) != INTEGER_CST
10085 || TREE_INT_CST_LOW (arg2) & ~0xf)
10087 error ("argument 3 must be a 4-bit unsigned literal");
10091 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10092 || icode == CODE_FOR_vsx_xxpermdi_v2di
10093 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10094 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10095 || icode == CODE_FOR_vsx_xxsldwi_v4si
10096 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10097 || icode == CODE_FOR_vsx_xxsldwi_v2di
10098 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10100 /* Only allow 2-bit unsigned literals. */
10102 if (TREE_CODE (arg2) != INTEGER_CST
10103 || TREE_INT_CST_LOW (arg2) & ~0x3)
10105 error ("argument 3 must be a 2-bit unsigned literal");
10109 else if (icode == CODE_FOR_vsx_set_v2df
10110 || icode == CODE_FOR_vsx_set_v2di)
10112 /* Only allow 1-bit unsigned literals. */
10114 if (TREE_CODE (arg2) != INTEGER_CST
10115 || TREE_INT_CST_LOW (arg2) & ~0x1)
10117 error ("argument 3 must be a 1-bit unsigned literal");
10123 || GET_MODE (target) != tmode
10124 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10125 target = gen_reg_rtx (tmode);
10127 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10128 op0 = copy_to_mode_reg (mode0, op0);
10129 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10130 op1 = copy_to_mode_reg (mode1, op1);
10131 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10132 op2 = copy_to_mode_reg (mode2, op2);
10134 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10135 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10137 pat = GEN_FCN (icode) (target, op0, op1, op2);
10145 /* Expand the lvx builtins. */
10147 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10149 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10150 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10152 enum machine_mode tmode, mode0;
10154 enum insn_code icode;
10158 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10159 icode = CODE_FOR_vector_altivec_load_v16qi;
10161 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10162 icode = CODE_FOR_vector_altivec_load_v8hi;
10164 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10165 icode = CODE_FOR_vector_altivec_load_v4si;
10167 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10168 icode = CODE_FOR_vector_altivec_load_v4sf;
10170 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10171 icode = CODE_FOR_vector_altivec_load_v2df;
10173 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10174 icode = CODE_FOR_vector_altivec_load_v2di;
10177 *expandedp = false;
10183 arg0 = CALL_EXPR_ARG (exp, 0);
10184 op0 = expand_normal (arg0);
10185 tmode = insn_data[icode].operand[0].mode;
10186 mode0 = insn_data[icode].operand[1].mode;
10189 || GET_MODE (target) != tmode
10190 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10191 target = gen_reg_rtx (tmode);
10193 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10194 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10196 pat = GEN_FCN (icode) (target, op0);
10203 /* Expand the stvx builtins. */
10205 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10208 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10209 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10211 enum machine_mode mode0, mode1;
10213 enum insn_code icode;
10217 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10218 icode = CODE_FOR_vector_altivec_store_v16qi;
10220 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10221 icode = CODE_FOR_vector_altivec_store_v8hi;
10223 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10224 icode = CODE_FOR_vector_altivec_store_v4si;
10226 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10227 icode = CODE_FOR_vector_altivec_store_v4sf;
10229 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10230 icode = CODE_FOR_vector_altivec_store_v2df;
10232 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10233 icode = CODE_FOR_vector_altivec_store_v2di;
10236 *expandedp = false;
10240 arg0 = CALL_EXPR_ARG (exp, 0);
10241 arg1 = CALL_EXPR_ARG (exp, 1);
10242 op0 = expand_normal (arg0);
10243 op1 = expand_normal (arg1);
10244 mode0 = insn_data[icode].operand[0].mode;
10245 mode1 = insn_data[icode].operand[1].mode;
10247 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10248 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10249 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10250 op1 = copy_to_mode_reg (mode1, op1);
10252 pat = GEN_FCN (icode) (op0, op1);
10260 /* Expand the dst builtins. */
10262 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10265 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10266 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10267 tree arg0, arg1, arg2;
10268 enum machine_mode mode0, mode1;
10269 rtx pat, op0, op1, op2;
10270 const struct builtin_description *d;
10273 *expandedp = false;
10275 /* Handle DST variants. */
10277 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10278 if (d->code == fcode)
10280 arg0 = CALL_EXPR_ARG (exp, 0);
10281 arg1 = CALL_EXPR_ARG (exp, 1);
10282 arg2 = CALL_EXPR_ARG (exp, 2);
10283 op0 = expand_normal (arg0);
10284 op1 = expand_normal (arg1);
10285 op2 = expand_normal (arg2);
10286 mode0 = insn_data[d->icode].operand[0].mode;
10287 mode1 = insn_data[d->icode].operand[1].mode;
10289 /* Invalid arguments, bail out before generating bad rtl. */
10290 if (arg0 == error_mark_node
10291 || arg1 == error_mark_node
10292 || arg2 == error_mark_node)
10297 if (TREE_CODE (arg2) != INTEGER_CST
10298 || TREE_INT_CST_LOW (arg2) & ~0x3)
10300 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10304 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10305 op0 = copy_to_mode_reg (Pmode, op0);
10306 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10307 op1 = copy_to_mode_reg (mode1, op1);
10309 pat = GEN_FCN (d->icode) (op0, op1, op2);
10319 /* Expand vec_init builtin. */
10321 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10323 enum machine_mode tmode = TYPE_MODE (type);
10324 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10325 int i, n_elt = GET_MODE_NUNITS (tmode);
10326 rtvec v = rtvec_alloc (n_elt);
10328 gcc_assert (VECTOR_MODE_P (tmode));
10329 gcc_assert (n_elt == call_expr_nargs (exp));
10331 for (i = 0; i < n_elt; ++i)
10333 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10334 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10337 if (!target || !register_operand (target, tmode))
10338 target = gen_reg_rtx (tmode);
10340 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10344 /* Return the integer constant in ARG. Constrain it to be in the range
10345 of the subparts of VEC_TYPE; issue an error if not. */
10348 get_element_number (tree vec_type, tree arg)
10350 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10352 if (!host_integerp (arg, 1)
10353 || (elt = tree_low_cst (arg, 1), elt > max))
10355 error ("selector must be an integer constant in the range 0..%wi", max);
10362 /* Expand vec_set builtin. */
10364 altivec_expand_vec_set_builtin (tree exp)
10366 enum machine_mode tmode, mode1;
10367 tree arg0, arg1, arg2;
10371 arg0 = CALL_EXPR_ARG (exp, 0);
10372 arg1 = CALL_EXPR_ARG (exp, 1);
10373 arg2 = CALL_EXPR_ARG (exp, 2);
10375 tmode = TYPE_MODE (TREE_TYPE (arg0));
10376 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10377 gcc_assert (VECTOR_MODE_P (tmode));
10379 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10380 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10381 elt = get_element_number (TREE_TYPE (arg0), arg2);
10383 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10384 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10386 op0 = force_reg (tmode, op0);
10387 op1 = force_reg (mode1, op1);
10389 rs6000_expand_vector_set (op0, op1, elt);
10394 /* Expand vec_ext builtin. */
10396 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10398 enum machine_mode tmode, mode0;
10403 arg0 = CALL_EXPR_ARG (exp, 0);
10404 arg1 = CALL_EXPR_ARG (exp, 1);
10406 op0 = expand_normal (arg0);
10407 elt = get_element_number (TREE_TYPE (arg0), arg1);
10409 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10410 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10411 gcc_assert (VECTOR_MODE_P (mode0));
10413 op0 = force_reg (mode0, op0);
10415 if (optimize || !target || !register_operand (target, tmode))
10416 target = gen_reg_rtx (tmode);
10418 rs6000_expand_vector_extract (target, op0, elt);
10423 /* Expand the builtin in EXP and store the result in TARGET. Store
10424 true in *EXPANDEDP if we found a builtin to expand. */
10426 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10428 const struct builtin_description *d;
10430 enum insn_code icode;
10431 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10434 enum machine_mode tmode, mode0;
10435 enum rs6000_builtins fcode
10436 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10438 if (rs6000_overloaded_builtin_p (fcode))
10441 error ("unresolved overload for Altivec builtin %qF", fndecl);
10443 /* Given it is invalid, just generate a normal call. */
10444 return expand_call (exp, target, false);
10447 target = altivec_expand_ld_builtin (exp, target, expandedp);
10451 target = altivec_expand_st_builtin (exp, target, expandedp);
10455 target = altivec_expand_dst_builtin (exp, target, expandedp);
10463 case ALTIVEC_BUILTIN_STVX:
10464 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10465 case ALTIVEC_BUILTIN_STVEBX:
10466 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10467 case ALTIVEC_BUILTIN_STVEHX:
10468 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10469 case ALTIVEC_BUILTIN_STVEWX:
10470 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10471 case ALTIVEC_BUILTIN_STVXL:
10472 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10474 case ALTIVEC_BUILTIN_STVLX:
10475 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10476 case ALTIVEC_BUILTIN_STVLXL:
10477 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10478 case ALTIVEC_BUILTIN_STVRX:
10479 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10480 case ALTIVEC_BUILTIN_STVRXL:
10481 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10483 case VSX_BUILTIN_STXVD2X_V2DF:
10484 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10485 case VSX_BUILTIN_STXVD2X_V2DI:
10486 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10487 case VSX_BUILTIN_STXVW4X_V4SF:
10488 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10489 case VSX_BUILTIN_STXVW4X_V4SI:
10490 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10491 case VSX_BUILTIN_STXVW4X_V8HI:
10492 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10493 case VSX_BUILTIN_STXVW4X_V16QI:
10494 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10496 case ALTIVEC_BUILTIN_MFVSCR:
10497 icode = CODE_FOR_altivec_mfvscr;
10498 tmode = insn_data[icode].operand[0].mode;
10501 || GET_MODE (target) != tmode
10502 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10503 target = gen_reg_rtx (tmode);
10505 pat = GEN_FCN (icode) (target);
10511 case ALTIVEC_BUILTIN_MTVSCR:
10512 icode = CODE_FOR_altivec_mtvscr;
10513 arg0 = CALL_EXPR_ARG (exp, 0);
10514 op0 = expand_normal (arg0);
10515 mode0 = insn_data[icode].operand[0].mode;
10517 /* If we got invalid arguments bail out before generating bad rtl. */
10518 if (arg0 == error_mark_node)
10521 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10522 op0 = copy_to_mode_reg (mode0, op0);
10524 pat = GEN_FCN (icode) (op0);
10529 case ALTIVEC_BUILTIN_DSSALL:
10530 emit_insn (gen_altivec_dssall ());
10533 case ALTIVEC_BUILTIN_DSS:
10534 icode = CODE_FOR_altivec_dss;
10535 arg0 = CALL_EXPR_ARG (exp, 0);
10537 op0 = expand_normal (arg0);
10538 mode0 = insn_data[icode].operand[0].mode;
10540 /* If we got invalid arguments bail out before generating bad rtl. */
10541 if (arg0 == error_mark_node)
10544 if (TREE_CODE (arg0) != INTEGER_CST
10545 || TREE_INT_CST_LOW (arg0) & ~0x3)
10547 error ("argument to dss must be a 2-bit unsigned literal");
10551 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10552 op0 = copy_to_mode_reg (mode0, op0);
10554 emit_insn (gen_altivec_dss (op0));
10557 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10558 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10559 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10560 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10561 case VSX_BUILTIN_VEC_INIT_V2DF:
10562 case VSX_BUILTIN_VEC_INIT_V2DI:
10563 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10565 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10566 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10567 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10568 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10569 case VSX_BUILTIN_VEC_SET_V2DF:
10570 case VSX_BUILTIN_VEC_SET_V2DI:
10571 return altivec_expand_vec_set_builtin (exp);
10573 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10574 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10575 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10576 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10577 case VSX_BUILTIN_VEC_EXT_V2DF:
10578 case VSX_BUILTIN_VEC_EXT_V2DI:
10579 return altivec_expand_vec_ext_builtin (exp, target);
10583 /* Fall through. */
10586 /* Expand abs* operations. */
10588 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10589 if (d->code == fcode)
10590 return altivec_expand_abs_builtin (d->icode, exp, target);
10592 /* Expand the AltiVec predicates. */
10593 d = bdesc_altivec_preds;
10594 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10595 if (d->code == fcode)
10596 return altivec_expand_predicate_builtin (d->icode, exp, target);
10598 /* LV* are funky. We initialized them differently. */
10601 case ALTIVEC_BUILTIN_LVSL:
10602 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10603 exp, target, false);
10604 case ALTIVEC_BUILTIN_LVSR:
10605 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10606 exp, target, false);
10607 case ALTIVEC_BUILTIN_LVEBX:
10608 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10609 exp, target, false);
10610 case ALTIVEC_BUILTIN_LVEHX:
10611 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10612 exp, target, false);
10613 case ALTIVEC_BUILTIN_LVEWX:
10614 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10615 exp, target, false);
10616 case ALTIVEC_BUILTIN_LVXL:
10617 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10618 exp, target, false);
10619 case ALTIVEC_BUILTIN_LVX:
10620 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10621 exp, target, false);
10622 case ALTIVEC_BUILTIN_LVLX:
10623 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10624 exp, target, true);
10625 case ALTIVEC_BUILTIN_LVLXL:
10626 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10627 exp, target, true);
10628 case ALTIVEC_BUILTIN_LVRX:
10629 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10630 exp, target, true);
10631 case ALTIVEC_BUILTIN_LVRXL:
10632 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10633 exp, target, true);
10634 case VSX_BUILTIN_LXVD2X_V2DF:
10635 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10636 exp, target, false);
10637 case VSX_BUILTIN_LXVD2X_V2DI:
10638 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10639 exp, target, false);
10640 case VSX_BUILTIN_LXVW4X_V4SF:
10641 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10642 exp, target, false);
10643 case VSX_BUILTIN_LXVW4X_V4SI:
10644 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10645 exp, target, false);
10646 case VSX_BUILTIN_LXVW4X_V8HI:
10647 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10648 exp, target, false);
10649 case VSX_BUILTIN_LXVW4X_V16QI:
10650 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10651 exp, target, false);
10655 /* Fall through. */
10658 *expandedp = false;
10662 /* Expand the builtin in EXP and store the result in TARGET. Store
10663 true in *EXPANDEDP if we found a builtin to expand. */
10665 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10667 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10668 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10669 const struct builtin_description *d;
10676 case PAIRED_BUILTIN_STX:
10677 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10678 case PAIRED_BUILTIN_LX:
10679 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10682 /* Fall through. */
10685 /* Expand the paired predicates. */
10686 d = bdesc_paired_preds;
10687 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10688 if (d->code == fcode)
10689 return paired_expand_predicate_builtin (d->icode, exp, target);
10691 *expandedp = false;
10695 /* Binops that need to be initialized manually, but can be expanded
10696 automagically by rs6000_expand_binop_builtin. */
10697 static const struct builtin_description bdesc_2arg_spe[] =
10699 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10700 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10701 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10702 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10703 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10704 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10705 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10706 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10707 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10708 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10709 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10710 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10711 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10712 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10713 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10714 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10715 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10716 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10717 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10718 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10719 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10720 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10723 /* Expand the builtin in EXP and store the result in TARGET. Store
10724 true in *EXPANDEDP if we found a builtin to expand.
10726 This expands the SPE builtins that are not simple unary and binary
10729 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
10731 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10733 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10734 enum insn_code icode;
10735 enum machine_mode tmode, mode0;
10737 const struct builtin_description *d;
10742 /* Syntax check for a 5-bit unsigned immediate. */
10745 case SPE_BUILTIN_EVSTDD:
10746 case SPE_BUILTIN_EVSTDH:
10747 case SPE_BUILTIN_EVSTDW:
10748 case SPE_BUILTIN_EVSTWHE:
10749 case SPE_BUILTIN_EVSTWHO:
10750 case SPE_BUILTIN_EVSTWWE:
10751 case SPE_BUILTIN_EVSTWWO:
10752 arg1 = CALL_EXPR_ARG (exp, 2);
10753 if (TREE_CODE (arg1) != INTEGER_CST
10754 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10756 error ("argument 2 must be a 5-bit unsigned literal");
10764 /* The evsplat*i instructions are not quite generic. */
10767 case SPE_BUILTIN_EVSPLATFI:
10768 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
10770 case SPE_BUILTIN_EVSPLATI:
10771 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
10777 d = bdesc_2arg_spe;
10778 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
10779 if (d->code == fcode)
10780 return rs6000_expand_binop_builtin (d->icode, exp, target);
10782 d = bdesc_spe_predicates;
10783 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
10784 if (d->code == fcode)
10785 return spe_expand_predicate_builtin (d->icode, exp, target);
10787 d = bdesc_spe_evsel;
10788 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
10789 if (d->code == fcode)
10790 return spe_expand_evsel_builtin (d->icode, exp, target);
10794 case SPE_BUILTIN_EVSTDDX:
10795 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
10796 case SPE_BUILTIN_EVSTDHX:
10797 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
10798 case SPE_BUILTIN_EVSTDWX:
10799 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
10800 case SPE_BUILTIN_EVSTWHEX:
10801 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
10802 case SPE_BUILTIN_EVSTWHOX:
10803 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
10804 case SPE_BUILTIN_EVSTWWEX:
10805 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
10806 case SPE_BUILTIN_EVSTWWOX:
10807 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
10808 case SPE_BUILTIN_EVSTDD:
10809 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
10810 case SPE_BUILTIN_EVSTDH:
10811 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
10812 case SPE_BUILTIN_EVSTDW:
10813 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
10814 case SPE_BUILTIN_EVSTWHE:
10815 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
10816 case SPE_BUILTIN_EVSTWHO:
10817 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
10818 case SPE_BUILTIN_EVSTWWE:
10819 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
10820 case SPE_BUILTIN_EVSTWWO:
10821 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
10822 case SPE_BUILTIN_MFSPEFSCR:
10823 icode = CODE_FOR_spe_mfspefscr;
10824 tmode = insn_data[icode].operand[0].mode;
10827 || GET_MODE (target) != tmode
10828 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10829 target = gen_reg_rtx (tmode);
10831 pat = GEN_FCN (icode) (target);
10836 case SPE_BUILTIN_MTSPEFSCR:
10837 icode = CODE_FOR_spe_mtspefscr;
10838 arg0 = CALL_EXPR_ARG (exp, 0);
10839 op0 = expand_normal (arg0);
10840 mode0 = insn_data[icode].operand[0].mode;
10842 if (arg0 == error_mark_node)
10845 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10846 op0 = copy_to_mode_reg (mode0, op0);
10848 pat = GEN_FCN (icode) (op0);
10856 *expandedp = false;
10861 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10863 rtx pat, scratch, tmp;
10864 tree form = CALL_EXPR_ARG (exp, 0);
10865 tree arg0 = CALL_EXPR_ARG (exp, 1);
10866 tree arg1 = CALL_EXPR_ARG (exp, 2);
10867 rtx op0 = expand_normal (arg0);
10868 rtx op1 = expand_normal (arg1);
10869 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10870 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10872 enum rtx_code code;
10874 if (TREE_CODE (form) != INTEGER_CST)
10876 error ("argument 1 of __builtin_paired_predicate must be a constant");
10880 form_int = TREE_INT_CST_LOW (form);
10882 gcc_assert (mode0 == mode1);
10884 if (arg0 == error_mark_node || arg1 == error_mark_node)
10888 || GET_MODE (target) != SImode
10889 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
10890 target = gen_reg_rtx (SImode);
10891 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
10892 op0 = copy_to_mode_reg (mode0, op0);
10893 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
10894 op1 = copy_to_mode_reg (mode1, op1);
10896 scratch = gen_reg_rtx (CCFPmode);
10898 pat = GEN_FCN (icode) (scratch, op0, op1);
10920 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
10923 error ("argument 1 of __builtin_paired_predicate is out of range");
10927 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
10928 emit_move_insn (target, tmp);
10933 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10935 rtx pat, scratch, tmp;
10936 tree form = CALL_EXPR_ARG (exp, 0);
10937 tree arg0 = CALL_EXPR_ARG (exp, 1);
10938 tree arg1 = CALL_EXPR_ARG (exp, 2);
10939 rtx op0 = expand_normal (arg0);
10940 rtx op1 = expand_normal (arg1);
10941 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10942 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10944 enum rtx_code code;
10946 if (TREE_CODE (form) != INTEGER_CST)
10948 error ("argument 1 of __builtin_spe_predicate must be a constant");
10952 form_int = TREE_INT_CST_LOW (form);
10954 gcc_assert (mode0 == mode1);
10956 if (arg0 == error_mark_node || arg1 == error_mark_node)
10960 || GET_MODE (target) != SImode
10961 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
10962 target = gen_reg_rtx (SImode);
10964 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10965 op0 = copy_to_mode_reg (mode0, op0);
10966 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10967 op1 = copy_to_mode_reg (mode1, op1);
10969 scratch = gen_reg_rtx (CCmode);
10971 pat = GEN_FCN (icode) (scratch, op0, op1);
10976 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
10977 _lower_. We use one compare, but look in different bits of the
10978 CR for each variant.
10980 There are 2 elements in each SPE simd type (upper/lower). The CR
10981 bits are set as follows:
10983 BIT0 | BIT 1 | BIT 2 | BIT 3
10984 U | L | (U | L) | (U & L)
10986 So, for an "all" relationship, BIT 3 would be set.
10987 For an "any" relationship, BIT 2 would be set. Etc.
10989 Following traditional nomenclature, these bits map to:
10991 BIT0 | BIT 1 | BIT 2 | BIT 3
10994 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
10999 /* All variant. OV bit. */
11001 /* We need to get to the OV bit, which is the ORDERED bit. We
11002 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11003 that's ugly and will make validate_condition_mode die.
11004 So let's just use another pattern. */
11005 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11007 /* Any variant. EQ bit. */
11011 /* Upper variant. LT bit. */
11015 /* Lower variant. GT bit. */
11020 error ("argument 1 of __builtin_spe_predicate is out of range");
11024 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11025 emit_move_insn (target, tmp);
11030 /* The evsel builtins look like this:
11032 e = __builtin_spe_evsel_OP (a, b, c, d);
11034 and work like this:
11036 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11037 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11041 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11044 tree arg0 = CALL_EXPR_ARG (exp, 0);
11045 tree arg1 = CALL_EXPR_ARG (exp, 1);
11046 tree arg2 = CALL_EXPR_ARG (exp, 2);
11047 tree arg3 = CALL_EXPR_ARG (exp, 3);
11048 rtx op0 = expand_normal (arg0);
11049 rtx op1 = expand_normal (arg1);
11050 rtx op2 = expand_normal (arg2);
11051 rtx op3 = expand_normal (arg3);
11052 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11053 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11055 gcc_assert (mode0 == mode1);
11057 if (arg0 == error_mark_node || arg1 == error_mark_node
11058 || arg2 == error_mark_node || arg3 == error_mark_node)
11062 || GET_MODE (target) != mode0
11063 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11064 target = gen_reg_rtx (mode0);
11066 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11067 op0 = copy_to_mode_reg (mode0, op0);
11068 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11069 op1 = copy_to_mode_reg (mode0, op1);
11070 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11071 op2 = copy_to_mode_reg (mode0, op2);
11072 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11073 op3 = copy_to_mode_reg (mode0, op3);
11075 /* Generate the compare. */
11076 scratch = gen_reg_rtx (CCmode);
11077 pat = GEN_FCN (icode) (scratch, op0, op1);
11082 if (mode0 == V2SImode)
11083 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11085 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11090 /* Raise an error message for a builtin function that is called without the
11091 appropriate target options being set. */
11094 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11096 size_t uns_fncode = (size_t)fncode;
11097 const char *name = rs6000_builtin_info[uns_fncode].name;
11098 unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
11100 gcc_assert (name != NULL);
11101 if ((fnmask & RS6000_BTM_CELL) != 0)
11102 error ("Builtin function %s is only valid for the cell processor", name);
11103 else if ((fnmask & RS6000_BTM_VSX) != 0)
11104 error ("Builtin function %s requires the -mvsx option", name);
11105 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11106 error ("Builtin function %s requires the -maltivec option", name);
11107 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11108 error ("Builtin function %s requires the -mpaired option", name);
11109 else if ((fnmask & RS6000_BTM_SPE) != 0)
11110 error ("Builtin function %s requires the -mspe option", name);
11112 error ("Builtin function %s is not supported with the current options",
11116 /* Expand an expression EXP that calls a built-in function,
11117 with result going to TARGET if that's convenient
11118 (and in mode MODE if that's convenient).
11119 SUBTARGET may be used as the target for computing one of EXP's operands.
11120 IGNORE is nonzero if the value is to be ignored. */
11123 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11124 enum machine_mode mode ATTRIBUTE_UNUSED,
11125 int ignore ATTRIBUTE_UNUSED)
11127 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11128 enum rs6000_builtins fcode
11129 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11130 size_t uns_fcode = (size_t)fcode;
11131 const struct builtin_description *d;
11135 unsigned mask = rs6000_builtin_info[uns_fcode].mask;
11136 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11138 if (TARGET_DEBUG_BUILTIN)
11140 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11141 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11142 const char *name2 = ((icode != CODE_FOR_nothing)
11143 ? get_insn_name ((int)icode)
11147 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11149 default: name3 = "unknown"; break;
11150 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11151 case RS6000_BTC_UNARY: name3 = "unary"; break;
11152 case RS6000_BTC_BINARY: name3 = "binary"; break;
11153 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11154 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11155 case RS6000_BTC_ABS: name3 = "abs"; break;
11156 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11157 case RS6000_BTC_DST: name3 = "dst"; break;
11162 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11163 (name1) ? name1 : "---", fcode,
11164 (name2) ? name2 : "---", (int)icode,
11166 func_valid_p ? "" : ", not valid");
11171 rs6000_invalid_builtin (fcode);
11173 /* Given it is invalid, just generate a normal call. */
11174 return expand_call (exp, target, ignore);
11179 case RS6000_BUILTIN_RECIP:
11180 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11182 case RS6000_BUILTIN_RECIPF:
11183 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11185 case RS6000_BUILTIN_RSQRTF:
11186 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11188 case RS6000_BUILTIN_RSQRT:
11189 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11191 case POWER7_BUILTIN_BPERMD:
11192 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11193 ? CODE_FOR_bpermd_di
11194 : CODE_FOR_bpermd_si), exp, target);
11196 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11197 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11199 int icode = (int) CODE_FOR_altivec_lvsr;
11200 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11201 enum machine_mode mode = insn_data[icode].operand[1].mode;
11205 gcc_assert (TARGET_ALTIVEC);
11207 arg = CALL_EXPR_ARG (exp, 0);
11208 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11209 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11210 addr = memory_address (mode, op);
11211 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11215 /* For the load case need to negate the address. */
11216 op = gen_reg_rtx (GET_MODE (addr));
11217 emit_insn (gen_rtx_SET (VOIDmode, op,
11218 gen_rtx_NEG (GET_MODE (addr), addr)));
11220 op = gen_rtx_MEM (mode, op);
11223 || GET_MODE (target) != tmode
11224 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11225 target = gen_reg_rtx (tmode);
11227 /*pat = gen_altivec_lvsr (target, op);*/
11228 pat = GEN_FCN (icode) (target, op);
11236 case ALTIVEC_BUILTIN_VCFUX:
11237 case ALTIVEC_BUILTIN_VCFSX:
11238 case ALTIVEC_BUILTIN_VCTUXS:
11239 case ALTIVEC_BUILTIN_VCTSXS:
11240 /* FIXME: There's got to be a nicer way to handle this case than
11241 constructing a new CALL_EXPR. */
11242 if (call_expr_nargs (exp) == 1)
11244 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11245 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11253 if (TARGET_ALTIVEC)
11255 ret = altivec_expand_builtin (exp, target, &success);
11262 ret = spe_expand_builtin (exp, target, &success);
11267 if (TARGET_PAIRED_FLOAT)
11269 ret = paired_expand_builtin (exp, target, &success);
11275 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11277 /* Handle simple unary operations. */
11279 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11280 if (d->code == fcode)
11281 return rs6000_expand_unop_builtin (d->icode, exp, target);
11283 /* Handle simple binary operations. */
11285 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11286 if (d->code == fcode)
11287 return rs6000_expand_binop_builtin (d->icode, exp, target);
11289 /* Handle simple ternary operations. */
11291 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11292 if (d->code == fcode)
11293 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11295 gcc_unreachable ();
11299 rs6000_init_builtins (void)
11303 enum machine_mode mode;
11305 if (TARGET_DEBUG_BUILTIN)
11306 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11307 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11308 (TARGET_SPE) ? ", spe" : "",
11309 (TARGET_ALTIVEC) ? ", altivec" : "",
11310 (TARGET_VSX) ? ", vsx" : "");
11312 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11313 V2SF_type_node = build_vector_type (float_type_node, 2);
11314 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11315 V2DF_type_node = build_vector_type (double_type_node, 2);
11316 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11317 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11318 V4SF_type_node = build_vector_type (float_type_node, 4);
11319 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11320 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11322 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11323 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11324 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11325 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11327 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11328 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11329 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11330 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11332 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11333 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11334 'vector unsigned short'. */
11336 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11337 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11338 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11339 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11340 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11342 long_integer_type_internal_node = long_integer_type_node;
11343 long_unsigned_type_internal_node = long_unsigned_type_node;
11344 long_long_integer_type_internal_node = long_long_integer_type_node;
11345 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11346 intQI_type_internal_node = intQI_type_node;
11347 uintQI_type_internal_node = unsigned_intQI_type_node;
11348 intHI_type_internal_node = intHI_type_node;
11349 uintHI_type_internal_node = unsigned_intHI_type_node;
11350 intSI_type_internal_node = intSI_type_node;
11351 uintSI_type_internal_node = unsigned_intSI_type_node;
11352 intDI_type_internal_node = intDI_type_node;
11353 uintDI_type_internal_node = unsigned_intDI_type_node;
11354 float_type_internal_node = float_type_node;
11355 double_type_internal_node = double_type_node;
11356 void_type_internal_node = void_type_node;
11358 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11360 builtin_mode_to_type[QImode][0] = integer_type_node;
11361 builtin_mode_to_type[HImode][0] = integer_type_node;
11362 builtin_mode_to_type[SImode][0] = intSI_type_node;
11363 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11364 builtin_mode_to_type[DImode][0] = intDI_type_node;
11365 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11366 builtin_mode_to_type[SFmode][0] = float_type_node;
11367 builtin_mode_to_type[DFmode][0] = double_type_node;
11368 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11369 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11370 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11371 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11372 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11373 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11374 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11375 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11376 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11377 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11378 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11379 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11380 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11382 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
11383 TYPE_NAME (bool_char_type_node) = tdecl;
11385 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
11386 TYPE_NAME (bool_short_type_node) = tdecl;
11388 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
11389 TYPE_NAME (bool_int_type_node) = tdecl;
11391 tdecl = add_builtin_type ("__pixel", pixel_type_node);
11392 TYPE_NAME (pixel_type_node) = tdecl;
11394 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11395 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11396 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11397 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11398 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11400 tdecl = add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node);
11401 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11403 tdecl = add_builtin_type ("__vector signed char", V16QI_type_node);
11404 TYPE_NAME (V16QI_type_node) = tdecl;
11406 tdecl = add_builtin_type ("__vector __bool char", bool_V16QI_type_node);
11407 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11409 tdecl = add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node);
11410 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11412 tdecl = add_builtin_type ("__vector signed short", V8HI_type_node);
11413 TYPE_NAME (V8HI_type_node) = tdecl;
11415 tdecl = add_builtin_type ("__vector __bool short", bool_V8HI_type_node);
11416 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11418 tdecl = add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node);
11419 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11421 tdecl = add_builtin_type ("__vector signed int", V4SI_type_node);
11422 TYPE_NAME (V4SI_type_node) = tdecl;
11424 tdecl = add_builtin_type ("__vector __bool int", bool_V4SI_type_node);
11425 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11427 tdecl = add_builtin_type ("__vector float", V4SF_type_node);
11428 TYPE_NAME (V4SF_type_node) = tdecl;
11430 tdecl = add_builtin_type ("__vector __pixel", pixel_V8HI_type_node);
11431 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11433 tdecl = add_builtin_type ("__vector double", V2DF_type_node);
11434 TYPE_NAME (V2DF_type_node) = tdecl;
11436 tdecl = add_builtin_type ("__vector long", V2DI_type_node);
11437 TYPE_NAME (V2DI_type_node) = tdecl;
11439 tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);
11440 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11442 tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
11443 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11445 /* Paired and SPE builtins are only available if you build a compiler with
11446 the appropriate options, so only create those builtins with the
11447 appropriate compiler option. Create Altivec and VSX builtins on machines
11448 with at least the general purpose extensions (970 and newer) to allow the
11449 use of the target attribute. */
11450 if (TARGET_PAIRED_FLOAT)
11451 paired_init_builtins ();
11453 spe_init_builtins ();
11454 if (TARGET_EXTRA_BUILTINS)
11455 altivec_init_builtins ();
11456 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11457 rs6000_common_init_builtins ();
11459 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11460 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11461 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11463 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11464 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11465 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11467 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11468 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11469 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11471 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11472 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11473 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11475 mode = (TARGET_64BIT) ? DImode : SImode;
11476 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11477 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11478 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11481 /* AIX libm provides clog as __clog. */
11482 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11483 set_user_assembler_name (tdecl, "__clog");
11486 #ifdef SUBTARGET_INIT_BUILTINS
11487 SUBTARGET_INIT_BUILTINS;
11491 /* Returns the rs6000 builtin decl for CODE. */
11494 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11498 if (code >= RS6000_BUILTIN_COUNT)
11499 return error_mark_node;
11501 fnmask = rs6000_builtin_info[code].mask;
11502 if ((fnmask & rs6000_builtin_mask) != fnmask)
11504 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11505 return error_mark_node;
11508 return rs6000_builtin_decls[code];
11512 spe_init_builtins (void)
11514 tree puint_type_node = build_pointer_type (unsigned_type_node);
11515 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11516 const struct builtin_description *d;
11519 tree v2si_ftype_4_v2si
11520 = build_function_type_list (opaque_V2SI_type_node,
11521 opaque_V2SI_type_node,
11522 opaque_V2SI_type_node,
11523 opaque_V2SI_type_node,
11524 opaque_V2SI_type_node,
11527 tree v2sf_ftype_4_v2sf
11528 = build_function_type_list (opaque_V2SF_type_node,
11529 opaque_V2SF_type_node,
11530 opaque_V2SF_type_node,
11531 opaque_V2SF_type_node,
11532 opaque_V2SF_type_node,
11535 tree int_ftype_int_v2si_v2si
11536 = build_function_type_list (integer_type_node,
11538 opaque_V2SI_type_node,
11539 opaque_V2SI_type_node,
11542 tree int_ftype_int_v2sf_v2sf
11543 = build_function_type_list (integer_type_node,
11545 opaque_V2SF_type_node,
11546 opaque_V2SF_type_node,
11549 tree void_ftype_v2si_puint_int
11550 = build_function_type_list (void_type_node,
11551 opaque_V2SI_type_node,
11556 tree void_ftype_v2si_puint_char
11557 = build_function_type_list (void_type_node,
11558 opaque_V2SI_type_node,
11563 tree void_ftype_v2si_pv2si_int
11564 = build_function_type_list (void_type_node,
11565 opaque_V2SI_type_node,
11566 opaque_p_V2SI_type_node,
11570 tree void_ftype_v2si_pv2si_char
11571 = build_function_type_list (void_type_node,
11572 opaque_V2SI_type_node,
11573 opaque_p_V2SI_type_node,
11577 tree void_ftype_int
11578 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11580 tree int_ftype_void
11581 = build_function_type_list (integer_type_node, NULL_TREE);
11583 tree v2si_ftype_pv2si_int
11584 = build_function_type_list (opaque_V2SI_type_node,
11585 opaque_p_V2SI_type_node,
11589 tree v2si_ftype_puint_int
11590 = build_function_type_list (opaque_V2SI_type_node,
11595 tree v2si_ftype_pushort_int
11596 = build_function_type_list (opaque_V2SI_type_node,
11601 tree v2si_ftype_signed_char
11602 = build_function_type_list (opaque_V2SI_type_node,
11603 signed_char_type_node,
11606 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
11608 /* Initialize irregular SPE builtins. */
11610 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11611 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11612 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11613 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11614 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11615 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11616 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11617 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11618 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11619 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11620 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11621 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11622 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11623 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11624 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11625 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11626 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11627 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11630 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11631 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11632 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11633 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11634 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11635 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11636 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11637 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11638 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11639 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11640 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11641 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11642 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11643 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11644 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11645 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11646 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11647 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11648 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11649 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11650 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11651 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11654 d = bdesc_spe_predicates;
11655 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11659 switch (insn_data[d->icode].operand[1].mode)
11662 type = int_ftype_int_v2si_v2si;
11665 type = int_ftype_int_v2sf_v2sf;
11668 gcc_unreachable ();
11671 def_builtin (d->name, type, d->code);
11674 /* Evsel predicates. */
11675 d = bdesc_spe_evsel;
11676 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11680 switch (insn_data[d->icode].operand[1].mode)
11683 type = v2si_ftype_4_v2si;
11686 type = v2sf_ftype_4_v2sf;
11689 gcc_unreachable ();
11692 def_builtin (d->name, type, d->code);
11697 paired_init_builtins (void)
11699 const struct builtin_description *d;
11702 tree int_ftype_int_v2sf_v2sf
11703 = build_function_type_list (integer_type_node,
11708 tree pcfloat_type_node =
11709 build_pointer_type (build_qualified_type
11710 (float_type_node, TYPE_QUAL_CONST));
11712 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
11713 long_integer_type_node,
11716 tree void_ftype_v2sf_long_pcfloat =
11717 build_function_type_list (void_type_node,
11719 long_integer_type_node,
11724 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
11725 PAIRED_BUILTIN_LX);
11728 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
11729 PAIRED_BUILTIN_STX);
11732 d = bdesc_paired_preds;
11733 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
11737 if (TARGET_DEBUG_BUILTIN)
11738 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
11739 (int)i, get_insn_name (d->icode), (int)d->icode,
11740 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
11742 switch (insn_data[d->icode].operand[1].mode)
11745 type = int_ftype_int_v2sf_v2sf;
11748 gcc_unreachable ();
11751 def_builtin (d->name, type, d->code);
11756 altivec_init_builtins (void)
11758 const struct builtin_description *d;
11763 tree pvoid_type_node = build_pointer_type (void_type_node);
11765 tree pcvoid_type_node
11766 = build_pointer_type (build_qualified_type (void_type_node,
11769 tree int_ftype_opaque
11770 = build_function_type_list (integer_type_node,
11771 opaque_V4SI_type_node, NULL_TREE);
11772 tree opaque_ftype_opaque
11773 = build_function_type_list (integer_type_node, NULL_TREE);
11774 tree opaque_ftype_opaque_int
11775 = build_function_type_list (opaque_V4SI_type_node,
11776 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
11777 tree opaque_ftype_opaque_opaque_int
11778 = build_function_type_list (opaque_V4SI_type_node,
11779 opaque_V4SI_type_node, opaque_V4SI_type_node,
11780 integer_type_node, NULL_TREE);
11781 tree int_ftype_int_opaque_opaque
11782 = build_function_type_list (integer_type_node,
11783 integer_type_node, opaque_V4SI_type_node,
11784 opaque_V4SI_type_node, NULL_TREE);
11785 tree int_ftype_int_v4si_v4si
11786 = build_function_type_list (integer_type_node,
11787 integer_type_node, V4SI_type_node,
11788 V4SI_type_node, NULL_TREE);
11789 tree void_ftype_v4si
11790 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
11791 tree v8hi_ftype_void
11792 = build_function_type_list (V8HI_type_node, NULL_TREE);
11793 tree void_ftype_void
11794 = build_function_type_list (void_type_node, NULL_TREE);
11795 tree void_ftype_int
11796 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11798 tree opaque_ftype_long_pcvoid
11799 = build_function_type_list (opaque_V4SI_type_node,
11800 long_integer_type_node, pcvoid_type_node,
11802 tree v16qi_ftype_long_pcvoid
11803 = build_function_type_list (V16QI_type_node,
11804 long_integer_type_node, pcvoid_type_node,
11806 tree v8hi_ftype_long_pcvoid
11807 = build_function_type_list (V8HI_type_node,
11808 long_integer_type_node, pcvoid_type_node,
11810 tree v4si_ftype_long_pcvoid
11811 = build_function_type_list (V4SI_type_node,
11812 long_integer_type_node, pcvoid_type_node,
11814 tree v4sf_ftype_long_pcvoid
11815 = build_function_type_list (V4SF_type_node,
11816 long_integer_type_node, pcvoid_type_node,
11818 tree v2df_ftype_long_pcvoid
11819 = build_function_type_list (V2DF_type_node,
11820 long_integer_type_node, pcvoid_type_node,
11822 tree v2di_ftype_long_pcvoid
11823 = build_function_type_list (V2DI_type_node,
11824 long_integer_type_node, pcvoid_type_node,
11827 tree void_ftype_opaque_long_pvoid
11828 = build_function_type_list (void_type_node,
11829 opaque_V4SI_type_node, long_integer_type_node,
11830 pvoid_type_node, NULL_TREE);
11831 tree void_ftype_v4si_long_pvoid
11832 = build_function_type_list (void_type_node,
11833 V4SI_type_node, long_integer_type_node,
11834 pvoid_type_node, NULL_TREE);
11835 tree void_ftype_v16qi_long_pvoid
11836 = build_function_type_list (void_type_node,
11837 V16QI_type_node, long_integer_type_node,
11838 pvoid_type_node, NULL_TREE);
11839 tree void_ftype_v8hi_long_pvoid
11840 = build_function_type_list (void_type_node,
11841 V8HI_type_node, long_integer_type_node,
11842 pvoid_type_node, NULL_TREE);
11843 tree void_ftype_v4sf_long_pvoid
11844 = build_function_type_list (void_type_node,
11845 V4SF_type_node, long_integer_type_node,
11846 pvoid_type_node, NULL_TREE);
11847 tree void_ftype_v2df_long_pvoid
11848 = build_function_type_list (void_type_node,
11849 V2DF_type_node, long_integer_type_node,
11850 pvoid_type_node, NULL_TREE);
11851 tree void_ftype_v2di_long_pvoid
11852 = build_function_type_list (void_type_node,
11853 V2DI_type_node, long_integer_type_node,
11854 pvoid_type_node, NULL_TREE);
11855 tree int_ftype_int_v8hi_v8hi
11856 = build_function_type_list (integer_type_node,
11857 integer_type_node, V8HI_type_node,
11858 V8HI_type_node, NULL_TREE);
11859 tree int_ftype_int_v16qi_v16qi
11860 = build_function_type_list (integer_type_node,
11861 integer_type_node, V16QI_type_node,
11862 V16QI_type_node, NULL_TREE);
11863 tree int_ftype_int_v4sf_v4sf
11864 = build_function_type_list (integer_type_node,
11865 integer_type_node, V4SF_type_node,
11866 V4SF_type_node, NULL_TREE);
11867 tree int_ftype_int_v2df_v2df
11868 = build_function_type_list (integer_type_node,
11869 integer_type_node, V2DF_type_node,
11870 V2DF_type_node, NULL_TREE);
11871 tree v4si_ftype_v4si
11872 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
11873 tree v8hi_ftype_v8hi
11874 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
11875 tree v16qi_ftype_v16qi
11876 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
11877 tree v4sf_ftype_v4sf
11878 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
11879 tree v2df_ftype_v2df
11880 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
11881 tree void_ftype_pcvoid_int_int
11882 = build_function_type_list (void_type_node,
11883 pcvoid_type_node, integer_type_node,
11884 integer_type_node, NULL_TREE);
11886 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
11887 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
11888 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
11889 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
11890 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
11891 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
11892 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
11893 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
11894 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
11895 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
11896 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
11897 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
11898 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
11899 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
11900 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
11901 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
11902 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
11903 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
11904 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
11905 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
11906 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
11907 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
11908 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
11909 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
11910 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
11911 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
11912 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
11913 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
11914 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
11915 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
11917 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
11918 VSX_BUILTIN_LXVD2X_V2DF);
11919 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
11920 VSX_BUILTIN_LXVD2X_V2DI);
11921 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
11922 VSX_BUILTIN_LXVW4X_V4SF);
11923 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
11924 VSX_BUILTIN_LXVW4X_V4SI);
11925 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
11926 VSX_BUILTIN_LXVW4X_V8HI);
11927 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
11928 VSX_BUILTIN_LXVW4X_V16QI);
11929 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
11930 VSX_BUILTIN_STXVD2X_V2DF);
11931 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
11932 VSX_BUILTIN_STXVD2X_V2DI);
11933 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
11934 VSX_BUILTIN_STXVW4X_V4SF);
11935 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
11936 VSX_BUILTIN_STXVW4X_V4SI);
11937 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
11938 VSX_BUILTIN_STXVW4X_V8HI);
11939 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
11940 VSX_BUILTIN_STXVW4X_V16QI);
11941 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
11942 VSX_BUILTIN_VEC_LD);
11943 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
11944 VSX_BUILTIN_VEC_ST);
11946 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
11947 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
11948 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
11950 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
11951 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
11952 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
11953 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
11954 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
11955 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
11956 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
11957 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
11958 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
11959 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
11960 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
11961 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
11963 /* Cell builtins. */
11964 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
11965 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
11966 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
11967 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
11969 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
11970 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
11971 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
11972 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
11974 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
11975 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
11976 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
11977 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
11979 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
11980 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
11981 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
11982 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
11984 /* Add the DST variants. */
11986 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
11987 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
11989 /* Initialize the predicates. */
11990 d = bdesc_altivec_preds;
11991 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
11993 enum machine_mode mode1;
11996 if (rs6000_overloaded_builtin_p (d->code))
11999 mode1 = insn_data[d->icode].operand[1].mode;
12004 type = int_ftype_int_opaque_opaque;
12007 type = int_ftype_int_v4si_v4si;
12010 type = int_ftype_int_v8hi_v8hi;
12013 type = int_ftype_int_v16qi_v16qi;
12016 type = int_ftype_int_v4sf_v4sf;
12019 type = int_ftype_int_v2df_v2df;
12022 gcc_unreachable ();
12025 def_builtin (d->name, type, d->code);
12028 /* Initialize the abs* operators. */
12030 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12032 enum machine_mode mode0;
12035 mode0 = insn_data[d->icode].operand[0].mode;
12040 type = v4si_ftype_v4si;
12043 type = v8hi_ftype_v8hi;
12046 type = v16qi_ftype_v16qi;
12049 type = v4sf_ftype_v4sf;
12052 type = v2df_ftype_v2df;
12055 gcc_unreachable ();
12058 def_builtin (d->name, type, d->code);
12061 /* Initialize target builtin that implements
12062 targetm.vectorize.builtin_mask_for_load. */
12064 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12065 v16qi_ftype_long_pcvoid,
12066 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12067 BUILT_IN_MD, NULL, NULL_TREE);
12068 TREE_READONLY (decl) = 1;
12069 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12070 altivec_builtin_mask_for_load = decl;
12072 /* Access to the vec_init patterns. */
12073 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12074 integer_type_node, integer_type_node,
12075 integer_type_node, NULL_TREE);
12076 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12078 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12079 short_integer_type_node,
12080 short_integer_type_node,
12081 short_integer_type_node,
12082 short_integer_type_node,
12083 short_integer_type_node,
12084 short_integer_type_node,
12085 short_integer_type_node, NULL_TREE);
12086 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12088 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12089 char_type_node, char_type_node,
12090 char_type_node, char_type_node,
12091 char_type_node, char_type_node,
12092 char_type_node, char_type_node,
12093 char_type_node, char_type_node,
12094 char_type_node, char_type_node,
12095 char_type_node, char_type_node,
12096 char_type_node, NULL_TREE);
12097 def_builtin ("__builtin_vec_init_v16qi", ftype,
12098 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12100 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12101 float_type_node, float_type_node,
12102 float_type_node, NULL_TREE);
12103 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12105 /* VSX builtins. */
12106 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12107 double_type_node, NULL_TREE);
12108 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12110 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12111 intDI_type_node, NULL_TREE);
12112 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12114 /* Access to the vec_set patterns. */
12115 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12117 integer_type_node, NULL_TREE);
12118 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12120 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12122 integer_type_node, NULL_TREE);
12123 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12125 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12127 integer_type_node, NULL_TREE);
12128 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12130 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12132 integer_type_node, NULL_TREE);
12133 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12135 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12137 integer_type_node, NULL_TREE);
12138 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12140 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12142 integer_type_node, NULL_TREE);
12143 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12145 /* Access to the vec_extract patterns. */
12146 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12147 integer_type_node, NULL_TREE);
12148 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12150 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12151 integer_type_node, NULL_TREE);
12152 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12154 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12155 integer_type_node, NULL_TREE);
12156 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12158 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12159 integer_type_node, NULL_TREE);
12160 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12162 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12163 integer_type_node, NULL_TREE);
12164 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12166 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12167 integer_type_node, NULL_TREE);
12168 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12171 /* Hash function for builtin functions with up to 3 arguments and a return
12174 builtin_hash_function (const void *hash_entry)
12178 const struct builtin_hash_struct *bh =
12179 (const struct builtin_hash_struct *) hash_entry;
12181 for (i = 0; i < 4; i++)
12183 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12184 ret = (ret * 2) + bh->uns_p[i];
12190 /* Compare builtin hash entries H1 and H2 for equivalence. */
12192 builtin_hash_eq (const void *h1, const void *h2)
12194 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12195 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12197 return ((p1->mode[0] == p2->mode[0])
12198 && (p1->mode[1] == p2->mode[1])
12199 && (p1->mode[2] == p2->mode[2])
12200 && (p1->mode[3] == p2->mode[3])
12201 && (p1->uns_p[0] == p2->uns_p[0])
12202 && (p1->uns_p[1] == p2->uns_p[1])
12203 && (p1->uns_p[2] == p2->uns_p[2])
12204 && (p1->uns_p[3] == p2->uns_p[3]));
12207 /* Map types for builtin functions with an explicit return type and up to 3
12208 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12209 of the argument. */
12211 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12212 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12213 enum rs6000_builtins builtin, const char *name)
12215 struct builtin_hash_struct h;
12216 struct builtin_hash_struct *h2;
12220 tree ret_type = NULL_TREE;
12221 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12223 /* Create builtin_hash_table. */
12224 if (builtin_hash_table == NULL)
12225 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12226 builtin_hash_eq, NULL);
12228 h.type = NULL_TREE;
12229 h.mode[0] = mode_ret;
12230 h.mode[1] = mode_arg0;
12231 h.mode[2] = mode_arg1;
12232 h.mode[3] = mode_arg2;
12238 /* If the builtin is a type that produces unsigned results or takes unsigned
12239 arguments, and it is returned as a decl for the vectorizer (such as
12240 widening multiplies, permute), make sure the arguments and return value
12241 are type correct. */
12244 /* unsigned 2 argument functions. */
12245 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12246 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12247 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12248 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12254 /* unsigned 3 argument functions. */
12255 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12256 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12257 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12258 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12259 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12260 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12261 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12262 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12263 case VSX_BUILTIN_VPERM_16QI_UNS:
12264 case VSX_BUILTIN_VPERM_8HI_UNS:
12265 case VSX_BUILTIN_VPERM_4SI_UNS:
12266 case VSX_BUILTIN_VPERM_2DI_UNS:
12267 case VSX_BUILTIN_XXSEL_16QI_UNS:
12268 case VSX_BUILTIN_XXSEL_8HI_UNS:
12269 case VSX_BUILTIN_XXSEL_4SI_UNS:
12270 case VSX_BUILTIN_XXSEL_2DI_UNS:
12277 /* signed permute functions with unsigned char mask. */
12278 case ALTIVEC_BUILTIN_VPERM_16QI:
12279 case ALTIVEC_BUILTIN_VPERM_8HI:
12280 case ALTIVEC_BUILTIN_VPERM_4SI:
12281 case ALTIVEC_BUILTIN_VPERM_4SF:
12282 case ALTIVEC_BUILTIN_VPERM_2DI:
12283 case ALTIVEC_BUILTIN_VPERM_2DF:
12284 case VSX_BUILTIN_VPERM_16QI:
12285 case VSX_BUILTIN_VPERM_8HI:
12286 case VSX_BUILTIN_VPERM_4SI:
12287 case VSX_BUILTIN_VPERM_4SF:
12288 case VSX_BUILTIN_VPERM_2DI:
12289 case VSX_BUILTIN_VPERM_2DF:
12293 /* unsigned args, signed return. */
12294 case VSX_BUILTIN_XVCVUXDDP_UNS:
12295 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12299 /* signed args, unsigned return. */
12300 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12301 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12309 /* Figure out how many args are present. */
12310 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12314 fatal_error ("internal error: builtin function %s had no type", name);
12316 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12317 if (!ret_type && h.uns_p[0])
12318 ret_type = builtin_mode_to_type[h.mode[0]][0];
12321 fatal_error ("internal error: builtin function %s had an unexpected "
12322 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12324 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12325 arg_type[i] = NULL_TREE;
12327 for (i = 0; i < num_args; i++)
12329 int m = (int) h.mode[i+1];
12330 int uns_p = h.uns_p[i+1];
12332 arg_type[i] = builtin_mode_to_type[m][uns_p];
12333 if (!arg_type[i] && uns_p)
12334 arg_type[i] = builtin_mode_to_type[m][0];
12337 fatal_error ("internal error: builtin function %s, argument %d "
12338 "had unexpected argument type %s", name, i,
12339 GET_MODE_NAME (m));
12342 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12343 if (*found == NULL)
12345 h2 = ggc_alloc_builtin_hash_struct ();
12347 *found = (void *)h2;
12349 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12350 arg_type[2], NULL_TREE);
12353 return ((struct builtin_hash_struct *)(*found))->type;
12357 rs6000_common_init_builtins (void)
12359 const struct builtin_description *d;
12362 tree opaque_ftype_opaque = NULL_TREE;
12363 tree opaque_ftype_opaque_opaque = NULL_TREE;
12364 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12365 tree v2si_ftype_qi = NULL_TREE;
12366 tree v2si_ftype_v2si_qi = NULL_TREE;
12367 tree v2si_ftype_int_qi = NULL_TREE;
12368 unsigned builtin_mask = rs6000_builtin_mask;
12370 if (!TARGET_PAIRED_FLOAT)
12372 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12373 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12376 /* Paired and SPE builtins are only available if you build a compiler with
12377 the appropriate options, so only create those builtins with the
12378 appropriate compiler option. Create Altivec and VSX builtins on machines
12379 with at least the general purpose extensions (970 and newer) to allow the
12380 use of the target attribute.. */
12382 if (TARGET_EXTRA_BUILTINS)
12383 builtin_mask |= RS6000_BTM_COMMON;
12385 /* Add the ternary operators. */
12387 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12390 unsigned mask = d->mask;
12392 if ((mask & builtin_mask) != mask)
12394 if (TARGET_DEBUG_BUILTIN)
12395 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12399 if (rs6000_overloaded_builtin_p (d->code))
12401 if (! (type = opaque_ftype_opaque_opaque_opaque))
12402 type = opaque_ftype_opaque_opaque_opaque
12403 = build_function_type_list (opaque_V4SI_type_node,
12404 opaque_V4SI_type_node,
12405 opaque_V4SI_type_node,
12406 opaque_V4SI_type_node,
12411 enum insn_code icode = d->icode;
12412 if (d->name == 0 || icode == CODE_FOR_nothing)
12415 type = builtin_function_type (insn_data[icode].operand[0].mode,
12416 insn_data[icode].operand[1].mode,
12417 insn_data[icode].operand[2].mode,
12418 insn_data[icode].operand[3].mode,
12422 def_builtin (d->name, type, d->code);
12425 /* Add the binary operators. */
12427 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12429 enum machine_mode mode0, mode1, mode2;
12431 unsigned mask = d->mask;
12433 if ((mask & builtin_mask) != mask)
12435 if (TARGET_DEBUG_BUILTIN)
12436 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12440 if (rs6000_overloaded_builtin_p (d->code))
12442 if (! (type = opaque_ftype_opaque_opaque))
12443 type = opaque_ftype_opaque_opaque
12444 = build_function_type_list (opaque_V4SI_type_node,
12445 opaque_V4SI_type_node,
12446 opaque_V4SI_type_node,
12451 enum insn_code icode = d->icode;
12452 if (d->name == 0 || icode == CODE_FOR_nothing)
12455 mode0 = insn_data[icode].operand[0].mode;
12456 mode1 = insn_data[icode].operand[1].mode;
12457 mode2 = insn_data[icode].operand[2].mode;
12459 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12461 if (! (type = v2si_ftype_v2si_qi))
12462 type = v2si_ftype_v2si_qi
12463 = build_function_type_list (opaque_V2SI_type_node,
12464 opaque_V2SI_type_node,
12469 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12470 && mode2 == QImode)
12472 if (! (type = v2si_ftype_int_qi))
12473 type = v2si_ftype_int_qi
12474 = build_function_type_list (opaque_V2SI_type_node,
12481 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12485 def_builtin (d->name, type, d->code);
12488 /* Add the simple unary operators. */
12490 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12492 enum machine_mode mode0, mode1;
12494 unsigned mask = d->mask;
12496 if ((mask & builtin_mask) != mask)
12498 if (TARGET_DEBUG_BUILTIN)
12499 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12503 if (rs6000_overloaded_builtin_p (d->code))
12505 if (! (type = opaque_ftype_opaque))
12506 type = opaque_ftype_opaque
12507 = build_function_type_list (opaque_V4SI_type_node,
12508 opaque_V4SI_type_node,
12513 enum insn_code icode = d->icode;
12514 if (d->name == 0 || icode == CODE_FOR_nothing)
12517 mode0 = insn_data[icode].operand[0].mode;
12518 mode1 = insn_data[icode].operand[1].mode;
12520 if (mode0 == V2SImode && mode1 == QImode)
12522 if (! (type = v2si_ftype_qi))
12523 type = v2si_ftype_qi
12524 = build_function_type_list (opaque_V2SI_type_node,
12530 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12534 def_builtin (d->name, type, d->code);
12539 rs6000_init_libfuncs (void)
12541 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
12542 && !TARGET_POWER2 && !TARGET_POWERPC)
12544 /* AIX library routines for float->int conversion. */
12545 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
12546 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
12547 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
12548 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
12551 if (!TARGET_IEEEQUAD)
12552 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12553 if (!TARGET_XL_COMPAT)
12555 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12556 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12557 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12558 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12560 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12562 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12563 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12564 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12565 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12566 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12567 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12568 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12570 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12571 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12572 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12573 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12574 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12575 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12576 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12577 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12580 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12581 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12585 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12586 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12587 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12588 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12592 /* 32-bit SVR4 quad floating point routines. */
12594 set_optab_libfunc (add_optab, TFmode, "_q_add");
12595 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12596 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12597 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12598 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12599 if (TARGET_PPC_GPOPT || TARGET_POWER2)
12600 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12602 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12603 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12604 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12605 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12606 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12607 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12609 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12610 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12611 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12612 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12613 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12614 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12615 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12616 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12621 /* Expand a block clear operation, and return 1 if successful. Return 0
12622 if we should let the compiler generate normal code.
12624 operands[0] is the destination
12625 operands[1] is the length
12626 operands[3] is the alignment */
12629 expand_block_clear (rtx operands[])
12631 rtx orig_dest = operands[0];
12632 rtx bytes_rtx = operands[1];
12633 rtx align_rtx = operands[3];
12634 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12635 HOST_WIDE_INT align;
12636 HOST_WIDE_INT bytes;
12641 /* If this is not a fixed size move, just call memcpy */
12645 /* This must be a fixed size alignment */
12646 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12647 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12649 /* Anything to clear? */
12650 bytes = INTVAL (bytes_rtx);
12654 /* Use the builtin memset after a point, to avoid huge code bloat.
12655 When optimize_size, avoid any significant code bloat; calling
12656 memset is about 4 instructions, so allow for one instruction to
12657 load zero and three to do clearing. */
12658 if (TARGET_ALTIVEC && align >= 128)
12660 else if (TARGET_POWERPC64 && align >= 32)
12662 else if (TARGET_SPE && align >= 64)
12667 if (optimize_size && bytes > 3 * clear_step)
12669 if (! optimize_size && bytes > 8 * clear_step)
12672 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12674 enum machine_mode mode = BLKmode;
12677 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12682 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12687 else if (bytes >= 8 && TARGET_POWERPC64
12688 /* 64-bit loads and stores require word-aligned
12690 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12695 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12696 { /* move 4 bytes */
12700 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12701 { /* move 2 bytes */
12705 else /* move 1 byte at a time */
12711 dest = adjust_address (orig_dest, mode, offset);
12713 emit_move_insn (dest, CONST0_RTX (mode));
12720 /* Expand a block move operation, and return 1 if successful. Return 0
12721 if we should let the compiler generate normal code.
12723 operands[0] is the destination
12724 operands[1] is the source
12725 operands[2] is the length
12726 operands[3] is the alignment */
12728 #define MAX_MOVE_REG 4
12731 expand_block_move (rtx operands[])
12733 rtx orig_dest = operands[0];
12734 rtx orig_src = operands[1];
12735 rtx bytes_rtx = operands[2];
12736 rtx align_rtx = operands[3];
12737 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
12742 rtx stores[MAX_MOVE_REG];
12745 /* If this is not a fixed size move, just call memcpy */
12749 /* This must be a fixed size alignment */
12750 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12751 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12753 /* Anything to move? */
12754 bytes = INTVAL (bytes_rtx);
12758 if (bytes > rs6000_block_move_inline_limit)
12761 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
12764 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
12765 rtx (*mov) (rtx, rtx);
12767 enum machine_mode mode = BLKmode;
12770 /* Altivec first, since it will be faster than a string move
12771 when it applies, and usually not significantly larger. */
12772 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
12776 gen_func.mov = gen_movv4si;
12778 else if (TARGET_SPE && bytes >= 8 && align >= 64)
12782 gen_func.mov = gen_movv2si;
12784 else if (TARGET_STRING
12785 && bytes > 24 /* move up to 32 bytes at a time */
12791 && ! fixed_regs[10]
12792 && ! fixed_regs[11]
12793 && ! fixed_regs[12])
12795 move_bytes = (bytes > 32) ? 32 : bytes;
12796 gen_func.movmemsi = gen_movmemsi_8reg;
12798 else if (TARGET_STRING
12799 && bytes > 16 /* move up to 24 bytes at a time */
12805 && ! fixed_regs[10])
12807 move_bytes = (bytes > 24) ? 24 : bytes;
12808 gen_func.movmemsi = gen_movmemsi_6reg;
12810 else if (TARGET_STRING
12811 && bytes > 8 /* move up to 16 bytes at a time */
12815 && ! fixed_regs[8])
12817 move_bytes = (bytes > 16) ? 16 : bytes;
12818 gen_func.movmemsi = gen_movmemsi_4reg;
12820 else if (bytes >= 8 && TARGET_POWERPC64
12821 /* 64-bit loads and stores require word-aligned
12823 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12827 gen_func.mov = gen_movdi;
12829 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
12830 { /* move up to 8 bytes at a time */
12831 move_bytes = (bytes > 8) ? 8 : bytes;
12832 gen_func.movmemsi = gen_movmemsi_2reg;
12834 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12835 { /* move 4 bytes */
12838 gen_func.mov = gen_movsi;
12840 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12841 { /* move 2 bytes */
12844 gen_func.mov = gen_movhi;
12846 else if (TARGET_STRING && bytes > 1)
12847 { /* move up to 4 bytes at a time */
12848 move_bytes = (bytes > 4) ? 4 : bytes;
12849 gen_func.movmemsi = gen_movmemsi_1reg;
12851 else /* move 1 byte at a time */
12855 gen_func.mov = gen_movqi;
12858 src = adjust_address (orig_src, mode, offset);
12859 dest = adjust_address (orig_dest, mode, offset);
12861 if (mode != BLKmode)
12863 rtx tmp_reg = gen_reg_rtx (mode);
12865 emit_insn ((*gen_func.mov) (tmp_reg, src));
12866 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
12869 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
12872 for (i = 0; i < num_reg; i++)
12873 emit_insn (stores[i]);
12877 if (mode == BLKmode)
12879 /* Move the address into scratch registers. The movmemsi
12880 patterns require zero offset. */
12881 if (!REG_P (XEXP (src, 0)))
12883 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
12884 src = replace_equiv_address (src, src_reg);
12886 set_mem_size (src, move_bytes);
12888 if (!REG_P (XEXP (dest, 0)))
12890 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
12891 dest = replace_equiv_address (dest, dest_reg);
12893 set_mem_size (dest, move_bytes);
12895 emit_insn ((*gen_func.movmemsi) (dest, src,
12896 GEN_INT (move_bytes & 31),
12905 /* Return a string to perform a load_multiple operation.
12906 operands[0] is the vector.
12907 operands[1] is the source address.
12908 operands[2] is the first destination register. */
12911 rs6000_output_load_multiple (rtx operands[3])
12913 /* We have to handle the case where the pseudo used to contain the address
12914 is assigned to one of the output registers. */
12916 int words = XVECLEN (operands[0], 0);
12919 if (XVECLEN (operands[0], 0) == 1)
12920 return "{l|lwz} %2,0(%1)";
12922 for (i = 0; i < words; i++)
12923 if (refers_to_regno_p (REGNO (operands[2]) + i,
12924 REGNO (operands[2]) + i + 1, operands[1], 0))
12928 xop[0] = GEN_INT (4 * (words-1));
12929 xop[1] = operands[1];
12930 xop[2] = operands[2];
12931 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
12936 xop[0] = GEN_INT (4 * (words-1));
12937 xop[1] = operands[1];
12938 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12939 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
12944 for (j = 0; j < words; j++)
12947 xop[0] = GEN_INT (j * 4);
12948 xop[1] = operands[1];
12949 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
12950 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
12952 xop[0] = GEN_INT (i * 4);
12953 xop[1] = operands[1];
12954 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
12959 return "{lsi|lswi} %2,%1,%N0";
12963 /* A validation routine: say whether CODE, a condition code, and MODE
12964 match. The other alternatives either don't make sense or should
12965 never be generated. */
12968 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
12970 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
12971 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
12972 && GET_MODE_CLASS (mode) == MODE_CC);
12974 /* These don't make sense. */
12975 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
12976 || mode != CCUNSmode);
12978 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
12979 || mode == CCUNSmode);
12981 gcc_assert (mode == CCFPmode
12982 || (code != ORDERED && code != UNORDERED
12983 && code != UNEQ && code != LTGT
12984 && code != UNGT && code != UNLT
12985 && code != UNGE && code != UNLE));
12987 /* These should never be generated except for
12988 flag_finite_math_only. */
12989 gcc_assert (mode != CCFPmode
12990 || flag_finite_math_only
12991 || (code != LE && code != GE
12992 && code != UNEQ && code != LTGT
12993 && code != UNGT && code != UNLT));
12995 /* These are invalid; the information is not there. */
12996 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13000 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13001 mask required to convert the result of a rotate insn into a shift
13002 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13005 includes_lshift_p (rtx shiftop, rtx andop)
13007 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13009 shift_mask <<= INTVAL (shiftop);
13011 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13014 /* Similar, but for right shift. */
13017 includes_rshift_p (rtx shiftop, rtx andop)
13019 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13021 shift_mask >>= INTVAL (shiftop);
13023 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13026 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13027 to perform a left shift. It must have exactly SHIFTOP least
13028 significant 0's, then one or more 1's, then zero or more 0's. */
13031 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13033 if (GET_CODE (andop) == CONST_INT)
13035 HOST_WIDE_INT c, lsb, shift_mask;
13037 c = INTVAL (andop);
13038 if (c == 0 || c == ~0)
13042 shift_mask <<= INTVAL (shiftop);
13044 /* Find the least significant one bit. */
13047 /* It must coincide with the LSB of the shift mask. */
13048 if (-lsb != shift_mask)
13051 /* Invert to look for the next transition (if any). */
13054 /* Remove the low group of ones (originally low group of zeros). */
13057 /* Again find the lsb, and check we have all 1's above. */
13061 else if (GET_CODE (andop) == CONST_DOUBLE
13062 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13064 HOST_WIDE_INT low, high, lsb;
13065 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13067 low = CONST_DOUBLE_LOW (andop);
13068 if (HOST_BITS_PER_WIDE_INT < 64)
13069 high = CONST_DOUBLE_HIGH (andop);
13071 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13072 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13075 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13077 shift_mask_high = ~0;
13078 if (INTVAL (shiftop) > 32)
13079 shift_mask_high <<= INTVAL (shiftop) - 32;
13081 lsb = high & -high;
13083 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13089 lsb = high & -high;
13090 return high == -lsb;
13093 shift_mask_low = ~0;
13094 shift_mask_low <<= INTVAL (shiftop);
13098 if (-lsb != shift_mask_low)
13101 if (HOST_BITS_PER_WIDE_INT < 64)
13106 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13108 lsb = high & -high;
13109 return high == -lsb;
13113 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13119 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13120 to perform a left shift. It must have SHIFTOP or more least
13121 significant 0's, with the remainder of the word 1's. */
13124 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13126 if (GET_CODE (andop) == CONST_INT)
13128 HOST_WIDE_INT c, lsb, shift_mask;
13131 shift_mask <<= INTVAL (shiftop);
13132 c = INTVAL (andop);
13134 /* Find the least significant one bit. */
13137 /* It must be covered by the shift mask.
13138 This test also rejects c == 0. */
13139 if ((lsb & shift_mask) == 0)
13142 /* Check we have all 1's above the transition, and reject all 1's. */
13143 return c == -lsb && lsb != 1;
13145 else if (GET_CODE (andop) == CONST_DOUBLE
13146 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13148 HOST_WIDE_INT low, lsb, shift_mask_low;
13150 low = CONST_DOUBLE_LOW (andop);
13152 if (HOST_BITS_PER_WIDE_INT < 64)
13154 HOST_WIDE_INT high, shift_mask_high;
13156 high = CONST_DOUBLE_HIGH (andop);
13160 shift_mask_high = ~0;
13161 if (INTVAL (shiftop) > 32)
13162 shift_mask_high <<= INTVAL (shiftop) - 32;
13164 lsb = high & -high;
13166 if ((lsb & shift_mask_high) == 0)
13169 return high == -lsb;
13175 shift_mask_low = ~0;
13176 shift_mask_low <<= INTVAL (shiftop);
13180 if ((lsb & shift_mask_low) == 0)
13183 return low == -lsb && lsb != 1;
13189 /* Return 1 if operands will generate a valid arguments to rlwimi
13190 instruction for insert with right shift in 64-bit mode. The mask may
13191 not start on the first bit or stop on the last bit because wrap-around
13192 effects of instruction do not correspond to semantics of RTL insn. */
13195 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13197 if (INTVAL (startop) > 32
13198 && INTVAL (startop) < 64
13199 && INTVAL (sizeop) > 1
13200 && INTVAL (sizeop) + INTVAL (startop) < 64
13201 && INTVAL (shiftop) > 0
13202 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13203 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13209 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13210 for lfq and stfq insns iff the registers are hard registers. */
13213 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13215 /* We might have been passed a SUBREG. */
13216 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13219 /* We might have been passed non floating point registers. */
13220 if (!FP_REGNO_P (REGNO (reg1))
13221 || !FP_REGNO_P (REGNO (reg2)))
13224 return (REGNO (reg1) == REGNO (reg2) - 1);
13227 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13228 addr1 and addr2 must be in consecutive memory locations
13229 (addr2 == addr1 + 8). */
13232 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13235 unsigned int reg1, reg2;
13236 int offset1, offset2;
13238 /* The mems cannot be volatile. */
13239 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13242 addr1 = XEXP (mem1, 0);
13243 addr2 = XEXP (mem2, 0);
13245 /* Extract an offset (if used) from the first addr. */
13246 if (GET_CODE (addr1) == PLUS)
13248 /* If not a REG, return zero. */
13249 if (GET_CODE (XEXP (addr1, 0)) != REG)
13253 reg1 = REGNO (XEXP (addr1, 0));
13254 /* The offset must be constant! */
13255 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13257 offset1 = INTVAL (XEXP (addr1, 1));
13260 else if (GET_CODE (addr1) != REG)
13264 reg1 = REGNO (addr1);
13265 /* This was a simple (mem (reg)) expression. Offset is 0. */
13269 /* And now for the second addr. */
13270 if (GET_CODE (addr2) == PLUS)
13272 /* If not a REG, return zero. */
13273 if (GET_CODE (XEXP (addr2, 0)) != REG)
13277 reg2 = REGNO (XEXP (addr2, 0));
13278 /* The offset must be constant. */
13279 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13281 offset2 = INTVAL (XEXP (addr2, 1));
13284 else if (GET_CODE (addr2) != REG)
13288 reg2 = REGNO (addr2);
13289 /* This was a simple (mem (reg)) expression. Offset is 0. */
13293 /* Both of these must have the same base register. */
13297 /* The offset for the second addr must be 8 more than the first addr. */
13298 if (offset2 != offset1 + 8)
13301 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13308 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13310 static bool eliminated = false;
13313 if (mode != SDmode)
13314 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13317 rtx mem = cfun->machine->sdmode_stack_slot;
13318 gcc_assert (mem != NULL_RTX);
13322 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13323 cfun->machine->sdmode_stack_slot = mem;
13329 if (TARGET_DEBUG_ADDR)
13331 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13332 GET_MODE_NAME (mode));
13334 fprintf (stderr, "\tNULL_RTX\n");
13343 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13345 /* Don't walk into types. */
13346 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13348 *walk_subtrees = 0;
13352 switch (TREE_CODE (*tp))
13361 case VIEW_CONVERT_EXPR:
13362 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13372 enum reload_reg_type {
13374 VECTOR_REGISTER_TYPE,
13375 OTHER_REGISTER_TYPE
13378 static enum reload_reg_type
13379 rs6000_reload_register_type (enum reg_class rclass)
13385 return GPR_REGISTER_TYPE;
13390 return VECTOR_REGISTER_TYPE;
13393 return OTHER_REGISTER_TYPE;
13397 /* Inform reload about cases where moving X with a mode MODE to a register in
13398 RCLASS requires an extra scratch or immediate register. Return the class
13399 needed for the immediate register.
13401 For VSX and Altivec, we may need a register to convert sp+offset into
13404 For misaligned 64-bit gpr loads and stores we need a register to
13405 convert an offset address to indirect. */
13408 rs6000_secondary_reload (bool in_p,
13410 reg_class_t rclass_i,
13411 enum machine_mode mode,
13412 secondary_reload_info *sri)
13414 enum reg_class rclass = (enum reg_class) rclass_i;
13415 reg_class_t ret = ALL_REGS;
13416 enum insn_code icode;
13417 bool default_p = false;
13419 sri->icode = CODE_FOR_nothing;
13421 /* Convert vector loads and stores into gprs to use an additional base
13423 icode = rs6000_vector_reload[mode][in_p != false];
13424 if (icode != CODE_FOR_nothing)
13427 sri->icode = CODE_FOR_nothing;
13428 sri->extra_cost = 0;
13430 if (GET_CODE (x) == MEM)
13432 rtx addr = XEXP (x, 0);
13434 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13435 an extra register in that case, but it would need an extra
13436 register if the addressing is reg+reg or (reg+reg)&(-16). */
13437 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13439 if (!legitimate_indirect_address_p (addr, false)
13440 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13442 sri->icode = icode;
13443 /* account for splitting the loads, and converting the
13444 address from reg+reg to reg. */
13445 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13446 + ((GET_CODE (addr) == AND) ? 1 : 0));
13449 /* Loads to and stores from vector registers can only do reg+reg
13450 addressing. Altivec registers can also do (reg+reg)&(-16). */
13451 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13452 || rclass == FLOAT_REGS || rclass == NO_REGS)
13454 if (!VECTOR_MEM_ALTIVEC_P (mode)
13455 && GET_CODE (addr) == AND
13456 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13457 && INTVAL (XEXP (addr, 1)) == -16
13458 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13459 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13461 sri->icode = icode;
13462 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13465 else if (!legitimate_indirect_address_p (addr, false)
13466 && (rclass == NO_REGS
13467 || !legitimate_indexed_address_p (addr, false)))
13469 sri->icode = icode;
13470 sri->extra_cost = 1;
13473 icode = CODE_FOR_nothing;
13475 /* Any other loads, including to pseudo registers which haven't been
13476 assigned to a register yet, default to require a scratch
13480 sri->icode = icode;
13481 sri->extra_cost = 2;
13484 else if (REG_P (x))
13486 int regno = true_regnum (x);
13488 icode = CODE_FOR_nothing;
13489 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13493 enum reg_class xclass = REGNO_REG_CLASS (regno);
13494 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13495 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13497 /* If memory is needed, use default_secondary_reload to create the
13499 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13508 else if (TARGET_POWERPC64
13509 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13511 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13513 rtx addr = XEXP (x, 0);
13515 if (GET_CODE (addr) == PRE_MODIFY)
13516 addr = XEXP (addr, 1);
13517 else if (GET_CODE (addr) == LO_SUM
13518 && GET_CODE (XEXP (addr, 0)) == REG
13519 && GET_CODE (XEXP (addr, 1)) == CONST)
13520 addr = XEXP (XEXP (addr, 1), 0);
13522 if (GET_CODE (addr) == PLUS
13523 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13524 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
13527 sri->icode = CODE_FOR_reload_di_load;
13529 sri->icode = CODE_FOR_reload_di_store;
13530 sri->extra_cost = 2;
13540 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13542 gcc_assert (ret != ALL_REGS);
13544 if (TARGET_DEBUG_ADDR)
13547 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13549 reg_class_names[ret],
13550 in_p ? "true" : "false",
13551 reg_class_names[rclass],
13552 GET_MODE_NAME (mode));
13555 fprintf (stderr, ", default secondary reload");
13557 if (sri->icode != CODE_FOR_nothing)
13558 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13559 insn_data[sri->icode].name, sri->extra_cost);
13561 fprintf (stderr, "\n");
13569 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13570 to SP+reg addressing. */
13573 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13575 int regno = true_regnum (reg);
13576 enum machine_mode mode = GET_MODE (reg);
13577 enum reg_class rclass;
13579 rtx and_op2 = NULL_RTX;
13582 rtx scratch_or_premodify = scratch;
13586 if (TARGET_DEBUG_ADDR)
13588 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13589 store_p ? "store" : "load");
13590 fprintf (stderr, "reg:\n");
13592 fprintf (stderr, "mem:\n");
13594 fprintf (stderr, "scratch:\n");
13595 debug_rtx (scratch);
13598 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13599 gcc_assert (GET_CODE (mem) == MEM);
13600 rclass = REGNO_REG_CLASS (regno);
13601 addr = XEXP (mem, 0);
13605 /* GPRs can handle reg + small constant, all other addresses need to use
13606 the scratch register. */
13609 if (GET_CODE (addr) == AND)
13611 and_op2 = XEXP (addr, 1);
13612 addr = XEXP (addr, 0);
13615 if (GET_CODE (addr) == PRE_MODIFY)
13617 scratch_or_premodify = XEXP (addr, 0);
13618 gcc_assert (REG_P (scratch_or_premodify));
13619 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13620 addr = XEXP (addr, 1);
13623 if (GET_CODE (addr) == PLUS
13624 && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
13625 || and_op2 != NULL_RTX))
13627 addr_op1 = XEXP (addr, 0);
13628 addr_op2 = XEXP (addr, 1);
13629 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13631 if (!REG_P (addr_op2)
13632 && (GET_CODE (addr_op2) != CONST_INT
13633 || !satisfies_constraint_I (addr_op2)))
13635 if (TARGET_DEBUG_ADDR)
13638 "\nMove plus addr to register %s, mode = %s: ",
13639 rs6000_reg_names[REGNO (scratch)],
13640 GET_MODE_NAME (mode));
13641 debug_rtx (addr_op2);
13643 rs6000_emit_move (scratch, addr_op2, Pmode);
13644 addr_op2 = scratch;
13647 emit_insn (gen_rtx_SET (VOIDmode,
13648 scratch_or_premodify,
13649 gen_rtx_PLUS (Pmode,
13653 addr = scratch_or_premodify;
13654 scratch_or_premodify = scratch;
13656 else if (!legitimate_indirect_address_p (addr, false)
13657 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13659 if (TARGET_DEBUG_ADDR)
13661 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13662 rs6000_reg_names[REGNO (scratch_or_premodify)],
13663 GET_MODE_NAME (mode));
13666 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13667 addr = scratch_or_premodify;
13668 scratch_or_premodify = scratch;
13672 /* Float/Altivec registers can only handle reg+reg addressing. Move
13673 other addresses into a scratch register. */
13678 /* With float regs, we need to handle the AND ourselves, since we can't
13679 use the Altivec instruction with an implicit AND -16. Allow scalar
13680 loads to float registers to use reg+offset even if VSX. */
13681 if (GET_CODE (addr) == AND
13682 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13683 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13684 || INTVAL (XEXP (addr, 1)) != -16
13685 || !VECTOR_MEM_ALTIVEC_P (mode)))
13687 and_op2 = XEXP (addr, 1);
13688 addr = XEXP (addr, 0);
13691 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13692 as the address later. */
13693 if (GET_CODE (addr) == PRE_MODIFY
13694 && (!VECTOR_MEM_VSX_P (mode)
13695 || and_op2 != NULL_RTX
13696 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
13698 scratch_or_premodify = XEXP (addr, 0);
13699 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
13701 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13702 addr = XEXP (addr, 1);
13705 if (legitimate_indirect_address_p (addr, false) /* reg */
13706 || legitimate_indexed_address_p (addr, false) /* reg+reg */
13707 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
13708 || (GET_CODE (addr) == AND /* Altivec memory */
13709 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13710 && INTVAL (XEXP (addr, 1)) == -16
13711 && VECTOR_MEM_ALTIVEC_P (mode))
13712 || (rclass == FLOAT_REGS /* legacy float mem */
13713 && GET_MODE_SIZE (mode) == 8
13714 && and_op2 == NULL_RTX
13715 && scratch_or_premodify == scratch
13716 && rs6000_legitimate_offset_address_p (mode, addr, false)))
13719 else if (GET_CODE (addr) == PLUS)
13721 addr_op1 = XEXP (addr, 0);
13722 addr_op2 = XEXP (addr, 1);
13723 gcc_assert (REG_P (addr_op1));
13725 if (TARGET_DEBUG_ADDR)
13727 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
13728 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13729 debug_rtx (addr_op2);
13731 rs6000_emit_move (scratch, addr_op2, Pmode);
13732 emit_insn (gen_rtx_SET (VOIDmode,
13733 scratch_or_premodify,
13734 gen_rtx_PLUS (Pmode,
13737 addr = scratch_or_premodify;
13738 scratch_or_premodify = scratch;
13741 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
13742 || GET_CODE (addr) == CONST_INT || REG_P (addr))
13744 if (TARGET_DEBUG_ADDR)
13746 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13747 rs6000_reg_names[REGNO (scratch_or_premodify)],
13748 GET_MODE_NAME (mode));
13752 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13753 addr = scratch_or_premodify;
13754 scratch_or_premodify = scratch;
13758 gcc_unreachable ();
13763 gcc_unreachable ();
13766 /* If the original address involved a pre-modify that we couldn't use the VSX
13767 memory instruction with update, and we haven't taken care of already,
13768 store the address in the pre-modify register and use that as the
13770 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
13772 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
13773 addr = scratch_or_premodify;
13776 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
13777 memory instruction, recreate the AND now, including the clobber which is
13778 generated by the general ANDSI3/ANDDI3 patterns for the
13779 andi. instruction. */
13780 if (and_op2 != NULL_RTX)
13782 if (! legitimate_indirect_address_p (addr, false))
13784 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
13788 if (TARGET_DEBUG_ADDR)
13790 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
13791 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13792 debug_rtx (and_op2);
13795 and_rtx = gen_rtx_SET (VOIDmode,
13797 gen_rtx_AND (Pmode,
13801 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
13802 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13803 gen_rtvec (2, and_rtx, cc_clobber)));
13807 /* Adjust the address if it changed. */
13808 if (addr != XEXP (mem, 0))
13810 mem = change_address (mem, mode, addr);
13811 if (TARGET_DEBUG_ADDR)
13812 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
13815 /* Now create the move. */
13817 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
13819 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
13824 /* Convert reloads involving 64-bit gprs and misaligned offset
13825 addressing to use indirect addressing. */
13828 rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p)
13830 int regno = true_regnum (reg);
13831 enum reg_class rclass;
13833 rtx scratch_or_premodify = scratch;
13835 if (TARGET_DEBUG_ADDR)
13837 fprintf (stderr, "\nrs6000_secondary_reload_ppc64, type = %s\n",
13838 store_p ? "store" : "load");
13839 fprintf (stderr, "reg:\n");
13841 fprintf (stderr, "mem:\n");
13843 fprintf (stderr, "scratch:\n");
13844 debug_rtx (scratch);
13847 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13848 gcc_assert (GET_CODE (mem) == MEM);
13849 rclass = REGNO_REG_CLASS (regno);
13850 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
13851 addr = XEXP (mem, 0);
13853 if (GET_CODE (addr) == PRE_MODIFY)
13855 scratch_or_premodify = XEXP (addr, 0);
13856 gcc_assert (REG_P (scratch_or_premodify));
13857 addr = XEXP (addr, 1);
13859 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
13861 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13863 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
13865 /* Now create the move. */
13867 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
13869 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
13874 /* Allocate a 64-bit stack slot to be used for copying SDmode
13875 values through if this function has any SDmode references. */
13878 rs6000_alloc_sdmode_stack_slot (void)
13882 gimple_stmt_iterator gsi;
13884 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
13887 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
13889 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
13892 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
13893 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
13899 /* Check for any SDmode parameters of the function. */
13900 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
13902 if (TREE_TYPE (t) == error_mark_node)
13905 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
13906 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
13908 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
13909 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
13917 rs6000_instantiate_decls (void)
13919 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
13920 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
13923 /* Given an rtx X being reloaded into a reg required to be
13924 in class CLASS, return the class of reg to actually use.
13925 In general this is just CLASS; but on some machines
13926 in some cases it is preferable to use a more restrictive class.
13928 On the RS/6000, we have to return NO_REGS when we want to reload a
13929 floating-point CONST_DOUBLE to force it to be copied to memory.
13931 We also don't want to reload integer values into floating-point
13932 registers if we can at all help it. In fact, this can
13933 cause reload to die, if it tries to generate a reload of CTR
13934 into a FP register and discovers it doesn't have the memory location
13937 ??? Would it be a good idea to have reload do the converse, that is
13938 try to reload floating modes into FP registers if possible?
13941 static enum reg_class
13942 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
13944 enum machine_mode mode = GET_MODE (x);
13946 if (VECTOR_UNIT_VSX_P (mode)
13947 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
13950 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
13951 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
13952 && easy_vector_constant (x, mode))
13953 return ALTIVEC_REGS;
13955 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
13958 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
13959 return GENERAL_REGS;
13961 /* For VSX, prefer the traditional registers for 64-bit values because we can
13962 use the non-VSX loads. Prefer the Altivec registers if Altivec is
13963 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
13964 prefer Altivec loads.. */
13965 if (rclass == VSX_REGS)
13967 if (GET_MODE_SIZE (mode) <= 8)
13970 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
13971 return ALTIVEC_REGS;
13979 /* Debug version of rs6000_preferred_reload_class. */
13980 static enum reg_class
13981 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
13983 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
13986 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
13988 reg_class_names[ret], reg_class_names[rclass],
13989 GET_MODE_NAME (GET_MODE (x)));
13995 /* If we are copying between FP or AltiVec registers and anything else, we need
13996 a memory location. The exception is when we are targeting ppc64 and the
13997 move to/from fpr to gpr instructions are available. Also, under VSX, you
13998 can copy vector registers from the FP register set to the Altivec register
13999 set and vice versa. */
14002 rs6000_secondary_memory_needed (enum reg_class class1,
14003 enum reg_class class2,
14004 enum machine_mode mode)
14006 if (class1 == class2)
14009 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14010 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14011 between these classes. But we need memory for other things that can go in
14012 FLOAT_REGS like SFmode. */
14014 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14015 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14016 || class1 == FLOAT_REGS))
14017 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14018 && class2 != FLOAT_REGS);
14020 if (class1 == VSX_REGS || class2 == VSX_REGS)
14023 if (class1 == FLOAT_REGS
14024 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14025 || ((mode != DFmode)
14026 && (mode != DDmode)
14027 && (mode != DImode))))
14030 if (class2 == FLOAT_REGS
14031 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14032 || ((mode != DFmode)
14033 && (mode != DDmode)
14034 && (mode != DImode))))
14037 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14043 /* Debug version of rs6000_secondary_memory_needed. */
14045 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14046 enum reg_class class2,
14047 enum machine_mode mode)
14049 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14052 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14053 "class2 = %s, mode = %s\n",
14054 ret ? "true" : "false", reg_class_names[class1],
14055 reg_class_names[class2], GET_MODE_NAME (mode));
14060 /* Return the register class of a scratch register needed to copy IN into
14061 or out of a register in RCLASS in MODE. If it can be done directly,
14062 NO_REGS is returned. */
14064 static enum reg_class
14065 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14070 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14072 && MACHOPIC_INDIRECT
14076 /* We cannot copy a symbolic operand directly into anything
14077 other than BASE_REGS for TARGET_ELF. So indicate that a
14078 register from BASE_REGS is needed as an intermediate
14081 On Darwin, pic addresses require a load from memory, which
14082 needs a base register. */
14083 if (rclass != BASE_REGS
14084 && (GET_CODE (in) == SYMBOL_REF
14085 || GET_CODE (in) == HIGH
14086 || GET_CODE (in) == LABEL_REF
14087 || GET_CODE (in) == CONST))
14091 if (GET_CODE (in) == REG)
14093 regno = REGNO (in);
14094 if (regno >= FIRST_PSEUDO_REGISTER)
14096 regno = true_regnum (in);
14097 if (regno >= FIRST_PSEUDO_REGISTER)
14101 else if (GET_CODE (in) == SUBREG)
14103 regno = true_regnum (in);
14104 if (regno >= FIRST_PSEUDO_REGISTER)
14110 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14112 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14113 || (regno >= 0 && INT_REGNO_P (regno)))
14116 /* Constants, memory, and FP registers can go into FP registers. */
14117 if ((regno == -1 || FP_REGNO_P (regno))
14118 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14119 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14121 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14124 && (regno == -1 || VSX_REGNO_P (regno))
14125 && VSX_REG_CLASS_P (rclass))
14128 /* Memory, and AltiVec registers can go into AltiVec registers. */
14129 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14130 && rclass == ALTIVEC_REGS)
14133 /* We can copy among the CR registers. */
14134 if ((rclass == CR_REGS || rclass == CR0_REGS)
14135 && regno >= 0 && CR_REGNO_P (regno))
14138 /* Otherwise, we need GENERAL_REGS. */
14139 return GENERAL_REGS;
14142 /* Debug version of rs6000_secondary_reload_class. */
14143 static enum reg_class
14144 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14145 enum machine_mode mode, rtx in)
14147 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14149 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14150 "mode = %s, input rtx:\n",
14151 reg_class_names[ret], reg_class_names[rclass],
14152 GET_MODE_NAME (mode));
14158 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14161 rs6000_cannot_change_mode_class (enum machine_mode from,
14162 enum machine_mode to,
14163 enum reg_class rclass)
14165 unsigned from_size = GET_MODE_SIZE (from);
14166 unsigned to_size = GET_MODE_SIZE (to);
14168 if (from_size != to_size)
14170 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14171 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14172 && reg_classes_intersect_p (xclass, rclass));
14175 if (TARGET_E500_DOUBLE
14176 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14177 || (((to) == TFmode) + ((from) == TFmode)) == 1
14178 || (((to) == DDmode) + ((from) == DDmode)) == 1
14179 || (((to) == TDmode) + ((from) == TDmode)) == 1
14180 || (((to) == DImode) + ((from) == DImode)) == 1))
14183 /* Since the VSX register set includes traditional floating point registers
14184 and altivec registers, just check for the size being different instead of
14185 trying to check whether the modes are vector modes. Otherwise it won't
14186 allow say DF and DI to change classes. */
14187 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14188 return (from_size != 8 && from_size != 16);
14190 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14191 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14194 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14195 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14201 /* Debug version of rs6000_cannot_change_mode_class. */
14203 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14204 enum machine_mode to,
14205 enum reg_class rclass)
14207 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14210 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14211 "to = %s, rclass = %s\n",
14212 ret ? "true" : "false",
14213 GET_MODE_NAME (from), GET_MODE_NAME (to),
14214 reg_class_names[rclass]);
14219 /* Given a comparison operation, return the bit number in CCR to test. We
14220 know this is a valid comparison.
14222 SCC_P is 1 if this is for an scc. That means that %D will have been
14223 used instead of %C, so the bits will be in different places.
14225 Return -1 if OP isn't a valid comparison for some reason. */
14228 ccr_bit (rtx op, int scc_p)
14230 enum rtx_code code = GET_CODE (op);
14231 enum machine_mode cc_mode;
14236 if (!COMPARISON_P (op))
14239 reg = XEXP (op, 0);
14241 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14243 cc_mode = GET_MODE (reg);
14244 cc_regnum = REGNO (reg);
14245 base_bit = 4 * (cc_regnum - CR0_REGNO);
14247 validate_condition_mode (code, cc_mode);
14249 /* When generating a sCOND operation, only positive conditions are
14252 || code == EQ || code == GT || code == LT || code == UNORDERED
14253 || code == GTU || code == LTU);
14258 return scc_p ? base_bit + 3 : base_bit + 2;
14260 return base_bit + 2;
14261 case GT: case GTU: case UNLE:
14262 return base_bit + 1;
14263 case LT: case LTU: case UNGE:
14265 case ORDERED: case UNORDERED:
14266 return base_bit + 3;
14269 /* If scc, we will have done a cror to put the bit in the
14270 unordered position. So test that bit. For integer, this is ! LT
14271 unless this is an scc insn. */
14272 return scc_p ? base_bit + 3 : base_bit;
14275 return scc_p ? base_bit + 3 : base_bit + 1;
14278 gcc_unreachable ();
14282 /* Return the GOT register. */
14285 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14287 /* The second flow pass currently (June 1999) can't update
14288 regs_ever_live without disturbing other parts of the compiler, so
14289 update it here to make the prolog/epilogue code happy. */
14290 if (!can_create_pseudo_p ()
14291 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14292 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14294 crtl->uses_pic_offset_table = 1;
14296 return pic_offset_table_rtx;
14299 static rs6000_stack_t stack_info;
14301 /* Function to init struct machine_function.
14302 This will be called, via a pointer variable,
14303 from push_function_context. */
14305 static struct machine_function *
14306 rs6000_init_machine_status (void)
14308 stack_info.reload_completed = 0;
14309 return ggc_alloc_cleared_machine_function ();
14312 /* These macros test for integers and extract the low-order bits. */
14314 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14315 && GET_MODE (X) == VOIDmode)
14317 #define INT_LOWPART(X) \
14318 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14321 extract_MB (rtx op)
14324 unsigned long val = INT_LOWPART (op);
14326 /* If the high bit is zero, the value is the first 1 bit we find
14328 if ((val & 0x80000000) == 0)
14330 gcc_assert (val & 0xffffffff);
14333 while (((val <<= 1) & 0x80000000) == 0)
14338 /* If the high bit is set and the low bit is not, or the mask is all
14339 1's, the value is zero. */
14340 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14343 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14346 while (((val >>= 1) & 1) != 0)
14353 extract_ME (rtx op)
14356 unsigned long val = INT_LOWPART (op);
14358 /* If the low bit is zero, the value is the first 1 bit we find from
14360 if ((val & 1) == 0)
14362 gcc_assert (val & 0xffffffff);
14365 while (((val >>= 1) & 1) == 0)
14371 /* If the low bit is set and the high bit is not, or the mask is all
14372 1's, the value is 31. */
14373 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14376 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14379 while (((val <<= 1) & 0x80000000) != 0)
14385 /* Locate some local-dynamic symbol still in use by this function
14386 so that we can print its name in some tls_ld pattern. */
14388 static const char *
14389 rs6000_get_some_local_dynamic_name (void)
14393 if (cfun->machine->some_ld_name)
14394 return cfun->machine->some_ld_name;
14396 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14398 && for_each_rtx (&PATTERN (insn),
14399 rs6000_get_some_local_dynamic_name_1, 0))
14400 return cfun->machine->some_ld_name;
14402 gcc_unreachable ();
14405 /* Helper function for rs6000_get_some_local_dynamic_name. */
14408 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14412 if (GET_CODE (x) == SYMBOL_REF)
14414 const char *str = XSTR (x, 0);
14415 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14417 cfun->machine->some_ld_name = str;
14425 /* Write out a function code label. */
14428 rs6000_output_function_entry (FILE *file, const char *fname)
14430 if (fname[0] != '.')
14432 switch (DEFAULT_ABI)
14435 gcc_unreachable ();
14441 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14450 RS6000_OUTPUT_BASENAME (file, fname);
14453 /* Print an operand. Recognize special options, documented below. */
14456 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14457 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14459 #define SMALL_DATA_RELOC "sda21"
14460 #define SMALL_DATA_REG 0
14464 print_operand (FILE *file, rtx x, int code)
14467 unsigned HOST_WIDE_INT uval;
14472 /* Write out an instruction after the call which may be replaced
14473 with glue code by the loader. This depends on the AIX version. */
14474 asm_fprintf (file, RS6000_CALL_GLUE);
14477 /* %a is output_address. */
14480 /* If X is a constant integer whose low-order 5 bits are zero,
14481 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14482 in the AIX assembler where "sri" with a zero shift count
14483 writes a trash instruction. */
14484 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
14491 /* If constant, low-order 16 bits of constant, unsigned.
14492 Otherwise, write normally. */
14494 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14496 print_operand (file, x, 0);
14500 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14501 for 64-bit mask direction. */
14502 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14505 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14509 /* X is a CR register. Print the number of the GT bit of the CR. */
14510 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14511 output_operand_lossage ("invalid %%c value");
14513 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
14517 /* Like 'J' but get to the GT bit only. */
14518 gcc_assert (REG_P (x));
14520 /* Bit 1 is GT bit. */
14521 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14523 /* Add one for shift count in rlinm for scc. */
14524 fprintf (file, "%d", i + 1);
14528 /* X is a CR register. Print the number of the EQ bit of the CR */
14529 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14530 output_operand_lossage ("invalid %%E value");
14532 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14536 /* X is a CR register. Print the shift count needed to move it
14537 to the high-order four bits. */
14538 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14539 output_operand_lossage ("invalid %%f value");
14541 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14545 /* Similar, but print the count for the rotate in the opposite
14547 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14548 output_operand_lossage ("invalid %%F value");
14550 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14554 /* X is a constant integer. If it is negative, print "m",
14555 otherwise print "z". This is to make an aze or ame insn. */
14556 if (GET_CODE (x) != CONST_INT)
14557 output_operand_lossage ("invalid %%G value");
14558 else if (INTVAL (x) >= 0)
14565 /* If constant, output low-order five bits. Otherwise, write
14568 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14570 print_operand (file, x, 0);
14574 /* If constant, output low-order six bits. Otherwise, write
14577 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14579 print_operand (file, x, 0);
14583 /* Print `i' if this is a constant, else nothing. */
14589 /* Write the bit number in CCR for jump. */
14590 i = ccr_bit (x, 0);
14592 output_operand_lossage ("invalid %%j code");
14594 fprintf (file, "%d", i);
14598 /* Similar, but add one for shift count in rlinm for scc and pass
14599 scc flag to `ccr_bit'. */
14600 i = ccr_bit (x, 1);
14602 output_operand_lossage ("invalid %%J code");
14604 /* If we want bit 31, write a shift count of zero, not 32. */
14605 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14609 /* X must be a constant. Write the 1's complement of the
14612 output_operand_lossage ("invalid %%k value");
14614 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14618 /* X must be a symbolic constant on ELF. Write an
14619 expression suitable for an 'addi' that adds in the low 16
14620 bits of the MEM. */
14621 if (GET_CODE (x) == CONST)
14623 if (GET_CODE (XEXP (x, 0)) != PLUS
14624 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14625 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14626 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14627 output_operand_lossage ("invalid %%K value");
14629 print_operand_address (file, x);
14630 fputs ("@l", file);
14633 /* %l is output_asm_label. */
14636 /* Write second word of DImode or DFmode reference. Works on register
14637 or non-indexed memory only. */
14639 fputs (reg_names[REGNO (x) + 1], file);
14640 else if (MEM_P (x))
14642 /* Handle possible auto-increment. Since it is pre-increment and
14643 we have already done it, we can just use an offset of word. */
14644 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14645 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14646 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14648 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14649 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14652 output_address (XEXP (adjust_address_nv (x, SImode,
14656 if (small_data_operand (x, GET_MODE (x)))
14657 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14658 reg_names[SMALL_DATA_REG]);
14663 /* MB value for a mask operand. */
14664 if (! mask_operand (x, SImode))
14665 output_operand_lossage ("invalid %%m value");
14667 fprintf (file, "%d", extract_MB (x));
14671 /* ME value for a mask operand. */
14672 if (! mask_operand (x, SImode))
14673 output_operand_lossage ("invalid %%M value");
14675 fprintf (file, "%d", extract_ME (x));
14678 /* %n outputs the negative of its operand. */
14681 /* Write the number of elements in the vector times 4. */
14682 if (GET_CODE (x) != PARALLEL)
14683 output_operand_lossage ("invalid %%N value");
14685 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14689 /* Similar, but subtract 1 first. */
14690 if (GET_CODE (x) != PARALLEL)
14691 output_operand_lossage ("invalid %%O value");
14693 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14697 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14699 || INT_LOWPART (x) < 0
14700 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14701 output_operand_lossage ("invalid %%p value");
14703 fprintf (file, "%d", i);
14707 /* The operand must be an indirect memory reference. The result
14708 is the register name. */
14709 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14710 || REGNO (XEXP (x, 0)) >= 32)
14711 output_operand_lossage ("invalid %%P value");
14713 fputs (reg_names[REGNO (XEXP (x, 0))], file);
14717 /* This outputs the logical code corresponding to a boolean
14718 expression. The expression may have one or both operands
14719 negated (if one, only the first one). For condition register
14720 logical operations, it will also treat the negated
14721 CR codes as NOTs, but not handle NOTs of them. */
14723 const char *const *t = 0;
14725 enum rtx_code code = GET_CODE (x);
14726 static const char * const tbl[3][3] = {
14727 { "and", "andc", "nor" },
14728 { "or", "orc", "nand" },
14729 { "xor", "eqv", "xor" } };
14733 else if (code == IOR)
14735 else if (code == XOR)
14738 output_operand_lossage ("invalid %%q value");
14740 if (GET_CODE (XEXP (x, 0)) != NOT)
14744 if (GET_CODE (XEXP (x, 1)) == NOT)
14762 /* X is a CR register. Print the mask for `mtcrf'. */
14763 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14764 output_operand_lossage ("invalid %%R value");
14766 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
14770 /* Low 5 bits of 32 - value */
14772 output_operand_lossage ("invalid %%s value");
14774 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
14778 /* PowerPC64 mask position. All 0's is excluded.
14779 CONST_INT 32-bit mask is considered sign-extended so any
14780 transition must occur within the CONST_INT, not on the boundary. */
14781 if (! mask64_operand (x, DImode))
14782 output_operand_lossage ("invalid %%S value");
14784 uval = INT_LOWPART (x);
14786 if (uval & 1) /* Clear Left */
14788 #if HOST_BITS_PER_WIDE_INT > 64
14789 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14793 else /* Clear Right */
14796 #if HOST_BITS_PER_WIDE_INT > 64
14797 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14803 gcc_assert (i >= 0);
14804 fprintf (file, "%d", i);
14808 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
14809 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
14811 /* Bit 3 is OV bit. */
14812 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
14814 /* If we want bit 31, write a shift count of zero, not 32. */
14815 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14819 /* Print the symbolic name of a branch target register. */
14820 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
14821 && REGNO (x) != CTR_REGNO))
14822 output_operand_lossage ("invalid %%T value");
14823 else if (REGNO (x) == LR_REGNO)
14824 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
14826 fputs ("ctr", file);
14830 /* High-order 16 bits of constant for use in unsigned operand. */
14832 output_operand_lossage ("invalid %%u value");
14834 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
14835 (INT_LOWPART (x) >> 16) & 0xffff);
14839 /* High-order 16 bits of constant for use in signed operand. */
14841 output_operand_lossage ("invalid %%v value");
14843 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
14844 (INT_LOWPART (x) >> 16) & 0xffff);
14848 /* Print `u' if this has an auto-increment or auto-decrement. */
14850 && (GET_CODE (XEXP (x, 0)) == PRE_INC
14851 || GET_CODE (XEXP (x, 0)) == PRE_DEC
14852 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
14857 /* Print the trap code for this operand. */
14858 switch (GET_CODE (x))
14861 fputs ("eq", file); /* 4 */
14864 fputs ("ne", file); /* 24 */
14867 fputs ("lt", file); /* 16 */
14870 fputs ("le", file); /* 20 */
14873 fputs ("gt", file); /* 8 */
14876 fputs ("ge", file); /* 12 */
14879 fputs ("llt", file); /* 2 */
14882 fputs ("lle", file); /* 6 */
14885 fputs ("lgt", file); /* 1 */
14888 fputs ("lge", file); /* 5 */
14891 gcc_unreachable ();
14896 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
14899 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
14900 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
14902 print_operand (file, x, 0);
14906 /* MB value for a PowerPC64 rldic operand. */
14907 i = clz_hwi (GET_CODE (x) == CONST_INT
14908 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
14910 #if HOST_BITS_PER_WIDE_INT == 32
14911 if (GET_CODE (x) == CONST_INT && i > 0)
14912 i += 32; /* zero-extend high-part was all 0's */
14913 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
14914 i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32;
14917 fprintf (file, "%d", i);
14921 /* X is a FPR or Altivec register used in a VSX context. */
14922 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
14923 output_operand_lossage ("invalid %%x value");
14926 int reg = REGNO (x);
14927 int vsx_reg = (FP_REGNO_P (reg)
14929 : reg - FIRST_ALTIVEC_REGNO + 32);
14931 #ifdef TARGET_REGNAMES
14932 if (TARGET_REGNAMES)
14933 fprintf (file, "%%vs%d", vsx_reg);
14936 fprintf (file, "%d", vsx_reg);
14942 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
14943 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
14944 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
14949 /* Like 'L', for third word of TImode */
14951 fputs (reg_names[REGNO (x) + 2], file);
14952 else if (MEM_P (x))
14954 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14955 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14956 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
14957 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14958 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
14960 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
14961 if (small_data_operand (x, GET_MODE (x)))
14962 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14963 reg_names[SMALL_DATA_REG]);
14968 /* X is a SYMBOL_REF. Write out the name preceded by a
14969 period and without any trailing data in brackets. Used for function
14970 names. If we are configured for System V (or the embedded ABI) on
14971 the PowerPC, do not emit the period, since those systems do not use
14972 TOCs and the like. */
14973 gcc_assert (GET_CODE (x) == SYMBOL_REF);
14975 /* Mark the decl as referenced so that cgraph will output the
14977 if (SYMBOL_REF_DECL (x))
14978 mark_decl_referenced (SYMBOL_REF_DECL (x));
14980 /* For macho, check to see if we need a stub. */
14983 const char *name = XSTR (x, 0);
14985 if (darwin_emit_branch_islands
14986 && MACHOPIC_INDIRECT
14987 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
14988 name = machopic_indirection_name (x, /*stub_p=*/true);
14990 assemble_name (file, name);
14992 else if (!DOT_SYMBOLS)
14993 assemble_name (file, XSTR (x, 0));
14995 rs6000_output_function_entry (file, XSTR (x, 0));
14999 /* Like 'L', for last word of TImode. */
15001 fputs (reg_names[REGNO (x) + 3], file);
15002 else if (MEM_P (x))
15004 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15005 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15006 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15007 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15008 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15010 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15011 if (small_data_operand (x, GET_MODE (x)))
15012 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15013 reg_names[SMALL_DATA_REG]);
15017 /* Print AltiVec or SPE memory operand. */
15022 gcc_assert (MEM_P (x));
15026 /* Ugly hack because %y is overloaded. */
15027 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15028 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15029 || GET_MODE (x) == TFmode
15030 || GET_MODE (x) == TImode))
15032 /* Handle [reg]. */
15035 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15038 /* Handle [reg+UIMM]. */
15039 else if (GET_CODE (tmp) == PLUS &&
15040 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15044 gcc_assert (REG_P (XEXP (tmp, 0)));
15046 x = INTVAL (XEXP (tmp, 1));
15047 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15051 /* Fall through. Must be [reg+reg]. */
15053 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15054 && GET_CODE (tmp) == AND
15055 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15056 && INTVAL (XEXP (tmp, 1)) == -16)
15057 tmp = XEXP (tmp, 0);
15058 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15059 && GET_CODE (tmp) == PRE_MODIFY)
15060 tmp = XEXP (tmp, 1);
15062 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15065 if (!GET_CODE (tmp) == PLUS
15066 || !REG_P (XEXP (tmp, 0))
15067 || !REG_P (XEXP (tmp, 1)))
15069 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15073 if (REGNO (XEXP (tmp, 0)) == 0)
15074 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15075 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15077 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15078 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15085 fprintf (file, "%s", reg_names[REGNO (x)]);
15086 else if (MEM_P (x))
15088 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15089 know the width from the mode. */
15090 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15091 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15092 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15093 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15094 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15095 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15096 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15097 output_address (XEXP (XEXP (x, 0), 1));
15099 output_address (XEXP (x, 0));
15103 if (toc_relative_expr_p (x, false))
15104 /* This hack along with a corresponding hack in
15105 rs6000_output_addr_const_extra arranges to output addends
15106 where the assembler expects to find them. eg.
15107 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15108 without this hack would be output as "x@toc+4". We
15110 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15112 output_addr_const (file, x);
15117 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15121 output_operand_lossage ("invalid %%xn code");
15125 /* Print the address of an operand. */
15128 print_operand_address (FILE *file, rtx x)
15131 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15132 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15133 || GET_CODE (x) == LABEL_REF)
15135 output_addr_const (file, x);
15136 if (small_data_operand (x, GET_MODE (x)))
15137 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15138 reg_names[SMALL_DATA_REG]);
15140 gcc_assert (!TARGET_TOC);
15142 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15143 && REG_P (XEXP (x, 1)))
15145 if (REGNO (XEXP (x, 0)) == 0)
15146 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15147 reg_names[ REGNO (XEXP (x, 0)) ]);
15149 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15150 reg_names[ REGNO (XEXP (x, 1)) ]);
15152 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15153 && GET_CODE (XEXP (x, 1)) == CONST_INT)
15154 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15155 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15157 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15158 && CONSTANT_P (XEXP (x, 1)))
15160 fprintf (file, "lo16(");
15161 output_addr_const (file, XEXP (x, 1));
15162 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15166 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15167 && CONSTANT_P (XEXP (x, 1)))
15169 output_addr_const (file, XEXP (x, 1));
15170 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15173 else if (toc_relative_expr_p (x, false))
15175 /* This hack along with a corresponding hack in
15176 rs6000_output_addr_const_extra arranges to output addends
15177 where the assembler expects to find them. eg.
15179 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15180 without this hack would be output as "x@toc+8@l(9)". We
15181 want "x+8@toc@l(9)". */
15182 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15183 if (GET_CODE (x) == LO_SUM)
15184 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
15186 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base, 0, 1))]);
15189 gcc_unreachable ();
15192 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15195 rs6000_output_addr_const_extra (FILE *file, rtx x)
15197 if (GET_CODE (x) == UNSPEC)
15198 switch (XINT (x, 1))
15200 case UNSPEC_TOCREL:
15201 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
15202 && REG_P (XVECEXP (x, 0, 1))
15203 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
15204 output_addr_const (file, XVECEXP (x, 0, 0));
15205 if (x == tocrel_base && tocrel_offset != const0_rtx)
15207 if (INTVAL (tocrel_offset) >= 0)
15208 fprintf (file, "+");
15209 output_addr_const (file, CONST_CAST_RTX (tocrel_offset));
15211 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15214 assemble_name (file, toc_label_name);
15216 else if (TARGET_ELF)
15217 fputs ("@toc", file);
15221 case UNSPEC_MACHOPIC_OFFSET:
15222 output_addr_const (file, XVECEXP (x, 0, 0));
15224 machopic_output_function_base_name (file);
15231 /* Target hook for assembling integer objects. The PowerPC version has
15232 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15233 is defined. It also needs to handle DI-mode objects on 64-bit
15237 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15239 #ifdef RELOCATABLE_NEEDS_FIXUP
15240 /* Special handling for SI values. */
15241 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15243 static int recurse = 0;
15245 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15246 the .fixup section. Since the TOC section is already relocated, we
15247 don't need to mark it here. We used to skip the text section, but it
15248 should never be valid for relocated addresses to be placed in the text
15250 if (TARGET_RELOCATABLE
15251 && in_section != toc_section
15253 && GET_CODE (x) != CONST_INT
15254 && GET_CODE (x) != CONST_DOUBLE
15260 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15262 ASM_OUTPUT_LABEL (asm_out_file, buf);
15263 fprintf (asm_out_file, "\t.long\t(");
15264 output_addr_const (asm_out_file, x);
15265 fprintf (asm_out_file, ")@fixup\n");
15266 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15267 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15268 fprintf (asm_out_file, "\t.long\t");
15269 assemble_name (asm_out_file, buf);
15270 fprintf (asm_out_file, "\n\t.previous\n");
15274 /* Remove initial .'s to turn a -mcall-aixdesc function
15275 address into the address of the descriptor, not the function
15277 else if (GET_CODE (x) == SYMBOL_REF
15278 && XSTR (x, 0)[0] == '.'
15279 && DEFAULT_ABI == ABI_AIX)
15281 const char *name = XSTR (x, 0);
15282 while (*name == '.')
15285 fprintf (asm_out_file, "\t.long\t%s\n", name);
15289 #endif /* RELOCATABLE_NEEDS_FIXUP */
15290 return default_assemble_integer (x, size, aligned_p);
15293 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15294 /* Emit an assembler directive to set symbol visibility for DECL to
15295 VISIBILITY_TYPE. */
15298 rs6000_assemble_visibility (tree decl, int vis)
15300 /* Functions need to have their entry point symbol visibility set as
15301 well as their descriptor symbol visibility. */
15302 if (DEFAULT_ABI == ABI_AIX
15304 && TREE_CODE (decl) == FUNCTION_DECL)
15306 static const char * const visibility_types[] = {
15307 NULL, "internal", "hidden", "protected"
15310 const char *name, *type;
15312 name = ((* targetm.strip_name_encoding)
15313 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15314 type = visibility_types[vis];
15316 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15317 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15320 default_assemble_visibility (decl, vis);
15325 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15327 /* Reversal of FP compares takes care -- an ordered compare
15328 becomes an unordered compare and vice versa. */
15329 if (mode == CCFPmode
15330 && (!flag_finite_math_only
15331 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15332 || code == UNEQ || code == LTGT))
15333 return reverse_condition_maybe_unordered (code);
15335 return reverse_condition (code);
15338 /* Generate a compare for CODE. Return a brand-new rtx that
15339 represents the result of the compare. */
15342 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15344 enum machine_mode comp_mode;
15345 rtx compare_result;
15346 enum rtx_code code = GET_CODE (cmp);
15347 rtx op0 = XEXP (cmp, 0);
15348 rtx op1 = XEXP (cmp, 1);
15350 if (FLOAT_MODE_P (mode))
15351 comp_mode = CCFPmode;
15352 else if (code == GTU || code == LTU
15353 || code == GEU || code == LEU)
15354 comp_mode = CCUNSmode;
15355 else if ((code == EQ || code == NE)
15356 && unsigned_reg_p (op0)
15357 && (unsigned_reg_p (op1)
15358 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
15359 /* These are unsigned values, perhaps there will be a later
15360 ordering compare that can be shared with this one. */
15361 comp_mode = CCUNSmode;
15363 comp_mode = CCmode;
15365 /* First, the compare. */
15366 compare_result = gen_reg_rtx (comp_mode);
15368 /* E500 FP compare instructions on the GPRs. Yuck! */
15369 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15370 && FLOAT_MODE_P (mode))
15372 rtx cmp, or_result, compare_result2;
15373 enum machine_mode op_mode = GET_MODE (op0);
15375 if (op_mode == VOIDmode)
15376 op_mode = GET_MODE (op1);
15378 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15379 This explains the following mess. */
15383 case EQ: case UNEQ: case NE: case LTGT:
15387 cmp = (flag_finite_math_only && !flag_trapping_math)
15388 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15389 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15393 cmp = (flag_finite_math_only && !flag_trapping_math)
15394 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15395 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15399 cmp = (flag_finite_math_only && !flag_trapping_math)
15400 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15401 : gen_cmptfeq_gpr (compare_result, op0, op1);
15405 gcc_unreachable ();
15409 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15413 cmp = (flag_finite_math_only && !flag_trapping_math)
15414 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15415 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15419 cmp = (flag_finite_math_only && !flag_trapping_math)
15420 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15421 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15425 cmp = (flag_finite_math_only && !flag_trapping_math)
15426 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15427 : gen_cmptfgt_gpr (compare_result, op0, op1);
15431 gcc_unreachable ();
15435 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15439 cmp = (flag_finite_math_only && !flag_trapping_math)
15440 ? gen_tstsflt_gpr (compare_result, op0, op1)
15441 : gen_cmpsflt_gpr (compare_result, op0, op1);
15445 cmp = (flag_finite_math_only && !flag_trapping_math)
15446 ? gen_tstdflt_gpr (compare_result, op0, op1)
15447 : gen_cmpdflt_gpr (compare_result, op0, op1);
15451 cmp = (flag_finite_math_only && !flag_trapping_math)
15452 ? gen_tsttflt_gpr (compare_result, op0, op1)
15453 : gen_cmptflt_gpr (compare_result, op0, op1);
15457 gcc_unreachable ();
15461 gcc_unreachable ();
15464 /* Synthesize LE and GE from LT/GT || EQ. */
15465 if (code == LE || code == GE || code == LEU || code == GEU)
15471 case LE: code = LT; break;
15472 case GE: code = GT; break;
15473 case LEU: code = LT; break;
15474 case GEU: code = GT; break;
15475 default: gcc_unreachable ();
15478 compare_result2 = gen_reg_rtx (CCFPmode);
15484 cmp = (flag_finite_math_only && !flag_trapping_math)
15485 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15486 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15490 cmp = (flag_finite_math_only && !flag_trapping_math)
15491 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15492 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15496 cmp = (flag_finite_math_only && !flag_trapping_math)
15497 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15498 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15502 gcc_unreachable ();
15506 /* OR them together. */
15507 or_result = gen_reg_rtx (CCFPmode);
15508 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15510 compare_result = or_result;
15515 if (code == NE || code == LTGT)
15525 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15526 CLOBBERs to match cmptf_internal2 pattern. */
15527 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15528 && GET_MODE (op0) == TFmode
15529 && !TARGET_IEEEQUAD
15530 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15531 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15533 gen_rtx_SET (VOIDmode,
15535 gen_rtx_COMPARE (comp_mode, op0, op1)),
15536 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15537 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15538 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15539 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15540 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15541 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15542 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15543 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15544 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15545 else if (GET_CODE (op1) == UNSPEC
15546 && XINT (op1, 1) == UNSPEC_SP_TEST)
15548 rtx op1b = XVECEXP (op1, 0, 0);
15549 comp_mode = CCEQmode;
15550 compare_result = gen_reg_rtx (CCEQmode);
15552 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15554 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15557 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15558 gen_rtx_COMPARE (comp_mode, op0, op1)));
15561 /* Some kinds of FP comparisons need an OR operation;
15562 under flag_finite_math_only we don't bother. */
15563 if (FLOAT_MODE_P (mode)
15564 && !flag_finite_math_only
15565 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15566 && (code == LE || code == GE
15567 || code == UNEQ || code == LTGT
15568 || code == UNGT || code == UNLT))
15570 enum rtx_code or1, or2;
15571 rtx or1_rtx, or2_rtx, compare2_rtx;
15572 rtx or_result = gen_reg_rtx (CCEQmode);
15576 case LE: or1 = LT; or2 = EQ; break;
15577 case GE: or1 = GT; or2 = EQ; break;
15578 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15579 case LTGT: or1 = LT; or2 = GT; break;
15580 case UNGT: or1 = UNORDERED; or2 = GT; break;
15581 case UNLT: or1 = UNORDERED; or2 = LT; break;
15582 default: gcc_unreachable ();
15584 validate_condition_mode (or1, comp_mode);
15585 validate_condition_mode (or2, comp_mode);
15586 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15587 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15588 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15589 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15591 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15593 compare_result = or_result;
15597 validate_condition_mode (code, GET_MODE (compare_result));
15599 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15603 /* Emit the RTL for an sISEL pattern. */
15606 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15608 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15612 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15615 enum machine_mode op_mode;
15616 enum rtx_code cond_code;
15617 rtx result = operands[0];
15619 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15621 rs6000_emit_sISEL (mode, operands);
15625 condition_rtx = rs6000_generate_compare (operands[1], mode);
15626 cond_code = GET_CODE (condition_rtx);
15628 if (FLOAT_MODE_P (mode)
15629 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15633 PUT_MODE (condition_rtx, SImode);
15634 t = XEXP (condition_rtx, 0);
15636 gcc_assert (cond_code == NE || cond_code == EQ);
15638 if (cond_code == NE)
15639 emit_insn (gen_e500_flip_gt_bit (t, t));
15641 emit_insn (gen_move_from_CR_gt_bit (result, t));
15645 if (cond_code == NE
15646 || cond_code == GE || cond_code == LE
15647 || cond_code == GEU || cond_code == LEU
15648 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15650 rtx not_result = gen_reg_rtx (CCEQmode);
15651 rtx not_op, rev_cond_rtx;
15652 enum machine_mode cc_mode;
15654 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15656 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15657 SImode, XEXP (condition_rtx, 0), const0_rtx);
15658 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15659 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15660 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15663 op_mode = GET_MODE (XEXP (operands[1], 0));
15664 if (op_mode == VOIDmode)
15665 op_mode = GET_MODE (XEXP (operands[1], 1));
15667 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15669 PUT_MODE (condition_rtx, DImode);
15670 convert_move (result, condition_rtx, 0);
15674 PUT_MODE (condition_rtx, SImode);
15675 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15679 /* Emit a branch of kind CODE to location LOC. */
15682 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15684 rtx condition_rtx, loc_ref;
15686 condition_rtx = rs6000_generate_compare (operands[0], mode);
15687 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15688 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15689 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15690 loc_ref, pc_rtx)));
15693 /* Return the string to output a conditional branch to LABEL, which is
15694 the operand number of the label, or -1 if the branch is really a
15695 conditional return.
15697 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15698 condition code register and its mode specifies what kind of
15699 comparison we made.
15701 REVERSED is nonzero if we should reverse the sense of the comparison.
15703 INSN is the insn. */
15706 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
15708 static char string[64];
15709 enum rtx_code code = GET_CODE (op);
15710 rtx cc_reg = XEXP (op, 0);
15711 enum machine_mode mode = GET_MODE (cc_reg);
15712 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
15713 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
15714 int really_reversed = reversed ^ need_longbranch;
15720 validate_condition_mode (code, mode);
15722 /* Work out which way this really branches. We could use
15723 reverse_condition_maybe_unordered here always but this
15724 makes the resulting assembler clearer. */
15725 if (really_reversed)
15727 /* Reversal of FP compares takes care -- an ordered compare
15728 becomes an unordered compare and vice versa. */
15729 if (mode == CCFPmode)
15730 code = reverse_condition_maybe_unordered (code);
15732 code = reverse_condition (code);
15735 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
15737 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15742 /* Opposite of GT. */
15751 gcc_unreachable ();
15757 /* Not all of these are actually distinct opcodes, but
15758 we distinguish them for clarity of the resulting assembler. */
15759 case NE: case LTGT:
15760 ccode = "ne"; break;
15761 case EQ: case UNEQ:
15762 ccode = "eq"; break;
15764 ccode = "ge"; break;
15765 case GT: case GTU: case UNGT:
15766 ccode = "gt"; break;
15768 ccode = "le"; break;
15769 case LT: case LTU: case UNLT:
15770 ccode = "lt"; break;
15771 case UNORDERED: ccode = "un"; break;
15772 case ORDERED: ccode = "nu"; break;
15773 case UNGE: ccode = "nl"; break;
15774 case UNLE: ccode = "ng"; break;
15776 gcc_unreachable ();
15779 /* Maybe we have a guess as to how likely the branch is.
15780 The old mnemonics don't have a way to specify this information. */
15782 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
15783 if (note != NULL_RTX)
15785 /* PROB is the difference from 50%. */
15786 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
15788 /* Only hint for highly probable/improbable branches on newer
15789 cpus as static prediction overrides processor dynamic
15790 prediction. For older cpus we may as well always hint, but
15791 assume not taken for branches that are very close to 50% as a
15792 mispredicted taken branch is more expensive than a
15793 mispredicted not-taken branch. */
15794 if (rs6000_always_hint
15795 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
15796 && br_prob_note_reliable_p (note)))
15798 if (abs (prob) > REG_BR_PROB_BASE / 20
15799 && ((prob > 0) ^ need_longbranch))
15807 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
15809 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
15811 /* We need to escape any '%' characters in the reg_names string.
15812 Assume they'd only be the first character.... */
15813 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
15815 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
15819 /* If the branch distance was too far, we may have to use an
15820 unconditional branch to go the distance. */
15821 if (need_longbranch)
15822 s += sprintf (s, ",$+8\n\tb %s", label);
15824 s += sprintf (s, ",%s", label);
15830 /* Return the string to flip the GT bit on a CR. */
15832 output_e500_flip_gt_bit (rtx dst, rtx src)
15834 static char string[64];
15837 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
15838 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
15841 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
15842 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
15844 sprintf (string, "crnot %d,%d", a, b);
15848 /* Return insn for VSX or Altivec comparisons. */
15851 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
15854 enum machine_mode mode = GET_MODE (op0);
15862 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
15872 mask = gen_reg_rtx (mode);
15873 emit_insn (gen_rtx_SET (VOIDmode,
15875 gen_rtx_fmt_ee (code, mode, op0, op1)));
15882 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
15883 DMODE is expected destination mode. This is a recursive function. */
15886 rs6000_emit_vector_compare (enum rtx_code rcode,
15888 enum machine_mode dmode)
15891 bool swap_operands = false;
15892 bool try_again = false;
15894 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
15895 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
15897 /* See if the comparison works as is. */
15898 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
15906 swap_operands = true;
15911 swap_operands = true;
15919 /* Invert condition and try again.
15920 e.g., A != B becomes ~(A==B). */
15922 enum rtx_code rev_code;
15923 enum insn_code nor_code;
15926 rev_code = reverse_condition_maybe_unordered (rcode);
15927 if (rev_code == UNKNOWN)
15930 nor_code = optab_handler (one_cmpl_optab, dmode);
15931 if (nor_code == CODE_FOR_nothing)
15934 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
15938 mask = gen_reg_rtx (dmode);
15939 emit_insn (GEN_FCN (nor_code) (mask, mask2));
15947 /* Try GT/GTU/LT/LTU OR EQ */
15950 enum insn_code ior_code;
15951 enum rtx_code new_code;
15972 gcc_unreachable ();
15975 ior_code = optab_handler (ior_optab, dmode);
15976 if (ior_code == CODE_FOR_nothing)
15979 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
15983 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
15987 mask = gen_reg_rtx (dmode);
15988 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16006 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16011 /* You only get two chances. */
16015 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16016 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16017 operands for the relation operation COND. */
16020 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16021 rtx cond, rtx cc_op0, rtx cc_op1)
16023 enum machine_mode dest_mode = GET_MODE (dest);
16024 enum machine_mode mask_mode = GET_MODE (cc_op0);
16025 enum rtx_code rcode = GET_CODE (cond);
16026 enum machine_mode cc_mode = CCmode;
16030 bool invert_move = false;
16032 if (VECTOR_UNIT_NONE_P (dest_mode))
16035 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16036 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16040 /* Swap operands if we can, and fall back to doing the operation as
16041 specified, and doing a NOR to invert the test. */
16047 /* Invert condition and try again.
16048 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16049 invert_move = true;
16050 rcode = reverse_condition_maybe_unordered (rcode);
16051 if (rcode == UNKNOWN)
16055 /* Mark unsigned tests with CCUNSmode. */
16060 cc_mode = CCUNSmode;
16067 /* Get the vector mask for the given relational operations. */
16068 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16076 op_true = op_false;
16080 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16081 CONST0_RTX (dest_mode));
16082 emit_insn (gen_rtx_SET (VOIDmode,
16084 gen_rtx_IF_THEN_ELSE (dest_mode,
16091 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16092 operands of the last comparison is nonzero/true, FALSE_COND if it
16093 is zero/false. Return 0 if the hardware has no such operation. */
16096 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16098 enum rtx_code code = GET_CODE (op);
16099 rtx op0 = XEXP (op, 0);
16100 rtx op1 = XEXP (op, 1);
16101 REAL_VALUE_TYPE c1;
16102 enum machine_mode compare_mode = GET_MODE (op0);
16103 enum machine_mode result_mode = GET_MODE (dest);
16105 bool is_against_zero;
16107 /* These modes should always match. */
16108 if (GET_MODE (op1) != compare_mode
16109 /* In the isel case however, we can use a compare immediate, so
16110 op1 may be a small constant. */
16111 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16113 if (GET_MODE (true_cond) != result_mode)
16115 if (GET_MODE (false_cond) != result_mode)
16118 /* First, work out if the hardware can do this at all, or
16119 if it's too slow.... */
16120 if (!FLOAT_MODE_P (compare_mode))
16123 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16126 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16127 && SCALAR_FLOAT_MODE_P (compare_mode))
16130 is_against_zero = op1 == CONST0_RTX (compare_mode);
16132 /* A floating-point subtract might overflow, underflow, or produce
16133 an inexact result, thus changing the floating-point flags, so it
16134 can't be generated if we care about that. It's safe if one side
16135 of the construct is zero, since then no subtract will be
16137 if (SCALAR_FLOAT_MODE_P (compare_mode)
16138 && flag_trapping_math && ! is_against_zero)
16141 /* Eliminate half of the comparisons by switching operands, this
16142 makes the remaining code simpler. */
16143 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16144 || code == LTGT || code == LT || code == UNLE)
16146 code = reverse_condition_maybe_unordered (code);
16148 true_cond = false_cond;
16152 /* UNEQ and LTGT take four instructions for a comparison with zero,
16153 it'll probably be faster to use a branch here too. */
16154 if (code == UNEQ && HONOR_NANS (compare_mode))
16157 if (GET_CODE (op1) == CONST_DOUBLE)
16158 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16160 /* We're going to try to implement comparisons by performing
16161 a subtract, then comparing against zero. Unfortunately,
16162 Inf - Inf is NaN which is not zero, and so if we don't
16163 know that the operand is finite and the comparison
16164 would treat EQ different to UNORDERED, we can't do it. */
16165 if (HONOR_INFINITIES (compare_mode)
16166 && code != GT && code != UNGE
16167 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16168 /* Constructs of the form (a OP b ? a : b) are safe. */
16169 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16170 || (! rtx_equal_p (op0, true_cond)
16171 && ! rtx_equal_p (op1, true_cond))))
16174 /* At this point we know we can use fsel. */
16176 /* Reduce the comparison to a comparison against zero. */
16177 if (! is_against_zero)
16179 temp = gen_reg_rtx (compare_mode);
16180 emit_insn (gen_rtx_SET (VOIDmode, temp,
16181 gen_rtx_MINUS (compare_mode, op0, op1)));
16183 op1 = CONST0_RTX (compare_mode);
16186 /* If we don't care about NaNs we can reduce some of the comparisons
16187 down to faster ones. */
16188 if (! HONOR_NANS (compare_mode))
16194 true_cond = false_cond;
16207 /* Now, reduce everything down to a GE. */
16214 temp = gen_reg_rtx (compare_mode);
16215 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16220 temp = gen_reg_rtx (compare_mode);
16221 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16226 temp = gen_reg_rtx (compare_mode);
16227 emit_insn (gen_rtx_SET (VOIDmode, temp,
16228 gen_rtx_NEG (compare_mode,
16229 gen_rtx_ABS (compare_mode, op0))));
16234 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16235 temp = gen_reg_rtx (result_mode);
16236 emit_insn (gen_rtx_SET (VOIDmode, temp,
16237 gen_rtx_IF_THEN_ELSE (result_mode,
16238 gen_rtx_GE (VOIDmode,
16240 true_cond, false_cond)));
16241 false_cond = true_cond;
16244 temp = gen_reg_rtx (compare_mode);
16245 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16250 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16251 temp = gen_reg_rtx (result_mode);
16252 emit_insn (gen_rtx_SET (VOIDmode, temp,
16253 gen_rtx_IF_THEN_ELSE (result_mode,
16254 gen_rtx_GE (VOIDmode,
16256 true_cond, false_cond)));
16257 true_cond = false_cond;
16260 temp = gen_reg_rtx (compare_mode);
16261 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16266 gcc_unreachable ();
16269 emit_insn (gen_rtx_SET (VOIDmode, dest,
16270 gen_rtx_IF_THEN_ELSE (result_mode,
16271 gen_rtx_GE (VOIDmode,
16273 true_cond, false_cond)));
16277 /* Same as above, but for ints (isel). */
16280 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16282 rtx condition_rtx, cr;
16283 enum machine_mode mode = GET_MODE (dest);
16284 enum rtx_code cond_code;
16285 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16288 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16291 /* We still have to do the compare, because isel doesn't do a
16292 compare, it just looks at the CRx bits set by a previous compare
16294 condition_rtx = rs6000_generate_compare (op, mode);
16295 cond_code = GET_CODE (condition_rtx);
16296 cr = XEXP (condition_rtx, 0);
16297 signedp = GET_MODE (cr) == CCmode;
16299 isel_func = (mode == SImode
16300 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16301 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16305 case LT: case GT: case LTU: case GTU: case EQ:
16306 /* isel handles these directly. */
16310 /* We need to swap the sense of the comparison. */
16313 true_cond = false_cond;
16315 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16320 false_cond = force_reg (mode, false_cond);
16321 if (true_cond != const0_rtx)
16322 true_cond = force_reg (mode, true_cond);
16324 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16330 output_isel (rtx *operands)
16332 enum rtx_code code;
16334 code = GET_CODE (operands[1]);
16336 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16338 gcc_assert (GET_CODE (operands[2]) == REG
16339 && GET_CODE (operands[3]) == REG);
16340 PUT_CODE (operands[1], reverse_condition (code));
16341 return "isel %0,%3,%2,%j1";
16344 return "isel %0,%2,%3,%j1";
16348 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16350 enum machine_mode mode = GET_MODE (op0);
16354 /* VSX/altivec have direct min/max insns. */
16355 if ((code == SMAX || code == SMIN)
16356 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16357 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16359 emit_insn (gen_rtx_SET (VOIDmode,
16361 gen_rtx_fmt_ee (code, mode, op0, op1)));
16365 if (code == SMAX || code == SMIN)
16370 if (code == SMAX || code == UMAX)
16371 target = emit_conditional_move (dest, c, op0, op1, mode,
16372 op0, op1, mode, 0);
16374 target = emit_conditional_move (dest, c, op0, op1, mode,
16375 op1, op0, mode, 0);
16376 gcc_assert (target);
16377 if (target != dest)
16378 emit_move_insn (dest, target);
16381 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16382 COND is true. Mark the jump as unlikely to be taken. */
16385 emit_unlikely_jump (rtx cond, rtx label)
16387 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16390 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16391 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16392 add_reg_note (x, REG_BR_PROB, very_unlikely);
16395 /* A subroutine of the atomic operation splitters. Emit a load-locked
16396 instruction in MODE. */
16399 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16401 rtx (*fn) (rtx, rtx) = NULL;
16406 fn = gen_load_lockedsi;
16409 fn = gen_load_lockeddi;
16412 gcc_unreachable ();
16414 emit_insn (fn (reg, mem));
16417 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16418 instruction in MODE. */
16421 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16423 rtx (*fn) (rtx, rtx, rtx) = NULL;
16428 fn = gen_store_conditionalsi;
16431 fn = gen_store_conditionaldi;
16434 gcc_unreachable ();
16437 /* Emit sync before stwcx. to address PPC405 Erratum. */
16438 if (PPC405_ERRATUM77)
16439 emit_insn (gen_hwsync ());
16441 emit_insn (fn (res, mem, val));
16444 /* Expand barriers before and after a load_locked/store_cond sequence. */
16447 rs6000_pre_atomic_barrier (enum memmodel model)
16451 case MEMMODEL_RELAXED:
16452 case MEMMODEL_CONSUME:
16453 case MEMMODEL_ACQUIRE:
16455 case MEMMODEL_RELEASE:
16456 case MEMMODEL_ACQ_REL:
16457 emit_insn (gen_lwsync ());
16459 case MEMMODEL_SEQ_CST:
16460 emit_insn (gen_hwsync ());
16463 gcc_unreachable ();
16468 rs6000_post_atomic_barrier (enum memmodel model)
16472 case MEMMODEL_RELAXED:
16473 case MEMMODEL_CONSUME:
16474 case MEMMODEL_RELEASE:
16476 case MEMMODEL_ACQUIRE:
16477 case MEMMODEL_ACQ_REL:
16478 case MEMMODEL_SEQ_CST:
16479 emit_insn (gen_isync ());
16482 gcc_unreachable ();
16486 /* A subroutine of the various atomic expanders. For sub-word operations,
16487 we must adjust things to operate on SImode. Given the original MEM,
16488 return a new aligned memory. Also build and return the quantities by
16489 which to shift and mask. */
16492 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16494 rtx addr, align, shift, mask, mem;
16495 HOST_WIDE_INT shift_mask;
16496 enum machine_mode mode = GET_MODE (orig_mem);
16498 /* For smaller modes, we have to implement this via SImode. */
16499 shift_mask = (mode == QImode ? 0x18 : 0x10);
16501 addr = XEXP (orig_mem, 0);
16502 addr = force_reg (GET_MODE (addr), addr);
16504 /* Aligned memory containing subword. Generate a new memory. We
16505 do not want any of the existing MEM_ATTR data, as we're now
16506 accessing memory outside the original object. */
16507 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16508 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16509 mem = gen_rtx_MEM (SImode, align);
16510 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16511 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16512 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16514 /* Shift amount for subword relative to aligned word. */
16515 shift = gen_reg_rtx (SImode);
16516 addr = gen_lowpart (SImode, addr);
16517 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16518 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16519 shift, 1, OPTAB_LIB_WIDEN);
16522 /* Mask for insertion. */
16523 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16524 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16530 /* A subroutine of the various atomic expanders. For sub-word operands,
16531 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16534 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16538 x = gen_reg_rtx (SImode);
16539 emit_insn (gen_rtx_SET (VOIDmode, x,
16540 gen_rtx_AND (SImode,
16541 gen_rtx_NOT (SImode, mask),
16544 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16549 /* A subroutine of the various atomic expanders. For sub-word operands,
16550 extract WIDE to NARROW via SHIFT. */
16553 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16555 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16556 wide, 1, OPTAB_LIB_WIDEN);
16557 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16560 /* Expand an atomic compare and swap operation. */
16563 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16565 rtx boolval, retval, mem, oldval, newval, cond;
16566 rtx label1, label2, x, mask, shift;
16567 enum machine_mode mode;
16568 enum memmodel mod_s, mod_f;
16571 boolval = operands[0];
16572 retval = operands[1];
16574 oldval = operands[3];
16575 newval = operands[4];
16576 is_weak = (INTVAL (operands[5]) != 0);
16577 mod_s = (enum memmodel) INTVAL (operands[6]);
16578 mod_f = (enum memmodel) INTVAL (operands[7]);
16579 mode = GET_MODE (mem);
16581 mask = shift = NULL_RTX;
16582 if (mode == QImode || mode == HImode)
16584 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16586 /* Shift and mask OLDVAL into position with the word. */
16587 oldval = convert_modes (SImode, mode, oldval, 1);
16588 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16589 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16591 /* Shift and mask NEWVAL into position within the word. */
16592 newval = convert_modes (SImode, mode, newval, 1);
16593 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16594 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16596 /* Prepare to adjust the return value. */
16597 retval = gen_reg_rtx (SImode);
16600 else if (reg_overlap_mentioned_p (retval, oldval))
16601 oldval = copy_to_reg (oldval);
16603 rs6000_pre_atomic_barrier (mod_s);
16608 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16609 emit_label (XEXP (label1, 0));
16611 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16613 emit_load_locked (mode, retval, mem);
16618 x = expand_simple_binop (SImode, AND, retval, mask,
16619 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16622 cond = gen_reg_rtx (CCmode);
16623 x = gen_rtx_COMPARE (CCmode, x, oldval);
16624 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16626 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16627 emit_unlikely_jump (x, label2);
16631 x = rs6000_mask_atomic_subword (retval, newval, mask);
16633 emit_store_conditional (mode, cond, mem, x);
16637 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16638 emit_unlikely_jump (x, label1);
16641 if (mod_f != MEMMODEL_RELAXED)
16642 emit_label (XEXP (label2, 0));
16644 rs6000_post_atomic_barrier (mod_s);
16646 if (mod_f == MEMMODEL_RELAXED)
16647 emit_label (XEXP (label2, 0));
16650 rs6000_finish_atomic_subword (operands[1], retval, shift);
16652 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16653 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16654 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16657 /* Expand an atomic exchange operation. */
16660 rs6000_expand_atomic_exchange (rtx operands[])
16662 rtx retval, mem, val, cond;
16663 enum machine_mode mode;
16664 enum memmodel model;
16665 rtx label, x, mask, shift;
16667 retval = operands[0];
16670 model = (enum memmodel) INTVAL (operands[3]);
16671 mode = GET_MODE (mem);
16673 mask = shift = NULL_RTX;
16674 if (mode == QImode || mode == HImode)
16676 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16678 /* Shift and mask VAL into position with the word. */
16679 val = convert_modes (SImode, mode, val, 1);
16680 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16681 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16683 /* Prepare to adjust the return value. */
16684 retval = gen_reg_rtx (SImode);
16688 rs6000_pre_atomic_barrier (model);
16690 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16691 emit_label (XEXP (label, 0));
16693 emit_load_locked (mode, retval, mem);
16697 x = rs6000_mask_atomic_subword (retval, val, mask);
16699 cond = gen_reg_rtx (CCmode);
16700 emit_store_conditional (mode, cond, mem, x);
16702 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16703 emit_unlikely_jump (x, label);
16705 rs6000_post_atomic_barrier (model);
16708 rs6000_finish_atomic_subword (operands[0], retval, shift);
16711 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16712 to perform. MEM is the memory on which to operate. VAL is the second
16713 operand of the binary operator. BEFORE and AFTER are optional locations to
16714 return the value of MEM either before of after the operation. MODEL_RTX
16715 is a CONST_INT containing the memory model to use. */
16718 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
16719 rtx orig_before, rtx orig_after, rtx model_rtx)
16721 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
16722 enum machine_mode mode = GET_MODE (mem);
16723 rtx label, x, cond, mask, shift;
16724 rtx before = orig_before, after = orig_after;
16726 mask = shift = NULL_RTX;
16727 if (mode == QImode || mode == HImode)
16729 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16731 /* Shift and mask VAL into position with the word. */
16732 val = convert_modes (SImode, mode, val, 1);
16733 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16734 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16740 /* We've already zero-extended VAL. That is sufficient to
16741 make certain that it does not affect other bits. */
16746 /* If we make certain that all of the other bits in VAL are
16747 set, that will be sufficient to not affect other bits. */
16748 x = gen_rtx_NOT (SImode, mask);
16749 x = gen_rtx_IOR (SImode, x, val);
16750 emit_insn (gen_rtx_SET (VOIDmode, val, x));
16757 /* These will all affect bits outside the field and need
16758 adjustment via MASK within the loop. */
16762 gcc_unreachable ();
16765 /* Prepare to adjust the return value. */
16766 before = gen_reg_rtx (SImode);
16768 after = gen_reg_rtx (SImode);
16772 rs6000_pre_atomic_barrier (model);
16774 label = gen_label_rtx ();
16775 emit_label (label);
16776 label = gen_rtx_LABEL_REF (VOIDmode, label);
16778 if (before == NULL_RTX)
16779 before = gen_reg_rtx (mode);
16781 emit_load_locked (mode, before, mem);
16785 x = expand_simple_binop (mode, AND, before, val,
16786 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16787 after = expand_simple_unop (mode, NOT, x, after, 1);
16791 after = expand_simple_binop (mode, code, before, val,
16792 after, 1, OPTAB_LIB_WIDEN);
16798 x = expand_simple_binop (SImode, AND, after, mask,
16799 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16800 x = rs6000_mask_atomic_subword (before, x, mask);
16803 cond = gen_reg_rtx (CCmode);
16804 emit_store_conditional (mode, cond, mem, x);
16806 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16807 emit_unlikely_jump (x, label);
16809 rs6000_post_atomic_barrier (model);
16814 rs6000_finish_atomic_subword (orig_before, before, shift);
16816 rs6000_finish_atomic_subword (orig_after, after, shift);
16818 else if (orig_after && after != orig_after)
16819 emit_move_insn (orig_after, after);
16822 /* Emit instructions to move SRC to DST. Called by splitters for
16823 multi-register moves. It will emit at most one instruction for
16824 each register that is accessed; that is, it won't emit li/lis pairs
16825 (or equivalent for 64-bit code). One of SRC or DST must be a hard
16829 rs6000_split_multireg_move (rtx dst, rtx src)
16831 /* The register number of the first register being moved. */
16833 /* The mode that is to be moved. */
16834 enum machine_mode mode;
16835 /* The mode that the move is being done in, and its size. */
16836 enum machine_mode reg_mode;
16838 /* The number of registers that will be moved. */
16841 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
16842 mode = GET_MODE (dst);
16843 nregs = hard_regno_nregs[reg][mode];
16844 if (FP_REGNO_P (reg))
16845 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
16846 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
16847 else if (ALTIVEC_REGNO_P (reg))
16848 reg_mode = V16QImode;
16849 else if (TARGET_E500_DOUBLE && mode == TFmode)
16852 reg_mode = word_mode;
16853 reg_mode_size = GET_MODE_SIZE (reg_mode);
16855 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
16857 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
16859 /* Move register range backwards, if we might have destructive
16862 for (i = nregs - 1; i >= 0; i--)
16863 emit_insn (gen_rtx_SET (VOIDmode,
16864 simplify_gen_subreg (reg_mode, dst, mode,
16865 i * reg_mode_size),
16866 simplify_gen_subreg (reg_mode, src, mode,
16867 i * reg_mode_size)));
16873 bool used_update = false;
16874 rtx restore_basereg = NULL_RTX;
16876 if (MEM_P (src) && INT_REGNO_P (reg))
16880 if (GET_CODE (XEXP (src, 0)) == PRE_INC
16881 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
16884 breg = XEXP (XEXP (src, 0), 0);
16885 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
16886 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
16887 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
16888 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
16889 src = replace_equiv_address (src, breg);
16891 else if (! rs6000_offsettable_memref_p (src))
16893 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
16895 rtx basereg = XEXP (XEXP (src, 0), 0);
16898 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
16899 emit_insn (gen_rtx_SET (VOIDmode, ndst,
16900 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
16901 used_update = true;
16904 emit_insn (gen_rtx_SET (VOIDmode, basereg,
16905 XEXP (XEXP (src, 0), 1)));
16906 src = replace_equiv_address (src, basereg);
16910 rtx basereg = gen_rtx_REG (Pmode, reg);
16911 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
16912 src = replace_equiv_address (src, basereg);
16916 breg = XEXP (src, 0);
16917 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
16918 breg = XEXP (breg, 0);
16920 /* If the base register we are using to address memory is
16921 also a destination reg, then change that register last. */
16923 && REGNO (breg) >= REGNO (dst)
16924 && REGNO (breg) < REGNO (dst) + nregs)
16925 j = REGNO (breg) - REGNO (dst);
16927 else if (MEM_P (dst) && INT_REGNO_P (reg))
16931 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
16932 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
16935 breg = XEXP (XEXP (dst, 0), 0);
16936 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
16937 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
16938 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
16940 /* We have to update the breg before doing the store.
16941 Use store with update, if available. */
16945 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
16946 emit_insn (TARGET_32BIT
16947 ? (TARGET_POWERPC64
16948 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
16949 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
16950 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
16951 used_update = true;
16954 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
16955 dst = replace_equiv_address (dst, breg);
16957 else if (!rs6000_offsettable_memref_p (dst)
16958 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
16960 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
16962 rtx basereg = XEXP (XEXP (dst, 0), 0);
16965 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
16966 emit_insn (gen_rtx_SET (VOIDmode,
16967 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
16968 used_update = true;
16971 emit_insn (gen_rtx_SET (VOIDmode, basereg,
16972 XEXP (XEXP (dst, 0), 1)));
16973 dst = replace_equiv_address (dst, basereg);
16977 rtx basereg = XEXP (XEXP (dst, 0), 0);
16978 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
16979 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
16981 && REG_P (offsetreg)
16982 && REGNO (basereg) != REGNO (offsetreg));
16983 if (REGNO (basereg) == 0)
16985 rtx tmp = offsetreg;
16986 offsetreg = basereg;
16989 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
16990 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
16991 dst = replace_equiv_address (dst, basereg);
16994 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
16995 gcc_assert (rs6000_offsettable_memref_p (dst));
16998 for (i = 0; i < nregs; i++)
17000 /* Calculate index to next subword. */
17005 /* If compiler already emitted move of first word by
17006 store with update, no need to do anything. */
17007 if (j == 0 && used_update)
17010 emit_insn (gen_rtx_SET (VOIDmode,
17011 simplify_gen_subreg (reg_mode, dst, mode,
17012 j * reg_mode_size),
17013 simplify_gen_subreg (reg_mode, src, mode,
17014 j * reg_mode_size)));
17016 if (restore_basereg != NULL_RTX)
17017 emit_insn (restore_basereg);
17022 /* This page contains routines that are used to determine what the
17023 function prologue and epilogue code will do and write them out. */
17028 return !call_used_regs[r] && df_regs_ever_live_p (r);
17031 /* Return the first fixed-point register that is required to be
17032 saved. 32 if none. */
17035 first_reg_to_save (void)
17039 /* Find lowest numbered live register. */
17040 for (first_reg = 13; first_reg <= 31; first_reg++)
17041 if (save_reg_p (first_reg))
17044 if (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM
17045 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17046 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17047 || (TARGET_TOC && TARGET_MINIMAL_TOC))
17048 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
17049 first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM;
17053 && crtl->uses_pic_offset_table
17054 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17055 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17061 /* Similar, for FP regs. */
17064 first_fp_reg_to_save (void)
17068 /* Find lowest numbered live register. */
17069 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17070 if (save_reg_p (first_reg))
17076 /* Similar, for AltiVec regs. */
17079 first_altivec_reg_to_save (void)
17083 /* Stack frame remains as is unless we are in AltiVec ABI. */
17084 if (! TARGET_ALTIVEC_ABI)
17085 return LAST_ALTIVEC_REGNO + 1;
17087 /* On Darwin, the unwind routines are compiled without
17088 TARGET_ALTIVEC, and use save_world to save/restore the
17089 altivec registers when necessary. */
17090 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17091 && ! TARGET_ALTIVEC)
17092 return FIRST_ALTIVEC_REGNO + 20;
17094 /* Find lowest numbered live register. */
17095 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17096 if (save_reg_p (i))
17102 /* Return a 32-bit mask of the AltiVec registers we need to set in
17103 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17104 the 32-bit word is 0. */
17106 static unsigned int
17107 compute_vrsave_mask (void)
17109 unsigned int i, mask = 0;
17111 /* On Darwin, the unwind routines are compiled without
17112 TARGET_ALTIVEC, and use save_world to save/restore the
17113 call-saved altivec registers when necessary. */
17114 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17115 && ! TARGET_ALTIVEC)
17118 /* First, find out if we use _any_ altivec registers. */
17119 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17120 if (df_regs_ever_live_p (i))
17121 mask |= ALTIVEC_REG_BIT (i);
17126 /* Next, remove the argument registers from the set. These must
17127 be in the VRSAVE mask set by the caller, so we don't need to add
17128 them in again. More importantly, the mask we compute here is
17129 used to generate CLOBBERs in the set_vrsave insn, and we do not
17130 wish the argument registers to die. */
17131 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17132 mask &= ~ALTIVEC_REG_BIT (i);
17134 /* Similarly, remove the return value from the set. */
17137 diddle_return_value (is_altivec_return_reg, &yes);
17139 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17145 /* For a very restricted set of circumstances, we can cut down the
17146 size of prologues/epilogues by calling our own save/restore-the-world
17150 compute_save_world_info (rs6000_stack_t *info_ptr)
17152 info_ptr->world_save_p = 1;
17153 info_ptr->world_save_p
17154 = (WORLD_SAVE_P (info_ptr)
17155 && DEFAULT_ABI == ABI_DARWIN
17156 && !cfun->has_nonlocal_label
17157 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17158 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17159 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17160 && info_ptr->cr_save_p);
17162 /* This will not work in conjunction with sibcalls. Make sure there
17163 are none. (This check is expensive, but seldom executed.) */
17164 if (WORLD_SAVE_P (info_ptr))
17167 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17168 if ( GET_CODE (insn) == CALL_INSN
17169 && SIBLING_CALL_P (insn))
17171 info_ptr->world_save_p = 0;
17176 if (WORLD_SAVE_P (info_ptr))
17178 /* Even if we're not touching VRsave, make sure there's room on the
17179 stack for it, if it looks like we're calling SAVE_WORLD, which
17180 will attempt to save it. */
17181 info_ptr->vrsave_size = 4;
17183 /* If we are going to save the world, we need to save the link register too. */
17184 info_ptr->lr_save_p = 1;
17186 /* "Save" the VRsave register too if we're saving the world. */
17187 if (info_ptr->vrsave_mask == 0)
17188 info_ptr->vrsave_mask = compute_vrsave_mask ();
17190 /* Because the Darwin register save/restore routines only handle
17191 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17193 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17194 && (info_ptr->first_altivec_reg_save
17195 >= FIRST_SAVED_ALTIVEC_REGNO));
17202 is_altivec_return_reg (rtx reg, void *xyes)
17204 bool *yes = (bool *) xyes;
17205 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17210 /* Look for user-defined global regs in the range FIRST to LAST-1.
17211 We should not restore these, and so cannot use lmw or out-of-line
17212 restore functions if there are any. We also can't save them
17213 (well, emit frame notes for them), because frame unwinding during
17214 exception handling will restore saved registers. */
17217 global_regs_p (unsigned first, unsigned last)
17219 while (first < last)
17220 if (global_regs[first++])
17225 /* Determine the strategy for savings/restoring registers. */
17228 SAVRES_MULTIPLE = 0x1,
17229 SAVE_INLINE_FPRS = 0x2,
17230 SAVE_INLINE_GPRS = 0x4,
17231 REST_INLINE_FPRS = 0x8,
17232 REST_INLINE_GPRS = 0x10,
17233 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17234 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17235 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80,
17236 SAVE_INLINE_VRS = 0x100,
17237 REST_INLINE_VRS = 0x200
17240 #ifndef V_SAVE_INLINE
17241 #define V_SAVE_INLINE(FIRST_REG) 1
17245 rs6000_savres_strategy (rs6000_stack_t *info,
17246 bool using_static_chain_p)
17251 if (TARGET_MULTIPLE
17252 && !TARGET_POWERPC64
17253 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17254 && info->first_gp_reg_save < 31
17255 && !global_regs_p (info->first_gp_reg_save, 32))
17256 strategy |= SAVRES_MULTIPLE;
17258 if (crtl->calls_eh_return
17259 || cfun->machine->ra_need_lr)
17260 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17261 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
17262 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17264 if (info->first_fp_reg_save == 64
17265 || FP_SAVE_INLINE (info->first_fp_reg_save)
17266 /* The out-of-line FP routines use double-precision stores;
17267 we can't use those routines if we don't have such stores. */
17268 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17269 || global_regs_p (info->first_fp_reg_save, 64))
17270 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17272 if (info->first_gp_reg_save == 32
17273 || GP_SAVE_INLINE (info->first_gp_reg_save)
17274 || (!(strategy & SAVRES_MULTIPLE)
17275 && global_regs_p (info->first_gp_reg_save, 32)))
17276 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17278 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
17279 || V_SAVE_INLINE (info->first_altivec_reg_save)
17280 || global_regs_p (info->first_altivec_reg_save, LAST_ALTIVEC_REGNO + 1))
17281 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17283 /* Don't bother to try to save things out-of-line if r11 is occupied
17284 by the static chain. It would require too much fiddling and the
17285 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17286 pointer on Darwin, and AIX uses r1 or r12. */
17287 if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)
17288 strategy |= ((DEFAULT_ABI == ABI_DARWIN
17289 ? 0 : SAVE_INLINE_FPRS | REST_INLINE_FPRS)
17291 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17293 /* If we are going to use store multiple, then don't even bother
17294 with the out-of-line routines, since the store-multiple
17295 instruction will always be smaller. */
17296 if ((strategy & SAVRES_MULTIPLE))
17297 strategy |= SAVE_INLINE_GPRS;
17299 /* info->lr_save_p isn't yet set if the only reason lr needs to be
17300 saved is an out-of-line save or restore. Set up the value for
17301 the next test (excluding out-of-line gpr restore). */
17302 lr_save_p = (info->lr_save_p
17303 || !(strategy & SAVE_INLINE_GPRS)
17304 || !(strategy & SAVE_INLINE_FPRS)
17305 || !(strategy & SAVE_INLINE_VRS)
17306 || !(strategy & REST_INLINE_FPRS)
17307 || !(strategy & REST_INLINE_VRS));
17309 /* The situation is more complicated with load multiple. We'd
17310 prefer to use the out-of-line routines for restores, since the
17311 "exit" out-of-line routines can handle the restore of LR and the
17312 frame teardown. However if doesn't make sense to use the
17313 out-of-line routine if that is the only reason we'd need to save
17314 LR, and we can't use the "exit" out-of-line gpr restore if we
17315 have saved some fprs; In those cases it is advantageous to use
17316 load multiple when available. */
17317 if ((strategy & SAVRES_MULTIPLE)
17319 || info->first_fp_reg_save != 64))
17320 strategy |= REST_INLINE_GPRS;
17322 /* We can only use load multiple or the out-of-line routines to
17323 restore if we've used store multiple or out-of-line routines
17324 in the prologue, i.e. if we've saved all the registers from
17325 first_gp_reg_save. Otherwise, we risk loading garbage. */
17326 if ((strategy & (SAVE_INLINE_GPRS | SAVRES_MULTIPLE)) == SAVE_INLINE_GPRS)
17327 strategy |= REST_INLINE_GPRS;
17329 /* Saving CR interferes with the exit routines used on the SPE, so
17332 && info->spe_64bit_regs_used
17333 && info->cr_save_p)
17334 strategy |= REST_INLINE_GPRS;
17336 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
17339 if (!(strategy & SAVE_INLINE_FPRS))
17340 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17341 else if (!(strategy & SAVE_INLINE_GPRS)
17342 && info->first_fp_reg_save == 64)
17343 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17346 if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17347 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17349 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17350 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17355 /* Calculate the stack information for the current function. This is
17356 complicated by having two separate calling sequences, the AIX calling
17357 sequence and the V.4 calling sequence.
17359 AIX (and Darwin/Mac OS X) stack frames look like:
17361 SP----> +---------------------------------------+
17362 | back chain to caller | 0 0
17363 +---------------------------------------+
17364 | saved CR | 4 8 (8-11)
17365 +---------------------------------------+
17367 +---------------------------------------+
17368 | reserved for compilers | 12 24
17369 +---------------------------------------+
17370 | reserved for binders | 16 32
17371 +---------------------------------------+
17372 | saved TOC pointer | 20 40
17373 +---------------------------------------+
17374 | Parameter save area (P) | 24 48
17375 +---------------------------------------+
17376 | Alloca space (A) | 24+P etc.
17377 +---------------------------------------+
17378 | Local variable space (L) | 24+P+A
17379 +---------------------------------------+
17380 | Float/int conversion temporary (X) | 24+P+A+L
17381 +---------------------------------------+
17382 | Save area for AltiVec registers (W) | 24+P+A+L+X
17383 +---------------------------------------+
17384 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17385 +---------------------------------------+
17386 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17387 +---------------------------------------+
17388 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17389 +---------------------------------------+
17390 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17391 +---------------------------------------+
17392 old SP->| back chain to caller's caller |
17393 +---------------------------------------+
17395 The required alignment for AIX configurations is two words (i.e., 8
17399 V.4 stack frames look like:
17401 SP----> +---------------------------------------+
17402 | back chain to caller | 0
17403 +---------------------------------------+
17404 | caller's saved LR | 4
17405 +---------------------------------------+
17406 | Parameter save area (P) | 8
17407 +---------------------------------------+
17408 | Alloca space (A) | 8+P
17409 +---------------------------------------+
17410 | Varargs save area (V) | 8+P+A
17411 +---------------------------------------+
17412 | Local variable space (L) | 8+P+A+V
17413 +---------------------------------------+
17414 | Float/int conversion temporary (X) | 8+P+A+V+L
17415 +---------------------------------------+
17416 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17417 +---------------------------------------+
17418 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17419 +---------------------------------------+
17420 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17421 +---------------------------------------+
17422 | SPE: area for 64-bit GP registers |
17423 +---------------------------------------+
17424 | SPE alignment padding |
17425 +---------------------------------------+
17426 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17427 +---------------------------------------+
17428 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17429 +---------------------------------------+
17430 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17431 +---------------------------------------+
17432 old SP->| back chain to caller's caller |
17433 +---------------------------------------+
17435 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17436 given. (But note below and in sysv4.h that we require only 8 and
17437 may round up the size of our stack frame anyways. The historical
17438 reason is early versions of powerpc-linux which didn't properly
17439 align the stack at program startup. A happy side-effect is that
17440 -mno-eabi libraries can be used with -meabi programs.)
17442 The EABI configuration defaults to the V.4 layout. However,
17443 the stack alignment requirements may differ. If -mno-eabi is not
17444 given, the required stack alignment is 8 bytes; if -mno-eabi is
17445 given, the required alignment is 16 bytes. (But see V.4 comment
17448 #ifndef ABI_STACK_BOUNDARY
17449 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17452 static rs6000_stack_t *
17453 rs6000_stack_info (void)
17455 rs6000_stack_t *info_ptr = &stack_info;
17456 int reg_size = TARGET_32BIT ? 4 : 8;
17460 HOST_WIDE_INT non_fixed_size;
17461 bool using_static_chain_p;
17463 if (reload_completed && info_ptr->reload_completed)
17466 memset (info_ptr, 0, sizeof (*info_ptr));
17467 info_ptr->reload_completed = reload_completed;
17471 /* Cache value so we don't rescan instruction chain over and over. */
17472 if (cfun->machine->insn_chain_scanned_p == 0)
17473 cfun->machine->insn_chain_scanned_p
17474 = spe_func_has_64bit_regs_p () + 1;
17475 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17478 /* Select which calling sequence. */
17479 info_ptr->abi = DEFAULT_ABI;
17481 /* Calculate which registers need to be saved & save area size. */
17482 info_ptr->first_gp_reg_save = first_reg_to_save ();
17483 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17484 even if it currently looks like we won't. Reload may need it to
17485 get at a constant; if so, it will have already created a constant
17486 pool entry for it. */
17487 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17488 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17489 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17490 && crtl->uses_const_pool
17491 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17492 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17494 first_gp = info_ptr->first_gp_reg_save;
17496 info_ptr->gp_size = reg_size * (32 - first_gp);
17498 /* For the SPE, we have an additional upper 32-bits on each GPR.
17499 Ideally we should save the entire 64-bits only when the upper
17500 half is used in SIMD instructions. Since we only record
17501 registers live (not the size they are used in), this proves
17502 difficult because we'd have to traverse the instruction chain at
17503 the right time, taking reload into account. This is a real pain,
17504 so we opt to save the GPRs in 64-bits always if but one register
17505 gets used in 64-bits. Otherwise, all the registers in the frame
17506 get saved in 32-bits.
17508 So... since when we save all GPRs (except the SP) in 64-bits, the
17509 traditional GP save area will be empty. */
17510 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17511 info_ptr->gp_size = 0;
17513 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17514 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17516 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17517 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17518 - info_ptr->first_altivec_reg_save);
17520 /* Does this function call anything? */
17521 info_ptr->calls_p = (! current_function_is_leaf
17522 || cfun->machine->ra_needs_full_frame);
17524 /* Determine if we need to save the condition code registers. */
17525 if (df_regs_ever_live_p (CR2_REGNO)
17526 || df_regs_ever_live_p (CR3_REGNO)
17527 || df_regs_ever_live_p (CR4_REGNO))
17529 info_ptr->cr_save_p = 1;
17530 if (DEFAULT_ABI == ABI_V4)
17531 info_ptr->cr_size = reg_size;
17534 /* If the current function calls __builtin_eh_return, then we need
17535 to allocate stack space for registers that will hold data for
17536 the exception handler. */
17537 if (crtl->calls_eh_return)
17540 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17543 /* SPE saves EH registers in 64-bits. */
17544 ehrd_size = i * (TARGET_SPE_ABI
17545 && info_ptr->spe_64bit_regs_used != 0
17546 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17551 /* Determine various sizes. */
17552 info_ptr->reg_size = reg_size;
17553 info_ptr->fixed_size = RS6000_SAVE_AREA;
17554 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17555 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17556 TARGET_ALTIVEC ? 16 : 8);
17557 if (FRAME_GROWS_DOWNWARD)
17558 info_ptr->vars_size
17559 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17560 + info_ptr->parm_size,
17561 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17562 - (info_ptr->fixed_size + info_ptr->vars_size
17563 + info_ptr->parm_size);
17565 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17566 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17568 info_ptr->spe_gp_size = 0;
17570 if (TARGET_ALTIVEC_ABI)
17571 info_ptr->vrsave_mask = compute_vrsave_mask ();
17573 info_ptr->vrsave_mask = 0;
17575 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17576 info_ptr->vrsave_size = 4;
17578 info_ptr->vrsave_size = 0;
17580 compute_save_world_info (info_ptr);
17582 /* Calculate the offsets. */
17583 switch (DEFAULT_ABI)
17587 gcc_unreachable ();
17591 info_ptr->fp_save_offset = - info_ptr->fp_size;
17592 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17594 if (TARGET_ALTIVEC_ABI)
17596 info_ptr->vrsave_save_offset
17597 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17599 /* Align stack so vector save area is on a quadword boundary.
17600 The padding goes above the vectors. */
17601 if (info_ptr->altivec_size != 0)
17602 info_ptr->altivec_padding_size
17603 = info_ptr->vrsave_save_offset & 0xF;
17605 info_ptr->altivec_padding_size = 0;
17607 info_ptr->altivec_save_offset
17608 = info_ptr->vrsave_save_offset
17609 - info_ptr->altivec_padding_size
17610 - info_ptr->altivec_size;
17611 gcc_assert (info_ptr->altivec_size == 0
17612 || info_ptr->altivec_save_offset % 16 == 0);
17614 /* Adjust for AltiVec case. */
17615 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17618 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17619 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17620 info_ptr->lr_save_offset = 2*reg_size;
17624 info_ptr->fp_save_offset = - info_ptr->fp_size;
17625 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17626 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
17628 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17630 /* Align stack so SPE GPR save area is aligned on a
17631 double-word boundary. */
17632 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
17633 info_ptr->spe_padding_size
17634 = 8 - (-info_ptr->cr_save_offset % 8);
17636 info_ptr->spe_padding_size = 0;
17638 info_ptr->spe_gp_save_offset
17639 = info_ptr->cr_save_offset
17640 - info_ptr->spe_padding_size
17641 - info_ptr->spe_gp_size;
17643 /* Adjust for SPE case. */
17644 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
17646 else if (TARGET_ALTIVEC_ABI)
17648 info_ptr->vrsave_save_offset
17649 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
17651 /* Align stack so vector save area is on a quadword boundary. */
17652 if (info_ptr->altivec_size != 0)
17653 info_ptr->altivec_padding_size
17654 = 16 - (-info_ptr->vrsave_save_offset % 16);
17656 info_ptr->altivec_padding_size = 0;
17658 info_ptr->altivec_save_offset
17659 = info_ptr->vrsave_save_offset
17660 - info_ptr->altivec_padding_size
17661 - info_ptr->altivec_size;
17663 /* Adjust for AltiVec case. */
17664 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
17667 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
17668 info_ptr->ehrd_offset -= ehrd_size;
17669 info_ptr->lr_save_offset = reg_size;
17673 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
17674 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
17675 + info_ptr->gp_size
17676 + info_ptr->altivec_size
17677 + info_ptr->altivec_padding_size
17678 + info_ptr->spe_gp_size
17679 + info_ptr->spe_padding_size
17681 + info_ptr->cr_size
17682 + info_ptr->vrsave_size,
17685 non_fixed_size = (info_ptr->vars_size
17686 + info_ptr->parm_size
17687 + info_ptr->save_size);
17689 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
17690 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
17692 /* Determine if we need to save the link register. */
17693 if (info_ptr->calls_p
17694 || (DEFAULT_ABI == ABI_AIX
17696 && !TARGET_PROFILE_KERNEL)
17697 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
17698 #ifdef TARGET_RELOCATABLE
17699 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
17701 || rs6000_ra_ever_killed ())
17702 info_ptr->lr_save_p = 1;
17704 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
17705 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
17706 && call_used_regs[STATIC_CHAIN_REGNUM]);
17707 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
17708 using_static_chain_p);
17710 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
17711 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
17712 || !(info_ptr->savres_strategy & SAVE_INLINE_VRS)
17713 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
17714 || !(info_ptr->savres_strategy & REST_INLINE_FPRS)
17715 || !(info_ptr->savres_strategy & REST_INLINE_VRS))
17716 info_ptr->lr_save_p = 1;
17718 if (info_ptr->lr_save_p)
17719 df_set_regs_ever_live (LR_REGNO, true);
17721 /* Determine if we need to allocate any stack frame:
17723 For AIX we need to push the stack if a frame pointer is needed
17724 (because the stack might be dynamically adjusted), if we are
17725 debugging, if we make calls, or if the sum of fp_save, gp_save,
17726 and local variables are more than the space needed to save all
17727 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17728 + 18*8 = 288 (GPR13 reserved).
17730 For V.4 we don't have the stack cushion that AIX uses, but assume
17731 that the debugger can handle stackless frames. */
17733 if (info_ptr->calls_p)
17734 info_ptr->push_p = 1;
17736 else if (DEFAULT_ABI == ABI_V4)
17737 info_ptr->push_p = non_fixed_size != 0;
17739 else if (frame_pointer_needed)
17740 info_ptr->push_p = 1;
17742 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
17743 info_ptr->push_p = 1;
17746 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
17748 /* Zero offsets if we're not saving those registers. */
17749 if (info_ptr->fp_size == 0)
17750 info_ptr->fp_save_offset = 0;
17752 if (info_ptr->gp_size == 0)
17753 info_ptr->gp_save_offset = 0;
17755 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
17756 info_ptr->altivec_save_offset = 0;
17758 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
17759 info_ptr->vrsave_save_offset = 0;
17761 if (! TARGET_SPE_ABI
17762 || info_ptr->spe_64bit_regs_used == 0
17763 || info_ptr->spe_gp_size == 0)
17764 info_ptr->spe_gp_save_offset = 0;
17766 if (! info_ptr->lr_save_p)
17767 info_ptr->lr_save_offset = 0;
17769 if (! info_ptr->cr_save_p)
17770 info_ptr->cr_save_offset = 0;
17775 /* Return true if the current function uses any GPRs in 64-bit SIMD
17779 spe_func_has_64bit_regs_p (void)
17783 /* Functions that save and restore all the call-saved registers will
17784 need to save/restore the registers in 64-bits. */
17785 if (crtl->calls_eh_return
17786 || cfun->calls_setjmp
17787 || crtl->has_nonlocal_goto)
17790 insns = get_insns ();
17792 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
17798 /* FIXME: This should be implemented with attributes...
17800 (set_attr "spe64" "true")....then,
17801 if (get_spe64(insn)) return true;
17803 It's the only reliable way to do the stuff below. */
17805 i = PATTERN (insn);
17806 if (GET_CODE (i) == SET)
17808 enum machine_mode mode = GET_MODE (SET_SRC (i));
17810 if (SPE_VECTOR_MODE (mode))
17812 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
17822 debug_stack_info (rs6000_stack_t *info)
17824 const char *abi_string;
17827 info = rs6000_stack_info ();
17829 fprintf (stderr, "\nStack information for function %s:\n",
17830 ((current_function_decl && DECL_NAME (current_function_decl))
17831 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
17836 default: abi_string = "Unknown"; break;
17837 case ABI_NONE: abi_string = "NONE"; break;
17838 case ABI_AIX: abi_string = "AIX"; break;
17839 case ABI_DARWIN: abi_string = "Darwin"; break;
17840 case ABI_V4: abi_string = "V.4"; break;
17843 fprintf (stderr, "\tABI = %5s\n", abi_string);
17845 if (TARGET_ALTIVEC_ABI)
17846 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
17848 if (TARGET_SPE_ABI)
17849 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
17851 if (info->first_gp_reg_save != 32)
17852 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
17854 if (info->first_fp_reg_save != 64)
17855 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
17857 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
17858 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
17859 info->first_altivec_reg_save);
17861 if (info->lr_save_p)
17862 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
17864 if (info->cr_save_p)
17865 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
17867 if (info->vrsave_mask)
17868 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
17871 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
17874 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
17876 if (info->gp_save_offset)
17877 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
17879 if (info->fp_save_offset)
17880 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
17882 if (info->altivec_save_offset)
17883 fprintf (stderr, "\taltivec_save_offset = %5d\n",
17884 info->altivec_save_offset);
17886 if (info->spe_gp_save_offset)
17887 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
17888 info->spe_gp_save_offset);
17890 if (info->vrsave_save_offset)
17891 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
17892 info->vrsave_save_offset);
17894 if (info->lr_save_offset)
17895 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
17897 if (info->cr_save_offset)
17898 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
17900 if (info->varargs_save_offset)
17901 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
17903 if (info->total_size)
17904 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
17907 if (info->vars_size)
17908 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
17911 if (info->parm_size)
17912 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
17914 if (info->fixed_size)
17915 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
17918 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
17920 if (info->spe_gp_size)
17921 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
17924 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
17926 if (info->altivec_size)
17927 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
17929 if (info->vrsave_size)
17930 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
17932 if (info->altivec_padding_size)
17933 fprintf (stderr, "\taltivec_padding_size= %5d\n",
17934 info->altivec_padding_size);
17936 if (info->spe_padding_size)
17937 fprintf (stderr, "\tspe_padding_size = %5d\n",
17938 info->spe_padding_size);
17941 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
17943 if (info->save_size)
17944 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
17946 if (info->reg_size != 4)
17947 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
17949 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
17951 fprintf (stderr, "\n");
17955 rs6000_return_addr (int count, rtx frame)
17957 /* Currently we don't optimize very well between prolog and body
17958 code and for PIC code the code can be actually quite bad, so
17959 don't try to be too clever here. */
17960 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
17962 cfun->machine->ra_needs_full_frame = 1;
17969 plus_constant (Pmode,
17971 (gen_rtx_MEM (Pmode,
17972 memory_address (Pmode, frame))),
17973 RETURN_ADDRESS_OFFSET)));
17976 cfun->machine->ra_need_lr = 1;
17977 return get_hard_reg_initial_val (Pmode, LR_REGNO);
17980 /* Say whether a function is a candidate for sibcall handling or not. */
17983 rs6000_function_ok_for_sibcall (tree decl, tree exp)
17988 fntype = TREE_TYPE (decl);
17990 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
17992 /* We can't do it if the called function has more vector parameters
17993 than the current function; there's nowhere to put the VRsave code. */
17994 if (TARGET_ALTIVEC_ABI
17995 && TARGET_ALTIVEC_VRSAVE
17996 && !(decl && decl == current_function_decl))
17998 function_args_iterator args_iter;
18002 /* Functions with vector parameters are required to have a
18003 prototype, so the argument type info must be available
18005 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18006 if (TREE_CODE (type) == VECTOR_TYPE
18007 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18010 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18011 if (TREE_CODE (type) == VECTOR_TYPE
18012 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18019 /* Under the AIX ABI we can't allow calls to non-local functions,
18020 because the callee may have a different TOC pointer to the
18021 caller and there's no way to ensure we restore the TOC when we
18022 return. With the secure-plt SYSV ABI we can't make non-local
18023 calls when -fpic/PIC because the plt call stubs use r30. */
18024 if (DEFAULT_ABI == ABI_DARWIN
18025 || (DEFAULT_ABI == ABI_AIX
18027 && !DECL_EXTERNAL (decl)
18028 && (*targetm.binds_local_p) (decl))
18029 || (DEFAULT_ABI == ABI_V4
18030 && (!TARGET_SECURE_PLT
18033 && (*targetm.binds_local_p) (decl)))))
18035 tree attr_list = TYPE_ATTRIBUTES (fntype);
18037 if (!lookup_attribute ("longcall", attr_list)
18038 || lookup_attribute ("shortcall", attr_list))
18045 /* NULL if INSN insn is valid within a low-overhead loop.
18046 Otherwise return why doloop cannot be applied.
18047 PowerPC uses the COUNT register for branch on table instructions. */
18049 static const char *
18050 rs6000_invalid_within_doloop (const_rtx insn)
18053 return "Function call in the loop.";
18056 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18057 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18058 return "Computed branch in the loop.";
18064 rs6000_ra_ever_killed (void)
18070 if (cfun->is_thunk)
18073 if (cfun->machine->lr_save_state)
18074 return cfun->machine->lr_save_state - 1;
18076 /* regs_ever_live has LR marked as used if any sibcalls are present,
18077 but this should not force saving and restoring in the
18078 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18079 clobbers LR, so that is inappropriate. */
18081 /* Also, the prologue can generate a store into LR that
18082 doesn't really count, like this:
18085 bcl to set PIC register
18089 When we're called from the epilogue, we need to avoid counting
18090 this as a store. */
18092 push_topmost_sequence ();
18093 top = get_insns ();
18094 pop_topmost_sequence ();
18095 reg = gen_rtx_REG (Pmode, LR_REGNO);
18097 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18103 if (!SIBLING_CALL_P (insn))
18106 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18108 else if (set_of (reg, insn) != NULL_RTX
18109 && !prologue_epilogue_contains (insn))
18116 /* Emit instructions needed to load the TOC register.
18117 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18118 a constant pool; or for SVR4 -fpic. */
18121 rs6000_emit_load_toc_table (int fromprolog)
18124 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18126 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18129 rtx lab, tmp1, tmp2, got;
18131 lab = gen_label_rtx ();
18132 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18133 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18135 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18137 got = rs6000_got_sym ();
18138 tmp1 = tmp2 = dest;
18141 tmp1 = gen_reg_rtx (Pmode);
18142 tmp2 = gen_reg_rtx (Pmode);
18144 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18145 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18146 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18147 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18149 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18151 emit_insn (gen_load_toc_v4_pic_si ());
18152 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18154 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18157 rtx temp0 = (fromprolog
18158 ? gen_rtx_REG (Pmode, 0)
18159 : gen_reg_rtx (Pmode));
18165 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18166 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18168 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18169 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18171 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18172 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18173 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18179 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18180 lab = gen_label_rtx ();
18181 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18182 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18183 if (TARGET_LINK_STACK)
18184 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18185 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18187 emit_insn (gen_addsi3 (dest, temp0, dest));
18189 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18191 /* This is for AIX code running in non-PIC ELF32. */
18194 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18195 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18197 emit_insn (gen_elf_high (dest, realsym));
18198 emit_insn (gen_elf_low (dest, dest, realsym));
18202 gcc_assert (DEFAULT_ABI == ABI_AIX);
18205 emit_insn (gen_load_toc_aix_si (dest));
18207 emit_insn (gen_load_toc_aix_di (dest));
18211 /* Emit instructions to restore the link register after determining where
18212 its value has been stored. */
18215 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18217 rs6000_stack_t *info = rs6000_stack_info ();
18220 operands[0] = source;
18221 operands[1] = scratch;
18223 if (info->lr_save_p)
18225 rtx frame_rtx = stack_pointer_rtx;
18226 HOST_WIDE_INT sp_offset = 0;
18229 if (frame_pointer_needed
18230 || cfun->calls_alloca
18231 || info->total_size > 32767)
18233 tmp = gen_frame_mem (Pmode, frame_rtx);
18234 emit_move_insn (operands[1], tmp);
18235 frame_rtx = operands[1];
18237 else if (info->push_p)
18238 sp_offset = info->total_size;
18240 tmp = plus_constant (Pmode, frame_rtx,
18241 info->lr_save_offset + sp_offset);
18242 tmp = gen_frame_mem (Pmode, tmp);
18243 emit_move_insn (tmp, operands[0]);
18246 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18248 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18249 state of lr_save_p so any change from here on would be a bug. In
18250 particular, stop rs6000_ra_ever_killed from considering the SET
18251 of lr we may have added just above. */
18252 cfun->machine->lr_save_state = info->lr_save_p + 1;
18255 static GTY(()) alias_set_type set = -1;
18258 get_TOC_alias_set (void)
18261 set = new_alias_set ();
18265 /* This returns nonzero if the current function uses the TOC. This is
18266 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18267 is generated by the ABI_V4 load_toc_* patterns. */
18274 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18277 rtx pat = PATTERN (insn);
18280 if (GET_CODE (pat) == PARALLEL)
18281 for (i = 0; i < XVECLEN (pat, 0); i++)
18283 rtx sub = XVECEXP (pat, 0, i);
18284 if (GET_CODE (sub) == USE)
18286 sub = XEXP (sub, 0);
18287 if (GET_CODE (sub) == UNSPEC
18288 && XINT (sub, 1) == UNSPEC_TOC)
18298 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18300 rtx tocrel, tocreg, hi;
18302 if (TARGET_DEBUG_ADDR)
18304 if (GET_CODE (symbol) == SYMBOL_REF)
18305 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18309 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18310 GET_RTX_NAME (GET_CODE (symbol)));
18311 debug_rtx (symbol);
18315 if (!can_create_pseudo_p ())
18316 df_set_regs_ever_live (TOC_REGISTER, true);
18318 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18319 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
18320 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
18323 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
18324 if (largetoc_reg != NULL)
18326 emit_move_insn (largetoc_reg, hi);
18329 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
18332 /* Issue assembly directives that create a reference to the given DWARF
18333 FRAME_TABLE_LABEL from the current function section. */
18335 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18337 fprintf (asm_out_file, "\t.ref %s\n",
18338 TARGET_STRIP_NAME_ENCODING (frame_table_label));
18341 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18342 and the change to the stack pointer. */
18345 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
18352 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18353 if (hard_frame_needed)
18354 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
18355 if (!(REGNO (fp) == STACK_POINTER_REGNUM
18356 || (hard_frame_needed
18357 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
18360 p = rtvec_alloc (i);
18363 rtx mem = gen_frame_mem (BLKmode, regs[i]);
18364 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, const0_rtx);
18367 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
18370 /* Emit the correct code for allocating stack space, as insns.
18371 If COPY_REG, make sure a copy of the old frame is left there.
18372 The generated code may use hard register 0 as a temporary. */
18375 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
18378 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18379 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18380 rtx todec = gen_int_mode (-size, Pmode);
18383 if (INTVAL (todec) != -size)
18385 warning (0, "stack frame too large");
18386 emit_insn (gen_trap ());
18390 if (crtl->limit_stack)
18392 if (REG_P (stack_limit_rtx)
18393 && REGNO (stack_limit_rtx) > 1
18394 && REGNO (stack_limit_rtx) <= 31)
18396 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18397 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18400 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18402 && DEFAULT_ABI == ABI_V4)
18404 rtx toload = gen_rtx_CONST (VOIDmode,
18405 gen_rtx_PLUS (Pmode,
18409 emit_insn (gen_elf_high (tmp_reg, toload));
18410 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18411 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18415 warning (0, "stack limit expression is not supported");
18421 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
18423 emit_move_insn (copy_reg, stack_reg);
18428 /* Need a note here so that try_split doesn't get confused. */
18429 if (get_last_insn () == NULL_RTX)
18430 emit_note (NOTE_INSN_DELETED);
18431 insn = emit_move_insn (tmp_reg, todec);
18432 try_split (PATTERN (insn), insn, 0);
18436 insn = emit_insn (TARGET_32BIT
18437 ? gen_movsi_update_stack (stack_reg, stack_reg,
18439 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18440 todec, stack_reg));
18441 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18442 it now and set the alias set/attributes. The above gen_*_update
18443 calls will generate a PARALLEL with the MEM set being the first
18445 par = PATTERN (insn);
18446 gcc_assert (GET_CODE (par) == PARALLEL);
18447 set = XVECEXP (par, 0, 0);
18448 gcc_assert (GET_CODE (set) == SET);
18449 mem = SET_DEST (set);
18450 gcc_assert (MEM_P (mem));
18451 MEM_NOTRAP_P (mem) = 1;
18452 set_mem_alias_set (mem, get_frame_alias_set ());
18454 RTX_FRAME_RELATED_P (insn) = 1;
18455 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18456 gen_rtx_SET (VOIDmode, stack_reg,
18457 gen_rtx_PLUS (Pmode, stack_reg,
18458 GEN_INT (-size))));
18461 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18463 #if PROBE_INTERVAL > 32768
18464 #error Cannot use indexed addressing mode for stack probing
18467 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18468 inclusive. These are offsets from the current stack pointer. */
18471 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18473 /* See if we have a constant small number of probes to generate. If so,
18474 that's the easy case. */
18475 if (first + size <= 32768)
18479 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18480 it exceeds SIZE. If only one probe is needed, this will not
18481 generate any code. Then probe at FIRST + SIZE. */
18482 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18483 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18486 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18490 /* Otherwise, do the same as above, but in a loop. Note that we must be
18491 extra careful with variables wrapping around because we might be at
18492 the very top (or the very bottom) of the address space and we have
18493 to be able to handle this case properly; in particular, we use an
18494 equality test for the loop condition. */
18497 HOST_WIDE_INT rounded_size;
18498 rtx r12 = gen_rtx_REG (Pmode, 12);
18499 rtx r0 = gen_rtx_REG (Pmode, 0);
18501 /* Sanity check for the addressing mode we're going to use. */
18502 gcc_assert (first <= 32768);
18504 /* Step 1: round SIZE to the previous multiple of the interval. */
18506 rounded_size = size & -PROBE_INTERVAL;
18509 /* Step 2: compute initial and final value of the loop counter. */
18511 /* TEST_ADDR = SP + FIRST. */
18512 emit_insn (gen_rtx_SET (VOIDmode, r12,
18513 plus_constant (Pmode, stack_pointer_rtx,
18516 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18517 if (rounded_size > 32768)
18519 emit_move_insn (r0, GEN_INT (-rounded_size));
18520 emit_insn (gen_rtx_SET (VOIDmode, r0,
18521 gen_rtx_PLUS (Pmode, r12, r0)));
18524 emit_insn (gen_rtx_SET (VOIDmode, r0,
18525 plus_constant (Pmode, r12, -rounded_size)));
18528 /* Step 3: the loop
18530 while (TEST_ADDR != LAST_ADDR)
18532 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18536 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18537 until it is equal to ROUNDED_SIZE. */
18540 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18542 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18545 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18546 that SIZE is equal to ROUNDED_SIZE. */
18548 if (size != rounded_size)
18549 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
18553 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18554 absolute addresses. */
18557 output_probe_stack_range (rtx reg1, rtx reg2)
18559 static int labelno = 0;
18560 char loop_lab[32], end_lab[32];
18563 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18564 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18566 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18568 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18572 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
18574 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
18576 fputs ("\tbeq 0,", asm_out_file);
18577 assemble_name_raw (asm_out_file, end_lab);
18578 fputc ('\n', asm_out_file);
18580 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18581 xops[1] = GEN_INT (-PROBE_INTERVAL);
18582 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
18584 /* Probe at TEST_ADDR and branch. */
18585 xops[1] = gen_rtx_REG (Pmode, 0);
18586 output_asm_insn ("{st|stw} %1,0(%0)", xops);
18587 fprintf (asm_out_file, "\tb ");
18588 assemble_name_raw (asm_out_file, loop_lab);
18589 fputc ('\n', asm_out_file);
18591 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18596 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18597 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18598 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18599 deduce these equivalences by itself so it wasn't necessary to hold
18600 its hand so much. Don't be tempted to always supply d2_f_d_e with
18601 the actual cfa register, ie. r31 when we are using a hard frame
18602 pointer. That fails when saving regs off r1, and sched moves the
18603 r31 setup past the reg saves. */
18606 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18607 rtx reg2, rtx rreg)
18611 if (REGNO (reg) == STACK_POINTER_REGNUM && reg2 == NULL_RTX)
18613 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
18616 gcc_checking_assert (val == 0);
18617 real = PATTERN (insn);
18618 if (GET_CODE (real) == PARALLEL)
18619 for (i = 0; i < XVECLEN (real, 0); i++)
18620 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18622 rtx set = XVECEXP (real, 0, i);
18624 RTX_FRAME_RELATED_P (set) = 1;
18626 RTX_FRAME_RELATED_P (insn) = 1;
18630 /* copy_rtx will not make unique copies of registers, so we need to
18631 ensure we don't have unwanted sharing here. */
18633 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18636 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18638 real = copy_rtx (PATTERN (insn));
18640 if (reg2 != NULL_RTX)
18641 real = replace_rtx (real, reg2, rreg);
18643 if (REGNO (reg) == STACK_POINTER_REGNUM)
18644 gcc_checking_assert (val == 0);
18646 real = replace_rtx (real, reg,
18647 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
18648 STACK_POINTER_REGNUM),
18651 /* We expect that 'real' is either a SET or a PARALLEL containing
18652 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18653 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18655 if (GET_CODE (real) == SET)
18659 temp = simplify_rtx (SET_SRC (set));
18661 SET_SRC (set) = temp;
18662 temp = simplify_rtx (SET_DEST (set));
18664 SET_DEST (set) = temp;
18665 if (GET_CODE (SET_DEST (set)) == MEM)
18667 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18669 XEXP (SET_DEST (set), 0) = temp;
18676 gcc_assert (GET_CODE (real) == PARALLEL);
18677 for (i = 0; i < XVECLEN (real, 0); i++)
18678 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18680 rtx set = XVECEXP (real, 0, i);
18682 temp = simplify_rtx (SET_SRC (set));
18684 SET_SRC (set) = temp;
18685 temp = simplify_rtx (SET_DEST (set));
18687 SET_DEST (set) = temp;
18688 if (GET_CODE (SET_DEST (set)) == MEM)
18690 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18692 XEXP (SET_DEST (set), 0) = temp;
18694 RTX_FRAME_RELATED_P (set) = 1;
18698 RTX_FRAME_RELATED_P (insn) = 1;
18699 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
18704 /* Returns an insn that has a vrsave set operation with the
18705 appropriate CLOBBERs. */
18708 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
18711 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
18712 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
18715 = gen_rtx_SET (VOIDmode,
18717 gen_rtx_UNSPEC_VOLATILE (SImode,
18718 gen_rtvec (2, reg, vrsave),
18719 UNSPECV_SET_VRSAVE));
18723 /* We need to clobber the registers in the mask so the scheduler
18724 does not move sets to VRSAVE before sets of AltiVec registers.
18726 However, if the function receives nonlocal gotos, reload will set
18727 all call saved registers live. We will end up with:
18729 (set (reg 999) (mem))
18730 (parallel [ (set (reg vrsave) (unspec blah))
18731 (clobber (reg 999))])
18733 The clobber will cause the store into reg 999 to be dead, and
18734 flow will attempt to delete an epilogue insn. In this case, we
18735 need an unspec use/set of the register. */
18737 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
18738 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
18740 if (!epiloguep || call_used_regs [i])
18741 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
18742 gen_rtx_REG (V4SImode, i));
18745 rtx reg = gen_rtx_REG (V4SImode, i);
18748 = gen_rtx_SET (VOIDmode,
18750 gen_rtx_UNSPEC (V4SImode,
18751 gen_rtvec (1, reg), 27));
18755 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
18757 for (i = 0; i < nclobs; ++i)
18758 XVECEXP (insn, 0, i) = clobs[i];
18764 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
18768 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
18769 mem = gen_frame_mem (GET_MODE (reg), addr);
18770 return gen_rtx_SET (VOIDmode, store ? mem : reg, store ? reg : mem);
18774 gen_frame_load (rtx reg, rtx frame_reg, int offset)
18776 return gen_frame_set (reg, frame_reg, offset, false);
18780 gen_frame_store (rtx reg, rtx frame_reg, int offset)
18782 return gen_frame_set (reg, frame_reg, offset, true);
18785 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18786 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18789 emit_frame_save (rtx frame_reg, enum machine_mode mode,
18790 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
18794 /* Some cases that need register indexed addressing. */
18795 gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
18796 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
18797 || (TARGET_E500_DOUBLE && mode == DFmode)
18799 && SPE_VECTOR_MODE (mode)
18800 && !SPE_CONST_OFFSET_OK (offset))));
18802 reg = gen_rtx_REG (mode, regno);
18803 insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
18804 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
18805 NULL_RTX, NULL_RTX);
18808 /* Emit an offset memory reference suitable for a frame store, while
18809 converting to a valid addressing mode. */
18812 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
18814 rtx int_rtx, offset_rtx;
18816 int_rtx = GEN_INT (offset);
18818 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
18819 || (TARGET_E500_DOUBLE && mode == DFmode))
18821 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
18822 emit_move_insn (offset_rtx, int_rtx);
18825 offset_rtx = int_rtx;
18827 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
18830 #ifndef TARGET_FIX_AND_CONTINUE
18831 #define TARGET_FIX_AND_CONTINUE 0
18834 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
18835 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
18836 #define LAST_SAVRES_REGISTER 31
18837 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
18848 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
18850 /* Temporary holding space for an out-of-line register save/restore
18852 static char savres_routine_name[30];
18854 /* Return the name for an out-of-line register save/restore routine.
18855 We are saving/restoring GPRs if GPR is true. */
18858 rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
18860 const char *prefix = "";
18861 const char *suffix = "";
18863 /* Different targets are supposed to define
18864 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
18865 routine name could be defined with:
18867 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
18869 This is a nice idea in practice, but in reality, things are
18870 complicated in several ways:
18872 - ELF targets have save/restore routines for GPRs.
18874 - SPE targets use different prefixes for 32/64-bit registers, and
18875 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
18877 - PPC64 ELF targets have routines for save/restore of GPRs that
18878 differ in what they do with the link register, so having a set
18879 prefix doesn't work. (We only use one of the save routines at
18880 the moment, though.)
18882 - PPC32 elf targets have "exit" versions of the restore routines
18883 that restore the link register and can save some extra space.
18884 These require an extra suffix. (There are also "tail" versions
18885 of the restore routines and "GOT" versions of the save routines,
18886 but we don't generate those at present. Same problems apply,
18889 We deal with all this by synthesizing our own prefix/suffix and
18890 using that for the simple sprintf call shown above. */
18893 /* No floating point saves on the SPE. */
18894 gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
18896 if ((sel & SAVRES_SAVE))
18897 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
18899 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
18901 if ((sel & SAVRES_LR))
18904 else if (DEFAULT_ABI == ABI_V4)
18909 if ((sel & SAVRES_REG) == SAVRES_GPR)
18910 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
18911 else if ((sel & SAVRES_REG) == SAVRES_FPR)
18912 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
18913 else if ((sel & SAVRES_REG) == SAVRES_VR)
18914 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
18918 if ((sel & SAVRES_LR))
18921 else if (DEFAULT_ABI == ABI_AIX)
18923 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
18924 /* No out-of-line save/restore routines for GPRs on AIX. */
18925 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
18929 if ((sel & SAVRES_REG) == SAVRES_GPR)
18930 prefix = ((sel & SAVRES_SAVE)
18931 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
18932 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
18933 else if ((sel & SAVRES_REG) == SAVRES_FPR)
18935 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
18936 if ((sel & SAVRES_LR))
18937 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
18941 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
18942 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
18945 else if ((sel & SAVRES_REG) == SAVRES_VR)
18946 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
18951 if (DEFAULT_ABI == ABI_DARWIN)
18953 /* The Darwin approach is (slightly) different, in order to be
18954 compatible with code generated by the system toolchain. There is a
18955 single symbol for the start of save sequence, and the code here
18956 embeds an offset into that code on the basis of the first register
18958 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
18959 if ((sel & SAVRES_REG) == SAVRES_GPR)
18960 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
18961 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
18962 (regno - 13) * 4, prefix, regno);
18963 else if ((sel & SAVRES_REG) == SAVRES_FPR)
18964 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
18965 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
18966 else if ((sel & SAVRES_REG) == SAVRES_VR)
18967 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
18968 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
18973 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
18975 return savres_routine_name;
18978 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
18979 We are saving/restoring GPRs if GPR is true. */
18982 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
18984 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
18985 ? info->first_gp_reg_save
18986 : (sel & SAVRES_REG) == SAVRES_FPR
18987 ? info->first_fp_reg_save - 32
18988 : (sel & SAVRES_REG) == SAVRES_VR
18989 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
18994 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
18995 versions of the gpr routines. */
18996 if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
18997 && info->spe_64bit_regs_used)
18998 select ^= SAVRES_FPR ^ SAVRES_GPR;
19000 /* Don't generate bogus routine names. */
19001 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19002 && regno <= LAST_SAVRES_REGISTER
19003 && select >= 0 && select <= 12);
19005 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19011 name = rs6000_savres_routine_name (info, regno, sel);
19013 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19014 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19015 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19021 /* Emit a sequence of insns, including a stack tie if needed, for
19022 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
19023 reset the stack pointer, but move the base of the frame into
19024 reg UPDT_REGNO for use by out-of-line register restore routines. */
19027 rs6000_emit_stack_reset (rs6000_stack_t *info,
19028 rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
19029 unsigned updt_regno)
19033 /* This blockage is needed so that sched doesn't decide to move
19034 the sp change before the register restores. */
19035 if (DEFAULT_ABI == ABI_V4
19037 && info->spe_64bit_regs_used != 0
19038 && info->first_gp_reg_save != 32))
19039 rs6000_emit_stack_tie (frame_reg_rtx, frame_pointer_needed);
19041 /* If we are restoring registers out-of-line, we will be using the
19042 "exit" variants of the restore routines, which will reset the
19043 stack for us. But we do need to point updt_reg into the
19044 right place for those routines. */
19045 updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
19047 if (frame_off != 0)
19048 return emit_insn (gen_add3_insn (updt_reg_rtx,
19049 frame_reg_rtx, GEN_INT (frame_off)));
19050 else if (REGNO (frame_reg_rtx) != updt_regno)
19051 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
19056 static inline unsigned
19057 ptr_regno_for_savres (int sel)
19059 if (DEFAULT_ABI == ABI_AIX)
19060 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
19061 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
19064 /* Construct a parallel rtx describing the effect of a call to an
19065 out-of-line register save/restore routine, and emit the insn
19066 or jump_insn as appropriate. */
19069 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19070 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
19071 enum machine_mode reg_mode, int sel)
19074 int offset, start_reg, end_reg, n_regs, use_reg;
19075 int reg_size = GET_MODE_SIZE (reg_mode);
19081 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19082 ? info->first_gp_reg_save
19083 : (sel & SAVRES_REG) == SAVRES_FPR
19084 ? info->first_fp_reg_save
19085 : (sel & SAVRES_REG) == SAVRES_VR
19086 ? info->first_altivec_reg_save
19088 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19090 : (sel & SAVRES_REG) == SAVRES_FPR
19092 : (sel & SAVRES_REG) == SAVRES_VR
19093 ? LAST_ALTIVEC_REGNO + 1
19095 n_regs = end_reg - start_reg;
19096 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
19097 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
19100 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19101 RTVEC_ELT (p, offset++) = ret_rtx;
19103 RTVEC_ELT (p, offset++)
19104 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19106 sym = rs6000_savres_routine_sym (info, sel);
19107 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19109 use_reg = ptr_regno_for_savres (sel);
19110 if ((sel & SAVRES_REG) == SAVRES_VR)
19112 /* Vector regs are saved/restored using [reg+reg] addressing. */
19113 RTVEC_ELT (p, offset++)
19114 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19115 RTVEC_ELT (p, offset++)
19116 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
19119 RTVEC_ELT (p, offset++)
19120 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19122 for (i = 0; i < end_reg - start_reg; i++)
19123 RTVEC_ELT (p, i + offset)
19124 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
19125 frame_reg_rtx, save_area_offset + reg_size * i,
19126 (sel & SAVRES_SAVE) != 0);
19128 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19129 RTVEC_ELT (p, i + offset)
19130 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
19132 par = gen_rtx_PARALLEL (VOIDmode, p);
19134 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19136 insn = emit_jump_insn (par);
19137 JUMP_LABEL (insn) = ret_rtx;
19140 insn = emit_insn (par);
19144 /* Determine whether the gp REG is really used. */
19147 rs6000_reg_live_or_pic_offset_p (int reg)
19149 /* If the function calls eh_return, claim used all the registers that would
19150 be checked for liveness otherwise. This is required for the PIC offset
19151 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19152 register allocation purposes in this case. */
19154 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19155 && (!call_used_regs[reg]
19156 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19157 && !TARGET_SINGLE_PIC_BASE
19158 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19159 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19160 && !TARGET_SINGLE_PIC_BASE
19161 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19162 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19165 /* Emit function prologue as insns. */
19168 rs6000_emit_prologue (void)
19170 rs6000_stack_t *info = rs6000_stack_info ();
19171 enum machine_mode reg_mode = Pmode;
19172 int reg_size = TARGET_32BIT ? 4 : 8;
19173 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19174 rtx frame_reg_rtx = sp_reg_rtx;
19175 unsigned int cr_save_regno;
19176 rtx cr_save_rtx = NULL_RTX;
19179 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19180 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19181 && call_used_regs[STATIC_CHAIN_REGNUM]);
19182 /* Offset to top of frame for frame_reg and sp respectively. */
19183 HOST_WIDE_INT frame_off = 0;
19184 HOST_WIDE_INT sp_off = 0;
19186 #ifdef ENABLE_CHECKING
19187 /* Track and check usage of r0, r11, r12. */
19188 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
19189 #define START_USE(R) do \
19191 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19192 reg_inuse |= 1 << (R); \
19194 #define END_USE(R) do \
19196 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
19197 reg_inuse &= ~(1 << (R)); \
19199 #define NOT_INUSE(R) do \
19201 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19204 #define START_USE(R) do {} while (0)
19205 #define END_USE(R) do {} while (0)
19206 #define NOT_INUSE(R) do {} while (0)
19209 if (flag_stack_usage_info)
19210 current_function_static_stack_size = info->total_size;
19212 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19213 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19215 if (TARGET_FIX_AND_CONTINUE)
19217 /* gdb on darwin arranges to forward a function from the old
19218 address by modifying the first 5 instructions of the function
19219 to branch to the overriding function. This is necessary to
19220 permit function pointers that point to the old function to
19221 actually forward to the new function. */
19222 emit_insn (gen_nop ());
19223 emit_insn (gen_nop ());
19224 emit_insn (gen_nop ());
19225 emit_insn (gen_nop ());
19226 emit_insn (gen_nop ());
19229 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19231 reg_mode = V2SImode;
19235 /* Handle world saves specially here. */
19236 if (WORLD_SAVE_P (info))
19243 /* save_world expects lr in r0. */
19244 reg0 = gen_rtx_REG (Pmode, 0);
19245 if (info->lr_save_p)
19247 insn = emit_move_insn (reg0,
19248 gen_rtx_REG (Pmode, LR_REGNO));
19249 RTX_FRAME_RELATED_P (insn) = 1;
19252 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19253 assumptions about the offsets of various bits of the stack
19255 gcc_assert (info->gp_save_offset == -220
19256 && info->fp_save_offset == -144
19257 && info->lr_save_offset == 8
19258 && info->cr_save_offset == 4
19261 && (!crtl->calls_eh_return
19262 || info->ehrd_offset == -432)
19263 && info->vrsave_save_offset == -224
19264 && info->altivec_save_offset == -416);
19266 treg = gen_rtx_REG (SImode, 11);
19267 emit_move_insn (treg, GEN_INT (-info->total_size));
19269 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19270 in R11. It also clobbers R12, so beware! */
19272 /* Preserve CR2 for save_world prologues */
19274 sz += 32 - info->first_gp_reg_save;
19275 sz += 64 - info->first_fp_reg_save;
19276 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19277 p = rtvec_alloc (sz);
19279 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19280 gen_rtx_REG (SImode,
19282 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19283 gen_rtx_SYMBOL_REF (Pmode,
19285 /* We do floats first so that the instruction pattern matches
19287 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19289 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19291 info->first_fp_reg_save + i),
19293 info->fp_save_offset + frame_off + 8 * i);
19294 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19296 = gen_frame_store (gen_rtx_REG (V4SImode,
19297 info->first_altivec_reg_save + i),
19299 info->altivec_save_offset + frame_off + 16 * i);
19300 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19302 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19304 info->gp_save_offset + frame_off + reg_size * i);
19306 /* CR register traditionally saved as CR2. */
19308 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
19309 frame_reg_rtx, info->cr_save_offset + frame_off);
19310 /* Explain about use of R0. */
19311 if (info->lr_save_p)
19313 = gen_frame_store (reg0,
19314 frame_reg_rtx, info->lr_save_offset + frame_off);
19315 /* Explain what happens to the stack pointer. */
19317 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19318 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19321 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19322 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19323 treg, GEN_INT (-info->total_size));
19324 sp_off = frame_off = info->total_size;
19327 strategy = info->savres_strategy;
19329 /* For V.4, update stack before we do any saving and set back pointer. */
19330 if (! WORLD_SAVE_P (info)
19332 && (DEFAULT_ABI == ABI_V4
19333 || crtl->calls_eh_return))
19335 bool need_r11 = (TARGET_SPE
19336 ? (!(strategy & SAVE_INLINE_GPRS)
19337 && info->spe_64bit_regs_used == 0)
19338 : (!(strategy & SAVE_INLINE_FPRS)
19339 || !(strategy & SAVE_INLINE_GPRS)
19340 || !(strategy & SAVE_INLINE_VRS)));
19341 int ptr_regno = -1;
19342 rtx ptr_reg = NULL_RTX;
19345 if (info->total_size < 32767)
19346 frame_off = info->total_size;
19349 else if (info->cr_save_p
19351 || info->first_fp_reg_save < 64
19352 || info->first_gp_reg_save < 32
19353 || info->altivec_size != 0
19354 || info->vrsave_mask != 0
19355 || crtl->calls_eh_return)
19359 /* The prologue won't be saving any regs so there is no need
19360 to set up a frame register to access any frame save area.
19361 We also won't be using frame_off anywhere below, but set
19362 the correct value anyway to protect against future
19363 changes to this function. */
19364 frame_off = info->total_size;
19366 if (ptr_regno != -1)
19368 /* Set up the frame offset to that needed by the first
19369 out-of-line save function. */
19370 START_USE (ptr_regno);
19371 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19372 frame_reg_rtx = ptr_reg;
19373 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
19374 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
19375 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
19376 ptr_off = info->gp_save_offset + info->gp_size;
19377 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
19378 ptr_off = info->altivec_save_offset + info->altivec_size;
19379 frame_off = -ptr_off;
19381 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19382 sp_off = info->total_size;
19383 if (frame_reg_rtx != sp_reg_rtx)
19384 rs6000_emit_stack_tie (frame_reg_rtx, false);
19387 /* If we use the link register, get it into r0. */
19388 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19390 rtx addr, reg, mem;
19392 reg = gen_rtx_REG (Pmode, 0);
19394 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
19395 RTX_FRAME_RELATED_P (insn) = 1;
19397 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19398 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19400 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19401 GEN_INT (info->lr_save_offset + frame_off));
19402 mem = gen_rtx_MEM (Pmode, addr);
19403 /* This should not be of rs6000_sr_alias_set, because of
19404 __builtin_return_address. */
19406 insn = emit_move_insn (mem, reg);
19407 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19408 NULL_RTX, NULL_RTX);
19413 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
19414 r12 will be needed by out-of-line gpr restore. */
19415 cr_save_regno = (DEFAULT_ABI == ABI_AIX
19416 && !(strategy & (SAVE_INLINE_GPRS
19417 | SAVE_NOINLINE_GPRS_SAVES_LR))
19419 if (!WORLD_SAVE_P (info)
19421 && REGNO (frame_reg_rtx) != cr_save_regno
19422 && !(using_static_chain_p && cr_save_regno == 11))
19426 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
19427 START_USE (cr_save_regno);
19428 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19429 RTX_FRAME_RELATED_P (insn) = 1;
19430 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19431 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19432 But that's OK. All we have to do is specify that _one_ condition
19433 code register is saved in this stack slot. The thrower's epilogue
19434 will then restore all the call-saved registers.
19435 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19436 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19437 gen_rtx_REG (SImode, CR2_REGNO));
19438 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19441 /* Do any required saving of fpr's. If only one or two to save, do
19442 it ourselves. Otherwise, call function. */
19443 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
19446 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19447 if (save_reg_p (info->first_fp_reg_save + i))
19448 emit_frame_save (frame_reg_rtx,
19449 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19450 ? DFmode : SFmode),
19451 info->first_fp_reg_save + i,
19452 info->fp_save_offset + frame_off + 8 * i,
19453 sp_off - frame_off);
19455 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19457 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
19458 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
19459 unsigned ptr_regno = ptr_regno_for_savres (sel);
19460 rtx ptr_reg = frame_reg_rtx;
19462 if (REGNO (frame_reg_rtx) == ptr_regno)
19463 gcc_checking_assert (frame_off == 0);
19466 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19467 NOT_INUSE (ptr_regno);
19468 emit_insn (gen_add3_insn (ptr_reg,
19469 frame_reg_rtx, GEN_INT (frame_off)));
19471 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19472 info->fp_save_offset,
19473 info->lr_save_offset,
19475 rs6000_frame_related (insn, ptr_reg, sp_off,
19476 NULL_RTX, NULL_RTX);
19481 /* Save GPRs. This is done as a PARALLEL if we are using
19482 the store-multiple instructions. */
19483 if (!WORLD_SAVE_P (info)
19485 && info->spe_64bit_regs_used != 0
19486 && info->first_gp_reg_save != 32)
19489 rtx spe_save_area_ptr;
19490 HOST_WIDE_INT save_off;
19491 int ool_adjust = 0;
19493 /* Determine whether we can address all of the registers that need
19494 to be saved with an offset from frame_reg_rtx that fits in
19495 the small const field for SPE memory instructions. */
19496 int spe_regs_addressable
19497 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
19498 + reg_size * (32 - info->first_gp_reg_save - 1))
19499 && (strategy & SAVE_INLINE_GPRS));
19501 if (spe_regs_addressable)
19503 spe_save_area_ptr = frame_reg_rtx;
19504 save_off = frame_off;
19508 /* Make r11 point to the start of the SPE save area. We need
19509 to be careful here if r11 is holding the static chain. If
19510 it is, then temporarily save it in r0. */
19511 HOST_WIDE_INT offset;
19513 if (!(strategy & SAVE_INLINE_GPRS))
19514 ool_adjust = 8 * (info->first_gp_reg_save
19515 - (FIRST_SAVRES_REGISTER + 1));
19516 offset = info->spe_gp_save_offset + frame_off - ool_adjust;
19517 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19518 save_off = frame_off - offset;
19520 if (using_static_chain_p)
19522 rtx r0 = gen_rtx_REG (Pmode, 0);
19525 gcc_assert (info->first_gp_reg_save > 11);
19527 emit_move_insn (r0, spe_save_area_ptr);
19529 else if (REGNO (frame_reg_rtx) != 11)
19532 emit_insn (gen_addsi3 (spe_save_area_ptr,
19533 frame_reg_rtx, GEN_INT (offset)));
19534 if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
19535 frame_off = -info->spe_gp_save_offset + ool_adjust;
19538 if ((strategy & SAVE_INLINE_GPRS))
19540 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19541 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19542 emit_frame_save (spe_save_area_ptr, reg_mode,
19543 info->first_gp_reg_save + i,
19544 (info->spe_gp_save_offset + save_off
19546 sp_off - save_off);
19550 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19551 info->spe_gp_save_offset + save_off,
19553 SAVRES_SAVE | SAVRES_GPR);
19555 rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
19556 NULL_RTX, NULL_RTX);
19559 /* Move the static chain pointer back. */
19560 if (!spe_regs_addressable)
19562 if (using_static_chain_p)
19564 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19567 else if (REGNO (frame_reg_rtx) != 11)
19571 else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
19573 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
19574 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
19575 unsigned ptr_regno = ptr_regno_for_savres (sel);
19576 rtx ptr_reg = frame_reg_rtx;
19577 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
19578 int end_save = info->gp_save_offset + info->gp_size;
19582 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19584 /* Need to adjust r11 (r12) if we saved any FPRs. */
19585 if (end_save + frame_off != 0)
19587 rtx offset = GEN_INT (end_save + frame_off);
19590 frame_off = -end_save;
19592 NOT_INUSE (ptr_regno);
19593 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
19595 else if (!ptr_set_up)
19597 NOT_INUSE (ptr_regno);
19598 emit_move_insn (ptr_reg, frame_reg_rtx);
19600 ptr_off = -end_save;
19601 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19602 info->gp_save_offset + ptr_off,
19603 info->lr_save_offset + ptr_off,
19605 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
19606 NULL_RTX, NULL_RTX);
19610 else if (!WORLD_SAVE_P (info) && (strategy & SAVRES_MULTIPLE))
19614 p = rtvec_alloc (32 - info->first_gp_reg_save);
19615 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19617 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19619 info->gp_save_offset + frame_off + reg_size * i);
19620 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19621 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19622 NULL_RTX, NULL_RTX);
19624 else if (!WORLD_SAVE_P (info))
19627 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19628 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19629 emit_frame_save (frame_reg_rtx, reg_mode,
19630 info->first_gp_reg_save + i,
19631 info->gp_save_offset + frame_off + reg_size * i,
19632 sp_off - frame_off);
19635 if (crtl->calls_eh_return)
19642 unsigned int regno = EH_RETURN_DATA_REGNO (i);
19643 if (regno == INVALID_REGNUM)
19647 p = rtvec_alloc (i);
19651 unsigned int regno = EH_RETURN_DATA_REGNO (i);
19652 if (regno == INVALID_REGNUM)
19656 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
19658 info->ehrd_offset + sp_off + reg_size * (int) i);
19659 RTVEC_ELT (p, i) = insn;
19660 RTX_FRAME_RELATED_P (insn) = 1;
19663 insn = emit_insn (gen_blockage ());
19664 RTX_FRAME_RELATED_P (insn) = 1;
19665 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
19668 /* In AIX ABI we need to make sure r2 is really saved. */
19669 if (TARGET_AIX && crtl->calls_eh_return)
19671 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
19672 rtx save_insn, join_insn, note;
19673 long toc_restore_insn;
19675 tmp_reg = gen_rtx_REG (Pmode, 11);
19676 tmp_reg_si = gen_rtx_REG (SImode, 11);
19677 if (using_static_chain_p)
19680 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
19684 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
19685 /* Peek at instruction to which this function returns. If it's
19686 restoring r2, then we know we've already saved r2. We can't
19687 unconditionally save r2 because the value we have will already
19688 be updated if we arrived at this function via a plt call or
19689 toc adjusting stub. */
19690 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
19691 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
19692 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
19693 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
19694 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
19695 validate_condition_mode (EQ, CCUNSmode);
19696 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
19697 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19698 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
19699 toc_save_done = gen_label_rtx ();
19700 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
19701 gen_rtx_EQ (VOIDmode, compare_result,
19703 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
19705 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
19706 JUMP_LABEL (jump) = toc_save_done;
19707 LABEL_NUSES (toc_save_done) += 1;
19709 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
19710 TOC_REGNUM, frame_off + 5 * reg_size,
19711 sp_off - frame_off);
19713 emit_label (toc_save_done);
19715 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19716 have a CFG that has different saves along different paths.
19717 Move the note to a dummy blockage insn, which describes that
19718 R2 is unconditionally saved after the label. */
19719 /* ??? An alternate representation might be a special insn pattern
19720 containing both the branch and the store. That might let the
19721 code that minimizes the number of DW_CFA_advance opcodes better
19722 freedom in placing the annotations. */
19723 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
19725 remove_note (save_insn, note);
19727 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
19728 copy_rtx (PATTERN (save_insn)), NULL_RTX);
19729 RTX_FRAME_RELATED_P (save_insn) = 0;
19731 join_insn = emit_insn (gen_blockage ());
19732 REG_NOTES (join_insn) = note;
19733 RTX_FRAME_RELATED_P (join_insn) = 1;
19735 if (using_static_chain_p)
19737 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
19744 /* Save CR if we use any that must be preserved. */
19745 if (!WORLD_SAVE_P (info) && info->cr_save_p)
19747 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19748 GEN_INT (info->cr_save_offset + frame_off));
19749 rtx mem = gen_frame_mem (SImode, addr);
19750 /* See the large comment above about why CR2_REGNO is used. */
19751 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
19753 /* If we didn't copy cr before, do so now using r0. */
19754 if (cr_save_rtx == NULL_RTX)
19759 cr_save_rtx = gen_rtx_REG (SImode, 0);
19760 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19761 RTX_FRAME_RELATED_P (insn) = 1;
19762 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
19763 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19765 insn = emit_move_insn (mem, cr_save_rtx);
19766 END_USE (REGNO (cr_save_rtx));
19768 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19769 NULL_RTX, NULL_RTX);
19772 /* Update stack and set back pointer unless this is V.4,
19773 for which it was done previously. */
19774 if (!WORLD_SAVE_P (info) && info->push_p
19775 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
19777 rtx ptr_reg = NULL;
19780 /* If saving altivec regs we need to be able to address all save
19781 locations using a 16-bit offset. */
19782 if ((strategy & SAVE_INLINE_VRS) == 0
19783 || (info->altivec_size != 0
19784 && (info->altivec_save_offset + info->altivec_size - 16
19785 + info->total_size - frame_off) > 32767)
19786 || (info->vrsave_mask != 0
19787 && (info->vrsave_save_offset
19788 + info->total_size - frame_off) > 32767))
19790 int sel = SAVRES_SAVE | SAVRES_VR;
19791 unsigned ptr_regno = ptr_regno_for_savres (sel);
19793 if (REGNO (frame_reg_rtx) != ptr_regno)
19794 START_USE (ptr_regno);
19795 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19796 frame_reg_rtx = ptr_reg;
19797 ptr_off = info->altivec_save_offset + info->altivec_size;
19798 frame_off = -ptr_off;
19800 else if (REGNO (frame_reg_rtx) == 1)
19801 frame_off = info->total_size;
19802 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19803 sp_off = info->total_size;
19804 if (frame_reg_rtx != sp_reg_rtx)
19805 rs6000_emit_stack_tie (frame_reg_rtx, false);
19808 /* Set frame pointer, if needed. */
19809 if (frame_pointer_needed)
19811 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
19813 RTX_FRAME_RELATED_P (insn) = 1;
19816 /* Save AltiVec registers if needed. Save here because the red zone does
19817 not always include AltiVec registers. */
19818 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
19819 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
19821 int end_save = info->altivec_save_offset + info->altivec_size;
19823 /* Oddly, the vector save/restore functions point r0 at the end
19824 of the save area, then use r11 or r12 to load offsets for
19825 [reg+reg] addressing. */
19826 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
19827 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
19828 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
19830 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
19832 if (end_save + frame_off != 0)
19834 rtx offset = GEN_INT (end_save + frame_off);
19836 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
19839 emit_move_insn (ptr_reg, frame_reg_rtx);
19841 ptr_off = -end_save;
19842 insn = rs6000_emit_savres_rtx (info, scratch_reg,
19843 info->altivec_save_offset + ptr_off,
19844 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
19845 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
19846 NULL_RTX, NULL_RTX);
19847 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
19849 /* The oddity mentioned above clobbered our frame reg. */
19850 emit_move_insn (frame_reg_rtx, ptr_reg);
19851 frame_off = ptr_off;
19854 else if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
19855 && info->altivec_size != 0)
19859 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
19860 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19862 rtx areg, savereg, mem;
19865 offset = (info->altivec_save_offset + frame_off
19866 + 16 * (i - info->first_altivec_reg_save));
19868 savereg = gen_rtx_REG (V4SImode, i);
19871 areg = gen_rtx_REG (Pmode, 0);
19872 emit_move_insn (areg, GEN_INT (offset));
19874 /* AltiVec addressing mode is [reg+reg]. */
19875 mem = gen_frame_mem (V4SImode,
19876 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
19878 insn = emit_move_insn (mem, savereg);
19880 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19881 areg, GEN_INT (offset));
19885 /* VRSAVE is a bit vector representing which AltiVec registers
19886 are used. The OS uses this to determine which vector
19887 registers to save on a context switch. We need to save
19888 VRSAVE on the stack frame, add whatever AltiVec registers we
19889 used in this function, and do the corresponding magic in the
19892 if (!WORLD_SAVE_P (info)
19894 && TARGET_ALTIVEC_VRSAVE
19895 && info->vrsave_mask != 0)
19901 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
19902 as frame_reg_rtx and r11 as the static chain pointer for
19903 nested functions. */
19905 if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
19907 else if (REGNO (frame_reg_rtx) == 12)
19910 if (using_static_chain_p)
19914 NOT_INUSE (save_regno);
19915 reg = gen_rtx_REG (SImode, save_regno);
19916 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19918 emit_insn (gen_get_vrsave_internal (reg));
19920 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
19923 offset = info->vrsave_save_offset + frame_off;
19924 insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
19926 /* Include the registers in the mask. */
19927 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
19929 insn = emit_insn (generate_set_vrsave (reg, info, 0));
19932 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
19933 if (!TARGET_SINGLE_PIC_BASE
19934 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
19935 || (DEFAULT_ABI == ABI_V4
19936 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
19937 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
19939 /* If emit_load_toc_table will use the link register, we need to save
19940 it. We use R12 for this purpose because emit_load_toc_table
19941 can use register 0. This allows us to use a plain 'blr' to return
19942 from the procedure more often. */
19943 int save_LR_around_toc_setup = (TARGET_ELF
19944 && DEFAULT_ABI != ABI_AIX
19946 && ! info->lr_save_p
19947 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
19948 if (save_LR_around_toc_setup)
19950 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19951 rtx tmp = gen_rtx_REG (Pmode, 12);
19953 insn = emit_move_insn (tmp, lr);
19954 RTX_FRAME_RELATED_P (insn) = 1;
19956 rs6000_emit_load_toc_table (TRUE);
19958 insn = emit_move_insn (lr, tmp);
19959 add_reg_note (insn, REG_CFA_RESTORE, lr);
19960 RTX_FRAME_RELATED_P (insn) = 1;
19963 rs6000_emit_load_toc_table (TRUE);
19967 if (!TARGET_SINGLE_PIC_BASE
19968 && DEFAULT_ABI == ABI_DARWIN
19969 && flag_pic && crtl->uses_pic_offset_table)
19971 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19972 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
19974 /* Save and restore LR locally around this call (in R0). */
19975 if (!info->lr_save_p)
19976 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
19978 emit_insn (gen_load_macho_picbase (src));
19980 emit_move_insn (gen_rtx_REG (Pmode,
19981 RS6000_PIC_OFFSET_TABLE_REGNUM),
19984 if (!info->lr_save_p)
19985 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
19989 /* If we need to, save the TOC register after doing the stack setup.
19990 Do not emit eh frame info for this save. The unwinder wants info,
19991 conceptually attached to instructions in this function, about
19992 register values in the caller of this function. This R2 may have
19993 already been changed from the value in the caller.
19994 We don't attempt to write accurate DWARF EH frame info for R2
19995 because code emitted by gcc for a (non-pointer) function call
19996 doesn't save and restore R2. Instead, R2 is managed out-of-line
19997 by a linker generated plt call stub when the function resides in
19998 a shared library. This behaviour is costly to describe in DWARF,
19999 both in terms of the size of DWARF info and the time taken in the
20000 unwinder to interpret it. R2 changes, apart from the
20001 calls_eh_return case earlier in this function, are handled by
20002 linux-unwind.h frob_update_context. */
20003 if (rs6000_save_toc_in_prologue_p ())
20005 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
20006 emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));
20010 /* Write function prologue. */
20013 rs6000_output_function_prologue (FILE *file,
20014 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20016 rs6000_stack_t *info = rs6000_stack_info ();
20018 if (TARGET_DEBUG_STACK)
20019 debug_stack_info (info);
20021 /* Write .extern for any function we will call to save and restore
20023 if (info->first_fp_reg_save < 64
20028 int regno = info->first_fp_reg_save - 32;
20030 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20032 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
20033 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
20034 name = rs6000_savres_routine_name (info, regno, sel);
20035 fprintf (file, "\t.extern %s\n", name);
20037 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20039 bool lr = (info->savres_strategy
20040 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20041 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20042 name = rs6000_savres_routine_name (info, regno, sel);
20043 fprintf (file, "\t.extern %s\n", name);
20047 /* Write .extern for AIX common mode routines, if needed. */
20048 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
20050 fputs ("\t.extern __mulh\n", file);
20051 fputs ("\t.extern __mull\n", file);
20052 fputs ("\t.extern __divss\n", file);
20053 fputs ("\t.extern __divus\n", file);
20054 fputs ("\t.extern __quoss\n", file);
20055 fputs ("\t.extern __quous\n", file);
20056 common_mode_defined = 1;
20059 rs6000_pic_labelno++;
20062 /* Non-zero if vmx regs are restored before the frame pop, zero if
20063 we restore after the pop when possible. */
20064 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20066 /* Restoring cr is a two step process: loading a reg from the frame
20067 save, then moving the reg to cr. For ABI_V4 we must let the
20068 unwinder know that the stack location is no longer valid at or
20069 before the stack deallocation, but we can't emit a cfa_restore for
20070 cr at the stack deallocation like we do for other registers.
20071 The trouble is that it is possible for the move to cr to be
20072 scheduled after the stack deallocation. So say exactly where cr
20073 is located on each of the two insns. */
20076 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
20078 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
20079 rtx reg = gen_rtx_REG (SImode, regno);
20080 rtx insn = emit_move_insn (reg, mem);
20082 if (!exit_func && DEFAULT_ABI == ABI_V4)
20084 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20085 rtx set = gen_rtx_SET (VOIDmode, reg, cr);
20087 add_reg_note (insn, REG_CFA_REGISTER, set);
20088 RTX_FRAME_RELATED_P (insn) = 1;
20093 /* Reload CR from REG. */
20096 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
20101 if (using_mfcr_multiple)
20103 for (i = 0; i < 8; i++)
20104 if (save_reg_p (CR0_REGNO + i))
20106 gcc_assert (count);
20109 if (using_mfcr_multiple && count > 1)
20114 p = rtvec_alloc (count);
20117 for (i = 0; i < 8; i++)
20118 if (save_reg_p (CR0_REGNO + i))
20120 rtvec r = rtvec_alloc (2);
20121 RTVEC_ELT (r, 0) = reg;
20122 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20123 RTVEC_ELT (p, ndx) =
20124 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i),
20125 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20128 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20129 gcc_assert (ndx == count);
20132 for (i = 0; i < 8; i++)
20133 if (save_reg_p (CR0_REGNO + i))
20134 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),
20137 if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20139 rtx insn = get_last_insn ();
20140 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20142 add_reg_note (insn, REG_CFA_RESTORE, cr);
20143 RTX_FRAME_RELATED_P (insn) = 1;
20147 /* Like cr, the move to lr instruction can be scheduled after the
20148 stack deallocation, but unlike cr, its stack frame save is still
20149 valid. So we only need to emit the cfa_restore on the correct
20153 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
20155 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
20156 rtx reg = gen_rtx_REG (Pmode, regno);
20158 emit_move_insn (reg, mem);
20162 restore_saved_lr (int regno, bool exit_func)
20164 rtx reg = gen_rtx_REG (Pmode, regno);
20165 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20166 rtx insn = emit_move_insn (lr, reg);
20168 if (!exit_func && flag_shrink_wrap)
20170 add_reg_note (insn, REG_CFA_RESTORE, lr);
20171 RTX_FRAME_RELATED_P (insn) = 1;
20176 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
20178 if (info->cr_save_p)
20179 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20180 gen_rtx_REG (SImode, CR2_REGNO),
20182 if (info->lr_save_p)
20183 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20184 gen_rtx_REG (Pmode, LR_REGNO),
20186 return cfa_restores;
20189 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20190 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20191 below stack pointer not cloberred by signals. */
20194 offset_below_red_zone_p (HOST_WIDE_INT offset)
20196 return offset < (DEFAULT_ABI == ABI_V4
20198 : TARGET_32BIT ? -220 : -288);
20201 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20204 emit_cfa_restores (rtx cfa_restores)
20206 rtx insn = get_last_insn ();
20207 rtx *loc = ®_NOTES (insn);
20210 loc = &XEXP (*loc, 1);
20211 *loc = cfa_restores;
20212 RTX_FRAME_RELATED_P (insn) = 1;
20215 /* Emit function epilogue as insns. */
20218 rs6000_emit_epilogue (int sibcall)
20220 rs6000_stack_t *info;
20221 int restoring_GPRs_inline;
20222 int restoring_FPRs_inline;
20223 int using_load_multiple;
20224 int using_mtcr_multiple;
20225 int use_backchain_to_restore_sp;
20228 HOST_WIDE_INT frame_off = 0;
20229 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20230 rtx frame_reg_rtx = sp_reg_rtx;
20231 rtx cfa_restores = NULL_RTX;
20233 rtx cr_save_reg = NULL_RTX;
20234 enum machine_mode reg_mode = Pmode;
20235 int reg_size = TARGET_32BIT ? 4 : 8;
20238 unsigned ptr_regno;
20240 info = rs6000_stack_info ();
20242 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20244 reg_mode = V2SImode;
20248 strategy = info->savres_strategy;
20249 using_load_multiple = strategy & SAVRES_MULTIPLE;
20250 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20251 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20252 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20253 || rs6000_cpu == PROCESSOR_PPC603
20254 || rs6000_cpu == PROCESSOR_PPC750
20256 /* Restore via the backchain when we have a large frame, since this
20257 is more efficient than an addis, addi pair. The second condition
20258 here will not trigger at the moment; We don't actually need a
20259 frame pointer for alloca, but the generic parts of the compiler
20260 give us one anyway. */
20261 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20262 || (cfun->calls_alloca
20263 && !frame_pointer_needed));
20264 restore_lr = (info->lr_save_p
20265 && (restoring_FPRs_inline
20266 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20267 && (restoring_GPRs_inline
20268 || info->first_fp_reg_save < 64));
20270 if (WORLD_SAVE_P (info))
20274 const char *alloc_rname;
20277 /* eh_rest_world_r10 will return to the location saved in the LR
20278 stack slot (which is not likely to be our caller.)
20279 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20280 rest_world is similar, except any R10 parameter is ignored.
20281 The exception-handling stuff that was here in 2.95 is no
20282 longer necessary. */
20286 + 32 - info->first_gp_reg_save
20287 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20288 + 63 + 1 - info->first_fp_reg_save);
20290 strcpy (rname, ((crtl->calls_eh_return) ?
20291 "*eh_rest_world_r10" : "*rest_world"));
20292 alloc_rname = ggc_strdup (rname);
20295 RTVEC_ELT (p, j++) = ret_rtx;
20296 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20297 gen_rtx_REG (Pmode,
20300 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20301 /* The instruction pattern requires a clobber here;
20302 it is shared with the restVEC helper. */
20304 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20307 /* CR register traditionally saved as CR2. */
20308 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
20310 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
20311 if (flag_shrink_wrap)
20313 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20314 gen_rtx_REG (Pmode, LR_REGNO),
20316 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20320 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20322 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20324 = gen_frame_load (reg,
20325 frame_reg_rtx, info->gp_save_offset + reg_size * i);
20326 if (flag_shrink_wrap)
20327 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20329 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20331 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20333 = gen_frame_load (reg,
20334 frame_reg_rtx, info->altivec_save_offset + 16 * i);
20335 if (flag_shrink_wrap)
20336 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20338 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20340 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
20341 ? DFmode : SFmode),
20342 info->first_fp_reg_save + i);
20344 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
20345 if (flag_shrink_wrap)
20346 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20349 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20351 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20353 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20355 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20357 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20358 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20360 if (flag_shrink_wrap)
20362 REG_NOTES (insn) = cfa_restores;
20363 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20364 RTX_FRAME_RELATED_P (insn) = 1;
20369 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
20371 frame_off = info->total_size;
20373 /* Restore AltiVec registers if we must do so before adjusting the
20375 if (TARGET_ALTIVEC_ABI
20376 && info->altivec_size != 0
20377 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20378 || (DEFAULT_ABI != ABI_V4
20379 && offset_below_red_zone_p (info->altivec_save_offset))))
20382 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20384 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20385 if (use_backchain_to_restore_sp)
20387 int frame_regno = 11;
20389 if ((strategy & REST_INLINE_VRS) == 0)
20391 /* Of r11 and r12, select the one not clobbered by an
20392 out-of-line restore function for the frame register. */
20393 frame_regno = 11 + 12 - scratch_regno;
20395 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
20396 emit_move_insn (frame_reg_rtx,
20397 gen_rtx_MEM (Pmode, sp_reg_rtx));
20400 else if (frame_pointer_needed)
20401 frame_reg_rtx = hard_frame_pointer_rtx;
20403 if ((strategy & REST_INLINE_VRS) == 0)
20405 int end_save = info->altivec_save_offset + info->altivec_size;
20407 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20408 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20410 if (end_save + frame_off != 0)
20412 rtx offset = GEN_INT (end_save + frame_off);
20414 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20417 emit_move_insn (ptr_reg, frame_reg_rtx);
20419 ptr_off = -end_save;
20420 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20421 info->altivec_save_offset + ptr_off,
20422 0, V4SImode, SAVRES_VR);
20426 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20427 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20429 rtx addr, areg, mem, reg;
20431 areg = gen_rtx_REG (Pmode, 0);
20433 (areg, GEN_INT (info->altivec_save_offset
20435 + 16 * (i - info->first_altivec_reg_save)));
20437 /* AltiVec addressing mode is [reg+reg]. */
20438 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20439 mem = gen_frame_mem (V4SImode, addr);
20441 reg = gen_rtx_REG (V4SImode, i);
20442 emit_move_insn (reg, mem);
20446 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20447 if (((strategy & REST_INLINE_VRS) == 0
20448 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20449 && (flag_shrink_wrap
20450 || (offset_below_red_zone_p
20451 (info->altivec_save_offset
20452 + 16 * (i - info->first_altivec_reg_save)))))
20454 rtx reg = gen_rtx_REG (V4SImode, i);
20455 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20459 /* Restore VRSAVE if we must do so before adjusting the stack. */
20461 && TARGET_ALTIVEC_VRSAVE
20462 && info->vrsave_mask != 0
20463 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20464 || (DEFAULT_ABI != ABI_V4
20465 && offset_below_red_zone_p (info->vrsave_save_offset))))
20469 if (frame_reg_rtx == sp_reg_rtx)
20471 if (use_backchain_to_restore_sp)
20473 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20474 emit_move_insn (frame_reg_rtx,
20475 gen_rtx_MEM (Pmode, sp_reg_rtx));
20478 else if (frame_pointer_needed)
20479 frame_reg_rtx = hard_frame_pointer_rtx;
20482 reg = gen_rtx_REG (SImode, 12);
20483 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20484 info->vrsave_save_offset + frame_off));
20486 emit_insn (generate_set_vrsave (reg, info, 1));
20490 /* If we have a large stack frame, restore the old stack pointer
20491 using the backchain. */
20492 if (use_backchain_to_restore_sp)
20494 if (frame_reg_rtx == sp_reg_rtx)
20496 /* Under V.4, don't reset the stack pointer until after we're done
20497 loading the saved registers. */
20498 if (DEFAULT_ABI == ABI_V4)
20499 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20501 insn = emit_move_insn (frame_reg_rtx,
20502 gen_rtx_MEM (Pmode, sp_reg_rtx));
20505 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20506 && DEFAULT_ABI == ABI_V4)
20507 /* frame_reg_rtx has been set up by the altivec restore. */
20511 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20512 frame_reg_rtx = sp_reg_rtx;
20515 /* If we have a frame pointer, we can restore the old stack pointer
20517 else if (frame_pointer_needed)
20519 frame_reg_rtx = sp_reg_rtx;
20520 if (DEFAULT_ABI == ABI_V4)
20521 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20522 /* Prevent reordering memory accesses against stack pointer restore. */
20523 else if (cfun->calls_alloca
20524 || offset_below_red_zone_p (-info->total_size))
20525 rs6000_emit_stack_tie (frame_reg_rtx, true);
20527 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20528 GEN_INT (info->total_size)));
20531 else if (info->push_p
20532 && DEFAULT_ABI != ABI_V4
20533 && !crtl->calls_eh_return)
20535 /* Prevent reordering memory accesses against stack pointer restore. */
20536 if (cfun->calls_alloca
20537 || offset_below_red_zone_p (-info->total_size))
20538 rs6000_emit_stack_tie (frame_reg_rtx, false);
20539 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20540 GEN_INT (info->total_size)));
20543 if (insn && frame_reg_rtx == sp_reg_rtx)
20547 REG_NOTES (insn) = cfa_restores;
20548 cfa_restores = NULL_RTX;
20550 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20551 RTX_FRAME_RELATED_P (insn) = 1;
20554 /* Restore AltiVec registers if we have not done so already. */
20555 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20556 && TARGET_ALTIVEC_ABI
20557 && info->altivec_size != 0
20558 && (DEFAULT_ABI == ABI_V4
20559 || !offset_below_red_zone_p (info->altivec_save_offset)))
20563 if ((strategy & REST_INLINE_VRS) == 0)
20565 int end_save = info->altivec_save_offset + info->altivec_size;
20567 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20568 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20569 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20571 if (end_save + frame_off != 0)
20573 rtx offset = GEN_INT (end_save + frame_off);
20575 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20578 emit_move_insn (ptr_reg, frame_reg_rtx);
20580 ptr_off = -end_save;
20581 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20582 info->altivec_save_offset + ptr_off,
20583 0, V4SImode, SAVRES_VR);
20584 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20586 /* Frame reg was clobbered by out-of-line save. Restore it
20587 from ptr_reg, and if we are calling out-of-line gpr or
20588 fpr restore set up the correct pointer and offset. */
20589 unsigned newptr_regno = 1;
20590 if (!restoring_GPRs_inline)
20592 bool lr = info->gp_save_offset + info->gp_size == 0;
20593 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
20594 newptr_regno = ptr_regno_for_savres (sel);
20595 end_save = info->gp_save_offset + info->gp_size;
20597 else if (!restoring_FPRs_inline)
20599 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
20600 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20601 newptr_regno = ptr_regno_for_savres (sel);
20602 end_save = info->gp_save_offset + info->gp_size;
20605 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
20606 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
20608 if (end_save + ptr_off != 0)
20610 rtx offset = GEN_INT (end_save + ptr_off);
20612 frame_off = -end_save;
20613 emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
20617 frame_off = ptr_off;
20618 emit_move_insn (frame_reg_rtx, ptr_reg);
20624 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20625 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20627 rtx addr, areg, mem, reg;
20629 areg = gen_rtx_REG (Pmode, 0);
20631 (areg, GEN_INT (info->altivec_save_offset
20633 + 16 * (i - info->first_altivec_reg_save)));
20635 /* AltiVec addressing mode is [reg+reg]. */
20636 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20637 mem = gen_frame_mem (V4SImode, addr);
20639 reg = gen_rtx_REG (V4SImode, i);
20640 emit_move_insn (reg, mem);
20644 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20645 if (((strategy & REST_INLINE_VRS) == 0
20646 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20647 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20649 rtx reg = gen_rtx_REG (V4SImode, i);
20650 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20654 /* Restore VRSAVE if we have not done so already. */
20655 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20657 && TARGET_ALTIVEC_VRSAVE
20658 && info->vrsave_mask != 0
20659 && (DEFAULT_ABI == ABI_V4
20660 || !offset_below_red_zone_p (info->vrsave_save_offset)))
20664 reg = gen_rtx_REG (SImode, 12);
20665 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20666 info->vrsave_save_offset + frame_off));
20668 emit_insn (generate_set_vrsave (reg, info, 1));
20671 /* If we exit by an out-of-line restore function on ABI_V4 then that
20672 function will deallocate the stack, so we don't need to worry
20673 about the unwinder restoring cr from an invalid stack frame
20675 exit_func = (!restoring_FPRs_inline
20676 || (!restoring_GPRs_inline
20677 && info->first_fp_reg_save == 64));
20679 /* Get the old lr if we saved it. If we are restoring registers
20680 out-of-line, then the out-of-line routines can do this for us. */
20681 if (restore_lr && restoring_GPRs_inline)
20682 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
20684 /* Get the old cr if we saved it. */
20685 if (info->cr_save_p)
20687 unsigned cr_save_regno = 12;
20689 if (!restoring_GPRs_inline)
20691 /* Ensure we don't use the register used by the out-of-line
20692 gpr register restore below. */
20693 bool lr = info->gp_save_offset + info->gp_size == 0;
20694 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
20695 int gpr_ptr_regno = ptr_regno_for_savres (sel);
20697 if (gpr_ptr_regno == 12)
20698 cr_save_regno = 11;
20699 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
20701 else if (REGNO (frame_reg_rtx) == 12)
20702 cr_save_regno = 11;
20704 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
20705 info->cr_save_offset + frame_off,
20709 /* Set LR here to try to overlap restores below. */
20710 if (restore_lr && restoring_GPRs_inline)
20711 restore_saved_lr (0, exit_func);
20713 /* Load exception handler data registers, if needed. */
20714 if (crtl->calls_eh_return)
20716 unsigned int i, regno;
20720 rtx reg = gen_rtx_REG (reg_mode, 2);
20721 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20722 frame_off + 5 * reg_size));
20729 regno = EH_RETURN_DATA_REGNO (i);
20730 if (regno == INVALID_REGNUM)
20733 /* Note: possible use of r0 here to address SPE regs. */
20734 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
20735 info->ehrd_offset + frame_off
20736 + reg_size * (int) i);
20738 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
20742 /* Restore GPRs. This is done as a PARALLEL if we are using
20743 the load-multiple instructions. */
20745 && info->spe_64bit_regs_used
20746 && info->first_gp_reg_save != 32)
20748 /* Determine whether we can address all of the registers that need
20749 to be saved with an offset from frame_reg_rtx that fits in
20750 the small const field for SPE memory instructions. */
20751 int spe_regs_addressable
20752 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
20753 + reg_size * (32 - info->first_gp_reg_save - 1))
20754 && restoring_GPRs_inline);
20756 if (!spe_regs_addressable)
20758 int ool_adjust = 0;
20759 rtx old_frame_reg_rtx = frame_reg_rtx;
20760 /* Make r11 point to the start of the SPE save area. We worried about
20761 not clobbering it when we were saving registers in the prologue.
20762 There's no need to worry here because the static chain is passed
20763 anew to every function. */
20765 if (!restoring_GPRs_inline)
20766 ool_adjust = 8 * (info->first_gp_reg_save
20767 - (FIRST_SAVRES_REGISTER + 1));
20768 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20769 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
20770 GEN_INT (info->spe_gp_save_offset
20773 /* Keep the invariant that frame_reg_rtx + frame_off points
20774 at the top of the stack frame. */
20775 frame_off = -info->spe_gp_save_offset + ool_adjust;
20778 if (restoring_GPRs_inline)
20780 HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
20782 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20783 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20785 rtx offset, addr, mem, reg;
20787 /* We're doing all this to ensure that the immediate offset
20788 fits into the immediate field of 'evldd'. */
20789 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
20791 offset = GEN_INT (spe_offset + reg_size * i);
20792 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
20793 mem = gen_rtx_MEM (V2SImode, addr);
20794 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20796 emit_move_insn (reg, mem);
20800 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20801 info->spe_gp_save_offset + frame_off,
20802 info->lr_save_offset + frame_off,
20804 SAVRES_GPR | SAVRES_LR);
20806 else if (!restoring_GPRs_inline)
20808 /* We are jumping to an out-of-line function. */
20810 int end_save = info->gp_save_offset + info->gp_size;
20811 bool can_use_exit = end_save == 0;
20812 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
20815 /* Emit stack reset code if we need it. */
20816 ptr_regno = ptr_regno_for_savres (sel);
20817 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
20819 rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
20820 else if (end_save + frame_off != 0)
20821 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
20822 GEN_INT (end_save + frame_off)));
20823 else if (REGNO (frame_reg_rtx) != ptr_regno)
20824 emit_move_insn (ptr_reg, frame_reg_rtx);
20825 if (REGNO (frame_reg_rtx) == ptr_regno)
20826 frame_off = -end_save;
20828 if (can_use_exit && info->cr_save_p)
20829 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
20831 ptr_off = -end_save;
20832 rs6000_emit_savres_rtx (info, ptr_reg,
20833 info->gp_save_offset + ptr_off,
20834 info->lr_save_offset + ptr_off,
20837 else if (using_load_multiple)
20840 p = rtvec_alloc (32 - info->first_gp_reg_save);
20841 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20843 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
20845 info->gp_save_offset + frame_off + reg_size * i);
20846 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20850 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20851 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20852 emit_insn (gen_frame_load
20853 (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
20855 info->gp_save_offset + frame_off + reg_size * i));
20858 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20860 /* If the frame pointer was used then we can't delay emitting
20861 a REG_CFA_DEF_CFA note. This must happen on the insn that
20862 restores the frame pointer, r31. We may have already emitted
20863 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
20864 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
20865 be harmless if emitted. */
20866 if (frame_pointer_needed)
20868 insn = get_last_insn ();
20869 add_reg_note (insn, REG_CFA_DEF_CFA,
20870 plus_constant (Pmode, frame_reg_rtx, frame_off));
20871 RTX_FRAME_RELATED_P (insn) = 1;
20874 /* Set up cfa_restores. We always need these when
20875 shrink-wrapping. If not shrink-wrapping then we only need
20876 the cfa_restore when the stack location is no longer valid.
20877 The cfa_restores must be emitted on or before the insn that
20878 invalidates the stack, and of course must not be emitted
20879 before the insn that actually does the restore. The latter
20880 is why it is a bad idea to emit the cfa_restores as a group
20881 on the last instruction here that actually does a restore:
20882 That insn may be reordered with respect to others doing
20884 if (flag_shrink_wrap
20885 && !restoring_GPRs_inline
20886 && info->first_fp_reg_save == 64)
20887 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
20889 for (i = info->first_gp_reg_save; i < 32; i++)
20890 if (!restoring_GPRs_inline
20891 || using_load_multiple
20892 || rs6000_reg_live_or_pic_offset_p (i))
20894 rtx reg = gen_rtx_REG (reg_mode, i);
20896 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20900 if (!restoring_GPRs_inline
20901 && info->first_fp_reg_save == 64)
20903 /* We are jumping to an out-of-line function. */
20905 emit_cfa_restores (cfa_restores);
20909 if (restore_lr && !restoring_GPRs_inline)
20911 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
20912 restore_saved_lr (0, exit_func);
20915 /* Restore fpr's if we need to do it without calling a function. */
20916 if (restoring_FPRs_inline)
20917 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20918 if (save_reg_p (info->first_fp_reg_save + i))
20920 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
20921 ? DFmode : SFmode),
20922 info->first_fp_reg_save + i);
20923 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20924 info->fp_save_offset + frame_off + 8 * i));
20925 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20926 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20929 /* If we saved cr, restore it here. Just those that were used. */
20930 if (info->cr_save_p)
20931 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
20933 /* If this is V.4, unwind the stack pointer after all of the loads
20934 have been done, or set up r11 if we are restoring fp out of line. */
20936 if (!restoring_FPRs_inline)
20938 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20939 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20940 ptr_regno = ptr_regno_for_savres (sel);
20943 insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
20944 if (REGNO (frame_reg_rtx) == ptr_regno)
20947 if (insn && restoring_FPRs_inline)
20951 REG_NOTES (insn) = cfa_restores;
20952 cfa_restores = NULL_RTX;
20954 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20955 RTX_FRAME_RELATED_P (insn) = 1;
20958 if (crtl->calls_eh_return)
20960 rtx sa = EH_RETURN_STACKADJ_RTX;
20961 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
20967 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20968 if (! restoring_FPRs_inline)
20970 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
20971 RTVEC_ELT (p, 0) = ret_rtx;
20977 /* We can't hang the cfa_restores off a simple return,
20978 since the shrink-wrap code sometimes uses an existing
20979 return. This means there might be a path from
20980 pre-prologue code to this return, and dwarf2cfi code
20981 wants the eh_frame unwinder state to be the same on
20982 all paths to any point. So we need to emit the
20983 cfa_restores before the return. For -m64 we really
20984 don't need epilogue cfa_restores at all, except for
20985 this irritating dwarf2cfi with shrink-wrap
20986 requirement; The stack red-zone means eh_frame info
20987 from the prologue telling the unwinder to restore
20988 from the stack is perfectly good right to the end of
20990 emit_insn (gen_blockage ());
20991 emit_cfa_restores (cfa_restores);
20992 cfa_restores = NULL_RTX;
20994 p = rtvec_alloc (2);
20995 RTVEC_ELT (p, 0) = simple_return_rtx;
20998 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
20999 ? gen_rtx_USE (VOIDmode,
21000 gen_rtx_REG (Pmode, LR_REGNO))
21001 : gen_rtx_CLOBBER (VOIDmode,
21002 gen_rtx_REG (Pmode, LR_REGNO)));
21004 /* If we have to restore more than two FP registers, branch to the
21005 restore function. It will return to our caller. */
21006 if (! restoring_FPRs_inline)
21011 if (flag_shrink_wrap)
21012 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21014 sym = rs6000_savres_routine_sym (info,
21015 SAVRES_FPR | (lr ? SAVRES_LR : 0));
21016 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
21017 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
21018 gen_rtx_REG (Pmode,
21019 DEFAULT_ABI == ABI_AIX
21021 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21023 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
21025 RTVEC_ELT (p, i + 4)
21026 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
21027 if (flag_shrink_wrap)
21028 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
21033 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
21039 /* Ensure the cfa_restores are hung off an insn that won't
21040 be reordered above other restores. */
21041 emit_insn (gen_blockage ());
21043 emit_cfa_restores (cfa_restores);
21047 /* Write function epilogue. */
21050 rs6000_output_function_epilogue (FILE *file,
21051 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
21054 macho_branch_islands ();
21055 /* Mach-O doesn't support labels at the end of objects, so if
21056 it looks like we might want one, insert a NOP. */
21058 rtx insn = get_last_insn ();
21059 rtx deleted_debug_label = NULL_RTX;
21062 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
21064 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21065 notes only, instead set their CODE_LABEL_NUMBER to -1,
21066 otherwise there would be code generation differences
21067 in between -g and -g0. */
21068 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21069 deleted_debug_label = insn;
21070 insn = PREV_INSN (insn);
21075 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
21076 fputs ("\tnop\n", file);
21077 else if (deleted_debug_label)
21078 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
21079 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21080 CODE_LABEL_NUMBER (insn) = -1;
21084 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21087 We don't output a traceback table if -finhibit-size-directive was
21088 used. The documentation for -finhibit-size-directive reads
21089 ``don't output a @code{.size} assembler directive, or anything
21090 else that would cause trouble if the function is split in the
21091 middle, and the two halves are placed at locations far apart in
21092 memory.'' The traceback table has this property, since it
21093 includes the offset from the start of the function to the
21094 traceback table itself.
21096 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21097 different traceback table. */
21098 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
21099 && rs6000_traceback != traceback_none && !cfun->is_thunk)
21101 const char *fname = NULL;
21102 const char *language_string = lang_hooks.name;
21103 int fixed_parms = 0, float_parms = 0, parm_info = 0;
21105 int optional_tbtab;
21106 rs6000_stack_t *info = rs6000_stack_info ();
21108 if (rs6000_traceback == traceback_full)
21109 optional_tbtab = 1;
21110 else if (rs6000_traceback == traceback_part)
21111 optional_tbtab = 0;
21113 optional_tbtab = !optimize_size && !TARGET_ELF;
21115 if (optional_tbtab)
21117 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
21118 while (*fname == '.') /* V.4 encodes . in the name */
21121 /* Need label immediately before tbtab, so we can compute
21122 its offset from the function start. */
21123 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21124 ASM_OUTPUT_LABEL (file, fname);
21127 /* The .tbtab pseudo-op can only be used for the first eight
21128 expressions, since it can't handle the possibly variable
21129 length fields that follow. However, if you omit the optional
21130 fields, the assembler outputs zeros for all optional fields
21131 anyways, giving each variable length field is minimum length
21132 (as defined in sys/debug.h). Thus we can not use the .tbtab
21133 pseudo-op at all. */
21135 /* An all-zero word flags the start of the tbtab, for debuggers
21136 that have to find it by searching forward from the entry
21137 point or from the current pc. */
21138 fputs ("\t.long 0\n", file);
21140 /* Tbtab format type. Use format type 0. */
21141 fputs ("\t.byte 0,", file);
21143 /* Language type. Unfortunately, there does not seem to be any
21144 official way to discover the language being compiled, so we
21145 use language_string.
21146 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21147 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21148 a number, so for now use 9. LTO and Go aren't assigned numbers
21149 either, so for now use 0. */
21150 if (! strcmp (language_string, "GNU C")
21151 || ! strcmp (language_string, "GNU GIMPLE")
21152 || ! strcmp (language_string, "GNU Go"))
21154 else if (! strcmp (language_string, "GNU F77")
21155 || ! strcmp (language_string, "GNU Fortran"))
21157 else if (! strcmp (language_string, "GNU Pascal"))
21159 else if (! strcmp (language_string, "GNU Ada"))
21161 else if (! strcmp (language_string, "GNU C++")
21162 || ! strcmp (language_string, "GNU Objective-C++"))
21164 else if (! strcmp (language_string, "GNU Java"))
21166 else if (! strcmp (language_string, "GNU Objective-C"))
21169 gcc_unreachable ();
21170 fprintf (file, "%d,", i);
21172 /* 8 single bit fields: global linkage (not set for C extern linkage,
21173 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21174 from start of procedure stored in tbtab, internal function, function
21175 has controlled storage, function has no toc, function uses fp,
21176 function logs/aborts fp operations. */
21177 /* Assume that fp operations are used if any fp reg must be saved. */
21178 fprintf (file, "%d,",
21179 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21181 /* 6 bitfields: function is interrupt handler, name present in
21182 proc table, function calls alloca, on condition directives
21183 (controls stack walks, 3 bits), saves condition reg, saves
21185 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21186 set up as a frame pointer, even when there is no alloca call. */
21187 fprintf (file, "%d,",
21188 ((optional_tbtab << 6)
21189 | ((optional_tbtab & frame_pointer_needed) << 5)
21190 | (info->cr_save_p << 1)
21191 | (info->lr_save_p)));
21193 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21195 fprintf (file, "%d,",
21196 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21198 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21199 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21201 if (optional_tbtab)
21203 /* Compute the parameter info from the function decl argument
21206 int next_parm_info_bit = 31;
21208 for (decl = DECL_ARGUMENTS (current_function_decl);
21209 decl; decl = DECL_CHAIN (decl))
21211 rtx parameter = DECL_INCOMING_RTL (decl);
21212 enum machine_mode mode = GET_MODE (parameter);
21214 if (GET_CODE (parameter) == REG)
21216 if (SCALAR_FLOAT_MODE_P (mode))
21237 gcc_unreachable ();
21240 /* If only one bit will fit, don't or in this entry. */
21241 if (next_parm_info_bit > 0)
21242 parm_info |= (bits << (next_parm_info_bit - 1));
21243 next_parm_info_bit -= 2;
21247 fixed_parms += ((GET_MODE_SIZE (mode)
21248 + (UNITS_PER_WORD - 1))
21250 next_parm_info_bit -= 1;
21256 /* Number of fixed point parameters. */
21257 /* This is actually the number of words of fixed point parameters; thus
21258 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21259 fprintf (file, "%d,", fixed_parms);
21261 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21263 /* This is actually the number of fp registers that hold parameters;
21264 and thus the maximum value is 13. */
21265 /* Set parameters on stack bit if parameters are not in their original
21266 registers, regardless of whether they are on the stack? Xlc
21267 seems to set the bit when not optimizing. */
21268 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21270 if (! optional_tbtab)
21273 /* Optional fields follow. Some are variable length. */
21275 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21276 11 double float. */
21277 /* There is an entry for each parameter in a register, in the order that
21278 they occur in the parameter list. Any intervening arguments on the
21279 stack are ignored. If the list overflows a long (max possible length
21280 34 bits) then completely leave off all elements that don't fit. */
21281 /* Only emit this long if there was at least one parameter. */
21282 if (fixed_parms || float_parms)
21283 fprintf (file, "\t.long %d\n", parm_info);
21285 /* Offset from start of code to tb table. */
21286 fputs ("\t.long ", file);
21287 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21288 RS6000_OUTPUT_BASENAME (file, fname);
21290 rs6000_output_function_entry (file, fname);
21293 /* Interrupt handler mask. */
21294 /* Omit this long, since we never set the interrupt handler bit
21297 /* Number of CTL (controlled storage) anchors. */
21298 /* Omit this long, since the has_ctl bit is never set above. */
21300 /* Displacement into stack of each CTL anchor. */
21301 /* Omit this list of longs, because there are no CTL anchors. */
21303 /* Length of function name. */
21306 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21308 /* Function name. */
21309 assemble_string (fname, strlen (fname));
21311 /* Register for alloca automatic storage; this is always reg 31.
21312 Only emit this if the alloca bit was set above. */
21313 if (frame_pointer_needed)
21314 fputs ("\t.byte 31\n", file);
21316 fputs ("\t.align 2\n", file);
21320 /* A C compound statement that outputs the assembler code for a thunk
21321 function, used to implement C++ virtual function calls with
21322 multiple inheritance. The thunk acts as a wrapper around a virtual
21323 function, adjusting the implicit object parameter before handing
21324 control off to the real function.
21326 First, emit code to add the integer DELTA to the location that
21327 contains the incoming first argument. Assume that this argument
21328 contains a pointer, and is the one used to pass the `this' pointer
21329 in C++. This is the incoming argument *before* the function
21330 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21331 values of all other incoming arguments.
21333 After the addition, emit code to jump to FUNCTION, which is a
21334 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21335 not touch the return address. Hence returning from FUNCTION will
21336 return to whoever called the current `thunk'.
21338 The effect must be as if FUNCTION had been called directly with the
21339 adjusted first argument. This macro is responsible for emitting
21340 all of the code for a thunk function; output_function_prologue()
21341 and output_function_epilogue() are not invoked.
21343 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21344 been extracted from it.) It might possibly be useful on some
21345 targets, but probably not.
21347 If you do not define this macro, the target-independent code in the
21348 C++ frontend will generate a less efficient heavyweight thunk that
21349 calls FUNCTION instead of jumping to it. The generic approach does
21350 not support varargs. */
21353 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21354 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21357 rtx this_rtx, insn, funexp;
21359 reload_completed = 1;
21360 epilogue_completed = 1;
21362 /* Mark the end of the (empty) prologue. */
21363 emit_note (NOTE_INSN_PROLOGUE_END);
21365 /* Find the "this" pointer. If the function returns a structure,
21366 the structure return pointer is in r3. */
21367 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21368 this_rtx = gen_rtx_REG (Pmode, 4);
21370 this_rtx = gen_rtx_REG (Pmode, 3);
21372 /* Apply the constant offset, if required. */
21374 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21376 /* Apply the offset from the vtable, if required. */
21379 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21380 rtx tmp = gen_rtx_REG (Pmode, 12);
21382 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21383 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21385 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21386 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21390 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21392 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21394 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21397 /* Generate a tail call to the target function. */
21398 if (!TREE_USED (function))
21400 assemble_external (function);
21401 TREE_USED (function) = 1;
21403 funexp = XEXP (DECL_RTL (function), 0);
21404 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21407 if (MACHOPIC_INDIRECT)
21408 funexp = machopic_indirect_call_target (funexp);
21411 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21412 generate sibcall RTL explicitly. */
21413 insn = emit_call_insn (
21414 gen_rtx_PARALLEL (VOIDmode,
21416 gen_rtx_CALL (VOIDmode,
21417 funexp, const0_rtx),
21418 gen_rtx_USE (VOIDmode, const0_rtx),
21419 gen_rtx_USE (VOIDmode,
21420 gen_rtx_REG (SImode,
21422 simple_return_rtx)));
21423 SIBLING_CALL_P (insn) = 1;
21426 /* Run just enough of rest_of_compilation to get the insns emitted.
21427 There's not really enough bulk here to make other passes such as
21428 instruction scheduling worth while. Note that use_thunk calls
21429 assemble_start_function and assemble_end_function. */
21430 insn = get_insns ();
21431 insn_locators_alloc ();
21432 shorten_branches (insn);
21433 final_start_function (insn, file, 1);
21434 final (insn, file, 1);
21435 final_end_function ();
21437 reload_completed = 0;
21438 epilogue_completed = 0;
21441 /* A quick summary of the various types of 'constant-pool tables'
21444 Target Flags Name One table per
21445 AIX (none) AIX TOC object file
21446 AIX -mfull-toc AIX TOC object file
21447 AIX -mminimal-toc AIX minimal TOC translation unit
21448 SVR4/EABI (none) SVR4 SDATA object file
21449 SVR4/EABI -fpic SVR4 pic object file
21450 SVR4/EABI -fPIC SVR4 PIC translation unit
21451 SVR4/EABI -mrelocatable EABI TOC function
21452 SVR4/EABI -maix AIX TOC object file
21453 SVR4/EABI -maix -mminimal-toc
21454 AIX minimal TOC translation unit
21456 Name Reg. Set by entries contains:
21457 made by addrs? fp? sum?
21459 AIX TOC 2 crt0 as Y option option
21460 AIX minimal TOC 30 prolog gcc Y Y option
21461 SVR4 SDATA 13 crt0 gcc N Y N
21462 SVR4 pic 30 prolog ld Y not yet N
21463 SVR4 PIC 30 prolog gcc Y option option
21464 EABI TOC 30 prolog gcc Y option option
21468 /* Hash functions for the hash table. */
21471 rs6000_hash_constant (rtx k)
21473 enum rtx_code code = GET_CODE (k);
21474 enum machine_mode mode = GET_MODE (k);
21475 unsigned result = (code << 3) ^ mode;
21476 const char *format;
21479 format = GET_RTX_FORMAT (code);
21480 flen = strlen (format);
21486 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21489 if (mode != VOIDmode)
21490 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21502 for (; fidx < flen; fidx++)
21503 switch (format[fidx])
21508 const char *str = XSTR (k, fidx);
21509 len = strlen (str);
21510 result = result * 613 + len;
21511 for (i = 0; i < len; i++)
21512 result = result * 613 + (unsigned) str[i];
21517 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21521 result = result * 613 + (unsigned) XINT (k, fidx);
21524 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21525 result = result * 613 + (unsigned) XWINT (k, fidx);
21529 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21530 result = result * 613 + (unsigned) (XWINT (k, fidx)
21537 gcc_unreachable ();
21544 toc_hash_function (const void *hash_entry)
21546 const struct toc_hash_struct *thc =
21547 (const struct toc_hash_struct *) hash_entry;
21548 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21551 /* Compare H1 and H2 for equivalence. */
21554 toc_hash_eq (const void *h1, const void *h2)
21556 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21557 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21559 if (((const struct toc_hash_struct *) h1)->key_mode
21560 != ((const struct toc_hash_struct *) h2)->key_mode)
21563 return rtx_equal_p (r1, r2);
21566 /* These are the names given by the C++ front-end to vtables, and
21567 vtable-like objects. Ideally, this logic should not be here;
21568 instead, there should be some programmatic way of inquiring as
21569 to whether or not an object is a vtable. */
21571 #define VTABLE_NAME_P(NAME) \
21572 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21573 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21574 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21575 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21576 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21578 #ifdef NO_DOLLAR_IN_LABEL
21579 /* Return a GGC-allocated character string translating dollar signs in
21580 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21583 rs6000_xcoff_strip_dollar (const char *name)
21589 q = (const char *) strchr (name, '$');
21591 if (q == 0 || q == name)
21594 len = strlen (name);
21595 strip = XALLOCAVEC (char, len + 1);
21596 strcpy (strip, name);
21597 p = strip + (q - name);
21601 p = strchr (p + 1, '$');
21604 return ggc_alloc_string (strip, len);
21609 rs6000_output_symbol_ref (FILE *file, rtx x)
21611 /* Currently C++ toc references to vtables can be emitted before it
21612 is decided whether the vtable is public or private. If this is
21613 the case, then the linker will eventually complain that there is
21614 a reference to an unknown section. Thus, for vtables only,
21615 we emit the TOC reference to reference the symbol and not the
21617 const char *name = XSTR (x, 0);
21619 if (VTABLE_NAME_P (name))
21621 RS6000_OUTPUT_BASENAME (file, name);
21624 assemble_name (file, name);
21627 /* Output a TOC entry. We derive the entry name from what is being
21631 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
21634 const char *name = buf;
21636 HOST_WIDE_INT offset = 0;
21638 gcc_assert (!TARGET_NO_TOC);
21640 /* When the linker won't eliminate them, don't output duplicate
21641 TOC entries (this happens on AIX if there is any kind of TOC,
21642 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21644 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
21646 struct toc_hash_struct *h;
21649 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21650 time because GGC is not initialized at that point. */
21651 if (toc_hash_table == NULL)
21652 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
21653 toc_hash_eq, NULL);
21655 h = ggc_alloc_toc_hash_struct ();
21657 h->key_mode = mode;
21658 h->labelno = labelno;
21660 found = htab_find_slot (toc_hash_table, h, INSERT);
21661 if (*found == NULL)
21663 else /* This is indeed a duplicate.
21664 Set this label equal to that label. */
21666 fputs ("\t.set ", file);
21667 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21668 fprintf (file, "%d,", labelno);
21669 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21670 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
21676 /* If we're going to put a double constant in the TOC, make sure it's
21677 aligned properly when strict alignment is on. */
21678 if (GET_CODE (x) == CONST_DOUBLE
21679 && STRICT_ALIGNMENT
21680 && GET_MODE_BITSIZE (mode) >= 64
21681 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
21682 ASM_OUTPUT_ALIGN (file, 3);
21685 (*targetm.asm_out.internal_label) (file, "LC", labelno);
21687 /* Handle FP constants specially. Note that if we have a minimal
21688 TOC, things we put here aren't actually in the TOC, so we can allow
21690 if (GET_CODE (x) == CONST_DOUBLE &&
21691 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
21693 REAL_VALUE_TYPE rv;
21696 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21697 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21698 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
21700 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
21704 if (TARGET_MINIMAL_TOC)
21705 fputs (DOUBLE_INT_ASM_OP, file);
21707 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21708 k[0] & 0xffffffff, k[1] & 0xffffffff,
21709 k[2] & 0xffffffff, k[3] & 0xffffffff);
21710 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
21711 k[0] & 0xffffffff, k[1] & 0xffffffff,
21712 k[2] & 0xffffffff, k[3] & 0xffffffff);
21717 if (TARGET_MINIMAL_TOC)
21718 fputs ("\t.long ", file);
21720 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21721 k[0] & 0xffffffff, k[1] & 0xffffffff,
21722 k[2] & 0xffffffff, k[3] & 0xffffffff);
21723 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21724 k[0] & 0xffffffff, k[1] & 0xffffffff,
21725 k[2] & 0xffffffff, k[3] & 0xffffffff);
21729 else if (GET_CODE (x) == CONST_DOUBLE &&
21730 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
21732 REAL_VALUE_TYPE rv;
21735 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21737 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21738 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
21740 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
21744 if (TARGET_MINIMAL_TOC)
21745 fputs (DOUBLE_INT_ASM_OP, file);
21747 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21748 k[0] & 0xffffffff, k[1] & 0xffffffff);
21749 fprintf (file, "0x%lx%08lx\n",
21750 k[0] & 0xffffffff, k[1] & 0xffffffff);
21755 if (TARGET_MINIMAL_TOC)
21756 fputs ("\t.long ", file);
21758 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21759 k[0] & 0xffffffff, k[1] & 0xffffffff);
21760 fprintf (file, "0x%lx,0x%lx\n",
21761 k[0] & 0xffffffff, k[1] & 0xffffffff);
21765 else if (GET_CODE (x) == CONST_DOUBLE &&
21766 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
21768 REAL_VALUE_TYPE rv;
21771 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21772 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21773 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
21775 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
21779 if (TARGET_MINIMAL_TOC)
21780 fputs (DOUBLE_INT_ASM_OP, file);
21782 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21783 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
21788 if (TARGET_MINIMAL_TOC)
21789 fputs ("\t.long ", file);
21791 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21792 fprintf (file, "0x%lx\n", l & 0xffffffff);
21796 else if (GET_MODE (x) == VOIDmode
21797 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
21799 unsigned HOST_WIDE_INT low;
21800 HOST_WIDE_INT high;
21802 if (GET_CODE (x) == CONST_DOUBLE)
21804 low = CONST_DOUBLE_LOW (x);
21805 high = CONST_DOUBLE_HIGH (x);
21808 #if HOST_BITS_PER_WIDE_INT == 32
21811 high = (low & 0x80000000) ? ~0 : 0;
21815 low = INTVAL (x) & 0xffffffff;
21816 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
21820 /* TOC entries are always Pmode-sized, but since this
21821 is a bigendian machine then if we're putting smaller
21822 integer constants in the TOC we have to pad them.
21823 (This is still a win over putting the constants in
21824 a separate constant pool, because then we'd have
21825 to have both a TOC entry _and_ the actual constant.)
21827 For a 32-bit target, CONST_INT values are loaded and shifted
21828 entirely within `low' and can be stored in one TOC entry. */
21830 /* It would be easy to make this work, but it doesn't now. */
21831 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
21833 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
21835 #if HOST_BITS_PER_WIDE_INT == 32
21836 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
21837 POINTER_SIZE, &low, &high, 0);
21840 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
21841 high = (HOST_WIDE_INT) low >> 32;
21848 if (TARGET_MINIMAL_TOC)
21849 fputs (DOUBLE_INT_ASM_OP, file);
21851 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21852 (long) high & 0xffffffff, (long) low & 0xffffffff);
21853 fprintf (file, "0x%lx%08lx\n",
21854 (long) high & 0xffffffff, (long) low & 0xffffffff);
21859 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
21861 if (TARGET_MINIMAL_TOC)
21862 fputs ("\t.long ", file);
21864 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21865 (long) high & 0xffffffff, (long) low & 0xffffffff);
21866 fprintf (file, "0x%lx,0x%lx\n",
21867 (long) high & 0xffffffff, (long) low & 0xffffffff);
21871 if (TARGET_MINIMAL_TOC)
21872 fputs ("\t.long ", file);
21874 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
21875 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
21881 if (GET_CODE (x) == CONST)
21883 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
21884 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
21886 base = XEXP (XEXP (x, 0), 0);
21887 offset = INTVAL (XEXP (XEXP (x, 0), 1));
21890 switch (GET_CODE (base))
21893 name = XSTR (base, 0);
21897 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
21898 CODE_LABEL_NUMBER (XEXP (base, 0)));
21902 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
21906 gcc_unreachable ();
21909 if (TARGET_MINIMAL_TOC)
21910 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
21913 fputs ("\t.tc ", file);
21914 RS6000_OUTPUT_BASENAME (file, name);
21917 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
21919 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
21921 fputs ("[TC],", file);
21924 /* Currently C++ toc references to vtables can be emitted before it
21925 is decided whether the vtable is public or private. If this is
21926 the case, then the linker will eventually complain that there is
21927 a TOC reference to an unknown section. Thus, for vtables only,
21928 we emit the TOC reference to reference the symbol and not the
21930 if (VTABLE_NAME_P (name))
21932 RS6000_OUTPUT_BASENAME (file, name);
21934 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
21935 else if (offset > 0)
21936 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
21939 output_addr_const (file, x);
21943 /* Output an assembler pseudo-op to write an ASCII string of N characters
21944 starting at P to FILE.
21946 On the RS/6000, we have to do this using the .byte operation and
21947 write out special characters outside the quoted string.
21948 Also, the assembler is broken; very long strings are truncated,
21949 so we must artificially break them up early. */
21952 output_ascii (FILE *file, const char *p, int n)
21955 int i, count_string;
21956 const char *for_string = "\t.byte \"";
21957 const char *for_decimal = "\t.byte ";
21958 const char *to_close = NULL;
21961 for (i = 0; i < n; i++)
21964 if (c >= ' ' && c < 0177)
21967 fputs (for_string, file);
21970 /* Write two quotes to get one. */
21978 for_decimal = "\"\n\t.byte ";
21982 if (count_string >= 512)
21984 fputs (to_close, file);
21986 for_string = "\t.byte \"";
21987 for_decimal = "\t.byte ";
21995 fputs (for_decimal, file);
21996 fprintf (file, "%d", c);
21998 for_string = "\n\t.byte \"";
21999 for_decimal = ", ";
22005 /* Now close the string if we have written one. Then end the line. */
22007 fputs (to_close, file);
22010 /* Generate a unique section name for FILENAME for a section type
22011 represented by SECTION_DESC. Output goes into BUF.
22013 SECTION_DESC can be any string, as long as it is different for each
22014 possible section type.
22016 We name the section in the same manner as xlc. The name begins with an
22017 underscore followed by the filename (after stripping any leading directory
22018 names) with the last period replaced by the string SECTION_DESC. If
22019 FILENAME does not contain a period, SECTION_DESC is appended to the end of
22023 rs6000_gen_section_name (char **buf, const char *filename,
22024 const char *section_desc)
22026 const char *q, *after_last_slash, *last_period = 0;
22030 after_last_slash = filename;
22031 for (q = filename; *q; q++)
22034 after_last_slash = q + 1;
22035 else if (*q == '.')
22039 len = strlen (after_last_slash) + strlen (section_desc) + 2;
22040 *buf = (char *) xmalloc (len);
22045 for (q = after_last_slash; *q; q++)
22047 if (q == last_period)
22049 strcpy (p, section_desc);
22050 p += strlen (section_desc);
22054 else if (ISALNUM (*q))
22058 if (last_period == 0)
22059 strcpy (p, section_desc);
22064 /* Emit profile function. */
22067 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
22069 /* Non-standard profiling for kernels, which just saves LR then calls
22070 _mcount without worrying about arg saves. The idea is to change
22071 the function prologue as little as possible as it isn't easy to
22072 account for arg save/restore code added just for _mcount. */
22073 if (TARGET_PROFILE_KERNEL)
22076 if (DEFAULT_ABI == ABI_AIX)
22078 #ifndef NO_PROFILE_COUNTERS
22079 # define NO_PROFILE_COUNTERS 0
22081 if (NO_PROFILE_COUNTERS)
22082 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22083 LCT_NORMAL, VOIDmode, 0);
22087 const char *label_name;
22090 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22091 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
22092 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
22094 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22095 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
22098 else if (DEFAULT_ABI == ABI_DARWIN)
22100 const char *mcount_name = RS6000_MCOUNT;
22101 int caller_addr_regno = LR_REGNO;
22103 /* Be conservative and always set this, at least for now. */
22104 crtl->uses_pic_offset_table = 1;
22107 /* For PIC code, set up a stub and collect the caller's address
22108 from r0, which is where the prologue puts it. */
22109 if (MACHOPIC_INDIRECT
22110 && crtl->uses_pic_offset_table)
22111 caller_addr_regno = 0;
22113 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
22114 LCT_NORMAL, VOIDmode, 1,
22115 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
22119 /* Write function profiler code. */
22122 output_function_profiler (FILE *file, int labelno)
22126 switch (DEFAULT_ABI)
22129 gcc_unreachable ();
22134 warning (0, "no profiling of 64-bit code for this ABI");
22137 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22138 fprintf (file, "\tmflr %s\n", reg_names[0]);
22139 if (NO_PROFILE_COUNTERS)
22141 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22142 reg_names[0], reg_names[1]);
22144 else if (TARGET_SECURE_PLT && flag_pic)
22146 if (TARGET_LINK_STACK)
22149 get_ppc476_thunk_name (name);
22150 asm_fprintf (file, "\tbl %s\n", name);
22153 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22154 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22155 reg_names[0], reg_names[1]);
22156 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22157 asm_fprintf (file, "\t{cau|addis} %s,%s,",
22158 reg_names[12], reg_names[12]);
22159 assemble_name (file, buf);
22160 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
22161 assemble_name (file, buf);
22162 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22164 else if (flag_pic == 1)
22166 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22167 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22168 reg_names[0], reg_names[1]);
22169 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22170 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
22171 assemble_name (file, buf);
22172 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22174 else if (flag_pic > 1)
22176 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22177 reg_names[0], reg_names[1]);
22178 /* Now, we need to get the address of the label. */
22179 if (TARGET_LINK_STACK)
22182 get_ppc476_thunk_name (name);
22183 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22184 assemble_name (file, buf);
22185 fputs ("-.\n1:", file);
22186 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22187 asm_fprintf (file, "\taddi %s,%s,4\n",
22188 reg_names[11], reg_names[11]);
22192 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22193 assemble_name (file, buf);
22194 fputs ("-.\n1:", file);
22195 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22197 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
22198 reg_names[0], reg_names[11]);
22199 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
22200 reg_names[0], reg_names[0], reg_names[11]);
22204 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
22205 assemble_name (file, buf);
22206 fputs ("@ha\n", file);
22207 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22208 reg_names[0], reg_names[1]);
22209 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
22210 assemble_name (file, buf);
22211 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22214 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22215 fprintf (file, "\tbl %s%s\n",
22216 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22221 if (!TARGET_PROFILE_KERNEL)
22223 /* Don't do anything, done in output_profile_hook (). */
22227 gcc_assert (!TARGET_32BIT);
22229 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22230 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22232 if (cfun->static_chain_decl != NULL)
22234 asm_fprintf (file, "\tstd %s,24(%s)\n",
22235 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22236 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22237 asm_fprintf (file, "\tld %s,24(%s)\n",
22238 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22241 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22249 /* The following variable value is the last issued insn. */
22251 static rtx last_scheduled_insn;
22253 /* The following variable helps to balance issuing of load and
22254 store instructions */
22256 static int load_store_pendulum;
22258 /* Power4 load update and store update instructions are cracked into a
22259 load or store and an integer insn which are executed in the same cycle.
22260 Branches have their own dispatch slot which does not count against the
22261 GCC issue rate, but it changes the program flow so there are no other
22262 instructions to issue in this cycle. */
22265 rs6000_variable_issue_1 (rtx insn, int more)
22267 last_scheduled_insn = insn;
22268 if (GET_CODE (PATTERN (insn)) == USE
22269 || GET_CODE (PATTERN (insn)) == CLOBBER)
22271 cached_can_issue_more = more;
22272 return cached_can_issue_more;
22275 if (insn_terminates_group_p (insn, current_group))
22277 cached_can_issue_more = 0;
22278 return cached_can_issue_more;
22281 /* If no reservation, but reach here */
22282 if (recog_memoized (insn) < 0)
22285 if (rs6000_sched_groups)
22287 if (is_microcoded_insn (insn))
22288 cached_can_issue_more = 0;
22289 else if (is_cracked_insn (insn))
22290 cached_can_issue_more = more > 2 ? more - 2 : 0;
22292 cached_can_issue_more = more - 1;
22294 return cached_can_issue_more;
22297 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22300 cached_can_issue_more = more - 1;
22301 return cached_can_issue_more;
22305 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22307 int r = rs6000_variable_issue_1 (insn, more);
22309 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22313 /* Adjust the cost of a scheduling dependency. Return the new cost of
22314 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22317 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22319 enum attr_type attr_type;
22321 if (! recog_memoized (insn))
22324 switch (REG_NOTE_KIND (link))
22328 /* Data dependency; DEP_INSN writes a register that INSN reads
22329 some cycles later. */
22331 /* Separate a load from a narrower, dependent store. */
22332 if (rs6000_sched_groups
22333 && GET_CODE (PATTERN (insn)) == SET
22334 && GET_CODE (PATTERN (dep_insn)) == SET
22335 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22336 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22337 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22338 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22341 attr_type = get_attr_type (insn);
22346 /* Tell the first scheduling pass about the latency between
22347 a mtctr and bctr (and mtlr and br/blr). The first
22348 scheduling pass will not know about this latency since
22349 the mtctr instruction, which has the latency associated
22350 to it, will be generated by reload. */
22351 return TARGET_POWER ? 5 : 4;
22353 /* Leave some extra cycles between a compare and its
22354 dependent branch, to inhibit expensive mispredicts. */
22355 if ((rs6000_cpu_attr == CPU_PPC603
22356 || rs6000_cpu_attr == CPU_PPC604
22357 || rs6000_cpu_attr == CPU_PPC604E
22358 || rs6000_cpu_attr == CPU_PPC620
22359 || rs6000_cpu_attr == CPU_PPC630
22360 || rs6000_cpu_attr == CPU_PPC750
22361 || rs6000_cpu_attr == CPU_PPC7400
22362 || rs6000_cpu_attr == CPU_PPC7450
22363 || rs6000_cpu_attr == CPU_POWER4
22364 || rs6000_cpu_attr == CPU_POWER5
22365 || rs6000_cpu_attr == CPU_POWER7
22366 || rs6000_cpu_attr == CPU_CELL)
22367 && recog_memoized (dep_insn)
22368 && (INSN_CODE (dep_insn) >= 0))
22370 switch (get_attr_type (dep_insn))
22374 case TYPE_DELAYED_COMPARE:
22375 case TYPE_IMUL_COMPARE:
22376 case TYPE_LMUL_COMPARE:
22377 case TYPE_FPCOMPARE:
22378 case TYPE_CR_LOGICAL:
22379 case TYPE_DELAYED_CR:
22388 case TYPE_STORE_UX:
22390 case TYPE_FPSTORE_U:
22391 case TYPE_FPSTORE_UX:
22392 if ((rs6000_cpu == PROCESSOR_POWER6)
22393 && recog_memoized (dep_insn)
22394 && (INSN_CODE (dep_insn) >= 0))
22397 if (GET_CODE (PATTERN (insn)) != SET)
22398 /* If this happens, we have to extend this to schedule
22399 optimally. Return default for now. */
22402 /* Adjust the cost for the case where the value written
22403 by a fixed point operation is used as the address
22404 gen value on a store. */
22405 switch (get_attr_type (dep_insn))
22412 if (! store_data_bypass_p (dep_insn, insn))
22416 case TYPE_LOAD_EXT:
22417 case TYPE_LOAD_EXT_U:
22418 case TYPE_LOAD_EXT_UX:
22419 case TYPE_VAR_SHIFT_ROTATE:
22420 case TYPE_VAR_DELAYED_COMPARE:
22422 if (! store_data_bypass_p (dep_insn, insn))
22428 case TYPE_FAST_COMPARE:
22431 case TYPE_INSERT_WORD:
22432 case TYPE_INSERT_DWORD:
22433 case TYPE_FPLOAD_U:
22434 case TYPE_FPLOAD_UX:
22436 case TYPE_STORE_UX:
22437 case TYPE_FPSTORE_U:
22438 case TYPE_FPSTORE_UX:
22440 if (! store_data_bypass_p (dep_insn, insn))
22448 case TYPE_IMUL_COMPARE:
22449 case TYPE_LMUL_COMPARE:
22451 if (! store_data_bypass_p (dep_insn, insn))
22457 if (! store_data_bypass_p (dep_insn, insn))
22463 if (! store_data_bypass_p (dep_insn, insn))
22476 case TYPE_LOAD_EXT:
22477 case TYPE_LOAD_EXT_U:
22478 case TYPE_LOAD_EXT_UX:
22479 if ((rs6000_cpu == PROCESSOR_POWER6)
22480 && recog_memoized (dep_insn)
22481 && (INSN_CODE (dep_insn) >= 0))
22484 /* Adjust the cost for the case where the value written
22485 by a fixed point instruction is used within the address
22486 gen portion of a subsequent load(u)(x) */
22487 switch (get_attr_type (dep_insn))
22494 if (set_to_load_agen (dep_insn, insn))
22498 case TYPE_LOAD_EXT:
22499 case TYPE_LOAD_EXT_U:
22500 case TYPE_LOAD_EXT_UX:
22501 case TYPE_VAR_SHIFT_ROTATE:
22502 case TYPE_VAR_DELAYED_COMPARE:
22504 if (set_to_load_agen (dep_insn, insn))
22510 case TYPE_FAST_COMPARE:
22513 case TYPE_INSERT_WORD:
22514 case TYPE_INSERT_DWORD:
22515 case TYPE_FPLOAD_U:
22516 case TYPE_FPLOAD_UX:
22518 case TYPE_STORE_UX:
22519 case TYPE_FPSTORE_U:
22520 case TYPE_FPSTORE_UX:
22522 if (set_to_load_agen (dep_insn, insn))
22530 case TYPE_IMUL_COMPARE:
22531 case TYPE_LMUL_COMPARE:
22533 if (set_to_load_agen (dep_insn, insn))
22539 if (set_to_load_agen (dep_insn, insn))
22545 if (set_to_load_agen (dep_insn, insn))
22556 if ((rs6000_cpu == PROCESSOR_POWER6)
22557 && recog_memoized (dep_insn)
22558 && (INSN_CODE (dep_insn) >= 0)
22559 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22566 /* Fall out to return default cost. */
22570 case REG_DEP_OUTPUT:
22571 /* Output dependency; DEP_INSN writes a register that INSN writes some
22573 if ((rs6000_cpu == PROCESSOR_POWER6)
22574 && recog_memoized (dep_insn)
22575 && (INSN_CODE (dep_insn) >= 0))
22577 attr_type = get_attr_type (insn);
22582 if (get_attr_type (dep_insn) == TYPE_FP)
22586 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22594 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22599 gcc_unreachable ();
22605 /* Debug version of rs6000_adjust_cost. */
22608 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22610 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
22616 switch (REG_NOTE_KIND (link))
22618 default: dep = "unknown depencency"; break;
22619 case REG_DEP_TRUE: dep = "data dependency"; break;
22620 case REG_DEP_OUTPUT: dep = "output dependency"; break;
22621 case REG_DEP_ANTI: dep = "anti depencency"; break;
22625 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22626 "%s, insn:\n", ret, cost, dep);
22634 /* The function returns a true if INSN is microcoded.
22635 Return false otherwise. */
22638 is_microcoded_insn (rtx insn)
22640 if (!insn || !NONDEBUG_INSN_P (insn)
22641 || GET_CODE (PATTERN (insn)) == USE
22642 || GET_CODE (PATTERN (insn)) == CLOBBER)
22645 if (rs6000_cpu_attr == CPU_CELL)
22646 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
22648 if (rs6000_sched_groups)
22650 enum attr_type type = get_attr_type (insn);
22651 if (type == TYPE_LOAD_EXT_U
22652 || type == TYPE_LOAD_EXT_UX
22653 || type == TYPE_LOAD_UX
22654 || type == TYPE_STORE_UX
22655 || type == TYPE_MFCR)
22662 /* The function returns true if INSN is cracked into 2 instructions
22663 by the processor (and therefore occupies 2 issue slots). */
22666 is_cracked_insn (rtx insn)
22668 if (!insn || !NONDEBUG_INSN_P (insn)
22669 || GET_CODE (PATTERN (insn)) == USE
22670 || GET_CODE (PATTERN (insn)) == CLOBBER)
22673 if (rs6000_sched_groups)
22675 enum attr_type type = get_attr_type (insn);
22676 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
22677 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
22678 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
22679 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
22680 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
22681 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
22682 || type == TYPE_IDIV || type == TYPE_LDIV
22683 || type == TYPE_INSERT_WORD)
22690 /* The function returns true if INSN can be issued only from
22691 the branch slot. */
22694 is_branch_slot_insn (rtx insn)
22696 if (!insn || !NONDEBUG_INSN_P (insn)
22697 || GET_CODE (PATTERN (insn)) == USE
22698 || GET_CODE (PATTERN (insn)) == CLOBBER)
22701 if (rs6000_sched_groups)
22703 enum attr_type type = get_attr_type (insn);
22704 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
22712 /* The function returns true if out_inst sets a value that is
22713 used in the address generation computation of in_insn */
22715 set_to_load_agen (rtx out_insn, rtx in_insn)
22717 rtx out_set, in_set;
22719 /* For performance reasons, only handle the simple case where
22720 both loads are a single_set. */
22721 out_set = single_set (out_insn);
22724 in_set = single_set (in_insn);
22726 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
22732 /* The function returns true if the target storage location of
22733 out_insn is adjacent to the target storage location of in_insn */
22734 /* Return 1 if memory locations are adjacent. */
22737 adjacent_mem_locations (rtx insn1, rtx insn2)
22740 rtx a = get_store_dest (PATTERN (insn1));
22741 rtx b = get_store_dest (PATTERN (insn2));
22743 if ((GET_CODE (XEXP (a, 0)) == REG
22744 || (GET_CODE (XEXP (a, 0)) == PLUS
22745 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
22746 && (GET_CODE (XEXP (b, 0)) == REG
22747 || (GET_CODE (XEXP (b, 0)) == PLUS
22748 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
22750 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
22753 if (GET_CODE (XEXP (a, 0)) == PLUS)
22755 reg0 = XEXP (XEXP (a, 0), 0);
22756 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
22759 reg0 = XEXP (a, 0);
22761 if (GET_CODE (XEXP (b, 0)) == PLUS)
22763 reg1 = XEXP (XEXP (b, 0), 0);
22764 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
22767 reg1 = XEXP (b, 0);
22769 val_diff = val1 - val0;
22771 return ((REGNO (reg0) == REGNO (reg1))
22772 && ((MEM_SIZE_KNOWN_P (a) && val_diff == MEM_SIZE (a))
22773 || (MEM_SIZE_KNOWN_P (b) && val_diff == -MEM_SIZE (b))));
22779 /* A C statement (sans semicolon) to update the integer scheduling
22780 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22781 INSN earlier, reduce the priority to execute INSN later. Do not
22782 define this macro if you do not need to adjust the scheduling
22783 priorities of insns. */
22786 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
22788 /* On machines (like the 750) which have asymmetric integer units,
22789 where one integer unit can do multiply and divides and the other
22790 can't, reduce the priority of multiply/divide so it is scheduled
22791 before other integer operations. */
22794 if (! INSN_P (insn))
22797 if (GET_CODE (PATTERN (insn)) == USE)
22800 switch (rs6000_cpu_attr) {
22802 switch (get_attr_type (insn))
22809 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
22810 priority, priority);
22811 if (priority >= 0 && priority < 0x01000000)
22818 if (insn_must_be_first_in_group (insn)
22819 && reload_completed
22820 && current_sched_info->sched_max_insns_priority
22821 && rs6000_sched_restricted_insns_priority)
22824 /* Prioritize insns that can be dispatched only in the first
22826 if (rs6000_sched_restricted_insns_priority == 1)
22827 /* Attach highest priority to insn. This means that in
22828 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
22829 precede 'priority' (critical path) considerations. */
22830 return current_sched_info->sched_max_insns_priority;
22831 else if (rs6000_sched_restricted_insns_priority == 2)
22832 /* Increase priority of insn by a minimal amount. This means that in
22833 haifa-sched.c:ready_sort(), only 'priority' (critical path)
22834 considerations precede dispatch-slot restriction considerations. */
22835 return (priority + 1);
22838 if (rs6000_cpu == PROCESSOR_POWER6
22839 && ((load_store_pendulum == -2 && is_load_insn (insn))
22840 || (load_store_pendulum == 2 && is_store_insn (insn))))
22841 /* Attach highest priority to insn if the scheduler has just issued two
22842 stores and this instruction is a load, or two loads and this instruction
22843 is a store. Power6 wants loads and stores scheduled alternately
22845 return current_sched_info->sched_max_insns_priority;
22850 /* Return true if the instruction is nonpipelined on the Cell. */
22852 is_nonpipeline_insn (rtx insn)
22854 enum attr_type type;
22855 if (!insn || !NONDEBUG_INSN_P (insn)
22856 || GET_CODE (PATTERN (insn)) == USE
22857 || GET_CODE (PATTERN (insn)) == CLOBBER)
22860 type = get_attr_type (insn);
22861 if (type == TYPE_IMUL
22862 || type == TYPE_IMUL2
22863 || type == TYPE_IMUL3
22864 || type == TYPE_LMUL
22865 || type == TYPE_IDIV
22866 || type == TYPE_LDIV
22867 || type == TYPE_SDIV
22868 || type == TYPE_DDIV
22869 || type == TYPE_SSQRT
22870 || type == TYPE_DSQRT
22871 || type == TYPE_MFCR
22872 || type == TYPE_MFCRF
22873 || type == TYPE_MFJMPR)
22881 /* Return how many instructions the machine can issue per cycle. */
22884 rs6000_issue_rate (void)
22886 /* Unless scheduling for register pressure, use issue rate of 1 for
22887 first scheduling pass to decrease degradation. */
22888 if (!reload_completed && !flag_sched_pressure)
22891 switch (rs6000_cpu_attr) {
22892 case CPU_RIOS1: /* ? */
22894 case CPU_PPC601: /* ? */
22904 case CPU_PPCE300C2:
22905 case CPU_PPCE300C3:
22906 case CPU_PPCE500MC:
22907 case CPU_PPCE500MC64:
22927 /* Return how many instructions to look ahead for better insn
22931 rs6000_use_sched_lookahead (void)
22933 switch (rs6000_cpu_attr)
22940 return (reload_completed ? 8 : 0);
22947 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
22949 rs6000_use_sched_lookahead_guard (rtx insn)
22951 if (rs6000_cpu_attr != CPU_CELL)
22954 if (insn == NULL_RTX || !INSN_P (insn))
22957 if (!reload_completed
22958 || is_nonpipeline_insn (insn)
22959 || is_microcoded_insn (insn))
22965 /* Determine is PAT refers to memory. */
22968 is_mem_ref (rtx pat)
22974 /* stack_tie does not produce any real memory traffic. */
22975 if (tie_operand (pat, VOIDmode))
22978 if (GET_CODE (pat) == MEM)
22981 /* Recursively process the pattern. */
22982 fmt = GET_RTX_FORMAT (GET_CODE (pat));
22984 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
22987 ret |= is_mem_ref (XEXP (pat, i));
22988 else if (fmt[i] == 'E')
22989 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
22990 ret |= is_mem_ref (XVECEXP (pat, i, j));
22996 /* Determine if PAT is a PATTERN of a load insn. */
22999 is_load_insn1 (rtx pat)
23001 if (!pat || pat == NULL_RTX)
23004 if (GET_CODE (pat) == SET)
23005 return is_mem_ref (SET_SRC (pat));
23007 if (GET_CODE (pat) == PARALLEL)
23011 for (i = 0; i < XVECLEN (pat, 0); i++)
23012 if (is_load_insn1 (XVECEXP (pat, 0, i)))
23019 /* Determine if INSN loads from memory. */
23022 is_load_insn (rtx insn)
23024 if (!insn || !INSN_P (insn))
23027 if (GET_CODE (insn) == CALL_INSN)
23030 return is_load_insn1 (PATTERN (insn));
23033 /* Determine if PAT is a PATTERN of a store insn. */
23036 is_store_insn1 (rtx pat)
23038 if (!pat || pat == NULL_RTX)
23041 if (GET_CODE (pat) == SET)
23042 return is_mem_ref (SET_DEST (pat));
23044 if (GET_CODE (pat) == PARALLEL)
23048 for (i = 0; i < XVECLEN (pat, 0); i++)
23049 if (is_store_insn1 (XVECEXP (pat, 0, i)))
23056 /* Determine if INSN stores to memory. */
23059 is_store_insn (rtx insn)
23061 if (!insn || !INSN_P (insn))
23064 return is_store_insn1 (PATTERN (insn));
23067 /* Return the dest of a store insn. */
23070 get_store_dest (rtx pat)
23072 gcc_assert (is_store_insn1 (pat));
23074 if (GET_CODE (pat) == SET)
23075 return SET_DEST (pat);
23076 else if (GET_CODE (pat) == PARALLEL)
23080 for (i = 0; i < XVECLEN (pat, 0); i++)
23082 rtx inner_pat = XVECEXP (pat, 0, i);
23083 if (GET_CODE (inner_pat) == SET
23084 && is_mem_ref (SET_DEST (inner_pat)))
23088 /* We shouldn't get here, because we should have either a simple
23089 store insn or a store with update which are covered above. */
23093 /* Returns whether the dependence between INSN and NEXT is considered
23094 costly by the given target. */
23097 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
23102 /* If the flag is not enabled - no dependence is considered costly;
23103 allow all dependent insns in the same group.
23104 This is the most aggressive option. */
23105 if (rs6000_sched_costly_dep == no_dep_costly)
23108 /* If the flag is set to 1 - a dependence is always considered costly;
23109 do not allow dependent instructions in the same group.
23110 This is the most conservative option. */
23111 if (rs6000_sched_costly_dep == all_deps_costly)
23114 insn = DEP_PRO (dep);
23115 next = DEP_CON (dep);
23117 if (rs6000_sched_costly_dep == store_to_load_dep_costly
23118 && is_load_insn (next)
23119 && is_store_insn (insn))
23120 /* Prevent load after store in the same group. */
23123 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
23124 && is_load_insn (next)
23125 && is_store_insn (insn)
23126 && DEP_TYPE (dep) == REG_DEP_TRUE)
23127 /* Prevent load after store in the same group if it is a true
23131 /* The flag is set to X; dependences with latency >= X are considered costly,
23132 and will not be scheduled in the same group. */
23133 if (rs6000_sched_costly_dep <= max_dep_latency
23134 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23140 /* Return the next insn after INSN that is found before TAIL is reached,
23141 skipping any "non-active" insns - insns that will not actually occupy
23142 an issue slot. Return NULL_RTX if such an insn is not found. */
23145 get_next_active_insn (rtx insn, rtx tail)
23147 if (insn == NULL_RTX || insn == tail)
23152 insn = NEXT_INSN (insn);
23153 if (insn == NULL_RTX || insn == tail)
23158 || (NONJUMP_INSN_P (insn)
23159 && GET_CODE (PATTERN (insn)) != USE
23160 && GET_CODE (PATTERN (insn)) != CLOBBER
23161 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23167 /* We are about to begin issuing insns for this clock cycle. */
23170 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23171 rtx *ready ATTRIBUTE_UNUSED,
23172 int *pn_ready ATTRIBUTE_UNUSED,
23173 int clock_var ATTRIBUTE_UNUSED)
23175 int n_ready = *pn_ready;
23178 fprintf (dump, "// rs6000_sched_reorder :\n");
23180 /* Reorder the ready list, if the second to last ready insn
23181 is a nonepipeline insn. */
23182 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23184 if (is_nonpipeline_insn (ready[n_ready - 1])
23185 && (recog_memoized (ready[n_ready - 2]) > 0))
23186 /* Simply swap first two insns. */
23188 rtx tmp = ready[n_ready - 1];
23189 ready[n_ready - 1] = ready[n_ready - 2];
23190 ready[n_ready - 2] = tmp;
23194 if (rs6000_cpu == PROCESSOR_POWER6)
23195 load_store_pendulum = 0;
23197 return rs6000_issue_rate ();
23200 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23203 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23204 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23207 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23209 /* For Power6, we need to handle some special cases to try and keep the
23210 store queue from overflowing and triggering expensive flushes.
23212 This code monitors how load and store instructions are being issued
23213 and skews the ready list one way or the other to increase the likelihood
23214 that a desired instruction is issued at the proper time.
23216 A couple of things are done. First, we maintain a "load_store_pendulum"
23217 to track the current state of load/store issue.
23219 - If the pendulum is at zero, then no loads or stores have been
23220 issued in the current cycle so we do nothing.
23222 - If the pendulum is 1, then a single load has been issued in this
23223 cycle and we attempt to locate another load in the ready list to
23226 - If the pendulum is -2, then two stores have already been
23227 issued in this cycle, so we increase the priority of the first load
23228 in the ready list to increase it's likelihood of being chosen first
23231 - If the pendulum is -1, then a single store has been issued in this
23232 cycle and we attempt to locate another store in the ready list to
23233 issue with it, preferring a store to an adjacent memory location to
23234 facilitate store pairing in the store queue.
23236 - If the pendulum is 2, then two loads have already been
23237 issued in this cycle, so we increase the priority of the first store
23238 in the ready list to increase it's likelihood of being chosen first
23241 - If the pendulum < -2 or > 2, then do nothing.
23243 Note: This code covers the most common scenarios. There exist non
23244 load/store instructions which make use of the LSU and which
23245 would need to be accounted for to strictly model the behavior
23246 of the machine. Those instructions are currently unaccounted
23247 for to help minimize compile time overhead of this code.
23249 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23255 if (is_store_insn (last_scheduled_insn))
23256 /* Issuing a store, swing the load_store_pendulum to the left */
23257 load_store_pendulum--;
23258 else if (is_load_insn (last_scheduled_insn))
23259 /* Issuing a load, swing the load_store_pendulum to the right */
23260 load_store_pendulum++;
23262 return cached_can_issue_more;
23264 /* If the pendulum is balanced, or there is only one instruction on
23265 the ready list, then all is well, so return. */
23266 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23267 return cached_can_issue_more;
23269 if (load_store_pendulum == 1)
23271 /* A load has been issued in this cycle. Scan the ready list
23272 for another load to issue with it */
23277 if (is_load_insn (ready[pos]))
23279 /* Found a load. Move it to the head of the ready list,
23280 and adjust it's priority so that it is more likely to
23283 for (i=pos; i<*pn_ready-1; i++)
23284 ready[i] = ready[i + 1];
23285 ready[*pn_ready-1] = tmp;
23287 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23288 INSN_PRIORITY (tmp)++;
23294 else if (load_store_pendulum == -2)
23296 /* Two stores have been issued in this cycle. Increase the
23297 priority of the first load in the ready list to favor it for
23298 issuing in the next cycle. */
23303 if (is_load_insn (ready[pos])
23305 && INSN_PRIORITY_KNOWN (ready[pos]))
23307 INSN_PRIORITY (ready[pos])++;
23309 /* Adjust the pendulum to account for the fact that a load
23310 was found and increased in priority. This is to prevent
23311 increasing the priority of multiple loads */
23312 load_store_pendulum--;
23319 else if (load_store_pendulum == -1)
23321 /* A store has been issued in this cycle. Scan the ready list for
23322 another store to issue with it, preferring a store to an adjacent
23324 int first_store_pos = -1;
23330 if (is_store_insn (ready[pos]))
23332 /* Maintain the index of the first store found on the
23334 if (first_store_pos == -1)
23335 first_store_pos = pos;
23337 if (is_store_insn (last_scheduled_insn)
23338 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
23340 /* Found an adjacent store. Move it to the head of the
23341 ready list, and adjust it's priority so that it is
23342 more likely to stay there */
23344 for (i=pos; i<*pn_ready-1; i++)
23345 ready[i] = ready[i + 1];
23346 ready[*pn_ready-1] = tmp;
23348 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23349 INSN_PRIORITY (tmp)++;
23351 first_store_pos = -1;
23359 if (first_store_pos >= 0)
23361 /* An adjacent store wasn't found, but a non-adjacent store was,
23362 so move the non-adjacent store to the front of the ready
23363 list, and adjust its priority so that it is more likely to
23365 tmp = ready[first_store_pos];
23366 for (i=first_store_pos; i<*pn_ready-1; i++)
23367 ready[i] = ready[i + 1];
23368 ready[*pn_ready-1] = tmp;
23369 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23370 INSN_PRIORITY (tmp)++;
23373 else if (load_store_pendulum == 2)
23375 /* Two loads have been issued in this cycle. Increase the priority
23376 of the first store in the ready list to favor it for issuing in
23382 if (is_store_insn (ready[pos])
23384 && INSN_PRIORITY_KNOWN (ready[pos]))
23386 INSN_PRIORITY (ready[pos])++;
23388 /* Adjust the pendulum to account for the fact that a store
23389 was found and increased in priority. This is to prevent
23390 increasing the priority of multiple stores */
23391 load_store_pendulum++;
23400 return cached_can_issue_more;
23403 /* Return whether the presence of INSN causes a dispatch group termination
23404 of group WHICH_GROUP.
23406 If WHICH_GROUP == current_group, this function will return true if INSN
23407 causes the termination of the current group (i.e, the dispatch group to
23408 which INSN belongs). This means that INSN will be the last insn in the
23409 group it belongs to.
23411 If WHICH_GROUP == previous_group, this function will return true if INSN
23412 causes the termination of the previous group (i.e, the dispatch group that
23413 precedes the group to which INSN belongs). This means that INSN will be
23414 the first insn in the group it belongs to). */
23417 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23424 first = insn_must_be_first_in_group (insn);
23425 last = insn_must_be_last_in_group (insn);
23430 if (which_group == current_group)
23432 else if (which_group == previous_group)
23440 insn_must_be_first_in_group (rtx insn)
23442 enum attr_type type;
23445 || GET_CODE (insn) == NOTE
23446 || DEBUG_INSN_P (insn)
23447 || GET_CODE (PATTERN (insn)) == USE
23448 || GET_CODE (PATTERN (insn)) == CLOBBER)
23451 switch (rs6000_cpu)
23453 case PROCESSOR_POWER5:
23454 if (is_cracked_insn (insn))
23456 case PROCESSOR_POWER4:
23457 if (is_microcoded_insn (insn))
23460 if (!rs6000_sched_groups)
23463 type = get_attr_type (insn);
23470 case TYPE_DELAYED_CR:
23471 case TYPE_CR_LOGICAL:
23485 case PROCESSOR_POWER6:
23486 type = get_attr_type (insn);
23490 case TYPE_INSERT_DWORD:
23494 case TYPE_VAR_SHIFT_ROTATE:
23501 case TYPE_INSERT_WORD:
23502 case TYPE_DELAYED_COMPARE:
23503 case TYPE_IMUL_COMPARE:
23504 case TYPE_LMUL_COMPARE:
23505 case TYPE_FPCOMPARE:
23516 case TYPE_LOAD_EXT_UX:
23518 case TYPE_STORE_UX:
23519 case TYPE_FPLOAD_U:
23520 case TYPE_FPLOAD_UX:
23521 case TYPE_FPSTORE_U:
23522 case TYPE_FPSTORE_UX:
23528 case PROCESSOR_POWER7:
23529 type = get_attr_type (insn);
23533 case TYPE_CR_LOGICAL:
23540 case TYPE_DELAYED_COMPARE:
23541 case TYPE_VAR_DELAYED_COMPARE:
23547 case TYPE_LOAD_EXT:
23548 case TYPE_LOAD_EXT_U:
23549 case TYPE_LOAD_EXT_UX:
23551 case TYPE_STORE_UX:
23552 case TYPE_FPLOAD_U:
23553 case TYPE_FPLOAD_UX:
23554 case TYPE_FPSTORE_U:
23555 case TYPE_FPSTORE_UX:
23571 insn_must_be_last_in_group (rtx insn)
23573 enum attr_type type;
23576 || GET_CODE (insn) == NOTE
23577 || DEBUG_INSN_P (insn)
23578 || GET_CODE (PATTERN (insn)) == USE
23579 || GET_CODE (PATTERN (insn)) == CLOBBER)
23582 switch (rs6000_cpu) {
23583 case PROCESSOR_POWER4:
23584 case PROCESSOR_POWER5:
23585 if (is_microcoded_insn (insn))
23588 if (is_branch_slot_insn (insn))
23592 case PROCESSOR_POWER6:
23593 type = get_attr_type (insn);
23600 case TYPE_VAR_SHIFT_ROTATE:
23607 case TYPE_DELAYED_COMPARE:
23608 case TYPE_IMUL_COMPARE:
23609 case TYPE_LMUL_COMPARE:
23610 case TYPE_FPCOMPARE:
23624 case PROCESSOR_POWER7:
23625 type = get_attr_type (insn);
23633 case TYPE_LOAD_EXT_U:
23634 case TYPE_LOAD_EXT_UX:
23635 case TYPE_STORE_UX:
23648 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23649 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23652 is_costly_group (rtx *group_insns, rtx next_insn)
23655 int issue_rate = rs6000_issue_rate ();
23657 for (i = 0; i < issue_rate; i++)
23659 sd_iterator_def sd_it;
23661 rtx insn = group_insns[i];
23666 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
23668 rtx next = DEP_CON (dep);
23670 if (next == next_insn
23671 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
23679 /* Utility of the function redefine_groups.
23680 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23681 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23682 to keep it "far" (in a separate group) from GROUP_INSNS, following
23683 one of the following schemes, depending on the value of the flag
23684 -minsert_sched_nops = X:
23685 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23686 in order to force NEXT_INSN into a separate group.
23687 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23688 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23689 insertion (has a group just ended, how many vacant issue slots remain in the
23690 last group, and how many dispatch groups were encountered so far). */
23693 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
23694 rtx next_insn, bool *group_end, int can_issue_more,
23699 int issue_rate = rs6000_issue_rate ();
23700 bool end = *group_end;
23703 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
23704 return can_issue_more;
23706 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
23707 return can_issue_more;
23709 force = is_costly_group (group_insns, next_insn);
23711 return can_issue_more;
23713 if (sched_verbose > 6)
23714 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
23715 *group_count ,can_issue_more);
23717 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
23720 can_issue_more = 0;
23722 /* Since only a branch can be issued in the last issue_slot, it is
23723 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23724 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23725 in this case the last nop will start a new group and the branch
23726 will be forced to the new group. */
23727 if (can_issue_more && !is_branch_slot_insn (next_insn))
23730 while (can_issue_more > 0)
23733 emit_insn_before (nop, next_insn);
23741 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
23743 int n_nops = rs6000_sched_insert_nops;
23745 /* Nops can't be issued from the branch slot, so the effective
23746 issue_rate for nops is 'issue_rate - 1'. */
23747 if (can_issue_more == 0)
23748 can_issue_more = issue_rate;
23750 if (can_issue_more == 0)
23752 can_issue_more = issue_rate - 1;
23755 for (i = 0; i < issue_rate; i++)
23757 group_insns[i] = 0;
23764 emit_insn_before (nop, next_insn);
23765 if (can_issue_more == issue_rate - 1) /* new group begins */
23768 if (can_issue_more == 0)
23770 can_issue_more = issue_rate - 1;
23773 for (i = 0; i < issue_rate; i++)
23775 group_insns[i] = 0;
23781 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23784 /* Is next_insn going to start a new group? */
23787 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23788 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23789 || (can_issue_more < issue_rate &&
23790 insn_terminates_group_p (next_insn, previous_group)));
23791 if (*group_end && end)
23794 if (sched_verbose > 6)
23795 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
23796 *group_count, can_issue_more);
23797 return can_issue_more;
23800 return can_issue_more;
23803 /* This function tries to synch the dispatch groups that the compiler "sees"
23804 with the dispatch groups that the processor dispatcher is expected to
23805 form in practice. It tries to achieve this synchronization by forcing the
23806 estimated processor grouping on the compiler (as opposed to the function
23807 'pad_goups' which tries to force the scheduler's grouping on the processor).
23809 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23810 examines the (estimated) dispatch groups that will be formed by the processor
23811 dispatcher. It marks these group boundaries to reflect the estimated
23812 processor grouping, overriding the grouping that the scheduler had marked.
23813 Depending on the value of the flag '-minsert-sched-nops' this function can
23814 force certain insns into separate groups or force a certain distance between
23815 them by inserting nops, for example, if there exists a "costly dependence"
23818 The function estimates the group boundaries that the processor will form as
23819 follows: It keeps track of how many vacant issue slots are available after
23820 each insn. A subsequent insn will start a new group if one of the following
23822 - no more vacant issue slots remain in the current dispatch group.
23823 - only the last issue slot, which is the branch slot, is vacant, but the next
23824 insn is not a branch.
23825 - only the last 2 or less issue slots, including the branch slot, are vacant,
23826 which means that a cracked insn (which occupies two issue slots) can't be
23827 issued in this group.
23828 - less than 'issue_rate' slots are vacant, and the next insn always needs to
23829 start a new group. */
23832 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23834 rtx insn, next_insn;
23836 int can_issue_more;
23839 int group_count = 0;
23843 issue_rate = rs6000_issue_rate ();
23844 group_insns = XALLOCAVEC (rtx, issue_rate);
23845 for (i = 0; i < issue_rate; i++)
23847 group_insns[i] = 0;
23849 can_issue_more = issue_rate;
23851 insn = get_next_active_insn (prev_head_insn, tail);
23854 while (insn != NULL_RTX)
23856 slot = (issue_rate - can_issue_more);
23857 group_insns[slot] = insn;
23859 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23860 if (insn_terminates_group_p (insn, current_group))
23861 can_issue_more = 0;
23863 next_insn = get_next_active_insn (insn, tail);
23864 if (next_insn == NULL_RTX)
23865 return group_count + 1;
23867 /* Is next_insn going to start a new group? */
23869 = (can_issue_more == 0
23870 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23871 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23872 || (can_issue_more < issue_rate &&
23873 insn_terminates_group_p (next_insn, previous_group)));
23875 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
23876 next_insn, &group_end, can_issue_more,
23882 can_issue_more = 0;
23883 for (i = 0; i < issue_rate; i++)
23885 group_insns[i] = 0;
23889 if (GET_MODE (next_insn) == TImode && can_issue_more)
23890 PUT_MODE (next_insn, VOIDmode);
23891 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
23892 PUT_MODE (next_insn, TImode);
23895 if (can_issue_more == 0)
23896 can_issue_more = issue_rate;
23899 return group_count;
23902 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
23903 dispatch group boundaries that the scheduler had marked. Pad with nops
23904 any dispatch groups which have vacant issue slots, in order to force the
23905 scheduler's grouping on the processor dispatcher. The function
23906 returns the number of dispatch groups found. */
23909 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23911 rtx insn, next_insn;
23914 int can_issue_more;
23916 int group_count = 0;
23918 /* Initialize issue_rate. */
23919 issue_rate = rs6000_issue_rate ();
23920 can_issue_more = issue_rate;
23922 insn = get_next_active_insn (prev_head_insn, tail);
23923 next_insn = get_next_active_insn (insn, tail);
23925 while (insn != NULL_RTX)
23928 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23930 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
23932 if (next_insn == NULL_RTX)
23937 /* If the scheduler had marked group termination at this location
23938 (between insn and next_insn), and neither insn nor next_insn will
23939 force group termination, pad the group with nops to force group
23942 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
23943 && !insn_terminates_group_p (insn, current_group)
23944 && !insn_terminates_group_p (next_insn, previous_group))
23946 if (!is_branch_slot_insn (next_insn))
23949 while (can_issue_more)
23952 emit_insn_before (nop, next_insn);
23957 can_issue_more = issue_rate;
23962 next_insn = get_next_active_insn (insn, tail);
23965 return group_count;
23968 /* We're beginning a new block. Initialize data structures as necessary. */
23971 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
23972 int sched_verbose ATTRIBUTE_UNUSED,
23973 int max_ready ATTRIBUTE_UNUSED)
23975 last_scheduled_insn = NULL_RTX;
23976 load_store_pendulum = 0;
23979 /* The following function is called at the end of scheduling BB.
23980 After reload, it inserts nops at insn group bundling. */
23983 rs6000_sched_finish (FILE *dump, int sched_verbose)
23988 fprintf (dump, "=== Finishing schedule.\n");
23990 if (reload_completed && rs6000_sched_groups)
23992 /* Do not run sched_finish hook when selective scheduling enabled. */
23993 if (sel_sched_p ())
23996 if (rs6000_sched_insert_nops == sched_finish_none)
23999 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
24000 n_groups = pad_groups (dump, sched_verbose,
24001 current_sched_info->prev_head,
24002 current_sched_info->next_tail);
24004 n_groups = redefine_groups (dump, sched_verbose,
24005 current_sched_info->prev_head,
24006 current_sched_info->next_tail);
24008 if (sched_verbose >= 6)
24010 fprintf (dump, "ngroups = %d\n", n_groups);
24011 print_rtl (dump, current_sched_info->prev_head);
24012 fprintf (dump, "Done finish_sched\n");
24017 struct _rs6000_sched_context
24019 short cached_can_issue_more;
24020 rtx last_scheduled_insn;
24021 int load_store_pendulum;
24024 typedef struct _rs6000_sched_context rs6000_sched_context_def;
24025 typedef rs6000_sched_context_def *rs6000_sched_context_t;
24027 /* Allocate store for new scheduling context. */
24029 rs6000_alloc_sched_context (void)
24031 return xmalloc (sizeof (rs6000_sched_context_def));
24034 /* If CLEAN_P is true then initializes _SC with clean data,
24035 and from the global context otherwise. */
24037 rs6000_init_sched_context (void *_sc, bool clean_p)
24039 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24043 sc->cached_can_issue_more = 0;
24044 sc->last_scheduled_insn = NULL_RTX;
24045 sc->load_store_pendulum = 0;
24049 sc->cached_can_issue_more = cached_can_issue_more;
24050 sc->last_scheduled_insn = last_scheduled_insn;
24051 sc->load_store_pendulum = load_store_pendulum;
24055 /* Sets the global scheduling context to the one pointed to by _SC. */
24057 rs6000_set_sched_context (void *_sc)
24059 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24061 gcc_assert (sc != NULL);
24063 cached_can_issue_more = sc->cached_can_issue_more;
24064 last_scheduled_insn = sc->last_scheduled_insn;
24065 load_store_pendulum = sc->load_store_pendulum;
24070 rs6000_free_sched_context (void *_sc)
24072 gcc_assert (_sc != NULL);
24078 /* Length in units of the trampoline for entering a nested function. */
24081 rs6000_trampoline_size (void)
24085 switch (DEFAULT_ABI)
24088 gcc_unreachable ();
24091 ret = (TARGET_32BIT) ? 12 : 24;
24096 ret = (TARGET_32BIT) ? 40 : 48;
24103 /* Emit RTL insns to initialize the variable parts of a trampoline.
24104 FNADDR is an RTX for the address of the function's pure code.
24105 CXT is an RTX for the static chain value for the function. */
24108 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
24110 int regsize = (TARGET_32BIT) ? 4 : 8;
24111 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
24112 rtx ctx_reg = force_reg (Pmode, cxt);
24113 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
24115 switch (DEFAULT_ABI)
24118 gcc_unreachable ();
24120 /* Under AIX, just build the 3 word function descriptor */
24123 rtx fnmem, fn_reg, toc_reg;
24125 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
24126 error ("You cannot take the address of a nested function if you use "
24127 "the -mno-pointers-to-nested-functions option.");
24129 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
24130 fn_reg = gen_reg_rtx (Pmode);
24131 toc_reg = gen_reg_rtx (Pmode);
24133 /* Macro to shorten the code expansions below. */
24134 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24136 m_tramp = replace_equiv_address (m_tramp, addr);
24138 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24139 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24140 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24141 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24142 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24148 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24151 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24152 LCT_NORMAL, VOIDmode, 4,
24154 GEN_INT (rs6000_trampoline_size ()), SImode,
24162 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24163 identifier as an argument, so the front end shouldn't look it up. */
24166 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24168 return is_attribute_p ("altivec", attr_id);
24171 /* Handle the "altivec" attribute. The attribute may have
24172 arguments as follows:
24174 __attribute__((altivec(vector__)))
24175 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24176 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24178 and may appear more than once (e.g., 'vector bool char') in a
24179 given declaration. */
24182 rs6000_handle_altivec_attribute (tree *node,
24183 tree name ATTRIBUTE_UNUSED,
24185 int flags ATTRIBUTE_UNUSED,
24186 bool *no_add_attrs)
24188 tree type = *node, result = NULL_TREE;
24189 enum machine_mode mode;
24192 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24193 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24194 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24197 while (POINTER_TYPE_P (type)
24198 || TREE_CODE (type) == FUNCTION_TYPE
24199 || TREE_CODE (type) == METHOD_TYPE
24200 || TREE_CODE (type) == ARRAY_TYPE)
24201 type = TREE_TYPE (type);
24203 mode = TYPE_MODE (type);
24205 /* Check for invalid AltiVec type qualifiers. */
24206 if (type == long_double_type_node)
24207 error ("use of %<long double%> in AltiVec types is invalid");
24208 else if (type == boolean_type_node)
24209 error ("use of boolean types in AltiVec types is invalid");
24210 else if (TREE_CODE (type) == COMPLEX_TYPE)
24211 error ("use of %<complex%> in AltiVec types is invalid");
24212 else if (DECIMAL_FLOAT_MODE_P (mode))
24213 error ("use of decimal floating point types in AltiVec types is invalid");
24214 else if (!TARGET_VSX)
24216 if (type == long_unsigned_type_node || type == long_integer_type_node)
24219 error ("use of %<long%> in AltiVec types is invalid for "
24220 "64-bit code without -mvsx");
24221 else if (rs6000_warn_altivec_long)
24222 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24225 else if (type == long_long_unsigned_type_node
24226 || type == long_long_integer_type_node)
24227 error ("use of %<long long%> in AltiVec types is invalid without "
24229 else if (type == double_type_node)
24230 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24233 switch (altivec_type)
24236 unsigned_p = TYPE_UNSIGNED (type);
24240 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24243 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24246 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24249 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24251 case SFmode: result = V4SF_type_node; break;
24252 case DFmode: result = V2DF_type_node; break;
24253 /* If the user says 'vector int bool', we may be handed the 'bool'
24254 attribute _before_ the 'vector' attribute, and so select the
24255 proper type in the 'b' case below. */
24256 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24257 case V2DImode: case V2DFmode:
24265 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24266 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24267 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24268 case QImode: case V16QImode: result = bool_V16QI_type_node;
24275 case V8HImode: result = pixel_V8HI_type_node;
24281 /* Propagate qualifiers attached to the element type
24282 onto the vector type. */
24283 if (result && result != type && TYPE_QUALS (type))
24284 result = build_qualified_type (result, TYPE_QUALS (type));
24286 *no_add_attrs = true; /* No need to hang on to the attribute. */
24289 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24294 /* AltiVec defines four built-in scalar types that serve as vector
24295 elements; we must teach the compiler how to mangle them. */
24297 static const char *
24298 rs6000_mangle_type (const_tree type)
24300 type = TYPE_MAIN_VARIANT (type);
24302 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24303 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24306 if (type == bool_char_type_node) return "U6__boolc";
24307 if (type == bool_short_type_node) return "U6__bools";
24308 if (type == pixel_type_node) return "u7__pixel";
24309 if (type == bool_int_type_node) return "U6__booli";
24310 if (type == bool_long_type_node) return "U6__booll";
24312 /* Mangle IBM extended float long double as `g' (__float128) on
24313 powerpc*-linux where long-double-64 previously was the default. */
24314 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24316 && TARGET_LONG_DOUBLE_128
24317 && !TARGET_IEEEQUAD)
24320 /* For all other types, use normal C++ mangling. */
24324 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24325 struct attribute_spec.handler. */
24328 rs6000_handle_longcall_attribute (tree *node, tree name,
24329 tree args ATTRIBUTE_UNUSED,
24330 int flags ATTRIBUTE_UNUSED,
24331 bool *no_add_attrs)
24333 if (TREE_CODE (*node) != FUNCTION_TYPE
24334 && TREE_CODE (*node) != FIELD_DECL
24335 && TREE_CODE (*node) != TYPE_DECL)
24337 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24339 *no_add_attrs = true;
24345 /* Set longcall attributes on all functions declared when
24346 rs6000_default_long_calls is true. */
24348 rs6000_set_default_type_attributes (tree type)
24350 if (rs6000_default_long_calls
24351 && (TREE_CODE (type) == FUNCTION_TYPE
24352 || TREE_CODE (type) == METHOD_TYPE))
24353 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24355 TYPE_ATTRIBUTES (type));
24358 darwin_set_default_type_attributes (type);
24362 /* Return a reference suitable for calling a function with the
24363 longcall attribute. */
24366 rs6000_longcall_ref (rtx call_ref)
24368 const char *call_name;
24371 if (GET_CODE (call_ref) != SYMBOL_REF)
24374 /* System V adds '.' to the internal name, so skip them. */
24375 call_name = XSTR (call_ref, 0);
24376 if (*call_name == '.')
24378 while (*call_name == '.')
24381 node = get_identifier (call_name);
24382 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24385 return force_reg (Pmode, call_ref);
24388 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24389 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24392 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24393 struct attribute_spec.handler. */
24395 rs6000_handle_struct_attribute (tree *node, tree name,
24396 tree args ATTRIBUTE_UNUSED,
24397 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24400 if (DECL_P (*node))
24402 if (TREE_CODE (*node) == TYPE_DECL)
24403 type = &TREE_TYPE (*node);
24408 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24409 || TREE_CODE (*type) == UNION_TYPE)))
24411 warning (OPT_Wattributes, "%qE attribute ignored", name);
24412 *no_add_attrs = true;
24415 else if ((is_attribute_p ("ms_struct", name)
24416 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24417 || ((is_attribute_p ("gcc_struct", name)
24418 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24420 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24422 *no_add_attrs = true;
24429 rs6000_ms_bitfield_layout_p (const_tree record_type)
24431 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24432 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24433 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24436 #ifdef USING_ELFOS_H
24438 /* A get_unnamed_section callback, used for switching to toc_section. */
24441 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24443 if (DEFAULT_ABI == ABI_AIX
24444 && TARGET_MINIMAL_TOC
24445 && !TARGET_RELOCATABLE)
24447 if (!toc_initialized)
24449 toc_initialized = 1;
24450 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24451 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24452 fprintf (asm_out_file, "\t.tc ");
24453 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24454 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24455 fprintf (asm_out_file, "\n");
24457 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24458 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24459 fprintf (asm_out_file, " = .+32768\n");
24462 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24464 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24465 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24468 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24469 if (!toc_initialized)
24471 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24472 fprintf (asm_out_file, " = .+32768\n");
24473 toc_initialized = 1;
24478 /* Implement TARGET_ASM_INIT_SECTIONS. */
24481 rs6000_elf_asm_init_sections (void)
24484 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24487 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24488 SDATA2_SECTION_ASM_OP);
24491 /* Implement TARGET_SELECT_RTX_SECTION. */
24494 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24495 unsigned HOST_WIDE_INT align)
24497 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24498 return toc_section;
24500 return default_elf_select_rtx_section (mode, x, align);
24503 /* For a SYMBOL_REF, set generic flags and then perform some
24504 target-specific processing.
24506 When the AIX ABI is requested on a non-AIX system, replace the
24507 function name with the real name (with a leading .) rather than the
24508 function descriptor name. This saves a lot of overriding code to
24509 read the prefixes. */
24511 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
24513 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24515 default_encode_section_info (decl, rtl, first);
24518 && TREE_CODE (decl) == FUNCTION_DECL
24520 && DEFAULT_ABI == ABI_AIX)
24522 rtx sym_ref = XEXP (rtl, 0);
24523 size_t len = strlen (XSTR (sym_ref, 0));
24524 char *str = XALLOCAVEC (char, len + 2);
24526 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24527 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24532 compare_section_name (const char *section, const char *templ)
24536 len = strlen (templ);
24537 return (strncmp (section, templ, len) == 0
24538 && (section[len] == 0 || section[len] == '.'));
24542 rs6000_elf_in_small_data_p (const_tree decl)
24544 if (rs6000_sdata == SDATA_NONE)
24547 /* We want to merge strings, so we never consider them small data. */
24548 if (TREE_CODE (decl) == STRING_CST)
24551 /* Functions are never in the small data area. */
24552 if (TREE_CODE (decl) == FUNCTION_DECL)
24555 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24557 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24558 if (compare_section_name (section, ".sdata")
24559 || compare_section_name (section, ".sdata2")
24560 || compare_section_name (section, ".gnu.linkonce.s")
24561 || compare_section_name (section, ".sbss")
24562 || compare_section_name (section, ".sbss2")
24563 || compare_section_name (section, ".gnu.linkonce.sb")
24564 || strcmp (section, ".PPC.EMB.sdata0") == 0
24565 || strcmp (section, ".PPC.EMB.sbss0") == 0)
24570 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
24573 && size <= g_switch_value
24574 /* If it's not public, and we're not going to reference it there,
24575 there's no need to put it in the small data section. */
24576 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
24583 #endif /* USING_ELFOS_H */
24585 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24588 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
24590 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
24593 /* Return a REG that occurs in ADDR with coefficient 1.
24594 ADDR can be effectively incremented by incrementing REG.
24596 r0 is special and we must not select it as an address
24597 register by this routine since our caller will try to
24598 increment the returned register via an "la" instruction. */
24601 find_addr_reg (rtx addr)
24603 while (GET_CODE (addr) == PLUS)
24605 if (GET_CODE (XEXP (addr, 0)) == REG
24606 && REGNO (XEXP (addr, 0)) != 0)
24607 addr = XEXP (addr, 0);
24608 else if (GET_CODE (XEXP (addr, 1)) == REG
24609 && REGNO (XEXP (addr, 1)) != 0)
24610 addr = XEXP (addr, 1);
24611 else if (CONSTANT_P (XEXP (addr, 0)))
24612 addr = XEXP (addr, 1);
24613 else if (CONSTANT_P (XEXP (addr, 1)))
24614 addr = XEXP (addr, 0);
24616 gcc_unreachable ();
24618 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
24623 rs6000_fatal_bad_address (rtx op)
24625 fatal_insn ("bad address", op);
24630 typedef struct branch_island_d {
24631 tree function_name;
24636 DEF_VEC_O(branch_island);
24637 DEF_VEC_ALLOC_O(branch_island,gc);
24639 static VEC(branch_island,gc) *branch_islands;
24641 /* Remember to generate a branch island for far calls to the given
24645 add_compiler_branch_island (tree label_name, tree function_name,
24648 branch_island *bi = VEC_safe_push (branch_island, gc, branch_islands, NULL);
24650 bi->function_name = function_name;
24651 bi->label_name = label_name;
24652 bi->line_number = line_number;
24655 /* Generate far-jump branch islands for everything recorded in
24656 branch_islands. Invoked immediately after the last instruction of
24657 the epilogue has been emitted; the branch islands must be appended
24658 to, and contiguous with, the function body. Mach-O stubs are
24659 generated in machopic_output_stub(). */
24662 macho_branch_islands (void)
24666 while (!VEC_empty (branch_island, branch_islands))
24668 branch_island *bi = VEC_last (branch_island, branch_islands);
24669 const char *label = IDENTIFIER_POINTER (bi->label_name);
24670 const char *name = IDENTIFIER_POINTER (bi->function_name);
24671 char name_buf[512];
24672 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24673 if (name[0] == '*' || name[0] == '&')
24674 strcpy (name_buf, name+1);
24678 strcpy (name_buf+1, name);
24680 strcpy (tmp_buf, "\n");
24681 strcat (tmp_buf, label);
24682 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24683 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24684 dbxout_stabd (N_SLINE, bi->line_number);
24685 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24688 if (TARGET_LINK_STACK)
24691 get_ppc476_thunk_name (name);
24692 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
24693 strcat (tmp_buf, name);
24694 strcat (tmp_buf, "\n");
24695 strcat (tmp_buf, label);
24696 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24700 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
24701 strcat (tmp_buf, label);
24702 strcat (tmp_buf, "_pic\n");
24703 strcat (tmp_buf, label);
24704 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24707 strcat (tmp_buf, "\taddis r11,r11,ha16(");
24708 strcat (tmp_buf, name_buf);
24709 strcat (tmp_buf, " - ");
24710 strcat (tmp_buf, label);
24711 strcat (tmp_buf, "_pic)\n");
24713 strcat (tmp_buf, "\tmtlr r0\n");
24715 strcat (tmp_buf, "\taddi r12,r11,lo16(");
24716 strcat (tmp_buf, name_buf);
24717 strcat (tmp_buf, " - ");
24718 strcat (tmp_buf, label);
24719 strcat (tmp_buf, "_pic)\n");
24721 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
24725 strcat (tmp_buf, ":\nlis r12,hi16(");
24726 strcat (tmp_buf, name_buf);
24727 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
24728 strcat (tmp_buf, name_buf);
24729 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
24731 output_asm_insn (tmp_buf, 0);
24732 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24733 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24734 dbxout_stabd (N_SLINE, bi->line_number);
24735 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24736 VEC_pop (branch_island, branch_islands);
24740 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24741 already there or not. */
24744 no_previous_def (tree function_name)
24749 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24750 if (function_name == bi->function_name)
24755 /* GET_PREV_LABEL gets the label name from the previous definition of
24759 get_prev_label (tree function_name)
24764 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24765 if (function_name == bi->function_name)
24766 return bi->label_name;
24770 /* INSN is either a function call or a millicode call. It may have an
24771 unconditional jump in its delay slot.
24773 CALL_DEST is the routine we are calling. */
24776 output_call (rtx insn, rtx *operands, int dest_operand_number,
24777 int cookie_operand_number)
24779 static char buf[256];
24780 if (darwin_emit_branch_islands
24781 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
24782 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
24785 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
24787 if (no_previous_def (funname))
24789 rtx label_rtx = gen_label_rtx ();
24790 char *label_buf, temp_buf[256];
24791 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
24792 CODE_LABEL_NUMBER (label_rtx));
24793 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
24794 labelname = get_identifier (label_buf);
24795 add_compiler_branch_island (labelname, funname, insn_line (insn));
24798 labelname = get_prev_label (funname);
24800 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24801 instruction will reach 'foo', otherwise link as 'bl L42'".
24802 "L42" should be a 'branch island', that will do a far jump to
24803 'foo'. Branch islands are generated in
24804 macho_branch_islands(). */
24805 sprintf (buf, "jbsr %%z%d,%.246s",
24806 dest_operand_number, IDENTIFIER_POINTER (labelname));
24809 sprintf (buf, "bl %%z%d", dest_operand_number);
24813 /* Generate PIC and indirect symbol stubs. */
24816 machopic_output_stub (FILE *file, const char *symb, const char *stub)
24818 unsigned int length;
24819 char *symbol_name, *lazy_ptr_name;
24820 char *local_label_0;
24821 static int label = 0;
24823 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24824 symb = (*targetm.strip_name_encoding) (symb);
24827 length = strlen (symb);
24828 symbol_name = XALLOCAVEC (char, length + 32);
24829 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
24831 lazy_ptr_name = XALLOCAVEC (char, length + 32);
24832 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
24835 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
24837 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
24841 fprintf (file, "\t.align 5\n");
24843 fprintf (file, "%s:\n", stub);
24844 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24847 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
24848 sprintf (local_label_0, "\"L%011d$spb\"", label);
24850 fprintf (file, "\tmflr r0\n");
24851 if (TARGET_LINK_STACK)
24854 get_ppc476_thunk_name (name);
24855 fprintf (file, "\tbl %s\n", name);
24856 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24860 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
24861 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24863 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
24864 lazy_ptr_name, local_label_0);
24865 fprintf (file, "\tmtlr r0\n");
24866 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
24867 (TARGET_64BIT ? "ldu" : "lwzu"),
24868 lazy_ptr_name, local_label_0);
24869 fprintf (file, "\tmtctr r12\n");
24870 fprintf (file, "\tbctr\n");
24874 fprintf (file, "\t.align 4\n");
24876 fprintf (file, "%s:\n", stub);
24877 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24879 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
24880 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
24881 (TARGET_64BIT ? "ldu" : "lwzu"),
24883 fprintf (file, "\tmtctr r12\n");
24884 fprintf (file, "\tbctr\n");
24887 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
24888 fprintf (file, "%s:\n", lazy_ptr_name);
24889 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24890 fprintf (file, "%sdyld_stub_binding_helper\n",
24891 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
24894 /* Legitimize PIC addresses. If the address is already
24895 position-independent, we return ORIG. Newly generated
24896 position-independent addresses go into a reg. This is REG if non
24897 zero, otherwise we allocate register(s) as necessary. */
24899 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
24902 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
24907 if (reg == NULL && ! reload_in_progress && ! reload_completed)
24908 reg = gen_reg_rtx (Pmode);
24910 if (GET_CODE (orig) == CONST)
24914 if (GET_CODE (XEXP (orig, 0)) == PLUS
24915 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
24918 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
24920 /* Use a different reg for the intermediate value, as
24921 it will be marked UNCHANGING. */
24922 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
24923 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
24926 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
24929 if (GET_CODE (offset) == CONST_INT)
24931 if (SMALL_INT (offset))
24932 return plus_constant (Pmode, base, INTVAL (offset));
24933 else if (! reload_in_progress && ! reload_completed)
24934 offset = force_reg (Pmode, offset);
24937 rtx mem = force_const_mem (Pmode, orig);
24938 return machopic_legitimize_pic_address (mem, Pmode, reg);
24941 return gen_rtx_PLUS (Pmode, base, offset);
24944 /* Fall back on generic machopic code. */
24945 return machopic_legitimize_pic_address (orig, mode, reg);
24948 /* Output a .machine directive for the Darwin assembler, and call
24949 the generic start_file routine. */
24952 rs6000_darwin_file_start (void)
24954 static const struct
24960 { "ppc64", "ppc64", MASK_64BIT },
24961 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
24962 { "power4", "ppc970", 0 },
24963 { "G5", "ppc970", 0 },
24964 { "7450", "ppc7450", 0 },
24965 { "7400", "ppc7400", MASK_ALTIVEC },
24966 { "G4", "ppc7400", 0 },
24967 { "750", "ppc750", 0 },
24968 { "740", "ppc750", 0 },
24969 { "G3", "ppc750", 0 },
24970 { "604e", "ppc604e", 0 },
24971 { "604", "ppc604", 0 },
24972 { "603e", "ppc603", 0 },
24973 { "603", "ppc603", 0 },
24974 { "601", "ppc601", 0 },
24975 { NULL, "ppc", 0 } };
24976 const char *cpu_id = "";
24979 rs6000_file_start ();
24980 darwin_file_start ();
24982 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
24984 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
24985 cpu_id = rs6000_default_cpu;
24987 if (global_options_set.x_rs6000_cpu_index)
24988 cpu_id = processor_target_table[rs6000_cpu_index].name;
24990 /* Look through the mapping array. Pick the first name that either
24991 matches the argument, has a bit set in IF_SET that is also set
24992 in the target flags, or has a NULL name. */
24995 while (mapping[i].arg != NULL
24996 && strcmp (mapping[i].arg, cpu_id) != 0
24997 && (mapping[i].if_set & target_flags) == 0)
25000 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
25003 #endif /* TARGET_MACHO */
25007 rs6000_elf_reloc_rw_mask (void)
25011 else if (DEFAULT_ABI == ABI_AIX)
25017 /* Record an element in the table of global constructors. SYMBOL is
25018 a SYMBOL_REF of the function to be called; PRIORITY is a number
25019 between 0 and MAX_INIT_PRIORITY.
25021 This differs from default_named_section_asm_out_constructor in
25022 that we have special handling for -mrelocatable. */
25024 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
25026 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
25028 const char *section = ".ctors";
25031 if (priority != DEFAULT_INIT_PRIORITY)
25033 sprintf (buf, ".ctors.%.5u",
25034 /* Invert the numbering so the linker puts us in the proper
25035 order; constructors are run from right to left, and the
25036 linker sorts in increasing order. */
25037 MAX_INIT_PRIORITY - priority);
25041 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25042 assemble_align (POINTER_SIZE);
25044 if (TARGET_RELOCATABLE)
25046 fputs ("\t.long (", asm_out_file);
25047 output_addr_const (asm_out_file, symbol);
25048 fputs (")@fixup\n", asm_out_file);
25051 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25054 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
25056 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
25058 const char *section = ".dtors";
25061 if (priority != DEFAULT_INIT_PRIORITY)
25063 sprintf (buf, ".dtors.%.5u",
25064 /* Invert the numbering so the linker puts us in the proper
25065 order; constructors are run from right to left, and the
25066 linker sorts in increasing order. */
25067 MAX_INIT_PRIORITY - priority);
25071 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25072 assemble_align (POINTER_SIZE);
25074 if (TARGET_RELOCATABLE)
25076 fputs ("\t.long (", asm_out_file);
25077 output_addr_const (asm_out_file, symbol);
25078 fputs (")@fixup\n", asm_out_file);
25081 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25085 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
25089 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
25090 ASM_OUTPUT_LABEL (file, name);
25091 fputs (DOUBLE_INT_ASM_OP, file);
25092 rs6000_output_function_entry (file, name);
25093 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
25096 fputs ("\t.size\t", file);
25097 assemble_name (file, name);
25098 fputs (",24\n\t.type\t.", file);
25099 assemble_name (file, name);
25100 fputs (",@function\n", file);
25101 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
25103 fputs ("\t.globl\t.", file);
25104 assemble_name (file, name);
25109 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25110 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25111 rs6000_output_function_entry (file, name);
25112 fputs (":\n", file);
25116 if (TARGET_RELOCATABLE
25117 && !TARGET_SECURE_PLT
25118 && (get_pool_size () != 0 || crtl->profile)
25123 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
25125 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
25126 fprintf (file, "\t.long ");
25127 assemble_name (file, buf);
25129 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25130 assemble_name (file, buf);
25134 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25135 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25137 if (DEFAULT_ABI == ABI_AIX)
25139 const char *desc_name, *orig_name;
25141 orig_name = (*targetm.strip_name_encoding) (name);
25142 desc_name = orig_name;
25143 while (*desc_name == '.')
25146 if (TREE_PUBLIC (decl))
25147 fprintf (file, "\t.globl %s\n", desc_name);
25149 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25150 fprintf (file, "%s:\n", desc_name);
25151 fprintf (file, "\t.long %s\n", orig_name);
25152 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25153 if (DEFAULT_ABI == ABI_AIX)
25154 fputs ("\t.long 0\n", file);
25155 fprintf (file, "\t.previous\n");
25157 ASM_OUTPUT_LABEL (file, name);
25160 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
25162 rs6000_elf_file_end (void)
25164 #ifdef HAVE_AS_GNU_ATTRIBUTE
25165 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25167 if (rs6000_passes_float)
25168 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25169 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25170 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25172 if (rs6000_passes_vector)
25173 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25174 (TARGET_ALTIVEC_ABI ? 2
25175 : TARGET_SPE_ABI ? 3
25177 if (rs6000_returns_struct)
25178 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25179 aix_struct_return ? 2 : 1);
25182 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25184 file_end_indicate_exec_stack ();
25191 rs6000_xcoff_asm_output_anchor (rtx symbol)
25195 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25196 SYMBOL_REF_BLOCK_OFFSET (symbol));
25197 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25201 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25203 fputs (GLOBAL_ASM_OP, stream);
25204 RS6000_OUTPUT_BASENAME (stream, name);
25205 putc ('\n', stream);
25208 /* A get_unnamed_decl callback, used for read-only sections. PTR
25209 points to the section string variable. */
25212 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25214 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25215 *(const char *const *) directive,
25216 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25219 /* Likewise for read-write sections. */
25222 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25224 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25225 *(const char *const *) directive,
25226 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25229 /* A get_unnamed_section callback, used for switching to toc_section. */
25232 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25234 if (TARGET_MINIMAL_TOC)
25236 /* toc_section is always selected at least once from
25237 rs6000_xcoff_file_start, so this is guaranteed to
25238 always be defined once and only once in each file. */
25239 if (!toc_initialized)
25241 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25242 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25243 toc_initialized = 1;
25245 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25246 (TARGET_32BIT ? "" : ",3"));
25249 fputs ("\t.toc\n", asm_out_file);
25252 /* Implement TARGET_ASM_INIT_SECTIONS. */
25255 rs6000_xcoff_asm_init_sections (void)
25257 read_only_data_section
25258 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25259 &xcoff_read_only_section_name);
25261 private_data_section
25262 = get_unnamed_section (SECTION_WRITE,
25263 rs6000_xcoff_output_readwrite_section_asm_op,
25264 &xcoff_private_data_section_name);
25266 read_only_private_data_section
25267 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25268 &xcoff_private_data_section_name);
25271 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25273 readonly_data_section = read_only_data_section;
25274 exception_section = data_section;
25278 rs6000_xcoff_reloc_rw_mask (void)
25284 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25285 tree decl ATTRIBUTE_UNUSED)
25288 static const char * const suffix[3] = { "PR", "RO", "RW" };
25290 if (flags & SECTION_CODE)
25292 else if (flags & SECTION_WRITE)
25297 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25298 (flags & SECTION_CODE) ? "." : "",
25299 name, suffix[smclass], flags & SECTION_ENTSIZE);
25303 rs6000_xcoff_select_section (tree decl, int reloc,
25304 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25306 if (decl_readonly_section (decl, reloc))
25308 if (TREE_PUBLIC (decl))
25309 return read_only_data_section;
25311 return read_only_private_data_section;
25315 if (TREE_PUBLIC (decl))
25316 return data_section;
25318 return private_data_section;
25323 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25327 /* Use select_section for private and uninitialized data. */
25328 if (!TREE_PUBLIC (decl)
25329 || DECL_COMMON (decl)
25330 || DECL_INITIAL (decl) == NULL_TREE
25331 || DECL_INITIAL (decl) == error_mark_node
25332 || (flag_zero_initialized_in_bss
25333 && initializer_zerop (DECL_INITIAL (decl))))
25336 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25337 name = (*targetm.strip_name_encoding) (name);
25338 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25341 /* Select section for constant in constant pool.
25343 On RS/6000, all constants are in the private read-only data area.
25344 However, if this is being placed in the TOC it must be output as a
25348 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25349 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25351 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25352 return toc_section;
25354 return read_only_private_data_section;
25357 /* Remove any trailing [DS] or the like from the symbol name. */
25359 static const char *
25360 rs6000_xcoff_strip_name_encoding (const char *name)
25365 len = strlen (name);
25366 if (name[len - 1] == ']')
25367 return ggc_alloc_string (name, len - 4);
25372 /* Section attributes. AIX is always PIC. */
25374 static unsigned int
25375 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25377 unsigned int align;
25378 unsigned int flags = default_section_type_flags (decl, name, reloc);
25380 /* Align to at least UNIT size. */
25381 if (flags & SECTION_CODE || !decl)
25382 align = MIN_UNITS_PER_WORD;
25384 /* Increase alignment of large objects if not already stricter. */
25385 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25386 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25387 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25389 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25392 /* Output at beginning of assembler file.
25394 Initialize the section names for the RS/6000 at this point.
25396 Specify filename, including full path, to assembler.
25398 We want to go into the TOC section so at least one .toc will be emitted.
25399 Also, in order to output proper .bs/.es pairs, we need at least one static
25400 [RW] section emitted.
25402 Finally, declare mcount when profiling to make the assembler happy. */
25405 rs6000_xcoff_file_start (void)
25407 rs6000_gen_section_name (&xcoff_bss_section_name,
25408 main_input_filename, ".bss_");
25409 rs6000_gen_section_name (&xcoff_private_data_section_name,
25410 main_input_filename, ".rw_");
25411 rs6000_gen_section_name (&xcoff_read_only_section_name,
25412 main_input_filename, ".ro_");
25414 fputs ("\t.file\t", asm_out_file);
25415 output_quoted_string (asm_out_file, main_input_filename);
25416 fputc ('\n', asm_out_file);
25417 if (write_symbols != NO_DEBUG)
25418 switch_to_section (private_data_section);
25419 switch_to_section (text_section);
25421 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25422 rs6000_file_start ();
25425 /* Output at end of assembler file.
25426 On the RS/6000, referencing data should automatically pull in text. */
25429 rs6000_xcoff_file_end (void)
25431 switch_to_section (text_section);
25432 fputs ("_section_.text:\n", asm_out_file);
25433 switch_to_section (data_section);
25434 fputs (TARGET_32BIT
25435 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25438 #endif /* TARGET_XCOFF */
25440 /* Compute a (partial) cost for rtx X. Return true if the complete
25441 cost has been computed, and false if subexpressions should be
25442 scanned. In either case, *TOTAL contains the cost result. */
25445 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25446 int *total, bool speed)
25448 enum machine_mode mode = GET_MODE (x);
25452 /* On the RS/6000, if it is valid in the insn, it is free. */
25454 if (((outer_code == SET
25455 || outer_code == PLUS
25456 || outer_code == MINUS)
25457 && (satisfies_constraint_I (x)
25458 || satisfies_constraint_L (x)))
25459 || (outer_code == AND
25460 && (satisfies_constraint_K (x)
25462 ? satisfies_constraint_L (x)
25463 : satisfies_constraint_J (x))
25464 || mask_operand (x, mode)
25466 && mask64_operand (x, DImode))))
25467 || ((outer_code == IOR || outer_code == XOR)
25468 && (satisfies_constraint_K (x)
25470 ? satisfies_constraint_L (x)
25471 : satisfies_constraint_J (x))))
25472 || outer_code == ASHIFT
25473 || outer_code == ASHIFTRT
25474 || outer_code == LSHIFTRT
25475 || outer_code == ROTATE
25476 || outer_code == ROTATERT
25477 || outer_code == ZERO_EXTRACT
25478 || (outer_code == MULT
25479 && satisfies_constraint_I (x))
25480 || ((outer_code == DIV || outer_code == UDIV
25481 || outer_code == MOD || outer_code == UMOD)
25482 && exact_log2 (INTVAL (x)) >= 0)
25483 || (outer_code == COMPARE
25484 && (satisfies_constraint_I (x)
25485 || satisfies_constraint_K (x)))
25486 || ((outer_code == EQ || outer_code == NE)
25487 && (satisfies_constraint_I (x)
25488 || satisfies_constraint_K (x)
25490 ? satisfies_constraint_L (x)
25491 : satisfies_constraint_J (x))))
25492 || (outer_code == GTU
25493 && satisfies_constraint_I (x))
25494 || (outer_code == LTU
25495 && satisfies_constraint_P (x)))
25500 else if ((outer_code == PLUS
25501 && reg_or_add_cint_operand (x, VOIDmode))
25502 || (outer_code == MINUS
25503 && reg_or_sub_cint_operand (x, VOIDmode))
25504 || ((outer_code == SET
25505 || outer_code == IOR
25506 || outer_code == XOR)
25508 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25510 *total = COSTS_N_INSNS (1);
25516 if (mode == DImode && code == CONST_DOUBLE)
25518 if ((outer_code == IOR || outer_code == XOR)
25519 && CONST_DOUBLE_HIGH (x) == 0
25520 && (CONST_DOUBLE_LOW (x)
25521 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25526 else if ((outer_code == AND && and64_2_operand (x, DImode))
25527 || ((outer_code == SET
25528 || outer_code == IOR
25529 || outer_code == XOR)
25530 && CONST_DOUBLE_HIGH (x) == 0))
25532 *total = COSTS_N_INSNS (1);
25542 /* When optimizing for size, MEM should be slightly more expensive
25543 than generating address, e.g., (plus (reg) (const)).
25544 L1 cache latency is about two instructions. */
25545 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25554 if (FLOAT_MODE_P (mode))
25555 *total = rs6000_cost->fp;
25557 *total = COSTS_N_INSNS (1);
25561 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25562 && satisfies_constraint_I (XEXP (x, 1)))
25564 if (INTVAL (XEXP (x, 1)) >= -256
25565 && INTVAL (XEXP (x, 1)) <= 255)
25566 *total = rs6000_cost->mulsi_const9;
25568 *total = rs6000_cost->mulsi_const;
25570 else if (mode == SFmode)
25571 *total = rs6000_cost->fp;
25572 else if (FLOAT_MODE_P (mode))
25573 *total = rs6000_cost->dmul;
25574 else if (mode == DImode)
25575 *total = rs6000_cost->muldi;
25577 *total = rs6000_cost->mulsi;
25581 if (mode == SFmode)
25582 *total = rs6000_cost->fp;
25584 *total = rs6000_cost->dmul;
25589 if (FLOAT_MODE_P (mode))
25591 *total = mode == DFmode ? rs6000_cost->ddiv
25592 : rs6000_cost->sdiv;
25599 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25600 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
25602 if (code == DIV || code == MOD)
25604 *total = COSTS_N_INSNS (2);
25607 *total = COSTS_N_INSNS (1);
25611 if (GET_MODE (XEXP (x, 1)) == DImode)
25612 *total = rs6000_cost->divdi;
25614 *total = rs6000_cost->divsi;
25616 /* Add in shift and subtract for MOD. */
25617 if (code == MOD || code == UMOD)
25618 *total += COSTS_N_INSNS (2);
25623 *total = COSTS_N_INSNS (4);
25627 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
25631 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
25635 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
25647 *total = COSTS_N_INSNS (1);
25655 /* Handle mul_highpart. */
25656 if (outer_code == TRUNCATE
25657 && GET_CODE (XEXP (x, 0)) == MULT)
25659 if (mode == DImode)
25660 *total = rs6000_cost->muldi;
25662 *total = rs6000_cost->mulsi;
25665 else if (outer_code == AND)
25668 *total = COSTS_N_INSNS (1);
25673 if (GET_CODE (XEXP (x, 0)) == MEM)
25676 *total = COSTS_N_INSNS (1);
25682 if (!FLOAT_MODE_P (mode))
25684 *total = COSTS_N_INSNS (1);
25690 case UNSIGNED_FLOAT:
25693 case FLOAT_TRUNCATE:
25694 *total = rs6000_cost->fp;
25698 if (mode == DFmode)
25701 *total = rs6000_cost->fp;
25705 switch (XINT (x, 1))
25708 *total = rs6000_cost->fp;
25720 *total = COSTS_N_INSNS (1);
25723 else if (FLOAT_MODE_P (mode)
25724 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
25726 *total = rs6000_cost->fp;
25734 /* Carry bit requires mode == Pmode.
25735 NEG or PLUS already counted so only add one. */
25737 && (outer_code == NEG || outer_code == PLUS))
25739 *total = COSTS_N_INSNS (1);
25742 if (outer_code == SET)
25744 if (XEXP (x, 1) == const0_rtx)
25746 if (TARGET_ISEL && !TARGET_MFCRF)
25747 *total = COSTS_N_INSNS (8);
25749 *total = COSTS_N_INSNS (2);
25752 else if (mode == Pmode)
25754 *total = COSTS_N_INSNS (3);
25763 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
25765 if (TARGET_ISEL && !TARGET_MFCRF)
25766 *total = COSTS_N_INSNS (8);
25768 *total = COSTS_N_INSNS (2);
25772 if (outer_code == COMPARE)
25786 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25789 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
25792 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
25795 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25796 "opno = %d, total = %d, speed = %s, x:\n",
25797 ret ? "complete" : "scan inner",
25798 GET_RTX_NAME (code),
25799 GET_RTX_NAME (outer_code),
25802 speed ? "true" : "false");
25809 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25812 rs6000_debug_address_cost (rtx x, bool speed)
25814 int ret = TARGET_ADDRESS_COST (x, speed);
25816 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
25817 ret, speed ? "true" : "false");
25824 /* A C expression returning the cost of moving data from a register of class
25825 CLASS1 to one of CLASS2. */
25828 rs6000_register_move_cost (enum machine_mode mode,
25829 reg_class_t from, reg_class_t to)
25833 if (TARGET_DEBUG_COST)
25836 /* Moves from/to GENERAL_REGS. */
25837 if (reg_classes_intersect_p (to, GENERAL_REGS)
25838 || reg_classes_intersect_p (from, GENERAL_REGS))
25840 reg_class_t rclass = from;
25842 if (! reg_classes_intersect_p (to, GENERAL_REGS))
25845 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
25846 ret = (rs6000_memory_move_cost (mode, rclass, false)
25847 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
25849 /* It's more expensive to move CR_REGS than CR0_REGS because of the
25851 else if (rclass == CR_REGS)
25854 /* For those processors that have slow LR/CTR moves, make them more
25855 expensive than memory in order to bias spills to memory .*/
25856 else if ((rs6000_cpu == PROCESSOR_POWER6
25857 || rs6000_cpu == PROCESSOR_POWER7)
25858 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
25859 ret = 6 * hard_regno_nregs[0][mode];
25862 /* A move will cost one instruction per GPR moved. */
25863 ret = 2 * hard_regno_nregs[0][mode];
25866 /* If we have VSX, we can easily move between FPR or Altivec registers. */
25867 else if (VECTOR_UNIT_VSX_P (mode)
25868 && reg_classes_intersect_p (to, VSX_REGS)
25869 && reg_classes_intersect_p (from, VSX_REGS))
25870 ret = 2 * hard_regno_nregs[32][mode];
25872 /* Moving between two similar registers is just one instruction. */
25873 else if (reg_classes_intersect_p (to, from))
25874 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
25876 /* Everything else has to go through GENERAL_REGS. */
25878 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
25879 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
25881 if (TARGET_DEBUG_COST)
25883 if (dbg_cost_ctrl == 1)
25885 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
25886 ret, GET_MODE_NAME (mode), reg_class_names[from],
25887 reg_class_names[to]);
25894 /* A C expressions returning the cost of moving data of MODE from a register to
25898 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
25899 bool in ATTRIBUTE_UNUSED)
25903 if (TARGET_DEBUG_COST)
25906 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
25907 ret = 4 * hard_regno_nregs[0][mode];
25908 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
25909 ret = 4 * hard_regno_nregs[32][mode];
25910 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
25911 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
25913 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
25915 if (TARGET_DEBUG_COST)
25917 if (dbg_cost_ctrl == 1)
25919 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
25920 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
25927 /* Returns a code for a target-specific builtin that implements
25928 reciprocal of the function, or NULL_TREE if not available. */
25931 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
25932 bool sqrt ATTRIBUTE_UNUSED)
25934 if (optimize_insn_for_size_p ())
25940 case VSX_BUILTIN_XVSQRTDP:
25941 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
25944 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
25946 case VSX_BUILTIN_XVSQRTSP:
25947 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
25950 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
25959 case BUILT_IN_SQRT:
25960 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
25963 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
25965 case BUILT_IN_SQRTF:
25966 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
25969 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
25976 /* Load up a constant. If the mode is a vector mode, splat the value across
25977 all of the vector elements. */
25980 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
25984 if (mode == SFmode || mode == DFmode)
25986 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
25987 reg = force_reg (mode, d);
25989 else if (mode == V4SFmode)
25991 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
25992 rtvec v = gen_rtvec (4, d, d, d, d);
25993 reg = gen_reg_rtx (mode);
25994 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25996 else if (mode == V2DFmode)
25998 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
25999 rtvec v = gen_rtvec (2, d, d);
26000 reg = gen_reg_rtx (mode);
26001 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26004 gcc_unreachable ();
26009 /* Generate an FMA instruction. */
26012 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
26014 enum machine_mode mode = GET_MODE (target);
26017 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26018 gcc_assert (dst != NULL);
26021 emit_move_insn (target, dst);
26024 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
26027 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
26029 enum machine_mode mode = GET_MODE (target);
26032 /* Altivec does not support fms directly;
26033 generate in terms of fma in that case. */
26034 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
26035 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
26038 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
26039 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26041 gcc_assert (dst != NULL);
26044 emit_move_insn (target, dst);
26047 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
26050 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
26052 enum machine_mode mode = GET_MODE (dst);
26055 /* This is a tad more complicated, since the fnma_optab is for
26056 a different expression: fma(-m1, m2, a), which is the same
26057 thing except in the case of signed zeros.
26059 Fortunately we know that if FMA is supported that FNMSUB is
26060 also supported in the ISA. Just expand it directly. */
26062 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
26064 r = gen_rtx_NEG (mode, a);
26065 r = gen_rtx_FMA (mode, m1, m2, r);
26066 r = gen_rtx_NEG (mode, r);
26067 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
26070 /* Newton-Raphson approximation of floating point divide with just 2 passes
26071 (either single precision floating point, or newer machines with higher
26072 accuracy estimates). Support both scalar and vector divide. Assumes no
26073 trapping math and finite arguments. */
26076 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
26078 enum machine_mode mode = GET_MODE (dst);
26079 rtx x0, e0, e1, y1, u0, v0;
26080 enum insn_code code = optab_handler (smul_optab, mode);
26081 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26082 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
26084 gcc_assert (code != CODE_FOR_nothing);
26086 /* x0 = 1./d estimate */
26087 x0 = gen_reg_rtx (mode);
26088 emit_insn (gen_rtx_SET (VOIDmode, x0,
26089 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26092 e0 = gen_reg_rtx (mode);
26093 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
26095 e1 = gen_reg_rtx (mode);
26096 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
26098 y1 = gen_reg_rtx (mode);
26099 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
26101 u0 = gen_reg_rtx (mode);
26102 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
26104 v0 = gen_reg_rtx (mode);
26105 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
26107 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
26110 /* Newton-Raphson approximation of floating point divide that has a low
26111 precision estimate. Assumes no trapping math and finite arguments. */
26114 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
26116 enum machine_mode mode = GET_MODE (dst);
26117 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
26118 enum insn_code code = optab_handler (smul_optab, mode);
26119 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26121 gcc_assert (code != CODE_FOR_nothing);
26123 one = rs6000_load_constant_and_splat (mode, dconst1);
26125 /* x0 = 1./d estimate */
26126 x0 = gen_reg_rtx (mode);
26127 emit_insn (gen_rtx_SET (VOIDmode, x0,
26128 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26131 e0 = gen_reg_rtx (mode);
26132 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
26134 y1 = gen_reg_rtx (mode);
26135 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
26137 e1 = gen_reg_rtx (mode);
26138 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
26140 y2 = gen_reg_rtx (mode);
26141 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26143 e2 = gen_reg_rtx (mode);
26144 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26146 y3 = gen_reg_rtx (mode);
26147 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26149 u0 = gen_reg_rtx (mode);
26150 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26152 v0 = gen_reg_rtx (mode);
26153 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26155 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26158 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26159 add a reg_note saying that this was a division. Support both scalar and
26160 vector divide. Assumes no trapping math and finite arguments. */
26163 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26165 enum machine_mode mode = GET_MODE (dst);
26167 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26168 rs6000_emit_swdiv_high_precision (dst, n, d);
26170 rs6000_emit_swdiv_low_precision (dst, n, d);
26173 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26176 /* Newton-Raphson approximation of single/double-precision floating point
26177 rsqrt. Assumes no trapping math and finite arguments. */
26180 rs6000_emit_swrsqrt (rtx dst, rtx src)
26182 enum machine_mode mode = GET_MODE (src);
26183 rtx x0 = gen_reg_rtx (mode);
26184 rtx y = gen_reg_rtx (mode);
26185 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26186 REAL_VALUE_TYPE dconst3_2;
26189 enum insn_code code = optab_handler (smul_optab, mode);
26190 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26192 gcc_assert (code != CODE_FOR_nothing);
26194 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26195 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26196 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26198 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26200 /* x0 = rsqrt estimate */
26201 emit_insn (gen_rtx_SET (VOIDmode, x0,
26202 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26205 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26206 rs6000_emit_msub (y, src, halfthree, src);
26208 for (i = 0; i < passes; i++)
26210 rtx x1 = gen_reg_rtx (mode);
26211 rtx u = gen_reg_rtx (mode);
26212 rtx v = gen_reg_rtx (mode);
26214 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26215 emit_insn (gen_mul (u, x0, x0));
26216 rs6000_emit_nmsub (v, y, u, halfthree);
26217 emit_insn (gen_mul (x1, x0, v));
26221 emit_move_insn (dst, x0);
26225 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26226 (Power7) targets. DST is the target, and SRC is the argument operand. */
26229 rs6000_emit_popcount (rtx dst, rtx src)
26231 enum machine_mode mode = GET_MODE (dst);
26234 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26235 if (TARGET_POPCNTD)
26237 if (mode == SImode)
26238 emit_insn (gen_popcntdsi2 (dst, src));
26240 emit_insn (gen_popcntddi2 (dst, src));
26244 tmp1 = gen_reg_rtx (mode);
26246 if (mode == SImode)
26248 emit_insn (gen_popcntbsi2 (tmp1, src));
26249 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26251 tmp2 = force_reg (SImode, tmp2);
26252 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26256 emit_insn (gen_popcntbdi2 (tmp1, src));
26257 tmp2 = expand_mult (DImode, tmp1,
26258 GEN_INT ((HOST_WIDE_INT)
26259 0x01010101 << 32 | 0x01010101),
26261 tmp2 = force_reg (DImode, tmp2);
26262 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26267 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26268 target, and SRC is the argument operand. */
26271 rs6000_emit_parity (rtx dst, rtx src)
26273 enum machine_mode mode = GET_MODE (dst);
26276 tmp = gen_reg_rtx (mode);
26278 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26281 if (mode == SImode)
26283 emit_insn (gen_popcntbsi2 (tmp, src));
26284 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26288 emit_insn (gen_popcntbdi2 (tmp, src));
26289 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26294 if (mode == SImode)
26296 /* Is mult+shift >= shift+xor+shift+xor? */
26297 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26299 rtx tmp1, tmp2, tmp3, tmp4;
26301 tmp1 = gen_reg_rtx (SImode);
26302 emit_insn (gen_popcntbsi2 (tmp1, src));
26304 tmp2 = gen_reg_rtx (SImode);
26305 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26306 tmp3 = gen_reg_rtx (SImode);
26307 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26309 tmp4 = gen_reg_rtx (SImode);
26310 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26311 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26314 rs6000_emit_popcount (tmp, src);
26315 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26319 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26320 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26322 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26324 tmp1 = gen_reg_rtx (DImode);
26325 emit_insn (gen_popcntbdi2 (tmp1, src));
26327 tmp2 = gen_reg_rtx (DImode);
26328 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26329 tmp3 = gen_reg_rtx (DImode);
26330 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26332 tmp4 = gen_reg_rtx (DImode);
26333 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26334 tmp5 = gen_reg_rtx (DImode);
26335 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26337 tmp6 = gen_reg_rtx (DImode);
26338 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26339 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26342 rs6000_emit_popcount (tmp, src);
26343 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26347 /* Expand an Altivec constant permutation. Return true if we match
26348 an efficient implementation; false to fall back to VPERM. */
26351 altivec_expand_vec_perm_const (rtx operands[4])
26353 struct altivec_perm_insn {
26354 enum insn_code impl;
26355 unsigned char perm[16];
26357 static const struct altivec_perm_insn patterns[] = {
26358 { CODE_FOR_altivec_vpkuhum,
26359 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26360 { CODE_FOR_altivec_vpkuwum,
26361 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26362 { CODE_FOR_altivec_vmrghb,
26363 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26364 { CODE_FOR_altivec_vmrghh,
26365 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26366 { CODE_FOR_altivec_vmrghw,
26367 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26368 { CODE_FOR_altivec_vmrglb,
26369 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26370 { CODE_FOR_altivec_vmrglh,
26371 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26372 { CODE_FOR_altivec_vmrglw,
26373 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26376 unsigned int i, j, elt, which;
26377 unsigned char perm[16];
26378 rtx target, op0, op1, sel, x;
26381 target = operands[0];
26386 /* Unpack the constant selector. */
26387 for (i = which = 0; i < 16; ++i)
26389 rtx e = XVECEXP (sel, 0, i);
26390 elt = INTVAL (e) & 31;
26391 which |= (elt < 16 ? 1 : 2);
26395 /* Simplify the constant selector based on operands. */
26399 gcc_unreachable ();
26403 if (!rtx_equal_p (op0, op1))
26408 for (i = 0; i < 16; ++i)
26420 /* Look for splat patterns. */
26425 for (i = 0; i < 16; ++i)
26426 if (perm[i] != elt)
26430 emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
26436 for (i = 0; i < 16; i += 2)
26437 if (perm[i] != elt || perm[i + 1] != elt + 1)
26441 x = gen_reg_rtx (V8HImode);
26442 emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
26443 GEN_INT (elt / 2)));
26444 emit_move_insn (target, gen_lowpart (V16QImode, x));
26451 for (i = 0; i < 16; i += 4)
26453 || perm[i + 1] != elt + 1
26454 || perm[i + 2] != elt + 2
26455 || perm[i + 3] != elt + 3)
26459 x = gen_reg_rtx (V4SImode);
26460 emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
26461 GEN_INT (elt / 4)));
26462 emit_move_insn (target, gen_lowpart (V16QImode, x));
26468 /* Look for merge and pack patterns. */
26469 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
26473 elt = patterns[j].perm[0];
26474 if (perm[0] == elt)
26476 else if (perm[0] == elt + 16)
26480 for (i = 1; i < 16; ++i)
26482 elt = patterns[j].perm[i];
26484 elt = (elt >= 16 ? elt - 16 : elt + 16);
26485 else if (one_vec && elt >= 16)
26487 if (perm[i] != elt)
26492 enum insn_code icode = patterns[j].impl;
26493 enum machine_mode omode = insn_data[icode].operand[0].mode;
26494 enum machine_mode imode = insn_data[icode].operand[1].mode;
26497 x = op0, op0 = op1, op1 = x;
26498 if (imode != V16QImode)
26500 op0 = gen_lowpart (imode, op0);
26501 op1 = gen_lowpart (imode, op1);
26503 if (omode == V16QImode)
26506 x = gen_reg_rtx (omode);
26507 emit_insn (GEN_FCN (icode) (x, op0, op1));
26508 if (omode != V16QImode)
26509 emit_move_insn (target, gen_lowpart (V16QImode, x));
26517 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26518 Return true if we match an efficient implementation. */
26521 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
26522 unsigned char perm0, unsigned char perm1)
26526 /* If both selectors come from the same operand, fold to single op. */
26527 if ((perm0 & 2) == (perm1 & 2))
26534 /* If both operands are equal, fold to simpler permutation. */
26535 if (rtx_equal_p (op0, op1))
26538 perm1 = (perm1 & 1) + 2;
26540 /* If the first selector comes from the second operand, swap. */
26541 else if (perm0 & 2)
26547 x = op0, op0 = op1, op1 = x;
26549 /* If the second selector does not come from the second operand, fail. */
26550 else if ((perm1 & 2) == 0)
26554 if (target != NULL)
26556 enum machine_mode vmode, dmode;
26559 vmode = GET_MODE (target);
26560 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
26561 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
26563 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
26564 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
26565 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
26566 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26572 rs6000_expand_vec_perm_const (rtx operands[4])
26574 rtx target, op0, op1, sel;
26575 unsigned char perm0, perm1;
26577 target = operands[0];
26582 /* Unpack the constant selector. */
26583 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
26584 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
26586 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
26589 /* Test whether a constant permutation is supported. */
26592 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
26593 const unsigned char *sel)
26595 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
26596 if (TARGET_ALTIVEC)
26599 /* Check for ps_merge* or evmerge* insns. */
26600 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
26601 || (TARGET_SPE && vmode == V2SImode))
26603 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
26604 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
26605 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
26611 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
26614 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
26615 enum machine_mode vmode, unsigned nelt, rtx perm[])
26617 enum machine_mode imode;
26621 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
26623 imode = GET_MODE_INNER (vmode);
26624 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
26625 imode = mode_for_vector (imode, nelt);
26628 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
26629 x = expand_vec_perm (vmode, op0, op1, x, target);
26631 emit_move_insn (target, x);
26634 /* Expand an extract even operation. */
26637 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
26639 enum machine_mode vmode = GET_MODE (target);
26640 unsigned i, nelt = GET_MODE_NUNITS (vmode);
26643 for (i = 0; i < nelt; i++)
26644 perm[i] = GEN_INT (i * 2);
26646 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26649 /* Expand a vector interleave operation. */
26652 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
26654 enum machine_mode vmode = GET_MODE (target);
26655 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
26658 high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
26659 for (i = 0; i < nelt / 2; i++)
26661 perm[i * 2] = GEN_INT (i + high);
26662 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
26665 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26668 /* Return an RTX representing where to find the function value of a
26669 function returning MODE. */
26671 rs6000_complex_function_value (enum machine_mode mode)
26673 unsigned int regno;
26675 enum machine_mode inner = GET_MODE_INNER (mode);
26676 unsigned int inner_bytes = GET_MODE_SIZE (inner);
26678 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26679 regno = FP_ARG_RETURN;
26682 regno = GP_ARG_RETURN;
26684 /* 32-bit is OK since it'll go in r3/r4. */
26685 if (TARGET_32BIT && inner_bytes >= 4)
26686 return gen_rtx_REG (mode, regno);
26689 if (inner_bytes >= 8)
26690 return gen_rtx_REG (mode, regno);
26692 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
26694 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
26695 GEN_INT (inner_bytes));
26696 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
26699 /* Target hook for TARGET_FUNCTION_VALUE.
26701 On the SPE, both FPs and vectors are returned in r3.
26703 On RS/6000 an integer value is in r3 and a floating-point value is in
26704 fp1, unless -msoft-float. */
26707 rs6000_function_value (const_tree valtype,
26708 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
26709 bool outgoing ATTRIBUTE_UNUSED)
26711 enum machine_mode mode;
26712 unsigned int regno;
26714 /* Special handling for structs in darwin64. */
26716 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
26718 CUMULATIVE_ARGS valcum;
26722 valcum.fregno = FP_ARG_MIN_REG;
26723 valcum.vregno = ALTIVEC_ARG_MIN_REG;
26724 /* Do a trial code generation as if this were going to be passed as
26725 an argument; if any part goes in memory, we return NULL. */
26726 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
26729 /* Otherwise fall through to standard ABI rules. */
26732 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
26734 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26735 return gen_rtx_PARALLEL (DImode,
26737 gen_rtx_EXPR_LIST (VOIDmode,
26738 gen_rtx_REG (SImode, GP_ARG_RETURN),
26740 gen_rtx_EXPR_LIST (VOIDmode,
26741 gen_rtx_REG (SImode,
26742 GP_ARG_RETURN + 1),
26745 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
26747 return gen_rtx_PARALLEL (DCmode,
26749 gen_rtx_EXPR_LIST (VOIDmode,
26750 gen_rtx_REG (SImode, GP_ARG_RETURN),
26752 gen_rtx_EXPR_LIST (VOIDmode,
26753 gen_rtx_REG (SImode,
26754 GP_ARG_RETURN + 1),
26756 gen_rtx_EXPR_LIST (VOIDmode,
26757 gen_rtx_REG (SImode,
26758 GP_ARG_RETURN + 2),
26760 gen_rtx_EXPR_LIST (VOIDmode,
26761 gen_rtx_REG (SImode,
26762 GP_ARG_RETURN + 3),
26766 mode = TYPE_MODE (valtype);
26767 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
26768 || POINTER_TYPE_P (valtype))
26769 mode = TARGET_32BIT ? SImode : DImode;
26771 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26772 /* _Decimal128 must use an even/odd register pair. */
26773 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26774 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
26775 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
26776 regno = FP_ARG_RETURN;
26777 else if (TREE_CODE (valtype) == COMPLEX_TYPE
26778 && targetm.calls.split_complex_arg)
26779 return rs6000_complex_function_value (mode);
26780 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26781 return register is used in both cases, and we won't see V2DImode/V2DFmode
26782 for pure altivec, combine the two cases. */
26783 else if (TREE_CODE (valtype) == VECTOR_TYPE
26784 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
26785 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
26786 regno = ALTIVEC_ARG_RETURN;
26787 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26788 && (mode == DFmode || mode == DCmode
26789 || mode == TFmode || mode == TCmode))
26790 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26792 regno = GP_ARG_RETURN;
26794 return gen_rtx_REG (mode, regno);
26797 /* Define how to find the value returned by a library function
26798 assuming the value has mode MODE. */
26800 rs6000_libcall_value (enum machine_mode mode)
26802 unsigned int regno;
26804 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
26806 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26807 return gen_rtx_PARALLEL (DImode,
26809 gen_rtx_EXPR_LIST (VOIDmode,
26810 gen_rtx_REG (SImode, GP_ARG_RETURN),
26812 gen_rtx_EXPR_LIST (VOIDmode,
26813 gen_rtx_REG (SImode,
26814 GP_ARG_RETURN + 1),
26818 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26819 /* _Decimal128 must use an even/odd register pair. */
26820 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26821 else if (SCALAR_FLOAT_MODE_P (mode)
26822 && TARGET_HARD_FLOAT && TARGET_FPRS
26823 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
26824 regno = FP_ARG_RETURN;
26825 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26826 return register is used in both cases, and we won't see V2DImode/V2DFmode
26827 for pure altivec, combine the two cases. */
26828 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
26829 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
26830 regno = ALTIVEC_ARG_RETURN;
26831 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
26832 return rs6000_complex_function_value (mode);
26833 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26834 && (mode == DFmode || mode == DCmode
26835 || mode == TFmode || mode == TCmode))
26836 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26838 regno = GP_ARG_RETURN;
26840 return gen_rtx_REG (mode, regno);
26844 /* Given FROM and TO register numbers, say whether this elimination is allowed.
26845 Frame pointer elimination is automatically handled.
26847 For the RS/6000, if frame pointer elimination is being done, we would like
26848 to convert ap into fp, not sp.
26850 We need r30 if -mminimal-toc was specified, and there are constant pool
26854 rs6000_can_eliminate (const int from, const int to)
26856 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
26857 ? ! frame_pointer_needed
26858 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
26859 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
26863 /* Define the offset between two registers, FROM to be eliminated and its
26864 replacement TO, at the start of a routine. */
26866 rs6000_initial_elimination_offset (int from, int to)
26868 rs6000_stack_t *info = rs6000_stack_info ();
26869 HOST_WIDE_INT offset;
26871 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26872 offset = info->push_p ? 0 : -info->total_size;
26873 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26875 offset = info->push_p ? 0 : -info->total_size;
26876 if (FRAME_GROWS_DOWNWARD)
26877 offset += info->fixed_size + info->vars_size + info->parm_size;
26879 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26880 offset = FRAME_GROWS_DOWNWARD
26881 ? info->fixed_size + info->vars_size + info->parm_size
26883 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26884 offset = info->total_size;
26885 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26886 offset = info->push_p ? info->total_size : 0;
26887 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
26890 gcc_unreachable ();
26896 rs6000_dwarf_register_span (rtx reg)
26900 unsigned regno = REGNO (reg);
26901 enum machine_mode mode = GET_MODE (reg);
26905 && (SPE_VECTOR_MODE (GET_MODE (reg))
26906 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
26907 && mode != SFmode && mode != SDmode && mode != SCmode)))
26912 regno = REGNO (reg);
26914 /* The duality of the SPE register size wreaks all kinds of havoc.
26915 This is a way of distinguishing r0 in 32-bits from r0 in
26917 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
26918 gcc_assert (words <= 4);
26919 for (i = 0; i < words; i++, regno++)
26921 if (BYTES_BIG_ENDIAN)
26923 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
26924 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
26928 parts[2 * i] = gen_rtx_REG (SImode, regno);
26929 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
26933 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
26936 /* Fill in sizes for SPE register high parts in table used by unwinder. */
26939 rs6000_init_dwarf_reg_sizes_extra (tree address)
26944 enum machine_mode mode = TYPE_MODE (char_type_node);
26945 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
26946 rtx mem = gen_rtx_MEM (BLKmode, addr);
26947 rtx value = gen_int_mode (4, mode);
26949 for (i = 1201; i < 1232; i++)
26951 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
26952 HOST_WIDE_INT offset
26953 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
26955 emit_move_insn (adjust_address (mem, mode, offset), value);
26960 /* Map internal gcc register numbers to DWARF2 register numbers. */
26963 rs6000_dbx_register_number (unsigned int regno)
26965 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
26967 if (regno == MQ_REGNO)
26969 if (regno == LR_REGNO)
26971 if (regno == CTR_REGNO)
26973 if (CR_REGNO_P (regno))
26974 return regno - CR0_REGNO + 86;
26975 if (regno == CA_REGNO)
26976 return 101; /* XER */
26977 if (ALTIVEC_REGNO_P (regno))
26978 return regno - FIRST_ALTIVEC_REGNO + 1124;
26979 if (regno == VRSAVE_REGNO)
26981 if (regno == VSCR_REGNO)
26983 if (regno == SPE_ACC_REGNO)
26985 if (regno == SPEFSCR_REGNO)
26987 /* SPE high reg number. We get these values of regno from
26988 rs6000_dwarf_register_span. */
26989 gcc_assert (regno >= 1200 && regno < 1232);
26993 /* target hook eh_return_filter_mode */
26994 static enum machine_mode
26995 rs6000_eh_return_filter_mode (void)
26997 return TARGET_32BIT ? SImode : word_mode;
27000 /* Target hook for scalar_mode_supported_p. */
27002 rs6000_scalar_mode_supported_p (enum machine_mode mode)
27004 if (DECIMAL_FLOAT_MODE_P (mode))
27005 return default_decimal_float_supported_p ();
27007 return default_scalar_mode_supported_p (mode);
27010 /* Target hook for vector_mode_supported_p. */
27012 rs6000_vector_mode_supported_p (enum machine_mode mode)
27015 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
27018 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
27021 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
27028 /* Target hook for invalid_arg_for_unprototyped_fn. */
27029 static const char *
27030 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
27032 return (!rs6000_darwin64_abi
27034 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
27035 && (funcdecl == NULL_TREE
27036 || (TREE_CODE (funcdecl) == FUNCTION_DECL
27037 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
27038 ? N_("AltiVec argument passed to unprototyped function")
27042 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27043 setup by using __stack_chk_fail_local hidden function instead of
27044 calling __stack_chk_fail directly. Otherwise it is better to call
27045 __stack_chk_fail directly. */
27047 static tree ATTRIBUTE_UNUSED
27048 rs6000_stack_protect_fail (void)
27050 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
27051 ? default_hidden_stack_protect_fail ()
27052 : default_external_stack_protect_fail ();
27056 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
27057 int num_operands ATTRIBUTE_UNUSED)
27059 if (rs6000_warn_cell_microcode)
27062 int insn_code_number = recog_memoized (insn);
27063 location_t location = locator_location (INSN_LOCATOR (insn));
27065 /* Punt on insns we cannot recognize. */
27066 if (insn_code_number < 0)
27069 temp = get_insn_template (insn_code_number, insn);
27071 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
27072 warning_at (location, OPT_mwarn_cell_microcode,
27073 "emitting microcode insn %s\t[%s] #%d",
27074 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27075 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
27076 warning_at (location, OPT_mwarn_cell_microcode,
27077 "emitting conditional microcode insn %s\t[%s] #%d",
27078 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27083 /* Mask options that we want to support inside of attribute((target)) and
27084 #pragma GCC target operations. Note, we do not include things like
27085 64/32-bit, endianess, hard/soft floating point, etc. that would have
27086 different calling sequences. */
27088 struct rs6000_opt_mask {
27089 const char *name; /* option name */
27090 int mask; /* mask to set */
27091 bool invert; /* invert sense of mask */
27092 bool valid_target; /* option is a target option */
27095 static struct rs6000_opt_mask const rs6000_opt_masks[] =
27097 { "altivec", MASK_ALTIVEC, false, true },
27098 { "cmpb", MASK_CMPB, false, true },
27099 { "dlmzb", MASK_DLMZB, false, true },
27100 { "fprnd", MASK_FPRND, false, true },
27101 { "hard-dfp", MASK_DFP, false, true },
27102 { "isel", MASK_ISEL, false, true },
27103 { "mfcrf", MASK_MFCRF, false, true },
27104 { "mfpgpr", MASK_MFPGPR, false, true },
27105 { "mulhw", MASK_MULHW, false, true },
27106 { "multiple", MASK_MULTIPLE, false, true },
27107 { "update", MASK_NO_UPDATE, true , true },
27108 { "popcntb", MASK_POPCNTB, false, true },
27109 { "popcntd", MASK_POPCNTD, false, true },
27110 { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
27111 { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
27112 { "recip-precision", MASK_RECIP_PRECISION, false, true },
27113 { "string", MASK_STRING, false, true },
27114 { "vsx", MASK_VSX, false, true },
27117 { "aix64", MASK_64BIT, false, false },
27118 { "aix32", MASK_64BIT, true, false },
27120 { "64", MASK_64BIT, false, false },
27121 { "32", MASK_64BIT, true, false },
27125 { "eabi", MASK_EABI, false, false },
27127 #ifdef MASK_LITTLE_ENDIAN
27128 { "little", MASK_LITTLE_ENDIAN, false, false },
27129 { "big", MASK_LITTLE_ENDIAN, true, false },
27131 #ifdef MASK_RELOCATABLE
27132 { "relocatable", MASK_RELOCATABLE, false, false },
27134 #ifdef MASK_STRICT_ALIGN
27135 { "strict-align", MASK_STRICT_ALIGN, false, false },
27137 { "power", MASK_POWER, false, false },
27138 { "power2", MASK_POWER2, false, false },
27139 { "powerpc", MASK_POWERPC, false, false },
27140 { "soft-float", MASK_SOFT_FLOAT, false, false },
27141 { "string", MASK_STRING, false, false },
27144 /* Builtin mask mapping for printing the flags. */
27145 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27147 { "altivec", RS6000_BTM_ALTIVEC, false, false },
27148 { "vsx", RS6000_BTM_VSX, false, false },
27149 { "spe", RS6000_BTM_SPE, false, false },
27150 { "paired", RS6000_BTM_PAIRED, false, false },
27151 { "fre", RS6000_BTM_FRE, false, false },
27152 { "fres", RS6000_BTM_FRES, false, false },
27153 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
27154 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
27155 { "popcntd", RS6000_BTM_POPCNTD, false, false },
27156 { "powerpc", RS6000_BTM_POWERPC, false, false },
27157 { "cell", RS6000_BTM_CELL, false, false },
27160 /* Option variables that we want to support inside attribute((target)) and
27161 #pragma GCC target operations. */
27163 struct rs6000_opt_var {
27164 const char *name; /* option name */
27165 size_t global_offset; /* offset of the option in global_options. */
27166 size_t target_offset; /* offset of the option in target optiosn. */
27169 static struct rs6000_opt_var const rs6000_opt_vars[] =
27172 offsetof (struct gcc_options, x_TARGET_FRIZ),
27173 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27174 { "avoid-indexed-addresses",
27175 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27176 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27178 offsetof (struct gcc_options, x_rs6000_paired_float),
27179 offsetof (struct cl_target_option, x_rs6000_paired_float), },
27181 offsetof (struct gcc_options, x_rs6000_default_long_calls),
27182 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27185 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27186 parsing. Return true if there were no errors. */
27189 rs6000_inner_target_options (tree args, bool attr_p)
27193 if (args == NULL_TREE)
27196 else if (TREE_CODE (args) == STRING_CST)
27198 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27201 while ((q = strtok (p, ",")) != NULL)
27203 bool error_p = false;
27204 bool not_valid_p = false;
27205 const char *cpu_opt = NULL;
27208 if (strncmp (q, "cpu=", 4) == 0)
27210 int cpu_index = rs6000_cpu_name_lookup (q+4);
27211 if (cpu_index >= 0)
27212 rs6000_cpu_index = cpu_index;
27219 else if (strncmp (q, "tune=", 5) == 0)
27221 int tune_index = rs6000_cpu_name_lookup (q+5);
27222 if (tune_index >= 0)
27223 rs6000_tune_index = tune_index;
27233 bool invert = false;
27237 if (strncmp (r, "no-", 3) == 0)
27243 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27244 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27246 int mask = rs6000_opt_masks[i].mask;
27248 if (!rs6000_opt_masks[i].valid_target)
27249 not_valid_p = true;
27253 target_flags_explicit |= mask;
27255 /* VSX needs altivec, so -mvsx automagically sets
27257 if (mask == MASK_VSX && !invert)
27258 mask |= MASK_ALTIVEC;
27260 if (rs6000_opt_masks[i].invert)
27264 target_flags &= ~mask;
27266 target_flags |= mask;
27271 if (error_p && !not_valid_p)
27273 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27274 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27276 size_t j = rs6000_opt_vars[i].global_offset;
27277 *((int *) ((char *)&global_options + j)) = !invert;
27286 const char *eprefix, *esuffix;
27291 eprefix = "__attribute__((__target__(";
27296 eprefix = "#pragma GCC target ";
27301 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27303 else if (not_valid_p)
27304 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27306 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27311 else if (TREE_CODE (args) == TREE_LIST)
27315 tree value = TREE_VALUE (args);
27318 bool ret2 = rs6000_inner_target_options (value, attr_p);
27322 args = TREE_CHAIN (args);
27324 while (args != NULL_TREE);
27328 gcc_unreachable ();
27333 /* Print out the target options as a list for -mdebug=target. */
27336 rs6000_debug_target_options (tree args, const char *prefix)
27338 if (args == NULL_TREE)
27339 fprintf (stderr, "%s<NULL>", prefix);
27341 else if (TREE_CODE (args) == STRING_CST)
27343 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27346 while ((q = strtok (p, ",")) != NULL)
27349 fprintf (stderr, "%s\"%s\"", prefix, q);
27354 else if (TREE_CODE (args) == TREE_LIST)
27358 tree value = TREE_VALUE (args);
27361 rs6000_debug_target_options (value, prefix);
27364 args = TREE_CHAIN (args);
27366 while (args != NULL_TREE);
27370 gcc_unreachable ();
27376 /* Hook to validate attribute((target("..."))). */
27379 rs6000_valid_attribute_p (tree fndecl,
27380 tree ARG_UNUSED (name),
27384 struct cl_target_option cur_target;
27386 tree old_optimize = build_optimization_node ();
27387 tree new_target, new_optimize;
27388 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27390 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27392 if (TARGET_DEBUG_TARGET)
27394 tree tname = DECL_NAME (fndecl);
27395 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27397 fprintf (stderr, "function: %.*s\n",
27398 (int) IDENTIFIER_LENGTH (tname),
27399 IDENTIFIER_POINTER (tname));
27401 fprintf (stderr, "function: unknown\n");
27403 fprintf (stderr, "args:");
27404 rs6000_debug_target_options (args, " ");
27405 fprintf (stderr, "\n");
27408 fprintf (stderr, "flags: 0x%x\n", flags);
27410 fprintf (stderr, "--------------------\n");
27413 old_optimize = build_optimization_node ();
27414 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27416 /* If the function changed the optimization levels as well as setting target
27417 options, start with the optimizations specified. */
27418 if (func_optimize && func_optimize != old_optimize)
27419 cl_optimization_restore (&global_options,
27420 TREE_OPTIMIZATION (func_optimize));
27422 /* The target attributes may also change some optimization flags, so update
27423 the optimization options if necessary. */
27424 cl_target_option_save (&cur_target, &global_options);
27425 rs6000_cpu_index = rs6000_tune_index = -1;
27426 ret = rs6000_inner_target_options (args, true);
27428 /* Set up any additional state. */
27431 ret = rs6000_option_override_internal (false);
27432 new_target = build_target_option_node ();
27437 new_optimize = build_optimization_node ();
27444 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
27446 if (old_optimize != new_optimize)
27447 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
27450 cl_target_option_restore (&global_options, &cur_target);
27452 if (old_optimize != new_optimize)
27453 cl_optimization_restore (&global_options,
27454 TREE_OPTIMIZATION (old_optimize));
27460 /* Hook to validate the current #pragma GCC target and set the state, and
27461 update the macros based on what was changed. If ARGS is NULL, then
27462 POP_TARGET is used to reset the options. */
27465 rs6000_pragma_target_parse (tree args, tree pop_target)
27467 tree prev_tree = build_target_option_node ();
27469 struct cl_target_option *prev_opt, *cur_opt;
27470 unsigned prev_bumask, cur_bumask, diff_bumask;
27471 int prev_flags, cur_flags, diff_flags;
27473 if (TARGET_DEBUG_TARGET)
27475 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27476 fprintf (stderr, "args:");
27477 rs6000_debug_target_options (args, " ");
27478 fprintf (stderr, "\n");
27482 fprintf (stderr, "pop_target:\n");
27483 debug_tree (pop_target);
27486 fprintf (stderr, "pop_target: <NULL>\n");
27488 fprintf (stderr, "--------------------\n");
27493 cur_tree = ((pop_target)
27495 : target_option_default_node);
27496 cl_target_option_restore (&global_options,
27497 TREE_TARGET_OPTION (cur_tree));
27501 rs6000_cpu_index = rs6000_tune_index = -1;
27502 if (!rs6000_inner_target_options (args, false)
27503 || !rs6000_option_override_internal (false)
27504 || (cur_tree = build_target_option_node ()) == NULL_TREE)
27506 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27507 fprintf (stderr, "invalid pragma\n");
27513 target_option_current_node = cur_tree;
27515 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27516 change the macros that are defined. */
27517 if (rs6000_target_modify_macros_ptr)
27519 prev_opt = TREE_TARGET_OPTION (prev_tree);
27520 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27521 prev_flags = prev_opt->x_target_flags;
27523 cur_opt = TREE_TARGET_OPTION (cur_tree);
27524 cur_flags = cur_opt->x_target_flags;
27525 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27527 diff_bumask = (prev_bumask ^ cur_bumask);
27528 diff_flags = (prev_flags ^ cur_flags);
27530 if ((diff_flags != 0) || (diff_bumask != 0))
27532 /* Delete old macros. */
27533 rs6000_target_modify_macros_ptr (false,
27534 prev_flags & diff_flags,
27535 prev_bumask & diff_bumask);
27537 /* Define new macros. */
27538 rs6000_target_modify_macros_ptr (true,
27539 cur_flags & diff_flags,
27540 cur_bumask & diff_bumask);
27548 /* Remember the last target of rs6000_set_current_function. */
27549 static GTY(()) tree rs6000_previous_fndecl;
27551 /* Establish appropriate back-end context for processing the function
27552 FNDECL. The argument might be NULL to indicate processing at top
27553 level, outside of any function scope. */
27555 rs6000_set_current_function (tree fndecl)
27557 tree old_tree = (rs6000_previous_fndecl
27558 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
27561 tree new_tree = (fndecl
27562 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
27565 if (TARGET_DEBUG_TARGET)
27567 bool print_final = false;
27568 fprintf (stderr, "\n==================== rs6000_set_current_function");
27571 fprintf (stderr, ", fndecl %s (%p)",
27572 (DECL_NAME (fndecl)
27573 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
27574 : "<unknown>"), (void *)fndecl);
27576 if (rs6000_previous_fndecl)
27577 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
27579 fprintf (stderr, "\n");
27582 fprintf (stderr, "\nnew fndecl target specific options:\n");
27583 debug_tree (new_tree);
27584 print_final = true;
27589 fprintf (stderr, "\nold fndecl target specific options:\n");
27590 debug_tree (old_tree);
27591 print_final = true;
27595 fprintf (stderr, "--------------------\n");
27598 /* Only change the context if the function changes. This hook is called
27599 several times in the course of compiling a function, and we don't want to
27600 slow things down too much or call target_reinit when it isn't safe. */
27601 if (fndecl && fndecl != rs6000_previous_fndecl)
27603 rs6000_previous_fndecl = fndecl;
27604 if (old_tree == new_tree)
27609 cl_target_option_restore (&global_options,
27610 TREE_TARGET_OPTION (new_tree));
27616 struct cl_target_option *def
27617 = TREE_TARGET_OPTION (target_option_current_node);
27619 cl_target_option_restore (&global_options, def);
27626 /* Save the current options */
27629 rs6000_function_specific_save (struct cl_target_option *ptr)
27631 ptr->rs6000_target_flags_explicit = target_flags_explicit;
27634 /* Restore the current options */
27637 rs6000_function_specific_restore (struct cl_target_option *ptr)
27639 target_flags_explicit = ptr->rs6000_target_flags_explicit;
27640 (void) rs6000_option_override_internal (false);
27643 /* Print the current options */
27646 rs6000_function_specific_print (FILE *file, int indent,
27647 struct cl_target_option *ptr)
27650 int flags = ptr->x_target_flags;
27651 unsigned bu_mask = ptr->x_rs6000_builtin_mask;
27653 /* Print the various mask options. */
27654 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27655 if ((flags & rs6000_opt_masks[i].mask) != 0)
27657 flags &= ~ rs6000_opt_masks[i].mask;
27658 fprintf (file, "%*s-m%s%s\n", indent, "",
27659 rs6000_opt_masks[i].invert ? "no-" : "",
27660 rs6000_opt_masks[i].name);
27663 /* Print the various options that are variables. */
27664 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27666 size_t j = rs6000_opt_vars[i].target_offset;
27667 if (((signed char *) ptr)[j])
27668 fprintf (file, "%*s-m%s\n", indent, "",
27669 rs6000_opt_vars[i].name);
27672 /* Print the various builtin flags. */
27673 fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
27674 for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
27675 if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
27677 fprintf (file, "%*s%s builtins supported\n", indent, "",
27678 rs6000_builtin_mask_names[i].name);
27683 /* Hook to determine if one function can safely inline another. */
27686 rs6000_can_inline_p (tree caller, tree callee)
27689 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
27690 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
27692 /* If callee has no option attributes, then it is ok to inline. */
27696 /* If caller has no option attributes, but callee does then it is not ok to
27698 else if (!caller_tree)
27703 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
27704 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
27706 /* Callee's options should a subset of the caller's, i.e. a vsx function
27707 can inline an altivec function but a non-vsx function can't inline a
27709 if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
27710 == callee_opts->x_target_flags)
27714 if (TARGET_DEBUG_TARGET)
27715 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27716 (DECL_NAME (caller)
27717 ? IDENTIFIER_POINTER (DECL_NAME (caller))
27719 (DECL_NAME (callee)
27720 ? IDENTIFIER_POINTER (DECL_NAME (callee))
27722 (ret ? "can" : "cannot"));
27727 /* Allocate a stack temp and fixup the address so it meets the particular
27728 memory requirements (either offetable or REG+REG addressing). */
27731 rs6000_allocate_stack_temp (enum machine_mode mode,
27732 bool offsettable_p,
27735 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
27736 rtx addr = XEXP (stack, 0);
27737 int strict_p = (reload_in_progress || reload_completed);
27739 if (!legitimate_indirect_address_p (addr, strict_p))
27742 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
27743 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27745 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
27746 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27752 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27753 to such a form to deal with memory reference instructions like STFIWX that
27754 only take reg+reg addressing. */
27757 rs6000_address_for_fpconvert (rtx x)
27759 int strict_p = (reload_in_progress || reload_completed);
27762 gcc_assert (MEM_P (x));
27763 addr = XEXP (x, 0);
27764 if (! legitimate_indirect_address_p (addr, strict_p)
27765 && ! legitimate_indexed_address_p (addr, strict_p))
27767 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
27769 rtx reg = XEXP (addr, 0);
27770 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
27771 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
27772 gcc_assert (REG_P (reg));
27773 emit_insn (gen_add3_insn (reg, reg, size_rtx));
27776 else if (GET_CODE (addr) == PRE_MODIFY)
27778 rtx reg = XEXP (addr, 0);
27779 rtx expr = XEXP (addr, 1);
27780 gcc_assert (REG_P (reg));
27781 gcc_assert (GET_CODE (expr) == PLUS);
27782 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
27786 x = replace_equiv_address (x, copy_addr_to_reg (addr));
27792 /* Given a memory reference, if it is not in the form for altivec memory
27793 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27794 convert to the altivec format. */
27797 rs6000_address_for_altivec (rtx x)
27799 gcc_assert (MEM_P (x));
27800 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
27802 rtx addr = XEXP (x, 0);
27803 int strict_p = (reload_in_progress || reload_completed);
27805 if (!legitimate_indexed_address_p (addr, strict_p)
27806 && !legitimate_indirect_address_p (addr, strict_p))
27807 addr = copy_to_mode_reg (Pmode, addr);
27809 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
27810 x = change_address (x, GET_MODE (x), addr);
27816 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
27818 On the RS/6000, all integer constants are acceptable, most won't be valid
27819 for particular insns, though. Only easy FP constants are acceptable. */
27822 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
27824 if (rs6000_tls_referenced_p (x))
27827 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
27828 || GET_MODE (x) == VOIDmode
27829 || (TARGET_POWERPC64 && mode == DImode)
27830 || easy_fp_constant (x, mode)
27831 || easy_vector_constant (x, mode));
27835 /* A function pointer under AIX is a pointer to a data area whose first word
27836 contains the actual address of the function, whose second word contains a
27837 pointer to its TOC, and whose third word contains a value to place in the
27838 static chain register (r11). Note that if we load the static chain, our
27839 "trampoline" need not have any executable code. */
27842 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
27848 rtx stack_toc_offset;
27850 rtx func_toc_offset;
27852 rtx func_sc_offset;
27855 rtx (*call_func) (rtx, rtx, rtx, rtx);
27856 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
27858 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27859 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
27861 /* Load up address of the actual function. */
27862 func_desc = force_reg (Pmode, func_desc);
27863 func_addr = gen_reg_rtx (Pmode);
27864 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
27869 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
27870 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
27871 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
27872 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27874 call_func = gen_call_indirect_aix32bit;
27875 call_value_func = gen_call_value_indirect_aix32bit;
27879 call_func = gen_call_indirect_aix32bit_nor11;
27880 call_value_func = gen_call_value_indirect_aix32bit_nor11;
27885 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
27886 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
27887 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
27888 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27890 call_func = gen_call_indirect_aix64bit;
27891 call_value_func = gen_call_value_indirect_aix64bit;
27895 call_func = gen_call_indirect_aix64bit_nor11;
27896 call_value_func = gen_call_value_indirect_aix64bit_nor11;
27900 /* Reserved spot to store the TOC. */
27901 stack_toc_mem = gen_frame_mem (Pmode,
27902 gen_rtx_PLUS (Pmode,
27904 stack_toc_offset));
27907 gcc_assert (cfun->machine);
27909 /* Can we optimize saving the TOC in the prologue or do we need to do it at
27911 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
27912 cfun->machine->save_toc_in_prologue = true;
27916 MEM_VOLATILE_P (stack_toc_mem) = 1;
27917 emit_move_insn (stack_toc_mem, toc_reg);
27920 /* Calculate the address to load the TOC of the called function. We don't
27921 actually load this until the split after reload. */
27922 func_toc_mem = gen_rtx_MEM (Pmode,
27923 gen_rtx_PLUS (Pmode,
27927 /* If we have a static chain, load it up. */
27928 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27930 func_sc_mem = gen_rtx_MEM (Pmode,
27931 gen_rtx_PLUS (Pmode,
27935 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
27936 emit_move_insn (sc_reg, func_sc_mem);
27939 /* Create the call. */
27941 insn = call_value_func (value, func_addr, flag, func_toc_mem,
27944 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
27946 emit_call_insn (insn);
27949 /* Return whether we need to always update the saved TOC pointer when we update
27950 the stack pointer. */
27953 rs6000_save_toc_in_prologue_p (void)
27955 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
27958 #ifdef HAVE_GAS_HIDDEN
27959 # define USE_HIDDEN_LINKONCE 1
27961 # define USE_HIDDEN_LINKONCE 0
27964 /* Fills in the label name that should be used for a 476 link stack thunk. */
27967 get_ppc476_thunk_name (char name[32])
27969 gcc_assert (TARGET_LINK_STACK);
27971 if (USE_HIDDEN_LINKONCE)
27972 sprintf (name, "__ppc476.get_thunk");
27974 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
27977 /* This function emits the simple thunk routine that is used to preserve
27978 the link stack on the 476 cpu. */
27980 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
27982 rs6000_code_end (void)
27987 if (!TARGET_LINK_STACK)
27990 get_ppc476_thunk_name (name);
27992 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
27993 build_function_type_list (void_type_node, NULL_TREE));
27994 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
27995 NULL_TREE, void_type_node);
27996 TREE_PUBLIC (decl) = 1;
27997 TREE_STATIC (decl) = 1;
27999 if (USE_HIDDEN_LINKONCE)
28001 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
28002 targetm.asm_out.unique_section (decl, 0);
28003 switch_to_section (get_named_section (decl, NULL, 0));
28004 DECL_WEAK (decl) = 1;
28005 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
28006 targetm.asm_out.globalize_label (asm_out_file, name);
28007 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
28008 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
28012 switch_to_section (text_section);
28013 ASM_OUTPUT_LABEL (asm_out_file, name);
28016 DECL_INITIAL (decl) = make_node (BLOCK);
28017 current_function_decl = decl;
28018 init_function_start (decl);
28019 first_function_block_is_cold = false;
28020 /* Make sure unwind info is emitted for the thunk if needed. */
28021 final_start_function (emit_barrier (), asm_out_file, 1);
28023 fputs ("\tblr\n", asm_out_file);
28025 final_end_function ();
28026 init_insn_lengths ();
28027 free_after_compilation (cfun);
28029 current_function_decl = NULL;
28032 /* Add r30 to hard reg set if the prologue sets it up and it is not
28033 pic_offset_table_rtx. */
28036 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
28038 if (!TARGET_SINGLE_PIC_BASE
28040 && TARGET_MINIMAL_TOC
28041 && get_pool_size () != 0)
28042 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
28045 struct gcc_target targetm = TARGET_INITIALIZER;
28047 #include "gt-rs6000.h"