1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
72 #include "tree-pass.h"
75 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
78 #include "gstab.h" /* for N_SLINE */
80 #include "case-cfn-macros.h"
82 #include "tree-ssa-propagate.h"
84 /* This file should be included last. */
85 #include "target-def.h"
87 #ifndef TARGET_NO_PROTOTYPE
88 #define TARGET_NO_PROTOTYPE 0
91 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
92 systems will also set long double to be IEEE 128-bit. AIX and Darwin
93 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
94 those systems will not pick up this default. This needs to be after all
95 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
97 #ifndef TARGET_IEEEQUAD_DEFAULT
98 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
99 #define TARGET_IEEEQUAD_DEFAULT 1
101 #define TARGET_IEEEQUAD_DEFAULT 0
105 #define min(A,B) ((A) < (B) ? (A) : (B))
106 #define max(A,B) ((A) > (B) ? (A) : (B))
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
202 /* Width in bits of a pointer. */
203 unsigned rs6000_pointer_size;
205 #ifdef HAVE_AS_GNU_ATTRIBUTE
206 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
207 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
209 /* Flag whether floating point values have been passed/returned.
210 Note that this doesn't say whether fprs are used, since the
211 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
212 should be set for soft-float values passed in gprs and ieee128
213 values passed in vsx registers. */
214 static bool rs6000_passes_float;
215 static bool rs6000_passes_long_double;
216 /* Flag whether vector values have been passed/returned. */
217 static bool rs6000_passes_vector;
218 /* Flag whether small (<= 8 byte) structures have been returned. */
219 static bool rs6000_returns_struct;
222 /* Value is TRUE if register/mode pair is acceptable. */
223 static bool rs6000_hard_regno_mode_ok_p
224 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Maximum number of registers needed for a given register class and mode. */
227 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
229 /* How many registers are needed for a given register and mode. */
230 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
232 /* Map register number to register class. */
233 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
235 static int dbg_cost_ctrl;
237 /* Built in types. */
238 tree rs6000_builtin_types[RS6000_BTI_MAX];
239 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
241 /* Flag to say the TOC is initialized */
242 int toc_initialized, need_toc_init;
243 char toc_label_name[10];
245 /* Cached value of rs6000_variable_issue. This is cached in
246 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
247 static short cached_can_issue_more;
249 static GTY(()) section *read_only_data_section;
250 static GTY(()) section *private_data_section;
251 static GTY(()) section *tls_data_section;
252 static GTY(()) section *tls_private_data_section;
253 static GTY(()) section *read_only_private_data_section;
254 static GTY(()) section *sdata2_section;
255 static GTY(()) section *toc_section;
257 struct builtin_description
259 const HOST_WIDE_INT mask;
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Describe the vector unit used for modes. */
266 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
267 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
269 /* Register classes for various constraints that are based on the target
271 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
273 /* Describe the alignment of a vector. */
274 int rs6000_vector_align[NUM_MACHINE_MODES];
276 /* Map selected modes to types for builtins. */
277 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
279 /* What modes to automatically generate reciprocal divide estimate (fre) and
280 reciprocal sqrt (frsqrte) for. */
281 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
283 /* Masks to determine which reciprocal esitmate instructions to generate
285 enum rs6000_recip_mask {
286 RECIP_SF_DIV = 0x001, /* Use divide estimate */
287 RECIP_DF_DIV = 0x002,
288 RECIP_V4SF_DIV = 0x004,
289 RECIP_V2DF_DIV = 0x008,
291 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
292 RECIP_DF_RSQRT = 0x020,
293 RECIP_V4SF_RSQRT = 0x040,
294 RECIP_V2DF_RSQRT = 0x080,
296 /* Various combination of flags for -mrecip=xxx. */
298 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
299 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
300 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
302 RECIP_HIGH_PRECISION = RECIP_ALL,
304 /* On low precision machines like the power5, don't enable double precision
305 reciprocal square root estimate, since it isn't accurate enough. */
306 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
309 /* -mrecip options. */
312 const char *string; /* option name */
313 unsigned int mask; /* mask bits to set */
314 } recip_options[] = {
315 { "all", RECIP_ALL },
316 { "none", RECIP_NONE },
317 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
319 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
320 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
321 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
322 | RECIP_V2DF_RSQRT) },
323 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
324 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
327 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
333 { "power9", PPC_PLATFORM_POWER9 },
334 { "power8", PPC_PLATFORM_POWER8 },
335 { "power7", PPC_PLATFORM_POWER7 },
336 { "power6x", PPC_PLATFORM_POWER6X },
337 { "power6", PPC_PLATFORM_POWER6 },
338 { "power5+", PPC_PLATFORM_POWER5_PLUS },
339 { "power5", PPC_PLATFORM_POWER5 },
340 { "ppc970", PPC_PLATFORM_PPC970 },
341 { "power4", PPC_PLATFORM_POWER4 },
342 { "ppca2", PPC_PLATFORM_PPCA2 },
343 { "ppc476", PPC_PLATFORM_PPC476 },
344 { "ppc464", PPC_PLATFORM_PPC464 },
345 { "ppc440", PPC_PLATFORM_PPC440 },
346 { "ppc405", PPC_PLATFORM_PPC405 },
347 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
350 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
356 } cpu_supports_info[] = {
357 /* AT_HWCAP masks. */
358 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
359 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
360 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
361 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
362 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
363 { "booke", PPC_FEATURE_BOOKE, 0 },
364 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
365 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
366 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
367 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
368 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
369 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
370 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
371 { "notb", PPC_FEATURE_NO_TB, 0 },
372 { "pa6t", PPC_FEATURE_PA6T, 0 },
373 { "power4", PPC_FEATURE_POWER4, 0 },
374 { "power5", PPC_FEATURE_POWER5, 0 },
375 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
376 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
377 { "ppc32", PPC_FEATURE_32, 0 },
378 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
379 { "ppc64", PPC_FEATURE_64, 0 },
380 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
381 { "smt", PPC_FEATURE_SMT, 0 },
382 { "spe", PPC_FEATURE_HAS_SPE, 0 },
383 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
384 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
385 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
387 /* AT_HWCAP2 masks. */
388 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
389 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
390 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
391 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
392 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
393 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
394 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
395 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
396 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
397 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
398 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
399 { "darn", PPC_FEATURE2_DARN, 1 },
400 { "scv", PPC_FEATURE2_SCV, 1 }
403 /* On PowerPC, we have a limited number of target clones that we care about
404 which means we can use an array to hold the options, rather than having more
405 elaborate data structures to identify each possible variation. Order the
406 clones from the default to the highest ISA. */
408 CLONE_DEFAULT = 0, /* default clone. */
409 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
410 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
411 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
412 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
416 /* Map compiler ISA bits into HWCAP names. */
418 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
419 const char *name; /* name to use in __builtin_cpu_supports. */
422 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
423 { 0, "" }, /* Default options. */
424 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
425 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
426 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
427 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
431 /* Newer LIBCs explicitly export this symbol to declare that they provide
432 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
433 reference to this symbol whenever we expand a CPU builtin, so that
434 we never link against an old LIBC. */
435 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
437 /* True if we have expanded a CPU builtin. */
440 /* Pointer to function (in rs6000-c.c) that can define or undefine target
441 macros that have changed. Languages that don't support the preprocessor
442 don't link in rs6000-c.c, so we can't call it directly. */
443 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
445 /* Simplfy register classes into simpler classifications. We assume
446 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
447 check for standard register classes (gpr/floating/altivec/vsx) and
448 floating/vector classes (float/altivec/vsx). */
450 enum rs6000_reg_type {
461 /* Map register class to register type. */
462 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
464 /* First/last register type for the 'normal' register types (i.e. general
465 purpose, floating point, altivec, and VSX registers). */
466 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
468 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
471 /* Register classes we care about in secondary reload or go if legitimate
472 address. We only need to worry about GPR, FPR, and Altivec registers here,
473 along an ANY field that is the OR of the 3 register classes. */
475 enum rs6000_reload_reg_type {
476 RELOAD_REG_GPR, /* General purpose registers. */
477 RELOAD_REG_FPR, /* Traditional floating point regs. */
478 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
479 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
483 /* For setting up register classes, loop through the 3 register classes mapping
484 into real registers, and skip the ANY class, which is just an OR of the
486 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
487 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
489 /* Map reload register type to a register in the register class. */
490 struct reload_reg_map_type {
491 const char *name; /* Register class name. */
492 int reg; /* Register in the register class. */
495 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
496 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
497 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
498 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
499 { "Any", -1 }, /* RELOAD_REG_ANY. */
502 /* Mask bits for each register class, indexed per mode. Historically the
503 compiler has been more restrictive which types can do PRE_MODIFY instead of
504 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
505 typedef unsigned char addr_mask_type;
507 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
508 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
509 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
510 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
511 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
512 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
513 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
514 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
516 /* Register type masks based on the type, of valid addressing modes. */
517 struct rs6000_reg_addr {
518 enum insn_code reload_load; /* INSN to reload for loading. */
519 enum insn_code reload_store; /* INSN to reload for storing. */
520 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
521 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
522 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
523 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
524 /* INSNs for fusing addi with loads
525 or stores for each reg. class. */
526 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
527 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
528 /* INSNs for fusing addis with loads
529 or stores for each reg. class. */
530 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
531 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
532 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
533 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
534 bool fused_toc; /* Mode supports TOC fusion. */
537 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
539 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
541 mode_supports_pre_incdec_p (machine_mode mode)
543 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
547 /* Helper function to say whether a mode supports PRE_MODIFY. */
549 mode_supports_pre_modify_p (machine_mode mode)
551 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
555 /* Given that there exists at least one variable that is set (produced)
556 by OUT_INSN and read (consumed) by IN_INSN, return true iff
557 IN_INSN represents one or more memory store operations and none of
558 the variables set by OUT_INSN is used by IN_INSN as the address of a
559 store operation. If either IN_INSN or OUT_INSN does not represent
560 a "single" RTL SET expression (as loosely defined by the
561 implementation of the single_set function) or a PARALLEL with only
562 SETs, CLOBBERs, and USEs inside, this function returns false.
564 This rs6000-specific version of store_data_bypass_p checks for
565 certain conditions that result in assertion failures (and internal
566 compiler errors) in the generic store_data_bypass_p function and
567 returns false rather than calling store_data_bypass_p if one of the
568 problematic conditions is detected. */
571 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
578 in_set = single_set (in_insn);
581 if (MEM_P (SET_DEST (in_set)))
583 out_set = single_set (out_insn);
586 out_pat = PATTERN (out_insn);
587 if (GET_CODE (out_pat) == PARALLEL)
589 for (i = 0; i < XVECLEN (out_pat, 0); i++)
591 out_exp = XVECEXP (out_pat, 0, i);
592 if ((GET_CODE (out_exp) == CLOBBER)
593 || (GET_CODE (out_exp) == USE))
595 else if (GET_CODE (out_exp) != SET)
604 in_pat = PATTERN (in_insn);
605 if (GET_CODE (in_pat) != PARALLEL)
608 for (i = 0; i < XVECLEN (in_pat, 0); i++)
610 in_exp = XVECEXP (in_pat, 0, i);
611 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
613 else if (GET_CODE (in_exp) != SET)
616 if (MEM_P (SET_DEST (in_exp)))
618 out_set = single_set (out_insn);
621 out_pat = PATTERN (out_insn);
622 if (GET_CODE (out_pat) != PARALLEL)
624 for (j = 0; j < XVECLEN (out_pat, 0); j++)
626 out_exp = XVECEXP (out_pat, 0, j);
627 if ((GET_CODE (out_exp) == CLOBBER)
628 || (GET_CODE (out_exp) == USE))
630 else if (GET_CODE (out_exp) != SET)
637 return store_data_bypass_p (out_insn, in_insn);
640 /* Return true if we have D-form addressing in altivec registers. */
642 mode_supports_vmx_dform (machine_mode mode)
644 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
647 /* Return true if we have D-form addressing in VSX registers. This addressing
648 is more limited than normal d-form addressing in that the offset must be
649 aligned on a 16-byte boundary. */
651 mode_supports_vsx_dform_quad (machine_mode mode)
653 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
658 /* Processor costs (relative to an add) */
660 const struct processor_costs *rs6000_cost;
662 /* Instruction size costs on 32bit processors. */
664 struct processor_costs size32_cost = {
665 COSTS_N_INSNS (1), /* mulsi */
666 COSTS_N_INSNS (1), /* mulsi_const */
667 COSTS_N_INSNS (1), /* mulsi_const9 */
668 COSTS_N_INSNS (1), /* muldi */
669 COSTS_N_INSNS (1), /* divsi */
670 COSTS_N_INSNS (1), /* divdi */
671 COSTS_N_INSNS (1), /* fp */
672 COSTS_N_INSNS (1), /* dmul */
673 COSTS_N_INSNS (1), /* sdiv */
674 COSTS_N_INSNS (1), /* ddiv */
675 32, /* cache line size */
679 0, /* SF->DF convert */
682 /* Instruction size costs on 64bit processors. */
684 struct processor_costs size64_cost = {
685 COSTS_N_INSNS (1), /* mulsi */
686 COSTS_N_INSNS (1), /* mulsi_const */
687 COSTS_N_INSNS (1), /* mulsi_const9 */
688 COSTS_N_INSNS (1), /* muldi */
689 COSTS_N_INSNS (1), /* divsi */
690 COSTS_N_INSNS (1), /* divdi */
691 COSTS_N_INSNS (1), /* fp */
692 COSTS_N_INSNS (1), /* dmul */
693 COSTS_N_INSNS (1), /* sdiv */
694 COSTS_N_INSNS (1), /* ddiv */
695 128, /* cache line size */
699 0, /* SF->DF convert */
702 /* Instruction costs on RS64A processors. */
704 struct processor_costs rs64a_cost = {
705 COSTS_N_INSNS (20), /* mulsi */
706 COSTS_N_INSNS (12), /* mulsi_const */
707 COSTS_N_INSNS (8), /* mulsi_const9 */
708 COSTS_N_INSNS (34), /* muldi */
709 COSTS_N_INSNS (65), /* divsi */
710 COSTS_N_INSNS (67), /* divdi */
711 COSTS_N_INSNS (4), /* fp */
712 COSTS_N_INSNS (4), /* dmul */
713 COSTS_N_INSNS (31), /* sdiv */
714 COSTS_N_INSNS (31), /* ddiv */
715 128, /* cache line size */
719 0, /* SF->DF convert */
722 /* Instruction costs on MPCCORE processors. */
724 struct processor_costs mpccore_cost = {
725 COSTS_N_INSNS (2), /* mulsi */
726 COSTS_N_INSNS (2), /* mulsi_const */
727 COSTS_N_INSNS (2), /* mulsi_const9 */
728 COSTS_N_INSNS (2), /* muldi */
729 COSTS_N_INSNS (6), /* divsi */
730 COSTS_N_INSNS (6), /* divdi */
731 COSTS_N_INSNS (4), /* fp */
732 COSTS_N_INSNS (5), /* dmul */
733 COSTS_N_INSNS (10), /* sdiv */
734 COSTS_N_INSNS (17), /* ddiv */
735 32, /* cache line size */
739 0, /* SF->DF convert */
742 /* Instruction costs on PPC403 processors. */
744 struct processor_costs ppc403_cost = {
745 COSTS_N_INSNS (4), /* mulsi */
746 COSTS_N_INSNS (4), /* mulsi_const */
747 COSTS_N_INSNS (4), /* mulsi_const9 */
748 COSTS_N_INSNS (4), /* muldi */
749 COSTS_N_INSNS (33), /* divsi */
750 COSTS_N_INSNS (33), /* divdi */
751 COSTS_N_INSNS (11), /* fp */
752 COSTS_N_INSNS (11), /* dmul */
753 COSTS_N_INSNS (11), /* sdiv */
754 COSTS_N_INSNS (11), /* ddiv */
755 32, /* cache line size */
759 0, /* SF->DF convert */
762 /* Instruction costs on PPC405 processors. */
764 struct processor_costs ppc405_cost = {
765 COSTS_N_INSNS (5), /* mulsi */
766 COSTS_N_INSNS (4), /* mulsi_const */
767 COSTS_N_INSNS (3), /* mulsi_const9 */
768 COSTS_N_INSNS (5), /* muldi */
769 COSTS_N_INSNS (35), /* divsi */
770 COSTS_N_INSNS (35), /* divdi */
771 COSTS_N_INSNS (11), /* fp */
772 COSTS_N_INSNS (11), /* dmul */
773 COSTS_N_INSNS (11), /* sdiv */
774 COSTS_N_INSNS (11), /* ddiv */
775 32, /* cache line size */
779 0, /* SF->DF convert */
782 /* Instruction costs on PPC440 processors. */
784 struct processor_costs ppc440_cost = {
785 COSTS_N_INSNS (3), /* mulsi */
786 COSTS_N_INSNS (2), /* mulsi_const */
787 COSTS_N_INSNS (2), /* mulsi_const9 */
788 COSTS_N_INSNS (3), /* muldi */
789 COSTS_N_INSNS (34), /* divsi */
790 COSTS_N_INSNS (34), /* divdi */
791 COSTS_N_INSNS (5), /* fp */
792 COSTS_N_INSNS (5), /* dmul */
793 COSTS_N_INSNS (19), /* sdiv */
794 COSTS_N_INSNS (33), /* ddiv */
795 32, /* cache line size */
799 0, /* SF->DF convert */
802 /* Instruction costs on PPC476 processors. */
804 struct processor_costs ppc476_cost = {
805 COSTS_N_INSNS (4), /* mulsi */
806 COSTS_N_INSNS (4), /* mulsi_const */
807 COSTS_N_INSNS (4), /* mulsi_const9 */
808 COSTS_N_INSNS (4), /* muldi */
809 COSTS_N_INSNS (11), /* divsi */
810 COSTS_N_INSNS (11), /* divdi */
811 COSTS_N_INSNS (6), /* fp */
812 COSTS_N_INSNS (6), /* dmul */
813 COSTS_N_INSNS (19), /* sdiv */
814 COSTS_N_INSNS (33), /* ddiv */
815 32, /* l1 cache line size */
819 0, /* SF->DF convert */
822 /* Instruction costs on PPC601 processors. */
824 struct processor_costs ppc601_cost = {
825 COSTS_N_INSNS (5), /* mulsi */
826 COSTS_N_INSNS (5), /* mulsi_const */
827 COSTS_N_INSNS (5), /* mulsi_const9 */
828 COSTS_N_INSNS (5), /* muldi */
829 COSTS_N_INSNS (36), /* divsi */
830 COSTS_N_INSNS (36), /* divdi */
831 COSTS_N_INSNS (4), /* fp */
832 COSTS_N_INSNS (5), /* dmul */
833 COSTS_N_INSNS (17), /* sdiv */
834 COSTS_N_INSNS (31), /* ddiv */
835 32, /* cache line size */
839 0, /* SF->DF convert */
842 /* Instruction costs on PPC603 processors. */
844 struct processor_costs ppc603_cost = {
845 COSTS_N_INSNS (5), /* mulsi */
846 COSTS_N_INSNS (3), /* mulsi_const */
847 COSTS_N_INSNS (2), /* mulsi_const9 */
848 COSTS_N_INSNS (5), /* muldi */
849 COSTS_N_INSNS (37), /* divsi */
850 COSTS_N_INSNS (37), /* divdi */
851 COSTS_N_INSNS (3), /* fp */
852 COSTS_N_INSNS (4), /* dmul */
853 COSTS_N_INSNS (18), /* sdiv */
854 COSTS_N_INSNS (33), /* ddiv */
855 32, /* cache line size */
859 0, /* SF->DF convert */
862 /* Instruction costs on PPC604 processors. */
864 struct processor_costs ppc604_cost = {
865 COSTS_N_INSNS (4), /* mulsi */
866 COSTS_N_INSNS (4), /* mulsi_const */
867 COSTS_N_INSNS (4), /* mulsi_const9 */
868 COSTS_N_INSNS (4), /* muldi */
869 COSTS_N_INSNS (20), /* divsi */
870 COSTS_N_INSNS (20), /* divdi */
871 COSTS_N_INSNS (3), /* fp */
872 COSTS_N_INSNS (3), /* dmul */
873 COSTS_N_INSNS (18), /* sdiv */
874 COSTS_N_INSNS (32), /* ddiv */
875 32, /* cache line size */
879 0, /* SF->DF convert */
882 /* Instruction costs on PPC604e processors. */
884 struct processor_costs ppc604e_cost = {
885 COSTS_N_INSNS (2), /* mulsi */
886 COSTS_N_INSNS (2), /* mulsi_const */
887 COSTS_N_INSNS (2), /* mulsi_const9 */
888 COSTS_N_INSNS (2), /* muldi */
889 COSTS_N_INSNS (20), /* divsi */
890 COSTS_N_INSNS (20), /* divdi */
891 COSTS_N_INSNS (3), /* fp */
892 COSTS_N_INSNS (3), /* dmul */
893 COSTS_N_INSNS (18), /* sdiv */
894 COSTS_N_INSNS (32), /* ddiv */
895 32, /* cache line size */
899 0, /* SF->DF convert */
902 /* Instruction costs on PPC620 processors. */
904 struct processor_costs ppc620_cost = {
905 COSTS_N_INSNS (5), /* mulsi */
906 COSTS_N_INSNS (4), /* mulsi_const */
907 COSTS_N_INSNS (3), /* mulsi_const9 */
908 COSTS_N_INSNS (7), /* muldi */
909 COSTS_N_INSNS (21), /* divsi */
910 COSTS_N_INSNS (37), /* divdi */
911 COSTS_N_INSNS (3), /* fp */
912 COSTS_N_INSNS (3), /* dmul */
913 COSTS_N_INSNS (18), /* sdiv */
914 COSTS_N_INSNS (32), /* ddiv */
915 128, /* cache line size */
919 0, /* SF->DF convert */
922 /* Instruction costs on PPC630 processors. */
924 struct processor_costs ppc630_cost = {
925 COSTS_N_INSNS (5), /* mulsi */
926 COSTS_N_INSNS (4), /* mulsi_const */
927 COSTS_N_INSNS (3), /* mulsi_const9 */
928 COSTS_N_INSNS (7), /* muldi */
929 COSTS_N_INSNS (21), /* divsi */
930 COSTS_N_INSNS (37), /* divdi */
931 COSTS_N_INSNS (3), /* fp */
932 COSTS_N_INSNS (3), /* dmul */
933 COSTS_N_INSNS (17), /* sdiv */
934 COSTS_N_INSNS (21), /* ddiv */
935 128, /* cache line size */
939 0, /* SF->DF convert */
942 /* Instruction costs on Cell processor. */
943 /* COSTS_N_INSNS (1) ~ one add. */
945 struct processor_costs ppccell_cost = {
946 COSTS_N_INSNS (9/2)+2, /* mulsi */
947 COSTS_N_INSNS (6/2), /* mulsi_const */
948 COSTS_N_INSNS (6/2), /* mulsi_const9 */
949 COSTS_N_INSNS (15/2)+2, /* muldi */
950 COSTS_N_INSNS (38/2), /* divsi */
951 COSTS_N_INSNS (70/2), /* divdi */
952 COSTS_N_INSNS (10/2), /* fp */
953 COSTS_N_INSNS (10/2), /* dmul */
954 COSTS_N_INSNS (74/2), /* sdiv */
955 COSTS_N_INSNS (74/2), /* ddiv */
956 128, /* cache line size */
960 0, /* SF->DF convert */
963 /* Instruction costs on PPC750 and PPC7400 processors. */
965 struct processor_costs ppc750_cost = {
966 COSTS_N_INSNS (5), /* mulsi */
967 COSTS_N_INSNS (3), /* mulsi_const */
968 COSTS_N_INSNS (2), /* mulsi_const9 */
969 COSTS_N_INSNS (5), /* muldi */
970 COSTS_N_INSNS (17), /* divsi */
971 COSTS_N_INSNS (17), /* divdi */
972 COSTS_N_INSNS (3), /* fp */
973 COSTS_N_INSNS (3), /* dmul */
974 COSTS_N_INSNS (17), /* sdiv */
975 COSTS_N_INSNS (31), /* ddiv */
976 32, /* cache line size */
980 0, /* SF->DF convert */
983 /* Instruction costs on PPC7450 processors. */
985 struct processor_costs ppc7450_cost = {
986 COSTS_N_INSNS (4), /* mulsi */
987 COSTS_N_INSNS (3), /* mulsi_const */
988 COSTS_N_INSNS (3), /* mulsi_const9 */
989 COSTS_N_INSNS (4), /* muldi */
990 COSTS_N_INSNS (23), /* divsi */
991 COSTS_N_INSNS (23), /* divdi */
992 COSTS_N_INSNS (5), /* fp */
993 COSTS_N_INSNS (5), /* dmul */
994 COSTS_N_INSNS (21), /* sdiv */
995 COSTS_N_INSNS (35), /* ddiv */
996 32, /* cache line size */
1000 0, /* SF->DF convert */
1003 /* Instruction costs on PPC8540 processors. */
1005 struct processor_costs ppc8540_cost = {
1006 COSTS_N_INSNS (4), /* mulsi */
1007 COSTS_N_INSNS (4), /* mulsi_const */
1008 COSTS_N_INSNS (4), /* mulsi_const9 */
1009 COSTS_N_INSNS (4), /* muldi */
1010 COSTS_N_INSNS (19), /* divsi */
1011 COSTS_N_INSNS (19), /* divdi */
1012 COSTS_N_INSNS (4), /* fp */
1013 COSTS_N_INSNS (4), /* dmul */
1014 COSTS_N_INSNS (29), /* sdiv */
1015 COSTS_N_INSNS (29), /* ddiv */
1016 32, /* cache line size */
1019 1, /* prefetch streams /*/
1020 0, /* SF->DF convert */
1023 /* Instruction costs on E300C2 and E300C3 cores. */
1025 struct processor_costs ppce300c2c3_cost = {
1026 COSTS_N_INSNS (4), /* mulsi */
1027 COSTS_N_INSNS (4), /* mulsi_const */
1028 COSTS_N_INSNS (4), /* mulsi_const9 */
1029 COSTS_N_INSNS (4), /* muldi */
1030 COSTS_N_INSNS (19), /* divsi */
1031 COSTS_N_INSNS (19), /* divdi */
1032 COSTS_N_INSNS (3), /* fp */
1033 COSTS_N_INSNS (4), /* dmul */
1034 COSTS_N_INSNS (18), /* sdiv */
1035 COSTS_N_INSNS (33), /* ddiv */
1039 1, /* prefetch streams /*/
1040 0, /* SF->DF convert */
1043 /* Instruction costs on PPCE500MC processors. */
1045 struct processor_costs ppce500mc_cost = {
1046 COSTS_N_INSNS (4), /* mulsi */
1047 COSTS_N_INSNS (4), /* mulsi_const */
1048 COSTS_N_INSNS (4), /* mulsi_const9 */
1049 COSTS_N_INSNS (4), /* muldi */
1050 COSTS_N_INSNS (14), /* divsi */
1051 COSTS_N_INSNS (14), /* divdi */
1052 COSTS_N_INSNS (8), /* fp */
1053 COSTS_N_INSNS (10), /* dmul */
1054 COSTS_N_INSNS (36), /* sdiv */
1055 COSTS_N_INSNS (66), /* ddiv */
1056 64, /* cache line size */
1059 1, /* prefetch streams /*/
1060 0, /* SF->DF convert */
1063 /* Instruction costs on PPCE500MC64 processors. */
1065 struct processor_costs ppce500mc64_cost = {
1066 COSTS_N_INSNS (4), /* mulsi */
1067 COSTS_N_INSNS (4), /* mulsi_const */
1068 COSTS_N_INSNS (4), /* mulsi_const9 */
1069 COSTS_N_INSNS (4), /* muldi */
1070 COSTS_N_INSNS (14), /* divsi */
1071 COSTS_N_INSNS (14), /* divdi */
1072 COSTS_N_INSNS (4), /* fp */
1073 COSTS_N_INSNS (10), /* dmul */
1074 COSTS_N_INSNS (36), /* sdiv */
1075 COSTS_N_INSNS (66), /* ddiv */
1076 64, /* cache line size */
1079 1, /* prefetch streams /*/
1080 0, /* SF->DF convert */
1083 /* Instruction costs on PPCE5500 processors. */
1085 struct processor_costs ppce5500_cost = {
1086 COSTS_N_INSNS (5), /* mulsi */
1087 COSTS_N_INSNS (5), /* mulsi_const */
1088 COSTS_N_INSNS (4), /* mulsi_const9 */
1089 COSTS_N_INSNS (5), /* muldi */
1090 COSTS_N_INSNS (14), /* divsi */
1091 COSTS_N_INSNS (14), /* divdi */
1092 COSTS_N_INSNS (7), /* fp */
1093 COSTS_N_INSNS (10), /* dmul */
1094 COSTS_N_INSNS (36), /* sdiv */
1095 COSTS_N_INSNS (66), /* ddiv */
1096 64, /* cache line size */
1099 1, /* prefetch streams /*/
1100 0, /* SF->DF convert */
1103 /* Instruction costs on PPCE6500 processors. */
1105 struct processor_costs ppce6500_cost = {
1106 COSTS_N_INSNS (5), /* mulsi */
1107 COSTS_N_INSNS (5), /* mulsi_const */
1108 COSTS_N_INSNS (4), /* mulsi_const9 */
1109 COSTS_N_INSNS (5), /* muldi */
1110 COSTS_N_INSNS (14), /* divsi */
1111 COSTS_N_INSNS (14), /* divdi */
1112 COSTS_N_INSNS (7), /* fp */
1113 COSTS_N_INSNS (10), /* dmul */
1114 COSTS_N_INSNS (36), /* sdiv */
1115 COSTS_N_INSNS (66), /* ddiv */
1116 64, /* cache line size */
1119 1, /* prefetch streams /*/
1120 0, /* SF->DF convert */
1123 /* Instruction costs on AppliedMicro Titan processors. */
1125 struct processor_costs titan_cost = {
1126 COSTS_N_INSNS (5), /* mulsi */
1127 COSTS_N_INSNS (5), /* mulsi_const */
1128 COSTS_N_INSNS (5), /* mulsi_const9 */
1129 COSTS_N_INSNS (5), /* muldi */
1130 COSTS_N_INSNS (18), /* divsi */
1131 COSTS_N_INSNS (18), /* divdi */
1132 COSTS_N_INSNS (10), /* fp */
1133 COSTS_N_INSNS (10), /* dmul */
1134 COSTS_N_INSNS (46), /* sdiv */
1135 COSTS_N_INSNS (72), /* ddiv */
1136 32, /* cache line size */
1139 1, /* prefetch streams /*/
1140 0, /* SF->DF convert */
1143 /* Instruction costs on POWER4 and POWER5 processors. */
1145 struct processor_costs power4_cost = {
1146 COSTS_N_INSNS (3), /* mulsi */
1147 COSTS_N_INSNS (2), /* mulsi_const */
1148 COSTS_N_INSNS (2), /* mulsi_const9 */
1149 COSTS_N_INSNS (4), /* muldi */
1150 COSTS_N_INSNS (18), /* divsi */
1151 COSTS_N_INSNS (34), /* divdi */
1152 COSTS_N_INSNS (3), /* fp */
1153 COSTS_N_INSNS (3), /* dmul */
1154 COSTS_N_INSNS (17), /* sdiv */
1155 COSTS_N_INSNS (17), /* ddiv */
1156 128, /* cache line size */
1158 1024, /* l2 cache */
1159 8, /* prefetch streams /*/
1160 0, /* SF->DF convert */
1163 /* Instruction costs on POWER6 processors. */
1165 struct processor_costs power6_cost = {
1166 COSTS_N_INSNS (8), /* mulsi */
1167 COSTS_N_INSNS (8), /* mulsi_const */
1168 COSTS_N_INSNS (8), /* mulsi_const9 */
1169 COSTS_N_INSNS (8), /* muldi */
1170 COSTS_N_INSNS (22), /* divsi */
1171 COSTS_N_INSNS (28), /* divdi */
1172 COSTS_N_INSNS (3), /* fp */
1173 COSTS_N_INSNS (3), /* dmul */
1174 COSTS_N_INSNS (13), /* sdiv */
1175 COSTS_N_INSNS (16), /* ddiv */
1176 128, /* cache line size */
1178 2048, /* l2 cache */
1179 16, /* prefetch streams */
1180 0, /* SF->DF convert */
1183 /* Instruction costs on POWER7 processors. */
1185 struct processor_costs power7_cost = {
1186 COSTS_N_INSNS (2), /* mulsi */
1187 COSTS_N_INSNS (2), /* mulsi_const */
1188 COSTS_N_INSNS (2), /* mulsi_const9 */
1189 COSTS_N_INSNS (2), /* muldi */
1190 COSTS_N_INSNS (18), /* divsi */
1191 COSTS_N_INSNS (34), /* divdi */
1192 COSTS_N_INSNS (3), /* fp */
1193 COSTS_N_INSNS (3), /* dmul */
1194 COSTS_N_INSNS (13), /* sdiv */
1195 COSTS_N_INSNS (16), /* ddiv */
1196 128, /* cache line size */
1199 12, /* prefetch streams */
1200 COSTS_N_INSNS (3), /* SF->DF convert */
1203 /* Instruction costs on POWER8 processors. */
1205 struct processor_costs power8_cost = {
1206 COSTS_N_INSNS (3), /* mulsi */
1207 COSTS_N_INSNS (3), /* mulsi_const */
1208 COSTS_N_INSNS (3), /* mulsi_const9 */
1209 COSTS_N_INSNS (3), /* muldi */
1210 COSTS_N_INSNS (19), /* divsi */
1211 COSTS_N_INSNS (35), /* divdi */
1212 COSTS_N_INSNS (3), /* fp */
1213 COSTS_N_INSNS (3), /* dmul */
1214 COSTS_N_INSNS (14), /* sdiv */
1215 COSTS_N_INSNS (17), /* ddiv */
1216 128, /* cache line size */
1219 12, /* prefetch streams */
1220 COSTS_N_INSNS (3), /* SF->DF convert */
1223 /* Instruction costs on POWER9 processors. */
1225 struct processor_costs power9_cost = {
1226 COSTS_N_INSNS (3), /* mulsi */
1227 COSTS_N_INSNS (3), /* mulsi_const */
1228 COSTS_N_INSNS (3), /* mulsi_const9 */
1229 COSTS_N_INSNS (3), /* muldi */
1230 COSTS_N_INSNS (8), /* divsi */
1231 COSTS_N_INSNS (12), /* divdi */
1232 COSTS_N_INSNS (3), /* fp */
1233 COSTS_N_INSNS (3), /* dmul */
1234 COSTS_N_INSNS (13), /* sdiv */
1235 COSTS_N_INSNS (18), /* ddiv */
1236 128, /* cache line size */
1239 8, /* prefetch streams */
1240 COSTS_N_INSNS (3), /* SF->DF convert */
1243 /* Instruction costs on POWER A2 processors. */
1245 struct processor_costs ppca2_cost = {
1246 COSTS_N_INSNS (16), /* mulsi */
1247 COSTS_N_INSNS (16), /* mulsi_const */
1248 COSTS_N_INSNS (16), /* mulsi_const9 */
1249 COSTS_N_INSNS (16), /* muldi */
1250 COSTS_N_INSNS (22), /* divsi */
1251 COSTS_N_INSNS (28), /* divdi */
1252 COSTS_N_INSNS (3), /* fp */
1253 COSTS_N_INSNS (3), /* dmul */
1254 COSTS_N_INSNS (59), /* sdiv */
1255 COSTS_N_INSNS (72), /* ddiv */
1258 2048, /* l2 cache */
1259 16, /* prefetch streams */
1260 0, /* SF->DF convert */
1264 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1265 #undef RS6000_BUILTIN_0
1266 #undef RS6000_BUILTIN_1
1267 #undef RS6000_BUILTIN_2
1268 #undef RS6000_BUILTIN_3
1269 #undef RS6000_BUILTIN_A
1270 #undef RS6000_BUILTIN_D
1271 #undef RS6000_BUILTIN_H
1272 #undef RS6000_BUILTIN_P
1273 #undef RS6000_BUILTIN_Q
1274 #undef RS6000_BUILTIN_X
1276 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1304 { NAME, ICODE, MASK, ATTR },
1306 struct rs6000_builtin_info_type {
1308 const enum insn_code icode;
1309 const HOST_WIDE_INT mask;
1310 const unsigned attr;
1313 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1315 #include "rs6000-builtin.def"
1318 #undef RS6000_BUILTIN_0
1319 #undef RS6000_BUILTIN_1
1320 #undef RS6000_BUILTIN_2
1321 #undef RS6000_BUILTIN_3
1322 #undef RS6000_BUILTIN_A
1323 #undef RS6000_BUILTIN_D
1324 #undef RS6000_BUILTIN_H
1325 #undef RS6000_BUILTIN_P
1326 #undef RS6000_BUILTIN_Q
1327 #undef RS6000_BUILTIN_X
1329 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1330 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1333 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1334 static struct machine_function * rs6000_init_machine_status (void);
1335 static int rs6000_ra_ever_killed (void);
1336 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1338 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1339 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1340 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1341 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1342 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1343 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1345 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1347 static bool is_microcoded_insn (rtx_insn *);
1348 static bool is_nonpipeline_insn (rtx_insn *);
1349 static bool is_cracked_insn (rtx_insn *);
1350 static bool is_load_insn (rtx, rtx *);
1351 static bool is_store_insn (rtx, rtx *);
1352 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1353 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1354 static bool insn_must_be_first_in_group (rtx_insn *);
1355 static bool insn_must_be_last_in_group (rtx_insn *);
1356 static void altivec_init_builtins (void);
1357 static tree builtin_function_type (machine_mode, machine_mode,
1358 machine_mode, machine_mode,
1359 enum rs6000_builtins, const char *name);
1360 static void rs6000_common_init_builtins (void);
1361 static void paired_init_builtins (void);
1362 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1363 static void htm_init_builtins (void);
1364 static rs6000_stack_t *rs6000_stack_info (void);
1365 static void is_altivec_return_reg (rtx, void *);
1366 int easy_vector_constant (rtx, machine_mode);
1367 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1368 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1369 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1372 static void macho_branch_islands (void);
1374 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1376 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1378 static bool rs6000_mode_dependent_address (const_rtx);
1379 static bool rs6000_debug_mode_dependent_address (const_rtx);
1380 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1382 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1385 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1386 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1388 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1391 static bool rs6000_debug_can_change_mode_class (machine_mode,
1394 static bool rs6000_save_toc_in_prologue_p (void);
1395 static rtx rs6000_internal_arg_pointer (void);
1397 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1399 = rs6000_legitimize_reload_address;
1401 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1402 = rs6000_mode_dependent_address;
1404 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1406 = rs6000_secondary_reload_class;
1408 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1409 = rs6000_preferred_reload_class;
1411 const int INSN_NOT_AVAILABLE = -1;
1413 static void rs6000_print_isa_options (FILE *, int, const char *,
1415 static void rs6000_print_builtin_options (FILE *, int, const char *,
1417 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1419 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1420 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1421 enum rs6000_reg_type,
1423 secondary_reload_info *,
1425 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1426 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1427 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1429 /* Hash table stuff for keeping track of TOC entries. */
1431 struct GTY((for_user)) toc_hash_struct
1433 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1434 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1436 machine_mode key_mode;
1440 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1442 static hashval_t hash (toc_hash_struct *);
1443 static bool equal (toc_hash_struct *, toc_hash_struct *);
1446 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1448 /* Hash table to keep track of the argument types for builtin functions. */
1450 struct GTY((for_user)) builtin_hash_struct
1453 machine_mode mode[4]; /* return value + 3 arguments. */
1454 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1457 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1459 static hashval_t hash (builtin_hash_struct *);
1460 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1463 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1466 /* Default register names. */
1467 char rs6000_reg_names[][8] =
1469 "0", "1", "2", "3", "4", "5", "6", "7",
1470 "8", "9", "10", "11", "12", "13", "14", "15",
1471 "16", "17", "18", "19", "20", "21", "22", "23",
1472 "24", "25", "26", "27", "28", "29", "30", "31",
1473 "0", "1", "2", "3", "4", "5", "6", "7",
1474 "8", "9", "10", "11", "12", "13", "14", "15",
1475 "16", "17", "18", "19", "20", "21", "22", "23",
1476 "24", "25", "26", "27", "28", "29", "30", "31",
1477 "mq", "lr", "ctr","ap",
1478 "0", "1", "2", "3", "4", "5", "6", "7",
1480 /* AltiVec registers. */
1481 "0", "1", "2", "3", "4", "5", "6", "7",
1482 "8", "9", "10", "11", "12", "13", "14", "15",
1483 "16", "17", "18", "19", "20", "21", "22", "23",
1484 "24", "25", "26", "27", "28", "29", "30", "31",
1486 /* Soft frame pointer. */
1488 /* HTM SPR registers. */
1489 "tfhar", "tfiar", "texasr"
1492 #ifdef TARGET_REGNAMES
1493 static const char alt_reg_names[][8] =
1495 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1496 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1497 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1498 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1499 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1500 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1501 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1502 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1503 "mq", "lr", "ctr", "ap",
1504 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1506 /* AltiVec registers. */
1507 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1508 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1509 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1510 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1512 /* Soft frame pointer. */
1514 /* HTM SPR registers. */
1515 "tfhar", "tfiar", "texasr"
1519 /* Table of valid machine attributes. */
1521 static const struct attribute_spec rs6000_attribute_table[] =
1523 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1524 affects_type_identity, handler, exclude } */
1525 { "altivec", 1, 1, false, true, false, false,
1526 rs6000_handle_altivec_attribute, NULL },
1527 { "longcall", 0, 0, false, true, true, false,
1528 rs6000_handle_longcall_attribute, NULL },
1529 { "shortcall", 0, 0, false, true, true, false,
1530 rs6000_handle_longcall_attribute, NULL },
1531 { "ms_struct", 0, 0, false, false, false, false,
1532 rs6000_handle_struct_attribute, NULL },
1533 { "gcc_struct", 0, 0, false, false, false, false,
1534 rs6000_handle_struct_attribute, NULL },
1535 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1536 SUBTARGET_ATTRIBUTE_TABLE,
1538 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1541 #ifndef TARGET_PROFILE_KERNEL
1542 #define TARGET_PROFILE_KERNEL 0
1545 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1546 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1548 /* Initialize the GCC target structure. */
1549 #undef TARGET_ATTRIBUTE_TABLE
1550 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1551 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1552 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1553 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1554 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1556 #undef TARGET_ASM_ALIGNED_DI_OP
1557 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1559 /* Default unaligned ops are only provided for ELF. Find the ops needed
1560 for non-ELF systems. */
1561 #ifndef OBJECT_FORMAT_ELF
1563 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1565 #undef TARGET_ASM_UNALIGNED_HI_OP
1566 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1567 #undef TARGET_ASM_UNALIGNED_SI_OP
1568 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1569 #undef TARGET_ASM_UNALIGNED_DI_OP
1570 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1573 #undef TARGET_ASM_UNALIGNED_HI_OP
1574 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1575 #undef TARGET_ASM_UNALIGNED_SI_OP
1576 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1577 #undef TARGET_ASM_UNALIGNED_DI_OP
1578 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1579 #undef TARGET_ASM_ALIGNED_DI_OP
1580 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1584 /* This hook deals with fixups for relocatable code and DI-mode objects
1586 #undef TARGET_ASM_INTEGER
1587 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1589 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1590 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1591 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1594 #undef TARGET_SET_UP_BY_PROLOGUE
1595 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1597 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1599 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1600 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1601 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1602 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1603 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1604 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1605 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1606 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1607 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1608 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1610 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1611 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1613 #undef TARGET_INTERNAL_ARG_POINTER
1614 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1616 #undef TARGET_HAVE_TLS
1617 #define TARGET_HAVE_TLS HAVE_AS_TLS
1619 #undef TARGET_CANNOT_FORCE_CONST_MEM
1620 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1622 #undef TARGET_DELEGITIMIZE_ADDRESS
1623 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1625 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1626 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1628 #undef TARGET_LEGITIMATE_COMBINED_INSN
1629 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1631 #undef TARGET_ASM_FUNCTION_PROLOGUE
1632 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1633 #undef TARGET_ASM_FUNCTION_EPILOGUE
1634 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1636 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1637 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1639 #undef TARGET_LEGITIMIZE_ADDRESS
1640 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1642 #undef TARGET_SCHED_VARIABLE_ISSUE
1643 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1645 #undef TARGET_SCHED_ISSUE_RATE
1646 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1647 #undef TARGET_SCHED_ADJUST_COST
1648 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1649 #undef TARGET_SCHED_ADJUST_PRIORITY
1650 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1651 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1652 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1653 #undef TARGET_SCHED_INIT
1654 #define TARGET_SCHED_INIT rs6000_sched_init
1655 #undef TARGET_SCHED_FINISH
1656 #define TARGET_SCHED_FINISH rs6000_sched_finish
1657 #undef TARGET_SCHED_REORDER
1658 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1659 #undef TARGET_SCHED_REORDER2
1660 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1662 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1663 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1665 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1666 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1668 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1669 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1670 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1671 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1672 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1673 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1674 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1675 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1677 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1678 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1680 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1681 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1682 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1683 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1684 rs6000_builtin_support_vector_misalignment
1685 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1686 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1687 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1688 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1689 rs6000_builtin_vectorization_cost
1690 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1691 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1692 rs6000_preferred_simd_mode
1693 #undef TARGET_VECTORIZE_INIT_COST
1694 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1695 #undef TARGET_VECTORIZE_ADD_STMT_COST
1696 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1697 #undef TARGET_VECTORIZE_FINISH_COST
1698 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1699 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1700 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1702 #undef TARGET_INIT_BUILTINS
1703 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1704 #undef TARGET_BUILTIN_DECL
1705 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1707 #undef TARGET_FOLD_BUILTIN
1708 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1709 #undef TARGET_GIMPLE_FOLD_BUILTIN
1710 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1712 #undef TARGET_EXPAND_BUILTIN
1713 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1715 #undef TARGET_MANGLE_TYPE
1716 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1718 #undef TARGET_INIT_LIBFUNCS
1719 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1722 #undef TARGET_BINDS_LOCAL_P
1723 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1726 #undef TARGET_MS_BITFIELD_LAYOUT_P
1727 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1729 #undef TARGET_ASM_OUTPUT_MI_THUNK
1730 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1732 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1733 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1735 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1736 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1738 #undef TARGET_REGISTER_MOVE_COST
1739 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1740 #undef TARGET_MEMORY_MOVE_COST
1741 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1742 #undef TARGET_CANNOT_COPY_INSN_P
1743 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1744 #undef TARGET_RTX_COSTS
1745 #define TARGET_RTX_COSTS rs6000_rtx_costs
1746 #undef TARGET_ADDRESS_COST
1747 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1748 #undef TARGET_INSN_COST
1749 #define TARGET_INSN_COST rs6000_insn_cost
1751 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1752 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1754 #undef TARGET_PROMOTE_FUNCTION_MODE
1755 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1757 #undef TARGET_RETURN_IN_MEMORY
1758 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1760 #undef TARGET_RETURN_IN_MSB
1761 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1763 #undef TARGET_SETUP_INCOMING_VARARGS
1764 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1766 /* Always strict argument naming on rs6000. */
1767 #undef TARGET_STRICT_ARGUMENT_NAMING
1768 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1769 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1770 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1771 #undef TARGET_SPLIT_COMPLEX_ARG
1772 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1773 #undef TARGET_MUST_PASS_IN_STACK
1774 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1775 #undef TARGET_PASS_BY_REFERENCE
1776 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1777 #undef TARGET_ARG_PARTIAL_BYTES
1778 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1779 #undef TARGET_FUNCTION_ARG_ADVANCE
1780 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1781 #undef TARGET_FUNCTION_ARG
1782 #define TARGET_FUNCTION_ARG rs6000_function_arg
1783 #undef TARGET_FUNCTION_ARG_PADDING
1784 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1785 #undef TARGET_FUNCTION_ARG_BOUNDARY
1786 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1788 #undef TARGET_BUILD_BUILTIN_VA_LIST
1789 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1791 #undef TARGET_EXPAND_BUILTIN_VA_START
1792 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1794 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1795 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1797 #undef TARGET_EH_RETURN_FILTER_MODE
1798 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1800 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1801 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1803 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1804 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1806 #undef TARGET_FLOATN_MODE
1807 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1809 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1810 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1812 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1813 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1815 #undef TARGET_MD_ASM_ADJUST
1816 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1818 #undef TARGET_OPTION_OVERRIDE
1819 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1821 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1822 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1823 rs6000_builtin_vectorized_function
1825 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1826 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1827 rs6000_builtin_md_vectorized_function
1829 #undef TARGET_STACK_PROTECT_GUARD
1830 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1833 #undef TARGET_STACK_PROTECT_FAIL
1834 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1838 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1839 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1842 /* Use a 32-bit anchor range. This leads to sequences like:
1844 addis tmp,anchor,high
1847 where tmp itself acts as an anchor, and can be shared between
1848 accesses to the same 64k page. */
1849 #undef TARGET_MIN_ANCHOR_OFFSET
1850 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1851 #undef TARGET_MAX_ANCHOR_OFFSET
1852 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1853 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1854 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1855 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1856 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1858 #undef TARGET_BUILTIN_RECIPROCAL
1859 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1861 #undef TARGET_SECONDARY_RELOAD
1862 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1863 #undef TARGET_SECONDARY_MEMORY_NEEDED
1864 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1865 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1866 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1868 #undef TARGET_LEGITIMATE_ADDRESS_P
1869 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1871 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1872 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1874 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1875 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1877 #undef TARGET_CAN_ELIMINATE
1878 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1880 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1881 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1883 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1884 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1886 #undef TARGET_TRAMPOLINE_INIT
1887 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1889 #undef TARGET_FUNCTION_VALUE
1890 #define TARGET_FUNCTION_VALUE rs6000_function_value
1892 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1893 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1895 #undef TARGET_OPTION_SAVE
1896 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1898 #undef TARGET_OPTION_RESTORE
1899 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1901 #undef TARGET_OPTION_PRINT
1902 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1904 #undef TARGET_CAN_INLINE_P
1905 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1907 #undef TARGET_SET_CURRENT_FUNCTION
1908 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1910 #undef TARGET_LEGITIMATE_CONSTANT_P
1911 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1913 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1914 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1916 #undef TARGET_CAN_USE_DOLOOP_P
1917 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1919 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1920 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1922 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1923 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1924 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1925 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1926 #undef TARGET_UNWIND_WORD_MODE
1927 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1929 #undef TARGET_OFFLOAD_OPTIONS
1930 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1932 #undef TARGET_C_MODE_FOR_SUFFIX
1933 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1935 #undef TARGET_INVALID_BINARY_OP
1936 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1938 #undef TARGET_OPTAB_SUPPORTED_P
1939 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1941 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1942 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1944 #undef TARGET_COMPARE_VERSION_PRIORITY
1945 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1947 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1948 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1949 rs6000_generate_version_dispatcher_body
1951 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1952 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1953 rs6000_get_function_versions_dispatcher
1955 #undef TARGET_OPTION_FUNCTION_VERSIONS
1956 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1958 #undef TARGET_HARD_REGNO_NREGS
1959 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1960 #undef TARGET_HARD_REGNO_MODE_OK
1961 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1963 #undef TARGET_MODES_TIEABLE_P
1964 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1966 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1967 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1968 rs6000_hard_regno_call_part_clobbered
1970 #undef TARGET_SLOW_UNALIGNED_ACCESS
1971 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1973 #undef TARGET_CAN_CHANGE_MODE_CLASS
1974 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1976 #undef TARGET_CONSTANT_ALIGNMENT
1977 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1979 #undef TARGET_STARTING_FRAME_OFFSET
1980 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1983 /* Processor table. */
1986 const char *const name; /* Canonical processor name. */
1987 const enum processor_type processor; /* Processor type enum value. */
1988 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1991 static struct rs6000_ptt const processor_target_table[] =
1993 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1994 #include "rs6000-cpus.def"
1998 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2002 rs6000_cpu_name_lookup (const char *name)
2008 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2009 if (! strcmp (name, processor_target_table[i].name))
2017 /* Return number of consecutive hard regs needed starting at reg REGNO
2018 to hold something of mode MODE.
2019 This is ordinarily the length in words of a value of mode MODE
2020 but can be less for certain modes in special long registers.
2022 POWER and PowerPC GPRs hold 32 bits worth;
2023 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2026 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2028 unsigned HOST_WIDE_INT reg_size;
2030 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2031 128-bit floating point that can go in vector registers, which has VSX
2032 memory addressing. */
2033 if (FP_REGNO_P (regno))
2034 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2035 ? UNITS_PER_VSX_WORD
2036 : UNITS_PER_FP_WORD);
2038 else if (ALTIVEC_REGNO_P (regno))
2039 reg_size = UNITS_PER_ALTIVEC_WORD;
2042 reg_size = UNITS_PER_WORD;
2044 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2047 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2050 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2052 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2054 if (COMPLEX_MODE_P (mode))
2055 mode = GET_MODE_INNER (mode);
2057 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2058 register combinations, and use PTImode where we need to deal with quad
2059 word memory operations. Don't allow quad words in the argument or frame
2060 pointer registers, just registers 0..31. */
2061 if (mode == PTImode)
2062 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2063 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2064 && ((regno & 1) == 0));
2066 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2067 implementations. Don't allow an item to be split between a FP register
2068 and an Altivec register. Allow TImode in all VSX registers if the user
2070 if (TARGET_VSX && VSX_REGNO_P (regno)
2071 && (VECTOR_MEM_VSX_P (mode)
2072 || FLOAT128_VECTOR_P (mode)
2073 || reg_addr[mode].scalar_in_vmx_p
2075 || (TARGET_VADDUQM && mode == V1TImode)))
2077 if (FP_REGNO_P (regno))
2078 return FP_REGNO_P (last_regno);
2080 if (ALTIVEC_REGNO_P (regno))
2082 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2085 return ALTIVEC_REGNO_P (last_regno);
2089 /* The GPRs can hold any mode, but values bigger than one register
2090 cannot go past R31. */
2091 if (INT_REGNO_P (regno))
2092 return INT_REGNO_P (last_regno);
2094 /* The float registers (except for VSX vector modes) can only hold floating
2095 modes and DImode. */
2096 if (FP_REGNO_P (regno))
2098 if (FLOAT128_VECTOR_P (mode))
2101 if (SCALAR_FLOAT_MODE_P (mode)
2102 && (mode != TDmode || (regno % 2) == 0)
2103 && FP_REGNO_P (last_regno))
2106 if (GET_MODE_CLASS (mode) == MODE_INT)
2108 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2111 if (TARGET_P8_VECTOR && (mode == SImode))
2114 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2118 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
2119 && PAIRED_VECTOR_MODE (mode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2191 if (PAIRED_VECTOR_MODE (mode1))
2192 return PAIRED_VECTOR_MODE (mode2);
2193 if (PAIRED_VECTOR_MODE (mode2))
2199 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2202 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2206 && GET_MODE_SIZE (mode) > 4
2207 && INT_REGNO_P (regno))
2211 && FP_REGNO_P (regno)
2212 && GET_MODE_SIZE (mode) > 8
2213 && !FLOAT128_2REG_P (mode))
2219 /* Print interesting facts about registers. */
2221 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2225 for (r = first_regno; r <= last_regno; ++r)
2227 const char *comma = "";
2230 if (first_regno == last_regno)
2231 fprintf (stderr, "%s:\t", reg_name);
2233 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2236 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2237 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2241 fprintf (stderr, ",\n\t");
2246 if (rs6000_hard_regno_nregs[m][r] > 1)
2247 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2248 rs6000_hard_regno_nregs[m][r]);
2250 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2255 if (call_used_regs[r])
2259 fprintf (stderr, ",\n\t");
2264 len += fprintf (stderr, "%s%s", comma, "call-used");
2272 fprintf (stderr, ",\n\t");
2277 len += fprintf (stderr, "%s%s", comma, "fixed");
2283 fprintf (stderr, ",\n\t");
2287 len += fprintf (stderr, "%sreg-class = %s", comma,
2288 reg_class_names[(int)rs6000_regno_regclass[r]]);
2293 fprintf (stderr, ",\n\t");
2297 fprintf (stderr, "%sregno = %d\n", comma, r);
2302 rs6000_debug_vector_unit (enum rs6000_vector v)
2308 case VECTOR_NONE: ret = "none"; break;
2309 case VECTOR_ALTIVEC: ret = "altivec"; break;
2310 case VECTOR_VSX: ret = "vsx"; break;
2311 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2312 case VECTOR_PAIRED: ret = "paired"; break;
2313 case VECTOR_OTHER: ret = "other"; break;
2314 default: ret = "unknown"; break;
2320 /* Inner function printing just the address mask for a particular reload
2322 DEBUG_FUNCTION char *
2323 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2328 if ((mask & RELOAD_REG_VALID) != 0)
2330 else if (keep_spaces)
2333 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2335 else if (keep_spaces)
2338 if ((mask & RELOAD_REG_INDEXED) != 0)
2340 else if (keep_spaces)
2343 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2345 else if ((mask & RELOAD_REG_OFFSET) != 0)
2347 else if (keep_spaces)
2350 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2352 else if (keep_spaces)
2355 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2357 else if (keep_spaces)
2360 if ((mask & RELOAD_REG_AND_M16) != 0)
2362 else if (keep_spaces)
2370 /* Print the address masks in a human readble fashion. */
2372 rs6000_debug_print_mode (ssize_t m)
2378 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2379 for (rc = 0; rc < N_RELOAD_REG; rc++)
2380 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2381 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2383 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2384 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2385 fprintf (stderr, " Reload=%c%c",
2386 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2387 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2389 spaces += sizeof (" Reload=sl") - 1;
2391 if (reg_addr[m].scalar_in_vmx_p)
2393 fprintf (stderr, "%*s Upper=y", spaces, "");
2397 spaces += sizeof (" Upper=y") - 1;
2399 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2400 || reg_addr[m].fused_toc);
2403 for (rc = 0; rc < N_RELOAD_REG; rc++)
2405 if (rc != RELOAD_REG_ANY)
2407 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2408 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2410 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2411 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2413 fuse_extra_p = true;
2422 fprintf (stderr, "%*s Fuse:", spaces, "");
2425 for (rc = 0; rc < N_RELOAD_REG; rc++)
2427 if (rc != RELOAD_REG_ANY)
2431 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2433 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2438 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2440 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2445 if (load == '-' && store == '-')
2449 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2450 reload_reg_map[rc].name[0], load, store);
2456 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2458 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2462 spaces += sizeof (" P8gpr") - 1;
2464 if (reg_addr[m].fused_toc)
2466 fprintf (stderr, "%*sToc", (spaces + 1), "");
2470 spaces += sizeof (" Toc") - 1;
2473 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2475 if (rs6000_vector_unit[m] != VECTOR_NONE
2476 || rs6000_vector_mem[m] != VECTOR_NONE)
2478 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2480 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2481 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2484 fputs ("\n", stderr);
2487 #define DEBUG_FMT_ID "%-32s= "
2488 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2489 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2490 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2492 /* Print various interesting information with -mdebug=reg. */
2494 rs6000_debug_reg_global (void)
2496 static const char *const tf[2] = { "false", "true" };
2497 const char *nl = (const char *)0;
2500 char costly_num[20];
2502 char flags_buffer[40];
2503 const char *costly_str;
2504 const char *nop_str;
2505 const char *trace_str;
2506 const char *abi_str;
2507 const char *cmodel_str;
2508 struct cl_target_option cl_opts;
2510 /* Modes we want tieable information on. */
2511 static const machine_mode print_tieable_modes[] = {
2547 /* Virtual regs we are interested in. */
2548 const static struct {
2549 int regno; /* register number. */
2550 const char *name; /* register name. */
2551 } virtual_regs[] = {
2552 { STACK_POINTER_REGNUM, "stack pointer:" },
2553 { TOC_REGNUM, "toc: " },
2554 { STATIC_CHAIN_REGNUM, "static chain: " },
2555 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2556 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2557 { ARG_POINTER_REGNUM, "arg pointer: " },
2558 { FRAME_POINTER_REGNUM, "frame pointer:" },
2559 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2560 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2561 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2562 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2563 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2564 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2565 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2566 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2567 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2570 fputs ("\nHard register information:\n", stderr);
2571 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2572 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2573 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2576 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2577 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2578 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2579 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2580 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2581 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2583 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2584 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2585 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2589 "d reg_class = %s\n"
2590 "f reg_class = %s\n"
2591 "v reg_class = %s\n"
2592 "wa reg_class = %s\n"
2593 "wb reg_class = %s\n"
2594 "wd reg_class = %s\n"
2595 "we reg_class = %s\n"
2596 "wf reg_class = %s\n"
2597 "wg reg_class = %s\n"
2598 "wh reg_class = %s\n"
2599 "wi reg_class = %s\n"
2600 "wj reg_class = %s\n"
2601 "wk reg_class = %s\n"
2602 "wl reg_class = %s\n"
2603 "wm reg_class = %s\n"
2604 "wo reg_class = %s\n"
2605 "wp reg_class = %s\n"
2606 "wq reg_class = %s\n"
2607 "wr reg_class = %s\n"
2608 "ws reg_class = %s\n"
2609 "wt reg_class = %s\n"
2610 "wu reg_class = %s\n"
2611 "wv reg_class = %s\n"
2612 "ww reg_class = %s\n"
2613 "wx reg_class = %s\n"
2614 "wy reg_class = %s\n"
2615 "wz reg_class = %s\n"
2616 "wA reg_class = %s\n"
2617 "wH reg_class = %s\n"
2618 "wI reg_class = %s\n"
2619 "wJ reg_class = %s\n"
2620 "wK reg_class = %s\n"
2622 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2651 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2652 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2653 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2656 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2657 rs6000_debug_print_mode (m);
2659 fputs ("\n", stderr);
2661 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2663 machine_mode mode1 = print_tieable_modes[m1];
2664 bool first_time = true;
2666 nl = (const char *)0;
2667 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2669 machine_mode mode2 = print_tieable_modes[m2];
2670 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2674 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2679 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2684 fputs ("\n", stderr);
2690 if (rs6000_recip_control)
2692 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2694 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2695 if (rs6000_recip_bits[m])
2698 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2700 (RS6000_RECIP_AUTO_RE_P (m)
2702 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2703 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2705 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2708 fputs ("\n", stderr);
2711 if (rs6000_cpu_index >= 0)
2713 const char *name = processor_target_table[rs6000_cpu_index].name;
2715 = processor_target_table[rs6000_cpu_index].target_enable;
2717 sprintf (flags_buffer, "-mcpu=%s flags", name);
2718 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2721 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2723 if (rs6000_tune_index >= 0)
2725 const char *name = processor_target_table[rs6000_tune_index].name;
2727 = processor_target_table[rs6000_tune_index].target_enable;
2729 sprintf (flags_buffer, "-mtune=%s flags", name);
2730 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2733 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2735 cl_target_option_save (&cl_opts, &global_options);
2736 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2739 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2740 rs6000_isa_flags_explicit);
2742 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2743 rs6000_builtin_mask);
2745 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2747 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2748 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2750 switch (rs6000_sched_costly_dep)
2752 case max_dep_latency:
2753 costly_str = "max_dep_latency";
2757 costly_str = "no_dep_costly";
2760 case all_deps_costly:
2761 costly_str = "all_deps_costly";
2764 case true_store_to_load_dep_costly:
2765 costly_str = "true_store_to_load_dep_costly";
2768 case store_to_load_dep_costly:
2769 costly_str = "store_to_load_dep_costly";
2773 costly_str = costly_num;
2774 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2778 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2780 switch (rs6000_sched_insert_nops)
2782 case sched_finish_regroup_exact:
2783 nop_str = "sched_finish_regroup_exact";
2786 case sched_finish_pad_groups:
2787 nop_str = "sched_finish_pad_groups";
2790 case sched_finish_none:
2791 nop_str = "sched_finish_none";
2796 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2800 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2802 switch (rs6000_sdata)
2809 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2813 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2817 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2822 switch (rs6000_traceback)
2824 case traceback_default: trace_str = "default"; break;
2825 case traceback_none: trace_str = "none"; break;
2826 case traceback_part: trace_str = "part"; break;
2827 case traceback_full: trace_str = "full"; break;
2828 default: trace_str = "unknown"; break;
2831 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2833 switch (rs6000_current_cmodel)
2835 case CMODEL_SMALL: cmodel_str = "small"; break;
2836 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2837 case CMODEL_LARGE: cmodel_str = "large"; break;
2838 default: cmodel_str = "unknown"; break;
2841 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2843 switch (rs6000_current_abi)
2845 case ABI_NONE: abi_str = "none"; break;
2846 case ABI_AIX: abi_str = "aix"; break;
2847 case ABI_ELFv2: abi_str = "ELFv2"; break;
2848 case ABI_V4: abi_str = "V4"; break;
2849 case ABI_DARWIN: abi_str = "darwin"; break;
2850 default: abi_str = "unknown"; break;
2853 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2855 if (rs6000_altivec_abi)
2856 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2858 if (rs6000_darwin64_abi)
2859 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2861 fprintf (stderr, DEBUG_FMT_S, "single_float",
2862 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2864 fprintf (stderr, DEBUG_FMT_S, "double_float",
2865 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2867 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2868 (TARGET_SOFT_FLOAT ? "true" : "false"));
2870 if (TARGET_LINK_STACK)
2871 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2873 if (TARGET_P8_FUSION)
2877 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2878 if (TARGET_TOC_FUSION)
2879 strcat (options, ", toc");
2881 if (TARGET_P8_FUSION_SIGN)
2882 strcat (options, ", sign");
2884 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2887 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2888 TARGET_SECURE_PLT ? "secure" : "bss");
2889 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2890 aix_struct_return ? "aix" : "sysv");
2891 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2892 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2893 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2894 tf[!!rs6000_align_branch_targets]);
2895 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2896 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2897 rs6000_long_double_type_size);
2898 if (rs6000_long_double_type_size == 128)
2900 fprintf (stderr, DEBUG_FMT_S, "long double type",
2901 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2902 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2903 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2905 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2906 (int)rs6000_sched_restricted_insns_priority);
2907 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2909 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2910 (int)RS6000_BUILTIN_COUNT);
2912 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2913 (int)TARGET_FLOAT128_ENABLE_TYPE);
2916 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2917 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2919 if (TARGET_DIRECT_MOVE_128)
2920 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2921 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2925 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2926 legitimate address support to figure out the appropriate addressing to
2930 rs6000_setup_reg_addr_masks (void)
2932 ssize_t rc, reg, m, nregs;
2933 addr_mask_type any_addr_mask, addr_mask;
2935 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2937 machine_mode m2 = (machine_mode) m;
2938 bool complex_p = false;
2939 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2942 if (COMPLEX_MODE_P (m2))
2945 m2 = GET_MODE_INNER (m2);
2948 msize = GET_MODE_SIZE (m2);
2950 /* SDmode is special in that we want to access it only via REG+REG
2951 addressing on power7 and above, since we want to use the LFIWZX and
2952 STFIWZX instructions to load it. */
2953 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2956 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2959 reg = reload_reg_map[rc].reg;
2961 /* Can mode values go in the GPR/FPR/Altivec registers? */
2962 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2964 bool small_int_vsx_p = (small_int_p
2965 && (rc == RELOAD_REG_FPR
2966 || rc == RELOAD_REG_VMX));
2968 nregs = rs6000_hard_regno_nregs[m][reg];
2969 addr_mask |= RELOAD_REG_VALID;
2971 /* Indicate if the mode takes more than 1 physical register. If
2972 it takes a single register, indicate it can do REG+REG
2973 addressing. Small integers in VSX registers can only do
2974 REG+REG addressing. */
2975 if (small_int_vsx_p)
2976 addr_mask |= RELOAD_REG_INDEXED;
2977 else if (nregs > 1 || m == BLKmode || complex_p)
2978 addr_mask |= RELOAD_REG_MULTIPLE;
2980 addr_mask |= RELOAD_REG_INDEXED;
2982 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2983 addressing. If we allow scalars into Altivec registers,
2984 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2987 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2989 && !VECTOR_MODE_P (m2)
2990 && !FLOAT128_VECTOR_P (m2)
2992 && !small_int_vsx_p)
2994 addr_mask |= RELOAD_REG_PRE_INCDEC;
2996 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2997 we don't allow PRE_MODIFY for some multi-register
3002 addr_mask |= RELOAD_REG_PRE_MODIFY;
3006 if (TARGET_POWERPC64)
3007 addr_mask |= RELOAD_REG_PRE_MODIFY;
3013 addr_mask |= RELOAD_REG_PRE_MODIFY;
3019 /* GPR and FPR registers can do REG+OFFSET addressing, except
3020 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3021 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3022 if ((addr_mask != 0) && !indexed_only_p
3024 && (rc == RELOAD_REG_GPR
3025 || ((msize == 8 || m2 == SFmode)
3026 && (rc == RELOAD_REG_FPR
3027 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3028 addr_mask |= RELOAD_REG_OFFSET;
3030 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3031 instructions are enabled. The offset for 128-bit VSX registers is
3032 only 12-bits. While GPRs can handle the full offset range, VSX
3033 registers can only handle the restricted range. */
3034 else if ((addr_mask != 0) && !indexed_only_p
3035 && msize == 16 && TARGET_P9_VECTOR
3036 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3037 || (m2 == TImode && TARGET_VSX)))
3039 addr_mask |= RELOAD_REG_OFFSET;
3040 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3041 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3044 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3045 addressing on 128-bit types. */
3046 if (rc == RELOAD_REG_VMX && msize == 16
3047 && (addr_mask & RELOAD_REG_VALID) != 0)
3048 addr_mask |= RELOAD_REG_AND_M16;
3050 reg_addr[m].addr_mask[rc] = addr_mask;
3051 any_addr_mask |= addr_mask;
3054 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3059 /* Initialize the various global tables that are based on register size. */
3061 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3067 /* Precalculate REGNO_REG_CLASS. */
3068 rs6000_regno_regclass[0] = GENERAL_REGS;
3069 for (r = 1; r < 32; ++r)
3070 rs6000_regno_regclass[r] = BASE_REGS;
3072 for (r = 32; r < 64; ++r)
3073 rs6000_regno_regclass[r] = FLOAT_REGS;
3075 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3076 rs6000_regno_regclass[r] = NO_REGS;
3078 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3079 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3081 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3082 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3083 rs6000_regno_regclass[r] = CR_REGS;
3085 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3086 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3087 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3088 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3089 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3090 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3091 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3092 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3093 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3094 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3096 /* Precalculate register class to simpler reload register class. We don't
3097 need all of the register classes that are combinations of different
3098 classes, just the simple ones that have constraint letters. */
3099 for (c = 0; c < N_REG_CLASSES; c++)
3100 reg_class_to_reg_type[c] = NO_REG_TYPE;
3102 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3103 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3104 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3105 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3106 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3107 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3108 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3109 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3110 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3111 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3115 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3116 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3120 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3121 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3124 /* Precalculate the valid memory formats as well as the vector information,
3125 this must be set up before the rs6000_hard_regno_nregs_internal calls
3127 gcc_assert ((int)VECTOR_NONE == 0);
3128 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3129 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3131 gcc_assert ((int)CODE_FOR_nothing == 0);
3132 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3134 gcc_assert ((int)NO_REGS == 0);
3135 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3137 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3138 believes it can use native alignment or still uses 128-bit alignment. */
3139 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3150 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3151 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3152 if (TARGET_FLOAT128_TYPE)
3154 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3155 rs6000_vector_align[KFmode] = 128;
3157 if (FLOAT128_IEEE_P (TFmode))
3159 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3160 rs6000_vector_align[TFmode] = 128;
3164 /* V2DF mode, VSX only. */
3167 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3168 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3169 rs6000_vector_align[V2DFmode] = align64;
3172 /* V4SF mode, either VSX or Altivec. */
3175 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3176 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3177 rs6000_vector_align[V4SFmode] = align32;
3179 else if (TARGET_ALTIVEC)
3181 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3182 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3183 rs6000_vector_align[V4SFmode] = align32;
3186 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3190 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3191 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3192 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3193 rs6000_vector_align[V4SImode] = align32;
3194 rs6000_vector_align[V8HImode] = align32;
3195 rs6000_vector_align[V16QImode] = align32;
3199 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3200 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3201 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3205 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3206 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3207 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3211 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3212 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3215 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3216 rs6000_vector_unit[V2DImode]
3217 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3218 rs6000_vector_align[V2DImode] = align64;
3220 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3221 rs6000_vector_unit[V1TImode]
3222 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3223 rs6000_vector_align[V1TImode] = 128;
3226 /* DFmode, see if we want to use the VSX unit. Memory is handled
3227 differently, so don't set rs6000_vector_mem. */
3230 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3231 rs6000_vector_align[DFmode] = 64;
3234 /* SFmode, see if we want to use the VSX unit. */
3235 if (TARGET_P8_VECTOR)
3237 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3238 rs6000_vector_align[SFmode] = 32;
3241 /* Allow TImode in VSX register and set the VSX memory macros. */
3244 rs6000_vector_mem[TImode] = VECTOR_VSX;
3245 rs6000_vector_align[TImode] = align64;
3248 /* TODO add paired floating point vector support. */
3250 /* Register class constraints for the constraints that depend on compile
3251 switches. When the VSX code was added, different constraints were added
3252 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3253 of the VSX registers are used. The register classes for scalar floating
3254 point types is set, based on whether we allow that type into the upper
3255 (Altivec) registers. GCC has register classes to target the Altivec
3256 registers for load/store operations, to select using a VSX memory
3257 operation instead of the traditional floating point operation. The
3260 d - Register class to use with traditional DFmode instructions.
3261 f - Register class to use with traditional SFmode instructions.
3262 v - Altivec register.
3263 wa - Any VSX register.
3264 wc - Reserved to represent individual CR bits (used in LLVM).
3265 wd - Preferred register class for V2DFmode.
3266 wf - Preferred register class for V4SFmode.
3267 wg - Float register for power6x move insns.
3268 wh - FP register for direct move instructions.
3269 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3270 wj - FP or VSX register to hold 64-bit integers for direct moves.
3271 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3272 wl - Float register if we can do 32-bit signed int loads.
3273 wm - VSX register for ISA 2.07 direct move operations.
3274 wn - always NO_REGS.
3275 wr - GPR if 64-bit mode is permitted.
3276 ws - Register class to do ISA 2.06 DF operations.
3277 wt - VSX register for TImode in VSX registers.
3278 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3279 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3280 ww - Register class to do SF conversions in with VSX operations.
3281 wx - Float register if we can do 32-bit int stores.
3282 wy - Register class to do ISA 2.07 SF operations.
3283 wz - Float register if we can do 32-bit unsigned int loads.
3284 wH - Altivec register if SImode is allowed in VSX registers.
3285 wI - VSX register if SImode is allowed in VSX registers.
3286 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3287 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3289 if (TARGET_HARD_FLOAT)
3290 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3292 if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
3293 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3297 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3298 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3299 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3300 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3301 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3302 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3303 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3306 /* Add conditional constraints based on various options, to allow us to
3307 collapse multiple insn patterns. */
3309 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3311 if (TARGET_MFPGPR) /* DFmode */
3312 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3315 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3317 if (TARGET_DIRECT_MOVE)
3319 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3320 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3321 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3322 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3323 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3324 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3327 if (TARGET_POWERPC64)
3329 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3330 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3333 if (TARGET_P8_VECTOR) /* SFmode */
3335 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3336 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3337 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3339 else if (TARGET_VSX)
3340 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3343 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3346 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3348 if (TARGET_FLOAT128_TYPE)
3350 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3351 if (FLOAT128_IEEE_P (TFmode))
3352 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3355 if (TARGET_P9_VECTOR)
3357 /* Support for new D-form instructions. */
3358 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3360 /* Support for ISA 3.0 (power9) vectors. */
3361 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3364 /* Support for new direct moves (ISA 3.0 + 64bit). */
3365 if (TARGET_DIRECT_MOVE_128)
3366 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3368 /* Support small integers in VSX registers. */
3369 if (TARGET_P8_VECTOR)
3371 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3372 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3373 if (TARGET_P9_VECTOR)
3375 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3376 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3380 /* Set up the reload helper and direct move functions. */
3381 if (TARGET_VSX || TARGET_ALTIVEC)
3385 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3386 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3387 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3388 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3389 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3390 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3391 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3392 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3393 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3394 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3395 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3396 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3397 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3398 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3399 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3400 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3401 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3402 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3403 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3404 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3406 if (FLOAT128_VECTOR_P (KFmode))
3408 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3409 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3412 if (FLOAT128_VECTOR_P (TFmode))
3414 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3415 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3418 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3420 if (TARGET_NO_SDMODE_STACK)
3422 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3423 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3428 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3429 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3432 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3434 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3435 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3436 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3437 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3438 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3439 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3440 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3441 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3442 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3444 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3445 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3446 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3447 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3448 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3449 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3450 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3451 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3452 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3454 if (FLOAT128_VECTOR_P (KFmode))
3456 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3457 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3460 if (FLOAT128_VECTOR_P (TFmode))
3462 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3463 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3469 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3470 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3471 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3472 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3473 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3474 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3475 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3476 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3477 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3478 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3479 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3480 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3481 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3482 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3483 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3484 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3485 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3486 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3487 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3488 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3490 if (FLOAT128_VECTOR_P (KFmode))
3492 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3493 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3496 if (FLOAT128_IEEE_P (TFmode))
3498 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3499 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3502 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3504 if (TARGET_NO_SDMODE_STACK)
3506 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3507 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3512 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3513 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3516 if (TARGET_DIRECT_MOVE)
3518 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3519 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3520 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3524 reg_addr[DFmode].scalar_in_vmx_p = true;
3525 reg_addr[DImode].scalar_in_vmx_p = true;
3527 if (TARGET_P8_VECTOR)
3529 reg_addr[SFmode].scalar_in_vmx_p = true;
3530 reg_addr[SImode].scalar_in_vmx_p = true;
3532 if (TARGET_P9_VECTOR)
3534 reg_addr[HImode].scalar_in_vmx_p = true;
3535 reg_addr[QImode].scalar_in_vmx_p = true;
3540 /* Setup the fusion operations. */
3541 if (TARGET_P8_FUSION)
3543 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3544 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3545 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3547 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3550 if (TARGET_P9_FUSION)
3553 enum machine_mode mode; /* mode of the fused type. */
3554 enum machine_mode pmode; /* pointer mode. */
3555 enum rs6000_reload_reg_type rtype; /* register type. */
3556 enum insn_code load; /* load insn. */
3557 enum insn_code store; /* store insn. */
3560 static const struct fuse_insns addis_insns[] = {
3561 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3562 CODE_FOR_fusion_vsx_di_sf_load,
3563 CODE_FOR_fusion_vsx_di_sf_store },
3565 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3566 CODE_FOR_fusion_vsx_si_sf_load,
3567 CODE_FOR_fusion_vsx_si_sf_store },
3569 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3570 CODE_FOR_fusion_vsx_di_df_load,
3571 CODE_FOR_fusion_vsx_di_df_store },
3573 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3574 CODE_FOR_fusion_vsx_si_df_load,
3575 CODE_FOR_fusion_vsx_si_df_store },
3577 { E_DImode, E_DImode, RELOAD_REG_FPR,
3578 CODE_FOR_fusion_vsx_di_di_load,
3579 CODE_FOR_fusion_vsx_di_di_store },
3581 { E_DImode, E_SImode, RELOAD_REG_FPR,
3582 CODE_FOR_fusion_vsx_si_di_load,
3583 CODE_FOR_fusion_vsx_si_di_store },
3585 { E_QImode, E_DImode, RELOAD_REG_GPR,
3586 CODE_FOR_fusion_gpr_di_qi_load,
3587 CODE_FOR_fusion_gpr_di_qi_store },
3589 { E_QImode, E_SImode, RELOAD_REG_GPR,
3590 CODE_FOR_fusion_gpr_si_qi_load,
3591 CODE_FOR_fusion_gpr_si_qi_store },
3593 { E_HImode, E_DImode, RELOAD_REG_GPR,
3594 CODE_FOR_fusion_gpr_di_hi_load,
3595 CODE_FOR_fusion_gpr_di_hi_store },
3597 { E_HImode, E_SImode, RELOAD_REG_GPR,
3598 CODE_FOR_fusion_gpr_si_hi_load,
3599 CODE_FOR_fusion_gpr_si_hi_store },
3601 { E_SImode, E_DImode, RELOAD_REG_GPR,
3602 CODE_FOR_fusion_gpr_di_si_load,
3603 CODE_FOR_fusion_gpr_di_si_store },
3605 { E_SImode, E_SImode, RELOAD_REG_GPR,
3606 CODE_FOR_fusion_gpr_si_si_load,
3607 CODE_FOR_fusion_gpr_si_si_store },
3609 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3610 CODE_FOR_fusion_gpr_di_sf_load,
3611 CODE_FOR_fusion_gpr_di_sf_store },
3613 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3614 CODE_FOR_fusion_gpr_si_sf_load,
3615 CODE_FOR_fusion_gpr_si_sf_store },
3617 { E_DImode, E_DImode, RELOAD_REG_GPR,
3618 CODE_FOR_fusion_gpr_di_di_load,
3619 CODE_FOR_fusion_gpr_di_di_store },
3621 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3622 CODE_FOR_fusion_gpr_di_df_load,
3623 CODE_FOR_fusion_gpr_di_df_store },
3626 machine_mode cur_pmode = Pmode;
3629 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3631 machine_mode xmode = addis_insns[i].mode;
3632 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3634 if (addis_insns[i].pmode != cur_pmode)
3637 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3640 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3641 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3643 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3645 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3646 = addis_insns[i].load;
3647 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3648 = addis_insns[i].store;
3653 /* Note which types we support fusing TOC setup plus memory insn. We only do
3654 fused TOCs for medium/large code models. */
3655 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3656 && (TARGET_CMODEL != CMODEL_SMALL))
3658 reg_addr[QImode].fused_toc = true;
3659 reg_addr[HImode].fused_toc = true;
3660 reg_addr[SImode].fused_toc = true;
3661 reg_addr[DImode].fused_toc = true;
3662 if (TARGET_HARD_FLOAT)
3664 if (TARGET_SINGLE_FLOAT)
3665 reg_addr[SFmode].fused_toc = true;
3666 if (TARGET_DOUBLE_FLOAT)
3667 reg_addr[DFmode].fused_toc = true;
3671 /* Precalculate HARD_REGNO_NREGS. */
3672 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3673 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3674 rs6000_hard_regno_nregs[m][r]
3675 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3677 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3678 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3679 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3680 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3681 rs6000_hard_regno_mode_ok_p[m][r] = true;
3683 /* Precalculate CLASS_MAX_NREGS sizes. */
3684 for (c = 0; c < LIM_REG_CLASSES; ++c)
3688 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3689 reg_size = UNITS_PER_VSX_WORD;
3691 else if (c == ALTIVEC_REGS)
3692 reg_size = UNITS_PER_ALTIVEC_WORD;
3694 else if (c == FLOAT_REGS)
3695 reg_size = UNITS_PER_FP_WORD;
3698 reg_size = UNITS_PER_WORD;
3700 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3702 machine_mode m2 = (machine_mode)m;
3703 int reg_size2 = reg_size;
3705 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3707 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3708 reg_size2 = UNITS_PER_FP_WORD;
3710 rs6000_class_max_nregs[m][c]
3711 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3715 /* Calculate which modes to automatically generate code to use a the
3716 reciprocal divide and square root instructions. In the future, possibly
3717 automatically generate the instructions even if the user did not specify
3718 -mrecip. The older machines double precision reciprocal sqrt estimate is
3719 not accurate enough. */
3720 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3722 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3724 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3725 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3726 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3727 if (VECTOR_UNIT_VSX_P (V2DFmode))
3728 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3730 if (TARGET_FRSQRTES)
3731 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3733 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3734 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3735 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3736 if (VECTOR_UNIT_VSX_P (V2DFmode))
3737 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3739 if (rs6000_recip_control)
3741 if (!flag_finite_math_only)
3742 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3744 if (flag_trapping_math)
3745 warning (0, "%qs requires %qs or %qs", "-mrecip",
3746 "-fno-trapping-math", "-ffast-math");
3747 if (!flag_reciprocal_math)
3748 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3750 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3752 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3753 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3754 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3756 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3757 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3758 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3760 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3761 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3762 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3764 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3765 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3766 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3768 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3769 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3770 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3772 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3773 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3774 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3776 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3777 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3778 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3780 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3781 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3782 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3786 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3787 legitimate address support to figure out the appropriate addressing to
3789 rs6000_setup_reg_addr_masks ();
3791 if (global_init_p || TARGET_DEBUG_TARGET)
3793 if (TARGET_DEBUG_REG)
3794 rs6000_debug_reg_global ();
3796 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3798 "SImode variable mult cost = %d\n"
3799 "SImode constant mult cost = %d\n"
3800 "SImode short constant mult cost = %d\n"
3801 "DImode multipliciation cost = %d\n"
3802 "SImode division cost = %d\n"
3803 "DImode division cost = %d\n"
3804 "Simple fp operation cost = %d\n"
3805 "DFmode multiplication cost = %d\n"
3806 "SFmode division cost = %d\n"
3807 "DFmode division cost = %d\n"
3808 "cache line size = %d\n"
3809 "l1 cache size = %d\n"
3810 "l2 cache size = %d\n"
3811 "simultaneous prefetches = %d\n"
3814 rs6000_cost->mulsi_const,
3815 rs6000_cost->mulsi_const9,
3823 rs6000_cost->cache_line_size,
3824 rs6000_cost->l1_cache_size,
3825 rs6000_cost->l2_cache_size,
3826 rs6000_cost->simultaneous_prefetches);
3831 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3834 darwin_rs6000_override_options (void)
3836 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3838 rs6000_altivec_abi = 1;
3839 TARGET_ALTIVEC_VRSAVE = 1;
3840 rs6000_current_abi = ABI_DARWIN;
3842 if (DEFAULT_ABI == ABI_DARWIN
3844 darwin_one_byte_bool = 1;
3846 if (TARGET_64BIT && ! TARGET_POWERPC64)
3848 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3849 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3853 rs6000_default_long_calls = 1;
3854 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3857 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3859 if (!flag_mkernel && !flag_apple_kext
3861 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3862 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3864 /* Unless the user (not the configurer) has explicitly overridden
3865 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3866 G4 unless targeting the kernel. */
3869 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3870 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3871 && ! global_options_set.x_rs6000_cpu_index)
3873 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3878 /* If not otherwise specified by a target, make 'long double' equivalent to
3881 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3882 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3885 /* Return the builtin mask of the various options used that could affect which
3886 builtins were used. In the past we used target_flags, but we've run out of
3887 bits, and some options like PAIRED are no longer in target_flags. */
3890 rs6000_builtin_mask_calculate (void)
3892 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3893 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3894 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3895 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3896 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3897 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3898 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3899 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3900 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3901 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3902 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3903 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3904 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3905 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3906 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3907 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3908 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3909 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3910 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3911 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
3912 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3913 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3916 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3917 to clobber the XER[CA] bit because clobbering that bit without telling
3918 the compiler worked just fine with versions of GCC before GCC 5, and
3919 breaking a lot of older code in ways that are hard to track down is
3920 not such a great idea. */
3923 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3924 vec<const char *> &/*constraints*/,
3925 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3927 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3928 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3932 /* Override command line options.
3934 Combine build-specific configuration information with options
3935 specified on the command line to set various state variables which
3936 influence code generation, optimization, and expansion of built-in
3937 functions. Assure that command-line configuration preferences are
3938 compatible with each other and with the build configuration; issue
3939 warnings while adjusting configuration or error messages while
3940 rejecting configuration.
3942 Upon entry to this function:
3944 This function is called once at the beginning of
3945 compilation, and then again at the start and end of compiling
3946 each section of code that has a different configuration, as
3947 indicated, for example, by adding the
3949 __attribute__((__target__("cpu=power9")))
3951 qualifier to a function definition or, for example, by bracketing
3954 #pragma GCC target("altivec")
3958 #pragma GCC reset_options
3960 directives. Parameter global_init_p is true for the initial
3961 invocation, which initializes global variables, and false for all
3962 subsequent invocations.
3965 Various global state information is assumed to be valid. This
3966 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3967 default CPU specified at build configure time, TARGET_DEFAULT,
3968 representing the default set of option flags for the default
3969 target, and global_options_set.x_rs6000_isa_flags, representing
3970 which options were requested on the command line.
3972 Upon return from this function:
3974 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3975 was set by name on the command line. Additionally, if certain
3976 attributes are automatically enabled or disabled by this function
3977 in order to assure compatibility between options and
3978 configuration, the flags associated with those attributes are
3979 also set. By setting these "explicit bits", we avoid the risk
3980 that other code might accidentally overwrite these particular
3981 attributes with "default values".
3983 The various bits of rs6000_isa_flags are set to indicate the
3984 target options that have been selected for the most current
3985 compilation efforts. This has the effect of also turning on the
3986 associated TARGET_XXX values since these are macros which are
3987 generally defined to test the corresponding bit of the
3988 rs6000_isa_flags variable.
3990 The variable rs6000_builtin_mask is set to represent the target
3991 options for the most current compilation efforts, consistent with
3992 the current contents of rs6000_isa_flags. This variable controls
3993 expansion of built-in functions.
3995 Various other global variables and fields of global structures
3996 (over 50 in all) are initialized to reflect the desired options
3997 for the most current compilation efforts. */
4000 rs6000_option_override_internal (bool global_init_p)
4004 HOST_WIDE_INT set_masks;
4005 HOST_WIDE_INT ignore_masks;
4008 struct cl_target_option *main_target_opt
4009 = ((global_init_p || target_option_default_node == NULL)
4010 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4012 /* Print defaults. */
4013 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4014 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4016 /* Remember the explicit arguments. */
4018 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4020 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4021 library functions, so warn about it. The flag may be useful for
4022 performance studies from time to time though, so don't disable it
4024 if (global_options_set.x_rs6000_alignment_flags
4025 && rs6000_alignment_flags == MASK_ALIGN_POWER
4026 && DEFAULT_ABI == ABI_DARWIN
4028 warning (0, "%qs is not supported for 64-bit Darwin;"
4029 " it is incompatible with the installed C and C++ libraries",
4032 /* Numerous experiment shows that IRA based loop pressure
4033 calculation works better for RTL loop invariant motion on targets
4034 with enough (>= 32) registers. It is an expensive optimization.
4035 So it is on only for peak performance. */
4036 if (optimize >= 3 && global_init_p
4037 && !global_options_set.x_flag_ira_loop_pressure)
4038 flag_ira_loop_pressure = 1;
4040 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4041 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4042 options were already specified. */
4043 if (flag_sanitize & SANITIZE_USER_ADDRESS
4044 && !global_options_set.x_flag_asynchronous_unwind_tables)
4045 flag_asynchronous_unwind_tables = 1;
4047 /* Set the pointer size. */
4050 rs6000_pmode = DImode;
4051 rs6000_pointer_size = 64;
4055 rs6000_pmode = SImode;
4056 rs6000_pointer_size = 32;
4059 /* Some OSs don't support saving the high part of 64-bit registers on context
4060 switch. Other OSs don't support saving Altivec registers. On those OSs,
4061 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4062 if the user wants either, the user must explicitly specify them and we
4063 won't interfere with the user's specification. */
4065 set_masks = POWERPC_MASKS;
4066 #ifdef OS_MISSING_POWERPC64
4067 if (OS_MISSING_POWERPC64)
4068 set_masks &= ~OPTION_MASK_POWERPC64;
4070 #ifdef OS_MISSING_ALTIVEC
4071 if (OS_MISSING_ALTIVEC)
4072 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4073 | OTHER_VSX_VECTOR_MASKS);
4076 /* Don't override by the processor default if given explicitly. */
4077 set_masks &= ~rs6000_isa_flags_explicit;
4079 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4080 the cpu in a target attribute or pragma, but did not specify a tuning
4081 option, use the cpu for the tuning option rather than the option specified
4082 with -mtune on the command line. Process a '--with-cpu' configuration
4083 request as an implicit --cpu. */
4084 if (rs6000_cpu_index >= 0)
4085 cpu_index = rs6000_cpu_index;
4086 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4087 cpu_index = main_target_opt->x_rs6000_cpu_index;
4088 else if (OPTION_TARGET_CPU_DEFAULT)
4089 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4093 const char *unavailable_cpu = NULL;
4094 switch (processor_target_table[cpu_index].processor)
4096 #ifndef HAVE_AS_POWER9
4097 case PROCESSOR_POWER9:
4098 unavailable_cpu = "power9";
4101 #ifndef HAVE_AS_POWER8
4102 case PROCESSOR_POWER8:
4103 unavailable_cpu = "power8";
4106 #ifndef HAVE_AS_POPCNTD
4107 case PROCESSOR_POWER7:
4108 unavailable_cpu = "power7";
4112 case PROCESSOR_POWER6:
4113 unavailable_cpu = "power6";
4116 #ifndef HAVE_AS_POPCNTB
4117 case PROCESSOR_POWER5:
4118 unavailable_cpu = "power5";
4124 if (unavailable_cpu)
4127 warning (0, "will not generate %qs instructions because "
4128 "assembler lacks %qs support", unavailable_cpu,
4133 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4134 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4135 with those from the cpu, except for options that were explicitly set. If
4136 we don't have a cpu, do not override the target bits set in
4140 rs6000_cpu_index = cpu_index;
4141 rs6000_isa_flags &= ~set_masks;
4142 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4147 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4148 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4149 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4150 to using rs6000_isa_flags, we need to do the initialization here.
4152 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4153 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4154 HOST_WIDE_INT flags;
4156 flags = TARGET_DEFAULT;
4159 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4160 const char *default_cpu = (!TARGET_POWERPC64
4165 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4166 flags = processor_target_table[default_cpu_index].target_enable;
4168 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4171 if (rs6000_tune_index >= 0)
4172 tune_index = rs6000_tune_index;
4173 else if (cpu_index >= 0)
4174 rs6000_tune_index = tune_index = cpu_index;
4178 enum processor_type tune_proc
4179 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4182 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4183 if (processor_target_table[i].processor == tune_proc)
4191 rs6000_cpu = processor_target_table[cpu_index].processor;
4193 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4195 gcc_assert (tune_index >= 0);
4196 rs6000_tune = processor_target_table[tune_index].processor;
4198 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4199 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4200 || rs6000_cpu == PROCESSOR_PPCE5500)
4203 error ("AltiVec not supported in this target");
4206 /* If we are optimizing big endian systems for space, use the load/store
4207 multiple instructions. */
4208 if (BYTES_BIG_ENDIAN && optimize_size)
4209 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
4211 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
4212 because the hardware doesn't support the instructions used in little
4213 endian mode, and causes an alignment trap. The 750 does not cause an
4214 alignment trap (except when the target is unaligned). */
4216 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
4218 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4219 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4220 warning (0, "%qs is not supported on little endian systems",
4224 /* If little-endian, default to -mstrict-align on older processors.
4225 Testing for htm matches power8 and later. */
4226 if (!BYTES_BIG_ENDIAN
4227 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4228 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4230 /* -maltivec={le,be} implies -maltivec. */
4231 if (rs6000_altivec_element_order != 0)
4232 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
4234 /* Disallow -maltivec=le in big endian mode for now. This is not
4235 known to be useful for anyone. */
4236 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
4238 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4239 rs6000_altivec_element_order = 0;
4242 if (!rs6000_fold_gimple)
4244 "gimple folding of rs6000 builtins has been disabled.\n");
4246 /* Add some warnings for VSX. */
4249 const char *msg = NULL;
4250 if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
4252 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4253 msg = N_("-mvsx requires hardware floating point");
4256 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4257 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4260 else if (TARGET_PAIRED_FLOAT)
4261 msg = N_("-mvsx and -mpaired are incompatible");
4262 else if (TARGET_AVOID_XFORM > 0)
4263 msg = N_("-mvsx needs indexed addressing");
4264 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4265 & OPTION_MASK_ALTIVEC))
4267 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4268 msg = N_("-mvsx and -mno-altivec are incompatible");
4270 msg = N_("-mno-altivec disables vsx");
4276 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4277 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4281 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4282 the -mcpu setting to enable options that conflict. */
4283 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4284 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4285 | OPTION_MASK_ALTIVEC
4286 | OPTION_MASK_VSX)) != 0)
4287 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4288 | OPTION_MASK_DIRECT_MOVE)
4289 & ~rs6000_isa_flags_explicit);
4291 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4292 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4294 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4295 off all of the options that depend on those flags. */
4296 ignore_masks = rs6000_disable_incompatible_switches ();
4298 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4299 unless the user explicitly used the -mno-<option> to disable the code. */
4300 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4301 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4302 else if (TARGET_P9_MINMAX)
4306 if (cpu_index == PROCESSOR_POWER9)
4308 /* legacy behavior: allow -mcpu=power9 with certain
4309 capabilities explicitly disabled. */
4310 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4313 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4314 "for <xxx> less than power9", "-mcpu");
4316 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4317 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4318 & rs6000_isa_flags_explicit))
4319 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4320 were explicitly cleared. */
4321 error ("%qs incompatible with explicitly disabled options",
4324 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4326 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4327 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4328 else if (TARGET_VSX)
4329 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4330 else if (TARGET_POPCNTD)
4331 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4332 else if (TARGET_DFP)
4333 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4334 else if (TARGET_CMPB)
4335 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4336 else if (TARGET_FPRND)
4337 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4338 else if (TARGET_POPCNTB)
4339 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4340 else if (TARGET_ALTIVEC)
4341 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4343 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4345 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4346 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4347 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4350 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4352 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4353 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4354 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4357 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4359 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4360 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4361 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4364 if (TARGET_P8_VECTOR && !TARGET_VSX)
4366 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4367 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4368 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4369 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4371 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4372 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4373 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4377 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4379 rs6000_isa_flags |= OPTION_MASK_VSX;
4380 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4384 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4386 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4387 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4388 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4391 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4392 silently turn off quad memory mode. */
4393 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4395 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4396 warning (0, N_("-mquad-memory requires 64-bit mode"));
4398 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4399 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4401 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4402 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4405 /* Non-atomic quad memory load/store are disabled for little endian, since
4406 the words are reversed, but atomic operations can still be done by
4407 swapping the words. */
4408 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4410 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4411 warning (0, N_("-mquad-memory is not available in little endian "
4414 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4417 /* Assume if the user asked for normal quad memory instructions, they want
4418 the atomic versions as well, unless they explicity told us not to use quad
4419 word atomic instructions. */
4420 if (TARGET_QUAD_MEMORY
4421 && !TARGET_QUAD_MEMORY_ATOMIC
4422 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4423 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4425 /* If we can shrink-wrap the TOC register save separately, then use
4426 -msave-toc-indirect unless explicitly disabled. */
4427 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4428 && flag_shrink_wrap_separate
4429 && optimize_function_for_speed_p (cfun))
4430 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4432 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4433 generating power8 instructions. */
4434 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4435 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4436 & OPTION_MASK_P8_FUSION);
4438 /* Setting additional fusion flags turns on base fusion. */
4439 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4441 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4443 if (TARGET_P8_FUSION_SIGN)
4444 error ("%qs requires %qs", "-mpower8-fusion-sign",
4447 if (TARGET_TOC_FUSION)
4448 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4450 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4453 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4456 /* Power9 fusion is a superset over power8 fusion. */
4457 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4459 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4461 /* We prefer to not mention undocumented options in
4462 error messages. However, if users have managed to select
4463 power9-fusion without selecting power8-fusion, they
4464 already know about undocumented flags. */
4465 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4466 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4469 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4472 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4473 generating power9 instructions. */
4474 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4475 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4476 & OPTION_MASK_P9_FUSION);
4478 /* Power8 does not fuse sign extended loads with the addis. If we are
4479 optimizing at high levels for speed, convert a sign extended load into a
4480 zero extending load, and an explicit sign extension. */
4481 if (TARGET_P8_FUSION
4482 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4483 && optimize_function_for_speed_p (cfun)
4485 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4487 /* TOC fusion requires 64-bit and medium/large code model. */
4488 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4490 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4491 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4492 warning (0, N_("-mtoc-fusion requires 64-bit"));
4495 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4497 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4498 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4499 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4502 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4504 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4505 && (TARGET_CMODEL != CMODEL_SMALL)
4506 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4507 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4509 /* ISA 3.0 vector instructions include ISA 2.07. */
4510 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4512 /* We prefer to not mention undocumented options in
4513 error messages. However, if users have managed to select
4514 power9-vector without selecting power8-vector, they
4515 already know about undocumented flags. */
4516 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4517 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4518 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4519 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4521 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4522 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4523 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4527 /* OPTION_MASK_P9_VECTOR is explicit and
4528 OPTION_MASK_P8_VECTOR is not explicit. */
4529 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4530 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4534 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4535 support. If we only have ISA 2.06 support, and the user did not specify
4536 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4537 but we don't enable the full vectorization support */
4538 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4539 TARGET_ALLOW_MOVMISALIGN = 1;
4541 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4543 if (TARGET_ALLOW_MOVMISALIGN > 0
4544 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4545 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4547 TARGET_ALLOW_MOVMISALIGN = 0;
4550 /* Determine when unaligned vector accesses are permitted, and when
4551 they are preferred over masked Altivec loads. Note that if
4552 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4553 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4555 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4559 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4560 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4562 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4565 else if (!TARGET_ALLOW_MOVMISALIGN)
4567 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4568 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4569 "-mallow-movmisalign");
4571 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4575 /* Set long double size before the IEEE 128-bit tests. */
4576 if (!global_options_set.x_rs6000_long_double_type_size)
4578 if (main_target_opt != NULL
4579 && (main_target_opt->x_rs6000_long_double_type_size
4580 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4581 error ("target attribute or pragma changes long double size");
4583 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4586 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4587 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4588 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4589 those systems will not pick up this default. Warn if the user changes the
4590 default unless -Wno-psabi. */
4591 if (!global_options_set.x_rs6000_ieeequad)
4592 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4594 else if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4596 static bool warned_change_long_double;
4597 if (!warned_change_long_double)
4599 warned_change_long_double = true;
4600 if (TARGET_IEEEQUAD)
4601 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4603 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4607 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4608 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4609 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4610 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4611 the keyword as well as the type. */
4612 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4614 /* IEEE 128-bit floating point requires VSX support. */
4615 if (TARGET_FLOAT128_KEYWORD)
4619 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4620 error ("%qs requires VSX support", "-mfloat128");
4622 TARGET_FLOAT128_TYPE = 0;
4623 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4624 | OPTION_MASK_FLOAT128_HW);
4626 else if (!TARGET_FLOAT128_TYPE)
4628 TARGET_FLOAT128_TYPE = 1;
4629 warning (0, "The -mfloat128 option may not be fully supported");
4633 /* Enable the __float128 keyword under Linux by default. */
4634 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4635 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4636 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4638 /* If we have are supporting the float128 type and full ISA 3.0 support,
4639 enable -mfloat128-hardware by default. However, don't enable the
4640 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4641 because sometimes the compiler wants to put things in an integer
4642 container, and if we don't have __int128 support, it is impossible. */
4643 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4644 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4645 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4646 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4648 if (TARGET_FLOAT128_HW
4649 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4651 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4652 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4654 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4657 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4659 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4660 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4662 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4665 /* Print the options after updating the defaults. */
4666 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4667 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4669 /* E500mc does "better" if we inline more aggressively. Respect the
4670 user's opinion, though. */
4671 if (rs6000_block_move_inline_limit == 0
4672 && (rs6000_tune == PROCESSOR_PPCE500MC
4673 || rs6000_tune == PROCESSOR_PPCE500MC64
4674 || rs6000_tune == PROCESSOR_PPCE5500
4675 || rs6000_tune == PROCESSOR_PPCE6500))
4676 rs6000_block_move_inline_limit = 128;
4678 /* store_one_arg depends on expand_block_move to handle at least the
4679 size of reg_parm_stack_space. */
4680 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4681 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4685 /* If the appropriate debug option is enabled, replace the target hooks
4686 with debug versions that call the real version and then prints
4687 debugging information. */
4688 if (TARGET_DEBUG_COST)
4690 targetm.rtx_costs = rs6000_debug_rtx_costs;
4691 targetm.address_cost = rs6000_debug_address_cost;
4692 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4695 if (TARGET_DEBUG_ADDR)
4697 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4698 targetm.legitimize_address = rs6000_debug_legitimize_address;
4699 rs6000_secondary_reload_class_ptr
4700 = rs6000_debug_secondary_reload_class;
4701 targetm.secondary_memory_needed
4702 = rs6000_debug_secondary_memory_needed;
4703 targetm.can_change_mode_class
4704 = rs6000_debug_can_change_mode_class;
4705 rs6000_preferred_reload_class_ptr
4706 = rs6000_debug_preferred_reload_class;
4707 rs6000_legitimize_reload_address_ptr
4708 = rs6000_debug_legitimize_reload_address;
4709 rs6000_mode_dependent_address_ptr
4710 = rs6000_debug_mode_dependent_address;
4713 if (rs6000_veclibabi_name)
4715 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4716 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4719 error ("unknown vectorization library ABI type (%qs) for "
4720 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4726 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4727 target attribute or pragma which automatically enables both options,
4728 unless the altivec ABI was set. This is set by default for 64-bit, but
4730 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4732 TARGET_FLOAT128_TYPE = 0;
4733 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4734 | OPTION_MASK_FLOAT128_KEYWORD)
4735 & ~rs6000_isa_flags_explicit);
4738 /* Enable Altivec ABI for AIX -maltivec. */
4739 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4741 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4742 error ("target attribute or pragma changes AltiVec ABI");
4744 rs6000_altivec_abi = 1;
4747 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4748 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4749 be explicitly overridden in either case. */
4752 if (!global_options_set.x_rs6000_altivec_abi
4753 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4755 if (main_target_opt != NULL &&
4756 !main_target_opt->x_rs6000_altivec_abi)
4757 error ("target attribute or pragma changes AltiVec ABI");
4759 rs6000_altivec_abi = 1;
4763 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4764 So far, the only darwin64 targets are also MACH-O. */
4766 && DEFAULT_ABI == ABI_DARWIN
4769 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4770 error ("target attribute or pragma changes darwin64 ABI");
4773 rs6000_darwin64_abi = 1;
4774 /* Default to natural alignment, for better performance. */
4775 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4779 /* Place FP constants in the constant pool instead of TOC
4780 if section anchors enabled. */
4781 if (flag_section_anchors
4782 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4783 TARGET_NO_FP_IN_TOC = 1;
4785 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4786 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4788 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4789 SUBTARGET_OVERRIDE_OPTIONS;
4791 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4792 SUBSUBTARGET_OVERRIDE_OPTIONS;
4794 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4795 SUB3TARGET_OVERRIDE_OPTIONS;
4798 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4799 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4801 /* For the E500 family of cores, reset the single/double FP flags to let us
4802 check that they remain constant across attributes or pragmas. */
4806 case PROCESSOR_PPC8540:
4807 case PROCESSOR_PPC8548:
4808 case PROCESSOR_PPCE500MC:
4809 case PROCESSOR_PPCE500MC64:
4810 case PROCESSOR_PPCE5500:
4811 case PROCESSOR_PPCE6500:
4812 rs6000_single_float = 0;
4813 rs6000_double_float = 0;
4820 if (main_target_opt)
4822 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
4823 error ("target attribute or pragma changes single precision floating "
4825 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
4826 error ("target attribute or pragma changes double precision floating "
4830 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4831 && rs6000_tune != PROCESSOR_POWER5
4832 && rs6000_tune != PROCESSOR_POWER6
4833 && rs6000_tune != PROCESSOR_POWER7
4834 && rs6000_tune != PROCESSOR_POWER8
4835 && rs6000_tune != PROCESSOR_POWER9
4836 && rs6000_tune != PROCESSOR_PPCA2
4837 && rs6000_tune != PROCESSOR_CELL
4838 && rs6000_tune != PROCESSOR_PPC476);
4839 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4840 || rs6000_tune == PROCESSOR_POWER5
4841 || rs6000_tune == PROCESSOR_POWER7
4842 || rs6000_tune == PROCESSOR_POWER8);
4843 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4844 || rs6000_tune == PROCESSOR_POWER5
4845 || rs6000_tune == PROCESSOR_POWER6
4846 || rs6000_tune == PROCESSOR_POWER7
4847 || rs6000_tune == PROCESSOR_POWER8
4848 || rs6000_tune == PROCESSOR_POWER9
4849 || rs6000_tune == PROCESSOR_PPCE500MC
4850 || rs6000_tune == PROCESSOR_PPCE500MC64
4851 || rs6000_tune == PROCESSOR_PPCE5500
4852 || rs6000_tune == PROCESSOR_PPCE6500);
4854 /* Allow debug switches to override the above settings. These are set to -1
4855 in rs6000.opt to indicate the user hasn't directly set the switch. */
4856 if (TARGET_ALWAYS_HINT >= 0)
4857 rs6000_always_hint = TARGET_ALWAYS_HINT;
4859 if (TARGET_SCHED_GROUPS >= 0)
4860 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4862 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4863 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4865 rs6000_sched_restricted_insns_priority
4866 = (rs6000_sched_groups ? 1 : 0);
4868 /* Handle -msched-costly-dep option. */
4869 rs6000_sched_costly_dep
4870 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4872 if (rs6000_sched_costly_dep_str)
4874 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4875 rs6000_sched_costly_dep = no_dep_costly;
4876 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4877 rs6000_sched_costly_dep = all_deps_costly;
4878 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4879 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4880 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4881 rs6000_sched_costly_dep = store_to_load_dep_costly;
4883 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4884 atoi (rs6000_sched_costly_dep_str));
4887 /* Handle -minsert-sched-nops option. */
4888 rs6000_sched_insert_nops
4889 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4891 if (rs6000_sched_insert_nops_str)
4893 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4894 rs6000_sched_insert_nops = sched_finish_none;
4895 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4896 rs6000_sched_insert_nops = sched_finish_pad_groups;
4897 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4898 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4900 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4901 atoi (rs6000_sched_insert_nops_str));
4904 /* Handle stack protector */
4905 if (!global_options_set.x_rs6000_stack_protector_guard)
4906 #ifdef TARGET_THREAD_SSP_OFFSET
4907 rs6000_stack_protector_guard = SSP_TLS;
4909 rs6000_stack_protector_guard = SSP_GLOBAL;
4912 #ifdef TARGET_THREAD_SSP_OFFSET
4913 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4914 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4917 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4920 const char *str = rs6000_stack_protector_guard_offset_str;
4923 long offset = strtol (str, &endp, 0);
4924 if (!*str || *endp || errno)
4925 error ("%qs is not a valid number in %qs", str,
4926 "-mstack-protector-guard-offset=");
4928 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4929 || (TARGET_64BIT && (offset & 3)))
4930 error ("%qs is not a valid offset in %qs", str,
4931 "-mstack-protector-guard-offset=");
4933 rs6000_stack_protector_guard_offset = offset;
4936 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4938 const char *str = rs6000_stack_protector_guard_reg_str;
4939 int reg = decode_reg_name (str);
4941 if (!IN_RANGE (reg, 1, 31))
4942 error ("%qs is not a valid base register in %qs", str,
4943 "-mstack-protector-guard-reg=");
4945 rs6000_stack_protector_guard_reg = reg;
4948 if (rs6000_stack_protector_guard == SSP_TLS
4949 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4950 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4954 #ifdef TARGET_REGNAMES
4955 /* If the user desires alternate register names, copy in the
4956 alternate names now. */
4957 if (TARGET_REGNAMES)
4958 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4961 /* Set aix_struct_return last, after the ABI is determined.
4962 If -maix-struct-return or -msvr4-struct-return was explicitly
4963 used, don't override with the ABI default. */
4964 if (!global_options_set.x_aix_struct_return)
4965 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4968 /* IBM XL compiler defaults to unsigned bitfields. */
4969 if (TARGET_XL_COMPAT)
4970 flag_signed_bitfields = 0;
4973 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4974 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4976 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4978 /* We can only guarantee the availability of DI pseudo-ops when
4979 assembling for 64-bit targets. */
4982 targetm.asm_out.aligned_op.di = NULL;
4983 targetm.asm_out.unaligned_op.di = NULL;
4987 /* Set branch target alignment, if not optimizing for size. */
4990 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4991 aligned 8byte to avoid misprediction by the branch predictor. */
4992 if (rs6000_tune == PROCESSOR_TITAN
4993 || rs6000_tune == PROCESSOR_CELL)
4995 if (align_functions <= 0)
4996 align_functions = 8;
4997 if (align_jumps <= 0)
4999 if (align_loops <= 0)
5002 if (rs6000_align_branch_targets)
5004 if (align_functions <= 0)
5005 align_functions = 16;
5006 if (align_jumps <= 0)
5008 if (align_loops <= 0)
5010 can_override_loop_align = 1;
5014 if (align_jumps_max_skip <= 0)
5015 align_jumps_max_skip = 15;
5016 if (align_loops_max_skip <= 0)
5017 align_loops_max_skip = 15;
5020 /* Arrange to save and restore machine status around nested functions. */
5021 init_machine_status = rs6000_init_machine_status;
5023 /* We should always be splitting complex arguments, but we can't break
5024 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5025 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
5026 targetm.calls.split_complex_arg = NULL;
5028 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5029 if (DEFAULT_ABI == ABI_AIX)
5030 targetm.calls.custom_function_descriptors = 0;
5033 /* Initialize rs6000_cost with the appropriate target costs. */
5035 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
5037 switch (rs6000_tune)
5039 case PROCESSOR_RS64A:
5040 rs6000_cost = &rs64a_cost;
5043 case PROCESSOR_MPCCORE:
5044 rs6000_cost = &mpccore_cost;
5047 case PROCESSOR_PPC403:
5048 rs6000_cost = &ppc403_cost;
5051 case PROCESSOR_PPC405:
5052 rs6000_cost = &ppc405_cost;
5055 case PROCESSOR_PPC440:
5056 rs6000_cost = &ppc440_cost;
5059 case PROCESSOR_PPC476:
5060 rs6000_cost = &ppc476_cost;
5063 case PROCESSOR_PPC601:
5064 rs6000_cost = &ppc601_cost;
5067 case PROCESSOR_PPC603:
5068 rs6000_cost = &ppc603_cost;
5071 case PROCESSOR_PPC604:
5072 rs6000_cost = &ppc604_cost;
5075 case PROCESSOR_PPC604e:
5076 rs6000_cost = &ppc604e_cost;
5079 case PROCESSOR_PPC620:
5080 rs6000_cost = &ppc620_cost;
5083 case PROCESSOR_PPC630:
5084 rs6000_cost = &ppc630_cost;
5087 case PROCESSOR_CELL:
5088 rs6000_cost = &ppccell_cost;
5091 case PROCESSOR_PPC750:
5092 case PROCESSOR_PPC7400:
5093 rs6000_cost = &ppc750_cost;
5096 case PROCESSOR_PPC7450:
5097 rs6000_cost = &ppc7450_cost;
5100 case PROCESSOR_PPC8540:
5101 case PROCESSOR_PPC8548:
5102 rs6000_cost = &ppc8540_cost;
5105 case PROCESSOR_PPCE300C2:
5106 case PROCESSOR_PPCE300C3:
5107 rs6000_cost = &ppce300c2c3_cost;
5110 case PROCESSOR_PPCE500MC:
5111 rs6000_cost = &ppce500mc_cost;
5114 case PROCESSOR_PPCE500MC64:
5115 rs6000_cost = &ppce500mc64_cost;
5118 case PROCESSOR_PPCE5500:
5119 rs6000_cost = &ppce5500_cost;
5122 case PROCESSOR_PPCE6500:
5123 rs6000_cost = &ppce6500_cost;
5126 case PROCESSOR_TITAN:
5127 rs6000_cost = &titan_cost;
5130 case PROCESSOR_POWER4:
5131 case PROCESSOR_POWER5:
5132 rs6000_cost = &power4_cost;
5135 case PROCESSOR_POWER6:
5136 rs6000_cost = &power6_cost;
5139 case PROCESSOR_POWER7:
5140 rs6000_cost = &power7_cost;
5143 case PROCESSOR_POWER8:
5144 rs6000_cost = &power8_cost;
5147 case PROCESSOR_POWER9:
5148 rs6000_cost = &power9_cost;
5151 case PROCESSOR_PPCA2:
5152 rs6000_cost = &ppca2_cost;
5161 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5162 rs6000_cost->simultaneous_prefetches,
5163 global_options.x_param_values,
5164 global_options_set.x_param_values);
5165 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5166 global_options.x_param_values,
5167 global_options_set.x_param_values);
5168 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5169 rs6000_cost->cache_line_size,
5170 global_options.x_param_values,
5171 global_options_set.x_param_values);
5172 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5173 global_options.x_param_values,
5174 global_options_set.x_param_values);
5176 /* Increase loop peeling limits based on performance analysis. */
5177 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5178 global_options.x_param_values,
5179 global_options_set.x_param_values);
5180 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5181 global_options.x_param_values,
5182 global_options_set.x_param_values);
5184 /* Use the 'model' -fsched-pressure algorithm by default. */
5185 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5186 SCHED_PRESSURE_MODEL,
5187 global_options.x_param_values,
5188 global_options_set.x_param_values);
5190 /* If using typedef char *va_list, signal that
5191 __builtin_va_start (&ap, 0) can be optimized to
5192 ap = __builtin_next_arg (0). */
5193 if (DEFAULT_ABI != ABI_V4)
5194 targetm.expand_builtin_va_start = NULL;
5197 /* Set up single/double float flags.
5198 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5199 then set both flags. */
5200 if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
5201 rs6000_single_float = rs6000_double_float = 1;
5203 /* If not explicitly specified via option, decide whether to generate indexed
5204 load/store instructions. A value of -1 indicates that the
5205 initial value of this variable has not been overwritten. During
5206 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5207 if (TARGET_AVOID_XFORM == -1)
5208 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5209 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5210 need indexed accesses and the type used is the scalar type of the element
5211 being loaded or stored. */
5212 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5213 && !TARGET_ALTIVEC);
5215 /* Set the -mrecip options. */
5216 if (rs6000_recip_name)
5218 char *p = ASTRDUP (rs6000_recip_name);
5220 unsigned int mask, i;
5223 while ((q = strtok (p, ",")) != NULL)
5234 if (!strcmp (q, "default"))
5235 mask = ((TARGET_RECIP_PRECISION)
5236 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5239 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5240 if (!strcmp (q, recip_options[i].string))
5242 mask = recip_options[i].mask;
5246 if (i == ARRAY_SIZE (recip_options))
5248 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5256 rs6000_recip_control &= ~mask;
5258 rs6000_recip_control |= mask;
5262 /* Set the builtin mask of the various options used that could affect which
5263 builtins were used. In the past we used target_flags, but we've run out
5264 of bits, and some options like PAIRED are no longer in target_flags. */
5265 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5266 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5267 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5268 rs6000_builtin_mask);
5270 /* Initialize all of the registers. */
5271 rs6000_init_hard_regno_mode_ok (global_init_p);
5273 /* Save the initial options in case the user does function specific options */
5275 target_option_default_node = target_option_current_node
5276 = build_target_option_node (&global_options);
5278 /* If not explicitly specified via option, decide whether to generate the
5279 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5280 if (TARGET_LINK_STACK == -1)
5281 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5286 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5287 define the target cpu type. */
5290 rs6000_option_override (void)
5292 (void) rs6000_option_override_internal (true);
5296 /* Implement targetm.vectorize.builtin_mask_for_load. */
5298 rs6000_builtin_mask_for_load (void)
5300 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5301 if ((TARGET_ALTIVEC && !TARGET_VSX)
5302 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5303 return altivec_builtin_mask_for_load;
5308 /* Implement LOOP_ALIGN. */
5310 rs6000_loop_align (rtx label)
5315 /* Don't override loop alignment if -falign-loops was specified. */
5316 if (!can_override_loop_align)
5317 return align_loops_log;
5319 bb = BLOCK_FOR_INSN (label);
5320 ninsns = num_loop_insns(bb->loop_father);
5322 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5323 if (ninsns > 4 && ninsns <= 8
5324 && (rs6000_tune == PROCESSOR_POWER4
5325 || rs6000_tune == PROCESSOR_POWER5
5326 || rs6000_tune == PROCESSOR_POWER6
5327 || rs6000_tune == PROCESSOR_POWER7
5328 || rs6000_tune == PROCESSOR_POWER8
5329 || rs6000_tune == PROCESSOR_POWER9))
5332 return align_loops_log;
5335 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5337 rs6000_loop_align_max_skip (rtx_insn *label)
5339 return (1 << rs6000_loop_align (label)) - 1;
5342 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5343 after applying N number of iterations. This routine does not determine
5344 how may iterations are required to reach desired alignment. */
5347 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5354 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5357 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5367 /* Assuming that all other types are naturally aligned. CHECKME! */
5372 /* Return true if the vector misalignment factor is supported by the
5375 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5382 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5385 /* Return if movmisalign pattern is not supported for this mode. */
5386 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5389 if (misalignment == -1)
5391 /* Misalignment factor is unknown at compile time but we know
5392 it's word aligned. */
5393 if (rs6000_vector_alignment_reachable (type, is_packed))
5395 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5397 if (element_size == 64 || element_size == 32)
5404 /* VSX supports word-aligned vector. */
5405 if (misalignment % 4 == 0)
5411 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5413 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5414 tree vectype, int misalign)
5419 switch (type_of_cost)
5429 case cond_branch_not_taken:
5438 case vec_promote_demote:
5444 case cond_branch_taken:
5447 case unaligned_load:
5448 case vector_gather_load:
5449 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5452 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5454 elements = TYPE_VECTOR_SUBPARTS (vectype);
5456 /* Double word aligned. */
5464 /* Double word aligned. */
5468 /* Unknown misalignment. */
5481 /* Misaligned loads are not supported. */
5486 case unaligned_store:
5487 case vector_scatter_store:
5488 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5491 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5493 elements = TYPE_VECTOR_SUBPARTS (vectype);
5495 /* Double word aligned. */
5503 /* Double word aligned. */
5507 /* Unknown misalignment. */
5520 /* Misaligned stores are not supported. */
5526 /* This is a rough approximation assuming non-constant elements
5527 constructed into a vector via element insertion. FIXME:
5528 vec_construct is not granular enough for uniformly good
5529 decisions. If the initialization is a splat, this is
5530 cheaper than we estimate. Improve this someday. */
5531 elem_type = TREE_TYPE (vectype);
5532 /* 32-bit vectors loaded into registers are stored as double
5533 precision, so we need 2 permutes, 2 converts, and 1 merge
5534 to construct a vector of short floats from them. */
5535 if (SCALAR_FLOAT_TYPE_P (elem_type)
5536 && TYPE_PRECISION (elem_type) == 32)
5538 /* On POWER9, integer vector types are built up in GPRs and then
5539 use a direct move (2 cycles). For POWER8 this is even worse,
5540 as we need two direct moves and a merge, and the direct moves
5542 else if (INTEGRAL_TYPE_P (elem_type))
5544 if (TARGET_P9_VECTOR)
5545 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5547 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5550 /* V2DFmode doesn't need a direct move. */
5558 /* Implement targetm.vectorize.preferred_simd_mode. */
5561 rs6000_preferred_simd_mode (scalar_mode mode)
5570 if (TARGET_ALTIVEC || TARGET_VSX)
5587 if (TARGET_PAIRED_FLOAT
5593 typedef struct _rs6000_cost_data
5595 struct loop *loop_info;
5599 /* Test for likely overcommitment of vector hardware resources. If a
5600 loop iteration is relatively large, and too large a percentage of
5601 instructions in the loop are vectorized, the cost model may not
5602 adequately reflect delays from unavailable vector resources.
5603 Penalize the loop body cost for this case. */
5606 rs6000_density_test (rs6000_cost_data *data)
5608 const int DENSITY_PCT_THRESHOLD = 85;
5609 const int DENSITY_SIZE_THRESHOLD = 70;
5610 const int DENSITY_PENALTY = 10;
5611 struct loop *loop = data->loop_info;
5612 basic_block *bbs = get_loop_body (loop);
5613 int nbbs = loop->num_nodes;
5614 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5617 for (i = 0; i < nbbs; i++)
5619 basic_block bb = bbs[i];
5620 gimple_stmt_iterator gsi;
5622 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5624 gimple *stmt = gsi_stmt (gsi);
5625 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5627 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5628 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5634 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5636 if (density_pct > DENSITY_PCT_THRESHOLD
5637 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5639 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5640 if (dump_enabled_p ())
5641 dump_printf_loc (MSG_NOTE, vect_location,
5642 "density %d%%, cost %d exceeds threshold, penalizing "
5643 "loop body cost by %d%%", density_pct,
5644 vec_cost + not_vec_cost, DENSITY_PENALTY);
5648 /* Implement targetm.vectorize.init_cost. */
5650 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5651 instruction is needed by the vectorization. */
5652 static bool rs6000_vect_nonmem;
5655 rs6000_init_cost (struct loop *loop_info)
5657 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5658 data->loop_info = loop_info;
5659 data->cost[vect_prologue] = 0;
5660 data->cost[vect_body] = 0;
5661 data->cost[vect_epilogue] = 0;
5662 rs6000_vect_nonmem = false;
5666 /* Implement targetm.vectorize.add_stmt_cost. */
5669 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5670 struct _stmt_vec_info *stmt_info, int misalign,
5671 enum vect_cost_model_location where)
5673 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5674 unsigned retval = 0;
5676 if (flag_vect_cost_model)
5678 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5679 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5681 /* Statements in an inner loop relative to the loop being
5682 vectorized are weighted more heavily. The value here is
5683 arbitrary and could potentially be improved with analysis. */
5684 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5685 count *= 50; /* FIXME. */
5687 retval = (unsigned) (count * stmt_cost);
5688 cost_data->cost[where] += retval;
5690 /* Check whether we're doing something other than just a copy loop.
5691 Not all such loops may be profitably vectorized; see
5692 rs6000_finish_cost. */
5693 if ((kind == vec_to_scalar || kind == vec_perm
5694 || kind == vec_promote_demote || kind == vec_construct
5695 || kind == scalar_to_vec)
5696 || (where == vect_body && kind == vector_stmt))
5697 rs6000_vect_nonmem = true;
5703 /* Implement targetm.vectorize.finish_cost. */
5706 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5707 unsigned *body_cost, unsigned *epilogue_cost)
5709 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5711 if (cost_data->loop_info)
5712 rs6000_density_test (cost_data);
5714 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5715 that require versioning for any reason. The vectorization is at
5716 best a wash inside the loop, and the versioning checks make
5717 profitability highly unlikely and potentially quite harmful. */
5718 if (cost_data->loop_info)
5720 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5721 if (!rs6000_vect_nonmem
5722 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5723 && LOOP_REQUIRES_VERSIONING (vec_info))
5724 cost_data->cost[vect_body] += 10000;
5727 *prologue_cost = cost_data->cost[vect_prologue];
5728 *body_cost = cost_data->cost[vect_body];
5729 *epilogue_cost = cost_data->cost[vect_epilogue];
5732 /* Implement targetm.vectorize.destroy_cost_data. */
5735 rs6000_destroy_cost_data (void *data)
5740 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5741 library with vectorized intrinsics. */
5744 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5748 const char *suffix = NULL;
5749 tree fntype, new_fndecl, bdecl = NULL_TREE;
5752 machine_mode el_mode, in_mode;
5755 /* Libmass is suitable for unsafe math only as it does not correctly support
5756 parts of IEEE with the required precision such as denormals. Only support
5757 it if we have VSX to use the simd d2 or f4 functions.
5758 XXX: Add variable length support. */
5759 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5762 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5763 n = TYPE_VECTOR_SUBPARTS (type_out);
5764 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5765 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5766 if (el_mode != in_mode
5802 if (el_mode == DFmode && n == 2)
5804 bdecl = mathfn_built_in (double_type_node, fn);
5805 suffix = "d2"; /* pow -> powd2 */
5807 else if (el_mode == SFmode && n == 4)
5809 bdecl = mathfn_built_in (float_type_node, fn);
5810 suffix = "4"; /* powf -> powf4 */
5822 gcc_assert (suffix != NULL);
5823 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5827 strcpy (name, bname + sizeof ("__builtin_") - 1);
5828 strcat (name, suffix);
5831 fntype = build_function_type_list (type_out, type_in, NULL);
5832 else if (n_args == 2)
5833 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5837 /* Build a function declaration for the vectorized function. */
5838 new_fndecl = build_decl (BUILTINS_LOCATION,
5839 FUNCTION_DECL, get_identifier (name), fntype);
5840 TREE_PUBLIC (new_fndecl) = 1;
5841 DECL_EXTERNAL (new_fndecl) = 1;
5842 DECL_IS_NOVOPS (new_fndecl) = 1;
5843 TREE_READONLY (new_fndecl) = 1;
5848 /* Returns a function decl for a vectorized version of the builtin function
5849 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5850 if it is not available. */
5853 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5856 machine_mode in_mode, out_mode;
5859 if (TARGET_DEBUG_BUILTIN)
5860 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5861 combined_fn_name (combined_fn (fn)),
5862 GET_MODE_NAME (TYPE_MODE (type_out)),
5863 GET_MODE_NAME (TYPE_MODE (type_in)));
5865 if (TREE_CODE (type_out) != VECTOR_TYPE
5866 || TREE_CODE (type_in) != VECTOR_TYPE)
5869 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5870 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5871 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5872 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5877 if (VECTOR_UNIT_VSX_P (V2DFmode)
5878 && out_mode == DFmode && out_n == 2
5879 && in_mode == DFmode && in_n == 2)
5880 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5881 if (VECTOR_UNIT_VSX_P (V4SFmode)
5882 && out_mode == SFmode && out_n == 4
5883 && in_mode == SFmode && in_n == 4)
5884 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5885 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5886 && out_mode == SFmode && out_n == 4
5887 && in_mode == SFmode && in_n == 4)
5888 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5891 if (VECTOR_UNIT_VSX_P (V2DFmode)
5892 && out_mode == DFmode && out_n == 2
5893 && in_mode == DFmode && in_n == 2)
5894 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5895 if (VECTOR_UNIT_VSX_P (V4SFmode)
5896 && out_mode == SFmode && out_n == 4
5897 && in_mode == SFmode && in_n == 4)
5898 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5899 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5900 && out_mode == SFmode && out_n == 4
5901 && in_mode == SFmode && in_n == 4)
5902 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5905 if (VECTOR_UNIT_VSX_P (V2DFmode)
5906 && out_mode == DFmode && out_n == 2
5907 && in_mode == DFmode && in_n == 2)
5908 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5909 if (VECTOR_UNIT_VSX_P (V4SFmode)
5910 && out_mode == SFmode && out_n == 4
5911 && in_mode == SFmode && in_n == 4)
5912 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5913 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5914 && out_mode == SFmode && out_n == 4
5915 && in_mode == SFmode && in_n == 4)
5916 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5919 if (VECTOR_UNIT_VSX_P (V2DFmode)
5920 && out_mode == DFmode && out_n == 2
5921 && in_mode == DFmode && in_n == 2)
5922 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5923 if (VECTOR_UNIT_VSX_P (V4SFmode)
5924 && out_mode == SFmode && out_n == 4
5925 && in_mode == SFmode && in_n == 4)
5926 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5927 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5928 && out_mode == SFmode && out_n == 4
5929 && in_mode == SFmode && in_n == 4)
5930 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5933 if (VECTOR_UNIT_VSX_P (V2DFmode)
5934 && out_mode == DFmode && out_n == 2
5935 && in_mode == DFmode && in_n == 2)
5936 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5937 if (VECTOR_UNIT_VSX_P (V4SFmode)
5938 && out_mode == SFmode && out_n == 4
5939 && in_mode == SFmode && in_n == 4)
5940 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5941 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5942 && out_mode == SFmode && out_n == 4
5943 && in_mode == SFmode && in_n == 4)
5944 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5947 if (VECTOR_UNIT_VSX_P (V2DFmode)
5948 && flag_unsafe_math_optimizations
5949 && out_mode == DFmode && out_n == 2
5950 && in_mode == DFmode && in_n == 2)
5951 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5952 if (VECTOR_UNIT_VSX_P (V4SFmode)
5953 && flag_unsafe_math_optimizations
5954 && out_mode == SFmode && out_n == 4
5955 && in_mode == SFmode && in_n == 4)
5956 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5959 if (VECTOR_UNIT_VSX_P (V2DFmode)
5960 && !flag_trapping_math
5961 && out_mode == DFmode && out_n == 2
5962 && in_mode == DFmode && in_n == 2)
5963 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5964 if (VECTOR_UNIT_VSX_P (V4SFmode)
5965 && !flag_trapping_math
5966 && out_mode == SFmode && out_n == 4
5967 && in_mode == SFmode && in_n == 4)
5968 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5974 /* Generate calls to libmass if appropriate. */
5975 if (rs6000_veclib_handler)
5976 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5981 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5984 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5987 machine_mode in_mode, out_mode;
5990 if (TARGET_DEBUG_BUILTIN)
5991 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5992 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5993 GET_MODE_NAME (TYPE_MODE (type_out)),
5994 GET_MODE_NAME (TYPE_MODE (type_in)));
5996 if (TREE_CODE (type_out) != VECTOR_TYPE
5997 || TREE_CODE (type_in) != VECTOR_TYPE)
6000 out_mode = TYPE_MODE (TREE_TYPE (type_out));
6001 out_n = TYPE_VECTOR_SUBPARTS (type_out);
6002 in_mode = TYPE_MODE (TREE_TYPE (type_in));
6003 in_n = TYPE_VECTOR_SUBPARTS (type_in);
6005 enum rs6000_builtins fn
6006 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
6009 case RS6000_BUILTIN_RSQRTF:
6010 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6011 && out_mode == SFmode && out_n == 4
6012 && in_mode == SFmode && in_n == 4)
6013 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
6015 case RS6000_BUILTIN_RSQRT:
6016 if (VECTOR_UNIT_VSX_P (V2DFmode)
6017 && out_mode == DFmode && out_n == 2
6018 && in_mode == DFmode && in_n == 2)
6019 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
6021 case RS6000_BUILTIN_RECIPF:
6022 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6023 && out_mode == SFmode && out_n == 4
6024 && in_mode == SFmode && in_n == 4)
6025 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
6027 case RS6000_BUILTIN_RECIP:
6028 if (VECTOR_UNIT_VSX_P (V2DFmode)
6029 && out_mode == DFmode && out_n == 2
6030 && in_mode == DFmode && in_n == 2)
6031 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
6039 /* Default CPU string for rs6000*_file_start functions. */
6040 static const char *rs6000_default_cpu;
6042 /* Do anything needed at the start of the asm file. */
6045 rs6000_file_start (void)
6048 const char *start = buffer;
6049 FILE *file = asm_out_file;
6051 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6053 default_file_start ();
6055 if (flag_verbose_asm)
6057 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6059 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6061 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6065 if (global_options_set.x_rs6000_cpu_index)
6067 fprintf (file, "%s -mcpu=%s", start,
6068 processor_target_table[rs6000_cpu_index].name);
6072 if (global_options_set.x_rs6000_tune_index)
6074 fprintf (file, "%s -mtune=%s", start,
6075 processor_target_table[rs6000_tune_index].name);
6079 if (PPC405_ERRATUM77)
6081 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6085 #ifdef USING_ELFOS_H
6086 switch (rs6000_sdata)
6088 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6089 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6090 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6091 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6094 if (rs6000_sdata && g_switch_value)
6096 fprintf (file, "%s -G %d", start,
6106 #ifdef USING_ELFOS_H
6107 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6108 && !global_options_set.x_rs6000_cpu_index)
6110 fputs ("\t.machine ", asm_out_file);
6111 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6112 fputs ("power9\n", asm_out_file);
6113 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6114 fputs ("power8\n", asm_out_file);
6115 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6116 fputs ("power7\n", asm_out_file);
6117 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6118 fputs ("power6\n", asm_out_file);
6119 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6120 fputs ("power5\n", asm_out_file);
6121 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6122 fputs ("power4\n", asm_out_file);
6123 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6124 fputs ("ppc64\n", asm_out_file);
6126 fputs ("ppc\n", asm_out_file);
6130 if (DEFAULT_ABI == ABI_ELFv2)
6131 fprintf (file, "\t.abiversion 2\n");
6135 /* Return nonzero if this function is known to have a null epilogue. */
6138 direct_return (void)
6140 if (reload_completed)
6142 rs6000_stack_t *info = rs6000_stack_info ();
6144 if (info->first_gp_reg_save == 32
6145 && info->first_fp_reg_save == 64
6146 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6147 && ! info->lr_save_p
6148 && ! info->cr_save_p
6149 && info->vrsave_size == 0
6157 /* Return the number of instructions it takes to form a constant in an
6158 integer register. */
6161 num_insns_constant_wide (HOST_WIDE_INT value)
6163 /* signed constant loadable with addi */
6164 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6167 /* constant loadable with addis */
6168 else if ((value & 0xffff) == 0
6169 && (value >> 31 == -1 || value >> 31 == 0))
6172 else if (TARGET_POWERPC64)
6174 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6175 HOST_WIDE_INT high = value >> 31;
6177 if (high == 0 || high == -1)
6183 return num_insns_constant_wide (high) + 1;
6185 return num_insns_constant_wide (low) + 1;
6187 return (num_insns_constant_wide (high)
6188 + num_insns_constant_wide (low) + 1);
6196 num_insns_constant (rtx op, machine_mode mode)
6198 HOST_WIDE_INT low, high;
6200 switch (GET_CODE (op))
6203 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6204 && rs6000_is_valid_and_mask (op, mode))
6207 return num_insns_constant_wide (INTVAL (op));
6209 case CONST_WIDE_INT:
6212 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6213 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6214 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6219 if (mode == SFmode || mode == SDmode)
6223 if (DECIMAL_FLOAT_MODE_P (mode))
6224 REAL_VALUE_TO_TARGET_DECIMAL32
6225 (*CONST_DOUBLE_REAL_VALUE (op), l);
6227 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6228 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6232 if (DECIMAL_FLOAT_MODE_P (mode))
6233 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6235 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6236 high = l[WORDS_BIG_ENDIAN == 0];
6237 low = l[WORDS_BIG_ENDIAN != 0];
6240 return (num_insns_constant_wide (low)
6241 + num_insns_constant_wide (high));
6244 if ((high == 0 && low >= 0)
6245 || (high == -1 && low < 0))
6246 return num_insns_constant_wide (low);
6248 else if (rs6000_is_valid_and_mask (op, mode))
6252 return num_insns_constant_wide (high) + 1;
6255 return (num_insns_constant_wide (high)
6256 + num_insns_constant_wide (low) + 1);
6264 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6265 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6266 corresponding element of the vector, but for V4SFmode and V2SFmode,
6267 the corresponding "float" is interpreted as an SImode integer. */
6270 const_vector_elt_as_int (rtx op, unsigned int elt)
6274 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6275 gcc_assert (GET_MODE (op) != V2DImode
6276 && GET_MODE (op) != V2DFmode);
6278 tmp = CONST_VECTOR_ELT (op, elt);
6279 if (GET_MODE (op) == V4SFmode
6280 || GET_MODE (op) == V2SFmode)
6281 tmp = gen_lowpart (SImode, tmp);
6282 return INTVAL (tmp);
6285 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6286 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6287 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6288 all items are set to the same value and contain COPIES replicas of the
6289 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6290 operand and the others are set to the value of the operand's msb. */
6293 vspltis_constant (rtx op, unsigned step, unsigned copies)
6295 machine_mode mode = GET_MODE (op);
6296 machine_mode inner = GET_MODE_INNER (mode);
6304 HOST_WIDE_INT splat_val;
6305 HOST_WIDE_INT msb_val;
6307 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6310 nunits = GET_MODE_NUNITS (mode);
6311 bitsize = GET_MODE_BITSIZE (inner);
6312 mask = GET_MODE_MASK (inner);
6314 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6316 msb_val = val >= 0 ? 0 : -1;
6318 /* Construct the value to be splatted, if possible. If not, return 0. */
6319 for (i = 2; i <= copies; i *= 2)
6321 HOST_WIDE_INT small_val;
6323 small_val = splat_val >> bitsize;
6325 if (splat_val != ((HOST_WIDE_INT)
6326 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6327 | (small_val & mask)))
6329 splat_val = small_val;
6332 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6333 if (EASY_VECTOR_15 (splat_val))
6336 /* Also check if we can splat, and then add the result to itself. Do so if
6337 the value is positive, of if the splat instruction is using OP's mode;
6338 for splat_val < 0, the splat and the add should use the same mode. */
6339 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6340 && (splat_val >= 0 || (step == 1 && copies == 1)))
6343 /* Also check if are loading up the most significant bit which can be done by
6344 loading up -1 and shifting the value left by -1. */
6345 else if (EASY_VECTOR_MSB (splat_val, inner))
6351 /* Check if VAL is present in every STEP-th element, and the
6352 other elements are filled with its most significant bit. */
6353 for (i = 1; i < nunits; ++i)
6355 HOST_WIDE_INT desired_val;
6356 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6357 if ((i & (step - 1)) == 0)
6360 desired_val = msb_val;
6362 if (desired_val != const_vector_elt_as_int (op, elt))
6369 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6370 instruction, filling in the bottom elements with 0 or -1.
6372 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6373 for the number of zeroes to shift in, or negative for the number of 0xff
6376 OP is a CONST_VECTOR. */
6379 vspltis_shifted (rtx op)
6381 machine_mode mode = GET_MODE (op);
6382 machine_mode inner = GET_MODE_INNER (mode);
6390 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6393 /* We need to create pseudo registers to do the shift, so don't recognize
6394 shift vector constants after reload. */
6395 if (!can_create_pseudo_p ())
6398 nunits = GET_MODE_NUNITS (mode);
6399 mask = GET_MODE_MASK (inner);
6401 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6403 /* Check if the value can really be the operand of a vspltis[bhw]. */
6404 if (EASY_VECTOR_15 (val))
6407 /* Also check if we are loading up the most significant bit which can be done
6408 by loading up -1 and shifting the value left by -1. */
6409 else if (EASY_VECTOR_MSB (val, inner))
6415 /* Check if VAL is present in every STEP-th element until we find elements
6416 that are 0 or all 1 bits. */
6417 for (i = 1; i < nunits; ++i)
6419 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6420 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6422 /* If the value isn't the splat value, check for the remaining elements
6428 for (j = i+1; j < nunits; ++j)
6430 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6431 if (const_vector_elt_as_int (op, elt2) != 0)
6435 return (nunits - i) * GET_MODE_SIZE (inner);
6438 else if ((elt_val & mask) == mask)
6440 for (j = i+1; j < nunits; ++j)
6442 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6443 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6447 return -((nunits - i) * GET_MODE_SIZE (inner));
6455 /* If all elements are equal, we don't need to do VLSDOI. */
6460 /* Return true if OP is of the given MODE and can be synthesized
6461 with a vspltisb, vspltish or vspltisw. */
6464 easy_altivec_constant (rtx op, machine_mode mode)
6466 unsigned step, copies;
6468 if (mode == VOIDmode)
6469 mode = GET_MODE (op);
6470 else if (mode != GET_MODE (op))
6473 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6475 if (mode == V2DFmode)
6476 return zero_constant (op, mode);
6478 else if (mode == V2DImode)
6480 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6481 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6484 if (zero_constant (op, mode))
6487 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6488 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6494 /* V1TImode is a special container for TImode. Ignore for now. */
6495 else if (mode == V1TImode)
6498 /* Start with a vspltisw. */
6499 step = GET_MODE_NUNITS (mode) / 4;
6502 if (vspltis_constant (op, step, copies))
6505 /* Then try with a vspltish. */
6511 if (vspltis_constant (op, step, copies))
6514 /* And finally a vspltisb. */
6520 if (vspltis_constant (op, step, copies))
6523 if (vspltis_shifted (op) != 0)
6529 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6530 result is OP. Abort if it is not possible. */
6533 gen_easy_altivec_constant (rtx op)
6535 machine_mode mode = GET_MODE (op);
6536 int nunits = GET_MODE_NUNITS (mode);
6537 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6538 unsigned step = nunits / 4;
6539 unsigned copies = 1;
6541 /* Start with a vspltisw. */
6542 if (vspltis_constant (op, step, copies))
6543 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6545 /* Then try with a vspltish. */
6551 if (vspltis_constant (op, step, copies))
6552 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6554 /* And finally a vspltisb. */
6560 if (vspltis_constant (op, step, copies))
6561 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6566 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6567 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6569 Return the number of instructions needed (1 or 2) into the address pointed
6572 Return the constant that is being split via CONSTANT_PTR. */
6575 xxspltib_constant_p (rtx op,
6580 size_t nunits = GET_MODE_NUNITS (mode);
6582 HOST_WIDE_INT value;
6585 /* Set the returned values to out of bound values. */
6586 *num_insns_ptr = -1;
6587 *constant_ptr = 256;
6589 if (!TARGET_P9_VECTOR)
6592 if (mode == VOIDmode)
6593 mode = GET_MODE (op);
6595 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6598 /* Handle (vec_duplicate <constant>). */
6599 if (GET_CODE (op) == VEC_DUPLICATE)
6601 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6602 && mode != V2DImode)
6605 element = XEXP (op, 0);
6606 if (!CONST_INT_P (element))
6609 value = INTVAL (element);
6610 if (!IN_RANGE (value, -128, 127))
6614 /* Handle (const_vector [...]). */
6615 else if (GET_CODE (op) == CONST_VECTOR)
6617 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6618 && mode != V2DImode)
6621 element = CONST_VECTOR_ELT (op, 0);
6622 if (!CONST_INT_P (element))
6625 value = INTVAL (element);
6626 if (!IN_RANGE (value, -128, 127))
6629 for (i = 1; i < nunits; i++)
6631 element = CONST_VECTOR_ELT (op, i);
6632 if (!CONST_INT_P (element))
6635 if (value != INTVAL (element))
6640 /* Handle integer constants being loaded into the upper part of the VSX
6641 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6642 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6643 else if (CONST_INT_P (op))
6645 if (!SCALAR_INT_MODE_P (mode))
6648 value = INTVAL (op);
6649 if (!IN_RANGE (value, -128, 127))
6652 if (!IN_RANGE (value, -1, 0))
6654 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6657 if (EASY_VECTOR_15 (value))
6665 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6666 sign extend. Special case 0/-1 to allow getting any VSX register instead
6667 of an Altivec register. */
6668 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6669 && EASY_VECTOR_15 (value))
6672 /* Return # of instructions and the constant byte for XXSPLTIB. */
6673 if (mode == V16QImode)
6676 else if (IN_RANGE (value, -1, 0))
6682 *constant_ptr = (int) value;
6687 output_vec_const_move (rtx *operands)
6695 mode = GET_MODE (dest);
6699 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6700 int xxspltib_value = 256;
6703 if (zero_constant (vec, mode))
6705 if (TARGET_P9_VECTOR)
6706 return "xxspltib %x0,0";
6708 else if (dest_vmx_p)
6709 return "vspltisw %0,0";
6712 return "xxlxor %x0,%x0,%x0";
6715 if (all_ones_constant (vec, mode))
6717 if (TARGET_P9_VECTOR)
6718 return "xxspltib %x0,255";
6720 else if (dest_vmx_p)
6721 return "vspltisw %0,-1";
6723 else if (TARGET_P8_VECTOR)
6724 return "xxlorc %x0,%x0,%x0";
6730 if (TARGET_P9_VECTOR
6731 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6735 operands[2] = GEN_INT (xxspltib_value & 0xff);
6736 return "xxspltib %x0,%2";
6747 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6748 if (zero_constant (vec, mode))
6749 return "vspltisw %0,0";
6751 if (all_ones_constant (vec, mode))
6752 return "vspltisw %0,-1";
6754 /* Do we need to construct a value using VSLDOI? */
6755 shift = vspltis_shifted (vec);
6759 splat_vec = gen_easy_altivec_constant (vec);
6760 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6761 operands[1] = XEXP (splat_vec, 0);
6762 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6765 switch (GET_MODE (splat_vec))
6768 return "vspltisw %0,%1";
6771 return "vspltish %0,%1";
6774 return "vspltisb %0,%1";
6784 /* Initialize TARGET of vector PAIRED to VALS. */
6787 paired_expand_vector_init (rtx target, rtx vals)
6789 machine_mode mode = GET_MODE (target);
6790 int n_elts = GET_MODE_NUNITS (mode);
6792 rtx x, new_rtx, tmp, constant_op, op1, op2;
6795 for (i = 0; i < n_elts; ++i)
6797 x = XVECEXP (vals, 0, i);
6798 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6803 /* Load from constant pool. */
6804 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
6810 /* The vector is initialized only with non-constants. */
6811 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
6812 XVECEXP (vals, 0, 1));
6814 emit_move_insn (target, new_rtx);
6818 /* One field is non-constant and the other one is a constant. Load the
6819 constant from the constant pool and use ps_merge instruction to
6820 construct the whole vector. */
6821 op1 = XVECEXP (vals, 0, 0);
6822 op2 = XVECEXP (vals, 0, 1);
6824 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
6826 tmp = gen_reg_rtx (GET_MODE (constant_op));
6827 emit_move_insn (tmp, constant_op);
6829 if (CONSTANT_P (op1))
6830 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
6832 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
6834 emit_move_insn (target, new_rtx);
6838 paired_expand_vector_move (rtx operands[])
6840 rtx op0 = operands[0], op1 = operands[1];
6842 emit_move_insn (op0, op1);
6845 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6846 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6847 operands for the relation operation COND. This is a recursive
6851 paired_emit_vector_compare (enum rtx_code rcode,
6852 rtx dest, rtx op0, rtx op1,
6853 rtx cc_op0, rtx cc_op1)
6855 rtx tmp = gen_reg_rtx (V2SFmode);
6858 gcc_assert (TARGET_PAIRED_FLOAT);
6859 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
6865 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6869 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6870 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
6874 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
6877 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6880 tmp1 = gen_reg_rtx (V2SFmode);
6881 max = gen_reg_rtx (V2SFmode);
6882 min = gen_reg_rtx (V2SFmode);
6883 gen_reg_rtx (V2SFmode);
6885 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6886 emit_insn (gen_selv2sf4
6887 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6888 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
6889 emit_insn (gen_selv2sf4
6890 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6891 emit_insn (gen_subv2sf3 (tmp1, min, max));
6892 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
6895 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
6898 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6901 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
6904 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6907 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
6916 /* Emit vector conditional expression.
6917 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6918 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6921 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
6922 rtx cond, rtx cc_op0, rtx cc_op1)
6924 enum rtx_code rcode = GET_CODE (cond);
6926 if (!TARGET_PAIRED_FLOAT)
6929 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
6934 /* Initialize vector TARGET to VALS. */
6937 rs6000_expand_vector_init (rtx target, rtx vals)
6939 machine_mode mode = GET_MODE (target);
6940 machine_mode inner_mode = GET_MODE_INNER (mode);
6941 int n_elts = GET_MODE_NUNITS (mode);
6942 int n_var = 0, one_var = -1;
6943 bool all_same = true, all_const_zero = true;
6947 for (i = 0; i < n_elts; ++i)
6949 x = XVECEXP (vals, 0, i);
6950 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6951 ++n_var, one_var = i;
6952 else if (x != CONST0_RTX (inner_mode))
6953 all_const_zero = false;
6955 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6961 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6962 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6963 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6965 /* Zero register. */
6966 emit_move_insn (target, CONST0_RTX (mode));
6969 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6971 /* Splat immediate. */
6972 emit_insn (gen_rtx_SET (target, const_vec));
6977 /* Load from constant pool. */
6978 emit_move_insn (target, const_vec);
6983 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6984 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6988 size_t num_elements = all_same ? 1 : 2;
6989 for (i = 0; i < num_elements; i++)
6991 op[i] = XVECEXP (vals, 0, i);
6992 /* Just in case there is a SUBREG with a smaller mode, do a
6994 if (GET_MODE (op[i]) != inner_mode)
6996 rtx tmp = gen_reg_rtx (inner_mode);
6997 convert_move (tmp, op[i], 0);
7000 /* Allow load with splat double word. */
7001 else if (MEM_P (op[i]))
7004 op[i] = force_reg (inner_mode, op[i]);
7006 else if (!REG_P (op[i]))
7007 op[i] = force_reg (inner_mode, op[i]);
7012 if (mode == V2DFmode)
7013 emit_insn (gen_vsx_splat_v2df (target, op[0]));
7015 emit_insn (gen_vsx_splat_v2di (target, op[0]));
7019 if (mode == V2DFmode)
7020 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
7022 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
7027 /* Special case initializing vector int if we are on 64-bit systems with
7028 direct move or we have the ISA 3.0 instructions. */
7029 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
7030 && TARGET_DIRECT_MOVE_64BIT)
7034 rtx element0 = XVECEXP (vals, 0, 0);
7035 if (MEM_P (element0))
7036 element0 = rs6000_address_for_fpconvert (element0);
7038 element0 = force_reg (SImode, element0);
7040 if (TARGET_P9_VECTOR)
7041 emit_insn (gen_vsx_splat_v4si (target, element0));
7044 rtx tmp = gen_reg_rtx (DImode);
7045 emit_insn (gen_zero_extendsidi2 (tmp, element0));
7046 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
7055 for (i = 0; i < 4; i++)
7057 elements[i] = XVECEXP (vals, 0, i);
7058 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
7059 elements[i] = copy_to_mode_reg (SImode, elements[i]);
7062 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
7063 elements[2], elements[3]));
7068 /* With single precision floating point on VSX, know that internally single
7069 precision is actually represented as a double, and either make 2 V2DF
7070 vectors, and convert these vectors to single precision, or do one
7071 conversion, and splat the result to the other elements. */
7072 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
7076 rtx element0 = XVECEXP (vals, 0, 0);
7078 if (TARGET_P9_VECTOR)
7080 if (MEM_P (element0))
7081 element0 = rs6000_address_for_fpconvert (element0);
7083 emit_insn (gen_vsx_splat_v4sf (target, element0));
7088 rtx freg = gen_reg_rtx (V4SFmode);
7089 rtx sreg = force_reg (SFmode, element0);
7090 rtx cvt = (TARGET_XSCVDPSPN
7091 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
7092 : gen_vsx_xscvdpsp_scalar (freg, sreg));
7095 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
7101 rtx dbl_even = gen_reg_rtx (V2DFmode);
7102 rtx dbl_odd = gen_reg_rtx (V2DFmode);
7103 rtx flt_even = gen_reg_rtx (V4SFmode);
7104 rtx flt_odd = gen_reg_rtx (V4SFmode);
7105 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
7106 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
7107 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
7108 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
7110 /* Use VMRGEW if we can instead of doing a permute. */
7111 if (TARGET_P8_VECTOR)
7113 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
7114 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
7115 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7116 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7117 if (BYTES_BIG_ENDIAN)
7118 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
7120 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
7124 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
7125 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
7126 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7127 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7128 rs6000_expand_extract_even (target, flt_even, flt_odd);
7134 /* Special case initializing vector short/char that are splats if we are on
7135 64-bit systems with direct move. */
7136 if (all_same && TARGET_DIRECT_MOVE_64BIT
7137 && (mode == V16QImode || mode == V8HImode))
7139 rtx op0 = XVECEXP (vals, 0, 0);
7140 rtx di_tmp = gen_reg_rtx (DImode);
7143 op0 = force_reg (GET_MODE_INNER (mode), op0);
7145 if (mode == V16QImode)
7147 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
7148 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
7152 if (mode == V8HImode)
7154 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
7155 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
7160 /* Store value to stack temp. Load vector element. Splat. However, splat
7161 of 64-bit items is not supported on Altivec. */
7162 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
7164 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7165 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
7166 XVECEXP (vals, 0, 0));
7167 x = gen_rtx_UNSPEC (VOIDmode,
7168 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7169 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7171 gen_rtx_SET (target, mem),
7173 x = gen_rtx_VEC_SELECT (inner_mode, target,
7174 gen_rtx_PARALLEL (VOIDmode,
7175 gen_rtvec (1, const0_rtx)));
7176 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
7180 /* One field is non-constant. Load constant then overwrite
7184 rtx copy = copy_rtx (vals);
7186 /* Load constant part of vector, substitute neighboring value for
7188 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
7189 rs6000_expand_vector_init (target, copy);
7191 /* Insert variable. */
7192 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7196 /* Construct the vector in memory one field at a time
7197 and load the whole vector. */
7198 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7199 for (i = 0; i < n_elts; i++)
7200 emit_move_insn (adjust_address_nv (mem, inner_mode,
7201 i * GET_MODE_SIZE (inner_mode)),
7202 XVECEXP (vals, 0, i));
7203 emit_move_insn (target, mem);
7206 /* Set field ELT of TARGET to VAL. */
7209 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7211 machine_mode mode = GET_MODE (target);
7212 machine_mode inner_mode = GET_MODE_INNER (mode);
7213 rtx reg = gen_reg_rtx (mode);
7215 int width = GET_MODE_SIZE (inner_mode);
7218 val = force_reg (GET_MODE (val), val);
7220 if (VECTOR_MEM_VSX_P (mode))
7222 rtx insn = NULL_RTX;
7223 rtx elt_rtx = GEN_INT (elt);
7225 if (mode == V2DFmode)
7226 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7228 else if (mode == V2DImode)
7229 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7231 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7233 if (mode == V4SImode)
7234 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7235 else if (mode == V8HImode)
7236 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7237 else if (mode == V16QImode)
7238 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7239 else if (mode == V4SFmode)
7240 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7250 /* Simplify setting single element vectors like V1TImode. */
7251 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7253 emit_move_insn (target, gen_lowpart (mode, val));
7257 /* Load single variable value. */
7258 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7259 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7260 x = gen_rtx_UNSPEC (VOIDmode,
7261 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7262 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7264 gen_rtx_SET (reg, mem),
7267 /* Linear sequence. */
7268 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7269 for (i = 0; i < 16; ++i)
7270 XVECEXP (mask, 0, i) = GEN_INT (i);
7272 /* Set permute mask to insert element into target. */
7273 for (i = 0; i < width; ++i)
7274 XVECEXP (mask, 0, elt*width + i)
7275 = GEN_INT (i + 0x10);
7276 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7278 if (BYTES_BIG_ENDIAN)
7279 x = gen_rtx_UNSPEC (mode,
7280 gen_rtvec (3, target, reg,
7281 force_reg (V16QImode, x)),
7285 if (TARGET_P9_VECTOR)
7286 x = gen_rtx_UNSPEC (mode,
7287 gen_rtvec (3, reg, target,
7288 force_reg (V16QImode, x)),
7292 /* Invert selector. We prefer to generate VNAND on P8 so
7293 that future fusion opportunities can kick in, but must
7294 generate VNOR elsewhere. */
7295 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7296 rtx iorx = (TARGET_P8_VECTOR
7297 ? gen_rtx_IOR (V16QImode, notx, notx)
7298 : gen_rtx_AND (V16QImode, notx, notx));
7299 rtx tmp = gen_reg_rtx (V16QImode);
7300 emit_insn (gen_rtx_SET (tmp, iorx));
7302 /* Permute with operands reversed and adjusted selector. */
7303 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7308 emit_insn (gen_rtx_SET (target, x));
7311 /* Extract field ELT from VEC into TARGET. */
7314 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7316 machine_mode mode = GET_MODE (vec);
7317 machine_mode inner_mode = GET_MODE_INNER (mode);
7320 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7327 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7328 emit_move_insn (target, gen_lowpart (TImode, vec));
7331 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7334 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7337 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7340 if (TARGET_DIRECT_MOVE_64BIT)
7342 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7348 if (TARGET_DIRECT_MOVE_64BIT)
7350 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7356 if (TARGET_DIRECT_MOVE_64BIT)
7358 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7364 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7365 && TARGET_DIRECT_MOVE_64BIT)
7367 if (GET_MODE (elt) != DImode)
7369 rtx tmp = gen_reg_rtx (DImode);
7370 convert_move (tmp, elt, 0);
7373 else if (!REG_P (elt))
7374 elt = force_reg (DImode, elt);
7379 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7383 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7387 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7391 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7395 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7399 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7407 gcc_assert (CONST_INT_P (elt));
7409 /* Allocate mode-sized buffer. */
7410 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7412 emit_move_insn (mem, vec);
7414 /* Add offset to field within buffer matching vector element. */
7415 mem = adjust_address_nv (mem, inner_mode,
7416 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7418 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7421 /* Helper function to return the register number of a RTX. */
7423 regno_or_subregno (rtx op)
7427 else if (SUBREG_P (op))
7428 return subreg_regno (op);
7433 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7434 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7435 temporary (BASE_TMP) to fixup the address. Return the new memory address
7436 that is valid for reads or writes to a given register (SCALAR_REG). */
7439 rs6000_adjust_vec_address (rtx scalar_reg,
7443 machine_mode scalar_mode)
7445 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7446 rtx addr = XEXP (mem, 0);
7451 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7452 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7454 /* Calculate what we need to add to the address to get the element
7456 if (CONST_INT_P (element))
7457 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7460 int byte_shift = exact_log2 (scalar_size);
7461 gcc_assert (byte_shift >= 0);
7463 if (byte_shift == 0)
7464 element_offset = element;
7468 if (TARGET_POWERPC64)
7469 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7471 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7473 element_offset = base_tmp;
7477 /* Create the new address pointing to the element within the vector. If we
7478 are adding 0, we don't have to change the address. */
7479 if (element_offset == const0_rtx)
7482 /* A simple indirect address can be converted into a reg + offset
7484 else if (REG_P (addr) || SUBREG_P (addr))
7485 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7487 /* Optimize D-FORM addresses with constant offset with a constant element, to
7488 include the element offset in the address directly. */
7489 else if (GET_CODE (addr) == PLUS)
7491 rtx op0 = XEXP (addr, 0);
7492 rtx op1 = XEXP (addr, 1);
7495 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7496 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7498 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7499 rtx offset_rtx = GEN_INT (offset);
7501 if (IN_RANGE (offset, -32768, 32767)
7502 && (scalar_size < 8 || (offset & 0x3) == 0))
7503 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7506 emit_move_insn (base_tmp, offset_rtx);
7507 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7512 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7513 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7515 /* Note, ADDI requires the register being added to be a base
7516 register. If the register was R0, load it up into the temporary
7519 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7521 insn = gen_add3_insn (base_tmp, op1, element_offset);
7522 gcc_assert (insn != NULL_RTX);
7527 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7529 insn = gen_add3_insn (base_tmp, element_offset, op1);
7530 gcc_assert (insn != NULL_RTX);
7536 emit_move_insn (base_tmp, op1);
7537 emit_insn (gen_add2_insn (base_tmp, element_offset));
7540 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7546 emit_move_insn (base_tmp, addr);
7547 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7550 /* If we have a PLUS, we need to see whether the particular register class
7551 allows for D-FORM or X-FORM addressing. */
7552 if (GET_CODE (new_addr) == PLUS)
7554 rtx op1 = XEXP (new_addr, 1);
7555 addr_mask_type addr_mask;
7556 int scalar_regno = regno_or_subregno (scalar_reg);
7558 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7559 if (INT_REGNO_P (scalar_regno))
7560 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7562 else if (FP_REGNO_P (scalar_regno))
7563 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7565 else if (ALTIVEC_REGNO_P (scalar_regno))
7566 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7571 if (REG_P (op1) || SUBREG_P (op1))
7572 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7574 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7577 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7578 valid_addr_p = true;
7581 valid_addr_p = false;
7585 emit_move_insn (base_tmp, new_addr);
7586 new_addr = base_tmp;
7589 return change_address (mem, scalar_mode, new_addr);
7592 /* Split a variable vec_extract operation into the component instructions. */
7595 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7598 machine_mode mode = GET_MODE (src);
7599 machine_mode scalar_mode = GET_MODE (dest);
7600 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7601 int byte_shift = exact_log2 (scalar_size);
7603 gcc_assert (byte_shift >= 0);
7605 /* If we are given a memory address, optimize to load just the element. We
7606 don't have to adjust the vector element number on little endian
7610 gcc_assert (REG_P (tmp_gpr));
7611 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7612 tmp_gpr, scalar_mode));
7616 else if (REG_P (src) || SUBREG_P (src))
7618 int bit_shift = byte_shift + 3;
7620 int dest_regno = regno_or_subregno (dest);
7621 int src_regno = regno_or_subregno (src);
7622 int element_regno = regno_or_subregno (element);
7624 gcc_assert (REG_P (tmp_gpr));
7626 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7627 a general purpose register. */
7628 if (TARGET_P9_VECTOR
7629 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7630 && INT_REGNO_P (dest_regno)
7631 && ALTIVEC_REGNO_P (src_regno)
7632 && INT_REGNO_P (element_regno))
7634 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7635 rtx element_si = gen_rtx_REG (SImode, element_regno);
7637 if (mode == V16QImode)
7638 emit_insn (VECTOR_ELT_ORDER_BIG
7639 ? gen_vextublx (dest_si, element_si, src)
7640 : gen_vextubrx (dest_si, element_si, src));
7642 else if (mode == V8HImode)
7644 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7645 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7646 emit_insn (VECTOR_ELT_ORDER_BIG
7647 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7648 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7654 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7655 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7656 emit_insn (VECTOR_ELT_ORDER_BIG
7657 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7658 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7665 gcc_assert (REG_P (tmp_altivec));
7667 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7668 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7669 will shift the element into the upper position (adding 3 to convert a
7670 byte shift into a bit shift). */
7671 if (scalar_size == 8)
7673 if (!VECTOR_ELT_ORDER_BIG)
7675 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7681 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7683 emit_insn (gen_rtx_SET (tmp_gpr,
7684 gen_rtx_AND (DImode,
7685 gen_rtx_ASHIFT (DImode,
7692 if (!VECTOR_ELT_ORDER_BIG)
7694 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7696 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7697 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7703 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7706 /* Get the value into the lower byte of the Altivec register where VSLO
7708 if (TARGET_P9_VECTOR)
7709 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7710 else if (can_create_pseudo_p ())
7711 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7714 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7715 emit_move_insn (tmp_di, tmp_gpr);
7716 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7719 /* Do the VSLO to get the value into the final location. */
7723 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7727 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7732 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7733 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7734 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7735 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7738 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7746 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7747 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7748 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7749 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7751 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7752 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7753 GEN_INT (64 - (8 * scalar_size))));
7767 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7768 two SImode values. */
7771 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7773 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7775 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7777 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7778 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7780 emit_move_insn (dest, GEN_INT (const1 | const2));
7784 /* Put si1 into upper 32-bits of dest. */
7785 if (CONST_INT_P (si1))
7786 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7789 /* Generate RLDIC. */
7790 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7791 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7792 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7793 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7794 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7795 emit_insn (gen_rtx_SET (dest, and_rtx));
7798 /* Put si2 into the temporary. */
7799 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7800 if (CONST_INT_P (si2))
7801 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7803 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7805 /* Combine the two parts. */
7806 emit_insn (gen_iordi3 (dest, dest, tmp));
7810 /* Split a V4SI initialization. */
7813 rs6000_split_v4si_init (rtx operands[])
7815 rtx dest = operands[0];
7817 /* Destination is a GPR, build up the two DImode parts in place. */
7818 if (REG_P (dest) || SUBREG_P (dest))
7820 int d_regno = regno_or_subregno (dest);
7821 rtx scalar1 = operands[1];
7822 rtx scalar2 = operands[2];
7823 rtx scalar3 = operands[3];
7824 rtx scalar4 = operands[4];
7825 rtx tmp1 = operands[5];
7826 rtx tmp2 = operands[6];
7828 /* Even though we only need one temporary (plus the destination, which
7829 has an early clobber constraint, try to use two temporaries, one for
7830 each double word created. That way the 2nd insn scheduling pass can
7831 rearrange things so the two parts are done in parallel. */
7832 if (BYTES_BIG_ENDIAN)
7834 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7835 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7836 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7837 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7841 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7842 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7843 gcc_assert (!VECTOR_ELT_ORDER_BIG);
7844 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7845 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7854 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7855 selects whether the alignment is abi mandated, optional, or
7856 both abi and optional alignment. */
7859 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7861 if (how != align_opt)
7863 if (TREE_CODE (type) == VECTOR_TYPE)
7865 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
7870 else if (align < 128)
7875 if (how != align_abi)
7877 if (TREE_CODE (type) == ARRAY_TYPE
7878 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7880 if (align < BITS_PER_WORD)
7881 align = BITS_PER_WORD;
7888 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7889 instructions simply ignore the low bits; VSX memory instructions
7890 are aligned to 4 or 8 bytes. */
7893 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7895 return (STRICT_ALIGNMENT
7896 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7897 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7898 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7899 && (int) align < VECTOR_ALIGN (mode)))));
7902 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7905 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7907 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7909 if (computed != 128)
7912 if (!warned && warn_psabi)
7915 inform (input_location,
7916 "the layout of aggregates containing vectors with"
7917 " %d-byte alignment has changed in GCC 5",
7918 computed / BITS_PER_UNIT);
7921 /* In current GCC there is no special case. */
7928 /* AIX increases natural record alignment to doubleword if the first
7929 field is an FP double while the FP fields remain word aligned. */
7932 rs6000_special_round_type_align (tree type, unsigned int computed,
7933 unsigned int specified)
7935 unsigned int align = MAX (computed, specified);
7936 tree field = TYPE_FIELDS (type);
7938 /* Skip all non field decls */
7939 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7940 field = DECL_CHAIN (field);
7942 if (field != NULL && field != type)
7944 type = TREE_TYPE (field);
7945 while (TREE_CODE (type) == ARRAY_TYPE)
7946 type = TREE_TYPE (type);
7948 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7949 align = MAX (align, 64);
7955 /* Darwin increases record alignment to the natural alignment of
7959 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7960 unsigned int specified)
7962 unsigned int align = MAX (computed, specified);
7964 if (TYPE_PACKED (type))
7967 /* Find the first field, looking down into aggregates. */
7969 tree field = TYPE_FIELDS (type);
7970 /* Skip all non field decls */
7971 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7972 field = DECL_CHAIN (field);
7975 /* A packed field does not contribute any extra alignment. */
7976 if (DECL_PACKED (field))
7978 type = TREE_TYPE (field);
7979 while (TREE_CODE (type) == ARRAY_TYPE)
7980 type = TREE_TYPE (type);
7981 } while (AGGREGATE_TYPE_P (type));
7983 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7984 align = MAX (align, TYPE_ALIGN (type));
7989 /* Return 1 for an operand in small memory on V.4/eabi. */
7992 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7993 machine_mode mode ATTRIBUTE_UNUSED)
7998 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
8001 if (DEFAULT_ABI != ABI_V4)
8004 if (GET_CODE (op) == SYMBOL_REF)
8007 else if (GET_CODE (op) != CONST
8008 || GET_CODE (XEXP (op, 0)) != PLUS
8009 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
8010 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
8015 rtx sum = XEXP (op, 0);
8016 HOST_WIDE_INT summand;
8018 /* We have to be careful here, because it is the referenced address
8019 that must be 32k from _SDA_BASE_, not just the symbol. */
8020 summand = INTVAL (XEXP (sum, 1));
8021 if (summand < 0 || summand > g_switch_value)
8024 sym_ref = XEXP (sum, 0);
8027 return SYMBOL_REF_SMALL_P (sym_ref);
8033 /* Return true if either operand is a general purpose register. */
8036 gpr_or_gpr_p (rtx op0, rtx op1)
8038 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
8039 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
8042 /* Return true if this is a move direct operation between GPR registers and
8043 floating point/VSX registers. */
8046 direct_move_p (rtx op0, rtx op1)
8050 if (!REG_P (op0) || !REG_P (op1))
8053 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
8056 regno0 = REGNO (op0);
8057 regno1 = REGNO (op1);
8058 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
8061 if (INT_REGNO_P (regno0))
8062 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
8064 else if (INT_REGNO_P (regno1))
8066 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
8069 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
8076 /* Return true if the OFFSET is valid for the quad address instructions that
8077 use d-form (register + offset) addressing. */
8080 quad_address_offset_p (HOST_WIDE_INT offset)
8082 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
8085 /* Return true if the ADDR is an acceptable address for a quad memory
8086 operation of mode MODE (either LQ/STQ for general purpose registers, or
8087 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8088 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8089 3.0 LXV/STXV instruction. */
8092 quad_address_p (rtx addr, machine_mode mode, bool strict)
8096 if (GET_MODE_SIZE (mode) != 16)
8099 if (legitimate_indirect_address_p (addr, strict))
8102 if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
8105 if (GET_CODE (addr) != PLUS)
8108 op0 = XEXP (addr, 0);
8109 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
8112 op1 = XEXP (addr, 1);
8113 if (!CONST_INT_P (op1))
8116 return quad_address_offset_p (INTVAL (op1));
8119 /* Return true if this is a load or store quad operation. This function does
8120 not handle the atomic quad memory instructions. */
8123 quad_load_store_p (rtx op0, rtx op1)
8127 if (!TARGET_QUAD_MEMORY)
8130 else if (REG_P (op0) && MEM_P (op1))
8131 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
8132 && quad_memory_operand (op1, GET_MODE (op1))
8133 && !reg_overlap_mentioned_p (op0, op1));
8135 else if (MEM_P (op0) && REG_P (op1))
8136 ret = (quad_memory_operand (op0, GET_MODE (op0))
8137 && quad_int_reg_operand (op1, GET_MODE (op1)));
8142 if (TARGET_DEBUG_ADDR)
8144 fprintf (stderr, "\n========== quad_load_store, return %s\n",
8145 ret ? "true" : "false");
8146 debug_rtx (gen_rtx_SET (op0, op1));
8152 /* Given an address, return a constant offset term if one exists. */
8155 address_offset (rtx op)
8157 if (GET_CODE (op) == PRE_INC
8158 || GET_CODE (op) == PRE_DEC)
8160 else if (GET_CODE (op) == PRE_MODIFY
8161 || GET_CODE (op) == LO_SUM)
8164 if (GET_CODE (op) == CONST)
8167 if (GET_CODE (op) == PLUS)
8170 if (CONST_INT_P (op))
8176 /* Return true if the MEM operand is a memory operand suitable for use
8177 with a (full width, possibly multiple) gpr load/store. On
8178 powerpc64 this means the offset must be divisible by 4.
8179 Implements 'Y' constraint.
8181 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8182 a constraint function we know the operand has satisfied a suitable
8183 memory predicate. Also accept some odd rtl generated by reload
8184 (see rs6000_legitimize_reload_address for various forms). It is
8185 important that reload rtl be accepted by appropriate constraints
8186 but not by the operand predicate.
8188 Offsetting a lo_sum should not be allowed, except where we know by
8189 alignment that a 32k boundary is not crossed, but see the ???
8190 comment in rs6000_legitimize_reload_address. Note that by
8191 "offsetting" here we mean a further offset to access parts of the
8192 MEM. It's fine to have a lo_sum where the inner address is offset
8193 from a sym, since the same sym+offset will appear in the high part
8194 of the address calculation. */
8197 mem_operand_gpr (rtx op, machine_mode mode)
8199 unsigned HOST_WIDE_INT offset;
8201 rtx addr = XEXP (op, 0);
8203 op = address_offset (addr);
8207 offset = INTVAL (op);
8208 if (TARGET_POWERPC64 && (offset & 3) != 0)
8211 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8215 if (GET_CODE (addr) == LO_SUM)
8216 /* For lo_sum addresses, we must allow any offset except one that
8217 causes a wrap, so test only the low 16 bits. */
8218 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8220 return offset + 0x8000 < 0x10000u - extra;
8223 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8224 enforce an offset divisible by 4 even for 32-bit. */
8227 mem_operand_ds_form (rtx op, machine_mode mode)
8229 unsigned HOST_WIDE_INT offset;
8231 rtx addr = XEXP (op, 0);
8233 if (!offsettable_address_p (false, mode, addr))
8236 op = address_offset (addr);
8240 offset = INTVAL (op);
8241 if ((offset & 3) != 0)
8244 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8248 if (GET_CODE (addr) == LO_SUM)
8249 /* For lo_sum addresses, we must allow any offset except one that
8250 causes a wrap, so test only the low 16 bits. */
8251 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8253 return offset + 0x8000 < 0x10000u - extra;
8256 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8259 reg_offset_addressing_ok_p (machine_mode mode)
8273 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8274 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8275 a vector mode, if we want to use the VSX registers to move it around,
8276 we need to restrict ourselves to reg+reg addressing. Similarly for
8277 IEEE 128-bit floating point that is passed in a single vector
8279 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8280 return mode_supports_vsx_dform_quad (mode);
8285 /* Paired vector modes. Only reg+reg addressing is valid. */
8286 if (TARGET_PAIRED_FLOAT)
8291 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8292 addressing for the LFIWZX and STFIWX instructions. */
8293 if (TARGET_NO_SDMODE_STACK)
8305 virtual_stack_registers_memory_p (rtx op)
8309 if (GET_CODE (op) == REG)
8310 regnum = REGNO (op);
8312 else if (GET_CODE (op) == PLUS
8313 && GET_CODE (XEXP (op, 0)) == REG
8314 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8315 regnum = REGNO (XEXP (op, 0));
8320 return (regnum >= FIRST_VIRTUAL_REGISTER
8321 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8324 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8325 is known to not straddle a 32k boundary. This function is used
8326 to determine whether -mcmodel=medium code can use TOC pointer
8327 relative addressing for OP. This means the alignment of the TOC
8328 pointer must also be taken into account, and unfortunately that is
8331 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8332 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8336 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8340 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8342 if (GET_CODE (op) != SYMBOL_REF)
8345 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8347 if (mode_supports_vsx_dform_quad (mode))
8350 dsize = GET_MODE_SIZE (mode);
8351 decl = SYMBOL_REF_DECL (op);
8357 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8358 replacing memory addresses with an anchor plus offset. We
8359 could find the decl by rummaging around in the block->objects
8360 VEC for the given offset but that seems like too much work. */
8361 dalign = BITS_PER_UNIT;
8362 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8363 && SYMBOL_REF_ANCHOR_P (op)
8364 && SYMBOL_REF_BLOCK (op) != NULL)
8366 struct object_block *block = SYMBOL_REF_BLOCK (op);
8368 dalign = block->alignment;
8369 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8371 else if (CONSTANT_POOL_ADDRESS_P (op))
8373 /* It would be nice to have get_pool_align().. */
8374 machine_mode cmode = get_pool_mode (op);
8376 dalign = GET_MODE_ALIGNMENT (cmode);
8379 else if (DECL_P (decl))
8381 dalign = DECL_ALIGN (decl);
8385 /* Allow BLKmode when the entire object is known to not
8386 cross a 32k boundary. */
8387 if (!DECL_SIZE_UNIT (decl))
8390 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8393 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8397 dalign /= BITS_PER_UNIT;
8398 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8399 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8400 return dalign >= dsize;
8406 /* Find how many bits of the alignment we know for this access. */
8407 dalign /= BITS_PER_UNIT;
8408 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8409 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8411 lsb = offset & -offset;
8415 return dalign >= dsize;
8419 constant_pool_expr_p (rtx op)
8423 split_const (op, &base, &offset);
8424 return (GET_CODE (base) == SYMBOL_REF
8425 && CONSTANT_POOL_ADDRESS_P (base)
8426 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8429 /* These are only used to pass through from print_operand/print_operand_address
8430 to rs6000_output_addr_const_extra over the intervening function
8431 output_addr_const which is not target code. */
8432 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8434 /* Return true if OP is a toc pointer relative address (the output
8435 of create_TOC_reference). If STRICT, do not match non-split
8436 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8437 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8438 TOCREL_OFFSET_RET respectively. */
8441 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8442 const_rtx *tocrel_offset_ret)
8447 if (TARGET_CMODEL != CMODEL_SMALL)
8449 /* When strict ensure we have everything tidy. */
8451 && !(GET_CODE (op) == LO_SUM
8452 && REG_P (XEXP (op, 0))
8453 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8456 /* When not strict, allow non-split TOC addresses and also allow
8457 (lo_sum (high ..)) TOC addresses created during reload. */
8458 if (GET_CODE (op) == LO_SUM)
8462 const_rtx tocrel_base = op;
8463 const_rtx tocrel_offset = const0_rtx;
8465 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8467 tocrel_base = XEXP (op, 0);
8468 tocrel_offset = XEXP (op, 1);
8471 if (tocrel_base_ret)
8472 *tocrel_base_ret = tocrel_base;
8473 if (tocrel_offset_ret)
8474 *tocrel_offset_ret = tocrel_offset;
8476 return (GET_CODE (tocrel_base) == UNSPEC
8477 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8480 /* Return true if X is a constant pool address, and also for cmodel=medium
8481 if X is a toc-relative address known to be offsettable within MODE. */
8484 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8487 const_rtx tocrel_base, tocrel_offset;
8488 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8489 && (TARGET_CMODEL != CMODEL_MEDIUM
8490 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8492 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8493 INTVAL (tocrel_offset), mode)));
8497 legitimate_small_data_p (machine_mode mode, rtx x)
8499 return (DEFAULT_ABI == ABI_V4
8500 && !flag_pic && !TARGET_TOC
8501 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8502 && small_data_operand (x, mode));
8506 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8507 bool strict, bool worst_case)
8509 unsigned HOST_WIDE_INT offset;
8512 if (GET_CODE (x) != PLUS)
8514 if (!REG_P (XEXP (x, 0)))
8516 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8518 if (mode_supports_vsx_dform_quad (mode))
8519 return quad_address_p (x, mode, strict);
8520 if (!reg_offset_addressing_ok_p (mode))
8521 return virtual_stack_registers_memory_p (x);
8522 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8524 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8527 offset = INTVAL (XEXP (x, 1));
8533 /* Paired single modes: offset addressing isn't valid. */
8539 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8541 if (VECTOR_MEM_VSX_P (mode))
8546 if (!TARGET_POWERPC64)
8548 else if (offset & 3)
8561 if (!TARGET_POWERPC64)
8563 else if (offset & 3)
8572 return offset < 0x10000 - extra;
8576 legitimate_indexed_address_p (rtx x, int strict)
8580 if (GET_CODE (x) != PLUS)
8586 return (REG_P (op0) && REG_P (op1)
8587 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8588 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8589 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8590 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8594 avoiding_indexed_address_p (machine_mode mode)
8596 /* Avoid indexed addressing for modes that have non-indexed
8597 load/store instruction forms. */
8598 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8602 legitimate_indirect_address_p (rtx x, int strict)
8604 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8608 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8610 if (!TARGET_MACHO || !flag_pic
8611 || mode != SImode || GET_CODE (x) != MEM)
8615 if (GET_CODE (x) != LO_SUM)
8617 if (GET_CODE (XEXP (x, 0)) != REG)
8619 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8623 return CONSTANT_P (x);
8627 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8629 if (GET_CODE (x) != LO_SUM)
8631 if (GET_CODE (XEXP (x, 0)) != REG)
8633 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8635 /* quad word addresses are restricted, and we can't use LO_SUM. */
8636 if (mode_supports_vsx_dform_quad (mode))
8640 if (TARGET_ELF || TARGET_MACHO)
8644 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8646 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8647 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8648 recognizes some LO_SUM addresses as valid although this
8649 function says opposite. In most cases, LRA through different
8650 transformations can generate correct code for address reloads.
8651 It can not manage only some LO_SUM cases. So we need to add
8652 code analogous to one in rs6000_legitimize_reload_address for
8653 LOW_SUM here saying that some addresses are still valid. */
8654 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8655 && small_toc_ref (x, VOIDmode));
8656 if (TARGET_TOC && ! large_toc_ok)
8658 if (GET_MODE_NUNITS (mode) != 1)
8660 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8661 && !(/* ??? Assume floating point reg based on mode? */
8662 TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
8663 && (mode == DFmode || mode == DDmode)))
8666 return CONSTANT_P (x) || large_toc_ok;
8673 /* Try machine-dependent ways of modifying an illegitimate address
8674 to be legitimate. If we find one, return the new, valid address.
8675 This is used from only one place: `memory_address' in explow.c.
8677 OLDX is the address as it was before break_out_memory_refs was
8678 called. In some cases it is useful to look at this to decide what
8681 It is always safe for this function to do nothing. It exists to
8682 recognize opportunities to optimize the output.
8684 On RS/6000, first check for the sum of a register with a constant
8685 integer that is out of range. If so, generate code to add the
8686 constant with the low-order 16 bits masked to the register and force
8687 this result into another register (this can be done with `cau').
8688 Then generate an address of REG+(CONST&0xffff), allowing for the
8689 possibility of bit 16 being a one.
8691 Then check for the sum of a register and something not constant, try to
8692 load the other things into a register and return the sum. */
8695 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8700 if (!reg_offset_addressing_ok_p (mode)
8701 || mode_supports_vsx_dform_quad (mode))
8703 if (virtual_stack_registers_memory_p (x))
8706 /* In theory we should not be seeing addresses of the form reg+0,
8707 but just in case it is generated, optimize it away. */
8708 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8709 return force_reg (Pmode, XEXP (x, 0));
8711 /* For TImode with load/store quad, restrict addresses to just a single
8712 pointer, so it works with both GPRs and VSX registers. */
8713 /* Make sure both operands are registers. */
8714 else if (GET_CODE (x) == PLUS
8715 && (mode != TImode || !TARGET_VSX))
8716 return gen_rtx_PLUS (Pmode,
8717 force_reg (Pmode, XEXP (x, 0)),
8718 force_reg (Pmode, XEXP (x, 1)));
8720 return force_reg (Pmode, x);
8722 if (GET_CODE (x) == SYMBOL_REF)
8724 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8726 return rs6000_legitimize_tls_address (x, model);
8738 /* As in legitimate_offset_address_p we do not assume
8739 worst-case. The mode here is just a hint as to the registers
8740 used. A TImode is usually in gprs, but may actually be in
8741 fprs. Leave worst-case scenario for reload to handle via
8742 insn constraints. PTImode is only GPRs. */
8749 if (GET_CODE (x) == PLUS
8750 && GET_CODE (XEXP (x, 0)) == REG
8751 && GET_CODE (XEXP (x, 1)) == CONST_INT
8752 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8754 && !PAIRED_VECTOR_MODE (mode))
8756 HOST_WIDE_INT high_int, low_int;
8758 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8759 if (low_int >= 0x8000 - extra)
8761 high_int = INTVAL (XEXP (x, 1)) - low_int;
8762 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8763 GEN_INT (high_int)), 0);
8764 return plus_constant (Pmode, sum, low_int);
8766 else if (GET_CODE (x) == PLUS
8767 && GET_CODE (XEXP (x, 0)) == REG
8768 && GET_CODE (XEXP (x, 1)) != CONST_INT
8769 && GET_MODE_NUNITS (mode) == 1
8770 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8771 || (/* ??? Assume floating point reg based on mode? */
8772 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8773 && (mode == DFmode || mode == DDmode)))
8774 && !avoiding_indexed_address_p (mode))
8776 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8777 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8779 else if (PAIRED_VECTOR_MODE (mode))
8783 /* We accept [reg + reg]. */
8785 if (GET_CODE (x) == PLUS)
8787 rtx op1 = XEXP (x, 0);
8788 rtx op2 = XEXP (x, 1);
8791 op1 = force_reg (Pmode, op1);
8792 op2 = force_reg (Pmode, op2);
8794 /* We can't always do [reg + reg] for these, because [reg +
8795 reg + offset] is not a legitimate addressing mode. */
8796 y = gen_rtx_PLUS (Pmode, op1, op2);
8798 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
8799 return force_reg (Pmode, y);
8804 return force_reg (Pmode, x);
8806 else if ((TARGET_ELF
8808 || !MACHO_DYNAMIC_NO_PIC_P
8814 && GET_CODE (x) != CONST_INT
8815 && GET_CODE (x) != CONST_WIDE_INT
8816 && GET_CODE (x) != CONST_DOUBLE
8818 && GET_MODE_NUNITS (mode) == 1
8819 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8820 || (/* ??? Assume floating point reg based on mode? */
8821 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8822 && (mode == DFmode || mode == DDmode))))
8824 rtx reg = gen_reg_rtx (Pmode);
8826 emit_insn (gen_elf_high (reg, x));
8828 emit_insn (gen_macho_high (reg, x));
8829 return gen_rtx_LO_SUM (Pmode, reg, x);
8832 && GET_CODE (x) == SYMBOL_REF
8833 && constant_pool_expr_p (x)
8834 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8835 return create_TOC_reference (x, NULL_RTX);
8840 /* Debug version of rs6000_legitimize_address. */
8842 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8848 ret = rs6000_legitimize_address (x, oldx, mode);
8849 insns = get_insns ();
8855 "\nrs6000_legitimize_address: mode %s, old code %s, "
8856 "new code %s, modified\n",
8857 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8858 GET_RTX_NAME (GET_CODE (ret)));
8860 fprintf (stderr, "Original address:\n");
8863 fprintf (stderr, "oldx:\n");
8866 fprintf (stderr, "New address:\n");
8871 fprintf (stderr, "Insns added:\n");
8872 debug_rtx_list (insns, 20);
8878 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8879 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8890 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8891 We need to emit DTP-relative relocations. */
8893 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8895 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8900 fputs ("\t.long\t", file);
8903 fputs (DOUBLE_INT_ASM_OP, file);
8908 output_addr_const (file, x);
8910 fputs ("@dtprel+0x8000", file);
8911 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8913 switch (SYMBOL_REF_TLS_MODEL (x))
8917 case TLS_MODEL_LOCAL_EXEC:
8918 fputs ("@le", file);
8920 case TLS_MODEL_INITIAL_EXEC:
8921 fputs ("@ie", file);
8923 case TLS_MODEL_GLOBAL_DYNAMIC:
8924 case TLS_MODEL_LOCAL_DYNAMIC:
8933 /* Return true if X is a symbol that refers to real (rather than emulated)
8937 rs6000_real_tls_symbol_ref_p (rtx x)
8939 return (GET_CODE (x) == SYMBOL_REF
8940 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8943 /* In the name of slightly smaller debug output, and to cater to
8944 general assembler lossage, recognize various UNSPEC sequences
8945 and turn them back into a direct symbol reference. */
8948 rs6000_delegitimize_address (rtx orig_x)
8952 orig_x = delegitimize_mem_from_attrs (orig_x);
8958 if (TARGET_CMODEL != CMODEL_SMALL
8959 && GET_CODE (y) == LO_SUM)
8963 if (GET_CODE (y) == PLUS
8964 && GET_MODE (y) == Pmode
8965 && CONST_INT_P (XEXP (y, 1)))
8967 offset = XEXP (y, 1);
8971 if (GET_CODE (y) == UNSPEC
8972 && XINT (y, 1) == UNSPEC_TOCREL)
8974 y = XVECEXP (y, 0, 0);
8977 /* Do not associate thread-local symbols with the original
8978 constant pool symbol. */
8980 && GET_CODE (y) == SYMBOL_REF
8981 && CONSTANT_POOL_ADDRESS_P (y)
8982 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8986 if (offset != NULL_RTX)
8987 y = gen_rtx_PLUS (Pmode, y, offset);
8988 if (!MEM_P (orig_x))
8991 return replace_equiv_address_nv (orig_x, y);
8995 && GET_CODE (orig_x) == LO_SUM
8996 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8998 y = XEXP (XEXP (orig_x, 1), 0);
8999 if (GET_CODE (y) == UNSPEC
9000 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
9001 return XVECEXP (y, 0, 0);
9007 /* Return true if X shouldn't be emitted into the debug info.
9008 The linker doesn't like .toc section references from
9009 .debug_* sections, so reject .toc section symbols. */
9012 rs6000_const_not_ok_for_debug_p (rtx x)
9014 if (GET_CODE (x) == UNSPEC)
9016 if (GET_CODE (x) == SYMBOL_REF
9017 && CONSTANT_POOL_ADDRESS_P (x))
9019 rtx c = get_pool_constant (x);
9020 machine_mode cmode = get_pool_mode (x);
9021 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
9029 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9032 rs6000_legitimate_combined_insn (rtx_insn *insn)
9034 int icode = INSN_CODE (insn);
9036 /* Reject creating doloop insns. Combine should not be allowed
9037 to create these for a number of reasons:
9038 1) In a nested loop, if combine creates one of these in an
9039 outer loop and the register allocator happens to allocate ctr
9040 to the outer loop insn, then the inner loop can't use ctr.
9041 Inner loops ought to be more highly optimized.
9042 2) Combine often wants to create one of these from what was
9043 originally a three insn sequence, first combining the three
9044 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9045 allocated ctr, the splitter takes use back to the three insn
9046 sequence. It's better to stop combine at the two insn
9048 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9049 insns, the register allocator sometimes uses floating point
9050 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9051 jump insn and output reloads are not implemented for jumps,
9052 the ctrsi/ctrdi splitters need to handle all possible cases.
9053 That's a pain, and it gets to be seriously difficult when a
9054 splitter that runs after reload needs memory to transfer from
9055 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9056 for the difficult case. It's better to not create problems
9057 in the first place. */
9058 if (icode != CODE_FOR_nothing
9059 && (icode == CODE_FOR_bdz_si
9060 || icode == CODE_FOR_bdz_di
9061 || icode == CODE_FOR_bdnz_si
9062 || icode == CODE_FOR_bdnz_di
9063 || icode == CODE_FOR_bdztf_si
9064 || icode == CODE_FOR_bdztf_di
9065 || icode == CODE_FOR_bdnztf_si
9066 || icode == CODE_FOR_bdnztf_di))
9072 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9074 static GTY(()) rtx rs6000_tls_symbol;
9076 rs6000_tls_get_addr (void)
9078 if (!rs6000_tls_symbol)
9079 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
9081 return rs6000_tls_symbol;
9084 /* Construct the SYMBOL_REF for TLS GOT references. */
9086 static GTY(()) rtx rs6000_got_symbol;
9088 rs6000_got_sym (void)
9090 if (!rs6000_got_symbol)
9092 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9093 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
9094 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
9097 return rs6000_got_symbol;
9100 /* AIX Thread-Local Address support. */
9103 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
9105 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
9109 name = XSTR (addr, 0);
9110 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9111 or the symbol will be in TLS private data section. */
9112 if (name[strlen (name) - 1] != ']'
9113 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
9114 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
9116 tlsname = XALLOCAVEC (char, strlen (name) + 4);
9117 strcpy (tlsname, name);
9119 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
9120 tlsaddr = copy_rtx (addr);
9121 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
9126 /* Place addr into TOC constant pool. */
9127 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
9129 /* Output the TOC entry and create the MEM referencing the value. */
9130 if (constant_pool_expr_p (XEXP (sym, 0))
9131 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
9133 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
9134 mem = gen_const_mem (Pmode, tocref);
9135 set_mem_alias_set (mem, get_TOC_alias_set ());
9140 /* Use global-dynamic for local-dynamic. */
9141 if (model == TLS_MODEL_GLOBAL_DYNAMIC
9142 || model == TLS_MODEL_LOCAL_DYNAMIC)
9144 /* Create new TOC reference for @m symbol. */
9145 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
9146 tlsname = XALLOCAVEC (char, strlen (name) + 1);
9147 strcpy (tlsname, "*LCM");
9148 strcat (tlsname, name + 3);
9149 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
9150 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
9151 tocref = create_TOC_reference (modaddr, NULL_RTX);
9152 rtx modmem = gen_const_mem (Pmode, tocref);
9153 set_mem_alias_set (modmem, get_TOC_alias_set ());
9155 rtx modreg = gen_reg_rtx (Pmode);
9156 emit_insn (gen_rtx_SET (modreg, modmem));
9158 tmpreg = gen_reg_rtx (Pmode);
9159 emit_insn (gen_rtx_SET (tmpreg, mem));
9161 dest = gen_reg_rtx (Pmode);
9163 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
9165 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
9168 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9169 else if (TARGET_32BIT)
9171 tlsreg = gen_reg_rtx (SImode);
9172 emit_insn (gen_tls_get_tpointer (tlsreg));
9175 tlsreg = gen_rtx_REG (DImode, 13);
9177 /* Load the TOC value into temporary register. */
9178 tmpreg = gen_reg_rtx (Pmode);
9179 emit_insn (gen_rtx_SET (tmpreg, mem));
9180 set_unique_reg_note (get_last_insn (), REG_EQUAL,
9181 gen_rtx_MINUS (Pmode, addr, tlsreg));
9183 /* Add TOC symbol value to TLS pointer. */
9184 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
9189 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9190 this (thread-local) address. */
9193 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
9198 return rs6000_legitimize_tls_address_aix (addr, model);
9200 dest = gen_reg_rtx (Pmode);
9201 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
9207 tlsreg = gen_rtx_REG (Pmode, 13);
9208 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
9212 tlsreg = gen_rtx_REG (Pmode, 2);
9213 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
9217 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
9221 tmp = gen_reg_rtx (Pmode);
9224 tlsreg = gen_rtx_REG (Pmode, 13);
9225 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
9229 tlsreg = gen_rtx_REG (Pmode, 2);
9230 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
9234 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
9236 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
9241 rtx r3, got, tga, tmp1, tmp2, call_insn;
9243 /* We currently use relocations like @got@tlsgd for tls, which
9244 means the linker will handle allocation of tls entries, placing
9245 them in the .got section. So use a pointer to the .got section,
9246 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9247 or to secondary GOT sections used by 32-bit -fPIC. */
9249 got = gen_rtx_REG (Pmode, 2);
9253 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9256 rtx gsym = rs6000_got_sym ();
9257 got = gen_reg_rtx (Pmode);
9259 rs6000_emit_move (got, gsym, Pmode);
9264 tmp1 = gen_reg_rtx (Pmode);
9265 tmp2 = gen_reg_rtx (Pmode);
9266 mem = gen_const_mem (Pmode, tmp1);
9267 lab = gen_label_rtx ();
9268 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9269 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9270 if (TARGET_LINK_STACK)
9271 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9272 emit_move_insn (tmp2, mem);
9273 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9274 set_unique_reg_note (last, REG_EQUAL, gsym);
9279 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9281 tga = rs6000_tls_get_addr ();
9282 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9285 r3 = gen_rtx_REG (Pmode, 3);
9286 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9289 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9291 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9293 else if (DEFAULT_ABI == ABI_V4)
9294 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9297 call_insn = last_call_insn ();
9298 PATTERN (call_insn) = insn;
9299 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9300 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9301 pic_offset_table_rtx);
9303 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9305 tga = rs6000_tls_get_addr ();
9306 tmp1 = gen_reg_rtx (Pmode);
9307 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9310 r3 = gen_rtx_REG (Pmode, 3);
9311 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9314 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9316 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9318 else if (DEFAULT_ABI == ABI_V4)
9319 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9322 call_insn = last_call_insn ();
9323 PATTERN (call_insn) = insn;
9324 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9325 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9326 pic_offset_table_rtx);
9328 if (rs6000_tls_size == 16)
9331 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9333 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9335 else if (rs6000_tls_size == 32)
9337 tmp2 = gen_reg_rtx (Pmode);
9339 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9341 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9344 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9346 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9350 tmp2 = gen_reg_rtx (Pmode);
9352 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9354 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9356 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9362 /* IE, or 64-bit offset LE. */
9363 tmp2 = gen_reg_rtx (Pmode);
9365 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9367 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9370 insn = gen_tls_tls_64 (dest, tmp2, addr);
9372 insn = gen_tls_tls_32 (dest, tmp2, addr);
9380 /* Only create the global variable for the stack protect guard if we are using
9381 the global flavor of that guard. */
9383 rs6000_init_stack_protect_guard (void)
9385 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9386 return default_stack_protect_guard ();
9391 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9394 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9396 if (GET_CODE (x) == HIGH
9397 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9400 /* A TLS symbol in the TOC cannot contain a sum. */
9401 if (GET_CODE (x) == CONST
9402 && GET_CODE (XEXP (x, 0)) == PLUS
9403 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9404 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9407 /* Do not place an ELF TLS symbol in the constant pool. */
9408 return TARGET_ELF && tls_referenced_p (x);
9411 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9412 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9413 can be addressed relative to the toc pointer. */
9416 use_toc_relative_ref (rtx sym, machine_mode mode)
9418 return ((constant_pool_expr_p (sym)
9419 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9420 get_pool_mode (sym)))
9421 || (TARGET_CMODEL == CMODEL_MEDIUM
9422 && SYMBOL_REF_LOCAL_P (sym)
9423 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9426 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9427 replace the input X, or the original X if no replacement is called for.
9428 The output parameter *WIN is 1 if the calling macro should goto WIN,
9431 For RS/6000, we wish to handle large displacements off a base
9432 register by splitting the addend across an addiu/addis and the mem insn.
9433 This cuts number of extra insns needed from 3 to 1.
9435 On Darwin, we use this to generate code for floating point constants.
9436 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9437 The Darwin code is inside #if TARGET_MACHO because only then are the
9438 machopic_* functions defined. */
9440 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9441 int opnum, int type,
9442 int ind_levels ATTRIBUTE_UNUSED, int *win)
9444 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9445 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9447 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9448 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9451 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9452 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9453 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9454 && TARGET_P9_VECTOR)
9455 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9456 && TARGET_P9_VECTOR)))
9457 reg_offset_p = false;
9459 /* We must recognize output that we have already generated ourselves. */
9460 if (GET_CODE (x) == PLUS
9461 && GET_CODE (XEXP (x, 0)) == PLUS
9462 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9463 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9464 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9466 if (TARGET_DEBUG_ADDR)
9468 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9471 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9472 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9473 opnum, (enum reload_type) type);
9478 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9479 if (GET_CODE (x) == LO_SUM
9480 && GET_CODE (XEXP (x, 0)) == HIGH)
9482 if (TARGET_DEBUG_ADDR)
9484 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9487 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9488 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9489 opnum, (enum reload_type) type);
9495 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9496 && GET_CODE (x) == LO_SUM
9497 && GET_CODE (XEXP (x, 0)) == PLUS
9498 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9499 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9500 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9501 && machopic_operand_p (XEXP (x, 1)))
9503 /* Result of previous invocation of this function on Darwin
9504 floating point constant. */
9505 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9506 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9507 opnum, (enum reload_type) type);
9513 if (TARGET_CMODEL != CMODEL_SMALL
9516 && small_toc_ref (x, VOIDmode))
9518 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9519 x = gen_rtx_LO_SUM (Pmode, hi, x);
9520 if (TARGET_DEBUG_ADDR)
9522 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9525 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9526 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9527 opnum, (enum reload_type) type);
9532 if (GET_CODE (x) == PLUS
9533 && REG_P (XEXP (x, 0))
9534 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9535 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9536 && CONST_INT_P (XEXP (x, 1))
9538 && !PAIRED_VECTOR_MODE (mode)
9539 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9541 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9542 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9544 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9546 /* Check for 32-bit overflow or quad addresses with one of the
9547 four least significant bits set. */
9548 if (high + low != val
9549 || (quad_offset_p && (low & 0xf)))
9555 /* Reload the high part into a base reg; leave the low part
9556 in the mem directly. */
9558 x = gen_rtx_PLUS (GET_MODE (x),
9559 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9563 if (TARGET_DEBUG_ADDR)
9565 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9568 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9569 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9570 opnum, (enum reload_type) type);
9575 if (GET_CODE (x) == SYMBOL_REF
9578 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9579 && !PAIRED_VECTOR_MODE (mode)
9581 && DEFAULT_ABI == ABI_DARWIN
9582 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9583 && machopic_symbol_defined_p (x)
9585 && DEFAULT_ABI == ABI_V4
9588 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9589 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9591 ??? Assume floating point reg based on mode? This assumption is
9592 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9593 where reload ends up doing a DFmode load of a constant from
9594 mem using two gprs. Unfortunately, at this point reload
9595 hasn't yet selected regs so poking around in reload data
9596 won't help and even if we could figure out the regs reliably,
9597 we'd still want to allow this transformation when the mem is
9598 naturally aligned. Since we say the address is good here, we
9599 can't disable offsets from LO_SUMs in mem_operand_gpr.
9600 FIXME: Allow offset from lo_sum for other modes too, when
9601 mem is sufficiently aligned.
9603 Also disallow this if the type can go in VMX/Altivec registers, since
9604 those registers do not have d-form (reg+offset) address modes. */
9605 && !reg_addr[mode].scalar_in_vmx_p
9610 && (mode != TImode || !TARGET_VSX)
9612 && (mode != DImode || TARGET_POWERPC64)
9613 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9614 || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
9619 rtx offset = machopic_gen_offset (x);
9620 x = gen_rtx_LO_SUM (GET_MODE (x),
9621 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9622 gen_rtx_HIGH (Pmode, offset)), offset);
9626 x = gen_rtx_LO_SUM (GET_MODE (x),
9627 gen_rtx_HIGH (Pmode, x), x);
9629 if (TARGET_DEBUG_ADDR)
9631 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9634 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9635 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9636 opnum, (enum reload_type) type);
9641 /* Reload an offset address wrapped by an AND that represents the
9642 masking of the lower bits. Strip the outer AND and let reload
9643 convert the offset address into an indirect address. For VSX,
9644 force reload to create the address with an AND in a separate
9645 register, because we can't guarantee an altivec register will
9647 if (VECTOR_MEM_ALTIVEC_P (mode)
9648 && GET_CODE (x) == AND
9649 && GET_CODE (XEXP (x, 0)) == PLUS
9650 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9651 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9652 && GET_CODE (XEXP (x, 1)) == CONST_INT
9653 && INTVAL (XEXP (x, 1)) == -16)
9663 && GET_CODE (x) == SYMBOL_REF
9664 && use_toc_relative_ref (x, mode))
9666 x = create_TOC_reference (x, NULL_RTX);
9667 if (TARGET_CMODEL != CMODEL_SMALL)
9669 if (TARGET_DEBUG_ADDR)
9671 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9674 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9675 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9676 opnum, (enum reload_type) type);
9685 /* Debug version of rs6000_legitimize_reload_address. */
9687 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9688 int opnum, int type,
9689 int ind_levels, int *win)
9691 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9694 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9695 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9696 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9700 fprintf (stderr, "Same address returned\n");
9702 fprintf (stderr, "NULL returned\n");
9705 fprintf (stderr, "New address:\n");
9712 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9713 that is a valid memory address for an instruction.
9714 The MODE argument is the machine mode for the MEM expression
9715 that wants to use this address.
9717 On the RS/6000, there are four valid address: a SYMBOL_REF that
9718 refers to a constant pool entry of an address (or the sum of it
9719 plus a constant), a short (16-bit signed) constant plus a register,
9720 the sum of two registers, or a register indirect, possibly with an
9721 auto-increment. For DFmode, DDmode and DImode with a constant plus
9722 register, we must ensure that both words are addressable or PowerPC64
9723 with offset word aligned.
9725 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9726 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9727 because adjacent memory cells are accessed by adding word-sized offsets
9728 during assembly output. */
9730 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9732 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9733 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9735 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9736 if (VECTOR_MEM_ALTIVEC_P (mode)
9737 && GET_CODE (x) == AND
9738 && GET_CODE (XEXP (x, 1)) == CONST_INT
9739 && INTVAL (XEXP (x, 1)) == -16)
9742 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9744 if (legitimate_indirect_address_p (x, reg_ok_strict))
9747 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9748 && mode_supports_pre_incdec_p (mode)
9749 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9751 /* Handle restricted vector d-form offsets in ISA 3.0. */
9754 if (quad_address_p (x, mode, reg_ok_strict))
9757 else if (virtual_stack_registers_memory_p (x))
9760 else if (reg_offset_p)
9762 if (legitimate_small_data_p (mode, x))
9764 if (legitimate_constant_pool_address_p (x, mode,
9765 reg_ok_strict || lra_in_progress))
9767 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9768 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9772 /* For TImode, if we have TImode in VSX registers, only allow register
9773 indirect addresses. This will allow the values to go in either GPRs
9774 or VSX registers without reloading. The vector types would tend to
9775 go into VSX registers, so we allow REG+REG, while TImode seems
9776 somewhat split, in that some uses are GPR based, and some VSX based. */
9777 /* FIXME: We could loosen this by changing the following to
9778 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9779 but currently we cannot allow REG+REG addressing for TImode. See
9780 PR72827 for complete details on how this ends up hoodwinking DSE. */
9781 if (mode == TImode && TARGET_VSX)
9783 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9786 && GET_CODE (x) == PLUS
9787 && GET_CODE (XEXP (x, 0)) == REG
9788 && (XEXP (x, 0) == virtual_stack_vars_rtx
9789 || XEXP (x, 0) == arg_pointer_rtx)
9790 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9792 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9794 if (!FLOAT128_2REG_P (mode)
9795 && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9797 || (mode != DFmode && mode != DDmode))
9798 && (TARGET_POWERPC64 || mode != DImode)
9799 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9801 && !avoiding_indexed_address_p (mode)
9802 && legitimate_indexed_address_p (x, reg_ok_strict))
9804 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9805 && mode_supports_pre_modify_p (mode)
9806 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9807 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9808 reg_ok_strict, false)
9809 || (!avoiding_indexed_address_p (mode)
9810 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9811 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9813 if (reg_offset_p && !quad_offset_p
9814 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9819 /* Debug version of rs6000_legitimate_address_p. */
9821 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9824 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9826 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9827 "strict = %d, reload = %s, code = %s\n",
9828 ret ? "true" : "false",
9829 GET_MODE_NAME (mode),
9831 (reload_completed ? "after" : "before"),
9832 GET_RTX_NAME (GET_CODE (x)));
9838 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9841 rs6000_mode_dependent_address_p (const_rtx addr,
9842 addr_space_t as ATTRIBUTE_UNUSED)
9844 return rs6000_mode_dependent_address_ptr (addr);
9847 /* Go to LABEL if ADDR (a legitimate address expression)
9848 has an effect that depends on the machine mode it is used for.
9850 On the RS/6000 this is true of all integral offsets (since AltiVec
9851 and VSX modes don't allow them) or is a pre-increment or decrement.
9853 ??? Except that due to conceptual problems in offsettable_address_p
9854 we can't really report the problems of integral offsets. So leave
9855 this assuming that the adjustable offset must be valid for the
9856 sub-words of a TFmode operand, which is what we had before. */
9859 rs6000_mode_dependent_address (const_rtx addr)
9861 switch (GET_CODE (addr))
9864 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9865 is considered a legitimate address before reload, so there
9866 are no offset restrictions in that case. Note that this
9867 condition is safe in strict mode because any address involving
9868 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9869 been rejected as illegitimate. */
9870 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9871 && XEXP (addr, 0) != arg_pointer_rtx
9872 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9874 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9875 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9880 /* Anything in the constant pool is sufficiently aligned that
9881 all bytes have the same high part address. */
9882 return !legitimate_constant_pool_address_p (addr, QImode, false);
9884 /* Auto-increment cases are now treated generically in recog.c. */
9886 return TARGET_UPDATE;
9888 /* AND is only allowed in Altivec loads. */
9899 /* Debug version of rs6000_mode_dependent_address. */
9901 rs6000_debug_mode_dependent_address (const_rtx addr)
9903 bool ret = rs6000_mode_dependent_address (addr);
9905 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9906 ret ? "true" : "false");
9912 /* Implement FIND_BASE_TERM. */
9915 rs6000_find_base_term (rtx op)
9920 if (GET_CODE (base) == CONST)
9921 base = XEXP (base, 0);
9922 if (GET_CODE (base) == PLUS)
9923 base = XEXP (base, 0);
9924 if (GET_CODE (base) == UNSPEC)
9925 switch (XINT (base, 1))
9928 case UNSPEC_MACHOPIC_OFFSET:
9929 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9930 for aliasing purposes. */
9931 return XVECEXP (base, 0, 0);
9937 /* More elaborate version of recog's offsettable_memref_p predicate
9938 that works around the ??? note of rs6000_mode_dependent_address.
9939 In particular it accepts
9941 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9943 in 32-bit mode, that the recog predicate rejects. */
9946 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
9953 /* First mimic offsettable_memref_p. */
9954 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
9957 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9958 the latter predicate knows nothing about the mode of the memory
9959 reference and, therefore, assumes that it is the largest supported
9960 mode (TFmode). As a consequence, legitimate offsettable memory
9961 references are rejected. rs6000_legitimate_offset_address_p contains
9962 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9963 at least with a little bit of help here given that we know the
9964 actual registers used. */
9965 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9966 || GET_MODE_SIZE (reg_mode) == 4);
9967 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9971 /* Determine the reassociation width to be used in reassociate_bb.
9972 This takes into account how many parallel operations we
9973 can actually do of a given type, and also the latency.
9977 vect add/sub/mul 2/cycle
9978 fp add/sub/mul 2/cycle
9983 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9986 switch (rs6000_tune)
9988 case PROCESSOR_POWER8:
9989 case PROCESSOR_POWER9:
9990 if (DECIMAL_FLOAT_MODE_P (mode))
9992 if (VECTOR_MODE_P (mode))
9994 if (INTEGRAL_MODE_P (mode))
9995 return opc == MULT_EXPR ? 4 : 6;
9996 if (FLOAT_MODE_P (mode))
10005 /* Change register usage conditional on target flags. */
10007 rs6000_conditional_register_usage (void)
10011 if (TARGET_DEBUG_TARGET)
10012 fprintf (stderr, "rs6000_conditional_register_usage called\n");
10014 /* Set MQ register fixed (already call_used) so that it will not be
10016 fixed_regs[64] = 1;
10018 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10020 fixed_regs[13] = call_used_regs[13]
10021 = call_really_used_regs[13] = 1;
10023 /* Conditionally disable FPRs. */
10024 if (TARGET_SOFT_FLOAT)
10025 for (i = 32; i < 64; i++)
10026 fixed_regs[i] = call_used_regs[i]
10027 = call_really_used_regs[i] = 1;
10029 /* The TOC register is not killed across calls in a way that is
10030 visible to the compiler. */
10031 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10032 call_really_used_regs[2] = 0;
10034 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
10035 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10037 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10038 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10039 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10040 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10042 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
10043 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10044 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10045 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10047 if (TARGET_TOC && TARGET_MINIMAL_TOC)
10048 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10049 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10051 if (!TARGET_ALTIVEC && !TARGET_VSX)
10053 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10054 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10055 call_really_used_regs[VRSAVE_REGNO] = 1;
10058 if (TARGET_ALTIVEC || TARGET_VSX)
10059 global_regs[VSCR_REGNO] = 1;
10061 if (TARGET_ALTIVEC_ABI)
10063 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
10064 call_used_regs[i] = call_really_used_regs[i] = 1;
10066 /* AIX reserves VR20:31 in non-extended ABI mode. */
10068 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
10069 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10074 /* Output insns to set DEST equal to the constant SOURCE as a series of
10075 lis, ori and shl instructions and return TRUE. */
10078 rs6000_emit_set_const (rtx dest, rtx source)
10080 machine_mode mode = GET_MODE (dest);
10085 gcc_checking_assert (CONST_INT_P (source));
10086 c = INTVAL (source);
10091 emit_insn (gen_rtx_SET (dest, source));
10095 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
10097 emit_insn (gen_rtx_SET (copy_rtx (temp),
10098 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
10099 emit_insn (gen_rtx_SET (dest,
10100 gen_rtx_IOR (SImode, copy_rtx (temp),
10101 GEN_INT (c & 0xffff))));
10105 if (!TARGET_POWERPC64)
10109 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
10111 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
10113 emit_move_insn (hi, GEN_INT (c >> 32));
10114 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
10115 emit_move_insn (lo, GEN_INT (c));
10118 rs6000_emit_set_long_const (dest, c);
10122 gcc_unreachable ();
10125 insn = get_last_insn ();
10126 set = single_set (insn);
10127 if (! CONSTANT_P (SET_SRC (set)))
10128 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
10133 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10134 Output insns to set DEST equal to the constant C as a series of
10135 lis, ori and shl instructions. */
10138 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
10141 HOST_WIDE_INT ud1, ud2, ud3, ud4;
10151 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
10152 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
10153 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
10155 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
10156 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
10158 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10160 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10161 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10163 emit_move_insn (dest,
10164 gen_rtx_IOR (DImode, copy_rtx (temp),
10167 else if (ud3 == 0 && ud4 == 0)
10169 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10171 gcc_assert (ud2 & 0x8000);
10172 emit_move_insn (copy_rtx (temp),
10173 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10175 emit_move_insn (copy_rtx (temp),
10176 gen_rtx_IOR (DImode, copy_rtx (temp),
10178 emit_move_insn (dest,
10179 gen_rtx_ZERO_EXTEND (DImode,
10180 gen_lowpart (SImode,
10181 copy_rtx (temp))));
10183 else if ((ud4 == 0xffff && (ud3 & 0x8000))
10184 || (ud4 == 0 && ! (ud3 & 0x8000)))
10186 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10188 emit_move_insn (copy_rtx (temp),
10189 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
10191 emit_move_insn (copy_rtx (temp),
10192 gen_rtx_IOR (DImode, copy_rtx (temp),
10194 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10195 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10198 emit_move_insn (dest,
10199 gen_rtx_IOR (DImode, copy_rtx (temp),
10204 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10206 emit_move_insn (copy_rtx (temp),
10207 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
10209 emit_move_insn (copy_rtx (temp),
10210 gen_rtx_IOR (DImode, copy_rtx (temp),
10213 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
10214 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10217 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10218 gen_rtx_IOR (DImode, copy_rtx (temp),
10219 GEN_INT (ud2 << 16)));
10221 emit_move_insn (dest,
10222 gen_rtx_IOR (DImode, copy_rtx (temp),
10227 /* Helper for the following. Get rid of [r+r] memory refs
10228 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10231 rs6000_eliminate_indexed_memrefs (rtx operands[2])
10233 if (GET_CODE (operands[0]) == MEM
10234 && GET_CODE (XEXP (operands[0], 0)) != REG
10235 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
10236 GET_MODE (operands[0]), false))
10238 = replace_equiv_address (operands[0],
10239 copy_addr_to_reg (XEXP (operands[0], 0)));
10241 if (GET_CODE (operands[1]) == MEM
10242 && GET_CODE (XEXP (operands[1], 0)) != REG
10243 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10244 GET_MODE (operands[1]), false))
10246 = replace_equiv_address (operands[1],
10247 copy_addr_to_reg (XEXP (operands[1], 0)));
10250 /* Generate a vector of constants to permute MODE for a little-endian
10251 storage operation by swapping the two halves of a vector. */
10253 rs6000_const_vec (machine_mode mode)
10281 v = rtvec_alloc (subparts);
10283 for (i = 0; i < subparts / 2; ++i)
10284 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10285 for (i = subparts / 2; i < subparts; ++i)
10286 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10291 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10292 store operation. */
10294 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10296 /* Scalar permutations are easier to express in integer modes rather than
10297 floating-point modes, so cast them here. We use V1TImode instead
10298 of TImode to ensure that the values don't go through GPRs. */
10299 if (FLOAT128_VECTOR_P (mode))
10301 dest = gen_lowpart (V1TImode, dest);
10302 source = gen_lowpart (V1TImode, source);
10306 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10308 if (mode == TImode || mode == V1TImode)
10309 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10313 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10314 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10318 /* Emit a little-endian load from vector memory location SOURCE to VSX
10319 register DEST in mode MODE. The load is done with two permuting
10320 insn's that represent an lxvd2x and xxpermdi. */
10322 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10324 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10326 if (mode == TImode || mode == V1TImode)
10329 dest = gen_lowpart (V2DImode, dest);
10330 source = adjust_address (source, V2DImode, 0);
10333 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10334 rs6000_emit_le_vsx_permute (tmp, source, mode);
10335 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10338 /* Emit a little-endian store to vector memory location DEST from VSX
10339 register SOURCE in mode MODE. The store is done with two permuting
10340 insn's that represent an xxpermdi and an stxvd2x. */
10342 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10344 /* This should never be called during or after LRA, because it does
10345 not re-permute the source register. It is intended only for use
10347 gcc_assert (!lra_in_progress && !reload_completed);
10349 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10351 if (mode == TImode || mode == V1TImode)
10354 dest = adjust_address (dest, V2DImode, 0);
10355 source = gen_lowpart (V2DImode, source);
10358 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10359 rs6000_emit_le_vsx_permute (tmp, source, mode);
10360 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10363 /* Emit a sequence representing a little-endian VSX load or store,
10364 moving data from SOURCE to DEST in mode MODE. This is done
10365 separately from rs6000_emit_move to ensure it is called only
10366 during expand. LE VSX loads and stores introduced later are
10367 handled with a split. The expand-time RTL generation allows
10368 us to optimize away redundant pairs of register-permutes. */
10370 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10372 gcc_assert (!BYTES_BIG_ENDIAN
10373 && VECTOR_MEM_VSX_P (mode)
10374 && !TARGET_P9_VECTOR
10375 && !gpr_or_gpr_p (dest, source)
10376 && (MEM_P (source) ^ MEM_P (dest)));
10378 if (MEM_P (source))
10380 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10381 rs6000_emit_le_vsx_load (dest, source, mode);
10385 if (!REG_P (source))
10386 source = force_reg (mode, source);
10387 rs6000_emit_le_vsx_store (dest, source, mode);
10391 /* Return whether a SFmode or SImode move can be done without converting one
10392 mode to another. This arrises when we have:
10394 (SUBREG:SF (REG:SI ...))
10395 (SUBREG:SI (REG:SF ...))
10397 and one of the values is in a floating point/vector register, where SFmode
10398 scalars are stored in DFmode format. */
10401 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10403 if (TARGET_ALLOW_SF_SUBREG)
10406 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10409 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10412 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10413 if (SUBREG_P (dest))
10415 rtx dest_subreg = SUBREG_REG (dest);
10416 rtx src_subreg = SUBREG_REG (src);
10417 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10424 /* Helper function to change moves with:
10426 (SUBREG:SF (REG:SI)) and
10427 (SUBREG:SI (REG:SF))
10429 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10430 values are stored as DFmode values in the VSX registers. We need to convert
10431 the bits before we can use a direct move or operate on the bits in the
10432 vector register as an integer type.
10434 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10437 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10439 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10440 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10441 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10443 rtx inner_source = SUBREG_REG (source);
10444 machine_mode inner_mode = GET_MODE (inner_source);
10446 if (mode == SImode && inner_mode == SFmode)
10448 emit_insn (gen_movsi_from_sf (dest, inner_source));
10452 if (mode == SFmode && inner_mode == SImode)
10454 emit_insn (gen_movsf_from_si (dest, inner_source));
10462 /* Emit a move from SOURCE to DEST in mode MODE. */
10464 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10467 operands[0] = dest;
10468 operands[1] = source;
10470 if (TARGET_DEBUG_ADDR)
10473 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10474 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10475 GET_MODE_NAME (mode),
10478 can_create_pseudo_p ());
10480 fprintf (stderr, "source:\n");
10481 debug_rtx (source);
10484 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10485 if (CONST_WIDE_INT_P (operands[1])
10486 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10488 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10489 gcc_unreachable ();
10492 /* See if we need to special case SImode/SFmode SUBREG moves. */
10493 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10494 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10497 /* Check if GCC is setting up a block move that will end up using FP
10498 registers as temporaries. We must make sure this is acceptable. */
10499 if (GET_CODE (operands[0]) == MEM
10500 && GET_CODE (operands[1]) == MEM
10502 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10503 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10504 && ! (rs6000_slow_unaligned_access (SImode,
10505 (MEM_ALIGN (operands[0]) > 32
10506 ? 32 : MEM_ALIGN (operands[0])))
10507 || rs6000_slow_unaligned_access (SImode,
10508 (MEM_ALIGN (operands[1]) > 32
10509 ? 32 : MEM_ALIGN (operands[1]))))
10510 && ! MEM_VOLATILE_P (operands [0])
10511 && ! MEM_VOLATILE_P (operands [1]))
10513 emit_move_insn (adjust_address (operands[0], SImode, 0),
10514 adjust_address (operands[1], SImode, 0));
10515 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10516 adjust_address (copy_rtx (operands[1]), SImode, 4));
10520 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10521 && !gpc_reg_operand (operands[1], mode))
10522 operands[1] = force_reg (mode, operands[1]);
10524 /* Recognize the case where operand[1] is a reference to thread-local
10525 data and load its address to a register. */
10526 if (tls_referenced_p (operands[1]))
10528 enum tls_model model;
10529 rtx tmp = operands[1];
10532 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10534 addend = XEXP (XEXP (tmp, 0), 1);
10535 tmp = XEXP (XEXP (tmp, 0), 0);
10538 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10539 model = SYMBOL_REF_TLS_MODEL (tmp);
10540 gcc_assert (model != 0);
10542 tmp = rs6000_legitimize_tls_address (tmp, model);
10545 tmp = gen_rtx_PLUS (mode, tmp, addend);
10546 tmp = force_operand (tmp, operands[0]);
10551 /* 128-bit constant floating-point values on Darwin should really be loaded
10552 as two parts. However, this premature splitting is a problem when DFmode
10553 values can go into Altivec registers. */
10554 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10555 && GET_CODE (operands[1]) == CONST_DOUBLE)
10557 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10558 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10560 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10561 GET_MODE_SIZE (DFmode)),
10562 simplify_gen_subreg (DFmode, operands[1], mode,
10563 GET_MODE_SIZE (DFmode)),
10568 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10569 p1:SD) if p1 is not of floating point class and p0 is spilled as
10570 we can have no analogous movsd_store for this. */
10571 if (lra_in_progress && mode == DDmode
10572 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10573 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10574 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10575 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10578 int regno = REGNO (SUBREG_REG (operands[1]));
10580 if (regno >= FIRST_PSEUDO_REGISTER)
10582 cl = reg_preferred_class (regno);
10583 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10585 if (regno >= 0 && ! FP_REGNO_P (regno))
10588 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10589 operands[1] = SUBREG_REG (operands[1]);
10592 if (lra_in_progress
10594 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10595 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10596 && (REG_P (operands[1])
10597 || (GET_CODE (operands[1]) == SUBREG
10598 && REG_P (SUBREG_REG (operands[1])))))
10600 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10601 ? SUBREG_REG (operands[1]) : operands[1]);
10604 if (regno >= FIRST_PSEUDO_REGISTER)
10606 cl = reg_preferred_class (regno);
10607 gcc_assert (cl != NO_REGS);
10608 regno = ira_class_hard_regs[cl][0];
10610 if (FP_REGNO_P (regno))
10612 if (GET_MODE (operands[0]) != DDmode)
10613 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10614 emit_insn (gen_movsd_store (operands[0], operands[1]));
10616 else if (INT_REGNO_P (regno))
10617 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10622 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10623 p:DD)) if p0 is not of floating point class and p1 is spilled as
10624 we can have no analogous movsd_load for this. */
10625 if (lra_in_progress && mode == DDmode
10626 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10627 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10628 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10629 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10632 int regno = REGNO (SUBREG_REG (operands[0]));
10634 if (regno >= FIRST_PSEUDO_REGISTER)
10636 cl = reg_preferred_class (regno);
10637 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10639 if (regno >= 0 && ! FP_REGNO_P (regno))
10642 operands[0] = SUBREG_REG (operands[0]);
10643 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10646 if (lra_in_progress
10648 && (REG_P (operands[0])
10649 || (GET_CODE (operands[0]) == SUBREG
10650 && REG_P (SUBREG_REG (operands[0]))))
10651 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10652 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10654 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10655 ? SUBREG_REG (operands[0]) : operands[0]);
10658 if (regno >= FIRST_PSEUDO_REGISTER)
10660 cl = reg_preferred_class (regno);
10661 gcc_assert (cl != NO_REGS);
10662 regno = ira_class_hard_regs[cl][0];
10664 if (FP_REGNO_P (regno))
10666 if (GET_MODE (operands[1]) != DDmode)
10667 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10668 emit_insn (gen_movsd_load (operands[0], operands[1]));
10670 else if (INT_REGNO_P (regno))
10671 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10677 /* FIXME: In the long term, this switch statement should go away
10678 and be replaced by a sequence of tests based on things like
10684 if (CONSTANT_P (operands[1])
10685 && GET_CODE (operands[1]) != CONST_INT)
10686 operands[1] = force_const_mem (mode, operands[1]);
10693 if (FLOAT128_2REG_P (mode))
10694 rs6000_eliminate_indexed_memrefs (operands);
10701 if (CONSTANT_P (operands[1])
10702 && ! easy_fp_constant (operands[1], mode))
10703 operands[1] = force_const_mem (mode, operands[1]);
10715 if (CONSTANT_P (operands[1])
10716 && !easy_vector_constant (operands[1], mode))
10717 operands[1] = force_const_mem (mode, operands[1]);
10722 /* Use default pattern for address of ELF small data */
10725 && DEFAULT_ABI == ABI_V4
10726 && (GET_CODE (operands[1]) == SYMBOL_REF
10727 || GET_CODE (operands[1]) == CONST)
10728 && small_data_operand (operands[1], mode))
10730 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10734 if (DEFAULT_ABI == ABI_V4
10735 && mode == Pmode && mode == SImode
10736 && flag_pic == 1 && got_operand (operands[1], mode))
10738 emit_insn (gen_movsi_got (operands[0], operands[1]));
10742 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10746 && CONSTANT_P (operands[1])
10747 && GET_CODE (operands[1]) != HIGH
10748 && GET_CODE (operands[1]) != CONST_INT)
10750 rtx target = (!can_create_pseudo_p ()
10752 : gen_reg_rtx (mode));
10754 /* If this is a function address on -mcall-aixdesc,
10755 convert it to the address of the descriptor. */
10756 if (DEFAULT_ABI == ABI_AIX
10757 && GET_CODE (operands[1]) == SYMBOL_REF
10758 && XSTR (operands[1], 0)[0] == '.')
10760 const char *name = XSTR (operands[1], 0);
10762 while (*name == '.')
10764 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10765 CONSTANT_POOL_ADDRESS_P (new_ref)
10766 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10767 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10768 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10769 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10770 operands[1] = new_ref;
10773 if (DEFAULT_ABI == ABI_DARWIN)
10776 if (MACHO_DYNAMIC_NO_PIC_P)
10778 /* Take care of any required data indirection. */
10779 operands[1] = rs6000_machopic_legitimize_pic_address (
10780 operands[1], mode, operands[0]);
10781 if (operands[0] != operands[1])
10782 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10786 emit_insn (gen_macho_high (target, operands[1]));
10787 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10791 emit_insn (gen_elf_high (target, operands[1]));
10792 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10796 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10797 and we have put it in the TOC, we just need to make a TOC-relative
10798 reference to it. */
10800 && GET_CODE (operands[1]) == SYMBOL_REF
10801 && use_toc_relative_ref (operands[1], mode))
10802 operands[1] = create_TOC_reference (operands[1], operands[0]);
10803 else if (mode == Pmode
10804 && CONSTANT_P (operands[1])
10805 && GET_CODE (operands[1]) != HIGH
10806 && ((GET_CODE (operands[1]) != CONST_INT
10807 && ! easy_fp_constant (operands[1], mode))
10808 || (GET_CODE (operands[1]) == CONST_INT
10809 && (num_insns_constant (operands[1], mode)
10810 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10811 || (GET_CODE (operands[0]) == REG
10812 && FP_REGNO_P (REGNO (operands[0]))))
10813 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10814 && (TARGET_CMODEL == CMODEL_SMALL
10815 || can_create_pseudo_p ()
10816 || (REG_P (operands[0])
10817 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10821 /* Darwin uses a special PIC legitimizer. */
10822 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10825 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10827 if (operands[0] != operands[1])
10828 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10833 /* If we are to limit the number of things we put in the TOC and
10834 this is a symbol plus a constant we can add in one insn,
10835 just put the symbol in the TOC and add the constant. */
10836 if (GET_CODE (operands[1]) == CONST
10837 && TARGET_NO_SUM_IN_TOC
10838 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10839 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10840 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10841 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10842 && ! side_effects_p (operands[0]))
10845 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10846 rtx other = XEXP (XEXP (operands[1], 0), 1);
10848 sym = force_reg (mode, sym);
10849 emit_insn (gen_add3_insn (operands[0], sym, other));
10853 operands[1] = force_const_mem (mode, operands[1]);
10856 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10857 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10859 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10861 operands[1] = gen_const_mem (mode, tocref);
10862 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10868 if (!VECTOR_MEM_VSX_P (TImode))
10869 rs6000_eliminate_indexed_memrefs (operands);
10873 rs6000_eliminate_indexed_memrefs (operands);
10877 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10880 /* Above, we may have called force_const_mem which may have returned
10881 an invalid address. If we can, fix this up; otherwise, reload will
10882 have to deal with it. */
10883 if (GET_CODE (operands[1]) == MEM)
10884 operands[1] = validize_mem (operands[1]);
10886 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10889 /* Nonzero if we can use a floating-point register to pass this arg. */
10890 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10891 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10892 && (CUM)->fregno <= FP_ARG_MAX_REG \
10893 && TARGET_HARD_FLOAT)
10895 /* Nonzero if we can use an AltiVec register to pass this arg. */
10896 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10897 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10898 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10899 && TARGET_ALTIVEC_ABI \
10902 /* Walk down the type tree of TYPE counting consecutive base elements.
10903 If *MODEP is VOIDmode, then set it to the first valid floating point
10904 or vector type. If a non-floating point or vector type is found, or
10905 if a floating point or vector type that doesn't match a non-VOIDmode
10906 *MODEP is found, then return -1, otherwise return the count in the
10910 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10913 HOST_WIDE_INT size;
10915 switch (TREE_CODE (type))
10918 mode = TYPE_MODE (type);
10919 if (!SCALAR_FLOAT_MODE_P (mode))
10922 if (*modep == VOIDmode)
10925 if (*modep == mode)
10931 mode = TYPE_MODE (TREE_TYPE (type));
10932 if (!SCALAR_FLOAT_MODE_P (mode))
10935 if (*modep == VOIDmode)
10938 if (*modep == mode)
10944 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10947 /* Use V4SImode as representative of all 128-bit vector types. */
10948 size = int_size_in_bytes (type);
10958 if (*modep == VOIDmode)
10961 /* Vector modes are considered to be opaque: two vectors are
10962 equivalent for the purposes of being homogeneous aggregates
10963 if they are the same size. */
10964 if (*modep == mode)
10972 tree index = TYPE_DOMAIN (type);
10974 /* Can't handle incomplete types nor sizes that are not
10976 if (!COMPLETE_TYPE_P (type)
10977 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10980 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10983 || !TYPE_MAX_VALUE (index)
10984 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10985 || !TYPE_MIN_VALUE (index)
10986 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10990 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10991 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10993 /* There must be no padding. */
10994 if (wi::to_wide (TYPE_SIZE (type))
10995 != count * GET_MODE_BITSIZE (*modep))
11007 /* Can't handle incomplete types nor sizes that are not
11009 if (!COMPLETE_TYPE_P (type)
11010 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11013 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11015 if (TREE_CODE (field) != FIELD_DECL)
11018 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11021 count += sub_count;
11024 /* There must be no padding. */
11025 if (wi::to_wide (TYPE_SIZE (type))
11026 != count * GET_MODE_BITSIZE (*modep))
11033 case QUAL_UNION_TYPE:
11035 /* These aren't very interesting except in a degenerate case. */
11040 /* Can't handle incomplete types nor sizes that are not
11042 if (!COMPLETE_TYPE_P (type)
11043 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11046 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11048 if (TREE_CODE (field) != FIELD_DECL)
11051 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11054 count = count > sub_count ? count : sub_count;
11057 /* There must be no padding. */
11058 if (wi::to_wide (TYPE_SIZE (type))
11059 != count * GET_MODE_BITSIZE (*modep))
11072 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11073 float or vector aggregate that shall be passed in FP/vector registers
11074 according to the ELFv2 ABI, return the homogeneous element mode in
11075 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11077 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11080 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
11081 machine_mode *elt_mode,
11084 /* Note that we do not accept complex types at the top level as
11085 homogeneous aggregates; these types are handled via the
11086 targetm.calls.split_complex_arg mechanism. Complex types
11087 can be elements of homogeneous aggregates, however. */
11088 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
11089 && AGGREGATE_TYPE_P (type))
11091 machine_mode field_mode = VOIDmode;
11092 int field_count = rs6000_aggregate_candidate (type, &field_mode);
11094 if (field_count > 0)
11096 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
11097 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
11099 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11100 up to AGGR_ARG_NUM_REG registers. */
11101 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
11104 *elt_mode = field_mode;
11106 *n_elts = field_count;
11119 /* Return a nonzero value to say to return the function value in
11120 memory, just as large structures are always returned. TYPE will be
11121 the data type of the value, and FNTYPE will be the type of the
11122 function doing the returning, or @code{NULL} for libcalls.
11124 The AIX ABI for the RS/6000 specifies that all structures are
11125 returned in memory. The Darwin ABI does the same.
11127 For the Darwin 64 Bit ABI, a function result can be returned in
11128 registers or in memory, depending on the size of the return data
11129 type. If it is returned in registers, the value occupies the same
11130 registers as it would if it were the first and only function
11131 argument. Otherwise, the function places its result in memory at
11132 the location pointed to by GPR3.
11134 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11135 but a draft put them in memory, and GCC used to implement the draft
11136 instead of the final standard. Therefore, aix_struct_return
11137 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11138 compatibility can change DRAFT_V4_STRUCT_RET to override the
11139 default, and -m switches get the final word. See
11140 rs6000_option_override_internal for more details.
11142 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11143 long double support is enabled. These values are returned in memory.
11145 int_size_in_bytes returns -1 for variable size objects, which go in
11146 memory always. The cast to unsigned makes -1 > 8. */
11149 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
11151 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11153 && rs6000_darwin64_abi
11154 && TREE_CODE (type) == RECORD_TYPE
11155 && int_size_in_bytes (type) > 0)
11157 CUMULATIVE_ARGS valcum;
11161 valcum.fregno = FP_ARG_MIN_REG;
11162 valcum.vregno = ALTIVEC_ARG_MIN_REG;
11163 /* Do a trial code generation as if this were going to be passed
11164 as an argument; if any part goes in memory, we return NULL. */
11165 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
11168 /* Otherwise fall through to more conventional ABI rules. */
11171 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11172 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
11176 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11177 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
11178 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
11181 if (AGGREGATE_TYPE_P (type)
11182 && (aix_struct_return
11183 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
11186 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11187 modes only exist for GCC vector types if -maltivec. */
11188 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
11189 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11192 /* Return synthetic vectors in memory. */
11193 if (TREE_CODE (type) == VECTOR_TYPE
11194 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11196 static bool warned_for_return_big_vectors = false;
11197 if (!warned_for_return_big_vectors)
11199 warning (OPT_Wpsabi, "GCC vector returned by reference: "
11200 "non-standard ABI extension with no compatibility "
11202 warned_for_return_big_vectors = true;
11207 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11208 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11214 /* Specify whether values returned in registers should be at the most
11215 significant end of a register. We want aggregates returned by
11216 value to match the way aggregates are passed to functions. */
11219 rs6000_return_in_msb (const_tree valtype)
11221 return (DEFAULT_ABI == ABI_ELFv2
11222 && BYTES_BIG_ENDIAN
11223 && AGGREGATE_TYPE_P (valtype)
11224 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11228 #ifdef HAVE_AS_GNU_ATTRIBUTE
11229 /* Return TRUE if a call to function FNDECL may be one that
11230 potentially affects the function calling ABI of the object file. */
11233 call_ABI_of_interest (tree fndecl)
11235 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11237 struct cgraph_node *c_node;
11239 /* Libcalls are always interesting. */
11240 if (fndecl == NULL_TREE)
11243 /* Any call to an external function is interesting. */
11244 if (DECL_EXTERNAL (fndecl))
11247 /* Interesting functions that we are emitting in this object file. */
11248 c_node = cgraph_node::get (fndecl);
11249 c_node = c_node->ultimate_alias_target ();
11250 return !c_node->only_called_directly_p ();
11256 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11257 for a call to a function whose data type is FNTYPE.
11258 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11260 For incoming args we set the number of arguments in the prototype large
11261 so we never return a PARALLEL. */
11264 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11265 rtx libname ATTRIBUTE_UNUSED, int incoming,
11266 int libcall, int n_named_args,
11267 tree fndecl ATTRIBUTE_UNUSED,
11268 machine_mode return_mode ATTRIBUTE_UNUSED)
11270 static CUMULATIVE_ARGS zero_cumulative;
11272 *cum = zero_cumulative;
11274 cum->fregno = FP_ARG_MIN_REG;
11275 cum->vregno = ALTIVEC_ARG_MIN_REG;
11276 cum->prototype = (fntype && prototype_p (fntype));
11277 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11278 ? CALL_LIBCALL : CALL_NORMAL);
11279 cum->sysv_gregno = GP_ARG_MIN_REG;
11280 cum->stdarg = stdarg_p (fntype);
11281 cum->libcall = libcall;
11283 cum->nargs_prototype = 0;
11284 if (incoming || cum->prototype)
11285 cum->nargs_prototype = n_named_args;
11287 /* Check for a longcall attribute. */
11288 if ((!fntype && rs6000_default_long_calls)
11290 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11291 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11292 cum->call_cookie |= CALL_LONG;
11294 if (TARGET_DEBUG_ARG)
11296 fprintf (stderr, "\ninit_cumulative_args:");
11299 tree ret_type = TREE_TYPE (fntype);
11300 fprintf (stderr, " ret code = %s,",
11301 get_tree_code_name (TREE_CODE (ret_type)));
11304 if (cum->call_cookie & CALL_LONG)
11305 fprintf (stderr, " longcall,");
11307 fprintf (stderr, " proto = %d, nargs = %d\n",
11308 cum->prototype, cum->nargs_prototype);
11311 #ifdef HAVE_AS_GNU_ATTRIBUTE
11312 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11314 cum->escapes = call_ABI_of_interest (fndecl);
11321 return_type = TREE_TYPE (fntype);
11322 return_mode = TYPE_MODE (return_type);
11325 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11327 if (return_type != NULL)
11329 if (TREE_CODE (return_type) == RECORD_TYPE
11330 && TYPE_TRANSPARENT_AGGR (return_type))
11332 return_type = TREE_TYPE (first_field (return_type));
11333 return_mode = TYPE_MODE (return_type);
11335 if (AGGREGATE_TYPE_P (return_type)
11336 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11338 rs6000_returns_struct = true;
11340 if (SCALAR_FLOAT_MODE_P (return_mode))
11342 rs6000_passes_float = true;
11343 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11344 && (FLOAT128_IBM_P (return_mode)
11345 || FLOAT128_IEEE_P (return_mode)
11346 || (return_type != NULL
11347 && (TYPE_MAIN_VARIANT (return_type)
11348 == long_double_type_node))))
11349 rs6000_passes_long_double = true;
11351 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
11352 || PAIRED_VECTOR_MODE (return_mode))
11353 rs6000_passes_vector = true;
11360 && TARGET_ALTIVEC_ABI
11361 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11363 error ("cannot return value in vector register because"
11364 " altivec instructions are disabled, use %qs"
11365 " to enable them", "-maltivec");
11369 /* The mode the ABI uses for a word. This is not the same as word_mode
11370 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11372 static scalar_int_mode
11373 rs6000_abi_word_mode (void)
11375 return TARGET_32BIT ? SImode : DImode;
11378 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11380 rs6000_offload_options (void)
11383 return xstrdup ("-foffload-abi=lp64");
11385 return xstrdup ("-foffload-abi=ilp32");
11388 /* On rs6000, function arguments are promoted, as are function return
11391 static machine_mode
11392 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11394 int *punsignedp ATTRIBUTE_UNUSED,
11397 PROMOTE_MODE (mode, *punsignedp, type);
11402 /* Return true if TYPE must be passed on the stack and not in registers. */
11405 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11407 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11408 return must_pass_in_stack_var_size (mode, type);
11410 return must_pass_in_stack_var_size_or_pad (mode, type);
11414 is_complex_IBM_long_double (machine_mode mode)
11416 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
11419 /* Whether ABI_V4 passes MODE args to a function in floating point
11423 abi_v4_pass_in_fpr (machine_mode mode)
11425 if (!TARGET_HARD_FLOAT)
11427 if (TARGET_SINGLE_FLOAT && mode == SFmode)
11429 if (TARGET_DOUBLE_FLOAT && mode == DFmode)
11431 /* ABI_V4 passes complex IBM long double in 8 gprs.
11432 Stupid, but we can't change the ABI now. */
11433 if (is_complex_IBM_long_double (mode))
11435 if (FLOAT128_2REG_P (mode))
11437 if (DECIMAL_FLOAT_MODE_P (mode))
11442 /* Implement TARGET_FUNCTION_ARG_PADDING.
11444 For the AIX ABI structs are always stored left shifted in their
11447 static pad_direction
11448 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11450 #ifndef AGGREGATE_PADDING_FIXED
11451 #define AGGREGATE_PADDING_FIXED 0
11453 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11454 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11457 if (!AGGREGATE_PADDING_FIXED)
11459 /* GCC used to pass structures of the same size as integer types as
11460 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11461 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11462 passed padded downward, except that -mstrict-align further
11463 muddied the water in that multi-component structures of 2 and 4
11464 bytes in size were passed padded upward.
11466 The following arranges for best compatibility with previous
11467 versions of gcc, but removes the -mstrict-align dependency. */
11468 if (BYTES_BIG_ENDIAN)
11470 HOST_WIDE_INT size = 0;
11472 if (mode == BLKmode)
11474 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11475 size = int_size_in_bytes (type);
11478 size = GET_MODE_SIZE (mode);
11480 if (size == 1 || size == 2 || size == 4)
11481 return PAD_DOWNWARD;
11486 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11488 if (type != 0 && AGGREGATE_TYPE_P (type))
11492 /* Fall back to the default. */
11493 return default_function_arg_padding (mode, type);
11496 /* If defined, a C expression that gives the alignment boundary, in bits,
11497 of an argument with the specified mode and type. If it is not defined,
11498 PARM_BOUNDARY is used for all arguments.
11500 V.4 wants long longs and doubles to be double word aligned. Just
11501 testing the mode size is a boneheaded way to do this as it means
11502 that other types such as complex int are also double word aligned.
11503 However, we're stuck with this because changing the ABI might break
11504 existing library interfaces.
11506 Quadword align Altivec/VSX vectors.
11507 Quadword align large synthetic vector types. */
11509 static unsigned int
11510 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11512 machine_mode elt_mode;
11515 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11517 if (DEFAULT_ABI == ABI_V4
11518 && (GET_MODE_SIZE (mode) == 8
11519 || (TARGET_HARD_FLOAT
11520 && !is_complex_IBM_long_double (mode)
11521 && FLOAT128_2REG_P (mode))))
11523 else if (FLOAT128_VECTOR_P (mode))
11525 else if (PAIRED_VECTOR_MODE (mode)
11526 || (type && TREE_CODE (type) == VECTOR_TYPE
11527 && int_size_in_bytes (type) >= 8
11528 && int_size_in_bytes (type) < 16))
11530 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11531 || (type && TREE_CODE (type) == VECTOR_TYPE
11532 && int_size_in_bytes (type) >= 16))
11535 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11536 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11537 -mcompat-align-parm is used. */
11538 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11539 || DEFAULT_ABI == ABI_ELFv2)
11540 && type && TYPE_ALIGN (type) > 64)
11542 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11543 or homogeneous float/vector aggregates here. We already handled
11544 vector aggregates above, but still need to check for float here. */
11545 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11546 && !SCALAR_FLOAT_MODE_P (elt_mode));
11548 /* We used to check for BLKmode instead of the above aggregate type
11549 check. Warn when this results in any difference to the ABI. */
11550 if (aggregate_p != (mode == BLKmode))
11552 static bool warned;
11553 if (!warned && warn_psabi)
11556 inform (input_location,
11557 "the ABI of passing aggregates with %d-byte alignment"
11558 " has changed in GCC 5",
11559 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11567 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11568 implement the "aggregate type" check as a BLKmode check here; this
11569 means certain aggregate types are in fact not aligned. */
11570 if (TARGET_MACHO && rs6000_darwin64_abi
11572 && type && TYPE_ALIGN (type) > 64)
11575 return PARM_BOUNDARY;
11578 /* The offset in words to the start of the parameter save area. */
11580 static unsigned int
11581 rs6000_parm_offset (void)
11583 return (DEFAULT_ABI == ABI_V4 ? 2
11584 : DEFAULT_ABI == ABI_ELFv2 ? 4
11588 /* For a function parm of MODE and TYPE, return the starting word in
11589 the parameter area. NWORDS of the parameter area are already used. */
11591 static unsigned int
11592 rs6000_parm_start (machine_mode mode, const_tree type,
11593 unsigned int nwords)
11595 unsigned int align;
11597 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11598 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11601 /* Compute the size (in words) of a function argument. */
11603 static unsigned long
11604 rs6000_arg_size (machine_mode mode, const_tree type)
11606 unsigned long size;
11608 if (mode != BLKmode)
11609 size = GET_MODE_SIZE (mode);
11611 size = int_size_in_bytes (type);
11614 return (size + 3) >> 2;
11616 return (size + 7) >> 3;
11619 /* Use this to flush pending int fields. */
11622 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11623 HOST_WIDE_INT bitpos, int final)
11625 unsigned int startbit, endbit;
11626 int intregs, intoffset;
11628 /* Handle the situations where a float is taking up the first half
11629 of the GPR, and the other half is empty (typically due to
11630 alignment restrictions). We can detect this by a 8-byte-aligned
11631 int field, or by seeing that this is the final flush for this
11632 argument. Count the word and continue on. */
11633 if (cum->floats_in_gpr == 1
11634 && (cum->intoffset % 64 == 0
11635 || (cum->intoffset == -1 && final)))
11638 cum->floats_in_gpr = 0;
11641 if (cum->intoffset == -1)
11644 intoffset = cum->intoffset;
11645 cum->intoffset = -1;
11646 cum->floats_in_gpr = 0;
11648 if (intoffset % BITS_PER_WORD != 0)
11650 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11651 if (!int_mode_for_size (bits, 0).exists ())
11653 /* We couldn't find an appropriate mode, which happens,
11654 e.g., in packed structs when there are 3 bytes to load.
11655 Back intoffset back to the beginning of the word in this
11657 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11661 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11662 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11663 intregs = (endbit - startbit) / BITS_PER_WORD;
11664 cum->words += intregs;
11665 /* words should be unsigned. */
11666 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11668 int pad = (endbit/BITS_PER_WORD) - cum->words;
11673 /* The darwin64 ABI calls for us to recurse down through structs,
11674 looking for elements passed in registers. Unfortunately, we have
11675 to track int register count here also because of misalignments
11676 in powerpc alignment mode. */
11679 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11681 HOST_WIDE_INT startbitpos)
11685 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11686 if (TREE_CODE (f) == FIELD_DECL)
11688 HOST_WIDE_INT bitpos = startbitpos;
11689 tree ftype = TREE_TYPE (f);
11691 if (ftype == error_mark_node)
11693 mode = TYPE_MODE (ftype);
11695 if (DECL_SIZE (f) != 0
11696 && tree_fits_uhwi_p (bit_position (f)))
11697 bitpos += int_bit_position (f);
11699 /* ??? FIXME: else assume zero offset. */
11701 if (TREE_CODE (ftype) == RECORD_TYPE)
11702 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11703 else if (USE_FP_FOR_ARG_P (cum, mode))
11705 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11706 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11707 cum->fregno += n_fpregs;
11708 /* Single-precision floats present a special problem for
11709 us, because they are smaller than an 8-byte GPR, and so
11710 the structure-packing rules combined with the standard
11711 varargs behavior mean that we want to pack float/float
11712 and float/int combinations into a single register's
11713 space. This is complicated by the arg advance flushing,
11714 which works on arbitrarily large groups of int-type
11716 if (mode == SFmode)
11718 if (cum->floats_in_gpr == 1)
11720 /* Two floats in a word; count the word and reset
11721 the float count. */
11723 cum->floats_in_gpr = 0;
11725 else if (bitpos % 64 == 0)
11727 /* A float at the beginning of an 8-byte word;
11728 count it and put off adjusting cum->words until
11729 we see if a arg advance flush is going to do it
11731 cum->floats_in_gpr++;
11735 /* The float is at the end of a word, preceded
11736 by integer fields, so the arg advance flush
11737 just above has already set cum->words and
11738 everything is taken care of. */
11742 cum->words += n_fpregs;
11744 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11746 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11750 else if (cum->intoffset == -1)
11751 cum->intoffset = bitpos;
11755 /* Check for an item that needs to be considered specially under the darwin 64
11756 bit ABI. These are record types where the mode is BLK or the structure is
11757 8 bytes in size. */
11759 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11761 return rs6000_darwin64_abi
11762 && ((mode == BLKmode
11763 && TREE_CODE (type) == RECORD_TYPE
11764 && int_size_in_bytes (type) > 0)
11765 || (type && TREE_CODE (type) == RECORD_TYPE
11766 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11769 /* Update the data in CUM to advance over an argument
11770 of mode MODE and data type TYPE.
11771 (TYPE is null for libcalls where that information may not be available.)
11773 Note that for args passed by reference, function_arg will be called
11774 with MODE and TYPE set to that of the pointer to the arg, not the arg
11778 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11779 const_tree type, bool named, int depth)
11781 machine_mode elt_mode;
11784 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11786 /* Only tick off an argument if we're not recursing. */
11788 cum->nargs_prototype--;
11790 #ifdef HAVE_AS_GNU_ATTRIBUTE
11791 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11794 if (SCALAR_FLOAT_MODE_P (mode))
11796 rs6000_passes_float = true;
11797 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11798 && (FLOAT128_IBM_P (mode)
11799 || FLOAT128_IEEE_P (mode)
11801 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11802 rs6000_passes_long_double = true;
11804 if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11805 || (PAIRED_VECTOR_MODE (mode)
11807 && cum->sysv_gregno <= GP_ARG_MAX_REG))
11808 rs6000_passes_vector = true;
11812 if (TARGET_ALTIVEC_ABI
11813 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11814 || (type && TREE_CODE (type) == VECTOR_TYPE
11815 && int_size_in_bytes (type) == 16)))
11817 bool stack = false;
11819 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11821 cum->vregno += n_elts;
11823 if (!TARGET_ALTIVEC)
11824 error ("cannot pass argument in vector register because"
11825 " altivec instructions are disabled, use %qs"
11826 " to enable them", "-maltivec");
11828 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11829 even if it is going to be passed in a vector register.
11830 Darwin does the same for variable-argument functions. */
11831 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11833 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11843 /* Vector parameters must be 16-byte aligned. In 32-bit
11844 mode this means we need to take into account the offset
11845 to the parameter save area. In 64-bit mode, they just
11846 have to start on an even word, since the parameter save
11847 area is 16-byte aligned. */
11849 align = -(rs6000_parm_offset () + cum->words) & 3;
11851 align = cum->words & 1;
11852 cum->words += align + rs6000_arg_size (mode, type);
11854 if (TARGET_DEBUG_ARG)
11856 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11857 cum->words, align);
11858 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11859 cum->nargs_prototype, cum->prototype,
11860 GET_MODE_NAME (mode));
11864 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11866 int size = int_size_in_bytes (type);
11867 /* Variable sized types have size == -1 and are
11868 treated as if consisting entirely of ints.
11869 Pad to 16 byte boundary if needed. */
11870 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11871 && (cum->words % 2) != 0)
11873 /* For varargs, we can just go up by the size of the struct. */
11875 cum->words += (size + 7) / 8;
11878 /* It is tempting to say int register count just goes up by
11879 sizeof(type)/8, but this is wrong in a case such as
11880 { int; double; int; } [powerpc alignment]. We have to
11881 grovel through the fields for these too. */
11882 cum->intoffset = 0;
11883 cum->floats_in_gpr = 0;
11884 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11885 rs6000_darwin64_record_arg_advance_flush (cum,
11886 size * BITS_PER_UNIT, 1);
11888 if (TARGET_DEBUG_ARG)
11890 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11891 cum->words, TYPE_ALIGN (type), size);
11893 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11894 cum->nargs_prototype, cum->prototype,
11895 GET_MODE_NAME (mode));
11898 else if (DEFAULT_ABI == ABI_V4)
11900 if (abi_v4_pass_in_fpr (mode))
11902 /* _Decimal128 must use an even/odd register pair. This assumes
11903 that the register number is odd when fregno is odd. */
11904 if (mode == TDmode && (cum->fregno % 2) == 1)
11907 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11908 <= FP_ARG_V4_MAX_REG)
11909 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11912 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11913 if (mode == DFmode || FLOAT128_IBM_P (mode)
11914 || mode == DDmode || mode == TDmode)
11915 cum->words += cum->words & 1;
11916 cum->words += rs6000_arg_size (mode, type);
11921 int n_words = rs6000_arg_size (mode, type);
11922 int gregno = cum->sysv_gregno;
11924 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11925 As does any other 2 word item such as complex int due to a
11926 historical mistake. */
11928 gregno += (1 - gregno) & 1;
11930 /* Multi-reg args are not split between registers and stack. */
11931 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11933 /* Long long is aligned on the stack. So are other 2 word
11934 items such as complex int due to a historical mistake. */
11936 cum->words += cum->words & 1;
11937 cum->words += n_words;
11940 /* Note: continuing to accumulate gregno past when we've started
11941 spilling to the stack indicates the fact that we've started
11942 spilling to the stack to expand_builtin_saveregs. */
11943 cum->sysv_gregno = gregno + n_words;
11946 if (TARGET_DEBUG_ARG)
11948 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11949 cum->words, cum->fregno);
11950 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11951 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11952 fprintf (stderr, "mode = %4s, named = %d\n",
11953 GET_MODE_NAME (mode), named);
11958 int n_words = rs6000_arg_size (mode, type);
11959 int start_words = cum->words;
11960 int align_words = rs6000_parm_start (mode, type, start_words);
11962 cum->words = align_words + n_words;
11964 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11966 /* _Decimal128 must be passed in an even/odd float register pair.
11967 This assumes that the register number is odd when fregno is
11969 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11971 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11974 if (TARGET_DEBUG_ARG)
11976 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11977 cum->words, cum->fregno);
11978 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11979 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11980 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11981 named, align_words - start_words, depth);
11987 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11988 const_tree type, bool named)
11990 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11994 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11995 structure between cum->intoffset and bitpos to integer registers. */
11998 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11999 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
12002 unsigned int regno;
12003 unsigned int startbit, endbit;
12004 int this_regno, intregs, intoffset;
12007 if (cum->intoffset == -1)
12010 intoffset = cum->intoffset;
12011 cum->intoffset = -1;
12013 /* If this is the trailing part of a word, try to only load that
12014 much into the register. Otherwise load the whole register. Note
12015 that in the latter case we may pick up unwanted bits. It's not a
12016 problem at the moment but may wish to revisit. */
12018 if (intoffset % BITS_PER_WORD != 0)
12020 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
12021 if (!int_mode_for_size (bits, 0).exists (&mode))
12023 /* We couldn't find an appropriate mode, which happens,
12024 e.g., in packed structs when there are 3 bytes to load.
12025 Back intoffset back to the beginning of the word in this
12027 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
12034 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
12035 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
12036 intregs = (endbit - startbit) / BITS_PER_WORD;
12037 this_regno = cum->words + intoffset / BITS_PER_WORD;
12039 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
12040 cum->use_stack = 1;
12042 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
12046 intoffset /= BITS_PER_UNIT;
12049 regno = GP_ARG_MIN_REG + this_regno;
12050 reg = gen_rtx_REG (mode, regno);
12052 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
12055 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
12059 while (intregs > 0);
12062 /* Recursive workhorse for the following. */
12065 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
12066 HOST_WIDE_INT startbitpos, rtx rvec[],
12071 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
12072 if (TREE_CODE (f) == FIELD_DECL)
12074 HOST_WIDE_INT bitpos = startbitpos;
12075 tree ftype = TREE_TYPE (f);
12077 if (ftype == error_mark_node)
12079 mode = TYPE_MODE (ftype);
12081 if (DECL_SIZE (f) != 0
12082 && tree_fits_uhwi_p (bit_position (f)))
12083 bitpos += int_bit_position (f);
12085 /* ??? FIXME: else assume zero offset. */
12087 if (TREE_CODE (ftype) == RECORD_TYPE)
12088 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
12089 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
12091 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
12095 case E_SCmode: mode = SFmode; break;
12096 case E_DCmode: mode = DFmode; break;
12097 case E_TCmode: mode = TFmode; break;
12101 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12102 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
12104 gcc_assert (cum->fregno == FP_ARG_MAX_REG
12105 && (mode == TFmode || mode == TDmode));
12106 /* Long double or _Decimal128 split over regs and memory. */
12107 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12111 = gen_rtx_EXPR_LIST (VOIDmode,
12112 gen_rtx_REG (mode, cum->fregno++),
12113 GEN_INT (bitpos / BITS_PER_UNIT));
12114 if (FLOAT128_2REG_P (mode))
12117 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
12119 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12121 = gen_rtx_EXPR_LIST (VOIDmode,
12122 gen_rtx_REG (mode, cum->vregno++),
12123 GEN_INT (bitpos / BITS_PER_UNIT));
12125 else if (cum->intoffset == -1)
12126 cum->intoffset = bitpos;
12130 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12131 the register(s) to be used for each field and subfield of a struct
12132 being passed by value, along with the offset of where the
12133 register's value may be found in the block. FP fields go in FP
12134 register, vector fields go in vector registers, and everything
12135 else goes in int registers, packed as in memory.
12137 This code is also used for function return values. RETVAL indicates
12138 whether this is the case.
12140 Much of this is taken from the SPARC V9 port, which has a similar
12141 calling convention. */
12144 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
12145 bool named, bool retval)
12147 rtx rvec[FIRST_PSEUDO_REGISTER];
12148 int k = 1, kbase = 1;
12149 HOST_WIDE_INT typesize = int_size_in_bytes (type);
12150 /* This is a copy; modifications are not visible to our caller. */
12151 CUMULATIVE_ARGS copy_cum = *orig_cum;
12152 CUMULATIVE_ARGS *cum = ©_cum;
12154 /* Pad to 16 byte boundary if needed. */
12155 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
12156 && (cum->words % 2) != 0)
12159 cum->intoffset = 0;
12160 cum->use_stack = 0;
12161 cum->named = named;
12163 /* Put entries into rvec[] for individual FP and vector fields, and
12164 for the chunks of memory that go in int regs. Note we start at
12165 element 1; 0 is reserved for an indication of using memory, and
12166 may or may not be filled in below. */
12167 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
12168 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
12170 /* If any part of the struct went on the stack put all of it there.
12171 This hack is because the generic code for
12172 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12173 parts of the struct are not at the beginning. */
12174 if (cum->use_stack)
12177 return NULL_RTX; /* doesn't go in registers at all */
12179 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12181 if (k > 1 || cum->use_stack)
12182 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
12187 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12190 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
12195 rtx rvec[GP_ARG_NUM_REG + 1];
12197 if (align_words >= GP_ARG_NUM_REG)
12200 n_units = rs6000_arg_size (mode, type);
12202 /* Optimize the simple case where the arg fits in one gpr, except in
12203 the case of BLKmode due to assign_parms assuming that registers are
12204 BITS_PER_WORD wide. */
12206 || (n_units == 1 && mode != BLKmode))
12207 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12210 if (align_words + n_units > GP_ARG_NUM_REG)
12211 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12212 using a magic NULL_RTX component.
12213 This is not strictly correct. Only some of the arg belongs in
12214 memory, not all of it. However, the normal scheme using
12215 function_arg_partial_nregs can result in unusual subregs, eg.
12216 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12217 store the whole arg to memory is often more efficient than code
12218 to store pieces, and we know that space is available in the right
12219 place for the whole arg. */
12220 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12225 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12226 rtx off = GEN_INT (i++ * 4);
12227 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12229 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12231 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12234 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12235 but must also be copied into the parameter save area starting at
12236 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12237 to the GPRs and/or memory. Return the number of elements used. */
12240 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12241 int align_words, rtx *rvec)
12245 if (align_words < GP_ARG_NUM_REG)
12247 int n_words = rs6000_arg_size (mode, type);
12249 if (align_words + n_words > GP_ARG_NUM_REG
12251 || (TARGET_32BIT && TARGET_POWERPC64))
12253 /* If this is partially on the stack, then we only
12254 include the portion actually in registers here. */
12255 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12258 if (align_words + n_words > GP_ARG_NUM_REG)
12260 /* Not all of the arg fits in gprs. Say that it goes in memory
12261 too, using a magic NULL_RTX component. Also see comment in
12262 rs6000_mixed_function_arg for why the normal
12263 function_arg_partial_nregs scheme doesn't work in this case. */
12264 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12269 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12270 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12271 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12273 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12277 /* The whole arg fits in gprs. */
12278 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12279 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12284 /* It's entirely in memory. */
12285 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12291 /* RVEC is a vector of K components of an argument of mode MODE.
12292 Construct the final function_arg return value from it. */
12295 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12297 gcc_assert (k >= 1);
12299 /* Avoid returning a PARALLEL in the trivial cases. */
12302 if (XEXP (rvec[0], 0) == NULL_RTX)
12305 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12306 return XEXP (rvec[0], 0);
12309 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12312 /* Determine where to put an argument to a function.
12313 Value is zero to push the argument on the stack,
12314 or a hard register in which to store the argument.
12316 MODE is the argument's machine mode.
12317 TYPE is the data type of the argument (as a tree).
12318 This is null for libcalls where that information may
12320 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12321 the preceding args and about the function being called. It is
12322 not modified in this routine.
12323 NAMED is nonzero if this argument is a named parameter
12324 (otherwise it is an extra parameter matching an ellipsis).
12326 On RS/6000 the first eight words of non-FP are normally in registers
12327 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12328 Under V.4, the first 8 FP args are in registers.
12330 If this is floating-point and no prototype is specified, we use
12331 both an FP and integer register (or possibly FP reg and stack). Library
12332 functions (when CALL_LIBCALL is set) always have the proper types for args,
12333 so we can pass the FP value just in one register. emit_library_function
12334 doesn't support PARALLEL anyway.
12336 Note that for args passed by reference, function_arg will be called
12337 with MODE and TYPE set to that of the pointer to the arg, not the arg
12341 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12342 const_tree type, bool named)
12344 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12345 enum rs6000_abi abi = DEFAULT_ABI;
12346 machine_mode elt_mode;
12349 /* Return a marker to indicate whether CR1 needs to set or clear the
12350 bit that V.4 uses to say fp args were passed in registers.
12351 Assume that we don't need the marker for software floating point,
12352 or compiler generated library calls. */
12353 if (mode == VOIDmode)
12356 && (cum->call_cookie & CALL_LIBCALL) == 0
12358 || (cum->nargs_prototype < 0
12359 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12360 && TARGET_HARD_FLOAT)
12361 return GEN_INT (cum->call_cookie
12362 | ((cum->fregno == FP_ARG_MIN_REG)
12363 ? CALL_V4_SET_FP_ARGS
12364 : CALL_V4_CLEAR_FP_ARGS));
12366 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12369 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12371 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12373 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12374 if (rslt != NULL_RTX)
12376 /* Else fall through to usual handling. */
12379 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12381 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12385 /* Do we also need to pass this argument in the parameter save area?
12386 Library support functions for IEEE 128-bit are assumed to not need the
12387 value passed both in GPRs and in vector registers. */
12388 if (TARGET_64BIT && !cum->prototype
12389 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12391 int align_words = ROUND_UP (cum->words, 2);
12392 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12395 /* Describe where this argument goes in the vector registers. */
12396 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12398 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12399 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12400 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12403 return rs6000_finish_function_arg (mode, rvec, k);
12405 else if (TARGET_ALTIVEC_ABI
12406 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12407 || (type && TREE_CODE (type) == VECTOR_TYPE
12408 && int_size_in_bytes (type) == 16)))
12410 if (named || abi == ABI_V4)
12414 /* Vector parameters to varargs functions under AIX or Darwin
12415 get passed in memory and possibly also in GPRs. */
12416 int align, align_words, n_words;
12417 machine_mode part_mode;
12419 /* Vector parameters must be 16-byte aligned. In 32-bit
12420 mode this means we need to take into account the offset
12421 to the parameter save area. In 64-bit mode, they just
12422 have to start on an even word, since the parameter save
12423 area is 16-byte aligned. */
12425 align = -(rs6000_parm_offset () + cum->words) & 3;
12427 align = cum->words & 1;
12428 align_words = cum->words + align;
12430 /* Out of registers? Memory, then. */
12431 if (align_words >= GP_ARG_NUM_REG)
12434 if (TARGET_32BIT && TARGET_POWERPC64)
12435 return rs6000_mixed_function_arg (mode, type, align_words);
12437 /* The vector value goes in GPRs. Only the part of the
12438 value in GPRs is reported here. */
12440 n_words = rs6000_arg_size (mode, type);
12441 if (align_words + n_words > GP_ARG_NUM_REG)
12442 /* Fortunately, there are only two possibilities, the value
12443 is either wholly in GPRs or half in GPRs and half not. */
12444 part_mode = DImode;
12446 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12450 else if (abi == ABI_V4)
12452 if (abi_v4_pass_in_fpr (mode))
12454 /* _Decimal128 must use an even/odd register pair. This assumes
12455 that the register number is odd when fregno is odd. */
12456 if (mode == TDmode && (cum->fregno % 2) == 1)
12459 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12460 <= FP_ARG_V4_MAX_REG)
12461 return gen_rtx_REG (mode, cum->fregno);
12467 int n_words = rs6000_arg_size (mode, type);
12468 int gregno = cum->sysv_gregno;
12470 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12471 As does any other 2 word item such as complex int due to a
12472 historical mistake. */
12474 gregno += (1 - gregno) & 1;
12476 /* Multi-reg args are not split between registers and stack. */
12477 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12480 if (TARGET_32BIT && TARGET_POWERPC64)
12481 return rs6000_mixed_function_arg (mode, type,
12482 gregno - GP_ARG_MIN_REG);
12483 return gen_rtx_REG (mode, gregno);
12488 int align_words = rs6000_parm_start (mode, type, cum->words);
12490 /* _Decimal128 must be passed in an even/odd float register pair.
12491 This assumes that the register number is odd when fregno is odd. */
12492 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12495 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12497 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12500 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12503 /* Do we also need to pass this argument in the parameter
12505 if (type && (cum->nargs_prototype <= 0
12506 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12507 && TARGET_XL_COMPAT
12508 && align_words >= GP_ARG_NUM_REG)))
12509 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12511 /* Describe where this argument goes in the fprs. */
12512 for (i = 0; i < n_elts
12513 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12515 /* Check if the argument is split over registers and memory.
12516 This can only ever happen for long double or _Decimal128;
12517 complex types are handled via split_complex_arg. */
12518 machine_mode fmode = elt_mode;
12519 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12521 gcc_assert (FLOAT128_2REG_P (fmode));
12522 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12525 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12526 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12527 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12530 /* If there were not enough FPRs to hold the argument, the rest
12531 usually goes into memory. However, if the current position
12532 is still within the register parameter area, a portion may
12533 actually have to go into GPRs.
12535 Note that it may happen that the portion of the argument
12536 passed in the first "half" of the first GPR was already
12537 passed in the last FPR as well.
12539 For unnamed arguments, we already set up GPRs to cover the
12540 whole argument in rs6000_psave_function_arg, so there is
12541 nothing further to do at this point. */
12542 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12543 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12544 && cum->nargs_prototype > 0)
12546 static bool warned;
12548 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12549 int n_words = rs6000_arg_size (mode, type);
12551 align_words += fpr_words;
12552 n_words -= fpr_words;
12556 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12557 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12558 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12560 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12562 if (!warned && warn_psabi)
12565 inform (input_location,
12566 "the ABI of passing homogeneous float aggregates"
12567 " has changed in GCC 5");
12571 return rs6000_finish_function_arg (mode, rvec, k);
12573 else if (align_words < GP_ARG_NUM_REG)
12575 if (TARGET_32BIT && TARGET_POWERPC64)
12576 return rs6000_mixed_function_arg (mode, type, align_words);
12578 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12585 /* For an arg passed partly in registers and partly in memory, this is
12586 the number of bytes passed in registers. For args passed entirely in
12587 registers or entirely in memory, zero. When an arg is described by a
12588 PARALLEL, perhaps using more than one register type, this function
12589 returns the number of bytes used by the first element of the PARALLEL. */
12592 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12593 tree type, bool named)
12595 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12596 bool passed_in_gprs = true;
12599 machine_mode elt_mode;
12602 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12604 if (DEFAULT_ABI == ABI_V4)
12607 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12609 /* If we are passing this arg in the fixed parameter save area (gprs or
12610 memory) as well as VRs, we do not use the partial bytes mechanism;
12611 instead, rs6000_function_arg will return a PARALLEL including a memory
12612 element as necessary. Library support functions for IEEE 128-bit are
12613 assumed to not need the value passed both in GPRs and in vector
12615 if (TARGET_64BIT && !cum->prototype
12616 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12619 /* Otherwise, we pass in VRs only. Check for partial copies. */
12620 passed_in_gprs = false;
12621 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12622 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12625 /* In this complicated case we just disable the partial_nregs code. */
12626 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12629 align_words = rs6000_parm_start (mode, type, cum->words);
12631 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12633 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12635 /* If we are passing this arg in the fixed parameter save area
12636 (gprs or memory) as well as FPRs, we do not use the partial
12637 bytes mechanism; instead, rs6000_function_arg will return a
12638 PARALLEL including a memory element as necessary. */
12640 && (cum->nargs_prototype <= 0
12641 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12642 && TARGET_XL_COMPAT
12643 && align_words >= GP_ARG_NUM_REG)))
12646 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12647 passed_in_gprs = false;
12648 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12650 /* Compute number of bytes / words passed in FPRs. If there
12651 is still space available in the register parameter area
12652 *after* that amount, a part of the argument will be passed
12653 in GPRs. In that case, the total amount passed in any
12654 registers is equal to the amount that would have been passed
12655 in GPRs if everything were passed there, so we fall back to
12656 the GPR code below to compute the appropriate value. */
12657 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12658 * MIN (8, GET_MODE_SIZE (elt_mode)));
12659 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12661 if (align_words + fpr_words < GP_ARG_NUM_REG)
12662 passed_in_gprs = true;
12669 && align_words < GP_ARG_NUM_REG
12670 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12671 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12673 if (ret != 0 && TARGET_DEBUG_ARG)
12674 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12679 /* A C expression that indicates when an argument must be passed by
12680 reference. If nonzero for an argument, a copy of that argument is
12681 made in memory and a pointer to the argument is passed instead of
12682 the argument itself. The pointer is passed in whatever way is
12683 appropriate for passing a pointer to that type.
12685 Under V.4, aggregates and long double are passed by reference.
12687 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12688 reference unless the AltiVec vector extension ABI is in force.
12690 As an extension to all ABIs, variable sized types are passed by
12694 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12695 machine_mode mode, const_tree type,
12696 bool named ATTRIBUTE_UNUSED)
12701 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12702 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12704 if (TARGET_DEBUG_ARG)
12705 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12709 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12711 if (TARGET_DEBUG_ARG)
12712 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12716 if (int_size_in_bytes (type) < 0)
12718 if (TARGET_DEBUG_ARG)
12719 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12723 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12724 modes only exist for GCC vector types if -maltivec. */
12725 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12727 if (TARGET_DEBUG_ARG)
12728 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12732 /* Pass synthetic vectors in memory. */
12733 if (TREE_CODE (type) == VECTOR_TYPE
12734 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12736 static bool warned_for_pass_big_vectors = false;
12737 if (TARGET_DEBUG_ARG)
12738 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12739 if (!warned_for_pass_big_vectors)
12741 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12742 "non-standard ABI extension with no compatibility "
12744 warned_for_pass_big_vectors = true;
12752 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12753 already processes. Return true if the parameter must be passed
12754 (fully or partially) on the stack. */
12757 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12763 /* Catch errors. */
12764 if (type == NULL || type == error_mark_node)
12767 /* Handle types with no storage requirement. */
12768 if (TYPE_MODE (type) == VOIDmode)
12771 /* Handle complex types. */
12772 if (TREE_CODE (type) == COMPLEX_TYPE)
12773 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12774 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12776 /* Handle transparent aggregates. */
12777 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12778 && TYPE_TRANSPARENT_AGGR (type))
12779 type = TREE_TYPE (first_field (type));
12781 /* See if this arg was passed by invisible reference. */
12782 if (pass_by_reference (get_cumulative_args (args_so_far),
12783 TYPE_MODE (type), type, true))
12784 type = build_pointer_type (type);
12786 /* Find mode as it is passed by the ABI. */
12787 unsignedp = TYPE_UNSIGNED (type);
12788 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12790 /* If we must pass in stack, we need a stack. */
12791 if (rs6000_must_pass_in_stack (mode, type))
12794 /* If there is no incoming register, we need a stack. */
12795 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12796 if (entry_parm == NULL)
12799 /* Likewise if we need to pass both in registers and on the stack. */
12800 if (GET_CODE (entry_parm) == PARALLEL
12801 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12804 /* Also true if we're partially in registers and partially not. */
12805 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12808 /* Update info on where next arg arrives in registers. */
12809 rs6000_function_arg_advance (args_so_far, mode, type, true);
12813 /* Return true if FUN has no prototype, has a variable argument
12814 list, or passes any parameter in memory. */
12817 rs6000_function_parms_need_stack (tree fun, bool incoming)
12819 tree fntype, result;
12820 CUMULATIVE_ARGS args_so_far_v;
12821 cumulative_args_t args_so_far;
12824 /* Must be a libcall, all of which only use reg parms. */
12829 fntype = TREE_TYPE (fun);
12831 /* Varargs functions need the parameter save area. */
12832 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12835 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12836 args_so_far = pack_cumulative_args (&args_so_far_v);
12838 /* When incoming, we will have been passed the function decl.
12839 It is necessary to use the decl to handle K&R style functions,
12840 where TYPE_ARG_TYPES may not be available. */
12843 gcc_assert (DECL_P (fun));
12844 result = DECL_RESULT (fun);
12847 result = TREE_TYPE (fntype);
12849 if (result && aggregate_value_p (result, fntype))
12851 if (!TYPE_P (result))
12852 result = TREE_TYPE (result);
12853 result = build_pointer_type (result);
12854 rs6000_parm_needs_stack (args_so_far, result);
12861 for (parm = DECL_ARGUMENTS (fun);
12862 parm && parm != void_list_node;
12863 parm = TREE_CHAIN (parm))
12864 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12869 function_args_iterator args_iter;
12872 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12873 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12880 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12881 usually a constant depending on the ABI. However, in the ELFv2 ABI
12882 the register parameter area is optional when calling a function that
12883 has a prototype is scope, has no variable argument list, and passes
12884 all parameters in registers. */
12887 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12889 int reg_parm_stack_space;
12891 switch (DEFAULT_ABI)
12894 reg_parm_stack_space = 0;
12899 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12903 /* ??? Recomputing this every time is a bit expensive. Is there
12904 a place to cache this information? */
12905 if (rs6000_function_parms_need_stack (fun, incoming))
12906 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12908 reg_parm_stack_space = 0;
12912 return reg_parm_stack_space;
12916 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12919 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12924 for (i = 0; i < nregs; i++)
12926 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12927 if (reload_completed)
12929 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12932 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12933 i * GET_MODE_SIZE (reg_mode));
12936 tem = replace_equiv_address (tem, XEXP (tem, 0));
12940 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12944 /* Perform any needed actions needed for a function that is receiving a
12945 variable number of arguments.
12949 MODE and TYPE are the mode and type of the current parameter.
12951 PRETEND_SIZE is a variable that should be set to the amount of stack
12952 that must be pushed by the prolog to pretend that our caller pushed
12955 Normally, this macro will push all remaining incoming registers on the
12956 stack and set PRETEND_SIZE to the length of the registers pushed. */
12959 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12960 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12963 CUMULATIVE_ARGS next_cum;
12964 int reg_size = TARGET_32BIT ? 4 : 8;
12965 rtx save_area = NULL_RTX, mem;
12966 int first_reg_offset;
12967 alias_set_type set;
12969 /* Skip the last named argument. */
12970 next_cum = *get_cumulative_args (cum);
12971 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12973 if (DEFAULT_ABI == ABI_V4)
12975 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12979 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12980 HOST_WIDE_INT offset = 0;
12982 /* Try to optimize the size of the varargs save area.
12983 The ABI requires that ap.reg_save_area is doubleword
12984 aligned, but we don't need to allocate space for all
12985 the bytes, only those to which we actually will save
12987 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12988 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12989 if (TARGET_HARD_FLOAT
12990 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12991 && cfun->va_list_fpr_size)
12994 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12995 * UNITS_PER_FP_WORD;
12996 if (cfun->va_list_fpr_size
12997 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12998 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
13000 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13001 * UNITS_PER_FP_WORD;
13005 offset = -((first_reg_offset * reg_size) & ~7);
13006 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
13008 gpr_reg_num = cfun->va_list_gpr_size;
13009 if (reg_size == 4 && (first_reg_offset & 1))
13012 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
13015 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
13016 * UNITS_PER_FP_WORD
13017 - (int) (GP_ARG_NUM_REG * reg_size);
13019 if (gpr_size + fpr_size)
13022 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
13023 gcc_assert (GET_CODE (reg_save_area) == MEM);
13024 reg_save_area = XEXP (reg_save_area, 0);
13025 if (GET_CODE (reg_save_area) == PLUS)
13027 gcc_assert (XEXP (reg_save_area, 0)
13028 == virtual_stack_vars_rtx);
13029 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
13030 offset += INTVAL (XEXP (reg_save_area, 1));
13033 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
13036 cfun->machine->varargs_save_offset = offset;
13037 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
13042 first_reg_offset = next_cum.words;
13043 save_area = crtl->args.internal_arg_pointer;
13045 if (targetm.calls.must_pass_in_stack (mode, type))
13046 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
13049 set = get_varargs_alias_set ();
13050 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
13051 && cfun->va_list_gpr_size)
13053 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
13055 if (va_list_gpr_counter_field)
13056 /* V4 va_list_gpr_size counts number of registers needed. */
13057 n_gpr = cfun->va_list_gpr_size;
13059 /* char * va_list instead counts number of bytes needed. */
13060 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
13065 mem = gen_rtx_MEM (BLKmode,
13066 plus_constant (Pmode, save_area,
13067 first_reg_offset * reg_size));
13068 MEM_NOTRAP_P (mem) = 1;
13069 set_mem_alias_set (mem, set);
13070 set_mem_align (mem, BITS_PER_WORD);
13072 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
13076 /* Save FP registers if needed. */
13077 if (DEFAULT_ABI == ABI_V4
13078 && TARGET_HARD_FLOAT
13080 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13081 && cfun->va_list_fpr_size)
13083 int fregno = next_cum.fregno, nregs;
13084 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
13085 rtx lab = gen_label_rtx ();
13086 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
13087 * UNITS_PER_FP_WORD);
13090 (gen_rtx_SET (pc_rtx,
13091 gen_rtx_IF_THEN_ELSE (VOIDmode,
13092 gen_rtx_NE (VOIDmode, cr1,
13094 gen_rtx_LABEL_REF (VOIDmode, lab),
13098 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
13099 fregno++, off += UNITS_PER_FP_WORD, nregs++)
13101 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13103 plus_constant (Pmode, save_area, off));
13104 MEM_NOTRAP_P (mem) = 1;
13105 set_mem_alias_set (mem, set);
13106 set_mem_align (mem, GET_MODE_ALIGNMENT (
13107 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13108 ? DFmode : SFmode));
13109 emit_move_insn (mem, gen_rtx_REG (
13110 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13111 ? DFmode : SFmode, fregno));
13118 /* Create the va_list data type. */
13121 rs6000_build_builtin_va_list (void)
13123 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
13125 /* For AIX, prefer 'char *' because that's what the system
13126 header files like. */
13127 if (DEFAULT_ABI != ABI_V4)
13128 return build_pointer_type (char_type_node);
13130 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
13131 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
13132 get_identifier ("__va_list_tag"), record);
13134 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
13135 unsigned_char_type_node);
13136 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
13137 unsigned_char_type_node);
13138 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13139 every user file. */
13140 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13141 get_identifier ("reserved"), short_unsigned_type_node);
13142 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13143 get_identifier ("overflow_arg_area"),
13145 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13146 get_identifier ("reg_save_area"),
13149 va_list_gpr_counter_field = f_gpr;
13150 va_list_fpr_counter_field = f_fpr;
13152 DECL_FIELD_CONTEXT (f_gpr) = record;
13153 DECL_FIELD_CONTEXT (f_fpr) = record;
13154 DECL_FIELD_CONTEXT (f_res) = record;
13155 DECL_FIELD_CONTEXT (f_ovf) = record;
13156 DECL_FIELD_CONTEXT (f_sav) = record;
13158 TYPE_STUB_DECL (record) = type_decl;
13159 TYPE_NAME (record) = type_decl;
13160 TYPE_FIELDS (record) = f_gpr;
13161 DECL_CHAIN (f_gpr) = f_fpr;
13162 DECL_CHAIN (f_fpr) = f_res;
13163 DECL_CHAIN (f_res) = f_ovf;
13164 DECL_CHAIN (f_ovf) = f_sav;
13166 layout_type (record);
13168 /* The correct type is an array type of one element. */
13169 return build_array_type (record, build_index_type (size_zero_node));
13172 /* Implement va_start. */
13175 rs6000_va_start (tree valist, rtx nextarg)
13177 HOST_WIDE_INT words, n_gpr, n_fpr;
13178 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13179 tree gpr, fpr, ovf, sav, t;
13181 /* Only SVR4 needs something special. */
13182 if (DEFAULT_ABI != ABI_V4)
13184 std_expand_builtin_va_start (valist, nextarg);
13188 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13189 f_fpr = DECL_CHAIN (f_gpr);
13190 f_res = DECL_CHAIN (f_fpr);
13191 f_ovf = DECL_CHAIN (f_res);
13192 f_sav = DECL_CHAIN (f_ovf);
13194 valist = build_simple_mem_ref (valist);
13195 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13196 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13198 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13200 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13203 /* Count number of gp and fp argument registers used. */
13204 words = crtl->args.info.words;
13205 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
13207 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
13210 if (TARGET_DEBUG_ARG)
13211 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
13212 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
13213 words, n_gpr, n_fpr);
13215 if (cfun->va_list_gpr_size)
13217 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13218 build_int_cst (NULL_TREE, n_gpr));
13219 TREE_SIDE_EFFECTS (t) = 1;
13220 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13223 if (cfun->va_list_fpr_size)
13225 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13226 build_int_cst (NULL_TREE, n_fpr));
13227 TREE_SIDE_EFFECTS (t) = 1;
13228 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13230 #ifdef HAVE_AS_GNU_ATTRIBUTE
13231 if (call_ABI_of_interest (cfun->decl))
13232 rs6000_passes_float = true;
13236 /* Find the overflow area. */
13237 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13239 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13240 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13241 TREE_SIDE_EFFECTS (t) = 1;
13242 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13244 /* If there were no va_arg invocations, don't set up the register
13246 if (!cfun->va_list_gpr_size
13247 && !cfun->va_list_fpr_size
13248 && n_gpr < GP_ARG_NUM_REG
13249 && n_fpr < FP_ARG_V4_MAX_REG)
13252 /* Find the register save area. */
13253 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13254 if (cfun->machine->varargs_save_offset)
13255 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13256 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13257 TREE_SIDE_EFFECTS (t) = 1;
13258 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13261 /* Implement va_arg. */
13264 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13265 gimple_seq *post_p)
13267 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13268 tree gpr, fpr, ovf, sav, reg, t, u;
13269 int size, rsize, n_reg, sav_ofs, sav_scale;
13270 tree lab_false, lab_over, addr;
13272 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13276 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13278 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13279 return build_va_arg_indirect_ref (t);
13282 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13283 earlier version of gcc, with the property that it always applied alignment
13284 adjustments to the va-args (even for zero-sized types). The cheapest way
13285 to deal with this is to replicate the effect of the part of
13286 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13288 We don't need to check for pass-by-reference because of the test above.
13289 We can return a simplifed answer, since we know there's no offset to add. */
13292 && rs6000_darwin64_abi)
13293 || DEFAULT_ABI == ABI_ELFv2
13294 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13295 && integer_zerop (TYPE_SIZE (type)))
13297 unsigned HOST_WIDE_INT align, boundary;
13298 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13299 align = PARM_BOUNDARY / BITS_PER_UNIT;
13300 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13301 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13302 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13303 boundary /= BITS_PER_UNIT;
13304 if (boundary > align)
13307 /* This updates arg ptr by the amount that would be necessary
13308 to align the zero-sized (but not zero-alignment) item. */
13309 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13310 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13311 gimplify_and_add (t, pre_p);
13313 t = fold_convert (sizetype, valist_tmp);
13314 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13315 fold_convert (TREE_TYPE (valist),
13316 fold_build2 (BIT_AND_EXPR, sizetype, t,
13317 size_int (-boundary))));
13318 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13319 gimplify_and_add (t, pre_p);
13321 /* Since it is zero-sized there's no increment for the item itself. */
13322 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13323 return build_va_arg_indirect_ref (valist_tmp);
13326 if (DEFAULT_ABI != ABI_V4)
13328 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13330 tree elem_type = TREE_TYPE (type);
13331 machine_mode elem_mode = TYPE_MODE (elem_type);
13332 int elem_size = GET_MODE_SIZE (elem_mode);
13334 if (elem_size < UNITS_PER_WORD)
13336 tree real_part, imag_part;
13337 gimple_seq post = NULL;
13339 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13341 /* Copy the value into a temporary, lest the formal temporary
13342 be reused out from under us. */
13343 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13344 gimple_seq_add_seq (pre_p, post);
13346 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13349 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13353 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13356 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13357 f_fpr = DECL_CHAIN (f_gpr);
13358 f_res = DECL_CHAIN (f_fpr);
13359 f_ovf = DECL_CHAIN (f_res);
13360 f_sav = DECL_CHAIN (f_ovf);
13362 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13363 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13365 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13367 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13370 size = int_size_in_bytes (type);
13371 rsize = (size + 3) / 4;
13372 int pad = 4 * rsize - size;
13375 machine_mode mode = TYPE_MODE (type);
13376 if (abi_v4_pass_in_fpr (mode))
13378 /* FP args go in FP registers, if present. */
13380 n_reg = (size + 7) / 8;
13381 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
13382 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
13383 if (mode != SFmode && mode != SDmode)
13388 /* Otherwise into GP registers. */
13397 /* Pull the value out of the saved registers.... */
13400 addr = create_tmp_var (ptr_type_node, "addr");
13402 /* AltiVec vectors never go in registers when -mabi=altivec. */
13403 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13407 lab_false = create_artificial_label (input_location);
13408 lab_over = create_artificial_label (input_location);
13410 /* Long long is aligned in the registers. As are any other 2 gpr
13411 item such as complex int due to a historical mistake. */
13413 if (n_reg == 2 && reg == gpr)
13416 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13417 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13418 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13419 unshare_expr (reg), u);
13421 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13422 reg number is 0 for f1, so we want to make it odd. */
13423 else if (reg == fpr && mode == TDmode)
13425 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13426 build_int_cst (TREE_TYPE (reg), 1));
13427 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13430 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13431 t = build2 (GE_EXPR, boolean_type_node, u, t);
13432 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13433 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13434 gimplify_and_add (t, pre_p);
13438 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13440 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13441 build_int_cst (TREE_TYPE (reg), n_reg));
13442 u = fold_convert (sizetype, u);
13443 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13444 t = fold_build_pointer_plus (t, u);
13446 /* _Decimal32 varargs are located in the second word of the 64-bit
13447 FP register for 32-bit binaries. */
13448 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13449 t = fold_build_pointer_plus_hwi (t, size);
13451 /* Args are passed right-aligned. */
13452 if (BYTES_BIG_ENDIAN)
13453 t = fold_build_pointer_plus_hwi (t, pad);
13455 gimplify_assign (addr, t, pre_p);
13457 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13459 stmt = gimple_build_label (lab_false);
13460 gimple_seq_add_stmt (pre_p, stmt);
13462 if ((n_reg == 2 && !regalign) || n_reg > 2)
13464 /* Ensure that we don't find any more args in regs.
13465 Alignment has taken care of for special cases. */
13466 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13470 /* ... otherwise out of the overflow area. */
13472 /* Care for on-stack alignment if needed. */
13476 t = fold_build_pointer_plus_hwi (t, align - 1);
13477 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13478 build_int_cst (TREE_TYPE (t), -align));
13481 /* Args are passed right-aligned. */
13482 if (BYTES_BIG_ENDIAN)
13483 t = fold_build_pointer_plus_hwi (t, pad);
13485 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13487 gimplify_assign (unshare_expr (addr), t, pre_p);
13489 t = fold_build_pointer_plus_hwi (t, size);
13490 gimplify_assign (unshare_expr (ovf), t, pre_p);
13494 stmt = gimple_build_label (lab_over);
13495 gimple_seq_add_stmt (pre_p, stmt);
13498 if (STRICT_ALIGNMENT
13499 && (TYPE_ALIGN (type)
13500 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13502 /* The value (of type complex double, for example) may not be
13503 aligned in memory in the saved registers, so copy via a
13504 temporary. (This is the same code as used for SPARC.) */
13505 tree tmp = create_tmp_var (type, "va_arg_tmp");
13506 tree dest_addr = build_fold_addr_expr (tmp);
13508 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13509 3, dest_addr, addr, size_int (rsize * 4));
13511 gimplify_and_add (copy, pre_p);
13515 addr = fold_convert (ptrtype, addr);
13516 return build_va_arg_indirect_ref (addr);
13522 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13525 unsigned classify = rs6000_builtin_info[(int)code].attr;
13526 const char *attr_string = "";
13528 gcc_assert (name != NULL);
13529 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13531 if (rs6000_builtin_decls[(int)code])
13532 fatal_error (input_location,
13533 "internal error: builtin function %qs already processed",
13536 rs6000_builtin_decls[(int)code] = t =
13537 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13539 /* Set any special attributes. */
13540 if ((classify & RS6000_BTC_CONST) != 0)
13542 /* const function, function only depends on the inputs. */
13543 TREE_READONLY (t) = 1;
13544 TREE_NOTHROW (t) = 1;
13545 attr_string = ", const";
13547 else if ((classify & RS6000_BTC_PURE) != 0)
13549 /* pure function, function can read global memory, but does not set any
13551 DECL_PURE_P (t) = 1;
13552 TREE_NOTHROW (t) = 1;
13553 attr_string = ", pure";
13555 else if ((classify & RS6000_BTC_FP) != 0)
13557 /* Function is a math function. If rounding mode is on, then treat the
13558 function as not reading global memory, but it can have arbitrary side
13559 effects. If it is off, then assume the function is a const function.
13560 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13561 builtin-attribute.def that is used for the math functions. */
13562 TREE_NOTHROW (t) = 1;
13563 if (flag_rounding_math)
13565 DECL_PURE_P (t) = 1;
13566 DECL_IS_NOVOPS (t) = 1;
13567 attr_string = ", fp, pure";
13571 TREE_READONLY (t) = 1;
13572 attr_string = ", fp, const";
13575 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13576 gcc_unreachable ();
13578 if (TARGET_DEBUG_BUILTIN)
13579 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13580 (int)code, name, attr_string);
13583 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13585 #undef RS6000_BUILTIN_0
13586 #undef RS6000_BUILTIN_1
13587 #undef RS6000_BUILTIN_2
13588 #undef RS6000_BUILTIN_3
13589 #undef RS6000_BUILTIN_A
13590 #undef RS6000_BUILTIN_D
13591 #undef RS6000_BUILTIN_H
13592 #undef RS6000_BUILTIN_P
13593 #undef RS6000_BUILTIN_Q
13594 #undef RS6000_BUILTIN_X
13596 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13597 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13598 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13599 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13600 { MASK, ICODE, NAME, ENUM },
13602 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13603 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13604 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13605 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13606 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13607 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13609 static const struct builtin_description bdesc_3arg[] =
13611 #include "rs6000-builtin.def"
13614 /* DST operations: void foo (void *, const int, const char). */
13616 #undef RS6000_BUILTIN_0
13617 #undef RS6000_BUILTIN_1
13618 #undef RS6000_BUILTIN_2
13619 #undef RS6000_BUILTIN_3
13620 #undef RS6000_BUILTIN_A
13621 #undef RS6000_BUILTIN_D
13622 #undef RS6000_BUILTIN_H
13623 #undef RS6000_BUILTIN_P
13624 #undef RS6000_BUILTIN_Q
13625 #undef RS6000_BUILTIN_X
13627 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13628 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13629 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13630 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13631 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13632 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13633 { MASK, ICODE, NAME, ENUM },
13635 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13636 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13637 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13638 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13640 static const struct builtin_description bdesc_dst[] =
13642 #include "rs6000-builtin.def"
13645 /* Simple binary operations: VECc = foo (VECa, VECb). */
13647 #undef RS6000_BUILTIN_0
13648 #undef RS6000_BUILTIN_1
13649 #undef RS6000_BUILTIN_2
13650 #undef RS6000_BUILTIN_3
13651 #undef RS6000_BUILTIN_A
13652 #undef RS6000_BUILTIN_D
13653 #undef RS6000_BUILTIN_H
13654 #undef RS6000_BUILTIN_P
13655 #undef RS6000_BUILTIN_Q
13656 #undef RS6000_BUILTIN_X
13658 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13659 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13660 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13661 { MASK, ICODE, NAME, ENUM },
13663 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13664 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13665 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13666 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13667 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13668 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13669 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13671 static const struct builtin_description bdesc_2arg[] =
13673 #include "rs6000-builtin.def"
13676 #undef RS6000_BUILTIN_0
13677 #undef RS6000_BUILTIN_1
13678 #undef RS6000_BUILTIN_2
13679 #undef RS6000_BUILTIN_3
13680 #undef RS6000_BUILTIN_A
13681 #undef RS6000_BUILTIN_D
13682 #undef RS6000_BUILTIN_H
13683 #undef RS6000_BUILTIN_P
13684 #undef RS6000_BUILTIN_Q
13685 #undef RS6000_BUILTIN_X
13687 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13688 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13689 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13690 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13691 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13692 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13693 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13694 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13695 { MASK, ICODE, NAME, ENUM },
13697 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13698 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13700 /* AltiVec predicates. */
13702 static const struct builtin_description bdesc_altivec_preds[] =
13704 #include "rs6000-builtin.def"
13707 /* PAIRED predicates. */
13708 #undef RS6000_BUILTIN_0
13709 #undef RS6000_BUILTIN_1
13710 #undef RS6000_BUILTIN_2
13711 #undef RS6000_BUILTIN_3
13712 #undef RS6000_BUILTIN_A
13713 #undef RS6000_BUILTIN_D
13714 #undef RS6000_BUILTIN_H
13715 #undef RS6000_BUILTIN_P
13716 #undef RS6000_BUILTIN_Q
13717 #undef RS6000_BUILTIN_X
13719 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13720 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13721 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13722 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13723 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13724 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13725 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13726 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13727 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13728 { MASK, ICODE, NAME, ENUM },
13730 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13732 static const struct builtin_description bdesc_paired_preds[] =
13734 #include "rs6000-builtin.def"
13737 /* ABS* operations. */
13739 #undef RS6000_BUILTIN_0
13740 #undef RS6000_BUILTIN_1
13741 #undef RS6000_BUILTIN_2
13742 #undef RS6000_BUILTIN_3
13743 #undef RS6000_BUILTIN_A
13744 #undef RS6000_BUILTIN_D
13745 #undef RS6000_BUILTIN_H
13746 #undef RS6000_BUILTIN_P
13747 #undef RS6000_BUILTIN_Q
13748 #undef RS6000_BUILTIN_X
13750 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13751 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13752 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13753 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13754 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13755 { MASK, ICODE, NAME, ENUM },
13757 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13758 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13759 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13760 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13761 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13763 static const struct builtin_description bdesc_abs[] =
13765 #include "rs6000-builtin.def"
13768 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13771 #undef RS6000_BUILTIN_0
13772 #undef RS6000_BUILTIN_1
13773 #undef RS6000_BUILTIN_2
13774 #undef RS6000_BUILTIN_3
13775 #undef RS6000_BUILTIN_A
13776 #undef RS6000_BUILTIN_D
13777 #undef RS6000_BUILTIN_H
13778 #undef RS6000_BUILTIN_P
13779 #undef RS6000_BUILTIN_Q
13780 #undef RS6000_BUILTIN_X
13782 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13783 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13784 { MASK, ICODE, NAME, ENUM },
13786 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13787 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13788 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13789 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13790 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13791 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13792 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13793 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13795 static const struct builtin_description bdesc_1arg[] =
13797 #include "rs6000-builtin.def"
13800 /* Simple no-argument operations: result = __builtin_darn_32 () */
13802 #undef RS6000_BUILTIN_0
13803 #undef RS6000_BUILTIN_1
13804 #undef RS6000_BUILTIN_2
13805 #undef RS6000_BUILTIN_3
13806 #undef RS6000_BUILTIN_A
13807 #undef RS6000_BUILTIN_D
13808 #undef RS6000_BUILTIN_H
13809 #undef RS6000_BUILTIN_P
13810 #undef RS6000_BUILTIN_Q
13811 #undef RS6000_BUILTIN_X
13813 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13814 { MASK, ICODE, NAME, ENUM },
13816 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13817 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13818 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13819 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13820 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13821 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13822 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13823 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13824 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13826 static const struct builtin_description bdesc_0arg[] =
13828 #include "rs6000-builtin.def"
13831 /* HTM builtins. */
13832 #undef RS6000_BUILTIN_0
13833 #undef RS6000_BUILTIN_1
13834 #undef RS6000_BUILTIN_2
13835 #undef RS6000_BUILTIN_3
13836 #undef RS6000_BUILTIN_A
13837 #undef RS6000_BUILTIN_D
13838 #undef RS6000_BUILTIN_H
13839 #undef RS6000_BUILTIN_P
13840 #undef RS6000_BUILTIN_Q
13841 #undef RS6000_BUILTIN_X
13843 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13844 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13845 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13846 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13847 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13848 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13849 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13850 { MASK, ICODE, NAME, ENUM },
13852 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13853 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13854 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13856 static const struct builtin_description bdesc_htm[] =
13858 #include "rs6000-builtin.def"
13861 #undef RS6000_BUILTIN_0
13862 #undef RS6000_BUILTIN_1
13863 #undef RS6000_BUILTIN_2
13864 #undef RS6000_BUILTIN_3
13865 #undef RS6000_BUILTIN_A
13866 #undef RS6000_BUILTIN_D
13867 #undef RS6000_BUILTIN_H
13868 #undef RS6000_BUILTIN_P
13869 #undef RS6000_BUILTIN_Q
13871 /* Return true if a builtin function is overloaded. */
13873 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13875 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13879 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13881 return rs6000_builtin_info[(int)fncode].name;
13884 /* Expand an expression EXP that calls a builtin without arguments. */
13886 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13889 machine_mode tmode = insn_data[icode].operand[0].mode;
13891 if (icode == CODE_FOR_nothing)
13892 /* Builtin not supported on this processor. */
13896 || GET_MODE (target) != tmode
13897 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13898 target = gen_reg_rtx (tmode);
13900 pat = GEN_FCN (icode) (target);
13910 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13913 tree arg0 = CALL_EXPR_ARG (exp, 0);
13914 tree arg1 = CALL_EXPR_ARG (exp, 1);
13915 rtx op0 = expand_normal (arg0);
13916 rtx op1 = expand_normal (arg1);
13917 machine_mode mode0 = insn_data[icode].operand[0].mode;
13918 machine_mode mode1 = insn_data[icode].operand[1].mode;
13920 if (icode == CODE_FOR_nothing)
13921 /* Builtin not supported on this processor. */
13924 /* If we got invalid arguments bail out before generating bad rtl. */
13925 if (arg0 == error_mark_node || arg1 == error_mark_node)
13928 if (GET_CODE (op0) != CONST_INT
13929 || INTVAL (op0) > 255
13930 || INTVAL (op0) < 0)
13932 error ("argument 1 must be an 8-bit field value");
13936 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13937 op0 = copy_to_mode_reg (mode0, op0);
13939 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13940 op1 = copy_to_mode_reg (mode1, op1);
13942 pat = GEN_FCN (icode) (op0, op1);
13951 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13954 tree arg0 = CALL_EXPR_ARG (exp, 0);
13955 rtx op0 = expand_normal (arg0);
13956 machine_mode tmode = insn_data[icode].operand[0].mode;
13957 machine_mode mode0 = insn_data[icode].operand[1].mode;
13959 if (icode == CODE_FOR_nothing)
13960 /* Builtin not supported on this processor. */
13963 /* If we got invalid arguments bail out before generating bad rtl. */
13964 if (arg0 == error_mark_node)
13967 if (icode == CODE_FOR_altivec_vspltisb
13968 || icode == CODE_FOR_altivec_vspltish
13969 || icode == CODE_FOR_altivec_vspltisw)
13971 /* Only allow 5-bit *signed* literals. */
13972 if (GET_CODE (op0) != CONST_INT
13973 || INTVAL (op0) > 15
13974 || INTVAL (op0) < -16)
13976 error ("argument 1 must be a 5-bit signed literal");
13977 return CONST0_RTX (tmode);
13982 || GET_MODE (target) != tmode
13983 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13984 target = gen_reg_rtx (tmode);
13986 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13987 op0 = copy_to_mode_reg (mode0, op0);
13989 pat = GEN_FCN (icode) (target, op0);
13998 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
14000 rtx pat, scratch1, scratch2;
14001 tree arg0 = CALL_EXPR_ARG (exp, 0);
14002 rtx op0 = expand_normal (arg0);
14003 machine_mode tmode = insn_data[icode].operand[0].mode;
14004 machine_mode mode0 = insn_data[icode].operand[1].mode;
14006 /* If we have invalid arguments, bail out before generating bad rtl. */
14007 if (arg0 == error_mark_node)
14011 || GET_MODE (target) != tmode
14012 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14013 target = gen_reg_rtx (tmode);
14015 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14016 op0 = copy_to_mode_reg (mode0, op0);
14018 scratch1 = gen_reg_rtx (mode0);
14019 scratch2 = gen_reg_rtx (mode0);
14021 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
14030 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
14033 tree arg0 = CALL_EXPR_ARG (exp, 0);
14034 tree arg1 = CALL_EXPR_ARG (exp, 1);
14035 rtx op0 = expand_normal (arg0);
14036 rtx op1 = expand_normal (arg1);
14037 machine_mode tmode = insn_data[icode].operand[0].mode;
14038 machine_mode mode0 = insn_data[icode].operand[1].mode;
14039 machine_mode mode1 = insn_data[icode].operand[2].mode;
14041 if (icode == CODE_FOR_nothing)
14042 /* Builtin not supported on this processor. */
14045 /* If we got invalid arguments bail out before generating bad rtl. */
14046 if (arg0 == error_mark_node || arg1 == error_mark_node)
14049 if (icode == CODE_FOR_altivec_vcfux
14050 || icode == CODE_FOR_altivec_vcfsx
14051 || icode == CODE_FOR_altivec_vctsxs
14052 || icode == CODE_FOR_altivec_vctuxs
14053 || icode == CODE_FOR_altivec_vspltb
14054 || icode == CODE_FOR_altivec_vsplth
14055 || icode == CODE_FOR_altivec_vspltw)
14057 /* Only allow 5-bit unsigned literals. */
14059 if (TREE_CODE (arg1) != INTEGER_CST
14060 || TREE_INT_CST_LOW (arg1) & ~0x1f)
14062 error ("argument 2 must be a 5-bit unsigned literal");
14063 return CONST0_RTX (tmode);
14066 else if (icode == CODE_FOR_dfptstsfi_eq_dd
14067 || icode == CODE_FOR_dfptstsfi_lt_dd
14068 || icode == CODE_FOR_dfptstsfi_gt_dd
14069 || icode == CODE_FOR_dfptstsfi_unordered_dd
14070 || icode == CODE_FOR_dfptstsfi_eq_td
14071 || icode == CODE_FOR_dfptstsfi_lt_td
14072 || icode == CODE_FOR_dfptstsfi_gt_td
14073 || icode == CODE_FOR_dfptstsfi_unordered_td)
14075 /* Only allow 6-bit unsigned literals. */
14077 if (TREE_CODE (arg0) != INTEGER_CST
14078 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
14080 error ("argument 1 must be a 6-bit unsigned literal");
14081 return CONST0_RTX (tmode);
14084 else if (icode == CODE_FOR_xststdcqp_kf
14085 || icode == CODE_FOR_xststdcqp_tf
14086 || icode == CODE_FOR_xststdcdp
14087 || icode == CODE_FOR_xststdcsp
14088 || icode == CODE_FOR_xvtstdcdp
14089 || icode == CODE_FOR_xvtstdcsp)
14091 /* Only allow 7-bit unsigned literals. */
14093 if (TREE_CODE (arg1) != INTEGER_CST
14094 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
14096 error ("argument 2 must be a 7-bit unsigned literal");
14097 return CONST0_RTX (tmode);
14100 else if (icode == CODE_FOR_unpackv1ti
14101 || icode == CODE_FOR_unpackkf
14102 || icode == CODE_FOR_unpacktf
14103 || icode == CODE_FOR_unpackif
14104 || icode == CODE_FOR_unpacktd)
14106 /* Only allow 1-bit unsigned literals. */
14108 if (TREE_CODE (arg1) != INTEGER_CST
14109 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
14111 error ("argument 2 must be a 1-bit unsigned literal");
14112 return CONST0_RTX (tmode);
14117 || GET_MODE (target) != tmode
14118 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14119 target = gen_reg_rtx (tmode);
14121 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14122 op0 = copy_to_mode_reg (mode0, op0);
14123 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14124 op1 = copy_to_mode_reg (mode1, op1);
14126 pat = GEN_FCN (icode) (target, op0, op1);
14135 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
14138 tree cr6_form = CALL_EXPR_ARG (exp, 0);
14139 tree arg0 = CALL_EXPR_ARG (exp, 1);
14140 tree arg1 = CALL_EXPR_ARG (exp, 2);
14141 rtx op0 = expand_normal (arg0);
14142 rtx op1 = expand_normal (arg1);
14143 machine_mode tmode = SImode;
14144 machine_mode mode0 = insn_data[icode].operand[1].mode;
14145 machine_mode mode1 = insn_data[icode].operand[2].mode;
14148 if (TREE_CODE (cr6_form) != INTEGER_CST)
14150 error ("argument 1 of %qs must be a constant",
14151 "__builtin_altivec_predicate");
14155 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
14157 gcc_assert (mode0 == mode1);
14159 /* If we have invalid arguments, bail out before generating bad rtl. */
14160 if (arg0 == error_mark_node || arg1 == error_mark_node)
14164 || GET_MODE (target) != tmode
14165 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14166 target = gen_reg_rtx (tmode);
14168 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14169 op0 = copy_to_mode_reg (mode0, op0);
14170 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14171 op1 = copy_to_mode_reg (mode1, op1);
14173 /* Note that for many of the relevant operations (e.g. cmpne or
14174 cmpeq) with float or double operands, it makes more sense for the
14175 mode of the allocated scratch register to select a vector of
14176 integer. But the choice to copy the mode of operand 0 was made
14177 long ago and there are no plans to change it. */
14178 scratch = gen_reg_rtx (mode0);
14180 pat = GEN_FCN (icode) (scratch, op0, op1);
14185 /* The vec_any* and vec_all* predicates use the same opcodes for two
14186 different operations, but the bits in CR6 will be different
14187 depending on what information we want. So we have to play tricks
14188 with CR6 to get the right bits out.
14190 If you think this is disgusting, look at the specs for the
14191 AltiVec predicates. */
14193 switch (cr6_form_int)
14196 emit_insn (gen_cr6_test_for_zero (target));
14199 emit_insn (gen_cr6_test_for_zero_reverse (target));
14202 emit_insn (gen_cr6_test_for_lt (target));
14205 emit_insn (gen_cr6_test_for_lt_reverse (target));
14208 error ("argument 1 of %qs is out of range",
14209 "__builtin_altivec_predicate");
14217 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
14220 tree arg0 = CALL_EXPR_ARG (exp, 0);
14221 tree arg1 = CALL_EXPR_ARG (exp, 1);
14222 machine_mode tmode = insn_data[icode].operand[0].mode;
14223 machine_mode mode0 = Pmode;
14224 machine_mode mode1 = Pmode;
14225 rtx op0 = expand_normal (arg0);
14226 rtx op1 = expand_normal (arg1);
14228 if (icode == CODE_FOR_nothing)
14229 /* Builtin not supported on this processor. */
14232 /* If we got invalid arguments bail out before generating bad rtl. */
14233 if (arg0 == error_mark_node || arg1 == error_mark_node)
14237 || GET_MODE (target) != tmode
14238 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14239 target = gen_reg_rtx (tmode);
14241 op1 = copy_to_mode_reg (mode1, op1);
14243 if (op0 == const0_rtx)
14245 addr = gen_rtx_MEM (tmode, op1);
14249 op0 = copy_to_mode_reg (mode0, op0);
14250 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
14253 pat = GEN_FCN (icode) (target, addr);
14262 /* Return a constant vector for use as a little-endian permute control vector
14263 to reverse the order of elements of the given vector mode. */
14265 swap_selector_for_mode (machine_mode mode)
14267 /* These are little endian vectors, so their elements are reversed
14268 from what you would normally expect for a permute control vector. */
14269 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14270 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14271 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14272 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14273 unsigned int *swaparray, i;
14290 swaparray = swap16;
14293 gcc_unreachable ();
14296 for (i = 0; i < 16; ++i)
14297 perm[i] = GEN_INT (swaparray[i]);
14299 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
14303 swap_endian_selector_for_mode (machine_mode mode)
14305 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14306 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14307 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14308 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14310 unsigned int *swaparray, i;
14330 gcc_unreachable ();
14333 for (i = 0; i < 16; ++i)
14334 perm[i] = GEN_INT (swaparray[i]);
14336 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
14337 gen_rtvec_v (16, perm)));
14340 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14341 with -maltivec=be specified. Issue the load followed by an element-
14342 reversing permute. */
14344 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14346 rtx tmp = gen_reg_rtx (mode);
14347 rtx load = gen_rtx_SET (tmp, op1);
14348 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14349 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
14350 rtx sel = swap_selector_for_mode (mode);
14351 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
14353 gcc_assert (REG_P (op0));
14355 emit_insn (gen_rtx_SET (op0, vperm));
14358 /* Generate code for a "stvxl" built-in for a little endian target with
14359 -maltivec=be specified. Issue the store preceded by an element-reversing
14362 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14364 rtx tmp = gen_reg_rtx (mode);
14365 rtx store = gen_rtx_SET (op0, tmp);
14366 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14367 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
14368 rtx sel = swap_selector_for_mode (mode);
14371 gcc_assert (REG_P (op1));
14372 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14373 emit_insn (gen_rtx_SET (tmp, vperm));
14377 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14378 specified. Issue the store preceded by an element-reversing permute. */
14380 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14382 machine_mode inner_mode = GET_MODE_INNER (mode);
14383 rtx tmp = gen_reg_rtx (mode);
14384 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
14385 rtx sel = swap_selector_for_mode (mode);
14388 gcc_assert (REG_P (op1));
14389 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14390 emit_insn (gen_rtx_SET (tmp, vperm));
14391 emit_insn (gen_rtx_SET (op0, stvx));
14395 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14398 tree arg0 = CALL_EXPR_ARG (exp, 0);
14399 tree arg1 = CALL_EXPR_ARG (exp, 1);
14400 machine_mode tmode = insn_data[icode].operand[0].mode;
14401 machine_mode mode0 = Pmode;
14402 machine_mode mode1 = Pmode;
14403 rtx op0 = expand_normal (arg0);
14404 rtx op1 = expand_normal (arg1);
14406 if (icode == CODE_FOR_nothing)
14407 /* Builtin not supported on this processor. */
14410 /* If we got invalid arguments bail out before generating bad rtl. */
14411 if (arg0 == error_mark_node || arg1 == error_mark_node)
14415 || GET_MODE (target) != tmode
14416 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14417 target = gen_reg_rtx (tmode);
14419 op1 = copy_to_mode_reg (mode1, op1);
14421 /* For LVX, express the RTL accurately by ANDing the address with -16.
14422 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14423 so the raw address is fine. */
14424 if (icode == CODE_FOR_altivec_lvx_v2df_2op
14425 || icode == CODE_FOR_altivec_lvx_v2di_2op
14426 || icode == CODE_FOR_altivec_lvx_v4sf_2op
14427 || icode == CODE_FOR_altivec_lvx_v4si_2op
14428 || icode == CODE_FOR_altivec_lvx_v8hi_2op
14429 || icode == CODE_FOR_altivec_lvx_v16qi_2op)
14432 if (op0 == const0_rtx)
14436 op0 = copy_to_mode_reg (mode0, op0);
14437 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14439 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14440 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14442 /* For -maltivec=be, emit the load and follow it up with a
14443 permute to swap the elements. */
14444 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14446 rtx temp = gen_reg_rtx (tmode);
14447 emit_insn (gen_rtx_SET (temp, addr));
14449 rtx sel = swap_selector_for_mode (tmode);
14450 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
14452 emit_insn (gen_rtx_SET (target, vperm));
14455 emit_insn (gen_rtx_SET (target, addr));
14459 if (op0 == const0_rtx)
14460 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14463 op0 = copy_to_mode_reg (mode0, op0);
14464 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14465 gen_rtx_PLUS (Pmode, op1, op0));
14468 pat = GEN_FCN (icode) (target, addr);
14478 paired_expand_stv_builtin (enum insn_code icode, tree exp)
14480 tree arg0 = CALL_EXPR_ARG (exp, 0);
14481 tree arg1 = CALL_EXPR_ARG (exp, 1);
14482 tree arg2 = CALL_EXPR_ARG (exp, 2);
14483 rtx op0 = expand_normal (arg0);
14484 rtx op1 = expand_normal (arg1);
14485 rtx op2 = expand_normal (arg2);
14487 machine_mode tmode = insn_data[icode].operand[0].mode;
14488 machine_mode mode1 = Pmode;
14489 machine_mode mode2 = Pmode;
14491 /* Invalid arguments. Bail before doing anything stoopid! */
14492 if (arg0 == error_mark_node
14493 || arg1 == error_mark_node
14494 || arg2 == error_mark_node)
14497 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
14498 op0 = copy_to_mode_reg (tmode, op0);
14500 op2 = copy_to_mode_reg (mode2, op2);
14502 if (op1 == const0_rtx)
14504 addr = gen_rtx_MEM (tmode, op2);
14508 op1 = copy_to_mode_reg (mode1, op1);
14509 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
14512 pat = GEN_FCN (icode) (addr, op0);
14519 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14522 tree arg0 = CALL_EXPR_ARG (exp, 0);
14523 tree arg1 = CALL_EXPR_ARG (exp, 1);
14524 tree arg2 = CALL_EXPR_ARG (exp, 2);
14525 rtx op0 = expand_normal (arg0);
14526 rtx op1 = expand_normal (arg1);
14527 rtx op2 = expand_normal (arg2);
14528 machine_mode mode0 = insn_data[icode].operand[0].mode;
14529 machine_mode mode1 = insn_data[icode].operand[1].mode;
14530 machine_mode mode2 = insn_data[icode].operand[2].mode;
14532 if (icode == CODE_FOR_nothing)
14533 /* Builtin not supported on this processor. */
14536 /* If we got invalid arguments bail out before generating bad rtl. */
14537 if (arg0 == error_mark_node
14538 || arg1 == error_mark_node
14539 || arg2 == error_mark_node)
14542 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14543 op0 = copy_to_mode_reg (mode0, op0);
14544 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14545 op1 = copy_to_mode_reg (mode1, op1);
14546 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14547 op2 = copy_to_mode_reg (mode2, op2);
14549 pat = GEN_FCN (icode) (op0, op1, op2);
14557 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14559 tree arg0 = CALL_EXPR_ARG (exp, 0);
14560 tree arg1 = CALL_EXPR_ARG (exp, 1);
14561 tree arg2 = CALL_EXPR_ARG (exp, 2);
14562 rtx op0 = expand_normal (arg0);
14563 rtx op1 = expand_normal (arg1);
14564 rtx op2 = expand_normal (arg2);
14565 rtx pat, addr, rawaddr;
14566 machine_mode tmode = insn_data[icode].operand[0].mode;
14567 machine_mode smode = insn_data[icode].operand[1].mode;
14568 machine_mode mode1 = Pmode;
14569 machine_mode mode2 = Pmode;
14571 /* Invalid arguments. Bail before doing anything stoopid! */
14572 if (arg0 == error_mark_node
14573 || arg1 == error_mark_node
14574 || arg2 == error_mark_node)
14577 op2 = copy_to_mode_reg (mode2, op2);
14579 /* For STVX, express the RTL accurately by ANDing the address with -16.
14580 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14581 so the raw address is fine. */
14582 if (icode == CODE_FOR_altivec_stvx_v2df_2op
14583 || icode == CODE_FOR_altivec_stvx_v2di_2op
14584 || icode == CODE_FOR_altivec_stvx_v4sf_2op
14585 || icode == CODE_FOR_altivec_stvx_v4si_2op
14586 || icode == CODE_FOR_altivec_stvx_v8hi_2op
14587 || icode == CODE_FOR_altivec_stvx_v16qi_2op)
14589 if (op1 == const0_rtx)
14593 op1 = copy_to_mode_reg (mode1, op1);
14594 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14597 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14598 addr = gen_rtx_MEM (tmode, addr);
14600 op0 = copy_to_mode_reg (tmode, op0);
14602 /* For -maltivec=be, emit a permute to swap the elements, followed
14604 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14606 rtx temp = gen_reg_rtx (tmode);
14607 rtx sel = swap_selector_for_mode (tmode);
14608 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
14610 emit_insn (gen_rtx_SET (temp, vperm));
14611 emit_insn (gen_rtx_SET (addr, temp));
14614 emit_insn (gen_rtx_SET (addr, op0));
14618 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14619 op0 = copy_to_mode_reg (smode, op0);
14621 if (op1 == const0_rtx)
14622 addr = gen_rtx_MEM (tmode, op2);
14625 op1 = copy_to_mode_reg (mode1, op1);
14626 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14629 pat = GEN_FCN (icode) (addr, op0);
14637 /* Return the appropriate SPR number associated with the given builtin. */
14638 static inline HOST_WIDE_INT
14639 htm_spr_num (enum rs6000_builtins code)
14641 if (code == HTM_BUILTIN_GET_TFHAR
14642 || code == HTM_BUILTIN_SET_TFHAR)
14644 else if (code == HTM_BUILTIN_GET_TFIAR
14645 || code == HTM_BUILTIN_SET_TFIAR)
14647 else if (code == HTM_BUILTIN_GET_TEXASR
14648 || code == HTM_BUILTIN_SET_TEXASR)
14650 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14651 || code == HTM_BUILTIN_SET_TEXASRU);
14652 return TEXASRU_SPR;
14655 /* Return the appropriate SPR regno associated with the given builtin. */
14656 static inline HOST_WIDE_INT
14657 htm_spr_regno (enum rs6000_builtins code)
14659 if (code == HTM_BUILTIN_GET_TFHAR
14660 || code == HTM_BUILTIN_SET_TFHAR)
14661 return TFHAR_REGNO;
14662 else if (code == HTM_BUILTIN_GET_TFIAR
14663 || code == HTM_BUILTIN_SET_TFIAR)
14664 return TFIAR_REGNO;
14665 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14666 || code == HTM_BUILTIN_SET_TEXASR
14667 || code == HTM_BUILTIN_GET_TEXASRU
14668 || code == HTM_BUILTIN_SET_TEXASRU);
14669 return TEXASR_REGNO;
14672 /* Return the correct ICODE value depending on whether we are
14673 setting or reading the HTM SPRs. */
14674 static inline enum insn_code
14675 rs6000_htm_spr_icode (bool nonvoid)
14678 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14680 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14683 /* Expand the HTM builtin in EXP and store the result in TARGET.
14684 Store true in *EXPANDEDP if we found a builtin to expand. */
14686 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14688 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14689 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14690 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14691 const struct builtin_description *d;
14696 if (!TARGET_POWERPC64
14697 && (fcode == HTM_BUILTIN_TABORTDC
14698 || fcode == HTM_BUILTIN_TABORTDCI))
14700 size_t uns_fcode = (size_t)fcode;
14701 const char *name = rs6000_builtin_info[uns_fcode].name;
14702 error ("builtin %qs is only valid in 64-bit mode", name);
14706 /* Expand the HTM builtins. */
14708 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14709 if (d->code == fcode)
14711 rtx op[MAX_HTM_OPERANDS], pat;
14714 call_expr_arg_iterator iter;
14715 unsigned attr = rs6000_builtin_info[fcode].attr;
14716 enum insn_code icode = d->icode;
14717 const struct insn_operand_data *insn_op;
14718 bool uses_spr = (attr & RS6000_BTC_SPR);
14722 icode = rs6000_htm_spr_icode (nonvoid);
14723 insn_op = &insn_data[icode].operand[0];
14727 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14729 || GET_MODE (target) != tmode
14730 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14731 target = gen_reg_rtx (tmode);
14733 op[nopnds++] = target;
14736 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14738 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14741 insn_op = &insn_data[icode].operand[nopnds];
14743 op[nopnds] = expand_normal (arg);
14745 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14747 if (!strcmp (insn_op->constraint, "n"))
14749 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14750 if (!CONST_INT_P (op[nopnds]))
14751 error ("argument %d must be an unsigned literal", arg_num);
14753 error ("argument %d is an unsigned literal that is "
14754 "out of range", arg_num);
14757 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14763 /* Handle the builtins for extended mnemonics. These accept
14764 no arguments, but map to builtins that take arguments. */
14767 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14768 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14769 op[nopnds++] = GEN_INT (1);
14771 attr |= RS6000_BTC_UNARY;
14773 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14774 op[nopnds++] = GEN_INT (0);
14776 attr |= RS6000_BTC_UNARY;
14782 /* If this builtin accesses SPRs, then pass in the appropriate
14783 SPR number and SPR regno as the last two operands. */
14786 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14787 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14788 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14790 /* If this builtin accesses a CR, then pass in a scratch
14791 CR as the last operand. */
14792 else if (attr & RS6000_BTC_CR)
14793 { cr = gen_reg_rtx (CCmode);
14799 int expected_nopnds = 0;
14800 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14801 expected_nopnds = 1;
14802 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14803 expected_nopnds = 2;
14804 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14805 expected_nopnds = 3;
14806 if (!(attr & RS6000_BTC_VOID))
14807 expected_nopnds += 1;
14809 expected_nopnds += 2;
14811 gcc_assert (nopnds == expected_nopnds
14812 && nopnds <= MAX_HTM_OPERANDS);
14818 pat = GEN_FCN (icode) (op[0]);
14821 pat = GEN_FCN (icode) (op[0], op[1]);
14824 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14827 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14830 gcc_unreachable ();
14836 if (attr & RS6000_BTC_CR)
14838 if (fcode == HTM_BUILTIN_TBEGIN)
14840 /* Emit code to set TARGET to true or false depending on
14841 whether the tbegin. instruction successfully or failed
14842 to start a transaction. We do this by placing the 1's
14843 complement of CR's EQ bit into TARGET. */
14844 rtx scratch = gen_reg_rtx (SImode);
14845 emit_insn (gen_rtx_SET (scratch,
14846 gen_rtx_EQ (SImode, cr,
14848 emit_insn (gen_rtx_SET (target,
14849 gen_rtx_XOR (SImode, scratch,
14854 /* Emit code to copy the 4-bit condition register field
14855 CR into the least significant end of register TARGET. */
14856 rtx scratch1 = gen_reg_rtx (SImode);
14857 rtx scratch2 = gen_reg_rtx (SImode);
14858 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14859 emit_insn (gen_movcc (subreg, cr));
14860 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14861 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14870 *expandedp = false;
14874 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14877 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14880 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14881 if (fcode == RS6000_BUILTIN_CPU_INIT)
14884 if (target == 0 || GET_MODE (target) != SImode)
14885 target = gen_reg_rtx (SImode);
14887 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14888 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14889 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14890 to a STRING_CST. */
14891 if (TREE_CODE (arg) == ARRAY_REF
14892 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14893 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14894 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14895 arg = TREE_OPERAND (arg, 0);
14897 if (TREE_CODE (arg) != STRING_CST)
14899 error ("builtin %qs only accepts a string argument",
14900 rs6000_builtin_info[(size_t) fcode].name);
14904 if (fcode == RS6000_BUILTIN_CPU_IS)
14906 const char *cpu = TREE_STRING_POINTER (arg);
14907 rtx cpuid = NULL_RTX;
14908 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14909 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14911 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14912 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14915 if (cpuid == NULL_RTX)
14917 /* Invalid CPU argument. */
14918 error ("cpu %qs is an invalid argument to builtin %qs",
14919 cpu, rs6000_builtin_info[(size_t) fcode].name);
14923 rtx platform = gen_reg_rtx (SImode);
14924 rtx tcbmem = gen_const_mem (SImode,
14925 gen_rtx_PLUS (Pmode,
14926 gen_rtx_REG (Pmode, TLS_REGNUM),
14927 GEN_INT (TCB_PLATFORM_OFFSET)));
14928 emit_move_insn (platform, tcbmem);
14929 emit_insn (gen_eqsi3 (target, platform, cpuid));
14931 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14933 const char *hwcap = TREE_STRING_POINTER (arg);
14934 rtx mask = NULL_RTX;
14936 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14937 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14939 mask = GEN_INT (cpu_supports_info[i].mask);
14940 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14943 if (mask == NULL_RTX)
14945 /* Invalid HWCAP argument. */
14946 error ("%s %qs is an invalid argument to builtin %qs",
14947 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14951 rtx tcb_hwcap = gen_reg_rtx (SImode);
14952 rtx tcbmem = gen_const_mem (SImode,
14953 gen_rtx_PLUS (Pmode,
14954 gen_rtx_REG (Pmode, TLS_REGNUM),
14955 GEN_INT (hwcap_offset)));
14956 emit_move_insn (tcb_hwcap, tcbmem);
14957 rtx scratch1 = gen_reg_rtx (SImode);
14958 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14959 rtx scratch2 = gen_reg_rtx (SImode);
14960 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14961 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14964 gcc_unreachable ();
14966 /* Record that we have expanded a CPU builtin, so that we can later
14967 emit a reference to the special symbol exported by LIBC to ensure we
14968 do not link against an old LIBC that doesn't support this feature. */
14969 cpu_builtin_p = true;
14972 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14973 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14975 /* For old LIBCs, always return FALSE. */
14976 emit_move_insn (target, GEN_INT (0));
14977 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14983 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14986 tree arg0 = CALL_EXPR_ARG (exp, 0);
14987 tree arg1 = CALL_EXPR_ARG (exp, 1);
14988 tree arg2 = CALL_EXPR_ARG (exp, 2);
14989 rtx op0 = expand_normal (arg0);
14990 rtx op1 = expand_normal (arg1);
14991 rtx op2 = expand_normal (arg2);
14992 machine_mode tmode = insn_data[icode].operand[0].mode;
14993 machine_mode mode0 = insn_data[icode].operand[1].mode;
14994 machine_mode mode1 = insn_data[icode].operand[2].mode;
14995 machine_mode mode2 = insn_data[icode].operand[3].mode;
14997 if (icode == CODE_FOR_nothing)
14998 /* Builtin not supported on this processor. */
15001 /* If we got invalid arguments bail out before generating bad rtl. */
15002 if (arg0 == error_mark_node
15003 || arg1 == error_mark_node
15004 || arg2 == error_mark_node)
15007 /* Check and prepare argument depending on the instruction code.
15009 Note that a switch statement instead of the sequence of tests
15010 would be incorrect as many of the CODE_FOR values could be
15011 CODE_FOR_nothing and that would yield multiple alternatives
15012 with identical values. We'd never reach here at runtime in
15014 if (icode == CODE_FOR_altivec_vsldoi_v4sf
15015 || icode == CODE_FOR_altivec_vsldoi_v2df
15016 || icode == CODE_FOR_altivec_vsldoi_v4si
15017 || icode == CODE_FOR_altivec_vsldoi_v8hi
15018 || icode == CODE_FOR_altivec_vsldoi_v16qi)
15020 /* Only allow 4-bit unsigned literals. */
15022 if (TREE_CODE (arg2) != INTEGER_CST
15023 || TREE_INT_CST_LOW (arg2) & ~0xf)
15025 error ("argument 3 must be a 4-bit unsigned literal");
15026 return CONST0_RTX (tmode);
15029 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
15030 || icode == CODE_FOR_vsx_xxpermdi_v2di
15031 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
15032 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
15033 || icode == CODE_FOR_vsx_xxpermdi_v1ti
15034 || icode == CODE_FOR_vsx_xxpermdi_v4sf
15035 || icode == CODE_FOR_vsx_xxpermdi_v4si
15036 || icode == CODE_FOR_vsx_xxpermdi_v8hi
15037 || icode == CODE_FOR_vsx_xxpermdi_v16qi
15038 || icode == CODE_FOR_vsx_xxsldwi_v16qi
15039 || icode == CODE_FOR_vsx_xxsldwi_v8hi
15040 || icode == CODE_FOR_vsx_xxsldwi_v4si
15041 || icode == CODE_FOR_vsx_xxsldwi_v4sf
15042 || icode == CODE_FOR_vsx_xxsldwi_v2di
15043 || icode == CODE_FOR_vsx_xxsldwi_v2df)
15045 /* Only allow 2-bit unsigned literals. */
15047 if (TREE_CODE (arg2) != INTEGER_CST
15048 || TREE_INT_CST_LOW (arg2) & ~0x3)
15050 error ("argument 3 must be a 2-bit unsigned literal");
15051 return CONST0_RTX (tmode);
15054 else if (icode == CODE_FOR_vsx_set_v2df
15055 || icode == CODE_FOR_vsx_set_v2di
15056 || icode == CODE_FOR_bcdadd
15057 || icode == CODE_FOR_bcdadd_lt
15058 || icode == CODE_FOR_bcdadd_eq
15059 || icode == CODE_FOR_bcdadd_gt
15060 || icode == CODE_FOR_bcdsub
15061 || icode == CODE_FOR_bcdsub_lt
15062 || icode == CODE_FOR_bcdsub_eq
15063 || icode == CODE_FOR_bcdsub_gt)
15065 /* Only allow 1-bit unsigned literals. */
15067 if (TREE_CODE (arg2) != INTEGER_CST
15068 || TREE_INT_CST_LOW (arg2) & ~0x1)
15070 error ("argument 3 must be a 1-bit unsigned literal");
15071 return CONST0_RTX (tmode);
15074 else if (icode == CODE_FOR_dfp_ddedpd_dd
15075 || icode == CODE_FOR_dfp_ddedpd_td)
15077 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15079 if (TREE_CODE (arg0) != INTEGER_CST
15080 || TREE_INT_CST_LOW (arg2) & ~0x3)
15082 error ("argument 1 must be 0 or 2");
15083 return CONST0_RTX (tmode);
15086 else if (icode == CODE_FOR_dfp_denbcd_dd
15087 || icode == CODE_FOR_dfp_denbcd_td)
15089 /* Only allow 1-bit unsigned literals. */
15091 if (TREE_CODE (arg0) != INTEGER_CST
15092 || TREE_INT_CST_LOW (arg0) & ~0x1)
15094 error ("argument 1 must be a 1-bit unsigned literal");
15095 return CONST0_RTX (tmode);
15098 else if (icode == CODE_FOR_dfp_dscli_dd
15099 || icode == CODE_FOR_dfp_dscli_td
15100 || icode == CODE_FOR_dfp_dscri_dd
15101 || icode == CODE_FOR_dfp_dscri_td)
15103 /* Only allow 6-bit unsigned literals. */
15105 if (TREE_CODE (arg1) != INTEGER_CST
15106 || TREE_INT_CST_LOW (arg1) & ~0x3f)
15108 error ("argument 2 must be a 6-bit unsigned literal");
15109 return CONST0_RTX (tmode);
15112 else if (icode == CODE_FOR_crypto_vshasigmaw
15113 || icode == CODE_FOR_crypto_vshasigmad)
15115 /* Check whether the 2nd and 3rd arguments are integer constants and in
15116 range and prepare arguments. */
15118 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
15120 error ("argument 2 must be 0 or 1");
15121 return CONST0_RTX (tmode);
15125 if (TREE_CODE (arg2) != INTEGER_CST
15126 || wi::geu_p (wi::to_wide (arg2), 16))
15128 error ("argument 3 must be in the range 0..15");
15129 return CONST0_RTX (tmode);
15134 || GET_MODE (target) != tmode
15135 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15136 target = gen_reg_rtx (tmode);
15138 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15139 op0 = copy_to_mode_reg (mode0, op0);
15140 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15141 op1 = copy_to_mode_reg (mode1, op1);
15142 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15143 op2 = copy_to_mode_reg (mode2, op2);
15145 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
15146 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
15148 pat = GEN_FCN (icode) (target, op0, op1, op2);
15156 /* Expand the lvx builtins. */
15158 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
15160 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15161 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15163 machine_mode tmode, mode0;
15165 enum insn_code icode;
15169 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
15170 icode = CODE_FOR_vector_altivec_load_v16qi;
15172 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
15173 icode = CODE_FOR_vector_altivec_load_v8hi;
15175 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
15176 icode = CODE_FOR_vector_altivec_load_v4si;
15178 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
15179 icode = CODE_FOR_vector_altivec_load_v4sf;
15181 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
15182 icode = CODE_FOR_vector_altivec_load_v2df;
15184 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
15185 icode = CODE_FOR_vector_altivec_load_v2di;
15187 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
15188 icode = CODE_FOR_vector_altivec_load_v1ti;
15191 *expandedp = false;
15197 arg0 = CALL_EXPR_ARG (exp, 0);
15198 op0 = expand_normal (arg0);
15199 tmode = insn_data[icode].operand[0].mode;
15200 mode0 = insn_data[icode].operand[1].mode;
15203 || GET_MODE (target) != tmode
15204 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15205 target = gen_reg_rtx (tmode);
15207 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15208 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15210 pat = GEN_FCN (icode) (target, op0);
15217 /* Expand the stvx builtins. */
15219 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15222 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15223 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15225 machine_mode mode0, mode1;
15227 enum insn_code icode;
15231 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
15232 icode = CODE_FOR_vector_altivec_store_v16qi;
15234 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
15235 icode = CODE_FOR_vector_altivec_store_v8hi;
15237 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
15238 icode = CODE_FOR_vector_altivec_store_v4si;
15240 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
15241 icode = CODE_FOR_vector_altivec_store_v4sf;
15243 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
15244 icode = CODE_FOR_vector_altivec_store_v2df;
15246 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
15247 icode = CODE_FOR_vector_altivec_store_v2di;
15249 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
15250 icode = CODE_FOR_vector_altivec_store_v1ti;
15253 *expandedp = false;
15257 arg0 = CALL_EXPR_ARG (exp, 0);
15258 arg1 = CALL_EXPR_ARG (exp, 1);
15259 op0 = expand_normal (arg0);
15260 op1 = expand_normal (arg1);
15261 mode0 = insn_data[icode].operand[0].mode;
15262 mode1 = insn_data[icode].operand[1].mode;
15264 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15265 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15266 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15267 op1 = copy_to_mode_reg (mode1, op1);
15269 pat = GEN_FCN (icode) (op0, op1);
15277 /* Expand the dst builtins. */
15279 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15282 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15283 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15284 tree arg0, arg1, arg2;
15285 machine_mode mode0, mode1;
15286 rtx pat, op0, op1, op2;
15287 const struct builtin_description *d;
15290 *expandedp = false;
15292 /* Handle DST variants. */
15294 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
15295 if (d->code == fcode)
15297 arg0 = CALL_EXPR_ARG (exp, 0);
15298 arg1 = CALL_EXPR_ARG (exp, 1);
15299 arg2 = CALL_EXPR_ARG (exp, 2);
15300 op0 = expand_normal (arg0);
15301 op1 = expand_normal (arg1);
15302 op2 = expand_normal (arg2);
15303 mode0 = insn_data[d->icode].operand[0].mode;
15304 mode1 = insn_data[d->icode].operand[1].mode;
15306 /* Invalid arguments, bail out before generating bad rtl. */
15307 if (arg0 == error_mark_node
15308 || arg1 == error_mark_node
15309 || arg2 == error_mark_node)
15314 if (TREE_CODE (arg2) != INTEGER_CST
15315 || TREE_INT_CST_LOW (arg2) & ~0x3)
15317 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
15321 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15322 op0 = copy_to_mode_reg (Pmode, op0);
15323 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15324 op1 = copy_to_mode_reg (mode1, op1);
15326 pat = GEN_FCN (d->icode) (op0, op1, op2);
15336 /* Expand vec_init builtin. */
15338 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
15340 machine_mode tmode = TYPE_MODE (type);
15341 machine_mode inner_mode = GET_MODE_INNER (tmode);
15342 int i, n_elt = GET_MODE_NUNITS (tmode);
15344 gcc_assert (VECTOR_MODE_P (tmode));
15345 gcc_assert (n_elt == call_expr_nargs (exp));
15347 if (!target || !register_operand (target, tmode))
15348 target = gen_reg_rtx (tmode);
15350 /* If we have a vector compromised of a single element, such as V1TImode, do
15351 the initialization directly. */
15352 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
15354 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
15355 emit_move_insn (target, gen_lowpart (tmode, x));
15359 rtvec v = rtvec_alloc (n_elt);
15361 for (i = 0; i < n_elt; ++i)
15363 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
15364 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15367 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
15373 /* Return the integer constant in ARG. Constrain it to be in the range
15374 of the subparts of VEC_TYPE; issue an error if not. */
15377 get_element_number (tree vec_type, tree arg)
15379 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15381 if (!tree_fits_uhwi_p (arg)
15382 || (elt = tree_to_uhwi (arg), elt > max))
15384 error ("selector must be an integer constant in the range 0..%wi", max);
15391 /* Expand vec_set builtin. */
15393 altivec_expand_vec_set_builtin (tree exp)
15395 machine_mode tmode, mode1;
15396 tree arg0, arg1, arg2;
15400 arg0 = CALL_EXPR_ARG (exp, 0);
15401 arg1 = CALL_EXPR_ARG (exp, 1);
15402 arg2 = CALL_EXPR_ARG (exp, 2);
15404 tmode = TYPE_MODE (TREE_TYPE (arg0));
15405 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15406 gcc_assert (VECTOR_MODE_P (tmode));
15408 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
15409 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
15410 elt = get_element_number (TREE_TYPE (arg0), arg2);
15412 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15413 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15415 op0 = force_reg (tmode, op0);
15416 op1 = force_reg (mode1, op1);
15418 rs6000_expand_vector_set (op0, op1, elt);
15423 /* Expand vec_ext builtin. */
15425 altivec_expand_vec_ext_builtin (tree exp, rtx target)
15427 machine_mode tmode, mode0;
15432 arg0 = CALL_EXPR_ARG (exp, 0);
15433 arg1 = CALL_EXPR_ARG (exp, 1);
15435 op0 = expand_normal (arg0);
15436 op1 = expand_normal (arg1);
15438 /* Call get_element_number to validate arg1 if it is a constant. */
15439 if (TREE_CODE (arg1) == INTEGER_CST)
15440 (void) get_element_number (TREE_TYPE (arg0), arg1);
15442 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15443 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15444 gcc_assert (VECTOR_MODE_P (mode0));
15446 op0 = force_reg (mode0, op0);
15448 if (optimize || !target || !register_operand (target, tmode))
15449 target = gen_reg_rtx (tmode);
15451 rs6000_expand_vector_extract (target, op0, op1);
15456 /* Expand the builtin in EXP and store the result in TARGET. Store
15457 true in *EXPANDEDP if we found a builtin to expand. */
15459 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
15461 const struct builtin_description *d;
15463 enum insn_code icode;
15464 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15465 tree arg0, arg1, arg2;
15467 machine_mode tmode, mode0;
15468 enum rs6000_builtins fcode
15469 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15471 if (rs6000_overloaded_builtin_p (fcode))
15474 error ("unresolved overload for Altivec builtin %qF", fndecl);
15476 /* Given it is invalid, just generate a normal call. */
15477 return expand_call (exp, target, false);
15480 target = altivec_expand_ld_builtin (exp, target, expandedp);
15484 target = altivec_expand_st_builtin (exp, target, expandedp);
15488 target = altivec_expand_dst_builtin (exp, target, expandedp);
15496 case ALTIVEC_BUILTIN_STVX_V2DF:
15497 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
15498 case ALTIVEC_BUILTIN_STVX_V2DI:
15499 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
15500 case ALTIVEC_BUILTIN_STVX_V4SF:
15501 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
15502 case ALTIVEC_BUILTIN_STVX:
15503 case ALTIVEC_BUILTIN_STVX_V4SI:
15504 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
15505 case ALTIVEC_BUILTIN_STVX_V8HI:
15506 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
15507 case ALTIVEC_BUILTIN_STVX_V16QI:
15508 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
15509 case ALTIVEC_BUILTIN_STVEBX:
15510 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
15511 case ALTIVEC_BUILTIN_STVEHX:
15512 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
15513 case ALTIVEC_BUILTIN_STVEWX:
15514 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
15515 case ALTIVEC_BUILTIN_STVXL_V2DF:
15516 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
15517 case ALTIVEC_BUILTIN_STVXL_V2DI:
15518 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
15519 case ALTIVEC_BUILTIN_STVXL_V4SF:
15520 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
15521 case ALTIVEC_BUILTIN_STVXL:
15522 case ALTIVEC_BUILTIN_STVXL_V4SI:
15523 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
15524 case ALTIVEC_BUILTIN_STVXL_V8HI:
15525 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
15526 case ALTIVEC_BUILTIN_STVXL_V16QI:
15527 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
15529 case ALTIVEC_BUILTIN_STVLX:
15530 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
15531 case ALTIVEC_BUILTIN_STVLXL:
15532 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
15533 case ALTIVEC_BUILTIN_STVRX:
15534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
15535 case ALTIVEC_BUILTIN_STVRXL:
15536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
15538 case P9V_BUILTIN_STXVL:
15539 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
15541 case P9V_BUILTIN_XST_LEN_R:
15542 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
15544 case VSX_BUILTIN_STXVD2X_V1TI:
15545 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
15546 case VSX_BUILTIN_STXVD2X_V2DF:
15547 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
15548 case VSX_BUILTIN_STXVD2X_V2DI:
15549 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
15550 case VSX_BUILTIN_STXVW4X_V4SF:
15551 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
15552 case VSX_BUILTIN_STXVW4X_V4SI:
15553 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
15554 case VSX_BUILTIN_STXVW4X_V8HI:
15555 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
15556 case VSX_BUILTIN_STXVW4X_V16QI:
15557 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
15559 /* For the following on big endian, it's ok to use any appropriate
15560 unaligned-supporting store, so use a generic expander. For
15561 little-endian, the exact element-reversing instruction must
15563 case VSX_BUILTIN_ST_ELEMREV_V2DF:
15565 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
15566 : CODE_FOR_vsx_st_elemrev_v2df);
15567 return altivec_expand_stv_builtin (code, exp);
15569 case VSX_BUILTIN_ST_ELEMREV_V2DI:
15571 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
15572 : CODE_FOR_vsx_st_elemrev_v2di);
15573 return altivec_expand_stv_builtin (code, exp);
15575 case VSX_BUILTIN_ST_ELEMREV_V4SF:
15577 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
15578 : CODE_FOR_vsx_st_elemrev_v4sf);
15579 return altivec_expand_stv_builtin (code, exp);
15581 case VSX_BUILTIN_ST_ELEMREV_V4SI:
15583 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
15584 : CODE_FOR_vsx_st_elemrev_v4si);
15585 return altivec_expand_stv_builtin (code, exp);
15587 case VSX_BUILTIN_ST_ELEMREV_V8HI:
15589 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
15590 : CODE_FOR_vsx_st_elemrev_v8hi);
15591 return altivec_expand_stv_builtin (code, exp);
15593 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15595 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15596 : CODE_FOR_vsx_st_elemrev_v16qi);
15597 return altivec_expand_stv_builtin (code, exp);
15600 case ALTIVEC_BUILTIN_MFVSCR:
15601 icode = CODE_FOR_altivec_mfvscr;
15602 tmode = insn_data[icode].operand[0].mode;
15605 || GET_MODE (target) != tmode
15606 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15607 target = gen_reg_rtx (tmode);
15609 pat = GEN_FCN (icode) (target);
15615 case ALTIVEC_BUILTIN_MTVSCR:
15616 icode = CODE_FOR_altivec_mtvscr;
15617 arg0 = CALL_EXPR_ARG (exp, 0);
15618 op0 = expand_normal (arg0);
15619 mode0 = insn_data[icode].operand[0].mode;
15621 /* If we got invalid arguments bail out before generating bad rtl. */
15622 if (arg0 == error_mark_node)
15625 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15626 op0 = copy_to_mode_reg (mode0, op0);
15628 pat = GEN_FCN (icode) (op0);
15633 case ALTIVEC_BUILTIN_DSSALL:
15634 emit_insn (gen_altivec_dssall ());
15637 case ALTIVEC_BUILTIN_DSS:
15638 icode = CODE_FOR_altivec_dss;
15639 arg0 = CALL_EXPR_ARG (exp, 0);
15641 op0 = expand_normal (arg0);
15642 mode0 = insn_data[icode].operand[0].mode;
15644 /* If we got invalid arguments bail out before generating bad rtl. */
15645 if (arg0 == error_mark_node)
15648 if (TREE_CODE (arg0) != INTEGER_CST
15649 || TREE_INT_CST_LOW (arg0) & ~0x3)
15651 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15655 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15656 op0 = copy_to_mode_reg (mode0, op0);
15658 emit_insn (gen_altivec_dss (op0));
15661 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15662 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15663 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15664 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15665 case VSX_BUILTIN_VEC_INIT_V2DF:
15666 case VSX_BUILTIN_VEC_INIT_V2DI:
15667 case VSX_BUILTIN_VEC_INIT_V1TI:
15668 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15670 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15671 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15672 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15673 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15674 case VSX_BUILTIN_VEC_SET_V2DF:
15675 case VSX_BUILTIN_VEC_SET_V2DI:
15676 case VSX_BUILTIN_VEC_SET_V1TI:
15677 return altivec_expand_vec_set_builtin (exp);
15679 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15680 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15681 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15682 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15683 case VSX_BUILTIN_VEC_EXT_V2DF:
15684 case VSX_BUILTIN_VEC_EXT_V2DI:
15685 case VSX_BUILTIN_VEC_EXT_V1TI:
15686 return altivec_expand_vec_ext_builtin (exp, target);
15688 case P9V_BUILTIN_VEXTRACT4B:
15689 case P9V_BUILTIN_VEC_VEXTRACT4B:
15690 arg1 = CALL_EXPR_ARG (exp, 1);
15693 /* Generate a normal call if it is invalid. */
15694 if (arg1 == error_mark_node)
15695 return expand_call (exp, target, false);
15697 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15699 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15700 return expand_call (exp, target, false);
15704 case P9V_BUILTIN_VINSERT4B:
15705 case P9V_BUILTIN_VINSERT4B_DI:
15706 case P9V_BUILTIN_VEC_VINSERT4B:
15707 arg2 = CALL_EXPR_ARG (exp, 2);
15710 /* Generate a normal call if it is invalid. */
15711 if (arg2 == error_mark_node)
15712 return expand_call (exp, target, false);
15714 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15716 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15717 return expand_call (exp, target, false);
15723 /* Fall through. */
15726 /* Expand abs* operations. */
15728 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15729 if (d->code == fcode)
15730 return altivec_expand_abs_builtin (d->icode, exp, target);
15732 /* Expand the AltiVec predicates. */
15733 d = bdesc_altivec_preds;
15734 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15735 if (d->code == fcode)
15736 return altivec_expand_predicate_builtin (d->icode, exp, target);
15738 /* LV* are funky. We initialized them differently. */
15741 case ALTIVEC_BUILTIN_LVSL:
15742 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15743 exp, target, false);
15744 case ALTIVEC_BUILTIN_LVSR:
15745 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15746 exp, target, false);
15747 case ALTIVEC_BUILTIN_LVEBX:
15748 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15749 exp, target, false);
15750 case ALTIVEC_BUILTIN_LVEHX:
15751 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15752 exp, target, false);
15753 case ALTIVEC_BUILTIN_LVEWX:
15754 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15755 exp, target, false);
15756 case ALTIVEC_BUILTIN_LVXL_V2DF:
15757 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15758 exp, target, false);
15759 case ALTIVEC_BUILTIN_LVXL_V2DI:
15760 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15761 exp, target, false);
15762 case ALTIVEC_BUILTIN_LVXL_V4SF:
15763 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15764 exp, target, false);
15765 case ALTIVEC_BUILTIN_LVXL:
15766 case ALTIVEC_BUILTIN_LVXL_V4SI:
15767 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15768 exp, target, false);
15769 case ALTIVEC_BUILTIN_LVXL_V8HI:
15770 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15771 exp, target, false);
15772 case ALTIVEC_BUILTIN_LVXL_V16QI:
15773 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15774 exp, target, false);
15775 case ALTIVEC_BUILTIN_LVX_V2DF:
15776 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
15777 exp, target, false);
15778 case ALTIVEC_BUILTIN_LVX_V2DI:
15779 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
15780 exp, target, false);
15781 case ALTIVEC_BUILTIN_LVX_V4SF:
15782 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
15783 exp, target, false);
15784 case ALTIVEC_BUILTIN_LVX:
15785 case ALTIVEC_BUILTIN_LVX_V4SI:
15786 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
15787 exp, target, false);
15788 case ALTIVEC_BUILTIN_LVX_V8HI:
15789 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
15790 exp, target, false);
15791 case ALTIVEC_BUILTIN_LVX_V16QI:
15792 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
15793 exp, target, false);
15794 case ALTIVEC_BUILTIN_LVLX:
15795 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15796 exp, target, true);
15797 case ALTIVEC_BUILTIN_LVLXL:
15798 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15799 exp, target, true);
15800 case ALTIVEC_BUILTIN_LVRX:
15801 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15802 exp, target, true);
15803 case ALTIVEC_BUILTIN_LVRXL:
15804 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15805 exp, target, true);
15806 case VSX_BUILTIN_LXVD2X_V1TI:
15807 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15808 exp, target, false);
15809 case VSX_BUILTIN_LXVD2X_V2DF:
15810 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15811 exp, target, false);
15812 case VSX_BUILTIN_LXVD2X_V2DI:
15813 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15814 exp, target, false);
15815 case VSX_BUILTIN_LXVW4X_V4SF:
15816 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15817 exp, target, false);
15818 case VSX_BUILTIN_LXVW4X_V4SI:
15819 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15820 exp, target, false);
15821 case VSX_BUILTIN_LXVW4X_V8HI:
15822 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15823 exp, target, false);
15824 case VSX_BUILTIN_LXVW4X_V16QI:
15825 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15826 exp, target, false);
15827 /* For the following on big endian, it's ok to use any appropriate
15828 unaligned-supporting load, so use a generic expander. For
15829 little-endian, the exact element-reversing instruction must
15831 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15833 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15834 : CODE_FOR_vsx_ld_elemrev_v2df);
15835 return altivec_expand_lv_builtin (code, exp, target, false);
15837 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15839 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15840 : CODE_FOR_vsx_ld_elemrev_v2di);
15841 return altivec_expand_lv_builtin (code, exp, target, false);
15843 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15845 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15846 : CODE_FOR_vsx_ld_elemrev_v4sf);
15847 return altivec_expand_lv_builtin (code, exp, target, false);
15849 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15851 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15852 : CODE_FOR_vsx_ld_elemrev_v4si);
15853 return altivec_expand_lv_builtin (code, exp, target, false);
15855 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15857 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15858 : CODE_FOR_vsx_ld_elemrev_v8hi);
15859 return altivec_expand_lv_builtin (code, exp, target, false);
15861 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15863 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15864 : CODE_FOR_vsx_ld_elemrev_v16qi);
15865 return altivec_expand_lv_builtin (code, exp, target, false);
15870 /* Fall through. */
15873 *expandedp = false;
15877 /* Expand the builtin in EXP and store the result in TARGET. Store
15878 true in *EXPANDEDP if we found a builtin to expand. */
15880 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
15882 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15883 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15884 const struct builtin_description *d;
15891 case PAIRED_BUILTIN_STX:
15892 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
15893 case PAIRED_BUILTIN_LX:
15894 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
15897 /* Fall through. */
15900 /* Expand the paired predicates. */
15901 d = bdesc_paired_preds;
15902 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
15903 if (d->code == fcode)
15904 return paired_expand_predicate_builtin (d->icode, exp, target);
15906 *expandedp = false;
15911 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
15913 rtx pat, scratch, tmp;
15914 tree form = CALL_EXPR_ARG (exp, 0);
15915 tree arg0 = CALL_EXPR_ARG (exp, 1);
15916 tree arg1 = CALL_EXPR_ARG (exp, 2);
15917 rtx op0 = expand_normal (arg0);
15918 rtx op1 = expand_normal (arg1);
15919 machine_mode mode0 = insn_data[icode].operand[1].mode;
15920 machine_mode mode1 = insn_data[icode].operand[2].mode;
15922 enum rtx_code code;
15924 if (TREE_CODE (form) != INTEGER_CST)
15926 error ("argument 1 of %s must be a constant",
15927 "__builtin_paired_predicate");
15931 form_int = TREE_INT_CST_LOW (form);
15933 gcc_assert (mode0 == mode1);
15935 if (arg0 == error_mark_node || arg1 == error_mark_node)
15939 || GET_MODE (target) != SImode
15940 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
15941 target = gen_reg_rtx (SImode);
15942 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15943 op0 = copy_to_mode_reg (mode0, op0);
15944 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
15945 op1 = copy_to_mode_reg (mode1, op1);
15947 scratch = gen_reg_rtx (CCFPmode);
15949 pat = GEN_FCN (icode) (scratch, op0, op1);
15971 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
15974 error ("argument 1 of %qs is out of range",
15975 "__builtin_paired_predicate");
15979 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
15980 emit_move_insn (target, tmp);
15984 /* Raise an error message for a builtin function that is called without the
15985 appropriate target options being set. */
15988 rs6000_invalid_builtin (enum rs6000_builtins fncode)
15990 size_t uns_fncode = (size_t) fncode;
15991 const char *name = rs6000_builtin_info[uns_fncode].name;
15992 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
15994 gcc_assert (name != NULL);
15995 if ((fnmask & RS6000_BTM_CELL) != 0)
15996 error ("builtin function %qs is only valid for the cell processor", name);
15997 else if ((fnmask & RS6000_BTM_VSX) != 0)
15998 error ("builtin function %qs requires the %qs option", name, "-mvsx");
15999 else if ((fnmask & RS6000_BTM_HTM) != 0)
16000 error ("builtin function %qs requires the %qs option", name, "-mhtm");
16001 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
16002 error ("builtin function %qs requires the %qs option", name, "-maltivec");
16003 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
16004 error ("builtin function %qs requires the %qs option", name, "-mpaired");
16005 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16006 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16007 error ("builtin function %qs requires the %qs and %qs options",
16008 name, "-mhard-dfp", "-mpower8-vector");
16009 else if ((fnmask & RS6000_BTM_DFP) != 0)
16010 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
16011 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
16012 error ("builtin function %qs requires the %qs option", name,
16013 "-mpower8-vector");
16014 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16015 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16016 error ("builtin function %qs requires the %qs and %qs options",
16017 name, "-mcpu=power9", "-m64");
16018 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
16019 error ("builtin function %qs requires the %qs option", name,
16021 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16022 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16023 error ("builtin function %qs requires the %qs and %qs options",
16024 name, "-mcpu=power9", "-m64");
16025 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
16026 error ("builtin function %qs requires the %qs option", name,
16028 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16029 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16030 error ("builtin function %qs requires the %qs and %qs options",
16031 name, "-mhard-float", "-mlong-double-128");
16032 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
16033 error ("builtin function %qs requires the %qs option", name,
16035 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
16036 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
16038 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
16039 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
16041 error ("builtin function %qs is not supported with the current options",
16045 /* Target hook for early folding of built-ins, shamelessly stolen
16049 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
16050 int n_args ATTRIBUTE_UNUSED,
16051 tree *args ATTRIBUTE_UNUSED,
16052 bool ignore ATTRIBUTE_UNUSED)
16054 #ifdef SUBTARGET_FOLD_BUILTIN
16055 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
16061 /* Helper function to sort out which built-ins may be valid without having
16064 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
16068 case ALTIVEC_BUILTIN_STVX_V16QI:
16069 case ALTIVEC_BUILTIN_STVX_V8HI:
16070 case ALTIVEC_BUILTIN_STVX_V4SI:
16071 case ALTIVEC_BUILTIN_STVX_V4SF:
16072 case ALTIVEC_BUILTIN_STVX_V2DI:
16073 case ALTIVEC_BUILTIN_STVX_V2DF:
16080 /* Helper function to handle the gimple folding of a vector compare
16081 operation. This sets up true/false vectors, and uses the
16082 VEC_COND_EXPR operation.
16083 CODE indicates which comparison is to be made. (EQ, GT, ...).
16084 TYPE indicates the type of the result. */
16086 fold_build_vec_cmp (tree_code code, tree type,
16087 tree arg0, tree arg1)
16089 tree cmp_type = build_same_sized_truth_vector_type (type);
16090 tree zero_vec = build_zero_cst (type);
16091 tree minus_one_vec = build_minus_one_cst (type);
16092 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
16093 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
16096 /* Helper function to handle the in-between steps for the
16097 vector compare built-ins. */
16099 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
16101 tree arg0 = gimple_call_arg (stmt, 0);
16102 tree arg1 = gimple_call_arg (stmt, 1);
16103 tree lhs = gimple_call_lhs (stmt);
16104 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
16105 gimple *g = gimple_build_assign (lhs, cmp);
16106 gimple_set_location (g, gimple_location (stmt));
16107 gsi_replace (gsi, g, true);
16110 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16111 a constant, use rs6000_fold_builtin.) */
16114 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
16116 gimple *stmt = gsi_stmt (*gsi);
16117 tree fndecl = gimple_call_fndecl (stmt);
16118 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
16119 enum rs6000_builtins fn_code
16120 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16121 tree arg0, arg1, lhs, temp;
16124 size_t uns_fncode = (size_t) fn_code;
16125 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
16126 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
16127 const char *fn_name2 = (icode != CODE_FOR_nothing)
16128 ? get_insn_name ((int) icode)
16131 if (TARGET_DEBUG_BUILTIN)
16132 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
16133 fn_code, fn_name1, fn_name2);
16135 if (!rs6000_fold_gimple)
16138 /* Prevent gimple folding for code that does not have a LHS, unless it is
16139 allowed per the rs6000_builtin_valid_without_lhs helper function. */
16140 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
16143 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
16144 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
16145 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
16151 /* Flavors of vec_add. We deliberately don't expand
16152 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16153 TImode, resulting in much poorer code generation. */
16154 case ALTIVEC_BUILTIN_VADDUBM:
16155 case ALTIVEC_BUILTIN_VADDUHM:
16156 case ALTIVEC_BUILTIN_VADDUWM:
16157 case P8V_BUILTIN_VADDUDM:
16158 case ALTIVEC_BUILTIN_VADDFP:
16159 case VSX_BUILTIN_XVADDDP:
16160 arg0 = gimple_call_arg (stmt, 0);
16161 arg1 = gimple_call_arg (stmt, 1);
16162 lhs = gimple_call_lhs (stmt);
16163 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
16164 gimple_set_location (g, gimple_location (stmt));
16165 gsi_replace (gsi, g, true);
16167 /* Flavors of vec_sub. We deliberately don't expand
16168 P8V_BUILTIN_VSUBUQM. */
16169 case ALTIVEC_BUILTIN_VSUBUBM:
16170 case ALTIVEC_BUILTIN_VSUBUHM:
16171 case ALTIVEC_BUILTIN_VSUBUWM:
16172 case P8V_BUILTIN_VSUBUDM:
16173 case ALTIVEC_BUILTIN_VSUBFP:
16174 case VSX_BUILTIN_XVSUBDP:
16175 arg0 = gimple_call_arg (stmt, 0);
16176 arg1 = gimple_call_arg (stmt, 1);
16177 lhs = gimple_call_lhs (stmt);
16178 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
16179 gimple_set_location (g, gimple_location (stmt));
16180 gsi_replace (gsi, g, true);
16182 case VSX_BUILTIN_XVMULSP:
16183 case VSX_BUILTIN_XVMULDP:
16184 arg0 = gimple_call_arg (stmt, 0);
16185 arg1 = gimple_call_arg (stmt, 1);
16186 lhs = gimple_call_lhs (stmt);
16187 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
16188 gimple_set_location (g, gimple_location (stmt));
16189 gsi_replace (gsi, g, true);
16191 /* Even element flavors of vec_mul (signed). */
16192 case ALTIVEC_BUILTIN_VMULESB:
16193 case ALTIVEC_BUILTIN_VMULESH:
16194 case ALTIVEC_BUILTIN_VMULESW:
16195 /* Even element flavors of vec_mul (unsigned). */
16196 case ALTIVEC_BUILTIN_VMULEUB:
16197 case ALTIVEC_BUILTIN_VMULEUH:
16198 case ALTIVEC_BUILTIN_VMULEUW:
16199 arg0 = gimple_call_arg (stmt, 0);
16200 arg1 = gimple_call_arg (stmt, 1);
16201 lhs = gimple_call_lhs (stmt);
16202 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
16203 gimple_set_location (g, gimple_location (stmt));
16204 gsi_replace (gsi, g, true);
16206 /* Odd element flavors of vec_mul (signed). */
16207 case ALTIVEC_BUILTIN_VMULOSB:
16208 case ALTIVEC_BUILTIN_VMULOSH:
16209 case ALTIVEC_BUILTIN_VMULOSW:
16210 /* Odd element flavors of vec_mul (unsigned). */
16211 case ALTIVEC_BUILTIN_VMULOUB:
16212 case ALTIVEC_BUILTIN_VMULOUH:
16213 case ALTIVEC_BUILTIN_VMULOUW:
16214 arg0 = gimple_call_arg (stmt, 0);
16215 arg1 = gimple_call_arg (stmt, 1);
16216 lhs = gimple_call_lhs (stmt);
16217 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
16218 gimple_set_location (g, gimple_location (stmt));
16219 gsi_replace (gsi, g, true);
16221 /* Flavors of vec_div (Integer). */
16222 case VSX_BUILTIN_DIV_V2DI:
16223 case VSX_BUILTIN_UDIV_V2DI:
16224 arg0 = gimple_call_arg (stmt, 0);
16225 arg1 = gimple_call_arg (stmt, 1);
16226 lhs = gimple_call_lhs (stmt);
16227 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
16228 gimple_set_location (g, gimple_location (stmt));
16229 gsi_replace (gsi, g, true);
16231 /* Flavors of vec_div (Float). */
16232 case VSX_BUILTIN_XVDIVSP:
16233 case VSX_BUILTIN_XVDIVDP:
16234 arg0 = gimple_call_arg (stmt, 0);
16235 arg1 = gimple_call_arg (stmt, 1);
16236 lhs = gimple_call_lhs (stmt);
16237 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
16238 gimple_set_location (g, gimple_location (stmt));
16239 gsi_replace (gsi, g, true);
16241 /* Flavors of vec_and. */
16242 case ALTIVEC_BUILTIN_VAND:
16243 arg0 = gimple_call_arg (stmt, 0);
16244 arg1 = gimple_call_arg (stmt, 1);
16245 lhs = gimple_call_lhs (stmt);
16246 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
16247 gimple_set_location (g, gimple_location (stmt));
16248 gsi_replace (gsi, g, true);
16250 /* Flavors of vec_andc. */
16251 case ALTIVEC_BUILTIN_VANDC:
16252 arg0 = gimple_call_arg (stmt, 0);
16253 arg1 = gimple_call_arg (stmt, 1);
16254 lhs = gimple_call_lhs (stmt);
16255 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16256 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16257 gimple_set_location (g, gimple_location (stmt));
16258 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16259 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
16260 gimple_set_location (g, gimple_location (stmt));
16261 gsi_replace (gsi, g, true);
16263 /* Flavors of vec_nand. */
16264 case P8V_BUILTIN_VEC_NAND:
16265 case P8V_BUILTIN_NAND_V16QI:
16266 case P8V_BUILTIN_NAND_V8HI:
16267 case P8V_BUILTIN_NAND_V4SI:
16268 case P8V_BUILTIN_NAND_V4SF:
16269 case P8V_BUILTIN_NAND_V2DF:
16270 case P8V_BUILTIN_NAND_V2DI:
16271 arg0 = gimple_call_arg (stmt, 0);
16272 arg1 = gimple_call_arg (stmt, 1);
16273 lhs = gimple_call_lhs (stmt);
16274 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16275 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
16276 gimple_set_location (g, gimple_location (stmt));
16277 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16278 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16279 gimple_set_location (g, gimple_location (stmt));
16280 gsi_replace (gsi, g, true);
16282 /* Flavors of vec_or. */
16283 case ALTIVEC_BUILTIN_VOR:
16284 arg0 = gimple_call_arg (stmt, 0);
16285 arg1 = gimple_call_arg (stmt, 1);
16286 lhs = gimple_call_lhs (stmt);
16287 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
16288 gimple_set_location (g, gimple_location (stmt));
16289 gsi_replace (gsi, g, true);
16291 /* flavors of vec_orc. */
16292 case P8V_BUILTIN_ORC_V16QI:
16293 case P8V_BUILTIN_ORC_V8HI:
16294 case P8V_BUILTIN_ORC_V4SI:
16295 case P8V_BUILTIN_ORC_V4SF:
16296 case P8V_BUILTIN_ORC_V2DF:
16297 case P8V_BUILTIN_ORC_V2DI:
16298 arg0 = gimple_call_arg (stmt, 0);
16299 arg1 = gimple_call_arg (stmt, 1);
16300 lhs = gimple_call_lhs (stmt);
16301 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16302 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16303 gimple_set_location (g, gimple_location (stmt));
16304 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16305 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
16306 gimple_set_location (g, gimple_location (stmt));
16307 gsi_replace (gsi, g, true);
16309 /* Flavors of vec_xor. */
16310 case ALTIVEC_BUILTIN_VXOR:
16311 arg0 = gimple_call_arg (stmt, 0);
16312 arg1 = gimple_call_arg (stmt, 1);
16313 lhs = gimple_call_lhs (stmt);
16314 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
16315 gimple_set_location (g, gimple_location (stmt));
16316 gsi_replace (gsi, g, true);
16318 /* Flavors of vec_nor. */
16319 case ALTIVEC_BUILTIN_VNOR:
16320 arg0 = gimple_call_arg (stmt, 0);
16321 arg1 = gimple_call_arg (stmt, 1);
16322 lhs = gimple_call_lhs (stmt);
16323 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16324 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
16325 gimple_set_location (g, gimple_location (stmt));
16326 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16327 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16328 gimple_set_location (g, gimple_location (stmt));
16329 gsi_replace (gsi, g, true);
16331 /* flavors of vec_abs. */
16332 case ALTIVEC_BUILTIN_ABS_V16QI:
16333 case ALTIVEC_BUILTIN_ABS_V8HI:
16334 case ALTIVEC_BUILTIN_ABS_V4SI:
16335 case ALTIVEC_BUILTIN_ABS_V4SF:
16336 case P8V_BUILTIN_ABS_V2DI:
16337 case VSX_BUILTIN_XVABSDP:
16338 arg0 = gimple_call_arg (stmt, 0);
16339 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16340 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16342 lhs = gimple_call_lhs (stmt);
16343 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
16344 gimple_set_location (g, gimple_location (stmt));
16345 gsi_replace (gsi, g, true);
16347 /* flavors of vec_min. */
16348 case VSX_BUILTIN_XVMINDP:
16349 case P8V_BUILTIN_VMINSD:
16350 case P8V_BUILTIN_VMINUD:
16351 case ALTIVEC_BUILTIN_VMINSB:
16352 case ALTIVEC_BUILTIN_VMINSH:
16353 case ALTIVEC_BUILTIN_VMINSW:
16354 case ALTIVEC_BUILTIN_VMINUB:
16355 case ALTIVEC_BUILTIN_VMINUH:
16356 case ALTIVEC_BUILTIN_VMINUW:
16357 case ALTIVEC_BUILTIN_VMINFP:
16358 arg0 = gimple_call_arg (stmt, 0);
16359 arg1 = gimple_call_arg (stmt, 1);
16360 lhs = gimple_call_lhs (stmt);
16361 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
16362 gimple_set_location (g, gimple_location (stmt));
16363 gsi_replace (gsi, g, true);
16365 /* flavors of vec_max. */
16366 case VSX_BUILTIN_XVMAXDP:
16367 case P8V_BUILTIN_VMAXSD:
16368 case P8V_BUILTIN_VMAXUD:
16369 case ALTIVEC_BUILTIN_VMAXSB:
16370 case ALTIVEC_BUILTIN_VMAXSH:
16371 case ALTIVEC_BUILTIN_VMAXSW:
16372 case ALTIVEC_BUILTIN_VMAXUB:
16373 case ALTIVEC_BUILTIN_VMAXUH:
16374 case ALTIVEC_BUILTIN_VMAXUW:
16375 case ALTIVEC_BUILTIN_VMAXFP:
16376 arg0 = gimple_call_arg (stmt, 0);
16377 arg1 = gimple_call_arg (stmt, 1);
16378 lhs = gimple_call_lhs (stmt);
16379 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
16380 gimple_set_location (g, gimple_location (stmt));
16381 gsi_replace (gsi, g, true);
16383 /* Flavors of vec_eqv. */
16384 case P8V_BUILTIN_EQV_V16QI:
16385 case P8V_BUILTIN_EQV_V8HI:
16386 case P8V_BUILTIN_EQV_V4SI:
16387 case P8V_BUILTIN_EQV_V4SF:
16388 case P8V_BUILTIN_EQV_V2DF:
16389 case P8V_BUILTIN_EQV_V2DI:
16390 arg0 = gimple_call_arg (stmt, 0);
16391 arg1 = gimple_call_arg (stmt, 1);
16392 lhs = gimple_call_lhs (stmt);
16393 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16394 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
16395 gimple_set_location (g, gimple_location (stmt));
16396 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16397 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16398 gimple_set_location (g, gimple_location (stmt));
16399 gsi_replace (gsi, g, true);
16401 /* Flavors of vec_rotate_left. */
16402 case ALTIVEC_BUILTIN_VRLB:
16403 case ALTIVEC_BUILTIN_VRLH:
16404 case ALTIVEC_BUILTIN_VRLW:
16405 case P8V_BUILTIN_VRLD:
16406 arg0 = gimple_call_arg (stmt, 0);
16407 arg1 = gimple_call_arg (stmt, 1);
16408 lhs = gimple_call_lhs (stmt);
16409 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
16410 gimple_set_location (g, gimple_location (stmt));
16411 gsi_replace (gsi, g, true);
16413 /* Flavors of vector shift right algebraic.
16414 vec_sra{b,h,w} -> vsra{b,h,w}. */
16415 case ALTIVEC_BUILTIN_VSRAB:
16416 case ALTIVEC_BUILTIN_VSRAH:
16417 case ALTIVEC_BUILTIN_VSRAW:
16418 case P8V_BUILTIN_VSRAD:
16419 arg0 = gimple_call_arg (stmt, 0);
16420 arg1 = gimple_call_arg (stmt, 1);
16421 lhs = gimple_call_lhs (stmt);
16422 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
16423 gimple_set_location (g, gimple_location (stmt));
16424 gsi_replace (gsi, g, true);
16426 /* Flavors of vector shift left.
16427 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16428 case ALTIVEC_BUILTIN_VSLB:
16429 case ALTIVEC_BUILTIN_VSLH:
16430 case ALTIVEC_BUILTIN_VSLW:
16431 case P8V_BUILTIN_VSLD:
16432 arg0 = gimple_call_arg (stmt, 0);
16433 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16434 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16436 arg1 = gimple_call_arg (stmt, 1);
16437 lhs = gimple_call_lhs (stmt);
16438 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
16439 gimple_set_location (g, gimple_location (stmt));
16440 gsi_replace (gsi, g, true);
16442 /* Flavors of vector shift right. */
16443 case ALTIVEC_BUILTIN_VSRB:
16444 case ALTIVEC_BUILTIN_VSRH:
16445 case ALTIVEC_BUILTIN_VSRW:
16446 case P8V_BUILTIN_VSRD:
16448 arg0 = gimple_call_arg (stmt, 0);
16449 arg1 = gimple_call_arg (stmt, 1);
16450 lhs = gimple_call_lhs (stmt);
16451 gimple_seq stmts = NULL;
16452 /* Convert arg0 to unsigned. */
16454 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
16455 unsigned_type_for (TREE_TYPE (arg0)), arg0);
16457 = gimple_build (&stmts, RSHIFT_EXPR,
16458 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
16459 /* Convert result back to the lhs type. */
16460 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
16461 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16462 update_call_from_tree (gsi, res);
16465 /* Vector loads. */
16466 case ALTIVEC_BUILTIN_LVX_V16QI:
16467 case ALTIVEC_BUILTIN_LVX_V8HI:
16468 case ALTIVEC_BUILTIN_LVX_V4SI:
16469 case ALTIVEC_BUILTIN_LVX_V4SF:
16470 case ALTIVEC_BUILTIN_LVX_V2DI:
16471 case ALTIVEC_BUILTIN_LVX_V2DF:
16473 arg0 = gimple_call_arg (stmt, 0); // offset
16474 arg1 = gimple_call_arg (stmt, 1); // address
16475 /* Do not fold for -maltivec=be on LE targets. */
16476 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16478 lhs = gimple_call_lhs (stmt);
16479 location_t loc = gimple_location (stmt);
16480 /* Since arg1 may be cast to a different type, just use ptr_type_node
16481 here instead of trying to enforce TBAA on pointer types. */
16482 tree arg1_type = ptr_type_node;
16483 tree lhs_type = TREE_TYPE (lhs);
16484 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16485 the tree using the value from arg0. The resulting type will match
16486 the type of arg1. */
16487 gimple_seq stmts = NULL;
16488 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
16489 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16490 arg1_type, arg1, temp_offset);
16491 /* Mask off any lower bits from the address. */
16492 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16493 arg1_type, temp_addr,
16494 build_int_cst (arg1_type, -16));
16495 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16496 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16497 take an offset, but since we've already incorporated the offset
16498 above, here we just pass in a zero. */
16500 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
16501 build_int_cst (arg1_type, 0)));
16502 gimple_set_location (g, loc);
16503 gsi_replace (gsi, g, true);
16506 /* Vector stores. */
16507 case ALTIVEC_BUILTIN_STVX_V16QI:
16508 case ALTIVEC_BUILTIN_STVX_V8HI:
16509 case ALTIVEC_BUILTIN_STVX_V4SI:
16510 case ALTIVEC_BUILTIN_STVX_V4SF:
16511 case ALTIVEC_BUILTIN_STVX_V2DI:
16512 case ALTIVEC_BUILTIN_STVX_V2DF:
16514 /* Do not fold for -maltivec=be on LE targets. */
16515 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16517 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
16518 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
16519 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
16520 location_t loc = gimple_location (stmt);
16521 tree arg0_type = TREE_TYPE (arg0);
16522 /* Use ptr_type_node (no TBAA) for the arg2_type.
16523 FIXME: (Richard) "A proper fix would be to transition this type as
16524 seen from the frontend to GIMPLE, for example in a similar way we
16525 do for MEM_REFs by piggy-backing that on an extra argument, a
16526 constant zero pointer of the alias pointer type to use (which would
16527 also serve as a type indicator of the store itself). I'd use a
16528 target specific internal function for this (not sure if we can have
16529 those target specific, but I guess if it's folded away then that's
16530 fine) and get away with the overload set." */
16531 tree arg2_type = ptr_type_node;
16532 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16533 the tree using the value from arg0. The resulting type will match
16534 the type of arg2. */
16535 gimple_seq stmts = NULL;
16536 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
16537 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16538 arg2_type, arg2, temp_offset);
16539 /* Mask off any lower bits from the address. */
16540 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16541 arg2_type, temp_addr,
16542 build_int_cst (arg2_type, -16));
16543 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16544 /* The desired gimple result should be similar to:
16545 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
16547 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
16548 build_int_cst (arg2_type, 0)), arg0);
16549 gimple_set_location (g, loc);
16550 gsi_replace (gsi, g, true);
16554 /* Vector Fused multiply-add (fma). */
16555 case ALTIVEC_BUILTIN_VMADDFP:
16556 case VSX_BUILTIN_XVMADDDP:
16557 case ALTIVEC_BUILTIN_VMLADDUHM:
16559 arg0 = gimple_call_arg (stmt, 0);
16560 arg1 = gimple_call_arg (stmt, 1);
16561 tree arg2 = gimple_call_arg (stmt, 2);
16562 lhs = gimple_call_lhs (stmt);
16563 gimple *g = gimple_build_assign (lhs, FMA_EXPR, arg0, arg1, arg2);
16564 gimple_set_location (g, gimple_location (stmt));
16565 gsi_replace (gsi, g, true);
16569 /* Vector compares; EQ, NE, GE, GT, LE. */
16570 case ALTIVEC_BUILTIN_VCMPEQUB:
16571 case ALTIVEC_BUILTIN_VCMPEQUH:
16572 case ALTIVEC_BUILTIN_VCMPEQUW:
16573 case P8V_BUILTIN_VCMPEQUD:
16574 fold_compare_helper (gsi, EQ_EXPR, stmt);
16577 case P9V_BUILTIN_CMPNEB:
16578 case P9V_BUILTIN_CMPNEH:
16579 case P9V_BUILTIN_CMPNEW:
16580 fold_compare_helper (gsi, NE_EXPR, stmt);
16583 case VSX_BUILTIN_CMPGE_16QI:
16584 case VSX_BUILTIN_CMPGE_U16QI:
16585 case VSX_BUILTIN_CMPGE_8HI:
16586 case VSX_BUILTIN_CMPGE_U8HI:
16587 case VSX_BUILTIN_CMPGE_4SI:
16588 case VSX_BUILTIN_CMPGE_U4SI:
16589 case VSX_BUILTIN_CMPGE_2DI:
16590 case VSX_BUILTIN_CMPGE_U2DI:
16591 fold_compare_helper (gsi, GE_EXPR, stmt);
16594 case ALTIVEC_BUILTIN_VCMPGTSB:
16595 case ALTIVEC_BUILTIN_VCMPGTUB:
16596 case ALTIVEC_BUILTIN_VCMPGTSH:
16597 case ALTIVEC_BUILTIN_VCMPGTUH:
16598 case ALTIVEC_BUILTIN_VCMPGTSW:
16599 case ALTIVEC_BUILTIN_VCMPGTUW:
16600 case P8V_BUILTIN_VCMPGTUD:
16601 case P8V_BUILTIN_VCMPGTSD:
16602 fold_compare_helper (gsi, GT_EXPR, stmt);
16605 case VSX_BUILTIN_CMPLE_16QI:
16606 case VSX_BUILTIN_CMPLE_U16QI:
16607 case VSX_BUILTIN_CMPLE_8HI:
16608 case VSX_BUILTIN_CMPLE_U8HI:
16609 case VSX_BUILTIN_CMPLE_4SI:
16610 case VSX_BUILTIN_CMPLE_U4SI:
16611 case VSX_BUILTIN_CMPLE_2DI:
16612 case VSX_BUILTIN_CMPLE_U2DI:
16613 fold_compare_helper (gsi, LE_EXPR, stmt);
16616 /* flavors of vec_splat_[us]{8,16,32}. */
16617 case ALTIVEC_BUILTIN_VSPLTISB:
16618 case ALTIVEC_BUILTIN_VSPLTISH:
16619 case ALTIVEC_BUILTIN_VSPLTISW:
16621 arg0 = gimple_call_arg (stmt, 0);
16622 lhs = gimple_call_lhs (stmt);
16623 /* Only fold the vec_splat_*() if arg0 is constant. */
16624 if (TREE_CODE (arg0) != INTEGER_CST)
16626 gimple_seq stmts = NULL;
16627 location_t loc = gimple_location (stmt);
16628 tree splat_value = gimple_convert (&stmts, loc,
16629 TREE_TYPE (TREE_TYPE (lhs)), arg0);
16630 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16631 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
16632 g = gimple_build_assign (lhs, splat_tree);
16633 gimple_set_location (g, gimple_location (stmt));
16634 gsi_replace (gsi, g, true);
16639 if (TARGET_DEBUG_BUILTIN)
16640 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16641 fn_code, fn_name1, fn_name2);
16648 /* Expand an expression EXP that calls a built-in function,
16649 with result going to TARGET if that's convenient
16650 (and in mode MODE if that's convenient).
16651 SUBTARGET may be used as the target for computing one of EXP's operands.
16652 IGNORE is nonzero if the value is to be ignored. */
16655 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16656 machine_mode mode ATTRIBUTE_UNUSED,
16657 int ignore ATTRIBUTE_UNUSED)
16659 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16660 enum rs6000_builtins fcode
16661 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16662 size_t uns_fcode = (size_t)fcode;
16663 const struct builtin_description *d;
16667 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16668 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16669 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16671 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16672 floating point type, depending on whether long double is the IBM extended
16673 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16674 we only define one variant of the built-in function, and switch the code
16675 when defining it, rather than defining two built-ins and using the
16676 overload table in rs6000-c.c to switch between the two. If we don't have
16677 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16678 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16679 #ifdef HAVE_AS_POWER9
16680 if (FLOAT128_IEEE_P (TFmode))
16686 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16687 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16688 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16689 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16690 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16691 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16692 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16693 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16694 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16695 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16696 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16697 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16698 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16702 if (TARGET_DEBUG_BUILTIN)
16704 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16705 const char *name2 = (icode != CODE_FOR_nothing)
16706 ? get_insn_name ((int) icode)
16710 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16712 default: name3 = "unknown"; break;
16713 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16714 case RS6000_BTC_UNARY: name3 = "unary"; break;
16715 case RS6000_BTC_BINARY: name3 = "binary"; break;
16716 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16717 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16718 case RS6000_BTC_ABS: name3 = "abs"; break;
16719 case RS6000_BTC_DST: name3 = "dst"; break;
16724 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16725 (name1) ? name1 : "---", fcode,
16726 (name2) ? name2 : "---", (int) icode,
16728 func_valid_p ? "" : ", not valid");
16733 rs6000_invalid_builtin (fcode);
16735 /* Given it is invalid, just generate a normal call. */
16736 return expand_call (exp, target, ignore);
16741 case RS6000_BUILTIN_RECIP:
16742 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16744 case RS6000_BUILTIN_RECIPF:
16745 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16747 case RS6000_BUILTIN_RSQRTF:
16748 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16750 case RS6000_BUILTIN_RSQRT:
16751 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16753 case POWER7_BUILTIN_BPERMD:
16754 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16755 ? CODE_FOR_bpermd_di
16756 : CODE_FOR_bpermd_si), exp, target);
16758 case RS6000_BUILTIN_GET_TB:
16759 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16762 case RS6000_BUILTIN_MFTB:
16763 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16764 ? CODE_FOR_rs6000_mftb_di
16765 : CODE_FOR_rs6000_mftb_si),
16768 case RS6000_BUILTIN_MFFS:
16769 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16771 case RS6000_BUILTIN_MTFSF:
16772 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16774 case RS6000_BUILTIN_CPU_INIT:
16775 case RS6000_BUILTIN_CPU_IS:
16776 case RS6000_BUILTIN_CPU_SUPPORTS:
16777 return cpu_expand_builtin (fcode, exp, target);
16779 case MISC_BUILTIN_SPEC_BARRIER:
16781 emit_insn (gen_rs6000_speculation_barrier ());
16785 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16786 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16788 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16789 : (int) CODE_FOR_altivec_lvsl_direct);
16790 machine_mode tmode = insn_data[icode2].operand[0].mode;
16791 machine_mode mode = insn_data[icode2].operand[1].mode;
16795 gcc_assert (TARGET_ALTIVEC);
16797 arg = CALL_EXPR_ARG (exp, 0);
16798 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16799 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16800 addr = memory_address (mode, op);
16801 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16805 /* For the load case need to negate the address. */
16806 op = gen_reg_rtx (GET_MODE (addr));
16807 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16809 op = gen_rtx_MEM (mode, op);
16812 || GET_MODE (target) != tmode
16813 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16814 target = gen_reg_rtx (tmode);
16816 pat = GEN_FCN (icode2) (target, op);
16824 case ALTIVEC_BUILTIN_VCFUX:
16825 case ALTIVEC_BUILTIN_VCFSX:
16826 case ALTIVEC_BUILTIN_VCTUXS:
16827 case ALTIVEC_BUILTIN_VCTSXS:
16828 /* FIXME: There's got to be a nicer way to handle this case than
16829 constructing a new CALL_EXPR. */
16830 if (call_expr_nargs (exp) == 1)
16832 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16833 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16841 if (TARGET_ALTIVEC)
16843 ret = altivec_expand_builtin (exp, target, &success);
16848 if (TARGET_PAIRED_FLOAT)
16850 ret = paired_expand_builtin (exp, target, &success);
16857 ret = htm_expand_builtin (exp, target, &success);
16863 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16864 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16865 gcc_assert (attr == RS6000_BTC_UNARY
16866 || attr == RS6000_BTC_BINARY
16867 || attr == RS6000_BTC_TERNARY
16868 || attr == RS6000_BTC_SPECIAL);
16870 /* Handle simple unary operations. */
16872 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16873 if (d->code == fcode)
16874 return rs6000_expand_unop_builtin (icode, exp, target);
16876 /* Handle simple binary operations. */
16878 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16879 if (d->code == fcode)
16880 return rs6000_expand_binop_builtin (icode, exp, target);
16882 /* Handle simple ternary operations. */
16884 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16885 if (d->code == fcode)
16886 return rs6000_expand_ternop_builtin (icode, exp, target);
16888 /* Handle simple no-argument operations. */
16890 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16891 if (d->code == fcode)
16892 return rs6000_expand_zeroop_builtin (icode, target);
16894 gcc_unreachable ();
16897 /* Create a builtin vector type with a name. Taking care not to give
16898 the canonical type a name. */
16901 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16903 tree result = build_vector_type (elt_type, num_elts);
16905 /* Copy so we don't give the canonical type a name. */
16906 result = build_variant_type_copy (result);
16908 add_builtin_type (name, result);
16914 rs6000_init_builtins (void)
16920 if (TARGET_DEBUG_BUILTIN)
16921 fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
16922 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
16923 (TARGET_ALTIVEC) ? ", altivec" : "",
16924 (TARGET_VSX) ? ", vsx" : "");
16926 V2SI_type_node = build_vector_type (intSI_type_node, 2);
16927 V2SF_type_node = build_vector_type (float_type_node, 2);
16928 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16929 : "__vector long long",
16930 intDI_type_node, 2);
16931 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16932 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16933 intSI_type_node, 4);
16934 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16935 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16936 intHI_type_node, 8);
16937 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16938 intQI_type_node, 16);
16940 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16941 unsigned_intQI_type_node, 16);
16942 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16943 unsigned_intHI_type_node, 8);
16944 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16945 unsigned_intSI_type_node, 4);
16946 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16947 ? "__vector unsigned long"
16948 : "__vector unsigned long long",
16949 unsigned_intDI_type_node, 2);
16951 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
16952 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
16953 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
16954 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16956 const_str_type_node
16957 = build_pointer_type (build_qualified_type (char_type_node,
16960 /* We use V1TI mode as a special container to hold __int128_t items that
16961 must live in VSX registers. */
16962 if (intTI_type_node)
16964 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16965 intTI_type_node, 1);
16966 unsigned_V1TI_type_node
16967 = rs6000_vector_type ("__vector unsigned __int128",
16968 unsigned_intTI_type_node, 1);
16971 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16972 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16973 'vector unsigned short'. */
16975 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16976 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16977 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16978 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16979 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16981 long_integer_type_internal_node = long_integer_type_node;
16982 long_unsigned_type_internal_node = long_unsigned_type_node;
16983 long_long_integer_type_internal_node = long_long_integer_type_node;
16984 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16985 intQI_type_internal_node = intQI_type_node;
16986 uintQI_type_internal_node = unsigned_intQI_type_node;
16987 intHI_type_internal_node = intHI_type_node;
16988 uintHI_type_internal_node = unsigned_intHI_type_node;
16989 intSI_type_internal_node = intSI_type_node;
16990 uintSI_type_internal_node = unsigned_intSI_type_node;
16991 intDI_type_internal_node = intDI_type_node;
16992 uintDI_type_internal_node = unsigned_intDI_type_node;
16993 intTI_type_internal_node = intTI_type_node;
16994 uintTI_type_internal_node = unsigned_intTI_type_node;
16995 float_type_internal_node = float_type_node;
16996 double_type_internal_node = double_type_node;
16997 long_double_type_internal_node = long_double_type_node;
16998 dfloat64_type_internal_node = dfloat64_type_node;
16999 dfloat128_type_internal_node = dfloat128_type_node;
17000 void_type_internal_node = void_type_node;
17002 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
17003 IFmode is the IBM extended 128-bit format that is a pair of doubles.
17004 TFmode will be either IEEE 128-bit floating point or the IBM double-double
17005 format that uses a pair of doubles, depending on the switches and
17008 If we don't support for either 128-bit IBM double double or IEEE 128-bit
17009 floating point, we need make sure the type is non-zero or else self-test
17010 fails during bootstrap.
17012 We don't register a built-in type for __ibm128 if the type is the same as
17013 long double. Instead we add a #define for __ibm128 in
17014 rs6000_cpu_cpp_builtins to long double.
17016 For IEEE 128-bit floating point, always create the type __ieee128. If the
17017 user used -mfloat128, rs6000-c.c will create a define from __float128 to
17019 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
17021 ibm128_float_type_node = make_node (REAL_TYPE);
17022 TYPE_PRECISION (ibm128_float_type_node) = 128;
17023 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
17024 layout_type (ibm128_float_type_node);
17026 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
17030 ibm128_float_type_node = long_double_type_node;
17032 if (TARGET_FLOAT128_TYPE)
17034 ieee128_float_type_node = float128_type_node;
17035 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
17040 ieee128_float_type_node = long_double_type_node;
17042 /* Initialize the modes for builtin_function_type, mapping a machine mode to
17044 builtin_mode_to_type[QImode][0] = integer_type_node;
17045 builtin_mode_to_type[HImode][0] = integer_type_node;
17046 builtin_mode_to_type[SImode][0] = intSI_type_node;
17047 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
17048 builtin_mode_to_type[DImode][0] = intDI_type_node;
17049 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
17050 builtin_mode_to_type[TImode][0] = intTI_type_node;
17051 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
17052 builtin_mode_to_type[SFmode][0] = float_type_node;
17053 builtin_mode_to_type[DFmode][0] = double_type_node;
17054 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
17055 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
17056 builtin_mode_to_type[TFmode][0] = long_double_type_node;
17057 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
17058 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
17059 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
17060 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
17061 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
17062 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
17063 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
17064 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
17065 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
17066 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
17067 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
17068 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
17069 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
17070 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
17071 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
17072 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
17074 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
17075 TYPE_NAME (bool_char_type_node) = tdecl;
17077 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
17078 TYPE_NAME (bool_short_type_node) = tdecl;
17080 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
17081 TYPE_NAME (bool_int_type_node) = tdecl;
17083 tdecl = add_builtin_type ("__pixel", pixel_type_node);
17084 TYPE_NAME (pixel_type_node) = tdecl;
17086 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
17087 bool_char_type_node, 16);
17088 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
17089 bool_short_type_node, 8);
17090 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
17091 bool_int_type_node, 4);
17092 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17093 ? "__vector __bool long"
17094 : "__vector __bool long long",
17095 bool_long_type_node, 2);
17096 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
17097 pixel_type_node, 8);
17099 /* Paired builtins are only available if you build a compiler with the
17100 appropriate options, so only create those builtins with the appropriate
17101 compiler option. Create Altivec and VSX builtins on machines with at
17102 least the general purpose extensions (970 and newer) to allow the use of
17103 the target attribute. */
17104 if (TARGET_PAIRED_FLOAT)
17105 paired_init_builtins ();
17106 if (TARGET_EXTRA_BUILTINS)
17107 altivec_init_builtins ();
17109 htm_init_builtins ();
17111 if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
17112 rs6000_common_init_builtins ();
17114 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
17115 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
17116 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
17118 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
17119 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
17120 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
17122 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
17123 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
17124 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
17126 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
17127 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
17128 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
17130 mode = (TARGET_64BIT) ? DImode : SImode;
17131 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
17132 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
17133 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
17135 ftype = build_function_type_list (unsigned_intDI_type_node,
17137 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
17140 ftype = build_function_type_list (unsigned_intDI_type_node,
17143 ftype = build_function_type_list (unsigned_intSI_type_node,
17145 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
17147 ftype = build_function_type_list (double_type_node, NULL_TREE);
17148 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
17150 ftype = build_function_type_list (void_type_node,
17151 intSI_type_node, double_type_node,
17153 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
17155 ftype = build_function_type_list (void_type_node, NULL_TREE);
17156 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
17157 def_builtin ("__builtin_rs6000_speculation_barrier", ftype,
17158 MISC_BUILTIN_SPEC_BARRIER);
17160 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
17162 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
17163 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
17165 /* AIX libm provides clog as __clog. */
17166 if (TARGET_XCOFF &&
17167 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
17168 set_user_assembler_name (tdecl, "__clog");
17170 #ifdef SUBTARGET_INIT_BUILTINS
17171 SUBTARGET_INIT_BUILTINS;
17175 /* Returns the rs6000 builtin decl for CODE. */
17178 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
17180 HOST_WIDE_INT fnmask;
17182 if (code >= RS6000_BUILTIN_COUNT)
17183 return error_mark_node;
17185 fnmask = rs6000_builtin_info[code].mask;
17186 if ((fnmask & rs6000_builtin_mask) != fnmask)
17188 rs6000_invalid_builtin ((enum rs6000_builtins)code);
17189 return error_mark_node;
17192 return rs6000_builtin_decls[code];
17196 paired_init_builtins (void)
17198 const struct builtin_description *d;
17200 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17202 tree int_ftype_int_v2sf_v2sf
17203 = build_function_type_list (integer_type_node,
17208 tree pcfloat_type_node =
17209 build_pointer_type (build_qualified_type
17210 (float_type_node, TYPE_QUAL_CONST));
17212 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
17213 long_integer_type_node,
17216 tree void_ftype_v2sf_long_pcfloat =
17217 build_function_type_list (void_type_node,
17219 long_integer_type_node,
17224 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
17225 PAIRED_BUILTIN_LX);
17228 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
17229 PAIRED_BUILTIN_STX);
17232 d = bdesc_paired_preds;
17233 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
17236 HOST_WIDE_INT mask = d->mask;
17238 if ((mask & builtin_mask) != mask)
17240 if (TARGET_DEBUG_BUILTIN)
17241 fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
17246 /* Cannot define builtin if the instruction is disabled. */
17247 gcc_assert (d->icode != CODE_FOR_nothing);
17249 if (TARGET_DEBUG_BUILTIN)
17250 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
17251 (int)i, get_insn_name (d->icode), (int)d->icode,
17252 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
17254 switch (insn_data[d->icode].operand[1].mode)
17257 type = int_ftype_int_v2sf_v2sf;
17260 gcc_unreachable ();
17263 def_builtin (d->name, type, d->code);
17268 altivec_init_builtins (void)
17270 const struct builtin_description *d;
17274 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17276 tree pvoid_type_node = build_pointer_type (void_type_node);
17278 tree pcvoid_type_node
17279 = build_pointer_type (build_qualified_type (void_type_node,
17282 tree int_ftype_opaque
17283 = build_function_type_list (integer_type_node,
17284 opaque_V4SI_type_node, NULL_TREE);
17285 tree opaque_ftype_opaque
17286 = build_function_type_list (integer_type_node, NULL_TREE);
17287 tree opaque_ftype_opaque_int
17288 = build_function_type_list (opaque_V4SI_type_node,
17289 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
17290 tree opaque_ftype_opaque_opaque_int
17291 = build_function_type_list (opaque_V4SI_type_node,
17292 opaque_V4SI_type_node, opaque_V4SI_type_node,
17293 integer_type_node, NULL_TREE);
17294 tree opaque_ftype_opaque_opaque_opaque
17295 = build_function_type_list (opaque_V4SI_type_node,
17296 opaque_V4SI_type_node, opaque_V4SI_type_node,
17297 opaque_V4SI_type_node, NULL_TREE);
17298 tree opaque_ftype_opaque_opaque
17299 = build_function_type_list (opaque_V4SI_type_node,
17300 opaque_V4SI_type_node, opaque_V4SI_type_node,
17302 tree int_ftype_int_opaque_opaque
17303 = build_function_type_list (integer_type_node,
17304 integer_type_node, opaque_V4SI_type_node,
17305 opaque_V4SI_type_node, NULL_TREE);
17306 tree int_ftype_int_v4si_v4si
17307 = build_function_type_list (integer_type_node,
17308 integer_type_node, V4SI_type_node,
17309 V4SI_type_node, NULL_TREE);
17310 tree int_ftype_int_v2di_v2di
17311 = build_function_type_list (integer_type_node,
17312 integer_type_node, V2DI_type_node,
17313 V2DI_type_node, NULL_TREE);
17314 tree void_ftype_v4si
17315 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
17316 tree v8hi_ftype_void
17317 = build_function_type_list (V8HI_type_node, NULL_TREE);
17318 tree void_ftype_void
17319 = build_function_type_list (void_type_node, NULL_TREE);
17320 tree void_ftype_int
17321 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
17323 tree opaque_ftype_long_pcvoid
17324 = build_function_type_list (opaque_V4SI_type_node,
17325 long_integer_type_node, pcvoid_type_node,
17327 tree v16qi_ftype_long_pcvoid
17328 = build_function_type_list (V16QI_type_node,
17329 long_integer_type_node, pcvoid_type_node,
17331 tree v8hi_ftype_long_pcvoid
17332 = build_function_type_list (V8HI_type_node,
17333 long_integer_type_node, pcvoid_type_node,
17335 tree v4si_ftype_long_pcvoid
17336 = build_function_type_list (V4SI_type_node,
17337 long_integer_type_node, pcvoid_type_node,
17339 tree v4sf_ftype_long_pcvoid
17340 = build_function_type_list (V4SF_type_node,
17341 long_integer_type_node, pcvoid_type_node,
17343 tree v2df_ftype_long_pcvoid
17344 = build_function_type_list (V2DF_type_node,
17345 long_integer_type_node, pcvoid_type_node,
17347 tree v2di_ftype_long_pcvoid
17348 = build_function_type_list (V2DI_type_node,
17349 long_integer_type_node, pcvoid_type_node,
17352 tree void_ftype_opaque_long_pvoid
17353 = build_function_type_list (void_type_node,
17354 opaque_V4SI_type_node, long_integer_type_node,
17355 pvoid_type_node, NULL_TREE);
17356 tree void_ftype_v4si_long_pvoid
17357 = build_function_type_list (void_type_node,
17358 V4SI_type_node, long_integer_type_node,
17359 pvoid_type_node, NULL_TREE);
17360 tree void_ftype_v16qi_long_pvoid
17361 = build_function_type_list (void_type_node,
17362 V16QI_type_node, long_integer_type_node,
17363 pvoid_type_node, NULL_TREE);
17365 tree void_ftype_v16qi_pvoid_long
17366 = build_function_type_list (void_type_node,
17367 V16QI_type_node, pvoid_type_node,
17368 long_integer_type_node, NULL_TREE);
17370 tree void_ftype_v8hi_long_pvoid
17371 = build_function_type_list (void_type_node,
17372 V8HI_type_node, long_integer_type_node,
17373 pvoid_type_node, NULL_TREE);
17374 tree void_ftype_v4sf_long_pvoid
17375 = build_function_type_list (void_type_node,
17376 V4SF_type_node, long_integer_type_node,
17377 pvoid_type_node, NULL_TREE);
17378 tree void_ftype_v2df_long_pvoid
17379 = build_function_type_list (void_type_node,
17380 V2DF_type_node, long_integer_type_node,
17381 pvoid_type_node, NULL_TREE);
17382 tree void_ftype_v2di_long_pvoid
17383 = build_function_type_list (void_type_node,
17384 V2DI_type_node, long_integer_type_node,
17385 pvoid_type_node, NULL_TREE);
17386 tree int_ftype_int_v8hi_v8hi
17387 = build_function_type_list (integer_type_node,
17388 integer_type_node, V8HI_type_node,
17389 V8HI_type_node, NULL_TREE);
17390 tree int_ftype_int_v16qi_v16qi
17391 = build_function_type_list (integer_type_node,
17392 integer_type_node, V16QI_type_node,
17393 V16QI_type_node, NULL_TREE);
17394 tree int_ftype_int_v4sf_v4sf
17395 = build_function_type_list (integer_type_node,
17396 integer_type_node, V4SF_type_node,
17397 V4SF_type_node, NULL_TREE);
17398 tree int_ftype_int_v2df_v2df
17399 = build_function_type_list (integer_type_node,
17400 integer_type_node, V2DF_type_node,
17401 V2DF_type_node, NULL_TREE);
17402 tree v2di_ftype_v2di
17403 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
17404 tree v4si_ftype_v4si
17405 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17406 tree v8hi_ftype_v8hi
17407 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17408 tree v16qi_ftype_v16qi
17409 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17410 tree v4sf_ftype_v4sf
17411 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17412 tree v2df_ftype_v2df
17413 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17414 tree void_ftype_pcvoid_int_int
17415 = build_function_type_list (void_type_node,
17416 pcvoid_type_node, integer_type_node,
17417 integer_type_node, NULL_TREE);
17419 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
17420 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
17421 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
17422 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
17423 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
17424 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
17425 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
17426 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
17427 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
17428 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
17429 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
17430 ALTIVEC_BUILTIN_LVXL_V2DF);
17431 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
17432 ALTIVEC_BUILTIN_LVXL_V2DI);
17433 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
17434 ALTIVEC_BUILTIN_LVXL_V4SF);
17435 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
17436 ALTIVEC_BUILTIN_LVXL_V4SI);
17437 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
17438 ALTIVEC_BUILTIN_LVXL_V8HI);
17439 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
17440 ALTIVEC_BUILTIN_LVXL_V16QI);
17441 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
17442 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
17443 ALTIVEC_BUILTIN_LVX_V2DF);
17444 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
17445 ALTIVEC_BUILTIN_LVX_V2DI);
17446 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
17447 ALTIVEC_BUILTIN_LVX_V4SF);
17448 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
17449 ALTIVEC_BUILTIN_LVX_V4SI);
17450 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
17451 ALTIVEC_BUILTIN_LVX_V8HI);
17452 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
17453 ALTIVEC_BUILTIN_LVX_V16QI);
17454 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
17455 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
17456 ALTIVEC_BUILTIN_STVX_V2DF);
17457 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
17458 ALTIVEC_BUILTIN_STVX_V2DI);
17459 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
17460 ALTIVEC_BUILTIN_STVX_V4SF);
17461 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
17462 ALTIVEC_BUILTIN_STVX_V4SI);
17463 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
17464 ALTIVEC_BUILTIN_STVX_V8HI);
17465 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
17466 ALTIVEC_BUILTIN_STVX_V16QI);
17467 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
17468 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
17469 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
17470 ALTIVEC_BUILTIN_STVXL_V2DF);
17471 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
17472 ALTIVEC_BUILTIN_STVXL_V2DI);
17473 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
17474 ALTIVEC_BUILTIN_STVXL_V4SF);
17475 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
17476 ALTIVEC_BUILTIN_STVXL_V4SI);
17477 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
17478 ALTIVEC_BUILTIN_STVXL_V8HI);
17479 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
17480 ALTIVEC_BUILTIN_STVXL_V16QI);
17481 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
17482 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
17483 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
17484 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
17485 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
17486 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
17487 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
17488 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
17489 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
17490 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
17491 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
17492 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
17493 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
17494 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
17495 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
17496 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
17498 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
17499 VSX_BUILTIN_LXVD2X_V2DF);
17500 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
17501 VSX_BUILTIN_LXVD2X_V2DI);
17502 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
17503 VSX_BUILTIN_LXVW4X_V4SF);
17504 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
17505 VSX_BUILTIN_LXVW4X_V4SI);
17506 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
17507 VSX_BUILTIN_LXVW4X_V8HI);
17508 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
17509 VSX_BUILTIN_LXVW4X_V16QI);
17510 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
17511 VSX_BUILTIN_STXVD2X_V2DF);
17512 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
17513 VSX_BUILTIN_STXVD2X_V2DI);
17514 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
17515 VSX_BUILTIN_STXVW4X_V4SF);
17516 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
17517 VSX_BUILTIN_STXVW4X_V4SI);
17518 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
17519 VSX_BUILTIN_STXVW4X_V8HI);
17520 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
17521 VSX_BUILTIN_STXVW4X_V16QI);
17523 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
17524 VSX_BUILTIN_LD_ELEMREV_V2DF);
17525 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
17526 VSX_BUILTIN_LD_ELEMREV_V2DI);
17527 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
17528 VSX_BUILTIN_LD_ELEMREV_V4SF);
17529 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
17530 VSX_BUILTIN_LD_ELEMREV_V4SI);
17531 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
17532 VSX_BUILTIN_LD_ELEMREV_V8HI);
17533 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
17534 VSX_BUILTIN_LD_ELEMREV_V16QI);
17535 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
17536 VSX_BUILTIN_ST_ELEMREV_V2DF);
17537 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
17538 VSX_BUILTIN_ST_ELEMREV_V2DI);
17539 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17540 VSX_BUILTIN_ST_ELEMREV_V4SF);
17541 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17542 VSX_BUILTIN_ST_ELEMREV_V4SI);
17543 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
17544 VSX_BUILTIN_ST_ELEMREV_V8HI);
17545 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
17546 VSX_BUILTIN_ST_ELEMREV_V16QI);
17548 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17549 VSX_BUILTIN_VEC_LD);
17550 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17551 VSX_BUILTIN_VEC_ST);
17552 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17553 VSX_BUILTIN_VEC_XL);
17554 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17555 VSX_BUILTIN_VEC_XL_BE);
17556 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17557 VSX_BUILTIN_VEC_XST);
17558 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
17559 VSX_BUILTIN_VEC_XST_BE);
17561 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17562 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17563 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17565 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17566 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17567 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17568 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17569 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17570 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17571 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17572 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17573 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17574 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17575 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17576 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17578 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17579 ALTIVEC_BUILTIN_VEC_ADDE);
17580 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17581 ALTIVEC_BUILTIN_VEC_ADDEC);
17582 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17583 ALTIVEC_BUILTIN_VEC_CMPNE);
17584 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17585 ALTIVEC_BUILTIN_VEC_MUL);
17586 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17587 ALTIVEC_BUILTIN_VEC_SUBE);
17588 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17589 ALTIVEC_BUILTIN_VEC_SUBEC);
17591 /* Cell builtins. */
17592 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17593 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17594 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17595 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17597 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17598 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17599 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17600 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17602 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17603 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17604 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17605 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17607 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17608 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17609 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17610 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17612 if (TARGET_P9_VECTOR)
17614 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17615 P9V_BUILTIN_STXVL);
17616 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17617 P9V_BUILTIN_XST_LEN_R);
17620 /* Add the DST variants. */
17622 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17624 HOST_WIDE_INT mask = d->mask;
17626 /* It is expected that these dst built-in functions may have
17627 d->icode equal to CODE_FOR_nothing. */
17628 if ((mask & builtin_mask) != mask)
17630 if (TARGET_DEBUG_BUILTIN)
17631 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17635 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17638 /* Initialize the predicates. */
17639 d = bdesc_altivec_preds;
17640 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17642 machine_mode mode1;
17644 HOST_WIDE_INT mask = d->mask;
17646 if ((mask & builtin_mask) != mask)
17648 if (TARGET_DEBUG_BUILTIN)
17649 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17654 if (rs6000_overloaded_builtin_p (d->code))
17658 /* Cannot define builtin if the instruction is disabled. */
17659 gcc_assert (d->icode != CODE_FOR_nothing);
17660 mode1 = insn_data[d->icode].operand[1].mode;
17666 type = int_ftype_int_opaque_opaque;
17669 type = int_ftype_int_v2di_v2di;
17672 type = int_ftype_int_v4si_v4si;
17675 type = int_ftype_int_v8hi_v8hi;
17678 type = int_ftype_int_v16qi_v16qi;
17681 type = int_ftype_int_v4sf_v4sf;
17684 type = int_ftype_int_v2df_v2df;
17687 gcc_unreachable ();
17690 def_builtin (d->name, type, d->code);
17693 /* Initialize the abs* operators. */
17695 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17697 machine_mode mode0;
17699 HOST_WIDE_INT mask = d->mask;
17701 if ((mask & builtin_mask) != mask)
17703 if (TARGET_DEBUG_BUILTIN)
17704 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17709 /* Cannot define builtin if the instruction is disabled. */
17710 gcc_assert (d->icode != CODE_FOR_nothing);
17711 mode0 = insn_data[d->icode].operand[0].mode;
17716 type = v2di_ftype_v2di;
17719 type = v4si_ftype_v4si;
17722 type = v8hi_ftype_v8hi;
17725 type = v16qi_ftype_v16qi;
17728 type = v4sf_ftype_v4sf;
17731 type = v2df_ftype_v2df;
17734 gcc_unreachable ();
17737 def_builtin (d->name, type, d->code);
17740 /* Initialize target builtin that implements
17741 targetm.vectorize.builtin_mask_for_load. */
17743 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17744 v16qi_ftype_long_pcvoid,
17745 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17746 BUILT_IN_MD, NULL, NULL_TREE);
17747 TREE_READONLY (decl) = 1;
17748 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17749 altivec_builtin_mask_for_load = decl;
17751 /* Access to the vec_init patterns. */
17752 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17753 integer_type_node, integer_type_node,
17754 integer_type_node, NULL_TREE);
17755 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17757 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17758 short_integer_type_node,
17759 short_integer_type_node,
17760 short_integer_type_node,
17761 short_integer_type_node,
17762 short_integer_type_node,
17763 short_integer_type_node,
17764 short_integer_type_node, NULL_TREE);
17765 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17767 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17768 char_type_node, char_type_node,
17769 char_type_node, char_type_node,
17770 char_type_node, char_type_node,
17771 char_type_node, char_type_node,
17772 char_type_node, char_type_node,
17773 char_type_node, char_type_node,
17774 char_type_node, char_type_node,
17775 char_type_node, NULL_TREE);
17776 def_builtin ("__builtin_vec_init_v16qi", ftype,
17777 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17779 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17780 float_type_node, float_type_node,
17781 float_type_node, NULL_TREE);
17782 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17784 /* VSX builtins. */
17785 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17786 double_type_node, NULL_TREE);
17787 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17789 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17790 intDI_type_node, NULL_TREE);
17791 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17793 /* Access to the vec_set patterns. */
17794 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17796 integer_type_node, NULL_TREE);
17797 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17799 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17801 integer_type_node, NULL_TREE);
17802 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17804 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17806 integer_type_node, NULL_TREE);
17807 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17809 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17811 integer_type_node, NULL_TREE);
17812 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17814 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17816 integer_type_node, NULL_TREE);
17817 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17819 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17821 integer_type_node, NULL_TREE);
17822 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17824 /* Access to the vec_extract patterns. */
17825 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17826 integer_type_node, NULL_TREE);
17827 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17829 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17830 integer_type_node, NULL_TREE);
17831 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17833 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17834 integer_type_node, NULL_TREE);
17835 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17837 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17838 integer_type_node, NULL_TREE);
17839 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17841 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17842 integer_type_node, NULL_TREE);
17843 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17845 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17846 integer_type_node, NULL_TREE);
17847 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17850 if (V1TI_type_node)
17852 tree v1ti_ftype_long_pcvoid
17853 = build_function_type_list (V1TI_type_node,
17854 long_integer_type_node, pcvoid_type_node,
17856 tree void_ftype_v1ti_long_pvoid
17857 = build_function_type_list (void_type_node,
17858 V1TI_type_node, long_integer_type_node,
17859 pvoid_type_node, NULL_TREE);
17860 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17861 VSX_BUILTIN_LXVD2X_V1TI);
17862 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17863 VSX_BUILTIN_STXVD2X_V1TI);
17864 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17865 NULL_TREE, NULL_TREE);
17866 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17867 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17869 integer_type_node, NULL_TREE);
17870 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17871 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17872 integer_type_node, NULL_TREE);
17873 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17879 htm_init_builtins (void)
17881 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17882 const struct builtin_description *d;
17886 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17888 tree op[MAX_HTM_OPERANDS], type;
17889 HOST_WIDE_INT mask = d->mask;
17890 unsigned attr = rs6000_builtin_info[d->code].attr;
17891 bool void_func = (attr & RS6000_BTC_VOID);
17892 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17894 tree gpr_type_node;
17898 /* It is expected that these htm built-in functions may have
17899 d->icode equal to CODE_FOR_nothing. */
17901 if (TARGET_32BIT && TARGET_POWERPC64)
17902 gpr_type_node = long_long_unsigned_type_node;
17904 gpr_type_node = long_unsigned_type_node;
17906 if (attr & RS6000_BTC_SPR)
17908 rettype = gpr_type_node;
17909 argtype = gpr_type_node;
17911 else if (d->code == HTM_BUILTIN_TABORTDC
17912 || d->code == HTM_BUILTIN_TABORTDCI)
17914 rettype = unsigned_type_node;
17915 argtype = gpr_type_node;
17919 rettype = unsigned_type_node;
17920 argtype = unsigned_type_node;
17923 if ((mask & builtin_mask) != mask)
17925 if (TARGET_DEBUG_BUILTIN)
17926 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17932 if (TARGET_DEBUG_BUILTIN)
17933 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17934 (long unsigned) i);
17938 op[nopnds++] = (void_func) ? void_type_node : rettype;
17940 if (attr_args == RS6000_BTC_UNARY)
17941 op[nopnds++] = argtype;
17942 else if (attr_args == RS6000_BTC_BINARY)
17944 op[nopnds++] = argtype;
17945 op[nopnds++] = argtype;
17947 else if (attr_args == RS6000_BTC_TERNARY)
17949 op[nopnds++] = argtype;
17950 op[nopnds++] = argtype;
17951 op[nopnds++] = argtype;
17957 type = build_function_type_list (op[0], NULL_TREE);
17960 type = build_function_type_list (op[0], op[1], NULL_TREE);
17963 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17966 type = build_function_type_list (op[0], op[1], op[2], op[3],
17970 gcc_unreachable ();
17973 def_builtin (d->name, type, d->code);
17977 /* Hash function for builtin functions with up to 3 arguments and a return
17980 builtin_hasher::hash (builtin_hash_struct *bh)
17985 for (i = 0; i < 4; i++)
17987 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17988 ret = (ret * 2) + bh->uns_p[i];
17994 /* Compare builtin hash entries H1 and H2 for equivalence. */
17996 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17998 return ((p1->mode[0] == p2->mode[0])
17999 && (p1->mode[1] == p2->mode[1])
18000 && (p1->mode[2] == p2->mode[2])
18001 && (p1->mode[3] == p2->mode[3])
18002 && (p1->uns_p[0] == p2->uns_p[0])
18003 && (p1->uns_p[1] == p2->uns_p[1])
18004 && (p1->uns_p[2] == p2->uns_p[2])
18005 && (p1->uns_p[3] == p2->uns_p[3]));
18008 /* Map types for builtin functions with an explicit return type and up to 3
18009 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18010 of the argument. */
18012 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
18013 machine_mode mode_arg1, machine_mode mode_arg2,
18014 enum rs6000_builtins builtin, const char *name)
18016 struct builtin_hash_struct h;
18017 struct builtin_hash_struct *h2;
18020 tree ret_type = NULL_TREE;
18021 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
18023 /* Create builtin_hash_table. */
18024 if (builtin_hash_table == NULL)
18025 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
18027 h.type = NULL_TREE;
18028 h.mode[0] = mode_ret;
18029 h.mode[1] = mode_arg0;
18030 h.mode[2] = mode_arg1;
18031 h.mode[3] = mode_arg2;
18037 /* If the builtin is a type that produces unsigned results or takes unsigned
18038 arguments, and it is returned as a decl for the vectorizer (such as
18039 widening multiplies, permute), make sure the arguments and return value
18040 are type correct. */
18043 /* unsigned 1 argument functions. */
18044 case CRYPTO_BUILTIN_VSBOX:
18045 case P8V_BUILTIN_VGBBD:
18046 case MISC_BUILTIN_CDTBCD:
18047 case MISC_BUILTIN_CBCDTD:
18052 /* unsigned 2 argument functions. */
18053 case ALTIVEC_BUILTIN_VMULEUB:
18054 case ALTIVEC_BUILTIN_VMULEUH:
18055 case ALTIVEC_BUILTIN_VMULEUW:
18056 case ALTIVEC_BUILTIN_VMULOUB:
18057 case ALTIVEC_BUILTIN_VMULOUH:
18058 case ALTIVEC_BUILTIN_VMULOUW:
18059 case CRYPTO_BUILTIN_VCIPHER:
18060 case CRYPTO_BUILTIN_VCIPHERLAST:
18061 case CRYPTO_BUILTIN_VNCIPHER:
18062 case CRYPTO_BUILTIN_VNCIPHERLAST:
18063 case CRYPTO_BUILTIN_VPMSUMB:
18064 case CRYPTO_BUILTIN_VPMSUMH:
18065 case CRYPTO_BUILTIN_VPMSUMW:
18066 case CRYPTO_BUILTIN_VPMSUMD:
18067 case CRYPTO_BUILTIN_VPMSUM:
18068 case MISC_BUILTIN_ADDG6S:
18069 case MISC_BUILTIN_DIVWEU:
18070 case MISC_BUILTIN_DIVWEUO:
18071 case MISC_BUILTIN_DIVDEU:
18072 case MISC_BUILTIN_DIVDEUO:
18073 case VSX_BUILTIN_UDIV_V2DI:
18074 case ALTIVEC_BUILTIN_VMAXUB:
18075 case ALTIVEC_BUILTIN_VMINUB:
18076 case ALTIVEC_BUILTIN_VMAXUH:
18077 case ALTIVEC_BUILTIN_VMINUH:
18078 case ALTIVEC_BUILTIN_VMAXUW:
18079 case ALTIVEC_BUILTIN_VMINUW:
18080 case P8V_BUILTIN_VMAXUD:
18081 case P8V_BUILTIN_VMINUD:
18087 /* unsigned 3 argument functions. */
18088 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
18089 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
18090 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
18091 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
18092 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
18093 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
18094 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
18095 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
18096 case VSX_BUILTIN_VPERM_16QI_UNS:
18097 case VSX_BUILTIN_VPERM_8HI_UNS:
18098 case VSX_BUILTIN_VPERM_4SI_UNS:
18099 case VSX_BUILTIN_VPERM_2DI_UNS:
18100 case VSX_BUILTIN_XXSEL_16QI_UNS:
18101 case VSX_BUILTIN_XXSEL_8HI_UNS:
18102 case VSX_BUILTIN_XXSEL_4SI_UNS:
18103 case VSX_BUILTIN_XXSEL_2DI_UNS:
18104 case CRYPTO_BUILTIN_VPERMXOR:
18105 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
18106 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
18107 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
18108 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
18109 case CRYPTO_BUILTIN_VSHASIGMAW:
18110 case CRYPTO_BUILTIN_VSHASIGMAD:
18111 case CRYPTO_BUILTIN_VSHASIGMA:
18118 /* signed permute functions with unsigned char mask. */
18119 case ALTIVEC_BUILTIN_VPERM_16QI:
18120 case ALTIVEC_BUILTIN_VPERM_8HI:
18121 case ALTIVEC_BUILTIN_VPERM_4SI:
18122 case ALTIVEC_BUILTIN_VPERM_4SF:
18123 case ALTIVEC_BUILTIN_VPERM_2DI:
18124 case ALTIVEC_BUILTIN_VPERM_2DF:
18125 case VSX_BUILTIN_VPERM_16QI:
18126 case VSX_BUILTIN_VPERM_8HI:
18127 case VSX_BUILTIN_VPERM_4SI:
18128 case VSX_BUILTIN_VPERM_4SF:
18129 case VSX_BUILTIN_VPERM_2DI:
18130 case VSX_BUILTIN_VPERM_2DF:
18134 /* unsigned args, signed return. */
18135 case VSX_BUILTIN_XVCVUXDSP:
18136 case VSX_BUILTIN_XVCVUXDDP_UNS:
18137 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
18141 /* signed args, unsigned return. */
18142 case VSX_BUILTIN_XVCVDPUXDS_UNS:
18143 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
18144 case MISC_BUILTIN_UNPACK_TD:
18145 case MISC_BUILTIN_UNPACK_V1TI:
18149 /* unsigned arguments, bool return (compares). */
18150 case ALTIVEC_BUILTIN_VCMPEQUB:
18151 case ALTIVEC_BUILTIN_VCMPEQUH:
18152 case ALTIVEC_BUILTIN_VCMPEQUW:
18153 case P8V_BUILTIN_VCMPEQUD:
18154 case VSX_BUILTIN_CMPGE_U16QI:
18155 case VSX_BUILTIN_CMPGE_U8HI:
18156 case VSX_BUILTIN_CMPGE_U4SI:
18157 case VSX_BUILTIN_CMPGE_U2DI:
18158 case ALTIVEC_BUILTIN_VCMPGTUB:
18159 case ALTIVEC_BUILTIN_VCMPGTUH:
18160 case ALTIVEC_BUILTIN_VCMPGTUW:
18161 case P8V_BUILTIN_VCMPGTUD:
18166 /* unsigned arguments for 128-bit pack instructions. */
18167 case MISC_BUILTIN_PACK_TD:
18168 case MISC_BUILTIN_PACK_V1TI:
18173 /* unsigned second arguments (vector shift right). */
18174 case ALTIVEC_BUILTIN_VSRB:
18175 case ALTIVEC_BUILTIN_VSRH:
18176 case ALTIVEC_BUILTIN_VSRW:
18177 case P8V_BUILTIN_VSRD:
18185 /* Figure out how many args are present. */
18186 while (num_args > 0 && h.mode[num_args] == VOIDmode)
18189 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
18190 if (!ret_type && h.uns_p[0])
18191 ret_type = builtin_mode_to_type[h.mode[0]][0];
18194 fatal_error (input_location,
18195 "internal error: builtin function %qs had an unexpected "
18196 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
18198 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
18199 arg_type[i] = NULL_TREE;
18201 for (i = 0; i < num_args; i++)
18203 int m = (int) h.mode[i+1];
18204 int uns_p = h.uns_p[i+1];
18206 arg_type[i] = builtin_mode_to_type[m][uns_p];
18207 if (!arg_type[i] && uns_p)
18208 arg_type[i] = builtin_mode_to_type[m][0];
18211 fatal_error (input_location,
18212 "internal error: builtin function %qs, argument %d "
18213 "had unexpected argument type %qs", name, i,
18214 GET_MODE_NAME (m));
18217 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
18218 if (*found == NULL)
18220 h2 = ggc_alloc<builtin_hash_struct> ();
18224 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
18225 arg_type[2], NULL_TREE);
18228 return (*found)->type;
18232 rs6000_common_init_builtins (void)
18234 const struct builtin_description *d;
18237 tree opaque_ftype_opaque = NULL_TREE;
18238 tree opaque_ftype_opaque_opaque = NULL_TREE;
18239 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
18240 tree v2si_ftype = NULL_TREE;
18241 tree v2si_ftype_qi = NULL_TREE;
18242 tree v2si_ftype_v2si_qi = NULL_TREE;
18243 tree v2si_ftype_int_qi = NULL_TREE;
18244 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18246 if (!TARGET_PAIRED_FLOAT)
18248 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
18249 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
18252 /* Paired builtins are only available if you build a compiler with the
18253 appropriate options, so only create those builtins with the appropriate
18254 compiler option. Create Altivec and VSX builtins on machines with at
18255 least the general purpose extensions (970 and newer) to allow the use of
18256 the target attribute.. */
18258 if (TARGET_EXTRA_BUILTINS)
18259 builtin_mask |= RS6000_BTM_COMMON;
18261 /* Add the ternary operators. */
18263 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
18266 HOST_WIDE_INT mask = d->mask;
18268 if ((mask & builtin_mask) != mask)
18270 if (TARGET_DEBUG_BUILTIN)
18271 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
18275 if (rs6000_overloaded_builtin_p (d->code))
18277 if (! (type = opaque_ftype_opaque_opaque_opaque))
18278 type = opaque_ftype_opaque_opaque_opaque
18279 = build_function_type_list (opaque_V4SI_type_node,
18280 opaque_V4SI_type_node,
18281 opaque_V4SI_type_node,
18282 opaque_V4SI_type_node,
18287 enum insn_code icode = d->icode;
18290 if (TARGET_DEBUG_BUILTIN)
18291 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18297 if (icode == CODE_FOR_nothing)
18299 if (TARGET_DEBUG_BUILTIN)
18300 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
18306 type = builtin_function_type (insn_data[icode].operand[0].mode,
18307 insn_data[icode].operand[1].mode,
18308 insn_data[icode].operand[2].mode,
18309 insn_data[icode].operand[3].mode,
18313 def_builtin (d->name, type, d->code);
18316 /* Add the binary operators. */
18318 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
18320 machine_mode mode0, mode1, mode2;
18322 HOST_WIDE_INT mask = d->mask;
18324 if ((mask & builtin_mask) != mask)
18326 if (TARGET_DEBUG_BUILTIN)
18327 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
18331 if (rs6000_overloaded_builtin_p (d->code))
18333 if (! (type = opaque_ftype_opaque_opaque))
18334 type = opaque_ftype_opaque_opaque
18335 = build_function_type_list (opaque_V4SI_type_node,
18336 opaque_V4SI_type_node,
18337 opaque_V4SI_type_node,
18342 enum insn_code icode = d->icode;
18345 if (TARGET_DEBUG_BUILTIN)
18346 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18352 if (icode == CODE_FOR_nothing)
18354 if (TARGET_DEBUG_BUILTIN)
18355 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
18361 mode0 = insn_data[icode].operand[0].mode;
18362 mode1 = insn_data[icode].operand[1].mode;
18363 mode2 = insn_data[icode].operand[2].mode;
18365 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
18367 if (! (type = v2si_ftype_v2si_qi))
18368 type = v2si_ftype_v2si_qi
18369 = build_function_type_list (opaque_V2SI_type_node,
18370 opaque_V2SI_type_node,
18375 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
18376 && mode2 == QImode)
18378 if (! (type = v2si_ftype_int_qi))
18379 type = v2si_ftype_int_qi
18380 = build_function_type_list (opaque_V2SI_type_node,
18387 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
18391 def_builtin (d->name, type, d->code);
18394 /* Add the simple unary operators. */
18396 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
18398 machine_mode mode0, mode1;
18400 HOST_WIDE_INT mask = d->mask;
18402 if ((mask & builtin_mask) != mask)
18404 if (TARGET_DEBUG_BUILTIN)
18405 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
18409 if (rs6000_overloaded_builtin_p (d->code))
18411 if (! (type = opaque_ftype_opaque))
18412 type = opaque_ftype_opaque
18413 = build_function_type_list (opaque_V4SI_type_node,
18414 opaque_V4SI_type_node,
18419 enum insn_code icode = d->icode;
18422 if (TARGET_DEBUG_BUILTIN)
18423 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18429 if (icode == CODE_FOR_nothing)
18431 if (TARGET_DEBUG_BUILTIN)
18432 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
18438 mode0 = insn_data[icode].operand[0].mode;
18439 mode1 = insn_data[icode].operand[1].mode;
18441 if (mode0 == V2SImode && mode1 == QImode)
18443 if (! (type = v2si_ftype_qi))
18444 type = v2si_ftype_qi
18445 = build_function_type_list (opaque_V2SI_type_node,
18451 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
18455 def_builtin (d->name, type, d->code);
18458 /* Add the simple no-argument operators. */
18460 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
18462 machine_mode mode0;
18464 HOST_WIDE_INT mask = d->mask;
18466 if ((mask & builtin_mask) != mask)
18468 if (TARGET_DEBUG_BUILTIN)
18469 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
18472 if (rs6000_overloaded_builtin_p (d->code))
18474 if (!opaque_ftype_opaque)
18475 opaque_ftype_opaque
18476 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
18477 type = opaque_ftype_opaque;
18481 enum insn_code icode = d->icode;
18484 if (TARGET_DEBUG_BUILTIN)
18485 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18486 (long unsigned) i);
18489 if (icode == CODE_FOR_nothing)
18491 if (TARGET_DEBUG_BUILTIN)
18493 "rs6000_builtin, skip no-argument %s (no code)\n",
18497 mode0 = insn_data[icode].operand[0].mode;
18498 if (mode0 == V2SImode)
18500 /* code for paired single */
18501 if (! (type = v2si_ftype))
18504 = build_function_type_list (opaque_V2SI_type_node,
18510 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
18513 def_builtin (d->name, type, d->code);
18517 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18519 init_float128_ibm (machine_mode mode)
18521 if (!TARGET_XL_COMPAT)
18523 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
18524 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
18525 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
18526 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
18528 if (!TARGET_HARD_FLOAT)
18530 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
18531 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
18532 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
18533 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
18534 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
18535 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
18536 set_optab_libfunc (le_optab, mode, "__gcc_qle");
18537 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
18539 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
18540 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
18541 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
18542 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
18543 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
18544 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
18545 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
18546 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
18551 set_optab_libfunc (add_optab, mode, "_xlqadd");
18552 set_optab_libfunc (sub_optab, mode, "_xlqsub");
18553 set_optab_libfunc (smul_optab, mode, "_xlqmul");
18554 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
18557 /* Add various conversions for IFmode to use the traditional TFmode
18559 if (mode == IFmode)
18561 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
18562 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
18563 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
18564 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
18565 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
18566 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
18568 if (TARGET_POWERPC64)
18570 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
18571 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
18572 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
18573 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
18578 /* Set up IEEE 128-bit floating point routines. Use different names if the
18579 arguments can be passed in a vector register. The historical PowerPC
18580 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18581 continue to use that if we aren't using vector registers to pass IEEE
18582 128-bit floating point. */
18585 init_float128_ieee (machine_mode mode)
18587 if (FLOAT128_VECTOR_P (mode))
18589 set_optab_libfunc (add_optab, mode, "__addkf3");
18590 set_optab_libfunc (sub_optab, mode, "__subkf3");
18591 set_optab_libfunc (neg_optab, mode, "__negkf2");
18592 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18593 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18594 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18595 set_optab_libfunc (abs_optab, mode, "__abstkf2");
18597 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18598 set_optab_libfunc (ne_optab, mode, "__nekf2");
18599 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18600 set_optab_libfunc (ge_optab, mode, "__gekf2");
18601 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18602 set_optab_libfunc (le_optab, mode, "__lekf2");
18603 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18605 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18606 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18607 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18608 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18610 set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
18611 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18612 set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
18614 set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
18615 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18616 set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
18618 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
18619 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
18620 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
18621 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
18622 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
18623 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
18625 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18626 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18627 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18628 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18630 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18631 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18632 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18633 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18635 if (TARGET_POWERPC64)
18637 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18638 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18639 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18640 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18646 set_optab_libfunc (add_optab, mode, "_q_add");
18647 set_optab_libfunc (sub_optab, mode, "_q_sub");
18648 set_optab_libfunc (neg_optab, mode, "_q_neg");
18649 set_optab_libfunc (smul_optab, mode, "_q_mul");
18650 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18651 if (TARGET_PPC_GPOPT)
18652 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18654 set_optab_libfunc (eq_optab, mode, "_q_feq");
18655 set_optab_libfunc (ne_optab, mode, "_q_fne");
18656 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18657 set_optab_libfunc (ge_optab, mode, "_q_fge");
18658 set_optab_libfunc (lt_optab, mode, "_q_flt");
18659 set_optab_libfunc (le_optab, mode, "_q_fle");
18661 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18662 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18663 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18664 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18665 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18666 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18667 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18668 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18673 rs6000_init_libfuncs (void)
18675 /* __float128 support. */
18676 if (TARGET_FLOAT128_TYPE)
18678 init_float128_ibm (IFmode);
18679 init_float128_ieee (KFmode);
18682 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18683 if (TARGET_LONG_DOUBLE_128)
18685 if (!TARGET_IEEEQUAD)
18686 init_float128_ibm (TFmode);
18688 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18690 init_float128_ieee (TFmode);
18694 /* Emit a potentially record-form instruction, setting DST from SRC.
18695 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18696 signed comparison of DST with zero. If DOT is 1, the generated RTL
18697 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18698 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18699 a separate COMPARE. */
18702 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18706 emit_move_insn (dst, src);
18710 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18712 emit_move_insn (dst, src);
18713 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18717 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18720 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18721 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18725 rtx set = gen_rtx_SET (dst, src);
18726 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18731 /* A validation routine: say whether CODE, a condition code, and MODE
18732 match. The other alternatives either don't make sense or should
18733 never be generated. */
18736 validate_condition_mode (enum rtx_code code, machine_mode mode)
18738 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18739 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18740 && GET_MODE_CLASS (mode) == MODE_CC);
18742 /* These don't make sense. */
18743 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18744 || mode != CCUNSmode);
18746 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18747 || mode == CCUNSmode);
18749 gcc_assert (mode == CCFPmode
18750 || (code != ORDERED && code != UNORDERED
18751 && code != UNEQ && code != LTGT
18752 && code != UNGT && code != UNLT
18753 && code != UNGE && code != UNLE));
18755 /* These should never be generated except for
18756 flag_finite_math_only. */
18757 gcc_assert (mode != CCFPmode
18758 || flag_finite_math_only
18759 || (code != LE && code != GE
18760 && code != UNEQ && code != LTGT
18761 && code != UNGT && code != UNLT));
18763 /* These are invalid; the information is not there. */
18764 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18768 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18769 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18770 not zero, store there the bit offset (counted from the right) where
18771 the single stretch of 1 bits begins; and similarly for B, the bit
18772 offset where it ends. */
18775 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18777 unsigned HOST_WIDE_INT val = INTVAL (mask);
18778 unsigned HOST_WIDE_INT bit;
18780 int n = GET_MODE_PRECISION (mode);
18782 if (mode != DImode && mode != SImode)
18785 if (INTVAL (mask) >= 0)
18788 ne = exact_log2 (bit);
18789 nb = exact_log2 (val + bit);
18791 else if (val + 1 == 0)
18800 nb = exact_log2 (bit);
18801 ne = exact_log2 (val + bit);
18806 ne = exact_log2 (bit);
18807 if (val + bit == 0)
18815 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18826 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18827 or rldicr instruction, to implement an AND with it in mode MODE. */
18830 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18834 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18837 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18839 if (mode == DImode)
18840 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18842 /* For SImode, rlwinm can do everything. */
18843 if (mode == SImode)
18844 return (nb < 32 && ne < 32);
18849 /* Return the instruction template for an AND with mask in mode MODE, with
18850 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18853 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18857 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18858 gcc_unreachable ();
18860 if (mode == DImode && ne == 0)
18862 operands[3] = GEN_INT (63 - nb);
18864 return "rldicl. %0,%1,0,%3";
18865 return "rldicl %0,%1,0,%3";
18868 if (mode == DImode && nb == 63)
18870 operands[3] = GEN_INT (63 - ne);
18872 return "rldicr. %0,%1,0,%3";
18873 return "rldicr %0,%1,0,%3";
18876 if (nb < 32 && ne < 32)
18878 operands[3] = GEN_INT (31 - nb);
18879 operands[4] = GEN_INT (31 - ne);
18881 return "rlwinm. %0,%1,0,%3,%4";
18882 return "rlwinm %0,%1,0,%3,%4";
18885 gcc_unreachable ();
18888 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18889 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18890 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18893 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18897 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18900 int n = GET_MODE_PRECISION (mode);
18903 if (CONST_INT_P (XEXP (shift, 1)))
18905 sh = INTVAL (XEXP (shift, 1));
18906 if (sh < 0 || sh >= n)
18910 rtx_code code = GET_CODE (shift);
18912 /* Convert any shift by 0 to a rotate, to simplify below code. */
18916 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18917 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18919 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18925 /* DImode rotates need rld*. */
18926 if (mode == DImode && code == ROTATE)
18927 return (nb == 63 || ne == 0 || ne == sh);
18929 /* SImode rotates need rlw*. */
18930 if (mode == SImode && code == ROTATE)
18931 return (nb < 32 && ne < 32 && sh < 32);
18933 /* Wrap-around masks are only okay for rotates. */
18937 /* Variable shifts are only okay for rotates. */
18941 /* Don't allow ASHIFT if the mask is wrong for that. */
18942 if (code == ASHIFT && ne < sh)
18945 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18946 if the mask is wrong for that. */
18947 if (nb < 32 && ne < 32 && sh < 32
18948 && !(code == LSHIFTRT && nb >= 32 - sh))
18951 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18952 if the mask is wrong for that. */
18953 if (code == LSHIFTRT)
18955 if (nb == 63 || ne == 0 || ne == sh)
18956 return !(code == LSHIFTRT && nb >= sh);
18961 /* Return the instruction template for a shift with mask in mode MODE, with
18962 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18965 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18969 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18970 gcc_unreachable ();
18972 if (mode == DImode && ne == 0)
18974 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18975 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18976 operands[3] = GEN_INT (63 - nb);
18978 return "rld%I2cl. %0,%1,%2,%3";
18979 return "rld%I2cl %0,%1,%2,%3";
18982 if (mode == DImode && nb == 63)
18984 operands[3] = GEN_INT (63 - ne);
18986 return "rld%I2cr. %0,%1,%2,%3";
18987 return "rld%I2cr %0,%1,%2,%3";
18991 && GET_CODE (operands[4]) != LSHIFTRT
18992 && CONST_INT_P (operands[2])
18993 && ne == INTVAL (operands[2]))
18995 operands[3] = GEN_INT (63 - nb);
18997 return "rld%I2c. %0,%1,%2,%3";
18998 return "rld%I2c %0,%1,%2,%3";
19001 if (nb < 32 && ne < 32)
19003 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19004 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19005 operands[3] = GEN_INT (31 - nb);
19006 operands[4] = GEN_INT (31 - ne);
19007 /* This insn can also be a 64-bit rotate with mask that really makes
19008 it just a shift right (with mask); the %h below are to adjust for
19009 that situation (shift count is >= 32 in that case). */
19011 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19012 return "rlw%I2nm %0,%1,%h2,%3,%4";
19015 gcc_unreachable ();
19018 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19019 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19020 ASHIFT, or LSHIFTRT) in mode MODE. */
19023 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
19027 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19030 int n = GET_MODE_PRECISION (mode);
19032 int sh = INTVAL (XEXP (shift, 1));
19033 if (sh < 0 || sh >= n)
19036 rtx_code code = GET_CODE (shift);
19038 /* Convert any shift by 0 to a rotate, to simplify below code. */
19042 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19043 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19045 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19051 /* DImode rotates need rldimi. */
19052 if (mode == DImode && code == ROTATE)
19055 /* SImode rotates need rlwimi. */
19056 if (mode == SImode && code == ROTATE)
19057 return (nb < 32 && ne < 32 && sh < 32);
19059 /* Wrap-around masks are only okay for rotates. */
19063 /* Don't allow ASHIFT if the mask is wrong for that. */
19064 if (code == ASHIFT && ne < sh)
19067 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19068 if the mask is wrong for that. */
19069 if (nb < 32 && ne < 32 && sh < 32
19070 && !(code == LSHIFTRT && nb >= 32 - sh))
19073 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19074 if the mask is wrong for that. */
19075 if (code == LSHIFTRT)
19078 return !(code == LSHIFTRT && nb >= sh);
19083 /* Return the instruction template for an insert with mask in mode MODE, with
19084 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19087 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
19091 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19092 gcc_unreachable ();
19094 /* Prefer rldimi because rlwimi is cracked. */
19095 if (TARGET_POWERPC64
19096 && (!dot || mode == DImode)
19097 && GET_CODE (operands[4]) != LSHIFTRT
19098 && ne == INTVAL (operands[2]))
19100 operands[3] = GEN_INT (63 - nb);
19102 return "rldimi. %0,%1,%2,%3";
19103 return "rldimi %0,%1,%2,%3";
19106 if (nb < 32 && ne < 32)
19108 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19109 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19110 operands[3] = GEN_INT (31 - nb);
19111 operands[4] = GEN_INT (31 - ne);
19113 return "rlwimi. %0,%1,%2,%3,%4";
19114 return "rlwimi %0,%1,%2,%3,%4";
19117 gcc_unreachable ();
19120 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19121 using two machine instructions. */
19124 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
19126 /* There are two kinds of AND we can handle with two insns:
19127 1) those we can do with two rl* insn;
19130 We do not handle that last case yet. */
19132 /* If there is just one stretch of ones, we can do it. */
19133 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
19136 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19137 one insn, we can do the whole thing with two. */
19138 unsigned HOST_WIDE_INT val = INTVAL (c);
19139 unsigned HOST_WIDE_INT bit1 = val & -val;
19140 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19141 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19142 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19143 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
19146 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19147 If EXPAND is true, split rotate-and-mask instructions we generate to
19148 their constituent parts as well (this is used during expand); if DOT
19149 is 1, make the last insn a record-form instruction clobbering the
19150 destination GPR and setting the CC reg (from operands[3]); if 2, set
19151 that GPR as well as the CC reg. */
19154 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
19156 gcc_assert (!(expand && dot));
19158 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
19160 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19161 shift right. This generates better code than doing the masks without
19162 shifts, or shifting first right and then left. */
19164 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
19166 gcc_assert (mode == DImode);
19168 int shift = 63 - nb;
19171 rtx tmp1 = gen_reg_rtx (DImode);
19172 rtx tmp2 = gen_reg_rtx (DImode);
19173 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
19174 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
19175 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
19179 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
19180 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
19181 emit_move_insn (operands[0], tmp);
19182 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
19183 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19188 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19189 that does the rest. */
19190 unsigned HOST_WIDE_INT bit1 = val & -val;
19191 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19192 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19193 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19195 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
19196 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
19198 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
19200 /* Two "no-rotate"-and-mask instructions, for SImode. */
19201 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
19203 gcc_assert (mode == SImode);
19205 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19206 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
19207 emit_move_insn (reg, tmp);
19208 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19209 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19213 gcc_assert (mode == DImode);
19215 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19216 insns; we have to do the first in SImode, because it wraps. */
19217 if (mask2 <= 0xffffffff
19218 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
19220 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19221 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
19223 rtx reg_low = gen_lowpart (SImode, reg);
19224 emit_move_insn (reg_low, tmp);
19225 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19226 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19230 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19231 at the top end), rotate back and clear the other hole. */
19232 int right = exact_log2 (bit3);
19233 int left = 64 - right;
19235 /* Rotate the mask too. */
19236 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
19240 rtx tmp1 = gen_reg_rtx (DImode);
19241 rtx tmp2 = gen_reg_rtx (DImode);
19242 rtx tmp3 = gen_reg_rtx (DImode);
19243 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
19244 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
19245 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
19246 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
19250 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
19251 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
19252 emit_move_insn (operands[0], tmp);
19253 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
19254 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
19255 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19259 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19260 for lfq and stfq insns iff the registers are hard registers. */
19263 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
19265 /* We might have been passed a SUBREG. */
19266 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
19269 /* We might have been passed non floating point registers. */
19270 if (!FP_REGNO_P (REGNO (reg1))
19271 || !FP_REGNO_P (REGNO (reg2)))
19274 return (REGNO (reg1) == REGNO (reg2) - 1);
19277 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19278 addr1 and addr2 must be in consecutive memory locations
19279 (addr2 == addr1 + 8). */
19282 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
19285 unsigned int reg1, reg2;
19286 int offset1, offset2;
19288 /* The mems cannot be volatile. */
19289 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
19292 addr1 = XEXP (mem1, 0);
19293 addr2 = XEXP (mem2, 0);
19295 /* Extract an offset (if used) from the first addr. */
19296 if (GET_CODE (addr1) == PLUS)
19298 /* If not a REG, return zero. */
19299 if (GET_CODE (XEXP (addr1, 0)) != REG)
19303 reg1 = REGNO (XEXP (addr1, 0));
19304 /* The offset must be constant! */
19305 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
19307 offset1 = INTVAL (XEXP (addr1, 1));
19310 else if (GET_CODE (addr1) != REG)
19314 reg1 = REGNO (addr1);
19315 /* This was a simple (mem (reg)) expression. Offset is 0. */
19319 /* And now for the second addr. */
19320 if (GET_CODE (addr2) == PLUS)
19322 /* If not a REG, return zero. */
19323 if (GET_CODE (XEXP (addr2, 0)) != REG)
19327 reg2 = REGNO (XEXP (addr2, 0));
19328 /* The offset must be constant. */
19329 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
19331 offset2 = INTVAL (XEXP (addr2, 1));
19334 else if (GET_CODE (addr2) != REG)
19338 reg2 = REGNO (addr2);
19339 /* This was a simple (mem (reg)) expression. Offset is 0. */
19343 /* Both of these must have the same base register. */
19347 /* The offset for the second addr must be 8 more than the first addr. */
19348 if (offset2 != offset1 + 8)
19351 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19356 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19357 need to use DDmode, in all other cases we can use the same mode. */
19358 static machine_mode
19359 rs6000_secondary_memory_needed_mode (machine_mode mode)
19361 if (lra_in_progress && mode == SDmode)
19366 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19367 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19368 only work on the traditional altivec registers, note if an altivec register
19371 static enum rs6000_reg_type
19372 register_to_reg_type (rtx reg, bool *is_altivec)
19374 HOST_WIDE_INT regno;
19375 enum reg_class rclass;
19377 if (GET_CODE (reg) == SUBREG)
19378 reg = SUBREG_REG (reg);
19381 return NO_REG_TYPE;
19383 regno = REGNO (reg);
19384 if (regno >= FIRST_PSEUDO_REGISTER)
19386 if (!lra_in_progress && !reload_completed)
19387 return PSEUDO_REG_TYPE;
19389 regno = true_regnum (reg);
19390 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
19391 return PSEUDO_REG_TYPE;
19394 gcc_assert (regno >= 0);
19396 if (is_altivec && ALTIVEC_REGNO_P (regno))
19397 *is_altivec = true;
19399 rclass = rs6000_regno_regclass[regno];
19400 return reg_class_to_reg_type[(int)rclass];
19403 /* Helper function to return the cost of adding a TOC entry address. */
19406 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
19410 if (TARGET_CMODEL != CMODEL_SMALL)
19411 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
19414 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
19419 /* Helper function for rs6000_secondary_reload to determine whether the memory
19420 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19421 needs reloading. Return negative if the memory is not handled by the memory
19422 helper functions and to try a different reload method, 0 if no additional
19423 instructions are need, and positive to give the extra cost for the
19427 rs6000_secondary_reload_memory (rtx addr,
19428 enum reg_class rclass,
19431 int extra_cost = 0;
19432 rtx reg, and_arg, plus_arg0, plus_arg1;
19433 addr_mask_type addr_mask;
19434 const char *type = NULL;
19435 const char *fail_msg = NULL;
19437 if (GPR_REG_CLASS_P (rclass))
19438 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19440 else if (rclass == FLOAT_REGS)
19441 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19443 else if (rclass == ALTIVEC_REGS)
19444 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19446 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19447 else if (rclass == VSX_REGS)
19448 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
19449 & ~RELOAD_REG_AND_M16);
19451 /* If the register allocator hasn't made up its mind yet on the register
19452 class to use, settle on defaults to use. */
19453 else if (rclass == NO_REGS)
19455 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
19456 & ~RELOAD_REG_AND_M16);
19458 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
19459 addr_mask &= ~(RELOAD_REG_INDEXED
19460 | RELOAD_REG_PRE_INCDEC
19461 | RELOAD_REG_PRE_MODIFY);
19467 /* If the register isn't valid in this register class, just return now. */
19468 if ((addr_mask & RELOAD_REG_VALID) == 0)
19470 if (TARGET_DEBUG_ADDR)
19473 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19474 "not valid in class\n",
19475 GET_MODE_NAME (mode), reg_class_names[rclass]);
19482 switch (GET_CODE (addr))
19484 /* Does the register class supports auto update forms for this mode? We
19485 don't need a scratch register, since the powerpc only supports
19486 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19489 reg = XEXP (addr, 0);
19490 if (!base_reg_operand (addr, GET_MODE (reg)))
19492 fail_msg = "no base register #1";
19496 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19504 reg = XEXP (addr, 0);
19505 plus_arg1 = XEXP (addr, 1);
19506 if (!base_reg_operand (reg, GET_MODE (reg))
19507 || GET_CODE (plus_arg1) != PLUS
19508 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
19510 fail_msg = "bad PRE_MODIFY";
19514 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19521 /* Do we need to simulate AND -16 to clear the bottom address bits used
19522 in VMX load/stores? Only allow the AND for vector sizes. */
19524 and_arg = XEXP (addr, 0);
19525 if (GET_MODE_SIZE (mode) != 16
19526 || GET_CODE (XEXP (addr, 1)) != CONST_INT
19527 || INTVAL (XEXP (addr, 1)) != -16)
19529 fail_msg = "bad Altivec AND #1";
19533 if (rclass != ALTIVEC_REGS)
19535 if (legitimate_indirect_address_p (and_arg, false))
19538 else if (legitimate_indexed_address_p (and_arg, false))
19543 fail_msg = "bad Altivec AND #2";
19551 /* If this is an indirect address, make sure it is a base register. */
19554 if (!legitimate_indirect_address_p (addr, false))
19561 /* If this is an indexed address, make sure the register class can handle
19562 indexed addresses for this mode. */
19564 plus_arg0 = XEXP (addr, 0);
19565 plus_arg1 = XEXP (addr, 1);
19567 /* (plus (plus (reg) (constant)) (constant)) is generated during
19568 push_reload processing, so handle it now. */
19569 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19571 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19578 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19579 push_reload processing, so handle it now. */
19580 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19582 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19585 type = "indexed #2";
19589 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19591 fail_msg = "no base register #2";
19595 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19597 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19598 || !legitimate_indexed_address_p (addr, false))
19605 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19606 && CONST_INT_P (plus_arg1))
19608 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19611 type = "vector d-form offset";
19615 /* Make sure the register class can handle offset addresses. */
19616 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19618 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19621 type = "offset #2";
19627 fail_msg = "bad PLUS";
19634 /* Quad offsets are restricted and can't handle normal addresses. */
19635 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19638 type = "vector d-form lo_sum";
19641 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19643 fail_msg = "bad LO_SUM";
19647 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19654 /* Static addresses need to create a TOC entry. */
19658 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19661 type = "vector d-form lo_sum #2";
19667 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19671 /* TOC references look like offsetable memory. */
19673 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19675 fail_msg = "bad UNSPEC";
19679 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19682 type = "vector d-form lo_sum #3";
19685 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19688 type = "toc reference";
19694 fail_msg = "bad address";
19699 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19701 if (extra_cost < 0)
19703 "rs6000_secondary_reload_memory error: mode = %s, "
19704 "class = %s, addr_mask = '%s', %s\n",
19705 GET_MODE_NAME (mode),
19706 reg_class_names[rclass],
19707 rs6000_debug_addr_mask (addr_mask, false),
19708 (fail_msg != NULL) ? fail_msg : "<bad address>");
19712 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19713 "addr_mask = '%s', extra cost = %d, %s\n",
19714 GET_MODE_NAME (mode),
19715 reg_class_names[rclass],
19716 rs6000_debug_addr_mask (addr_mask, false),
19718 (type) ? type : "<none>");
19726 /* Helper function for rs6000_secondary_reload to return true if a move to a
19727 different register classe is really a simple move. */
19730 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19731 enum rs6000_reg_type from_type,
19734 int size = GET_MODE_SIZE (mode);
19736 /* Add support for various direct moves available. In this function, we only
19737 look at cases where we don't need any extra registers, and one or more
19738 simple move insns are issued. Originally small integers are not allowed
19739 in FPR/VSX registers. Single precision binary floating is not a simple
19740 move because we need to convert to the single precision memory layout.
19741 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19742 need special direct move handling, which we do not support yet. */
19743 if (TARGET_DIRECT_MOVE
19744 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19745 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19747 if (TARGET_POWERPC64)
19749 /* ISA 2.07: MTVSRD or MVFVSRD. */
19753 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19754 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19758 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19759 if (TARGET_P8_VECTOR)
19761 if (mode == SImode)
19764 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19768 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19769 if (mode == SDmode)
19773 /* Power6+: MFTGPR or MFFGPR. */
19774 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19775 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19776 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19779 /* Move to/from SPR. */
19780 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19781 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19782 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19788 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19789 special direct moves that involve allocating an extra register, return the
19790 insn code of the helper function if there is such a function or
19791 CODE_FOR_nothing if not. */
19794 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19795 enum rs6000_reg_type from_type,
19797 secondary_reload_info *sri,
19801 enum insn_code icode = CODE_FOR_nothing;
19803 int size = GET_MODE_SIZE (mode);
19805 if (TARGET_POWERPC64 && size == 16)
19807 /* Handle moving 128-bit values from GPRs to VSX point registers on
19808 ISA 2.07 (power8, power9) when running in 64-bit mode using
19809 XXPERMDI to glue the two 64-bit values back together. */
19810 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19812 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19813 icode = reg_addr[mode].reload_vsx_gpr;
19816 /* Handle moving 128-bit values from VSX point registers to GPRs on
19817 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19818 bottom 64-bit value. */
19819 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19821 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19822 icode = reg_addr[mode].reload_gpr_vsx;
19826 else if (TARGET_POWERPC64 && mode == SFmode)
19828 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19830 cost = 3; /* xscvdpspn, mfvsrd, and. */
19831 icode = reg_addr[mode].reload_gpr_vsx;
19834 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19836 cost = 2; /* mtvsrz, xscvspdpn. */
19837 icode = reg_addr[mode].reload_vsx_gpr;
19841 else if (!TARGET_POWERPC64 && size == 8)
19843 /* Handle moving 64-bit values from GPRs to floating point registers on
19844 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19845 32-bit values back together. Altivec register classes must be handled
19846 specially since a different instruction is used, and the secondary
19847 reload support requires a single instruction class in the scratch
19848 register constraint. However, right now TFmode is not allowed in
19849 Altivec registers, so the pattern will never match. */
19850 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19852 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19853 icode = reg_addr[mode].reload_fpr_gpr;
19857 if (icode != CODE_FOR_nothing)
19862 sri->icode = icode;
19863 sri->extra_cost = cost;
19870 /* Return whether a move between two register classes can be done either
19871 directly (simple move) or via a pattern that uses a single extra temporary
19872 (using ISA 2.07's direct move in this case. */
19875 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19876 enum rs6000_reg_type from_type,
19878 secondary_reload_info *sri,
19881 /* Fall back to load/store reloads if either type is not a register. */
19882 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19885 /* If we haven't allocated registers yet, assume the move can be done for the
19886 standard register types. */
19887 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19888 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19889 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19892 /* Moves to the same set of registers is a simple move for non-specialized
19894 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19897 /* Check whether a simple move can be done directly. */
19898 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19902 sri->icode = CODE_FOR_nothing;
19903 sri->extra_cost = 0;
19908 /* Now check if we can do it in a few steps. */
19909 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19913 /* Inform reload about cases where moving X with a mode MODE to a register in
19914 RCLASS requires an extra scratch or immediate register. Return the class
19915 needed for the immediate register.
19917 For VSX and Altivec, we may need a register to convert sp+offset into
19920 For misaligned 64-bit gpr loads and stores we need a register to
19921 convert an offset address to indirect. */
19924 rs6000_secondary_reload (bool in_p,
19926 reg_class_t rclass_i,
19928 secondary_reload_info *sri)
19930 enum reg_class rclass = (enum reg_class) rclass_i;
19931 reg_class_t ret = ALL_REGS;
19932 enum insn_code icode;
19933 bool default_p = false;
19934 bool done_p = false;
19936 /* Allow subreg of memory before/during reload. */
19937 bool memory_p = (MEM_P (x)
19938 || (!reload_completed && GET_CODE (x) == SUBREG
19939 && MEM_P (SUBREG_REG (x))));
19941 sri->icode = CODE_FOR_nothing;
19942 sri->t_icode = CODE_FOR_nothing;
19943 sri->extra_cost = 0;
19945 ? reg_addr[mode].reload_load
19946 : reg_addr[mode].reload_store);
19948 if (REG_P (x) || register_operand (x, mode))
19950 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19951 bool altivec_p = (rclass == ALTIVEC_REGS);
19952 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19955 std::swap (to_type, from_type);
19957 /* Can we do a direct move of some sort? */
19958 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19961 icode = (enum insn_code)sri->icode;
19968 /* Make sure 0.0 is not reloaded or forced into memory. */
19969 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19976 /* If this is a scalar floating point value and we want to load it into the
19977 traditional Altivec registers, do it via a move via a traditional floating
19978 point register, unless we have D-form addressing. Also make sure that
19979 non-zero constants use a FPR. */
19980 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19981 && !mode_supports_vmx_dform (mode)
19982 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19983 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
19990 /* Handle reload of load/stores if we have reload helper functions. */
19991 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19993 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19996 if (extra_cost >= 0)
20000 if (extra_cost > 0)
20002 sri->extra_cost = extra_cost;
20003 sri->icode = icode;
20008 /* Handle unaligned loads and stores of integer registers. */
20009 if (!done_p && TARGET_POWERPC64
20010 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20012 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
20014 rtx addr = XEXP (x, 0);
20015 rtx off = address_offset (addr);
20017 if (off != NULL_RTX)
20019 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20020 unsigned HOST_WIDE_INT offset = INTVAL (off);
20022 /* We need a secondary reload when our legitimate_address_p
20023 says the address is good (as otherwise the entire address
20024 will be reloaded), and the offset is not a multiple of
20025 four or we have an address wrap. Address wrap will only
20026 occur for LO_SUMs since legitimate_offset_address_p
20027 rejects addresses for 16-byte mems that will wrap. */
20028 if (GET_CODE (addr) == LO_SUM
20029 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20030 && ((offset & 3) != 0
20031 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
20032 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
20033 && (offset & 3) != 0))
20035 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20037 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
20038 : CODE_FOR_reload_di_load);
20040 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
20041 : CODE_FOR_reload_di_store);
20042 sri->extra_cost = 2;
20053 if (!done_p && !TARGET_POWERPC64
20054 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20056 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
20058 rtx addr = XEXP (x, 0);
20059 rtx off = address_offset (addr);
20061 if (off != NULL_RTX)
20063 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20064 unsigned HOST_WIDE_INT offset = INTVAL (off);
20066 /* We need a secondary reload when our legitimate_address_p
20067 says the address is good (as otherwise the entire address
20068 will be reloaded), and we have a wrap.
20070 legitimate_lo_sum_address_p allows LO_SUM addresses to
20071 have any offset so test for wrap in the low 16 bits.
20073 legitimate_offset_address_p checks for the range
20074 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20075 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20076 [0x7ff4,0x7fff] respectively, so test for the
20077 intersection of these ranges, [0x7ffc,0x7fff] and
20078 [0x7ff4,0x7ff7] respectively.
20080 Note that the address we see here may have been
20081 manipulated by legitimize_reload_address. */
20082 if (GET_CODE (addr) == LO_SUM
20083 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
20084 : offset - (0x8000 - extra) < UNITS_PER_WORD)
20087 sri->icode = CODE_FOR_reload_si_load;
20089 sri->icode = CODE_FOR_reload_si_store;
20090 sri->extra_cost = 2;
20105 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
20107 gcc_assert (ret != ALL_REGS);
20109 if (TARGET_DEBUG_ADDR)
20112 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20114 reg_class_names[ret],
20115 in_p ? "true" : "false",
20116 reg_class_names[rclass],
20117 GET_MODE_NAME (mode));
20119 if (reload_completed)
20120 fputs (", after reload", stderr);
20123 fputs (", done_p not set", stderr);
20126 fputs (", default secondary reload", stderr);
20128 if (sri->icode != CODE_FOR_nothing)
20129 fprintf (stderr, ", reload func = %s, extra cost = %d",
20130 insn_data[sri->icode].name, sri->extra_cost);
20132 else if (sri->extra_cost > 0)
20133 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
20135 fputs ("\n", stderr);
20142 /* Better tracing for rs6000_secondary_reload_inner. */
20145 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
20150 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
20152 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
20153 store_p ? "store" : "load");
20156 set = gen_rtx_SET (mem, reg);
20158 set = gen_rtx_SET (reg, mem);
20160 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
20161 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
20164 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
20165 ATTRIBUTE_NORETURN;
20168 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
20171 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
20172 gcc_unreachable ();
20175 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20176 reload helper functions. These were identified in
20177 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20178 reload, it calls the insns:
20179 reload_<RELOAD:mode>_<P:mptrsize>_store
20180 reload_<RELOAD:mode>_<P:mptrsize>_load
20182 which in turn calls this function, to do whatever is necessary to create
20183 valid addresses. */
20186 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
20188 int regno = true_regnum (reg);
20189 machine_mode mode = GET_MODE (reg);
20190 addr_mask_type addr_mask;
20193 rtx op_reg, op0, op1;
20198 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
20199 || !base_reg_operand (scratch, GET_MODE (scratch)))
20200 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20202 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
20203 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
20205 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
20206 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
20208 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
20209 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
20212 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20214 /* Make sure the mode is valid in this register class. */
20215 if ((addr_mask & RELOAD_REG_VALID) == 0)
20216 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20218 if (TARGET_DEBUG_ADDR)
20219 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
20221 new_addr = addr = XEXP (mem, 0);
20222 switch (GET_CODE (addr))
20224 /* Does the register class support auto update forms for this mode? If
20225 not, do the update now. We don't need a scratch register, since the
20226 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20229 op_reg = XEXP (addr, 0);
20230 if (!base_reg_operand (op_reg, Pmode))
20231 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20233 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
20235 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
20241 op0 = XEXP (addr, 0);
20242 op1 = XEXP (addr, 1);
20243 if (!base_reg_operand (op0, Pmode)
20244 || GET_CODE (op1) != PLUS
20245 || !rtx_equal_p (op0, XEXP (op1, 0)))
20246 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20248 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
20250 emit_insn (gen_rtx_SET (op0, op1));
20255 /* Do we need to simulate AND -16 to clear the bottom address bits used
20256 in VMX load/stores? */
20258 op0 = XEXP (addr, 0);
20259 op1 = XEXP (addr, 1);
20260 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
20262 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
20265 else if (GET_CODE (op1) == PLUS)
20267 emit_insn (gen_rtx_SET (scratch, op1));
20272 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20274 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
20275 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
20276 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
20277 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
20278 new_addr = scratch;
20282 /* If this is an indirect address, make sure it is a base register. */
20285 if (!base_reg_operand (addr, GET_MODE (addr)))
20287 emit_insn (gen_rtx_SET (scratch, addr));
20288 new_addr = scratch;
20292 /* If this is an indexed address, make sure the register class can handle
20293 indexed addresses for this mode. */
20295 op0 = XEXP (addr, 0);
20296 op1 = XEXP (addr, 1);
20297 if (!base_reg_operand (op0, Pmode))
20298 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20300 else if (int_reg_operand (op1, Pmode))
20302 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20304 emit_insn (gen_rtx_SET (scratch, addr));
20305 new_addr = scratch;
20309 else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
20311 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
20312 || !quad_address_p (addr, mode, false))
20314 emit_insn (gen_rtx_SET (scratch, addr));
20315 new_addr = scratch;
20319 /* Make sure the register class can handle offset addresses. */
20320 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
20322 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20324 emit_insn (gen_rtx_SET (scratch, addr));
20325 new_addr = scratch;
20330 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20335 op0 = XEXP (addr, 0);
20336 op1 = XEXP (addr, 1);
20337 if (!base_reg_operand (op0, Pmode))
20338 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20340 else if (int_reg_operand (op1, Pmode))
20342 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20344 emit_insn (gen_rtx_SET (scratch, addr));
20345 new_addr = scratch;
20349 /* Quad offsets are restricted and can't handle normal addresses. */
20350 else if (mode_supports_vsx_dform_quad (mode))
20352 emit_insn (gen_rtx_SET (scratch, addr));
20353 new_addr = scratch;
20356 /* Make sure the register class can handle offset addresses. */
20357 else if (legitimate_lo_sum_address_p (mode, addr, false))
20359 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20361 emit_insn (gen_rtx_SET (scratch, addr));
20362 new_addr = scratch;
20367 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20374 rs6000_emit_move (scratch, addr, Pmode);
20375 new_addr = scratch;
20379 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20382 /* Adjust the address if it changed. */
20383 if (addr != new_addr)
20385 mem = replace_equiv_address_nv (mem, new_addr);
20386 if (TARGET_DEBUG_ADDR)
20387 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20390 /* Now create the move. */
20392 emit_insn (gen_rtx_SET (mem, reg));
20394 emit_insn (gen_rtx_SET (reg, mem));
20399 /* Convert reloads involving 64-bit gprs and misaligned offset
20400 addressing, or multiple 32-bit gprs and offsets that are too large,
20401 to use indirect addressing. */
20404 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
20406 int regno = true_regnum (reg);
20407 enum reg_class rclass;
20409 rtx scratch_or_premodify = scratch;
20411 if (TARGET_DEBUG_ADDR)
20413 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
20414 store_p ? "store" : "load");
20415 fprintf (stderr, "reg:\n");
20417 fprintf (stderr, "mem:\n");
20419 fprintf (stderr, "scratch:\n");
20420 debug_rtx (scratch);
20423 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
20424 gcc_assert (GET_CODE (mem) == MEM);
20425 rclass = REGNO_REG_CLASS (regno);
20426 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
20427 addr = XEXP (mem, 0);
20429 if (GET_CODE (addr) == PRE_MODIFY)
20431 gcc_assert (REG_P (XEXP (addr, 0))
20432 && GET_CODE (XEXP (addr, 1)) == PLUS
20433 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
20434 scratch_or_premodify = XEXP (addr, 0);
20435 if (!HARD_REGISTER_P (scratch_or_premodify))
20436 /* If we have a pseudo here then reload will have arranged
20437 to have it replaced, but only in the original insn.
20438 Use the replacement here too. */
20439 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
20441 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20442 expressions from the original insn, without unsharing them.
20443 Any RTL that points into the original insn will of course
20444 have register replacements applied. That is why we don't
20445 need to look for replacements under the PLUS. */
20446 addr = XEXP (addr, 1);
20448 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
20450 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
20452 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
20454 /* Now create the move. */
20456 emit_insn (gen_rtx_SET (mem, reg));
20458 emit_insn (gen_rtx_SET (reg, mem));
20463 /* Given an rtx X being reloaded into a reg required to be
20464 in class CLASS, return the class of reg to actually use.
20465 In general this is just CLASS; but on some machines
20466 in some cases it is preferable to use a more restrictive class.
20468 On the RS/6000, we have to return NO_REGS when we want to reload a
20469 floating-point CONST_DOUBLE to force it to be copied to memory.
20471 We also don't want to reload integer values into floating-point
20472 registers if we can at all help it. In fact, this can
20473 cause reload to die, if it tries to generate a reload of CTR
20474 into a FP register and discovers it doesn't have the memory location
20477 ??? Would it be a good idea to have reload do the converse, that is
20478 try to reload floating modes into FP registers if possible?
20481 static enum reg_class
20482 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
20484 machine_mode mode = GET_MODE (x);
20485 bool is_constant = CONSTANT_P (x);
20487 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20488 reload class for it. */
20489 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20490 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
20493 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
20494 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
20497 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20498 the reloading of address expressions using PLUS into floating point
20500 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
20504 /* Zero is always allowed in all VSX registers. */
20505 if (x == CONST0_RTX (mode))
20508 /* If this is a vector constant that can be formed with a few Altivec
20509 instructions, we want altivec registers. */
20510 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
20511 return ALTIVEC_REGS;
20513 /* If this is an integer constant that can easily be loaded into
20514 vector registers, allow it. */
20515 if (CONST_INT_P (x))
20517 HOST_WIDE_INT value = INTVAL (x);
20519 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20520 2.06 can generate it in the Altivec registers with
20524 if (TARGET_P8_VECTOR)
20526 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20527 return ALTIVEC_REGS;
20532 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20533 a sign extend in the Altivec registers. */
20534 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
20535 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
20536 return ALTIVEC_REGS;
20539 /* Force constant to memory. */
20543 /* D-form addressing can easily reload the value. */
20544 if (mode_supports_vmx_dform (mode)
20545 || mode_supports_vsx_dform_quad (mode))
20548 /* If this is a scalar floating point value and we don't have D-form
20549 addressing, prefer the traditional floating point registers so that we
20550 can use D-form (register+offset) addressing. */
20551 if (rclass == VSX_REGS
20552 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
20555 /* Prefer the Altivec registers if Altivec is handling the vector
20556 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20558 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20559 || mode == V1TImode)
20560 return ALTIVEC_REGS;
20565 if (is_constant || GET_CODE (x) == PLUS)
20567 if (reg_class_subset_p (GENERAL_REGS, rclass))
20568 return GENERAL_REGS;
20569 if (reg_class_subset_p (BASE_REGS, rclass))
20574 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20575 return GENERAL_REGS;
20580 /* Debug version of rs6000_preferred_reload_class. */
20581 static enum reg_class
20582 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20584 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20587 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20589 reg_class_names[ret], reg_class_names[rclass],
20590 GET_MODE_NAME (GET_MODE (x)));
20596 /* If we are copying between FP or AltiVec registers and anything else, we need
20597 a memory location. The exception is when we are targeting ppc64 and the
20598 move to/from fpr to gpr instructions are available. Also, under VSX, you
20599 can copy vector registers from the FP register set to the Altivec register
20600 set and vice versa. */
20603 rs6000_secondary_memory_needed (machine_mode mode,
20604 reg_class_t from_class,
20605 reg_class_t to_class)
20607 enum rs6000_reg_type from_type, to_type;
20608 bool altivec_p = ((from_class == ALTIVEC_REGS)
20609 || (to_class == ALTIVEC_REGS));
20611 /* If a simple/direct move is available, we don't need secondary memory */
20612 from_type = reg_class_to_reg_type[(int)from_class];
20613 to_type = reg_class_to_reg_type[(int)to_class];
20615 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20616 (secondary_reload_info *)0, altivec_p))
20619 /* If we have a floating point or vector register class, we need to use
20620 memory to transfer the data. */
20621 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20627 /* Debug version of rs6000_secondary_memory_needed. */
20629 rs6000_debug_secondary_memory_needed (machine_mode mode,
20630 reg_class_t from_class,
20631 reg_class_t to_class)
20633 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20636 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20637 "to_class = %s, mode = %s\n",
20638 ret ? "true" : "false",
20639 reg_class_names[from_class],
20640 reg_class_names[to_class],
20641 GET_MODE_NAME (mode));
20646 /* Return the register class of a scratch register needed to copy IN into
20647 or out of a register in RCLASS in MODE. If it can be done directly,
20648 NO_REGS is returned. */
20650 static enum reg_class
20651 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20656 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20658 && MACHOPIC_INDIRECT
20662 /* We cannot copy a symbolic operand directly into anything
20663 other than BASE_REGS for TARGET_ELF. So indicate that a
20664 register from BASE_REGS is needed as an intermediate
20667 On Darwin, pic addresses require a load from memory, which
20668 needs a base register. */
20669 if (rclass != BASE_REGS
20670 && (GET_CODE (in) == SYMBOL_REF
20671 || GET_CODE (in) == HIGH
20672 || GET_CODE (in) == LABEL_REF
20673 || GET_CODE (in) == CONST))
20677 if (GET_CODE (in) == REG)
20679 regno = REGNO (in);
20680 if (regno >= FIRST_PSEUDO_REGISTER)
20682 regno = true_regnum (in);
20683 if (regno >= FIRST_PSEUDO_REGISTER)
20687 else if (GET_CODE (in) == SUBREG)
20689 regno = true_regnum (in);
20690 if (regno >= FIRST_PSEUDO_REGISTER)
20696 /* If we have VSX register moves, prefer moving scalar values between
20697 Altivec registers and GPR by going via an FPR (and then via memory)
20698 instead of reloading the secondary memory address for Altivec moves. */
20700 && GET_MODE_SIZE (mode) < 16
20701 && !mode_supports_vmx_dform (mode)
20702 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20703 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20704 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20705 && (regno >= 0 && INT_REGNO_P (regno)))))
20708 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20710 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20711 || (regno >= 0 && INT_REGNO_P (regno)))
20714 /* Constants, memory, and VSX registers can go into VSX registers (both the
20715 traditional floating point and the altivec registers). */
20716 if (rclass == VSX_REGS
20717 && (regno == -1 || VSX_REGNO_P (regno)))
20720 /* Constants, memory, and FP registers can go into FP registers. */
20721 if ((regno == -1 || FP_REGNO_P (regno))
20722 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20723 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20725 /* Memory, and AltiVec registers can go into AltiVec registers. */
20726 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20727 && rclass == ALTIVEC_REGS)
20730 /* We can copy among the CR registers. */
20731 if ((rclass == CR_REGS || rclass == CR0_REGS)
20732 && regno >= 0 && CR_REGNO_P (regno))
20735 /* Otherwise, we need GENERAL_REGS. */
20736 return GENERAL_REGS;
20739 /* Debug version of rs6000_secondary_reload_class. */
20740 static enum reg_class
20741 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20742 machine_mode mode, rtx in)
20744 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20746 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20747 "mode = %s, input rtx:\n",
20748 reg_class_names[ret], reg_class_names[rclass],
20749 GET_MODE_NAME (mode));
20755 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20758 rs6000_can_change_mode_class (machine_mode from,
20760 reg_class_t rclass)
20762 unsigned from_size = GET_MODE_SIZE (from);
20763 unsigned to_size = GET_MODE_SIZE (to);
20765 if (from_size != to_size)
20767 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20769 if (reg_classes_intersect_p (xclass, rclass))
20771 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20772 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20773 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20774 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20776 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20777 single register under VSX because the scalar part of the register
20778 is in the upper 64-bits, and not the lower 64-bits. Types like
20779 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20780 IEEE floating point can't overlap, and neither can small
20783 if (to_float128_vector_p && from_float128_vector_p)
20786 else if (to_float128_vector_p || from_float128_vector_p)
20789 /* TDmode in floating-mode registers must always go into a register
20790 pair with the most significant word in the even-numbered register
20791 to match ISA requirements. In little-endian mode, this does not
20792 match subreg numbering, so we cannot allow subregs. */
20793 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20796 if (from_size < 8 || to_size < 8)
20799 if (from_size == 8 && (8 * to_nregs) != to_size)
20802 if (to_size == 8 && (8 * from_nregs) != from_size)
20811 /* Since the VSX register set includes traditional floating point registers
20812 and altivec registers, just check for the size being different instead of
20813 trying to check whether the modes are vector modes. Otherwise it won't
20814 allow say DF and DI to change classes. For types like TFmode and TDmode
20815 that take 2 64-bit registers, rather than a single 128-bit register, don't
20816 allow subregs of those types to other 128 bit types. */
20817 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20819 unsigned num_regs = (from_size + 15) / 16;
20820 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20821 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20824 return (from_size == 8 || from_size == 16);
20827 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20828 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20834 /* Debug version of rs6000_can_change_mode_class. */
20836 rs6000_debug_can_change_mode_class (machine_mode from,
20838 reg_class_t rclass)
20840 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20843 "rs6000_can_change_mode_class, return %s, from = %s, "
20844 "to = %s, rclass = %s\n",
20845 ret ? "true" : "false",
20846 GET_MODE_NAME (from), GET_MODE_NAME (to),
20847 reg_class_names[rclass]);
20852 /* Return a string to do a move operation of 128 bits of data. */
20855 rs6000_output_move_128bit (rtx operands[])
20857 rtx dest = operands[0];
20858 rtx src = operands[1];
20859 machine_mode mode = GET_MODE (dest);
20862 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20863 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20867 dest_regno = REGNO (dest);
20868 dest_gpr_p = INT_REGNO_P (dest_regno);
20869 dest_fp_p = FP_REGNO_P (dest_regno);
20870 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20871 dest_vsx_p = dest_fp_p | dest_vmx_p;
20876 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20881 src_regno = REGNO (src);
20882 src_gpr_p = INT_REGNO_P (src_regno);
20883 src_fp_p = FP_REGNO_P (src_regno);
20884 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20885 src_vsx_p = src_fp_p | src_vmx_p;
20890 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20893 /* Register moves. */
20894 if (dest_regno >= 0 && src_regno >= 0)
20901 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20902 return (WORDS_BIG_ENDIAN
20903 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20904 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20906 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20910 else if (TARGET_VSX && dest_vsx_p)
20913 return "xxlor %x0,%x1,%x1";
20915 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20916 return (WORDS_BIG_ENDIAN
20917 ? "mtvsrdd %x0,%1,%L1"
20918 : "mtvsrdd %x0,%L1,%1");
20920 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20924 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20925 return "vor %0,%1,%1";
20927 else if (dest_fp_p && src_fp_p)
20932 else if (dest_regno >= 0 && MEM_P (src))
20936 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20942 else if (TARGET_ALTIVEC && dest_vmx_p
20943 && altivec_indexed_or_indirect_operand (src, mode))
20944 return "lvx %0,%y1";
20946 else if (TARGET_VSX && dest_vsx_p)
20948 if (mode_supports_vsx_dform_quad (mode)
20949 && quad_address_p (XEXP (src, 0), mode, true))
20950 return "lxv %x0,%1";
20952 else if (TARGET_P9_VECTOR)
20953 return "lxvx %x0,%y1";
20955 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20956 return "lxvw4x %x0,%y1";
20959 return "lxvd2x %x0,%y1";
20962 else if (TARGET_ALTIVEC && dest_vmx_p)
20963 return "lvx %0,%y1";
20965 else if (dest_fp_p)
20970 else if (src_regno >= 0 && MEM_P (dest))
20974 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20975 return "stq %1,%0";
20980 else if (TARGET_ALTIVEC && src_vmx_p
20981 && altivec_indexed_or_indirect_operand (src, mode))
20982 return "stvx %1,%y0";
20984 else if (TARGET_VSX && src_vsx_p)
20986 if (mode_supports_vsx_dform_quad (mode)
20987 && quad_address_p (XEXP (dest, 0), mode, true))
20988 return "stxv %x1,%0";
20990 else if (TARGET_P9_VECTOR)
20991 return "stxvx %x1,%y0";
20993 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20994 return "stxvw4x %x1,%y0";
20997 return "stxvd2x %x1,%y0";
21000 else if (TARGET_ALTIVEC && src_vmx_p)
21001 return "stvx %1,%y0";
21008 else if (dest_regno >= 0
21009 && (GET_CODE (src) == CONST_INT
21010 || GET_CODE (src) == CONST_WIDE_INT
21011 || GET_CODE (src) == CONST_DOUBLE
21012 || GET_CODE (src) == CONST_VECTOR))
21017 else if ((dest_vmx_p && TARGET_ALTIVEC)
21018 || (dest_vsx_p && TARGET_VSX))
21019 return output_vec_const_move (operands);
21022 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
21025 /* Validate a 128-bit move. */
21027 rs6000_move_128bit_ok_p (rtx operands[])
21029 machine_mode mode = GET_MODE (operands[0]);
21030 return (gpc_reg_operand (operands[0], mode)
21031 || gpc_reg_operand (operands[1], mode));
21034 /* Return true if a 128-bit move needs to be split. */
21036 rs6000_split_128bit_ok_p (rtx operands[])
21038 if (!reload_completed)
21041 if (!gpr_or_gpr_p (operands[0], operands[1]))
21044 if (quad_load_store_p (operands[0], operands[1]))
21051 /* Given a comparison operation, return the bit number in CCR to test. We
21052 know this is a valid comparison.
21054 SCC_P is 1 if this is for an scc. That means that %D will have been
21055 used instead of %C, so the bits will be in different places.
21057 Return -1 if OP isn't a valid comparison for some reason. */
21060 ccr_bit (rtx op, int scc_p)
21062 enum rtx_code code = GET_CODE (op);
21063 machine_mode cc_mode;
21068 if (!COMPARISON_P (op))
21071 reg = XEXP (op, 0);
21073 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
21075 cc_mode = GET_MODE (reg);
21076 cc_regnum = REGNO (reg);
21077 base_bit = 4 * (cc_regnum - CR0_REGNO);
21079 validate_condition_mode (code, cc_mode);
21081 /* When generating a sCOND operation, only positive conditions are
21084 || code == EQ || code == GT || code == LT || code == UNORDERED
21085 || code == GTU || code == LTU);
21090 return scc_p ? base_bit + 3 : base_bit + 2;
21092 return base_bit + 2;
21093 case GT: case GTU: case UNLE:
21094 return base_bit + 1;
21095 case LT: case LTU: case UNGE:
21097 case ORDERED: case UNORDERED:
21098 return base_bit + 3;
21101 /* If scc, we will have done a cror to put the bit in the
21102 unordered position. So test that bit. For integer, this is ! LT
21103 unless this is an scc insn. */
21104 return scc_p ? base_bit + 3 : base_bit;
21107 return scc_p ? base_bit + 3 : base_bit + 1;
21110 gcc_unreachable ();
21114 /* Return the GOT register. */
21117 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
21119 /* The second flow pass currently (June 1999) can't update
21120 regs_ever_live without disturbing other parts of the compiler, so
21121 update it here to make the prolog/epilogue code happy. */
21122 if (!can_create_pseudo_p ()
21123 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21124 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
21126 crtl->uses_pic_offset_table = 1;
21128 return pic_offset_table_rtx;
21131 static rs6000_stack_t stack_info;
21133 /* Function to init struct machine_function.
21134 This will be called, via a pointer variable,
21135 from push_function_context. */
21137 static struct machine_function *
21138 rs6000_init_machine_status (void)
21140 stack_info.reload_completed = 0;
21141 return ggc_cleared_alloc<machine_function> ();
21144 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21146 /* Write out a function code label. */
21149 rs6000_output_function_entry (FILE *file, const char *fname)
21151 if (fname[0] != '.')
21153 switch (DEFAULT_ABI)
21156 gcc_unreachable ();
21162 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
21172 RS6000_OUTPUT_BASENAME (file, fname);
21175 /* Print an operand. Recognize special options, documented below. */
21178 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21179 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21181 #define SMALL_DATA_RELOC "sda21"
21182 #define SMALL_DATA_REG 0
21186 print_operand (FILE *file, rtx x, int code)
21189 unsigned HOST_WIDE_INT uval;
21193 /* %a is output_address. */
21195 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21199 /* Like 'J' but get to the GT bit only. */
21200 gcc_assert (REG_P (x));
21202 /* Bit 1 is GT bit. */
21203 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
21205 /* Add one for shift count in rlinm for scc. */
21206 fprintf (file, "%d", i + 1);
21210 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21213 output_operand_lossage ("invalid %%e value");
21218 if ((uval & 0xffff) == 0 && uval != 0)
21223 /* X is a CR register. Print the number of the EQ bit of the CR */
21224 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21225 output_operand_lossage ("invalid %%E value");
21227 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
21231 /* X is a CR register. Print the shift count needed to move it
21232 to the high-order four bits. */
21233 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21234 output_operand_lossage ("invalid %%f value");
21236 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
21240 /* Similar, but print the count for the rotate in the opposite
21242 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21243 output_operand_lossage ("invalid %%F value");
21245 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
21249 /* X is a constant integer. If it is negative, print "m",
21250 otherwise print "z". This is to make an aze or ame insn. */
21251 if (GET_CODE (x) != CONST_INT)
21252 output_operand_lossage ("invalid %%G value");
21253 else if (INTVAL (x) >= 0)
21260 /* If constant, output low-order five bits. Otherwise, write
21263 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
21265 print_operand (file, x, 0);
21269 /* If constant, output low-order six bits. Otherwise, write
21272 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
21274 print_operand (file, x, 0);
21278 /* Print `i' if this is a constant, else nothing. */
21284 /* Write the bit number in CCR for jump. */
21285 i = ccr_bit (x, 0);
21287 output_operand_lossage ("invalid %%j code");
21289 fprintf (file, "%d", i);
21293 /* Similar, but add one for shift count in rlinm for scc and pass
21294 scc flag to `ccr_bit'. */
21295 i = ccr_bit (x, 1);
21297 output_operand_lossage ("invalid %%J code");
21299 /* If we want bit 31, write a shift count of zero, not 32. */
21300 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21304 /* X must be a constant. Write the 1's complement of the
21307 output_operand_lossage ("invalid %%k value");
21309 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
21313 /* X must be a symbolic constant on ELF. Write an
21314 expression suitable for an 'addi' that adds in the low 16
21315 bits of the MEM. */
21316 if (GET_CODE (x) == CONST)
21318 if (GET_CODE (XEXP (x, 0)) != PLUS
21319 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
21320 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
21321 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
21322 output_operand_lossage ("invalid %%K value");
21324 print_operand_address (file, x);
21325 fputs ("@l", file);
21328 /* %l is output_asm_label. */
21331 /* Write second word of DImode or DFmode reference. Works on register
21332 or non-indexed memory only. */
21334 fputs (reg_names[REGNO (x) + 1], file);
21335 else if (MEM_P (x))
21337 machine_mode mode = GET_MODE (x);
21338 /* Handle possible auto-increment. Since it is pre-increment and
21339 we have already done it, we can just use an offset of word. */
21340 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21341 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21342 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21344 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21345 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21348 output_address (mode, XEXP (adjust_address_nv (x, SImode,
21352 if (small_data_operand (x, GET_MODE (x)))
21353 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21354 reg_names[SMALL_DATA_REG]);
21358 case 'N': /* Unused */
21359 /* Write the number of elements in the vector times 4. */
21360 if (GET_CODE (x) != PARALLEL)
21361 output_operand_lossage ("invalid %%N value");
21363 fprintf (file, "%d", XVECLEN (x, 0) * 4);
21366 case 'O': /* Unused */
21367 /* Similar, but subtract 1 first. */
21368 if (GET_CODE (x) != PARALLEL)
21369 output_operand_lossage ("invalid %%O value");
21371 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
21375 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21378 || (i = exact_log2 (INTVAL (x))) < 0)
21379 output_operand_lossage ("invalid %%p value");
21381 fprintf (file, "%d", i);
21385 /* The operand must be an indirect memory reference. The result
21386 is the register name. */
21387 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
21388 || REGNO (XEXP (x, 0)) >= 32)
21389 output_operand_lossage ("invalid %%P value");
21391 fputs (reg_names[REGNO (XEXP (x, 0))], file);
21395 /* This outputs the logical code corresponding to a boolean
21396 expression. The expression may have one or both operands
21397 negated (if one, only the first one). For condition register
21398 logical operations, it will also treat the negated
21399 CR codes as NOTs, but not handle NOTs of them. */
21401 const char *const *t = 0;
21403 enum rtx_code code = GET_CODE (x);
21404 static const char * const tbl[3][3] = {
21405 { "and", "andc", "nor" },
21406 { "or", "orc", "nand" },
21407 { "xor", "eqv", "xor" } };
21411 else if (code == IOR)
21413 else if (code == XOR)
21416 output_operand_lossage ("invalid %%q value");
21418 if (GET_CODE (XEXP (x, 0)) != NOT)
21422 if (GET_CODE (XEXP (x, 1)) == NOT)
21433 if (! TARGET_MFCRF)
21439 /* X is a CR register. Print the mask for `mtcrf'. */
21440 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21441 output_operand_lossage ("invalid %%R value");
21443 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
21447 /* Low 5 bits of 32 - value */
21449 output_operand_lossage ("invalid %%s value");
21451 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
21455 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21456 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
21458 /* Bit 3 is OV bit. */
21459 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
21461 /* If we want bit 31, write a shift count of zero, not 32. */
21462 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21466 /* Print the symbolic name of a branch target register. */
21467 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
21468 && REGNO (x) != CTR_REGNO))
21469 output_operand_lossage ("invalid %%T value");
21470 else if (REGNO (x) == LR_REGNO)
21471 fputs ("lr", file);
21473 fputs ("ctr", file);
21477 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21478 for use in unsigned operand. */
21481 output_operand_lossage ("invalid %%u value");
21486 if ((uval & 0xffff) == 0)
21489 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
21493 /* High-order 16 bits of constant for use in signed operand. */
21495 output_operand_lossage ("invalid %%v value");
21497 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
21498 (INTVAL (x) >> 16) & 0xffff);
21502 /* Print `u' if this has an auto-increment or auto-decrement. */
21504 && (GET_CODE (XEXP (x, 0)) == PRE_INC
21505 || GET_CODE (XEXP (x, 0)) == PRE_DEC
21506 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
21511 /* Print the trap code for this operand. */
21512 switch (GET_CODE (x))
21515 fputs ("eq", file); /* 4 */
21518 fputs ("ne", file); /* 24 */
21521 fputs ("lt", file); /* 16 */
21524 fputs ("le", file); /* 20 */
21527 fputs ("gt", file); /* 8 */
21530 fputs ("ge", file); /* 12 */
21533 fputs ("llt", file); /* 2 */
21536 fputs ("lle", file); /* 6 */
21539 fputs ("lgt", file); /* 1 */
21542 fputs ("lge", file); /* 5 */
21545 gcc_unreachable ();
21550 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21553 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21554 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21556 print_operand (file, x, 0);
21560 /* X is a FPR or Altivec register used in a VSX context. */
21561 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21562 output_operand_lossage ("invalid %%x value");
21565 int reg = REGNO (x);
21566 int vsx_reg = (FP_REGNO_P (reg)
21568 : reg - FIRST_ALTIVEC_REGNO + 32);
21570 #ifdef TARGET_REGNAMES
21571 if (TARGET_REGNAMES)
21572 fprintf (file, "%%vs%d", vsx_reg);
21575 fprintf (file, "%d", vsx_reg);
21581 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21582 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21583 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21588 /* Like 'L', for third word of TImode/PTImode */
21590 fputs (reg_names[REGNO (x) + 2], file);
21591 else if (MEM_P (x))
21593 machine_mode mode = GET_MODE (x);
21594 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21595 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21596 output_address (mode, plus_constant (Pmode,
21597 XEXP (XEXP (x, 0), 0), 8));
21598 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21599 output_address (mode, plus_constant (Pmode,
21600 XEXP (XEXP (x, 0), 0), 8));
21602 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21603 if (small_data_operand (x, GET_MODE (x)))
21604 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21605 reg_names[SMALL_DATA_REG]);
21610 /* X is a SYMBOL_REF. Write out the name preceded by a
21611 period and without any trailing data in brackets. Used for function
21612 names. If we are configured for System V (or the embedded ABI) on
21613 the PowerPC, do not emit the period, since those systems do not use
21614 TOCs and the like. */
21615 gcc_assert (GET_CODE (x) == SYMBOL_REF);
21617 /* For macho, check to see if we need a stub. */
21620 const char *name = XSTR (x, 0);
21622 if (darwin_emit_branch_islands
21623 && MACHOPIC_INDIRECT
21624 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21625 name = machopic_indirection_name (x, /*stub_p=*/true);
21627 assemble_name (file, name);
21629 else if (!DOT_SYMBOLS)
21630 assemble_name (file, XSTR (x, 0));
21632 rs6000_output_function_entry (file, XSTR (x, 0));
21636 /* Like 'L', for last word of TImode/PTImode. */
21638 fputs (reg_names[REGNO (x) + 3], file);
21639 else if (MEM_P (x))
21641 machine_mode mode = GET_MODE (x);
21642 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21643 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21644 output_address (mode, plus_constant (Pmode,
21645 XEXP (XEXP (x, 0), 0), 12));
21646 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21647 output_address (mode, plus_constant (Pmode,
21648 XEXP (XEXP (x, 0), 0), 12));
21650 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21651 if (small_data_operand (x, GET_MODE (x)))
21652 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21653 reg_names[SMALL_DATA_REG]);
21657 /* Print AltiVec memory operand. */
21662 gcc_assert (MEM_P (x));
21666 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
21667 && GET_CODE (tmp) == AND
21668 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21669 && INTVAL (XEXP (tmp, 1)) == -16)
21670 tmp = XEXP (tmp, 0);
21671 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21672 && GET_CODE (tmp) == PRE_MODIFY)
21673 tmp = XEXP (tmp, 1);
21675 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21678 if (GET_CODE (tmp) != PLUS
21679 || !REG_P (XEXP (tmp, 0))
21680 || !REG_P (XEXP (tmp, 1)))
21682 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21686 if (REGNO (XEXP (tmp, 0)) == 0)
21687 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21688 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21690 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21691 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21698 fprintf (file, "%s", reg_names[REGNO (x)]);
21699 else if (MEM_P (x))
21701 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21702 know the width from the mode. */
21703 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21704 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21705 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21706 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21707 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21708 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21709 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21710 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21712 output_address (GET_MODE (x), XEXP (x, 0));
21716 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21717 /* This hack along with a corresponding hack in
21718 rs6000_output_addr_const_extra arranges to output addends
21719 where the assembler expects to find them. eg.
21720 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21721 without this hack would be output as "x@toc+4". We
21723 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21725 output_addr_const (file, x);
21730 if (const char *name = get_some_local_dynamic_name ())
21731 assemble_name (file, name);
21733 output_operand_lossage ("'%%&' used without any "
21734 "local dynamic TLS references");
21738 output_operand_lossage ("invalid %%xn code");
21742 /* Print the address of an operand. */
21745 print_operand_address (FILE *file, rtx x)
21748 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21749 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21750 || GET_CODE (x) == LABEL_REF)
21752 output_addr_const (file, x);
21753 if (small_data_operand (x, GET_MODE (x)))
21754 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21755 reg_names[SMALL_DATA_REG]);
21757 gcc_assert (!TARGET_TOC);
21759 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21760 && REG_P (XEXP (x, 1)))
21762 if (REGNO (XEXP (x, 0)) == 0)
21763 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21764 reg_names[ REGNO (XEXP (x, 0)) ]);
21766 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21767 reg_names[ REGNO (XEXP (x, 1)) ]);
21769 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21770 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21771 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21772 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21774 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21775 && CONSTANT_P (XEXP (x, 1)))
21777 fprintf (file, "lo16(");
21778 output_addr_const (file, XEXP (x, 1));
21779 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21783 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21784 && CONSTANT_P (XEXP (x, 1)))
21786 output_addr_const (file, XEXP (x, 1));
21787 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21790 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21792 /* This hack along with a corresponding hack in
21793 rs6000_output_addr_const_extra arranges to output addends
21794 where the assembler expects to find them. eg.
21796 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21797 without this hack would be output as "x@toc+8@l(9)". We
21798 want "x+8@toc@l(9)". */
21799 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21800 if (GET_CODE (x) == LO_SUM)
21801 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21803 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21806 gcc_unreachable ();
21809 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21812 rs6000_output_addr_const_extra (FILE *file, rtx x)
21814 if (GET_CODE (x) == UNSPEC)
21815 switch (XINT (x, 1))
21817 case UNSPEC_TOCREL:
21818 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21819 && REG_P (XVECEXP (x, 0, 1))
21820 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21821 output_addr_const (file, XVECEXP (x, 0, 0));
21822 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21824 if (INTVAL (tocrel_offset_oac) >= 0)
21825 fprintf (file, "+");
21826 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21828 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21831 assemble_name (file, toc_label_name);
21834 else if (TARGET_ELF)
21835 fputs ("@toc", file);
21839 case UNSPEC_MACHOPIC_OFFSET:
21840 output_addr_const (file, XVECEXP (x, 0, 0));
21842 machopic_output_function_base_name (file);
21849 /* Target hook for assembling integer objects. The PowerPC version has
21850 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21851 is defined. It also needs to handle DI-mode objects on 64-bit
21855 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21857 #ifdef RELOCATABLE_NEEDS_FIXUP
21858 /* Special handling for SI values. */
21859 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21861 static int recurse = 0;
21863 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21864 the .fixup section. Since the TOC section is already relocated, we
21865 don't need to mark it here. We used to skip the text section, but it
21866 should never be valid for relocated addresses to be placed in the text
21868 if (DEFAULT_ABI == ABI_V4
21869 && (TARGET_RELOCATABLE || flag_pic > 1)
21870 && in_section != toc_section
21872 && !CONST_SCALAR_INT_P (x)
21878 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21880 ASM_OUTPUT_LABEL (asm_out_file, buf);
21881 fprintf (asm_out_file, "\t.long\t(");
21882 output_addr_const (asm_out_file, x);
21883 fprintf (asm_out_file, ")@fixup\n");
21884 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21885 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21886 fprintf (asm_out_file, "\t.long\t");
21887 assemble_name (asm_out_file, buf);
21888 fprintf (asm_out_file, "\n\t.previous\n");
21892 /* Remove initial .'s to turn a -mcall-aixdesc function
21893 address into the address of the descriptor, not the function
21895 else if (GET_CODE (x) == SYMBOL_REF
21896 && XSTR (x, 0)[0] == '.'
21897 && DEFAULT_ABI == ABI_AIX)
21899 const char *name = XSTR (x, 0);
21900 while (*name == '.')
21903 fprintf (asm_out_file, "\t.long\t%s\n", name);
21907 #endif /* RELOCATABLE_NEEDS_FIXUP */
21908 return default_assemble_integer (x, size, aligned_p);
21911 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21912 /* Emit an assembler directive to set symbol visibility for DECL to
21913 VISIBILITY_TYPE. */
21916 rs6000_assemble_visibility (tree decl, int vis)
21921 /* Functions need to have their entry point symbol visibility set as
21922 well as their descriptor symbol visibility. */
21923 if (DEFAULT_ABI == ABI_AIX
21925 && TREE_CODE (decl) == FUNCTION_DECL)
21927 static const char * const visibility_types[] = {
21928 NULL, "protected", "hidden", "internal"
21931 const char *name, *type;
21933 name = ((* targetm.strip_name_encoding)
21934 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21935 type = visibility_types[vis];
21937 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21938 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21941 default_assemble_visibility (decl, vis);
21946 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21948 /* Reversal of FP compares takes care -- an ordered compare
21949 becomes an unordered compare and vice versa. */
21950 if (mode == CCFPmode
21951 && (!flag_finite_math_only
21952 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21953 || code == UNEQ || code == LTGT))
21954 return reverse_condition_maybe_unordered (code);
21956 return reverse_condition (code);
21959 /* Generate a compare for CODE. Return a brand-new rtx that
21960 represents the result of the compare. */
21963 rs6000_generate_compare (rtx cmp, machine_mode mode)
21965 machine_mode comp_mode;
21966 rtx compare_result;
21967 enum rtx_code code = GET_CODE (cmp);
21968 rtx op0 = XEXP (cmp, 0);
21969 rtx op1 = XEXP (cmp, 1);
21971 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21972 comp_mode = CCmode;
21973 else if (FLOAT_MODE_P (mode))
21974 comp_mode = CCFPmode;
21975 else if (code == GTU || code == LTU
21976 || code == GEU || code == LEU)
21977 comp_mode = CCUNSmode;
21978 else if ((code == EQ || code == NE)
21979 && unsigned_reg_p (op0)
21980 && (unsigned_reg_p (op1)
21981 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21982 /* These are unsigned values, perhaps there will be a later
21983 ordering compare that can be shared with this one. */
21984 comp_mode = CCUNSmode;
21986 comp_mode = CCmode;
21988 /* If we have an unsigned compare, make sure we don't have a signed value as
21990 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
21991 && INTVAL (op1) < 0)
21993 op0 = copy_rtx_if_shared (op0);
21994 op1 = force_reg (GET_MODE (op0), op1);
21995 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21998 /* First, the compare. */
21999 compare_result = gen_reg_rtx (comp_mode);
22001 /* IEEE 128-bit support in VSX registers when we do not have hardware
22003 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22005 rtx libfunc = NULL_RTX;
22006 bool check_nan = false;
22013 libfunc = optab_libfunc (eq_optab, mode);
22018 libfunc = optab_libfunc (ge_optab, mode);
22023 libfunc = optab_libfunc (le_optab, mode);
22028 libfunc = optab_libfunc (unord_optab, mode);
22029 code = (code == UNORDERED) ? NE : EQ;
22035 libfunc = optab_libfunc (ge_optab, mode);
22036 code = (code == UNGE) ? GE : GT;
22042 libfunc = optab_libfunc (le_optab, mode);
22043 code = (code == UNLE) ? LE : LT;
22049 libfunc = optab_libfunc (eq_optab, mode);
22050 code = (code = UNEQ) ? EQ : NE;
22054 gcc_unreachable ();
22057 gcc_assert (libfunc);
22060 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22061 SImode, op0, mode, op1, mode);
22063 /* The library signals an exception for signalling NaNs, so we need to
22064 handle isgreater, etc. by first checking isordered. */
22067 rtx ne_rtx, normal_dest, unord_dest;
22068 rtx unord_func = optab_libfunc (unord_optab, mode);
22069 rtx join_label = gen_label_rtx ();
22070 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
22071 rtx unord_cmp = gen_reg_rtx (comp_mode);
22074 /* Test for either value being a NaN. */
22075 gcc_assert (unord_func);
22076 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
22077 SImode, op0, mode, op1, mode);
22079 /* Set value (0) if either value is a NaN, and jump to the join
22081 dest = gen_reg_rtx (SImode);
22082 emit_move_insn (dest, const1_rtx);
22083 emit_insn (gen_rtx_SET (unord_cmp,
22084 gen_rtx_COMPARE (comp_mode, unord_dest,
22087 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
22088 emit_jump_insn (gen_rtx_SET (pc_rtx,
22089 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
22093 /* Do the normal comparison, knowing that the values are not
22095 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22096 SImode, op0, mode, op1, mode);
22098 emit_insn (gen_cstoresi4 (dest,
22099 gen_rtx_fmt_ee (code, SImode, normal_dest,
22101 normal_dest, const0_rtx));
22103 /* Join NaN and non-Nan paths. Compare dest against 0. */
22104 emit_label (join_label);
22108 emit_insn (gen_rtx_SET (compare_result,
22109 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
22114 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22115 CLOBBERs to match cmptf_internal2 pattern. */
22116 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
22117 && FLOAT128_IBM_P (GET_MODE (op0))
22118 && TARGET_HARD_FLOAT)
22119 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22121 gen_rtx_SET (compare_result,
22122 gen_rtx_COMPARE (comp_mode, op0, op1)),
22123 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22124 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22125 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22126 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22127 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22128 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22129 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22130 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22131 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
22132 else if (GET_CODE (op1) == UNSPEC
22133 && XINT (op1, 1) == UNSPEC_SP_TEST)
22135 rtx op1b = XVECEXP (op1, 0, 0);
22136 comp_mode = CCEQmode;
22137 compare_result = gen_reg_rtx (CCEQmode);
22139 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
22141 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
22144 emit_insn (gen_rtx_SET (compare_result,
22145 gen_rtx_COMPARE (comp_mode, op0, op1)));
22148 /* Some kinds of FP comparisons need an OR operation;
22149 under flag_finite_math_only we don't bother. */
22150 if (FLOAT_MODE_P (mode)
22151 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
22152 && !flag_finite_math_only
22153 && (code == LE || code == GE
22154 || code == UNEQ || code == LTGT
22155 || code == UNGT || code == UNLT))
22157 enum rtx_code or1, or2;
22158 rtx or1_rtx, or2_rtx, compare2_rtx;
22159 rtx or_result = gen_reg_rtx (CCEQmode);
22163 case LE: or1 = LT; or2 = EQ; break;
22164 case GE: or1 = GT; or2 = EQ; break;
22165 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
22166 case LTGT: or1 = LT; or2 = GT; break;
22167 case UNGT: or1 = UNORDERED; or2 = GT; break;
22168 case UNLT: or1 = UNORDERED; or2 = LT; break;
22169 default: gcc_unreachable ();
22171 validate_condition_mode (or1, comp_mode);
22172 validate_condition_mode (or2, comp_mode);
22173 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
22174 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
22175 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
22176 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
22178 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
22180 compare_result = or_result;
22184 validate_condition_mode (code, GET_MODE (compare_result));
22186 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
22190 /* Return the diagnostic message string if the binary operation OP is
22191 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22194 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
22198 machine_mode mode1 = TYPE_MODE (type1);
22199 machine_mode mode2 = TYPE_MODE (type2);
22201 /* For complex modes, use the inner type. */
22202 if (COMPLEX_MODE_P (mode1))
22203 mode1 = GET_MODE_INNER (mode1);
22205 if (COMPLEX_MODE_P (mode2))
22206 mode2 = GET_MODE_INNER (mode2);
22208 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22209 double to intermix unless -mfloat128-convert. */
22210 if (mode1 == mode2)
22213 if (!TARGET_FLOAT128_CVT)
22215 if ((mode1 == KFmode && mode2 == IFmode)
22216 || (mode1 == IFmode && mode2 == KFmode))
22217 return N_("__float128 and __ibm128 cannot be used in the same "
22220 if (TARGET_IEEEQUAD
22221 && ((mode1 == IFmode && mode2 == TFmode)
22222 || (mode1 == TFmode && mode2 == IFmode)))
22223 return N_("__ibm128 and long double cannot be used in the same "
22226 if (!TARGET_IEEEQUAD
22227 && ((mode1 == KFmode && mode2 == TFmode)
22228 || (mode1 == TFmode && mode2 == KFmode)))
22229 return N_("__float128 and long double cannot be used in the same "
22237 /* Expand floating point conversion to/from __float128 and __ibm128. */
22240 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
22242 machine_mode dest_mode = GET_MODE (dest);
22243 machine_mode src_mode = GET_MODE (src);
22244 convert_optab cvt = unknown_optab;
22245 bool do_move = false;
22246 rtx libfunc = NULL_RTX;
22248 typedef rtx (*rtx_2func_t) (rtx, rtx);
22249 rtx_2func_t hw_convert = (rtx_2func_t)0;
22253 rtx_2func_t from_df;
22254 rtx_2func_t from_sf;
22255 rtx_2func_t from_si_sign;
22256 rtx_2func_t from_si_uns;
22257 rtx_2func_t from_di_sign;
22258 rtx_2func_t from_di_uns;
22261 rtx_2func_t to_si_sign;
22262 rtx_2func_t to_si_uns;
22263 rtx_2func_t to_di_sign;
22264 rtx_2func_t to_di_uns;
22265 } hw_conversions[2] = {
22266 /* convertions to/from KFmode */
22268 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
22269 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
22270 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
22271 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
22272 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
22273 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
22274 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
22275 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
22276 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
22277 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
22278 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
22279 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
22282 /* convertions to/from TFmode */
22284 gen_extenddftf2_hw, /* TFmode <- DFmode. */
22285 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22286 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22287 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22288 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22289 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22290 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22291 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22292 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22293 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22294 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22295 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22299 if (dest_mode == src_mode)
22300 gcc_unreachable ();
22302 /* Eliminate memory operations. */
22304 src = force_reg (src_mode, src);
22308 rtx tmp = gen_reg_rtx (dest_mode);
22309 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22310 rs6000_emit_move (dest, tmp, dest_mode);
22314 /* Convert to IEEE 128-bit floating point. */
22315 if (FLOAT128_IEEE_P (dest_mode))
22317 if (dest_mode == KFmode)
22319 else if (dest_mode == TFmode)
22322 gcc_unreachable ();
22328 hw_convert = hw_conversions[kf_or_tf].from_df;
22333 hw_convert = hw_conversions[kf_or_tf].from_sf;
22339 if (FLOAT128_IBM_P (src_mode))
22348 cvt = ufloat_optab;
22349 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22353 cvt = sfloat_optab;
22354 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22361 cvt = ufloat_optab;
22362 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22366 cvt = sfloat_optab;
22367 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22372 gcc_unreachable ();
22376 /* Convert from IEEE 128-bit floating point. */
22377 else if (FLOAT128_IEEE_P (src_mode))
22379 if (src_mode == KFmode)
22381 else if (src_mode == TFmode)
22384 gcc_unreachable ();
22390 hw_convert = hw_conversions[kf_or_tf].to_df;
22395 hw_convert = hw_conversions[kf_or_tf].to_sf;
22401 if (FLOAT128_IBM_P (dest_mode))
22411 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22416 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22424 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22429 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22434 gcc_unreachable ();
22438 /* Both IBM format. */
22439 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22443 gcc_unreachable ();
22445 /* Handle conversion between TFmode/KFmode. */
22447 emit_move_insn (dest, gen_lowpart (dest_mode, src));
22449 /* Handle conversion if we have hardware support. */
22450 else if (TARGET_FLOAT128_HW && hw_convert)
22451 emit_insn ((hw_convert) (dest, src));
22453 /* Call an external function to do the conversion. */
22454 else if (cvt != unknown_optab)
22456 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22457 gcc_assert (libfunc != NULL_RTX);
22459 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22462 gcc_assert (dest2 != NULL_RTX);
22463 if (!rtx_equal_p (dest, dest2))
22464 emit_move_insn (dest, dest2);
22468 gcc_unreachable ();
22474 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22475 can be used as that dest register. Return the dest register. */
22478 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22480 if (op2 == const0_rtx)
22483 if (GET_CODE (scratch) == SCRATCH)
22484 scratch = gen_reg_rtx (mode);
22486 if (logical_operand (op2, mode))
22487 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22489 emit_insn (gen_rtx_SET (scratch,
22490 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22496 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22499 machine_mode op_mode;
22500 enum rtx_code cond_code;
22501 rtx result = operands[0];
22503 condition_rtx = rs6000_generate_compare (operands[1], mode);
22504 cond_code = GET_CODE (condition_rtx);
22506 if (cond_code == NE
22507 || cond_code == GE || cond_code == LE
22508 || cond_code == GEU || cond_code == LEU
22509 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22511 rtx not_result = gen_reg_rtx (CCEQmode);
22512 rtx not_op, rev_cond_rtx;
22513 machine_mode cc_mode;
22515 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22517 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22518 SImode, XEXP (condition_rtx, 0), const0_rtx);
22519 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22520 emit_insn (gen_rtx_SET (not_result, not_op));
22521 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22524 op_mode = GET_MODE (XEXP (operands[1], 0));
22525 if (op_mode == VOIDmode)
22526 op_mode = GET_MODE (XEXP (operands[1], 1));
22528 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22530 PUT_MODE (condition_rtx, DImode);
22531 convert_move (result, condition_rtx, 0);
22535 PUT_MODE (condition_rtx, SImode);
22536 emit_insn (gen_rtx_SET (result, condition_rtx));
22540 /* Emit a branch of kind CODE to location LOC. */
22543 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22545 rtx condition_rtx, loc_ref;
22547 condition_rtx = rs6000_generate_compare (operands[0], mode);
22548 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22549 emit_jump_insn (gen_rtx_SET (pc_rtx,
22550 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22551 loc_ref, pc_rtx)));
22554 /* Return the string to output a conditional branch to LABEL, which is
22555 the operand template of the label, or NULL if the branch is really a
22556 conditional return.
22558 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22559 condition code register and its mode specifies what kind of
22560 comparison we made.
22562 REVERSED is nonzero if we should reverse the sense of the comparison.
22564 INSN is the insn. */
22567 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22569 static char string[64];
22570 enum rtx_code code = GET_CODE (op);
22571 rtx cc_reg = XEXP (op, 0);
22572 machine_mode mode = GET_MODE (cc_reg);
22573 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22574 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22575 int really_reversed = reversed ^ need_longbranch;
22581 validate_condition_mode (code, mode);
22583 /* Work out which way this really branches. We could use
22584 reverse_condition_maybe_unordered here always but this
22585 makes the resulting assembler clearer. */
22586 if (really_reversed)
22588 /* Reversal of FP compares takes care -- an ordered compare
22589 becomes an unordered compare and vice versa. */
22590 if (mode == CCFPmode)
22591 code = reverse_condition_maybe_unordered (code);
22593 code = reverse_condition (code);
22598 /* Not all of these are actually distinct opcodes, but
22599 we distinguish them for clarity of the resulting assembler. */
22600 case NE: case LTGT:
22601 ccode = "ne"; break;
22602 case EQ: case UNEQ:
22603 ccode = "eq"; break;
22605 ccode = "ge"; break;
22606 case GT: case GTU: case UNGT:
22607 ccode = "gt"; break;
22609 ccode = "le"; break;
22610 case LT: case LTU: case UNLT:
22611 ccode = "lt"; break;
22612 case UNORDERED: ccode = "un"; break;
22613 case ORDERED: ccode = "nu"; break;
22614 case UNGE: ccode = "nl"; break;
22615 case UNLE: ccode = "ng"; break;
22617 gcc_unreachable ();
22620 /* Maybe we have a guess as to how likely the branch is. */
22622 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22623 if (note != NULL_RTX)
22625 /* PROB is the difference from 50%. */
22626 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22627 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22629 /* Only hint for highly probable/improbable branches on newer cpus when
22630 we have real profile data, as static prediction overrides processor
22631 dynamic prediction. For older cpus we may as well always hint, but
22632 assume not taken for branches that are very close to 50% as a
22633 mispredicted taken branch is more expensive than a
22634 mispredicted not-taken branch. */
22635 if (rs6000_always_hint
22636 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22637 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22638 && br_prob_note_reliable_p (note)))
22640 if (abs (prob) > REG_BR_PROB_BASE / 20
22641 && ((prob > 0) ^ need_longbranch))
22649 s += sprintf (s, "b%slr%s ", ccode, pred);
22651 s += sprintf (s, "b%s%s ", ccode, pred);
22653 /* We need to escape any '%' characters in the reg_names string.
22654 Assume they'd only be the first character.... */
22655 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22657 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22661 /* If the branch distance was too far, we may have to use an
22662 unconditional branch to go the distance. */
22663 if (need_longbranch)
22664 s += sprintf (s, ",$+8\n\tb %s", label);
22666 s += sprintf (s, ",%s", label);
22672 /* Return insn for VSX or Altivec comparisons. */
22675 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22678 machine_mode mode = GET_MODE (op0);
22686 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22697 mask = gen_reg_rtx (mode);
22698 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22705 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22706 DMODE is expected destination mode. This is a recursive function. */
22709 rs6000_emit_vector_compare (enum rtx_code rcode,
22711 machine_mode dmode)
22714 bool swap_operands = false;
22715 bool try_again = false;
22717 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22718 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22720 /* See if the comparison works as is. */
22721 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22729 swap_operands = true;
22734 swap_operands = true;
22742 /* Invert condition and try again.
22743 e.g., A != B becomes ~(A==B). */
22745 enum rtx_code rev_code;
22746 enum insn_code nor_code;
22749 rev_code = reverse_condition_maybe_unordered (rcode);
22750 if (rev_code == UNKNOWN)
22753 nor_code = optab_handler (one_cmpl_optab, dmode);
22754 if (nor_code == CODE_FOR_nothing)
22757 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22761 mask = gen_reg_rtx (dmode);
22762 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22770 /* Try GT/GTU/LT/LTU OR EQ */
22773 enum insn_code ior_code;
22774 enum rtx_code new_code;
22795 gcc_unreachable ();
22798 ior_code = optab_handler (ior_optab, dmode);
22799 if (ior_code == CODE_FOR_nothing)
22802 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22806 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22810 mask = gen_reg_rtx (dmode);
22811 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22822 std::swap (op0, op1);
22824 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22829 /* You only get two chances. */
22833 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22834 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22835 operands for the relation operation COND. */
22838 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22839 rtx cond, rtx cc_op0, rtx cc_op1)
22841 machine_mode dest_mode = GET_MODE (dest);
22842 machine_mode mask_mode = GET_MODE (cc_op0);
22843 enum rtx_code rcode = GET_CODE (cond);
22844 machine_mode cc_mode = CCmode;
22847 bool invert_move = false;
22849 if (VECTOR_UNIT_NONE_P (dest_mode))
22852 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22853 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22857 /* Swap operands if we can, and fall back to doing the operation as
22858 specified, and doing a NOR to invert the test. */
22864 /* Invert condition and try again.
22865 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22866 invert_move = true;
22867 rcode = reverse_condition_maybe_unordered (rcode);
22868 if (rcode == UNKNOWN)
22874 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22876 /* Invert condition to avoid compound test. */
22877 invert_move = true;
22878 rcode = reverse_condition (rcode);
22886 /* Mark unsigned tests with CCUNSmode. */
22887 cc_mode = CCUNSmode;
22889 /* Invert condition to avoid compound test if necessary. */
22890 if (rcode == GEU || rcode == LEU)
22892 invert_move = true;
22893 rcode = reverse_condition (rcode);
22901 /* Get the vector mask for the given relational operations. */
22902 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22908 std::swap (op_true, op_false);
22910 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22911 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22912 && (GET_CODE (op_true) == CONST_VECTOR
22913 || GET_CODE (op_false) == CONST_VECTOR))
22915 rtx constant_0 = CONST0_RTX (dest_mode);
22916 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22918 if (op_true == constant_m1 && op_false == constant_0)
22920 emit_move_insn (dest, mask);
22924 else if (op_true == constant_0 && op_false == constant_m1)
22926 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22930 /* If we can't use the vector comparison directly, perhaps we can use
22931 the mask for the true or false fields, instead of loading up a
22933 if (op_true == constant_m1)
22936 if (op_false == constant_0)
22940 if (!REG_P (op_true) && !SUBREG_P (op_true))
22941 op_true = force_reg (dest_mode, op_true);
22943 if (!REG_P (op_false) && !SUBREG_P (op_false))
22944 op_false = force_reg (dest_mode, op_false);
22946 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22947 CONST0_RTX (dest_mode));
22948 emit_insn (gen_rtx_SET (dest,
22949 gen_rtx_IF_THEN_ELSE (dest_mode,
22956 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22957 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22958 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22959 hardware has no such operation. */
22962 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22964 enum rtx_code code = GET_CODE (op);
22965 rtx op0 = XEXP (op, 0);
22966 rtx op1 = XEXP (op, 1);
22967 machine_mode compare_mode = GET_MODE (op0);
22968 machine_mode result_mode = GET_MODE (dest);
22969 bool max_p = false;
22971 if (result_mode != compare_mode)
22974 if (code == GE || code == GT)
22976 else if (code == LE || code == LT)
22981 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22984 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22990 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22994 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22995 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22996 operands of the last comparison is nonzero/true, FALSE_COND if it is
22997 zero/false. Return 0 if the hardware has no such operation. */
23000 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23002 enum rtx_code code = GET_CODE (op);
23003 rtx op0 = XEXP (op, 0);
23004 rtx op1 = XEXP (op, 1);
23005 machine_mode result_mode = GET_MODE (dest);
23010 if (!can_create_pseudo_p ())
23023 code = swap_condition (code);
23024 std::swap (op0, op1);
23031 /* Generate: [(parallel [(set (dest)
23032 (if_then_else (op (cmp1) (cmp2))
23035 (clobber (scratch))])]. */
23037 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
23038 cmove_rtx = gen_rtx_SET (dest,
23039 gen_rtx_IF_THEN_ELSE (result_mode,
23044 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
23045 emit_insn (gen_rtx_PARALLEL (VOIDmode,
23046 gen_rtvec (2, cmove_rtx, clobber_rtx)));
23051 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23052 operands of the last comparison is nonzero/true, FALSE_COND if it
23053 is zero/false. Return 0 if the hardware has no such operation. */
23056 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23058 enum rtx_code code = GET_CODE (op);
23059 rtx op0 = XEXP (op, 0);
23060 rtx op1 = XEXP (op, 1);
23061 machine_mode compare_mode = GET_MODE (op0);
23062 machine_mode result_mode = GET_MODE (dest);
23064 bool is_against_zero;
23066 /* These modes should always match. */
23067 if (GET_MODE (op1) != compare_mode
23068 /* In the isel case however, we can use a compare immediate, so
23069 op1 may be a small constant. */
23070 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
23072 if (GET_MODE (true_cond) != result_mode)
23074 if (GET_MODE (false_cond) != result_mode)
23077 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23078 if (TARGET_P9_MINMAX
23079 && (compare_mode == SFmode || compare_mode == DFmode)
23080 && (result_mode == SFmode || result_mode == DFmode))
23082 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
23085 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
23089 /* Don't allow using floating point comparisons for integer results for
23091 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
23094 /* First, work out if the hardware can do this at all, or
23095 if it's too slow.... */
23096 if (!FLOAT_MODE_P (compare_mode))
23099 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
23103 is_against_zero = op1 == CONST0_RTX (compare_mode);
23105 /* A floating-point subtract might overflow, underflow, or produce
23106 an inexact result, thus changing the floating-point flags, so it
23107 can't be generated if we care about that. It's safe if one side
23108 of the construct is zero, since then no subtract will be
23110 if (SCALAR_FLOAT_MODE_P (compare_mode)
23111 && flag_trapping_math && ! is_against_zero)
23114 /* Eliminate half of the comparisons by switching operands, this
23115 makes the remaining code simpler. */
23116 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
23117 || code == LTGT || code == LT || code == UNLE)
23119 code = reverse_condition_maybe_unordered (code);
23121 true_cond = false_cond;
23125 /* UNEQ and LTGT take four instructions for a comparison with zero,
23126 it'll probably be faster to use a branch here too. */
23127 if (code == UNEQ && HONOR_NANS (compare_mode))
23130 /* We're going to try to implement comparisons by performing
23131 a subtract, then comparing against zero. Unfortunately,
23132 Inf - Inf is NaN which is not zero, and so if we don't
23133 know that the operand is finite and the comparison
23134 would treat EQ different to UNORDERED, we can't do it. */
23135 if (HONOR_INFINITIES (compare_mode)
23136 && code != GT && code != UNGE
23137 && (GET_CODE (op1) != CONST_DOUBLE
23138 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
23139 /* Constructs of the form (a OP b ? a : b) are safe. */
23140 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
23141 || (! rtx_equal_p (op0, true_cond)
23142 && ! rtx_equal_p (op1, true_cond))))
23145 /* At this point we know we can use fsel. */
23147 /* Reduce the comparison to a comparison against zero. */
23148 if (! is_against_zero)
23150 temp = gen_reg_rtx (compare_mode);
23151 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
23153 op1 = CONST0_RTX (compare_mode);
23156 /* If we don't care about NaNs we can reduce some of the comparisons
23157 down to faster ones. */
23158 if (! HONOR_NANS (compare_mode))
23164 true_cond = false_cond;
23177 /* Now, reduce everything down to a GE. */
23184 temp = gen_reg_rtx (compare_mode);
23185 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23190 temp = gen_reg_rtx (compare_mode);
23191 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
23196 temp = gen_reg_rtx (compare_mode);
23197 emit_insn (gen_rtx_SET (temp,
23198 gen_rtx_NEG (compare_mode,
23199 gen_rtx_ABS (compare_mode, op0))));
23204 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23205 temp = gen_reg_rtx (result_mode);
23206 emit_insn (gen_rtx_SET (temp,
23207 gen_rtx_IF_THEN_ELSE (result_mode,
23208 gen_rtx_GE (VOIDmode,
23210 true_cond, false_cond)));
23211 false_cond = true_cond;
23214 temp = gen_reg_rtx (compare_mode);
23215 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23220 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23221 temp = gen_reg_rtx (result_mode);
23222 emit_insn (gen_rtx_SET (temp,
23223 gen_rtx_IF_THEN_ELSE (result_mode,
23224 gen_rtx_GE (VOIDmode,
23226 true_cond, false_cond)));
23227 true_cond = false_cond;
23230 temp = gen_reg_rtx (compare_mode);
23231 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23236 gcc_unreachable ();
23239 emit_insn (gen_rtx_SET (dest,
23240 gen_rtx_IF_THEN_ELSE (result_mode,
23241 gen_rtx_GE (VOIDmode,
23243 true_cond, false_cond)));
23247 /* Same as above, but for ints (isel). */
23250 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23252 rtx condition_rtx, cr;
23253 machine_mode mode = GET_MODE (dest);
23254 enum rtx_code cond_code;
23255 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
23258 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
23261 /* We still have to do the compare, because isel doesn't do a
23262 compare, it just looks at the CRx bits set by a previous compare
23264 condition_rtx = rs6000_generate_compare (op, mode);
23265 cond_code = GET_CODE (condition_rtx);
23266 cr = XEXP (condition_rtx, 0);
23267 signedp = GET_MODE (cr) == CCmode;
23269 isel_func = (mode == SImode
23270 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
23271 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
23275 case LT: case GT: case LTU: case GTU: case EQ:
23276 /* isel handles these directly. */
23280 /* We need to swap the sense of the comparison. */
23282 std::swap (false_cond, true_cond);
23283 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23288 false_cond = force_reg (mode, false_cond);
23289 if (true_cond != const0_rtx)
23290 true_cond = force_reg (mode, true_cond);
23292 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23298 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23300 machine_mode mode = GET_MODE (op0);
23304 /* VSX/altivec have direct min/max insns. */
23305 if ((code == SMAX || code == SMIN)
23306 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23307 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23309 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23313 if (code == SMAX || code == SMIN)
23318 if (code == SMAX || code == UMAX)
23319 target = emit_conditional_move (dest, c, op0, op1, mode,
23320 op0, op1, mode, 0);
23322 target = emit_conditional_move (dest, c, op0, op1, mode,
23323 op1, op0, mode, 0);
23324 gcc_assert (target);
23325 if (target != dest)
23326 emit_move_insn (dest, target);
23329 /* Split a signbit operation on 64-bit machines with direct move. Also allow
23330 for the value to come from memory or if it is already loaded into a GPR. */
23333 rs6000_split_signbit (rtx dest, rtx src)
23335 machine_mode d_mode = GET_MODE (dest);
23336 machine_mode s_mode = GET_MODE (src);
23337 rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
23338 rtx shift_reg = dest_di;
23340 gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
23344 rtx mem = (WORDS_BIG_ENDIAN
23345 ? adjust_address (src, DImode, 0)
23346 : adjust_address (src, DImode, 8));
23347 emit_insn (gen_rtx_SET (dest_di, mem));
23352 unsigned int r = reg_or_subregno (src);
23354 if (INT_REGNO_P (r))
23355 shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
23359 /* Generate the special mfvsrd instruction to get it in a GPR. */
23360 gcc_assert (VSX_REGNO_P (r));
23361 if (s_mode == KFmode)
23362 emit_insn (gen_signbitkf2_dm2 (dest_di, src));
23364 emit_insn (gen_signbittf2_dm2 (dest_di, src));
23368 emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
23372 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23373 COND is true. Mark the jump as unlikely to be taken. */
23376 emit_unlikely_jump (rtx cond, rtx label)
23378 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23379 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23380 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23383 /* A subroutine of the atomic operation splitters. Emit a load-locked
23384 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23385 the zero_extend operation. */
23388 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23390 rtx (*fn) (rtx, rtx) = NULL;
23395 fn = gen_load_lockedqi;
23398 fn = gen_load_lockedhi;
23401 if (GET_MODE (mem) == QImode)
23402 fn = gen_load_lockedqi_si;
23403 else if (GET_MODE (mem) == HImode)
23404 fn = gen_load_lockedhi_si;
23406 fn = gen_load_lockedsi;
23409 fn = gen_load_lockeddi;
23412 fn = gen_load_lockedti;
23415 gcc_unreachable ();
23417 emit_insn (fn (reg, mem));
23420 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23421 instruction in MODE. */
23424 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23426 rtx (*fn) (rtx, rtx, rtx) = NULL;
23431 fn = gen_store_conditionalqi;
23434 fn = gen_store_conditionalhi;
23437 fn = gen_store_conditionalsi;
23440 fn = gen_store_conditionaldi;
23443 fn = gen_store_conditionalti;
23446 gcc_unreachable ();
23449 /* Emit sync before stwcx. to address PPC405 Erratum. */
23450 if (PPC405_ERRATUM77)
23451 emit_insn (gen_hwsync ());
23453 emit_insn (fn (res, mem, val));
23456 /* Expand barriers before and after a load_locked/store_cond sequence. */
23459 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23461 rtx addr = XEXP (mem, 0);
23463 if (!legitimate_indirect_address_p (addr, reload_completed)
23464 && !legitimate_indexed_address_p (addr, reload_completed))
23466 addr = force_reg (Pmode, addr);
23467 mem = replace_equiv_address_nv (mem, addr);
23472 case MEMMODEL_RELAXED:
23473 case MEMMODEL_CONSUME:
23474 case MEMMODEL_ACQUIRE:
23476 case MEMMODEL_RELEASE:
23477 case MEMMODEL_ACQ_REL:
23478 emit_insn (gen_lwsync ());
23480 case MEMMODEL_SEQ_CST:
23481 emit_insn (gen_hwsync ());
23484 gcc_unreachable ();
23490 rs6000_post_atomic_barrier (enum memmodel model)
23494 case MEMMODEL_RELAXED:
23495 case MEMMODEL_CONSUME:
23496 case MEMMODEL_RELEASE:
23498 case MEMMODEL_ACQUIRE:
23499 case MEMMODEL_ACQ_REL:
23500 case MEMMODEL_SEQ_CST:
23501 emit_insn (gen_isync ());
23504 gcc_unreachable ();
23508 /* A subroutine of the various atomic expanders. For sub-word operations,
23509 we must adjust things to operate on SImode. Given the original MEM,
23510 return a new aligned memory. Also build and return the quantities by
23511 which to shift and mask. */
23514 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23516 rtx addr, align, shift, mask, mem;
23517 HOST_WIDE_INT shift_mask;
23518 machine_mode mode = GET_MODE (orig_mem);
23520 /* For smaller modes, we have to implement this via SImode. */
23521 shift_mask = (mode == QImode ? 0x18 : 0x10);
23523 addr = XEXP (orig_mem, 0);
23524 addr = force_reg (GET_MODE (addr), addr);
23526 /* Aligned memory containing subword. Generate a new memory. We
23527 do not want any of the existing MEM_ATTR data, as we're now
23528 accessing memory outside the original object. */
23529 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23530 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23531 mem = gen_rtx_MEM (SImode, align);
23532 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23533 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23534 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23536 /* Shift amount for subword relative to aligned word. */
23537 shift = gen_reg_rtx (SImode);
23538 addr = gen_lowpart (SImode, addr);
23539 rtx tmp = gen_reg_rtx (SImode);
23540 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23541 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23542 if (BYTES_BIG_ENDIAN)
23543 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23544 shift, 1, OPTAB_LIB_WIDEN);
23547 /* Mask for insertion. */
23548 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23549 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23555 /* A subroutine of the various atomic expanders. For sub-word operands,
23556 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23559 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23563 x = gen_reg_rtx (SImode);
23564 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23565 gen_rtx_NOT (SImode, mask),
23568 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23573 /* A subroutine of the various atomic expanders. For sub-word operands,
23574 extract WIDE to NARROW via SHIFT. */
23577 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23579 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23580 wide, 1, OPTAB_LIB_WIDEN);
23581 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23584 /* Expand an atomic compare and swap operation. */
23587 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23589 rtx boolval, retval, mem, oldval, newval, cond;
23590 rtx label1, label2, x, mask, shift;
23591 machine_mode mode, orig_mode;
23592 enum memmodel mod_s, mod_f;
23595 boolval = operands[0];
23596 retval = operands[1];
23598 oldval = operands[3];
23599 newval = operands[4];
23600 is_weak = (INTVAL (operands[5]) != 0);
23601 mod_s = memmodel_base (INTVAL (operands[6]));
23602 mod_f = memmodel_base (INTVAL (operands[7]));
23603 orig_mode = mode = GET_MODE (mem);
23605 mask = shift = NULL_RTX;
23606 if (mode == QImode || mode == HImode)
23608 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23609 lwarx and shift/mask operations. With power8, we need to do the
23610 comparison in SImode, but the store is still done in QI/HImode. */
23611 oldval = convert_modes (SImode, mode, oldval, 1);
23613 if (!TARGET_SYNC_HI_QI)
23615 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23617 /* Shift and mask OLDVAL into position with the word. */
23618 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23619 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23621 /* Shift and mask NEWVAL into position within the word. */
23622 newval = convert_modes (SImode, mode, newval, 1);
23623 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23624 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23627 /* Prepare to adjust the return value. */
23628 retval = gen_reg_rtx (SImode);
23631 else if (reg_overlap_mentioned_p (retval, oldval))
23632 oldval = copy_to_reg (oldval);
23634 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23635 oldval = copy_to_mode_reg (mode, oldval);
23637 if (reg_overlap_mentioned_p (retval, newval))
23638 newval = copy_to_reg (newval);
23640 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23645 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23646 emit_label (XEXP (label1, 0));
23648 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23650 emit_load_locked (mode, retval, mem);
23654 x = expand_simple_binop (SImode, AND, retval, mask,
23655 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23657 cond = gen_reg_rtx (CCmode);
23658 /* If we have TImode, synthesize a comparison. */
23659 if (mode != TImode)
23660 x = gen_rtx_COMPARE (CCmode, x, oldval);
23663 rtx xor1_result = gen_reg_rtx (DImode);
23664 rtx xor2_result = gen_reg_rtx (DImode);
23665 rtx or_result = gen_reg_rtx (DImode);
23666 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23667 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23668 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23669 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23671 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23672 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23673 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23674 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23677 emit_insn (gen_rtx_SET (cond, x));
23679 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23680 emit_unlikely_jump (x, label2);
23684 x = rs6000_mask_atomic_subword (retval, newval, mask);
23686 emit_store_conditional (orig_mode, cond, mem, x);
23690 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23691 emit_unlikely_jump (x, label1);
23694 if (!is_mm_relaxed (mod_f))
23695 emit_label (XEXP (label2, 0));
23697 rs6000_post_atomic_barrier (mod_s);
23699 if (is_mm_relaxed (mod_f))
23700 emit_label (XEXP (label2, 0));
23703 rs6000_finish_atomic_subword (operands[1], retval, shift);
23704 else if (mode != GET_MODE (operands[1]))
23705 convert_move (operands[1], retval, 1);
23707 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23708 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23709 emit_insn (gen_rtx_SET (boolval, x));
23712 /* Expand an atomic exchange operation. */
23715 rs6000_expand_atomic_exchange (rtx operands[])
23717 rtx retval, mem, val, cond;
23719 enum memmodel model;
23720 rtx label, x, mask, shift;
23722 retval = operands[0];
23725 model = memmodel_base (INTVAL (operands[3]));
23726 mode = GET_MODE (mem);
23728 mask = shift = NULL_RTX;
23729 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23731 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23733 /* Shift and mask VAL into position with the word. */
23734 val = convert_modes (SImode, mode, val, 1);
23735 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23736 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23738 /* Prepare to adjust the return value. */
23739 retval = gen_reg_rtx (SImode);
23743 mem = rs6000_pre_atomic_barrier (mem, model);
23745 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23746 emit_label (XEXP (label, 0));
23748 emit_load_locked (mode, retval, mem);
23752 x = rs6000_mask_atomic_subword (retval, val, mask);
23754 cond = gen_reg_rtx (CCmode);
23755 emit_store_conditional (mode, cond, mem, x);
23757 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23758 emit_unlikely_jump (x, label);
23760 rs6000_post_atomic_barrier (model);
23763 rs6000_finish_atomic_subword (operands[0], retval, shift);
23766 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23767 to perform. MEM is the memory on which to operate. VAL is the second
23768 operand of the binary operator. BEFORE and AFTER are optional locations to
23769 return the value of MEM either before of after the operation. MODEL_RTX
23770 is a CONST_INT containing the memory model to use. */
23773 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23774 rtx orig_before, rtx orig_after, rtx model_rtx)
23776 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23777 machine_mode mode = GET_MODE (mem);
23778 machine_mode store_mode = mode;
23779 rtx label, x, cond, mask, shift;
23780 rtx before = orig_before, after = orig_after;
23782 mask = shift = NULL_RTX;
23783 /* On power8, we want to use SImode for the operation. On previous systems,
23784 use the operation in a subword and shift/mask to get the proper byte or
23786 if (mode == QImode || mode == HImode)
23788 if (TARGET_SYNC_HI_QI)
23790 val = convert_modes (SImode, mode, val, 1);
23792 /* Prepare to adjust the return value. */
23793 before = gen_reg_rtx (SImode);
23795 after = gen_reg_rtx (SImode);
23800 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23802 /* Shift and mask VAL into position with the word. */
23803 val = convert_modes (SImode, mode, val, 1);
23804 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23805 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23811 /* We've already zero-extended VAL. That is sufficient to
23812 make certain that it does not affect other bits. */
23817 /* If we make certain that all of the other bits in VAL are
23818 set, that will be sufficient to not affect other bits. */
23819 x = gen_rtx_NOT (SImode, mask);
23820 x = gen_rtx_IOR (SImode, x, val);
23821 emit_insn (gen_rtx_SET (val, x));
23828 /* These will all affect bits outside the field and need
23829 adjustment via MASK within the loop. */
23833 gcc_unreachable ();
23836 /* Prepare to adjust the return value. */
23837 before = gen_reg_rtx (SImode);
23839 after = gen_reg_rtx (SImode);
23840 store_mode = mode = SImode;
23844 mem = rs6000_pre_atomic_barrier (mem, model);
23846 label = gen_label_rtx ();
23847 emit_label (label);
23848 label = gen_rtx_LABEL_REF (VOIDmode, label);
23850 if (before == NULL_RTX)
23851 before = gen_reg_rtx (mode);
23853 emit_load_locked (mode, before, mem);
23857 x = expand_simple_binop (mode, AND, before, val,
23858 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23859 after = expand_simple_unop (mode, NOT, x, after, 1);
23863 after = expand_simple_binop (mode, code, before, val,
23864 after, 1, OPTAB_LIB_WIDEN);
23870 x = expand_simple_binop (SImode, AND, after, mask,
23871 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23872 x = rs6000_mask_atomic_subword (before, x, mask);
23874 else if (store_mode != mode)
23875 x = convert_modes (store_mode, mode, x, 1);
23877 cond = gen_reg_rtx (CCmode);
23878 emit_store_conditional (store_mode, cond, mem, x);
23880 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23881 emit_unlikely_jump (x, label);
23883 rs6000_post_atomic_barrier (model);
23887 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23888 then do the calcuations in a SImode register. */
23890 rs6000_finish_atomic_subword (orig_before, before, shift);
23892 rs6000_finish_atomic_subword (orig_after, after, shift);
23894 else if (store_mode != mode)
23896 /* QImode/HImode on machines with lbarx/lharx where we do the native
23897 operation and then do the calcuations in a SImode register. */
23899 convert_move (orig_before, before, 1);
23901 convert_move (orig_after, after, 1);
23903 else if (orig_after && after != orig_after)
23904 emit_move_insn (orig_after, after);
23907 /* Emit instructions to move SRC to DST. Called by splitters for
23908 multi-register moves. It will emit at most one instruction for
23909 each register that is accessed; that is, it won't emit li/lis pairs
23910 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23914 rs6000_split_multireg_move (rtx dst, rtx src)
23916 /* The register number of the first register being moved. */
23918 /* The mode that is to be moved. */
23920 /* The mode that the move is being done in, and its size. */
23921 machine_mode reg_mode;
23923 /* The number of registers that will be moved. */
23926 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23927 mode = GET_MODE (dst);
23928 nregs = hard_regno_nregs (reg, mode);
23929 if (FP_REGNO_P (reg))
23930 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23931 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
23932 else if (ALTIVEC_REGNO_P (reg))
23933 reg_mode = V16QImode;
23935 reg_mode = word_mode;
23936 reg_mode_size = GET_MODE_SIZE (reg_mode);
23938 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23940 /* TDmode residing in FP registers is special, since the ISA requires that
23941 the lower-numbered word of a register pair is always the most significant
23942 word, even in little-endian mode. This does not match the usual subreg
23943 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23944 the appropriate constituent registers "by hand" in little-endian mode.
23946 Note we do not need to check for destructive overlap here since TDmode
23947 can only reside in even/odd register pairs. */
23948 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23953 for (i = 0; i < nregs; i++)
23955 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23956 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23958 p_src = simplify_gen_subreg (reg_mode, src, mode,
23959 i * reg_mode_size);
23961 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23962 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23964 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23965 i * reg_mode_size);
23967 emit_insn (gen_rtx_SET (p_dst, p_src));
23973 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23975 /* Move register range backwards, if we might have destructive
23978 for (i = nregs - 1; i >= 0; i--)
23979 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23980 i * reg_mode_size),
23981 simplify_gen_subreg (reg_mode, src, mode,
23982 i * reg_mode_size)));
23988 bool used_update = false;
23989 rtx restore_basereg = NULL_RTX;
23991 if (MEM_P (src) && INT_REGNO_P (reg))
23995 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23996 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23999 breg = XEXP (XEXP (src, 0), 0);
24000 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
24001 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
24002 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
24003 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24004 src = replace_equiv_address (src, breg);
24006 else if (! rs6000_offsettable_memref_p (src, reg_mode))
24008 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
24010 rtx basereg = XEXP (XEXP (src, 0), 0);
24013 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
24014 emit_insn (gen_rtx_SET (ndst,
24015 gen_rtx_MEM (reg_mode,
24017 used_update = true;
24020 emit_insn (gen_rtx_SET (basereg,
24021 XEXP (XEXP (src, 0), 1)));
24022 src = replace_equiv_address (src, basereg);
24026 rtx basereg = gen_rtx_REG (Pmode, reg);
24027 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
24028 src = replace_equiv_address (src, basereg);
24032 breg = XEXP (src, 0);
24033 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
24034 breg = XEXP (breg, 0);
24036 /* If the base register we are using to address memory is
24037 also a destination reg, then change that register last. */
24039 && REGNO (breg) >= REGNO (dst)
24040 && REGNO (breg) < REGNO (dst) + nregs)
24041 j = REGNO (breg) - REGNO (dst);
24043 else if (MEM_P (dst) && INT_REGNO_P (reg))
24047 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
24048 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
24051 breg = XEXP (XEXP (dst, 0), 0);
24052 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
24053 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
24054 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
24056 /* We have to update the breg before doing the store.
24057 Use store with update, if available. */
24061 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24062 emit_insn (TARGET_32BIT
24063 ? (TARGET_POWERPC64
24064 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
24065 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
24066 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
24067 used_update = true;
24070 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24071 dst = replace_equiv_address (dst, breg);
24073 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
24074 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
24076 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
24078 rtx basereg = XEXP (XEXP (dst, 0), 0);
24081 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24082 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
24085 used_update = true;
24088 emit_insn (gen_rtx_SET (basereg,
24089 XEXP (XEXP (dst, 0), 1)));
24090 dst = replace_equiv_address (dst, basereg);
24094 rtx basereg = XEXP (XEXP (dst, 0), 0);
24095 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
24096 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
24098 && REG_P (offsetreg)
24099 && REGNO (basereg) != REGNO (offsetreg));
24100 if (REGNO (basereg) == 0)
24102 rtx tmp = offsetreg;
24103 offsetreg = basereg;
24106 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
24107 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
24108 dst = replace_equiv_address (dst, basereg);
24111 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
24112 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
24115 for (i = 0; i < nregs; i++)
24117 /* Calculate index to next subword. */
24122 /* If compiler already emitted move of first word by
24123 store with update, no need to do anything. */
24124 if (j == 0 && used_update)
24127 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24128 j * reg_mode_size),
24129 simplify_gen_subreg (reg_mode, src, mode,
24130 j * reg_mode_size)));
24132 if (restore_basereg != NULL_RTX)
24133 emit_insn (restore_basereg);
24138 /* This page contains routines that are used to determine what the
24139 function prologue and epilogue code will do and write them out. */
24141 /* Determine whether the REG is really used. */
24144 save_reg_p (int reg)
24146 /* We need to mark the PIC offset register live for the same conditions
24147 as it is set up, or otherwise it won't be saved before we clobber it. */
24149 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
24151 /* When calling eh_return, we must return true for all the cases
24152 where conditional_register_usage marks the PIC offset reg
24154 if (TARGET_TOC && TARGET_MINIMAL_TOC
24155 && (crtl->calls_eh_return
24156 || df_regs_ever_live_p (reg)
24157 || !constant_pool_empty_p ()))
24160 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
24165 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
24168 /* Return the first fixed-point register that is required to be
24169 saved. 32 if none. */
24172 first_reg_to_save (void)
24176 /* Find lowest numbered live register. */
24177 for (first_reg = 13; first_reg <= 31; first_reg++)
24178 if (save_reg_p (first_reg))
24183 && crtl->uses_pic_offset_table
24184 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
24185 return RS6000_PIC_OFFSET_TABLE_REGNUM;
24191 /* Similar, for FP regs. */
24194 first_fp_reg_to_save (void)
24198 /* Find lowest numbered live register. */
24199 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
24200 if (save_reg_p (first_reg))
24206 /* Similar, for AltiVec regs. */
24209 first_altivec_reg_to_save (void)
24213 /* Stack frame remains as is unless we are in AltiVec ABI. */
24214 if (! TARGET_ALTIVEC_ABI)
24215 return LAST_ALTIVEC_REGNO + 1;
24217 /* On Darwin, the unwind routines are compiled without
24218 TARGET_ALTIVEC, and use save_world to save/restore the
24219 altivec registers when necessary. */
24220 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24221 && ! TARGET_ALTIVEC)
24222 return FIRST_ALTIVEC_REGNO + 20;
24224 /* Find lowest numbered live register. */
24225 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
24226 if (save_reg_p (i))
24232 /* Return a 32-bit mask of the AltiVec registers we need to set in
24233 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24234 the 32-bit word is 0. */
24236 static unsigned int
24237 compute_vrsave_mask (void)
24239 unsigned int i, mask = 0;
24241 /* On Darwin, the unwind routines are compiled without
24242 TARGET_ALTIVEC, and use save_world to save/restore the
24243 call-saved altivec registers when necessary. */
24244 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24245 && ! TARGET_ALTIVEC)
24248 /* First, find out if we use _any_ altivec registers. */
24249 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
24250 if (df_regs_ever_live_p (i))
24251 mask |= ALTIVEC_REG_BIT (i);
24256 /* Next, remove the argument registers from the set. These must
24257 be in the VRSAVE mask set by the caller, so we don't need to add
24258 them in again. More importantly, the mask we compute here is
24259 used to generate CLOBBERs in the set_vrsave insn, and we do not
24260 wish the argument registers to die. */
24261 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
24262 mask &= ~ALTIVEC_REG_BIT (i);
24264 /* Similarly, remove the return value from the set. */
24267 diddle_return_value (is_altivec_return_reg, &yes);
24269 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
24275 /* For a very restricted set of circumstances, we can cut down the
24276 size of prologues/epilogues by calling our own save/restore-the-world
24280 compute_save_world_info (rs6000_stack_t *info)
24282 info->world_save_p = 1;
24284 = (WORLD_SAVE_P (info)
24285 && DEFAULT_ABI == ABI_DARWIN
24286 && !cfun->has_nonlocal_label
24287 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
24288 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
24289 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
24290 && info->cr_save_p);
24292 /* This will not work in conjunction with sibcalls. Make sure there
24293 are none. (This check is expensive, but seldom executed.) */
24294 if (WORLD_SAVE_P (info))
24297 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
24298 if (CALL_P (insn) && SIBLING_CALL_P (insn))
24300 info->world_save_p = 0;
24305 if (WORLD_SAVE_P (info))
24307 /* Even if we're not touching VRsave, make sure there's room on the
24308 stack for it, if it looks like we're calling SAVE_WORLD, which
24309 will attempt to save it. */
24310 info->vrsave_size = 4;
24312 /* If we are going to save the world, we need to save the link register too. */
24313 info->lr_save_p = 1;
24315 /* "Save" the VRsave register too if we're saving the world. */
24316 if (info->vrsave_mask == 0)
24317 info->vrsave_mask = compute_vrsave_mask ();
24319 /* Because the Darwin register save/restore routines only handle
24320 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24322 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
24323 && (info->first_altivec_reg_save
24324 >= FIRST_SAVED_ALTIVEC_REGNO));
24332 is_altivec_return_reg (rtx reg, void *xyes)
24334 bool *yes = (bool *) xyes;
24335 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24340 /* Return whether REG is a global user reg or has been specifed by
24341 -ffixed-REG. We should not restore these, and so cannot use
24342 lmw or out-of-line restore functions if there are any. We also
24343 can't save them (well, emit frame notes for them), because frame
24344 unwinding during exception handling will restore saved registers. */
24347 fixed_reg_p (int reg)
24349 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24350 backend sets it, overriding anything the user might have given. */
24351 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24352 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24353 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24354 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24357 return fixed_regs[reg];
24360 /* Determine the strategy for savings/restoring registers. */
24363 SAVE_MULTIPLE = 0x1,
24364 SAVE_INLINE_GPRS = 0x2,
24365 SAVE_INLINE_FPRS = 0x4,
24366 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24367 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24368 SAVE_INLINE_VRS = 0x20,
24369 REST_MULTIPLE = 0x100,
24370 REST_INLINE_GPRS = 0x200,
24371 REST_INLINE_FPRS = 0x400,
24372 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24373 REST_INLINE_VRS = 0x1000
24377 rs6000_savres_strategy (rs6000_stack_t *info,
24378 bool using_static_chain_p)
24382 /* Select between in-line and out-of-line save and restore of regs.
24383 First, all the obvious cases where we don't use out-of-line. */
24384 if (crtl->calls_eh_return
24385 || cfun->machine->ra_need_lr)
24386 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24387 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24388 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24390 if (info->first_gp_reg_save == 32)
24391 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24393 if (info->first_fp_reg_save == 64
24394 /* The out-of-line FP routines use double-precision stores;
24395 we can't use those routines if we don't have such stores. */
24396 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
24397 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24399 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24400 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24402 /* Define cutoff for using out-of-line functions to save registers. */
24403 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24405 if (!optimize_size)
24407 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24408 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24409 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24413 /* Prefer out-of-line restore if it will exit. */
24414 if (info->first_fp_reg_save > 61)
24415 strategy |= SAVE_INLINE_FPRS;
24416 if (info->first_gp_reg_save > 29)
24418 if (info->first_fp_reg_save == 64)
24419 strategy |= SAVE_INLINE_GPRS;
24421 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24423 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24424 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24427 else if (DEFAULT_ABI == ABI_DARWIN)
24429 if (info->first_fp_reg_save > 60)
24430 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24431 if (info->first_gp_reg_save > 29)
24432 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24433 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24437 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24438 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24439 || info->first_fp_reg_save > 61)
24440 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24441 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24442 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24445 /* Don't bother to try to save things out-of-line if r11 is occupied
24446 by the static chain. It would require too much fiddling and the
24447 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24448 pointer on Darwin, and AIX uses r1 or r12. */
24449 if (using_static_chain_p
24450 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24451 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24453 | SAVE_INLINE_VRS);
24455 /* Don't ever restore fixed regs. That means we can't use the
24456 out-of-line register restore functions if a fixed reg is in the
24457 range of regs restored. */
24458 if (!(strategy & REST_INLINE_FPRS))
24459 for (int i = info->first_fp_reg_save; i < 64; i++)
24462 strategy |= REST_INLINE_FPRS;
24466 /* We can only use the out-of-line routines to restore fprs if we've
24467 saved all the registers from first_fp_reg_save in the prologue.
24468 Otherwise, we risk loading garbage. Of course, if we have saved
24469 out-of-line then we know we haven't skipped any fprs. */
24470 if ((strategy & SAVE_INLINE_FPRS)
24471 && !(strategy & REST_INLINE_FPRS))
24472 for (int i = info->first_fp_reg_save; i < 64; i++)
24473 if (!save_reg_p (i))
24475 strategy |= REST_INLINE_FPRS;
24479 /* Similarly, for altivec regs. */
24480 if (!(strategy & REST_INLINE_VRS))
24481 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24484 strategy |= REST_INLINE_VRS;
24488 if ((strategy & SAVE_INLINE_VRS)
24489 && !(strategy & REST_INLINE_VRS))
24490 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24491 if (!save_reg_p (i))
24493 strategy |= REST_INLINE_VRS;
24497 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24498 saved is an out-of-line save or restore. Set up the value for
24499 the next test (excluding out-of-line gprs). */
24500 bool lr_save_p = (info->lr_save_p
24501 || !(strategy & SAVE_INLINE_FPRS)
24502 || !(strategy & SAVE_INLINE_VRS)
24503 || !(strategy & REST_INLINE_FPRS)
24504 || !(strategy & REST_INLINE_VRS));
24506 if (TARGET_MULTIPLE
24507 && !TARGET_POWERPC64
24508 && info->first_gp_reg_save < 31
24509 && !(flag_shrink_wrap
24510 && flag_shrink_wrap_separate
24511 && optimize_function_for_speed_p (cfun)))
24514 for (int i = info->first_gp_reg_save; i < 32; i++)
24515 if (save_reg_p (i))
24519 /* Don't use store multiple if only one reg needs to be
24520 saved. This can occur for example when the ABI_V4 pic reg
24521 (r30) needs to be saved to make calls, but r31 is not
24523 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24526 /* Prefer store multiple for saves over out-of-line
24527 routines, since the store-multiple instruction will
24528 always be smaller. */
24529 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24531 /* The situation is more complicated with load multiple.
24532 We'd prefer to use the out-of-line routines for restores,
24533 since the "exit" out-of-line routines can handle the
24534 restore of LR and the frame teardown. However if doesn't
24535 make sense to use the out-of-line routine if that is the
24536 only reason we'd need to save LR, and we can't use the
24537 "exit" out-of-line gpr restore if we have saved some
24538 fprs; In those cases it is advantageous to use load
24539 multiple when available. */
24540 if (info->first_fp_reg_save != 64 || !lr_save_p)
24541 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24545 /* Using the "exit" out-of-line routine does not improve code size
24546 if using it would require lr to be saved and if only saving one
24548 else if (!lr_save_p && info->first_gp_reg_save > 29)
24549 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24551 /* Don't ever restore fixed regs. */
24552 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24553 for (int i = info->first_gp_reg_save; i < 32; i++)
24554 if (fixed_reg_p (i))
24556 strategy |= REST_INLINE_GPRS;
24557 strategy &= ~REST_MULTIPLE;
24561 /* We can only use load multiple or the out-of-line routines to
24562 restore gprs if we've saved all the registers from
24563 first_gp_reg_save. Otherwise, we risk loading garbage.
24564 Of course, if we have saved out-of-line or used stmw then we know
24565 we haven't skipped any gprs. */
24566 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24567 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24568 for (int i = info->first_gp_reg_save; i < 32; i++)
24569 if (!save_reg_p (i))
24571 strategy |= REST_INLINE_GPRS;
24572 strategy &= ~REST_MULTIPLE;
24576 if (TARGET_ELF && TARGET_64BIT)
24578 if (!(strategy & SAVE_INLINE_FPRS))
24579 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24580 else if (!(strategy & SAVE_INLINE_GPRS)
24581 && info->first_fp_reg_save == 64)
24582 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24584 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24585 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24587 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24588 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24593 /* Calculate the stack information for the current function. This is
24594 complicated by having two separate calling sequences, the AIX calling
24595 sequence and the V.4 calling sequence.
24597 AIX (and Darwin/Mac OS X) stack frames look like:
24599 SP----> +---------------------------------------+
24600 | back chain to caller | 0 0
24601 +---------------------------------------+
24602 | saved CR | 4 8 (8-11)
24603 +---------------------------------------+
24605 +---------------------------------------+
24606 | reserved for compilers | 12 24
24607 +---------------------------------------+
24608 | reserved for binders | 16 32
24609 +---------------------------------------+
24610 | saved TOC pointer | 20 40
24611 +---------------------------------------+
24612 | Parameter save area (+padding*) (P) | 24 48
24613 +---------------------------------------+
24614 | Alloca space (A) | 24+P etc.
24615 +---------------------------------------+
24616 | Local variable space (L) | 24+P+A
24617 +---------------------------------------+
24618 | Float/int conversion temporary (X) | 24+P+A+L
24619 +---------------------------------------+
24620 | Save area for AltiVec registers (W) | 24+P+A+L+X
24621 +---------------------------------------+
24622 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24623 +---------------------------------------+
24624 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24625 +---------------------------------------+
24626 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24627 +---------------------------------------+
24628 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24629 +---------------------------------------+
24630 old SP->| back chain to caller's caller |
24631 +---------------------------------------+
24633 * If the alloca area is present, the parameter save area is
24634 padded so that the former starts 16-byte aligned.
24636 The required alignment for AIX configurations is two words (i.e., 8
24639 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24641 SP----> +---------------------------------------+
24642 | Back chain to caller | 0
24643 +---------------------------------------+
24644 | Save area for CR | 8
24645 +---------------------------------------+
24647 +---------------------------------------+
24648 | Saved TOC pointer | 24
24649 +---------------------------------------+
24650 | Parameter save area (+padding*) (P) | 32
24651 +---------------------------------------+
24652 | Alloca space (A) | 32+P
24653 +---------------------------------------+
24654 | Local variable space (L) | 32+P+A
24655 +---------------------------------------+
24656 | Save area for AltiVec registers (W) | 32+P+A+L
24657 +---------------------------------------+
24658 | AltiVec alignment padding (Y) | 32+P+A+L+W
24659 +---------------------------------------+
24660 | Save area for GP registers (G) | 32+P+A+L+W+Y
24661 +---------------------------------------+
24662 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24663 +---------------------------------------+
24664 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24665 +---------------------------------------+
24667 * If the alloca area is present, the parameter save area is
24668 padded so that the former starts 16-byte aligned.
24670 V.4 stack frames look like:
24672 SP----> +---------------------------------------+
24673 | back chain to caller | 0
24674 +---------------------------------------+
24675 | caller's saved LR | 4
24676 +---------------------------------------+
24677 | Parameter save area (+padding*) (P) | 8
24678 +---------------------------------------+
24679 | Alloca space (A) | 8+P
24680 +---------------------------------------+
24681 | Varargs save area (V) | 8+P+A
24682 +---------------------------------------+
24683 | Local variable space (L) | 8+P+A+V
24684 +---------------------------------------+
24685 | Float/int conversion temporary (X) | 8+P+A+V+L
24686 +---------------------------------------+
24687 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24688 +---------------------------------------+
24689 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24690 +---------------------------------------+
24691 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24692 +---------------------------------------+
24693 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24694 +---------------------------------------+
24695 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24696 +---------------------------------------+
24697 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24698 +---------------------------------------+
24699 old SP->| back chain to caller's caller |
24700 +---------------------------------------+
24702 * If the alloca area is present and the required alignment is
24703 16 bytes, the parameter save area is padded so that the
24704 alloca area starts 16-byte aligned.
24706 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24707 given. (But note below and in sysv4.h that we require only 8 and
24708 may round up the size of our stack frame anyways. The historical
24709 reason is early versions of powerpc-linux which didn't properly
24710 align the stack at program startup. A happy side-effect is that
24711 -mno-eabi libraries can be used with -meabi programs.)
24713 The EABI configuration defaults to the V.4 layout. However,
24714 the stack alignment requirements may differ. If -mno-eabi is not
24715 given, the required stack alignment is 8 bytes; if -mno-eabi is
24716 given, the required alignment is 16 bytes. (But see V.4 comment
24719 #ifndef ABI_STACK_BOUNDARY
24720 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24723 static rs6000_stack_t *
24724 rs6000_stack_info (void)
24726 /* We should never be called for thunks, we are not set up for that. */
24727 gcc_assert (!cfun->is_thunk);
24729 rs6000_stack_t *info = &stack_info;
24730 int reg_size = TARGET_32BIT ? 4 : 8;
24735 HOST_WIDE_INT non_fixed_size;
24736 bool using_static_chain_p;
24738 if (reload_completed && info->reload_completed)
24741 memset (info, 0, sizeof (*info));
24742 info->reload_completed = reload_completed;
24744 /* Select which calling sequence. */
24745 info->abi = DEFAULT_ABI;
24747 /* Calculate which registers need to be saved & save area size. */
24748 info->first_gp_reg_save = first_reg_to_save ();
24749 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24750 even if it currently looks like we won't. Reload may need it to
24751 get at a constant; if so, it will have already created a constant
24752 pool entry for it. */
24753 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24754 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24755 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24756 && crtl->uses_const_pool
24757 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24758 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24760 first_gp = info->first_gp_reg_save;
24762 info->gp_size = reg_size * (32 - first_gp);
24764 info->first_fp_reg_save = first_fp_reg_to_save ();
24765 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24767 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24768 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24769 - info->first_altivec_reg_save);
24771 /* Does this function call anything? */
24772 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24774 /* Determine if we need to save the condition code registers. */
24775 if (save_reg_p (CR2_REGNO)
24776 || save_reg_p (CR3_REGNO)
24777 || save_reg_p (CR4_REGNO))
24779 info->cr_save_p = 1;
24780 if (DEFAULT_ABI == ABI_V4)
24781 info->cr_size = reg_size;
24784 /* If the current function calls __builtin_eh_return, then we need
24785 to allocate stack space for registers that will hold data for
24786 the exception handler. */
24787 if (crtl->calls_eh_return)
24790 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24793 ehrd_size = i * UNITS_PER_WORD;
24798 /* In the ELFv2 ABI, we also need to allocate space for separate
24799 CR field save areas if the function calls __builtin_eh_return. */
24800 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24802 /* This hard-codes that we have three call-saved CR fields. */
24803 ehcr_size = 3 * reg_size;
24804 /* We do *not* use the regular CR save mechanism. */
24805 info->cr_save_p = 0;
24810 /* Determine various sizes. */
24811 info->reg_size = reg_size;
24812 info->fixed_size = RS6000_SAVE_AREA;
24813 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24814 if (cfun->calls_alloca)
24816 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24817 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24819 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24820 TARGET_ALTIVEC ? 16 : 8);
24821 if (FRAME_GROWS_DOWNWARD)
24823 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24824 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24825 - (info->fixed_size + info->vars_size + info->parm_size);
24827 if (TARGET_ALTIVEC_ABI)
24828 info->vrsave_mask = compute_vrsave_mask ();
24830 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24831 info->vrsave_size = 4;
24833 compute_save_world_info (info);
24835 /* Calculate the offsets. */
24836 switch (DEFAULT_ABI)
24840 gcc_unreachable ();
24845 info->fp_save_offset = -info->fp_size;
24846 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24848 if (TARGET_ALTIVEC_ABI)
24850 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24852 /* Align stack so vector save area is on a quadword boundary.
24853 The padding goes above the vectors. */
24854 if (info->altivec_size != 0)
24855 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24857 info->altivec_save_offset = info->vrsave_save_offset
24858 - info->altivec_padding_size
24859 - info->altivec_size;
24860 gcc_assert (info->altivec_size == 0
24861 || info->altivec_save_offset % 16 == 0);
24863 /* Adjust for AltiVec case. */
24864 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24867 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24869 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24870 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24871 info->lr_save_offset = 2*reg_size;
24875 info->fp_save_offset = -info->fp_size;
24876 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24877 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24879 if (TARGET_ALTIVEC_ABI)
24881 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24883 /* Align stack so vector save area is on a quadword boundary. */
24884 if (info->altivec_size != 0)
24885 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24887 info->altivec_save_offset = info->vrsave_save_offset
24888 - info->altivec_padding_size
24889 - info->altivec_size;
24891 /* Adjust for AltiVec case. */
24892 info->ehrd_offset = info->altivec_save_offset;
24895 info->ehrd_offset = info->cr_save_offset;
24897 info->ehrd_offset -= ehrd_size;
24898 info->lr_save_offset = reg_size;
24901 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24902 info->save_size = RS6000_ALIGN (info->fp_size
24904 + info->altivec_size
24905 + info->altivec_padding_size
24909 + info->vrsave_size,
24912 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24914 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24915 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24917 /* Determine if we need to save the link register. */
24919 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24921 && !TARGET_PROFILE_KERNEL)
24922 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24923 #ifdef TARGET_RELOCATABLE
24924 || (DEFAULT_ABI == ABI_V4
24925 && (TARGET_RELOCATABLE || flag_pic > 1)
24926 && !constant_pool_empty_p ())
24928 || rs6000_ra_ever_killed ())
24929 info->lr_save_p = 1;
24931 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24932 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24933 && call_used_regs[STATIC_CHAIN_REGNUM]);
24934 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24936 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24937 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24938 || !(info->savres_strategy & SAVE_INLINE_VRS)
24939 || !(info->savres_strategy & REST_INLINE_GPRS)
24940 || !(info->savres_strategy & REST_INLINE_FPRS)
24941 || !(info->savres_strategy & REST_INLINE_VRS))
24942 info->lr_save_p = 1;
24944 if (info->lr_save_p)
24945 df_set_regs_ever_live (LR_REGNO, true);
24947 /* Determine if we need to allocate any stack frame:
24949 For AIX we need to push the stack if a frame pointer is needed
24950 (because the stack might be dynamically adjusted), if we are
24951 debugging, if we make calls, or if the sum of fp_save, gp_save,
24952 and local variables are more than the space needed to save all
24953 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24954 + 18*8 = 288 (GPR13 reserved).
24956 For V.4 we don't have the stack cushion that AIX uses, but assume
24957 that the debugger can handle stackless frames. */
24962 else if (DEFAULT_ABI == ABI_V4)
24963 info->push_p = non_fixed_size != 0;
24965 else if (frame_pointer_needed)
24968 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24972 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24978 debug_stack_info (rs6000_stack_t *info)
24980 const char *abi_string;
24983 info = rs6000_stack_info ();
24985 fprintf (stderr, "\nStack information for function %s:\n",
24986 ((current_function_decl && DECL_NAME (current_function_decl))
24987 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24992 default: abi_string = "Unknown"; break;
24993 case ABI_NONE: abi_string = "NONE"; break;
24994 case ABI_AIX: abi_string = "AIX"; break;
24995 case ABI_ELFv2: abi_string = "ELFv2"; break;
24996 case ABI_DARWIN: abi_string = "Darwin"; break;
24997 case ABI_V4: abi_string = "V.4"; break;
25000 fprintf (stderr, "\tABI = %5s\n", abi_string);
25002 if (TARGET_ALTIVEC_ABI)
25003 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
25005 if (info->first_gp_reg_save != 32)
25006 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
25008 if (info->first_fp_reg_save != 64)
25009 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
25011 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
25012 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
25013 info->first_altivec_reg_save);
25015 if (info->lr_save_p)
25016 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
25018 if (info->cr_save_p)
25019 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
25021 if (info->vrsave_mask)
25022 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
25025 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
25028 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
25031 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
25034 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
25036 if (info->altivec_size)
25037 fprintf (stderr, "\taltivec_save_offset = %5d\n",
25038 info->altivec_save_offset);
25040 if (info->vrsave_size)
25041 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
25042 info->vrsave_save_offset);
25044 if (info->lr_save_p)
25045 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
25047 if (info->cr_save_p)
25048 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
25050 if (info->varargs_save_offset)
25051 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
25053 if (info->total_size)
25054 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25057 if (info->vars_size)
25058 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25061 if (info->parm_size)
25062 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
25064 if (info->fixed_size)
25065 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
25068 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
25071 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
25073 if (info->altivec_size)
25074 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
25076 if (info->vrsave_size)
25077 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
25079 if (info->altivec_padding_size)
25080 fprintf (stderr, "\taltivec_padding_size= %5d\n",
25081 info->altivec_padding_size);
25084 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
25086 if (info->save_size)
25087 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
25089 if (info->reg_size != 4)
25090 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
25092 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
25094 fprintf (stderr, "\n");
25098 rs6000_return_addr (int count, rtx frame)
25100 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25101 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25103 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
25105 cfun->machine->ra_needs_full_frame = 1;
25108 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25109 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25110 frame = stack_pointer_rtx;
25111 rtx prev_frame_addr = memory_address (Pmode, frame);
25112 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
25113 rtx lr_save_off = plus_constant (Pmode,
25114 prev_frame, RETURN_ADDRESS_OFFSET);
25115 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
25116 return gen_rtx_MEM (Pmode, lr_save_addr);
25119 cfun->machine->ra_need_lr = 1;
25120 return get_hard_reg_initial_val (Pmode, LR_REGNO);
25123 /* Say whether a function is a candidate for sibcall handling or not. */
25126 rs6000_function_ok_for_sibcall (tree decl, tree exp)
25131 fntype = TREE_TYPE (decl);
25133 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
25135 /* We can't do it if the called function has more vector parameters
25136 than the current function; there's nowhere to put the VRsave code. */
25137 if (TARGET_ALTIVEC_ABI
25138 && TARGET_ALTIVEC_VRSAVE
25139 && !(decl && decl == current_function_decl))
25141 function_args_iterator args_iter;
25145 /* Functions with vector parameters are required to have a
25146 prototype, so the argument type info must be available
25148 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
25149 if (TREE_CODE (type) == VECTOR_TYPE
25150 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25153 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
25154 if (TREE_CODE (type) == VECTOR_TYPE
25155 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25162 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25163 functions, because the callee may have a different TOC pointer to
25164 the caller and there's no way to ensure we restore the TOC when
25165 we return. With the secure-plt SYSV ABI we can't make non-local
25166 calls when -fpic/PIC because the plt call stubs use r30. */
25167 if (DEFAULT_ABI == ABI_DARWIN
25168 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25170 && !DECL_EXTERNAL (decl)
25171 && !DECL_WEAK (decl)
25172 && (*targetm.binds_local_p) (decl))
25173 || (DEFAULT_ABI == ABI_V4
25174 && (!TARGET_SECURE_PLT
25177 && (*targetm.binds_local_p) (decl)))))
25179 tree attr_list = TYPE_ATTRIBUTES (fntype);
25181 if (!lookup_attribute ("longcall", attr_list)
25182 || lookup_attribute ("shortcall", attr_list))
25190 rs6000_ra_ever_killed (void)
25196 if (cfun->is_thunk)
25199 if (cfun->machine->lr_save_state)
25200 return cfun->machine->lr_save_state - 1;
25202 /* regs_ever_live has LR marked as used if any sibcalls are present,
25203 but this should not force saving and restoring in the
25204 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25205 clobbers LR, so that is inappropriate. */
25207 /* Also, the prologue can generate a store into LR that
25208 doesn't really count, like this:
25211 bcl to set PIC register
25215 When we're called from the epilogue, we need to avoid counting
25216 this as a store. */
25218 push_topmost_sequence ();
25219 top = get_insns ();
25220 pop_topmost_sequence ();
25221 reg = gen_rtx_REG (Pmode, LR_REGNO);
25223 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
25229 if (!SIBLING_CALL_P (insn))
25232 else if (find_regno_note (insn, REG_INC, LR_REGNO))
25234 else if (set_of (reg, insn) != NULL_RTX
25235 && !prologue_epilogue_contains (insn))
25242 /* Emit instructions needed to load the TOC register.
25243 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25244 a constant pool; or for SVR4 -fpic. */
25247 rs6000_emit_load_toc_table (int fromprolog)
25250 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
25252 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
25255 rtx lab, tmp1, tmp2, got;
25257 lab = gen_label_rtx ();
25258 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
25259 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25262 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25266 got = rs6000_got_sym ();
25267 tmp1 = tmp2 = dest;
25270 tmp1 = gen_reg_rtx (Pmode);
25271 tmp2 = gen_reg_rtx (Pmode);
25273 emit_insn (gen_load_toc_v4_PIC_1 (lab));
25274 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
25275 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
25276 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
25278 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
25280 emit_insn (gen_load_toc_v4_pic_si ());
25281 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25283 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
25286 rtx temp0 = (fromprolog
25287 ? gen_rtx_REG (Pmode, 0)
25288 : gen_reg_rtx (Pmode));
25294 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25295 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25297 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25298 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25300 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25301 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25302 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25308 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25310 lab = gen_label_rtx ();
25311 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25312 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25313 if (TARGET_LINK_STACK)
25314 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25315 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25317 emit_insn (gen_addsi3 (dest, temp0, dest));
25319 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25321 /* This is for AIX code running in non-PIC ELF32. */
25322 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25325 emit_insn (gen_elf_high (dest, realsym));
25326 emit_insn (gen_elf_low (dest, dest, realsym));
25330 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25333 emit_insn (gen_load_toc_aix_si (dest));
25335 emit_insn (gen_load_toc_aix_di (dest));
25339 /* Emit instructions to restore the link register after determining where
25340 its value has been stored. */
25343 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25345 rs6000_stack_t *info = rs6000_stack_info ();
25348 operands[0] = source;
25349 operands[1] = scratch;
25351 if (info->lr_save_p)
25353 rtx frame_rtx = stack_pointer_rtx;
25354 HOST_WIDE_INT sp_offset = 0;
25357 if (frame_pointer_needed
25358 || cfun->calls_alloca
25359 || info->total_size > 32767)
25361 tmp = gen_frame_mem (Pmode, frame_rtx);
25362 emit_move_insn (operands[1], tmp);
25363 frame_rtx = operands[1];
25365 else if (info->push_p)
25366 sp_offset = info->total_size;
25368 tmp = plus_constant (Pmode, frame_rtx,
25369 info->lr_save_offset + sp_offset);
25370 tmp = gen_frame_mem (Pmode, tmp);
25371 emit_move_insn (tmp, operands[0]);
25374 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25376 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25377 state of lr_save_p so any change from here on would be a bug. In
25378 particular, stop rs6000_ra_ever_killed from considering the SET
25379 of lr we may have added just above. */
25380 cfun->machine->lr_save_state = info->lr_save_p + 1;
25383 static GTY(()) alias_set_type set = -1;
25386 get_TOC_alias_set (void)
25389 set = new_alias_set ();
25393 /* This returns nonzero if the current function uses the TOC. This is
25394 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25395 is generated by the ABI_V4 load_toc_* patterns.
25396 Return 2 instead of 1 if the load_toc_* pattern is in the function
25397 partition that doesn't start the function. */
25405 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25409 rtx pat = PATTERN (insn);
25412 if (GET_CODE (pat) == PARALLEL)
25413 for (i = 0; i < XVECLEN (pat, 0); i++)
25415 rtx sub = XVECEXP (pat, 0, i);
25416 if (GET_CODE (sub) == USE)
25418 sub = XEXP (sub, 0);
25419 if (GET_CODE (sub) == UNSPEC
25420 && XINT (sub, 1) == UNSPEC_TOC)
25425 else if (crtl->has_bb_partition
25427 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25435 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25437 rtx tocrel, tocreg, hi;
25439 if (TARGET_DEBUG_ADDR)
25441 if (GET_CODE (symbol) == SYMBOL_REF)
25442 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25446 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25447 GET_RTX_NAME (GET_CODE (symbol)));
25448 debug_rtx (symbol);
25452 if (!can_create_pseudo_p ())
25453 df_set_regs_ever_live (TOC_REGISTER, true);
25455 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25456 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25457 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25460 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25461 if (largetoc_reg != NULL)
25463 emit_move_insn (largetoc_reg, hi);
25466 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25469 /* Issue assembly directives that create a reference to the given DWARF
25470 FRAME_TABLE_LABEL from the current function section. */
25472 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25474 fprintf (asm_out_file, "\t.ref %s\n",
25475 (* targetm.strip_name_encoding) (frame_table_label));
25478 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25479 and the change to the stack pointer. */
25482 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25489 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25490 if (hard_frame_needed)
25491 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25492 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25493 || (hard_frame_needed
25494 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25497 p = rtvec_alloc (i);
25500 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25501 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25504 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25507 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25508 and set the appropriate attributes for the generated insn. Return the
25509 first insn which adjusts the stack pointer or the last insn before
25510 the stack adjustment loop.
25512 SIZE_INT is used to create the CFI note for the allocation.
25514 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25515 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25517 ORIG_SP contains the backchain value that must be stored at *sp. */
25520 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25524 rtx size_rtx = GEN_INT (-size_int);
25525 if (size_int > 32767)
25527 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25528 /* Need a note here so that try_split doesn't get confused. */
25529 if (get_last_insn () == NULL_RTX)
25530 emit_note (NOTE_INSN_DELETED);
25531 insn = emit_move_insn (tmp_reg, size_rtx);
25532 try_split (PATTERN (insn), insn, 0);
25533 size_rtx = tmp_reg;
25536 if (Pmode == SImode)
25537 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25542 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
25546 rtx par = PATTERN (insn);
25547 gcc_assert (GET_CODE (par) == PARALLEL);
25548 rtx set = XVECEXP (par, 0, 0);
25549 gcc_assert (GET_CODE (set) == SET);
25550 rtx mem = SET_DEST (set);
25551 gcc_assert (MEM_P (mem));
25552 MEM_NOTRAP_P (mem) = 1;
25553 set_mem_alias_set (mem, get_frame_alias_set ());
25555 RTX_FRAME_RELATED_P (insn) = 1;
25556 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25557 gen_rtx_SET (stack_pointer_rtx,
25558 gen_rtx_PLUS (Pmode,
25560 GEN_INT (-size_int))));
25562 /* Emit a blockage to ensure the allocation/probing insns are
25563 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25564 note for similar reasons. */
25565 if (flag_stack_clash_protection)
25567 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25568 emit_insn (gen_blockage ());
25574 static HOST_WIDE_INT
25575 get_stack_clash_protection_probe_interval (void)
25577 return (HOST_WIDE_INT_1U
25578 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25581 static HOST_WIDE_INT
25582 get_stack_clash_protection_guard_size (void)
25584 return (HOST_WIDE_INT_1U
25585 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25588 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25589 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25591 COPY_REG, if non-null, should contain a copy of the original
25592 stack pointer at exit from this function.
25594 This is subtly different than the Ada probing in that it tries hard to
25595 prevent attacks that jump the stack guard. Thus it is never allowed to
25596 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25597 space without a suitable probe. */
25599 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25602 rtx orig_sp = copy_reg;
25604 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25606 /* Round the size down to a multiple of PROBE_INTERVAL. */
25607 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25609 /* If explicitly requested,
25610 or the rounded size is not the same as the original size
25611 or the the rounded size is greater than a page,
25612 then we will need a copy of the original stack pointer. */
25613 if (rounded_size != orig_size
25614 || rounded_size > probe_interval
25617 /* If the caller did not request a copy of the incoming stack
25618 pointer, then we use r0 to hold the copy. */
25620 orig_sp = gen_rtx_REG (Pmode, 0);
25621 emit_move_insn (orig_sp, stack_pointer_rtx);
25624 /* There's three cases here.
25626 One is a single probe which is the most common and most efficiently
25627 implemented as it does not have to have a copy of the original
25628 stack pointer if there are no residuals.
25630 Second is unrolled allocation/probes which we use if there's just
25631 a few of them. It needs to save the original stack pointer into a
25632 temporary for use as a source register in the allocation/probe.
25634 Last is a loop. This is the most uncommon case and least efficient. */
25635 rtx_insn *retval = NULL;
25636 if (rounded_size == probe_interval)
25638 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25640 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25642 else if (rounded_size <= 8 * probe_interval)
25644 /* The ABI requires using the store with update insns to allocate
25645 space and store the backchain into the stack
25647 So we save the current stack pointer into a temporary, then
25648 emit the store-with-update insns to store the saved stack pointer
25649 into the right location in each new page. */
25650 for (int i = 0; i < rounded_size; i += probe_interval)
25653 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25655 /* Save the first stack adjustment in RETVAL. */
25660 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25664 /* Compute the ending address. */
25666 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25667 rtx rs = GEN_INT (-rounded_size);
25669 if (add_operand (rs, Pmode))
25670 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25673 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25674 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25675 stack_pointer_rtx));
25676 /* Describe the effect of INSN to the CFI engine. */
25677 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25678 gen_rtx_SET (end_addr,
25679 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25682 RTX_FRAME_RELATED_P (insn) = 1;
25684 /* Emit the loop. */
25686 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25687 stack_pointer_rtx, orig_sp,
25690 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25691 stack_pointer_rtx, orig_sp,
25693 RTX_FRAME_RELATED_P (retval) = 1;
25694 /* Describe the effect of INSN to the CFI engine. */
25695 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25696 gen_rtx_SET (stack_pointer_rtx, end_addr));
25698 /* Emit a blockage to ensure the allocation/probing insns are
25699 not optimized, combined, removed, etc. Other cases handle this
25700 within their call to rs6000_emit_allocate_stack_1. */
25701 emit_insn (gen_blockage ());
25703 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25706 if (orig_size != rounded_size)
25708 /* Allocate (and implicitly probe) any residual space. */
25709 HOST_WIDE_INT residual = orig_size - rounded_size;
25711 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25713 /* If the residual was the only allocation, then we can return the
25714 allocating insn. */
25722 /* Emit the correct code for allocating stack space, as insns.
25723 If COPY_REG, make sure a copy of the old frame is left there.
25724 The generated code may use hard register 0 as a temporary. */
25727 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25730 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25731 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25732 rtx todec = gen_int_mode (-size, Pmode);
25734 if (INTVAL (todec) != -size)
25736 warning (0, "stack frame too large");
25737 emit_insn (gen_trap ());
25741 if (crtl->limit_stack)
25743 if (REG_P (stack_limit_rtx)
25744 && REGNO (stack_limit_rtx) > 1
25745 && REGNO (stack_limit_rtx) <= 31)
25748 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25751 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25753 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25755 && DEFAULT_ABI == ABI_V4
25758 rtx toload = gen_rtx_CONST (VOIDmode,
25759 gen_rtx_PLUS (Pmode,
25763 emit_insn (gen_elf_high (tmp_reg, toload));
25764 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25765 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25769 warning (0, "stack limit expression is not supported");
25772 if (flag_stack_clash_protection)
25774 if (size < get_stack_clash_protection_guard_size ())
25775 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25778 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25781 /* If we asked for a copy with an offset, then we still need add in
25783 if (copy_reg && copy_off)
25784 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25792 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25794 emit_move_insn (copy_reg, stack_reg);
25797 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25798 it now and set the alias set/attributes. The above gen_*_update
25799 calls will generate a PARALLEL with the MEM set being the first
25801 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25805 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25807 #if PROBE_INTERVAL > 32768
25808 #error Cannot use indexed addressing mode for stack probing
25811 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25812 inclusive. These are offsets from the current stack pointer. */
25815 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25817 /* See if we have a constant small number of probes to generate. If so,
25818 that's the easy case. */
25819 if (first + size <= 32768)
25823 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25824 it exceeds SIZE. If only one probe is needed, this will not
25825 generate any code. Then probe at FIRST + SIZE. */
25826 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25827 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25830 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25834 /* Otherwise, do the same as above, but in a loop. Note that we must be
25835 extra careful with variables wrapping around because we might be at
25836 the very top (or the very bottom) of the address space and we have
25837 to be able to handle this case properly; in particular, we use an
25838 equality test for the loop condition. */
25841 HOST_WIDE_INT rounded_size;
25842 rtx r12 = gen_rtx_REG (Pmode, 12);
25843 rtx r0 = gen_rtx_REG (Pmode, 0);
25845 /* Sanity check for the addressing mode we're going to use. */
25846 gcc_assert (first <= 32768);
25848 /* Step 1: round SIZE to the previous multiple of the interval. */
25850 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25853 /* Step 2: compute initial and final value of the loop counter. */
25855 /* TEST_ADDR = SP + FIRST. */
25856 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25859 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25860 if (rounded_size > 32768)
25862 emit_move_insn (r0, GEN_INT (-rounded_size));
25863 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25866 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25870 /* Step 3: the loop
25874 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25877 while (TEST_ADDR != LAST_ADDR)
25879 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25880 until it is equal to ROUNDED_SIZE. */
25883 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25885 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25888 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25889 that SIZE is equal to ROUNDED_SIZE. */
25891 if (size != rounded_size)
25892 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25896 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25897 addresses, not offsets. */
25899 static const char *
25900 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25902 static int labelno = 0;
25906 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25909 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25911 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25913 xops[1] = GEN_INT (-PROBE_INTERVAL);
25914 output_asm_insn ("addi %0,%0,%1", xops);
25916 /* Probe at TEST_ADDR. */
25917 xops[1] = gen_rtx_REG (Pmode, 0);
25918 output_asm_insn ("stw %1,0(%0)", xops);
25920 /* Test if TEST_ADDR == LAST_ADDR. */
25923 output_asm_insn ("cmpd 0,%0,%1", xops);
25925 output_asm_insn ("cmpw 0,%0,%1", xops);
25928 fputs ("\tbne 0,", asm_out_file);
25929 assemble_name_raw (asm_out_file, loop_lab);
25930 fputc ('\n', asm_out_file);
25935 /* This function is called when rs6000_frame_related is processing
25936 SETs within a PARALLEL, and returns whether the REGNO save ought to
25937 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25938 for out-of-line register save functions, store multiple, and the
25939 Darwin world_save. They may contain registers that don't really
25943 interesting_frame_related_regno (unsigned int regno)
25945 /* Saves apparently of r0 are actually saving LR. It doesn't make
25946 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25947 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25948 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25949 as frame related. */
25952 /* If we see CR2 then we are here on a Darwin world save. Saves of
25953 CR2 signify the whole CR is being saved. This is a long-standing
25954 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25955 that CR needs to be saved. */
25956 if (regno == CR2_REGNO)
25958 /* Omit frame info for any user-defined global regs. If frame info
25959 is supplied for them, frame unwinding will restore a user reg.
25960 Also omit frame info for any reg we don't need to save, as that
25961 bloats frame info and can cause problems with shrink wrapping.
25962 Since global regs won't be seen as needing to be saved, both of
25963 these conditions are covered by save_reg_p. */
25964 return save_reg_p (regno);
25967 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25968 addresses, not offsets.
25970 REG2 contains the backchain that must be stored into *sp at each allocation.
25972 This is subtly different than the Ada probing above in that it tries hard
25973 to prevent attacks that jump the stack guard. Thus, it is never allowed
25974 to allocate more than PROBE_INTERVAL bytes of stack space without a
25977 static const char *
25978 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25980 static int labelno = 0;
25984 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25986 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25988 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25990 /* This allocates and probes. */
25993 xops[2] = GEN_INT (-probe_interval);
25995 output_asm_insn ("stdu %1,%2(%0)", xops);
25997 output_asm_insn ("stwu %1,%2(%0)", xops);
25999 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
26003 output_asm_insn ("cmpd 0,%0,%1", xops);
26005 output_asm_insn ("cmpw 0,%0,%1", xops);
26007 fputs ("\tbne 0,", asm_out_file);
26008 assemble_name_raw (asm_out_file, loop_lab);
26009 fputc ('\n', asm_out_file);
26014 /* Wrapper around the output_probe_stack_range routines. */
26016 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
26018 if (flag_stack_clash_protection)
26019 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
26021 return output_probe_stack_range_1 (reg1, reg3);
26024 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
26025 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
26026 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
26027 deduce these equivalences by itself so it wasn't necessary to hold
26028 its hand so much. Don't be tempted to always supply d2_f_d_e with
26029 the actual cfa register, ie. r31 when we are using a hard frame
26030 pointer. That fails when saving regs off r1, and sched moves the
26031 r31 setup past the reg saves. */
26034 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
26035 rtx reg2, rtx repl2)
26039 if (REGNO (reg) == STACK_POINTER_REGNUM)
26041 gcc_checking_assert (val == 0);
26045 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26048 rtx pat = PATTERN (insn);
26049 if (!repl && !reg2)
26051 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26052 if (GET_CODE (pat) == PARALLEL)
26053 for (int i = 0; i < XVECLEN (pat, 0); i++)
26054 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26056 rtx set = XVECEXP (pat, 0, i);
26058 if (!REG_P (SET_SRC (set))
26059 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26060 RTX_FRAME_RELATED_P (set) = 1;
26062 RTX_FRAME_RELATED_P (insn) = 1;
26066 /* We expect that 'pat' is either a SET or a PARALLEL containing
26067 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26068 are important so they all have to be marked RTX_FRAME_RELATED_P.
26069 Call simplify_replace_rtx on the SETs rather than the whole insn
26070 so as to leave the other stuff alone (for example USE of r12). */
26072 set_used_flags (pat);
26073 if (GET_CODE (pat) == SET)
26076 pat = simplify_replace_rtx (pat, reg, repl);
26078 pat = simplify_replace_rtx (pat, reg2, repl2);
26080 else if (GET_CODE (pat) == PARALLEL)
26082 pat = shallow_copy_rtx (pat);
26083 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
26085 for (int i = 0; i < XVECLEN (pat, 0); i++)
26086 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26088 rtx set = XVECEXP (pat, 0, i);
26091 set = simplify_replace_rtx (set, reg, repl);
26093 set = simplify_replace_rtx (set, reg2, repl2);
26094 XVECEXP (pat, 0, i) = set;
26096 if (!REG_P (SET_SRC (set))
26097 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26098 RTX_FRAME_RELATED_P (set) = 1;
26102 gcc_unreachable ();
26104 RTX_FRAME_RELATED_P (insn) = 1;
26105 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
26110 /* Returns an insn that has a vrsave set operation with the
26111 appropriate CLOBBERs. */
26114 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
26117 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
26118 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26121 = gen_rtx_SET (vrsave,
26122 gen_rtx_UNSPEC_VOLATILE (SImode,
26123 gen_rtvec (2, reg, vrsave),
26124 UNSPECV_SET_VRSAVE));
26128 /* We need to clobber the registers in the mask so the scheduler
26129 does not move sets to VRSAVE before sets of AltiVec registers.
26131 However, if the function receives nonlocal gotos, reload will set
26132 all call saved registers live. We will end up with:
26134 (set (reg 999) (mem))
26135 (parallel [ (set (reg vrsave) (unspec blah))
26136 (clobber (reg 999))])
26138 The clobber will cause the store into reg 999 to be dead, and
26139 flow will attempt to delete an epilogue insn. In this case, we
26140 need an unspec use/set of the register. */
26142 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
26143 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
26145 if (!epiloguep || call_used_regs [i])
26146 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
26147 gen_rtx_REG (V4SImode, i));
26150 rtx reg = gen_rtx_REG (V4SImode, i);
26153 = gen_rtx_SET (reg,
26154 gen_rtx_UNSPEC (V4SImode,
26155 gen_rtvec (1, reg), 27));
26159 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
26161 for (i = 0; i < nclobs; ++i)
26162 XVECEXP (insn, 0, i) = clobs[i];
26168 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
26172 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
26173 mem = gen_frame_mem (GET_MODE (reg), addr);
26174 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
26178 gen_frame_load (rtx reg, rtx frame_reg, int offset)
26180 return gen_frame_set (reg, frame_reg, offset, false);
26184 gen_frame_store (rtx reg, rtx frame_reg, int offset)
26186 return gen_frame_set (reg, frame_reg, offset, true);
26189 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26190 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26193 emit_frame_save (rtx frame_reg, machine_mode mode,
26194 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
26198 /* Some cases that need register indexed addressing. */
26199 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
26200 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
26202 reg = gen_rtx_REG (mode, regno);
26203 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
26204 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
26205 NULL_RTX, NULL_RTX);
26208 /* Emit an offset memory reference suitable for a frame store, while
26209 converting to a valid addressing mode. */
26212 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
26214 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
26217 #ifndef TARGET_FIX_AND_CONTINUE
26218 #define TARGET_FIX_AND_CONTINUE 0
26221 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26222 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26223 #define LAST_SAVRES_REGISTER 31
26224 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26235 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
26237 /* Temporary holding space for an out-of-line register save/restore
26239 static char savres_routine_name[30];
26241 /* Return the name for an out-of-line register save/restore routine.
26242 We are saving/restoring GPRs if GPR is true. */
26245 rs6000_savres_routine_name (int regno, int sel)
26247 const char *prefix = "";
26248 const char *suffix = "";
26250 /* Different targets are supposed to define
26251 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26252 routine name could be defined with:
26254 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26256 This is a nice idea in practice, but in reality, things are
26257 complicated in several ways:
26259 - ELF targets have save/restore routines for GPRs.
26261 - PPC64 ELF targets have routines for save/restore of GPRs that
26262 differ in what they do with the link register, so having a set
26263 prefix doesn't work. (We only use one of the save routines at
26264 the moment, though.)
26266 - PPC32 elf targets have "exit" versions of the restore routines
26267 that restore the link register and can save some extra space.
26268 These require an extra suffix. (There are also "tail" versions
26269 of the restore routines and "GOT" versions of the save routines,
26270 but we don't generate those at present. Same problems apply,
26273 We deal with all this by synthesizing our own prefix/suffix and
26274 using that for the simple sprintf call shown above. */
26275 if (DEFAULT_ABI == ABI_V4)
26280 if ((sel & SAVRES_REG) == SAVRES_GPR)
26281 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
26282 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26283 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
26284 else if ((sel & SAVRES_REG) == SAVRES_VR)
26285 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26289 if ((sel & SAVRES_LR))
26292 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26294 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26295 /* No out-of-line save/restore routines for GPRs on AIX. */
26296 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26300 if ((sel & SAVRES_REG) == SAVRES_GPR)
26301 prefix = ((sel & SAVRES_SAVE)
26302 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26303 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26304 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26306 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26307 if ((sel & SAVRES_LR))
26308 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26312 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26313 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26316 else if ((sel & SAVRES_REG) == SAVRES_VR)
26317 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26322 if (DEFAULT_ABI == ABI_DARWIN)
26324 /* The Darwin approach is (slightly) different, in order to be
26325 compatible with code generated by the system toolchain. There is a
26326 single symbol for the start of save sequence, and the code here
26327 embeds an offset into that code on the basis of the first register
26329 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26330 if ((sel & SAVRES_REG) == SAVRES_GPR)
26331 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26332 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26333 (regno - 13) * 4, prefix, regno);
26334 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26335 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26336 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26337 else if ((sel & SAVRES_REG) == SAVRES_VR)
26338 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26339 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26344 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26346 return savres_routine_name;
26349 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26350 We are saving/restoring GPRs if GPR is true. */
26353 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26355 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26356 ? info->first_gp_reg_save
26357 : (sel & SAVRES_REG) == SAVRES_FPR
26358 ? info->first_fp_reg_save - 32
26359 : (sel & SAVRES_REG) == SAVRES_VR
26360 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26365 /* Don't generate bogus routine names. */
26366 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26367 && regno <= LAST_SAVRES_REGISTER
26368 && select >= 0 && select <= 12);
26370 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26376 name = rs6000_savres_routine_name (regno, sel);
26378 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26379 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26380 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26386 /* Emit a sequence of insns, including a stack tie if needed, for
26387 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26388 reset the stack pointer, but move the base of the frame into
26389 reg UPDT_REGNO for use by out-of-line register restore routines. */
26392 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26393 unsigned updt_regno)
26395 /* If there is nothing to do, don't do anything. */
26396 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26399 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26401 /* This blockage is needed so that sched doesn't decide to move
26402 the sp change before the register restores. */
26403 if (DEFAULT_ABI == ABI_V4)
26404 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26405 GEN_INT (frame_off)));
26407 /* If we are restoring registers out-of-line, we will be using the
26408 "exit" variants of the restore routines, which will reset the
26409 stack for us. But we do need to point updt_reg into the
26410 right place for those routines. */
26411 if (frame_off != 0)
26412 return emit_insn (gen_add3_insn (updt_reg_rtx,
26413 frame_reg_rtx, GEN_INT (frame_off)));
26415 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26420 /* Return the register number used as a pointer by out-of-line
26421 save/restore functions. */
26423 static inline unsigned
26424 ptr_regno_for_savres (int sel)
26426 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26427 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26428 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26431 /* Construct a parallel rtx describing the effect of a call to an
26432 out-of-line register save/restore routine, and emit the insn
26433 or jump_insn as appropriate. */
26436 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26437 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26438 machine_mode reg_mode, int sel)
26441 int offset, start_reg, end_reg, n_regs, use_reg;
26442 int reg_size = GET_MODE_SIZE (reg_mode);
26449 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26450 ? info->first_gp_reg_save
26451 : (sel & SAVRES_REG) == SAVRES_FPR
26452 ? info->first_fp_reg_save
26453 : (sel & SAVRES_REG) == SAVRES_VR
26454 ? info->first_altivec_reg_save
26456 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26458 : (sel & SAVRES_REG) == SAVRES_FPR
26460 : (sel & SAVRES_REG) == SAVRES_VR
26461 ? LAST_ALTIVEC_REGNO + 1
26463 n_regs = end_reg - start_reg;
26464 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26465 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26468 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26469 RTVEC_ELT (p, offset++) = ret_rtx;
26471 RTVEC_ELT (p, offset++)
26472 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
26474 sym = rs6000_savres_routine_sym (info, sel);
26475 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26477 use_reg = ptr_regno_for_savres (sel);
26478 if ((sel & SAVRES_REG) == SAVRES_VR)
26480 /* Vector regs are saved/restored using [reg+reg] addressing. */
26481 RTVEC_ELT (p, offset++)
26482 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26483 RTVEC_ELT (p, offset++)
26484 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26487 RTVEC_ELT (p, offset++)
26488 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26490 for (i = 0; i < end_reg - start_reg; i++)
26491 RTVEC_ELT (p, i + offset)
26492 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26493 frame_reg_rtx, save_area_offset + reg_size * i,
26494 (sel & SAVRES_SAVE) != 0);
26496 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26497 RTVEC_ELT (p, i + offset)
26498 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26500 par = gen_rtx_PARALLEL (VOIDmode, p);
26502 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26504 insn = emit_jump_insn (par);
26505 JUMP_LABEL (insn) = ret_rtx;
26508 insn = emit_insn (par);
26512 /* Emit prologue code to store CR fields that need to be saved into REG. This
26513 function should only be called when moving the non-volatile CRs to REG, it
26514 is not a general purpose routine to move the entire set of CRs to REG.
26515 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26519 rs6000_emit_prologue_move_from_cr (rtx reg)
26521 /* Only the ELFv2 ABI allows storing only selected fields. */
26522 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26524 int i, cr_reg[8], count = 0;
26526 /* Collect CR fields that must be saved. */
26527 for (i = 0; i < 8; i++)
26528 if (save_reg_p (CR0_REGNO + i))
26529 cr_reg[count++] = i;
26531 /* If it's just a single one, use mfcrf. */
26534 rtvec p = rtvec_alloc (1);
26535 rtvec r = rtvec_alloc (2);
26536 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26537 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26539 = gen_rtx_SET (reg,
26540 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26542 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26546 /* ??? It might be better to handle count == 2 / 3 cases here
26547 as well, using logical operations to combine the values. */
26550 emit_insn (gen_prologue_movesi_from_cr (reg));
26553 /* Return whether the split-stack arg pointer (r12) is used. */
26556 split_stack_arg_pointer_used_p (void)
26558 /* If the pseudo holding the arg pointer is no longer a pseudo,
26559 then the arg pointer is used. */
26560 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26561 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26562 || (REGNO (cfun->machine->split_stack_arg_pointer)
26563 < FIRST_PSEUDO_REGISTER)))
26566 /* Unfortunately we also need to do some code scanning, since
26567 r12 may have been substituted for the pseudo. */
26569 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26570 FOR_BB_INSNS (bb, insn)
26571 if (NONDEBUG_INSN_P (insn))
26573 /* A call destroys r12. */
26578 FOR_EACH_INSN_USE (use, insn)
26580 rtx x = DF_REF_REG (use);
26581 if (REG_P (x) && REGNO (x) == 12)
26585 FOR_EACH_INSN_DEF (def, insn)
26587 rtx x = DF_REF_REG (def);
26588 if (REG_P (x) && REGNO (x) == 12)
26592 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26595 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26598 rs6000_global_entry_point_needed_p (void)
26600 /* Only needed for the ELFv2 ABI. */
26601 if (DEFAULT_ABI != ABI_ELFv2)
26604 /* With -msingle-pic-base, we assume the whole program shares the same
26605 TOC, so no global entry point prologues are needed anywhere. */
26606 if (TARGET_SINGLE_PIC_BASE)
26609 /* Ensure we have a global entry point for thunks. ??? We could
26610 avoid that if the target routine doesn't need a global entry point,
26611 but we do not know whether this is the case at this point. */
26612 if (cfun->is_thunk)
26615 /* For regular functions, rs6000_emit_prologue sets this flag if the
26616 routine ever uses the TOC pointer. */
26617 return cfun->machine->r2_setup_needed;
26620 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26622 rs6000_get_separate_components (void)
26624 rs6000_stack_t *info = rs6000_stack_info ();
26626 if (WORLD_SAVE_P (info))
26629 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26630 && !(info->savres_strategy & REST_MULTIPLE));
26632 /* Component 0 is the save/restore of LR (done via GPR0).
26633 Component 2 is the save of the TOC (GPR2).
26634 Components 13..31 are the save/restore of GPR13..GPR31.
26635 Components 46..63 are the save/restore of FPR14..FPR31. */
26637 cfun->machine->n_components = 64;
26639 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26640 bitmap_clear (components);
26642 int reg_size = TARGET_32BIT ? 4 : 8;
26643 int fp_reg_size = 8;
26645 /* The GPRs we need saved to the frame. */
26646 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26647 && (info->savres_strategy & REST_INLINE_GPRS))
26649 int offset = info->gp_save_offset;
26651 offset += info->total_size;
26653 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26655 if (IN_RANGE (offset, -0x8000, 0x7fff)
26656 && save_reg_p (regno))
26657 bitmap_set_bit (components, regno);
26659 offset += reg_size;
26663 /* Don't mess with the hard frame pointer. */
26664 if (frame_pointer_needed)
26665 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26667 /* Don't mess with the fixed TOC register. */
26668 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26669 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26670 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26671 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26673 /* The FPRs we need saved to the frame. */
26674 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26675 && (info->savres_strategy & REST_INLINE_FPRS))
26677 int offset = info->fp_save_offset;
26679 offset += info->total_size;
26681 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26683 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26684 bitmap_set_bit (components, regno);
26686 offset += fp_reg_size;
26690 /* Optimize LR save and restore if we can. This is component 0. Any
26691 out-of-line register save/restore routines need LR. */
26692 if (info->lr_save_p
26693 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26694 && (info->savres_strategy & SAVE_INLINE_GPRS)
26695 && (info->savres_strategy & REST_INLINE_GPRS)
26696 && (info->savres_strategy & SAVE_INLINE_FPRS)
26697 && (info->savres_strategy & REST_INLINE_FPRS)
26698 && (info->savres_strategy & SAVE_INLINE_VRS)
26699 && (info->savres_strategy & REST_INLINE_VRS))
26701 int offset = info->lr_save_offset;
26703 offset += info->total_size;
26704 if (IN_RANGE (offset, -0x8000, 0x7fff))
26705 bitmap_set_bit (components, 0);
26708 /* Optimize saving the TOC. This is component 2. */
26709 if (cfun->machine->save_toc_in_prologue)
26710 bitmap_set_bit (components, 2);
26715 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26717 rs6000_components_for_bb (basic_block bb)
26719 rs6000_stack_t *info = rs6000_stack_info ();
26721 bitmap in = DF_LIVE_IN (bb);
26722 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26723 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26725 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26726 bitmap_clear (components);
26728 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26731 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26732 if (bitmap_bit_p (in, regno)
26733 || bitmap_bit_p (gen, regno)
26734 || bitmap_bit_p (kill, regno))
26735 bitmap_set_bit (components, regno);
26738 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26739 if (bitmap_bit_p (in, regno)
26740 || bitmap_bit_p (gen, regno)
26741 || bitmap_bit_p (kill, regno))
26742 bitmap_set_bit (components, regno);
26744 /* The link register. */
26745 if (bitmap_bit_p (in, LR_REGNO)
26746 || bitmap_bit_p (gen, LR_REGNO)
26747 || bitmap_bit_p (kill, LR_REGNO))
26748 bitmap_set_bit (components, 0);
26750 /* The TOC save. */
26751 if (bitmap_bit_p (in, TOC_REGNUM)
26752 || bitmap_bit_p (gen, TOC_REGNUM)
26753 || bitmap_bit_p (kill, TOC_REGNUM))
26754 bitmap_set_bit (components, 2);
26759 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26761 rs6000_disqualify_components (sbitmap components, edge e,
26762 sbitmap edge_components, bool /*is_prologue*/)
26764 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26765 live where we want to place that code. */
26766 if (bitmap_bit_p (edge_components, 0)
26767 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26770 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26771 "on entry to bb %d\n", e->dest->index);
26772 bitmap_clear_bit (components, 0);
26776 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26778 rs6000_emit_prologue_components (sbitmap components)
26780 rs6000_stack_t *info = rs6000_stack_info ();
26781 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26782 ? HARD_FRAME_POINTER_REGNUM
26783 : STACK_POINTER_REGNUM);
26785 machine_mode reg_mode = Pmode;
26786 int reg_size = TARGET_32BIT ? 4 : 8;
26787 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26789 int fp_reg_size = 8;
26791 /* Prologue for LR. */
26792 if (bitmap_bit_p (components, 0))
26794 rtx reg = gen_rtx_REG (reg_mode, 0);
26795 rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
26796 RTX_FRAME_RELATED_P (insn) = 1;
26797 add_reg_note (insn, REG_CFA_REGISTER, NULL);
26799 int offset = info->lr_save_offset;
26801 offset += info->total_size;
26803 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26804 RTX_FRAME_RELATED_P (insn) = 1;
26805 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26806 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26807 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26810 /* Prologue for TOC. */
26811 if (bitmap_bit_p (components, 2))
26813 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26814 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26815 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26818 /* Prologue for the GPRs. */
26819 int offset = info->gp_save_offset;
26821 offset += info->total_size;
26823 for (int i = info->first_gp_reg_save; i < 32; i++)
26825 if (bitmap_bit_p (components, i))
26827 rtx reg = gen_rtx_REG (reg_mode, i);
26828 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26829 RTX_FRAME_RELATED_P (insn) = 1;
26830 rtx set = copy_rtx (single_set (insn));
26831 add_reg_note (insn, REG_CFA_OFFSET, set);
26834 offset += reg_size;
26837 /* Prologue for the FPRs. */
26838 offset = info->fp_save_offset;
26840 offset += info->total_size;
26842 for (int i = info->first_fp_reg_save; i < 64; i++)
26844 if (bitmap_bit_p (components, i))
26846 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26847 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26848 RTX_FRAME_RELATED_P (insn) = 1;
26849 rtx set = copy_rtx (single_set (insn));
26850 add_reg_note (insn, REG_CFA_OFFSET, set);
26853 offset += fp_reg_size;
26857 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26859 rs6000_emit_epilogue_components (sbitmap components)
26861 rs6000_stack_t *info = rs6000_stack_info ();
26862 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26863 ? HARD_FRAME_POINTER_REGNUM
26864 : STACK_POINTER_REGNUM);
26866 machine_mode reg_mode = Pmode;
26867 int reg_size = TARGET_32BIT ? 4 : 8;
26869 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26871 int fp_reg_size = 8;
26873 /* Epilogue for the FPRs. */
26874 int offset = info->fp_save_offset;
26876 offset += info->total_size;
26878 for (int i = info->first_fp_reg_save; i < 64; i++)
26880 if (bitmap_bit_p (components, i))
26882 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26883 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26884 RTX_FRAME_RELATED_P (insn) = 1;
26885 add_reg_note (insn, REG_CFA_RESTORE, reg);
26888 offset += fp_reg_size;
26891 /* Epilogue for the GPRs. */
26892 offset = info->gp_save_offset;
26894 offset += info->total_size;
26896 for (int i = info->first_gp_reg_save; i < 32; i++)
26898 if (bitmap_bit_p (components, i))
26900 rtx reg = gen_rtx_REG (reg_mode, i);
26901 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26902 RTX_FRAME_RELATED_P (insn) = 1;
26903 add_reg_note (insn, REG_CFA_RESTORE, reg);
26906 offset += reg_size;
26909 /* Epilogue for LR. */
26910 if (bitmap_bit_p (components, 0))
26912 int offset = info->lr_save_offset;
26914 offset += info->total_size;
26916 rtx reg = gen_rtx_REG (reg_mode, 0);
26917 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26919 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26920 insn = emit_move_insn (lr, reg);
26921 RTX_FRAME_RELATED_P (insn) = 1;
26922 add_reg_note (insn, REG_CFA_RESTORE, lr);
26926 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26928 rs6000_set_handled_components (sbitmap components)
26930 rs6000_stack_t *info = rs6000_stack_info ();
26932 for (int i = info->first_gp_reg_save; i < 32; i++)
26933 if (bitmap_bit_p (components, i))
26934 cfun->machine->gpr_is_wrapped_separately[i] = true;
26936 for (int i = info->first_fp_reg_save; i < 64; i++)
26937 if (bitmap_bit_p (components, i))
26938 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26940 if (bitmap_bit_p (components, 0))
26941 cfun->machine->lr_is_wrapped_separately = true;
26943 if (bitmap_bit_p (components, 2))
26944 cfun->machine->toc_is_wrapped_separately = true;
26947 /* VRSAVE is a bit vector representing which AltiVec registers
26948 are used. The OS uses this to determine which vector
26949 registers to save on a context switch. We need to save
26950 VRSAVE on the stack frame, add whatever AltiVec registers we
26951 used in this function, and do the corresponding magic in the
26954 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26955 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26957 /* Get VRSAVE into a GPR. */
26958 rtx reg = gen_rtx_REG (SImode, save_regno);
26959 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26961 emit_insn (gen_get_vrsave_internal (reg));
26963 emit_insn (gen_rtx_SET (reg, vrsave));
26966 int offset = info->vrsave_save_offset + frame_off;
26967 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26969 /* Include the registers in the mask. */
26970 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26972 emit_insn (generate_set_vrsave (reg, info, 0));
26975 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26976 called, it left the arg pointer to the old stack in r29. Otherwise, the
26977 arg pointer is the top of the current frame. */
26979 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26980 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26982 cfun->machine->split_stack_argp_used = true;
26986 rtx r12 = gen_rtx_REG (Pmode, 12);
26987 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26988 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26989 emit_insn_before (set_r12, sp_adjust);
26991 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26993 rtx r12 = gen_rtx_REG (Pmode, 12);
26994 if (frame_off == 0)
26995 emit_move_insn (r12, frame_reg_rtx);
26997 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
27002 rtx r12 = gen_rtx_REG (Pmode, 12);
27003 rtx r29 = gen_rtx_REG (Pmode, 29);
27004 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
27005 rtx not_more = gen_label_rtx ();
27008 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27009 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
27010 gen_rtx_LABEL_REF (VOIDmode, not_more),
27012 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27013 JUMP_LABEL (jump) = not_more;
27014 LABEL_NUSES (not_more) += 1;
27015 emit_move_insn (r12, r29);
27016 emit_label (not_more);
27020 /* Emit function prologue as insns. */
27023 rs6000_emit_prologue (void)
27025 rs6000_stack_t *info = rs6000_stack_info ();
27026 machine_mode reg_mode = Pmode;
27027 int reg_size = TARGET_32BIT ? 4 : 8;
27028 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
27030 int fp_reg_size = 8;
27031 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27032 rtx frame_reg_rtx = sp_reg_rtx;
27033 unsigned int cr_save_regno;
27034 rtx cr_save_rtx = NULL_RTX;
27037 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
27038 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
27039 && call_used_regs[STATIC_CHAIN_REGNUM]);
27040 int using_split_stack = (flag_split_stack
27041 && (lookup_attribute ("no_split_stack",
27042 DECL_ATTRIBUTES (cfun->decl))
27045 /* Offset to top of frame for frame_reg and sp respectively. */
27046 HOST_WIDE_INT frame_off = 0;
27047 HOST_WIDE_INT sp_off = 0;
27048 /* sp_adjust is the stack adjusting instruction, tracked so that the
27049 insn setting up the split-stack arg pointer can be emitted just
27050 prior to it, when r12 is not used here for other purposes. */
27051 rtx_insn *sp_adjust = 0;
27054 /* Track and check usage of r0, r11, r12. */
27055 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
27056 #define START_USE(R) do \
27058 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27059 reg_inuse |= 1 << (R); \
27061 #define END_USE(R) do \
27063 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27064 reg_inuse &= ~(1 << (R)); \
27066 #define NOT_INUSE(R) do \
27068 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27071 #define START_USE(R) do {} while (0)
27072 #define END_USE(R) do {} while (0)
27073 #define NOT_INUSE(R) do {} while (0)
27076 if (DEFAULT_ABI == ABI_ELFv2
27077 && !TARGET_SINGLE_PIC_BASE)
27079 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
27081 /* With -mminimal-toc we may generate an extra use of r2 below. */
27082 if (TARGET_TOC && TARGET_MINIMAL_TOC
27083 && !constant_pool_empty_p ())
27084 cfun->machine->r2_setup_needed = true;
27088 if (flag_stack_usage_info)
27089 current_function_static_stack_size = info->total_size;
27091 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
27093 HOST_WIDE_INT size = info->total_size;
27095 if (crtl->is_leaf && !cfun->calls_alloca)
27097 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
27098 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27099 size - get_stack_check_protect ());
27102 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
27105 if (TARGET_FIX_AND_CONTINUE)
27107 /* gdb on darwin arranges to forward a function from the old
27108 address by modifying the first 5 instructions of the function
27109 to branch to the overriding function. This is necessary to
27110 permit function pointers that point to the old function to
27111 actually forward to the new function. */
27112 emit_insn (gen_nop ());
27113 emit_insn (gen_nop ());
27114 emit_insn (gen_nop ());
27115 emit_insn (gen_nop ());
27116 emit_insn (gen_nop ());
27119 /* Handle world saves specially here. */
27120 if (WORLD_SAVE_P (info))
27127 /* save_world expects lr in r0. */
27128 reg0 = gen_rtx_REG (Pmode, 0);
27129 if (info->lr_save_p)
27131 insn = emit_move_insn (reg0,
27132 gen_rtx_REG (Pmode, LR_REGNO));
27133 RTX_FRAME_RELATED_P (insn) = 1;
27136 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27137 assumptions about the offsets of various bits of the stack
27139 gcc_assert (info->gp_save_offset == -220
27140 && info->fp_save_offset == -144
27141 && info->lr_save_offset == 8
27142 && info->cr_save_offset == 4
27145 && (!crtl->calls_eh_return
27146 || info->ehrd_offset == -432)
27147 && info->vrsave_save_offset == -224
27148 && info->altivec_save_offset == -416);
27150 treg = gen_rtx_REG (SImode, 11);
27151 emit_move_insn (treg, GEN_INT (-info->total_size));
27153 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27154 in R11. It also clobbers R12, so beware! */
27156 /* Preserve CR2 for save_world prologues */
27158 sz += 32 - info->first_gp_reg_save;
27159 sz += 64 - info->first_fp_reg_save;
27160 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
27161 p = rtvec_alloc (sz);
27163 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
27164 gen_rtx_REG (SImode,
27166 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
27167 gen_rtx_SYMBOL_REF (Pmode,
27169 /* We do floats first so that the instruction pattern matches
27171 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
27173 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
27175 info->first_fp_reg_save + i),
27177 info->fp_save_offset + frame_off + 8 * i);
27178 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27180 = gen_frame_store (gen_rtx_REG (V4SImode,
27181 info->first_altivec_reg_save + i),
27183 info->altivec_save_offset + frame_off + 16 * i);
27184 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27186 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27188 info->gp_save_offset + frame_off + reg_size * i);
27190 /* CR register traditionally saved as CR2. */
27192 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
27193 frame_reg_rtx, info->cr_save_offset + frame_off);
27194 /* Explain about use of R0. */
27195 if (info->lr_save_p)
27197 = gen_frame_store (reg0,
27198 frame_reg_rtx, info->lr_save_offset + frame_off);
27199 /* Explain what happens to the stack pointer. */
27201 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
27202 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
27205 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27206 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27207 treg, GEN_INT (-info->total_size));
27208 sp_off = frame_off = info->total_size;
27211 strategy = info->savres_strategy;
27213 /* For V.4, update stack before we do any saving and set back pointer. */
27214 if (! WORLD_SAVE_P (info)
27216 && (DEFAULT_ABI == ABI_V4
27217 || crtl->calls_eh_return))
27219 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
27220 || !(strategy & SAVE_INLINE_GPRS)
27221 || !(strategy & SAVE_INLINE_VRS));
27222 int ptr_regno = -1;
27223 rtx ptr_reg = NULL_RTX;
27226 if (info->total_size < 32767)
27227 frame_off = info->total_size;
27230 else if (info->cr_save_p
27232 || info->first_fp_reg_save < 64
27233 || info->first_gp_reg_save < 32
27234 || info->altivec_size != 0
27235 || info->vrsave_size != 0
27236 || crtl->calls_eh_return)
27240 /* The prologue won't be saving any regs so there is no need
27241 to set up a frame register to access any frame save area.
27242 We also won't be using frame_off anywhere below, but set
27243 the correct value anyway to protect against future
27244 changes to this function. */
27245 frame_off = info->total_size;
27247 if (ptr_regno != -1)
27249 /* Set up the frame offset to that needed by the first
27250 out-of-line save function. */
27251 START_USE (ptr_regno);
27252 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27253 frame_reg_rtx = ptr_reg;
27254 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
27255 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
27256 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
27257 ptr_off = info->gp_save_offset + info->gp_size;
27258 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
27259 ptr_off = info->altivec_save_offset + info->altivec_size;
27260 frame_off = -ptr_off;
27262 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27264 if (REGNO (frame_reg_rtx) == 12)
27266 sp_off = info->total_size;
27267 if (frame_reg_rtx != sp_reg_rtx)
27268 rs6000_emit_stack_tie (frame_reg_rtx, false);
27271 /* If we use the link register, get it into r0. */
27272 if (!WORLD_SAVE_P (info) && info->lr_save_p
27273 && !cfun->machine->lr_is_wrapped_separately)
27275 rtx addr, reg, mem;
27277 reg = gen_rtx_REG (Pmode, 0);
27279 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
27280 RTX_FRAME_RELATED_P (insn) = 1;
27282 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
27283 | SAVE_NOINLINE_FPRS_SAVES_LR)))
27285 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27286 GEN_INT (info->lr_save_offset + frame_off));
27287 mem = gen_rtx_MEM (Pmode, addr);
27288 /* This should not be of rs6000_sr_alias_set, because of
27289 __builtin_return_address. */
27291 insn = emit_move_insn (mem, reg);
27292 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27293 NULL_RTX, NULL_RTX);
27298 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27299 r12 will be needed by out-of-line gpr restore. */
27300 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27301 && !(strategy & (SAVE_INLINE_GPRS
27302 | SAVE_NOINLINE_GPRS_SAVES_LR))
27304 if (!WORLD_SAVE_P (info)
27306 && REGNO (frame_reg_rtx) != cr_save_regno
27307 && !(using_static_chain_p && cr_save_regno == 11)
27308 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27310 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27311 START_USE (cr_save_regno);
27312 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27315 /* Do any required saving of fpr's. If only one or two to save, do
27316 it ourselves. Otherwise, call function. */
27317 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27319 int offset = info->fp_save_offset + frame_off;
27320 for (int i = info->first_fp_reg_save; i < 64; i++)
27323 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27324 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27325 sp_off - frame_off);
27327 offset += fp_reg_size;
27330 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27332 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27333 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27334 unsigned ptr_regno = ptr_regno_for_savres (sel);
27335 rtx ptr_reg = frame_reg_rtx;
27337 if (REGNO (frame_reg_rtx) == ptr_regno)
27338 gcc_checking_assert (frame_off == 0);
27341 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27342 NOT_INUSE (ptr_regno);
27343 emit_insn (gen_add3_insn (ptr_reg,
27344 frame_reg_rtx, GEN_INT (frame_off)));
27346 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27347 info->fp_save_offset,
27348 info->lr_save_offset,
27350 rs6000_frame_related (insn, ptr_reg, sp_off,
27351 NULL_RTX, NULL_RTX);
27356 /* Save GPRs. This is done as a PARALLEL if we are using
27357 the store-multiple instructions. */
27358 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27360 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27361 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27362 unsigned ptr_regno = ptr_regno_for_savres (sel);
27363 rtx ptr_reg = frame_reg_rtx;
27364 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27365 int end_save = info->gp_save_offset + info->gp_size;
27368 if (ptr_regno == 12)
27371 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27373 /* Need to adjust r11 (r12) if we saved any FPRs. */
27374 if (end_save + frame_off != 0)
27376 rtx offset = GEN_INT (end_save + frame_off);
27379 frame_off = -end_save;
27381 NOT_INUSE (ptr_regno);
27382 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27384 else if (!ptr_set_up)
27386 NOT_INUSE (ptr_regno);
27387 emit_move_insn (ptr_reg, frame_reg_rtx);
27389 ptr_off = -end_save;
27390 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27391 info->gp_save_offset + ptr_off,
27392 info->lr_save_offset + ptr_off,
27394 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27395 NULL_RTX, NULL_RTX);
27399 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27403 p = rtvec_alloc (32 - info->first_gp_reg_save);
27404 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27406 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27408 info->gp_save_offset + frame_off + reg_size * i);
27409 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27410 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27411 NULL_RTX, NULL_RTX);
27413 else if (!WORLD_SAVE_P (info))
27415 int offset = info->gp_save_offset + frame_off;
27416 for (int i = info->first_gp_reg_save; i < 32; i++)
27419 && !cfun->machine->gpr_is_wrapped_separately[i])
27420 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27421 sp_off - frame_off);
27423 offset += reg_size;
27427 if (crtl->calls_eh_return)
27434 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27435 if (regno == INVALID_REGNUM)
27439 p = rtvec_alloc (i);
27443 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27444 if (regno == INVALID_REGNUM)
27448 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27450 info->ehrd_offset + sp_off + reg_size * (int) i);
27451 RTVEC_ELT (p, i) = set;
27452 RTX_FRAME_RELATED_P (set) = 1;
27455 insn = emit_insn (gen_blockage ());
27456 RTX_FRAME_RELATED_P (insn) = 1;
27457 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27460 /* In AIX ABI we need to make sure r2 is really saved. */
27461 if (TARGET_AIX && crtl->calls_eh_return)
27463 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27464 rtx join_insn, note;
27465 rtx_insn *save_insn;
27466 long toc_restore_insn;
27468 tmp_reg = gen_rtx_REG (Pmode, 11);
27469 tmp_reg_si = gen_rtx_REG (SImode, 11);
27470 if (using_static_chain_p)
27473 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27477 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27478 /* Peek at instruction to which this function returns. If it's
27479 restoring r2, then we know we've already saved r2. We can't
27480 unconditionally save r2 because the value we have will already
27481 be updated if we arrived at this function via a plt call or
27482 toc adjusting stub. */
27483 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27484 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27485 + RS6000_TOC_SAVE_SLOT);
27486 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27487 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27488 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27489 validate_condition_mode (EQ, CCUNSmode);
27490 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27491 emit_insn (gen_rtx_SET (compare_result,
27492 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27493 toc_save_done = gen_label_rtx ();
27494 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27495 gen_rtx_EQ (VOIDmode, compare_result,
27497 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27499 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27500 JUMP_LABEL (jump) = toc_save_done;
27501 LABEL_NUSES (toc_save_done) += 1;
27503 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27504 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27505 sp_off - frame_off);
27507 emit_label (toc_save_done);
27509 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27510 have a CFG that has different saves along different paths.
27511 Move the note to a dummy blockage insn, which describes that
27512 R2 is unconditionally saved after the label. */
27513 /* ??? An alternate representation might be a special insn pattern
27514 containing both the branch and the store. That might let the
27515 code that minimizes the number of DW_CFA_advance opcodes better
27516 freedom in placing the annotations. */
27517 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27519 remove_note (save_insn, note);
27521 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27522 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27523 RTX_FRAME_RELATED_P (save_insn) = 0;
27525 join_insn = emit_insn (gen_blockage ());
27526 REG_NOTES (join_insn) = note;
27527 RTX_FRAME_RELATED_P (join_insn) = 1;
27529 if (using_static_chain_p)
27531 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27538 /* Save CR if we use any that must be preserved. */
27539 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27541 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27542 GEN_INT (info->cr_save_offset + frame_off));
27543 rtx mem = gen_frame_mem (SImode, addr);
27545 /* If we didn't copy cr before, do so now using r0. */
27546 if (cr_save_rtx == NULL_RTX)
27549 cr_save_rtx = gen_rtx_REG (SImode, 0);
27550 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27553 /* Saving CR requires a two-instruction sequence: one instruction
27554 to move the CR to a general-purpose register, and a second
27555 instruction that stores the GPR to memory.
27557 We do not emit any DWARF CFI records for the first of these,
27558 because we cannot properly represent the fact that CR is saved in
27559 a register. One reason is that we cannot express that multiple
27560 CR fields are saved; another reason is that on 64-bit, the size
27561 of the CR register in DWARF (4 bytes) differs from the size of
27562 a general-purpose register.
27564 This means if any intervening instruction were to clobber one of
27565 the call-saved CR fields, we'd have incorrect CFI. To prevent
27566 this from happening, we mark the store to memory as a use of
27567 those CR fields, which prevents any such instruction from being
27568 scheduled in between the two instructions. */
27573 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27574 for (i = 0; i < 8; i++)
27575 if (save_reg_p (CR0_REGNO + i))
27576 crsave_v[n_crsave++]
27577 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27579 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27580 gen_rtvec_v (n_crsave, crsave_v)));
27581 END_USE (REGNO (cr_save_rtx));
27583 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27584 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27585 so we need to construct a frame expression manually. */
27586 RTX_FRAME_RELATED_P (insn) = 1;
27588 /* Update address to be stack-pointer relative, like
27589 rs6000_frame_related would do. */
27590 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27591 GEN_INT (info->cr_save_offset + sp_off));
27592 mem = gen_frame_mem (SImode, addr);
27594 if (DEFAULT_ABI == ABI_ELFv2)
27596 /* In the ELFv2 ABI we generate separate CFI records for each
27597 CR field that was actually saved. They all point to the
27598 same 32-bit stack slot. */
27602 for (i = 0; i < 8; i++)
27603 if (save_reg_p (CR0_REGNO + i))
27606 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27608 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27612 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27613 gen_rtx_PARALLEL (VOIDmode,
27614 gen_rtvec_v (n_crframe, crframe)));
27618 /* In other ABIs, by convention, we use a single CR regnum to
27619 represent the fact that all call-saved CR fields are saved.
27620 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27621 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27622 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27626 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27627 *separate* slots if the routine calls __builtin_eh_return, so
27628 that they can be independently restored by the unwinder. */
27629 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27631 int i, cr_off = info->ehcr_offset;
27634 /* ??? We might get better performance by using multiple mfocrf
27636 crsave = gen_rtx_REG (SImode, 0);
27637 emit_insn (gen_prologue_movesi_from_cr (crsave));
27639 for (i = 0; i < 8; i++)
27640 if (!call_used_regs[CR0_REGNO + i])
27642 rtvec p = rtvec_alloc (2);
27644 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27646 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27648 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27650 RTX_FRAME_RELATED_P (insn) = 1;
27651 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27652 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27653 sp_reg_rtx, cr_off + sp_off));
27655 cr_off += reg_size;
27659 /* If we are emitting stack probes, but allocate no stack, then
27660 just note that in the dump file. */
27661 if (flag_stack_clash_protection
27664 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27666 /* Update stack and set back pointer unless this is V.4,
27667 for which it was done previously. */
27668 if (!WORLD_SAVE_P (info) && info->push_p
27669 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27671 rtx ptr_reg = NULL;
27674 /* If saving altivec regs we need to be able to address all save
27675 locations using a 16-bit offset. */
27676 if ((strategy & SAVE_INLINE_VRS) == 0
27677 || (info->altivec_size != 0
27678 && (info->altivec_save_offset + info->altivec_size - 16
27679 + info->total_size - frame_off) > 32767)
27680 || (info->vrsave_size != 0
27681 && (info->vrsave_save_offset
27682 + info->total_size - frame_off) > 32767))
27684 int sel = SAVRES_SAVE | SAVRES_VR;
27685 unsigned ptr_regno = ptr_regno_for_savres (sel);
27687 if (using_static_chain_p
27688 && ptr_regno == STATIC_CHAIN_REGNUM)
27690 if (REGNO (frame_reg_rtx) != ptr_regno)
27691 START_USE (ptr_regno);
27692 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27693 frame_reg_rtx = ptr_reg;
27694 ptr_off = info->altivec_save_offset + info->altivec_size;
27695 frame_off = -ptr_off;
27697 else if (REGNO (frame_reg_rtx) == 1)
27698 frame_off = info->total_size;
27699 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27701 if (REGNO (frame_reg_rtx) == 12)
27703 sp_off = info->total_size;
27704 if (frame_reg_rtx != sp_reg_rtx)
27705 rs6000_emit_stack_tie (frame_reg_rtx, false);
27708 /* Set frame pointer, if needed. */
27709 if (frame_pointer_needed)
27711 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27713 RTX_FRAME_RELATED_P (insn) = 1;
27716 /* Save AltiVec registers if needed. Save here because the red zone does
27717 not always include AltiVec registers. */
27718 if (!WORLD_SAVE_P (info)
27719 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27721 int end_save = info->altivec_save_offset + info->altivec_size;
27723 /* Oddly, the vector save/restore functions point r0 at the end
27724 of the save area, then use r11 or r12 to load offsets for
27725 [reg+reg] addressing. */
27726 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27727 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27728 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27730 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27732 if (scratch_regno == 12)
27734 if (end_save + frame_off != 0)
27736 rtx offset = GEN_INT (end_save + frame_off);
27738 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27741 emit_move_insn (ptr_reg, frame_reg_rtx);
27743 ptr_off = -end_save;
27744 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27745 info->altivec_save_offset + ptr_off,
27746 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27747 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27748 NULL_RTX, NULL_RTX);
27749 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27751 /* The oddity mentioned above clobbered our frame reg. */
27752 emit_move_insn (frame_reg_rtx, ptr_reg);
27753 frame_off = ptr_off;
27756 else if (!WORLD_SAVE_P (info)
27757 && info->altivec_size != 0)
27761 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27762 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27764 rtx areg, savereg, mem;
27765 HOST_WIDE_INT offset;
27767 offset = (info->altivec_save_offset + frame_off
27768 + 16 * (i - info->first_altivec_reg_save));
27770 savereg = gen_rtx_REG (V4SImode, i);
27772 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27774 mem = gen_frame_mem (V4SImode,
27775 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27776 GEN_INT (offset)));
27777 insn = emit_insn (gen_rtx_SET (mem, savereg));
27783 areg = gen_rtx_REG (Pmode, 0);
27784 emit_move_insn (areg, GEN_INT (offset));
27786 /* AltiVec addressing mode is [reg+reg]. */
27787 mem = gen_frame_mem (V4SImode,
27788 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27790 /* Rather than emitting a generic move, force use of the stvx
27791 instruction, which we always want on ISA 2.07 (power8) systems.
27792 In particular we don't want xxpermdi/stxvd2x for little
27794 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27797 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27798 areg, GEN_INT (offset));
27802 /* VRSAVE is a bit vector representing which AltiVec registers
27803 are used. The OS uses this to determine which vector
27804 registers to save on a context switch. We need to save
27805 VRSAVE on the stack frame, add whatever AltiVec registers we
27806 used in this function, and do the corresponding magic in the
27809 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27811 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27812 be using r12 as frame_reg_rtx and r11 as the static chain
27813 pointer for nested functions. */
27814 int save_regno = 12;
27815 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27816 && !using_static_chain_p)
27818 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27821 if (using_static_chain_p)
27824 NOT_INUSE (save_regno);
27826 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27829 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27830 if (!TARGET_SINGLE_PIC_BASE
27831 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27832 && !constant_pool_empty_p ())
27833 || (DEFAULT_ABI == ABI_V4
27834 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27835 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27837 /* If emit_load_toc_table will use the link register, we need to save
27838 it. We use R12 for this purpose because emit_load_toc_table
27839 can use register 0. This allows us to use a plain 'blr' to return
27840 from the procedure more often. */
27841 int save_LR_around_toc_setup = (TARGET_ELF
27842 && DEFAULT_ABI == ABI_V4
27844 && ! info->lr_save_p
27845 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27846 if (save_LR_around_toc_setup)
27848 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27849 rtx tmp = gen_rtx_REG (Pmode, 12);
27852 insn = emit_move_insn (tmp, lr);
27853 RTX_FRAME_RELATED_P (insn) = 1;
27855 rs6000_emit_load_toc_table (TRUE);
27857 insn = emit_move_insn (lr, tmp);
27858 add_reg_note (insn, REG_CFA_RESTORE, lr);
27859 RTX_FRAME_RELATED_P (insn) = 1;
27862 rs6000_emit_load_toc_table (TRUE);
27866 if (!TARGET_SINGLE_PIC_BASE
27867 && DEFAULT_ABI == ABI_DARWIN
27868 && flag_pic && crtl->uses_pic_offset_table)
27870 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27871 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27873 /* Save and restore LR locally around this call (in R0). */
27874 if (!info->lr_save_p)
27875 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27877 emit_insn (gen_load_macho_picbase (src));
27879 emit_move_insn (gen_rtx_REG (Pmode,
27880 RS6000_PIC_OFFSET_TABLE_REGNUM),
27883 if (!info->lr_save_p)
27884 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27888 /* If we need to, save the TOC register after doing the stack setup.
27889 Do not emit eh frame info for this save. The unwinder wants info,
27890 conceptually attached to instructions in this function, about
27891 register values in the caller of this function. This R2 may have
27892 already been changed from the value in the caller.
27893 We don't attempt to write accurate DWARF EH frame info for R2
27894 because code emitted by gcc for a (non-pointer) function call
27895 doesn't save and restore R2. Instead, R2 is managed out-of-line
27896 by a linker generated plt call stub when the function resides in
27897 a shared library. This behavior is costly to describe in DWARF,
27898 both in terms of the size of DWARF info and the time taken in the
27899 unwinder to interpret it. R2 changes, apart from the
27900 calls_eh_return case earlier in this function, are handled by
27901 linux-unwind.h frob_update_context. */
27902 if (rs6000_save_toc_in_prologue_p ()
27903 && !cfun->machine->toc_is_wrapped_separately)
27905 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27906 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27909 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27910 if (using_split_stack && split_stack_arg_pointer_used_p ())
27911 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27914 /* Output .extern statements for the save/restore routines we use. */
27917 rs6000_output_savres_externs (FILE *file)
27919 rs6000_stack_t *info = rs6000_stack_info ();
27921 if (TARGET_DEBUG_STACK)
27922 debug_stack_info (info);
27924 /* Write .extern for any function we will call to save and restore
27926 if (info->first_fp_reg_save < 64
27931 int regno = info->first_fp_reg_save - 32;
27933 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27935 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27936 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27937 name = rs6000_savres_routine_name (regno, sel);
27938 fprintf (file, "\t.extern %s\n", name);
27940 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27942 bool lr = (info->savres_strategy
27943 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27944 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27945 name = rs6000_savres_routine_name (regno, sel);
27946 fprintf (file, "\t.extern %s\n", name);
27951 /* Write function prologue. */
27954 rs6000_output_function_prologue (FILE *file)
27956 if (!cfun->is_thunk)
27957 rs6000_output_savres_externs (file);
27959 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27960 immediately after the global entry point label. */
27961 if (rs6000_global_entry_point_needed_p ())
27963 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27965 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27967 if (TARGET_CMODEL != CMODEL_LARGE)
27969 /* In the small and medium code models, we assume the TOC is less
27970 2 GB away from the text section, so it can be computed via the
27971 following two-instruction sequence. */
27974 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27975 fprintf (file, "0:\taddis 2,12,.TOC.-");
27976 assemble_name (file, buf);
27977 fprintf (file, "@ha\n");
27978 fprintf (file, "\taddi 2,2,.TOC.-");
27979 assemble_name (file, buf);
27980 fprintf (file, "@l\n");
27984 /* In the large code model, we allow arbitrary offsets between the
27985 TOC and the text section, so we have to load the offset from
27986 memory. The data field is emitted directly before the global
27987 entry point in rs6000_elf_declare_function_name. */
27990 #ifdef HAVE_AS_ENTRY_MARKERS
27991 /* If supported by the linker, emit a marker relocation. If the
27992 total code size of the final executable or shared library
27993 happens to fit into 2 GB after all, the linker will replace
27994 this code sequence with the sequence for the small or medium
27996 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27998 fprintf (file, "\tld 2,");
27999 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
28000 assemble_name (file, buf);
28001 fprintf (file, "-");
28002 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28003 assemble_name (file, buf);
28004 fprintf (file, "(12)\n");
28005 fprintf (file, "\tadd 2,2,12\n");
28008 fputs ("\t.localentry\t", file);
28009 assemble_name (file, name);
28010 fputs (",.-", file);
28011 assemble_name (file, name);
28012 fputs ("\n", file);
28015 /* Output -mprofile-kernel code. This needs to be done here instead of
28016 in output_function_profile since it must go after the ELFv2 ABI
28017 local entry point. */
28018 if (TARGET_PROFILE_KERNEL && crtl->profile)
28020 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
28021 gcc_assert (!TARGET_32BIT);
28023 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
28025 /* In the ELFv2 ABI we have no compiler stack word. It must be
28026 the resposibility of _mcount to preserve the static chain
28027 register if required. */
28028 if (DEFAULT_ABI != ABI_ELFv2
28029 && cfun->static_chain_decl != NULL)
28031 asm_fprintf (file, "\tstd %s,24(%s)\n",
28032 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28033 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28034 asm_fprintf (file, "\tld %s,24(%s)\n",
28035 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28038 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28041 rs6000_pic_labelno++;
28044 /* -mprofile-kernel code calls mcount before the function prolog,
28045 so a profiled leaf function should stay a leaf function. */
28047 rs6000_keep_leaf_when_profiled ()
28049 return TARGET_PROFILE_KERNEL;
28052 /* Non-zero if vmx regs are restored before the frame pop, zero if
28053 we restore after the pop when possible. */
28054 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28056 /* Restoring cr is a two step process: loading a reg from the frame
28057 save, then moving the reg to cr. For ABI_V4 we must let the
28058 unwinder know that the stack location is no longer valid at or
28059 before the stack deallocation, but we can't emit a cfa_restore for
28060 cr at the stack deallocation like we do for other registers.
28061 The trouble is that it is possible for the move to cr to be
28062 scheduled after the stack deallocation. So say exactly where cr
28063 is located on each of the two insns. */
28066 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
28068 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
28069 rtx reg = gen_rtx_REG (SImode, regno);
28070 rtx_insn *insn = emit_move_insn (reg, mem);
28072 if (!exit_func && DEFAULT_ABI == ABI_V4)
28074 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28075 rtx set = gen_rtx_SET (reg, cr);
28077 add_reg_note (insn, REG_CFA_REGISTER, set);
28078 RTX_FRAME_RELATED_P (insn) = 1;
28083 /* Reload CR from REG. */
28086 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
28091 if (using_mfcr_multiple)
28093 for (i = 0; i < 8; i++)
28094 if (save_reg_p (CR0_REGNO + i))
28096 gcc_assert (count);
28099 if (using_mfcr_multiple && count > 1)
28105 p = rtvec_alloc (count);
28108 for (i = 0; i < 8; i++)
28109 if (save_reg_p (CR0_REGNO + i))
28111 rtvec r = rtvec_alloc (2);
28112 RTVEC_ELT (r, 0) = reg;
28113 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
28114 RTVEC_ELT (p, ndx) =
28115 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
28116 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
28119 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28120 gcc_assert (ndx == count);
28122 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28123 CR field separately. */
28124 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28126 for (i = 0; i < 8; i++)
28127 if (save_reg_p (CR0_REGNO + i))
28128 add_reg_note (insn, REG_CFA_RESTORE,
28129 gen_rtx_REG (SImode, CR0_REGNO + i));
28131 RTX_FRAME_RELATED_P (insn) = 1;
28135 for (i = 0; i < 8; i++)
28136 if (save_reg_p (CR0_REGNO + i))
28138 rtx insn = emit_insn (gen_movsi_to_cr_one
28139 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28141 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28142 CR field separately, attached to the insn that in fact
28143 restores this particular CR field. */
28144 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28146 add_reg_note (insn, REG_CFA_RESTORE,
28147 gen_rtx_REG (SImode, CR0_REGNO + i));
28149 RTX_FRAME_RELATED_P (insn) = 1;
28153 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28154 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
28155 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
28157 rtx_insn *insn = get_last_insn ();
28158 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28160 add_reg_note (insn, REG_CFA_RESTORE, cr);
28161 RTX_FRAME_RELATED_P (insn) = 1;
28165 /* Like cr, the move to lr instruction can be scheduled after the
28166 stack deallocation, but unlike cr, its stack frame save is still
28167 valid. So we only need to emit the cfa_restore on the correct
28171 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
28173 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
28174 rtx reg = gen_rtx_REG (Pmode, regno);
28176 emit_move_insn (reg, mem);
28180 restore_saved_lr (int regno, bool exit_func)
28182 rtx reg = gen_rtx_REG (Pmode, regno);
28183 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
28184 rtx_insn *insn = emit_move_insn (lr, reg);
28186 if (!exit_func && flag_shrink_wrap)
28188 add_reg_note (insn, REG_CFA_RESTORE, lr);
28189 RTX_FRAME_RELATED_P (insn) = 1;
28194 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
28196 if (DEFAULT_ABI == ABI_ELFv2)
28199 for (i = 0; i < 8; i++)
28200 if (save_reg_p (CR0_REGNO + i))
28202 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
28203 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
28207 else if (info->cr_save_p)
28208 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28209 gen_rtx_REG (SImode, CR2_REGNO),
28212 if (info->lr_save_p)
28213 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28214 gen_rtx_REG (Pmode, LR_REGNO),
28216 return cfa_restores;
28219 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28220 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28221 below stack pointer not cloberred by signals. */
28224 offset_below_red_zone_p (HOST_WIDE_INT offset)
28226 return offset < (DEFAULT_ABI == ABI_V4
28228 : TARGET_32BIT ? -220 : -288);
28231 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28234 emit_cfa_restores (rtx cfa_restores)
28236 rtx_insn *insn = get_last_insn ();
28237 rtx *loc = ®_NOTES (insn);
28240 loc = &XEXP (*loc, 1);
28241 *loc = cfa_restores;
28242 RTX_FRAME_RELATED_P (insn) = 1;
28245 /* Emit function epilogue as insns. */
28248 rs6000_emit_epilogue (int sibcall)
28250 rs6000_stack_t *info;
28251 int restoring_GPRs_inline;
28252 int restoring_FPRs_inline;
28253 int using_load_multiple;
28254 int using_mtcr_multiple;
28255 int use_backchain_to_restore_sp;
28258 HOST_WIDE_INT frame_off = 0;
28259 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
28260 rtx frame_reg_rtx = sp_reg_rtx;
28261 rtx cfa_restores = NULL_RTX;
28263 rtx cr_save_reg = NULL_RTX;
28264 machine_mode reg_mode = Pmode;
28265 int reg_size = TARGET_32BIT ? 4 : 8;
28266 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
28268 int fp_reg_size = 8;
28271 unsigned ptr_regno;
28273 info = rs6000_stack_info ();
28275 strategy = info->savres_strategy;
28276 using_load_multiple = strategy & REST_MULTIPLE;
28277 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
28278 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
28279 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
28280 || rs6000_tune == PROCESSOR_PPC603
28281 || rs6000_tune == PROCESSOR_PPC750
28283 /* Restore via the backchain when we have a large frame, since this
28284 is more efficient than an addis, addi pair. The second condition
28285 here will not trigger at the moment; We don't actually need a
28286 frame pointer for alloca, but the generic parts of the compiler
28287 give us one anyway. */
28288 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
28289 ? info->lr_save_offset
28291 || (cfun->calls_alloca
28292 && !frame_pointer_needed));
28293 restore_lr = (info->lr_save_p
28294 && (restoring_FPRs_inline
28295 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28296 && (restoring_GPRs_inline
28297 || info->first_fp_reg_save < 64)
28298 && !cfun->machine->lr_is_wrapped_separately);
28301 if (WORLD_SAVE_P (info))
28305 const char *alloc_rname;
28308 /* eh_rest_world_r10 will return to the location saved in the LR
28309 stack slot (which is not likely to be our caller.)
28310 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28311 rest_world is similar, except any R10 parameter is ignored.
28312 The exception-handling stuff that was here in 2.95 is no
28313 longer necessary. */
28316 + 32 - info->first_gp_reg_save
28317 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28318 + 63 + 1 - info->first_fp_reg_save);
28320 strcpy (rname, ((crtl->calls_eh_return) ?
28321 "*eh_rest_world_r10" : "*rest_world"));
28322 alloc_rname = ggc_strdup (rname);
28325 RTVEC_ELT (p, j++) = ret_rtx;
28327 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
28328 /* The instruction pattern requires a clobber here;
28329 it is shared with the restVEC helper. */
28331 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
28334 /* CR register traditionally saved as CR2. */
28335 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28337 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28338 if (flag_shrink_wrap)
28340 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28341 gen_rtx_REG (Pmode, LR_REGNO),
28343 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28347 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28349 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28351 = gen_frame_load (reg,
28352 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28353 if (flag_shrink_wrap
28354 && save_reg_p (info->first_gp_reg_save + i))
28355 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28357 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28359 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28361 = gen_frame_load (reg,
28362 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28363 if (flag_shrink_wrap
28364 && save_reg_p (info->first_altivec_reg_save + i))
28365 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28367 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28369 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
28370 ? DFmode : SFmode),
28371 info->first_fp_reg_save + i);
28373 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28374 if (flag_shrink_wrap
28375 && save_reg_p (info->first_fp_reg_save + i))
28376 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28379 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
28381 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
28383 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
28385 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
28387 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28388 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28390 if (flag_shrink_wrap)
28392 REG_NOTES (insn) = cfa_restores;
28393 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28394 RTX_FRAME_RELATED_P (insn) = 1;
28399 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28401 frame_off = info->total_size;
28403 /* Restore AltiVec registers if we must do so before adjusting the
28405 if (info->altivec_size != 0
28406 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28407 || (DEFAULT_ABI != ABI_V4
28408 && offset_below_red_zone_p (info->altivec_save_offset))))
28411 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28413 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28414 if (use_backchain_to_restore_sp)
28416 int frame_regno = 11;
28418 if ((strategy & REST_INLINE_VRS) == 0)
28420 /* Of r11 and r12, select the one not clobbered by an
28421 out-of-line restore function for the frame register. */
28422 frame_regno = 11 + 12 - scratch_regno;
28424 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28425 emit_move_insn (frame_reg_rtx,
28426 gen_rtx_MEM (Pmode, sp_reg_rtx));
28429 else if (frame_pointer_needed)
28430 frame_reg_rtx = hard_frame_pointer_rtx;
28432 if ((strategy & REST_INLINE_VRS) == 0)
28434 int end_save = info->altivec_save_offset + info->altivec_size;
28436 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28437 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28439 if (end_save + frame_off != 0)
28441 rtx offset = GEN_INT (end_save + frame_off);
28443 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28446 emit_move_insn (ptr_reg, frame_reg_rtx);
28448 ptr_off = -end_save;
28449 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28450 info->altivec_save_offset + ptr_off,
28451 0, V4SImode, SAVRES_VR);
28455 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28456 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28458 rtx addr, areg, mem, insn;
28459 rtx reg = gen_rtx_REG (V4SImode, i);
28460 HOST_WIDE_INT offset
28461 = (info->altivec_save_offset + frame_off
28462 + 16 * (i - info->first_altivec_reg_save));
28464 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28466 mem = gen_frame_mem (V4SImode,
28467 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28468 GEN_INT (offset)));
28469 insn = gen_rtx_SET (reg, mem);
28473 areg = gen_rtx_REG (Pmode, 0);
28474 emit_move_insn (areg, GEN_INT (offset));
28476 /* AltiVec addressing mode is [reg+reg]. */
28477 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28478 mem = gen_frame_mem (V4SImode, addr);
28480 /* Rather than emitting a generic move, force use of the
28481 lvx instruction, which we always want. In particular we
28482 don't want lxvd2x/xxpermdi for little endian. */
28483 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28486 (void) emit_insn (insn);
28490 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28491 if (((strategy & REST_INLINE_VRS) == 0
28492 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28493 && (flag_shrink_wrap
28494 || (offset_below_red_zone_p
28495 (info->altivec_save_offset
28496 + 16 * (i - info->first_altivec_reg_save))))
28499 rtx reg = gen_rtx_REG (V4SImode, i);
28500 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28504 /* Restore VRSAVE if we must do so before adjusting the stack. */
28505 if (info->vrsave_size != 0
28506 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28507 || (DEFAULT_ABI != ABI_V4
28508 && offset_below_red_zone_p (info->vrsave_save_offset))))
28512 if (frame_reg_rtx == sp_reg_rtx)
28514 if (use_backchain_to_restore_sp)
28516 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28517 emit_move_insn (frame_reg_rtx,
28518 gen_rtx_MEM (Pmode, sp_reg_rtx));
28521 else if (frame_pointer_needed)
28522 frame_reg_rtx = hard_frame_pointer_rtx;
28525 reg = gen_rtx_REG (SImode, 12);
28526 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28527 info->vrsave_save_offset + frame_off));
28529 emit_insn (generate_set_vrsave (reg, info, 1));
28533 /* If we have a large stack frame, restore the old stack pointer
28534 using the backchain. */
28535 if (use_backchain_to_restore_sp)
28537 if (frame_reg_rtx == sp_reg_rtx)
28539 /* Under V.4, don't reset the stack pointer until after we're done
28540 loading the saved registers. */
28541 if (DEFAULT_ABI == ABI_V4)
28542 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28544 insn = emit_move_insn (frame_reg_rtx,
28545 gen_rtx_MEM (Pmode, sp_reg_rtx));
28548 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28549 && DEFAULT_ABI == ABI_V4)
28550 /* frame_reg_rtx has been set up by the altivec restore. */
28554 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28555 frame_reg_rtx = sp_reg_rtx;
28558 /* If we have a frame pointer, we can restore the old stack pointer
28560 else if (frame_pointer_needed)
28562 frame_reg_rtx = sp_reg_rtx;
28563 if (DEFAULT_ABI == ABI_V4)
28564 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28565 /* Prevent reordering memory accesses against stack pointer restore. */
28566 else if (cfun->calls_alloca
28567 || offset_below_red_zone_p (-info->total_size))
28568 rs6000_emit_stack_tie (frame_reg_rtx, true);
28570 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28571 GEN_INT (info->total_size)));
28574 else if (info->push_p
28575 && DEFAULT_ABI != ABI_V4
28576 && !crtl->calls_eh_return)
28578 /* Prevent reordering memory accesses against stack pointer restore. */
28579 if (cfun->calls_alloca
28580 || offset_below_red_zone_p (-info->total_size))
28581 rs6000_emit_stack_tie (frame_reg_rtx, false);
28582 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28583 GEN_INT (info->total_size)));
28586 if (insn && frame_reg_rtx == sp_reg_rtx)
28590 REG_NOTES (insn) = cfa_restores;
28591 cfa_restores = NULL_RTX;
28593 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28594 RTX_FRAME_RELATED_P (insn) = 1;
28597 /* Restore AltiVec registers if we have not done so already. */
28598 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28599 && info->altivec_size != 0
28600 && (DEFAULT_ABI == ABI_V4
28601 || !offset_below_red_zone_p (info->altivec_save_offset)))
28605 if ((strategy & REST_INLINE_VRS) == 0)
28607 int end_save = info->altivec_save_offset + info->altivec_size;
28609 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28610 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28611 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28613 if (end_save + frame_off != 0)
28615 rtx offset = GEN_INT (end_save + frame_off);
28617 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28620 emit_move_insn (ptr_reg, frame_reg_rtx);
28622 ptr_off = -end_save;
28623 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28624 info->altivec_save_offset + ptr_off,
28625 0, V4SImode, SAVRES_VR);
28626 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28628 /* Frame reg was clobbered by out-of-line save. Restore it
28629 from ptr_reg, and if we are calling out-of-line gpr or
28630 fpr restore set up the correct pointer and offset. */
28631 unsigned newptr_regno = 1;
28632 if (!restoring_GPRs_inline)
28634 bool lr = info->gp_save_offset + info->gp_size == 0;
28635 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28636 newptr_regno = ptr_regno_for_savres (sel);
28637 end_save = info->gp_save_offset + info->gp_size;
28639 else if (!restoring_FPRs_inline)
28641 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28642 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28643 newptr_regno = ptr_regno_for_savres (sel);
28644 end_save = info->fp_save_offset + info->fp_size;
28647 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28648 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28650 if (end_save + ptr_off != 0)
28652 rtx offset = GEN_INT (end_save + ptr_off);
28654 frame_off = -end_save;
28656 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28659 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28664 frame_off = ptr_off;
28665 emit_move_insn (frame_reg_rtx, ptr_reg);
28671 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28672 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28674 rtx addr, areg, mem, insn;
28675 rtx reg = gen_rtx_REG (V4SImode, i);
28676 HOST_WIDE_INT offset
28677 = (info->altivec_save_offset + frame_off
28678 + 16 * (i - info->first_altivec_reg_save));
28680 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28682 mem = gen_frame_mem (V4SImode,
28683 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28684 GEN_INT (offset)));
28685 insn = gen_rtx_SET (reg, mem);
28689 areg = gen_rtx_REG (Pmode, 0);
28690 emit_move_insn (areg, GEN_INT (offset));
28692 /* AltiVec addressing mode is [reg+reg]. */
28693 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28694 mem = gen_frame_mem (V4SImode, addr);
28696 /* Rather than emitting a generic move, force use of the
28697 lvx instruction, which we always want. In particular we
28698 don't want lxvd2x/xxpermdi for little endian. */
28699 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28702 (void) emit_insn (insn);
28706 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28707 if (((strategy & REST_INLINE_VRS) == 0
28708 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28709 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28712 rtx reg = gen_rtx_REG (V4SImode, i);
28713 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28717 /* Restore VRSAVE if we have not done so already. */
28718 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28719 && info->vrsave_size != 0
28720 && (DEFAULT_ABI == ABI_V4
28721 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28725 reg = gen_rtx_REG (SImode, 12);
28726 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28727 info->vrsave_save_offset + frame_off));
28729 emit_insn (generate_set_vrsave (reg, info, 1));
28732 /* If we exit by an out-of-line restore function on ABI_V4 then that
28733 function will deallocate the stack, so we don't need to worry
28734 about the unwinder restoring cr from an invalid stack frame
28736 exit_func = (!restoring_FPRs_inline
28737 || (!restoring_GPRs_inline
28738 && info->first_fp_reg_save == 64));
28740 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28741 *separate* slots if the routine calls __builtin_eh_return, so
28742 that they can be independently restored by the unwinder. */
28743 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28745 int i, cr_off = info->ehcr_offset;
28747 for (i = 0; i < 8; i++)
28748 if (!call_used_regs[CR0_REGNO + i])
28750 rtx reg = gen_rtx_REG (SImode, 0);
28751 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28752 cr_off + frame_off));
28754 insn = emit_insn (gen_movsi_to_cr_one
28755 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28757 if (!exit_func && flag_shrink_wrap)
28759 add_reg_note (insn, REG_CFA_RESTORE,
28760 gen_rtx_REG (SImode, CR0_REGNO + i));
28762 RTX_FRAME_RELATED_P (insn) = 1;
28765 cr_off += reg_size;
28769 /* Get the old lr if we saved it. If we are restoring registers
28770 out-of-line, then the out-of-line routines can do this for us. */
28771 if (restore_lr && restoring_GPRs_inline)
28772 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28774 /* Get the old cr if we saved it. */
28775 if (info->cr_save_p)
28777 unsigned cr_save_regno = 12;
28779 if (!restoring_GPRs_inline)
28781 /* Ensure we don't use the register used by the out-of-line
28782 gpr register restore below. */
28783 bool lr = info->gp_save_offset + info->gp_size == 0;
28784 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28785 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28787 if (gpr_ptr_regno == 12)
28788 cr_save_regno = 11;
28789 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28791 else if (REGNO (frame_reg_rtx) == 12)
28792 cr_save_regno = 11;
28794 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28795 info->cr_save_offset + frame_off,
28799 /* Set LR here to try to overlap restores below. */
28800 if (restore_lr && restoring_GPRs_inline)
28801 restore_saved_lr (0, exit_func);
28803 /* Load exception handler data registers, if needed. */
28804 if (crtl->calls_eh_return)
28806 unsigned int i, regno;
28810 rtx reg = gen_rtx_REG (reg_mode, 2);
28811 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28812 frame_off + RS6000_TOC_SAVE_SLOT));
28819 regno = EH_RETURN_DATA_REGNO (i);
28820 if (regno == INVALID_REGNUM)
28823 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28824 info->ehrd_offset + frame_off
28825 + reg_size * (int) i);
28827 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28831 /* Restore GPRs. This is done as a PARALLEL if we are using
28832 the load-multiple instructions. */
28833 if (!restoring_GPRs_inline)
28835 /* We are jumping to an out-of-line function. */
28837 int end_save = info->gp_save_offset + info->gp_size;
28838 bool can_use_exit = end_save == 0;
28839 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28842 /* Emit stack reset code if we need it. */
28843 ptr_regno = ptr_regno_for_savres (sel);
28844 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28846 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28847 else if (end_save + frame_off != 0)
28848 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28849 GEN_INT (end_save + frame_off)));
28850 else if (REGNO (frame_reg_rtx) != ptr_regno)
28851 emit_move_insn (ptr_reg, frame_reg_rtx);
28852 if (REGNO (frame_reg_rtx) == ptr_regno)
28853 frame_off = -end_save;
28855 if (can_use_exit && info->cr_save_p)
28856 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28858 ptr_off = -end_save;
28859 rs6000_emit_savres_rtx (info, ptr_reg,
28860 info->gp_save_offset + ptr_off,
28861 info->lr_save_offset + ptr_off,
28864 else if (using_load_multiple)
28867 p = rtvec_alloc (32 - info->first_gp_reg_save);
28868 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28870 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28872 info->gp_save_offset + frame_off + reg_size * i);
28873 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28877 int offset = info->gp_save_offset + frame_off;
28878 for (i = info->first_gp_reg_save; i < 32; i++)
28881 && !cfun->machine->gpr_is_wrapped_separately[i])
28883 rtx reg = gen_rtx_REG (reg_mode, i);
28884 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28887 offset += reg_size;
28891 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28893 /* If the frame pointer was used then we can't delay emitting
28894 a REG_CFA_DEF_CFA note. This must happen on the insn that
28895 restores the frame pointer, r31. We may have already emitted
28896 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28897 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28898 be harmless if emitted. */
28899 if (frame_pointer_needed)
28901 insn = get_last_insn ();
28902 add_reg_note (insn, REG_CFA_DEF_CFA,
28903 plus_constant (Pmode, frame_reg_rtx, frame_off));
28904 RTX_FRAME_RELATED_P (insn) = 1;
28907 /* Set up cfa_restores. We always need these when
28908 shrink-wrapping. If not shrink-wrapping then we only need
28909 the cfa_restore when the stack location is no longer valid.
28910 The cfa_restores must be emitted on or before the insn that
28911 invalidates the stack, and of course must not be emitted
28912 before the insn that actually does the restore. The latter
28913 is why it is a bad idea to emit the cfa_restores as a group
28914 on the last instruction here that actually does a restore:
28915 That insn may be reordered with respect to others doing
28917 if (flag_shrink_wrap
28918 && !restoring_GPRs_inline
28919 && info->first_fp_reg_save == 64)
28920 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28922 for (i = info->first_gp_reg_save; i < 32; i++)
28924 && !cfun->machine->gpr_is_wrapped_separately[i])
28926 rtx reg = gen_rtx_REG (reg_mode, i);
28927 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28931 if (!restoring_GPRs_inline
28932 && info->first_fp_reg_save == 64)
28934 /* We are jumping to an out-of-line function. */
28936 emit_cfa_restores (cfa_restores);
28940 if (restore_lr && !restoring_GPRs_inline)
28942 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28943 restore_saved_lr (0, exit_func);
28946 /* Restore fpr's if we need to do it without calling a function. */
28947 if (restoring_FPRs_inline)
28949 int offset = info->fp_save_offset + frame_off;
28950 for (i = info->first_fp_reg_save; i < 64; i++)
28953 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28955 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28956 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28957 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28958 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28962 offset += fp_reg_size;
28966 /* If we saved cr, restore it here. Just those that were used. */
28967 if (info->cr_save_p)
28968 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28970 /* If this is V.4, unwind the stack pointer after all of the loads
28971 have been done, or set up r11 if we are restoring fp out of line. */
28973 if (!restoring_FPRs_inline)
28975 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28976 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28977 ptr_regno = ptr_regno_for_savres (sel);
28980 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28981 if (REGNO (frame_reg_rtx) == ptr_regno)
28984 if (insn && restoring_FPRs_inline)
28988 REG_NOTES (insn) = cfa_restores;
28989 cfa_restores = NULL_RTX;
28991 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28992 RTX_FRAME_RELATED_P (insn) = 1;
28995 if (crtl->calls_eh_return)
28997 rtx sa = EH_RETURN_STACKADJ_RTX;
28998 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
29001 if (!sibcall && restoring_FPRs_inline)
29005 /* We can't hang the cfa_restores off a simple return,
29006 since the shrink-wrap code sometimes uses an existing
29007 return. This means there might be a path from
29008 pre-prologue code to this return, and dwarf2cfi code
29009 wants the eh_frame unwinder state to be the same on
29010 all paths to any point. So we need to emit the
29011 cfa_restores before the return. For -m64 we really
29012 don't need epilogue cfa_restores at all, except for
29013 this irritating dwarf2cfi with shrink-wrap
29014 requirement; The stack red-zone means eh_frame info
29015 from the prologue telling the unwinder to restore
29016 from the stack is perfectly good right to the end of
29018 emit_insn (gen_blockage ());
29019 emit_cfa_restores (cfa_restores);
29020 cfa_restores = NULL_RTX;
29023 emit_jump_insn (targetm.gen_simple_return ());
29026 if (!sibcall && !restoring_FPRs_inline)
29028 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29029 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
29031 RTVEC_ELT (p, elt++) = ret_rtx;
29033 RTVEC_ELT (p, elt++)
29034 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
29036 /* We have to restore more than two FP registers, so branch to the
29037 restore function. It will return to our caller. */
29042 if (flag_shrink_wrap)
29043 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29045 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
29046 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
29047 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
29048 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
29050 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
29052 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
29054 RTVEC_ELT (p, elt++)
29055 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
29056 if (flag_shrink_wrap
29057 && save_reg_p (info->first_fp_reg_save + i))
29058 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29061 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
29067 /* Ensure the cfa_restores are hung off an insn that won't
29068 be reordered above other restores. */
29069 emit_insn (gen_blockage ());
29071 emit_cfa_restores (cfa_restores);
29075 /* Write function epilogue. */
29078 rs6000_output_function_epilogue (FILE *file)
29081 macho_branch_islands ();
29084 rtx_insn *insn = get_last_insn ();
29085 rtx_insn *deleted_debug_label = NULL;
29087 /* Mach-O doesn't support labels at the end of objects, so if
29088 it looks like we might want one, take special action.
29090 First, collect any sequence of deleted debug labels. */
29093 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
29095 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29096 notes only, instead set their CODE_LABEL_NUMBER to -1,
29097 otherwise there would be code generation differences
29098 in between -g and -g0. */
29099 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29100 deleted_debug_label = insn;
29101 insn = PREV_INSN (insn);
29104 /* Second, if we have:
29107 then this needs to be detected, so skip past the barrier. */
29109 if (insn && BARRIER_P (insn))
29110 insn = PREV_INSN (insn);
29112 /* Up to now we've only seen notes or barriers. */
29117 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
29118 /* Trailing label: <barrier>. */
29119 fputs ("\tnop\n", file);
29122 /* Lastly, see if we have a completely empty function body. */
29123 while (insn && ! INSN_P (insn))
29124 insn = PREV_INSN (insn);
29125 /* If we don't find any insns, we've got an empty function body;
29126 I.e. completely empty - without a return or branch. This is
29127 taken as the case where a function body has been removed
29128 because it contains an inline __builtin_unreachable(). GCC
29129 states that reaching __builtin_unreachable() means UB so we're
29130 not obliged to do anything special; however, we want
29131 non-zero-sized function bodies. To meet this, and help the
29132 user out, let's trap the case. */
29134 fputs ("\ttrap\n", file);
29137 else if (deleted_debug_label)
29138 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
29139 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29140 CODE_LABEL_NUMBER (insn) = -1;
29144 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29147 We don't output a traceback table if -finhibit-size-directive was
29148 used. The documentation for -finhibit-size-directive reads
29149 ``don't output a @code{.size} assembler directive, or anything
29150 else that would cause trouble if the function is split in the
29151 middle, and the two halves are placed at locations far apart in
29152 memory.'' The traceback table has this property, since it
29153 includes the offset from the start of the function to the
29154 traceback table itself.
29156 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29157 different traceback table. */
29158 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29159 && ! flag_inhibit_size_directive
29160 && rs6000_traceback != traceback_none && !cfun->is_thunk)
29162 const char *fname = NULL;
29163 const char *language_string = lang_hooks.name;
29164 int fixed_parms = 0, float_parms = 0, parm_info = 0;
29166 int optional_tbtab;
29167 rs6000_stack_t *info = rs6000_stack_info ();
29169 if (rs6000_traceback == traceback_full)
29170 optional_tbtab = 1;
29171 else if (rs6000_traceback == traceback_part)
29172 optional_tbtab = 0;
29174 optional_tbtab = !optimize_size && !TARGET_ELF;
29176 if (optional_tbtab)
29178 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
29179 while (*fname == '.') /* V.4 encodes . in the name */
29182 /* Need label immediately before tbtab, so we can compute
29183 its offset from the function start. */
29184 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29185 ASM_OUTPUT_LABEL (file, fname);
29188 /* The .tbtab pseudo-op can only be used for the first eight
29189 expressions, since it can't handle the possibly variable
29190 length fields that follow. However, if you omit the optional
29191 fields, the assembler outputs zeros for all optional fields
29192 anyways, giving each variable length field is minimum length
29193 (as defined in sys/debug.h). Thus we can not use the .tbtab
29194 pseudo-op at all. */
29196 /* An all-zero word flags the start of the tbtab, for debuggers
29197 that have to find it by searching forward from the entry
29198 point or from the current pc. */
29199 fputs ("\t.long 0\n", file);
29201 /* Tbtab format type. Use format type 0. */
29202 fputs ("\t.byte 0,", file);
29204 /* Language type. Unfortunately, there does not seem to be any
29205 official way to discover the language being compiled, so we
29206 use language_string.
29207 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
29208 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29209 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
29210 either, so for now use 0. */
29212 || ! strcmp (language_string, "GNU GIMPLE")
29213 || ! strcmp (language_string, "GNU Go")
29214 || ! strcmp (language_string, "libgccjit"))
29216 else if (! strcmp (language_string, "GNU F77")
29217 || lang_GNU_Fortran ())
29219 else if (! strcmp (language_string, "GNU Pascal"))
29221 else if (! strcmp (language_string, "GNU Ada"))
29223 else if (lang_GNU_CXX ()
29224 || ! strcmp (language_string, "GNU Objective-C++"))
29226 else if (! strcmp (language_string, "GNU Java"))
29228 else if (! strcmp (language_string, "GNU Objective-C"))
29231 gcc_unreachable ();
29232 fprintf (file, "%d,", i);
29234 /* 8 single bit fields: global linkage (not set for C extern linkage,
29235 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29236 from start of procedure stored in tbtab, internal function, function
29237 has controlled storage, function has no toc, function uses fp,
29238 function logs/aborts fp operations. */
29239 /* Assume that fp operations are used if any fp reg must be saved. */
29240 fprintf (file, "%d,",
29241 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
29243 /* 6 bitfields: function is interrupt handler, name present in
29244 proc table, function calls alloca, on condition directives
29245 (controls stack walks, 3 bits), saves condition reg, saves
29247 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29248 set up as a frame pointer, even when there is no alloca call. */
29249 fprintf (file, "%d,",
29250 ((optional_tbtab << 6)
29251 | ((optional_tbtab & frame_pointer_needed) << 5)
29252 | (info->cr_save_p << 1)
29253 | (info->lr_save_p)));
29255 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29257 fprintf (file, "%d,",
29258 (info->push_p << 7) | (64 - info->first_fp_reg_save));
29260 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29261 fprintf (file, "%d,", (32 - first_reg_to_save ()));
29263 if (optional_tbtab)
29265 /* Compute the parameter info from the function decl argument
29268 int next_parm_info_bit = 31;
29270 for (decl = DECL_ARGUMENTS (current_function_decl);
29271 decl; decl = DECL_CHAIN (decl))
29273 rtx parameter = DECL_INCOMING_RTL (decl);
29274 machine_mode mode = GET_MODE (parameter);
29276 if (GET_CODE (parameter) == REG)
29278 if (SCALAR_FLOAT_MODE_P (mode))
29301 gcc_unreachable ();
29304 /* If only one bit will fit, don't or in this entry. */
29305 if (next_parm_info_bit > 0)
29306 parm_info |= (bits << (next_parm_info_bit - 1));
29307 next_parm_info_bit -= 2;
29311 fixed_parms += ((GET_MODE_SIZE (mode)
29312 + (UNITS_PER_WORD - 1))
29314 next_parm_info_bit -= 1;
29320 /* Number of fixed point parameters. */
29321 /* This is actually the number of words of fixed point parameters; thus
29322 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29323 fprintf (file, "%d,", fixed_parms);
29325 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29327 /* This is actually the number of fp registers that hold parameters;
29328 and thus the maximum value is 13. */
29329 /* Set parameters on stack bit if parameters are not in their original
29330 registers, regardless of whether they are on the stack? Xlc
29331 seems to set the bit when not optimizing. */
29332 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29334 if (optional_tbtab)
29336 /* Optional fields follow. Some are variable length. */
29338 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29339 float, 11 double float. */
29340 /* There is an entry for each parameter in a register, in the order
29341 that they occur in the parameter list. Any intervening arguments
29342 on the stack are ignored. If the list overflows a long (max
29343 possible length 34 bits) then completely leave off all elements
29345 /* Only emit this long if there was at least one parameter. */
29346 if (fixed_parms || float_parms)
29347 fprintf (file, "\t.long %d\n", parm_info);
29349 /* Offset from start of code to tb table. */
29350 fputs ("\t.long ", file);
29351 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29352 RS6000_OUTPUT_BASENAME (file, fname);
29354 rs6000_output_function_entry (file, fname);
29357 /* Interrupt handler mask. */
29358 /* Omit this long, since we never set the interrupt handler bit
29361 /* Number of CTL (controlled storage) anchors. */
29362 /* Omit this long, since the has_ctl bit is never set above. */
29364 /* Displacement into stack of each CTL anchor. */
29365 /* Omit this list of longs, because there are no CTL anchors. */
29367 /* Length of function name. */
29370 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29372 /* Function name. */
29373 assemble_string (fname, strlen (fname));
29375 /* Register for alloca automatic storage; this is always reg 31.
29376 Only emit this if the alloca bit was set above. */
29377 if (frame_pointer_needed)
29378 fputs ("\t.byte 31\n", file);
29380 fputs ("\t.align 2\n", file);
29384 /* Arrange to define .LCTOC1 label, if not already done. */
29388 if (!toc_initialized)
29390 switch_to_section (toc_section);
29391 switch_to_section (current_function_section ());
29396 /* -fsplit-stack support. */
29398 /* A SYMBOL_REF for __morestack. */
29399 static GTY(()) rtx morestack_ref;
29402 gen_add3_const (rtx rt, rtx ra, long c)
29405 return gen_adddi3 (rt, ra, GEN_INT (c));
29407 return gen_addsi3 (rt, ra, GEN_INT (c));
29410 /* Emit -fsplit-stack prologue, which goes before the regular function
29411 prologue (at local entry point in the case of ELFv2). */
29414 rs6000_expand_split_stack_prologue (void)
29416 rs6000_stack_t *info = rs6000_stack_info ();
29417 unsigned HOST_WIDE_INT allocate;
29418 long alloc_hi, alloc_lo;
29419 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29422 gcc_assert (flag_split_stack && reload_completed);
29427 if (global_regs[29])
29429 error ("%qs uses register r29", "-fsplit-stack");
29430 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29431 "conflicts with %qD", global_regs_decl[29]);
29434 allocate = info->total_size;
29435 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29437 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29440 if (morestack_ref == NULL_RTX)
29442 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29443 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29444 | SYMBOL_FLAG_FUNCTION);
29447 r0 = gen_rtx_REG (Pmode, 0);
29448 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29449 r12 = gen_rtx_REG (Pmode, 12);
29450 emit_insn (gen_load_split_stack_limit (r0));
29451 /* Always emit two insns here to calculate the requested stack,
29452 so that the linker can edit them when adjusting size for calling
29453 non-split-stack code. */
29454 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29455 alloc_lo = -allocate - alloc_hi;
29458 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29460 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29462 emit_insn (gen_nop ());
29466 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29467 emit_insn (gen_nop ());
29470 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29471 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29472 ok_label = gen_label_rtx ();
29473 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29474 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29475 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29477 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29478 JUMP_LABEL (insn) = ok_label;
29479 /* Mark the jump as very likely to be taken. */
29480 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29482 lr = gen_rtx_REG (Pmode, LR_REGNO);
29483 insn = emit_move_insn (r0, lr);
29484 RTX_FRAME_RELATED_P (insn) = 1;
29485 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29486 RTX_FRAME_RELATED_P (insn) = 1;
29488 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29489 const0_rtx, const0_rtx));
29490 call_fusage = NULL_RTX;
29491 use_reg (&call_fusage, r12);
29492 /* Say the call uses r0, even though it doesn't, to stop regrename
29493 from twiddling with the insns saving lr, trashing args for cfun.
29494 The insns restoring lr are similarly protected by making
29495 split_stack_return use r0. */
29496 use_reg (&call_fusage, r0);
29497 add_function_usage_to (insn, call_fusage);
29498 /* Indicate that this function can't jump to non-local gotos. */
29499 make_reg_eh_region_note_nothrow_nononlocal (insn);
29500 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29501 insn = emit_move_insn (lr, r0);
29502 add_reg_note (insn, REG_CFA_RESTORE, lr);
29503 RTX_FRAME_RELATED_P (insn) = 1;
29504 emit_insn (gen_split_stack_return ());
29506 emit_label (ok_label);
29507 LABEL_NUSES (ok_label) = 1;
29510 /* Return the internal arg pointer used for function incoming
29511 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29512 to copy it to a pseudo in order for it to be preserved over calls
29513 and suchlike. We'd really like to use a pseudo here for the
29514 internal arg pointer but data-flow analysis is not prepared to
29515 accept pseudos as live at the beginning of a function. */
29518 rs6000_internal_arg_pointer (void)
29520 if (flag_split_stack
29521 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29525 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29529 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29530 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29532 /* Put the pseudo initialization right after the note at the
29533 beginning of the function. */
29534 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29535 gen_rtx_REG (Pmode, 12));
29536 push_topmost_sequence ();
29537 emit_insn_after (pat, get_insns ());
29538 pop_topmost_sequence ();
29540 return plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29541 FIRST_PARM_OFFSET (current_function_decl));
29543 return virtual_incoming_args_rtx;
29546 /* We may have to tell the dataflow pass that the split stack prologue
29547 is initializing a register. */
29550 rs6000_live_on_entry (bitmap regs)
29552 if (flag_split_stack)
29553 bitmap_set_bit (regs, 12);
29556 /* Emit -fsplit-stack dynamic stack allocation space check. */
29559 rs6000_split_stack_space_check (rtx size, rtx label)
29561 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29562 rtx limit = gen_reg_rtx (Pmode);
29563 rtx requested = gen_reg_rtx (Pmode);
29564 rtx cmp = gen_reg_rtx (CCUNSmode);
29567 emit_insn (gen_load_split_stack_limit (limit));
29568 if (CONST_INT_P (size))
29569 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29572 size = force_reg (Pmode, size);
29573 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29575 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29576 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29577 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29578 gen_rtx_LABEL_REF (VOIDmode, label),
29580 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29581 JUMP_LABEL (jump) = label;
29584 /* A C compound statement that outputs the assembler code for a thunk
29585 function, used to implement C++ virtual function calls with
29586 multiple inheritance. The thunk acts as a wrapper around a virtual
29587 function, adjusting the implicit object parameter before handing
29588 control off to the real function.
29590 First, emit code to add the integer DELTA to the location that
29591 contains the incoming first argument. Assume that this argument
29592 contains a pointer, and is the one used to pass the `this' pointer
29593 in C++. This is the incoming argument *before* the function
29594 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29595 values of all other incoming arguments.
29597 After the addition, emit code to jump to FUNCTION, which is a
29598 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29599 not touch the return address. Hence returning from FUNCTION will
29600 return to whoever called the current `thunk'.
29602 The effect must be as if FUNCTION had been called directly with the
29603 adjusted first argument. This macro is responsible for emitting
29604 all of the code for a thunk function; output_function_prologue()
29605 and output_function_epilogue() are not invoked.
29607 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29608 been extracted from it.) It might possibly be useful on some
29609 targets, but probably not.
29611 If you do not define this macro, the target-independent code in the
29612 C++ frontend will generate a less efficient heavyweight thunk that
29613 calls FUNCTION instead of jumping to it. The generic approach does
29614 not support varargs. */
29617 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29618 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29621 rtx this_rtx, funexp;
29624 reload_completed = 1;
29625 epilogue_completed = 1;
29627 /* Mark the end of the (empty) prologue. */
29628 emit_note (NOTE_INSN_PROLOGUE_END);
29630 /* Find the "this" pointer. If the function returns a structure,
29631 the structure return pointer is in r3. */
29632 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29633 this_rtx = gen_rtx_REG (Pmode, 4);
29635 this_rtx = gen_rtx_REG (Pmode, 3);
29637 /* Apply the constant offset, if required. */
29639 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29641 /* Apply the offset from the vtable, if required. */
29644 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29645 rtx tmp = gen_rtx_REG (Pmode, 12);
29647 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29648 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29650 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29651 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29655 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29657 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29659 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29662 /* Generate a tail call to the target function. */
29663 if (!TREE_USED (function))
29665 assemble_external (function);
29666 TREE_USED (function) = 1;
29668 funexp = XEXP (DECL_RTL (function), 0);
29669 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29672 if (MACHOPIC_INDIRECT)
29673 funexp = machopic_indirect_call_target (funexp);
29676 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29677 generate sibcall RTL explicitly. */
29678 insn = emit_call_insn (
29679 gen_rtx_PARALLEL (VOIDmode,
29681 gen_rtx_CALL (VOIDmode,
29682 funexp, const0_rtx),
29683 gen_rtx_USE (VOIDmode, const0_rtx),
29684 simple_return_rtx)));
29685 SIBLING_CALL_P (insn) = 1;
29688 /* Run just enough of rest_of_compilation to get the insns emitted.
29689 There's not really enough bulk here to make other passes such as
29690 instruction scheduling worth while. Note that use_thunk calls
29691 assemble_start_function and assemble_end_function. */
29692 insn = get_insns ();
29693 shorten_branches (insn);
29694 final_start_function (insn, file, 1);
29695 final (insn, file, 1);
29696 final_end_function ();
29698 reload_completed = 0;
29699 epilogue_completed = 0;
29702 /* A quick summary of the various types of 'constant-pool tables'
29705 Target Flags Name One table per
29706 AIX (none) AIX TOC object file
29707 AIX -mfull-toc AIX TOC object file
29708 AIX -mminimal-toc AIX minimal TOC translation unit
29709 SVR4/EABI (none) SVR4 SDATA object file
29710 SVR4/EABI -fpic SVR4 pic object file
29711 SVR4/EABI -fPIC SVR4 PIC translation unit
29712 SVR4/EABI -mrelocatable EABI TOC function
29713 SVR4/EABI -maix AIX TOC object file
29714 SVR4/EABI -maix -mminimal-toc
29715 AIX minimal TOC translation unit
29717 Name Reg. Set by entries contains:
29718 made by addrs? fp? sum?
29720 AIX TOC 2 crt0 as Y option option
29721 AIX minimal TOC 30 prolog gcc Y Y option
29722 SVR4 SDATA 13 crt0 gcc N Y N
29723 SVR4 pic 30 prolog ld Y not yet N
29724 SVR4 PIC 30 prolog gcc Y option option
29725 EABI TOC 30 prolog gcc Y option option
29729 /* Hash functions for the hash table. */
29732 rs6000_hash_constant (rtx k)
29734 enum rtx_code code = GET_CODE (k);
29735 machine_mode mode = GET_MODE (k);
29736 unsigned result = (code << 3) ^ mode;
29737 const char *format;
29740 format = GET_RTX_FORMAT (code);
29741 flen = strlen (format);
29747 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29749 case CONST_WIDE_INT:
29752 flen = CONST_WIDE_INT_NUNITS (k);
29753 for (i = 0; i < flen; i++)
29754 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29759 if (mode != VOIDmode)
29760 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29772 for (; fidx < flen; fidx++)
29773 switch (format[fidx])
29778 const char *str = XSTR (k, fidx);
29779 len = strlen (str);
29780 result = result * 613 + len;
29781 for (i = 0; i < len; i++)
29782 result = result * 613 + (unsigned) str[i];
29787 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29791 result = result * 613 + (unsigned) XINT (k, fidx);
29794 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29795 result = result * 613 + (unsigned) XWINT (k, fidx);
29799 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29800 result = result * 613 + (unsigned) (XWINT (k, fidx)
29807 gcc_unreachable ();
29814 toc_hasher::hash (toc_hash_struct *thc)
29816 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29819 /* Compare H1 and H2 for equivalence. */
29822 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29827 if (h1->key_mode != h2->key_mode)
29830 return rtx_equal_p (r1, r2);
29833 /* These are the names given by the C++ front-end to vtables, and
29834 vtable-like objects. Ideally, this logic should not be here;
29835 instead, there should be some programmatic way of inquiring as
29836 to whether or not an object is a vtable. */
29838 #define VTABLE_NAME_P(NAME) \
29839 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29840 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29841 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29842 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29843 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29845 #ifdef NO_DOLLAR_IN_LABEL
29846 /* Return a GGC-allocated character string translating dollar signs in
29847 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29850 rs6000_xcoff_strip_dollar (const char *name)
29856 q = (const char *) strchr (name, '$');
29858 if (q == 0 || q == name)
29861 len = strlen (name);
29862 strip = XALLOCAVEC (char, len + 1);
29863 strcpy (strip, name);
29864 p = strip + (q - name);
29868 p = strchr (p + 1, '$');
29871 return ggc_alloc_string (strip, len);
29876 rs6000_output_symbol_ref (FILE *file, rtx x)
29878 const char *name = XSTR (x, 0);
29880 /* Currently C++ toc references to vtables can be emitted before it
29881 is decided whether the vtable is public or private. If this is
29882 the case, then the linker will eventually complain that there is
29883 a reference to an unknown section. Thus, for vtables only,
29884 we emit the TOC reference to reference the identifier and not the
29886 if (VTABLE_NAME_P (name))
29888 RS6000_OUTPUT_BASENAME (file, name);
29891 assemble_name (file, name);
29894 /* Output a TOC entry. We derive the entry name from what is being
29898 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29901 const char *name = buf;
29903 HOST_WIDE_INT offset = 0;
29905 gcc_assert (!TARGET_NO_TOC);
29907 /* When the linker won't eliminate them, don't output duplicate
29908 TOC entries (this happens on AIX if there is any kind of TOC,
29909 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29911 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29913 struct toc_hash_struct *h;
29915 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29916 time because GGC is not initialized at that point. */
29917 if (toc_hash_table == NULL)
29918 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29920 h = ggc_alloc<toc_hash_struct> ();
29922 h->key_mode = mode;
29923 h->labelno = labelno;
29925 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29926 if (*found == NULL)
29928 else /* This is indeed a duplicate.
29929 Set this label equal to that label. */
29931 fputs ("\t.set ", file);
29932 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29933 fprintf (file, "%d,", labelno);
29934 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29935 fprintf (file, "%d\n", ((*found)->labelno));
29938 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
29939 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29940 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29942 fputs ("\t.set ", file);
29943 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29944 fprintf (file, "%d,", labelno);
29945 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29946 fprintf (file, "%d\n", ((*found)->labelno));
29953 /* If we're going to put a double constant in the TOC, make sure it's
29954 aligned properly when strict alignment is on. */
29955 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29956 && STRICT_ALIGNMENT
29957 && GET_MODE_BITSIZE (mode) >= 64
29958 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29959 ASM_OUTPUT_ALIGN (file, 3);
29962 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29964 /* Handle FP constants specially. Note that if we have a minimal
29965 TOC, things we put here aren't actually in the TOC, so we can allow
29967 if (GET_CODE (x) == CONST_DOUBLE &&
29968 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29969 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29973 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29974 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29976 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29980 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29981 fputs (DOUBLE_INT_ASM_OP, file);
29983 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29984 k[0] & 0xffffffff, k[1] & 0xffffffff,
29985 k[2] & 0xffffffff, k[3] & 0xffffffff);
29986 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29987 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29988 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29989 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29990 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29995 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29996 fputs ("\t.long ", file);
29998 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29999 k[0] & 0xffffffff, k[1] & 0xffffffff,
30000 k[2] & 0xffffffff, k[3] & 0xffffffff);
30001 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
30002 k[0] & 0xffffffff, k[1] & 0xffffffff,
30003 k[2] & 0xffffffff, k[3] & 0xffffffff);
30007 else if (GET_CODE (x) == CONST_DOUBLE &&
30008 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
30012 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30013 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
30015 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30019 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30020 fputs (DOUBLE_INT_ASM_OP, file);
30022 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30023 k[0] & 0xffffffff, k[1] & 0xffffffff);
30024 fprintf (file, "0x%lx%08lx\n",
30025 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30026 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
30031 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30032 fputs ("\t.long ", file);
30034 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30035 k[0] & 0xffffffff, k[1] & 0xffffffff);
30036 fprintf (file, "0x%lx,0x%lx\n",
30037 k[0] & 0xffffffff, k[1] & 0xffffffff);
30041 else if (GET_CODE (x) == CONST_DOUBLE &&
30042 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
30046 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30047 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
30049 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
30053 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30054 fputs (DOUBLE_INT_ASM_OP, file);
30056 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30057 if (WORDS_BIG_ENDIAN)
30058 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
30060 fprintf (file, "0x%lx\n", l & 0xffffffff);
30065 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30066 fputs ("\t.long ", file);
30068 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30069 fprintf (file, "0x%lx\n", l & 0xffffffff);
30073 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
30075 unsigned HOST_WIDE_INT low;
30076 HOST_WIDE_INT high;
30078 low = INTVAL (x) & 0xffffffff;
30079 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
30081 /* TOC entries are always Pmode-sized, so when big-endian
30082 smaller integer constants in the TOC need to be padded.
30083 (This is still a win over putting the constants in
30084 a separate constant pool, because then we'd have
30085 to have both a TOC entry _and_ the actual constant.)
30087 For a 32-bit target, CONST_INT values are loaded and shifted
30088 entirely within `low' and can be stored in one TOC entry. */
30090 /* It would be easy to make this work, but it doesn't now. */
30091 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
30093 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
30096 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
30097 high = (HOST_WIDE_INT) low >> 32;
30103 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30104 fputs (DOUBLE_INT_ASM_OP, file);
30106 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30107 (long) high & 0xffffffff, (long) low & 0xffffffff);
30108 fprintf (file, "0x%lx%08lx\n",
30109 (long) high & 0xffffffff, (long) low & 0xffffffff);
30114 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
30116 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30117 fputs ("\t.long ", file);
30119 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30120 (long) high & 0xffffffff, (long) low & 0xffffffff);
30121 fprintf (file, "0x%lx,0x%lx\n",
30122 (long) high & 0xffffffff, (long) low & 0xffffffff);
30126 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30127 fputs ("\t.long ", file);
30129 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
30130 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
30136 if (GET_CODE (x) == CONST)
30138 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
30139 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
30141 base = XEXP (XEXP (x, 0), 0);
30142 offset = INTVAL (XEXP (XEXP (x, 0), 1));
30145 switch (GET_CODE (base))
30148 name = XSTR (base, 0);
30152 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
30153 CODE_LABEL_NUMBER (XEXP (base, 0)));
30157 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
30161 gcc_unreachable ();
30164 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30165 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
30168 fputs ("\t.tc ", file);
30169 RS6000_OUTPUT_BASENAME (file, name);
30172 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
30174 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
30176 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30177 after other TOC symbols, reducing overflow of small TOC access
30178 to [TC] symbols. */
30179 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
30180 ? "[TE]," : "[TC],", file);
30183 /* Currently C++ toc references to vtables can be emitted before it
30184 is decided whether the vtable is public or private. If this is
30185 the case, then the linker will eventually complain that there is
30186 a TOC reference to an unknown section. Thus, for vtables only,
30187 we emit the TOC reference to reference the symbol and not the
30189 if (VTABLE_NAME_P (name))
30191 RS6000_OUTPUT_BASENAME (file, name);
30193 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
30194 else if (offset > 0)
30195 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
30198 output_addr_const (file, x);
30201 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
30203 switch (SYMBOL_REF_TLS_MODEL (base))
30207 case TLS_MODEL_LOCAL_EXEC:
30208 fputs ("@le", file);
30210 case TLS_MODEL_INITIAL_EXEC:
30211 fputs ("@ie", file);
30213 /* Use global-dynamic for local-dynamic. */
30214 case TLS_MODEL_GLOBAL_DYNAMIC:
30215 case TLS_MODEL_LOCAL_DYNAMIC:
30217 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
30218 fputs ("\t.tc .", file);
30219 RS6000_OUTPUT_BASENAME (file, name);
30220 fputs ("[TC],", file);
30221 output_addr_const (file, x);
30222 fputs ("@m", file);
30225 gcc_unreachable ();
30233 /* Output an assembler pseudo-op to write an ASCII string of N characters
30234 starting at P to FILE.
30236 On the RS/6000, we have to do this using the .byte operation and
30237 write out special characters outside the quoted string.
30238 Also, the assembler is broken; very long strings are truncated,
30239 so we must artificially break them up early. */
30242 output_ascii (FILE *file, const char *p, int n)
30245 int i, count_string;
30246 const char *for_string = "\t.byte \"";
30247 const char *for_decimal = "\t.byte ";
30248 const char *to_close = NULL;
30251 for (i = 0; i < n; i++)
30254 if (c >= ' ' && c < 0177)
30257 fputs (for_string, file);
30260 /* Write two quotes to get one. */
30268 for_decimal = "\"\n\t.byte ";
30272 if (count_string >= 512)
30274 fputs (to_close, file);
30276 for_string = "\t.byte \"";
30277 for_decimal = "\t.byte ";
30285 fputs (for_decimal, file);
30286 fprintf (file, "%d", c);
30288 for_string = "\n\t.byte \"";
30289 for_decimal = ", ";
30295 /* Now close the string if we have written one. Then end the line. */
30297 fputs (to_close, file);
30300 /* Generate a unique section name for FILENAME for a section type
30301 represented by SECTION_DESC. Output goes into BUF.
30303 SECTION_DESC can be any string, as long as it is different for each
30304 possible section type.
30306 We name the section in the same manner as xlc. The name begins with an
30307 underscore followed by the filename (after stripping any leading directory
30308 names) with the last period replaced by the string SECTION_DESC. If
30309 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30313 rs6000_gen_section_name (char **buf, const char *filename,
30314 const char *section_desc)
30316 const char *q, *after_last_slash, *last_period = 0;
30320 after_last_slash = filename;
30321 for (q = filename; *q; q++)
30324 after_last_slash = q + 1;
30325 else if (*q == '.')
30329 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30330 *buf = (char *) xmalloc (len);
30335 for (q = after_last_slash; *q; q++)
30337 if (q == last_period)
30339 strcpy (p, section_desc);
30340 p += strlen (section_desc);
30344 else if (ISALNUM (*q))
30348 if (last_period == 0)
30349 strcpy (p, section_desc);
30354 /* Emit profile function. */
30357 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30359 /* Non-standard profiling for kernels, which just saves LR then calls
30360 _mcount without worrying about arg saves. The idea is to change
30361 the function prologue as little as possible as it isn't easy to
30362 account for arg save/restore code added just for _mcount. */
30363 if (TARGET_PROFILE_KERNEL)
30366 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30368 #ifndef NO_PROFILE_COUNTERS
30369 # define NO_PROFILE_COUNTERS 0
30371 if (NO_PROFILE_COUNTERS)
30372 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30373 LCT_NORMAL, VOIDmode);
30377 const char *label_name;
30380 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30381 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30382 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30384 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30385 LCT_NORMAL, VOIDmode, fun, Pmode);
30388 else if (DEFAULT_ABI == ABI_DARWIN)
30390 const char *mcount_name = RS6000_MCOUNT;
30391 int caller_addr_regno = LR_REGNO;
30393 /* Be conservative and always set this, at least for now. */
30394 crtl->uses_pic_offset_table = 1;
30397 /* For PIC code, set up a stub and collect the caller's address
30398 from r0, which is where the prologue puts it. */
30399 if (MACHOPIC_INDIRECT
30400 && crtl->uses_pic_offset_table)
30401 caller_addr_regno = 0;
30403 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30404 LCT_NORMAL, VOIDmode,
30405 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30409 /* Write function profiler code. */
30412 output_function_profiler (FILE *file, int labelno)
30416 switch (DEFAULT_ABI)
30419 gcc_unreachable ();
30424 warning (0, "no profiling of 64-bit code for this ABI");
30427 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30428 fprintf (file, "\tmflr %s\n", reg_names[0]);
30429 if (NO_PROFILE_COUNTERS)
30431 asm_fprintf (file, "\tstw %s,4(%s)\n",
30432 reg_names[0], reg_names[1]);
30434 else if (TARGET_SECURE_PLT && flag_pic)
30436 if (TARGET_LINK_STACK)
30439 get_ppc476_thunk_name (name);
30440 asm_fprintf (file, "\tbl %s\n", name);
30443 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30444 asm_fprintf (file, "\tstw %s,4(%s)\n",
30445 reg_names[0], reg_names[1]);
30446 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30447 asm_fprintf (file, "\taddis %s,%s,",
30448 reg_names[12], reg_names[12]);
30449 assemble_name (file, buf);
30450 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30451 assemble_name (file, buf);
30452 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30454 else if (flag_pic == 1)
30456 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30457 asm_fprintf (file, "\tstw %s,4(%s)\n",
30458 reg_names[0], reg_names[1]);
30459 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30460 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30461 assemble_name (file, buf);
30462 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30464 else if (flag_pic > 1)
30466 asm_fprintf (file, "\tstw %s,4(%s)\n",
30467 reg_names[0], reg_names[1]);
30468 /* Now, we need to get the address of the label. */
30469 if (TARGET_LINK_STACK)
30472 get_ppc476_thunk_name (name);
30473 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30474 assemble_name (file, buf);
30475 fputs ("-.\n1:", file);
30476 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30477 asm_fprintf (file, "\taddi %s,%s,4\n",
30478 reg_names[11], reg_names[11]);
30482 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30483 assemble_name (file, buf);
30484 fputs ("-.\n1:", file);
30485 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30487 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30488 reg_names[0], reg_names[11]);
30489 asm_fprintf (file, "\tadd %s,%s,%s\n",
30490 reg_names[0], reg_names[0], reg_names[11]);
30494 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30495 assemble_name (file, buf);
30496 fputs ("@ha\n", file);
30497 asm_fprintf (file, "\tstw %s,4(%s)\n",
30498 reg_names[0], reg_names[1]);
30499 asm_fprintf (file, "\tla %s,", reg_names[0]);
30500 assemble_name (file, buf);
30501 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30504 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30505 fprintf (file, "\tbl %s%s\n",
30506 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30512 /* Don't do anything, done in output_profile_hook (). */
30519 /* The following variable value is the last issued insn. */
30521 static rtx_insn *last_scheduled_insn;
30523 /* The following variable helps to balance issuing of load and
30524 store instructions */
30526 static int load_store_pendulum;
30528 /* The following variable helps pair divide insns during scheduling. */
30529 static int divide_cnt;
30530 /* The following variable helps pair and alternate vector and vector load
30531 insns during scheduling. */
30532 static int vec_pairing;
30535 /* Power4 load update and store update instructions are cracked into a
30536 load or store and an integer insn which are executed in the same cycle.
30537 Branches have their own dispatch slot which does not count against the
30538 GCC issue rate, but it changes the program flow so there are no other
30539 instructions to issue in this cycle. */
30542 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30544 last_scheduled_insn = insn;
30545 if (GET_CODE (PATTERN (insn)) == USE
30546 || GET_CODE (PATTERN (insn)) == CLOBBER)
30548 cached_can_issue_more = more;
30549 return cached_can_issue_more;
30552 if (insn_terminates_group_p (insn, current_group))
30554 cached_can_issue_more = 0;
30555 return cached_can_issue_more;
30558 /* If no reservation, but reach here */
30559 if (recog_memoized (insn) < 0)
30562 if (rs6000_sched_groups)
30564 if (is_microcoded_insn (insn))
30565 cached_can_issue_more = 0;
30566 else if (is_cracked_insn (insn))
30567 cached_can_issue_more = more > 2 ? more - 2 : 0;
30569 cached_can_issue_more = more - 1;
30571 return cached_can_issue_more;
30574 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30577 cached_can_issue_more = more - 1;
30578 return cached_can_issue_more;
30582 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30584 int r = rs6000_variable_issue_1 (insn, more);
30586 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30590 /* Adjust the cost of a scheduling dependency. Return the new cost of
30591 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30594 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30597 enum attr_type attr_type;
30599 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30606 /* Data dependency; DEP_INSN writes a register that INSN reads
30607 some cycles later. */
30609 /* Separate a load from a narrower, dependent store. */
30610 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30611 && GET_CODE (PATTERN (insn)) == SET
30612 && GET_CODE (PATTERN (dep_insn)) == SET
30613 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30614 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30615 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30616 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30619 attr_type = get_attr_type (insn);
30624 /* Tell the first scheduling pass about the latency between
30625 a mtctr and bctr (and mtlr and br/blr). The first
30626 scheduling pass will not know about this latency since
30627 the mtctr instruction, which has the latency associated
30628 to it, will be generated by reload. */
30631 /* Leave some extra cycles between a compare and its
30632 dependent branch, to inhibit expensive mispredicts. */
30633 if ((rs6000_tune == PROCESSOR_PPC603
30634 || rs6000_tune == PROCESSOR_PPC604
30635 || rs6000_tune == PROCESSOR_PPC604e
30636 || rs6000_tune == PROCESSOR_PPC620
30637 || rs6000_tune == PROCESSOR_PPC630
30638 || rs6000_tune == PROCESSOR_PPC750
30639 || rs6000_tune == PROCESSOR_PPC7400
30640 || rs6000_tune == PROCESSOR_PPC7450
30641 || rs6000_tune == PROCESSOR_PPCE5500
30642 || rs6000_tune == PROCESSOR_PPCE6500
30643 || rs6000_tune == PROCESSOR_POWER4
30644 || rs6000_tune == PROCESSOR_POWER5
30645 || rs6000_tune == PROCESSOR_POWER7
30646 || rs6000_tune == PROCESSOR_POWER8
30647 || rs6000_tune == PROCESSOR_POWER9
30648 || rs6000_tune == PROCESSOR_CELL)
30649 && recog_memoized (dep_insn)
30650 && (INSN_CODE (dep_insn) >= 0))
30652 switch (get_attr_type (dep_insn))
30655 case TYPE_FPCOMPARE:
30656 case TYPE_CR_LOGICAL:
30660 if (get_attr_dot (dep_insn) == DOT_YES)
30665 if (get_attr_dot (dep_insn) == DOT_YES
30666 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30677 if ((rs6000_tune == PROCESSOR_POWER6)
30678 && recog_memoized (dep_insn)
30679 && (INSN_CODE (dep_insn) >= 0))
30682 if (GET_CODE (PATTERN (insn)) != SET)
30683 /* If this happens, we have to extend this to schedule
30684 optimally. Return default for now. */
30687 /* Adjust the cost for the case where the value written
30688 by a fixed point operation is used as the address
30689 gen value on a store. */
30690 switch (get_attr_type (dep_insn))
30695 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30696 return get_attr_sign_extend (dep_insn)
30697 == SIGN_EXTEND_YES ? 6 : 4;
30702 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30703 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30713 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30721 if (get_attr_update (dep_insn) == UPDATE_YES
30722 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30728 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30734 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30735 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30745 if ((rs6000_tune == PROCESSOR_POWER6)
30746 && recog_memoized (dep_insn)
30747 && (INSN_CODE (dep_insn) >= 0))
30750 /* Adjust the cost for the case where the value written
30751 by a fixed point instruction is used within the address
30752 gen portion of a subsequent load(u)(x) */
30753 switch (get_attr_type (dep_insn))
30758 if (set_to_load_agen (dep_insn, insn))
30759 return get_attr_sign_extend (dep_insn)
30760 == SIGN_EXTEND_YES ? 6 : 4;
30765 if (set_to_load_agen (dep_insn, insn))
30766 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30776 if (set_to_load_agen (dep_insn, insn))
30784 if (get_attr_update (dep_insn) == UPDATE_YES
30785 && set_to_load_agen (dep_insn, insn))
30791 if (set_to_load_agen (dep_insn, insn))
30797 if (set_to_load_agen (dep_insn, insn))
30798 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30808 if ((rs6000_tune == PROCESSOR_POWER6)
30809 && get_attr_update (insn) == UPDATE_NO
30810 && recog_memoized (dep_insn)
30811 && (INSN_CODE (dep_insn) >= 0)
30812 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30819 /* Fall out to return default cost. */
30823 case REG_DEP_OUTPUT:
30824 /* Output dependency; DEP_INSN writes a register that INSN writes some
30826 if ((rs6000_tune == PROCESSOR_POWER6)
30827 && recog_memoized (dep_insn)
30828 && (INSN_CODE (dep_insn) >= 0))
30830 attr_type = get_attr_type (insn);
30835 case TYPE_FPSIMPLE:
30836 if (get_attr_type (dep_insn) == TYPE_FP
30837 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30841 if (get_attr_update (insn) == UPDATE_NO
30842 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30849 /* Fall through, no cost for output dependency. */
30853 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30858 gcc_unreachable ();
30864 /* Debug version of rs6000_adjust_cost. */
30867 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30868 int cost, unsigned int dw)
30870 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30878 default: dep = "unknown depencency"; break;
30879 case REG_DEP_TRUE: dep = "data dependency"; break;
30880 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30881 case REG_DEP_ANTI: dep = "anti depencency"; break;
30885 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30886 "%s, insn:\n", ret, cost, dep);
30894 /* The function returns a true if INSN is microcoded.
30895 Return false otherwise. */
30898 is_microcoded_insn (rtx_insn *insn)
30900 if (!insn || !NONDEBUG_INSN_P (insn)
30901 || GET_CODE (PATTERN (insn)) == USE
30902 || GET_CODE (PATTERN (insn)) == CLOBBER)
30905 if (rs6000_tune == PROCESSOR_CELL)
30906 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30908 if (rs6000_sched_groups
30909 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30911 enum attr_type type = get_attr_type (insn);
30912 if ((type == TYPE_LOAD
30913 && get_attr_update (insn) == UPDATE_YES
30914 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30915 || ((type == TYPE_LOAD || type == TYPE_STORE)
30916 && get_attr_update (insn) == UPDATE_YES
30917 && get_attr_indexed (insn) == INDEXED_YES)
30918 || type == TYPE_MFCR)
30925 /* The function returns true if INSN is cracked into 2 instructions
30926 by the processor (and therefore occupies 2 issue slots). */
30929 is_cracked_insn (rtx_insn *insn)
30931 if (!insn || !NONDEBUG_INSN_P (insn)
30932 || GET_CODE (PATTERN (insn)) == USE
30933 || GET_CODE (PATTERN (insn)) == CLOBBER)
30936 if (rs6000_sched_groups
30937 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30939 enum attr_type type = get_attr_type (insn);
30940 if ((type == TYPE_LOAD
30941 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30942 && get_attr_update (insn) == UPDATE_NO)
30943 || (type == TYPE_LOAD
30944 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30945 && get_attr_update (insn) == UPDATE_YES
30946 && get_attr_indexed (insn) == INDEXED_NO)
30947 || (type == TYPE_STORE
30948 && get_attr_update (insn) == UPDATE_YES
30949 && get_attr_indexed (insn) == INDEXED_NO)
30950 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30951 && get_attr_update (insn) == UPDATE_YES)
30952 || (type == TYPE_CR_LOGICAL
30953 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30954 || (type == TYPE_EXTS
30955 && get_attr_dot (insn) == DOT_YES)
30956 || (type == TYPE_SHIFT
30957 && get_attr_dot (insn) == DOT_YES
30958 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30959 || (type == TYPE_MUL
30960 && get_attr_dot (insn) == DOT_YES)
30961 || type == TYPE_DIV
30962 || (type == TYPE_INSERT
30963 && get_attr_size (insn) == SIZE_32))
30970 /* The function returns true if INSN can be issued only from
30971 the branch slot. */
30974 is_branch_slot_insn (rtx_insn *insn)
30976 if (!insn || !NONDEBUG_INSN_P (insn)
30977 || GET_CODE (PATTERN (insn)) == USE
30978 || GET_CODE (PATTERN (insn)) == CLOBBER)
30981 if (rs6000_sched_groups)
30983 enum attr_type type = get_attr_type (insn);
30984 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30992 /* The function returns true if out_inst sets a value that is
30993 used in the address generation computation of in_insn */
30995 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30997 rtx out_set, in_set;
30999 /* For performance reasons, only handle the simple case where
31000 both loads are a single_set. */
31001 out_set = single_set (out_insn);
31004 in_set = single_set (in_insn);
31006 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
31012 /* Try to determine base/offset/size parts of the given MEM.
31013 Return true if successful, false if all the values couldn't
31016 This function only looks for REG or REG+CONST address forms.
31017 REG+REG address form will return false. */
31020 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
31021 HOST_WIDE_INT *size)
31024 if MEM_SIZE_KNOWN_P (mem)
31025 *size = MEM_SIZE (mem);
31029 addr_rtx = (XEXP (mem, 0));
31030 if (GET_CODE (addr_rtx) == PRE_MODIFY)
31031 addr_rtx = XEXP (addr_rtx, 1);
31034 while (GET_CODE (addr_rtx) == PLUS
31035 && CONST_INT_P (XEXP (addr_rtx, 1)))
31037 *offset += INTVAL (XEXP (addr_rtx, 1));
31038 addr_rtx = XEXP (addr_rtx, 0);
31040 if (!REG_P (addr_rtx))
31047 /* The function returns true if the target storage location of
31048 mem1 is adjacent to the target storage location of mem2 */
31049 /* Return 1 if memory locations are adjacent. */
31052 adjacent_mem_locations (rtx mem1, rtx mem2)
31055 HOST_WIDE_INT off1, size1, off2, size2;
31057 if (get_memref_parts (mem1, ®1, &off1, &size1)
31058 && get_memref_parts (mem2, ®2, &off2, &size2))
31059 return ((REGNO (reg1) == REGNO (reg2))
31060 && ((off1 + size1 == off2)
31061 || (off2 + size2 == off1)));
31066 /* This function returns true if it can be determined that the two MEM
31067 locations overlap by at least 1 byte based on base reg/offset/size. */
31070 mem_locations_overlap (rtx mem1, rtx mem2)
31073 HOST_WIDE_INT off1, size1, off2, size2;
31075 if (get_memref_parts (mem1, ®1, &off1, &size1)
31076 && get_memref_parts (mem2, ®2, &off2, &size2))
31077 return ((REGNO (reg1) == REGNO (reg2))
31078 && (((off1 <= off2) && (off1 + size1 > off2))
31079 || ((off2 <= off1) && (off2 + size2 > off1))));
31084 /* A C statement (sans semicolon) to update the integer scheduling
31085 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31086 INSN earlier, reduce the priority to execute INSN later. Do not
31087 define this macro if you do not need to adjust the scheduling
31088 priorities of insns. */
31091 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
31093 rtx load_mem, str_mem;
31094 /* On machines (like the 750) which have asymmetric integer units,
31095 where one integer unit can do multiply and divides and the other
31096 can't, reduce the priority of multiply/divide so it is scheduled
31097 before other integer operations. */
31100 if (! INSN_P (insn))
31103 if (GET_CODE (PATTERN (insn)) == USE)
31106 switch (rs6000_tune) {
31107 case PROCESSOR_PPC750:
31108 switch (get_attr_type (insn))
31115 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
31116 priority, priority);
31117 if (priority >= 0 && priority < 0x01000000)
31124 if (insn_must_be_first_in_group (insn)
31125 && reload_completed
31126 && current_sched_info->sched_max_insns_priority
31127 && rs6000_sched_restricted_insns_priority)
31130 /* Prioritize insns that can be dispatched only in the first
31132 if (rs6000_sched_restricted_insns_priority == 1)
31133 /* Attach highest priority to insn. This means that in
31134 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31135 precede 'priority' (critical path) considerations. */
31136 return current_sched_info->sched_max_insns_priority;
31137 else if (rs6000_sched_restricted_insns_priority == 2)
31138 /* Increase priority of insn by a minimal amount. This means that in
31139 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31140 considerations precede dispatch-slot restriction considerations. */
31141 return (priority + 1);
31144 if (rs6000_tune == PROCESSOR_POWER6
31145 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
31146 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
31147 /* Attach highest priority to insn if the scheduler has just issued two
31148 stores and this instruction is a load, or two loads and this instruction
31149 is a store. Power6 wants loads and stores scheduled alternately
31151 return current_sched_info->sched_max_insns_priority;
31156 /* Return true if the instruction is nonpipelined on the Cell. */
31158 is_nonpipeline_insn (rtx_insn *insn)
31160 enum attr_type type;
31161 if (!insn || !NONDEBUG_INSN_P (insn)
31162 || GET_CODE (PATTERN (insn)) == USE
31163 || GET_CODE (PATTERN (insn)) == CLOBBER)
31166 type = get_attr_type (insn);
31167 if (type == TYPE_MUL
31168 || type == TYPE_DIV
31169 || type == TYPE_SDIV
31170 || type == TYPE_DDIV
31171 || type == TYPE_SSQRT
31172 || type == TYPE_DSQRT
31173 || type == TYPE_MFCR
31174 || type == TYPE_MFCRF
31175 || type == TYPE_MFJMPR)
31183 /* Return how many instructions the machine can issue per cycle. */
31186 rs6000_issue_rate (void)
31188 /* Unless scheduling for register pressure, use issue rate of 1 for
31189 first scheduling pass to decrease degradation. */
31190 if (!reload_completed && !flag_sched_pressure)
31193 switch (rs6000_tune) {
31194 case PROCESSOR_RS64A:
31195 case PROCESSOR_PPC601: /* ? */
31196 case PROCESSOR_PPC7450:
31198 case PROCESSOR_PPC440:
31199 case PROCESSOR_PPC603:
31200 case PROCESSOR_PPC750:
31201 case PROCESSOR_PPC7400:
31202 case PROCESSOR_PPC8540:
31203 case PROCESSOR_PPC8548:
31204 case PROCESSOR_CELL:
31205 case PROCESSOR_PPCE300C2:
31206 case PROCESSOR_PPCE300C3:
31207 case PROCESSOR_PPCE500MC:
31208 case PROCESSOR_PPCE500MC64:
31209 case PROCESSOR_PPCE5500:
31210 case PROCESSOR_PPCE6500:
31211 case PROCESSOR_TITAN:
31213 case PROCESSOR_PPC476:
31214 case PROCESSOR_PPC604:
31215 case PROCESSOR_PPC604e:
31216 case PROCESSOR_PPC620:
31217 case PROCESSOR_PPC630:
31219 case PROCESSOR_POWER4:
31220 case PROCESSOR_POWER5:
31221 case PROCESSOR_POWER6:
31222 case PROCESSOR_POWER7:
31224 case PROCESSOR_POWER8:
31226 case PROCESSOR_POWER9:
31233 /* Return how many instructions to look ahead for better insn
31237 rs6000_use_sched_lookahead (void)
31239 switch (rs6000_tune)
31241 case PROCESSOR_PPC8540:
31242 case PROCESSOR_PPC8548:
31245 case PROCESSOR_CELL:
31246 return (reload_completed ? 8 : 0);
31253 /* We are choosing insn from the ready queue. Return zero if INSN can be
31256 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
31258 if (ready_index == 0)
31261 if (rs6000_tune != PROCESSOR_CELL)
31264 gcc_assert (insn != NULL_RTX && INSN_P (insn));
31266 if (!reload_completed
31267 || is_nonpipeline_insn (insn)
31268 || is_microcoded_insn (insn))
31274 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31275 and return true. */
31278 find_mem_ref (rtx pat, rtx *mem_ref)
31283 /* stack_tie does not produce any real memory traffic. */
31284 if (tie_operand (pat, VOIDmode))
31287 if (GET_CODE (pat) == MEM)
31293 /* Recursively process the pattern. */
31294 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31296 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31300 if (find_mem_ref (XEXP (pat, i), mem_ref))
31303 else if (fmt[i] == 'E')
31304 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31306 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31314 /* Determine if PAT is a PATTERN of a load insn. */
31317 is_load_insn1 (rtx pat, rtx *load_mem)
31319 if (!pat || pat == NULL_RTX)
31322 if (GET_CODE (pat) == SET)
31323 return find_mem_ref (SET_SRC (pat), load_mem);
31325 if (GET_CODE (pat) == PARALLEL)
31329 for (i = 0; i < XVECLEN (pat, 0); i++)
31330 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31337 /* Determine if INSN loads from memory. */
31340 is_load_insn (rtx insn, rtx *load_mem)
31342 if (!insn || !INSN_P (insn))
31348 return is_load_insn1 (PATTERN (insn), load_mem);
31351 /* Determine if PAT is a PATTERN of a store insn. */
31354 is_store_insn1 (rtx pat, rtx *str_mem)
31356 if (!pat || pat == NULL_RTX)
31359 if (GET_CODE (pat) == SET)
31360 return find_mem_ref (SET_DEST (pat), str_mem);
31362 if (GET_CODE (pat) == PARALLEL)
31366 for (i = 0; i < XVECLEN (pat, 0); i++)
31367 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31374 /* Determine if INSN stores to memory. */
31377 is_store_insn (rtx insn, rtx *str_mem)
31379 if (!insn || !INSN_P (insn))
31382 return is_store_insn1 (PATTERN (insn), str_mem);
31385 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31388 is_power9_pairable_vec_type (enum attr_type type)
31392 case TYPE_VECSIMPLE:
31393 case TYPE_VECCOMPLEX:
31397 case TYPE_VECFLOAT:
31399 case TYPE_VECDOUBLE:
31407 /* Returns whether the dependence between INSN and NEXT is considered
31408 costly by the given target. */
31411 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31415 rtx load_mem, str_mem;
31417 /* If the flag is not enabled - no dependence is considered costly;
31418 allow all dependent insns in the same group.
31419 This is the most aggressive option. */
31420 if (rs6000_sched_costly_dep == no_dep_costly)
31423 /* If the flag is set to 1 - a dependence is always considered costly;
31424 do not allow dependent instructions in the same group.
31425 This is the most conservative option. */
31426 if (rs6000_sched_costly_dep == all_deps_costly)
31429 insn = DEP_PRO (dep);
31430 next = DEP_CON (dep);
31432 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31433 && is_load_insn (next, &load_mem)
31434 && is_store_insn (insn, &str_mem))
31435 /* Prevent load after store in the same group. */
31438 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31439 && is_load_insn (next, &load_mem)
31440 && is_store_insn (insn, &str_mem)
31441 && DEP_TYPE (dep) == REG_DEP_TRUE
31442 && mem_locations_overlap(str_mem, load_mem))
31443 /* Prevent load after store in the same group if it is a true
31447 /* The flag is set to X; dependences with latency >= X are considered costly,
31448 and will not be scheduled in the same group. */
31449 if (rs6000_sched_costly_dep <= max_dep_latency
31450 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31456 /* Return the next insn after INSN that is found before TAIL is reached,
31457 skipping any "non-active" insns - insns that will not actually occupy
31458 an issue slot. Return NULL_RTX if such an insn is not found. */
31461 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31463 if (insn == NULL_RTX || insn == tail)
31468 insn = NEXT_INSN (insn);
31469 if (insn == NULL_RTX || insn == tail)
31473 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31474 || (NONJUMP_INSN_P (insn)
31475 && GET_CODE (PATTERN (insn)) != USE
31476 && GET_CODE (PATTERN (insn)) != CLOBBER
31477 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31483 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31486 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31491 enum attr_type type, type2;
31493 type = get_attr_type (last_scheduled_insn);
31495 /* Try to issue fixed point divides back-to-back in pairs so they will be
31496 routed to separate execution units and execute in parallel. */
31497 if (type == TYPE_DIV && divide_cnt == 0)
31499 /* First divide has been scheduled. */
31502 /* Scan the ready list looking for another divide, if found move it
31503 to the end of the list so it is chosen next. */
31507 if (recog_memoized (ready[pos]) >= 0
31508 && get_attr_type (ready[pos]) == TYPE_DIV)
31511 for (i = pos; i < lastpos; i++)
31512 ready[i] = ready[i + 1];
31513 ready[lastpos] = tmp;
31521 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31524 /* The best dispatch throughput for vector and vector load insns can be
31525 achieved by interleaving a vector and vector load such that they'll
31526 dispatch to the same superslice. If this pairing cannot be achieved
31527 then it is best to pair vector insns together and vector load insns
31530 To aid in this pairing, vec_pairing maintains the current state with
31531 the following values:
31533 0 : Initial state, no vecload/vector pairing has been started.
31535 1 : A vecload or vector insn has been issued and a candidate for
31536 pairing has been found and moved to the end of the ready
31538 if (type == TYPE_VECLOAD)
31540 /* Issued a vecload. */
31541 if (vec_pairing == 0)
31543 int vecload_pos = -1;
31544 /* We issued a single vecload, look for a vector insn to pair it
31545 with. If one isn't found, try to pair another vecload. */
31549 if (recog_memoized (ready[pos]) >= 0)
31551 type2 = get_attr_type (ready[pos]);
31552 if (is_power9_pairable_vec_type (type2))
31554 /* Found a vector insn to pair with, move it to the
31555 end of the ready list so it is scheduled next. */
31557 for (i = pos; i < lastpos; i++)
31558 ready[i] = ready[i + 1];
31559 ready[lastpos] = tmp;
31561 return cached_can_issue_more;
31563 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31564 /* Remember position of first vecload seen. */
31569 if (vecload_pos >= 0)
31571 /* Didn't find a vector to pair with but did find a vecload,
31572 move it to the end of the ready list. */
31573 tmp = ready[vecload_pos];
31574 for (i = vecload_pos; i < lastpos; i++)
31575 ready[i] = ready[i + 1];
31576 ready[lastpos] = tmp;
31578 return cached_can_issue_more;
31582 else if (is_power9_pairable_vec_type (type))
31584 /* Issued a vector operation. */
31585 if (vec_pairing == 0)
31588 /* We issued a single vector insn, look for a vecload to pair it
31589 with. If one isn't found, try to pair another vector. */
31593 if (recog_memoized (ready[pos]) >= 0)
31595 type2 = get_attr_type (ready[pos]);
31596 if (type2 == TYPE_VECLOAD)
31598 /* Found a vecload insn to pair with, move it to the
31599 end of the ready list so it is scheduled next. */
31601 for (i = pos; i < lastpos; i++)
31602 ready[i] = ready[i + 1];
31603 ready[lastpos] = tmp;
31605 return cached_can_issue_more;
31607 else if (is_power9_pairable_vec_type (type2)
31609 /* Remember position of first vector insn seen. */
31616 /* Didn't find a vecload to pair with but did find a vector
31617 insn, move it to the end of the ready list. */
31618 tmp = ready[vec_pos];
31619 for (i = vec_pos; i < lastpos; i++)
31620 ready[i] = ready[i + 1];
31621 ready[lastpos] = tmp;
31623 return cached_can_issue_more;
31628 /* We've either finished a vec/vecload pair, couldn't find an insn to
31629 continue the current pair, or the last insn had nothing to do with
31630 with pairing. In any case, reset the state. */
31634 return cached_can_issue_more;
31637 /* We are about to begin issuing insns for this clock cycle. */
31640 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31641 rtx_insn **ready ATTRIBUTE_UNUSED,
31642 int *pn_ready ATTRIBUTE_UNUSED,
31643 int clock_var ATTRIBUTE_UNUSED)
31645 int n_ready = *pn_ready;
31648 fprintf (dump, "// rs6000_sched_reorder :\n");
31650 /* Reorder the ready list, if the second to last ready insn
31651 is a nonepipeline insn. */
31652 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31654 if (is_nonpipeline_insn (ready[n_ready - 1])
31655 && (recog_memoized (ready[n_ready - 2]) > 0))
31656 /* Simply swap first two insns. */
31657 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31660 if (rs6000_tune == PROCESSOR_POWER6)
31661 load_store_pendulum = 0;
31663 return rs6000_issue_rate ();
31666 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31669 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31670 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31673 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31675 /* For Power6, we need to handle some special cases to try and keep the
31676 store queue from overflowing and triggering expensive flushes.
31678 This code monitors how load and store instructions are being issued
31679 and skews the ready list one way or the other to increase the likelihood
31680 that a desired instruction is issued at the proper time.
31682 A couple of things are done. First, we maintain a "load_store_pendulum"
31683 to track the current state of load/store issue.
31685 - If the pendulum is at zero, then no loads or stores have been
31686 issued in the current cycle so we do nothing.
31688 - If the pendulum is 1, then a single load has been issued in this
31689 cycle and we attempt to locate another load in the ready list to
31692 - If the pendulum is -2, then two stores have already been
31693 issued in this cycle, so we increase the priority of the first load
31694 in the ready list to increase it's likelihood of being chosen first
31697 - If the pendulum is -1, then a single store has been issued in this
31698 cycle and we attempt to locate another store in the ready list to
31699 issue with it, preferring a store to an adjacent memory location to
31700 facilitate store pairing in the store queue.
31702 - If the pendulum is 2, then two loads have already been
31703 issued in this cycle, so we increase the priority of the first store
31704 in the ready list to increase it's likelihood of being chosen first
31707 - If the pendulum < -2 or > 2, then do nothing.
31709 Note: This code covers the most common scenarios. There exist non
31710 load/store instructions which make use of the LSU and which
31711 would need to be accounted for to strictly model the behavior
31712 of the machine. Those instructions are currently unaccounted
31713 for to help minimize compile time overhead of this code.
31715 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31720 rtx load_mem, str_mem;
31722 if (is_store_insn (last_scheduled_insn, &str_mem))
31723 /* Issuing a store, swing the load_store_pendulum to the left */
31724 load_store_pendulum--;
31725 else if (is_load_insn (last_scheduled_insn, &load_mem))
31726 /* Issuing a load, swing the load_store_pendulum to the right */
31727 load_store_pendulum++;
31729 return cached_can_issue_more;
31731 /* If the pendulum is balanced, or there is only one instruction on
31732 the ready list, then all is well, so return. */
31733 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31734 return cached_can_issue_more;
31736 if (load_store_pendulum == 1)
31738 /* A load has been issued in this cycle. Scan the ready list
31739 for another load to issue with it */
31744 if (is_load_insn (ready[pos], &load_mem))
31746 /* Found a load. Move it to the head of the ready list,
31747 and adjust it's priority so that it is more likely to
31750 for (i=pos; i<*pn_ready-1; i++)
31751 ready[i] = ready[i + 1];
31752 ready[*pn_ready-1] = tmp;
31754 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31755 INSN_PRIORITY (tmp)++;
31761 else if (load_store_pendulum == -2)
31763 /* Two stores have been issued in this cycle. Increase the
31764 priority of the first load in the ready list to favor it for
31765 issuing in the next cycle. */
31770 if (is_load_insn (ready[pos], &load_mem)
31772 && INSN_PRIORITY_KNOWN (ready[pos]))
31774 INSN_PRIORITY (ready[pos])++;
31776 /* Adjust the pendulum to account for the fact that a load
31777 was found and increased in priority. This is to prevent
31778 increasing the priority of multiple loads */
31779 load_store_pendulum--;
31786 else if (load_store_pendulum == -1)
31788 /* A store has been issued in this cycle. Scan the ready list for
31789 another store to issue with it, preferring a store to an adjacent
31791 int first_store_pos = -1;
31797 if (is_store_insn (ready[pos], &str_mem))
31800 /* Maintain the index of the first store found on the
31802 if (first_store_pos == -1)
31803 first_store_pos = pos;
31805 if (is_store_insn (last_scheduled_insn, &str_mem2)
31806 && adjacent_mem_locations (str_mem, str_mem2))
31808 /* Found an adjacent store. Move it to the head of the
31809 ready list, and adjust it's priority so that it is
31810 more likely to stay there */
31812 for (i=pos; i<*pn_ready-1; i++)
31813 ready[i] = ready[i + 1];
31814 ready[*pn_ready-1] = tmp;
31816 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31817 INSN_PRIORITY (tmp)++;
31819 first_store_pos = -1;
31827 if (first_store_pos >= 0)
31829 /* An adjacent store wasn't found, but a non-adjacent store was,
31830 so move the non-adjacent store to the front of the ready
31831 list, and adjust its priority so that it is more likely to
31833 tmp = ready[first_store_pos];
31834 for (i=first_store_pos; i<*pn_ready-1; i++)
31835 ready[i] = ready[i + 1];
31836 ready[*pn_ready-1] = tmp;
31837 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31838 INSN_PRIORITY (tmp)++;
31841 else if (load_store_pendulum == 2)
31843 /* Two loads have been issued in this cycle. Increase the priority
31844 of the first store in the ready list to favor it for issuing in
31850 if (is_store_insn (ready[pos], &str_mem)
31852 && INSN_PRIORITY_KNOWN (ready[pos]))
31854 INSN_PRIORITY (ready[pos])++;
31856 /* Adjust the pendulum to account for the fact that a store
31857 was found and increased in priority. This is to prevent
31858 increasing the priority of multiple stores */
31859 load_store_pendulum++;
31868 /* Do Power9 dependent reordering if necessary. */
31869 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31870 && recog_memoized (last_scheduled_insn) >= 0)
31871 return power9_sched_reorder2 (ready, *pn_ready - 1);
31873 return cached_can_issue_more;
31876 /* Return whether the presence of INSN causes a dispatch group termination
31877 of group WHICH_GROUP.
31879 If WHICH_GROUP == current_group, this function will return true if INSN
31880 causes the termination of the current group (i.e, the dispatch group to
31881 which INSN belongs). This means that INSN will be the last insn in the
31882 group it belongs to.
31884 If WHICH_GROUP == previous_group, this function will return true if INSN
31885 causes the termination of the previous group (i.e, the dispatch group that
31886 precedes the group to which INSN belongs). This means that INSN will be
31887 the first insn in the group it belongs to). */
31890 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31897 first = insn_must_be_first_in_group (insn);
31898 last = insn_must_be_last_in_group (insn);
31903 if (which_group == current_group)
31905 else if (which_group == previous_group)
31913 insn_must_be_first_in_group (rtx_insn *insn)
31915 enum attr_type type;
31919 || DEBUG_INSN_P (insn)
31920 || GET_CODE (PATTERN (insn)) == USE
31921 || GET_CODE (PATTERN (insn)) == CLOBBER)
31924 switch (rs6000_tune)
31926 case PROCESSOR_POWER5:
31927 if (is_cracked_insn (insn))
31930 case PROCESSOR_POWER4:
31931 if (is_microcoded_insn (insn))
31934 if (!rs6000_sched_groups)
31937 type = get_attr_type (insn);
31944 case TYPE_CR_LOGICAL:
31957 case PROCESSOR_POWER6:
31958 type = get_attr_type (insn);
31967 case TYPE_FPCOMPARE:
31978 if (get_attr_dot (insn) == DOT_NO
31979 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31984 if (get_attr_size (insn) == SIZE_32)
31992 if (get_attr_update (insn) == UPDATE_YES)
32000 case PROCESSOR_POWER7:
32001 type = get_attr_type (insn);
32005 case TYPE_CR_LOGICAL:
32019 if (get_attr_dot (insn) == DOT_YES)
32024 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32025 || get_attr_update (insn) == UPDATE_YES)
32032 if (get_attr_update (insn) == UPDATE_YES)
32040 case PROCESSOR_POWER8:
32041 type = get_attr_type (insn);
32045 case TYPE_CR_LOGICAL:
32053 case TYPE_VECSTORE:
32060 if (get_attr_dot (insn) == DOT_YES)
32065 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32066 || get_attr_update (insn) == UPDATE_YES)
32071 if (get_attr_update (insn) == UPDATE_YES
32072 && get_attr_indexed (insn) == INDEXED_YES)
32088 insn_must_be_last_in_group (rtx_insn *insn)
32090 enum attr_type type;
32094 || DEBUG_INSN_P (insn)
32095 || GET_CODE (PATTERN (insn)) == USE
32096 || GET_CODE (PATTERN (insn)) == CLOBBER)
32099 switch (rs6000_tune) {
32100 case PROCESSOR_POWER4:
32101 case PROCESSOR_POWER5:
32102 if (is_microcoded_insn (insn))
32105 if (is_branch_slot_insn (insn))
32109 case PROCESSOR_POWER6:
32110 type = get_attr_type (insn);
32118 case TYPE_FPCOMPARE:
32129 if (get_attr_dot (insn) == DOT_NO
32130 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32135 if (get_attr_size (insn) == SIZE_32)
32143 case PROCESSOR_POWER7:
32144 type = get_attr_type (insn);
32154 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32155 && get_attr_update (insn) == UPDATE_YES)
32160 if (get_attr_update (insn) == UPDATE_YES
32161 && get_attr_indexed (insn) == INDEXED_YES)
32169 case PROCESSOR_POWER8:
32170 type = get_attr_type (insn);
32182 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32183 && get_attr_update (insn) == UPDATE_YES)
32188 if (get_attr_update (insn) == UPDATE_YES
32189 && get_attr_indexed (insn) == INDEXED_YES)
32204 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32205 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32208 is_costly_group (rtx *group_insns, rtx next_insn)
32211 int issue_rate = rs6000_issue_rate ();
32213 for (i = 0; i < issue_rate; i++)
32215 sd_iterator_def sd_it;
32217 rtx insn = group_insns[i];
32222 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
32224 rtx next = DEP_CON (dep);
32226 if (next == next_insn
32227 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
32235 /* Utility of the function redefine_groups.
32236 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32237 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32238 to keep it "far" (in a separate group) from GROUP_INSNS, following
32239 one of the following schemes, depending on the value of the flag
32240 -minsert_sched_nops = X:
32241 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32242 in order to force NEXT_INSN into a separate group.
32243 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32244 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32245 insertion (has a group just ended, how many vacant issue slots remain in the
32246 last group, and how many dispatch groups were encountered so far). */
32249 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
32250 rtx_insn *next_insn, bool *group_end, int can_issue_more,
32255 int issue_rate = rs6000_issue_rate ();
32256 bool end = *group_end;
32259 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
32260 return can_issue_more;
32262 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
32263 return can_issue_more;
32265 force = is_costly_group (group_insns, next_insn);
32267 return can_issue_more;
32269 if (sched_verbose > 6)
32270 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32271 *group_count ,can_issue_more);
32273 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32276 can_issue_more = 0;
32278 /* Since only a branch can be issued in the last issue_slot, it is
32279 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32280 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32281 in this case the last nop will start a new group and the branch
32282 will be forced to the new group. */
32283 if (can_issue_more && !is_branch_slot_insn (next_insn))
32286 /* Do we have a special group ending nop? */
32287 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
32288 || rs6000_tune == PROCESSOR_POWER8)
32290 nop = gen_group_ending_nop ();
32291 emit_insn_before (nop, next_insn);
32292 can_issue_more = 0;
32295 while (can_issue_more > 0)
32298 emit_insn_before (nop, next_insn);
32306 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32308 int n_nops = rs6000_sched_insert_nops;
32310 /* Nops can't be issued from the branch slot, so the effective
32311 issue_rate for nops is 'issue_rate - 1'. */
32312 if (can_issue_more == 0)
32313 can_issue_more = issue_rate;
32315 if (can_issue_more == 0)
32317 can_issue_more = issue_rate - 1;
32320 for (i = 0; i < issue_rate; i++)
32322 group_insns[i] = 0;
32329 emit_insn_before (nop, next_insn);
32330 if (can_issue_more == issue_rate - 1) /* new group begins */
32333 if (can_issue_more == 0)
32335 can_issue_more = issue_rate - 1;
32338 for (i = 0; i < issue_rate; i++)
32340 group_insns[i] = 0;
32346 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32349 /* Is next_insn going to start a new group? */
32352 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32353 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32354 || (can_issue_more < issue_rate &&
32355 insn_terminates_group_p (next_insn, previous_group)));
32356 if (*group_end && end)
32359 if (sched_verbose > 6)
32360 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32361 *group_count, can_issue_more);
32362 return can_issue_more;
32365 return can_issue_more;
32368 /* This function tries to synch the dispatch groups that the compiler "sees"
32369 with the dispatch groups that the processor dispatcher is expected to
32370 form in practice. It tries to achieve this synchronization by forcing the
32371 estimated processor grouping on the compiler (as opposed to the function
32372 'pad_goups' which tries to force the scheduler's grouping on the processor).
32374 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32375 examines the (estimated) dispatch groups that will be formed by the processor
32376 dispatcher. It marks these group boundaries to reflect the estimated
32377 processor grouping, overriding the grouping that the scheduler had marked.
32378 Depending on the value of the flag '-minsert-sched-nops' this function can
32379 force certain insns into separate groups or force a certain distance between
32380 them by inserting nops, for example, if there exists a "costly dependence"
32383 The function estimates the group boundaries that the processor will form as
32384 follows: It keeps track of how many vacant issue slots are available after
32385 each insn. A subsequent insn will start a new group if one of the following
32387 - no more vacant issue slots remain in the current dispatch group.
32388 - only the last issue slot, which is the branch slot, is vacant, but the next
32389 insn is not a branch.
32390 - only the last 2 or less issue slots, including the branch slot, are vacant,
32391 which means that a cracked insn (which occupies two issue slots) can't be
32392 issued in this group.
32393 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32394 start a new group. */
32397 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32400 rtx_insn *insn, *next_insn;
32402 int can_issue_more;
32405 int group_count = 0;
32409 issue_rate = rs6000_issue_rate ();
32410 group_insns = XALLOCAVEC (rtx, issue_rate);
32411 for (i = 0; i < issue_rate; i++)
32413 group_insns[i] = 0;
32415 can_issue_more = issue_rate;
32417 insn = get_next_active_insn (prev_head_insn, tail);
32420 while (insn != NULL_RTX)
32422 slot = (issue_rate - can_issue_more);
32423 group_insns[slot] = insn;
32425 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32426 if (insn_terminates_group_p (insn, current_group))
32427 can_issue_more = 0;
32429 next_insn = get_next_active_insn (insn, tail);
32430 if (next_insn == NULL_RTX)
32431 return group_count + 1;
32433 /* Is next_insn going to start a new group? */
32435 = (can_issue_more == 0
32436 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32437 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32438 || (can_issue_more < issue_rate &&
32439 insn_terminates_group_p (next_insn, previous_group)));
32441 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32442 next_insn, &group_end, can_issue_more,
32448 can_issue_more = 0;
32449 for (i = 0; i < issue_rate; i++)
32451 group_insns[i] = 0;
32455 if (GET_MODE (next_insn) == TImode && can_issue_more)
32456 PUT_MODE (next_insn, VOIDmode);
32457 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32458 PUT_MODE (next_insn, TImode);
32461 if (can_issue_more == 0)
32462 can_issue_more = issue_rate;
32465 return group_count;
32468 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32469 dispatch group boundaries that the scheduler had marked. Pad with nops
32470 any dispatch groups which have vacant issue slots, in order to force the
32471 scheduler's grouping on the processor dispatcher. The function
32472 returns the number of dispatch groups found. */
32475 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32478 rtx_insn *insn, *next_insn;
32481 int can_issue_more;
32483 int group_count = 0;
32485 /* Initialize issue_rate. */
32486 issue_rate = rs6000_issue_rate ();
32487 can_issue_more = issue_rate;
32489 insn = get_next_active_insn (prev_head_insn, tail);
32490 next_insn = get_next_active_insn (insn, tail);
32492 while (insn != NULL_RTX)
32495 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32497 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32499 if (next_insn == NULL_RTX)
32504 /* If the scheduler had marked group termination at this location
32505 (between insn and next_insn), and neither insn nor next_insn will
32506 force group termination, pad the group with nops to force group
32509 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32510 && !insn_terminates_group_p (insn, current_group)
32511 && !insn_terminates_group_p (next_insn, previous_group))
32513 if (!is_branch_slot_insn (next_insn))
32516 while (can_issue_more)
32519 emit_insn_before (nop, next_insn);
32524 can_issue_more = issue_rate;
32529 next_insn = get_next_active_insn (insn, tail);
32532 return group_count;
32535 /* We're beginning a new block. Initialize data structures as necessary. */
32538 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32539 int sched_verbose ATTRIBUTE_UNUSED,
32540 int max_ready ATTRIBUTE_UNUSED)
32542 last_scheduled_insn = NULL;
32543 load_store_pendulum = 0;
32548 /* The following function is called at the end of scheduling BB.
32549 After reload, it inserts nops at insn group bundling. */
32552 rs6000_sched_finish (FILE *dump, int sched_verbose)
32557 fprintf (dump, "=== Finishing schedule.\n");
32559 if (reload_completed && rs6000_sched_groups)
32561 /* Do not run sched_finish hook when selective scheduling enabled. */
32562 if (sel_sched_p ())
32565 if (rs6000_sched_insert_nops == sched_finish_none)
32568 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32569 n_groups = pad_groups (dump, sched_verbose,
32570 current_sched_info->prev_head,
32571 current_sched_info->next_tail);
32573 n_groups = redefine_groups (dump, sched_verbose,
32574 current_sched_info->prev_head,
32575 current_sched_info->next_tail);
32577 if (sched_verbose >= 6)
32579 fprintf (dump, "ngroups = %d\n", n_groups);
32580 print_rtl (dump, current_sched_info->prev_head);
32581 fprintf (dump, "Done finish_sched\n");
32586 struct rs6000_sched_context
32588 short cached_can_issue_more;
32589 rtx_insn *last_scheduled_insn;
32590 int load_store_pendulum;
32595 typedef struct rs6000_sched_context rs6000_sched_context_def;
32596 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32598 /* Allocate store for new scheduling context. */
32600 rs6000_alloc_sched_context (void)
32602 return xmalloc (sizeof (rs6000_sched_context_def));
32605 /* If CLEAN_P is true then initializes _SC with clean data,
32606 and from the global context otherwise. */
32608 rs6000_init_sched_context (void *_sc, bool clean_p)
32610 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32614 sc->cached_can_issue_more = 0;
32615 sc->last_scheduled_insn = NULL;
32616 sc->load_store_pendulum = 0;
32617 sc->divide_cnt = 0;
32618 sc->vec_pairing = 0;
32622 sc->cached_can_issue_more = cached_can_issue_more;
32623 sc->last_scheduled_insn = last_scheduled_insn;
32624 sc->load_store_pendulum = load_store_pendulum;
32625 sc->divide_cnt = divide_cnt;
32626 sc->vec_pairing = vec_pairing;
32630 /* Sets the global scheduling context to the one pointed to by _SC. */
32632 rs6000_set_sched_context (void *_sc)
32634 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32636 gcc_assert (sc != NULL);
32638 cached_can_issue_more = sc->cached_can_issue_more;
32639 last_scheduled_insn = sc->last_scheduled_insn;
32640 load_store_pendulum = sc->load_store_pendulum;
32641 divide_cnt = sc->divide_cnt;
32642 vec_pairing = sc->vec_pairing;
32647 rs6000_free_sched_context (void *_sc)
32649 gcc_assert (_sc != NULL);
32655 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32657 switch (get_attr_type (insn))
32672 /* Length in units of the trampoline for entering a nested function. */
32675 rs6000_trampoline_size (void)
32679 switch (DEFAULT_ABI)
32682 gcc_unreachable ();
32685 ret = (TARGET_32BIT) ? 12 : 24;
32689 gcc_assert (!TARGET_32BIT);
32695 ret = (TARGET_32BIT) ? 40 : 48;
32702 /* Emit RTL insns to initialize the variable parts of a trampoline.
32703 FNADDR is an RTX for the address of the function's pure code.
32704 CXT is an RTX for the static chain value for the function. */
32707 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32709 int regsize = (TARGET_32BIT) ? 4 : 8;
32710 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32711 rtx ctx_reg = force_reg (Pmode, cxt);
32712 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32714 switch (DEFAULT_ABI)
32717 gcc_unreachable ();
32719 /* Under AIX, just build the 3 word function descriptor */
32722 rtx fnmem, fn_reg, toc_reg;
32724 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32725 error ("you cannot take the address of a nested function if you use "
32726 "the %qs option", "-mno-pointers-to-nested-functions");
32728 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32729 fn_reg = gen_reg_rtx (Pmode);
32730 toc_reg = gen_reg_rtx (Pmode);
32732 /* Macro to shorten the code expansions below. */
32733 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32735 m_tramp = replace_equiv_address (m_tramp, addr);
32737 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32738 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32739 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32740 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32741 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32747 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32751 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32752 LCT_NORMAL, VOIDmode,
32754 GEN_INT (rs6000_trampoline_size ()), SImode,
32762 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32763 identifier as an argument, so the front end shouldn't look it up. */
32766 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32768 return is_attribute_p ("altivec", attr_id);
32771 /* Handle the "altivec" attribute. The attribute may have
32772 arguments as follows:
32774 __attribute__((altivec(vector__)))
32775 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32776 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32778 and may appear more than once (e.g., 'vector bool char') in a
32779 given declaration. */
32782 rs6000_handle_altivec_attribute (tree *node,
32783 tree name ATTRIBUTE_UNUSED,
32785 int flags ATTRIBUTE_UNUSED,
32786 bool *no_add_attrs)
32788 tree type = *node, result = NULL_TREE;
32792 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32793 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32794 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32797 while (POINTER_TYPE_P (type)
32798 || TREE_CODE (type) == FUNCTION_TYPE
32799 || TREE_CODE (type) == METHOD_TYPE
32800 || TREE_CODE (type) == ARRAY_TYPE)
32801 type = TREE_TYPE (type);
32803 mode = TYPE_MODE (type);
32805 /* Check for invalid AltiVec type qualifiers. */
32806 if (type == long_double_type_node)
32807 error ("use of %<long double%> in AltiVec types is invalid");
32808 else if (type == boolean_type_node)
32809 error ("use of boolean types in AltiVec types is invalid");
32810 else if (TREE_CODE (type) == COMPLEX_TYPE)
32811 error ("use of %<complex%> in AltiVec types is invalid");
32812 else if (DECIMAL_FLOAT_MODE_P (mode))
32813 error ("use of decimal floating point types in AltiVec types is invalid");
32814 else if (!TARGET_VSX)
32816 if (type == long_unsigned_type_node || type == long_integer_type_node)
32819 error ("use of %<long%> in AltiVec types is invalid for "
32820 "64-bit code without %qs", "-mvsx");
32821 else if (rs6000_warn_altivec_long)
32822 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32825 else if (type == long_long_unsigned_type_node
32826 || type == long_long_integer_type_node)
32827 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32829 else if (type == double_type_node)
32830 error ("use of %<double%> in AltiVec types is invalid without %qs",
32834 switch (altivec_type)
32837 unsigned_p = TYPE_UNSIGNED (type);
32841 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32844 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32847 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32850 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32853 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32855 case E_SFmode: result = V4SF_type_node; break;
32856 case E_DFmode: result = V2DF_type_node; break;
32857 /* If the user says 'vector int bool', we may be handed the 'bool'
32858 attribute _before_ the 'vector' attribute, and so select the
32859 proper type in the 'b' case below. */
32860 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32861 case E_V2DImode: case E_V2DFmode:
32869 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32870 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32871 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32872 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32879 case E_V8HImode: result = pixel_V8HI_type_node;
32885 /* Propagate qualifiers attached to the element type
32886 onto the vector type. */
32887 if (result && result != type && TYPE_QUALS (type))
32888 result = build_qualified_type (result, TYPE_QUALS (type));
32890 *no_add_attrs = true; /* No need to hang on to the attribute. */
32893 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32898 /* AltiVec defines four built-in scalar types that serve as vector
32899 elements; we must teach the compiler how to mangle them. */
32901 static const char *
32902 rs6000_mangle_type (const_tree type)
32904 type = TYPE_MAIN_VARIANT (type);
32906 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32907 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32910 if (type == bool_char_type_node) return "U6__boolc";
32911 if (type == bool_short_type_node) return "U6__bools";
32912 if (type == pixel_type_node) return "u7__pixel";
32913 if (type == bool_int_type_node) return "U6__booli";
32914 if (type == bool_long_type_node) return "U6__booll";
32916 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
32917 "g" for IBM extended double, no matter whether it is long double (using
32918 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
32919 if (TARGET_FLOAT128_TYPE)
32921 if (type == ieee128_float_type_node)
32922 return "U10__float128";
32924 if (TARGET_LONG_DOUBLE_128)
32926 if (type == long_double_type_node)
32927 return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
32929 if (type == ibm128_float_type_node)
32934 /* Mangle IBM extended float long double as `g' (__float128) on
32935 powerpc*-linux where long-double-64 previously was the default. */
32936 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
32938 && TARGET_LONG_DOUBLE_128
32939 && !TARGET_IEEEQUAD)
32942 /* For all other types, use normal C++ mangling. */
32946 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32947 struct attribute_spec.handler. */
32950 rs6000_handle_longcall_attribute (tree *node, tree name,
32951 tree args ATTRIBUTE_UNUSED,
32952 int flags ATTRIBUTE_UNUSED,
32953 bool *no_add_attrs)
32955 if (TREE_CODE (*node) != FUNCTION_TYPE
32956 && TREE_CODE (*node) != FIELD_DECL
32957 && TREE_CODE (*node) != TYPE_DECL)
32959 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32961 *no_add_attrs = true;
32967 /* Set longcall attributes on all functions declared when
32968 rs6000_default_long_calls is true. */
32970 rs6000_set_default_type_attributes (tree type)
32972 if (rs6000_default_long_calls
32973 && (TREE_CODE (type) == FUNCTION_TYPE
32974 || TREE_CODE (type) == METHOD_TYPE))
32975 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32977 TYPE_ATTRIBUTES (type));
32980 darwin_set_default_type_attributes (type);
32984 /* Return a reference suitable for calling a function with the
32985 longcall attribute. */
32988 rs6000_longcall_ref (rtx call_ref)
32990 const char *call_name;
32993 if (GET_CODE (call_ref) != SYMBOL_REF)
32996 /* System V adds '.' to the internal name, so skip them. */
32997 call_name = XSTR (call_ref, 0);
32998 if (*call_name == '.')
33000 while (*call_name == '.')
33003 node = get_identifier (call_name);
33004 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
33007 return force_reg (Pmode, call_ref);
33010 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
33011 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
33014 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
33015 struct attribute_spec.handler. */
33017 rs6000_handle_struct_attribute (tree *node, tree name,
33018 tree args ATTRIBUTE_UNUSED,
33019 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
33022 if (DECL_P (*node))
33024 if (TREE_CODE (*node) == TYPE_DECL)
33025 type = &TREE_TYPE (*node);
33030 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
33031 || TREE_CODE (*type) == UNION_TYPE)))
33033 warning (OPT_Wattributes, "%qE attribute ignored", name);
33034 *no_add_attrs = true;
33037 else if ((is_attribute_p ("ms_struct", name)
33038 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
33039 || ((is_attribute_p ("gcc_struct", name)
33040 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
33042 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
33044 *no_add_attrs = true;
33051 rs6000_ms_bitfield_layout_p (const_tree record_type)
33053 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
33054 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
33055 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
33058 #ifdef USING_ELFOS_H
33060 /* A get_unnamed_section callback, used for switching to toc_section. */
33063 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33065 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33066 && TARGET_MINIMAL_TOC)
33068 if (!toc_initialized)
33070 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33071 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33072 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
33073 fprintf (asm_out_file, "\t.tc ");
33074 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
33075 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33076 fprintf (asm_out_file, "\n");
33078 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33079 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33080 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33081 fprintf (asm_out_file, " = .+32768\n");
33082 toc_initialized = 1;
33085 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33087 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33089 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33090 if (!toc_initialized)
33092 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33093 toc_initialized = 1;
33098 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33099 if (!toc_initialized)
33101 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33102 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33103 fprintf (asm_out_file, " = .+32768\n");
33104 toc_initialized = 1;
33109 /* Implement TARGET_ASM_INIT_SECTIONS. */
33112 rs6000_elf_asm_init_sections (void)
33115 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
33118 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
33119 SDATA2_SECTION_ASM_OP);
33122 /* Implement TARGET_SELECT_RTX_SECTION. */
33125 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
33126 unsigned HOST_WIDE_INT align)
33128 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33129 return toc_section;
33131 return default_elf_select_rtx_section (mode, x, align);
33134 /* For a SYMBOL_REF, set generic flags and then perform some
33135 target-specific processing.
33137 When the AIX ABI is requested on a non-AIX system, replace the
33138 function name with the real name (with a leading .) rather than the
33139 function descriptor name. This saves a lot of overriding code to
33140 read the prefixes. */
33142 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
33144 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
33146 default_encode_section_info (decl, rtl, first);
33149 && TREE_CODE (decl) == FUNCTION_DECL
33151 && DEFAULT_ABI == ABI_AIX)
33153 rtx sym_ref = XEXP (rtl, 0);
33154 size_t len = strlen (XSTR (sym_ref, 0));
33155 char *str = XALLOCAVEC (char, len + 2);
33157 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
33158 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
33163 compare_section_name (const char *section, const char *templ)
33167 len = strlen (templ);
33168 return (strncmp (section, templ, len) == 0
33169 && (section[len] == 0 || section[len] == '.'));
33173 rs6000_elf_in_small_data_p (const_tree decl)
33175 if (rs6000_sdata == SDATA_NONE)
33178 /* We want to merge strings, so we never consider them small data. */
33179 if (TREE_CODE (decl) == STRING_CST)
33182 /* Functions are never in the small data area. */
33183 if (TREE_CODE (decl) == FUNCTION_DECL)
33186 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
33188 const char *section = DECL_SECTION_NAME (decl);
33189 if (compare_section_name (section, ".sdata")
33190 || compare_section_name (section, ".sdata2")
33191 || compare_section_name (section, ".gnu.linkonce.s")
33192 || compare_section_name (section, ".sbss")
33193 || compare_section_name (section, ".sbss2")
33194 || compare_section_name (section, ".gnu.linkonce.sb")
33195 || strcmp (section, ".PPC.EMB.sdata0") == 0
33196 || strcmp (section, ".PPC.EMB.sbss0") == 0)
33201 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
33204 && size <= g_switch_value
33205 /* If it's not public, and we're not going to reference it there,
33206 there's no need to put it in the small data section. */
33207 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
33214 #endif /* USING_ELFOS_H */
33216 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33219 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
33221 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
33224 /* Do not place thread-local symbols refs in the object blocks. */
33227 rs6000_use_blocks_for_decl_p (const_tree decl)
33229 return !DECL_THREAD_LOCAL_P (decl);
33232 /* Return a REG that occurs in ADDR with coefficient 1.
33233 ADDR can be effectively incremented by incrementing REG.
33235 r0 is special and we must not select it as an address
33236 register by this routine since our caller will try to
33237 increment the returned register via an "la" instruction. */
33240 find_addr_reg (rtx addr)
33242 while (GET_CODE (addr) == PLUS)
33244 if (GET_CODE (XEXP (addr, 0)) == REG
33245 && REGNO (XEXP (addr, 0)) != 0)
33246 addr = XEXP (addr, 0);
33247 else if (GET_CODE (XEXP (addr, 1)) == REG
33248 && REGNO (XEXP (addr, 1)) != 0)
33249 addr = XEXP (addr, 1);
33250 else if (CONSTANT_P (XEXP (addr, 0)))
33251 addr = XEXP (addr, 1);
33252 else if (CONSTANT_P (XEXP (addr, 1)))
33253 addr = XEXP (addr, 0);
33255 gcc_unreachable ();
33257 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
33262 rs6000_fatal_bad_address (rtx op)
33264 fatal_insn ("bad address", op);
33269 typedef struct branch_island_d {
33270 tree function_name;
33276 static vec<branch_island, va_gc> *branch_islands;
33278 /* Remember to generate a branch island for far calls to the given
33282 add_compiler_branch_island (tree label_name, tree function_name,
33285 branch_island bi = {function_name, label_name, line_number};
33286 vec_safe_push (branch_islands, bi);
33289 /* Generate far-jump branch islands for everything recorded in
33290 branch_islands. Invoked immediately after the last instruction of
33291 the epilogue has been emitted; the branch islands must be appended
33292 to, and contiguous with, the function body. Mach-O stubs are
33293 generated in machopic_output_stub(). */
33296 macho_branch_islands (void)
33300 while (!vec_safe_is_empty (branch_islands))
33302 branch_island *bi = &branch_islands->last ();
33303 const char *label = IDENTIFIER_POINTER (bi->label_name);
33304 const char *name = IDENTIFIER_POINTER (bi->function_name);
33305 char name_buf[512];
33306 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33307 if (name[0] == '*' || name[0] == '&')
33308 strcpy (name_buf, name+1);
33312 strcpy (name_buf+1, name);
33314 strcpy (tmp_buf, "\n");
33315 strcat (tmp_buf, label);
33316 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33317 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33318 dbxout_stabd (N_SLINE, bi->line_number);
33319 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33322 if (TARGET_LINK_STACK)
33325 get_ppc476_thunk_name (name);
33326 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33327 strcat (tmp_buf, name);
33328 strcat (tmp_buf, "\n");
33329 strcat (tmp_buf, label);
33330 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33334 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33335 strcat (tmp_buf, label);
33336 strcat (tmp_buf, "_pic\n");
33337 strcat (tmp_buf, label);
33338 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33341 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33342 strcat (tmp_buf, name_buf);
33343 strcat (tmp_buf, " - ");
33344 strcat (tmp_buf, label);
33345 strcat (tmp_buf, "_pic)\n");
33347 strcat (tmp_buf, "\tmtlr r0\n");
33349 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33350 strcat (tmp_buf, name_buf);
33351 strcat (tmp_buf, " - ");
33352 strcat (tmp_buf, label);
33353 strcat (tmp_buf, "_pic)\n");
33355 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33359 strcat (tmp_buf, ":\nlis r12,hi16(");
33360 strcat (tmp_buf, name_buf);
33361 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33362 strcat (tmp_buf, name_buf);
33363 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33365 output_asm_insn (tmp_buf, 0);
33366 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33367 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33368 dbxout_stabd (N_SLINE, bi->line_number);
33369 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33370 branch_islands->pop ();
33374 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33375 already there or not. */
33378 no_previous_def (tree function_name)
33383 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33384 if (function_name == bi->function_name)
33389 /* GET_PREV_LABEL gets the label name from the previous definition of
33393 get_prev_label (tree function_name)
33398 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33399 if (function_name == bi->function_name)
33400 return bi->label_name;
33404 /* INSN is either a function call or a millicode call. It may have an
33405 unconditional jump in its delay slot.
33407 CALL_DEST is the routine we are calling. */
33410 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
33411 int cookie_operand_number)
33413 static char buf[256];
33414 if (darwin_emit_branch_islands
33415 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
33416 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
33419 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
33421 if (no_previous_def (funname))
33423 rtx label_rtx = gen_label_rtx ();
33424 char *label_buf, temp_buf[256];
33425 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
33426 CODE_LABEL_NUMBER (label_rtx));
33427 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
33428 labelname = get_identifier (label_buf);
33429 add_compiler_branch_island (labelname, funname, insn_line (insn));
33432 labelname = get_prev_label (funname);
33434 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33435 instruction will reach 'foo', otherwise link as 'bl L42'".
33436 "L42" should be a 'branch island', that will do a far jump to
33437 'foo'. Branch islands are generated in
33438 macho_branch_islands(). */
33439 sprintf (buf, "jbsr %%z%d,%.246s",
33440 dest_operand_number, IDENTIFIER_POINTER (labelname));
33443 sprintf (buf, "bl %%z%d", dest_operand_number);
33447 /* Generate PIC and indirect symbol stubs. */
33450 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33452 unsigned int length;
33453 char *symbol_name, *lazy_ptr_name;
33454 char *local_label_0;
33455 static int label = 0;
33457 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33458 symb = (*targetm.strip_name_encoding) (symb);
33461 length = strlen (symb);
33462 symbol_name = XALLOCAVEC (char, length + 32);
33463 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33465 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33466 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33469 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33471 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33475 fprintf (file, "\t.align 5\n");
33477 fprintf (file, "%s:\n", stub);
33478 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33481 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33482 sprintf (local_label_0, "\"L%011d$spb\"", label);
33484 fprintf (file, "\tmflr r0\n");
33485 if (TARGET_LINK_STACK)
33488 get_ppc476_thunk_name (name);
33489 fprintf (file, "\tbl %s\n", name);
33490 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33494 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33495 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33497 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33498 lazy_ptr_name, local_label_0);
33499 fprintf (file, "\tmtlr r0\n");
33500 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33501 (TARGET_64BIT ? "ldu" : "lwzu"),
33502 lazy_ptr_name, local_label_0);
33503 fprintf (file, "\tmtctr r12\n");
33504 fprintf (file, "\tbctr\n");
33508 fprintf (file, "\t.align 4\n");
33510 fprintf (file, "%s:\n", stub);
33511 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33513 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33514 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33515 (TARGET_64BIT ? "ldu" : "lwzu"),
33517 fprintf (file, "\tmtctr r12\n");
33518 fprintf (file, "\tbctr\n");
33521 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33522 fprintf (file, "%s:\n", lazy_ptr_name);
33523 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33524 fprintf (file, "%sdyld_stub_binding_helper\n",
33525 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33528 /* Legitimize PIC addresses. If the address is already
33529 position-independent, we return ORIG. Newly generated
33530 position-independent addresses go into a reg. This is REG if non
33531 zero, otherwise we allocate register(s) as necessary. */
33533 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33536 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33541 if (reg == NULL && !reload_completed)
33542 reg = gen_reg_rtx (Pmode);
33544 if (GET_CODE (orig) == CONST)
33548 if (GET_CODE (XEXP (orig, 0)) == PLUS
33549 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33552 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33554 /* Use a different reg for the intermediate value, as
33555 it will be marked UNCHANGING. */
33556 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33557 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33560 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33563 if (GET_CODE (offset) == CONST_INT)
33565 if (SMALL_INT (offset))
33566 return plus_constant (Pmode, base, INTVAL (offset));
33567 else if (!reload_completed)
33568 offset = force_reg (Pmode, offset);
33571 rtx mem = force_const_mem (Pmode, orig);
33572 return machopic_legitimize_pic_address (mem, Pmode, reg);
33575 return gen_rtx_PLUS (Pmode, base, offset);
33578 /* Fall back on generic machopic code. */
33579 return machopic_legitimize_pic_address (orig, mode, reg);
33582 /* Output a .machine directive for the Darwin assembler, and call
33583 the generic start_file routine. */
33586 rs6000_darwin_file_start (void)
33588 static const struct
33592 HOST_WIDE_INT if_set;
33594 { "ppc64", "ppc64", MASK_64BIT },
33595 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33596 { "power4", "ppc970", 0 },
33597 { "G5", "ppc970", 0 },
33598 { "7450", "ppc7450", 0 },
33599 { "7400", "ppc7400", MASK_ALTIVEC },
33600 { "G4", "ppc7400", 0 },
33601 { "750", "ppc750", 0 },
33602 { "740", "ppc750", 0 },
33603 { "G3", "ppc750", 0 },
33604 { "604e", "ppc604e", 0 },
33605 { "604", "ppc604", 0 },
33606 { "603e", "ppc603", 0 },
33607 { "603", "ppc603", 0 },
33608 { "601", "ppc601", 0 },
33609 { NULL, "ppc", 0 } };
33610 const char *cpu_id = "";
33613 rs6000_file_start ();
33614 darwin_file_start ();
33616 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33618 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33619 cpu_id = rs6000_default_cpu;
33621 if (global_options_set.x_rs6000_cpu_index)
33622 cpu_id = processor_target_table[rs6000_cpu_index].name;
33624 /* Look through the mapping array. Pick the first name that either
33625 matches the argument, has a bit set in IF_SET that is also set
33626 in the target flags, or has a NULL name. */
33629 while (mapping[i].arg != NULL
33630 && strcmp (mapping[i].arg, cpu_id) != 0
33631 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33634 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33637 #endif /* TARGET_MACHO */
33641 rs6000_elf_reloc_rw_mask (void)
33645 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33651 /* Record an element in the table of global constructors. SYMBOL is
33652 a SYMBOL_REF of the function to be called; PRIORITY is a number
33653 between 0 and MAX_INIT_PRIORITY.
33655 This differs from default_named_section_asm_out_constructor in
33656 that we have special handling for -mrelocatable. */
33658 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33660 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33662 const char *section = ".ctors";
33665 if (priority != DEFAULT_INIT_PRIORITY)
33667 sprintf (buf, ".ctors.%.5u",
33668 /* Invert the numbering so the linker puts us in the proper
33669 order; constructors are run from right to left, and the
33670 linker sorts in increasing order. */
33671 MAX_INIT_PRIORITY - priority);
33675 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33676 assemble_align (POINTER_SIZE);
33678 if (DEFAULT_ABI == ABI_V4
33679 && (TARGET_RELOCATABLE || flag_pic > 1))
33681 fputs ("\t.long (", asm_out_file);
33682 output_addr_const (asm_out_file, symbol);
33683 fputs (")@fixup\n", asm_out_file);
33686 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33689 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33691 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33693 const char *section = ".dtors";
33696 if (priority != DEFAULT_INIT_PRIORITY)
33698 sprintf (buf, ".dtors.%.5u",
33699 /* Invert the numbering so the linker puts us in the proper
33700 order; constructors are run from right to left, and the
33701 linker sorts in increasing order. */
33702 MAX_INIT_PRIORITY - priority);
33706 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33707 assemble_align (POINTER_SIZE);
33709 if (DEFAULT_ABI == ABI_V4
33710 && (TARGET_RELOCATABLE || flag_pic > 1))
33712 fputs ("\t.long (", asm_out_file);
33713 output_addr_const (asm_out_file, symbol);
33714 fputs (")@fixup\n", asm_out_file);
33717 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33721 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33723 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33725 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33726 ASM_OUTPUT_LABEL (file, name);
33727 fputs (DOUBLE_INT_ASM_OP, file);
33728 rs6000_output_function_entry (file, name);
33729 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33732 fputs ("\t.size\t", file);
33733 assemble_name (file, name);
33734 fputs (",24\n\t.type\t.", file);
33735 assemble_name (file, name);
33736 fputs (",@function\n", file);
33737 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33739 fputs ("\t.globl\t.", file);
33740 assemble_name (file, name);
33745 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33746 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33747 rs6000_output_function_entry (file, name);
33748 fputs (":\n", file);
33753 if (DEFAULT_ABI == ABI_V4
33754 && (TARGET_RELOCATABLE || flag_pic > 1)
33755 && !TARGET_SECURE_PLT
33756 && (!constant_pool_empty_p () || crtl->profile)
33757 && (uses_toc = uses_TOC ()))
33762 switch_to_other_text_partition ();
33763 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33765 fprintf (file, "\t.long ");
33766 assemble_name (file, toc_label_name);
33769 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33770 assemble_name (file, buf);
33773 switch_to_other_text_partition ();
33776 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33777 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33779 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33783 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33785 fprintf (file, "\t.quad .TOC.-");
33786 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33787 assemble_name (file, buf);
33791 if (DEFAULT_ABI == ABI_AIX)
33793 const char *desc_name, *orig_name;
33795 orig_name = (*targetm.strip_name_encoding) (name);
33796 desc_name = orig_name;
33797 while (*desc_name == '.')
33800 if (TREE_PUBLIC (decl))
33801 fprintf (file, "\t.globl %s\n", desc_name);
33803 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33804 fprintf (file, "%s:\n", desc_name);
33805 fprintf (file, "\t.long %s\n", orig_name);
33806 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33807 fputs ("\t.long 0\n", file);
33808 fprintf (file, "\t.previous\n");
33810 ASM_OUTPUT_LABEL (file, name);
33813 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33815 rs6000_elf_file_end (void)
33817 #ifdef HAVE_AS_GNU_ATTRIBUTE
33818 /* ??? The value emitted depends on options active at file end.
33819 Assume anyone using #pragma or attributes that might change
33820 options knows what they are doing. */
33821 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33822 && rs6000_passes_float)
33828 else if (TARGET_SF_FPR)
33832 if (rs6000_passes_long_double)
33834 if (!TARGET_LONG_DOUBLE_128)
33836 else if (TARGET_IEEEQUAD)
33841 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33843 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33845 if (rs6000_passes_vector)
33846 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33847 (TARGET_ALTIVEC_ABI ? 2 : 1));
33848 if (rs6000_returns_struct)
33849 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33850 aix_struct_return ? 2 : 1);
33853 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33854 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33855 file_end_indicate_exec_stack ();
33858 if (flag_split_stack)
33859 file_end_indicate_split_stack ();
33863 /* We have expanded a CPU builtin, so we need to emit a reference to
33864 the special symbol that LIBC uses to declare it supports the
33865 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33866 switch_to_section (data_section);
33867 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33868 fprintf (asm_out_file, "\t%s %s\n",
33869 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33876 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33877 #define HAVE_XCOFF_DWARF_EXTRAS 0
33880 static enum unwind_info_type
33881 rs6000_xcoff_debug_unwind_info (void)
33887 rs6000_xcoff_asm_output_anchor (rtx symbol)
33891 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33892 SYMBOL_REF_BLOCK_OFFSET (symbol));
33893 fprintf (asm_out_file, "%s", SET_ASM_OP);
33894 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33895 fprintf (asm_out_file, ",");
33896 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33897 fprintf (asm_out_file, "\n");
33901 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33903 fputs (GLOBAL_ASM_OP, stream);
33904 RS6000_OUTPUT_BASENAME (stream, name);
33905 putc ('\n', stream);
33908 /* A get_unnamed_decl callback, used for read-only sections. PTR
33909 points to the section string variable. */
33912 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33914 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33915 *(const char *const *) directive,
33916 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33919 /* Likewise for read-write sections. */
33922 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33924 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33925 *(const char *const *) directive,
33926 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33930 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33932 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33933 *(const char *const *) directive,
33934 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33937 /* A get_unnamed_section callback, used for switching to toc_section. */
33940 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33942 if (TARGET_MINIMAL_TOC)
33944 /* toc_section is always selected at least once from
33945 rs6000_xcoff_file_start, so this is guaranteed to
33946 always be defined once and only once in each file. */
33947 if (!toc_initialized)
33949 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33950 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33951 toc_initialized = 1;
33953 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33954 (TARGET_32BIT ? "" : ",3"));
33957 fputs ("\t.toc\n", asm_out_file);
33960 /* Implement TARGET_ASM_INIT_SECTIONS. */
33963 rs6000_xcoff_asm_init_sections (void)
33965 read_only_data_section
33966 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33967 &xcoff_read_only_section_name);
33969 private_data_section
33970 = get_unnamed_section (SECTION_WRITE,
33971 rs6000_xcoff_output_readwrite_section_asm_op,
33972 &xcoff_private_data_section_name);
33975 = get_unnamed_section (SECTION_TLS,
33976 rs6000_xcoff_output_tls_section_asm_op,
33977 &xcoff_tls_data_section_name);
33979 tls_private_data_section
33980 = get_unnamed_section (SECTION_TLS,
33981 rs6000_xcoff_output_tls_section_asm_op,
33982 &xcoff_private_data_section_name);
33984 read_only_private_data_section
33985 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33986 &xcoff_private_data_section_name);
33989 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33991 readonly_data_section = read_only_data_section;
33995 rs6000_xcoff_reloc_rw_mask (void)
34001 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
34002 tree decl ATTRIBUTE_UNUSED)
34005 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
34007 if (flags & SECTION_EXCLUDE)
34009 else if (flags & SECTION_DEBUG)
34011 fprintf (asm_out_file, "\t.dwsect %s\n", name);
34014 else if (flags & SECTION_CODE)
34016 else if (flags & SECTION_TLS)
34018 else if (flags & SECTION_WRITE)
34023 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
34024 (flags & SECTION_CODE) ? "." : "",
34025 name, suffix[smclass], flags & SECTION_ENTSIZE);
34028 #define IN_NAMED_SECTION(DECL) \
34029 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
34030 && DECL_SECTION_NAME (DECL) != NULL)
34033 rs6000_xcoff_select_section (tree decl, int reloc,
34034 unsigned HOST_WIDE_INT align)
34036 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
34038 if (align > BIGGEST_ALIGNMENT)
34040 resolve_unique_section (decl, reloc, true);
34041 if (IN_NAMED_SECTION (decl))
34042 return get_named_section (decl, NULL, reloc);
34045 if (decl_readonly_section (decl, reloc))
34047 if (TREE_PUBLIC (decl))
34048 return read_only_data_section;
34050 return read_only_private_data_section;
34055 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34057 if (TREE_PUBLIC (decl))
34058 return tls_data_section;
34059 else if (bss_initializer_p (decl))
34061 /* Convert to COMMON to emit in BSS. */
34062 DECL_COMMON (decl) = 1;
34063 return tls_comm_section;
34066 return tls_private_data_section;
34070 if (TREE_PUBLIC (decl))
34071 return data_section;
34073 return private_data_section;
34078 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
34082 /* Use select_section for private data and uninitialized data with
34083 alignment <= BIGGEST_ALIGNMENT. */
34084 if (!TREE_PUBLIC (decl)
34085 || DECL_COMMON (decl)
34086 || (DECL_INITIAL (decl) == NULL_TREE
34087 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
34088 || DECL_INITIAL (decl) == error_mark_node
34089 || (flag_zero_initialized_in_bss
34090 && initializer_zerop (DECL_INITIAL (decl))))
34093 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
34094 name = (*targetm.strip_name_encoding) (name);
34095 set_decl_section_name (decl, name);
34098 /* Select section for constant in constant pool.
34100 On RS/6000, all constants are in the private read-only data area.
34101 However, if this is being placed in the TOC it must be output as a
34105 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
34106 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
34108 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
34109 return toc_section;
34111 return read_only_private_data_section;
34114 /* Remove any trailing [DS] or the like from the symbol name. */
34116 static const char *
34117 rs6000_xcoff_strip_name_encoding (const char *name)
34122 len = strlen (name);
34123 if (name[len - 1] == ']')
34124 return ggc_alloc_string (name, len - 4);
34129 /* Section attributes. AIX is always PIC. */
34131 static unsigned int
34132 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
34134 unsigned int align;
34135 unsigned int flags = default_section_type_flags (decl, name, reloc);
34137 /* Align to at least UNIT size. */
34138 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
34139 align = MIN_UNITS_PER_WORD;
34141 /* Increase alignment of large objects if not already stricter. */
34142 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
34143 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
34144 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
34146 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
34149 /* Output at beginning of assembler file.
34151 Initialize the section names for the RS/6000 at this point.
34153 Specify filename, including full path, to assembler.
34155 We want to go into the TOC section so at least one .toc will be emitted.
34156 Also, in order to output proper .bs/.es pairs, we need at least one static
34157 [RW] section emitted.
34159 Finally, declare mcount when profiling to make the assembler happy. */
34162 rs6000_xcoff_file_start (void)
34164 rs6000_gen_section_name (&xcoff_bss_section_name,
34165 main_input_filename, ".bss_");
34166 rs6000_gen_section_name (&xcoff_private_data_section_name,
34167 main_input_filename, ".rw_");
34168 rs6000_gen_section_name (&xcoff_read_only_section_name,
34169 main_input_filename, ".ro_");
34170 rs6000_gen_section_name (&xcoff_tls_data_section_name,
34171 main_input_filename, ".tls_");
34172 rs6000_gen_section_name (&xcoff_tbss_section_name,
34173 main_input_filename, ".tbss_[UL]");
34175 fputs ("\t.file\t", asm_out_file);
34176 output_quoted_string (asm_out_file, main_input_filename);
34177 fputc ('\n', asm_out_file);
34178 if (write_symbols != NO_DEBUG)
34179 switch_to_section (private_data_section);
34180 switch_to_section (toc_section);
34181 switch_to_section (text_section);
34183 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
34184 rs6000_file_start ();
34187 /* Output at end of assembler file.
34188 On the RS/6000, referencing data should automatically pull in text. */
34191 rs6000_xcoff_file_end (void)
34193 switch_to_section (text_section);
34194 fputs ("_section_.text:\n", asm_out_file);
34195 switch_to_section (data_section);
34196 fputs (TARGET_32BIT
34197 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34201 struct declare_alias_data
34204 bool function_descriptor;
34207 /* Declare alias N. A helper function for for_node_and_aliases. */
34210 rs6000_declare_alias (struct symtab_node *n, void *d)
34212 struct declare_alias_data *data = (struct declare_alias_data *)d;
34213 /* Main symbol is output specially, because varasm machinery does part of
34214 the job for us - we do not need to declare .globl/lglobs and such. */
34215 if (!n->alias || n->weakref)
34218 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
34221 /* Prevent assemble_alias from trying to use .set pseudo operation
34222 that does not behave as expected by the middle-end. */
34223 TREE_ASM_WRITTEN (n->decl) = true;
34225 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
34226 char *buffer = (char *) alloca (strlen (name) + 2);
34228 int dollar_inside = 0;
34230 strcpy (buffer, name);
34231 p = strchr (buffer, '$');
34235 p = strchr (p + 1, '$');
34237 if (TREE_PUBLIC (n->decl))
34239 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
34241 if (dollar_inside) {
34242 if (data->function_descriptor)
34243 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34244 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34246 if (data->function_descriptor)
34248 fputs ("\t.globl .", data->file);
34249 RS6000_OUTPUT_BASENAME (data->file, buffer);
34250 putc ('\n', data->file);
34252 fputs ("\t.globl ", data->file);
34253 RS6000_OUTPUT_BASENAME (data->file, buffer);
34254 putc ('\n', data->file);
34256 #ifdef ASM_WEAKEN_DECL
34257 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
34258 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
34265 if (data->function_descriptor)
34266 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34267 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34269 if (data->function_descriptor)
34271 fputs ("\t.lglobl .", data->file);
34272 RS6000_OUTPUT_BASENAME (data->file, buffer);
34273 putc ('\n', data->file);
34275 fputs ("\t.lglobl ", data->file);
34276 RS6000_OUTPUT_BASENAME (data->file, buffer);
34277 putc ('\n', data->file);
34279 if (data->function_descriptor)
34280 fputs (".", data->file);
34281 RS6000_OUTPUT_BASENAME (data->file, buffer);
34282 fputs (":\n", data->file);
34287 #ifdef HAVE_GAS_HIDDEN
34288 /* Helper function to calculate visibility of a DECL
34289 and return the value as a const string. */
34291 static const char *
34292 rs6000_xcoff_visibility (tree decl)
34294 static const char * const visibility_types[] = {
34295 "", ",protected", ",hidden", ",internal"
34298 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34300 if (TREE_CODE (decl) == FUNCTION_DECL
34301 && cgraph_node::get (decl)
34302 && cgraph_node::get (decl)->instrumentation_clone
34303 && cgraph_node::get (decl)->instrumented_version)
34304 vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
34306 return visibility_types[vis];
34311 /* This macro produces the initial definition of a function name.
34312 On the RS/6000, we need to place an extra '.' in the function name and
34313 output the function descriptor.
34314 Dollar signs are converted to underscores.
34316 The csect for the function will have already been created when
34317 text_section was selected. We do have to go back to that csect, however.
34319 The third and fourth parameters to the .function pseudo-op (16 and 044)
34320 are placeholders which no longer have any use.
34322 Because AIX assembler's .set command has unexpected semantics, we output
34323 all aliases as alternative labels in front of the definition. */
34326 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34328 char *buffer = (char *) alloca (strlen (name) + 1);
34330 int dollar_inside = 0;
34331 struct declare_alias_data data = {file, false};
34333 strcpy (buffer, name);
34334 p = strchr (buffer, '$');
34338 p = strchr (p + 1, '$');
34340 if (TREE_PUBLIC (decl))
34342 if (!RS6000_WEAK || !DECL_WEAK (decl))
34344 if (dollar_inside) {
34345 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34346 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34348 fputs ("\t.globl .", file);
34349 RS6000_OUTPUT_BASENAME (file, buffer);
34350 #ifdef HAVE_GAS_HIDDEN
34351 fputs (rs6000_xcoff_visibility (decl), file);
34358 if (dollar_inside) {
34359 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34360 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34362 fputs ("\t.lglobl .", file);
34363 RS6000_OUTPUT_BASENAME (file, buffer);
34366 fputs ("\t.csect ", file);
34367 RS6000_OUTPUT_BASENAME (file, buffer);
34368 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34369 RS6000_OUTPUT_BASENAME (file, buffer);
34370 fputs (":\n", file);
34371 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34373 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34374 RS6000_OUTPUT_BASENAME (file, buffer);
34375 fputs (", TOC[tc0], 0\n", file);
34377 switch_to_section (function_section (decl));
34379 RS6000_OUTPUT_BASENAME (file, buffer);
34380 fputs (":\n", file);
34381 data.function_descriptor = true;
34382 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34384 if (!DECL_IGNORED_P (decl))
34386 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34387 xcoffout_declare_function (file, decl, buffer);
34388 else if (write_symbols == DWARF2_DEBUG)
34390 name = (*targetm.strip_name_encoding) (name);
34391 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34398 /* Output assembly language to globalize a symbol from a DECL,
34399 possibly with visibility. */
34402 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34404 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34405 fputs (GLOBAL_ASM_OP, stream);
34406 RS6000_OUTPUT_BASENAME (stream, name);
34407 #ifdef HAVE_GAS_HIDDEN
34408 fputs (rs6000_xcoff_visibility (decl), stream);
34410 putc ('\n', stream);
34413 /* Output assembly language to define a symbol as COMMON from a DECL,
34414 possibly with visibility. */
34417 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34418 tree decl ATTRIBUTE_UNUSED,
34420 unsigned HOST_WIDE_INT size,
34421 unsigned HOST_WIDE_INT align)
34423 unsigned HOST_WIDE_INT align2 = 2;
34426 align2 = floor_log2 (align / BITS_PER_UNIT);
34430 fputs (COMMON_ASM_OP, stream);
34431 RS6000_OUTPUT_BASENAME (stream, name);
34434 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34437 #ifdef HAVE_GAS_HIDDEN
34439 fputs (rs6000_xcoff_visibility (decl), stream);
34441 putc ('\n', stream);
34444 /* This macro produces the initial definition of a object (variable) name.
34445 Because AIX assembler's .set command has unexpected semantics, we output
34446 all aliases as alternative labels in front of the definition. */
34449 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34451 struct declare_alias_data data = {file, false};
34452 RS6000_OUTPUT_BASENAME (file, name);
34453 fputs (":\n", file);
34454 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34458 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34461 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34463 fputs (integer_asm_op (size, FALSE), file);
34464 assemble_name (file, label);
34465 fputs ("-$", file);
34468 /* Output a symbol offset relative to the dbase for the current object.
34469 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34472 __gcc_unwind_dbase is embedded in all executables/libraries through
34473 libgcc/config/rs6000/crtdbase.S. */
34476 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34478 fputs (integer_asm_op (size, FALSE), file);
34479 assemble_name (file, label);
34480 fputs("-__gcc_unwind_dbase", file);
34485 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34489 const char *symname;
34491 default_encode_section_info (decl, rtl, first);
34493 /* Careful not to prod global register variables. */
34496 symbol = XEXP (rtl, 0);
34497 if (GET_CODE (symbol) != SYMBOL_REF)
34500 flags = SYMBOL_REF_FLAGS (symbol);
34502 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34503 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34505 SYMBOL_REF_FLAGS (symbol) = flags;
34507 /* Append mapping class to extern decls. */
34508 symname = XSTR (symbol, 0);
34509 if (decl /* sync condition with assemble_external () */
34510 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34511 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34512 || TREE_CODE (decl) == FUNCTION_DECL)
34513 && symname[strlen (symname) - 1] != ']')
34515 char *newname = (char *) alloca (strlen (symname) + 5);
34516 strcpy (newname, symname);
34517 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34518 ? "[DS]" : "[UA]"));
34519 XSTR (symbol, 0) = ggc_strdup (newname);
34522 #endif /* HAVE_AS_TLS */
34523 #endif /* TARGET_XCOFF */
34526 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34527 const char *name, const char *val)
34529 fputs ("\t.weak\t", stream);
34530 RS6000_OUTPUT_BASENAME (stream, name);
34531 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34532 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34535 fputs ("[DS]", stream);
34536 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34538 fputs (rs6000_xcoff_visibility (decl), stream);
34540 fputs ("\n\t.weak\t.", stream);
34541 RS6000_OUTPUT_BASENAME (stream, name);
34543 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34545 fputs (rs6000_xcoff_visibility (decl), stream);
34547 fputc ('\n', stream);
34550 #ifdef ASM_OUTPUT_DEF
34551 ASM_OUTPUT_DEF (stream, name, val);
34553 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34554 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34556 fputs ("\t.set\t.", stream);
34557 RS6000_OUTPUT_BASENAME (stream, name);
34558 fputs (",.", stream);
34559 RS6000_OUTPUT_BASENAME (stream, val);
34560 fputc ('\n', stream);
34566 /* Return true if INSN should not be copied. */
34569 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34571 return recog_memoized (insn) >= 0
34572 && get_attr_cannot_copy (insn);
34575 /* Compute a (partial) cost for rtx X. Return true if the complete
34576 cost has been computed, and false if subexpressions should be
34577 scanned. In either case, *TOTAL contains the cost result. */
34580 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34581 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34583 int code = GET_CODE (x);
34587 /* On the RS/6000, if it is valid in the insn, it is free. */
34589 if (((outer_code == SET
34590 || outer_code == PLUS
34591 || outer_code == MINUS)
34592 && (satisfies_constraint_I (x)
34593 || satisfies_constraint_L (x)))
34594 || (outer_code == AND
34595 && (satisfies_constraint_K (x)
34597 ? satisfies_constraint_L (x)
34598 : satisfies_constraint_J (x))))
34599 || ((outer_code == IOR || outer_code == XOR)
34600 && (satisfies_constraint_K (x)
34602 ? satisfies_constraint_L (x)
34603 : satisfies_constraint_J (x))))
34604 || outer_code == ASHIFT
34605 || outer_code == ASHIFTRT
34606 || outer_code == LSHIFTRT
34607 || outer_code == ROTATE
34608 || outer_code == ROTATERT
34609 || outer_code == ZERO_EXTRACT
34610 || (outer_code == MULT
34611 && satisfies_constraint_I (x))
34612 || ((outer_code == DIV || outer_code == UDIV
34613 || outer_code == MOD || outer_code == UMOD)
34614 && exact_log2 (INTVAL (x)) >= 0)
34615 || (outer_code == COMPARE
34616 && (satisfies_constraint_I (x)
34617 || satisfies_constraint_K (x)))
34618 || ((outer_code == EQ || outer_code == NE)
34619 && (satisfies_constraint_I (x)
34620 || satisfies_constraint_K (x)
34622 ? satisfies_constraint_L (x)
34623 : satisfies_constraint_J (x))))
34624 || (outer_code == GTU
34625 && satisfies_constraint_I (x))
34626 || (outer_code == LTU
34627 && satisfies_constraint_P (x)))
34632 else if ((outer_code == PLUS
34633 && reg_or_add_cint_operand (x, VOIDmode))
34634 || (outer_code == MINUS
34635 && reg_or_sub_cint_operand (x, VOIDmode))
34636 || ((outer_code == SET
34637 || outer_code == IOR
34638 || outer_code == XOR)
34640 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34642 *total = COSTS_N_INSNS (1);
34648 case CONST_WIDE_INT:
34652 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34656 /* When optimizing for size, MEM should be slightly more expensive
34657 than generating address, e.g., (plus (reg) (const)).
34658 L1 cache latency is about two instructions. */
34659 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34660 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34661 *total += COSTS_N_INSNS (100);
34670 if (FLOAT_MODE_P (mode))
34671 *total = rs6000_cost->fp;
34673 *total = COSTS_N_INSNS (1);
34677 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34678 && satisfies_constraint_I (XEXP (x, 1)))
34680 if (INTVAL (XEXP (x, 1)) >= -256
34681 && INTVAL (XEXP (x, 1)) <= 255)
34682 *total = rs6000_cost->mulsi_const9;
34684 *total = rs6000_cost->mulsi_const;
34686 else if (mode == SFmode)
34687 *total = rs6000_cost->fp;
34688 else if (FLOAT_MODE_P (mode))
34689 *total = rs6000_cost->dmul;
34690 else if (mode == DImode)
34691 *total = rs6000_cost->muldi;
34693 *total = rs6000_cost->mulsi;
34697 if (mode == SFmode)
34698 *total = rs6000_cost->fp;
34700 *total = rs6000_cost->dmul;
34705 if (FLOAT_MODE_P (mode))
34707 *total = mode == DFmode ? rs6000_cost->ddiv
34708 : rs6000_cost->sdiv;
34715 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34716 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34718 if (code == DIV || code == MOD)
34720 *total = COSTS_N_INSNS (2);
34723 *total = COSTS_N_INSNS (1);
34727 if (GET_MODE (XEXP (x, 1)) == DImode)
34728 *total = rs6000_cost->divdi;
34730 *total = rs6000_cost->divsi;
34732 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34733 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34734 *total += COSTS_N_INSNS (2);
34738 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34742 *total = COSTS_N_INSNS (4);
34746 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34750 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34754 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34757 *total = COSTS_N_INSNS (1);
34761 if (CONST_INT_P (XEXP (x, 1)))
34763 rtx left = XEXP (x, 0);
34764 rtx_code left_code = GET_CODE (left);
34766 /* rotate-and-mask: 1 insn. */
34767 if ((left_code == ROTATE
34768 || left_code == ASHIFT
34769 || left_code == LSHIFTRT)
34770 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34772 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34773 if (!CONST_INT_P (XEXP (left, 1)))
34774 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34775 *total += COSTS_N_INSNS (1);
34779 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34780 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34781 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34782 || (val & 0xffff) == val
34783 || (val & 0xffff0000) == val
34784 || ((val & 0xffff) == 0 && mode == SImode))
34786 *total = rtx_cost (left, mode, AND, 0, speed);
34787 *total += COSTS_N_INSNS (1);
34792 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34794 *total = rtx_cost (left, mode, AND, 0, speed);
34795 *total += COSTS_N_INSNS (2);
34800 *total = COSTS_N_INSNS (1);
34805 *total = COSTS_N_INSNS (1);
34811 *total = COSTS_N_INSNS (1);
34815 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34816 the sign extend and shift separately within the insn. */
34817 if (TARGET_EXTSWSLI && mode == DImode
34818 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34819 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34830 /* Handle mul_highpart. */
34831 if (outer_code == TRUNCATE
34832 && GET_CODE (XEXP (x, 0)) == MULT)
34834 if (mode == DImode)
34835 *total = rs6000_cost->muldi;
34837 *total = rs6000_cost->mulsi;
34840 else if (outer_code == AND)
34843 *total = COSTS_N_INSNS (1);
34848 if (GET_CODE (XEXP (x, 0)) == MEM)
34851 *total = COSTS_N_INSNS (1);
34857 if (!FLOAT_MODE_P (mode))
34859 *total = COSTS_N_INSNS (1);
34865 case UNSIGNED_FLOAT:
34868 case FLOAT_TRUNCATE:
34869 *total = rs6000_cost->fp;
34873 if (mode == DFmode)
34874 *total = rs6000_cost->sfdf_convert;
34876 *total = rs6000_cost->fp;
34880 switch (XINT (x, 1))
34883 *total = rs6000_cost->fp;
34895 *total = COSTS_N_INSNS (1);
34898 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34900 *total = rs6000_cost->fp;
34909 /* Carry bit requires mode == Pmode.
34910 NEG or PLUS already counted so only add one. */
34912 && (outer_code == NEG || outer_code == PLUS))
34914 *total = COSTS_N_INSNS (1);
34922 if (outer_code == SET)
34924 if (XEXP (x, 1) == const0_rtx)
34926 *total = COSTS_N_INSNS (2);
34931 *total = COSTS_N_INSNS (3);
34936 if (outer_code == COMPARE)
34950 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34953 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34954 int opno, int *total, bool speed)
34956 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34959 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34960 "opno = %d, total = %d, speed = %s, x:\n",
34961 ret ? "complete" : "scan inner",
34962 GET_MODE_NAME (mode),
34963 GET_RTX_NAME (outer_code),
34966 speed ? "true" : "false");
34974 rs6000_insn_cost (rtx_insn *insn, bool speed)
34976 if (recog_memoized (insn) < 0)
34980 return get_attr_length (insn);
34982 int cost = get_attr_cost (insn);
34986 int n = get_attr_length (insn) / 4;
34987 enum attr_type type = get_attr_type (insn);
34994 cost = COSTS_N_INSNS (n + 1);
34998 switch (get_attr_size (insn))
35001 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
35004 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
35007 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
35010 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
35013 gcc_unreachable ();
35017 switch (get_attr_size (insn))
35020 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
35023 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
35026 gcc_unreachable ();
35031 cost = n * rs6000_cost->fp;
35034 cost = n * rs6000_cost->dmul;
35037 cost = n * rs6000_cost->sdiv;
35040 cost = n * rs6000_cost->ddiv;
35047 cost = COSTS_N_INSNS (n + 2);
35051 cost = COSTS_N_INSNS (n);
35057 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35060 rs6000_debug_address_cost (rtx x, machine_mode mode,
35061 addr_space_t as, bool speed)
35063 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
35065 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35066 ret, speed ? "true" : "false");
35073 /* A C expression returning the cost of moving data from a register of class
35074 CLASS1 to one of CLASS2. */
35077 rs6000_register_move_cost (machine_mode mode,
35078 reg_class_t from, reg_class_t to)
35082 if (TARGET_DEBUG_COST)
35085 /* Moves from/to GENERAL_REGS. */
35086 if (reg_classes_intersect_p (to, GENERAL_REGS)
35087 || reg_classes_intersect_p (from, GENERAL_REGS))
35089 reg_class_t rclass = from;
35091 if (! reg_classes_intersect_p (to, GENERAL_REGS))
35094 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
35095 ret = (rs6000_memory_move_cost (mode, rclass, false)
35096 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
35098 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35100 else if (rclass == CR_REGS)
35103 /* For those processors that have slow LR/CTR moves, make them more
35104 expensive than memory in order to bias spills to memory .*/
35105 else if ((rs6000_tune == PROCESSOR_POWER6
35106 || rs6000_tune == PROCESSOR_POWER7
35107 || rs6000_tune == PROCESSOR_POWER8
35108 || rs6000_tune == PROCESSOR_POWER9)
35109 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
35110 ret = 6 * hard_regno_nregs (0, mode);
35113 /* A move will cost one instruction per GPR moved. */
35114 ret = 2 * hard_regno_nregs (0, mode);
35117 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35118 else if (VECTOR_MEM_VSX_P (mode)
35119 && reg_classes_intersect_p (to, VSX_REGS)
35120 && reg_classes_intersect_p (from, VSX_REGS))
35121 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
35123 /* Moving between two similar registers is just one instruction. */
35124 else if (reg_classes_intersect_p (to, from))
35125 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
35127 /* Everything else has to go through GENERAL_REGS. */
35129 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
35130 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
35132 if (TARGET_DEBUG_COST)
35134 if (dbg_cost_ctrl == 1)
35136 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
35137 ret, GET_MODE_NAME (mode), reg_class_names[from],
35138 reg_class_names[to]);
35145 /* A C expressions returning the cost of moving data of MODE from a register to
35149 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
35150 bool in ATTRIBUTE_UNUSED)
35154 if (TARGET_DEBUG_COST)
35157 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
35158 ret = 4 * hard_regno_nregs (0, mode);
35159 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
35160 || reg_classes_intersect_p (rclass, VSX_REGS)))
35161 ret = 4 * hard_regno_nregs (32, mode);
35162 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
35163 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
35165 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
35167 if (TARGET_DEBUG_COST)
35169 if (dbg_cost_ctrl == 1)
35171 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35172 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
35179 /* Returns a code for a target-specific builtin that implements
35180 reciprocal of the function, or NULL_TREE if not available. */
35183 rs6000_builtin_reciprocal (tree fndecl)
35185 switch (DECL_FUNCTION_CODE (fndecl))
35187 case VSX_BUILTIN_XVSQRTDP:
35188 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
35191 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
35193 case VSX_BUILTIN_XVSQRTSP:
35194 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
35197 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
35204 /* Load up a constant. If the mode is a vector mode, splat the value across
35205 all of the vector elements. */
35208 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
35212 if (mode == SFmode || mode == DFmode)
35214 rtx d = const_double_from_real_value (dconst, mode);
35215 reg = force_reg (mode, d);
35217 else if (mode == V4SFmode)
35219 rtx d = const_double_from_real_value (dconst, SFmode);
35220 rtvec v = gen_rtvec (4, d, d, d, d);
35221 reg = gen_reg_rtx (mode);
35222 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35224 else if (mode == V2DFmode)
35226 rtx d = const_double_from_real_value (dconst, DFmode);
35227 rtvec v = gen_rtvec (2, d, d);
35228 reg = gen_reg_rtx (mode);
35229 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35232 gcc_unreachable ();
35237 /* Generate an FMA instruction. */
35240 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35242 machine_mode mode = GET_MODE (target);
35245 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35246 gcc_assert (dst != NULL);
35249 emit_move_insn (target, dst);
35252 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35255 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35257 machine_mode mode = GET_MODE (dst);
35260 /* This is a tad more complicated, since the fnma_optab is for
35261 a different expression: fma(-m1, m2, a), which is the same
35262 thing except in the case of signed zeros.
35264 Fortunately we know that if FMA is supported that FNMSUB is
35265 also supported in the ISA. Just expand it directly. */
35267 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35269 r = gen_rtx_NEG (mode, a);
35270 r = gen_rtx_FMA (mode, m1, m2, r);
35271 r = gen_rtx_NEG (mode, r);
35272 emit_insn (gen_rtx_SET (dst, r));
35275 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35276 add a reg_note saying that this was a division. Support both scalar and
35277 vector divide. Assumes no trapping math and finite arguments. */
35280 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35282 machine_mode mode = GET_MODE (dst);
35283 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35286 /* Low precision estimates guarantee 5 bits of accuracy. High
35287 precision estimates guarantee 14 bits of accuracy. SFmode
35288 requires 23 bits of accuracy. DFmode requires 52 bits of
35289 accuracy. Each pass at least doubles the accuracy, leading
35290 to the following. */
35291 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35292 if (mode == DFmode || mode == V2DFmode)
35295 enum insn_code code = optab_handler (smul_optab, mode);
35296 insn_gen_fn gen_mul = GEN_FCN (code);
35298 gcc_assert (code != CODE_FOR_nothing);
35300 one = rs6000_load_constant_and_splat (mode, dconst1);
35302 /* x0 = 1./d estimate */
35303 x0 = gen_reg_rtx (mode);
35304 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35307 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35310 /* e0 = 1. - d * x0 */
35311 e0 = gen_reg_rtx (mode);
35312 rs6000_emit_nmsub (e0, d, x0, one);
35314 /* x1 = x0 + e0 * x0 */
35315 x1 = gen_reg_rtx (mode);
35316 rs6000_emit_madd (x1, e0, x0, x0);
35318 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35319 ++i, xprev = xnext, eprev = enext) {
35321 /* enext = eprev * eprev */
35322 enext = gen_reg_rtx (mode);
35323 emit_insn (gen_mul (enext, eprev, eprev));
35325 /* xnext = xprev + enext * xprev */
35326 xnext = gen_reg_rtx (mode);
35327 rs6000_emit_madd (xnext, enext, xprev, xprev);
35333 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35335 /* u = n * xprev */
35336 u = gen_reg_rtx (mode);
35337 emit_insn (gen_mul (u, n, xprev));
35339 /* v = n - (d * u) */
35340 v = gen_reg_rtx (mode);
35341 rs6000_emit_nmsub (v, d, u, n);
35343 /* dst = (v * xprev) + u */
35344 rs6000_emit_madd (dst, v, xprev, u);
35347 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35350 /* Goldschmidt's Algorithm for single/double-precision floating point
35351 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35354 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35356 machine_mode mode = GET_MODE (src);
35357 rtx e = gen_reg_rtx (mode);
35358 rtx g = gen_reg_rtx (mode);
35359 rtx h = gen_reg_rtx (mode);
35361 /* Low precision estimates guarantee 5 bits of accuracy. High
35362 precision estimates guarantee 14 bits of accuracy. SFmode
35363 requires 23 bits of accuracy. DFmode requires 52 bits of
35364 accuracy. Each pass at least doubles the accuracy, leading
35365 to the following. */
35366 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35367 if (mode == DFmode || mode == V2DFmode)
35372 enum insn_code code = optab_handler (smul_optab, mode);
35373 insn_gen_fn gen_mul = GEN_FCN (code);
35375 gcc_assert (code != CODE_FOR_nothing);
35377 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35379 /* e = rsqrt estimate */
35380 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35383 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35386 rtx zero = force_reg (mode, CONST0_RTX (mode));
35388 if (mode == SFmode)
35390 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35393 emit_move_insn (e, target);
35397 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35398 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35402 /* g = sqrt estimate. */
35403 emit_insn (gen_mul (g, e, src));
35404 /* h = 1/(2*sqrt) estimate. */
35405 emit_insn (gen_mul (h, e, mhalf));
35411 rtx t = gen_reg_rtx (mode);
35412 rs6000_emit_nmsub (t, g, h, mhalf);
35413 /* Apply correction directly to 1/rsqrt estimate. */
35414 rs6000_emit_madd (dst, e, t, e);
35418 for (i = 0; i < passes; i++)
35420 rtx t1 = gen_reg_rtx (mode);
35421 rtx g1 = gen_reg_rtx (mode);
35422 rtx h1 = gen_reg_rtx (mode);
35424 rs6000_emit_nmsub (t1, g, h, mhalf);
35425 rs6000_emit_madd (g1, g, t1, g);
35426 rs6000_emit_madd (h1, h, t1, h);
35431 /* Multiply by 2 for 1/rsqrt. */
35432 emit_insn (gen_add3_insn (dst, h, h));
35437 rtx t = gen_reg_rtx (mode);
35438 rs6000_emit_nmsub (t, g, h, mhalf);
35439 rs6000_emit_madd (dst, g, t, g);
35445 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35446 (Power7) targets. DST is the target, and SRC is the argument operand. */
35449 rs6000_emit_popcount (rtx dst, rtx src)
35451 machine_mode mode = GET_MODE (dst);
35454 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35455 if (TARGET_POPCNTD)
35457 if (mode == SImode)
35458 emit_insn (gen_popcntdsi2 (dst, src));
35460 emit_insn (gen_popcntddi2 (dst, src));
35464 tmp1 = gen_reg_rtx (mode);
35466 if (mode == SImode)
35468 emit_insn (gen_popcntbsi2 (tmp1, src));
35469 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35471 tmp2 = force_reg (SImode, tmp2);
35472 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35476 emit_insn (gen_popcntbdi2 (tmp1, src));
35477 tmp2 = expand_mult (DImode, tmp1,
35478 GEN_INT ((HOST_WIDE_INT)
35479 0x01010101 << 32 | 0x01010101),
35481 tmp2 = force_reg (DImode, tmp2);
35482 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35487 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35488 target, and SRC is the argument operand. */
35491 rs6000_emit_parity (rtx dst, rtx src)
35493 machine_mode mode = GET_MODE (dst);
35496 tmp = gen_reg_rtx (mode);
35498 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35501 if (mode == SImode)
35503 emit_insn (gen_popcntbsi2 (tmp, src));
35504 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35508 emit_insn (gen_popcntbdi2 (tmp, src));
35509 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35514 if (mode == SImode)
35516 /* Is mult+shift >= shift+xor+shift+xor? */
35517 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35519 rtx tmp1, tmp2, tmp3, tmp4;
35521 tmp1 = gen_reg_rtx (SImode);
35522 emit_insn (gen_popcntbsi2 (tmp1, src));
35524 tmp2 = gen_reg_rtx (SImode);
35525 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35526 tmp3 = gen_reg_rtx (SImode);
35527 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35529 tmp4 = gen_reg_rtx (SImode);
35530 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35531 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35534 rs6000_emit_popcount (tmp, src);
35535 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35539 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35540 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35542 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35544 tmp1 = gen_reg_rtx (DImode);
35545 emit_insn (gen_popcntbdi2 (tmp1, src));
35547 tmp2 = gen_reg_rtx (DImode);
35548 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35549 tmp3 = gen_reg_rtx (DImode);
35550 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35552 tmp4 = gen_reg_rtx (DImode);
35553 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35554 tmp5 = gen_reg_rtx (DImode);
35555 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35557 tmp6 = gen_reg_rtx (DImode);
35558 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35559 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35562 rs6000_emit_popcount (tmp, src);
35563 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35567 /* Expand an Altivec constant permutation for little endian mode.
35568 OP0 and OP1 are the input vectors and TARGET is the output vector.
35569 SEL specifies the constant permutation vector.
35571 There are two issues: First, the two input operands must be
35572 swapped so that together they form a double-wide array in LE
35573 order. Second, the vperm instruction has surprising behavior
35574 in LE mode: it interprets the elements of the source vectors
35575 in BE mode ("left to right") and interprets the elements of
35576 the destination vector in LE mode ("right to left"). To
35577 correct for this, we must subtract each element of the permute
35578 control vector from 31.
35580 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35581 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35582 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35583 serve as the permute control vector. Then, in BE mode,
35587 places the desired result in vr9. However, in LE mode the
35588 vector contents will be
35590 vr10 = 00000003 00000002 00000001 00000000
35591 vr11 = 00000007 00000006 00000005 00000004
35593 The result of the vperm using the same permute control vector is
35595 vr9 = 05000000 07000000 01000000 03000000
35597 That is, the leftmost 4 bytes of vr10 are interpreted as the
35598 source for the rightmost 4 bytes of vr9, and so on.
35600 If we change the permute control vector to
35602 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35610 vr9 = 00000006 00000004 00000002 00000000. */
35613 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35614 const vec_perm_indices &sel)
35618 rtx constv, unspec;
35620 /* Unpack and adjust the constant selector. */
35621 for (i = 0; i < 16; ++i)
35623 unsigned int elt = 31 - (sel[i] & 31);
35624 perm[i] = GEN_INT (elt);
35627 /* Expand to a permute, swapping the inputs and using the
35628 adjusted selector. */
35630 op0 = force_reg (V16QImode, op0);
35632 op1 = force_reg (V16QImode, op1);
35634 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35635 constv = force_reg (V16QImode, constv);
35636 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35638 if (!REG_P (target))
35640 rtx tmp = gen_reg_rtx (V16QImode);
35641 emit_move_insn (tmp, unspec);
35645 emit_move_insn (target, unspec);
35648 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35649 permute control vector. But here it's not a constant, so we must
35650 generate a vector NAND or NOR to do the adjustment. */
35653 altivec_expand_vec_perm_le (rtx operands[4])
35655 rtx notx, iorx, unspec;
35656 rtx target = operands[0];
35657 rtx op0 = operands[1];
35658 rtx op1 = operands[2];
35659 rtx sel = operands[3];
35661 rtx norreg = gen_reg_rtx (V16QImode);
35662 machine_mode mode = GET_MODE (target);
35664 /* Get everything in regs so the pattern matches. */
35666 op0 = force_reg (mode, op0);
35668 op1 = force_reg (mode, op1);
35670 sel = force_reg (V16QImode, sel);
35671 if (!REG_P (target))
35672 tmp = gen_reg_rtx (mode);
35674 if (TARGET_P9_VECTOR)
35676 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35681 /* Invert the selector with a VNAND if available, else a VNOR.
35682 The VNAND is preferred for future fusion opportunities. */
35683 notx = gen_rtx_NOT (V16QImode, sel);
35684 iorx = (TARGET_P8_VECTOR
35685 ? gen_rtx_IOR (V16QImode, notx, notx)
35686 : gen_rtx_AND (V16QImode, notx, notx));
35687 emit_insn (gen_rtx_SET (norreg, iorx));
35689 /* Permute with operands reversed and adjusted selector. */
35690 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35694 /* Copy into target, possibly by way of a register. */
35695 if (!REG_P (target))
35697 emit_move_insn (tmp, unspec);
35701 emit_move_insn (target, unspec);
35704 /* Expand an Altivec constant permutation. Return true if we match
35705 an efficient implementation; false to fall back to VPERM.
35707 OP0 and OP1 are the input vectors and TARGET is the output vector.
35708 SEL specifies the constant permutation vector. */
35711 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35712 const vec_perm_indices &sel)
35714 struct altivec_perm_insn {
35715 HOST_WIDE_INT mask;
35716 enum insn_code impl;
35717 unsigned char perm[16];
35719 static const struct altivec_perm_insn patterns[] = {
35720 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35721 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35722 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35723 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35724 { OPTION_MASK_ALTIVEC,
35725 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35726 : CODE_FOR_altivec_vmrglb_direct),
35727 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35728 { OPTION_MASK_ALTIVEC,
35729 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35730 : CODE_FOR_altivec_vmrglh_direct),
35731 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35732 { OPTION_MASK_ALTIVEC,
35733 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35734 : CODE_FOR_altivec_vmrglw_direct),
35735 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35736 { OPTION_MASK_ALTIVEC,
35737 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35738 : CODE_FOR_altivec_vmrghb_direct),
35739 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35740 { OPTION_MASK_ALTIVEC,
35741 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35742 : CODE_FOR_altivec_vmrghh_direct),
35743 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35744 { OPTION_MASK_ALTIVEC,
35745 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35746 : CODE_FOR_altivec_vmrghw_direct),
35747 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35748 { OPTION_MASK_P8_VECTOR,
35749 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35750 : CODE_FOR_p8_vmrgow_v4sf_direct),
35751 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35752 { OPTION_MASK_P8_VECTOR,
35753 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35754 : CODE_FOR_p8_vmrgew_v4sf_direct),
35755 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35758 unsigned int i, j, elt, which;
35759 unsigned char perm[16];
35763 /* Unpack the constant selector. */
35764 for (i = which = 0; i < 16; ++i)
35767 which |= (elt < 16 ? 1 : 2);
35771 /* Simplify the constant selector based on operands. */
35775 gcc_unreachable ();
35779 if (!rtx_equal_p (op0, op1))
35784 for (i = 0; i < 16; ++i)
35796 /* Look for splat patterns. */
35801 for (i = 0; i < 16; ++i)
35802 if (perm[i] != elt)
35806 if (!BYTES_BIG_ENDIAN)
35808 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35814 for (i = 0; i < 16; i += 2)
35815 if (perm[i] != elt || perm[i + 1] != elt + 1)
35819 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35820 x = gen_reg_rtx (V8HImode);
35821 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35823 emit_move_insn (target, gen_lowpart (V16QImode, x));
35830 for (i = 0; i < 16; i += 4)
35832 || perm[i + 1] != elt + 1
35833 || perm[i + 2] != elt + 2
35834 || perm[i + 3] != elt + 3)
35838 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35839 x = gen_reg_rtx (V4SImode);
35840 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35842 emit_move_insn (target, gen_lowpart (V16QImode, x));
35848 /* Look for merge and pack patterns. */
35849 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35853 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35856 elt = patterns[j].perm[0];
35857 if (perm[0] == elt)
35859 else if (perm[0] == elt + 16)
35863 for (i = 1; i < 16; ++i)
35865 elt = patterns[j].perm[i];
35867 elt = (elt >= 16 ? elt - 16 : elt + 16);
35868 else if (one_vec && elt >= 16)
35870 if (perm[i] != elt)
35875 enum insn_code icode = patterns[j].impl;
35876 machine_mode omode = insn_data[icode].operand[0].mode;
35877 machine_mode imode = insn_data[icode].operand[1].mode;
35879 /* For little-endian, don't use vpkuwum and vpkuhum if the
35880 underlying vector type is not V4SI and V8HI, respectively.
35881 For example, using vpkuwum with a V8HI picks up the even
35882 halfwords (BE numbering) when the even halfwords (LE
35883 numbering) are what we need. */
35884 if (!BYTES_BIG_ENDIAN
35885 && icode == CODE_FOR_altivec_vpkuwum_direct
35886 && ((GET_CODE (op0) == REG
35887 && GET_MODE (op0) != V4SImode)
35888 || (GET_CODE (op0) == SUBREG
35889 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35891 if (!BYTES_BIG_ENDIAN
35892 && icode == CODE_FOR_altivec_vpkuhum_direct
35893 && ((GET_CODE (op0) == REG
35894 && GET_MODE (op0) != V8HImode)
35895 || (GET_CODE (op0) == SUBREG
35896 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35899 /* For little-endian, the two input operands must be swapped
35900 (or swapped back) to ensure proper right-to-left numbering
35902 if (swapped ^ !BYTES_BIG_ENDIAN)
35903 std::swap (op0, op1);
35904 if (imode != V16QImode)
35906 op0 = gen_lowpart (imode, op0);
35907 op1 = gen_lowpart (imode, op1);
35909 if (omode == V16QImode)
35912 x = gen_reg_rtx (omode);
35913 emit_insn (GEN_FCN (icode) (x, op0, op1));
35914 if (omode != V16QImode)
35915 emit_move_insn (target, gen_lowpart (V16QImode, x));
35920 if (!BYTES_BIG_ENDIAN)
35922 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35929 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
35930 Return true if we match an efficient implementation. */
35933 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35934 unsigned char perm0, unsigned char perm1)
35938 /* If both selectors come from the same operand, fold to single op. */
35939 if ((perm0 & 2) == (perm1 & 2))
35946 /* If both operands are equal, fold to simpler permutation. */
35947 if (rtx_equal_p (op0, op1))
35950 perm1 = (perm1 & 1) + 2;
35952 /* If the first selector comes from the second operand, swap. */
35953 else if (perm0 & 2)
35959 std::swap (op0, op1);
35961 /* If the second selector does not come from the second operand, fail. */
35962 else if ((perm1 & 2) == 0)
35966 if (target != NULL)
35968 machine_mode vmode, dmode;
35971 vmode = GET_MODE (target);
35972 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35973 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35974 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35975 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35976 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35977 emit_insn (gen_rtx_SET (target, x));
35982 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35985 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35986 rtx op1, const vec_perm_indices &sel)
35988 bool testing_p = !target;
35990 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35991 if (TARGET_ALTIVEC && testing_p)
35994 /* Check for ps_merge* or xxpermdi insns. */
35995 if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT)
35996 || ((vmode == V2DFmode || vmode == V2DImode)
35997 && VECTOR_MEM_VSX_P (vmode)))
36001 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
36002 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
36004 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
36008 if (TARGET_ALTIVEC)
36010 /* Force the target-independent code to lower to V16QImode. */
36011 if (vmode != V16QImode)
36013 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
36020 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
36021 OP0 and OP1 are the input vectors and TARGET is the output vector.
36022 PERM specifies the constant permutation vector. */
36025 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
36026 machine_mode vmode, const vec_perm_builder &perm)
36028 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
36030 emit_move_insn (target, x);
36033 /* Expand an extract even operation. */
36036 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
36038 machine_mode vmode = GET_MODE (target);
36039 unsigned i, nelt = GET_MODE_NUNITS (vmode);
36040 vec_perm_builder perm (nelt, nelt, 1);
36042 for (i = 0; i < nelt; i++)
36043 perm.quick_push (i * 2);
36045 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36048 /* Expand a vector interleave operation. */
36051 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
36053 machine_mode vmode = GET_MODE (target);
36054 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
36055 vec_perm_builder perm (nelt, nelt, 1);
36057 high = (highp ? 0 : nelt / 2);
36058 for (i = 0; i < nelt / 2; i++)
36060 perm.quick_push (i + high);
36061 perm.quick_push (i + nelt + high);
36064 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36067 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36069 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
36071 HOST_WIDE_INT hwi_scale (scale);
36072 REAL_VALUE_TYPE r_pow;
36073 rtvec v = rtvec_alloc (2);
36075 rtx scale_vec = gen_reg_rtx (V2DFmode);
36076 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
36077 elt = const_double_from_real_value (r_pow, DFmode);
36078 RTVEC_ELT (v, 0) = elt;
36079 RTVEC_ELT (v, 1) = elt;
36080 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
36081 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
36084 /* Return an RTX representing where to find the function value of a
36085 function returning MODE. */
36087 rs6000_complex_function_value (machine_mode mode)
36089 unsigned int regno;
36091 machine_mode inner = GET_MODE_INNER (mode);
36092 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
36094 if (TARGET_FLOAT128_TYPE
36096 || (mode == TCmode && TARGET_IEEEQUAD)))
36097 regno = ALTIVEC_ARG_RETURN;
36099 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36100 regno = FP_ARG_RETURN;
36104 regno = GP_ARG_RETURN;
36106 /* 32-bit is OK since it'll go in r3/r4. */
36107 if (TARGET_32BIT && inner_bytes >= 4)
36108 return gen_rtx_REG (mode, regno);
36111 if (inner_bytes >= 8)
36112 return gen_rtx_REG (mode, regno);
36114 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
36116 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
36117 GEN_INT (inner_bytes));
36118 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
36121 /* Return an rtx describing a return value of MODE as a PARALLEL
36122 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36123 stride REG_STRIDE. */
36126 rs6000_parallel_return (machine_mode mode,
36127 int n_elts, machine_mode elt_mode,
36128 unsigned int regno, unsigned int reg_stride)
36130 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
36133 for (i = 0; i < n_elts; i++)
36135 rtx r = gen_rtx_REG (elt_mode, regno);
36136 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
36137 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36138 regno += reg_stride;
36144 /* Target hook for TARGET_FUNCTION_VALUE.
36146 An integer value is in r3 and a floating-point value is in fp1,
36147 unless -msoft-float. */
36150 rs6000_function_value (const_tree valtype,
36151 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
36152 bool outgoing ATTRIBUTE_UNUSED)
36155 unsigned int regno;
36156 machine_mode elt_mode;
36159 /* Special handling for structs in darwin64. */
36161 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
36163 CUMULATIVE_ARGS valcum;
36167 valcum.fregno = FP_ARG_MIN_REG;
36168 valcum.vregno = ALTIVEC_ARG_MIN_REG;
36169 /* Do a trial code generation as if this were going to be passed as
36170 an argument; if any part goes in memory, we return NULL. */
36171 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
36174 /* Otherwise fall through to standard ABI rules. */
36177 mode = TYPE_MODE (valtype);
36179 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36180 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
36182 int first_reg, n_regs;
36184 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
36186 /* _Decimal128 must use even/odd register pairs. */
36187 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36188 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
36192 first_reg = ALTIVEC_ARG_RETURN;
36196 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
36199 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36200 if (TARGET_32BIT && TARGET_POWERPC64)
36209 int count = GET_MODE_SIZE (mode) / 4;
36210 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
36213 if ((INTEGRAL_TYPE_P (valtype)
36214 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
36215 || POINTER_TYPE_P (valtype))
36216 mode = TARGET_32BIT ? SImode : DImode;
36218 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36219 /* _Decimal128 must use an even/odd register pair. */
36220 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36221 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36222 && !FLOAT128_VECTOR_P (mode)
36223 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
36224 regno = FP_ARG_RETURN;
36225 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36226 && targetm.calls.split_complex_arg)
36227 return rs6000_complex_function_value (mode);
36228 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36229 return register is used in both cases, and we won't see V2DImode/V2DFmode
36230 for pure altivec, combine the two cases. */
36231 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36232 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36233 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36234 regno = ALTIVEC_ARG_RETURN;
36236 regno = GP_ARG_RETURN;
36238 return gen_rtx_REG (mode, regno);
36241 /* Define how to find the value returned by a library function
36242 assuming the value has mode MODE. */
36244 rs6000_libcall_value (machine_mode mode)
36246 unsigned int regno;
36248 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36249 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36250 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36252 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36253 /* _Decimal128 must use an even/odd register pair. */
36254 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36255 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
36256 && TARGET_HARD_FLOAT
36257 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
36258 regno = FP_ARG_RETURN;
36259 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36260 return register is used in both cases, and we won't see V2DImode/V2DFmode
36261 for pure altivec, combine the two cases. */
36262 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36263 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36264 regno = ALTIVEC_ARG_RETURN;
36265 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36266 return rs6000_complex_function_value (mode);
36268 regno = GP_ARG_RETURN;
36270 return gen_rtx_REG (mode, regno);
36273 /* Compute register pressure classes. We implement the target hook to avoid
36274 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
36275 lead to incorrect estimates of number of available registers and therefor
36276 increased register pressure/spill. */
36278 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36283 pressure_classes[n++] = GENERAL_REGS;
36285 pressure_classes[n++] = VSX_REGS;
36288 if (TARGET_ALTIVEC)
36289 pressure_classes[n++] = ALTIVEC_REGS;
36290 if (TARGET_HARD_FLOAT)
36291 pressure_classes[n++] = FLOAT_REGS;
36293 pressure_classes[n++] = CR_REGS;
36294 pressure_classes[n++] = SPECIAL_REGS;
36299 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36300 Frame pointer elimination is automatically handled.
36302 For the RS/6000, if frame pointer elimination is being done, we would like
36303 to convert ap into fp, not sp.
36305 We need r30 if -mminimal-toc was specified, and there are constant pool
36309 rs6000_can_eliminate (const int from, const int to)
36311 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36312 ? ! frame_pointer_needed
36313 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36314 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36315 || constant_pool_empty_p ()
36319 /* Define the offset between two registers, FROM to be eliminated and its
36320 replacement TO, at the start of a routine. */
36322 rs6000_initial_elimination_offset (int from, int to)
36324 rs6000_stack_t *info = rs6000_stack_info ();
36325 HOST_WIDE_INT offset;
36327 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36328 offset = info->push_p ? 0 : -info->total_size;
36329 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36331 offset = info->push_p ? 0 : -info->total_size;
36332 if (FRAME_GROWS_DOWNWARD)
36333 offset += info->fixed_size + info->vars_size + info->parm_size;
36335 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36336 offset = FRAME_GROWS_DOWNWARD
36337 ? info->fixed_size + info->vars_size + info->parm_size
36339 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36340 offset = info->total_size;
36341 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36342 offset = info->push_p ? info->total_size : 0;
36343 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36346 gcc_unreachable ();
36351 /* Fill in sizes of registers used by unwinder. */
36354 rs6000_init_dwarf_reg_sizes_extra (tree address)
36356 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36359 machine_mode mode = TYPE_MODE (char_type_node);
36360 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36361 rtx mem = gen_rtx_MEM (BLKmode, addr);
36362 rtx value = gen_int_mode (16, mode);
36364 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36365 The unwinder still needs to know the size of Altivec registers. */
36367 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36369 int column = DWARF_REG_TO_UNWIND_COLUMN
36370 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36371 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36373 emit_move_insn (adjust_address (mem, mode, offset), value);
36378 /* Map internal gcc register numbers to debug format register numbers.
36379 FORMAT specifies the type of debug register number to use:
36380 0 -- debug information, except for frame-related sections
36381 1 -- DWARF .debug_frame section
36382 2 -- DWARF .eh_frame section */
36385 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36387 /* Except for the above, we use the internal number for non-DWARF
36388 debug information, and also for .eh_frame. */
36389 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
36392 /* On some platforms, we use the standard DWARF register
36393 numbering for .debug_info and .debug_frame. */
36394 #ifdef RS6000_USE_DWARF_NUMBERING
36397 if (regno == LR_REGNO)
36399 if (regno == CTR_REGNO)
36401 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36402 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36403 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36404 to the DWARF reg for CR. */
36405 if (format == 1 && regno == CR2_REGNO)
36407 if (CR_REGNO_P (regno))
36408 return regno - CR0_REGNO + 86;
36409 if (regno == CA_REGNO)
36410 return 101; /* XER */
36411 if (ALTIVEC_REGNO_P (regno))
36412 return regno - FIRST_ALTIVEC_REGNO + 1124;
36413 if (regno == VRSAVE_REGNO)
36415 if (regno == VSCR_REGNO)
36421 /* target hook eh_return_filter_mode */
36422 static scalar_int_mode
36423 rs6000_eh_return_filter_mode (void)
36425 return TARGET_32BIT ? SImode : word_mode;
36428 /* Target hook for scalar_mode_supported_p. */
36430 rs6000_scalar_mode_supported_p (scalar_mode mode)
36432 /* -m32 does not support TImode. This is the default, from
36433 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36434 same ABI as for -m32. But default_scalar_mode_supported_p allows
36435 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36436 for -mpowerpc64. */
36437 if (TARGET_32BIT && mode == TImode)
36440 if (DECIMAL_FLOAT_MODE_P (mode))
36441 return default_decimal_float_supported_p ();
36442 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36445 return default_scalar_mode_supported_p (mode);
36448 /* Target hook for vector_mode_supported_p. */
36450 rs6000_vector_mode_supported_p (machine_mode mode)
36453 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
36456 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36457 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36459 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36466 /* Target hook for floatn_mode. */
36467 static opt_scalar_float_mode
36468 rs6000_floatn_mode (int n, bool extended)
36478 if (TARGET_FLOAT128_TYPE)
36479 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36481 return opt_scalar_float_mode ();
36484 return opt_scalar_float_mode ();
36487 /* Those are the only valid _FloatNx types. */
36488 gcc_unreachable ();
36502 if (TARGET_FLOAT128_TYPE)
36503 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36505 return opt_scalar_float_mode ();
36508 return opt_scalar_float_mode ();
36514 /* Target hook for c_mode_for_suffix. */
36515 static machine_mode
36516 rs6000_c_mode_for_suffix (char suffix)
36518 if (TARGET_FLOAT128_TYPE)
36520 if (suffix == 'q' || suffix == 'Q')
36521 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36523 /* At the moment, we are not defining a suffix for IBM extended double.
36524 If/when the default for -mabi=ieeelongdouble is changed, and we want
36525 to support __ibm128 constants in legacy library code, we may need to
36526 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36527 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36528 __float80 constants. */
36534 /* Target hook for invalid_arg_for_unprototyped_fn. */
36535 static const char *
36536 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36538 return (!rs6000_darwin64_abi
36540 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36541 && (funcdecl == NULL_TREE
36542 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36543 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36544 ? N_("AltiVec argument passed to unprototyped function")
36548 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36549 setup by using __stack_chk_fail_local hidden function instead of
36550 calling __stack_chk_fail directly. Otherwise it is better to call
36551 __stack_chk_fail directly. */
36553 static tree ATTRIBUTE_UNUSED
36554 rs6000_stack_protect_fail (void)
36556 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36557 ? default_hidden_stack_protect_fail ()
36558 : default_external_stack_protect_fail ();
36561 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36564 static unsigned HOST_WIDE_INT
36565 rs6000_asan_shadow_offset (void)
36567 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36571 /* Mask options that we want to support inside of attribute((target)) and
36572 #pragma GCC target operations. Note, we do not include things like
36573 64/32-bit, endianness, hard/soft floating point, etc. that would have
36574 different calling sequences. */
36576 struct rs6000_opt_mask {
36577 const char *name; /* option name */
36578 HOST_WIDE_INT mask; /* mask to set */
36579 bool invert; /* invert sense of mask */
36580 bool valid_target; /* option is a target option */
36583 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36585 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36586 { "cmpb", OPTION_MASK_CMPB, false, true },
36587 { "crypto", OPTION_MASK_CRYPTO, false, true },
36588 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36589 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36590 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36592 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36593 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36594 { "fprnd", OPTION_MASK_FPRND, false, true },
36595 { "hard-dfp", OPTION_MASK_DFP, false, true },
36596 { "htm", OPTION_MASK_HTM, false, true },
36597 { "isel", OPTION_MASK_ISEL, false, true },
36598 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36599 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36600 { "modulo", OPTION_MASK_MODULO, false, true },
36601 { "mulhw", OPTION_MASK_MULHW, false, true },
36602 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36603 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36604 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36605 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36606 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36607 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36608 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
36609 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36610 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36611 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36612 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36613 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36614 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36615 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36616 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36617 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36618 { "string", 0, false, true },
36619 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
36620 { "update", OPTION_MASK_NO_UPDATE, true , true },
36621 { "vsx", OPTION_MASK_VSX, false, true },
36622 #ifdef OPTION_MASK_64BIT
36624 { "aix64", OPTION_MASK_64BIT, false, false },
36625 { "aix32", OPTION_MASK_64BIT, true, false },
36627 { "64", OPTION_MASK_64BIT, false, false },
36628 { "32", OPTION_MASK_64BIT, true, false },
36631 #ifdef OPTION_MASK_EABI
36632 { "eabi", OPTION_MASK_EABI, false, false },
36634 #ifdef OPTION_MASK_LITTLE_ENDIAN
36635 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36636 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36638 #ifdef OPTION_MASK_RELOCATABLE
36639 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36641 #ifdef OPTION_MASK_STRICT_ALIGN
36642 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36644 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36645 { "string", 0, false, false },
36648 /* Builtin mask mapping for printing the flags. */
36649 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36651 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36652 { "vsx", RS6000_BTM_VSX, false, false },
36653 { "paired", RS6000_BTM_PAIRED, false, false },
36654 { "fre", RS6000_BTM_FRE, false, false },
36655 { "fres", RS6000_BTM_FRES, false, false },
36656 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36657 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36658 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36659 { "cell", RS6000_BTM_CELL, false, false },
36660 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36661 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36662 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36663 { "crypto", RS6000_BTM_CRYPTO, false, false },
36664 { "htm", RS6000_BTM_HTM, false, false },
36665 { "hard-dfp", RS6000_BTM_DFP, false, false },
36666 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36667 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36668 { "float128", RS6000_BTM_FLOAT128, false, false },
36669 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36672 /* Option variables that we want to support inside attribute((target)) and
36673 #pragma GCC target operations. */
36675 struct rs6000_opt_var {
36676 const char *name; /* option name */
36677 size_t global_offset; /* offset of the option in global_options. */
36678 size_t target_offset; /* offset of the option in target options. */
36681 static struct rs6000_opt_var const rs6000_opt_vars[] =
36684 offsetof (struct gcc_options, x_TARGET_FRIZ),
36685 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36686 { "avoid-indexed-addresses",
36687 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36688 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36690 offsetof (struct gcc_options, x_rs6000_paired_float),
36691 offsetof (struct cl_target_option, x_rs6000_paired_float), },
36693 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36694 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36695 { "optimize-swaps",
36696 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36697 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36698 { "allow-movmisalign",
36699 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36700 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36702 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36703 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36705 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36706 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36707 { "align-branch-targets",
36708 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36709 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36711 offsetof (struct gcc_options, x_tls_markers),
36712 offsetof (struct cl_target_option, x_tls_markers), },
36714 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36715 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36717 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36718 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36719 { "speculate-indirect-jumps",
36720 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36721 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36724 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36725 parsing. Return true if there were no errors. */
36728 rs6000_inner_target_options (tree args, bool attr_p)
36732 if (args == NULL_TREE)
36735 else if (TREE_CODE (args) == STRING_CST)
36737 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36740 while ((q = strtok (p, ",")) != NULL)
36742 bool error_p = false;
36743 bool not_valid_p = false;
36744 const char *cpu_opt = NULL;
36747 if (strncmp (q, "cpu=", 4) == 0)
36749 int cpu_index = rs6000_cpu_name_lookup (q+4);
36750 if (cpu_index >= 0)
36751 rs6000_cpu_index = cpu_index;
36758 else if (strncmp (q, "tune=", 5) == 0)
36760 int tune_index = rs6000_cpu_name_lookup (q+5);
36761 if (tune_index >= 0)
36762 rs6000_tune_index = tune_index;
36772 bool invert = false;
36776 if (strncmp (r, "no-", 3) == 0)
36782 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36783 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36785 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36787 if (!rs6000_opt_masks[i].valid_target)
36788 not_valid_p = true;
36792 rs6000_isa_flags_explicit |= mask;
36794 /* VSX needs altivec, so -mvsx automagically sets
36795 altivec and disables -mavoid-indexed-addresses. */
36798 if (mask == OPTION_MASK_VSX)
36800 mask |= OPTION_MASK_ALTIVEC;
36801 TARGET_AVOID_XFORM = 0;
36805 if (rs6000_opt_masks[i].invert)
36809 rs6000_isa_flags &= ~mask;
36811 rs6000_isa_flags |= mask;
36816 if (error_p && !not_valid_p)
36818 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36819 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36821 size_t j = rs6000_opt_vars[i].global_offset;
36822 *((int *) ((char *)&global_options + j)) = !invert;
36824 not_valid_p = false;
36832 const char *eprefix, *esuffix;
36837 eprefix = "__attribute__((__target__(";
36842 eprefix = "#pragma GCC target ";
36847 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36849 else if (not_valid_p)
36850 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36852 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36857 else if (TREE_CODE (args) == TREE_LIST)
36861 tree value = TREE_VALUE (args);
36864 bool ret2 = rs6000_inner_target_options (value, attr_p);
36868 args = TREE_CHAIN (args);
36870 while (args != NULL_TREE);
36875 error ("attribute %<target%> argument not a string");
36882 /* Print out the target options as a list for -mdebug=target. */
36885 rs6000_debug_target_options (tree args, const char *prefix)
36887 if (args == NULL_TREE)
36888 fprintf (stderr, "%s<NULL>", prefix);
36890 else if (TREE_CODE (args) == STRING_CST)
36892 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36895 while ((q = strtok (p, ",")) != NULL)
36898 fprintf (stderr, "%s\"%s\"", prefix, q);
36903 else if (TREE_CODE (args) == TREE_LIST)
36907 tree value = TREE_VALUE (args);
36910 rs6000_debug_target_options (value, prefix);
36913 args = TREE_CHAIN (args);
36915 while (args != NULL_TREE);
36919 gcc_unreachable ();
36925 /* Hook to validate attribute((target("..."))). */
36928 rs6000_valid_attribute_p (tree fndecl,
36929 tree ARG_UNUSED (name),
36933 struct cl_target_option cur_target;
36936 tree new_target, new_optimize;
36937 tree func_optimize;
36939 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36941 if (TARGET_DEBUG_TARGET)
36943 tree tname = DECL_NAME (fndecl);
36944 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36946 fprintf (stderr, "function: %.*s\n",
36947 (int) IDENTIFIER_LENGTH (tname),
36948 IDENTIFIER_POINTER (tname));
36950 fprintf (stderr, "function: unknown\n");
36952 fprintf (stderr, "args:");
36953 rs6000_debug_target_options (args, " ");
36954 fprintf (stderr, "\n");
36957 fprintf (stderr, "flags: 0x%x\n", flags);
36959 fprintf (stderr, "--------------------\n");
36962 /* attribute((target("default"))) does nothing, beyond
36963 affecting multi-versioning. */
36964 if (TREE_VALUE (args)
36965 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36966 && TREE_CHAIN (args) == NULL_TREE
36967 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36970 old_optimize = build_optimization_node (&global_options);
36971 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36973 /* If the function changed the optimization levels as well as setting target
36974 options, start with the optimizations specified. */
36975 if (func_optimize && func_optimize != old_optimize)
36976 cl_optimization_restore (&global_options,
36977 TREE_OPTIMIZATION (func_optimize));
36979 /* The target attributes may also change some optimization flags, so update
36980 the optimization options if necessary. */
36981 cl_target_option_save (&cur_target, &global_options);
36982 rs6000_cpu_index = rs6000_tune_index = -1;
36983 ret = rs6000_inner_target_options (args, true);
36985 /* Set up any additional state. */
36988 ret = rs6000_option_override_internal (false);
36989 new_target = build_target_option_node (&global_options);
36994 new_optimize = build_optimization_node (&global_options);
37001 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
37003 if (old_optimize != new_optimize)
37004 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
37007 cl_target_option_restore (&global_options, &cur_target);
37009 if (old_optimize != new_optimize)
37010 cl_optimization_restore (&global_options,
37011 TREE_OPTIMIZATION (old_optimize));
37017 /* Hook to validate the current #pragma GCC target and set the state, and
37018 update the macros based on what was changed. If ARGS is NULL, then
37019 POP_TARGET is used to reset the options. */
37022 rs6000_pragma_target_parse (tree args, tree pop_target)
37024 tree prev_tree = build_target_option_node (&global_options);
37026 struct cl_target_option *prev_opt, *cur_opt;
37027 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
37028 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
37030 if (TARGET_DEBUG_TARGET)
37032 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
37033 fprintf (stderr, "args:");
37034 rs6000_debug_target_options (args, " ");
37035 fprintf (stderr, "\n");
37039 fprintf (stderr, "pop_target:\n");
37040 debug_tree (pop_target);
37043 fprintf (stderr, "pop_target: <NULL>\n");
37045 fprintf (stderr, "--------------------\n");
37050 cur_tree = ((pop_target)
37052 : target_option_default_node);
37053 cl_target_option_restore (&global_options,
37054 TREE_TARGET_OPTION (cur_tree));
37058 rs6000_cpu_index = rs6000_tune_index = -1;
37059 if (!rs6000_inner_target_options (args, false)
37060 || !rs6000_option_override_internal (false)
37061 || (cur_tree = build_target_option_node (&global_options))
37064 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
37065 fprintf (stderr, "invalid pragma\n");
37071 target_option_current_node = cur_tree;
37072 rs6000_activate_target_options (target_option_current_node);
37074 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37075 change the macros that are defined. */
37076 if (rs6000_target_modify_macros_ptr)
37078 prev_opt = TREE_TARGET_OPTION (prev_tree);
37079 prev_bumask = prev_opt->x_rs6000_builtin_mask;
37080 prev_flags = prev_opt->x_rs6000_isa_flags;
37082 cur_opt = TREE_TARGET_OPTION (cur_tree);
37083 cur_flags = cur_opt->x_rs6000_isa_flags;
37084 cur_bumask = cur_opt->x_rs6000_builtin_mask;
37086 diff_bumask = (prev_bumask ^ cur_bumask);
37087 diff_flags = (prev_flags ^ cur_flags);
37089 if ((diff_flags != 0) || (diff_bumask != 0))
37091 /* Delete old macros. */
37092 rs6000_target_modify_macros_ptr (false,
37093 prev_flags & diff_flags,
37094 prev_bumask & diff_bumask);
37096 /* Define new macros. */
37097 rs6000_target_modify_macros_ptr (true,
37098 cur_flags & diff_flags,
37099 cur_bumask & diff_bumask);
37107 /* Remember the last target of rs6000_set_current_function. */
37108 static GTY(()) tree rs6000_previous_fndecl;
37110 /* Restore target's globals from NEW_TREE and invalidate the
37111 rs6000_previous_fndecl cache. */
37114 rs6000_activate_target_options (tree new_tree)
37116 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
37117 if (TREE_TARGET_GLOBALS (new_tree))
37118 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
37119 else if (new_tree == target_option_default_node)
37120 restore_target_globals (&default_target_globals);
37122 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
37123 rs6000_previous_fndecl = NULL_TREE;
37126 /* Establish appropriate back-end context for processing the function
37127 FNDECL. The argument might be NULL to indicate processing at top
37128 level, outside of any function scope. */
37130 rs6000_set_current_function (tree fndecl)
37132 if (TARGET_DEBUG_TARGET)
37134 fprintf (stderr, "\n==================== rs6000_set_current_function");
37137 fprintf (stderr, ", fndecl %s (%p)",
37138 (DECL_NAME (fndecl)
37139 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
37140 : "<unknown>"), (void *)fndecl);
37142 if (rs6000_previous_fndecl)
37143 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
37145 fprintf (stderr, "\n");
37148 /* Only change the context if the function changes. This hook is called
37149 several times in the course of compiling a function, and we don't want to
37150 slow things down too much or call target_reinit when it isn't safe. */
37151 if (fndecl == rs6000_previous_fndecl)
37155 if (rs6000_previous_fndecl == NULL_TREE)
37156 old_tree = target_option_current_node;
37157 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
37158 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
37160 old_tree = target_option_default_node;
37163 if (fndecl == NULL_TREE)
37165 if (old_tree != target_option_current_node)
37166 new_tree = target_option_current_node;
37168 new_tree = NULL_TREE;
37172 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37173 if (new_tree == NULL_TREE)
37174 new_tree = target_option_default_node;
37177 if (TARGET_DEBUG_TARGET)
37181 fprintf (stderr, "\nnew fndecl target specific options:\n");
37182 debug_tree (new_tree);
37187 fprintf (stderr, "\nold fndecl target specific options:\n");
37188 debug_tree (old_tree);
37191 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37192 fprintf (stderr, "--------------------\n");
37195 if (new_tree && old_tree != new_tree)
37196 rs6000_activate_target_options (new_tree);
37199 rs6000_previous_fndecl = fndecl;
37203 /* Save the current options */
37206 rs6000_function_specific_save (struct cl_target_option *ptr,
37207 struct gcc_options *opts)
37209 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37210 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37213 /* Restore the current options */
37216 rs6000_function_specific_restore (struct gcc_options *opts,
37217 struct cl_target_option *ptr)
37220 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37221 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37222 (void) rs6000_option_override_internal (false);
37225 /* Print the current options */
37228 rs6000_function_specific_print (FILE *file, int indent,
37229 struct cl_target_option *ptr)
37231 rs6000_print_isa_options (file, indent, "Isa options set",
37232 ptr->x_rs6000_isa_flags);
37234 rs6000_print_isa_options (file, indent, "Isa options explicit",
37235 ptr->x_rs6000_isa_flags_explicit);
37238 /* Helper function to print the current isa or misc options on a line. */
37241 rs6000_print_options_internal (FILE *file,
37243 const char *string,
37244 HOST_WIDE_INT flags,
37245 const char *prefix,
37246 const struct rs6000_opt_mask *opts,
37247 size_t num_elements)
37250 size_t start_column = 0;
37252 size_t max_column = 120;
37253 size_t prefix_len = strlen (prefix);
37254 size_t comma_len = 0;
37255 const char *comma = "";
37258 start_column += fprintf (file, "%*s", indent, "");
37262 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37266 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37268 /* Print the various mask options. */
37269 cur_column = start_column;
37270 for (i = 0; i < num_elements; i++)
37272 bool invert = opts[i].invert;
37273 const char *name = opts[i].name;
37274 const char *no_str = "";
37275 HOST_WIDE_INT mask = opts[i].mask;
37276 size_t len = comma_len + prefix_len + strlen (name);
37280 if ((flags & mask) == 0)
37283 len += sizeof ("no-") - 1;
37291 if ((flags & mask) != 0)
37294 len += sizeof ("no-") - 1;
37301 if (cur_column > max_column)
37303 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37304 cur_column = start_column + len;
37308 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37310 comma_len = sizeof (", ") - 1;
37313 fputs ("\n", file);
37316 /* Helper function to print the current isa options on a line. */
37319 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37320 HOST_WIDE_INT flags)
37322 rs6000_print_options_internal (file, indent, string, flags, "-m",
37323 &rs6000_opt_masks[0],
37324 ARRAY_SIZE (rs6000_opt_masks));
37328 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37329 HOST_WIDE_INT flags)
37331 rs6000_print_options_internal (file, indent, string, flags, "",
37332 &rs6000_builtin_mask_names[0],
37333 ARRAY_SIZE (rs6000_builtin_mask_names));
37336 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37337 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37338 -mupper-regs-df, etc.).
37340 If the user used -mno-power8-vector, we need to turn off all of the implicit
37341 ISA 2.07 and 3.0 options that relate to the vector unit.
37343 If the user used -mno-power9-vector, we need to turn off all of the implicit
37344 ISA 3.0 options that relate to the vector unit.
37346 This function does not handle explicit options such as the user specifying
37347 -mdirect-move. These are handled in rs6000_option_override_internal, and
37348 the appropriate error is given if needed.
37350 We return a mask of all of the implicit options that should not be enabled
37353 static HOST_WIDE_INT
37354 rs6000_disable_incompatible_switches (void)
37356 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37359 static const struct {
37360 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37361 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37362 const char *const name; /* name of the switch. */
37364 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37365 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37366 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37369 for (i = 0; i < ARRAY_SIZE (flags); i++)
37371 HOST_WIDE_INT no_flag = flags[i].no_flag;
37373 if ((rs6000_isa_flags & no_flag) == 0
37374 && (rs6000_isa_flags_explicit & no_flag) != 0)
37376 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37377 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37383 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37384 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37386 set_flags &= ~rs6000_opt_masks[j].mask;
37387 error ("%<-mno-%s%> turns off %<-m%s%>",
37389 rs6000_opt_masks[j].name);
37392 gcc_assert (!set_flags);
37395 rs6000_isa_flags &= ~dep_flags;
37396 ignore_masks |= no_flag | dep_flags;
37400 return ignore_masks;
37404 /* Helper function for printing the function name when debugging. */
37406 static const char *
37407 get_decl_name (tree fn)
37414 name = DECL_NAME (fn);
37416 return "<no-name>";
37418 return IDENTIFIER_POINTER (name);
37421 /* Return the clone id of the target we are compiling code for in a target
37422 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37423 the priority list for the target clones (ordered from lowest to
37427 rs6000_clone_priority (tree fndecl)
37429 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37430 HOST_WIDE_INT isa_masks;
37431 int ret = CLONE_DEFAULT;
37432 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37433 const char *attrs_str = NULL;
37435 attrs = TREE_VALUE (TREE_VALUE (attrs));
37436 attrs_str = TREE_STRING_POINTER (attrs);
37438 /* Return priority zero for default function. Return the ISA needed for the
37439 function if it is not the default. */
37440 if (strcmp (attrs_str, "default") != 0)
37442 if (fn_opts == NULL_TREE)
37443 fn_opts = target_option_default_node;
37445 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37446 isa_masks = rs6000_isa_flags;
37448 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37450 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37451 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37455 if (TARGET_DEBUG_TARGET)
37456 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37457 get_decl_name (fndecl), ret);
37462 /* This compares the priority of target features in function DECL1 and DECL2.
37463 It returns positive value if DECL1 is higher priority, negative value if
37464 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37465 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37468 rs6000_compare_version_priority (tree decl1, tree decl2)
37470 int priority1 = rs6000_clone_priority (decl1);
37471 int priority2 = rs6000_clone_priority (decl2);
37472 int ret = priority1 - priority2;
37474 if (TARGET_DEBUG_TARGET)
37475 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37476 get_decl_name (decl1), get_decl_name (decl2), ret);
37481 /* Make a dispatcher declaration for the multi-versioned function DECL.
37482 Calls to DECL function will be replaced with calls to the dispatcher
37483 by the front-end. Returns the decl of the dispatcher function. */
37486 rs6000_get_function_versions_dispatcher (void *decl)
37488 tree fn = (tree) decl;
37489 struct cgraph_node *node = NULL;
37490 struct cgraph_node *default_node = NULL;
37491 struct cgraph_function_version_info *node_v = NULL;
37492 struct cgraph_function_version_info *first_v = NULL;
37494 tree dispatch_decl = NULL;
37496 struct cgraph_function_version_info *default_version_info = NULL;
37497 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37499 if (TARGET_DEBUG_TARGET)
37500 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37501 get_decl_name (fn));
37503 node = cgraph_node::get (fn);
37504 gcc_assert (node != NULL);
37506 node_v = node->function_version ();
37507 gcc_assert (node_v != NULL);
37509 if (node_v->dispatcher_resolver != NULL)
37510 return node_v->dispatcher_resolver;
37512 /* Find the default version and make it the first node. */
37514 /* Go to the beginning of the chain. */
37515 while (first_v->prev != NULL)
37516 first_v = first_v->prev;
37518 default_version_info = first_v;
37519 while (default_version_info != NULL)
37521 const tree decl2 = default_version_info->this_node->decl;
37522 if (is_function_default_version (decl2))
37524 default_version_info = default_version_info->next;
37527 /* If there is no default node, just return NULL. */
37528 if (default_version_info == NULL)
37531 /* Make default info the first node. */
37532 if (first_v != default_version_info)
37534 default_version_info->prev->next = default_version_info->next;
37535 if (default_version_info->next)
37536 default_version_info->next->prev = default_version_info->prev;
37537 first_v->prev = default_version_info;
37538 default_version_info->next = first_v;
37539 default_version_info->prev = NULL;
37542 default_node = default_version_info->this_node;
37544 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37545 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37546 "target_clones attribute needs GLIBC (2.23 and newer) that "
37547 "exports hardware capability bits");
37550 if (targetm.has_ifunc_p ())
37552 struct cgraph_function_version_info *it_v = NULL;
37553 struct cgraph_node *dispatcher_node = NULL;
37554 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37556 /* Right now, the dispatching is done via ifunc. */
37557 dispatch_decl = make_dispatcher_decl (default_node->decl);
37559 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37560 gcc_assert (dispatcher_node != NULL);
37561 dispatcher_node->dispatcher_function = 1;
37562 dispatcher_version_info
37563 = dispatcher_node->insert_new_function_version ();
37564 dispatcher_version_info->next = default_version_info;
37565 dispatcher_node->definition = 1;
37567 /* Set the dispatcher for all the versions. */
37568 it_v = default_version_info;
37569 while (it_v != NULL)
37571 it_v->dispatcher_resolver = dispatch_decl;
37577 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37578 "multiversioning needs ifunc which is not supported "
37583 return dispatch_decl;
37586 /* Make the resolver function decl to dispatch the versions of a multi-
37587 versioned function, DEFAULT_DECL. Create an empty basic block in the
37588 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37592 make_resolver_func (const tree default_decl,
37593 const tree dispatch_decl,
37594 basic_block *empty_bb)
37596 /* Make the resolver function static. The resolver function returns
37598 tree decl_name = clone_function_name (default_decl, "resolver");
37599 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37600 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37601 tree decl = build_fn_decl (resolver_name, type);
37602 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37604 DECL_NAME (decl) = decl_name;
37605 TREE_USED (decl) = 1;
37606 DECL_ARTIFICIAL (decl) = 1;
37607 DECL_IGNORED_P (decl) = 0;
37608 TREE_PUBLIC (decl) = 0;
37609 DECL_UNINLINABLE (decl) = 1;
37611 /* Resolver is not external, body is generated. */
37612 DECL_EXTERNAL (decl) = 0;
37613 DECL_EXTERNAL (dispatch_decl) = 0;
37615 DECL_CONTEXT (decl) = NULL_TREE;
37616 DECL_INITIAL (decl) = make_node (BLOCK);
37617 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37619 /* Build result decl and add to function_decl. */
37620 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37621 DECL_ARTIFICIAL (t) = 1;
37622 DECL_IGNORED_P (t) = 1;
37623 DECL_RESULT (decl) = t;
37625 gimplify_function_tree (decl);
37626 push_cfun (DECL_STRUCT_FUNCTION (decl));
37627 *empty_bb = init_lowered_empty_function (decl, false,
37628 profile_count::uninitialized ());
37630 cgraph_node::add_new_function (decl, true);
37631 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37635 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37636 DECL_ATTRIBUTES (dispatch_decl)
37637 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37639 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37644 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37645 return a pointer to VERSION_DECL if we are running on a machine that
37646 supports the index CLONE_ISA hardware architecture bits. This function will
37647 be called during version dispatch to decide which function version to
37648 execute. It returns the basic block at the end, to which more conditions
37652 add_condition_to_bb (tree function_decl, tree version_decl,
37653 int clone_isa, basic_block new_bb)
37655 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37657 gcc_assert (new_bb != NULL);
37658 gimple_seq gseq = bb_seq (new_bb);
37661 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37662 build_fold_addr_expr (version_decl));
37663 tree result_var = create_tmp_var (ptr_type_node);
37664 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37665 gimple *return_stmt = gimple_build_return (result_var);
37667 if (clone_isa == CLONE_DEFAULT)
37669 gimple_seq_add_stmt (&gseq, convert_stmt);
37670 gimple_seq_add_stmt (&gseq, return_stmt);
37671 set_bb_seq (new_bb, gseq);
37672 gimple_set_bb (convert_stmt, new_bb);
37673 gimple_set_bb (return_stmt, new_bb);
37678 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37679 tree cond_var = create_tmp_var (bool_int_type_node);
37680 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37681 const char *arg_str = rs6000_clone_map[clone_isa].name;
37682 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37683 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37684 gimple_call_set_lhs (call_cond_stmt, cond_var);
37686 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37687 gimple_set_bb (call_cond_stmt, new_bb);
37688 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37690 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37691 NULL_TREE, NULL_TREE);
37692 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37693 gimple_set_bb (if_else_stmt, new_bb);
37694 gimple_seq_add_stmt (&gseq, if_else_stmt);
37696 gimple_seq_add_stmt (&gseq, convert_stmt);
37697 gimple_seq_add_stmt (&gseq, return_stmt);
37698 set_bb_seq (new_bb, gseq);
37700 basic_block bb1 = new_bb;
37701 edge e12 = split_block (bb1, if_else_stmt);
37702 basic_block bb2 = e12->dest;
37703 e12->flags &= ~EDGE_FALLTHRU;
37704 e12->flags |= EDGE_TRUE_VALUE;
37706 edge e23 = split_block (bb2, return_stmt);
37707 gimple_set_bb (convert_stmt, bb2);
37708 gimple_set_bb (return_stmt, bb2);
37710 basic_block bb3 = e23->dest;
37711 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37714 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37720 /* This function generates the dispatch function for multi-versioned functions.
37721 DISPATCH_DECL is the function which will contain the dispatch logic.
37722 FNDECLS are the function choices for dispatch, and is a tree chain.
37723 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37724 code is generated. */
37727 dispatch_function_versions (tree dispatch_decl,
37729 basic_block *empty_bb)
37733 vec<tree> *fndecls;
37734 tree clones[CLONE_MAX];
37736 if (TARGET_DEBUG_TARGET)
37737 fputs ("dispatch_function_versions, top\n", stderr);
37739 gcc_assert (dispatch_decl != NULL
37740 && fndecls_p != NULL
37741 && empty_bb != NULL);
37743 /* fndecls_p is actually a vector. */
37744 fndecls = static_cast<vec<tree> *> (fndecls_p);
37746 /* At least one more version other than the default. */
37747 gcc_assert (fndecls->length () >= 2);
37749 /* The first version in the vector is the default decl. */
37750 memset ((void *) clones, '\0', sizeof (clones));
37751 clones[CLONE_DEFAULT] = (*fndecls)[0];
37753 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37754 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37755 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37756 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37757 to insert the code here to do the call. */
37759 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37761 int priority = rs6000_clone_priority (ele);
37762 if (!clones[priority])
37763 clones[priority] = ele;
37766 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37769 if (TARGET_DEBUG_TARGET)
37770 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37771 ix, get_decl_name (clones[ix]));
37773 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37780 /* Generate the dispatching code body to dispatch multi-versioned function
37781 DECL. The target hook is called to process the "target" attributes and
37782 provide the code to dispatch the right function at run-time. NODE points
37783 to the dispatcher decl whose body will be created. */
37786 rs6000_generate_version_dispatcher_body (void *node_p)
37789 basic_block empty_bb;
37790 struct cgraph_node *node = (cgraph_node *) node_p;
37791 struct cgraph_function_version_info *ninfo = node->function_version ();
37793 if (ninfo->dispatcher_resolver)
37794 return ninfo->dispatcher_resolver;
37796 /* node is going to be an alias, so remove the finalized bit. */
37797 node->definition = false;
37799 /* The first version in the chain corresponds to the default version. */
37800 ninfo->dispatcher_resolver = resolver
37801 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37803 if (TARGET_DEBUG_TARGET)
37804 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37805 get_decl_name (resolver));
37807 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37808 auto_vec<tree, 2> fn_ver_vec;
37810 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37812 vinfo = vinfo->next)
37814 struct cgraph_node *version = vinfo->this_node;
37815 /* Check for virtual functions here again, as by this time it should
37816 have been determined if this function needs a vtable index or
37817 not. This happens for methods in derived classes that override
37818 virtual methods in base classes but are not explicitly marked as
37820 if (DECL_VINDEX (version->decl))
37821 sorry ("Virtual function multiversioning not supported");
37823 fn_ver_vec.safe_push (version->decl);
37826 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37827 cgraph_edge::rebuild_edges ();
37833 /* Hook to determine if one function can safely inline another. */
37836 rs6000_can_inline_p (tree caller, tree callee)
37839 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37840 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37842 /* If callee has no option attributes, then it is ok to inline. */
37846 /* If caller has no option attributes, but callee does then it is not ok to
37848 else if (!caller_tree)
37853 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37854 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37856 /* Callee's options should a subset of the caller's, i.e. a vsx function
37857 can inline an altivec function but a non-vsx function can't inline a
37859 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37860 == callee_opts->x_rs6000_isa_flags)
37864 if (TARGET_DEBUG_TARGET)
37865 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37866 get_decl_name (caller), get_decl_name (callee),
37867 (ret ? "can" : "cannot"));
37872 /* Allocate a stack temp and fixup the address so it meets the particular
37873 memory requirements (either offetable or REG+REG addressing). */
37876 rs6000_allocate_stack_temp (machine_mode mode,
37877 bool offsettable_p,
37880 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37881 rtx addr = XEXP (stack, 0);
37882 int strict_p = reload_completed;
37884 if (!legitimate_indirect_address_p (addr, strict_p))
37887 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37888 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37890 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37891 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37897 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37898 to such a form to deal with memory reference instructions like STFIWX that
37899 only take reg+reg addressing. */
37902 rs6000_address_for_fpconvert (rtx x)
37906 gcc_assert (MEM_P (x));
37907 addr = XEXP (x, 0);
37908 if (can_create_pseudo_p ()
37909 && ! legitimate_indirect_address_p (addr, reload_completed)
37910 && ! legitimate_indexed_address_p (addr, reload_completed))
37912 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37914 rtx reg = XEXP (addr, 0);
37915 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37916 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37917 gcc_assert (REG_P (reg));
37918 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37921 else if (GET_CODE (addr) == PRE_MODIFY)
37923 rtx reg = XEXP (addr, 0);
37924 rtx expr = XEXP (addr, 1);
37925 gcc_assert (REG_P (reg));
37926 gcc_assert (GET_CODE (expr) == PLUS);
37927 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37931 x = replace_equiv_address (x, copy_addr_to_reg (addr));
37937 /* Given a memory reference, if it is not in the form for altivec memory
37938 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
37939 convert to the altivec format. */
37942 rs6000_address_for_altivec (rtx x)
37944 gcc_assert (MEM_P (x));
37945 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
37947 rtx addr = XEXP (x, 0);
37949 if (!legitimate_indexed_address_p (addr, reload_completed)
37950 && !legitimate_indirect_address_p (addr, reload_completed))
37951 addr = copy_to_mode_reg (Pmode, addr);
37953 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
37954 x = change_address (x, GET_MODE (x), addr);
37960 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37962 On the RS/6000, all integer constants are acceptable, most won't be valid
37963 for particular insns, though. Only easy FP constants are acceptable. */
37966 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37968 if (TARGET_ELF && tls_referenced_p (x))
37971 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
37972 || GET_MODE (x) == VOIDmode
37973 || (TARGET_POWERPC64 && mode == DImode)
37974 || easy_fp_constant (x, mode)
37975 || easy_vector_constant (x, mode));
37979 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37982 chain_already_loaded (rtx_insn *last)
37984 for (; last != NULL; last = PREV_INSN (last))
37986 if (NONJUMP_INSN_P (last))
37988 rtx patt = PATTERN (last);
37990 if (GET_CODE (patt) == SET)
37992 rtx lhs = XEXP (patt, 0);
37994 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
38002 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38005 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38007 const bool direct_call_p
38008 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
38009 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
38010 rtx toc_load = NULL_RTX;
38011 rtx toc_restore = NULL_RTX;
38013 rtx abi_reg = NULL_RTX;
38018 /* Handle longcall attributes. */
38019 if (INTVAL (cookie) & CALL_LONG)
38020 func_desc = rs6000_longcall_ref (func_desc);
38022 /* Handle indirect calls. */
38023 if (GET_CODE (func_desc) != SYMBOL_REF
38024 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
38026 /* Save the TOC into its reserved slot before the call,
38027 and prepare to restore it after the call. */
38028 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
38029 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
38030 rtx stack_toc_mem = gen_frame_mem (Pmode,
38031 gen_rtx_PLUS (Pmode, stack_ptr,
38032 stack_toc_offset));
38033 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
38034 gen_rtvec (1, stack_toc_offset),
38036 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
38038 /* Can we optimize saving the TOC in the prologue or
38039 do we need to do it at every call? */
38040 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
38041 cfun->machine->save_toc_in_prologue = true;
38044 MEM_VOLATILE_P (stack_toc_mem) = 1;
38045 emit_move_insn (stack_toc_mem, toc_reg);
38048 if (DEFAULT_ABI == ABI_ELFv2)
38050 /* A function pointer in the ELFv2 ABI is just a plain address, but
38051 the ABI requires it to be loaded into r12 before the call. */
38052 func_addr = gen_rtx_REG (Pmode, 12);
38053 emit_move_insn (func_addr, func_desc);
38054 abi_reg = func_addr;
38058 /* A function pointer under AIX is a pointer to a data area whose
38059 first word contains the actual address of the function, whose
38060 second word contains a pointer to its TOC, and whose third word
38061 contains a value to place in the static chain register (r11).
38062 Note that if we load the static chain, our "trampoline" need
38063 not have any executable code. */
38065 /* Load up address of the actual function. */
38066 func_desc = force_reg (Pmode, func_desc);
38067 func_addr = gen_reg_rtx (Pmode);
38068 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
38070 /* Prepare to load the TOC of the called function. Note that the
38071 TOC load must happen immediately before the actual call so
38072 that unwinding the TOC registers works correctly. See the
38073 comment in frob_update_context. */
38074 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
38075 rtx func_toc_mem = gen_rtx_MEM (Pmode,
38076 gen_rtx_PLUS (Pmode, func_desc,
38078 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
38080 /* If we have a static chain, load it up. But, if the call was
38081 originally direct, the 3rd word has not been written since no
38082 trampoline has been built, so we ought not to load it, lest we
38083 override a static chain value. */
38085 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38086 && !chain_already_loaded (get_current_sequence ()->next->last))
38088 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
38089 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
38090 rtx func_sc_mem = gen_rtx_MEM (Pmode,
38091 gen_rtx_PLUS (Pmode, func_desc,
38093 emit_move_insn (sc_reg, func_sc_mem);
38100 /* Direct calls use the TOC: for local calls, the callee will
38101 assume the TOC register is set; for non-local calls, the
38102 PLT stub needs the TOC register. */
38104 func_addr = func_desc;
38107 /* Create the call. */
38108 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
38109 if (value != NULL_RTX)
38110 call[0] = gen_rtx_SET (value, call[0]);
38114 call[n_call++] = toc_load;
38116 call[n_call++] = toc_restore;
38118 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
38120 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
38121 insn = emit_call_insn (insn);
38123 /* Mention all registers defined by the ABI to hold information
38124 as uses in CALL_INSN_FUNCTION_USAGE. */
38126 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38129 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38132 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38137 gcc_assert (INTVAL (cookie) == 0);
38139 /* Create the call. */
38140 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
38141 if (value != NULL_RTX)
38142 call[0] = gen_rtx_SET (value, call[0]);
38144 call[1] = simple_return_rtx;
38146 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
38147 insn = emit_call_insn (insn);
38149 /* Note use of the TOC register. */
38150 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
38153 /* Return whether we need to always update the saved TOC pointer when we update
38154 the stack pointer. */
38157 rs6000_save_toc_in_prologue_p (void)
38159 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38162 #ifdef HAVE_GAS_HIDDEN
38163 # define USE_HIDDEN_LINKONCE 1
38165 # define USE_HIDDEN_LINKONCE 0
38168 /* Fills in the label name that should be used for a 476 link stack thunk. */
38171 get_ppc476_thunk_name (char name[32])
38173 gcc_assert (TARGET_LINK_STACK);
38175 if (USE_HIDDEN_LINKONCE)
38176 sprintf (name, "__ppc476.get_thunk");
38178 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38181 /* This function emits the simple thunk routine that is used to preserve
38182 the link stack on the 476 cpu. */
38184 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38186 rs6000_code_end (void)
38191 if (!TARGET_LINK_STACK)
38194 get_ppc476_thunk_name (name);
38196 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38197 build_function_type_list (void_type_node, NULL_TREE));
38198 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38199 NULL_TREE, void_type_node);
38200 TREE_PUBLIC (decl) = 1;
38201 TREE_STATIC (decl) = 1;
38204 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38206 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38207 targetm.asm_out.unique_section (decl, 0);
38208 switch_to_section (get_named_section (decl, NULL, 0));
38209 DECL_WEAK (decl) = 1;
38210 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38211 targetm.asm_out.globalize_label (asm_out_file, name);
38212 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38213 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38218 switch_to_section (text_section);
38219 ASM_OUTPUT_LABEL (asm_out_file, name);
38222 DECL_INITIAL (decl) = make_node (BLOCK);
38223 current_function_decl = decl;
38224 allocate_struct_function (decl, false);
38225 init_function_start (decl);
38226 first_function_block_is_cold = false;
38227 /* Make sure unwind info is emitted for the thunk if needed. */
38228 final_start_function (emit_barrier (), asm_out_file, 1);
38230 fputs ("\tblr\n", asm_out_file);
38232 final_end_function ();
38233 init_insn_lengths ();
38234 free_after_compilation (cfun);
38236 current_function_decl = NULL;
38239 /* Add r30 to hard reg set if the prologue sets it up and it is not
38240 pic_offset_table_rtx. */
38243 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38245 if (!TARGET_SINGLE_PIC_BASE
38247 && TARGET_MINIMAL_TOC
38248 && !constant_pool_empty_p ())
38249 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38250 if (cfun->machine->split_stack_argp_used)
38251 add_to_hard_reg_set (&set->set, Pmode, 12);
38253 /* Make sure the hard reg set doesn't include r2, which was possibly added
38254 via PIC_OFFSET_TABLE_REGNUM. */
38256 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38260 /* Helper function for rs6000_split_logical to emit a logical instruction after
38261 spliting the operation to single GPR registers.
38263 DEST is the destination register.
38264 OP1 and OP2 are the input source registers.
38265 CODE is the base operation (AND, IOR, XOR, NOT).
38266 MODE is the machine mode.
38267 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38268 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38269 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38272 rs6000_split_logical_inner (rtx dest,
38275 enum rtx_code code,
38277 bool complement_final_p,
38278 bool complement_op1_p,
38279 bool complement_op2_p)
38283 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38284 if (op2 && GET_CODE (op2) == CONST_INT
38285 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38286 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38288 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38289 HOST_WIDE_INT value = INTVAL (op2) & mask;
38291 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38296 emit_insn (gen_rtx_SET (dest, const0_rtx));
38300 else if (value == mask)
38302 if (!rtx_equal_p (dest, op1))
38303 emit_insn (gen_rtx_SET (dest, op1));
38308 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38309 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38310 else if (code == IOR || code == XOR)
38314 if (!rtx_equal_p (dest, op1))
38315 emit_insn (gen_rtx_SET (dest, op1));
38321 if (code == AND && mode == SImode
38322 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38324 emit_insn (gen_andsi3 (dest, op1, op2));
38328 if (complement_op1_p)
38329 op1 = gen_rtx_NOT (mode, op1);
38331 if (complement_op2_p)
38332 op2 = gen_rtx_NOT (mode, op2);
38334 /* For canonical RTL, if only one arm is inverted it is the first. */
38335 if (!complement_op1_p && complement_op2_p)
38336 std::swap (op1, op2);
38338 bool_rtx = ((code == NOT)
38339 ? gen_rtx_NOT (mode, op1)
38340 : gen_rtx_fmt_ee (code, mode, op1, op2));
38342 if (complement_final_p)
38343 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38345 emit_insn (gen_rtx_SET (dest, bool_rtx));
38348 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38349 operations are split immediately during RTL generation to allow for more
38350 optimizations of the AND/IOR/XOR.
38352 OPERANDS is an array containing the destination and two input operands.
38353 CODE is the base operation (AND, IOR, XOR, NOT).
38354 MODE is the machine mode.
38355 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38356 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38357 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38358 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38359 formation of the AND instructions. */
38362 rs6000_split_logical_di (rtx operands[3],
38363 enum rtx_code code,
38364 bool complement_final_p,
38365 bool complement_op1_p,
38366 bool complement_op2_p)
38368 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38369 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38370 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38371 enum hi_lo { hi = 0, lo = 1 };
38372 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38375 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38376 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38377 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38378 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38381 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38384 if (GET_CODE (operands[2]) != CONST_INT)
38386 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38387 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38391 HOST_WIDE_INT value = INTVAL (operands[2]);
38392 HOST_WIDE_INT value_hi_lo[2];
38394 gcc_assert (!complement_final_p);
38395 gcc_assert (!complement_op1_p);
38396 gcc_assert (!complement_op2_p);
38398 value_hi_lo[hi] = value >> 32;
38399 value_hi_lo[lo] = value & lower_32bits;
38401 for (i = 0; i < 2; i++)
38403 HOST_WIDE_INT sub_value = value_hi_lo[i];
38405 if (sub_value & sign_bit)
38406 sub_value |= upper_32bits;
38408 op2_hi_lo[i] = GEN_INT (sub_value);
38410 /* If this is an AND instruction, check to see if we need to load
38411 the value in a register. */
38412 if (code == AND && sub_value != -1 && sub_value != 0
38413 && !and_operand (op2_hi_lo[i], SImode))
38414 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38419 for (i = 0; i < 2; i++)
38421 /* Split large IOR/XOR operations. */
38422 if ((code == IOR || code == XOR)
38423 && GET_CODE (op2_hi_lo[i]) == CONST_INT
38424 && !complement_final_p
38425 && !complement_op1_p
38426 && !complement_op2_p
38427 && !logical_const_operand (op2_hi_lo[i], SImode))
38429 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38430 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38431 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38432 rtx tmp = gen_reg_rtx (SImode);
38434 /* Make sure the constant is sign extended. */
38435 if ((hi_16bits & sign_bit) != 0)
38436 hi_16bits |= upper_32bits;
38438 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38439 code, SImode, false, false, false);
38441 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38442 code, SImode, false, false, false);
38445 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38446 code, SImode, complement_final_p,
38447 complement_op1_p, complement_op2_p);
38453 /* Split the insns that make up boolean operations operating on multiple GPR
38454 registers. The boolean MD patterns ensure that the inputs either are
38455 exactly the same as the output registers, or there is no overlap.
38457 OPERANDS is an array containing the destination and two input operands.
38458 CODE is the base operation (AND, IOR, XOR, NOT).
38459 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38460 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38461 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38464 rs6000_split_logical (rtx operands[3],
38465 enum rtx_code code,
38466 bool complement_final_p,
38467 bool complement_op1_p,
38468 bool complement_op2_p)
38470 machine_mode mode = GET_MODE (operands[0]);
38471 machine_mode sub_mode;
38473 int sub_size, regno0, regno1, nregs, i;
38475 /* If this is DImode, use the specialized version that can run before
38476 register allocation. */
38477 if (mode == DImode && !TARGET_POWERPC64)
38479 rs6000_split_logical_di (operands, code, complement_final_p,
38480 complement_op1_p, complement_op2_p);
38486 op2 = (code == NOT) ? NULL_RTX : operands[2];
38487 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38488 sub_size = GET_MODE_SIZE (sub_mode);
38489 regno0 = REGNO (op0);
38490 regno1 = REGNO (op1);
38492 gcc_assert (reload_completed);
38493 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38494 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38496 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38497 gcc_assert (nregs > 1);
38499 if (op2 && REG_P (op2))
38500 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38502 for (i = 0; i < nregs; i++)
38504 int offset = i * sub_size;
38505 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38506 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38507 rtx sub_op2 = ((code == NOT)
38509 : simplify_subreg (sub_mode, op2, mode, offset));
38511 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38512 complement_final_p, complement_op1_p,
38520 /* Return true if the peephole2 can combine a load involving a combination of
38521 an addis instruction and a load with an offset that can be fused together on
38525 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38526 rtx addis_value, /* addis value. */
38527 rtx target, /* target register that is loaded. */
38528 rtx mem) /* bottom part of the memory addr. */
38533 /* Validate arguments. */
38534 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38537 if (!base_reg_operand (target, GET_MODE (target)))
38540 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38543 /* Allow sign/zero extension. */
38544 if (GET_CODE (mem) == ZERO_EXTEND
38545 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38546 mem = XEXP (mem, 0);
38551 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38554 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38555 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38558 /* Validate that the register used to load the high value is either the
38559 register being loaded, or we can safely replace its use.
38561 This function is only called from the peephole2 pass and we assume that
38562 there are 2 instructions in the peephole (addis and load), so we want to
38563 check if the target register was not used in the memory address and the
38564 register to hold the addis result is dead after the peephole. */
38565 if (REGNO (addis_reg) != REGNO (target))
38567 if (reg_mentioned_p (target, mem))
38570 if (!peep2_reg_dead_p (2, addis_reg))
38573 /* If the target register being loaded is the stack pointer, we must
38574 avoid loading any other value into it, even temporarily. */
38575 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38579 base_reg = XEXP (addr, 0);
38580 return REGNO (addis_reg) == REGNO (base_reg);
38583 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38584 sequence. We adjust the addis register to use the target register. If the
38585 load sign extends, we adjust the code to do the zero extending load, and an
38586 explicit sign extension later since the fusion only covers zero extending
38590 operands[0] register set with addis (to be replaced with target)
38591 operands[1] value set via addis
38592 operands[2] target register being loaded
38593 operands[3] D-form memory reference using operands[0]. */
38596 expand_fusion_gpr_load (rtx *operands)
38598 rtx addis_value = operands[1];
38599 rtx target = operands[2];
38600 rtx orig_mem = operands[3];
38601 rtx new_addr, new_mem, orig_addr, offset;
38602 enum rtx_code plus_or_lo_sum;
38603 machine_mode target_mode = GET_MODE (target);
38604 machine_mode extend_mode = target_mode;
38605 machine_mode ptr_mode = Pmode;
38606 enum rtx_code extend = UNKNOWN;
38608 if (GET_CODE (orig_mem) == ZERO_EXTEND
38609 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38611 extend = GET_CODE (orig_mem);
38612 orig_mem = XEXP (orig_mem, 0);
38613 target_mode = GET_MODE (orig_mem);
38616 gcc_assert (MEM_P (orig_mem));
38618 orig_addr = XEXP (orig_mem, 0);
38619 plus_or_lo_sum = GET_CODE (orig_addr);
38620 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38622 offset = XEXP (orig_addr, 1);
38623 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38624 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38626 if (extend != UNKNOWN)
38627 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38629 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38630 UNSPEC_FUSION_GPR);
38631 emit_insn (gen_rtx_SET (target, new_mem));
38633 if (extend == SIGN_EXTEND)
38635 int sub_off = ((BYTES_BIG_ENDIAN)
38636 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38639 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38641 emit_insn (gen_rtx_SET (target,
38642 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38648 /* Emit the addis instruction that will be part of a fused instruction
38652 emit_fusion_addis (rtx target, rtx addis_value)
38655 const char *addis_str = NULL;
38657 /* Emit the addis instruction. */
38658 fuse_ops[0] = target;
38659 if (satisfies_constraint_L (addis_value))
38661 fuse_ops[1] = addis_value;
38662 addis_str = "lis %0,%v1";
38665 else if (GET_CODE (addis_value) == PLUS)
38667 rtx op0 = XEXP (addis_value, 0);
38668 rtx op1 = XEXP (addis_value, 1);
38670 if (REG_P (op0) && CONST_INT_P (op1)
38671 && satisfies_constraint_L (op1))
38675 addis_str = "addis %0,%1,%v2";
38679 else if (GET_CODE (addis_value) == HIGH)
38681 rtx value = XEXP (addis_value, 0);
38682 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38684 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38685 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38687 addis_str = "addis %0,%2,%1@toc@ha";
38689 else if (TARGET_XCOFF)
38690 addis_str = "addis %0,%1@u(%2)";
38693 gcc_unreachable ();
38696 else if (GET_CODE (value) == PLUS)
38698 rtx op0 = XEXP (value, 0);
38699 rtx op1 = XEXP (value, 1);
38701 if (GET_CODE (op0) == UNSPEC
38702 && XINT (op0, 1) == UNSPEC_TOCREL
38703 && CONST_INT_P (op1))
38705 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38706 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38709 addis_str = "addis %0,%2,%1+%3@toc@ha";
38711 else if (TARGET_XCOFF)
38712 addis_str = "addis %0,%1+%3@u(%2)";
38715 gcc_unreachable ();
38719 else if (satisfies_constraint_L (value))
38721 fuse_ops[1] = value;
38722 addis_str = "lis %0,%v1";
38725 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38727 fuse_ops[1] = value;
38728 addis_str = "lis %0,%1@ha";
38733 fatal_insn ("Could not generate addis value for fusion", addis_value);
38735 output_asm_insn (addis_str, fuse_ops);
38738 /* Emit a D-form load or store instruction that is the second instruction
38739 of a fusion sequence. */
38742 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
38743 const char *insn_str)
38746 char insn_template[80];
38748 fuse_ops[0] = load_store_reg;
38749 fuse_ops[1] = addis_reg;
38751 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38753 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38754 fuse_ops[2] = offset;
38755 output_asm_insn (insn_template, fuse_ops);
38758 else if (GET_CODE (offset) == UNSPEC
38759 && XINT (offset, 1) == UNSPEC_TOCREL)
38762 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38764 else if (TARGET_XCOFF)
38765 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38768 gcc_unreachable ();
38770 fuse_ops[2] = XVECEXP (offset, 0, 0);
38771 output_asm_insn (insn_template, fuse_ops);
38774 else if (GET_CODE (offset) == PLUS
38775 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38776 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38777 && CONST_INT_P (XEXP (offset, 1)))
38779 rtx tocrel_unspec = XEXP (offset, 0);
38781 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38783 else if (TARGET_XCOFF)
38784 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38787 gcc_unreachable ();
38789 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38790 fuse_ops[3] = XEXP (offset, 1);
38791 output_asm_insn (insn_template, fuse_ops);
38794 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38796 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38798 fuse_ops[2] = offset;
38799 output_asm_insn (insn_template, fuse_ops);
38803 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38808 /* Wrap a TOC address that can be fused to indicate that special fusion
38809 processing is needed. */
38812 fusion_wrap_memory_address (rtx old_mem)
38814 rtx old_addr = XEXP (old_mem, 0);
38815 rtvec v = gen_rtvec (1, old_addr);
38816 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38817 return replace_equiv_address_nv (old_mem, new_addr, false);
38820 /* Given an address, convert it into the addis and load offset parts. Addresses
38821 created during the peephole2 process look like:
38822 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38823 (unspec [(...)] UNSPEC_TOCREL))
38825 Addresses created via toc fusion look like:
38826 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38829 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38833 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38835 lo = XVECEXP (addr, 0, 0);
38836 hi = gen_rtx_HIGH (Pmode, lo);
38838 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38840 hi = XEXP (addr, 0);
38841 lo = XEXP (addr, 1);
38844 gcc_unreachable ();
38850 /* Return a string to fuse an addis instruction with a gpr load to the same
38851 register that we loaded up the addis instruction. The address that is used
38852 is the logical address that was formed during peephole2:
38853 (lo_sum (high) (low-part))
38855 Or the address is the TOC address that is wrapped before register allocation:
38856 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38858 The code is complicated, so we call output_asm_insn directly, and just
38862 emit_fusion_gpr_load (rtx target, rtx mem)
38867 const char *load_str = NULL;
38870 if (GET_CODE (mem) == ZERO_EXTEND)
38871 mem = XEXP (mem, 0);
38873 gcc_assert (REG_P (target) && MEM_P (mem));
38875 addr = XEXP (mem, 0);
38876 fusion_split_address (addr, &addis_value, &load_offset);
38878 /* Now emit the load instruction to the same register. */
38879 mode = GET_MODE (mem);
38897 gcc_assert (TARGET_POWERPC64);
38902 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38905 /* Emit the addis instruction. */
38906 emit_fusion_addis (target, addis_value);
38908 /* Emit the D-form load instruction. */
38909 emit_fusion_load_store (target, target, load_offset, load_str);
38915 /* Return true if the peephole2 can combine a load/store involving a
38916 combination of an addis instruction and the memory operation. This was
38917 added to the ISA 3.0 (power9) hardware. */
38920 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38921 rtx addis_value, /* addis value. */
38922 rtx dest, /* destination (memory or register). */
38923 rtx src) /* source (register or memory). */
38925 rtx addr, mem, offset;
38926 machine_mode mode = GET_MODE (src);
38928 /* Validate arguments. */
38929 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38932 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38935 /* Ignore extend operations that are part of the load. */
38936 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
38937 src = XEXP (src, 0);
38939 /* Test for memory<-register or register<-memory. */
38940 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
38948 else if (MEM_P (src))
38950 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
38959 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38960 if (GET_CODE (addr) == PLUS)
38962 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38965 return satisfies_constraint_I (XEXP (addr, 1));
38968 else if (GET_CODE (addr) == LO_SUM)
38970 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38973 offset = XEXP (addr, 1);
38974 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
38975 return small_toc_ref (offset, GET_MODE (offset));
38977 else if (TARGET_ELF && !TARGET_POWERPC64)
38978 return CONSTANT_P (offset);
38984 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38988 operands[0] register set with addis
38989 operands[1] value set via addis
38990 operands[2] target register being loaded
38991 operands[3] D-form memory reference using operands[0].
38993 This is similar to the fusion introduced with power8, except it scales to
38994 both loads/stores and does not require the result register to be the same as
38995 the base register. At the moment, we only do this if register set with addis
38999 expand_fusion_p9_load (rtx *operands)
39001 rtx tmp_reg = operands[0];
39002 rtx addis_value = operands[1];
39003 rtx target = operands[2];
39004 rtx orig_mem = operands[3];
39005 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
39006 enum rtx_code plus_or_lo_sum;
39007 machine_mode target_mode = GET_MODE (target);
39008 machine_mode extend_mode = target_mode;
39009 machine_mode ptr_mode = Pmode;
39010 enum rtx_code extend = UNKNOWN;
39012 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
39014 extend = GET_CODE (orig_mem);
39015 orig_mem = XEXP (orig_mem, 0);
39016 target_mode = GET_MODE (orig_mem);
39019 gcc_assert (MEM_P (orig_mem));
39021 orig_addr = XEXP (orig_mem, 0);
39022 plus_or_lo_sum = GET_CODE (orig_addr);
39023 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39025 offset = XEXP (orig_addr, 1);
39026 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39027 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39029 if (extend != UNKNOWN)
39030 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
39032 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
39035 set = gen_rtx_SET (target, new_mem);
39036 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39037 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39043 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39047 operands[0] register set with addis
39048 operands[1] value set via addis
39049 operands[2] target D-form memory being stored to
39050 operands[3] register being stored
39052 This is similar to the fusion introduced with power8, except it scales to
39053 both loads/stores and does not require the result register to be the same as
39054 the base register. At the moment, we only do this if register set with addis
39058 expand_fusion_p9_store (rtx *operands)
39060 rtx tmp_reg = operands[0];
39061 rtx addis_value = operands[1];
39062 rtx orig_mem = operands[2];
39063 rtx src = operands[3];
39064 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
39065 enum rtx_code plus_or_lo_sum;
39066 machine_mode target_mode = GET_MODE (orig_mem);
39067 machine_mode ptr_mode = Pmode;
39069 gcc_assert (MEM_P (orig_mem));
39071 orig_addr = XEXP (orig_mem, 0);
39072 plus_or_lo_sum = GET_CODE (orig_addr);
39073 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39075 offset = XEXP (orig_addr, 1);
39076 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39077 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39079 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
39082 set = gen_rtx_SET (new_mem, new_src);
39083 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39084 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39090 /* Return a string to fuse an addis instruction with a load using extended
39091 fusion. The address that is used is the logical address that was formed
39092 during peephole2: (lo_sum (high) (low-part))
39094 The code is complicated, so we call output_asm_insn directly, and just
39098 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
39100 machine_mode mode = GET_MODE (reg);
39104 const char *load_string;
39107 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
39109 mem = XEXP (mem, 0);
39110 mode = GET_MODE (mem);
39113 if (GET_CODE (reg) == SUBREG)
39115 gcc_assert (SUBREG_BYTE (reg) == 0);
39116 reg = SUBREG_REG (reg);
39120 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
39123 if (FP_REGNO_P (r))
39125 if (mode == SFmode)
39126 load_string = "lfs";
39127 else if (mode == DFmode || mode == DImode)
39128 load_string = "lfd";
39130 gcc_unreachable ();
39132 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39134 if (mode == SFmode)
39135 load_string = "lxssp";
39136 else if (mode == DFmode || mode == DImode)
39137 load_string = "lxsd";
39139 gcc_unreachable ();
39141 else if (INT_REGNO_P (r))
39146 load_string = "lbz";
39149 load_string = "lhz";
39153 load_string = "lwz";
39157 if (!TARGET_POWERPC64)
39158 gcc_unreachable ();
39159 load_string = "ld";
39162 gcc_unreachable ();
39166 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
39169 fatal_insn ("emit_fusion_p9_load not MEM", mem);
39171 addr = XEXP (mem, 0);
39172 fusion_split_address (addr, &hi, &lo);
39174 /* Emit the addis instruction. */
39175 emit_fusion_addis (tmp_reg, hi);
39177 /* Emit the D-form load instruction. */
39178 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
39183 /* Return a string to fuse an addis instruction with a store using extended
39184 fusion. The address that is used is the logical address that was formed
39185 during peephole2: (lo_sum (high) (low-part))
39187 The code is complicated, so we call output_asm_insn directly, and just
39191 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
39193 machine_mode mode = GET_MODE (reg);
39197 const char *store_string;
39200 if (GET_CODE (reg) == SUBREG)
39202 gcc_assert (SUBREG_BYTE (reg) == 0);
39203 reg = SUBREG_REG (reg);
39207 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
39210 if (FP_REGNO_P (r))
39212 if (mode == SFmode)
39213 store_string = "stfs";
39214 else if (mode == DFmode)
39215 store_string = "stfd";
39217 gcc_unreachable ();
39219 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39221 if (mode == SFmode)
39222 store_string = "stxssp";
39223 else if (mode == DFmode || mode == DImode)
39224 store_string = "stxsd";
39226 gcc_unreachable ();
39228 else if (INT_REGNO_P (r))
39233 store_string = "stb";
39236 store_string = "sth";
39240 store_string = "stw";
39244 if (!TARGET_POWERPC64)
39245 gcc_unreachable ();
39246 store_string = "std";
39249 gcc_unreachable ();
39253 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
39256 fatal_insn ("emit_fusion_p9_store not MEM", mem);
39258 addr = XEXP (mem, 0);
39259 fusion_split_address (addr, &hi, &lo);
39261 /* Emit the addis instruction. */
39262 emit_fusion_addis (tmp_reg, hi);
39264 /* Emit the D-form load instruction. */
39265 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
39270 #ifdef RS6000_GLIBC_ATOMIC_FENV
39271 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39272 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39275 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39278 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39280 if (!TARGET_HARD_FLOAT)
39282 #ifdef RS6000_GLIBC_ATOMIC_FENV
39283 if (atomic_hold_decl == NULL_TREE)
39286 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39287 get_identifier ("__atomic_feholdexcept"),
39288 build_function_type_list (void_type_node,
39289 double_ptr_type_node,
39291 TREE_PUBLIC (atomic_hold_decl) = 1;
39292 DECL_EXTERNAL (atomic_hold_decl) = 1;
39295 if (atomic_clear_decl == NULL_TREE)
39298 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39299 get_identifier ("__atomic_feclearexcept"),
39300 build_function_type_list (void_type_node,
39302 TREE_PUBLIC (atomic_clear_decl) = 1;
39303 DECL_EXTERNAL (atomic_clear_decl) = 1;
39306 tree const_double = build_qualified_type (double_type_node,
39308 tree const_double_ptr = build_pointer_type (const_double);
39309 if (atomic_update_decl == NULL_TREE)
39312 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39313 get_identifier ("__atomic_feupdateenv"),
39314 build_function_type_list (void_type_node,
39317 TREE_PUBLIC (atomic_update_decl) = 1;
39318 DECL_EXTERNAL (atomic_update_decl) = 1;
39321 tree fenv_var = create_tmp_var_raw (double_type_node);
39322 TREE_ADDRESSABLE (fenv_var) = 1;
39323 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39325 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39326 *clear = build_call_expr (atomic_clear_decl, 0);
39327 *update = build_call_expr (atomic_update_decl, 1,
39328 fold_convert (const_double_ptr, fenv_addr));
39333 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39334 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39335 tree call_mffs = build_call_expr (mffs, 0);
39337 /* Generates the equivalent of feholdexcept (&fenv_var)
39339 *fenv_var = __builtin_mffs ();
39341 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39342 __builtin_mtfsf (0xff, fenv_hold); */
39344 /* Mask to clear everything except for the rounding modes and non-IEEE
39345 arithmetic flag. */
39346 const unsigned HOST_WIDE_INT hold_exception_mask =
39347 HOST_WIDE_INT_C (0xffffffff00000007);
39349 tree fenv_var = create_tmp_var_raw (double_type_node);
39351 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39353 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39354 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39355 build_int_cst (uint64_type_node,
39356 hold_exception_mask));
39358 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39361 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39362 build_int_cst (unsigned_type_node, 0xff),
39365 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39367 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39369 double fenv_clear = __builtin_mffs ();
39370 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39371 __builtin_mtfsf (0xff, fenv_clear); */
39373 /* Mask to clear everything except for the rounding modes and non-IEEE
39374 arithmetic flag. */
39375 const unsigned HOST_WIDE_INT clear_exception_mask =
39376 HOST_WIDE_INT_C (0xffffffff00000000);
39378 tree fenv_clear = create_tmp_var_raw (double_type_node);
39380 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39382 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39383 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39385 build_int_cst (uint64_type_node,
39386 clear_exception_mask));
39388 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39389 fenv_clear_llu_and);
39391 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39392 build_int_cst (unsigned_type_node, 0xff),
39395 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39397 /* Generates the equivalent of feupdateenv (&fenv_var)
39399 double old_fenv = __builtin_mffs ();
39400 double fenv_update;
39401 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39402 (*(uint64_t*)fenv_var 0x1ff80fff);
39403 __builtin_mtfsf (0xff, fenv_update); */
39405 const unsigned HOST_WIDE_INT update_exception_mask =
39406 HOST_WIDE_INT_C (0xffffffff1fffff00);
39407 const unsigned HOST_WIDE_INT new_exception_mask =
39408 HOST_WIDE_INT_C (0x1ff80fff);
39410 tree old_fenv = create_tmp_var_raw (double_type_node);
39411 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39413 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39414 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39415 build_int_cst (uint64_type_node,
39416 update_exception_mask));
39418 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39419 build_int_cst (uint64_type_node,
39420 new_exception_mask));
39422 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39423 old_llu_and, new_llu_and);
39425 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39428 tree update_mtfsf = build_call_expr (mtfsf, 2,
39429 build_int_cst (unsigned_type_node, 0xff),
39430 fenv_update_mtfsf);
39432 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39436 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39438 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39440 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39441 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39443 /* The destination of the vmrgew instruction layout is:
39444 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39445 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39446 vmrgew instruction will be correct. */
39447 if (VECTOR_ELT_ORDER_BIG)
39449 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39451 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39456 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39457 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39460 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39461 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39463 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39464 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39466 if (VECTOR_ELT_ORDER_BIG)
39467 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39469 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39473 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39475 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39477 rtx_tmp0 = gen_reg_rtx (V2DImode);
39478 rtx_tmp1 = gen_reg_rtx (V2DImode);
39480 /* The destination of the vmrgew instruction layout is:
39481 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39482 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39483 vmrgew instruction will be correct. */
39484 if (VECTOR_ELT_ORDER_BIG)
39486 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39487 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39491 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39492 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39495 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39496 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39498 if (signed_convert)
39500 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39501 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39505 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39506 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39509 if (VECTOR_ELT_ORDER_BIG)
39510 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39512 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39516 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39519 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39521 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39522 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39524 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39525 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39527 rtx_tmp2 = gen_reg_rtx (V4SImode);
39528 rtx_tmp3 = gen_reg_rtx (V4SImode);
39530 if (signed_convert)
39532 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39533 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39537 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39538 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39541 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39544 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39547 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39548 optimization_type opt_type)
39553 return (opt_type == OPTIMIZE_FOR_SPEED
39554 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39561 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39563 static HOST_WIDE_INT
39564 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39566 if (TREE_CODE (exp) == STRING_CST
39567 && (STRICT_ALIGNMENT || !optimize_size))
39568 return MAX (align, BITS_PER_WORD);
39572 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39574 static HOST_WIDE_INT
39575 rs6000_starting_frame_offset (void)
39577 if (FRAME_GROWS_DOWNWARD)
39579 return RS6000_STARTING_FRAME_OFFSET;
39582 struct gcc_target targetm = TARGET_INITIALIZER;
39584 #include "gt-rs6000.h"