1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float;
228 static bool rs6000_passes_long_double;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
248 static int dbg_cost_ctrl;
250 /* Built in types. */
251 tree rs6000_builtin_types[RS6000_BTI_MAX];
252 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized, need_toc_init;
256 char toc_label_name[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more;
262 static GTY(()) section *read_only_data_section;
263 static GTY(()) section *private_data_section;
264 static GTY(()) section *tls_data_section;
265 static GTY(()) section *tls_private_data_section;
266 static GTY(()) section *read_only_private_data_section;
267 static GTY(()) section *sdata2_section;
268 static GTY(()) section *toc_section;
270 struct builtin_description
272 const HOST_WIDE_INT mask;
273 const enum insn_code icode;
274 const char *const name;
275 const enum rs6000_builtins code;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
280 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align[NUM_MACHINE_MODES];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask {
299 RECIP_SF_DIV = 0x001, /* Use divide estimate */
300 RECIP_DF_DIV = 0x002,
301 RECIP_V4SF_DIV = 0x004,
302 RECIP_V2DF_DIV = 0x008,
304 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT = 0x020,
306 RECIP_V4SF_RSQRT = 0x040,
307 RECIP_V2DF_RSQRT = 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
315 RECIP_HIGH_PRECISION = RECIP_ALL,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
322 /* -mrecip options. */
325 const char *string; /* option name */
326 unsigned int mask; /* mask bits to set */
327 } recip_options[] = {
328 { "all", RECIP_ALL },
329 { "none", RECIP_NONE },
330 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
334 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT) },
336 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
337 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9 },
347 { "power8", PPC_PLATFORM_POWER8 },
348 { "power7", PPC_PLATFORM_POWER7 },
349 { "power6x", PPC_PLATFORM_POWER6X },
350 { "power6", PPC_PLATFORM_POWER6 },
351 { "power5+", PPC_PLATFORM_POWER5_PLUS },
352 { "power5", PPC_PLATFORM_POWER5 },
353 { "ppc970", PPC_PLATFORM_PPC970 },
354 { "power4", PPC_PLATFORM_POWER4 },
355 { "ppca2", PPC_PLATFORM_PPCA2 },
356 { "ppc476", PPC_PLATFORM_PPC476 },
357 { "ppc464", PPC_PLATFORM_PPC464 },
358 { "ppc440", PPC_PLATFORM_PPC440 },
359 { "ppc405", PPC_PLATFORM_PPC405 },
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
376 { "booke", PPC_FEATURE_BOOKE, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
384 { "notb", PPC_FEATURE_NO_TB, 0 },
385 { "pa6t", PPC_FEATURE_PA6T, 0 },
386 { "power4", PPC_FEATURE_POWER4, 0 },
387 { "power5", PPC_FEATURE_POWER5, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
390 { "ppc32", PPC_FEATURE_32, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
392 { "ppc64", PPC_FEATURE_64, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
394 { "smt", PPC_FEATURE_SMT, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
412 { "darn", PPC_FEATURE2_DARN, 1 },
413 { "scv", PPC_FEATURE2_SCV, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT = 0, /* default clone. */
422 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
432 const char *name; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type {
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type {
489 RELOAD_REG_GPR, /* General purpose registers. */
490 RELOAD_REG_FPR, /* Traditional floating point regs. */
491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type {
504 const char *name; /* Register class name. */
505 int reg; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
509 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr {
531 enum insn_code reload_load; /* INSN to reload for loading. */
532 enum insn_code reload_store; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
537 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode)
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode)
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode)
562 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
598 in_set = single_set (in_insn);
601 if (MEM_P (SET_DEST (in_set)))
603 out_set = single_set (out_insn);
606 out_pat = PATTERN (out_insn);
607 if (GET_CODE (out_pat) == PARALLEL)
609 for (i = 0; i < XVECLEN (out_pat, 0); i++)
611 out_exp = XVECEXP (out_pat, 0, i);
612 if ((GET_CODE (out_exp) == CLOBBER)
613 || (GET_CODE (out_exp) == USE))
615 else if (GET_CODE (out_exp) != SET)
624 in_pat = PATTERN (in_insn);
625 if (GET_CODE (in_pat) != PARALLEL)
628 for (i = 0; i < XVECLEN (in_pat, 0); i++)
630 in_exp = XVECEXP (in_pat, 0, i);
631 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
633 else if (GET_CODE (in_exp) != SET)
636 if (MEM_P (SET_DEST (in_exp)))
638 out_set = single_set (out_insn);
641 out_pat = PATTERN (out_insn);
642 if (GET_CODE (out_pat) != PARALLEL)
644 for (j = 0; j < XVECLEN (out_pat, 0); j++)
646 out_exp = XVECEXP (out_pat, 0, j);
647 if ((GET_CODE (out_exp) == CLOBBER)
648 || (GET_CODE (out_exp) == USE))
650 else if (GET_CODE (out_exp) != SET)
657 return store_data_bypass_p (out_insn, in_insn);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs *rs6000_cost;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost = {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost = {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost = {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost = {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost = {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost = {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost = {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost = {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost = {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost = {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost = {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost = {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost = {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost = {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost = {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost = {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost = {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost = {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost = {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost = {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost = {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost = {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost = {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost = {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost = {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost = {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost = {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost = {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost = {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost = {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type {
1307 const enum insn_code icode;
1308 const HOST_WIDE_INT mask;
1309 const unsigned attr;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1332 static struct machine_function * rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1338 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1339 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1340 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1343 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1345 static bool is_microcoded_insn (rtx_insn *);
1346 static bool is_nonpipeline_insn (rtx_insn *);
1347 static bool is_cracked_insn (rtx_insn *);
1348 static bool is_load_insn (rtx, rtx *);
1349 static bool is_store_insn (rtx, rtx *);
1350 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1351 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1352 static bool insn_must_be_first_in_group (rtx_insn *);
1353 static bool insn_must_be_last_in_group (rtx_insn *);
1354 static void altivec_init_builtins (void);
1355 static tree builtin_function_type (machine_mode, machine_mode,
1356 machine_mode, machine_mode,
1357 enum rs6000_builtins, const char *name);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t *rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx, void *);
1362 int easy_vector_constant (rtx, machine_mode);
1363 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1364 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1365 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1368 static void macho_branch_islands (void);
1369 static tree get_prev_label (tree);
1371 static bool rs6000_mode_dependent_address (const_rtx);
1372 static bool rs6000_debug_mode_dependent_address (const_rtx);
1373 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1374 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1376 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1380 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1382 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1385 static bool rs6000_debug_can_change_mode_class (machine_mode,
1388 static bool rs6000_save_toc_in_prologue_p (void);
1389 static rtx rs6000_internal_arg_pointer (void);
1391 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1392 = rs6000_mode_dependent_address;
1394 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1396 = rs6000_secondary_reload_class;
1398 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1399 = rs6000_preferred_reload_class;
1401 const int INSN_NOT_AVAILABLE = -1;
1403 static void rs6000_print_isa_options (FILE *, int, const char *,
1405 static void rs6000_print_builtin_options (FILE *, int, const char *,
1407 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1409 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1410 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1411 enum rs6000_reg_type,
1413 secondary_reload_info *,
1415 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1416 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1417 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1419 /* Hash table stuff for keeping track of TOC entries. */
1421 struct GTY((for_user)) toc_hash_struct
1423 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1424 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1426 machine_mode key_mode;
1430 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1432 static hashval_t hash (toc_hash_struct *);
1433 static bool equal (toc_hash_struct *, toc_hash_struct *);
1436 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1438 /* Hash table to keep track of the argument types for builtin functions. */
1440 struct GTY((for_user)) builtin_hash_struct
1443 machine_mode mode[4]; /* return value + 3 arguments. */
1444 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1447 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1449 static hashval_t hash (builtin_hash_struct *);
1450 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1453 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1456 /* Default register names. */
1457 char rs6000_reg_names[][8] =
1460 "0", "1", "2", "3", "4", "5", "6", "7",
1461 "8", "9", "10", "11", "12", "13", "14", "15",
1462 "16", "17", "18", "19", "20", "21", "22", "23",
1463 "24", "25", "26", "27", "28", "29", "30", "31",
1465 "0", "1", "2", "3", "4", "5", "6", "7",
1466 "8", "9", "10", "11", "12", "13", "14", "15",
1467 "16", "17", "18", "19", "20", "21", "22", "23",
1468 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "lr", "ctr", "ca", "ap",
1477 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* vrsave vscr sfp */
1479 "vrsave", "vscr", "sfp",
1482 #ifdef TARGET_REGNAMES
1483 static const char alt_reg_names[][8] =
1486 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1487 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1488 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1489 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1491 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1492 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1493 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1494 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1496 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1497 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1498 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1499 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1501 "lr", "ctr", "ca", "ap",
1503 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* vrsave vscr sfp */
1505 "vrsave", "vscr", "sfp",
1509 /* Table of valid machine attributes. */
1511 static const struct attribute_spec rs6000_attribute_table[] =
1513 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1514 affects_type_identity, handler, exclude } */
1515 { "altivec", 1, 1, false, true, false, false,
1516 rs6000_handle_altivec_attribute, NULL },
1517 { "longcall", 0, 0, false, true, true, false,
1518 rs6000_handle_longcall_attribute, NULL },
1519 { "shortcall", 0, 0, false, true, true, false,
1520 rs6000_handle_longcall_attribute, NULL },
1521 { "ms_struct", 0, 0, false, false, false, false,
1522 rs6000_handle_struct_attribute, NULL },
1523 { "gcc_struct", 0, 0, false, false, false, false,
1524 rs6000_handle_struct_attribute, NULL },
1525 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1526 SUBTARGET_ATTRIBUTE_TABLE,
1528 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1531 #ifndef TARGET_PROFILE_KERNEL
1532 #define TARGET_PROFILE_KERNEL 0
1535 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1536 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1538 /* Initialize the GCC target structure. */
1539 #undef TARGET_ATTRIBUTE_TABLE
1540 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1541 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1542 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1543 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1544 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1546 #undef TARGET_ASM_ALIGNED_DI_OP
1547 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1549 /* Default unaligned ops are only provided for ELF. Find the ops needed
1550 for non-ELF systems. */
1551 #ifndef OBJECT_FORMAT_ELF
1553 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1555 #undef TARGET_ASM_UNALIGNED_HI_OP
1556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1557 #undef TARGET_ASM_UNALIGNED_SI_OP
1558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1559 #undef TARGET_ASM_UNALIGNED_DI_OP
1560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1569 #undef TARGET_ASM_ALIGNED_DI_OP
1570 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1574 /* This hook deals with fixups for relocatable code and DI-mode objects
1576 #undef TARGET_ASM_INTEGER
1577 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1579 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1580 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1581 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1584 #undef TARGET_SET_UP_BY_PROLOGUE
1585 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1587 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1588 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1589 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1590 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1591 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1592 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1593 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1594 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1595 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1597 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1600 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1601 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1603 #undef TARGET_INTERNAL_ARG_POINTER
1604 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1606 #undef TARGET_HAVE_TLS
1607 #define TARGET_HAVE_TLS HAVE_AS_TLS
1609 #undef TARGET_CANNOT_FORCE_CONST_MEM
1610 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1612 #undef TARGET_DELEGITIMIZE_ADDRESS
1613 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1615 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1616 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1618 #undef TARGET_LEGITIMATE_COMBINED_INSN
1619 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1621 #undef TARGET_ASM_FUNCTION_PROLOGUE
1622 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1623 #undef TARGET_ASM_FUNCTION_EPILOGUE
1624 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1626 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1627 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1629 #undef TARGET_LEGITIMIZE_ADDRESS
1630 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1632 #undef TARGET_SCHED_VARIABLE_ISSUE
1633 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1635 #undef TARGET_SCHED_ISSUE_RATE
1636 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1637 #undef TARGET_SCHED_ADJUST_COST
1638 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1639 #undef TARGET_SCHED_ADJUST_PRIORITY
1640 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1641 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1642 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1643 #undef TARGET_SCHED_INIT
1644 #define TARGET_SCHED_INIT rs6000_sched_init
1645 #undef TARGET_SCHED_FINISH
1646 #define TARGET_SCHED_FINISH rs6000_sched_finish
1647 #undef TARGET_SCHED_REORDER
1648 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1649 #undef TARGET_SCHED_REORDER2
1650 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1652 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1653 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1658 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1659 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1660 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1661 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1662 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1663 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1664 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1665 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1667 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1668 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1670 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1671 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1672 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1673 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1674 rs6000_builtin_support_vector_misalignment
1675 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1676 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1677 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1678 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1679 rs6000_builtin_vectorization_cost
1680 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1681 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1682 rs6000_preferred_simd_mode
1683 #undef TARGET_VECTORIZE_INIT_COST
1684 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1685 #undef TARGET_VECTORIZE_ADD_STMT_COST
1686 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1687 #undef TARGET_VECTORIZE_FINISH_COST
1688 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1689 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1690 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1692 #undef TARGET_INIT_BUILTINS
1693 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1694 #undef TARGET_BUILTIN_DECL
1695 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1697 #undef TARGET_FOLD_BUILTIN
1698 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1699 #undef TARGET_GIMPLE_FOLD_BUILTIN
1700 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1702 #undef TARGET_EXPAND_BUILTIN
1703 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1705 #undef TARGET_MANGLE_TYPE
1706 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1708 #undef TARGET_INIT_LIBFUNCS
1709 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1712 #undef TARGET_BINDS_LOCAL_P
1713 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1716 #undef TARGET_MS_BITFIELD_LAYOUT_P
1717 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1719 #undef TARGET_ASM_OUTPUT_MI_THUNK
1720 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1722 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1723 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1726 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1728 #undef TARGET_REGISTER_MOVE_COST
1729 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1730 #undef TARGET_MEMORY_MOVE_COST
1731 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1732 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1733 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
1734 rs6000_ira_change_pseudo_allocno_class
1735 #undef TARGET_CANNOT_COPY_INSN_P
1736 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1737 #undef TARGET_RTX_COSTS
1738 #define TARGET_RTX_COSTS rs6000_rtx_costs
1739 #undef TARGET_ADDRESS_COST
1740 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1741 #undef TARGET_INSN_COST
1742 #define TARGET_INSN_COST rs6000_insn_cost
1744 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1745 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1747 #undef TARGET_PROMOTE_FUNCTION_MODE
1748 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1750 #undef TARGET_RETURN_IN_MEMORY
1751 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1753 #undef TARGET_RETURN_IN_MSB
1754 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1759 /* Always strict argument naming on rs6000. */
1760 #undef TARGET_STRICT_ARGUMENT_NAMING
1761 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1762 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1763 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_SPLIT_COMPLEX_ARG
1765 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1766 #undef TARGET_MUST_PASS_IN_STACK
1767 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1768 #undef TARGET_PASS_BY_REFERENCE
1769 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1770 #undef TARGET_ARG_PARTIAL_BYTES
1771 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1772 #undef TARGET_FUNCTION_ARG_ADVANCE
1773 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1774 #undef TARGET_FUNCTION_ARG
1775 #define TARGET_FUNCTION_ARG rs6000_function_arg
1776 #undef TARGET_FUNCTION_ARG_PADDING
1777 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1778 #undef TARGET_FUNCTION_ARG_BOUNDARY
1779 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1781 #undef TARGET_BUILD_BUILTIN_VA_LIST
1782 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1784 #undef TARGET_EXPAND_BUILTIN_VA_START
1785 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1788 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1790 #undef TARGET_EH_RETURN_FILTER_MODE
1791 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1793 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1794 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1796 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1797 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1799 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1800 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1802 #undef TARGET_FLOATN_MODE
1803 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1805 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1806 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1808 #undef TARGET_MD_ASM_ADJUST
1809 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1811 #undef TARGET_OPTION_OVERRIDE
1812 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1814 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1815 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1816 rs6000_builtin_vectorized_function
1818 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1820 rs6000_builtin_md_vectorized_function
1822 #undef TARGET_STACK_PROTECT_GUARD
1823 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1826 #undef TARGET_STACK_PROTECT_FAIL
1827 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1831 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1832 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1835 /* Use a 32-bit anchor range. This leads to sequences like:
1837 addis tmp,anchor,high
1840 where tmp itself acts as an anchor, and can be shared between
1841 accesses to the same 64k page. */
1842 #undef TARGET_MIN_ANCHOR_OFFSET
1843 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1844 #undef TARGET_MAX_ANCHOR_OFFSET
1845 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1846 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1847 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1848 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1849 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1851 #undef TARGET_BUILTIN_RECIPROCAL
1852 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1854 #undef TARGET_SECONDARY_RELOAD
1855 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1856 #undef TARGET_SECONDARY_MEMORY_NEEDED
1857 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1859 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1861 #undef TARGET_LEGITIMATE_ADDRESS_P
1862 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1864 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1865 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1867 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1868 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1870 #undef TARGET_CAN_ELIMINATE
1871 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1873 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1874 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1876 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1877 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1879 #undef TARGET_TRAMPOLINE_INIT
1880 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1882 #undef TARGET_FUNCTION_VALUE
1883 #define TARGET_FUNCTION_VALUE rs6000_function_value
1885 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1886 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1888 #undef TARGET_OPTION_SAVE
1889 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1891 #undef TARGET_OPTION_RESTORE
1892 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1894 #undef TARGET_OPTION_PRINT
1895 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1897 #undef TARGET_CAN_INLINE_P
1898 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1900 #undef TARGET_SET_CURRENT_FUNCTION
1901 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1903 #undef TARGET_LEGITIMATE_CONSTANT_P
1904 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1906 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1907 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1909 #undef TARGET_CAN_USE_DOLOOP_P
1910 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1912 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1913 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1916 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1919 #undef TARGET_UNWIND_WORD_MODE
1920 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1922 #undef TARGET_OFFLOAD_OPTIONS
1923 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1925 #undef TARGET_C_MODE_FOR_SUFFIX
1926 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1928 #undef TARGET_INVALID_BINARY_OP
1929 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1931 #undef TARGET_OPTAB_SUPPORTED_P
1932 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1934 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1935 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1937 #undef TARGET_COMPARE_VERSION_PRIORITY
1938 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1940 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1941 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1942 rs6000_generate_version_dispatcher_body
1944 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1945 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1946 rs6000_get_function_versions_dispatcher
1948 #undef TARGET_OPTION_FUNCTION_VERSIONS
1949 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1951 #undef TARGET_HARD_REGNO_NREGS
1952 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1953 #undef TARGET_HARD_REGNO_MODE_OK
1954 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1956 #undef TARGET_MODES_TIEABLE_P
1957 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1959 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1960 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1961 rs6000_hard_regno_call_part_clobbered
1963 #undef TARGET_SLOW_UNALIGNED_ACCESS
1964 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1966 #undef TARGET_CAN_CHANGE_MODE_CLASS
1967 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1969 #undef TARGET_CONSTANT_ALIGNMENT
1970 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1972 #undef TARGET_STARTING_FRAME_OFFSET
1973 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1975 #if TARGET_ELF && RS6000_WEAK
1976 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1977 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1980 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1981 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1983 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1984 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1987 /* Processor table. */
1990 const char *const name; /* Canonical processor name. */
1991 const enum processor_type processor; /* Processor type enum value. */
1992 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1995 static struct rs6000_ptt const processor_target_table[] =
1997 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1998 #include "rs6000-cpus.def"
2002 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2006 rs6000_cpu_name_lookup (const char *name)
2012 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2013 if (! strcmp (name, processor_target_table[i].name))
2021 /* Return number of consecutive hard regs needed starting at reg REGNO
2022 to hold something of mode MODE.
2023 This is ordinarily the length in words of a value of mode MODE
2024 but can be less for certain modes in special long registers.
2026 POWER and PowerPC GPRs hold 32 bits worth;
2027 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2030 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2032 unsigned HOST_WIDE_INT reg_size;
2034 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2035 128-bit floating point that can go in vector registers, which has VSX
2036 memory addressing. */
2037 if (FP_REGNO_P (regno))
2038 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2039 ? UNITS_PER_VSX_WORD
2040 : UNITS_PER_FP_WORD);
2042 else if (ALTIVEC_REGNO_P (regno))
2043 reg_size = UNITS_PER_ALTIVEC_WORD;
2046 reg_size = UNITS_PER_WORD;
2048 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2054 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2056 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2058 if (COMPLEX_MODE_P (mode))
2059 mode = GET_MODE_INNER (mode);
2061 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2062 register combinations, and use PTImode where we need to deal with quad
2063 word memory operations. Don't allow quad words in the argument or frame
2064 pointer registers, just registers 0..31. */
2065 if (mode == PTImode)
2066 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2067 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2068 && ((regno & 1) == 0));
2070 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2071 implementations. Don't allow an item to be split between a FP register
2072 and an Altivec register. Allow TImode in all VSX registers if the user
2074 if (TARGET_VSX && VSX_REGNO_P (regno)
2075 && (VECTOR_MEM_VSX_P (mode)
2076 || FLOAT128_VECTOR_P (mode)
2077 || reg_addr[mode].scalar_in_vmx_p
2079 || (TARGET_VADDUQM && mode == V1TImode)))
2081 if (FP_REGNO_P (regno))
2082 return FP_REGNO_P (last_regno);
2084 if (ALTIVEC_REGNO_P (regno))
2086 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2089 return ALTIVEC_REGNO_P (last_regno);
2093 /* The GPRs can hold any mode, but values bigger than one register
2094 cannot go past R31. */
2095 if (INT_REGNO_P (regno))
2096 return INT_REGNO_P (last_regno);
2098 /* The float registers (except for VSX vector modes) can only hold floating
2099 modes and DImode. */
2100 if (FP_REGNO_P (regno))
2102 if (FLOAT128_VECTOR_P (mode))
2105 if (SCALAR_FLOAT_MODE_P (mode)
2106 && (mode != TDmode || (regno % 2) == 0)
2107 && FP_REGNO_P (last_regno))
2110 if (GET_MODE_CLASS (mode) == MODE_INT)
2112 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2115 if (TARGET_P8_VECTOR && (mode == SImode))
2118 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2194 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2197 rs6000_hard_regno_call_part_clobbered (rtx_insn *insn ATTRIBUTE_UNUSED,
2198 unsigned int regno, machine_mode mode)
2202 && GET_MODE_SIZE (mode) > 4
2203 && INT_REGNO_P (regno))
2207 && FP_REGNO_P (regno)
2208 && GET_MODE_SIZE (mode) > 8
2209 && !FLOAT128_2REG_P (mode))
2215 /* Print interesting facts about registers. */
2217 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2221 for (r = first_regno; r <= last_regno; ++r)
2223 const char *comma = "";
2226 if (first_regno == last_regno)
2227 fprintf (stderr, "%s:\t", reg_name);
2229 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2232 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2233 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2237 fprintf (stderr, ",\n\t");
2242 if (rs6000_hard_regno_nregs[m][r] > 1)
2243 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2244 rs6000_hard_regno_nregs[m][r]);
2246 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2251 if (call_used_regs[r])
2255 fprintf (stderr, ",\n\t");
2260 len += fprintf (stderr, "%s%s", comma, "call-used");
2268 fprintf (stderr, ",\n\t");
2273 len += fprintf (stderr, "%s%s", comma, "fixed");
2279 fprintf (stderr, ",\n\t");
2283 len += fprintf (stderr, "%sreg-class = %s", comma,
2284 reg_class_names[(int)rs6000_regno_regclass[r]]);
2289 fprintf (stderr, ",\n\t");
2293 fprintf (stderr, "%sregno = %d\n", comma, r);
2298 rs6000_debug_vector_unit (enum rs6000_vector v)
2304 case VECTOR_NONE: ret = "none"; break;
2305 case VECTOR_ALTIVEC: ret = "altivec"; break;
2306 case VECTOR_VSX: ret = "vsx"; break;
2307 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2308 default: ret = "unknown"; break;
2314 /* Inner function printing just the address mask for a particular reload
2316 DEBUG_FUNCTION char *
2317 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2322 if ((mask & RELOAD_REG_VALID) != 0)
2324 else if (keep_spaces)
2327 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2329 else if (keep_spaces)
2332 if ((mask & RELOAD_REG_INDEXED) != 0)
2334 else if (keep_spaces)
2337 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2339 else if ((mask & RELOAD_REG_OFFSET) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2346 else if (keep_spaces)
2349 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2351 else if (keep_spaces)
2354 if ((mask & RELOAD_REG_AND_M16) != 0)
2356 else if (keep_spaces)
2364 /* Print the address masks in a human readble fashion. */
2366 rs6000_debug_print_mode (ssize_t m)
2371 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2372 for (rc = 0; rc < N_RELOAD_REG; rc++)
2373 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2374 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2376 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2377 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2379 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2380 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2381 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2385 spaces += sizeof (" Reload=sl") - 1;
2387 if (reg_addr[m].scalar_in_vmx_p)
2389 fprintf (stderr, "%*s Upper=y", spaces, "");
2393 spaces += sizeof (" Upper=y") - 1;
2395 if (rs6000_vector_unit[m] != VECTOR_NONE
2396 || rs6000_vector_mem[m] != VECTOR_NONE)
2398 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2400 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2401 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2404 fputs ("\n", stderr);
2407 #define DEBUG_FMT_ID "%-32s= "
2408 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2409 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2410 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2412 /* Print various interesting information with -mdebug=reg. */
2414 rs6000_debug_reg_global (void)
2416 static const char *const tf[2] = { "false", "true" };
2417 const char *nl = (const char *)0;
2420 char costly_num[20];
2422 char flags_buffer[40];
2423 const char *costly_str;
2424 const char *nop_str;
2425 const char *trace_str;
2426 const char *abi_str;
2427 const char *cmodel_str;
2428 struct cl_target_option cl_opts;
2430 /* Modes we want tieable information on. */
2431 static const machine_mode print_tieable_modes[] = {
2465 /* Virtual regs we are interested in. */
2466 const static struct {
2467 int regno; /* register number. */
2468 const char *name; /* register name. */
2469 } virtual_regs[] = {
2470 { STACK_POINTER_REGNUM, "stack pointer:" },
2471 { TOC_REGNUM, "toc: " },
2472 { STATIC_CHAIN_REGNUM, "static chain: " },
2473 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2474 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2475 { ARG_POINTER_REGNUM, "arg pointer: " },
2476 { FRAME_POINTER_REGNUM, "frame pointer:" },
2477 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2478 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2479 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2480 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2481 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2482 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2483 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2484 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2485 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2488 fputs ("\nHard register information:\n", stderr);
2489 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2490 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2491 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2494 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2495 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2496 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2497 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2498 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2499 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2501 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2502 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2503 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2507 "d reg_class = %s\n"
2508 "f reg_class = %s\n"
2509 "v reg_class = %s\n"
2510 "wa reg_class = %s\n"
2511 "wd reg_class = %s\n"
2512 "we reg_class = %s\n"
2513 "wf reg_class = %s\n"
2514 "wg reg_class = %s\n"
2515 "wi reg_class = %s\n"
2516 "wp reg_class = %s\n"
2517 "wq reg_class = %s\n"
2518 "wr reg_class = %s\n"
2519 "ws reg_class = %s\n"
2520 "wt reg_class = %s\n"
2521 "wv reg_class = %s\n"
2522 "ww reg_class = %s\n"
2523 "wx reg_class = %s\n"
2524 "wA reg_class = %s\n"
2526 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2527 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2528 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2529 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2530 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2531 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2532 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2533 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2534 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2535 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2536 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2537 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2538 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2539 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2540 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2541 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2542 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2543 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
2546 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2547 rs6000_debug_print_mode (m);
2549 fputs ("\n", stderr);
2551 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2553 machine_mode mode1 = print_tieable_modes[m1];
2554 bool first_time = true;
2556 nl = (const char *)0;
2557 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2559 machine_mode mode2 = print_tieable_modes[m2];
2560 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2564 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2569 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2574 fputs ("\n", stderr);
2580 if (rs6000_recip_control)
2582 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2584 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2585 if (rs6000_recip_bits[m])
2588 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2590 (RS6000_RECIP_AUTO_RE_P (m)
2592 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2593 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2595 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2598 fputs ("\n", stderr);
2601 if (rs6000_cpu_index >= 0)
2603 const char *name = processor_target_table[rs6000_cpu_index].name;
2605 = processor_target_table[rs6000_cpu_index].target_enable;
2607 sprintf (flags_buffer, "-mcpu=%s flags", name);
2608 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2611 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2613 if (rs6000_tune_index >= 0)
2615 const char *name = processor_target_table[rs6000_tune_index].name;
2617 = processor_target_table[rs6000_tune_index].target_enable;
2619 sprintf (flags_buffer, "-mtune=%s flags", name);
2620 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2623 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2625 cl_target_option_save (&cl_opts, &global_options);
2626 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2629 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2630 rs6000_isa_flags_explicit);
2632 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2633 rs6000_builtin_mask);
2635 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2637 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2638 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2640 switch (rs6000_sched_costly_dep)
2642 case max_dep_latency:
2643 costly_str = "max_dep_latency";
2647 costly_str = "no_dep_costly";
2650 case all_deps_costly:
2651 costly_str = "all_deps_costly";
2654 case true_store_to_load_dep_costly:
2655 costly_str = "true_store_to_load_dep_costly";
2658 case store_to_load_dep_costly:
2659 costly_str = "store_to_load_dep_costly";
2663 costly_str = costly_num;
2664 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2668 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2670 switch (rs6000_sched_insert_nops)
2672 case sched_finish_regroup_exact:
2673 nop_str = "sched_finish_regroup_exact";
2676 case sched_finish_pad_groups:
2677 nop_str = "sched_finish_pad_groups";
2680 case sched_finish_none:
2681 nop_str = "sched_finish_none";
2686 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2690 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2692 switch (rs6000_sdata)
2699 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2703 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2707 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2712 switch (rs6000_traceback)
2714 case traceback_default: trace_str = "default"; break;
2715 case traceback_none: trace_str = "none"; break;
2716 case traceback_part: trace_str = "part"; break;
2717 case traceback_full: trace_str = "full"; break;
2718 default: trace_str = "unknown"; break;
2721 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2723 switch (rs6000_current_cmodel)
2725 case CMODEL_SMALL: cmodel_str = "small"; break;
2726 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2727 case CMODEL_LARGE: cmodel_str = "large"; break;
2728 default: cmodel_str = "unknown"; break;
2731 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2733 switch (rs6000_current_abi)
2735 case ABI_NONE: abi_str = "none"; break;
2736 case ABI_AIX: abi_str = "aix"; break;
2737 case ABI_ELFv2: abi_str = "ELFv2"; break;
2738 case ABI_V4: abi_str = "V4"; break;
2739 case ABI_DARWIN: abi_str = "darwin"; break;
2740 default: abi_str = "unknown"; break;
2743 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2745 if (rs6000_altivec_abi)
2746 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2748 if (rs6000_darwin64_abi)
2749 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2751 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2752 (TARGET_SOFT_FLOAT ? "true" : "false"));
2754 if (TARGET_LINK_STACK)
2755 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2757 if (TARGET_P8_FUSION)
2761 strcpy (options, "power8");
2762 if (TARGET_P8_FUSION_SIGN)
2763 strcat (options, ", sign");
2765 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2768 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2769 TARGET_SECURE_PLT ? "secure" : "bss");
2770 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2771 aix_struct_return ? "aix" : "sysv");
2772 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2773 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2774 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2775 tf[!!rs6000_align_branch_targets]);
2776 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2777 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2778 rs6000_long_double_type_size);
2779 if (rs6000_long_double_type_size > 64)
2781 fprintf (stderr, DEBUG_FMT_S, "long double type",
2782 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2783 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2784 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2786 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2787 (int)rs6000_sched_restricted_insns_priority);
2788 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2790 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2791 (int)RS6000_BUILTIN_COUNT);
2793 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2794 (int)TARGET_FLOAT128_ENABLE_TYPE);
2797 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2798 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2800 if (TARGET_DIRECT_MOVE_128)
2801 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2802 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2806 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2807 legitimate address support to figure out the appropriate addressing to
2811 rs6000_setup_reg_addr_masks (void)
2813 ssize_t rc, reg, m, nregs;
2814 addr_mask_type any_addr_mask, addr_mask;
2816 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2818 machine_mode m2 = (machine_mode) m;
2819 bool complex_p = false;
2820 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2823 if (COMPLEX_MODE_P (m2))
2826 m2 = GET_MODE_INNER (m2);
2829 msize = GET_MODE_SIZE (m2);
2831 /* SDmode is special in that we want to access it only via REG+REG
2832 addressing on power7 and above, since we want to use the LFIWZX and
2833 STFIWZX instructions to load it. */
2834 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2837 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2840 reg = reload_reg_map[rc].reg;
2842 /* Can mode values go in the GPR/FPR/Altivec registers? */
2843 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2845 bool small_int_vsx_p = (small_int_p
2846 && (rc == RELOAD_REG_FPR
2847 || rc == RELOAD_REG_VMX));
2849 nregs = rs6000_hard_regno_nregs[m][reg];
2850 addr_mask |= RELOAD_REG_VALID;
2852 /* Indicate if the mode takes more than 1 physical register. If
2853 it takes a single register, indicate it can do REG+REG
2854 addressing. Small integers in VSX registers can only do
2855 REG+REG addressing. */
2856 if (small_int_vsx_p)
2857 addr_mask |= RELOAD_REG_INDEXED;
2858 else if (nregs > 1 || m == BLKmode || complex_p)
2859 addr_mask |= RELOAD_REG_MULTIPLE;
2861 addr_mask |= RELOAD_REG_INDEXED;
2863 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2864 addressing. If we allow scalars into Altivec registers,
2865 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2867 For VSX systems, we don't allow update addressing for
2868 DFmode/SFmode if those registers can go in both the
2869 traditional floating point registers and Altivec registers.
2870 The load/store instructions for the Altivec registers do not
2871 have update forms. If we allowed update addressing, it seems
2872 to break IV-OPT code using floating point if the index type is
2873 int instead of long (PR target/81550 and target/84042). */
2876 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2878 && !VECTOR_MODE_P (m2)
2879 && !FLOAT128_VECTOR_P (m2)
2881 && (m != E_DFmode || !TARGET_VSX)
2882 && (m != E_SFmode || !TARGET_P8_VECTOR)
2883 && !small_int_vsx_p)
2885 addr_mask |= RELOAD_REG_PRE_INCDEC;
2887 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2888 we don't allow PRE_MODIFY for some multi-register
2893 addr_mask |= RELOAD_REG_PRE_MODIFY;
2897 if (TARGET_POWERPC64)
2898 addr_mask |= RELOAD_REG_PRE_MODIFY;
2903 if (TARGET_HARD_FLOAT)
2904 addr_mask |= RELOAD_REG_PRE_MODIFY;
2910 /* GPR and FPR registers can do REG+OFFSET addressing, except
2911 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2912 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2913 if ((addr_mask != 0) && !indexed_only_p
2915 && (rc == RELOAD_REG_GPR
2916 || ((msize == 8 || m2 == SFmode)
2917 && (rc == RELOAD_REG_FPR
2918 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2919 addr_mask |= RELOAD_REG_OFFSET;
2921 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2922 instructions are enabled. The offset for 128-bit VSX registers is
2923 only 12-bits. While GPRs can handle the full offset range, VSX
2924 registers can only handle the restricted range. */
2925 else if ((addr_mask != 0) && !indexed_only_p
2926 && msize == 16 && TARGET_P9_VECTOR
2927 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2928 || (m2 == TImode && TARGET_VSX)))
2930 addr_mask |= RELOAD_REG_OFFSET;
2931 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2932 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2935 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2936 addressing on 128-bit types. */
2937 if (rc == RELOAD_REG_VMX && msize == 16
2938 && (addr_mask & RELOAD_REG_VALID) != 0)
2939 addr_mask |= RELOAD_REG_AND_M16;
2941 reg_addr[m].addr_mask[rc] = addr_mask;
2942 any_addr_mask |= addr_mask;
2945 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2950 /* Initialize the various global tables that are based on register size. */
2952 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2958 /* Precalculate REGNO_REG_CLASS. */
2959 rs6000_regno_regclass[0] = GENERAL_REGS;
2960 for (r = 1; r < 32; ++r)
2961 rs6000_regno_regclass[r] = BASE_REGS;
2963 for (r = 32; r < 64; ++r)
2964 rs6000_regno_regclass[r] = FLOAT_REGS;
2966 for (r = 64; HARD_REGISTER_NUM_P (r); ++r)
2967 rs6000_regno_regclass[r] = NO_REGS;
2969 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2970 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2972 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2973 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2974 rs6000_regno_regclass[r] = CR_REGS;
2976 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2977 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2978 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2979 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2980 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2981 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2982 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2984 /* Precalculate register class to simpler reload register class. We don't
2985 need all of the register classes that are combinations of different
2986 classes, just the simple ones that have constraint letters. */
2987 for (c = 0; c < N_REG_CLASSES; c++)
2988 reg_class_to_reg_type[c] = NO_REG_TYPE;
2990 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2991 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
2992 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
2993 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
2994 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
2995 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
2996 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
2997 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
2998 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
2999 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3003 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3004 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3008 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3009 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3012 /* Precalculate the valid memory formats as well as the vector information,
3013 this must be set up before the rs6000_hard_regno_nregs_internal calls
3015 gcc_assert ((int)VECTOR_NONE == 0);
3016 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3017 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem));
3019 gcc_assert ((int)CODE_FOR_nothing == 0);
3020 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3022 gcc_assert ((int)NO_REGS == 0);
3023 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3025 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3026 believes it can use native alignment or still uses 128-bit alignment. */
3027 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3038 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3039 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3040 if (TARGET_FLOAT128_TYPE)
3042 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3043 rs6000_vector_align[KFmode] = 128;
3045 if (FLOAT128_IEEE_P (TFmode))
3047 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3048 rs6000_vector_align[TFmode] = 128;
3052 /* V2DF mode, VSX only. */
3055 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3056 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3057 rs6000_vector_align[V2DFmode] = align64;
3060 /* V4SF mode, either VSX or Altivec. */
3063 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3064 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3065 rs6000_vector_align[V4SFmode] = align32;
3067 else if (TARGET_ALTIVEC)
3069 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3070 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3071 rs6000_vector_align[V4SFmode] = align32;
3074 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3078 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3079 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3080 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3081 rs6000_vector_align[V4SImode] = align32;
3082 rs6000_vector_align[V8HImode] = align32;
3083 rs6000_vector_align[V16QImode] = align32;
3087 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3088 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3089 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3093 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3094 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3095 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3099 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3100 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3103 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3104 rs6000_vector_unit[V2DImode]
3105 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3106 rs6000_vector_align[V2DImode] = align64;
3108 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3109 rs6000_vector_unit[V1TImode]
3110 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3111 rs6000_vector_align[V1TImode] = 128;
3114 /* DFmode, see if we want to use the VSX unit. Memory is handled
3115 differently, so don't set rs6000_vector_mem. */
3118 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3119 rs6000_vector_align[DFmode] = 64;
3122 /* SFmode, see if we want to use the VSX unit. */
3123 if (TARGET_P8_VECTOR)
3125 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3126 rs6000_vector_align[SFmode] = 32;
3129 /* Allow TImode in VSX register and set the VSX memory macros. */
3132 rs6000_vector_mem[TImode] = VECTOR_VSX;
3133 rs6000_vector_align[TImode] = align64;
3136 /* Register class constraints for the constraints that depend on compile
3137 switches. When the VSX code was added, different constraints were added
3138 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3139 of the VSX registers are used. The register classes for scalar floating
3140 point types is set, based on whether we allow that type into the upper
3141 (Altivec) registers. GCC has register classes to target the Altivec
3142 registers for load/store operations, to select using a VSX memory
3143 operation instead of the traditional floating point operation. The
3146 d - Register class to use with traditional DFmode instructions.
3147 f - Register class to use with traditional SFmode instructions.
3148 v - Altivec register.
3149 wa - Any VSX register.
3150 wc - Reserved to represent individual CR bits (used in LLVM).
3151 wd - Preferred register class for V2DFmode.
3152 wf - Preferred register class for V4SFmode.
3153 wg - Float register for power6x move insns.
3154 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3155 wn - always NO_REGS.
3156 wr - GPR if 64-bit mode is permitted.
3157 ws - Register class to do ISA 2.06 DF operations.
3158 wt - VSX register for TImode in VSX registers.
3159 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3160 ww - Register class to do SF conversions in with VSX operations.
3161 wx - Float register if we can do 32-bit int stores. */
3163 if (TARGET_HARD_FLOAT)
3165 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3166 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3171 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3172 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3173 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3174 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3175 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3176 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3177 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3180 /* Add conditional constraints based on various options, to allow us to
3181 collapse multiple insn patterns. */
3183 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3185 if (TARGET_MFPGPR) /* DFmode */
3186 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3188 if (TARGET_POWERPC64)
3190 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3191 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3194 if (TARGET_P8_VECTOR) /* SFmode */
3195 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3196 else if (TARGET_VSX)
3197 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3200 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3202 if (TARGET_FLOAT128_TYPE)
3204 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3205 if (FLOAT128_IEEE_P (TFmode))
3206 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3209 /* Support for new direct moves (ISA 3.0 + 64bit). */
3210 if (TARGET_DIRECT_MOVE_128)
3211 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3213 /* Set up the reload helper and direct move functions. */
3214 if (TARGET_VSX || TARGET_ALTIVEC)
3218 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3219 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3220 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3221 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3222 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3223 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3224 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3225 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3226 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3227 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3228 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3229 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3230 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3231 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3232 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3233 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3234 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3235 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3236 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3237 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3239 if (FLOAT128_VECTOR_P (KFmode))
3241 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3242 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3245 if (FLOAT128_VECTOR_P (TFmode))
3247 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3248 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3251 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3253 if (TARGET_NO_SDMODE_STACK)
3255 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3256 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3261 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3262 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3265 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3267 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3268 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3269 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3270 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3271 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3272 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3273 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3274 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3275 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3277 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3278 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3279 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3280 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3281 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3282 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3283 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3284 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3285 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3287 if (FLOAT128_VECTOR_P (KFmode))
3289 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3290 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3293 if (FLOAT128_VECTOR_P (TFmode))
3295 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3296 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3302 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3303 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3304 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3305 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3306 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3307 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3308 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3309 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3310 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3311 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3312 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3313 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3314 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3315 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3316 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3317 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3318 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3319 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3320 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3321 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3323 if (FLOAT128_VECTOR_P (KFmode))
3325 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3326 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3329 if (FLOAT128_IEEE_P (TFmode))
3331 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3332 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3335 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3337 if (TARGET_NO_SDMODE_STACK)
3339 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3340 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3345 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3346 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3349 if (TARGET_DIRECT_MOVE)
3351 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3352 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3353 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3357 reg_addr[DFmode].scalar_in_vmx_p = true;
3358 reg_addr[DImode].scalar_in_vmx_p = true;
3360 if (TARGET_P8_VECTOR)
3362 reg_addr[SFmode].scalar_in_vmx_p = true;
3363 reg_addr[SImode].scalar_in_vmx_p = true;
3365 if (TARGET_P9_VECTOR)
3367 reg_addr[HImode].scalar_in_vmx_p = true;
3368 reg_addr[QImode].scalar_in_vmx_p = true;
3373 /* Precalculate HARD_REGNO_NREGS. */
3374 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3375 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3376 rs6000_hard_regno_nregs[m][r]
3377 = rs6000_hard_regno_nregs_internal (r, (machine_mode) m);
3379 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3380 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3381 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3382 rs6000_hard_regno_mode_ok_p[m][r]
3383 = rs6000_hard_regno_mode_ok_uncached (r, (machine_mode) m);
3385 /* Precalculate CLASS_MAX_NREGS sizes. */
3386 for (c = 0; c < LIM_REG_CLASSES; ++c)
3390 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3391 reg_size = UNITS_PER_VSX_WORD;
3393 else if (c == ALTIVEC_REGS)
3394 reg_size = UNITS_PER_ALTIVEC_WORD;
3396 else if (c == FLOAT_REGS)
3397 reg_size = UNITS_PER_FP_WORD;
3400 reg_size = UNITS_PER_WORD;
3402 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3404 machine_mode m2 = (machine_mode)m;
3405 int reg_size2 = reg_size;
3407 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3409 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3410 reg_size2 = UNITS_PER_FP_WORD;
3412 rs6000_class_max_nregs[m][c]
3413 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3417 /* Calculate which modes to automatically generate code to use a the
3418 reciprocal divide and square root instructions. In the future, possibly
3419 automatically generate the instructions even if the user did not specify
3420 -mrecip. The older machines double precision reciprocal sqrt estimate is
3421 not accurate enough. */
3422 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3424 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3426 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3427 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3428 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3429 if (VECTOR_UNIT_VSX_P (V2DFmode))
3430 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3432 if (TARGET_FRSQRTES)
3433 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3435 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3436 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3437 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3438 if (VECTOR_UNIT_VSX_P (V2DFmode))
3439 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3441 if (rs6000_recip_control)
3443 if (!flag_finite_math_only)
3444 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3446 if (flag_trapping_math)
3447 warning (0, "%qs requires %qs or %qs", "-mrecip",
3448 "-fno-trapping-math", "-ffast-math");
3449 if (!flag_reciprocal_math)
3450 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3452 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3454 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3455 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3456 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3458 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3459 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3460 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3462 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3463 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3464 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3466 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3467 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3468 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3470 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3471 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3472 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3474 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3475 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3476 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3478 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3479 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3480 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3482 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3483 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3484 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3488 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3489 legitimate address support to figure out the appropriate addressing to
3491 rs6000_setup_reg_addr_masks ();
3493 if (global_init_p || TARGET_DEBUG_TARGET)
3495 if (TARGET_DEBUG_REG)
3496 rs6000_debug_reg_global ();
3498 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3500 "SImode variable mult cost = %d\n"
3501 "SImode constant mult cost = %d\n"
3502 "SImode short constant mult cost = %d\n"
3503 "DImode multipliciation cost = %d\n"
3504 "SImode division cost = %d\n"
3505 "DImode division cost = %d\n"
3506 "Simple fp operation cost = %d\n"
3507 "DFmode multiplication cost = %d\n"
3508 "SFmode division cost = %d\n"
3509 "DFmode division cost = %d\n"
3510 "cache line size = %d\n"
3511 "l1 cache size = %d\n"
3512 "l2 cache size = %d\n"
3513 "simultaneous prefetches = %d\n"
3516 rs6000_cost->mulsi_const,
3517 rs6000_cost->mulsi_const9,
3525 rs6000_cost->cache_line_size,
3526 rs6000_cost->l1_cache_size,
3527 rs6000_cost->l2_cache_size,
3528 rs6000_cost->simultaneous_prefetches);
3533 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3536 darwin_rs6000_override_options (void)
3538 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3540 rs6000_altivec_abi = 1;
3541 TARGET_ALTIVEC_VRSAVE = 1;
3542 rs6000_current_abi = ABI_DARWIN;
3544 if (DEFAULT_ABI == ABI_DARWIN
3546 darwin_one_byte_bool = 1;
3548 if (TARGET_64BIT && ! TARGET_POWERPC64)
3550 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3551 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3555 rs6000_default_long_calls = 1;
3556 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3559 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3561 if (!flag_mkernel && !flag_apple_kext
3563 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3564 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3566 /* Unless the user (not the configurer) has explicitly overridden
3567 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3568 G4 unless targeting the kernel. */
3571 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3572 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3573 && ! global_options_set.x_rs6000_cpu_index)
3575 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3580 /* If not otherwise specified by a target, make 'long double' equivalent to
3583 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3584 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3587 /* Return the builtin mask of the various options used that could affect which
3588 builtins were used. In the past we used target_flags, but we've run out of
3589 bits, and some options are no longer in target_flags. */
3592 rs6000_builtin_mask_calculate (void)
3594 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3595 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3596 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3597 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3598 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3599 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3600 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3601 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3602 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3603 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3604 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3605 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3606 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3607 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3608 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3609 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3610 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3611 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3612 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3613 | ((TARGET_LONG_DOUBLE_128
3614 && TARGET_HARD_FLOAT
3615 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3616 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3617 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3620 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3621 to clobber the XER[CA] bit because clobbering that bit without telling
3622 the compiler worked just fine with versions of GCC before GCC 5, and
3623 breaking a lot of older code in ways that are hard to track down is
3624 not such a great idea. */
3627 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3628 vec<const char *> &/*constraints*/,
3629 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3631 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3632 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3636 /* Override command line options.
3638 Combine build-specific configuration information with options
3639 specified on the command line to set various state variables which
3640 influence code generation, optimization, and expansion of built-in
3641 functions. Assure that command-line configuration preferences are
3642 compatible with each other and with the build configuration; issue
3643 warnings while adjusting configuration or error messages while
3644 rejecting configuration.
3646 Upon entry to this function:
3648 This function is called once at the beginning of
3649 compilation, and then again at the start and end of compiling
3650 each section of code that has a different configuration, as
3651 indicated, for example, by adding the
3653 __attribute__((__target__("cpu=power9")))
3655 qualifier to a function definition or, for example, by bracketing
3658 #pragma GCC target("altivec")
3662 #pragma GCC reset_options
3664 directives. Parameter global_init_p is true for the initial
3665 invocation, which initializes global variables, and false for all
3666 subsequent invocations.
3669 Various global state information is assumed to be valid. This
3670 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3671 default CPU specified at build configure time, TARGET_DEFAULT,
3672 representing the default set of option flags for the default
3673 target, and global_options_set.x_rs6000_isa_flags, representing
3674 which options were requested on the command line.
3676 Upon return from this function:
3678 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3679 was set by name on the command line. Additionally, if certain
3680 attributes are automatically enabled or disabled by this function
3681 in order to assure compatibility between options and
3682 configuration, the flags associated with those attributes are
3683 also set. By setting these "explicit bits", we avoid the risk
3684 that other code might accidentally overwrite these particular
3685 attributes with "default values".
3687 The various bits of rs6000_isa_flags are set to indicate the
3688 target options that have been selected for the most current
3689 compilation efforts. This has the effect of also turning on the
3690 associated TARGET_XXX values since these are macros which are
3691 generally defined to test the corresponding bit of the
3692 rs6000_isa_flags variable.
3694 The variable rs6000_builtin_mask is set to represent the target
3695 options for the most current compilation efforts, consistent with
3696 the current contents of rs6000_isa_flags. This variable controls
3697 expansion of built-in functions.
3699 Various other global variables and fields of global structures
3700 (over 50 in all) are initialized to reflect the desired options
3701 for the most current compilation efforts. */
3704 rs6000_option_override_internal (bool global_init_p)
3708 HOST_WIDE_INT set_masks;
3709 HOST_WIDE_INT ignore_masks;
3712 struct cl_target_option *main_target_opt
3713 = ((global_init_p || target_option_default_node == NULL)
3714 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3716 /* Print defaults. */
3717 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3718 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3720 /* Remember the explicit arguments. */
3722 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3724 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3725 library functions, so warn about it. The flag may be useful for
3726 performance studies from time to time though, so don't disable it
3728 if (global_options_set.x_rs6000_alignment_flags
3729 && rs6000_alignment_flags == MASK_ALIGN_POWER
3730 && DEFAULT_ABI == ABI_DARWIN
3732 warning (0, "%qs is not supported for 64-bit Darwin;"
3733 " it is incompatible with the installed C and C++ libraries",
3736 /* Numerous experiment shows that IRA based loop pressure
3737 calculation works better for RTL loop invariant motion on targets
3738 with enough (>= 32) registers. It is an expensive optimization.
3739 So it is on only for peak performance. */
3740 if (optimize >= 3 && global_init_p
3741 && !global_options_set.x_flag_ira_loop_pressure)
3742 flag_ira_loop_pressure = 1;
3744 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3745 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3746 options were already specified. */
3747 if (flag_sanitize & SANITIZE_USER_ADDRESS
3748 && !global_options_set.x_flag_asynchronous_unwind_tables)
3749 flag_asynchronous_unwind_tables = 1;
3751 /* Set the pointer size. */
3754 rs6000_pmode = DImode;
3755 rs6000_pointer_size = 64;
3759 rs6000_pmode = SImode;
3760 rs6000_pointer_size = 32;
3763 /* Some OSs don't support saving the high part of 64-bit registers on context
3764 switch. Other OSs don't support saving Altivec registers. On those OSs,
3765 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3766 if the user wants either, the user must explicitly specify them and we
3767 won't interfere with the user's specification. */
3769 set_masks = POWERPC_MASKS;
3770 #ifdef OS_MISSING_POWERPC64
3771 if (OS_MISSING_POWERPC64)
3772 set_masks &= ~OPTION_MASK_POWERPC64;
3774 #ifdef OS_MISSING_ALTIVEC
3775 if (OS_MISSING_ALTIVEC)
3776 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3777 | OTHER_VSX_VECTOR_MASKS);
3780 /* Don't override by the processor default if given explicitly. */
3781 set_masks &= ~rs6000_isa_flags_explicit;
3783 if (global_init_p && rs6000_dejagnu_cpu_index >= 0)
3784 rs6000_cpu_index = rs6000_dejagnu_cpu_index;
3786 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3787 the cpu in a target attribute or pragma, but did not specify a tuning
3788 option, use the cpu for the tuning option rather than the option specified
3789 with -mtune on the command line. Process a '--with-cpu' configuration
3790 request as an implicit --cpu. */
3791 if (rs6000_cpu_index >= 0)
3792 cpu_index = rs6000_cpu_index;
3793 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3794 cpu_index = main_target_opt->x_rs6000_cpu_index;
3795 else if (OPTION_TARGET_CPU_DEFAULT)
3796 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3798 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3799 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3800 with those from the cpu, except for options that were explicitly set. If
3801 we don't have a cpu, do not override the target bits set in
3805 rs6000_cpu_index = cpu_index;
3806 rs6000_isa_flags &= ~set_masks;
3807 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3812 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3813 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3814 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3815 to using rs6000_isa_flags, we need to do the initialization here.
3817 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3818 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3819 HOST_WIDE_INT flags;
3821 flags = TARGET_DEFAULT;
3824 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3825 const char *default_cpu = (!TARGET_POWERPC64
3830 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3831 flags = processor_target_table[default_cpu_index].target_enable;
3833 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3836 if (rs6000_tune_index >= 0)
3837 tune_index = rs6000_tune_index;
3838 else if (cpu_index >= 0)
3839 rs6000_tune_index = tune_index = cpu_index;
3843 enum processor_type tune_proc
3844 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3847 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3848 if (processor_target_table[i].processor == tune_proc)
3856 rs6000_cpu = processor_target_table[cpu_index].processor;
3858 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3860 gcc_assert (tune_index >= 0);
3861 rs6000_tune = processor_target_table[tune_index].processor;
3863 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3864 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3865 || rs6000_cpu == PROCESSOR_PPCE5500)
3868 error ("AltiVec not supported in this target");
3871 /* If we are optimizing big endian systems for space, use the load/store
3872 multiple instructions. */
3873 if (BYTES_BIG_ENDIAN && optimize_size)
3874 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3876 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3877 because the hardware doesn't support the instructions used in little
3878 endian mode, and causes an alignment trap. The 750 does not cause an
3879 alignment trap (except when the target is unaligned). */
3881 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3883 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3884 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3885 warning (0, "%qs is not supported on little endian systems",
3889 /* If little-endian, default to -mstrict-align on older processors.
3890 Testing for htm matches power8 and later. */
3891 if (!BYTES_BIG_ENDIAN
3892 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3893 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3895 if (!rs6000_fold_gimple)
3897 "gimple folding of rs6000 builtins has been disabled.\n");
3899 /* Add some warnings for VSX. */
3902 const char *msg = NULL;
3903 if (!TARGET_HARD_FLOAT)
3905 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3906 msg = N_("%<-mvsx%> requires hardware floating point");
3909 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3910 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3913 else if (TARGET_AVOID_XFORM > 0)
3914 msg = N_("%<-mvsx%> needs indexed addressing");
3915 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3916 & OPTION_MASK_ALTIVEC))
3918 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3919 msg = N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
3921 msg = N_("%<-mno-altivec%> disables vsx");
3927 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3928 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3932 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3933 the -mcpu setting to enable options that conflict. */
3934 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3935 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3936 | OPTION_MASK_ALTIVEC
3937 | OPTION_MASK_VSX)) != 0)
3938 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3939 | OPTION_MASK_DIRECT_MOVE)
3940 & ~rs6000_isa_flags_explicit);
3942 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3943 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3945 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
3946 off all of the options that depend on those flags. */
3947 ignore_masks = rs6000_disable_incompatible_switches ();
3949 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3950 unless the user explicitly used the -mno-<option> to disable the code. */
3951 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
3952 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3953 else if (TARGET_P9_MINMAX)
3957 if (cpu_index == PROCESSOR_POWER9)
3959 /* legacy behavior: allow -mcpu=power9 with certain
3960 capabilities explicitly disabled. */
3961 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3964 error ("power9 target option is incompatible with %<%s=<xxx>%> "
3965 "for <xxx> less than power9", "-mcpu");
3967 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
3968 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
3969 & rs6000_isa_flags_explicit))
3970 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
3971 were explicitly cleared. */
3972 error ("%qs incompatible with explicitly disabled options",
3975 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
3977 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
3978 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
3979 else if (TARGET_VSX)
3980 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
3981 else if (TARGET_POPCNTD)
3982 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
3983 else if (TARGET_DFP)
3984 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
3985 else if (TARGET_CMPB)
3986 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
3987 else if (TARGET_FPRND)
3988 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
3989 else if (TARGET_POPCNTB)
3990 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
3991 else if (TARGET_ALTIVEC)
3992 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
3994 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
3996 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
3997 error ("%qs requires %qs", "-mcrypto", "-maltivec");
3998 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4001 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4003 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4004 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4005 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4008 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4010 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4011 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4012 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4015 if (TARGET_P8_VECTOR && !TARGET_VSX)
4017 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4018 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4019 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4020 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4022 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4023 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4024 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4028 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4030 rs6000_isa_flags |= OPTION_MASK_VSX;
4031 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4035 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4037 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4038 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4039 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4042 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4043 silently turn off quad memory mode. */
4044 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4046 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4047 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4049 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4050 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4052 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4053 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4056 /* Non-atomic quad memory load/store are disabled for little endian, since
4057 the words are reversed, but atomic operations can still be done by
4058 swapping the words. */
4059 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4061 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4062 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4065 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4068 /* Assume if the user asked for normal quad memory instructions, they want
4069 the atomic versions as well, unless they explicity told us not to use quad
4070 word atomic instructions. */
4071 if (TARGET_QUAD_MEMORY
4072 && !TARGET_QUAD_MEMORY_ATOMIC
4073 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4074 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4076 /* If we can shrink-wrap the TOC register save separately, then use
4077 -msave-toc-indirect unless explicitly disabled. */
4078 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4079 && flag_shrink_wrap_separate
4080 && optimize_function_for_speed_p (cfun))
4081 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4083 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4084 generating power8 instructions. Power9 does not optimize power8 fusion
4086 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4088 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4089 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4091 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4094 /* Setting additional fusion flags turns on base fusion. */
4095 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4097 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4099 if (TARGET_P8_FUSION_SIGN)
4100 error ("%qs requires %qs", "-mpower8-fusion-sign",
4103 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4106 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4109 /* Power8 does not fuse sign extended loads with the addis. If we are
4110 optimizing at high levels for speed, convert a sign extended load into a
4111 zero extending load, and an explicit sign extension. */
4112 if (TARGET_P8_FUSION
4113 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4114 && optimize_function_for_speed_p (cfun)
4116 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4118 /* ISA 3.0 vector instructions include ISA 2.07. */
4119 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4121 /* We prefer to not mention undocumented options in
4122 error messages. However, if users have managed to select
4123 power9-vector without selecting power8-vector, they
4124 already know about undocumented flags. */
4125 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4126 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4127 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4128 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4130 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4131 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4132 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4136 /* OPTION_MASK_P9_VECTOR is explicit and
4137 OPTION_MASK_P8_VECTOR is not explicit. */
4138 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4139 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4143 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4144 support. If we only have ISA 2.06 support, and the user did not specify
4145 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4146 but we don't enable the full vectorization support */
4147 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4148 TARGET_ALLOW_MOVMISALIGN = 1;
4150 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4152 if (TARGET_ALLOW_MOVMISALIGN > 0
4153 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4154 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4156 TARGET_ALLOW_MOVMISALIGN = 0;
4159 /* Determine when unaligned vector accesses are permitted, and when
4160 they are preferred over masked Altivec loads. Note that if
4161 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4162 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4164 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4168 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4169 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4171 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4174 else if (!TARGET_ALLOW_MOVMISALIGN)
4176 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4177 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4178 "-mallow-movmisalign");
4180 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4184 /* Use long double size to select the appropriate long double. We use
4185 TYPE_PRECISION to differentiate the 3 different long double types. We map
4186 128 into the precision used for TFmode. */
4187 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4189 : FLOAT_PRECISION_TFmode);
4191 /* Set long double size before the IEEE 128-bit tests. */
4192 if (!global_options_set.x_rs6000_long_double_type_size)
4194 if (main_target_opt != NULL
4195 && (main_target_opt->x_rs6000_long_double_type_size
4196 != default_long_double_size))
4197 error ("target attribute or pragma changes %<long double%> size");
4199 rs6000_long_double_type_size = default_long_double_size;
4201 else if (rs6000_long_double_type_size == 128)
4202 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4203 else if (global_options_set.x_rs6000_ieeequad)
4205 if (global_options.x_rs6000_ieeequad)
4206 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4208 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4211 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4212 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4213 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4214 those systems will not pick up this default. Warn if the user changes the
4215 default unless -Wno-psabi. */
4216 if (!global_options_set.x_rs6000_ieeequad)
4217 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4221 if (global_options.x_rs6000_ieeequad
4222 && (!TARGET_POPCNTD || !TARGET_VSX))
4223 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4225 if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4227 static bool warned_change_long_double;
4228 if (!warned_change_long_double)
4230 warned_change_long_double = true;
4231 if (TARGET_IEEEQUAD)
4232 warning (OPT_Wpsabi, "Using IEEE extended precision "
4235 warning (OPT_Wpsabi, "Using IBM extended precision "
4241 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4242 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4243 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4244 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4245 the keyword as well as the type. */
4246 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4248 /* IEEE 128-bit floating point requires VSX support. */
4249 if (TARGET_FLOAT128_KEYWORD)
4253 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4254 error ("%qs requires VSX support", "%<-mfloat128%>");
4256 TARGET_FLOAT128_TYPE = 0;
4257 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4258 | OPTION_MASK_FLOAT128_HW);
4260 else if (!TARGET_FLOAT128_TYPE)
4262 TARGET_FLOAT128_TYPE = 1;
4263 warning (0, "The %<-mfloat128%> option may not be fully supported");
4267 /* Enable the __float128 keyword under Linux by default. */
4268 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4269 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4270 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4272 /* If we have are supporting the float128 type and full ISA 3.0 support,
4273 enable -mfloat128-hardware by default. However, don't enable the
4274 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4275 because sometimes the compiler wants to put things in an integer
4276 container, and if we don't have __int128 support, it is impossible. */
4277 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4278 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4279 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4280 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4282 if (TARGET_FLOAT128_HW
4283 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4285 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4286 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4288 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4291 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4293 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4294 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4296 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4299 /* -mpcrel requires the prefixed load/store support on FUTURE systems. */
4300 if (!TARGET_FUTURE && TARGET_PCREL)
4302 if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
4303 error ("%qs requires %qs", "-mpcrel", "-mcpu=future");
4305 rs6000_isa_flags &= ~OPTION_MASK_PCREL;
4308 /* Print the options after updating the defaults. */
4309 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4310 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4312 /* E500mc does "better" if we inline more aggressively. Respect the
4313 user's opinion, though. */
4314 if (rs6000_block_move_inline_limit == 0
4315 && (rs6000_tune == PROCESSOR_PPCE500MC
4316 || rs6000_tune == PROCESSOR_PPCE500MC64
4317 || rs6000_tune == PROCESSOR_PPCE5500
4318 || rs6000_tune == PROCESSOR_PPCE6500))
4319 rs6000_block_move_inline_limit = 128;
4321 /* store_one_arg depends on expand_block_move to handle at least the
4322 size of reg_parm_stack_space. */
4323 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4324 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4328 /* If the appropriate debug option is enabled, replace the target hooks
4329 with debug versions that call the real version and then prints
4330 debugging information. */
4331 if (TARGET_DEBUG_COST)
4333 targetm.rtx_costs = rs6000_debug_rtx_costs;
4334 targetm.address_cost = rs6000_debug_address_cost;
4335 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4338 if (TARGET_DEBUG_ADDR)
4340 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4341 targetm.legitimize_address = rs6000_debug_legitimize_address;
4342 rs6000_secondary_reload_class_ptr
4343 = rs6000_debug_secondary_reload_class;
4344 targetm.secondary_memory_needed
4345 = rs6000_debug_secondary_memory_needed;
4346 targetm.can_change_mode_class
4347 = rs6000_debug_can_change_mode_class;
4348 rs6000_preferred_reload_class_ptr
4349 = rs6000_debug_preferred_reload_class;
4350 rs6000_mode_dependent_address_ptr
4351 = rs6000_debug_mode_dependent_address;
4354 if (rs6000_veclibabi_name)
4356 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4357 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4360 error ("unknown vectorization library ABI type (%qs) for "
4361 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4367 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4368 target attribute or pragma which automatically enables both options,
4369 unless the altivec ABI was set. This is set by default for 64-bit, but
4371 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4373 TARGET_FLOAT128_TYPE = 0;
4374 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4375 | OPTION_MASK_FLOAT128_KEYWORD)
4376 & ~rs6000_isa_flags_explicit);
4379 /* Enable Altivec ABI for AIX -maltivec. */
4380 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4382 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4383 error ("target attribute or pragma changes AltiVec ABI");
4385 rs6000_altivec_abi = 1;
4388 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4389 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4390 be explicitly overridden in either case. */
4393 if (!global_options_set.x_rs6000_altivec_abi
4394 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4396 if (main_target_opt != NULL &&
4397 !main_target_opt->x_rs6000_altivec_abi)
4398 error ("target attribute or pragma changes AltiVec ABI");
4400 rs6000_altivec_abi = 1;
4404 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4405 So far, the only darwin64 targets are also MACH-O. */
4407 && DEFAULT_ABI == ABI_DARWIN
4410 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4411 error ("target attribute or pragma changes darwin64 ABI");
4414 rs6000_darwin64_abi = 1;
4415 /* Default to natural alignment, for better performance. */
4416 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4420 /* Place FP constants in the constant pool instead of TOC
4421 if section anchors enabled. */
4422 if (flag_section_anchors
4423 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4424 TARGET_NO_FP_IN_TOC = 1;
4426 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4427 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4429 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4430 SUBTARGET_OVERRIDE_OPTIONS;
4432 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4433 SUBSUBTARGET_OVERRIDE_OPTIONS;
4435 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4436 SUB3TARGET_OVERRIDE_OPTIONS;
4439 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4440 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4442 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4443 && rs6000_tune != PROCESSOR_POWER5
4444 && rs6000_tune != PROCESSOR_POWER6
4445 && rs6000_tune != PROCESSOR_POWER7
4446 && rs6000_tune != PROCESSOR_POWER8
4447 && rs6000_tune != PROCESSOR_POWER9
4448 && rs6000_tune != PROCESSOR_FUTURE
4449 && rs6000_tune != PROCESSOR_PPCA2
4450 && rs6000_tune != PROCESSOR_CELL
4451 && rs6000_tune != PROCESSOR_PPC476);
4452 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4453 || rs6000_tune == PROCESSOR_POWER5
4454 || rs6000_tune == PROCESSOR_POWER7
4455 || rs6000_tune == PROCESSOR_POWER8);
4456 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4457 || rs6000_tune == PROCESSOR_POWER5
4458 || rs6000_tune == PROCESSOR_POWER6
4459 || rs6000_tune == PROCESSOR_POWER7
4460 || rs6000_tune == PROCESSOR_POWER8
4461 || rs6000_tune == PROCESSOR_POWER9
4462 || rs6000_tune == PROCESSOR_FUTURE
4463 || rs6000_tune == PROCESSOR_PPCE500MC
4464 || rs6000_tune == PROCESSOR_PPCE500MC64
4465 || rs6000_tune == PROCESSOR_PPCE5500
4466 || rs6000_tune == PROCESSOR_PPCE6500);
4468 /* Allow debug switches to override the above settings. These are set to -1
4469 in rs6000.opt to indicate the user hasn't directly set the switch. */
4470 if (TARGET_ALWAYS_HINT >= 0)
4471 rs6000_always_hint = TARGET_ALWAYS_HINT;
4473 if (TARGET_SCHED_GROUPS >= 0)
4474 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4476 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4477 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4479 rs6000_sched_restricted_insns_priority
4480 = (rs6000_sched_groups ? 1 : 0);
4482 /* Handle -msched-costly-dep option. */
4483 rs6000_sched_costly_dep
4484 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4486 if (rs6000_sched_costly_dep_str)
4488 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4489 rs6000_sched_costly_dep = no_dep_costly;
4490 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4491 rs6000_sched_costly_dep = all_deps_costly;
4492 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4493 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4494 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4495 rs6000_sched_costly_dep = store_to_load_dep_costly;
4497 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4498 atoi (rs6000_sched_costly_dep_str));
4501 /* Handle -minsert-sched-nops option. */
4502 rs6000_sched_insert_nops
4503 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4505 if (rs6000_sched_insert_nops_str)
4507 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4508 rs6000_sched_insert_nops = sched_finish_none;
4509 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4510 rs6000_sched_insert_nops = sched_finish_pad_groups;
4511 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4512 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4514 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4515 atoi (rs6000_sched_insert_nops_str));
4518 /* Handle stack protector */
4519 if (!global_options_set.x_rs6000_stack_protector_guard)
4520 #ifdef TARGET_THREAD_SSP_OFFSET
4521 rs6000_stack_protector_guard = SSP_TLS;
4523 rs6000_stack_protector_guard = SSP_GLOBAL;
4526 #ifdef TARGET_THREAD_SSP_OFFSET
4527 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4528 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4531 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4534 const char *str = rs6000_stack_protector_guard_offset_str;
4537 long offset = strtol (str, &endp, 0);
4538 if (!*str || *endp || errno)
4539 error ("%qs is not a valid number in %qs", str,
4540 "-mstack-protector-guard-offset=");
4542 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4543 || (TARGET_64BIT && (offset & 3)))
4544 error ("%qs is not a valid offset in %qs", str,
4545 "-mstack-protector-guard-offset=");
4547 rs6000_stack_protector_guard_offset = offset;
4550 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4552 const char *str = rs6000_stack_protector_guard_reg_str;
4553 int reg = decode_reg_name (str);
4555 if (!IN_RANGE (reg, 1, 31))
4556 error ("%qs is not a valid base register in %qs", str,
4557 "-mstack-protector-guard-reg=");
4559 rs6000_stack_protector_guard_reg = reg;
4562 if (rs6000_stack_protector_guard == SSP_TLS
4563 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4564 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4568 #ifdef TARGET_REGNAMES
4569 /* If the user desires alternate register names, copy in the
4570 alternate names now. */
4571 if (TARGET_REGNAMES)
4572 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4575 /* Set aix_struct_return last, after the ABI is determined.
4576 If -maix-struct-return or -msvr4-struct-return was explicitly
4577 used, don't override with the ABI default. */
4578 if (!global_options_set.x_aix_struct_return)
4579 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4582 /* IBM XL compiler defaults to unsigned bitfields. */
4583 if (TARGET_XL_COMPAT)
4584 flag_signed_bitfields = 0;
4587 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4588 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4590 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4592 /* We can only guarantee the availability of DI pseudo-ops when
4593 assembling for 64-bit targets. */
4596 targetm.asm_out.aligned_op.di = NULL;
4597 targetm.asm_out.unaligned_op.di = NULL;
4601 /* Set branch target alignment, if not optimizing for size. */
4604 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4605 aligned 8byte to avoid misprediction by the branch predictor. */
4606 if (rs6000_tune == PROCESSOR_TITAN
4607 || rs6000_tune == PROCESSOR_CELL)
4609 if (flag_align_functions && !str_align_functions)
4610 str_align_functions = "8";
4611 if (flag_align_jumps && !str_align_jumps)
4612 str_align_jumps = "8";
4613 if (flag_align_loops && !str_align_loops)
4614 str_align_loops = "8";
4616 if (rs6000_align_branch_targets)
4618 if (flag_align_functions && !str_align_functions)
4619 str_align_functions = "16";
4620 if (flag_align_jumps && !str_align_jumps)
4621 str_align_jumps = "16";
4622 if (flag_align_loops && !str_align_loops)
4624 can_override_loop_align = 1;
4625 str_align_loops = "16";
4629 if (flag_align_jumps && !str_align_jumps)
4630 str_align_jumps = "16";
4631 if (flag_align_loops && !str_align_loops)
4632 str_align_loops = "16";
4635 /* Arrange to save and restore machine status around nested functions. */
4636 init_machine_status = rs6000_init_machine_status;
4638 /* We should always be splitting complex arguments, but we can't break
4639 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4640 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4641 targetm.calls.split_complex_arg = NULL;
4643 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4644 if (DEFAULT_ABI == ABI_AIX)
4645 targetm.calls.custom_function_descriptors = 0;
4648 /* Initialize rs6000_cost with the appropriate target costs. */
4650 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4652 switch (rs6000_tune)
4654 case PROCESSOR_RS64A:
4655 rs6000_cost = &rs64a_cost;
4658 case PROCESSOR_MPCCORE:
4659 rs6000_cost = &mpccore_cost;
4662 case PROCESSOR_PPC403:
4663 rs6000_cost = &ppc403_cost;
4666 case PROCESSOR_PPC405:
4667 rs6000_cost = &ppc405_cost;
4670 case PROCESSOR_PPC440:
4671 rs6000_cost = &ppc440_cost;
4674 case PROCESSOR_PPC476:
4675 rs6000_cost = &ppc476_cost;
4678 case PROCESSOR_PPC601:
4679 rs6000_cost = &ppc601_cost;
4682 case PROCESSOR_PPC603:
4683 rs6000_cost = &ppc603_cost;
4686 case PROCESSOR_PPC604:
4687 rs6000_cost = &ppc604_cost;
4690 case PROCESSOR_PPC604e:
4691 rs6000_cost = &ppc604e_cost;
4694 case PROCESSOR_PPC620:
4695 rs6000_cost = &ppc620_cost;
4698 case PROCESSOR_PPC630:
4699 rs6000_cost = &ppc630_cost;
4702 case PROCESSOR_CELL:
4703 rs6000_cost = &ppccell_cost;
4706 case PROCESSOR_PPC750:
4707 case PROCESSOR_PPC7400:
4708 rs6000_cost = &ppc750_cost;
4711 case PROCESSOR_PPC7450:
4712 rs6000_cost = &ppc7450_cost;
4715 case PROCESSOR_PPC8540:
4716 case PROCESSOR_PPC8548:
4717 rs6000_cost = &ppc8540_cost;
4720 case PROCESSOR_PPCE300C2:
4721 case PROCESSOR_PPCE300C3:
4722 rs6000_cost = &ppce300c2c3_cost;
4725 case PROCESSOR_PPCE500MC:
4726 rs6000_cost = &ppce500mc_cost;
4729 case PROCESSOR_PPCE500MC64:
4730 rs6000_cost = &ppce500mc64_cost;
4733 case PROCESSOR_PPCE5500:
4734 rs6000_cost = &ppce5500_cost;
4737 case PROCESSOR_PPCE6500:
4738 rs6000_cost = &ppce6500_cost;
4741 case PROCESSOR_TITAN:
4742 rs6000_cost = &titan_cost;
4745 case PROCESSOR_POWER4:
4746 case PROCESSOR_POWER5:
4747 rs6000_cost = &power4_cost;
4750 case PROCESSOR_POWER6:
4751 rs6000_cost = &power6_cost;
4754 case PROCESSOR_POWER7:
4755 rs6000_cost = &power7_cost;
4758 case PROCESSOR_POWER8:
4759 rs6000_cost = &power8_cost;
4762 case PROCESSOR_POWER9:
4763 case PROCESSOR_FUTURE:
4764 rs6000_cost = &power9_cost;
4767 case PROCESSOR_PPCA2:
4768 rs6000_cost = &ppca2_cost;
4777 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4778 rs6000_cost->simultaneous_prefetches,
4779 global_options.x_param_values,
4780 global_options_set.x_param_values);
4781 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4782 global_options.x_param_values,
4783 global_options_set.x_param_values);
4784 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4785 rs6000_cost->cache_line_size,
4786 global_options.x_param_values,
4787 global_options_set.x_param_values);
4788 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4789 global_options.x_param_values,
4790 global_options_set.x_param_values);
4792 /* Increase loop peeling limits based on performance analysis. */
4793 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4794 global_options.x_param_values,
4795 global_options_set.x_param_values);
4796 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4797 global_options.x_param_values,
4798 global_options_set.x_param_values);
4800 /* Use the 'model' -fsched-pressure algorithm by default. */
4801 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4802 SCHED_PRESSURE_MODEL,
4803 global_options.x_param_values,
4804 global_options_set.x_param_values);
4806 /* If using typedef char *va_list, signal that
4807 __builtin_va_start (&ap, 0) can be optimized to
4808 ap = __builtin_next_arg (0). */
4809 if (DEFAULT_ABI != ABI_V4)
4810 targetm.expand_builtin_va_start = NULL;
4813 /* If not explicitly specified via option, decide whether to generate indexed
4814 load/store instructions. A value of -1 indicates that the
4815 initial value of this variable has not been overwritten. During
4816 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4817 if (TARGET_AVOID_XFORM == -1)
4818 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4819 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4820 need indexed accesses and the type used is the scalar type of the element
4821 being loaded or stored. */
4822 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4823 && !TARGET_ALTIVEC);
4825 /* Set the -mrecip options. */
4826 if (rs6000_recip_name)
4828 char *p = ASTRDUP (rs6000_recip_name);
4830 unsigned int mask, i;
4833 while ((q = strtok (p, ",")) != NULL)
4844 if (!strcmp (q, "default"))
4845 mask = ((TARGET_RECIP_PRECISION)
4846 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4849 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4850 if (!strcmp (q, recip_options[i].string))
4852 mask = recip_options[i].mask;
4856 if (i == ARRAY_SIZE (recip_options))
4858 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4866 rs6000_recip_control &= ~mask;
4868 rs6000_recip_control |= mask;
4872 /* Set the builtin mask of the various options used that could affect which
4873 builtins were used. In the past we used target_flags, but we've run out
4874 of bits, and some options are no longer in target_flags. */
4875 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4876 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4877 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4878 rs6000_builtin_mask);
4880 /* Initialize all of the registers. */
4881 rs6000_init_hard_regno_mode_ok (global_init_p);
4883 /* Save the initial options in case the user does function specific options */
4885 target_option_default_node = target_option_current_node
4886 = build_target_option_node (&global_options);
4888 /* If not explicitly specified via option, decide whether to generate the
4889 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4890 if (TARGET_LINK_STACK == -1)
4891 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4893 /* Deprecate use of -mno-speculate-indirect-jumps. */
4894 if (!rs6000_speculate_indirect_jumps)
4895 warning (0, "%qs is deprecated and not recommended in any circumstances",
4896 "-mno-speculate-indirect-jumps");
4901 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4902 define the target cpu type. */
4905 rs6000_option_override (void)
4907 (void) rs6000_option_override_internal (true);
4911 /* Implement targetm.vectorize.builtin_mask_for_load. */
4913 rs6000_builtin_mask_for_load (void)
4915 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4916 if ((TARGET_ALTIVEC && !TARGET_VSX)
4917 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4918 return altivec_builtin_mask_for_load;
4923 /* Implement LOOP_ALIGN. */
4925 rs6000_loop_align (rtx label)
4930 /* Don't override loop alignment if -falign-loops was specified. */
4931 if (!can_override_loop_align)
4934 bb = BLOCK_FOR_INSN (label);
4935 ninsns = num_loop_insns(bb->loop_father);
4937 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4938 if (ninsns > 4 && ninsns <= 8
4939 && (rs6000_tune == PROCESSOR_POWER4
4940 || rs6000_tune == PROCESSOR_POWER5
4941 || rs6000_tune == PROCESSOR_POWER6
4942 || rs6000_tune == PROCESSOR_POWER7
4943 || rs6000_tune == PROCESSOR_POWER8))
4944 return align_flags (5);
4949 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4950 after applying N number of iterations. This routine does not determine
4951 how may iterations are required to reach desired alignment. */
4954 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4961 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4964 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4974 /* Assuming that all other types are naturally aligned. CHECKME! */
4979 /* Return true if the vector misalignment factor is supported by the
4982 rs6000_builtin_support_vector_misalignment (machine_mode mode,
4989 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4992 /* Return if movmisalign pattern is not supported for this mode. */
4993 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
4996 if (misalignment == -1)
4998 /* Misalignment factor is unknown at compile time but we know
4999 it's word aligned. */
5000 if (rs6000_vector_alignment_reachable (type, is_packed))
5002 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5004 if (element_size == 64 || element_size == 32)
5011 /* VSX supports word-aligned vector. */
5012 if (misalignment % 4 == 0)
5018 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5020 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5021 tree vectype, int misalign)
5026 switch (type_of_cost)
5036 case cond_branch_not_taken:
5045 case vec_promote_demote:
5051 case cond_branch_taken:
5054 case unaligned_load:
5055 case vector_gather_load:
5056 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5059 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5061 elements = TYPE_VECTOR_SUBPARTS (vectype);
5063 /* Double word aligned. */
5071 /* Double word aligned. */
5075 /* Unknown misalignment. */
5088 /* Misaligned loads are not supported. */
5093 case unaligned_store:
5094 case vector_scatter_store:
5095 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5098 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5100 elements = TYPE_VECTOR_SUBPARTS (vectype);
5102 /* Double word aligned. */
5110 /* Double word aligned. */
5114 /* Unknown misalignment. */
5127 /* Misaligned stores are not supported. */
5133 /* This is a rough approximation assuming non-constant elements
5134 constructed into a vector via element insertion. FIXME:
5135 vec_construct is not granular enough for uniformly good
5136 decisions. If the initialization is a splat, this is
5137 cheaper than we estimate. Improve this someday. */
5138 elem_type = TREE_TYPE (vectype);
5139 /* 32-bit vectors loaded into registers are stored as double
5140 precision, so we need 2 permutes, 2 converts, and 1 merge
5141 to construct a vector of short floats from them. */
5142 if (SCALAR_FLOAT_TYPE_P (elem_type)
5143 && TYPE_PRECISION (elem_type) == 32)
5145 /* On POWER9, integer vector types are built up in GPRs and then
5146 use a direct move (2 cycles). For POWER8 this is even worse,
5147 as we need two direct moves and a merge, and the direct moves
5149 else if (INTEGRAL_TYPE_P (elem_type))
5151 if (TARGET_P9_VECTOR)
5152 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5154 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5157 /* V2DFmode doesn't need a direct move. */
5165 /* Implement targetm.vectorize.preferred_simd_mode. */
5168 rs6000_preferred_simd_mode (scalar_mode mode)
5177 if (TARGET_ALTIVEC || TARGET_VSX)
5197 typedef struct _rs6000_cost_data
5199 struct loop *loop_info;
5203 /* Test for likely overcommitment of vector hardware resources. If a
5204 loop iteration is relatively large, and too large a percentage of
5205 instructions in the loop are vectorized, the cost model may not
5206 adequately reflect delays from unavailable vector resources.
5207 Penalize the loop body cost for this case. */
5210 rs6000_density_test (rs6000_cost_data *data)
5212 const int DENSITY_PCT_THRESHOLD = 85;
5213 const int DENSITY_SIZE_THRESHOLD = 70;
5214 const int DENSITY_PENALTY = 10;
5215 struct loop *loop = data->loop_info;
5216 basic_block *bbs = get_loop_body (loop);
5217 int nbbs = loop->num_nodes;
5218 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5219 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5222 for (i = 0; i < nbbs; i++)
5224 basic_block bb = bbs[i];
5225 gimple_stmt_iterator gsi;
5227 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5229 gimple *stmt = gsi_stmt (gsi);
5230 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5232 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5233 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5239 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5241 if (density_pct > DENSITY_PCT_THRESHOLD
5242 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5244 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5245 if (dump_enabled_p ())
5246 dump_printf_loc (MSG_NOTE, vect_location,
5247 "density %d%%, cost %d exceeds threshold, penalizing "
5248 "loop body cost by %d%%", density_pct,
5249 vec_cost + not_vec_cost, DENSITY_PENALTY);
5253 /* Implement targetm.vectorize.init_cost. */
5255 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5256 instruction is needed by the vectorization. */
5257 static bool rs6000_vect_nonmem;
5260 rs6000_init_cost (struct loop *loop_info)
5262 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5263 data->loop_info = loop_info;
5264 data->cost[vect_prologue] = 0;
5265 data->cost[vect_body] = 0;
5266 data->cost[vect_epilogue] = 0;
5267 rs6000_vect_nonmem = false;
5271 /* Implement targetm.vectorize.add_stmt_cost. */
5274 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5275 struct _stmt_vec_info *stmt_info, int misalign,
5276 enum vect_cost_model_location where)
5278 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5279 unsigned retval = 0;
5281 if (flag_vect_cost_model)
5283 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5284 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5286 /* Statements in an inner loop relative to the loop being
5287 vectorized are weighted more heavily. The value here is
5288 arbitrary and could potentially be improved with analysis. */
5289 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5290 count *= 50; /* FIXME. */
5292 retval = (unsigned) (count * stmt_cost);
5293 cost_data->cost[where] += retval;
5295 /* Check whether we're doing something other than just a copy loop.
5296 Not all such loops may be profitably vectorized; see
5297 rs6000_finish_cost. */
5298 if ((kind == vec_to_scalar || kind == vec_perm
5299 || kind == vec_promote_demote || kind == vec_construct
5300 || kind == scalar_to_vec)
5301 || (where == vect_body && kind == vector_stmt))
5302 rs6000_vect_nonmem = true;
5308 /* Implement targetm.vectorize.finish_cost. */
5311 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5312 unsigned *body_cost, unsigned *epilogue_cost)
5314 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5316 if (cost_data->loop_info)
5317 rs6000_density_test (cost_data);
5319 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5320 that require versioning for any reason. The vectorization is at
5321 best a wash inside the loop, and the versioning checks make
5322 profitability highly unlikely and potentially quite harmful. */
5323 if (cost_data->loop_info)
5325 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5326 if (!rs6000_vect_nonmem
5327 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5328 && LOOP_REQUIRES_VERSIONING (vec_info))
5329 cost_data->cost[vect_body] += 10000;
5332 *prologue_cost = cost_data->cost[vect_prologue];
5333 *body_cost = cost_data->cost[vect_body];
5334 *epilogue_cost = cost_data->cost[vect_epilogue];
5337 /* Implement targetm.vectorize.destroy_cost_data. */
5340 rs6000_destroy_cost_data (void *data)
5345 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5346 library with vectorized intrinsics. */
5349 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5353 const char *suffix = NULL;
5354 tree fntype, new_fndecl, bdecl = NULL_TREE;
5357 machine_mode el_mode, in_mode;
5360 /* Libmass is suitable for unsafe math only as it does not correctly support
5361 parts of IEEE with the required precision such as denormals. Only support
5362 it if we have VSX to use the simd d2 or f4 functions.
5363 XXX: Add variable length support. */
5364 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5367 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5368 n = TYPE_VECTOR_SUBPARTS (type_out);
5369 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5370 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5371 if (el_mode != in_mode
5407 if (el_mode == DFmode && n == 2)
5409 bdecl = mathfn_built_in (double_type_node, fn);
5410 suffix = "d2"; /* pow -> powd2 */
5412 else if (el_mode == SFmode && n == 4)
5414 bdecl = mathfn_built_in (float_type_node, fn);
5415 suffix = "4"; /* powf -> powf4 */
5427 gcc_assert (suffix != NULL);
5428 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5432 strcpy (name, bname + sizeof ("__builtin_") - 1);
5433 strcat (name, suffix);
5436 fntype = build_function_type_list (type_out, type_in, NULL);
5437 else if (n_args == 2)
5438 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5442 /* Build a function declaration for the vectorized function. */
5443 new_fndecl = build_decl (BUILTINS_LOCATION,
5444 FUNCTION_DECL, get_identifier (name), fntype);
5445 TREE_PUBLIC (new_fndecl) = 1;
5446 DECL_EXTERNAL (new_fndecl) = 1;
5447 DECL_IS_NOVOPS (new_fndecl) = 1;
5448 TREE_READONLY (new_fndecl) = 1;
5453 /* Returns a function decl for a vectorized version of the builtin function
5454 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5455 if it is not available. */
5458 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5461 machine_mode in_mode, out_mode;
5464 if (TARGET_DEBUG_BUILTIN)
5465 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5466 combined_fn_name (combined_fn (fn)),
5467 GET_MODE_NAME (TYPE_MODE (type_out)),
5468 GET_MODE_NAME (TYPE_MODE (type_in)));
5470 if (TREE_CODE (type_out) != VECTOR_TYPE
5471 || TREE_CODE (type_in) != VECTOR_TYPE)
5474 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5475 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5476 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5477 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5482 if (VECTOR_UNIT_VSX_P (V2DFmode)
5483 && out_mode == DFmode && out_n == 2
5484 && in_mode == DFmode && in_n == 2)
5485 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5486 if (VECTOR_UNIT_VSX_P (V4SFmode)
5487 && out_mode == SFmode && out_n == 4
5488 && in_mode == SFmode && in_n == 4)
5489 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5490 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5491 && out_mode == SFmode && out_n == 4
5492 && in_mode == SFmode && in_n == 4)
5493 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5496 if (VECTOR_UNIT_VSX_P (V2DFmode)
5497 && out_mode == DFmode && out_n == 2
5498 && in_mode == DFmode && in_n == 2)
5499 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5500 if (VECTOR_UNIT_VSX_P (V4SFmode)
5501 && out_mode == SFmode && out_n == 4
5502 && in_mode == SFmode && in_n == 4)
5503 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5504 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5505 && out_mode == SFmode && out_n == 4
5506 && in_mode == SFmode && in_n == 4)
5507 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5510 if (VECTOR_UNIT_VSX_P (V2DFmode)
5511 && out_mode == DFmode && out_n == 2
5512 && in_mode == DFmode && in_n == 2)
5513 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5514 if (VECTOR_UNIT_VSX_P (V4SFmode)
5515 && out_mode == SFmode && out_n == 4
5516 && in_mode == SFmode && in_n == 4)
5517 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5518 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5519 && out_mode == SFmode && out_n == 4
5520 && in_mode == SFmode && in_n == 4)
5521 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5524 if (VECTOR_UNIT_VSX_P (V2DFmode)
5525 && out_mode == DFmode && out_n == 2
5526 && in_mode == DFmode && in_n == 2)
5527 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5528 if (VECTOR_UNIT_VSX_P (V4SFmode)
5529 && out_mode == SFmode && out_n == 4
5530 && in_mode == SFmode && in_n == 4)
5531 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5532 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5533 && out_mode == SFmode && out_n == 4
5534 && in_mode == SFmode && in_n == 4)
5535 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5538 if (VECTOR_UNIT_VSX_P (V2DFmode)
5539 && out_mode == DFmode && out_n == 2
5540 && in_mode == DFmode && in_n == 2)
5541 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5542 if (VECTOR_UNIT_VSX_P (V4SFmode)
5543 && out_mode == SFmode && out_n == 4
5544 && in_mode == SFmode && in_n == 4)
5545 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5546 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5547 && out_mode == SFmode && out_n == 4
5548 && in_mode == SFmode && in_n == 4)
5549 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5552 if (VECTOR_UNIT_VSX_P (V2DFmode)
5553 && flag_unsafe_math_optimizations
5554 && out_mode == DFmode && out_n == 2
5555 && in_mode == DFmode && in_n == 2)
5556 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5557 if (VECTOR_UNIT_VSX_P (V4SFmode)
5558 && flag_unsafe_math_optimizations
5559 && out_mode == SFmode && out_n == 4
5560 && in_mode == SFmode && in_n == 4)
5561 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5564 if (VECTOR_UNIT_VSX_P (V2DFmode)
5565 && !flag_trapping_math
5566 && out_mode == DFmode && out_n == 2
5567 && in_mode == DFmode && in_n == 2)
5568 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5569 if (VECTOR_UNIT_VSX_P (V4SFmode)
5570 && !flag_trapping_math
5571 && out_mode == SFmode && out_n == 4
5572 && in_mode == SFmode && in_n == 4)
5573 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5579 /* Generate calls to libmass if appropriate. */
5580 if (rs6000_veclib_handler)
5581 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5586 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5589 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5592 machine_mode in_mode, out_mode;
5595 if (TARGET_DEBUG_BUILTIN)
5596 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5597 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5598 GET_MODE_NAME (TYPE_MODE (type_out)),
5599 GET_MODE_NAME (TYPE_MODE (type_in)));
5601 if (TREE_CODE (type_out) != VECTOR_TYPE
5602 || TREE_CODE (type_in) != VECTOR_TYPE)
5605 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5606 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5607 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5608 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5610 enum rs6000_builtins fn
5611 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5614 case RS6000_BUILTIN_RSQRTF:
5615 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5616 && out_mode == SFmode && out_n == 4
5617 && in_mode == SFmode && in_n == 4)
5618 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5620 case RS6000_BUILTIN_RSQRT:
5621 if (VECTOR_UNIT_VSX_P (V2DFmode)
5622 && out_mode == DFmode && out_n == 2
5623 && in_mode == DFmode && in_n == 2)
5624 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5626 case RS6000_BUILTIN_RECIPF:
5627 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5628 && out_mode == SFmode && out_n == 4
5629 && in_mode == SFmode && in_n == 4)
5630 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5632 case RS6000_BUILTIN_RECIP:
5633 if (VECTOR_UNIT_VSX_P (V2DFmode)
5634 && out_mode == DFmode && out_n == 2
5635 && in_mode == DFmode && in_n == 2)
5636 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5644 /* Default CPU string for rs6000*_file_start functions. */
5645 static const char *rs6000_default_cpu;
5647 #ifdef USING_ELFOS_H
5648 static const char *rs6000_machine;
5651 rs6000_machine_from_flags (void)
5653 if ((rs6000_isa_flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER))
5656 if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
5658 if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
5660 if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
5662 if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
5664 if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
5666 if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0)
5668 if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5674 emit_asm_machine (void)
5676 fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
5680 /* Do anything needed at the start of the asm file. */
5683 rs6000_file_start (void)
5686 const char *start = buffer;
5687 FILE *file = asm_out_file;
5689 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5691 default_file_start ();
5693 if (flag_verbose_asm)
5695 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5697 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5699 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5703 if (global_options_set.x_rs6000_cpu_index)
5705 fprintf (file, "%s -mcpu=%s", start,
5706 processor_target_table[rs6000_cpu_index].name);
5710 if (global_options_set.x_rs6000_tune_index)
5712 fprintf (file, "%s -mtune=%s", start,
5713 processor_target_table[rs6000_tune_index].name);
5717 if (PPC405_ERRATUM77)
5719 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5723 #ifdef USING_ELFOS_H
5724 switch (rs6000_sdata)
5726 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5727 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5728 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5729 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5732 if (rs6000_sdata && g_switch_value)
5734 fprintf (file, "%s -G %d", start,
5744 #ifdef USING_ELFOS_H
5745 rs6000_machine = rs6000_machine_from_flags ();
5746 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5747 && !global_options_set.x_rs6000_cpu_index)
5748 emit_asm_machine ();
5751 if (DEFAULT_ABI == ABI_ELFv2)
5752 fprintf (file, "\t.abiversion 2\n");
5756 /* Return nonzero if this function is known to have a null epilogue. */
5759 direct_return (void)
5761 if (reload_completed)
5763 rs6000_stack_t *info = rs6000_stack_info ();
5765 if (info->first_gp_reg_save == 32
5766 && info->first_fp_reg_save == 64
5767 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5768 && ! info->lr_save_p
5769 && ! info->cr_save_p
5770 && info->vrsave_size == 0
5778 /* Helper for num_insns_constant. Calculate number of instructions to
5779 load VALUE to a single gpr using combinations of addi, addis, ori,
5780 oris and sldi instructions. */
5783 num_insns_constant_gpr (HOST_WIDE_INT value)
5785 /* signed constant loadable with addi */
5786 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5789 /* constant loadable with addis */
5790 else if ((value & 0xffff) == 0
5791 && (value >> 31 == -1 || value >> 31 == 0))
5794 else if (TARGET_POWERPC64)
5796 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5797 HOST_WIDE_INT high = value >> 31;
5799 if (high == 0 || high == -1)
5805 return num_insns_constant_gpr (high) + 1;
5807 return num_insns_constant_gpr (low) + 1;
5809 return (num_insns_constant_gpr (high)
5810 + num_insns_constant_gpr (low) + 1);
5817 /* Helper for num_insns_constant. Allow constants formed by the
5818 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5819 and handle modes that require multiple gprs. */
5822 num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
5824 int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5828 HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
5829 int insns = num_insns_constant_gpr (low);
5831 /* We won't get more than 2 from num_insns_constant_gpr
5832 except when TARGET_POWERPC64 and mode is DImode or
5833 wider, so the register mode must be DImode. */
5834 && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5837 value >>= BITS_PER_WORD;
5842 /* Return the number of instructions it takes to form a constant in as
5843 many gprs are needed for MODE. */
5846 num_insns_constant (rtx op, machine_mode mode)
5850 switch (GET_CODE (op))
5856 case CONST_WIDE_INT:
5859 for (int i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5860 insns += num_insns_constant_multi (CONST_WIDE_INT_ELT (op, i),
5867 const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
5869 if (mode == SFmode || mode == SDmode)
5874 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv, l);
5876 REAL_VALUE_TO_TARGET_SINGLE (*rv, l);
5877 /* See the first define_split in rs6000.md handling a
5878 const_double_operand. */
5882 else if (mode == DFmode || mode == DDmode)
5887 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv, l);
5889 REAL_VALUE_TO_TARGET_DOUBLE (*rv, l);
5891 /* See the second (32-bit) and third (64-bit) define_split
5892 in rs6000.md handling a const_double_operand. */
5893 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 1] << 32;
5894 val |= l[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffffUL;
5897 else if (mode == TFmode || mode == TDmode
5898 || mode == KFmode || mode == IFmode)
5904 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv, l);
5906 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv, l);
5908 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 3] << 32;
5909 val |= l[WORDS_BIG_ENDIAN ? 1 : 2] & 0xffffffffUL;
5910 insns = num_insns_constant_multi (val, DImode);
5911 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 2 : 1] << 32;
5912 val |= l[WORDS_BIG_ENDIAN ? 3 : 0] & 0xffffffffUL;
5913 insns += num_insns_constant_multi (val, DImode);
5925 return num_insns_constant_multi (val, mode);
5928 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5929 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5930 corresponding element of the vector, but for V4SFmode, the
5931 corresponding "float" is interpreted as an SImode integer. */
5934 const_vector_elt_as_int (rtx op, unsigned int elt)
5938 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5939 gcc_assert (GET_MODE (op) != V2DImode
5940 && GET_MODE (op) != V2DFmode);
5942 tmp = CONST_VECTOR_ELT (op, elt);
5943 if (GET_MODE (op) == V4SFmode)
5944 tmp = gen_lowpart (SImode, tmp);
5945 return INTVAL (tmp);
5948 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5949 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5950 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5951 all items are set to the same value and contain COPIES replicas of the
5952 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5953 operand and the others are set to the value of the operand's msb. */
5956 vspltis_constant (rtx op, unsigned step, unsigned copies)
5958 machine_mode mode = GET_MODE (op);
5959 machine_mode inner = GET_MODE_INNER (mode);
5967 HOST_WIDE_INT splat_val;
5968 HOST_WIDE_INT msb_val;
5970 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5973 nunits = GET_MODE_NUNITS (mode);
5974 bitsize = GET_MODE_BITSIZE (inner);
5975 mask = GET_MODE_MASK (inner);
5977 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5979 msb_val = val >= 0 ? 0 : -1;
5981 /* Construct the value to be splatted, if possible. If not, return 0. */
5982 for (i = 2; i <= copies; i *= 2)
5984 HOST_WIDE_INT small_val;
5986 small_val = splat_val >> bitsize;
5988 if (splat_val != ((HOST_WIDE_INT)
5989 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5990 | (small_val & mask)))
5992 splat_val = small_val;
5995 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5996 if (EASY_VECTOR_15 (splat_val))
5999 /* Also check if we can splat, and then add the result to itself. Do so if
6000 the value is positive, of if the splat instruction is using OP's mode;
6001 for splat_val < 0, the splat and the add should use the same mode. */
6002 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6003 && (splat_val >= 0 || (step == 1 && copies == 1)))
6006 /* Also check if are loading up the most significant bit which can be done by
6007 loading up -1 and shifting the value left by -1. */
6008 else if (EASY_VECTOR_MSB (splat_val, inner))
6014 /* Check if VAL is present in every STEP-th element, and the
6015 other elements are filled with its most significant bit. */
6016 for (i = 1; i < nunits; ++i)
6018 HOST_WIDE_INT desired_val;
6019 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6020 if ((i & (step - 1)) == 0)
6023 desired_val = msb_val;
6025 if (desired_val != const_vector_elt_as_int (op, elt))
6032 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6033 instruction, filling in the bottom elements with 0 or -1.
6035 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6036 for the number of zeroes to shift in, or negative for the number of 0xff
6039 OP is a CONST_VECTOR. */
6042 vspltis_shifted (rtx op)
6044 machine_mode mode = GET_MODE (op);
6045 machine_mode inner = GET_MODE_INNER (mode);
6053 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6056 /* We need to create pseudo registers to do the shift, so don't recognize
6057 shift vector constants after reload. */
6058 if (!can_create_pseudo_p ())
6061 nunits = GET_MODE_NUNITS (mode);
6062 mask = GET_MODE_MASK (inner);
6064 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6066 /* Check if the value can really be the operand of a vspltis[bhw]. */
6067 if (EASY_VECTOR_15 (val))
6070 /* Also check if we are loading up the most significant bit which can be done
6071 by loading up -1 and shifting the value left by -1. */
6072 else if (EASY_VECTOR_MSB (val, inner))
6078 /* Check if VAL is present in every STEP-th element until we find elements
6079 that are 0 or all 1 bits. */
6080 for (i = 1; i < nunits; ++i)
6082 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6083 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6085 /* If the value isn't the splat value, check for the remaining elements
6091 for (j = i+1; j < nunits; ++j)
6093 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6094 if (const_vector_elt_as_int (op, elt2) != 0)
6098 return (nunits - i) * GET_MODE_SIZE (inner);
6101 else if ((elt_val & mask) == mask)
6103 for (j = i+1; j < nunits; ++j)
6105 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6106 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6110 return -((nunits - i) * GET_MODE_SIZE (inner));
6118 /* If all elements are equal, we don't need to do VLSDOI. */
6123 /* Return true if OP is of the given MODE and can be synthesized
6124 with a vspltisb, vspltish or vspltisw. */
6127 easy_altivec_constant (rtx op, machine_mode mode)
6129 unsigned step, copies;
6131 if (mode == VOIDmode)
6132 mode = GET_MODE (op);
6133 else if (mode != GET_MODE (op))
6136 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6138 if (mode == V2DFmode)
6139 return zero_constant (op, mode);
6141 else if (mode == V2DImode)
6143 if (!CONST_INT_P (CONST_VECTOR_ELT (op, 0))
6144 || !CONST_INT_P (CONST_VECTOR_ELT (op, 1)))
6147 if (zero_constant (op, mode))
6150 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6151 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6157 /* V1TImode is a special container for TImode. Ignore for now. */
6158 else if (mode == V1TImode)
6161 /* Start with a vspltisw. */
6162 step = GET_MODE_NUNITS (mode) / 4;
6165 if (vspltis_constant (op, step, copies))
6168 /* Then try with a vspltish. */
6174 if (vspltis_constant (op, step, copies))
6177 /* And finally a vspltisb. */
6183 if (vspltis_constant (op, step, copies))
6186 if (vspltis_shifted (op) != 0)
6192 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6193 result is OP. Abort if it is not possible. */
6196 gen_easy_altivec_constant (rtx op)
6198 machine_mode mode = GET_MODE (op);
6199 int nunits = GET_MODE_NUNITS (mode);
6200 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6201 unsigned step = nunits / 4;
6202 unsigned copies = 1;
6204 /* Start with a vspltisw. */
6205 if (vspltis_constant (op, step, copies))
6206 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6208 /* Then try with a vspltish. */
6214 if (vspltis_constant (op, step, copies))
6215 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6217 /* And finally a vspltisb. */
6223 if (vspltis_constant (op, step, copies))
6224 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6229 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6230 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6232 Return the number of instructions needed (1 or 2) into the address pointed
6235 Return the constant that is being split via CONSTANT_PTR. */
6238 xxspltib_constant_p (rtx op,
6243 size_t nunits = GET_MODE_NUNITS (mode);
6245 HOST_WIDE_INT value;
6248 /* Set the returned values to out of bound values. */
6249 *num_insns_ptr = -1;
6250 *constant_ptr = 256;
6252 if (!TARGET_P9_VECTOR)
6255 if (mode == VOIDmode)
6256 mode = GET_MODE (op);
6258 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6261 /* Handle (vec_duplicate <constant>). */
6262 if (GET_CODE (op) == VEC_DUPLICATE)
6264 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6265 && mode != V2DImode)
6268 element = XEXP (op, 0);
6269 if (!CONST_INT_P (element))
6272 value = INTVAL (element);
6273 if (!IN_RANGE (value, -128, 127))
6277 /* Handle (const_vector [...]). */
6278 else if (GET_CODE (op) == CONST_VECTOR)
6280 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6281 && mode != V2DImode)
6284 element = CONST_VECTOR_ELT (op, 0);
6285 if (!CONST_INT_P (element))
6288 value = INTVAL (element);
6289 if (!IN_RANGE (value, -128, 127))
6292 for (i = 1; i < nunits; i++)
6294 element = CONST_VECTOR_ELT (op, i);
6295 if (!CONST_INT_P (element))
6298 if (value != INTVAL (element))
6303 /* Handle integer constants being loaded into the upper part of the VSX
6304 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6305 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6306 else if (CONST_INT_P (op))
6308 if (!SCALAR_INT_MODE_P (mode))
6311 value = INTVAL (op);
6312 if (!IN_RANGE (value, -128, 127))
6315 if (!IN_RANGE (value, -1, 0))
6317 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6320 if (EASY_VECTOR_15 (value))
6328 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6329 sign extend. Special case 0/-1 to allow getting any VSX register instead
6330 of an Altivec register. */
6331 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6332 && EASY_VECTOR_15 (value))
6335 /* Return # of instructions and the constant byte for XXSPLTIB. */
6336 if (mode == V16QImode)
6339 else if (IN_RANGE (value, -1, 0))
6345 *constant_ptr = (int) value;
6350 output_vec_const_move (rtx *operands)
6358 mode = GET_MODE (dest);
6362 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6363 int xxspltib_value = 256;
6366 if (zero_constant (vec, mode))
6368 if (TARGET_P9_VECTOR)
6369 return "xxspltib %x0,0";
6371 else if (dest_vmx_p)
6372 return "vspltisw %0,0";
6375 return "xxlxor %x0,%x0,%x0";
6378 if (all_ones_constant (vec, mode))
6380 if (TARGET_P9_VECTOR)
6381 return "xxspltib %x0,255";
6383 else if (dest_vmx_p)
6384 return "vspltisw %0,-1";
6386 else if (TARGET_P8_VECTOR)
6387 return "xxlorc %x0,%x0,%x0";
6393 if (TARGET_P9_VECTOR
6394 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6398 operands[2] = GEN_INT (xxspltib_value & 0xff);
6399 return "xxspltib %x0,%2";
6410 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6411 if (zero_constant (vec, mode))
6412 return "vspltisw %0,0";
6414 if (all_ones_constant (vec, mode))
6415 return "vspltisw %0,-1";
6417 /* Do we need to construct a value using VSLDOI? */
6418 shift = vspltis_shifted (vec);
6422 splat_vec = gen_easy_altivec_constant (vec);
6423 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6424 operands[1] = XEXP (splat_vec, 0);
6425 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6428 switch (GET_MODE (splat_vec))
6431 return "vspltisw %0,%1";
6434 return "vspltish %0,%1";
6437 return "vspltisb %0,%1";
6447 /* Initialize vector TARGET to VALS. */
6450 rs6000_expand_vector_init (rtx target, rtx vals)
6452 machine_mode mode = GET_MODE (target);
6453 machine_mode inner_mode = GET_MODE_INNER (mode);
6454 int n_elts = GET_MODE_NUNITS (mode);
6455 int n_var = 0, one_var = -1;
6456 bool all_same = true, all_const_zero = true;
6460 for (i = 0; i < n_elts; ++i)
6462 x = XVECEXP (vals, 0, i);
6463 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6464 ++n_var, one_var = i;
6465 else if (x != CONST0_RTX (inner_mode))
6466 all_const_zero = false;
6468 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6474 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6475 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6476 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6478 /* Zero register. */
6479 emit_move_insn (target, CONST0_RTX (mode));
6482 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6484 /* Splat immediate. */
6485 emit_insn (gen_rtx_SET (target, const_vec));
6490 /* Load from constant pool. */
6491 emit_move_insn (target, const_vec);
6496 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6497 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6501 size_t num_elements = all_same ? 1 : 2;
6502 for (i = 0; i < num_elements; i++)
6504 op[i] = XVECEXP (vals, 0, i);
6505 /* Just in case there is a SUBREG with a smaller mode, do a
6507 if (GET_MODE (op[i]) != inner_mode)
6509 rtx tmp = gen_reg_rtx (inner_mode);
6510 convert_move (tmp, op[i], 0);
6513 /* Allow load with splat double word. */
6514 else if (MEM_P (op[i]))
6517 op[i] = force_reg (inner_mode, op[i]);
6519 else if (!REG_P (op[i]))
6520 op[i] = force_reg (inner_mode, op[i]);
6525 if (mode == V2DFmode)
6526 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6528 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6532 if (mode == V2DFmode)
6533 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6535 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6540 /* Special case initializing vector int if we are on 64-bit systems with
6541 direct move or we have the ISA 3.0 instructions. */
6542 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6543 && TARGET_DIRECT_MOVE_64BIT)
6547 rtx element0 = XVECEXP (vals, 0, 0);
6548 if (MEM_P (element0))
6549 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6551 element0 = force_reg (SImode, element0);
6553 if (TARGET_P9_VECTOR)
6554 emit_insn (gen_vsx_splat_v4si (target, element0));
6557 rtx tmp = gen_reg_rtx (DImode);
6558 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6559 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6568 for (i = 0; i < 4; i++)
6569 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6571 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6572 elements[2], elements[3]));
6577 /* With single precision floating point on VSX, know that internally single
6578 precision is actually represented as a double, and either make 2 V2DF
6579 vectors, and convert these vectors to single precision, or do one
6580 conversion, and splat the result to the other elements. */
6581 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6585 rtx element0 = XVECEXP (vals, 0, 0);
6587 if (TARGET_P9_VECTOR)
6589 if (MEM_P (element0))
6590 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6592 emit_insn (gen_vsx_splat_v4sf (target, element0));
6597 rtx freg = gen_reg_rtx (V4SFmode);
6598 rtx sreg = force_reg (SFmode, element0);
6599 rtx cvt = (TARGET_XSCVDPSPN
6600 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6601 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6604 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6610 rtx dbl_even = gen_reg_rtx (V2DFmode);
6611 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6612 rtx flt_even = gen_reg_rtx (V4SFmode);
6613 rtx flt_odd = gen_reg_rtx (V4SFmode);
6614 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6615 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6616 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6617 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6619 /* Use VMRGEW if we can instead of doing a permute. */
6620 if (TARGET_P8_VECTOR)
6622 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6623 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6624 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6625 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6626 if (BYTES_BIG_ENDIAN)
6627 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6629 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6633 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6634 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6635 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6636 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6637 rs6000_expand_extract_even (target, flt_even, flt_odd);
6643 /* Special case initializing vector short/char that are splats if we are on
6644 64-bit systems with direct move. */
6645 if (all_same && TARGET_DIRECT_MOVE_64BIT
6646 && (mode == V16QImode || mode == V8HImode))
6648 rtx op0 = XVECEXP (vals, 0, 0);
6649 rtx di_tmp = gen_reg_rtx (DImode);
6652 op0 = force_reg (GET_MODE_INNER (mode), op0);
6654 if (mode == V16QImode)
6656 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6657 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6661 if (mode == V8HImode)
6663 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6664 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6669 /* Store value to stack temp. Load vector element. Splat. However, splat
6670 of 64-bit items is not supported on Altivec. */
6671 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6673 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6674 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6675 XVECEXP (vals, 0, 0));
6676 x = gen_rtx_UNSPEC (VOIDmode,
6677 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6678 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6680 gen_rtx_SET (target, mem),
6682 x = gen_rtx_VEC_SELECT (inner_mode, target,
6683 gen_rtx_PARALLEL (VOIDmode,
6684 gen_rtvec (1, const0_rtx)));
6685 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6689 /* One field is non-constant. Load constant then overwrite
6693 rtx copy = copy_rtx (vals);
6695 /* Load constant part of vector, substitute neighboring value for
6697 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6698 rs6000_expand_vector_init (target, copy);
6700 /* Insert variable. */
6701 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6705 /* Construct the vector in memory one field at a time
6706 and load the whole vector. */
6707 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6708 for (i = 0; i < n_elts; i++)
6709 emit_move_insn (adjust_address_nv (mem, inner_mode,
6710 i * GET_MODE_SIZE (inner_mode)),
6711 XVECEXP (vals, 0, i));
6712 emit_move_insn (target, mem);
6715 /* Set field ELT of TARGET to VAL. */
6718 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6720 machine_mode mode = GET_MODE (target);
6721 machine_mode inner_mode = GET_MODE_INNER (mode);
6722 rtx reg = gen_reg_rtx (mode);
6724 int width = GET_MODE_SIZE (inner_mode);
6727 val = force_reg (GET_MODE (val), val);
6729 if (VECTOR_MEM_VSX_P (mode))
6731 rtx insn = NULL_RTX;
6732 rtx elt_rtx = GEN_INT (elt);
6734 if (mode == V2DFmode)
6735 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6737 else if (mode == V2DImode)
6738 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6740 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6742 if (mode == V4SImode)
6743 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6744 else if (mode == V8HImode)
6745 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6746 else if (mode == V16QImode)
6747 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6748 else if (mode == V4SFmode)
6749 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6759 /* Simplify setting single element vectors like V1TImode. */
6760 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6762 emit_move_insn (target, gen_lowpart (mode, val));
6766 /* Load single variable value. */
6767 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6768 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6769 x = gen_rtx_UNSPEC (VOIDmode,
6770 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6771 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6773 gen_rtx_SET (reg, mem),
6776 /* Linear sequence. */
6777 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6778 for (i = 0; i < 16; ++i)
6779 XVECEXP (mask, 0, i) = GEN_INT (i);
6781 /* Set permute mask to insert element into target. */
6782 for (i = 0; i < width; ++i)
6783 XVECEXP (mask, 0, elt*width + i)
6784 = GEN_INT (i + 0x10);
6785 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6787 if (BYTES_BIG_ENDIAN)
6788 x = gen_rtx_UNSPEC (mode,
6789 gen_rtvec (3, target, reg,
6790 force_reg (V16QImode, x)),
6794 if (TARGET_P9_VECTOR)
6795 x = gen_rtx_UNSPEC (mode,
6796 gen_rtvec (3, reg, target,
6797 force_reg (V16QImode, x)),
6801 /* Invert selector. We prefer to generate VNAND on P8 so
6802 that future fusion opportunities can kick in, but must
6803 generate VNOR elsewhere. */
6804 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6805 rtx iorx = (TARGET_P8_VECTOR
6806 ? gen_rtx_IOR (V16QImode, notx, notx)
6807 : gen_rtx_AND (V16QImode, notx, notx));
6808 rtx tmp = gen_reg_rtx (V16QImode);
6809 emit_insn (gen_rtx_SET (tmp, iorx));
6811 /* Permute with operands reversed and adjusted selector. */
6812 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6817 emit_insn (gen_rtx_SET (target, x));
6820 /* Extract field ELT from VEC into TARGET. */
6823 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6825 machine_mode mode = GET_MODE (vec);
6826 machine_mode inner_mode = GET_MODE_INNER (mode);
6829 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6836 emit_move_insn (target, gen_lowpart (TImode, vec));
6839 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6842 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6845 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6848 if (TARGET_DIRECT_MOVE_64BIT)
6850 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6856 if (TARGET_DIRECT_MOVE_64BIT)
6858 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6864 if (TARGET_DIRECT_MOVE_64BIT)
6866 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6872 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6873 && TARGET_DIRECT_MOVE_64BIT)
6875 if (GET_MODE (elt) != DImode)
6877 rtx tmp = gen_reg_rtx (DImode);
6878 convert_move (tmp, elt, 0);
6881 else if (!REG_P (elt))
6882 elt = force_reg (DImode, elt);
6887 emit_move_insn (target, gen_lowpart (TImode, vec));
6891 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6895 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6899 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6903 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6907 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6911 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6919 /* Allocate mode-sized buffer. */
6920 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6922 emit_move_insn (mem, vec);
6923 if (CONST_INT_P (elt))
6925 int modulo_elt = INTVAL (elt) % GET_MODE_NUNITS (mode);
6927 /* Add offset to field within buffer matching vector element. */
6928 mem = adjust_address_nv (mem, inner_mode,
6929 modulo_elt * GET_MODE_SIZE (inner_mode));
6930 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6934 unsigned int ele_size = GET_MODE_SIZE (inner_mode);
6935 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
6936 rtx new_addr = gen_reg_rtx (Pmode);
6938 elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
6940 elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
6941 new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
6942 new_addr = change_address (mem, inner_mode, new_addr);
6943 emit_move_insn (target, new_addr);
6947 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6948 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6949 temporary (BASE_TMP) to fixup the address. Return the new memory address
6950 that is valid for reads or writes to a given register (SCALAR_REG). */
6953 rs6000_adjust_vec_address (rtx scalar_reg,
6957 machine_mode scalar_mode)
6959 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6960 rtx addr = XEXP (mem, 0);
6965 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6966 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6968 /* Calculate what we need to add to the address to get the element
6970 if (CONST_INT_P (element))
6971 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6974 int byte_shift = exact_log2 (scalar_size);
6975 gcc_assert (byte_shift >= 0);
6977 if (byte_shift == 0)
6978 element_offset = element;
6982 if (TARGET_POWERPC64)
6983 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6985 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6987 element_offset = base_tmp;
6991 /* Create the new address pointing to the element within the vector. If we
6992 are adding 0, we don't have to change the address. */
6993 if (element_offset == const0_rtx)
6996 /* A simple indirect address can be converted into a reg + offset
6998 else if (REG_P (addr) || SUBREG_P (addr))
6999 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7001 /* Optimize D-FORM addresses with constant offset with a constant element, to
7002 include the element offset in the address directly. */
7003 else if (GET_CODE (addr) == PLUS)
7005 rtx op0 = XEXP (addr, 0);
7006 rtx op1 = XEXP (addr, 1);
7009 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7010 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7012 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7013 rtx offset_rtx = GEN_INT (offset);
7015 if (IN_RANGE (offset, -32768, 32767)
7016 && (scalar_size < 8 || (offset & 0x3) == 0))
7017 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7020 emit_move_insn (base_tmp, offset_rtx);
7021 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7026 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7027 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7029 /* Note, ADDI requires the register being added to be a base
7030 register. If the register was R0, load it up into the temporary
7033 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7035 insn = gen_add3_insn (base_tmp, op1, element_offset);
7036 gcc_assert (insn != NULL_RTX);
7041 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7043 insn = gen_add3_insn (base_tmp, element_offset, op1);
7044 gcc_assert (insn != NULL_RTX);
7050 emit_move_insn (base_tmp, op1);
7051 emit_insn (gen_add2_insn (base_tmp, element_offset));
7054 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7060 emit_move_insn (base_tmp, addr);
7061 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7064 /* If we have a PLUS, we need to see whether the particular register class
7065 allows for D-FORM or X-FORM addressing. */
7066 if (GET_CODE (new_addr) == PLUS)
7068 rtx op1 = XEXP (new_addr, 1);
7069 addr_mask_type addr_mask;
7070 unsigned int scalar_regno = reg_or_subregno (scalar_reg);
7072 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
7073 if (INT_REGNO_P (scalar_regno))
7074 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7076 else if (FP_REGNO_P (scalar_regno))
7077 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7079 else if (ALTIVEC_REGNO_P (scalar_regno))
7080 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7085 if (REG_P (op1) || SUBREG_P (op1))
7086 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7088 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7091 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7092 valid_addr_p = true;
7095 valid_addr_p = false;
7099 emit_move_insn (base_tmp, new_addr);
7100 new_addr = base_tmp;
7103 return change_address (mem, scalar_mode, new_addr);
7106 /* Split a variable vec_extract operation into the component instructions. */
7109 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7112 machine_mode mode = GET_MODE (src);
7113 machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src));
7114 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7115 int byte_shift = exact_log2 (scalar_size);
7117 gcc_assert (byte_shift >= 0);
7119 /* If we are given a memory address, optimize to load just the element. We
7120 don't have to adjust the vector element number on little endian
7124 int num_elements = GET_MODE_NUNITS (mode);
7125 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7127 emit_insn (gen_anddi3 (element, element, num_ele_m1));
7128 gcc_assert (REG_P (tmp_gpr));
7129 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7130 tmp_gpr, scalar_mode));
7134 else if (REG_P (src) || SUBREG_P (src))
7136 int num_elements = GET_MODE_NUNITS (mode);
7137 int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
7138 int bit_shift = 7 - exact_log2 (num_elements);
7140 unsigned int dest_regno = reg_or_subregno (dest);
7141 unsigned int src_regno = reg_or_subregno (src);
7142 unsigned int element_regno = reg_or_subregno (element);
7144 gcc_assert (REG_P (tmp_gpr));
7146 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7147 a general purpose register. */
7148 if (TARGET_P9_VECTOR
7149 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7150 && INT_REGNO_P (dest_regno)
7151 && ALTIVEC_REGNO_P (src_regno)
7152 && INT_REGNO_P (element_regno))
7154 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7155 rtx element_si = gen_rtx_REG (SImode, element_regno);
7157 if (mode == V16QImode)
7158 emit_insn (BYTES_BIG_ENDIAN
7159 ? gen_vextublx (dest_si, element_si, src)
7160 : gen_vextubrx (dest_si, element_si, src));
7162 else if (mode == V8HImode)
7164 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7165 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7166 emit_insn (BYTES_BIG_ENDIAN
7167 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7168 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7174 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7175 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7176 emit_insn (BYTES_BIG_ENDIAN
7177 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7178 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7185 gcc_assert (REG_P (tmp_altivec));
7187 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7188 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7189 will shift the element into the upper position (adding 3 to convert a
7190 byte shift into a bit shift). */
7191 if (scalar_size == 8)
7193 if (!BYTES_BIG_ENDIAN)
7195 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7201 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7203 emit_insn (gen_rtx_SET (tmp_gpr,
7204 gen_rtx_AND (DImode,
7205 gen_rtx_ASHIFT (DImode,
7212 if (!BYTES_BIG_ENDIAN)
7214 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7216 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7217 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7223 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7226 /* Get the value into the lower byte of the Altivec register where VSLO
7228 if (TARGET_P9_VECTOR)
7229 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7230 else if (can_create_pseudo_p ())
7231 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7234 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7235 emit_move_insn (tmp_di, tmp_gpr);
7236 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7239 /* Do the VSLO to get the value into the final location. */
7243 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7247 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7252 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7253 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7254 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7255 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7258 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7266 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7267 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7268 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7269 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7271 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7272 emit_insn (gen_lshrdi3 (tmp_gpr_di, tmp_gpr_di,
7273 GEN_INT (64 - bits_in_element)));
7287 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7288 selects whether the alignment is abi mandated, optional, or
7289 both abi and optional alignment. */
7292 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7294 if (how != align_opt)
7296 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7300 if (how != align_abi)
7302 if (TREE_CODE (type) == ARRAY_TYPE
7303 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7305 if (align < BITS_PER_WORD)
7306 align = BITS_PER_WORD;
7313 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7314 instructions simply ignore the low bits; VSX memory instructions
7315 are aligned to 4 or 8 bytes. */
7318 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7320 return (STRICT_ALIGNMENT
7321 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7322 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7323 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7324 && (int) align < VECTOR_ALIGN (mode)))));
7327 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7330 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7332 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7334 if (computed != 128)
7337 if (!warned && warn_psabi)
7340 inform (input_location,
7341 "the layout of aggregates containing vectors with"
7342 " %d-byte alignment has changed in GCC 5",
7343 computed / BITS_PER_UNIT);
7346 /* In current GCC there is no special case. */
7353 /* AIX increases natural record alignment to doubleword if the first
7354 field is an FP double while the FP fields remain word aligned. */
7357 rs6000_special_round_type_align (tree type, unsigned int computed,
7358 unsigned int specified)
7360 unsigned int align = MAX (computed, specified);
7361 tree field = TYPE_FIELDS (type);
7363 /* Skip all non field decls */
7364 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7365 field = DECL_CHAIN (field);
7367 if (field != NULL && field != type)
7369 type = TREE_TYPE (field);
7370 while (TREE_CODE (type) == ARRAY_TYPE)
7371 type = TREE_TYPE (type);
7373 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7374 align = MAX (align, 64);
7380 /* Darwin increases record alignment to the natural alignment of
7384 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7385 unsigned int specified)
7387 unsigned int align = MAX (computed, specified);
7389 if (TYPE_PACKED (type))
7392 /* Find the first field, looking down into aggregates. */
7394 tree field = TYPE_FIELDS (type);
7395 /* Skip all non field decls */
7396 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7397 field = DECL_CHAIN (field);
7400 /* A packed field does not contribute any extra alignment. */
7401 if (DECL_PACKED (field))
7403 type = TREE_TYPE (field);
7404 while (TREE_CODE (type) == ARRAY_TYPE)
7405 type = TREE_TYPE (type);
7406 } while (AGGREGATE_TYPE_P (type));
7408 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7409 align = MAX (align, TYPE_ALIGN (type));
7414 /* Return 1 for an operand in small memory on V.4/eabi. */
7417 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7418 machine_mode mode ATTRIBUTE_UNUSED)
7423 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7426 if (DEFAULT_ABI != ABI_V4)
7429 if (SYMBOL_REF_P (op))
7432 else if (GET_CODE (op) != CONST
7433 || GET_CODE (XEXP (op, 0)) != PLUS
7434 || !SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
7435 || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
7440 rtx sum = XEXP (op, 0);
7441 HOST_WIDE_INT summand;
7443 /* We have to be careful here, because it is the referenced address
7444 that must be 32k from _SDA_BASE_, not just the symbol. */
7445 summand = INTVAL (XEXP (sum, 1));
7446 if (summand < 0 || summand > g_switch_value)
7449 sym_ref = XEXP (sum, 0);
7452 return SYMBOL_REF_SMALL_P (sym_ref);
7458 /* Return true if either operand is a general purpose register. */
7461 gpr_or_gpr_p (rtx op0, rtx op1)
7463 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7464 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7467 /* Return true if this is a move direct operation between GPR registers and
7468 floating point/VSX registers. */
7471 direct_move_p (rtx op0, rtx op1)
7475 if (!REG_P (op0) || !REG_P (op1))
7478 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7481 regno0 = REGNO (op0);
7482 regno1 = REGNO (op1);
7483 if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
7486 if (INT_REGNO_P (regno0))
7487 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7489 else if (INT_REGNO_P (regno1))
7491 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7494 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7501 /* Return true if the OFFSET is valid for the quad address instructions that
7502 use d-form (register + offset) addressing. */
7505 quad_address_offset_p (HOST_WIDE_INT offset)
7507 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7510 /* Return true if the ADDR is an acceptable address for a quad memory
7511 operation of mode MODE (either LQ/STQ for general purpose registers, or
7512 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7513 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7514 3.0 LXV/STXV instruction. */
7517 quad_address_p (rtx addr, machine_mode mode, bool strict)
7521 if (GET_MODE_SIZE (mode) != 16)
7524 if (legitimate_indirect_address_p (addr, strict))
7527 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7530 if (GET_CODE (addr) != PLUS)
7533 op0 = XEXP (addr, 0);
7534 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7537 op1 = XEXP (addr, 1);
7538 if (!CONST_INT_P (op1))
7541 return quad_address_offset_p (INTVAL (op1));
7544 /* Return true if this is a load or store quad operation. This function does
7545 not handle the atomic quad memory instructions. */
7548 quad_load_store_p (rtx op0, rtx op1)
7552 if (!TARGET_QUAD_MEMORY)
7555 else if (REG_P (op0) && MEM_P (op1))
7556 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7557 && quad_memory_operand (op1, GET_MODE (op1))
7558 && !reg_overlap_mentioned_p (op0, op1));
7560 else if (MEM_P (op0) && REG_P (op1))
7561 ret = (quad_memory_operand (op0, GET_MODE (op0))
7562 && quad_int_reg_operand (op1, GET_MODE (op1)));
7567 if (TARGET_DEBUG_ADDR)
7569 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7570 ret ? "true" : "false");
7571 debug_rtx (gen_rtx_SET (op0, op1));
7577 /* Given an address, return a constant offset term if one exists. */
7580 address_offset (rtx op)
7582 if (GET_CODE (op) == PRE_INC
7583 || GET_CODE (op) == PRE_DEC)
7585 else if (GET_CODE (op) == PRE_MODIFY
7586 || GET_CODE (op) == LO_SUM)
7589 if (GET_CODE (op) == CONST)
7592 if (GET_CODE (op) == PLUS)
7595 if (CONST_INT_P (op))
7601 /* Return true if the MEM operand is a memory operand suitable for use
7602 with a (full width, possibly multiple) gpr load/store. On
7603 powerpc64 this means the offset must be divisible by 4.
7604 Implements 'Y' constraint.
7606 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7607 a constraint function we know the operand has satisfied a suitable
7610 Offsetting a lo_sum should not be allowed, except where we know by
7611 alignment that a 32k boundary is not crossed. Note that by
7612 "offsetting" here we mean a further offset to access parts of the
7613 MEM. It's fine to have a lo_sum where the inner address is offset
7614 from a sym, since the same sym+offset will appear in the high part
7615 of the address calculation. */
7618 mem_operand_gpr (rtx op, machine_mode mode)
7620 unsigned HOST_WIDE_INT offset;
7622 rtx addr = XEXP (op, 0);
7624 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7626 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7627 && mode_supports_pre_incdec_p (mode)
7628 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7631 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7632 if (!rs6000_offsettable_memref_p (op, mode, false))
7635 op = address_offset (addr);
7639 offset = INTVAL (op);
7640 if (TARGET_POWERPC64 && (offset & 3) != 0)
7643 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7647 if (GET_CODE (addr) == LO_SUM)
7648 /* For lo_sum addresses, we must allow any offset except one that
7649 causes a wrap, so test only the low 16 bits. */
7650 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7652 return offset + 0x8000 < 0x10000u - extra;
7655 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7656 enforce an offset divisible by 4 even for 32-bit. */
7659 mem_operand_ds_form (rtx op, machine_mode mode)
7661 unsigned HOST_WIDE_INT offset;
7663 rtx addr = XEXP (op, 0);
7665 if (!offsettable_address_p (false, mode, addr))
7668 op = address_offset (addr);
7672 offset = INTVAL (op);
7673 if ((offset & 3) != 0)
7676 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7680 if (GET_CODE (addr) == LO_SUM)
7681 /* For lo_sum addresses, we must allow any offset except one that
7682 causes a wrap, so test only the low 16 bits. */
7683 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7685 return offset + 0x8000 < 0x10000u - extra;
7688 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7691 reg_offset_addressing_ok_p (machine_mode mode)
7705 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7706 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7707 a vector mode, if we want to use the VSX registers to move it around,
7708 we need to restrict ourselves to reg+reg addressing. Similarly for
7709 IEEE 128-bit floating point that is passed in a single vector
7711 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7712 return mode_supports_dq_form (mode);
7716 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7717 addressing for the LFIWZX and STFIWX instructions. */
7718 if (TARGET_NO_SDMODE_STACK)
7730 virtual_stack_registers_memory_p (rtx op)
7735 regnum = REGNO (op);
7737 else if (GET_CODE (op) == PLUS
7738 && REG_P (XEXP (op, 0))
7739 && CONST_INT_P (XEXP (op, 1)))
7740 regnum = REGNO (XEXP (op, 0));
7745 return (regnum >= FIRST_VIRTUAL_REGISTER
7746 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7749 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7750 is known to not straddle a 32k boundary. This function is used
7751 to determine whether -mcmodel=medium code can use TOC pointer
7752 relative addressing for OP. This means the alignment of the TOC
7753 pointer must also be taken into account, and unfortunately that is
7756 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7757 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7761 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7765 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7767 if (!SYMBOL_REF_P (op))
7770 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7772 if (mode_supports_dq_form (mode))
7775 dsize = GET_MODE_SIZE (mode);
7776 decl = SYMBOL_REF_DECL (op);
7782 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7783 replacing memory addresses with an anchor plus offset. We
7784 could find the decl by rummaging around in the block->objects
7785 VEC for the given offset but that seems like too much work. */
7786 dalign = BITS_PER_UNIT;
7787 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7788 && SYMBOL_REF_ANCHOR_P (op)
7789 && SYMBOL_REF_BLOCK (op) != NULL)
7791 struct object_block *block = SYMBOL_REF_BLOCK (op);
7793 dalign = block->alignment;
7794 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7796 else if (CONSTANT_POOL_ADDRESS_P (op))
7798 /* It would be nice to have get_pool_align().. */
7799 machine_mode cmode = get_pool_mode (op);
7801 dalign = GET_MODE_ALIGNMENT (cmode);
7804 else if (DECL_P (decl))
7806 dalign = DECL_ALIGN (decl);
7810 /* Allow BLKmode when the entire object is known to not
7811 cross a 32k boundary. */
7812 if (!DECL_SIZE_UNIT (decl))
7815 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7818 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7822 dalign /= BITS_PER_UNIT;
7823 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7824 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7825 return dalign >= dsize;
7831 /* Find how many bits of the alignment we know for this access. */
7832 dalign /= BITS_PER_UNIT;
7833 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7834 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7836 lsb = offset & -offset;
7840 return dalign >= dsize;
7844 constant_pool_expr_p (rtx op)
7848 split_const (op, &base, &offset);
7849 return (SYMBOL_REF_P (base)
7850 && CONSTANT_POOL_ADDRESS_P (base)
7851 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7854 /* These are only used to pass through from print_operand/print_operand_address
7855 to rs6000_output_addr_const_extra over the intervening function
7856 output_addr_const which is not target code. */
7857 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7859 /* Return true if OP is a toc pointer relative address (the output
7860 of create_TOC_reference). If STRICT, do not match non-split
7861 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7862 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7863 TOCREL_OFFSET_RET respectively. */
7866 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7867 const_rtx *tocrel_offset_ret)
7872 if (TARGET_CMODEL != CMODEL_SMALL)
7874 /* When strict ensure we have everything tidy. */
7876 && !(GET_CODE (op) == LO_SUM
7877 && REG_P (XEXP (op, 0))
7878 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7881 /* When not strict, allow non-split TOC addresses and also allow
7882 (lo_sum (high ..)) TOC addresses created during reload. */
7883 if (GET_CODE (op) == LO_SUM)
7887 const_rtx tocrel_base = op;
7888 const_rtx tocrel_offset = const0_rtx;
7890 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7892 tocrel_base = XEXP (op, 0);
7893 tocrel_offset = XEXP (op, 1);
7896 if (tocrel_base_ret)
7897 *tocrel_base_ret = tocrel_base;
7898 if (tocrel_offset_ret)
7899 *tocrel_offset_ret = tocrel_offset;
7901 return (GET_CODE (tocrel_base) == UNSPEC
7902 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7903 && REG_P (XVECEXP (tocrel_base, 0, 1))
7904 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7907 /* Return true if X is a constant pool address, and also for cmodel=medium
7908 if X is a toc-relative address known to be offsettable within MODE. */
7911 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7914 const_rtx tocrel_base, tocrel_offset;
7915 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7916 && (TARGET_CMODEL != CMODEL_MEDIUM
7917 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7919 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7920 INTVAL (tocrel_offset), mode)));
7924 legitimate_small_data_p (machine_mode mode, rtx x)
7926 return (DEFAULT_ABI == ABI_V4
7927 && !flag_pic && !TARGET_TOC
7928 && (SYMBOL_REF_P (x) || GET_CODE (x) == CONST)
7929 && small_data_operand (x, mode));
7933 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7934 bool strict, bool worst_case)
7936 unsigned HOST_WIDE_INT offset;
7939 if (GET_CODE (x) != PLUS)
7941 if (!REG_P (XEXP (x, 0)))
7943 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7945 if (mode_supports_dq_form (mode))
7946 return quad_address_p (x, mode, strict);
7947 if (!reg_offset_addressing_ok_p (mode))
7948 return virtual_stack_registers_memory_p (x);
7949 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7951 if (!CONST_INT_P (XEXP (x, 1)))
7954 offset = INTVAL (XEXP (x, 1));
7961 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7963 if (VECTOR_MEM_VSX_P (mode))
7968 if (!TARGET_POWERPC64)
7970 else if (offset & 3)
7983 if (!TARGET_POWERPC64)
7985 else if (offset & 3)
7994 return offset < 0x10000 - extra;
7998 legitimate_indexed_address_p (rtx x, int strict)
8002 if (GET_CODE (x) != PLUS)
8008 return (REG_P (op0) && REG_P (op1)
8009 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8010 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8011 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8012 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8016 avoiding_indexed_address_p (machine_mode mode)
8018 /* Avoid indexed addressing for modes that have non-indexed
8019 load/store instruction forms. */
8020 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8024 legitimate_indirect_address_p (rtx x, int strict)
8026 return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
8030 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8032 if (!TARGET_MACHO || !flag_pic
8033 || mode != SImode || !MEM_P (x))
8037 if (GET_CODE (x) != LO_SUM)
8039 if (!REG_P (XEXP (x, 0)))
8041 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8045 return CONSTANT_P (x);
8049 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8051 if (GET_CODE (x) != LO_SUM)
8053 if (!REG_P (XEXP (x, 0)))
8055 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8057 /* quad word addresses are restricted, and we can't use LO_SUM. */
8058 if (mode_supports_dq_form (mode))
8062 if (TARGET_ELF || TARGET_MACHO)
8066 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8068 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8069 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8070 recognizes some LO_SUM addresses as valid although this
8071 function says opposite. In most cases, LRA through different
8072 transformations can generate correct code for address reloads.
8073 It cannot manage only some LO_SUM cases. So we need to add
8074 code here saying that some addresses are still valid. */
8075 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8076 && small_toc_ref (x, VOIDmode));
8077 if (TARGET_TOC && ! large_toc_ok)
8079 if (GET_MODE_NUNITS (mode) != 1)
8081 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8082 && !(/* ??? Assume floating point reg based on mode? */
8083 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8086 return CONSTANT_P (x) || large_toc_ok;
8093 /* Try machine-dependent ways of modifying an illegitimate address
8094 to be legitimate. If we find one, return the new, valid address.
8095 This is used from only one place: `memory_address' in explow.c.
8097 OLDX is the address as it was before break_out_memory_refs was
8098 called. In some cases it is useful to look at this to decide what
8101 It is always safe for this function to do nothing. It exists to
8102 recognize opportunities to optimize the output.
8104 On RS/6000, first check for the sum of a register with a constant
8105 integer that is out of range. If so, generate code to add the
8106 constant with the low-order 16 bits masked to the register and force
8107 this result into another register (this can be done with `cau').
8108 Then generate an address of REG+(CONST&0xffff), allowing for the
8109 possibility of bit 16 being a one.
8111 Then check for the sum of a register and something not constant, try to
8112 load the other things into a register and return the sum. */
8115 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8120 if (!reg_offset_addressing_ok_p (mode)
8121 || mode_supports_dq_form (mode))
8123 if (virtual_stack_registers_memory_p (x))
8126 /* In theory we should not be seeing addresses of the form reg+0,
8127 but just in case it is generated, optimize it away. */
8128 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8129 return force_reg (Pmode, XEXP (x, 0));
8131 /* For TImode with load/store quad, restrict addresses to just a single
8132 pointer, so it works with both GPRs and VSX registers. */
8133 /* Make sure both operands are registers. */
8134 else if (GET_CODE (x) == PLUS
8135 && (mode != TImode || !TARGET_VSX))
8136 return gen_rtx_PLUS (Pmode,
8137 force_reg (Pmode, XEXP (x, 0)),
8138 force_reg (Pmode, XEXP (x, 1)));
8140 return force_reg (Pmode, x);
8142 if (SYMBOL_REF_P (x))
8144 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8146 return rs6000_legitimize_tls_address (x, model);
8158 /* As in legitimate_offset_address_p we do not assume
8159 worst-case. The mode here is just a hint as to the registers
8160 used. A TImode is usually in gprs, but may actually be in
8161 fprs. Leave worst-case scenario for reload to handle via
8162 insn constraints. PTImode is only GPRs. */
8169 if (GET_CODE (x) == PLUS
8170 && REG_P (XEXP (x, 0))
8171 && CONST_INT_P (XEXP (x, 1))
8172 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8173 >= 0x10000 - extra))
8175 HOST_WIDE_INT high_int, low_int;
8177 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8178 if (low_int >= 0x8000 - extra)
8180 high_int = INTVAL (XEXP (x, 1)) - low_int;
8181 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8182 GEN_INT (high_int)), 0);
8183 return plus_constant (Pmode, sum, low_int);
8185 else if (GET_CODE (x) == PLUS
8186 && REG_P (XEXP (x, 0))
8187 && !CONST_INT_P (XEXP (x, 1))
8188 && GET_MODE_NUNITS (mode) == 1
8189 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8190 || (/* ??? Assume floating point reg based on mode? */
8191 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8192 && !avoiding_indexed_address_p (mode))
8194 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8195 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8197 else if ((TARGET_ELF
8199 || !MACHO_DYNAMIC_NO_PIC_P
8206 && !CONST_WIDE_INT_P (x)
8207 && !CONST_DOUBLE_P (x)
8209 && GET_MODE_NUNITS (mode) == 1
8210 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8211 || (/* ??? Assume floating point reg based on mode? */
8212 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8214 rtx reg = gen_reg_rtx (Pmode);
8216 emit_insn (gen_elf_high (reg, x));
8218 emit_insn (gen_macho_high (reg, x));
8219 return gen_rtx_LO_SUM (Pmode, reg, x);
8223 && constant_pool_expr_p (x)
8224 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8225 return create_TOC_reference (x, NULL_RTX);
8230 /* Debug version of rs6000_legitimize_address. */
8232 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8238 ret = rs6000_legitimize_address (x, oldx, mode);
8239 insns = get_insns ();
8245 "\nrs6000_legitimize_address: mode %s, old code %s, "
8246 "new code %s, modified\n",
8247 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8248 GET_RTX_NAME (GET_CODE (ret)));
8250 fprintf (stderr, "Original address:\n");
8253 fprintf (stderr, "oldx:\n");
8256 fprintf (stderr, "New address:\n");
8261 fprintf (stderr, "Insns added:\n");
8262 debug_rtx_list (insns, 20);
8268 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8269 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8280 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8281 We need to emit DTP-relative relocations. */
8283 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8285 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8290 fputs ("\t.long\t", file);
8293 fputs (DOUBLE_INT_ASM_OP, file);
8298 output_addr_const (file, x);
8300 fputs ("@dtprel+0x8000", file);
8301 else if (TARGET_XCOFF && SYMBOL_REF_P (x))
8303 switch (SYMBOL_REF_TLS_MODEL (x))
8307 case TLS_MODEL_LOCAL_EXEC:
8308 fputs ("@le", file);
8310 case TLS_MODEL_INITIAL_EXEC:
8311 fputs ("@ie", file);
8313 case TLS_MODEL_GLOBAL_DYNAMIC:
8314 case TLS_MODEL_LOCAL_DYNAMIC:
8323 /* Return true if X is a symbol that refers to real (rather than emulated)
8327 rs6000_real_tls_symbol_ref_p (rtx x)
8329 return (SYMBOL_REF_P (x)
8330 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8333 /* In the name of slightly smaller debug output, and to cater to
8334 general assembler lossage, recognize various UNSPEC sequences
8335 and turn them back into a direct symbol reference. */
8338 rs6000_delegitimize_address (rtx orig_x)
8342 if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
8343 orig_x = XVECEXP (orig_x, 0, 0);
8345 orig_x = delegitimize_mem_from_attrs (orig_x);
8352 if (TARGET_CMODEL != CMODEL_SMALL && GET_CODE (y) == LO_SUM)
8356 if (GET_CODE (y) == PLUS
8357 && GET_MODE (y) == Pmode
8358 && CONST_INT_P (XEXP (y, 1)))
8360 offset = XEXP (y, 1);
8364 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL)
8366 y = XVECEXP (y, 0, 0);
8369 /* Do not associate thread-local symbols with the original
8370 constant pool symbol. */
8373 && CONSTANT_POOL_ADDRESS_P (y)
8374 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8378 if (offset != NULL_RTX)
8379 y = gen_rtx_PLUS (Pmode, y, offset);
8380 if (!MEM_P (orig_x))
8383 return replace_equiv_address_nv (orig_x, y);
8387 && GET_CODE (orig_x) == LO_SUM
8388 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8390 y = XEXP (XEXP (orig_x, 1), 0);
8391 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8392 return XVECEXP (y, 0, 0);
8398 /* Return true if X shouldn't be emitted into the debug info.
8399 The linker doesn't like .toc section references from
8400 .debug_* sections, so reject .toc section symbols. */
8403 rs6000_const_not_ok_for_debug_p (rtx x)
8405 if (GET_CODE (x) == UNSPEC)
8407 if (SYMBOL_REF_P (x)
8408 && CONSTANT_POOL_ADDRESS_P (x))
8410 rtx c = get_pool_constant (x);
8411 machine_mode cmode = get_pool_mode (x);
8412 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8419 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8422 rs6000_legitimate_combined_insn (rtx_insn *insn)
8424 int icode = INSN_CODE (insn);
8426 /* Reject creating doloop insns. Combine should not be allowed
8427 to create these for a number of reasons:
8428 1) In a nested loop, if combine creates one of these in an
8429 outer loop and the register allocator happens to allocate ctr
8430 to the outer loop insn, then the inner loop can't use ctr.
8431 Inner loops ought to be more highly optimized.
8432 2) Combine often wants to create one of these from what was
8433 originally a three insn sequence, first combining the three
8434 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8435 allocated ctr, the splitter takes use back to the three insn
8436 sequence. It's better to stop combine at the two insn
8438 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8439 insns, the register allocator sometimes uses floating point
8440 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8441 jump insn and output reloads are not implemented for jumps,
8442 the ctrsi/ctrdi splitters need to handle all possible cases.
8443 That's a pain, and it gets to be seriously difficult when a
8444 splitter that runs after reload needs memory to transfer from
8445 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8446 for the difficult case. It's better to not create problems
8447 in the first place. */
8448 if (icode != CODE_FOR_nothing
8449 && (icode == CODE_FOR_bdz_si
8450 || icode == CODE_FOR_bdz_di
8451 || icode == CODE_FOR_bdnz_si
8452 || icode == CODE_FOR_bdnz_di
8453 || icode == CODE_FOR_bdztf_si
8454 || icode == CODE_FOR_bdztf_di
8455 || icode == CODE_FOR_bdnztf_si
8456 || icode == CODE_FOR_bdnztf_di))
8462 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8464 static GTY(()) rtx rs6000_tls_symbol;
8466 rs6000_tls_get_addr (void)
8468 if (!rs6000_tls_symbol)
8469 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8471 return rs6000_tls_symbol;
8474 /* Construct the SYMBOL_REF for TLS GOT references. */
8476 static GTY(()) rtx rs6000_got_symbol;
8478 rs6000_got_sym (void)
8480 if (!rs6000_got_symbol)
8482 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8483 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8484 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8487 return rs6000_got_symbol;
8490 /* AIX Thread-Local Address support. */
8493 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8495 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8499 name = XSTR (addr, 0);
8500 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8501 or the symbol will be in TLS private data section. */
8502 if (name[strlen (name) - 1] != ']'
8503 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8504 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8506 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8507 strcpy (tlsname, name);
8509 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8510 tlsaddr = copy_rtx (addr);
8511 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8516 /* Place addr into TOC constant pool. */
8517 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8519 /* Output the TOC entry and create the MEM referencing the value. */
8520 if (constant_pool_expr_p (XEXP (sym, 0))
8521 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8523 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8524 mem = gen_const_mem (Pmode, tocref);
8525 set_mem_alias_set (mem, get_TOC_alias_set ());
8530 /* Use global-dynamic for local-dynamic. */
8531 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8532 || model == TLS_MODEL_LOCAL_DYNAMIC)
8534 /* Create new TOC reference for @m symbol. */
8535 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8536 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8537 strcpy (tlsname, "*LCM");
8538 strcat (tlsname, name + 3);
8539 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8540 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8541 tocref = create_TOC_reference (modaddr, NULL_RTX);
8542 rtx modmem = gen_const_mem (Pmode, tocref);
8543 set_mem_alias_set (modmem, get_TOC_alias_set ());
8545 rtx modreg = gen_reg_rtx (Pmode);
8546 emit_insn (gen_rtx_SET (modreg, modmem));
8548 tmpreg = gen_reg_rtx (Pmode);
8549 emit_insn (gen_rtx_SET (tmpreg, mem));
8551 dest = gen_reg_rtx (Pmode);
8553 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8555 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8558 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8559 else if (TARGET_32BIT)
8561 tlsreg = gen_reg_rtx (SImode);
8562 emit_insn (gen_tls_get_tpointer (tlsreg));
8565 tlsreg = gen_rtx_REG (DImode, 13);
8567 /* Load the TOC value into temporary register. */
8568 tmpreg = gen_reg_rtx (Pmode);
8569 emit_insn (gen_rtx_SET (tmpreg, mem));
8570 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8571 gen_rtx_MINUS (Pmode, addr, tlsreg));
8573 /* Add TOC symbol value to TLS pointer. */
8574 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8579 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8580 __tls_get_addr call. */
8583 rs6000_output_tlsargs (rtx *operands)
8585 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8588 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8589 op[0] = operands[0];
8590 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8591 op[1] = XVECEXP (operands[2], 0, 0);
8592 if (XINT (operands[2], 1) == UNSPEC_TLSGD)
8594 /* The GOT register. */
8595 op[2] = XVECEXP (operands[2], 0, 1);
8596 if (TARGET_CMODEL != CMODEL_SMALL)
8597 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8598 "addi %0,%0,%1@got@tlsgd@l", op);
8600 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op);
8602 else if (XINT (operands[2], 1) == UNSPEC_TLSLD)
8604 if (TARGET_CMODEL != CMODEL_SMALL)
8605 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8606 "addi %0,%0,%&@got@tlsld@l", op);
8608 output_asm_insn ("addi %0,%1,%&@got@tlsld", op);
8614 /* Passes the tls arg value for global dynamic and local dynamic
8615 emit_library_call_value in rs6000_legitimize_tls_address to
8616 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8617 marker relocs put on __tls_get_addr calls. */
8618 static rtx global_tlsarg;
8620 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8621 this (thread-local) address. */
8624 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8629 return rs6000_legitimize_tls_address_aix (addr, model);
8631 dest = gen_reg_rtx (Pmode);
8632 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8638 tlsreg = gen_rtx_REG (Pmode, 13);
8639 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8643 tlsreg = gen_rtx_REG (Pmode, 2);
8644 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8648 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8652 tmp = gen_reg_rtx (Pmode);
8655 tlsreg = gen_rtx_REG (Pmode, 13);
8656 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8660 tlsreg = gen_rtx_REG (Pmode, 2);
8661 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8665 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8667 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8672 rtx got, tga, tmp1, tmp2;
8674 /* We currently use relocations like @got@tlsgd for tls, which
8675 means the linker will handle allocation of tls entries, placing
8676 them in the .got section. So use a pointer to the .got section,
8677 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8678 or to secondary GOT sections used by 32-bit -fPIC. */
8680 got = gen_rtx_REG (Pmode, 2);
8684 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8687 rtx gsym = rs6000_got_sym ();
8688 got = gen_reg_rtx (Pmode);
8690 rs6000_emit_move (got, gsym, Pmode);
8695 tmp1 = gen_reg_rtx (Pmode);
8696 tmp2 = gen_reg_rtx (Pmode);
8697 mem = gen_const_mem (Pmode, tmp1);
8698 lab = gen_label_rtx ();
8699 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8700 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8701 if (TARGET_LINK_STACK)
8702 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8703 emit_move_insn (tmp2, mem);
8704 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8705 set_unique_reg_note (last, REG_EQUAL, gsym);
8710 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8712 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addr, got),
8714 tga = rs6000_tls_get_addr ();
8715 global_tlsarg = arg;
8716 if (TARGET_TLS_MARKERS)
8718 rtx argreg = gen_rtx_REG (Pmode, 3);
8719 emit_insn (gen_rtx_SET (argreg, arg));
8720 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8724 emit_library_call_value (tga, dest, LCT_CONST, Pmode);
8725 global_tlsarg = NULL_RTX;
8727 /* Make a note so that the result of this call can be CSEd. */
8728 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8729 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8730 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8732 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8734 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got), UNSPEC_TLSLD);
8735 tga = rs6000_tls_get_addr ();
8736 tmp1 = gen_reg_rtx (Pmode);
8737 global_tlsarg = arg;
8738 if (TARGET_TLS_MARKERS)
8740 rtx argreg = gen_rtx_REG (Pmode, 3);
8741 emit_insn (gen_rtx_SET (argreg, arg));
8742 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8746 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode);
8747 global_tlsarg = NULL_RTX;
8749 /* Make a note so that the result of this call can be CSEd. */
8750 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8751 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8752 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8754 if (rs6000_tls_size == 16)
8757 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8759 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8761 else if (rs6000_tls_size == 32)
8763 tmp2 = gen_reg_rtx (Pmode);
8765 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8767 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8770 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8772 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8776 tmp2 = gen_reg_rtx (Pmode);
8778 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8780 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8782 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8788 /* IE, or 64-bit offset LE. */
8789 tmp2 = gen_reg_rtx (Pmode);
8791 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8793 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8796 insn = gen_tls_tls_64 (dest, tmp2, addr);
8798 insn = gen_tls_tls_32 (dest, tmp2, addr);
8806 /* Only create the global variable for the stack protect guard if we are using
8807 the global flavor of that guard. */
8809 rs6000_init_stack_protect_guard (void)
8811 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8812 return default_stack_protect_guard ();
8817 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8820 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8822 if (GET_CODE (x) == HIGH
8823 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8826 /* A TLS symbol in the TOC cannot contain a sum. */
8827 if (GET_CODE (x) == CONST
8828 && GET_CODE (XEXP (x, 0)) == PLUS
8829 && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
8830 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8833 /* Do not place an ELF TLS symbol in the constant pool. */
8834 return TARGET_ELF && tls_referenced_p (x);
8837 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8838 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8839 can be addressed relative to the toc pointer. */
8842 use_toc_relative_ref (rtx sym, machine_mode mode)
8844 return ((constant_pool_expr_p (sym)
8845 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8846 get_pool_mode (sym)))
8847 || (TARGET_CMODEL == CMODEL_MEDIUM
8848 && SYMBOL_REF_LOCAL_P (sym)
8849 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8852 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8853 that is a valid memory address for an instruction.
8854 The MODE argument is the machine mode for the MEM expression
8855 that wants to use this address.
8857 On the RS/6000, there are four valid address: a SYMBOL_REF that
8858 refers to a constant pool entry of an address (or the sum of it
8859 plus a constant), a short (16-bit signed) constant plus a register,
8860 the sum of two registers, or a register indirect, possibly with an
8861 auto-increment. For DFmode, DDmode and DImode with a constant plus
8862 register, we must ensure that both words are addressable or PowerPC64
8863 with offset word aligned.
8865 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8866 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8867 because adjacent memory cells are accessed by adding word-sized offsets
8868 during assembly output. */
8870 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
8872 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8873 bool quad_offset_p = mode_supports_dq_form (mode);
8875 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8876 if (VECTOR_MEM_ALTIVEC_P (mode)
8877 && GET_CODE (x) == AND
8878 && CONST_INT_P (XEXP (x, 1))
8879 && INTVAL (XEXP (x, 1)) == -16)
8882 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
8884 if (legitimate_indirect_address_p (x, reg_ok_strict))
8887 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
8888 && mode_supports_pre_incdec_p (mode)
8889 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
8891 /* Handle restricted vector d-form offsets in ISA 3.0. */
8894 if (quad_address_p (x, mode, reg_ok_strict))
8897 else if (virtual_stack_registers_memory_p (x))
8900 else if (reg_offset_p)
8902 if (legitimate_small_data_p (mode, x))
8904 if (legitimate_constant_pool_address_p (x, mode,
8905 reg_ok_strict || lra_in_progress))
8909 /* For TImode, if we have TImode in VSX registers, only allow register
8910 indirect addresses. This will allow the values to go in either GPRs
8911 or VSX registers without reloading. The vector types would tend to
8912 go into VSX registers, so we allow REG+REG, while TImode seems
8913 somewhat split, in that some uses are GPR based, and some VSX based. */
8914 /* FIXME: We could loosen this by changing the following to
8915 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
8916 but currently we cannot allow REG+REG addressing for TImode. See
8917 PR72827 for complete details on how this ends up hoodwinking DSE. */
8918 if (mode == TImode && TARGET_VSX)
8920 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8923 && GET_CODE (x) == PLUS
8924 && REG_P (XEXP (x, 0))
8925 && (XEXP (x, 0) == virtual_stack_vars_rtx
8926 || XEXP (x, 0) == arg_pointer_rtx)
8927 && CONST_INT_P (XEXP (x, 1)))
8929 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
8931 if (!FLOAT128_2REG_P (mode)
8932 && (TARGET_HARD_FLOAT
8934 || (mode != DFmode && mode != DDmode))
8935 && (TARGET_POWERPC64 || mode != DImode)
8936 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
8938 && !avoiding_indexed_address_p (mode)
8939 && legitimate_indexed_address_p (x, reg_ok_strict))
8941 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
8942 && mode_supports_pre_modify_p (mode)
8943 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
8944 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
8945 reg_ok_strict, false)
8946 || (!avoiding_indexed_address_p (mode)
8947 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
8948 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8950 if (reg_offset_p && !quad_offset_p
8951 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
8956 /* Debug version of rs6000_legitimate_address_p. */
8958 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
8961 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
8963 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8964 "strict = %d, reload = %s, code = %s\n",
8965 ret ? "true" : "false",
8966 GET_MODE_NAME (mode),
8968 (reload_completed ? "after" : "before"),
8969 GET_RTX_NAME (GET_CODE (x)));
8975 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8978 rs6000_mode_dependent_address_p (const_rtx addr,
8979 addr_space_t as ATTRIBUTE_UNUSED)
8981 return rs6000_mode_dependent_address_ptr (addr);
8984 /* Go to LABEL if ADDR (a legitimate address expression)
8985 has an effect that depends on the machine mode it is used for.
8987 On the RS/6000 this is true of all integral offsets (since AltiVec
8988 and VSX modes don't allow them) or is a pre-increment or decrement.
8990 ??? Except that due to conceptual problems in offsettable_address_p
8991 we can't really report the problems of integral offsets. So leave
8992 this assuming that the adjustable offset must be valid for the
8993 sub-words of a TFmode operand, which is what we had before. */
8996 rs6000_mode_dependent_address (const_rtx addr)
8998 switch (GET_CODE (addr))
9001 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9002 is considered a legitimate address before reload, so there
9003 are no offset restrictions in that case. Note that this
9004 condition is safe in strict mode because any address involving
9005 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9006 been rejected as illegitimate. */
9007 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9008 && XEXP (addr, 0) != arg_pointer_rtx
9009 && CONST_INT_P (XEXP (addr, 1)))
9011 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9012 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9017 /* Anything in the constant pool is sufficiently aligned that
9018 all bytes have the same high part address. */
9019 return !legitimate_constant_pool_address_p (addr, QImode, false);
9021 /* Auto-increment cases are now treated generically in recog.c. */
9023 return TARGET_UPDATE;
9025 /* AND is only allowed in Altivec loads. */
9036 /* Debug version of rs6000_mode_dependent_address. */
9038 rs6000_debug_mode_dependent_address (const_rtx addr)
9040 bool ret = rs6000_mode_dependent_address (addr);
9042 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9043 ret ? "true" : "false");
9049 /* Implement FIND_BASE_TERM. */
9052 rs6000_find_base_term (rtx op)
9057 if (GET_CODE (base) == CONST)
9058 base = XEXP (base, 0);
9059 if (GET_CODE (base) == PLUS)
9060 base = XEXP (base, 0);
9061 if (GET_CODE (base) == UNSPEC)
9062 switch (XINT (base, 1))
9065 case UNSPEC_MACHOPIC_OFFSET:
9066 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9067 for aliasing purposes. */
9068 return XVECEXP (base, 0, 0);
9074 /* More elaborate version of recog's offsettable_memref_p predicate
9075 that works around the ??? note of rs6000_mode_dependent_address.
9076 In particular it accepts
9078 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9080 in 32-bit mode, that the recog predicate rejects. */
9083 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9090 /* First mimic offsettable_memref_p. */
9091 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9094 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9095 the latter predicate knows nothing about the mode of the memory
9096 reference and, therefore, assumes that it is the largest supported
9097 mode (TFmode). As a consequence, legitimate offsettable memory
9098 references are rejected. rs6000_legitimate_offset_address_p contains
9099 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9100 at least with a little bit of help here given that we know the
9101 actual registers used. */
9102 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9103 || GET_MODE_SIZE (reg_mode) == 4);
9104 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9105 strict, worst_case);
9108 /* Determine the reassociation width to be used in reassociate_bb.
9109 This takes into account how many parallel operations we
9110 can actually do of a given type, and also the latency.
9114 vect add/sub/mul 2/cycle
9115 fp add/sub/mul 2/cycle
9120 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9123 switch (rs6000_tune)
9125 case PROCESSOR_POWER8:
9126 case PROCESSOR_POWER9:
9127 case PROCESSOR_FUTURE:
9128 if (DECIMAL_FLOAT_MODE_P (mode))
9130 if (VECTOR_MODE_P (mode))
9132 if (INTEGRAL_MODE_P (mode))
9134 if (FLOAT_MODE_P (mode))
9143 /* Change register usage conditional on target flags. */
9145 rs6000_conditional_register_usage (void)
9149 if (TARGET_DEBUG_TARGET)
9150 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9152 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9154 fixed_regs[13] = call_used_regs[13]
9155 = call_really_used_regs[13] = 1;
9157 /* Conditionally disable FPRs. */
9158 if (TARGET_SOFT_FLOAT)
9159 for (i = 32; i < 64; i++)
9160 fixed_regs[i] = call_used_regs[i]
9161 = call_really_used_regs[i] = 1;
9163 /* The TOC register is not killed across calls in a way that is
9164 visible to the compiler. */
9165 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9166 call_really_used_regs[2] = 0;
9168 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9169 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9171 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9172 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9173 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9174 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9176 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9177 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9178 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9179 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9181 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9182 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9183 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9185 if (!TARGET_ALTIVEC && !TARGET_VSX)
9187 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9188 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9189 call_really_used_regs[VRSAVE_REGNO] = 1;
9192 if (TARGET_ALTIVEC || TARGET_VSX)
9193 global_regs[VSCR_REGNO] = 1;
9195 if (TARGET_ALTIVEC_ABI)
9197 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9198 call_used_regs[i] = call_really_used_regs[i] = 1;
9200 /* AIX reserves VR20:31 in non-extended ABI mode. */
9202 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9203 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9208 /* Output insns to set DEST equal to the constant SOURCE as a series of
9209 lis, ori and shl instructions and return TRUE. */
9212 rs6000_emit_set_const (rtx dest, rtx source)
9214 machine_mode mode = GET_MODE (dest);
9219 gcc_checking_assert (CONST_INT_P (source));
9220 c = INTVAL (source);
9225 emit_insn (gen_rtx_SET (dest, source));
9229 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9231 emit_insn (gen_rtx_SET (copy_rtx (temp),
9232 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9233 emit_insn (gen_rtx_SET (dest,
9234 gen_rtx_IOR (SImode, copy_rtx (temp),
9235 GEN_INT (c & 0xffff))));
9239 if (!TARGET_POWERPC64)
9243 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9245 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9247 emit_move_insn (hi, GEN_INT (c >> 32));
9248 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9249 emit_move_insn (lo, GEN_INT (c));
9252 rs6000_emit_set_long_const (dest, c);
9259 insn = get_last_insn ();
9260 set = single_set (insn);
9261 if (! CONSTANT_P (SET_SRC (set)))
9262 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9267 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9268 Output insns to set DEST equal to the constant C as a series of
9269 lis, ori and shl instructions. */
9272 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9275 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9285 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9286 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9287 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9289 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9290 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9292 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9294 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9295 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9297 emit_move_insn (dest,
9298 gen_rtx_IOR (DImode, copy_rtx (temp),
9301 else if (ud3 == 0 && ud4 == 0)
9303 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9305 gcc_assert (ud2 & 0x8000);
9306 emit_move_insn (copy_rtx (temp),
9307 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9309 emit_move_insn (copy_rtx (temp),
9310 gen_rtx_IOR (DImode, copy_rtx (temp),
9312 emit_move_insn (dest,
9313 gen_rtx_ZERO_EXTEND (DImode,
9314 gen_lowpart (SImode,
9317 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9318 || (ud4 == 0 && ! (ud3 & 0x8000)))
9320 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9322 emit_move_insn (copy_rtx (temp),
9323 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9325 emit_move_insn (copy_rtx (temp),
9326 gen_rtx_IOR (DImode, copy_rtx (temp),
9328 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9329 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9332 emit_move_insn (dest,
9333 gen_rtx_IOR (DImode, copy_rtx (temp),
9338 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9340 emit_move_insn (copy_rtx (temp),
9341 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9343 emit_move_insn (copy_rtx (temp),
9344 gen_rtx_IOR (DImode, copy_rtx (temp),
9347 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9348 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9351 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9352 gen_rtx_IOR (DImode, copy_rtx (temp),
9353 GEN_INT (ud2 << 16)));
9355 emit_move_insn (dest,
9356 gen_rtx_IOR (DImode, copy_rtx (temp),
9361 /* Helper for the following. Get rid of [r+r] memory refs
9362 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9365 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9367 if (MEM_P (operands[0])
9368 && !REG_P (XEXP (operands[0], 0))
9369 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9370 GET_MODE (operands[0]), false))
9372 = replace_equiv_address (operands[0],
9373 copy_addr_to_reg (XEXP (operands[0], 0)));
9375 if (MEM_P (operands[1])
9376 && !REG_P (XEXP (operands[1], 0))
9377 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9378 GET_MODE (operands[1]), false))
9380 = replace_equiv_address (operands[1],
9381 copy_addr_to_reg (XEXP (operands[1], 0)));
9384 /* Generate a vector of constants to permute MODE for a little-endian
9385 storage operation by swapping the two halves of a vector. */
9387 rs6000_const_vec (machine_mode mode)
9415 v = rtvec_alloc (subparts);
9417 for (i = 0; i < subparts / 2; ++i)
9418 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9419 for (i = subparts / 2; i < subparts; ++i)
9420 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9425 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9428 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9430 /* Scalar permutations are easier to express in integer modes rather than
9431 floating-point modes, so cast them here. We use V1TImode instead
9432 of TImode to ensure that the values don't go through GPRs. */
9433 if (FLOAT128_VECTOR_P (mode))
9435 dest = gen_lowpart (V1TImode, dest);
9436 source = gen_lowpart (V1TImode, source);
9440 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9442 if (mode == TImode || mode == V1TImode)
9443 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9447 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9448 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9452 /* Emit a little-endian load from vector memory location SOURCE to VSX
9453 register DEST in mode MODE. The load is done with two permuting
9454 insn's that represent an lxvd2x and xxpermdi. */
9456 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9458 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9460 if (mode == TImode || mode == V1TImode)
9463 dest = gen_lowpart (V2DImode, dest);
9464 source = adjust_address (source, V2DImode, 0);
9467 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9468 rs6000_emit_le_vsx_permute (tmp, source, mode);
9469 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9472 /* Emit a little-endian store to vector memory location DEST from VSX
9473 register SOURCE in mode MODE. The store is done with two permuting
9474 insn's that represent an xxpermdi and an stxvd2x. */
9476 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9478 /* This should never be called during or after LRA, because it does
9479 not re-permute the source register. It is intended only for use
9481 gcc_assert (!lra_in_progress && !reload_completed);
9483 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9485 if (mode == TImode || mode == V1TImode)
9488 dest = adjust_address (dest, V2DImode, 0);
9489 source = gen_lowpart (V2DImode, source);
9492 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9493 rs6000_emit_le_vsx_permute (tmp, source, mode);
9494 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9497 /* Emit a sequence representing a little-endian VSX load or store,
9498 moving data from SOURCE to DEST in mode MODE. This is done
9499 separately from rs6000_emit_move to ensure it is called only
9500 during expand. LE VSX loads and stores introduced later are
9501 handled with a split. The expand-time RTL generation allows
9502 us to optimize away redundant pairs of register-permutes. */
9504 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9506 gcc_assert (!BYTES_BIG_ENDIAN
9507 && VECTOR_MEM_VSX_P (mode)
9508 && !TARGET_P9_VECTOR
9509 && !gpr_or_gpr_p (dest, source)
9510 && (MEM_P (source) ^ MEM_P (dest)));
9514 gcc_assert (REG_P (dest) || SUBREG_P (dest));
9515 rs6000_emit_le_vsx_load (dest, source, mode);
9519 if (!REG_P (source))
9520 source = force_reg (mode, source);
9521 rs6000_emit_le_vsx_store (dest, source, mode);
9525 /* Return whether a SFmode or SImode move can be done without converting one
9526 mode to another. This arrises when we have:
9528 (SUBREG:SF (REG:SI ...))
9529 (SUBREG:SI (REG:SF ...))
9531 and one of the values is in a floating point/vector register, where SFmode
9532 scalars are stored in DFmode format. */
9535 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9537 if (TARGET_ALLOW_SF_SUBREG)
9540 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9543 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9546 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9547 if (SUBREG_P (dest))
9549 rtx dest_subreg = SUBREG_REG (dest);
9550 rtx src_subreg = SUBREG_REG (src);
9551 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9558 /* Helper function to change moves with:
9560 (SUBREG:SF (REG:SI)) and
9561 (SUBREG:SI (REG:SF))
9563 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9564 values are stored as DFmode values in the VSX registers. We need to convert
9565 the bits before we can use a direct move or operate on the bits in the
9566 vector register as an integer type.
9568 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9571 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9573 if (TARGET_DIRECT_MOVE_64BIT && !reload_completed
9574 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9575 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9577 rtx inner_source = SUBREG_REG (source);
9578 machine_mode inner_mode = GET_MODE (inner_source);
9580 if (mode == SImode && inner_mode == SFmode)
9582 emit_insn (gen_movsi_from_sf (dest, inner_source));
9586 if (mode == SFmode && inner_mode == SImode)
9588 emit_insn (gen_movsf_from_si (dest, inner_source));
9596 /* Emit a move from SOURCE to DEST in mode MODE. */
9598 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9602 operands[1] = source;
9604 if (TARGET_DEBUG_ADDR)
9607 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9608 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9609 GET_MODE_NAME (mode),
9612 can_create_pseudo_p ());
9614 fprintf (stderr, "source:\n");
9618 /* Check that we get CONST_WIDE_INT only when we should. */
9619 if (CONST_WIDE_INT_P (operands[1])
9620 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9623 #ifdef HAVE_AS_GNU_ATTRIBUTE
9624 /* If we use a long double type, set the flags in .gnu_attribute that say
9625 what the long double type is. This is to allow the linker's warning
9626 message for the wrong long double to be useful, even if the function does
9627 not do a call (for example, doing a 128-bit add on power9 if the long
9628 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9629 used if they aren't the default long dobule type. */
9630 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9632 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9633 rs6000_passes_float = rs6000_passes_long_double = true;
9635 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9636 rs6000_passes_float = rs6000_passes_long_double = true;
9640 /* See if we need to special case SImode/SFmode SUBREG moves. */
9641 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9642 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9645 /* Check if GCC is setting up a block move that will end up using FP
9646 registers as temporaries. We must make sure this is acceptable. */
9647 if (MEM_P (operands[0])
9648 && MEM_P (operands[1])
9650 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9651 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9652 && ! (rs6000_slow_unaligned_access (SImode,
9653 (MEM_ALIGN (operands[0]) > 32
9654 ? 32 : MEM_ALIGN (operands[0])))
9655 || rs6000_slow_unaligned_access (SImode,
9656 (MEM_ALIGN (operands[1]) > 32
9657 ? 32 : MEM_ALIGN (operands[1]))))
9658 && ! MEM_VOLATILE_P (operands [0])
9659 && ! MEM_VOLATILE_P (operands [1]))
9661 emit_move_insn (adjust_address (operands[0], SImode, 0),
9662 adjust_address (operands[1], SImode, 0));
9663 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9664 adjust_address (copy_rtx (operands[1]), SImode, 4));
9668 if (can_create_pseudo_p () && MEM_P (operands[0])
9669 && !gpc_reg_operand (operands[1], mode))
9670 operands[1] = force_reg (mode, operands[1]);
9672 /* Recognize the case where operand[1] is a reference to thread-local
9673 data and load its address to a register. */
9674 if (tls_referenced_p (operands[1]))
9676 enum tls_model model;
9677 rtx tmp = operands[1];
9680 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9682 addend = XEXP (XEXP (tmp, 0), 1);
9683 tmp = XEXP (XEXP (tmp, 0), 0);
9686 gcc_assert (SYMBOL_REF_P (tmp));
9687 model = SYMBOL_REF_TLS_MODEL (tmp);
9688 gcc_assert (model != 0);
9690 tmp = rs6000_legitimize_tls_address (tmp, model);
9693 tmp = gen_rtx_PLUS (mode, tmp, addend);
9694 tmp = force_operand (tmp, operands[0]);
9699 /* 128-bit constant floating-point values on Darwin should really be loaded
9700 as two parts. However, this premature splitting is a problem when DFmode
9701 values can go into Altivec registers. */
9702 if (TARGET_MACHO && CONST_DOUBLE_P (operands[1]) && FLOAT128_IBM_P (mode)
9703 && !reg_addr[DFmode].scalar_in_vmx_p)
9705 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9706 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9708 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9709 GET_MODE_SIZE (DFmode)),
9710 simplify_gen_subreg (DFmode, operands[1], mode,
9711 GET_MODE_SIZE (DFmode)),
9716 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9717 p1:SD) if p1 is not of floating point class and p0 is spilled as
9718 we can have no analogous movsd_store for this. */
9719 if (lra_in_progress && mode == DDmode
9720 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9721 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9722 && SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))
9723 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9726 int regno = REGNO (SUBREG_REG (operands[1]));
9728 if (!HARD_REGISTER_NUM_P (regno))
9730 cl = reg_preferred_class (regno);
9731 regno = reg_renumber[regno];
9733 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9735 if (regno >= 0 && ! FP_REGNO_P (regno))
9738 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9739 operands[1] = SUBREG_REG (operands[1]);
9744 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9745 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9746 && (REG_P (operands[1])
9747 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))))
9749 int regno = reg_or_subregno (operands[1]);
9752 if (!HARD_REGISTER_NUM_P (regno))
9754 cl = reg_preferred_class (regno);
9755 gcc_assert (cl != NO_REGS);
9756 regno = reg_renumber[regno];
9758 regno = ira_class_hard_regs[cl][0];
9760 if (FP_REGNO_P (regno))
9762 if (GET_MODE (operands[0]) != DDmode)
9763 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
9764 emit_insn (gen_movsd_store (operands[0], operands[1]));
9766 else if (INT_REGNO_P (regno))
9767 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9772 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9773 p:DD)) if p0 is not of floating point class and p1 is spilled as
9774 we can have no analogous movsd_load for this. */
9775 if (lra_in_progress && mode == DDmode
9776 && SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))
9777 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
9778 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9779 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9782 int regno = REGNO (SUBREG_REG (operands[0]));
9784 if (!HARD_REGISTER_NUM_P (regno))
9786 cl = reg_preferred_class (regno);
9787 regno = reg_renumber[regno];
9789 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
9791 if (regno >= 0 && ! FP_REGNO_P (regno))
9794 operands[0] = SUBREG_REG (operands[0]);
9795 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
9800 && (REG_P (operands[0])
9801 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
9802 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9803 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9805 int regno = reg_or_subregno (operands[0]);
9808 if (!HARD_REGISTER_NUM_P (regno))
9810 cl = reg_preferred_class (regno);
9811 gcc_assert (cl != NO_REGS);
9812 regno = reg_renumber[regno];
9814 regno = ira_class_hard_regs[cl][0];
9816 if (FP_REGNO_P (regno))
9818 if (GET_MODE (operands[1]) != DDmode)
9819 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
9820 emit_insn (gen_movsd_load (operands[0], operands[1]));
9822 else if (INT_REGNO_P (regno))
9823 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9829 /* FIXME: In the long term, this switch statement should go away
9830 and be replaced by a sequence of tests based on things like
9836 if (CONSTANT_P (operands[1])
9837 && !CONST_INT_P (operands[1]))
9838 operands[1] = force_const_mem (mode, operands[1]);
9845 if (FLOAT128_2REG_P (mode))
9846 rs6000_eliminate_indexed_memrefs (operands);
9853 if (CONSTANT_P (operands[1])
9854 && ! easy_fp_constant (operands[1], mode))
9855 operands[1] = force_const_mem (mode, operands[1]);
9865 if (CONSTANT_P (operands[1])
9866 && !easy_vector_constant (operands[1], mode))
9867 operands[1] = force_const_mem (mode, operands[1]);
9872 /* Use default pattern for address of ELF small data */
9875 && DEFAULT_ABI == ABI_V4
9876 && (SYMBOL_REF_P (operands[1])
9877 || GET_CODE (operands[1]) == CONST)
9878 && small_data_operand (operands[1], mode))
9880 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9884 if (DEFAULT_ABI == ABI_V4
9885 && mode == Pmode && mode == SImode
9886 && flag_pic == 1 && got_operand (operands[1], mode))
9888 emit_insn (gen_movsi_got (operands[0], operands[1]));
9892 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
9896 && CONSTANT_P (operands[1])
9897 && GET_CODE (operands[1]) != HIGH
9898 && !CONST_INT_P (operands[1]))
9900 rtx target = (!can_create_pseudo_p ()
9902 : gen_reg_rtx (mode));
9904 /* If this is a function address on -mcall-aixdesc,
9905 convert it to the address of the descriptor. */
9906 if (DEFAULT_ABI == ABI_AIX
9907 && SYMBOL_REF_P (operands[1])
9908 && XSTR (operands[1], 0)[0] == '.')
9910 const char *name = XSTR (operands[1], 0);
9912 while (*name == '.')
9914 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
9915 CONSTANT_POOL_ADDRESS_P (new_ref)
9916 = CONSTANT_POOL_ADDRESS_P (operands[1]);
9917 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
9918 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
9919 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
9920 operands[1] = new_ref;
9923 if (DEFAULT_ABI == ABI_DARWIN)
9926 if (MACHO_DYNAMIC_NO_PIC_P)
9928 /* Take care of any required data indirection. */
9929 operands[1] = rs6000_machopic_legitimize_pic_address (
9930 operands[1], mode, operands[0]);
9931 if (operands[0] != operands[1])
9932 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9936 emit_insn (gen_macho_high (target, operands[1]));
9937 emit_insn (gen_macho_low (operands[0], target, operands[1]));
9941 emit_insn (gen_elf_high (target, operands[1]));
9942 emit_insn (gen_elf_low (operands[0], target, operands[1]));
9946 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9947 and we have put it in the TOC, we just need to make a TOC-relative
9950 && SYMBOL_REF_P (operands[1])
9951 && use_toc_relative_ref (operands[1], mode))
9952 operands[1] = create_TOC_reference (operands[1], operands[0]);
9953 else if (mode == Pmode
9954 && CONSTANT_P (operands[1])
9955 && GET_CODE (operands[1]) != HIGH
9956 && ((REG_P (operands[0])
9957 && FP_REGNO_P (REGNO (operands[0])))
9958 || !CONST_INT_P (operands[1])
9959 || (num_insns_constant (operands[1], mode)
9960 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
9961 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
9962 && (TARGET_CMODEL == CMODEL_SMALL
9963 || can_create_pseudo_p ()
9964 || (REG_P (operands[0])
9965 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
9969 /* Darwin uses a special PIC legitimizer. */
9970 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
9973 rs6000_machopic_legitimize_pic_address (operands[1], mode,
9975 if (operands[0] != operands[1])
9976 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9981 /* If we are to limit the number of things we put in the TOC and
9982 this is a symbol plus a constant we can add in one insn,
9983 just put the symbol in the TOC and add the constant. */
9984 if (GET_CODE (operands[1]) == CONST
9985 && TARGET_NO_SUM_IN_TOC
9986 && GET_CODE (XEXP (operands[1], 0)) == PLUS
9987 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
9988 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
9989 || SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
9990 && ! side_effects_p (operands[0]))
9993 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
9994 rtx other = XEXP (XEXP (operands[1], 0), 1);
9996 sym = force_reg (mode, sym);
9997 emit_insn (gen_add3_insn (operands[0], sym, other));
10001 operands[1] = force_const_mem (mode, operands[1]);
10004 && SYMBOL_REF_P (XEXP (operands[1], 0))
10005 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10007 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10009 operands[1] = gen_const_mem (mode, tocref);
10010 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10016 if (!VECTOR_MEM_VSX_P (TImode))
10017 rs6000_eliminate_indexed_memrefs (operands);
10021 rs6000_eliminate_indexed_memrefs (operands);
10025 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10028 /* Above, we may have called force_const_mem which may have returned
10029 an invalid address. If we can, fix this up; otherwise, reload will
10030 have to deal with it. */
10031 if (MEM_P (operands[1]))
10032 operands[1] = validize_mem (operands[1]);
10034 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10037 /* Nonzero if we can use a floating-point register to pass this arg. */
10038 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10039 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10040 && (CUM)->fregno <= FP_ARG_MAX_REG \
10041 && TARGET_HARD_FLOAT)
10043 /* Nonzero if we can use an AltiVec register to pass this arg. */
10044 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10045 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10046 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10047 && TARGET_ALTIVEC_ABI \
10050 /* Walk down the type tree of TYPE counting consecutive base elements.
10051 If *MODEP is VOIDmode, then set it to the first valid floating point
10052 or vector type. If a non-floating point or vector type is found, or
10053 if a floating point or vector type that doesn't match a non-VOIDmode
10054 *MODEP is found, then return -1, otherwise return the count in the
10058 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10061 HOST_WIDE_INT size;
10063 switch (TREE_CODE (type))
10066 mode = TYPE_MODE (type);
10067 if (!SCALAR_FLOAT_MODE_P (mode))
10070 if (*modep == VOIDmode)
10073 if (*modep == mode)
10079 mode = TYPE_MODE (TREE_TYPE (type));
10080 if (!SCALAR_FLOAT_MODE_P (mode))
10083 if (*modep == VOIDmode)
10086 if (*modep == mode)
10092 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10095 /* Use V4SImode as representative of all 128-bit vector types. */
10096 size = int_size_in_bytes (type);
10106 if (*modep == VOIDmode)
10109 /* Vector modes are considered to be opaque: two vectors are
10110 equivalent for the purposes of being homogeneous aggregates
10111 if they are the same size. */
10112 if (*modep == mode)
10120 tree index = TYPE_DOMAIN (type);
10122 /* Can't handle incomplete types nor sizes that are not
10124 if (!COMPLETE_TYPE_P (type)
10125 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10128 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10131 || !TYPE_MAX_VALUE (index)
10132 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10133 || !TYPE_MIN_VALUE (index)
10134 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10138 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10139 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10141 /* There must be no padding. */
10142 if (wi::to_wide (TYPE_SIZE (type))
10143 != count * GET_MODE_BITSIZE (*modep))
10155 /* Can't handle incomplete types nor sizes that are not
10157 if (!COMPLETE_TYPE_P (type)
10158 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10161 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10163 if (TREE_CODE (field) != FIELD_DECL)
10166 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10169 count += sub_count;
10172 /* There must be no padding. */
10173 if (wi::to_wide (TYPE_SIZE (type))
10174 != count * GET_MODE_BITSIZE (*modep))
10181 case QUAL_UNION_TYPE:
10183 /* These aren't very interesting except in a degenerate case. */
10188 /* Can't handle incomplete types nor sizes that are not
10190 if (!COMPLETE_TYPE_P (type)
10191 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10194 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10196 if (TREE_CODE (field) != FIELD_DECL)
10199 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10202 count = count > sub_count ? count : sub_count;
10205 /* There must be no padding. */
10206 if (wi::to_wide (TYPE_SIZE (type))
10207 != count * GET_MODE_BITSIZE (*modep))
10220 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10221 float or vector aggregate that shall be passed in FP/vector registers
10222 according to the ELFv2 ABI, return the homogeneous element mode in
10223 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10225 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10228 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10229 machine_mode *elt_mode,
10232 /* Note that we do not accept complex types at the top level as
10233 homogeneous aggregates; these types are handled via the
10234 targetm.calls.split_complex_arg mechanism. Complex types
10235 can be elements of homogeneous aggregates, however. */
10236 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10237 && AGGREGATE_TYPE_P (type))
10239 machine_mode field_mode = VOIDmode;
10240 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10242 if (field_count > 0)
10244 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10245 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10247 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10248 up to AGGR_ARG_NUM_REG registers. */
10249 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10252 *elt_mode = field_mode;
10254 *n_elts = field_count;
10267 /* Return a nonzero value to say to return the function value in
10268 memory, just as large structures are always returned. TYPE will be
10269 the data type of the value, and FNTYPE will be the type of the
10270 function doing the returning, or @code{NULL} for libcalls.
10272 The AIX ABI for the RS/6000 specifies that all structures are
10273 returned in memory. The Darwin ABI does the same.
10275 For the Darwin 64 Bit ABI, a function result can be returned in
10276 registers or in memory, depending on the size of the return data
10277 type. If it is returned in registers, the value occupies the same
10278 registers as it would if it were the first and only function
10279 argument. Otherwise, the function places its result in memory at
10280 the location pointed to by GPR3.
10282 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10283 but a draft put them in memory, and GCC used to implement the draft
10284 instead of the final standard. Therefore, aix_struct_return
10285 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10286 compatibility can change DRAFT_V4_STRUCT_RET to override the
10287 default, and -m switches get the final word. See
10288 rs6000_option_override_internal for more details.
10290 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10291 long double support is enabled. These values are returned in memory.
10293 int_size_in_bytes returns -1 for variable size objects, which go in
10294 memory always. The cast to unsigned makes -1 > 8. */
10297 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10299 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10301 && rs6000_darwin64_abi
10302 && TREE_CODE (type) == RECORD_TYPE
10303 && int_size_in_bytes (type) > 0)
10305 CUMULATIVE_ARGS valcum;
10309 valcum.fregno = FP_ARG_MIN_REG;
10310 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10311 /* Do a trial code generation as if this were going to be passed
10312 as an argument; if any part goes in memory, we return NULL. */
10313 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10316 /* Otherwise fall through to more conventional ABI rules. */
10319 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10320 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10324 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10325 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10326 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10329 if (AGGREGATE_TYPE_P (type)
10330 && (aix_struct_return
10331 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10334 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10335 modes only exist for GCC vector types if -maltivec. */
10336 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10337 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10340 /* Return synthetic vectors in memory. */
10341 if (TREE_CODE (type) == VECTOR_TYPE
10342 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10344 static bool warned_for_return_big_vectors = false;
10345 if (!warned_for_return_big_vectors)
10347 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10348 "non-standard ABI extension with no compatibility "
10350 warned_for_return_big_vectors = true;
10355 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10356 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10362 /* Specify whether values returned in registers should be at the most
10363 significant end of a register. We want aggregates returned by
10364 value to match the way aggregates are passed to functions. */
10367 rs6000_return_in_msb (const_tree valtype)
10369 return (DEFAULT_ABI == ABI_ELFv2
10370 && BYTES_BIG_ENDIAN
10371 && AGGREGATE_TYPE_P (valtype)
10372 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10376 #ifdef HAVE_AS_GNU_ATTRIBUTE
10377 /* Return TRUE if a call to function FNDECL may be one that
10378 potentially affects the function calling ABI of the object file. */
10381 call_ABI_of_interest (tree fndecl)
10383 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10385 struct cgraph_node *c_node;
10387 /* Libcalls are always interesting. */
10388 if (fndecl == NULL_TREE)
10391 /* Any call to an external function is interesting. */
10392 if (DECL_EXTERNAL (fndecl))
10395 /* Interesting functions that we are emitting in this object file. */
10396 c_node = cgraph_node::get (fndecl);
10397 c_node = c_node->ultimate_alias_target ();
10398 return !c_node->only_called_directly_p ();
10404 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10405 for a call to a function whose data type is FNTYPE.
10406 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10408 For incoming args we set the number of arguments in the prototype large
10409 so we never return a PARALLEL. */
10412 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10413 rtx libname ATTRIBUTE_UNUSED, int incoming,
10414 int libcall, int n_named_args,
10416 machine_mode return_mode ATTRIBUTE_UNUSED)
10418 static CUMULATIVE_ARGS zero_cumulative;
10420 *cum = zero_cumulative;
10422 cum->fregno = FP_ARG_MIN_REG;
10423 cum->vregno = ALTIVEC_ARG_MIN_REG;
10424 cum->prototype = (fntype && prototype_p (fntype));
10425 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10426 ? CALL_LIBCALL : CALL_NORMAL);
10427 cum->sysv_gregno = GP_ARG_MIN_REG;
10428 cum->stdarg = stdarg_p (fntype);
10429 cum->libcall = libcall;
10431 cum->nargs_prototype = 0;
10432 if (incoming || cum->prototype)
10433 cum->nargs_prototype = n_named_args;
10435 /* Check for a longcall attribute. */
10436 if ((!fntype && rs6000_default_long_calls)
10438 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10439 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10440 cum->call_cookie |= CALL_LONG;
10441 else if (DEFAULT_ABI != ABI_DARWIN)
10443 bool is_local = (fndecl
10444 && !DECL_EXTERNAL (fndecl)
10445 && !DECL_WEAK (fndecl)
10446 && (*targetm.binds_local_p) (fndecl));
10452 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
10453 cum->call_cookie |= CALL_LONG;
10458 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
10459 cum->call_cookie |= CALL_LONG;
10463 if (TARGET_DEBUG_ARG)
10465 fprintf (stderr, "\ninit_cumulative_args:");
10468 tree ret_type = TREE_TYPE (fntype);
10469 fprintf (stderr, " ret code = %s,",
10470 get_tree_code_name (TREE_CODE (ret_type)));
10473 if (cum->call_cookie & CALL_LONG)
10474 fprintf (stderr, " longcall,");
10476 fprintf (stderr, " proto = %d, nargs = %d\n",
10477 cum->prototype, cum->nargs_prototype);
10480 #ifdef HAVE_AS_GNU_ATTRIBUTE
10481 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10483 cum->escapes = call_ABI_of_interest (fndecl);
10490 return_type = TREE_TYPE (fntype);
10491 return_mode = TYPE_MODE (return_type);
10494 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10496 if (return_type != NULL)
10498 if (TREE_CODE (return_type) == RECORD_TYPE
10499 && TYPE_TRANSPARENT_AGGR (return_type))
10501 return_type = TREE_TYPE (first_field (return_type));
10502 return_mode = TYPE_MODE (return_type);
10504 if (AGGREGATE_TYPE_P (return_type)
10505 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10507 rs6000_returns_struct = true;
10509 if (SCALAR_FLOAT_MODE_P (return_mode))
10511 rs6000_passes_float = true;
10512 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10513 && (FLOAT128_IBM_P (return_mode)
10514 || FLOAT128_IEEE_P (return_mode)
10515 || (return_type != NULL
10516 && (TYPE_MAIN_VARIANT (return_type)
10517 == long_double_type_node))))
10518 rs6000_passes_long_double = true;
10520 /* Note if we passed or return a IEEE 128-bit type. We changed
10521 the mangling for these types, and we may need to make an alias
10522 with the old mangling. */
10523 if (FLOAT128_IEEE_P (return_mode))
10524 rs6000_passes_ieee128 = true;
10526 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10527 rs6000_passes_vector = true;
10534 && TARGET_ALTIVEC_ABI
10535 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10537 error ("cannot return value in vector register because"
10538 " altivec instructions are disabled, use %qs"
10539 " to enable them", "-maltivec");
10543 /* The mode the ABI uses for a word. This is not the same as word_mode
10544 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10546 static scalar_int_mode
10547 rs6000_abi_word_mode (void)
10549 return TARGET_32BIT ? SImode : DImode;
10552 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10554 rs6000_offload_options (void)
10557 return xstrdup ("-foffload-abi=lp64");
10559 return xstrdup ("-foffload-abi=ilp32");
10562 /* On rs6000, function arguments are promoted, as are function return
10565 static machine_mode
10566 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10568 int *punsignedp ATTRIBUTE_UNUSED,
10571 PROMOTE_MODE (mode, *punsignedp, type);
10576 /* Return true if TYPE must be passed on the stack and not in registers. */
10579 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10581 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10582 return must_pass_in_stack_var_size (mode, type);
10584 return must_pass_in_stack_var_size_or_pad (mode, type);
10588 is_complex_IBM_long_double (machine_mode mode)
10590 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10593 /* Whether ABI_V4 passes MODE args to a function in floating point
10597 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10599 if (!TARGET_HARD_FLOAT)
10601 if (mode == DFmode)
10603 if (mode == SFmode && named)
10605 /* ABI_V4 passes complex IBM long double in 8 gprs.
10606 Stupid, but we can't change the ABI now. */
10607 if (is_complex_IBM_long_double (mode))
10609 if (FLOAT128_2REG_P (mode))
10611 if (DECIMAL_FLOAT_MODE_P (mode))
10616 /* Implement TARGET_FUNCTION_ARG_PADDING.
10618 For the AIX ABI structs are always stored left shifted in their
10621 static pad_direction
10622 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10624 #ifndef AGGREGATE_PADDING_FIXED
10625 #define AGGREGATE_PADDING_FIXED 0
10627 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10628 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10631 if (!AGGREGATE_PADDING_FIXED)
10633 /* GCC used to pass structures of the same size as integer types as
10634 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10635 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10636 passed padded downward, except that -mstrict-align further
10637 muddied the water in that multi-component structures of 2 and 4
10638 bytes in size were passed padded upward.
10640 The following arranges for best compatibility with previous
10641 versions of gcc, but removes the -mstrict-align dependency. */
10642 if (BYTES_BIG_ENDIAN)
10644 HOST_WIDE_INT size = 0;
10646 if (mode == BLKmode)
10648 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10649 size = int_size_in_bytes (type);
10652 size = GET_MODE_SIZE (mode);
10654 if (size == 1 || size == 2 || size == 4)
10655 return PAD_DOWNWARD;
10660 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10662 if (type != 0 && AGGREGATE_TYPE_P (type))
10666 /* Fall back to the default. */
10667 return default_function_arg_padding (mode, type);
10670 /* If defined, a C expression that gives the alignment boundary, in bits,
10671 of an argument with the specified mode and type. If it is not defined,
10672 PARM_BOUNDARY is used for all arguments.
10674 V.4 wants long longs and doubles to be double word aligned. Just
10675 testing the mode size is a boneheaded way to do this as it means
10676 that other types such as complex int are also double word aligned.
10677 However, we're stuck with this because changing the ABI might break
10678 existing library interfaces.
10680 Quadword align Altivec/VSX vectors.
10681 Quadword align large synthetic vector types. */
10683 static unsigned int
10684 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10686 machine_mode elt_mode;
10689 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10691 if (DEFAULT_ABI == ABI_V4
10692 && (GET_MODE_SIZE (mode) == 8
10693 || (TARGET_HARD_FLOAT
10694 && !is_complex_IBM_long_double (mode)
10695 && FLOAT128_2REG_P (mode))))
10697 else if (FLOAT128_VECTOR_P (mode))
10699 else if (type && TREE_CODE (type) == VECTOR_TYPE
10700 && int_size_in_bytes (type) >= 8
10701 && int_size_in_bytes (type) < 16)
10703 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10704 || (type && TREE_CODE (type) == VECTOR_TYPE
10705 && int_size_in_bytes (type) >= 16))
10708 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10709 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10710 -mcompat-align-parm is used. */
10711 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10712 || DEFAULT_ABI == ABI_ELFv2)
10713 && type && TYPE_ALIGN (type) > 64)
10715 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10716 or homogeneous float/vector aggregates here. We already handled
10717 vector aggregates above, but still need to check for float here. */
10718 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10719 && !SCALAR_FLOAT_MODE_P (elt_mode));
10721 /* We used to check for BLKmode instead of the above aggregate type
10722 check. Warn when this results in any difference to the ABI. */
10723 if (aggregate_p != (mode == BLKmode))
10725 static bool warned;
10726 if (!warned && warn_psabi)
10729 inform (input_location,
10730 "the ABI of passing aggregates with %d-byte alignment"
10731 " has changed in GCC 5",
10732 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10740 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10741 implement the "aggregate type" check as a BLKmode check here; this
10742 means certain aggregate types are in fact not aligned. */
10743 if (TARGET_MACHO && rs6000_darwin64_abi
10745 && type && TYPE_ALIGN (type) > 64)
10748 return PARM_BOUNDARY;
10751 /* The offset in words to the start of the parameter save area. */
10753 static unsigned int
10754 rs6000_parm_offset (void)
10756 return (DEFAULT_ABI == ABI_V4 ? 2
10757 : DEFAULT_ABI == ABI_ELFv2 ? 4
10761 /* For a function parm of MODE and TYPE, return the starting word in
10762 the parameter area. NWORDS of the parameter area are already used. */
10764 static unsigned int
10765 rs6000_parm_start (machine_mode mode, const_tree type,
10766 unsigned int nwords)
10768 unsigned int align;
10770 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
10771 return nwords + (-(rs6000_parm_offset () + nwords) & align);
10774 /* Compute the size (in words) of a function argument. */
10776 static unsigned long
10777 rs6000_arg_size (machine_mode mode, const_tree type)
10779 unsigned long size;
10781 if (mode != BLKmode)
10782 size = GET_MODE_SIZE (mode);
10784 size = int_size_in_bytes (type);
10787 return (size + 3) >> 2;
10789 return (size + 7) >> 3;
10792 /* Use this to flush pending int fields. */
10795 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
10796 HOST_WIDE_INT bitpos, int final)
10798 unsigned int startbit, endbit;
10799 int intregs, intoffset;
10801 /* Handle the situations where a float is taking up the first half
10802 of the GPR, and the other half is empty (typically due to
10803 alignment restrictions). We can detect this by a 8-byte-aligned
10804 int field, or by seeing that this is the final flush for this
10805 argument. Count the word and continue on. */
10806 if (cum->floats_in_gpr == 1
10807 && (cum->intoffset % 64 == 0
10808 || (cum->intoffset == -1 && final)))
10811 cum->floats_in_gpr = 0;
10814 if (cum->intoffset == -1)
10817 intoffset = cum->intoffset;
10818 cum->intoffset = -1;
10819 cum->floats_in_gpr = 0;
10821 if (intoffset % BITS_PER_WORD != 0)
10823 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
10824 if (!int_mode_for_size (bits, 0).exists ())
10826 /* We couldn't find an appropriate mode, which happens,
10827 e.g., in packed structs when there are 3 bytes to load.
10828 Back intoffset back to the beginning of the word in this
10830 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
10834 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
10835 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
10836 intregs = (endbit - startbit) / BITS_PER_WORD;
10837 cum->words += intregs;
10838 /* words should be unsigned. */
10839 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
10841 int pad = (endbit/BITS_PER_WORD) - cum->words;
10846 /* The darwin64 ABI calls for us to recurse down through structs,
10847 looking for elements passed in registers. Unfortunately, we have
10848 to track int register count here also because of misalignments
10849 in powerpc alignment mode. */
10852 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
10854 HOST_WIDE_INT startbitpos)
10858 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10859 if (TREE_CODE (f) == FIELD_DECL)
10861 HOST_WIDE_INT bitpos = startbitpos;
10862 tree ftype = TREE_TYPE (f);
10864 if (ftype == error_mark_node)
10866 mode = TYPE_MODE (ftype);
10868 if (DECL_SIZE (f) != 0
10869 && tree_fits_uhwi_p (bit_position (f)))
10870 bitpos += int_bit_position (f);
10872 /* ??? FIXME: else assume zero offset. */
10874 if (TREE_CODE (ftype) == RECORD_TYPE)
10875 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
10876 else if (USE_FP_FOR_ARG_P (cum, mode))
10878 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
10879 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10880 cum->fregno += n_fpregs;
10881 /* Single-precision floats present a special problem for
10882 us, because they are smaller than an 8-byte GPR, and so
10883 the structure-packing rules combined with the standard
10884 varargs behavior mean that we want to pack float/float
10885 and float/int combinations into a single register's
10886 space. This is complicated by the arg advance flushing,
10887 which works on arbitrarily large groups of int-type
10889 if (mode == SFmode)
10891 if (cum->floats_in_gpr == 1)
10893 /* Two floats in a word; count the word and reset
10894 the float count. */
10896 cum->floats_in_gpr = 0;
10898 else if (bitpos % 64 == 0)
10900 /* A float at the beginning of an 8-byte word;
10901 count it and put off adjusting cum->words until
10902 we see if a arg advance flush is going to do it
10904 cum->floats_in_gpr++;
10908 /* The float is at the end of a word, preceded
10909 by integer fields, so the arg advance flush
10910 just above has already set cum->words and
10911 everything is taken care of. */
10915 cum->words += n_fpregs;
10917 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10919 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10923 else if (cum->intoffset == -1)
10924 cum->intoffset = bitpos;
10928 /* Check for an item that needs to be considered specially under the darwin 64
10929 bit ABI. These are record types where the mode is BLK or the structure is
10930 8 bytes in size. */
10932 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
10934 return rs6000_darwin64_abi
10935 && ((mode == BLKmode
10936 && TREE_CODE (type) == RECORD_TYPE
10937 && int_size_in_bytes (type) > 0)
10938 || (type && TREE_CODE (type) == RECORD_TYPE
10939 && int_size_in_bytes (type) == 8)) ? 1 : 0;
10942 /* Update the data in CUM to advance over an argument
10943 of mode MODE and data type TYPE.
10944 (TYPE is null for libcalls where that information may not be available.)
10946 Note that for args passed by reference, function_arg will be called
10947 with MODE and TYPE set to that of the pointer to the arg, not the arg
10951 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
10952 const_tree type, bool named, int depth)
10954 machine_mode elt_mode;
10957 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10959 /* Only tick off an argument if we're not recursing. */
10961 cum->nargs_prototype--;
10963 #ifdef HAVE_AS_GNU_ATTRIBUTE
10964 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
10967 if (SCALAR_FLOAT_MODE_P (mode))
10969 rs6000_passes_float = true;
10970 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10971 && (FLOAT128_IBM_P (mode)
10972 || FLOAT128_IEEE_P (mode)
10974 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
10975 rs6000_passes_long_double = true;
10977 /* Note if we passed or return a IEEE 128-bit type. We changed the
10978 mangling for these types, and we may need to make an alias with
10979 the old mangling. */
10980 if (FLOAT128_IEEE_P (mode))
10981 rs6000_passes_ieee128 = true;
10983 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
10984 rs6000_passes_vector = true;
10988 if (TARGET_ALTIVEC_ABI
10989 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10990 || (type && TREE_CODE (type) == VECTOR_TYPE
10991 && int_size_in_bytes (type) == 16)))
10993 bool stack = false;
10995 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10997 cum->vregno += n_elts;
10999 if (!TARGET_ALTIVEC)
11000 error ("cannot pass argument in vector register because"
11001 " altivec instructions are disabled, use %qs"
11002 " to enable them", "-maltivec");
11004 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11005 even if it is going to be passed in a vector register.
11006 Darwin does the same for variable-argument functions. */
11007 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11009 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11019 /* Vector parameters must be 16-byte aligned. In 32-bit
11020 mode this means we need to take into account the offset
11021 to the parameter save area. In 64-bit mode, they just
11022 have to start on an even word, since the parameter save
11023 area is 16-byte aligned. */
11025 align = -(rs6000_parm_offset () + cum->words) & 3;
11027 align = cum->words & 1;
11028 cum->words += align + rs6000_arg_size (mode, type);
11030 if (TARGET_DEBUG_ARG)
11032 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11033 cum->words, align);
11034 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11035 cum->nargs_prototype, cum->prototype,
11036 GET_MODE_NAME (mode));
11040 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11042 int size = int_size_in_bytes (type);
11043 /* Variable sized types have size == -1 and are
11044 treated as if consisting entirely of ints.
11045 Pad to 16 byte boundary if needed. */
11046 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11047 && (cum->words % 2) != 0)
11049 /* For varargs, we can just go up by the size of the struct. */
11051 cum->words += (size + 7) / 8;
11054 /* It is tempting to say int register count just goes up by
11055 sizeof(type)/8, but this is wrong in a case such as
11056 { int; double; int; } [powerpc alignment]. We have to
11057 grovel through the fields for these too. */
11058 cum->intoffset = 0;
11059 cum->floats_in_gpr = 0;
11060 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11061 rs6000_darwin64_record_arg_advance_flush (cum,
11062 size * BITS_PER_UNIT, 1);
11064 if (TARGET_DEBUG_ARG)
11066 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11067 cum->words, TYPE_ALIGN (type), size);
11069 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11070 cum->nargs_prototype, cum->prototype,
11071 GET_MODE_NAME (mode));
11074 else if (DEFAULT_ABI == ABI_V4)
11076 if (abi_v4_pass_in_fpr (mode, named))
11078 /* _Decimal128 must use an even/odd register pair. This assumes
11079 that the register number is odd when fregno is odd. */
11080 if (mode == TDmode && (cum->fregno % 2) == 1)
11083 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11084 <= FP_ARG_V4_MAX_REG)
11085 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11088 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11089 if (mode == DFmode || FLOAT128_IBM_P (mode)
11090 || mode == DDmode || mode == TDmode)
11091 cum->words += cum->words & 1;
11092 cum->words += rs6000_arg_size (mode, type);
11097 int n_words = rs6000_arg_size (mode, type);
11098 int gregno = cum->sysv_gregno;
11100 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11101 As does any other 2 word item such as complex int due to a
11102 historical mistake. */
11104 gregno += (1 - gregno) & 1;
11106 /* Multi-reg args are not split between registers and stack. */
11107 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11109 /* Long long is aligned on the stack. So are other 2 word
11110 items such as complex int due to a historical mistake. */
11112 cum->words += cum->words & 1;
11113 cum->words += n_words;
11116 /* Note: continuing to accumulate gregno past when we've started
11117 spilling to the stack indicates the fact that we've started
11118 spilling to the stack to expand_builtin_saveregs. */
11119 cum->sysv_gregno = gregno + n_words;
11122 if (TARGET_DEBUG_ARG)
11124 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11125 cum->words, cum->fregno);
11126 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11127 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11128 fprintf (stderr, "mode = %4s, named = %d\n",
11129 GET_MODE_NAME (mode), named);
11134 int n_words = rs6000_arg_size (mode, type);
11135 int start_words = cum->words;
11136 int align_words = rs6000_parm_start (mode, type, start_words);
11138 cum->words = align_words + n_words;
11140 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11142 /* _Decimal128 must be passed in an even/odd float register pair.
11143 This assumes that the register number is odd when fregno is
11145 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11147 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11150 if (TARGET_DEBUG_ARG)
11152 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11153 cum->words, cum->fregno);
11154 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11155 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11156 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11157 named, align_words - start_words, depth);
11163 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11164 const_tree type, bool named)
11166 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11170 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11171 structure between cum->intoffset and bitpos to integer registers. */
11174 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11175 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11178 unsigned int regno;
11179 unsigned int startbit, endbit;
11180 int this_regno, intregs, intoffset;
11183 if (cum->intoffset == -1)
11186 intoffset = cum->intoffset;
11187 cum->intoffset = -1;
11189 /* If this is the trailing part of a word, try to only load that
11190 much into the register. Otherwise load the whole register. Note
11191 that in the latter case we may pick up unwanted bits. It's not a
11192 problem at the moment but may wish to revisit. */
11194 if (intoffset % BITS_PER_WORD != 0)
11196 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11197 if (!int_mode_for_size (bits, 0).exists (&mode))
11199 /* We couldn't find an appropriate mode, which happens,
11200 e.g., in packed structs when there are 3 bytes to load.
11201 Back intoffset back to the beginning of the word in this
11203 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11210 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11211 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11212 intregs = (endbit - startbit) / BITS_PER_WORD;
11213 this_regno = cum->words + intoffset / BITS_PER_WORD;
11215 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11216 cum->use_stack = 1;
11218 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11222 intoffset /= BITS_PER_UNIT;
11225 regno = GP_ARG_MIN_REG + this_regno;
11226 reg = gen_rtx_REG (mode, regno);
11228 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11231 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11235 while (intregs > 0);
11238 /* Recursive workhorse for the following. */
11241 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11242 HOST_WIDE_INT startbitpos, rtx rvec[],
11247 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11248 if (TREE_CODE (f) == FIELD_DECL)
11250 HOST_WIDE_INT bitpos = startbitpos;
11251 tree ftype = TREE_TYPE (f);
11253 if (ftype == error_mark_node)
11255 mode = TYPE_MODE (ftype);
11257 if (DECL_SIZE (f) != 0
11258 && tree_fits_uhwi_p (bit_position (f)))
11259 bitpos += int_bit_position (f);
11261 /* ??? FIXME: else assume zero offset. */
11263 if (TREE_CODE (ftype) == RECORD_TYPE)
11264 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11265 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11267 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11271 case E_SCmode: mode = SFmode; break;
11272 case E_DCmode: mode = DFmode; break;
11273 case E_TCmode: mode = TFmode; break;
11277 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11278 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11280 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11281 && (mode == TFmode || mode == TDmode));
11282 /* Long double or _Decimal128 split over regs and memory. */
11283 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11287 = gen_rtx_EXPR_LIST (VOIDmode,
11288 gen_rtx_REG (mode, cum->fregno++),
11289 GEN_INT (bitpos / BITS_PER_UNIT));
11290 if (FLOAT128_2REG_P (mode))
11293 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11295 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11297 = gen_rtx_EXPR_LIST (VOIDmode,
11298 gen_rtx_REG (mode, cum->vregno++),
11299 GEN_INT (bitpos / BITS_PER_UNIT));
11301 else if (cum->intoffset == -1)
11302 cum->intoffset = bitpos;
11306 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11307 the register(s) to be used for each field and subfield of a struct
11308 being passed by value, along with the offset of where the
11309 register's value may be found in the block. FP fields go in FP
11310 register, vector fields go in vector registers, and everything
11311 else goes in int registers, packed as in memory.
11313 This code is also used for function return values. RETVAL indicates
11314 whether this is the case.
11316 Much of this is taken from the SPARC V9 port, which has a similar
11317 calling convention. */
11320 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11321 bool named, bool retval)
11323 rtx rvec[FIRST_PSEUDO_REGISTER];
11324 int k = 1, kbase = 1;
11325 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11326 /* This is a copy; modifications are not visible to our caller. */
11327 CUMULATIVE_ARGS copy_cum = *orig_cum;
11328 CUMULATIVE_ARGS *cum = ©_cum;
11330 /* Pad to 16 byte boundary if needed. */
11331 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11332 && (cum->words % 2) != 0)
11335 cum->intoffset = 0;
11336 cum->use_stack = 0;
11337 cum->named = named;
11339 /* Put entries into rvec[] for individual FP and vector fields, and
11340 for the chunks of memory that go in int regs. Note we start at
11341 element 1; 0 is reserved for an indication of using memory, and
11342 may or may not be filled in below. */
11343 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11344 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11346 /* If any part of the struct went on the stack put all of it there.
11347 This hack is because the generic code for
11348 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11349 parts of the struct are not at the beginning. */
11350 if (cum->use_stack)
11353 return NULL_RTX; /* doesn't go in registers at all */
11355 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11357 if (k > 1 || cum->use_stack)
11358 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11363 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11366 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11371 rtx rvec[GP_ARG_NUM_REG + 1];
11373 if (align_words >= GP_ARG_NUM_REG)
11376 n_units = rs6000_arg_size (mode, type);
11378 /* Optimize the simple case where the arg fits in one gpr, except in
11379 the case of BLKmode due to assign_parms assuming that registers are
11380 BITS_PER_WORD wide. */
11382 || (n_units == 1 && mode != BLKmode))
11383 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11386 if (align_words + n_units > GP_ARG_NUM_REG)
11387 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11388 using a magic NULL_RTX component.
11389 This is not strictly correct. Only some of the arg belongs in
11390 memory, not all of it. However, the normal scheme using
11391 function_arg_partial_nregs can result in unusual subregs, eg.
11392 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11393 store the whole arg to memory is often more efficient than code
11394 to store pieces, and we know that space is available in the right
11395 place for the whole arg. */
11396 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11401 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11402 rtx off = GEN_INT (i++ * 4);
11403 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11405 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11407 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11410 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11411 but must also be copied into the parameter save area starting at
11412 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11413 to the GPRs and/or memory. Return the number of elements used. */
11416 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11417 int align_words, rtx *rvec)
11421 if (align_words < GP_ARG_NUM_REG)
11423 int n_words = rs6000_arg_size (mode, type);
11425 if (align_words + n_words > GP_ARG_NUM_REG
11427 || (TARGET_32BIT && TARGET_POWERPC64))
11429 /* If this is partially on the stack, then we only
11430 include the portion actually in registers here. */
11431 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11434 if (align_words + n_words > GP_ARG_NUM_REG)
11436 /* Not all of the arg fits in gprs. Say that it goes in memory
11437 too, using a magic NULL_RTX component. Also see comment in
11438 rs6000_mixed_function_arg for why the normal
11439 function_arg_partial_nregs scheme doesn't work in this case. */
11440 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11445 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11446 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11447 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11449 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11453 /* The whole arg fits in gprs. */
11454 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11455 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11460 /* It's entirely in memory. */
11461 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11467 /* RVEC is a vector of K components of an argument of mode MODE.
11468 Construct the final function_arg return value from it. */
11471 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11473 gcc_assert (k >= 1);
11475 /* Avoid returning a PARALLEL in the trivial cases. */
11478 if (XEXP (rvec[0], 0) == NULL_RTX)
11481 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11482 return XEXP (rvec[0], 0);
11485 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11488 /* Determine where to put an argument to a function.
11489 Value is zero to push the argument on the stack,
11490 or a hard register in which to store the argument.
11492 MODE is the argument's machine mode.
11493 TYPE is the data type of the argument (as a tree).
11494 This is null for libcalls where that information may
11496 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11497 the preceding args and about the function being called. It is
11498 not modified in this routine.
11499 NAMED is nonzero if this argument is a named parameter
11500 (otherwise it is an extra parameter matching an ellipsis).
11502 On RS/6000 the first eight words of non-FP are normally in registers
11503 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11504 Under V.4, the first 8 FP args are in registers.
11506 If this is floating-point and no prototype is specified, we use
11507 both an FP and integer register (or possibly FP reg and stack). Library
11508 functions (when CALL_LIBCALL is set) always have the proper types for args,
11509 so we can pass the FP value just in one register. emit_library_function
11510 doesn't support PARALLEL anyway.
11512 Note that for args passed by reference, function_arg will be called
11513 with MODE and TYPE set to that of the pointer to the arg, not the arg
11517 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11518 const_tree type, bool named)
11520 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11521 enum rs6000_abi abi = DEFAULT_ABI;
11522 machine_mode elt_mode;
11525 /* Return a marker to indicate whether CR1 needs to set or clear the
11526 bit that V.4 uses to say fp args were passed in registers.
11527 Assume that we don't need the marker for software floating point,
11528 or compiler generated library calls. */
11529 if (mode == VOIDmode)
11532 && (cum->call_cookie & CALL_LIBCALL) == 0
11534 || (cum->nargs_prototype < 0
11535 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11536 && TARGET_HARD_FLOAT)
11537 return GEN_INT (cum->call_cookie
11538 | ((cum->fregno == FP_ARG_MIN_REG)
11539 ? CALL_V4_SET_FP_ARGS
11540 : CALL_V4_CLEAR_FP_ARGS));
11542 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11545 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11547 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11549 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11550 if (rslt != NULL_RTX)
11552 /* Else fall through to usual handling. */
11555 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11557 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11561 /* Do we also need to pass this argument in the parameter save area?
11562 Library support functions for IEEE 128-bit are assumed to not need the
11563 value passed both in GPRs and in vector registers. */
11564 if (TARGET_64BIT && !cum->prototype
11565 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11567 int align_words = ROUND_UP (cum->words, 2);
11568 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11571 /* Describe where this argument goes in the vector registers. */
11572 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11574 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11575 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11576 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11579 return rs6000_finish_function_arg (mode, rvec, k);
11581 else if (TARGET_ALTIVEC_ABI
11582 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11583 || (type && TREE_CODE (type) == VECTOR_TYPE
11584 && int_size_in_bytes (type) == 16)))
11586 if (named || abi == ABI_V4)
11590 /* Vector parameters to varargs functions under AIX or Darwin
11591 get passed in memory and possibly also in GPRs. */
11592 int align, align_words, n_words;
11593 machine_mode part_mode;
11595 /* Vector parameters must be 16-byte aligned. In 32-bit
11596 mode this means we need to take into account the offset
11597 to the parameter save area. In 64-bit mode, they just
11598 have to start on an even word, since the parameter save
11599 area is 16-byte aligned. */
11601 align = -(rs6000_parm_offset () + cum->words) & 3;
11603 align = cum->words & 1;
11604 align_words = cum->words + align;
11606 /* Out of registers? Memory, then. */
11607 if (align_words >= GP_ARG_NUM_REG)
11610 if (TARGET_32BIT && TARGET_POWERPC64)
11611 return rs6000_mixed_function_arg (mode, type, align_words);
11613 /* The vector value goes in GPRs. Only the part of the
11614 value in GPRs is reported here. */
11616 n_words = rs6000_arg_size (mode, type);
11617 if (align_words + n_words > GP_ARG_NUM_REG)
11618 /* Fortunately, there are only two possibilities, the value
11619 is either wholly in GPRs or half in GPRs and half not. */
11620 part_mode = DImode;
11622 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11626 else if (abi == ABI_V4)
11628 if (abi_v4_pass_in_fpr (mode, named))
11630 /* _Decimal128 must use an even/odd register pair. This assumes
11631 that the register number is odd when fregno is odd. */
11632 if (mode == TDmode && (cum->fregno % 2) == 1)
11635 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11636 <= FP_ARG_V4_MAX_REG)
11637 return gen_rtx_REG (mode, cum->fregno);
11643 int n_words = rs6000_arg_size (mode, type);
11644 int gregno = cum->sysv_gregno;
11646 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11647 As does any other 2 word item such as complex int due to a
11648 historical mistake. */
11650 gregno += (1 - gregno) & 1;
11652 /* Multi-reg args are not split between registers and stack. */
11653 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11656 if (TARGET_32BIT && TARGET_POWERPC64)
11657 return rs6000_mixed_function_arg (mode, type,
11658 gregno - GP_ARG_MIN_REG);
11659 return gen_rtx_REG (mode, gregno);
11664 int align_words = rs6000_parm_start (mode, type, cum->words);
11666 /* _Decimal128 must be passed in an even/odd float register pair.
11667 This assumes that the register number is odd when fregno is odd. */
11668 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11671 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11672 && !(TARGET_AIX && !TARGET_ELF
11673 && type != NULL && AGGREGATE_TYPE_P (type)))
11675 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11678 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11681 /* Do we also need to pass this argument in the parameter
11683 if (type && (cum->nargs_prototype <= 0
11684 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11685 && TARGET_XL_COMPAT
11686 && align_words >= GP_ARG_NUM_REG)))
11687 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11689 /* Describe where this argument goes in the fprs. */
11690 for (i = 0; i < n_elts
11691 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11693 /* Check if the argument is split over registers and memory.
11694 This can only ever happen for long double or _Decimal128;
11695 complex types are handled via split_complex_arg. */
11696 machine_mode fmode = elt_mode;
11697 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11699 gcc_assert (FLOAT128_2REG_P (fmode));
11700 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11703 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11704 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11705 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11708 /* If there were not enough FPRs to hold the argument, the rest
11709 usually goes into memory. However, if the current position
11710 is still within the register parameter area, a portion may
11711 actually have to go into GPRs.
11713 Note that it may happen that the portion of the argument
11714 passed in the first "half" of the first GPR was already
11715 passed in the last FPR as well.
11717 For unnamed arguments, we already set up GPRs to cover the
11718 whole argument in rs6000_psave_function_arg, so there is
11719 nothing further to do at this point. */
11720 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11721 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11722 && cum->nargs_prototype > 0)
11724 static bool warned;
11726 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11727 int n_words = rs6000_arg_size (mode, type);
11729 align_words += fpr_words;
11730 n_words -= fpr_words;
11734 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11735 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11736 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11738 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11740 if (!warned && warn_psabi)
11743 inform (input_location,
11744 "the ABI of passing homogeneous %<float%> aggregates"
11745 " has changed in GCC 5");
11749 return rs6000_finish_function_arg (mode, rvec, k);
11751 else if (align_words < GP_ARG_NUM_REG)
11753 if (TARGET_32BIT && TARGET_POWERPC64)
11754 return rs6000_mixed_function_arg (mode, type, align_words);
11756 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11763 /* For an arg passed partly in registers and partly in memory, this is
11764 the number of bytes passed in registers. For args passed entirely in
11765 registers or entirely in memory, zero. When an arg is described by a
11766 PARALLEL, perhaps using more than one register type, this function
11767 returns the number of bytes used by the first element of the PARALLEL. */
11770 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11771 tree type, bool named)
11773 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11774 bool passed_in_gprs = true;
11777 machine_mode elt_mode;
11780 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11782 if (DEFAULT_ABI == ABI_V4)
11785 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11787 /* If we are passing this arg in the fixed parameter save area (gprs or
11788 memory) as well as VRs, we do not use the partial bytes mechanism;
11789 instead, rs6000_function_arg will return a PARALLEL including a memory
11790 element as necessary. Library support functions for IEEE 128-bit are
11791 assumed to not need the value passed both in GPRs and in vector
11793 if (TARGET_64BIT && !cum->prototype
11794 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11797 /* Otherwise, we pass in VRs only. Check for partial copies. */
11798 passed_in_gprs = false;
11799 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
11800 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
11803 /* In this complicated case we just disable the partial_nregs code. */
11804 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11807 align_words = rs6000_parm_start (mode, type, cum->words);
11809 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11810 && !(TARGET_AIX && !TARGET_ELF
11811 && type != NULL && AGGREGATE_TYPE_P (type)))
11813 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11815 /* If we are passing this arg in the fixed parameter save area
11816 (gprs or memory) as well as FPRs, we do not use the partial
11817 bytes mechanism; instead, rs6000_function_arg will return a
11818 PARALLEL including a memory element as necessary. */
11820 && (cum->nargs_prototype <= 0
11821 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11822 && TARGET_XL_COMPAT
11823 && align_words >= GP_ARG_NUM_REG)))
11826 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11827 passed_in_gprs = false;
11828 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
11830 /* Compute number of bytes / words passed in FPRs. If there
11831 is still space available in the register parameter area
11832 *after* that amount, a part of the argument will be passed
11833 in GPRs. In that case, the total amount passed in any
11834 registers is equal to the amount that would have been passed
11835 in GPRs if everything were passed there, so we fall back to
11836 the GPR code below to compute the appropriate value. */
11837 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
11838 * MIN (8, GET_MODE_SIZE (elt_mode)));
11839 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
11841 if (align_words + fpr_words < GP_ARG_NUM_REG)
11842 passed_in_gprs = true;
11849 && align_words < GP_ARG_NUM_REG
11850 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
11851 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
11853 if (ret != 0 && TARGET_DEBUG_ARG)
11854 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
11859 /* A C expression that indicates when an argument must be passed by
11860 reference. If nonzero for an argument, a copy of that argument is
11861 made in memory and a pointer to the argument is passed instead of
11862 the argument itself. The pointer is passed in whatever way is
11863 appropriate for passing a pointer to that type.
11865 Under V.4, aggregates and long double are passed by reference.
11867 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11868 reference unless the AltiVec vector extension ABI is in force.
11870 As an extension to all ABIs, variable sized types are passed by
11874 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
11875 machine_mode mode, const_tree type,
11876 bool named ATTRIBUTE_UNUSED)
11881 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11882 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11884 if (TARGET_DEBUG_ARG)
11885 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11889 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
11891 if (TARGET_DEBUG_ARG)
11892 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
11896 if (int_size_in_bytes (type) < 0)
11898 if (TARGET_DEBUG_ARG)
11899 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
11903 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11904 modes only exist for GCC vector types if -maltivec. */
11905 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11907 if (TARGET_DEBUG_ARG)
11908 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
11912 /* Pass synthetic vectors in memory. */
11913 if (TREE_CODE (type) == VECTOR_TYPE
11914 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11916 static bool warned_for_pass_big_vectors = false;
11917 if (TARGET_DEBUG_ARG)
11918 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
11919 if (!warned_for_pass_big_vectors)
11921 warning (OPT_Wpsabi, "GCC vector passed by reference: "
11922 "non-standard ABI extension with no compatibility "
11924 warned_for_pass_big_vectors = true;
11932 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11933 already processes. Return true if the parameter must be passed
11934 (fully or partially) on the stack. */
11937 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
11943 /* Catch errors. */
11944 if (type == NULL || type == error_mark_node)
11947 /* Handle types with no storage requirement. */
11948 if (TYPE_MODE (type) == VOIDmode)
11951 /* Handle complex types. */
11952 if (TREE_CODE (type) == COMPLEX_TYPE)
11953 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
11954 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
11956 /* Handle transparent aggregates. */
11957 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
11958 && TYPE_TRANSPARENT_AGGR (type))
11959 type = TREE_TYPE (first_field (type));
11961 /* See if this arg was passed by invisible reference. */
11962 if (pass_by_reference (get_cumulative_args (args_so_far),
11963 TYPE_MODE (type), type, true))
11964 type = build_pointer_type (type);
11966 /* Find mode as it is passed by the ABI. */
11967 unsignedp = TYPE_UNSIGNED (type);
11968 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
11970 /* If we must pass in stack, we need a stack. */
11971 if (rs6000_must_pass_in_stack (mode, type))
11974 /* If there is no incoming register, we need a stack. */
11975 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
11976 if (entry_parm == NULL)
11979 /* Likewise if we need to pass both in registers and on the stack. */
11980 if (GET_CODE (entry_parm) == PARALLEL
11981 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
11984 /* Also true if we're partially in registers and partially not. */
11985 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
11988 /* Update info on where next arg arrives in registers. */
11989 rs6000_function_arg_advance (args_so_far, mode, type, true);
11993 /* Return true if FUN has no prototype, has a variable argument
11994 list, or passes any parameter in memory. */
11997 rs6000_function_parms_need_stack (tree fun, bool incoming)
11999 tree fntype, result;
12000 CUMULATIVE_ARGS args_so_far_v;
12001 cumulative_args_t args_so_far;
12004 /* Must be a libcall, all of which only use reg parms. */
12009 fntype = TREE_TYPE (fun);
12011 /* Varargs functions need the parameter save area. */
12012 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12015 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12016 args_so_far = pack_cumulative_args (&args_so_far_v);
12018 /* When incoming, we will have been passed the function decl.
12019 It is necessary to use the decl to handle K&R style functions,
12020 where TYPE_ARG_TYPES may not be available. */
12023 gcc_assert (DECL_P (fun));
12024 result = DECL_RESULT (fun);
12027 result = TREE_TYPE (fntype);
12029 if (result && aggregate_value_p (result, fntype))
12031 if (!TYPE_P (result))
12032 result = TREE_TYPE (result);
12033 result = build_pointer_type (result);
12034 rs6000_parm_needs_stack (args_so_far, result);
12041 for (parm = DECL_ARGUMENTS (fun);
12042 parm && parm != void_list_node;
12043 parm = TREE_CHAIN (parm))
12044 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12049 function_args_iterator args_iter;
12052 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12053 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12060 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12061 usually a constant depending on the ABI. However, in the ELFv2 ABI
12062 the register parameter area is optional when calling a function that
12063 has a prototype is scope, has no variable argument list, and passes
12064 all parameters in registers. */
12067 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12069 int reg_parm_stack_space;
12071 switch (DEFAULT_ABI)
12074 reg_parm_stack_space = 0;
12079 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12083 /* ??? Recomputing this every time is a bit expensive. Is there
12084 a place to cache this information? */
12085 if (rs6000_function_parms_need_stack (fun, incoming))
12086 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12088 reg_parm_stack_space = 0;
12092 return reg_parm_stack_space;
12096 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12099 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12104 for (i = 0; i < nregs; i++)
12106 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12107 if (reload_completed)
12109 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12112 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12113 i * GET_MODE_SIZE (reg_mode));
12116 tem = replace_equiv_address (tem, XEXP (tem, 0));
12120 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12124 /* Perform any needed actions needed for a function that is receiving a
12125 variable number of arguments.
12129 MODE and TYPE are the mode and type of the current parameter.
12131 PRETEND_SIZE is a variable that should be set to the amount of stack
12132 that must be pushed by the prolog to pretend that our caller pushed
12135 Normally, this macro will push all remaining incoming registers on the
12136 stack and set PRETEND_SIZE to the length of the registers pushed. */
12139 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12140 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12143 CUMULATIVE_ARGS next_cum;
12144 int reg_size = TARGET_32BIT ? 4 : 8;
12145 rtx save_area = NULL_RTX, mem;
12146 int first_reg_offset;
12147 alias_set_type set;
12149 /* Skip the last named argument. */
12150 next_cum = *get_cumulative_args (cum);
12151 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12153 if (DEFAULT_ABI == ABI_V4)
12155 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12159 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12160 HOST_WIDE_INT offset = 0;
12162 /* Try to optimize the size of the varargs save area.
12163 The ABI requires that ap.reg_save_area is doubleword
12164 aligned, but we don't need to allocate space for all
12165 the bytes, only those to which we actually will save
12167 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12168 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12169 if (TARGET_HARD_FLOAT
12170 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12171 && cfun->va_list_fpr_size)
12174 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12175 * UNITS_PER_FP_WORD;
12176 if (cfun->va_list_fpr_size
12177 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12178 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12180 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12181 * UNITS_PER_FP_WORD;
12185 offset = -((first_reg_offset * reg_size) & ~7);
12186 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12188 gpr_reg_num = cfun->va_list_gpr_size;
12189 if (reg_size == 4 && (first_reg_offset & 1))
12192 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12195 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12196 * UNITS_PER_FP_WORD
12197 - (int) (GP_ARG_NUM_REG * reg_size);
12199 if (gpr_size + fpr_size)
12202 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12203 gcc_assert (MEM_P (reg_save_area));
12204 reg_save_area = XEXP (reg_save_area, 0);
12205 if (GET_CODE (reg_save_area) == PLUS)
12207 gcc_assert (XEXP (reg_save_area, 0)
12208 == virtual_stack_vars_rtx);
12209 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
12210 offset += INTVAL (XEXP (reg_save_area, 1));
12213 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12216 cfun->machine->varargs_save_offset = offset;
12217 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12222 first_reg_offset = next_cum.words;
12223 save_area = crtl->args.internal_arg_pointer;
12225 if (targetm.calls.must_pass_in_stack (mode, type))
12226 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12229 set = get_varargs_alias_set ();
12230 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12231 && cfun->va_list_gpr_size)
12233 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12235 if (va_list_gpr_counter_field)
12236 /* V4 va_list_gpr_size counts number of registers needed. */
12237 n_gpr = cfun->va_list_gpr_size;
12239 /* char * va_list instead counts number of bytes needed. */
12240 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12245 mem = gen_rtx_MEM (BLKmode,
12246 plus_constant (Pmode, save_area,
12247 first_reg_offset * reg_size));
12248 MEM_NOTRAP_P (mem) = 1;
12249 set_mem_alias_set (mem, set);
12250 set_mem_align (mem, BITS_PER_WORD);
12252 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12256 /* Save FP registers if needed. */
12257 if (DEFAULT_ABI == ABI_V4
12258 && TARGET_HARD_FLOAT
12260 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12261 && cfun->va_list_fpr_size)
12263 int fregno = next_cum.fregno, nregs;
12264 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12265 rtx lab = gen_label_rtx ();
12266 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12267 * UNITS_PER_FP_WORD);
12270 (gen_rtx_SET (pc_rtx,
12271 gen_rtx_IF_THEN_ELSE (VOIDmode,
12272 gen_rtx_NE (VOIDmode, cr1,
12274 gen_rtx_LABEL_REF (VOIDmode, lab),
12278 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12279 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12281 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12282 plus_constant (Pmode, save_area, off));
12283 MEM_NOTRAP_P (mem) = 1;
12284 set_mem_alias_set (mem, set);
12285 set_mem_align (mem, GET_MODE_ALIGNMENT (
12286 TARGET_HARD_FLOAT ? DFmode : SFmode));
12287 emit_move_insn (mem, gen_rtx_REG (
12288 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12295 /* Create the va_list data type. */
12298 rs6000_build_builtin_va_list (void)
12300 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12302 /* For AIX, prefer 'char *' because that's what the system
12303 header files like. */
12304 if (DEFAULT_ABI != ABI_V4)
12305 return build_pointer_type (char_type_node);
12307 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12308 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12309 get_identifier ("__va_list_tag"), record);
12311 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12312 unsigned_char_type_node);
12313 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12314 unsigned_char_type_node);
12315 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12316 every user file. */
12317 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12318 get_identifier ("reserved"), short_unsigned_type_node);
12319 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12320 get_identifier ("overflow_arg_area"),
12322 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12323 get_identifier ("reg_save_area"),
12326 va_list_gpr_counter_field = f_gpr;
12327 va_list_fpr_counter_field = f_fpr;
12329 DECL_FIELD_CONTEXT (f_gpr) = record;
12330 DECL_FIELD_CONTEXT (f_fpr) = record;
12331 DECL_FIELD_CONTEXT (f_res) = record;
12332 DECL_FIELD_CONTEXT (f_ovf) = record;
12333 DECL_FIELD_CONTEXT (f_sav) = record;
12335 TYPE_STUB_DECL (record) = type_decl;
12336 TYPE_NAME (record) = type_decl;
12337 TYPE_FIELDS (record) = f_gpr;
12338 DECL_CHAIN (f_gpr) = f_fpr;
12339 DECL_CHAIN (f_fpr) = f_res;
12340 DECL_CHAIN (f_res) = f_ovf;
12341 DECL_CHAIN (f_ovf) = f_sav;
12343 layout_type (record);
12345 /* The correct type is an array type of one element. */
12346 return build_array_type (record, build_index_type (size_zero_node));
12349 /* Implement va_start. */
12352 rs6000_va_start (tree valist, rtx nextarg)
12354 HOST_WIDE_INT words, n_gpr, n_fpr;
12355 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12356 tree gpr, fpr, ovf, sav, t;
12358 /* Only SVR4 needs something special. */
12359 if (DEFAULT_ABI != ABI_V4)
12361 std_expand_builtin_va_start (valist, nextarg);
12365 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12366 f_fpr = DECL_CHAIN (f_gpr);
12367 f_res = DECL_CHAIN (f_fpr);
12368 f_ovf = DECL_CHAIN (f_res);
12369 f_sav = DECL_CHAIN (f_ovf);
12371 valist = build_simple_mem_ref (valist);
12372 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12373 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12375 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12377 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12380 /* Count number of gp and fp argument registers used. */
12381 words = crtl->args.info.words;
12382 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12384 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12387 if (TARGET_DEBUG_ARG)
12388 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12389 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12390 words, n_gpr, n_fpr);
12392 if (cfun->va_list_gpr_size)
12394 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12395 build_int_cst (NULL_TREE, n_gpr));
12396 TREE_SIDE_EFFECTS (t) = 1;
12397 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12400 if (cfun->va_list_fpr_size)
12402 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12403 build_int_cst (NULL_TREE, n_fpr));
12404 TREE_SIDE_EFFECTS (t) = 1;
12405 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12407 #ifdef HAVE_AS_GNU_ATTRIBUTE
12408 if (call_ABI_of_interest (cfun->decl))
12409 rs6000_passes_float = true;
12413 /* Find the overflow area. */
12414 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12416 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12417 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12418 TREE_SIDE_EFFECTS (t) = 1;
12419 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12421 /* If there were no va_arg invocations, don't set up the register
12423 if (!cfun->va_list_gpr_size
12424 && !cfun->va_list_fpr_size
12425 && n_gpr < GP_ARG_NUM_REG
12426 && n_fpr < FP_ARG_V4_MAX_REG)
12429 /* Find the register save area. */
12430 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12431 if (cfun->machine->varargs_save_offset)
12432 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12433 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12434 TREE_SIDE_EFFECTS (t) = 1;
12435 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12438 /* Implement va_arg. */
12441 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12442 gimple_seq *post_p)
12444 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12445 tree gpr, fpr, ovf, sav, reg, t, u;
12446 int size, rsize, n_reg, sav_ofs, sav_scale;
12447 tree lab_false, lab_over, addr;
12449 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12453 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12455 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12456 return build_va_arg_indirect_ref (t);
12459 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12460 earlier version of gcc, with the property that it always applied alignment
12461 adjustments to the va-args (even for zero-sized types). The cheapest way
12462 to deal with this is to replicate the effect of the part of
12463 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12465 We don't need to check for pass-by-reference because of the test above.
12466 We can return a simplifed answer, since we know there's no offset to add. */
12469 && rs6000_darwin64_abi)
12470 || DEFAULT_ABI == ABI_ELFv2
12471 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12472 && integer_zerop (TYPE_SIZE (type)))
12474 unsigned HOST_WIDE_INT align, boundary;
12475 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12476 align = PARM_BOUNDARY / BITS_PER_UNIT;
12477 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12478 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12479 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12480 boundary /= BITS_PER_UNIT;
12481 if (boundary > align)
12484 /* This updates arg ptr by the amount that would be necessary
12485 to align the zero-sized (but not zero-alignment) item. */
12486 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12487 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12488 gimplify_and_add (t, pre_p);
12490 t = fold_convert (sizetype, valist_tmp);
12491 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12492 fold_convert (TREE_TYPE (valist),
12493 fold_build2 (BIT_AND_EXPR, sizetype, t,
12494 size_int (-boundary))));
12495 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12496 gimplify_and_add (t, pre_p);
12498 /* Since it is zero-sized there's no increment for the item itself. */
12499 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12500 return build_va_arg_indirect_ref (valist_tmp);
12503 if (DEFAULT_ABI != ABI_V4)
12505 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12507 tree elem_type = TREE_TYPE (type);
12508 machine_mode elem_mode = TYPE_MODE (elem_type);
12509 int elem_size = GET_MODE_SIZE (elem_mode);
12511 if (elem_size < UNITS_PER_WORD)
12513 tree real_part, imag_part;
12514 gimple_seq post = NULL;
12516 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12518 /* Copy the value into a temporary, lest the formal temporary
12519 be reused out from under us. */
12520 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12521 gimple_seq_add_seq (pre_p, post);
12523 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12526 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12530 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12533 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12534 f_fpr = DECL_CHAIN (f_gpr);
12535 f_res = DECL_CHAIN (f_fpr);
12536 f_ovf = DECL_CHAIN (f_res);
12537 f_sav = DECL_CHAIN (f_ovf);
12539 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12540 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12542 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12544 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12547 size = int_size_in_bytes (type);
12548 rsize = (size + 3) / 4;
12549 int pad = 4 * rsize - size;
12552 machine_mode mode = TYPE_MODE (type);
12553 if (abi_v4_pass_in_fpr (mode, false))
12555 /* FP args go in FP registers, if present. */
12557 n_reg = (size + 7) / 8;
12558 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12559 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12560 if (mode != SFmode && mode != SDmode)
12565 /* Otherwise into GP registers. */
12574 /* Pull the value out of the saved registers.... */
12577 addr = create_tmp_var (ptr_type_node, "addr");
12579 /* AltiVec vectors never go in registers when -mabi=altivec. */
12580 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12584 lab_false = create_artificial_label (input_location);
12585 lab_over = create_artificial_label (input_location);
12587 /* Long long is aligned in the registers. As are any other 2 gpr
12588 item such as complex int due to a historical mistake. */
12590 if (n_reg == 2 && reg == gpr)
12593 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12594 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12595 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12596 unshare_expr (reg), u);
12598 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12599 reg number is 0 for f1, so we want to make it odd. */
12600 else if (reg == fpr && mode == TDmode)
12602 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12603 build_int_cst (TREE_TYPE (reg), 1));
12604 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12607 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12608 t = build2 (GE_EXPR, boolean_type_node, u, t);
12609 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12610 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12611 gimplify_and_add (t, pre_p);
12615 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12617 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12618 build_int_cst (TREE_TYPE (reg), n_reg));
12619 u = fold_convert (sizetype, u);
12620 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12621 t = fold_build_pointer_plus (t, u);
12623 /* _Decimal32 varargs are located in the second word of the 64-bit
12624 FP register for 32-bit binaries. */
12625 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12626 t = fold_build_pointer_plus_hwi (t, size);
12628 /* Args are passed right-aligned. */
12629 if (BYTES_BIG_ENDIAN)
12630 t = fold_build_pointer_plus_hwi (t, pad);
12632 gimplify_assign (addr, t, pre_p);
12634 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12636 stmt = gimple_build_label (lab_false);
12637 gimple_seq_add_stmt (pre_p, stmt);
12639 if ((n_reg == 2 && !regalign) || n_reg > 2)
12641 /* Ensure that we don't find any more args in regs.
12642 Alignment has taken care of for special cases. */
12643 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12647 /* ... otherwise out of the overflow area. */
12649 /* Care for on-stack alignment if needed. */
12653 t = fold_build_pointer_plus_hwi (t, align - 1);
12654 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12655 build_int_cst (TREE_TYPE (t), -align));
12658 /* Args are passed right-aligned. */
12659 if (BYTES_BIG_ENDIAN)
12660 t = fold_build_pointer_plus_hwi (t, pad);
12662 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12664 gimplify_assign (unshare_expr (addr), t, pre_p);
12666 t = fold_build_pointer_plus_hwi (t, size);
12667 gimplify_assign (unshare_expr (ovf), t, pre_p);
12671 stmt = gimple_build_label (lab_over);
12672 gimple_seq_add_stmt (pre_p, stmt);
12675 if (STRICT_ALIGNMENT
12676 && (TYPE_ALIGN (type)
12677 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12679 /* The value (of type complex double, for example) may not be
12680 aligned in memory in the saved registers, so copy via a
12681 temporary. (This is the same code as used for SPARC.) */
12682 tree tmp = create_tmp_var (type, "va_arg_tmp");
12683 tree dest_addr = build_fold_addr_expr (tmp);
12685 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12686 3, dest_addr, addr, size_int (rsize * 4));
12687 TREE_ADDRESSABLE (tmp) = 1;
12689 gimplify_and_add (copy, pre_p);
12693 addr = fold_convert (ptrtype, addr);
12694 return build_va_arg_indirect_ref (addr);
12700 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12703 unsigned classify = rs6000_builtin_info[(int)code].attr;
12704 const char *attr_string = "";
12706 gcc_assert (name != NULL);
12707 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12709 if (rs6000_builtin_decls[(int)code])
12710 fatal_error (input_location,
12711 "internal error: builtin function %qs already processed",
12714 rs6000_builtin_decls[(int)code] = t =
12715 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12717 /* Set any special attributes. */
12718 if ((classify & RS6000_BTC_CONST) != 0)
12720 /* const function, function only depends on the inputs. */
12721 TREE_READONLY (t) = 1;
12722 TREE_NOTHROW (t) = 1;
12723 attr_string = ", const";
12725 else if ((classify & RS6000_BTC_PURE) != 0)
12727 /* pure function, function can read global memory, but does not set any
12729 DECL_PURE_P (t) = 1;
12730 TREE_NOTHROW (t) = 1;
12731 attr_string = ", pure";
12733 else if ((classify & RS6000_BTC_FP) != 0)
12735 /* Function is a math function. If rounding mode is on, then treat the
12736 function as not reading global memory, but it can have arbitrary side
12737 effects. If it is off, then assume the function is a const function.
12738 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12739 builtin-attribute.def that is used for the math functions. */
12740 TREE_NOTHROW (t) = 1;
12741 if (flag_rounding_math)
12743 DECL_PURE_P (t) = 1;
12744 DECL_IS_NOVOPS (t) = 1;
12745 attr_string = ", fp, pure";
12749 TREE_READONLY (t) = 1;
12750 attr_string = ", fp, const";
12753 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12754 gcc_unreachable ();
12756 if (TARGET_DEBUG_BUILTIN)
12757 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12758 (int)code, name, attr_string);
12761 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12763 #undef RS6000_BUILTIN_0
12764 #undef RS6000_BUILTIN_1
12765 #undef RS6000_BUILTIN_2
12766 #undef RS6000_BUILTIN_3
12767 #undef RS6000_BUILTIN_A
12768 #undef RS6000_BUILTIN_D
12769 #undef RS6000_BUILTIN_H
12770 #undef RS6000_BUILTIN_P
12771 #undef RS6000_BUILTIN_X
12773 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12774 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12775 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12776 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12777 { MASK, ICODE, NAME, ENUM },
12779 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12780 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12781 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12782 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12783 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12785 static const struct builtin_description bdesc_3arg[] =
12787 #include "rs6000-builtin.def"
12790 /* DST operations: void foo (void *, const int, const char). */
12792 #undef RS6000_BUILTIN_0
12793 #undef RS6000_BUILTIN_1
12794 #undef RS6000_BUILTIN_2
12795 #undef RS6000_BUILTIN_3
12796 #undef RS6000_BUILTIN_A
12797 #undef RS6000_BUILTIN_D
12798 #undef RS6000_BUILTIN_H
12799 #undef RS6000_BUILTIN_P
12800 #undef RS6000_BUILTIN_X
12802 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12803 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12804 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12805 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12806 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12807 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12808 { MASK, ICODE, NAME, ENUM },
12810 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12811 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12812 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12814 static const struct builtin_description bdesc_dst[] =
12816 #include "rs6000-builtin.def"
12819 /* Simple binary operations: VECc = foo (VECa, VECb). */
12821 #undef RS6000_BUILTIN_0
12822 #undef RS6000_BUILTIN_1
12823 #undef RS6000_BUILTIN_2
12824 #undef RS6000_BUILTIN_3
12825 #undef RS6000_BUILTIN_A
12826 #undef RS6000_BUILTIN_D
12827 #undef RS6000_BUILTIN_H
12828 #undef RS6000_BUILTIN_P
12829 #undef RS6000_BUILTIN_X
12831 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12832 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12833 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12834 { MASK, ICODE, NAME, ENUM },
12836 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12837 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12838 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12839 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12840 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12841 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12843 static const struct builtin_description bdesc_2arg[] =
12845 #include "rs6000-builtin.def"
12848 #undef RS6000_BUILTIN_0
12849 #undef RS6000_BUILTIN_1
12850 #undef RS6000_BUILTIN_2
12851 #undef RS6000_BUILTIN_3
12852 #undef RS6000_BUILTIN_A
12853 #undef RS6000_BUILTIN_D
12854 #undef RS6000_BUILTIN_H
12855 #undef RS6000_BUILTIN_P
12856 #undef RS6000_BUILTIN_X
12858 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12859 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12860 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12861 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12862 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12863 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12864 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12865 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12866 { MASK, ICODE, NAME, ENUM },
12868 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12870 /* AltiVec predicates. */
12872 static const struct builtin_description bdesc_altivec_preds[] =
12874 #include "rs6000-builtin.def"
12877 /* ABS* operations. */
12879 #undef RS6000_BUILTIN_0
12880 #undef RS6000_BUILTIN_1
12881 #undef RS6000_BUILTIN_2
12882 #undef RS6000_BUILTIN_3
12883 #undef RS6000_BUILTIN_A
12884 #undef RS6000_BUILTIN_D
12885 #undef RS6000_BUILTIN_H
12886 #undef RS6000_BUILTIN_P
12887 #undef RS6000_BUILTIN_X
12889 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12890 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12891 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12892 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12893 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12894 { MASK, ICODE, NAME, ENUM },
12896 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12897 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12898 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12899 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12901 static const struct builtin_description bdesc_abs[] =
12903 #include "rs6000-builtin.def"
12906 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12909 #undef RS6000_BUILTIN_0
12910 #undef RS6000_BUILTIN_1
12911 #undef RS6000_BUILTIN_2
12912 #undef RS6000_BUILTIN_3
12913 #undef RS6000_BUILTIN_A
12914 #undef RS6000_BUILTIN_D
12915 #undef RS6000_BUILTIN_H
12916 #undef RS6000_BUILTIN_P
12917 #undef RS6000_BUILTIN_X
12919 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12920 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12921 { MASK, ICODE, NAME, ENUM },
12923 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12924 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12925 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12926 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12927 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12928 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12929 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12931 static const struct builtin_description bdesc_1arg[] =
12933 #include "rs6000-builtin.def"
12936 /* Simple no-argument operations: result = __builtin_darn_32 () */
12938 #undef RS6000_BUILTIN_0
12939 #undef RS6000_BUILTIN_1
12940 #undef RS6000_BUILTIN_2
12941 #undef RS6000_BUILTIN_3
12942 #undef RS6000_BUILTIN_A
12943 #undef RS6000_BUILTIN_D
12944 #undef RS6000_BUILTIN_H
12945 #undef RS6000_BUILTIN_P
12946 #undef RS6000_BUILTIN_X
12948 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
12949 { MASK, ICODE, NAME, ENUM },
12951 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12952 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12953 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12954 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12955 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12956 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12957 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12958 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12960 static const struct builtin_description bdesc_0arg[] =
12962 #include "rs6000-builtin.def"
12965 /* HTM builtins. */
12966 #undef RS6000_BUILTIN_0
12967 #undef RS6000_BUILTIN_1
12968 #undef RS6000_BUILTIN_2
12969 #undef RS6000_BUILTIN_3
12970 #undef RS6000_BUILTIN_A
12971 #undef RS6000_BUILTIN_D
12972 #undef RS6000_BUILTIN_H
12973 #undef RS6000_BUILTIN_P
12974 #undef RS6000_BUILTIN_X
12976 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12977 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12978 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12979 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12980 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12981 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12982 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12983 { MASK, ICODE, NAME, ENUM },
12985 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12986 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12988 static const struct builtin_description bdesc_htm[] =
12990 #include "rs6000-builtin.def"
12993 #undef RS6000_BUILTIN_0
12994 #undef RS6000_BUILTIN_1
12995 #undef RS6000_BUILTIN_2
12996 #undef RS6000_BUILTIN_3
12997 #undef RS6000_BUILTIN_A
12998 #undef RS6000_BUILTIN_D
12999 #undef RS6000_BUILTIN_H
13000 #undef RS6000_BUILTIN_P
13002 /* Return true if a builtin function is overloaded. */
13004 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13006 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13010 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13012 return rs6000_builtin_info[(int)fncode].name;
13015 /* Expand an expression EXP that calls a builtin without arguments. */
13017 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13020 machine_mode tmode = insn_data[icode].operand[0].mode;
13022 if (icode == CODE_FOR_nothing)
13023 /* Builtin not supported on this processor. */
13026 if (icode == CODE_FOR_rs6000_mffsl
13027 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13029 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13034 || GET_MODE (target) != tmode
13035 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13036 target = gen_reg_rtx (tmode);
13038 pat = GEN_FCN (icode) (target);
13048 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13051 tree arg0 = CALL_EXPR_ARG (exp, 0);
13052 tree arg1 = CALL_EXPR_ARG (exp, 1);
13053 rtx op0 = expand_normal (arg0);
13054 rtx op1 = expand_normal (arg1);
13055 machine_mode mode0 = insn_data[icode].operand[0].mode;
13056 machine_mode mode1 = insn_data[icode].operand[1].mode;
13058 if (icode == CODE_FOR_nothing)
13059 /* Builtin not supported on this processor. */
13062 /* If we got invalid arguments bail out before generating bad rtl. */
13063 if (arg0 == error_mark_node || arg1 == error_mark_node)
13066 if (!CONST_INT_P (op0)
13067 || INTVAL (op0) > 255
13068 || INTVAL (op0) < 0)
13070 error ("argument 1 must be an 8-bit field value");
13074 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13075 op0 = copy_to_mode_reg (mode0, op0);
13077 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13078 op1 = copy_to_mode_reg (mode1, op1);
13080 pat = GEN_FCN (icode) (op0, op1);
13089 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13092 tree arg0 = CALL_EXPR_ARG (exp, 0);
13093 rtx op0 = expand_normal (arg0);
13095 if (icode == CODE_FOR_nothing)
13096 /* Builtin not supported on this processor. */
13099 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13101 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13102 "%<-msoft-float%>");
13106 /* If we got invalid arguments bail out before generating bad rtl. */
13107 if (arg0 == error_mark_node)
13110 /* Only allow bit numbers 0 to 31. */
13111 if (!u5bit_cint_operand (op0, VOIDmode))
13113 error ("Argument must be a constant between 0 and 31.");
13117 pat = GEN_FCN (icode) (op0);
13126 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13129 tree arg0 = CALL_EXPR_ARG (exp, 0);
13130 rtx op0 = expand_normal (arg0);
13131 machine_mode mode0 = insn_data[icode].operand[0].mode;
13133 if (icode == CODE_FOR_nothing)
13134 /* Builtin not supported on this processor. */
13137 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13139 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13143 /* If we got invalid arguments bail out before generating bad rtl. */
13144 if (arg0 == error_mark_node)
13147 /* If the argument is a constant, check the range. Argument can only be a
13148 2-bit value. Unfortunately, can't check the range of the value at
13149 compile time if the argument is a variable. The least significant two
13150 bits of the argument, regardless of type, are used to set the rounding
13151 mode. All other bits are ignored. */
13152 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
13154 error ("Argument must be a value between 0 and 3.");
13158 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13159 op0 = copy_to_mode_reg (mode0, op0);
13161 pat = GEN_FCN (icode) (op0);
13169 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13172 tree arg0 = CALL_EXPR_ARG (exp, 0);
13173 rtx op0 = expand_normal (arg0);
13174 machine_mode mode0 = insn_data[icode].operand[0].mode;
13177 /* Builtin not supported in 32-bit mode. */
13178 fatal_error (input_location,
13179 "%<__builtin_set_fpscr_drn%> is not supported "
13182 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13184 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13188 if (icode == CODE_FOR_nothing)
13189 /* Builtin not supported on this processor. */
13192 /* If we got invalid arguments bail out before generating bad rtl. */
13193 if (arg0 == error_mark_node)
13196 /* If the argument is a constant, check the range. Agrument can only be a
13197 3-bit value. Unfortunately, can't check the range of the value at
13198 compile time if the argument is a variable. The least significant two
13199 bits of the argument, regardless of type, are used to set the rounding
13200 mode. All other bits are ignored. */
13201 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
13203 error ("Argument must be a value between 0 and 7.");
13207 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13208 op0 = copy_to_mode_reg (mode0, op0);
13210 pat = GEN_FCN (icode) (op0);
13219 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13222 tree arg0 = CALL_EXPR_ARG (exp, 0);
13223 rtx op0 = expand_normal (arg0);
13224 machine_mode tmode = insn_data[icode].operand[0].mode;
13225 machine_mode mode0 = insn_data[icode].operand[1].mode;
13227 if (icode == CODE_FOR_nothing)
13228 /* Builtin not supported on this processor. */
13231 /* If we got invalid arguments bail out before generating bad rtl. */
13232 if (arg0 == error_mark_node)
13235 if (icode == CODE_FOR_altivec_vspltisb
13236 || icode == CODE_FOR_altivec_vspltish
13237 || icode == CODE_FOR_altivec_vspltisw)
13239 /* Only allow 5-bit *signed* literals. */
13240 if (!CONST_INT_P (op0)
13241 || INTVAL (op0) > 15
13242 || INTVAL (op0) < -16)
13244 error ("argument 1 must be a 5-bit signed literal");
13245 return CONST0_RTX (tmode);
13250 || GET_MODE (target) != tmode
13251 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13252 target = gen_reg_rtx (tmode);
13254 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13255 op0 = copy_to_mode_reg (mode0, op0);
13257 pat = GEN_FCN (icode) (target, op0);
13266 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13268 rtx pat, scratch1, scratch2;
13269 tree arg0 = CALL_EXPR_ARG (exp, 0);
13270 rtx op0 = expand_normal (arg0);
13271 machine_mode tmode = insn_data[icode].operand[0].mode;
13272 machine_mode mode0 = insn_data[icode].operand[1].mode;
13274 /* If we have invalid arguments, bail out before generating bad rtl. */
13275 if (arg0 == error_mark_node)
13279 || GET_MODE (target) != tmode
13280 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13281 target = gen_reg_rtx (tmode);
13283 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13284 op0 = copy_to_mode_reg (mode0, op0);
13286 scratch1 = gen_reg_rtx (mode0);
13287 scratch2 = gen_reg_rtx (mode0);
13289 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13298 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13301 tree arg0 = CALL_EXPR_ARG (exp, 0);
13302 tree arg1 = CALL_EXPR_ARG (exp, 1);
13303 rtx op0 = expand_normal (arg0);
13304 rtx op1 = expand_normal (arg1);
13305 machine_mode tmode = insn_data[icode].operand[0].mode;
13306 machine_mode mode0 = insn_data[icode].operand[1].mode;
13307 machine_mode mode1 = insn_data[icode].operand[2].mode;
13309 if (icode == CODE_FOR_nothing)
13310 /* Builtin not supported on this processor. */
13313 /* If we got invalid arguments bail out before generating bad rtl. */
13314 if (arg0 == error_mark_node || arg1 == error_mark_node)
13317 if (icode == CODE_FOR_unpackv1ti
13318 || icode == CODE_FOR_unpackkf
13319 || icode == CODE_FOR_unpacktf
13320 || icode == CODE_FOR_unpackif
13321 || icode == CODE_FOR_unpacktd)
13323 /* Only allow 1-bit unsigned literals. */
13325 if (TREE_CODE (arg1) != INTEGER_CST
13326 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13328 error ("argument 2 must be a 1-bit unsigned literal");
13329 return CONST0_RTX (tmode);
13332 else if (icode == CODE_FOR_altivec_vspltw)
13334 /* Only allow 2-bit unsigned literals. */
13336 if (TREE_CODE (arg1) != INTEGER_CST
13337 || TREE_INT_CST_LOW (arg1) & ~3)
13339 error ("argument 2 must be a 2-bit unsigned literal");
13340 return CONST0_RTX (tmode);
13343 else if (icode == CODE_FOR_altivec_vsplth)
13345 /* Only allow 3-bit unsigned literals. */
13347 if (TREE_CODE (arg1) != INTEGER_CST
13348 || TREE_INT_CST_LOW (arg1) & ~7)
13350 error ("argument 2 must be a 3-bit unsigned literal");
13351 return CONST0_RTX (tmode);
13354 else if (icode == CODE_FOR_altivec_vspltb)
13356 /* Only allow 4-bit unsigned literals. */
13358 if (TREE_CODE (arg1) != INTEGER_CST
13359 || TREE_INT_CST_LOW (arg1) & ~15)
13361 error ("argument 2 must be a 4-bit unsigned literal");
13362 return CONST0_RTX (tmode);
13365 else if (icode == CODE_FOR_altivec_vcfux
13366 || icode == CODE_FOR_altivec_vcfsx
13367 || icode == CODE_FOR_altivec_vctsxs
13368 || icode == CODE_FOR_altivec_vctuxs)
13370 /* Only allow 5-bit unsigned literals. */
13372 if (TREE_CODE (arg1) != INTEGER_CST
13373 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13375 error ("argument 2 must be a 5-bit unsigned literal");
13376 return CONST0_RTX (tmode);
13379 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13380 || icode == CODE_FOR_dfptstsfi_lt_dd
13381 || icode == CODE_FOR_dfptstsfi_gt_dd
13382 || icode == CODE_FOR_dfptstsfi_unordered_dd
13383 || icode == CODE_FOR_dfptstsfi_eq_td
13384 || icode == CODE_FOR_dfptstsfi_lt_td
13385 || icode == CODE_FOR_dfptstsfi_gt_td
13386 || icode == CODE_FOR_dfptstsfi_unordered_td)
13388 /* Only allow 6-bit unsigned literals. */
13390 if (TREE_CODE (arg0) != INTEGER_CST
13391 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13393 error ("argument 1 must be a 6-bit unsigned literal");
13394 return CONST0_RTX (tmode);
13397 else if (icode == CODE_FOR_xststdcqp_kf
13398 || icode == CODE_FOR_xststdcqp_tf
13399 || icode == CODE_FOR_xststdcdp
13400 || icode == CODE_FOR_xststdcsp
13401 || icode == CODE_FOR_xvtstdcdp
13402 || icode == CODE_FOR_xvtstdcsp)
13404 /* Only allow 7-bit unsigned literals. */
13406 if (TREE_CODE (arg1) != INTEGER_CST
13407 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13409 error ("argument 2 must be a 7-bit unsigned literal");
13410 return CONST0_RTX (tmode);
13415 || GET_MODE (target) != tmode
13416 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13417 target = gen_reg_rtx (tmode);
13419 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13420 op0 = copy_to_mode_reg (mode0, op0);
13421 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13422 op1 = copy_to_mode_reg (mode1, op1);
13424 pat = GEN_FCN (icode) (target, op0, op1);
13433 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13436 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13437 tree arg0 = CALL_EXPR_ARG (exp, 1);
13438 tree arg1 = CALL_EXPR_ARG (exp, 2);
13439 rtx op0 = expand_normal (arg0);
13440 rtx op1 = expand_normal (arg1);
13441 machine_mode tmode = SImode;
13442 machine_mode mode0 = insn_data[icode].operand[1].mode;
13443 machine_mode mode1 = insn_data[icode].operand[2].mode;
13446 if (TREE_CODE (cr6_form) != INTEGER_CST)
13448 error ("argument 1 of %qs must be a constant",
13449 "__builtin_altivec_predicate");
13453 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13455 gcc_assert (mode0 == mode1);
13457 /* If we have invalid arguments, bail out before generating bad rtl. */
13458 if (arg0 == error_mark_node || arg1 == error_mark_node)
13462 || GET_MODE (target) != tmode
13463 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13464 target = gen_reg_rtx (tmode);
13466 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13467 op0 = copy_to_mode_reg (mode0, op0);
13468 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13469 op1 = copy_to_mode_reg (mode1, op1);
13471 /* Note that for many of the relevant operations (e.g. cmpne or
13472 cmpeq) with float or double operands, it makes more sense for the
13473 mode of the allocated scratch register to select a vector of
13474 integer. But the choice to copy the mode of operand 0 was made
13475 long ago and there are no plans to change it. */
13476 scratch = gen_reg_rtx (mode0);
13478 pat = GEN_FCN (icode) (scratch, op0, op1);
13483 /* The vec_any* and vec_all* predicates use the same opcodes for two
13484 different operations, but the bits in CR6 will be different
13485 depending on what information we want. So we have to play tricks
13486 with CR6 to get the right bits out.
13488 If you think this is disgusting, look at the specs for the
13489 AltiVec predicates. */
13491 switch (cr6_form_int)
13494 emit_insn (gen_cr6_test_for_zero (target));
13497 emit_insn (gen_cr6_test_for_zero_reverse (target));
13500 emit_insn (gen_cr6_test_for_lt (target));
13503 emit_insn (gen_cr6_test_for_lt_reverse (target));
13506 error ("argument 1 of %qs is out of range",
13507 "__builtin_altivec_predicate");
13515 swap_endian_selector_for_mode (machine_mode mode)
13517 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13518 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13519 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13520 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13522 unsigned int *swaparray, i;
13542 gcc_unreachable ();
13545 for (i = 0; i < 16; ++i)
13546 perm[i] = GEN_INT (swaparray[i]);
13548 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13549 gen_rtvec_v (16, perm)));
13553 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13556 tree arg0 = CALL_EXPR_ARG (exp, 0);
13557 tree arg1 = CALL_EXPR_ARG (exp, 1);
13558 machine_mode tmode = insn_data[icode].operand[0].mode;
13559 machine_mode mode0 = Pmode;
13560 machine_mode mode1 = Pmode;
13561 rtx op0 = expand_normal (arg0);
13562 rtx op1 = expand_normal (arg1);
13564 if (icode == CODE_FOR_nothing)
13565 /* Builtin not supported on this processor. */
13568 /* If we got invalid arguments bail out before generating bad rtl. */
13569 if (arg0 == error_mark_node || arg1 == error_mark_node)
13573 || GET_MODE (target) != tmode
13574 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13575 target = gen_reg_rtx (tmode);
13577 op1 = copy_to_mode_reg (mode1, op1);
13579 /* For LVX, express the RTL accurately by ANDing the address with -16.
13580 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13581 so the raw address is fine. */
13582 if (icode == CODE_FOR_altivec_lvx_v1ti
13583 || icode == CODE_FOR_altivec_lvx_v2df
13584 || icode == CODE_FOR_altivec_lvx_v2di
13585 || icode == CODE_FOR_altivec_lvx_v4sf
13586 || icode == CODE_FOR_altivec_lvx_v4si
13587 || icode == CODE_FOR_altivec_lvx_v8hi
13588 || icode == CODE_FOR_altivec_lvx_v16qi)
13591 if (op0 == const0_rtx)
13595 op0 = copy_to_mode_reg (mode0, op0);
13596 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13598 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13599 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13601 emit_insn (gen_rtx_SET (target, addr));
13605 if (op0 == const0_rtx)
13606 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13609 op0 = copy_to_mode_reg (mode0, op0);
13610 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13611 gen_rtx_PLUS (Pmode, op1, op0));
13614 pat = GEN_FCN (icode) (target, addr);
13624 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13627 tree arg0 = CALL_EXPR_ARG (exp, 0);
13628 tree arg1 = CALL_EXPR_ARG (exp, 1);
13629 tree arg2 = CALL_EXPR_ARG (exp, 2);
13630 rtx op0 = expand_normal (arg0);
13631 rtx op1 = expand_normal (arg1);
13632 rtx op2 = expand_normal (arg2);
13633 machine_mode mode0 = insn_data[icode].operand[0].mode;
13634 machine_mode mode1 = insn_data[icode].operand[1].mode;
13635 machine_mode mode2 = insn_data[icode].operand[2].mode;
13637 if (icode == CODE_FOR_nothing)
13638 /* Builtin not supported on this processor. */
13641 /* If we got invalid arguments bail out before generating bad rtl. */
13642 if (arg0 == error_mark_node
13643 || arg1 == error_mark_node
13644 || arg2 == error_mark_node)
13647 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13648 op0 = copy_to_mode_reg (mode0, op0);
13649 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13650 op1 = copy_to_mode_reg (mode1, op1);
13651 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13652 op2 = copy_to_mode_reg (mode2, op2);
13654 pat = GEN_FCN (icode) (op0, op1, op2);
13662 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13664 tree arg0 = CALL_EXPR_ARG (exp, 0);
13665 tree arg1 = CALL_EXPR_ARG (exp, 1);
13666 tree arg2 = CALL_EXPR_ARG (exp, 2);
13667 rtx op0 = expand_normal (arg0);
13668 rtx op1 = expand_normal (arg1);
13669 rtx op2 = expand_normal (arg2);
13670 rtx pat, addr, rawaddr;
13671 machine_mode tmode = insn_data[icode].operand[0].mode;
13672 machine_mode smode = insn_data[icode].operand[1].mode;
13673 machine_mode mode1 = Pmode;
13674 machine_mode mode2 = Pmode;
13676 /* Invalid arguments. Bail before doing anything stoopid! */
13677 if (arg0 == error_mark_node
13678 || arg1 == error_mark_node
13679 || arg2 == error_mark_node)
13682 op2 = copy_to_mode_reg (mode2, op2);
13684 /* For STVX, express the RTL accurately by ANDing the address with -16.
13685 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13686 so the raw address is fine. */
13687 if (icode == CODE_FOR_altivec_stvx_v2df
13688 || icode == CODE_FOR_altivec_stvx_v2di
13689 || icode == CODE_FOR_altivec_stvx_v4sf
13690 || icode == CODE_FOR_altivec_stvx_v4si
13691 || icode == CODE_FOR_altivec_stvx_v8hi
13692 || icode == CODE_FOR_altivec_stvx_v16qi)
13694 if (op1 == const0_rtx)
13698 op1 = copy_to_mode_reg (mode1, op1);
13699 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13702 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13703 addr = gen_rtx_MEM (tmode, addr);
13705 op0 = copy_to_mode_reg (tmode, op0);
13707 emit_insn (gen_rtx_SET (addr, op0));
13711 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13712 op0 = copy_to_mode_reg (smode, op0);
13714 if (op1 == const0_rtx)
13715 addr = gen_rtx_MEM (tmode, op2);
13718 op1 = copy_to_mode_reg (mode1, op1);
13719 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13722 pat = GEN_FCN (icode) (addr, op0);
13730 /* Return the appropriate SPR number associated with the given builtin. */
13731 static inline HOST_WIDE_INT
13732 htm_spr_num (enum rs6000_builtins code)
13734 if (code == HTM_BUILTIN_GET_TFHAR
13735 || code == HTM_BUILTIN_SET_TFHAR)
13737 else if (code == HTM_BUILTIN_GET_TFIAR
13738 || code == HTM_BUILTIN_SET_TFIAR)
13740 else if (code == HTM_BUILTIN_GET_TEXASR
13741 || code == HTM_BUILTIN_SET_TEXASR)
13743 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13744 || code == HTM_BUILTIN_SET_TEXASRU);
13745 return TEXASRU_SPR;
13748 /* Return the correct ICODE value depending on whether we are
13749 setting or reading the HTM SPRs. */
13750 static inline enum insn_code
13751 rs6000_htm_spr_icode (bool nonvoid)
13754 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13756 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13759 /* Expand the HTM builtin in EXP and store the result in TARGET.
13760 Store true in *EXPANDEDP if we found a builtin to expand. */
13762 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
13764 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13765 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
13766 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13767 const struct builtin_description *d;
13772 if (!TARGET_POWERPC64
13773 && (fcode == HTM_BUILTIN_TABORTDC
13774 || fcode == HTM_BUILTIN_TABORTDCI))
13776 size_t uns_fcode = (size_t)fcode;
13777 const char *name = rs6000_builtin_info[uns_fcode].name;
13778 error ("builtin %qs is only valid in 64-bit mode", name);
13782 /* Expand the HTM builtins. */
13784 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13785 if (d->code == fcode)
13787 rtx op[MAX_HTM_OPERANDS], pat;
13790 call_expr_arg_iterator iter;
13791 unsigned attr = rs6000_builtin_info[fcode].attr;
13792 enum insn_code icode = d->icode;
13793 const struct insn_operand_data *insn_op;
13794 bool uses_spr = (attr & RS6000_BTC_SPR);
13798 icode = rs6000_htm_spr_icode (nonvoid);
13799 insn_op = &insn_data[icode].operand[0];
13803 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
13805 || GET_MODE (target) != tmode
13806 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
13807 target = gen_reg_rtx (tmode);
13809 op[nopnds++] = target;
13812 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
13814 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
13817 insn_op = &insn_data[icode].operand[nopnds];
13819 op[nopnds] = expand_normal (arg);
13821 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
13823 if (!strcmp (insn_op->constraint, "n"))
13825 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
13826 if (!CONST_INT_P (op[nopnds]))
13827 error ("argument %d must be an unsigned literal", arg_num);
13829 error ("argument %d is an unsigned literal that is "
13830 "out of range", arg_num);
13833 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
13839 /* Handle the builtins for extended mnemonics. These accept
13840 no arguments, but map to builtins that take arguments. */
13843 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
13844 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
13845 op[nopnds++] = GEN_INT (1);
13847 attr |= RS6000_BTC_UNARY;
13849 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
13850 op[nopnds++] = GEN_INT (0);
13852 attr |= RS6000_BTC_UNARY;
13858 /* If this builtin accesses SPRs, then pass in the appropriate
13859 SPR number and SPR regno as the last two operands. */
13862 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
13863 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
13865 /* If this builtin accesses a CR, then pass in a scratch
13866 CR as the last operand. */
13867 else if (attr & RS6000_BTC_CR)
13868 { cr = gen_reg_rtx (CCmode);
13874 int expected_nopnds = 0;
13875 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
13876 expected_nopnds = 1;
13877 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
13878 expected_nopnds = 2;
13879 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
13880 expected_nopnds = 3;
13881 if (!(attr & RS6000_BTC_VOID))
13882 expected_nopnds += 1;
13884 expected_nopnds += 1;
13886 gcc_assert (nopnds == expected_nopnds
13887 && nopnds <= MAX_HTM_OPERANDS);
13893 pat = GEN_FCN (icode) (op[0]);
13896 pat = GEN_FCN (icode) (op[0], op[1]);
13899 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
13902 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
13905 gcc_unreachable ();
13911 if (attr & RS6000_BTC_CR)
13913 if (fcode == HTM_BUILTIN_TBEGIN)
13915 /* Emit code to set TARGET to true or false depending on
13916 whether the tbegin. instruction successfully or failed
13917 to start a transaction. We do this by placing the 1's
13918 complement of CR's EQ bit into TARGET. */
13919 rtx scratch = gen_reg_rtx (SImode);
13920 emit_insn (gen_rtx_SET (scratch,
13921 gen_rtx_EQ (SImode, cr,
13923 emit_insn (gen_rtx_SET (target,
13924 gen_rtx_XOR (SImode, scratch,
13929 /* Emit code to copy the 4-bit condition register field
13930 CR into the least significant end of register TARGET. */
13931 rtx scratch1 = gen_reg_rtx (SImode);
13932 rtx scratch2 = gen_reg_rtx (SImode);
13933 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
13934 emit_insn (gen_movcc (subreg, cr));
13935 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
13936 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
13945 *expandedp = false;
13949 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
13952 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
13955 /* __builtin_cpu_init () is a nop, so expand to nothing. */
13956 if (fcode == RS6000_BUILTIN_CPU_INIT)
13959 if (target == 0 || GET_MODE (target) != SImode)
13960 target = gen_reg_rtx (SImode);
13962 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
13963 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
13964 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
13965 to a STRING_CST. */
13966 if (TREE_CODE (arg) == ARRAY_REF
13967 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
13968 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
13969 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
13970 arg = TREE_OPERAND (arg, 0);
13972 if (TREE_CODE (arg) != STRING_CST)
13974 error ("builtin %qs only accepts a string argument",
13975 rs6000_builtin_info[(size_t) fcode].name);
13979 if (fcode == RS6000_BUILTIN_CPU_IS)
13981 const char *cpu = TREE_STRING_POINTER (arg);
13982 rtx cpuid = NULL_RTX;
13983 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
13984 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
13986 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
13987 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
13990 if (cpuid == NULL_RTX)
13992 /* Invalid CPU argument. */
13993 error ("cpu %qs is an invalid argument to builtin %qs",
13994 cpu, rs6000_builtin_info[(size_t) fcode].name);
13998 rtx platform = gen_reg_rtx (SImode);
13999 rtx tcbmem = gen_const_mem (SImode,
14000 gen_rtx_PLUS (Pmode,
14001 gen_rtx_REG (Pmode, TLS_REGNUM),
14002 GEN_INT (TCB_PLATFORM_OFFSET)));
14003 emit_move_insn (platform, tcbmem);
14004 emit_insn (gen_eqsi3 (target, platform, cpuid));
14006 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14008 const char *hwcap = TREE_STRING_POINTER (arg);
14009 rtx mask = NULL_RTX;
14011 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14012 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14014 mask = GEN_INT (cpu_supports_info[i].mask);
14015 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14018 if (mask == NULL_RTX)
14020 /* Invalid HWCAP argument. */
14021 error ("%s %qs is an invalid argument to builtin %qs",
14022 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14026 rtx tcb_hwcap = gen_reg_rtx (SImode);
14027 rtx tcbmem = gen_const_mem (SImode,
14028 gen_rtx_PLUS (Pmode,
14029 gen_rtx_REG (Pmode, TLS_REGNUM),
14030 GEN_INT (hwcap_offset)));
14031 emit_move_insn (tcb_hwcap, tcbmem);
14032 rtx scratch1 = gen_reg_rtx (SImode);
14033 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14034 rtx scratch2 = gen_reg_rtx (SImode);
14035 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14036 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14039 gcc_unreachable ();
14041 /* Record that we have expanded a CPU builtin, so that we can later
14042 emit a reference to the special symbol exported by LIBC to ensure we
14043 do not link against an old LIBC that doesn't support this feature. */
14044 cpu_builtin_p = true;
14047 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14048 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14050 /* For old LIBCs, always return FALSE. */
14051 emit_move_insn (target, GEN_INT (0));
14052 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14058 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14061 tree arg0 = CALL_EXPR_ARG (exp, 0);
14062 tree arg1 = CALL_EXPR_ARG (exp, 1);
14063 tree arg2 = CALL_EXPR_ARG (exp, 2);
14064 rtx op0 = expand_normal (arg0);
14065 rtx op1 = expand_normal (arg1);
14066 rtx op2 = expand_normal (arg2);
14067 machine_mode tmode = insn_data[icode].operand[0].mode;
14068 machine_mode mode0 = insn_data[icode].operand[1].mode;
14069 machine_mode mode1 = insn_data[icode].operand[2].mode;
14070 machine_mode mode2 = insn_data[icode].operand[3].mode;
14072 if (icode == CODE_FOR_nothing)
14073 /* Builtin not supported on this processor. */
14076 /* If we got invalid arguments bail out before generating bad rtl. */
14077 if (arg0 == error_mark_node
14078 || arg1 == error_mark_node
14079 || arg2 == error_mark_node)
14082 /* Check and prepare argument depending on the instruction code.
14084 Note that a switch statement instead of the sequence of tests
14085 would be incorrect as many of the CODE_FOR values could be
14086 CODE_FOR_nothing and that would yield multiple alternatives
14087 with identical values. We'd never reach here at runtime in
14089 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14090 || icode == CODE_FOR_altivec_vsldoi_v2df
14091 || icode == CODE_FOR_altivec_vsldoi_v4si
14092 || icode == CODE_FOR_altivec_vsldoi_v8hi
14093 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14095 /* Only allow 4-bit unsigned literals. */
14097 if (TREE_CODE (arg2) != INTEGER_CST
14098 || TREE_INT_CST_LOW (arg2) & ~0xf)
14100 error ("argument 3 must be a 4-bit unsigned literal");
14101 return CONST0_RTX (tmode);
14104 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14105 || icode == CODE_FOR_vsx_xxpermdi_v2di
14106 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14107 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14108 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14109 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14110 || icode == CODE_FOR_vsx_xxpermdi_v4si
14111 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14112 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14113 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14114 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14115 || icode == CODE_FOR_vsx_xxsldwi_v4si
14116 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14117 || icode == CODE_FOR_vsx_xxsldwi_v2di
14118 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14120 /* Only allow 2-bit unsigned literals. */
14122 if (TREE_CODE (arg2) != INTEGER_CST
14123 || TREE_INT_CST_LOW (arg2) & ~0x3)
14125 error ("argument 3 must be a 2-bit unsigned literal");
14126 return CONST0_RTX (tmode);
14129 else if (icode == CODE_FOR_vsx_set_v2df
14130 || icode == CODE_FOR_vsx_set_v2di
14131 || icode == CODE_FOR_bcdadd
14132 || icode == CODE_FOR_bcdadd_lt
14133 || icode == CODE_FOR_bcdadd_eq
14134 || icode == CODE_FOR_bcdadd_gt
14135 || icode == CODE_FOR_bcdsub
14136 || icode == CODE_FOR_bcdsub_lt
14137 || icode == CODE_FOR_bcdsub_eq
14138 || icode == CODE_FOR_bcdsub_gt)
14140 /* Only allow 1-bit unsigned literals. */
14142 if (TREE_CODE (arg2) != INTEGER_CST
14143 || TREE_INT_CST_LOW (arg2) & ~0x1)
14145 error ("argument 3 must be a 1-bit unsigned literal");
14146 return CONST0_RTX (tmode);
14149 else if (icode == CODE_FOR_dfp_ddedpd_dd
14150 || icode == CODE_FOR_dfp_ddedpd_td)
14152 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14154 if (TREE_CODE (arg0) != INTEGER_CST
14155 || TREE_INT_CST_LOW (arg2) & ~0x3)
14157 error ("argument 1 must be 0 or 2");
14158 return CONST0_RTX (tmode);
14161 else if (icode == CODE_FOR_dfp_denbcd_dd
14162 || icode == CODE_FOR_dfp_denbcd_td)
14164 /* Only allow 1-bit unsigned literals. */
14166 if (TREE_CODE (arg0) != INTEGER_CST
14167 || TREE_INT_CST_LOW (arg0) & ~0x1)
14169 error ("argument 1 must be a 1-bit unsigned literal");
14170 return CONST0_RTX (tmode);
14173 else if (icode == CODE_FOR_dfp_dscli_dd
14174 || icode == CODE_FOR_dfp_dscli_td
14175 || icode == CODE_FOR_dfp_dscri_dd
14176 || icode == CODE_FOR_dfp_dscri_td)
14178 /* Only allow 6-bit unsigned literals. */
14180 if (TREE_CODE (arg1) != INTEGER_CST
14181 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14183 error ("argument 2 must be a 6-bit unsigned literal");
14184 return CONST0_RTX (tmode);
14187 else if (icode == CODE_FOR_crypto_vshasigmaw
14188 || icode == CODE_FOR_crypto_vshasigmad)
14190 /* Check whether the 2nd and 3rd arguments are integer constants and in
14191 range and prepare arguments. */
14193 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14195 error ("argument 2 must be 0 or 1");
14196 return CONST0_RTX (tmode);
14200 if (TREE_CODE (arg2) != INTEGER_CST
14201 || wi::geu_p (wi::to_wide (arg2), 16))
14203 error ("argument 3 must be in the range [0, 15]");
14204 return CONST0_RTX (tmode);
14209 || GET_MODE (target) != tmode
14210 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14211 target = gen_reg_rtx (tmode);
14213 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14214 op0 = copy_to_mode_reg (mode0, op0);
14215 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14216 op1 = copy_to_mode_reg (mode1, op1);
14217 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14218 op2 = copy_to_mode_reg (mode2, op2);
14220 pat = GEN_FCN (icode) (target, op0, op1, op2);
14229 /* Expand the dst builtins. */
14231 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14234 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14235 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14236 tree arg0, arg1, arg2;
14237 machine_mode mode0, mode1;
14238 rtx pat, op0, op1, op2;
14239 const struct builtin_description *d;
14242 *expandedp = false;
14244 /* Handle DST variants. */
14246 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14247 if (d->code == fcode)
14249 arg0 = CALL_EXPR_ARG (exp, 0);
14250 arg1 = CALL_EXPR_ARG (exp, 1);
14251 arg2 = CALL_EXPR_ARG (exp, 2);
14252 op0 = expand_normal (arg0);
14253 op1 = expand_normal (arg1);
14254 op2 = expand_normal (arg2);
14255 mode0 = insn_data[d->icode].operand[0].mode;
14256 mode1 = insn_data[d->icode].operand[1].mode;
14258 /* Invalid arguments, bail out before generating bad rtl. */
14259 if (arg0 == error_mark_node
14260 || arg1 == error_mark_node
14261 || arg2 == error_mark_node)
14266 if (TREE_CODE (arg2) != INTEGER_CST
14267 || TREE_INT_CST_LOW (arg2) & ~0x3)
14269 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14273 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14274 op0 = copy_to_mode_reg (Pmode, op0);
14275 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14276 op1 = copy_to_mode_reg (mode1, op1);
14278 pat = GEN_FCN (d->icode) (op0, op1, op2);
14288 /* Expand vec_init builtin. */
14290 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14292 machine_mode tmode = TYPE_MODE (type);
14293 machine_mode inner_mode = GET_MODE_INNER (tmode);
14294 int i, n_elt = GET_MODE_NUNITS (tmode);
14296 gcc_assert (VECTOR_MODE_P (tmode));
14297 gcc_assert (n_elt == call_expr_nargs (exp));
14299 if (!target || !register_operand (target, tmode))
14300 target = gen_reg_rtx (tmode);
14302 /* If we have a vector compromised of a single element, such as V1TImode, do
14303 the initialization directly. */
14304 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14306 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14307 emit_move_insn (target, gen_lowpart (tmode, x));
14311 rtvec v = rtvec_alloc (n_elt);
14313 for (i = 0; i < n_elt; ++i)
14315 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14316 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14319 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14325 /* Return the integer constant in ARG. Constrain it to be in the range
14326 of the subparts of VEC_TYPE; issue an error if not. */
14329 get_element_number (tree vec_type, tree arg)
14331 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14333 if (!tree_fits_uhwi_p (arg)
14334 || (elt = tree_to_uhwi (arg), elt > max))
14336 error ("selector must be an integer constant in the range [0, %wi]", max);
14343 /* Expand vec_set builtin. */
14345 altivec_expand_vec_set_builtin (tree exp)
14347 machine_mode tmode, mode1;
14348 tree arg0, arg1, arg2;
14352 arg0 = CALL_EXPR_ARG (exp, 0);
14353 arg1 = CALL_EXPR_ARG (exp, 1);
14354 arg2 = CALL_EXPR_ARG (exp, 2);
14356 tmode = TYPE_MODE (TREE_TYPE (arg0));
14357 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14358 gcc_assert (VECTOR_MODE_P (tmode));
14360 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14361 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14362 elt = get_element_number (TREE_TYPE (arg0), arg2);
14364 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14365 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14367 op0 = force_reg (tmode, op0);
14368 op1 = force_reg (mode1, op1);
14370 rs6000_expand_vector_set (op0, op1, elt);
14375 /* Expand vec_ext builtin. */
14377 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14379 machine_mode tmode, mode0;
14384 arg0 = CALL_EXPR_ARG (exp, 0);
14385 arg1 = CALL_EXPR_ARG (exp, 1);
14387 op0 = expand_normal (arg0);
14388 op1 = expand_normal (arg1);
14390 if (TREE_CODE (arg1) == INTEGER_CST)
14392 unsigned HOST_WIDE_INT elt;
14393 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
14394 unsigned int truncated_selector;
14395 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14396 returns low-order bits of INTEGER_CST for modulo indexing. */
14397 elt = TREE_INT_CST_LOW (arg1);
14398 truncated_selector = elt % size;
14399 op1 = GEN_INT (truncated_selector);
14402 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14403 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14404 gcc_assert (VECTOR_MODE_P (mode0));
14406 op0 = force_reg (mode0, op0);
14408 if (optimize || !target || !register_operand (target, tmode))
14409 target = gen_reg_rtx (tmode);
14411 rs6000_expand_vector_extract (target, op0, op1);
14416 /* Expand the builtin in EXP and store the result in TARGET. Store
14417 true in *EXPANDEDP if we found a builtin to expand. */
14419 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14421 const struct builtin_description *d;
14423 enum insn_code icode;
14424 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14425 tree arg0, arg1, arg2;
14427 machine_mode tmode, mode0;
14428 enum rs6000_builtins fcode
14429 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14431 if (rs6000_overloaded_builtin_p (fcode))
14434 error ("unresolved overload for Altivec builtin %qF", fndecl);
14436 /* Given it is invalid, just generate a normal call. */
14437 return expand_call (exp, target, false);
14440 target = altivec_expand_dst_builtin (exp, target, expandedp);
14448 case ALTIVEC_BUILTIN_STVX_V2DF:
14449 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14450 case ALTIVEC_BUILTIN_STVX_V2DI:
14451 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14452 case ALTIVEC_BUILTIN_STVX_V4SF:
14453 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14454 case ALTIVEC_BUILTIN_STVX:
14455 case ALTIVEC_BUILTIN_STVX_V4SI:
14456 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14457 case ALTIVEC_BUILTIN_STVX_V8HI:
14458 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14459 case ALTIVEC_BUILTIN_STVX_V16QI:
14460 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14461 case ALTIVEC_BUILTIN_STVEBX:
14462 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14463 case ALTIVEC_BUILTIN_STVEHX:
14464 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14465 case ALTIVEC_BUILTIN_STVEWX:
14466 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14467 case ALTIVEC_BUILTIN_STVXL_V2DF:
14468 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14469 case ALTIVEC_BUILTIN_STVXL_V2DI:
14470 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14471 case ALTIVEC_BUILTIN_STVXL_V4SF:
14472 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14473 case ALTIVEC_BUILTIN_STVXL:
14474 case ALTIVEC_BUILTIN_STVXL_V4SI:
14475 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14476 case ALTIVEC_BUILTIN_STVXL_V8HI:
14477 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14478 case ALTIVEC_BUILTIN_STVXL_V16QI:
14479 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14481 case ALTIVEC_BUILTIN_STVLX:
14482 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14483 case ALTIVEC_BUILTIN_STVLXL:
14484 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14485 case ALTIVEC_BUILTIN_STVRX:
14486 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14487 case ALTIVEC_BUILTIN_STVRXL:
14488 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14490 case P9V_BUILTIN_STXVL:
14491 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14493 case P9V_BUILTIN_XST_LEN_R:
14494 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14496 case VSX_BUILTIN_STXVD2X_V1TI:
14497 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14498 case VSX_BUILTIN_STXVD2X_V2DF:
14499 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14500 case VSX_BUILTIN_STXVD2X_V2DI:
14501 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14502 case VSX_BUILTIN_STXVW4X_V4SF:
14503 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14504 case VSX_BUILTIN_STXVW4X_V4SI:
14505 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14506 case VSX_BUILTIN_STXVW4X_V8HI:
14507 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14508 case VSX_BUILTIN_STXVW4X_V16QI:
14509 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14511 /* For the following on big endian, it's ok to use any appropriate
14512 unaligned-supporting store, so use a generic expander. For
14513 little-endian, the exact element-reversing instruction must
14515 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14517 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14518 : CODE_FOR_vsx_st_elemrev_v1ti);
14519 return altivec_expand_stv_builtin (code, exp);
14521 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14523 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14524 : CODE_FOR_vsx_st_elemrev_v2df);
14525 return altivec_expand_stv_builtin (code, exp);
14527 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14529 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14530 : CODE_FOR_vsx_st_elemrev_v2di);
14531 return altivec_expand_stv_builtin (code, exp);
14533 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14535 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14536 : CODE_FOR_vsx_st_elemrev_v4sf);
14537 return altivec_expand_stv_builtin (code, exp);
14539 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14541 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14542 : CODE_FOR_vsx_st_elemrev_v4si);
14543 return altivec_expand_stv_builtin (code, exp);
14545 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14547 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14548 : CODE_FOR_vsx_st_elemrev_v8hi);
14549 return altivec_expand_stv_builtin (code, exp);
14551 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14553 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14554 : CODE_FOR_vsx_st_elemrev_v16qi);
14555 return altivec_expand_stv_builtin (code, exp);
14558 case ALTIVEC_BUILTIN_MFVSCR:
14559 icode = CODE_FOR_altivec_mfvscr;
14560 tmode = insn_data[icode].operand[0].mode;
14563 || GET_MODE (target) != tmode
14564 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14565 target = gen_reg_rtx (tmode);
14567 pat = GEN_FCN (icode) (target);
14573 case ALTIVEC_BUILTIN_MTVSCR:
14574 icode = CODE_FOR_altivec_mtvscr;
14575 arg0 = CALL_EXPR_ARG (exp, 0);
14576 op0 = expand_normal (arg0);
14577 mode0 = insn_data[icode].operand[0].mode;
14579 /* If we got invalid arguments bail out before generating bad rtl. */
14580 if (arg0 == error_mark_node)
14583 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14584 op0 = copy_to_mode_reg (mode0, op0);
14586 pat = GEN_FCN (icode) (op0);
14591 case ALTIVEC_BUILTIN_DSSALL:
14592 emit_insn (gen_altivec_dssall ());
14595 case ALTIVEC_BUILTIN_DSS:
14596 icode = CODE_FOR_altivec_dss;
14597 arg0 = CALL_EXPR_ARG (exp, 0);
14599 op0 = expand_normal (arg0);
14600 mode0 = insn_data[icode].operand[0].mode;
14602 /* If we got invalid arguments bail out before generating bad rtl. */
14603 if (arg0 == error_mark_node)
14606 if (TREE_CODE (arg0) != INTEGER_CST
14607 || TREE_INT_CST_LOW (arg0) & ~0x3)
14609 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14613 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14614 op0 = copy_to_mode_reg (mode0, op0);
14616 emit_insn (gen_altivec_dss (op0));
14619 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14620 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14621 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14622 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14623 case VSX_BUILTIN_VEC_INIT_V2DF:
14624 case VSX_BUILTIN_VEC_INIT_V2DI:
14625 case VSX_BUILTIN_VEC_INIT_V1TI:
14626 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14628 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14629 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14630 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14631 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14632 case VSX_BUILTIN_VEC_SET_V2DF:
14633 case VSX_BUILTIN_VEC_SET_V2DI:
14634 case VSX_BUILTIN_VEC_SET_V1TI:
14635 return altivec_expand_vec_set_builtin (exp);
14637 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14638 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14639 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14640 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14641 case VSX_BUILTIN_VEC_EXT_V2DF:
14642 case VSX_BUILTIN_VEC_EXT_V2DI:
14643 case VSX_BUILTIN_VEC_EXT_V1TI:
14644 return altivec_expand_vec_ext_builtin (exp, target);
14646 case P9V_BUILTIN_VEC_EXTRACT4B:
14647 arg1 = CALL_EXPR_ARG (exp, 1);
14650 /* Generate a normal call if it is invalid. */
14651 if (arg1 == error_mark_node)
14652 return expand_call (exp, target, false);
14654 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14656 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
14657 return expand_call (exp, target, false);
14661 case P9V_BUILTIN_VEC_INSERT4B:
14662 arg2 = CALL_EXPR_ARG (exp, 2);
14665 /* Generate a normal call if it is invalid. */
14666 if (arg2 == error_mark_node)
14667 return expand_call (exp, target, false);
14669 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14671 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
14672 return expand_call (exp, target, false);
14678 /* Fall through. */
14681 /* Expand abs* operations. */
14683 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14684 if (d->code == fcode)
14685 return altivec_expand_abs_builtin (d->icode, exp, target);
14687 /* Expand the AltiVec predicates. */
14688 d = bdesc_altivec_preds;
14689 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14690 if (d->code == fcode)
14691 return altivec_expand_predicate_builtin (d->icode, exp, target);
14693 /* LV* are funky. We initialized them differently. */
14696 case ALTIVEC_BUILTIN_LVSL:
14697 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14698 exp, target, false);
14699 case ALTIVEC_BUILTIN_LVSR:
14700 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14701 exp, target, false);
14702 case ALTIVEC_BUILTIN_LVEBX:
14703 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14704 exp, target, false);
14705 case ALTIVEC_BUILTIN_LVEHX:
14706 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14707 exp, target, false);
14708 case ALTIVEC_BUILTIN_LVEWX:
14709 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14710 exp, target, false);
14711 case ALTIVEC_BUILTIN_LVXL_V2DF:
14712 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14713 exp, target, false);
14714 case ALTIVEC_BUILTIN_LVXL_V2DI:
14715 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14716 exp, target, false);
14717 case ALTIVEC_BUILTIN_LVXL_V4SF:
14718 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14719 exp, target, false);
14720 case ALTIVEC_BUILTIN_LVXL:
14721 case ALTIVEC_BUILTIN_LVXL_V4SI:
14722 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14723 exp, target, false);
14724 case ALTIVEC_BUILTIN_LVXL_V8HI:
14725 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14726 exp, target, false);
14727 case ALTIVEC_BUILTIN_LVXL_V16QI:
14728 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14729 exp, target, false);
14730 case ALTIVEC_BUILTIN_LVX_V1TI:
14731 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14732 exp, target, false);
14733 case ALTIVEC_BUILTIN_LVX_V2DF:
14734 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14735 exp, target, false);
14736 case ALTIVEC_BUILTIN_LVX_V2DI:
14737 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14738 exp, target, false);
14739 case ALTIVEC_BUILTIN_LVX_V4SF:
14740 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14741 exp, target, false);
14742 case ALTIVEC_BUILTIN_LVX:
14743 case ALTIVEC_BUILTIN_LVX_V4SI:
14744 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14745 exp, target, false);
14746 case ALTIVEC_BUILTIN_LVX_V8HI:
14747 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14748 exp, target, false);
14749 case ALTIVEC_BUILTIN_LVX_V16QI:
14750 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14751 exp, target, false);
14752 case ALTIVEC_BUILTIN_LVLX:
14753 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14754 exp, target, true);
14755 case ALTIVEC_BUILTIN_LVLXL:
14756 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14757 exp, target, true);
14758 case ALTIVEC_BUILTIN_LVRX:
14759 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14760 exp, target, true);
14761 case ALTIVEC_BUILTIN_LVRXL:
14762 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14763 exp, target, true);
14764 case VSX_BUILTIN_LXVD2X_V1TI:
14765 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14766 exp, target, false);
14767 case VSX_BUILTIN_LXVD2X_V2DF:
14768 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
14769 exp, target, false);
14770 case VSX_BUILTIN_LXVD2X_V2DI:
14771 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
14772 exp, target, false);
14773 case VSX_BUILTIN_LXVW4X_V4SF:
14774 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
14775 exp, target, false);
14776 case VSX_BUILTIN_LXVW4X_V4SI:
14777 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
14778 exp, target, false);
14779 case VSX_BUILTIN_LXVW4X_V8HI:
14780 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
14781 exp, target, false);
14782 case VSX_BUILTIN_LXVW4X_V16QI:
14783 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
14784 exp, target, false);
14785 /* For the following on big endian, it's ok to use any appropriate
14786 unaligned-supporting load, so use a generic expander. For
14787 little-endian, the exact element-reversing instruction must
14789 case VSX_BUILTIN_LD_ELEMREV_V2DF:
14791 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
14792 : CODE_FOR_vsx_ld_elemrev_v2df);
14793 return altivec_expand_lv_builtin (code, exp, target, false);
14795 case VSX_BUILTIN_LD_ELEMREV_V1TI:
14797 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
14798 : CODE_FOR_vsx_ld_elemrev_v1ti);
14799 return altivec_expand_lv_builtin (code, exp, target, false);
14801 case VSX_BUILTIN_LD_ELEMREV_V2DI:
14803 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
14804 : CODE_FOR_vsx_ld_elemrev_v2di);
14805 return altivec_expand_lv_builtin (code, exp, target, false);
14807 case VSX_BUILTIN_LD_ELEMREV_V4SF:
14809 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
14810 : CODE_FOR_vsx_ld_elemrev_v4sf);
14811 return altivec_expand_lv_builtin (code, exp, target, false);
14813 case VSX_BUILTIN_LD_ELEMREV_V4SI:
14815 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
14816 : CODE_FOR_vsx_ld_elemrev_v4si);
14817 return altivec_expand_lv_builtin (code, exp, target, false);
14819 case VSX_BUILTIN_LD_ELEMREV_V8HI:
14821 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
14822 : CODE_FOR_vsx_ld_elemrev_v8hi);
14823 return altivec_expand_lv_builtin (code, exp, target, false);
14825 case VSX_BUILTIN_LD_ELEMREV_V16QI:
14827 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
14828 : CODE_FOR_vsx_ld_elemrev_v16qi);
14829 return altivec_expand_lv_builtin (code, exp, target, false);
14834 /* Fall through. */
14837 *expandedp = false;
14841 /* Check whether a builtin function is supported in this target
14844 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
14846 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
14847 if ((fnmask & rs6000_builtin_mask) != fnmask)
14853 /* Raise an error message for a builtin function that is called without the
14854 appropriate target options being set. */
14857 rs6000_invalid_builtin (enum rs6000_builtins fncode)
14859 size_t uns_fncode = (size_t) fncode;
14860 const char *name = rs6000_builtin_info[uns_fncode].name;
14861 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
14863 gcc_assert (name != NULL);
14864 if ((fnmask & RS6000_BTM_CELL) != 0)
14865 error ("builtin function %qs is only valid for the cell processor", name);
14866 else if ((fnmask & RS6000_BTM_VSX) != 0)
14867 error ("builtin function %qs requires the %qs option", name, "-mvsx");
14868 else if ((fnmask & RS6000_BTM_HTM) != 0)
14869 error ("builtin function %qs requires the %qs option", name, "-mhtm");
14870 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
14871 error ("builtin function %qs requires the %qs option", name, "-maltivec");
14872 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14873 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14874 error ("builtin function %qs requires the %qs and %qs options",
14875 name, "-mhard-dfp", "-mpower8-vector");
14876 else if ((fnmask & RS6000_BTM_DFP) != 0)
14877 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
14878 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
14879 error ("builtin function %qs requires the %qs option", name,
14880 "-mpower8-vector");
14881 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14882 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14883 error ("builtin function %qs requires the %qs and %qs options",
14884 name, "-mcpu=power9", "-m64");
14885 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
14886 error ("builtin function %qs requires the %qs option", name,
14888 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14889 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14890 error ("builtin function %qs requires the %qs and %qs options",
14891 name, "-mcpu=power9", "-m64");
14892 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
14893 error ("builtin function %qs requires the %qs option", name,
14895 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
14897 if (!TARGET_HARD_FLOAT)
14898 error ("builtin function %qs requires the %qs option", name,
14901 error ("builtin function %qs requires the %qs option", name,
14902 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
14904 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
14905 error ("builtin function %qs requires the %qs option", name,
14907 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
14908 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
14910 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
14911 error ("builtin function %qs requires the %qs option", name,
14913 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14914 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14915 error ("builtin function %qs requires the %qs (or newer), and "
14916 "%qs or %qs options",
14917 name, "-mcpu=power7", "-m64", "-mpowerpc64");
14919 error ("builtin function %qs is not supported with the current options",
14923 /* Target hook for early folding of built-ins, shamelessly stolen
14927 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
14928 int n_args ATTRIBUTE_UNUSED,
14929 tree *args ATTRIBUTE_UNUSED,
14930 bool ignore ATTRIBUTE_UNUSED)
14932 #ifdef SUBTARGET_FOLD_BUILTIN
14933 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
14939 /* Helper function to sort out which built-ins may be valid without having
14942 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
14946 case ALTIVEC_BUILTIN_STVX_V16QI:
14947 case ALTIVEC_BUILTIN_STVX_V8HI:
14948 case ALTIVEC_BUILTIN_STVX_V4SI:
14949 case ALTIVEC_BUILTIN_STVX_V4SF:
14950 case ALTIVEC_BUILTIN_STVX_V2DI:
14951 case ALTIVEC_BUILTIN_STVX_V2DF:
14952 case VSX_BUILTIN_STXVW4X_V16QI:
14953 case VSX_BUILTIN_STXVW4X_V8HI:
14954 case VSX_BUILTIN_STXVW4X_V4SF:
14955 case VSX_BUILTIN_STXVW4X_V4SI:
14956 case VSX_BUILTIN_STXVD2X_V2DF:
14957 case VSX_BUILTIN_STXVD2X_V2DI:
14964 /* Helper function to handle the gimple folding of a vector compare
14965 operation. This sets up true/false vectors, and uses the
14966 VEC_COND_EXPR operation.
14967 CODE indicates which comparison is to be made. (EQ, GT, ...).
14968 TYPE indicates the type of the result. */
14970 fold_build_vec_cmp (tree_code code, tree type,
14971 tree arg0, tree arg1)
14973 tree cmp_type = build_same_sized_truth_vector_type (type);
14974 tree zero_vec = build_zero_cst (type);
14975 tree minus_one_vec = build_minus_one_cst (type);
14976 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
14977 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
14980 /* Helper function to handle the in-between steps for the
14981 vector compare built-ins. */
14983 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
14985 tree arg0 = gimple_call_arg (stmt, 0);
14986 tree arg1 = gimple_call_arg (stmt, 1);
14987 tree lhs = gimple_call_lhs (stmt);
14988 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
14989 gimple *g = gimple_build_assign (lhs, cmp);
14990 gimple_set_location (g, gimple_location (stmt));
14991 gsi_replace (gsi, g, true);
14994 /* Helper function to map V2DF and V4SF types to their
14995 integral equivalents (V2DI and V4SI). */
14996 tree map_to_integral_tree_type (tree input_tree_type)
14998 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
14999 return input_tree_type;
15002 if (types_compatible_p (TREE_TYPE (input_tree_type),
15003 TREE_TYPE (V2DF_type_node)))
15004 return V2DI_type_node;
15005 else if (types_compatible_p (TREE_TYPE (input_tree_type),
15006 TREE_TYPE (V4SF_type_node)))
15007 return V4SI_type_node;
15009 gcc_unreachable ();
15013 /* Helper function to handle the vector merge[hl] built-ins. The
15014 implementation difference between h and l versions for this code are in
15015 the values used when building of the permute vector for high word versus
15016 low word merge. The variance is keyed off the use_high parameter. */
15018 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15020 tree arg0 = gimple_call_arg (stmt, 0);
15021 tree arg1 = gimple_call_arg (stmt, 1);
15022 tree lhs = gimple_call_lhs (stmt);
15023 tree lhs_type = TREE_TYPE (lhs);
15024 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15025 int midpoint = n_elts / 2;
15031 /* The permute_type will match the lhs for integral types. For double and
15032 float types, the permute type needs to map to the V2 or V4 type that
15035 permute_type = map_to_integral_tree_type (lhs_type);
15036 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15038 for (int i = 0; i < midpoint; i++)
15040 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15042 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15043 offset + n_elts + i));
15046 tree permute = elts.build ();
15048 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15049 gimple_set_location (g, gimple_location (stmt));
15050 gsi_replace (gsi, g, true);
15053 /* Helper function to handle the vector merge[eo] built-ins. */
15055 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15057 tree arg0 = gimple_call_arg (stmt, 0);
15058 tree arg1 = gimple_call_arg (stmt, 1);
15059 tree lhs = gimple_call_lhs (stmt);
15060 tree lhs_type = TREE_TYPE (lhs);
15061 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15063 /* The permute_type will match the lhs for integral types. For double and
15064 float types, the permute type needs to map to the V2 or V4 type that
15067 permute_type = map_to_integral_tree_type (lhs_type);
15069 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15071 /* Build the permute vector. */
15072 for (int i = 0; i < n_elts / 2; i++)
15074 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15076 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15077 2*i + use_odd + n_elts));
15080 tree permute = elts.build ();
15082 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15083 gimple_set_location (g, gimple_location (stmt));
15084 gsi_replace (gsi, g, true);
15087 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15088 a constant, use rs6000_fold_builtin.) */
15091 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15093 gimple *stmt = gsi_stmt (*gsi);
15094 tree fndecl = gimple_call_fndecl (stmt);
15095 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15096 enum rs6000_builtins fn_code
15097 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15098 tree arg0, arg1, lhs, temp;
15099 enum tree_code bcode;
15102 size_t uns_fncode = (size_t) fn_code;
15103 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15104 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15105 const char *fn_name2 = (icode != CODE_FOR_nothing)
15106 ? get_insn_name ((int) icode)
15109 if (TARGET_DEBUG_BUILTIN)
15110 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15111 fn_code, fn_name1, fn_name2);
15113 if (!rs6000_fold_gimple)
15116 /* Prevent gimple folding for code that does not have a LHS, unless it is
15117 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15118 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15121 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15122 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15123 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15129 /* Flavors of vec_add. We deliberately don't expand
15130 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15131 TImode, resulting in much poorer code generation. */
15132 case ALTIVEC_BUILTIN_VADDUBM:
15133 case ALTIVEC_BUILTIN_VADDUHM:
15134 case ALTIVEC_BUILTIN_VADDUWM:
15135 case P8V_BUILTIN_VADDUDM:
15136 case ALTIVEC_BUILTIN_VADDFP:
15137 case VSX_BUILTIN_XVADDDP:
15140 arg0 = gimple_call_arg (stmt, 0);
15141 arg1 = gimple_call_arg (stmt, 1);
15142 lhs = gimple_call_lhs (stmt);
15143 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
15144 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
15146 /* Ensure the binary operation is performed in a type
15147 that wraps if it is integral type. */
15148 gimple_seq stmts = NULL;
15149 tree type = unsigned_type_for (TREE_TYPE (lhs));
15150 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15152 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15154 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
15155 type, uarg0, uarg1);
15156 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15157 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
15158 build1 (VIEW_CONVERT_EXPR,
15159 TREE_TYPE (lhs), res));
15160 gsi_replace (gsi, g, true);
15163 g = gimple_build_assign (lhs, bcode, arg0, arg1);
15164 gimple_set_location (g, gimple_location (stmt));
15165 gsi_replace (gsi, g, true);
15167 /* Flavors of vec_sub. We deliberately don't expand
15168 P8V_BUILTIN_VSUBUQM. */
15169 case ALTIVEC_BUILTIN_VSUBUBM:
15170 case ALTIVEC_BUILTIN_VSUBUHM:
15171 case ALTIVEC_BUILTIN_VSUBUWM:
15172 case P8V_BUILTIN_VSUBUDM:
15173 case ALTIVEC_BUILTIN_VSUBFP:
15174 case VSX_BUILTIN_XVSUBDP:
15175 bcode = MINUS_EXPR;
15177 case VSX_BUILTIN_XVMULSP:
15178 case VSX_BUILTIN_XVMULDP:
15179 arg0 = gimple_call_arg (stmt, 0);
15180 arg1 = gimple_call_arg (stmt, 1);
15181 lhs = gimple_call_lhs (stmt);
15182 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15183 gimple_set_location (g, gimple_location (stmt));
15184 gsi_replace (gsi, g, true);
15186 /* Even element flavors of vec_mul (signed). */
15187 case ALTIVEC_BUILTIN_VMULESB:
15188 case ALTIVEC_BUILTIN_VMULESH:
15189 case P8V_BUILTIN_VMULESW:
15190 /* Even element flavors of vec_mul (unsigned). */
15191 case ALTIVEC_BUILTIN_VMULEUB:
15192 case ALTIVEC_BUILTIN_VMULEUH:
15193 case P8V_BUILTIN_VMULEUW:
15194 arg0 = gimple_call_arg (stmt, 0);
15195 arg1 = gimple_call_arg (stmt, 1);
15196 lhs = gimple_call_lhs (stmt);
15197 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15198 gimple_set_location (g, gimple_location (stmt));
15199 gsi_replace (gsi, g, true);
15201 /* Odd element flavors of vec_mul (signed). */
15202 case ALTIVEC_BUILTIN_VMULOSB:
15203 case ALTIVEC_BUILTIN_VMULOSH:
15204 case P8V_BUILTIN_VMULOSW:
15205 /* Odd element flavors of vec_mul (unsigned). */
15206 case ALTIVEC_BUILTIN_VMULOUB:
15207 case ALTIVEC_BUILTIN_VMULOUH:
15208 case P8V_BUILTIN_VMULOUW:
15209 arg0 = gimple_call_arg (stmt, 0);
15210 arg1 = gimple_call_arg (stmt, 1);
15211 lhs = gimple_call_lhs (stmt);
15212 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15213 gimple_set_location (g, gimple_location (stmt));
15214 gsi_replace (gsi, g, true);
15216 /* Flavors of vec_div (Integer). */
15217 case VSX_BUILTIN_DIV_V2DI:
15218 case VSX_BUILTIN_UDIV_V2DI:
15219 arg0 = gimple_call_arg (stmt, 0);
15220 arg1 = gimple_call_arg (stmt, 1);
15221 lhs = gimple_call_lhs (stmt);
15222 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15223 gimple_set_location (g, gimple_location (stmt));
15224 gsi_replace (gsi, g, true);
15226 /* Flavors of vec_div (Float). */
15227 case VSX_BUILTIN_XVDIVSP:
15228 case VSX_BUILTIN_XVDIVDP:
15229 arg0 = gimple_call_arg (stmt, 0);
15230 arg1 = gimple_call_arg (stmt, 1);
15231 lhs = gimple_call_lhs (stmt);
15232 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15233 gimple_set_location (g, gimple_location (stmt));
15234 gsi_replace (gsi, g, true);
15236 /* Flavors of vec_and. */
15237 case ALTIVEC_BUILTIN_VAND:
15238 arg0 = gimple_call_arg (stmt, 0);
15239 arg1 = gimple_call_arg (stmt, 1);
15240 lhs = gimple_call_lhs (stmt);
15241 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15242 gimple_set_location (g, gimple_location (stmt));
15243 gsi_replace (gsi, g, true);
15245 /* Flavors of vec_andc. */
15246 case ALTIVEC_BUILTIN_VANDC:
15247 arg0 = gimple_call_arg (stmt, 0);
15248 arg1 = gimple_call_arg (stmt, 1);
15249 lhs = gimple_call_lhs (stmt);
15250 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15251 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15252 gimple_set_location (g, gimple_location (stmt));
15253 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15254 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15255 gimple_set_location (g, gimple_location (stmt));
15256 gsi_replace (gsi, g, true);
15258 /* Flavors of vec_nand. */
15259 case P8V_BUILTIN_VEC_NAND:
15260 case P8V_BUILTIN_NAND_V16QI:
15261 case P8V_BUILTIN_NAND_V8HI:
15262 case P8V_BUILTIN_NAND_V4SI:
15263 case P8V_BUILTIN_NAND_V4SF:
15264 case P8V_BUILTIN_NAND_V2DF:
15265 case P8V_BUILTIN_NAND_V2DI:
15266 arg0 = gimple_call_arg (stmt, 0);
15267 arg1 = gimple_call_arg (stmt, 1);
15268 lhs = gimple_call_lhs (stmt);
15269 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15270 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15271 gimple_set_location (g, gimple_location (stmt));
15272 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15273 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15274 gimple_set_location (g, gimple_location (stmt));
15275 gsi_replace (gsi, g, true);
15277 /* Flavors of vec_or. */
15278 case ALTIVEC_BUILTIN_VOR:
15279 arg0 = gimple_call_arg (stmt, 0);
15280 arg1 = gimple_call_arg (stmt, 1);
15281 lhs = gimple_call_lhs (stmt);
15282 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15283 gimple_set_location (g, gimple_location (stmt));
15284 gsi_replace (gsi, g, true);
15286 /* flavors of vec_orc. */
15287 case P8V_BUILTIN_ORC_V16QI:
15288 case P8V_BUILTIN_ORC_V8HI:
15289 case P8V_BUILTIN_ORC_V4SI:
15290 case P8V_BUILTIN_ORC_V4SF:
15291 case P8V_BUILTIN_ORC_V2DF:
15292 case P8V_BUILTIN_ORC_V2DI:
15293 arg0 = gimple_call_arg (stmt, 0);
15294 arg1 = gimple_call_arg (stmt, 1);
15295 lhs = gimple_call_lhs (stmt);
15296 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15297 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15298 gimple_set_location (g, gimple_location (stmt));
15299 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15300 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15301 gimple_set_location (g, gimple_location (stmt));
15302 gsi_replace (gsi, g, true);
15304 /* Flavors of vec_xor. */
15305 case ALTIVEC_BUILTIN_VXOR:
15306 arg0 = gimple_call_arg (stmt, 0);
15307 arg1 = gimple_call_arg (stmt, 1);
15308 lhs = gimple_call_lhs (stmt);
15309 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15310 gimple_set_location (g, gimple_location (stmt));
15311 gsi_replace (gsi, g, true);
15313 /* Flavors of vec_nor. */
15314 case ALTIVEC_BUILTIN_VNOR:
15315 arg0 = gimple_call_arg (stmt, 0);
15316 arg1 = gimple_call_arg (stmt, 1);
15317 lhs = gimple_call_lhs (stmt);
15318 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15319 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15320 gimple_set_location (g, gimple_location (stmt));
15321 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15322 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15323 gimple_set_location (g, gimple_location (stmt));
15324 gsi_replace (gsi, g, true);
15326 /* flavors of vec_abs. */
15327 case ALTIVEC_BUILTIN_ABS_V16QI:
15328 case ALTIVEC_BUILTIN_ABS_V8HI:
15329 case ALTIVEC_BUILTIN_ABS_V4SI:
15330 case ALTIVEC_BUILTIN_ABS_V4SF:
15331 case P8V_BUILTIN_ABS_V2DI:
15332 case VSX_BUILTIN_XVABSDP:
15333 arg0 = gimple_call_arg (stmt, 0);
15334 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15335 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15337 lhs = gimple_call_lhs (stmt);
15338 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15339 gimple_set_location (g, gimple_location (stmt));
15340 gsi_replace (gsi, g, true);
15342 /* flavors of vec_min. */
15343 case VSX_BUILTIN_XVMINDP:
15344 case P8V_BUILTIN_VMINSD:
15345 case P8V_BUILTIN_VMINUD:
15346 case ALTIVEC_BUILTIN_VMINSB:
15347 case ALTIVEC_BUILTIN_VMINSH:
15348 case ALTIVEC_BUILTIN_VMINSW:
15349 case ALTIVEC_BUILTIN_VMINUB:
15350 case ALTIVEC_BUILTIN_VMINUH:
15351 case ALTIVEC_BUILTIN_VMINUW:
15352 case ALTIVEC_BUILTIN_VMINFP:
15353 arg0 = gimple_call_arg (stmt, 0);
15354 arg1 = gimple_call_arg (stmt, 1);
15355 lhs = gimple_call_lhs (stmt);
15356 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15357 gimple_set_location (g, gimple_location (stmt));
15358 gsi_replace (gsi, g, true);
15360 /* flavors of vec_max. */
15361 case VSX_BUILTIN_XVMAXDP:
15362 case P8V_BUILTIN_VMAXSD:
15363 case P8V_BUILTIN_VMAXUD:
15364 case ALTIVEC_BUILTIN_VMAXSB:
15365 case ALTIVEC_BUILTIN_VMAXSH:
15366 case ALTIVEC_BUILTIN_VMAXSW:
15367 case ALTIVEC_BUILTIN_VMAXUB:
15368 case ALTIVEC_BUILTIN_VMAXUH:
15369 case ALTIVEC_BUILTIN_VMAXUW:
15370 case ALTIVEC_BUILTIN_VMAXFP:
15371 arg0 = gimple_call_arg (stmt, 0);
15372 arg1 = gimple_call_arg (stmt, 1);
15373 lhs = gimple_call_lhs (stmt);
15374 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15375 gimple_set_location (g, gimple_location (stmt));
15376 gsi_replace (gsi, g, true);
15378 /* Flavors of vec_eqv. */
15379 case P8V_BUILTIN_EQV_V16QI:
15380 case P8V_BUILTIN_EQV_V8HI:
15381 case P8V_BUILTIN_EQV_V4SI:
15382 case P8V_BUILTIN_EQV_V4SF:
15383 case P8V_BUILTIN_EQV_V2DF:
15384 case P8V_BUILTIN_EQV_V2DI:
15385 arg0 = gimple_call_arg (stmt, 0);
15386 arg1 = gimple_call_arg (stmt, 1);
15387 lhs = gimple_call_lhs (stmt);
15388 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15389 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15390 gimple_set_location (g, gimple_location (stmt));
15391 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15392 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15393 gimple_set_location (g, gimple_location (stmt));
15394 gsi_replace (gsi, g, true);
15396 /* Flavors of vec_rotate_left. */
15397 case ALTIVEC_BUILTIN_VRLB:
15398 case ALTIVEC_BUILTIN_VRLH:
15399 case ALTIVEC_BUILTIN_VRLW:
15400 case P8V_BUILTIN_VRLD:
15401 arg0 = gimple_call_arg (stmt, 0);
15402 arg1 = gimple_call_arg (stmt, 1);
15403 lhs = gimple_call_lhs (stmt);
15404 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15405 gimple_set_location (g, gimple_location (stmt));
15406 gsi_replace (gsi, g, true);
15408 /* Flavors of vector shift right algebraic.
15409 vec_sra{b,h,w} -> vsra{b,h,w}. */
15410 case ALTIVEC_BUILTIN_VSRAB:
15411 case ALTIVEC_BUILTIN_VSRAH:
15412 case ALTIVEC_BUILTIN_VSRAW:
15413 case P8V_BUILTIN_VSRAD:
15415 arg0 = gimple_call_arg (stmt, 0);
15416 arg1 = gimple_call_arg (stmt, 1);
15417 lhs = gimple_call_lhs (stmt);
15418 tree arg1_type = TREE_TYPE (arg1);
15419 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15420 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15421 location_t loc = gimple_location (stmt);
15422 /* Force arg1 into the range valid matching the arg0 type. */
15423 /* Build a vector consisting of the max valid bit-size values. */
15424 int n_elts = VECTOR_CST_NELTS (arg1);
15425 tree element_size = build_int_cst (unsigned_element_type,
15427 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15428 for (int i = 0; i < n_elts; i++)
15429 elts.safe_push (element_size);
15430 tree modulo_tree = elts.build ();
15431 /* Modulo the provided shift value against that vector. */
15432 gimple_seq stmts = NULL;
15433 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15434 unsigned_arg1_type, arg1);
15435 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15436 unsigned_arg1_type, unsigned_arg1,
15438 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15439 /* And finally, do the shift. */
15440 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
15441 gimple_set_location (g, loc);
15442 gsi_replace (gsi, g, true);
15445 /* Flavors of vector shift left.
15446 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15447 case ALTIVEC_BUILTIN_VSLB:
15448 case ALTIVEC_BUILTIN_VSLH:
15449 case ALTIVEC_BUILTIN_VSLW:
15450 case P8V_BUILTIN_VSLD:
15453 gimple_seq stmts = NULL;
15454 arg0 = gimple_call_arg (stmt, 0);
15455 tree arg0_type = TREE_TYPE (arg0);
15456 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15457 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15459 arg1 = gimple_call_arg (stmt, 1);
15460 tree arg1_type = TREE_TYPE (arg1);
15461 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15462 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15463 loc = gimple_location (stmt);
15464 lhs = gimple_call_lhs (stmt);
15465 /* Force arg1 into the range valid matching the arg0 type. */
15466 /* Build a vector consisting of the max valid bit-size values. */
15467 int n_elts = VECTOR_CST_NELTS (arg1);
15468 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15470 tree element_size = build_int_cst (unsigned_element_type,
15471 tree_size_in_bits / n_elts);
15472 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15473 for (int i = 0; i < n_elts; i++)
15474 elts.safe_push (element_size);
15475 tree modulo_tree = elts.build ();
15476 /* Modulo the provided shift value against that vector. */
15477 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15478 unsigned_arg1_type, arg1);
15479 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15480 unsigned_arg1_type, unsigned_arg1,
15482 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15483 /* And finally, do the shift. */
15484 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15485 gimple_set_location (g, gimple_location (stmt));
15486 gsi_replace (gsi, g, true);
15489 /* Flavors of vector shift right. */
15490 case ALTIVEC_BUILTIN_VSRB:
15491 case ALTIVEC_BUILTIN_VSRH:
15492 case ALTIVEC_BUILTIN_VSRW:
15493 case P8V_BUILTIN_VSRD:
15495 arg0 = gimple_call_arg (stmt, 0);
15496 arg1 = gimple_call_arg (stmt, 1);
15497 lhs = gimple_call_lhs (stmt);
15498 tree arg1_type = TREE_TYPE (arg1);
15499 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15500 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15501 location_t loc = gimple_location (stmt);
15502 gimple_seq stmts = NULL;
15503 /* Convert arg0 to unsigned. */
15505 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15506 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15507 /* Force arg1 into the range valid matching the arg0 type. */
15508 /* Build a vector consisting of the max valid bit-size values. */
15509 int n_elts = VECTOR_CST_NELTS (arg1);
15510 tree element_size = build_int_cst (unsigned_element_type,
15512 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15513 for (int i = 0; i < n_elts; i++)
15514 elts.safe_push (element_size);
15515 tree modulo_tree = elts.build ();
15516 /* Modulo the provided shift value against that vector. */
15517 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15518 unsigned_arg1_type, arg1);
15519 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15520 unsigned_arg1_type, unsigned_arg1,
15522 /* Do the shift. */
15524 = gimple_build (&stmts, RSHIFT_EXPR,
15525 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
15526 /* Convert result back to the lhs type. */
15527 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15528 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15529 update_call_from_tree (gsi, res);
15532 /* Vector loads. */
15533 case ALTIVEC_BUILTIN_LVX_V16QI:
15534 case ALTIVEC_BUILTIN_LVX_V8HI:
15535 case ALTIVEC_BUILTIN_LVX_V4SI:
15536 case ALTIVEC_BUILTIN_LVX_V4SF:
15537 case ALTIVEC_BUILTIN_LVX_V2DI:
15538 case ALTIVEC_BUILTIN_LVX_V2DF:
15539 case ALTIVEC_BUILTIN_LVX_V1TI:
15541 arg0 = gimple_call_arg (stmt, 0); // offset
15542 arg1 = gimple_call_arg (stmt, 1); // address
15543 lhs = gimple_call_lhs (stmt);
15544 location_t loc = gimple_location (stmt);
15545 /* Since arg1 may be cast to a different type, just use ptr_type_node
15546 here instead of trying to enforce TBAA on pointer types. */
15547 tree arg1_type = ptr_type_node;
15548 tree lhs_type = TREE_TYPE (lhs);
15549 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15550 the tree using the value from arg0. The resulting type will match
15551 the type of arg1. */
15552 gimple_seq stmts = NULL;
15553 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15554 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15555 arg1_type, arg1, temp_offset);
15556 /* Mask off any lower bits from the address. */
15557 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15558 arg1_type, temp_addr,
15559 build_int_cst (arg1_type, -16));
15560 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15561 if (!is_gimple_mem_ref_addr (aligned_addr))
15563 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15564 gimple *g = gimple_build_assign (t, aligned_addr);
15565 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15568 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15569 take an offset, but since we've already incorporated the offset
15570 above, here we just pass in a zero. */
15572 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15573 build_int_cst (arg1_type, 0)));
15574 gimple_set_location (g, loc);
15575 gsi_replace (gsi, g, true);
15578 /* Vector stores. */
15579 case ALTIVEC_BUILTIN_STVX_V16QI:
15580 case ALTIVEC_BUILTIN_STVX_V8HI:
15581 case ALTIVEC_BUILTIN_STVX_V4SI:
15582 case ALTIVEC_BUILTIN_STVX_V4SF:
15583 case ALTIVEC_BUILTIN_STVX_V2DI:
15584 case ALTIVEC_BUILTIN_STVX_V2DF:
15586 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15587 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15588 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15589 location_t loc = gimple_location (stmt);
15590 tree arg0_type = TREE_TYPE (arg0);
15591 /* Use ptr_type_node (no TBAA) for the arg2_type.
15592 FIXME: (Richard) "A proper fix would be to transition this type as
15593 seen from the frontend to GIMPLE, for example in a similar way we
15594 do for MEM_REFs by piggy-backing that on an extra argument, a
15595 constant zero pointer of the alias pointer type to use (which would
15596 also serve as a type indicator of the store itself). I'd use a
15597 target specific internal function for this (not sure if we can have
15598 those target specific, but I guess if it's folded away then that's
15599 fine) and get away with the overload set." */
15600 tree arg2_type = ptr_type_node;
15601 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15602 the tree using the value from arg0. The resulting type will match
15603 the type of arg2. */
15604 gimple_seq stmts = NULL;
15605 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15606 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15607 arg2_type, arg2, temp_offset);
15608 /* Mask off any lower bits from the address. */
15609 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15610 arg2_type, temp_addr,
15611 build_int_cst (arg2_type, -16));
15612 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15613 if (!is_gimple_mem_ref_addr (aligned_addr))
15615 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15616 gimple *g = gimple_build_assign (t, aligned_addr);
15617 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15620 /* The desired gimple result should be similar to:
15621 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15623 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15624 build_int_cst (arg2_type, 0)), arg0);
15625 gimple_set_location (g, loc);
15626 gsi_replace (gsi, g, true);
15630 /* unaligned Vector loads. */
15631 case VSX_BUILTIN_LXVW4X_V16QI:
15632 case VSX_BUILTIN_LXVW4X_V8HI:
15633 case VSX_BUILTIN_LXVW4X_V4SF:
15634 case VSX_BUILTIN_LXVW4X_V4SI:
15635 case VSX_BUILTIN_LXVD2X_V2DF:
15636 case VSX_BUILTIN_LXVD2X_V2DI:
15638 arg0 = gimple_call_arg (stmt, 0); // offset
15639 arg1 = gimple_call_arg (stmt, 1); // address
15640 lhs = gimple_call_lhs (stmt);
15641 location_t loc = gimple_location (stmt);
15642 /* Since arg1 may be cast to a different type, just use ptr_type_node
15643 here instead of trying to enforce TBAA on pointer types. */
15644 tree arg1_type = ptr_type_node;
15645 tree lhs_type = TREE_TYPE (lhs);
15646 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15647 required alignment (power) is 4 bytes regardless of data type. */
15648 tree align_ltype = build_aligned_type (lhs_type, 4);
15649 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15650 the tree using the value from arg0. The resulting type will match
15651 the type of arg1. */
15652 gimple_seq stmts = NULL;
15653 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15654 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15655 arg1_type, arg1, temp_offset);
15656 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15657 if (!is_gimple_mem_ref_addr (temp_addr))
15659 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15660 gimple *g = gimple_build_assign (t, temp_addr);
15661 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15664 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15665 take an offset, but since we've already incorporated the offset
15666 above, here we just pass in a zero. */
15668 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15669 build_int_cst (arg1_type, 0)));
15670 gimple_set_location (g, loc);
15671 gsi_replace (gsi, g, true);
15675 /* unaligned Vector stores. */
15676 case VSX_BUILTIN_STXVW4X_V16QI:
15677 case VSX_BUILTIN_STXVW4X_V8HI:
15678 case VSX_BUILTIN_STXVW4X_V4SF:
15679 case VSX_BUILTIN_STXVW4X_V4SI:
15680 case VSX_BUILTIN_STXVD2X_V2DF:
15681 case VSX_BUILTIN_STXVD2X_V2DI:
15683 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15684 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15685 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15686 location_t loc = gimple_location (stmt);
15687 tree arg0_type = TREE_TYPE (arg0);
15688 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15689 tree arg2_type = ptr_type_node;
15690 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15691 required alignment (power) is 4 bytes regardless of data type. */
15692 tree align_stype = build_aligned_type (arg0_type, 4);
15693 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15694 the tree using the value from arg1. */
15695 gimple_seq stmts = NULL;
15696 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15697 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15698 arg2_type, arg2, temp_offset);
15699 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15700 if (!is_gimple_mem_ref_addr (temp_addr))
15702 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15703 gimple *g = gimple_build_assign (t, temp_addr);
15704 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15708 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15709 build_int_cst (arg2_type, 0)), arg0);
15710 gimple_set_location (g, loc);
15711 gsi_replace (gsi, g, true);
15715 /* Vector Fused multiply-add (fma). */
15716 case ALTIVEC_BUILTIN_VMADDFP:
15717 case VSX_BUILTIN_XVMADDDP:
15718 case ALTIVEC_BUILTIN_VMLADDUHM:
15720 arg0 = gimple_call_arg (stmt, 0);
15721 arg1 = gimple_call_arg (stmt, 1);
15722 tree arg2 = gimple_call_arg (stmt, 2);
15723 lhs = gimple_call_lhs (stmt);
15724 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15725 gimple_call_set_lhs (g, lhs);
15726 gimple_call_set_nothrow (g, true);
15727 gimple_set_location (g, gimple_location (stmt));
15728 gsi_replace (gsi, g, true);
15732 /* Vector compares; EQ, NE, GE, GT, LE. */
15733 case ALTIVEC_BUILTIN_VCMPEQUB:
15734 case ALTIVEC_BUILTIN_VCMPEQUH:
15735 case ALTIVEC_BUILTIN_VCMPEQUW:
15736 case P8V_BUILTIN_VCMPEQUD:
15737 fold_compare_helper (gsi, EQ_EXPR, stmt);
15740 case P9V_BUILTIN_CMPNEB:
15741 case P9V_BUILTIN_CMPNEH:
15742 case P9V_BUILTIN_CMPNEW:
15743 fold_compare_helper (gsi, NE_EXPR, stmt);
15746 case VSX_BUILTIN_CMPGE_16QI:
15747 case VSX_BUILTIN_CMPGE_U16QI:
15748 case VSX_BUILTIN_CMPGE_8HI:
15749 case VSX_BUILTIN_CMPGE_U8HI:
15750 case VSX_BUILTIN_CMPGE_4SI:
15751 case VSX_BUILTIN_CMPGE_U4SI:
15752 case VSX_BUILTIN_CMPGE_2DI:
15753 case VSX_BUILTIN_CMPGE_U2DI:
15754 fold_compare_helper (gsi, GE_EXPR, stmt);
15757 case ALTIVEC_BUILTIN_VCMPGTSB:
15758 case ALTIVEC_BUILTIN_VCMPGTUB:
15759 case ALTIVEC_BUILTIN_VCMPGTSH:
15760 case ALTIVEC_BUILTIN_VCMPGTUH:
15761 case ALTIVEC_BUILTIN_VCMPGTSW:
15762 case ALTIVEC_BUILTIN_VCMPGTUW:
15763 case P8V_BUILTIN_VCMPGTUD:
15764 case P8V_BUILTIN_VCMPGTSD:
15765 fold_compare_helper (gsi, GT_EXPR, stmt);
15768 case VSX_BUILTIN_CMPLE_16QI:
15769 case VSX_BUILTIN_CMPLE_U16QI:
15770 case VSX_BUILTIN_CMPLE_8HI:
15771 case VSX_BUILTIN_CMPLE_U8HI:
15772 case VSX_BUILTIN_CMPLE_4SI:
15773 case VSX_BUILTIN_CMPLE_U4SI:
15774 case VSX_BUILTIN_CMPLE_2DI:
15775 case VSX_BUILTIN_CMPLE_U2DI:
15776 fold_compare_helper (gsi, LE_EXPR, stmt);
15779 /* flavors of vec_splat_[us]{8,16,32}. */
15780 case ALTIVEC_BUILTIN_VSPLTISB:
15781 case ALTIVEC_BUILTIN_VSPLTISH:
15782 case ALTIVEC_BUILTIN_VSPLTISW:
15784 arg0 = gimple_call_arg (stmt, 0);
15785 lhs = gimple_call_lhs (stmt);
15787 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15788 5-bit signed constant in range -16 to +15. */
15789 if (TREE_CODE (arg0) != INTEGER_CST
15790 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
15792 gimple_seq stmts = NULL;
15793 location_t loc = gimple_location (stmt);
15794 tree splat_value = gimple_convert (&stmts, loc,
15795 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15796 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15797 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15798 g = gimple_build_assign (lhs, splat_tree);
15799 gimple_set_location (g, gimple_location (stmt));
15800 gsi_replace (gsi, g, true);
15804 /* Flavors of vec_splat. */
15805 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15806 case ALTIVEC_BUILTIN_VSPLTB:
15807 case ALTIVEC_BUILTIN_VSPLTH:
15808 case ALTIVEC_BUILTIN_VSPLTW:
15809 case VSX_BUILTIN_XXSPLTD_V2DI:
15810 case VSX_BUILTIN_XXSPLTD_V2DF:
15812 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15813 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15814 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15815 is a valid index into the arg0 vector. */
15816 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15817 if (TREE_CODE (arg1) != INTEGER_CST
15818 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15820 lhs = gimple_call_lhs (stmt);
15821 tree lhs_type = TREE_TYPE (lhs);
15822 tree arg0_type = TREE_TYPE (arg0);
15824 if (TREE_CODE (arg0) == VECTOR_CST)
15825 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15828 /* Determine (in bits) the length and start location of the
15829 splat value for a call to the tree_vec_extract helper. */
15830 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15831 * BITS_PER_UNIT / n_elts;
15832 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15833 tree len = build_int_cst (bitsizetype, splat_elem_size);
15834 tree start = build_int_cst (bitsizetype, splat_start_bit);
15835 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15838 /* And finally, build the new vector. */
15839 tree splat_tree = build_vector_from_val (lhs_type, splat);
15840 g = gimple_build_assign (lhs, splat_tree);
15841 gimple_set_location (g, gimple_location (stmt));
15842 gsi_replace (gsi, g, true);
15846 /* vec_mergel (integrals). */
15847 case ALTIVEC_BUILTIN_VMRGLH:
15848 case ALTIVEC_BUILTIN_VMRGLW:
15849 case VSX_BUILTIN_XXMRGLW_4SI:
15850 case ALTIVEC_BUILTIN_VMRGLB:
15851 case VSX_BUILTIN_VEC_MERGEL_V2DI:
15852 case VSX_BUILTIN_XXMRGLW_4SF:
15853 case VSX_BUILTIN_VEC_MERGEL_V2DF:
15854 fold_mergehl_helper (gsi, stmt, 1);
15856 /* vec_mergeh (integrals). */
15857 case ALTIVEC_BUILTIN_VMRGHH:
15858 case ALTIVEC_BUILTIN_VMRGHW:
15859 case VSX_BUILTIN_XXMRGHW_4SI:
15860 case ALTIVEC_BUILTIN_VMRGHB:
15861 case VSX_BUILTIN_VEC_MERGEH_V2DI:
15862 case VSX_BUILTIN_XXMRGHW_4SF:
15863 case VSX_BUILTIN_VEC_MERGEH_V2DF:
15864 fold_mergehl_helper (gsi, stmt, 0);
15867 /* Flavors of vec_mergee. */
15868 case P8V_BUILTIN_VMRGEW_V4SI:
15869 case P8V_BUILTIN_VMRGEW_V2DI:
15870 case P8V_BUILTIN_VMRGEW_V4SF:
15871 case P8V_BUILTIN_VMRGEW_V2DF:
15872 fold_mergeeo_helper (gsi, stmt, 0);
15874 /* Flavors of vec_mergeo. */
15875 case P8V_BUILTIN_VMRGOW_V4SI:
15876 case P8V_BUILTIN_VMRGOW_V2DI:
15877 case P8V_BUILTIN_VMRGOW_V4SF:
15878 case P8V_BUILTIN_VMRGOW_V2DF:
15879 fold_mergeeo_helper (gsi, stmt, 1);
15882 /* d = vec_pack (a, b) */
15883 case P8V_BUILTIN_VPKUDUM:
15884 case ALTIVEC_BUILTIN_VPKUHUM:
15885 case ALTIVEC_BUILTIN_VPKUWUM:
15887 arg0 = gimple_call_arg (stmt, 0);
15888 arg1 = gimple_call_arg (stmt, 1);
15889 lhs = gimple_call_lhs (stmt);
15890 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
15891 gimple_set_location (g, gimple_location (stmt));
15892 gsi_replace (gsi, g, true);
15896 /* d = vec_unpackh (a) */
15897 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
15898 in this code is sensitive to endian-ness, and needs to be inverted to
15899 handle both LE and BE targets. */
15900 case ALTIVEC_BUILTIN_VUPKHSB:
15901 case ALTIVEC_BUILTIN_VUPKHSH:
15902 case P8V_BUILTIN_VUPKHSW:
15904 arg0 = gimple_call_arg (stmt, 0);
15905 lhs = gimple_call_lhs (stmt);
15906 if (BYTES_BIG_ENDIAN)
15907 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15909 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15910 gimple_set_location (g, gimple_location (stmt));
15911 gsi_replace (gsi, g, true);
15914 /* d = vec_unpackl (a) */
15915 case ALTIVEC_BUILTIN_VUPKLSB:
15916 case ALTIVEC_BUILTIN_VUPKLSH:
15917 case P8V_BUILTIN_VUPKLSW:
15919 arg0 = gimple_call_arg (stmt, 0);
15920 lhs = gimple_call_lhs (stmt);
15921 if (BYTES_BIG_ENDIAN)
15922 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15924 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15925 gimple_set_location (g, gimple_location (stmt));
15926 gsi_replace (gsi, g, true);
15929 /* There is no gimple type corresponding with pixel, so just return. */
15930 case ALTIVEC_BUILTIN_VUPKHPX:
15931 case ALTIVEC_BUILTIN_VUPKLPX:
15935 case ALTIVEC_BUILTIN_VPERM_16QI:
15936 case ALTIVEC_BUILTIN_VPERM_8HI:
15937 case ALTIVEC_BUILTIN_VPERM_4SI:
15938 case ALTIVEC_BUILTIN_VPERM_2DI:
15939 case ALTIVEC_BUILTIN_VPERM_4SF:
15940 case ALTIVEC_BUILTIN_VPERM_2DF:
15942 arg0 = gimple_call_arg (stmt, 0);
15943 arg1 = gimple_call_arg (stmt, 1);
15944 tree permute = gimple_call_arg (stmt, 2);
15945 lhs = gimple_call_lhs (stmt);
15946 location_t loc = gimple_location (stmt);
15947 gimple_seq stmts = NULL;
15948 // convert arg0 and arg1 to match the type of the permute
15949 // for the VEC_PERM_EXPR operation.
15950 tree permute_type = (TREE_TYPE (permute));
15951 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
15952 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
15953 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
15954 permute_type, arg0_ptype, arg1_ptype,
15956 // Convert the result back to the desired lhs type upon completion.
15957 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
15958 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15959 g = gimple_build_assign (lhs, temp);
15960 gimple_set_location (g, loc);
15961 gsi_replace (gsi, g, true);
15966 if (TARGET_DEBUG_BUILTIN)
15967 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
15968 fn_code, fn_name1, fn_name2);
15975 /* Expand an expression EXP that calls a built-in function,
15976 with result going to TARGET if that's convenient
15977 (and in mode MODE if that's convenient).
15978 SUBTARGET may be used as the target for computing one of EXP's operands.
15979 IGNORE is nonzero if the value is to be ignored. */
15982 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15983 machine_mode mode ATTRIBUTE_UNUSED,
15984 int ignore ATTRIBUTE_UNUSED)
15986 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15987 enum rs6000_builtins fcode
15988 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
15989 size_t uns_fcode = (size_t)fcode;
15990 const struct builtin_description *d;
15994 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
15995 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
15996 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
15998 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
15999 floating point type, depending on whether long double is the IBM extended
16000 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16001 we only define one variant of the built-in function, and switch the code
16002 when defining it, rather than defining two built-ins and using the
16003 overload table in rs6000-c.c to switch between the two. If we don't have
16004 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16005 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16006 if (FLOAT128_IEEE_P (TFmode))
16012 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16013 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16014 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16015 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16016 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16017 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16018 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16019 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16020 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16021 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16022 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16023 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16024 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16027 if (TARGET_DEBUG_BUILTIN)
16029 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16030 const char *name2 = (icode != CODE_FOR_nothing)
16031 ? get_insn_name ((int) icode)
16035 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16037 default: name3 = "unknown"; break;
16038 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16039 case RS6000_BTC_UNARY: name3 = "unary"; break;
16040 case RS6000_BTC_BINARY: name3 = "binary"; break;
16041 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16042 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16043 case RS6000_BTC_ABS: name3 = "abs"; break;
16044 case RS6000_BTC_DST: name3 = "dst"; break;
16049 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16050 (name1) ? name1 : "---", fcode,
16051 (name2) ? name2 : "---", (int) icode,
16053 func_valid_p ? "" : ", not valid");
16058 rs6000_invalid_builtin (fcode);
16060 /* Given it is invalid, just generate a normal call. */
16061 return expand_call (exp, target, ignore);
16066 case RS6000_BUILTIN_RECIP:
16067 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16069 case RS6000_BUILTIN_RECIPF:
16070 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16072 case RS6000_BUILTIN_RSQRTF:
16073 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16075 case RS6000_BUILTIN_RSQRT:
16076 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16078 case POWER7_BUILTIN_BPERMD:
16079 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16080 ? CODE_FOR_bpermd_di
16081 : CODE_FOR_bpermd_si), exp, target);
16083 case RS6000_BUILTIN_GET_TB:
16084 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16087 case RS6000_BUILTIN_MFTB:
16088 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16089 ? CODE_FOR_rs6000_mftb_di
16090 : CODE_FOR_rs6000_mftb_si),
16093 case RS6000_BUILTIN_MFFS:
16094 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16096 case RS6000_BUILTIN_MTFSB0:
16097 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16099 case RS6000_BUILTIN_MTFSB1:
16100 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16102 case RS6000_BUILTIN_SET_FPSCR_RN:
16103 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16106 case RS6000_BUILTIN_SET_FPSCR_DRN:
16108 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16111 case RS6000_BUILTIN_MFFSL:
16112 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16114 case RS6000_BUILTIN_MTFSF:
16115 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16117 case RS6000_BUILTIN_CPU_INIT:
16118 case RS6000_BUILTIN_CPU_IS:
16119 case RS6000_BUILTIN_CPU_SUPPORTS:
16120 return cpu_expand_builtin (fcode, exp, target);
16122 case MISC_BUILTIN_SPEC_BARRIER:
16124 emit_insn (gen_speculation_barrier ());
16128 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16129 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16131 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16132 : (int) CODE_FOR_altivec_lvsl_direct);
16133 machine_mode tmode = insn_data[icode2].operand[0].mode;
16134 machine_mode mode = insn_data[icode2].operand[1].mode;
16138 gcc_assert (TARGET_ALTIVEC);
16140 arg = CALL_EXPR_ARG (exp, 0);
16141 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16142 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16143 addr = memory_address (mode, op);
16144 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16148 /* For the load case need to negate the address. */
16149 op = gen_reg_rtx (GET_MODE (addr));
16150 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16152 op = gen_rtx_MEM (mode, op);
16155 || GET_MODE (target) != tmode
16156 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16157 target = gen_reg_rtx (tmode);
16159 pat = GEN_FCN (icode2) (target, op);
16167 case ALTIVEC_BUILTIN_VCFUX:
16168 case ALTIVEC_BUILTIN_VCFSX:
16169 case ALTIVEC_BUILTIN_VCTUXS:
16170 case ALTIVEC_BUILTIN_VCTSXS:
16171 /* FIXME: There's got to be a nicer way to handle this case than
16172 constructing a new CALL_EXPR. */
16173 if (call_expr_nargs (exp) == 1)
16175 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16176 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16180 /* For the pack and unpack int128 routines, fix up the builtin so it
16181 uses the correct IBM128 type. */
16182 case MISC_BUILTIN_PACK_IF:
16183 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16185 icode = CODE_FOR_packtf;
16186 fcode = MISC_BUILTIN_PACK_TF;
16187 uns_fcode = (size_t)fcode;
16191 case MISC_BUILTIN_UNPACK_IF:
16192 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16194 icode = CODE_FOR_unpacktf;
16195 fcode = MISC_BUILTIN_UNPACK_TF;
16196 uns_fcode = (size_t)fcode;
16204 if (TARGET_ALTIVEC)
16206 ret = altivec_expand_builtin (exp, target, &success);
16213 ret = htm_expand_builtin (exp, target, &success);
16219 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16220 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16221 gcc_assert (attr == RS6000_BTC_UNARY
16222 || attr == RS6000_BTC_BINARY
16223 || attr == RS6000_BTC_TERNARY
16224 || attr == RS6000_BTC_SPECIAL);
16226 /* Handle simple unary operations. */
16228 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16229 if (d->code == fcode)
16230 return rs6000_expand_unop_builtin (icode, exp, target);
16232 /* Handle simple binary operations. */
16234 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16235 if (d->code == fcode)
16236 return rs6000_expand_binop_builtin (icode, exp, target);
16238 /* Handle simple ternary operations. */
16240 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16241 if (d->code == fcode)
16242 return rs6000_expand_ternop_builtin (icode, exp, target);
16244 /* Handle simple no-argument operations. */
16246 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16247 if (d->code == fcode)
16248 return rs6000_expand_zeroop_builtin (icode, target);
16250 gcc_unreachable ();
16253 /* Create a builtin vector type with a name. Taking care not to give
16254 the canonical type a name. */
16257 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16259 tree result = build_vector_type (elt_type, num_elts);
16261 /* Copy so we don't give the canonical type a name. */
16262 result = build_variant_type_copy (result);
16264 add_builtin_type (name, result);
16270 rs6000_init_builtins (void)
16276 if (TARGET_DEBUG_BUILTIN)
16277 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16278 (TARGET_ALTIVEC) ? ", altivec" : "",
16279 (TARGET_VSX) ? ", vsx" : "");
16281 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16282 : "__vector long long",
16283 intDI_type_node, 2);
16284 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16285 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16286 intSI_type_node, 4);
16287 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16288 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16289 intHI_type_node, 8);
16290 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16291 intQI_type_node, 16);
16293 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16294 unsigned_intQI_type_node, 16);
16295 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16296 unsigned_intHI_type_node, 8);
16297 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16298 unsigned_intSI_type_node, 4);
16299 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16300 ? "__vector unsigned long"
16301 : "__vector unsigned long long",
16302 unsigned_intDI_type_node, 2);
16304 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16306 const_str_type_node
16307 = build_pointer_type (build_qualified_type (char_type_node,
16310 /* We use V1TI mode as a special container to hold __int128_t items that
16311 must live in VSX registers. */
16312 if (intTI_type_node)
16314 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16315 intTI_type_node, 1);
16316 unsigned_V1TI_type_node
16317 = rs6000_vector_type ("__vector unsigned __int128",
16318 unsigned_intTI_type_node, 1);
16321 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16322 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16323 'vector unsigned short'. */
16325 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16326 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16327 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16328 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16329 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16331 long_integer_type_internal_node = long_integer_type_node;
16332 long_unsigned_type_internal_node = long_unsigned_type_node;
16333 long_long_integer_type_internal_node = long_long_integer_type_node;
16334 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16335 intQI_type_internal_node = intQI_type_node;
16336 uintQI_type_internal_node = unsigned_intQI_type_node;
16337 intHI_type_internal_node = intHI_type_node;
16338 uintHI_type_internal_node = unsigned_intHI_type_node;
16339 intSI_type_internal_node = intSI_type_node;
16340 uintSI_type_internal_node = unsigned_intSI_type_node;
16341 intDI_type_internal_node = intDI_type_node;
16342 uintDI_type_internal_node = unsigned_intDI_type_node;
16343 intTI_type_internal_node = intTI_type_node;
16344 uintTI_type_internal_node = unsigned_intTI_type_node;
16345 float_type_internal_node = float_type_node;
16346 double_type_internal_node = double_type_node;
16347 long_double_type_internal_node = long_double_type_node;
16348 dfloat64_type_internal_node = dfloat64_type_node;
16349 dfloat128_type_internal_node = dfloat128_type_node;
16350 void_type_internal_node = void_type_node;
16352 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16353 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16354 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16355 format that uses a pair of doubles, depending on the switches and
16358 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16359 floating point, we need make sure the type is non-zero or else self-test
16360 fails during bootstrap.
16362 Always create __ibm128 as a separate type, even if the current long double
16363 format is IBM extended double.
16365 For IEEE 128-bit floating point, always create the type __ieee128. If the
16366 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16368 if (TARGET_FLOAT128_TYPE)
16370 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16371 ibm128_float_type_node = long_double_type_node;
16374 ibm128_float_type_node = make_node (REAL_TYPE);
16375 TYPE_PRECISION (ibm128_float_type_node) = 128;
16376 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16377 layout_type (ibm128_float_type_node);
16380 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16383 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16384 ieee128_float_type_node = long_double_type_node;
16386 ieee128_float_type_node = float128_type_node;
16388 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16393 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16395 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16397 builtin_mode_to_type[QImode][0] = integer_type_node;
16398 builtin_mode_to_type[HImode][0] = integer_type_node;
16399 builtin_mode_to_type[SImode][0] = intSI_type_node;
16400 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16401 builtin_mode_to_type[DImode][0] = intDI_type_node;
16402 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16403 builtin_mode_to_type[TImode][0] = intTI_type_node;
16404 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16405 builtin_mode_to_type[SFmode][0] = float_type_node;
16406 builtin_mode_to_type[DFmode][0] = double_type_node;
16407 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16408 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16409 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16410 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16411 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16412 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16413 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16414 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16415 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16416 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16417 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16418 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16419 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16420 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16421 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16422 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16423 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16425 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16426 TYPE_NAME (bool_char_type_node) = tdecl;
16428 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16429 TYPE_NAME (bool_short_type_node) = tdecl;
16431 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16432 TYPE_NAME (bool_int_type_node) = tdecl;
16434 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16435 TYPE_NAME (pixel_type_node) = tdecl;
16437 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16438 bool_char_type_node, 16);
16439 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16440 bool_short_type_node, 8);
16441 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16442 bool_int_type_node, 4);
16443 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16444 ? "__vector __bool long"
16445 : "__vector __bool long long",
16446 bool_long_long_type_node, 2);
16447 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16448 pixel_type_node, 8);
16450 /* Create Altivec and VSX builtins on machines with at least the
16451 general purpose extensions (970 and newer) to allow the use of
16452 the target attribute. */
16453 if (TARGET_EXTRA_BUILTINS)
16454 altivec_init_builtins ();
16456 htm_init_builtins ();
16458 if (TARGET_EXTRA_BUILTINS)
16459 rs6000_common_init_builtins ();
16461 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16462 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16463 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16465 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16466 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16467 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16469 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16470 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16471 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16473 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16474 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16475 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16477 mode = (TARGET_64BIT) ? DImode : SImode;
16478 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16479 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16480 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16482 ftype = build_function_type_list (unsigned_intDI_type_node,
16484 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16487 ftype = build_function_type_list (unsigned_intDI_type_node,
16490 ftype = build_function_type_list (unsigned_intSI_type_node,
16492 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16494 ftype = build_function_type_list (double_type_node, NULL_TREE);
16495 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16497 ftype = build_function_type_list (double_type_node, NULL_TREE);
16498 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16500 ftype = build_function_type_list (void_type_node,
16503 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16505 ftype = build_function_type_list (void_type_node,
16508 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16510 ftype = build_function_type_list (void_type_node,
16513 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16515 ftype = build_function_type_list (void_type_node,
16518 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16520 ftype = build_function_type_list (void_type_node,
16521 intSI_type_node, double_type_node,
16523 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16525 ftype = build_function_type_list (void_type_node, NULL_TREE);
16526 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16527 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16528 MISC_BUILTIN_SPEC_BARRIER);
16530 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16532 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16533 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16535 /* AIX libm provides clog as __clog. */
16536 if (TARGET_XCOFF &&
16537 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16538 set_user_assembler_name (tdecl, "__clog");
16540 #ifdef SUBTARGET_INIT_BUILTINS
16541 SUBTARGET_INIT_BUILTINS;
16545 /* Returns the rs6000 builtin decl for CODE. */
16548 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16550 HOST_WIDE_INT fnmask;
16552 if (code >= RS6000_BUILTIN_COUNT)
16553 return error_mark_node;
16555 fnmask = rs6000_builtin_info[code].mask;
16556 if ((fnmask & rs6000_builtin_mask) != fnmask)
16558 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16559 return error_mark_node;
16562 return rs6000_builtin_decls[code];
16566 altivec_init_builtins (void)
16568 const struct builtin_description *d;
16572 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16574 tree pvoid_type_node = build_pointer_type (void_type_node);
16576 tree pcvoid_type_node
16577 = build_pointer_type (build_qualified_type (void_type_node,
16580 tree int_ftype_opaque
16581 = build_function_type_list (integer_type_node,
16582 opaque_V4SI_type_node, NULL_TREE);
16583 tree opaque_ftype_opaque
16584 = build_function_type_list (integer_type_node, NULL_TREE);
16585 tree opaque_ftype_opaque_int
16586 = build_function_type_list (opaque_V4SI_type_node,
16587 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16588 tree opaque_ftype_opaque_opaque_int
16589 = build_function_type_list (opaque_V4SI_type_node,
16590 opaque_V4SI_type_node, opaque_V4SI_type_node,
16591 integer_type_node, NULL_TREE);
16592 tree opaque_ftype_opaque_opaque_opaque
16593 = build_function_type_list (opaque_V4SI_type_node,
16594 opaque_V4SI_type_node, opaque_V4SI_type_node,
16595 opaque_V4SI_type_node, NULL_TREE);
16596 tree opaque_ftype_opaque_opaque
16597 = build_function_type_list (opaque_V4SI_type_node,
16598 opaque_V4SI_type_node, opaque_V4SI_type_node,
16600 tree int_ftype_int_opaque_opaque
16601 = build_function_type_list (integer_type_node,
16602 integer_type_node, opaque_V4SI_type_node,
16603 opaque_V4SI_type_node, NULL_TREE);
16604 tree int_ftype_int_v4si_v4si
16605 = build_function_type_list (integer_type_node,
16606 integer_type_node, V4SI_type_node,
16607 V4SI_type_node, NULL_TREE);
16608 tree int_ftype_int_v2di_v2di
16609 = build_function_type_list (integer_type_node,
16610 integer_type_node, V2DI_type_node,
16611 V2DI_type_node, NULL_TREE);
16612 tree void_ftype_v4si
16613 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16614 tree v8hi_ftype_void
16615 = build_function_type_list (V8HI_type_node, NULL_TREE);
16616 tree void_ftype_void
16617 = build_function_type_list (void_type_node, NULL_TREE);
16618 tree void_ftype_int
16619 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16621 tree opaque_ftype_long_pcvoid
16622 = build_function_type_list (opaque_V4SI_type_node,
16623 long_integer_type_node, pcvoid_type_node,
16625 tree v16qi_ftype_long_pcvoid
16626 = build_function_type_list (V16QI_type_node,
16627 long_integer_type_node, pcvoid_type_node,
16629 tree v8hi_ftype_long_pcvoid
16630 = build_function_type_list (V8HI_type_node,
16631 long_integer_type_node, pcvoid_type_node,
16633 tree v4si_ftype_long_pcvoid
16634 = build_function_type_list (V4SI_type_node,
16635 long_integer_type_node, pcvoid_type_node,
16637 tree v4sf_ftype_long_pcvoid
16638 = build_function_type_list (V4SF_type_node,
16639 long_integer_type_node, pcvoid_type_node,
16641 tree v2df_ftype_long_pcvoid
16642 = build_function_type_list (V2DF_type_node,
16643 long_integer_type_node, pcvoid_type_node,
16645 tree v2di_ftype_long_pcvoid
16646 = build_function_type_list (V2DI_type_node,
16647 long_integer_type_node, pcvoid_type_node,
16649 tree v1ti_ftype_long_pcvoid
16650 = build_function_type_list (V1TI_type_node,
16651 long_integer_type_node, pcvoid_type_node,
16654 tree void_ftype_opaque_long_pvoid
16655 = build_function_type_list (void_type_node,
16656 opaque_V4SI_type_node, long_integer_type_node,
16657 pvoid_type_node, NULL_TREE);
16658 tree void_ftype_v4si_long_pvoid
16659 = build_function_type_list (void_type_node,
16660 V4SI_type_node, long_integer_type_node,
16661 pvoid_type_node, NULL_TREE);
16662 tree void_ftype_v16qi_long_pvoid
16663 = build_function_type_list (void_type_node,
16664 V16QI_type_node, long_integer_type_node,
16665 pvoid_type_node, NULL_TREE);
16667 tree void_ftype_v16qi_pvoid_long
16668 = build_function_type_list (void_type_node,
16669 V16QI_type_node, pvoid_type_node,
16670 long_integer_type_node, NULL_TREE);
16672 tree void_ftype_v8hi_long_pvoid
16673 = build_function_type_list (void_type_node,
16674 V8HI_type_node, long_integer_type_node,
16675 pvoid_type_node, NULL_TREE);
16676 tree void_ftype_v4sf_long_pvoid
16677 = build_function_type_list (void_type_node,
16678 V4SF_type_node, long_integer_type_node,
16679 pvoid_type_node, NULL_TREE);
16680 tree void_ftype_v2df_long_pvoid
16681 = build_function_type_list (void_type_node,
16682 V2DF_type_node, long_integer_type_node,
16683 pvoid_type_node, NULL_TREE);
16684 tree void_ftype_v1ti_long_pvoid
16685 = build_function_type_list (void_type_node,
16686 V1TI_type_node, long_integer_type_node,
16687 pvoid_type_node, NULL_TREE);
16688 tree void_ftype_v2di_long_pvoid
16689 = build_function_type_list (void_type_node,
16690 V2DI_type_node, long_integer_type_node,
16691 pvoid_type_node, NULL_TREE);
16692 tree int_ftype_int_v8hi_v8hi
16693 = build_function_type_list (integer_type_node,
16694 integer_type_node, V8HI_type_node,
16695 V8HI_type_node, NULL_TREE);
16696 tree int_ftype_int_v16qi_v16qi
16697 = build_function_type_list (integer_type_node,
16698 integer_type_node, V16QI_type_node,
16699 V16QI_type_node, NULL_TREE);
16700 tree int_ftype_int_v4sf_v4sf
16701 = build_function_type_list (integer_type_node,
16702 integer_type_node, V4SF_type_node,
16703 V4SF_type_node, NULL_TREE);
16704 tree int_ftype_int_v2df_v2df
16705 = build_function_type_list (integer_type_node,
16706 integer_type_node, V2DF_type_node,
16707 V2DF_type_node, NULL_TREE);
16708 tree v2di_ftype_v2di
16709 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16710 tree v4si_ftype_v4si
16711 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16712 tree v8hi_ftype_v8hi
16713 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16714 tree v16qi_ftype_v16qi
16715 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16716 tree v4sf_ftype_v4sf
16717 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16718 tree v2df_ftype_v2df
16719 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16720 tree void_ftype_pcvoid_int_int
16721 = build_function_type_list (void_type_node,
16722 pcvoid_type_node, integer_type_node,
16723 integer_type_node, NULL_TREE);
16725 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16726 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16727 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16728 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16729 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16730 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16731 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16732 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16733 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16734 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16735 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16736 ALTIVEC_BUILTIN_LVXL_V2DF);
16737 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16738 ALTIVEC_BUILTIN_LVXL_V2DI);
16739 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16740 ALTIVEC_BUILTIN_LVXL_V4SF);
16741 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16742 ALTIVEC_BUILTIN_LVXL_V4SI);
16743 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16744 ALTIVEC_BUILTIN_LVXL_V8HI);
16745 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16746 ALTIVEC_BUILTIN_LVXL_V16QI);
16747 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16748 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16749 ALTIVEC_BUILTIN_LVX_V1TI);
16750 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16751 ALTIVEC_BUILTIN_LVX_V2DF);
16752 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16753 ALTIVEC_BUILTIN_LVX_V2DI);
16754 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16755 ALTIVEC_BUILTIN_LVX_V4SF);
16756 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16757 ALTIVEC_BUILTIN_LVX_V4SI);
16758 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16759 ALTIVEC_BUILTIN_LVX_V8HI);
16760 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16761 ALTIVEC_BUILTIN_LVX_V16QI);
16762 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16763 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16764 ALTIVEC_BUILTIN_STVX_V2DF);
16765 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16766 ALTIVEC_BUILTIN_STVX_V2DI);
16767 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16768 ALTIVEC_BUILTIN_STVX_V4SF);
16769 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16770 ALTIVEC_BUILTIN_STVX_V4SI);
16771 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16772 ALTIVEC_BUILTIN_STVX_V8HI);
16773 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16774 ALTIVEC_BUILTIN_STVX_V16QI);
16775 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16776 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16777 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16778 ALTIVEC_BUILTIN_STVXL_V2DF);
16779 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16780 ALTIVEC_BUILTIN_STVXL_V2DI);
16781 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16782 ALTIVEC_BUILTIN_STVXL_V4SF);
16783 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16784 ALTIVEC_BUILTIN_STVXL_V4SI);
16785 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16786 ALTIVEC_BUILTIN_STVXL_V8HI);
16787 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16788 ALTIVEC_BUILTIN_STVXL_V16QI);
16789 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16790 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16791 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16792 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16793 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16794 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16795 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16796 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16797 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16798 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16799 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16800 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16801 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16802 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16803 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16804 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16806 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16807 VSX_BUILTIN_LXVD2X_V2DF);
16808 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16809 VSX_BUILTIN_LXVD2X_V2DI);
16810 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16811 VSX_BUILTIN_LXVW4X_V4SF);
16812 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16813 VSX_BUILTIN_LXVW4X_V4SI);
16814 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16815 VSX_BUILTIN_LXVW4X_V8HI);
16816 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16817 VSX_BUILTIN_LXVW4X_V16QI);
16818 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16819 VSX_BUILTIN_STXVD2X_V2DF);
16820 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16821 VSX_BUILTIN_STXVD2X_V2DI);
16822 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16823 VSX_BUILTIN_STXVW4X_V4SF);
16824 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16825 VSX_BUILTIN_STXVW4X_V4SI);
16826 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16827 VSX_BUILTIN_STXVW4X_V8HI);
16828 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16829 VSX_BUILTIN_STXVW4X_V16QI);
16831 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16832 VSX_BUILTIN_LD_ELEMREV_V2DF);
16833 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16834 VSX_BUILTIN_LD_ELEMREV_V2DI);
16835 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16836 VSX_BUILTIN_LD_ELEMREV_V4SF);
16837 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16838 VSX_BUILTIN_LD_ELEMREV_V4SI);
16839 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16840 VSX_BUILTIN_LD_ELEMREV_V8HI);
16841 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16842 VSX_BUILTIN_LD_ELEMREV_V16QI);
16843 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16844 VSX_BUILTIN_ST_ELEMREV_V2DF);
16845 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16846 VSX_BUILTIN_ST_ELEMREV_V1TI);
16847 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16848 VSX_BUILTIN_ST_ELEMREV_V2DI);
16849 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16850 VSX_BUILTIN_ST_ELEMREV_V4SF);
16851 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16852 VSX_BUILTIN_ST_ELEMREV_V4SI);
16853 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16854 VSX_BUILTIN_ST_ELEMREV_V8HI);
16855 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16856 VSX_BUILTIN_ST_ELEMREV_V16QI);
16858 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16859 VSX_BUILTIN_VEC_LD);
16860 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16861 VSX_BUILTIN_VEC_ST);
16862 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16863 VSX_BUILTIN_VEC_XL);
16864 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16865 VSX_BUILTIN_VEC_XL_BE);
16866 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16867 VSX_BUILTIN_VEC_XST);
16868 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16869 VSX_BUILTIN_VEC_XST_BE);
16871 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16872 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16873 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16875 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16876 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16877 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16878 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16879 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16880 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16881 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16882 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16883 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16884 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16885 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16886 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16888 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16889 ALTIVEC_BUILTIN_VEC_ADDE);
16890 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16891 ALTIVEC_BUILTIN_VEC_ADDEC);
16892 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16893 ALTIVEC_BUILTIN_VEC_CMPNE);
16894 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16895 ALTIVEC_BUILTIN_VEC_MUL);
16896 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16897 ALTIVEC_BUILTIN_VEC_SUBE);
16898 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16899 ALTIVEC_BUILTIN_VEC_SUBEC);
16901 /* Cell builtins. */
16902 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16903 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16904 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16905 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16907 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16908 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16909 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16910 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16912 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16913 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16914 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16915 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16917 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16918 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16919 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16920 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16922 if (TARGET_P9_VECTOR)
16924 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16925 P9V_BUILTIN_STXVL);
16926 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16927 P9V_BUILTIN_XST_LEN_R);
16930 /* Add the DST variants. */
16932 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16934 HOST_WIDE_INT mask = d->mask;
16936 /* It is expected that these dst built-in functions may have
16937 d->icode equal to CODE_FOR_nothing. */
16938 if ((mask & builtin_mask) != mask)
16940 if (TARGET_DEBUG_BUILTIN)
16941 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16945 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16948 /* Initialize the predicates. */
16949 d = bdesc_altivec_preds;
16950 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16952 machine_mode mode1;
16954 HOST_WIDE_INT mask = d->mask;
16956 if ((mask & builtin_mask) != mask)
16958 if (TARGET_DEBUG_BUILTIN)
16959 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16964 if (rs6000_overloaded_builtin_p (d->code))
16968 /* Cannot define builtin if the instruction is disabled. */
16969 gcc_assert (d->icode != CODE_FOR_nothing);
16970 mode1 = insn_data[d->icode].operand[1].mode;
16976 type = int_ftype_int_opaque_opaque;
16979 type = int_ftype_int_v2di_v2di;
16982 type = int_ftype_int_v4si_v4si;
16985 type = int_ftype_int_v8hi_v8hi;
16988 type = int_ftype_int_v16qi_v16qi;
16991 type = int_ftype_int_v4sf_v4sf;
16994 type = int_ftype_int_v2df_v2df;
16997 gcc_unreachable ();
17000 def_builtin (d->name, type, d->code);
17003 /* Initialize the abs* operators. */
17005 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17007 machine_mode mode0;
17009 HOST_WIDE_INT mask = d->mask;
17011 if ((mask & builtin_mask) != mask)
17013 if (TARGET_DEBUG_BUILTIN)
17014 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17019 /* Cannot define builtin if the instruction is disabled. */
17020 gcc_assert (d->icode != CODE_FOR_nothing);
17021 mode0 = insn_data[d->icode].operand[0].mode;
17026 type = v2di_ftype_v2di;
17029 type = v4si_ftype_v4si;
17032 type = v8hi_ftype_v8hi;
17035 type = v16qi_ftype_v16qi;
17038 type = v4sf_ftype_v4sf;
17041 type = v2df_ftype_v2df;
17044 gcc_unreachable ();
17047 def_builtin (d->name, type, d->code);
17050 /* Initialize target builtin that implements
17051 targetm.vectorize.builtin_mask_for_load. */
17053 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17054 v16qi_ftype_long_pcvoid,
17055 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17056 BUILT_IN_MD, NULL, NULL_TREE);
17057 TREE_READONLY (decl) = 1;
17058 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17059 altivec_builtin_mask_for_load = decl;
17061 /* Access to the vec_init patterns. */
17062 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17063 integer_type_node, integer_type_node,
17064 integer_type_node, NULL_TREE);
17065 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17067 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17068 short_integer_type_node,
17069 short_integer_type_node,
17070 short_integer_type_node,
17071 short_integer_type_node,
17072 short_integer_type_node,
17073 short_integer_type_node,
17074 short_integer_type_node, NULL_TREE);
17075 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17077 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17078 char_type_node, char_type_node,
17079 char_type_node, char_type_node,
17080 char_type_node, char_type_node,
17081 char_type_node, char_type_node,
17082 char_type_node, char_type_node,
17083 char_type_node, char_type_node,
17084 char_type_node, char_type_node,
17085 char_type_node, NULL_TREE);
17086 def_builtin ("__builtin_vec_init_v16qi", ftype,
17087 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17089 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17090 float_type_node, float_type_node,
17091 float_type_node, NULL_TREE);
17092 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17094 /* VSX builtins. */
17095 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17096 double_type_node, NULL_TREE);
17097 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17099 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17100 intDI_type_node, NULL_TREE);
17101 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17103 /* Access to the vec_set patterns. */
17104 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17106 integer_type_node, NULL_TREE);
17107 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17109 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17111 integer_type_node, NULL_TREE);
17112 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17114 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17116 integer_type_node, NULL_TREE);
17117 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17119 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17121 integer_type_node, NULL_TREE);
17122 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17124 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17126 integer_type_node, NULL_TREE);
17127 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17129 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17131 integer_type_node, NULL_TREE);
17132 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17134 /* Access to the vec_extract patterns. */
17135 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17136 integer_type_node, NULL_TREE);
17137 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17139 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17140 integer_type_node, NULL_TREE);
17141 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17143 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17144 integer_type_node, NULL_TREE);
17145 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17147 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17148 integer_type_node, NULL_TREE);
17149 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17151 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17152 integer_type_node, NULL_TREE);
17153 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17155 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17156 integer_type_node, NULL_TREE);
17157 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17160 if (V1TI_type_node)
17162 tree v1ti_ftype_long_pcvoid
17163 = build_function_type_list (V1TI_type_node,
17164 long_integer_type_node, pcvoid_type_node,
17166 tree void_ftype_v1ti_long_pvoid
17167 = build_function_type_list (void_type_node,
17168 V1TI_type_node, long_integer_type_node,
17169 pvoid_type_node, NULL_TREE);
17170 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17171 VSX_BUILTIN_LD_ELEMREV_V1TI);
17172 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17173 VSX_BUILTIN_LXVD2X_V1TI);
17174 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17175 VSX_BUILTIN_STXVD2X_V1TI);
17176 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17177 NULL_TREE, NULL_TREE);
17178 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17179 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17181 integer_type_node, NULL_TREE);
17182 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17183 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17184 integer_type_node, NULL_TREE);
17185 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17191 htm_init_builtins (void)
17193 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17194 const struct builtin_description *d;
17198 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17200 tree op[MAX_HTM_OPERANDS], type;
17201 HOST_WIDE_INT mask = d->mask;
17202 unsigned attr = rs6000_builtin_info[d->code].attr;
17203 bool void_func = (attr & RS6000_BTC_VOID);
17204 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17206 tree gpr_type_node;
17210 /* It is expected that these htm built-in functions may have
17211 d->icode equal to CODE_FOR_nothing. */
17213 if (TARGET_32BIT && TARGET_POWERPC64)
17214 gpr_type_node = long_long_unsigned_type_node;
17216 gpr_type_node = long_unsigned_type_node;
17218 if (attr & RS6000_BTC_SPR)
17220 rettype = gpr_type_node;
17221 argtype = gpr_type_node;
17223 else if (d->code == HTM_BUILTIN_TABORTDC
17224 || d->code == HTM_BUILTIN_TABORTDCI)
17226 rettype = unsigned_type_node;
17227 argtype = gpr_type_node;
17231 rettype = unsigned_type_node;
17232 argtype = unsigned_type_node;
17235 if ((mask & builtin_mask) != mask)
17237 if (TARGET_DEBUG_BUILTIN)
17238 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17244 if (TARGET_DEBUG_BUILTIN)
17245 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17246 (long unsigned) i);
17250 op[nopnds++] = (void_func) ? void_type_node : rettype;
17252 if (attr_args == RS6000_BTC_UNARY)
17253 op[nopnds++] = argtype;
17254 else if (attr_args == RS6000_BTC_BINARY)
17256 op[nopnds++] = argtype;
17257 op[nopnds++] = argtype;
17259 else if (attr_args == RS6000_BTC_TERNARY)
17261 op[nopnds++] = argtype;
17262 op[nopnds++] = argtype;
17263 op[nopnds++] = argtype;
17269 type = build_function_type_list (op[0], NULL_TREE);
17272 type = build_function_type_list (op[0], op[1], NULL_TREE);
17275 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17278 type = build_function_type_list (op[0], op[1], op[2], op[3],
17282 gcc_unreachable ();
17285 def_builtin (d->name, type, d->code);
17289 /* Hash function for builtin functions with up to 3 arguments and a return
17292 builtin_hasher::hash (builtin_hash_struct *bh)
17297 for (i = 0; i < 4; i++)
17299 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17300 ret = (ret * 2) + bh->uns_p[i];
17306 /* Compare builtin hash entries H1 and H2 for equivalence. */
17308 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17310 return ((p1->mode[0] == p2->mode[0])
17311 && (p1->mode[1] == p2->mode[1])
17312 && (p1->mode[2] == p2->mode[2])
17313 && (p1->mode[3] == p2->mode[3])
17314 && (p1->uns_p[0] == p2->uns_p[0])
17315 && (p1->uns_p[1] == p2->uns_p[1])
17316 && (p1->uns_p[2] == p2->uns_p[2])
17317 && (p1->uns_p[3] == p2->uns_p[3]));
17320 /* Map types for builtin functions with an explicit return type and up to 3
17321 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17322 of the argument. */
17324 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17325 machine_mode mode_arg1, machine_mode mode_arg2,
17326 enum rs6000_builtins builtin, const char *name)
17328 struct builtin_hash_struct h;
17329 struct builtin_hash_struct *h2;
17332 tree ret_type = NULL_TREE;
17333 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17335 /* Create builtin_hash_table. */
17336 if (builtin_hash_table == NULL)
17337 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17339 h.type = NULL_TREE;
17340 h.mode[0] = mode_ret;
17341 h.mode[1] = mode_arg0;
17342 h.mode[2] = mode_arg1;
17343 h.mode[3] = mode_arg2;
17349 /* If the builtin is a type that produces unsigned results or takes unsigned
17350 arguments, and it is returned as a decl for the vectorizer (such as
17351 widening multiplies, permute), make sure the arguments and return value
17352 are type correct. */
17355 /* unsigned 1 argument functions. */
17356 case CRYPTO_BUILTIN_VSBOX:
17357 case CRYPTO_BUILTIN_VSBOX_BE:
17358 case P8V_BUILTIN_VGBBD:
17359 case MISC_BUILTIN_CDTBCD:
17360 case MISC_BUILTIN_CBCDTD:
17365 /* unsigned 2 argument functions. */
17366 case ALTIVEC_BUILTIN_VMULEUB:
17367 case ALTIVEC_BUILTIN_VMULEUH:
17368 case P8V_BUILTIN_VMULEUW:
17369 case ALTIVEC_BUILTIN_VMULOUB:
17370 case ALTIVEC_BUILTIN_VMULOUH:
17371 case P8V_BUILTIN_VMULOUW:
17372 case CRYPTO_BUILTIN_VCIPHER:
17373 case CRYPTO_BUILTIN_VCIPHER_BE:
17374 case CRYPTO_BUILTIN_VCIPHERLAST:
17375 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
17376 case CRYPTO_BUILTIN_VNCIPHER:
17377 case CRYPTO_BUILTIN_VNCIPHER_BE:
17378 case CRYPTO_BUILTIN_VNCIPHERLAST:
17379 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
17380 case CRYPTO_BUILTIN_VPMSUMB:
17381 case CRYPTO_BUILTIN_VPMSUMH:
17382 case CRYPTO_BUILTIN_VPMSUMW:
17383 case CRYPTO_BUILTIN_VPMSUMD:
17384 case CRYPTO_BUILTIN_VPMSUM:
17385 case MISC_BUILTIN_ADDG6S:
17386 case MISC_BUILTIN_DIVWEU:
17387 case MISC_BUILTIN_DIVDEU:
17388 case VSX_BUILTIN_UDIV_V2DI:
17389 case ALTIVEC_BUILTIN_VMAXUB:
17390 case ALTIVEC_BUILTIN_VMINUB:
17391 case ALTIVEC_BUILTIN_VMAXUH:
17392 case ALTIVEC_BUILTIN_VMINUH:
17393 case ALTIVEC_BUILTIN_VMAXUW:
17394 case ALTIVEC_BUILTIN_VMINUW:
17395 case P8V_BUILTIN_VMAXUD:
17396 case P8V_BUILTIN_VMINUD:
17402 /* unsigned 3 argument functions. */
17403 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17404 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17405 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17406 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17407 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17408 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17409 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17410 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17411 case VSX_BUILTIN_VPERM_16QI_UNS:
17412 case VSX_BUILTIN_VPERM_8HI_UNS:
17413 case VSX_BUILTIN_VPERM_4SI_UNS:
17414 case VSX_BUILTIN_VPERM_2DI_UNS:
17415 case VSX_BUILTIN_XXSEL_16QI_UNS:
17416 case VSX_BUILTIN_XXSEL_8HI_UNS:
17417 case VSX_BUILTIN_XXSEL_4SI_UNS:
17418 case VSX_BUILTIN_XXSEL_2DI_UNS:
17419 case CRYPTO_BUILTIN_VPERMXOR:
17420 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17421 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17422 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17423 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17424 case CRYPTO_BUILTIN_VSHASIGMAW:
17425 case CRYPTO_BUILTIN_VSHASIGMAD:
17426 case CRYPTO_BUILTIN_VSHASIGMA:
17433 /* signed permute functions with unsigned char mask. */
17434 case ALTIVEC_BUILTIN_VPERM_16QI:
17435 case ALTIVEC_BUILTIN_VPERM_8HI:
17436 case ALTIVEC_BUILTIN_VPERM_4SI:
17437 case ALTIVEC_BUILTIN_VPERM_4SF:
17438 case ALTIVEC_BUILTIN_VPERM_2DI:
17439 case ALTIVEC_BUILTIN_VPERM_2DF:
17440 case VSX_BUILTIN_VPERM_16QI:
17441 case VSX_BUILTIN_VPERM_8HI:
17442 case VSX_BUILTIN_VPERM_4SI:
17443 case VSX_BUILTIN_VPERM_4SF:
17444 case VSX_BUILTIN_VPERM_2DI:
17445 case VSX_BUILTIN_VPERM_2DF:
17449 /* unsigned args, signed return. */
17450 case VSX_BUILTIN_XVCVUXDSP:
17451 case VSX_BUILTIN_XVCVUXDDP_UNS:
17452 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17456 /* signed args, unsigned return. */
17457 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17458 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17459 case MISC_BUILTIN_UNPACK_TD:
17460 case MISC_BUILTIN_UNPACK_V1TI:
17464 /* unsigned arguments, bool return (compares). */
17465 case ALTIVEC_BUILTIN_VCMPEQUB:
17466 case ALTIVEC_BUILTIN_VCMPEQUH:
17467 case ALTIVEC_BUILTIN_VCMPEQUW:
17468 case P8V_BUILTIN_VCMPEQUD:
17469 case VSX_BUILTIN_CMPGE_U16QI:
17470 case VSX_BUILTIN_CMPGE_U8HI:
17471 case VSX_BUILTIN_CMPGE_U4SI:
17472 case VSX_BUILTIN_CMPGE_U2DI:
17473 case ALTIVEC_BUILTIN_VCMPGTUB:
17474 case ALTIVEC_BUILTIN_VCMPGTUH:
17475 case ALTIVEC_BUILTIN_VCMPGTUW:
17476 case P8V_BUILTIN_VCMPGTUD:
17481 /* unsigned arguments for 128-bit pack instructions. */
17482 case MISC_BUILTIN_PACK_TD:
17483 case MISC_BUILTIN_PACK_V1TI:
17488 /* unsigned second arguments (vector shift right). */
17489 case ALTIVEC_BUILTIN_VSRB:
17490 case ALTIVEC_BUILTIN_VSRH:
17491 case ALTIVEC_BUILTIN_VSRW:
17492 case P8V_BUILTIN_VSRD:
17500 /* Figure out how many args are present. */
17501 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17504 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17505 if (!ret_type && h.uns_p[0])
17506 ret_type = builtin_mode_to_type[h.mode[0]][0];
17509 fatal_error (input_location,
17510 "internal error: builtin function %qs had an unexpected "
17511 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17513 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17514 arg_type[i] = NULL_TREE;
17516 for (i = 0; i < num_args; i++)
17518 int m = (int) h.mode[i+1];
17519 int uns_p = h.uns_p[i+1];
17521 arg_type[i] = builtin_mode_to_type[m][uns_p];
17522 if (!arg_type[i] && uns_p)
17523 arg_type[i] = builtin_mode_to_type[m][0];
17526 fatal_error (input_location,
17527 "internal error: builtin function %qs, argument %d "
17528 "had unexpected argument type %qs", name, i,
17529 GET_MODE_NAME (m));
17532 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17533 if (*found == NULL)
17535 h2 = ggc_alloc<builtin_hash_struct> ();
17539 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17540 arg_type[2], NULL_TREE);
17543 return (*found)->type;
17547 rs6000_common_init_builtins (void)
17549 const struct builtin_description *d;
17552 tree opaque_ftype_opaque = NULL_TREE;
17553 tree opaque_ftype_opaque_opaque = NULL_TREE;
17554 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17555 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17557 /* Create Altivec and VSX builtins on machines with at least the
17558 general purpose extensions (970 and newer) to allow the use of
17559 the target attribute. */
17561 if (TARGET_EXTRA_BUILTINS)
17562 builtin_mask |= RS6000_BTM_COMMON;
17564 /* Add the ternary operators. */
17566 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17569 HOST_WIDE_INT mask = d->mask;
17571 if ((mask & builtin_mask) != mask)
17573 if (TARGET_DEBUG_BUILTIN)
17574 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17578 if (rs6000_overloaded_builtin_p (d->code))
17580 if (! (type = opaque_ftype_opaque_opaque_opaque))
17581 type = opaque_ftype_opaque_opaque_opaque
17582 = build_function_type_list (opaque_V4SI_type_node,
17583 opaque_V4SI_type_node,
17584 opaque_V4SI_type_node,
17585 opaque_V4SI_type_node,
17590 enum insn_code icode = d->icode;
17593 if (TARGET_DEBUG_BUILTIN)
17594 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17600 if (icode == CODE_FOR_nothing)
17602 if (TARGET_DEBUG_BUILTIN)
17603 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17609 type = builtin_function_type (insn_data[icode].operand[0].mode,
17610 insn_data[icode].operand[1].mode,
17611 insn_data[icode].operand[2].mode,
17612 insn_data[icode].operand[3].mode,
17616 def_builtin (d->name, type, d->code);
17619 /* Add the binary operators. */
17621 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17623 machine_mode mode0, mode1, mode2;
17625 HOST_WIDE_INT mask = d->mask;
17627 if ((mask & builtin_mask) != mask)
17629 if (TARGET_DEBUG_BUILTIN)
17630 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17634 if (rs6000_overloaded_builtin_p (d->code))
17636 if (! (type = opaque_ftype_opaque_opaque))
17637 type = opaque_ftype_opaque_opaque
17638 = build_function_type_list (opaque_V4SI_type_node,
17639 opaque_V4SI_type_node,
17640 opaque_V4SI_type_node,
17645 enum insn_code icode = d->icode;
17648 if (TARGET_DEBUG_BUILTIN)
17649 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17655 if (icode == CODE_FOR_nothing)
17657 if (TARGET_DEBUG_BUILTIN)
17658 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17664 mode0 = insn_data[icode].operand[0].mode;
17665 mode1 = insn_data[icode].operand[1].mode;
17666 mode2 = insn_data[icode].operand[2].mode;
17668 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17672 def_builtin (d->name, type, d->code);
17675 /* Add the simple unary operators. */
17677 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17679 machine_mode mode0, mode1;
17681 HOST_WIDE_INT mask = d->mask;
17683 if ((mask & builtin_mask) != mask)
17685 if (TARGET_DEBUG_BUILTIN)
17686 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17690 if (rs6000_overloaded_builtin_p (d->code))
17692 if (! (type = opaque_ftype_opaque))
17693 type = opaque_ftype_opaque
17694 = build_function_type_list (opaque_V4SI_type_node,
17695 opaque_V4SI_type_node,
17700 enum insn_code icode = d->icode;
17703 if (TARGET_DEBUG_BUILTIN)
17704 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17710 if (icode == CODE_FOR_nothing)
17712 if (TARGET_DEBUG_BUILTIN)
17713 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17719 mode0 = insn_data[icode].operand[0].mode;
17720 mode1 = insn_data[icode].operand[1].mode;
17722 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17726 def_builtin (d->name, type, d->code);
17729 /* Add the simple no-argument operators. */
17731 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17733 machine_mode mode0;
17735 HOST_WIDE_INT mask = d->mask;
17737 if ((mask & builtin_mask) != mask)
17739 if (TARGET_DEBUG_BUILTIN)
17740 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17743 if (rs6000_overloaded_builtin_p (d->code))
17745 if (!opaque_ftype_opaque)
17746 opaque_ftype_opaque
17747 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17748 type = opaque_ftype_opaque;
17752 enum insn_code icode = d->icode;
17755 if (TARGET_DEBUG_BUILTIN)
17756 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17757 (long unsigned) i);
17760 if (icode == CODE_FOR_nothing)
17762 if (TARGET_DEBUG_BUILTIN)
17764 "rs6000_builtin, skip no-argument %s (no code)\n",
17768 mode0 = insn_data[icode].operand[0].mode;
17769 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17772 def_builtin (d->name, type, d->code);
17776 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17778 init_float128_ibm (machine_mode mode)
17780 if (!TARGET_XL_COMPAT)
17782 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17783 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17784 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17785 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17787 if (!TARGET_HARD_FLOAT)
17789 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17790 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17791 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17792 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17793 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17794 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17795 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17796 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17798 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17799 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17800 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17801 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17802 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17803 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17804 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17805 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17810 set_optab_libfunc (add_optab, mode, "_xlqadd");
17811 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17812 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17813 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17816 /* Add various conversions for IFmode to use the traditional TFmode
17818 if (mode == IFmode)
17820 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17821 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17822 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17823 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17824 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17825 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17827 if (TARGET_POWERPC64)
17829 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17830 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17831 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17832 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17837 /* Create a decl for either complex long double multiply or complex long double
17838 divide when long double is IEEE 128-bit floating point. We can't use
17839 __multc3 and __divtc3 because the original long double using IBM extended
17840 double used those names. The complex multiply/divide functions are encoded
17841 as builtin functions with a complex result and 4 scalar inputs. */
17844 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17846 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17849 set_builtin_decl (fncode, fndecl, true);
17851 if (TARGET_DEBUG_BUILTIN)
17852 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17857 /* Set up IEEE 128-bit floating point routines. Use different names if the
17858 arguments can be passed in a vector register. The historical PowerPC
17859 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17860 continue to use that if we aren't using vector registers to pass IEEE
17861 128-bit floating point. */
17864 init_float128_ieee (machine_mode mode)
17866 if (FLOAT128_VECTOR_P (mode))
17868 static bool complex_muldiv_init_p = false;
17870 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
17871 we have clone or target attributes, this will be called a second
17872 time. We want to create the built-in function only once. */
17873 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
17875 complex_muldiv_init_p = true;
17876 built_in_function fncode_mul =
17877 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17878 - MIN_MODE_COMPLEX_FLOAT);
17879 built_in_function fncode_div =
17880 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17881 - MIN_MODE_COMPLEX_FLOAT);
17883 tree fntype = build_function_type_list (complex_long_double_type_node,
17884 long_double_type_node,
17885 long_double_type_node,
17886 long_double_type_node,
17887 long_double_type_node,
17890 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17891 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17894 set_optab_libfunc (add_optab, mode, "__addkf3");
17895 set_optab_libfunc (sub_optab, mode, "__subkf3");
17896 set_optab_libfunc (neg_optab, mode, "__negkf2");
17897 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17898 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17899 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17900 set_optab_libfunc (abs_optab, mode, "__abskf2");
17901 set_optab_libfunc (powi_optab, mode, "__powikf2");
17903 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17904 set_optab_libfunc (ne_optab, mode, "__nekf2");
17905 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17906 set_optab_libfunc (ge_optab, mode, "__gekf2");
17907 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17908 set_optab_libfunc (le_optab, mode, "__lekf2");
17909 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17911 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17912 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17913 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17914 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17916 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17917 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17918 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17920 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17921 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17922 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17924 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
17925 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
17926 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
17927 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
17928 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
17929 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
17931 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17932 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17933 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17934 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17936 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17937 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17938 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17939 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17941 if (TARGET_POWERPC64)
17943 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17944 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17945 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17946 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17952 set_optab_libfunc (add_optab, mode, "_q_add");
17953 set_optab_libfunc (sub_optab, mode, "_q_sub");
17954 set_optab_libfunc (neg_optab, mode, "_q_neg");
17955 set_optab_libfunc (smul_optab, mode, "_q_mul");
17956 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17957 if (TARGET_PPC_GPOPT)
17958 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17960 set_optab_libfunc (eq_optab, mode, "_q_feq");
17961 set_optab_libfunc (ne_optab, mode, "_q_fne");
17962 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17963 set_optab_libfunc (ge_optab, mode, "_q_fge");
17964 set_optab_libfunc (lt_optab, mode, "_q_flt");
17965 set_optab_libfunc (le_optab, mode, "_q_fle");
17967 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17968 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17969 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17970 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17971 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17972 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17973 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17974 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17979 rs6000_init_libfuncs (void)
17981 /* __float128 support. */
17982 if (TARGET_FLOAT128_TYPE)
17984 init_float128_ibm (IFmode);
17985 init_float128_ieee (KFmode);
17988 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17989 if (TARGET_LONG_DOUBLE_128)
17991 if (!TARGET_IEEEQUAD)
17992 init_float128_ibm (TFmode);
17994 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
17996 init_float128_ieee (TFmode);
18000 /* Emit a potentially record-form instruction, setting DST from SRC.
18001 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18002 signed comparison of DST with zero. If DOT is 1, the generated RTL
18003 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18004 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18005 a separate COMPARE. */
18008 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18012 emit_move_insn (dst, src);
18016 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18018 emit_move_insn (dst, src);
18019 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18023 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18026 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18027 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18031 rtx set = gen_rtx_SET (dst, src);
18032 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18037 /* A validation routine: say whether CODE, a condition code, and MODE
18038 match. The other alternatives either don't make sense or should
18039 never be generated. */
18042 validate_condition_mode (enum rtx_code code, machine_mode mode)
18044 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18045 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18046 && GET_MODE_CLASS (mode) == MODE_CC);
18048 /* These don't make sense. */
18049 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18050 || mode != CCUNSmode);
18052 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18053 || mode == CCUNSmode);
18055 gcc_assert (mode == CCFPmode
18056 || (code != ORDERED && code != UNORDERED
18057 && code != UNEQ && code != LTGT
18058 && code != UNGT && code != UNLT
18059 && code != UNGE && code != UNLE));
18061 /* These should never be generated except for
18062 flag_finite_math_only. */
18063 gcc_assert (mode != CCFPmode
18064 || flag_finite_math_only
18065 || (code != LE && code != GE
18066 && code != UNEQ && code != LTGT
18067 && code != UNGT && code != UNLT));
18069 /* These are invalid; the information is not there. */
18070 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18074 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18075 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18076 not zero, store there the bit offset (counted from the right) where
18077 the single stretch of 1 bits begins; and similarly for B, the bit
18078 offset where it ends. */
18081 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18083 unsigned HOST_WIDE_INT val = INTVAL (mask);
18084 unsigned HOST_WIDE_INT bit;
18086 int n = GET_MODE_PRECISION (mode);
18088 if (mode != DImode && mode != SImode)
18091 if (INTVAL (mask) >= 0)
18094 ne = exact_log2 (bit);
18095 nb = exact_log2 (val + bit);
18097 else if (val + 1 == 0)
18106 nb = exact_log2 (bit);
18107 ne = exact_log2 (val + bit);
18112 ne = exact_log2 (bit);
18113 if (val + bit == 0)
18121 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18132 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18133 or rldicr instruction, to implement an AND with it in mode MODE. */
18136 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18140 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18143 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18145 if (mode == DImode)
18146 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18148 /* For SImode, rlwinm can do everything. */
18149 if (mode == SImode)
18150 return (nb < 32 && ne < 32);
18155 /* Return the instruction template for an AND with mask in mode MODE, with
18156 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18159 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18163 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18164 gcc_unreachable ();
18166 if (mode == DImode && ne == 0)
18168 operands[3] = GEN_INT (63 - nb);
18170 return "rldicl. %0,%1,0,%3";
18171 return "rldicl %0,%1,0,%3";
18174 if (mode == DImode && nb == 63)
18176 operands[3] = GEN_INT (63 - ne);
18178 return "rldicr. %0,%1,0,%3";
18179 return "rldicr %0,%1,0,%3";
18182 if (nb < 32 && ne < 32)
18184 operands[3] = GEN_INT (31 - nb);
18185 operands[4] = GEN_INT (31 - ne);
18187 return "rlwinm. %0,%1,0,%3,%4";
18188 return "rlwinm %0,%1,0,%3,%4";
18191 gcc_unreachable ();
18194 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18195 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18196 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18199 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18203 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18206 int n = GET_MODE_PRECISION (mode);
18209 if (CONST_INT_P (XEXP (shift, 1)))
18211 sh = INTVAL (XEXP (shift, 1));
18212 if (sh < 0 || sh >= n)
18216 rtx_code code = GET_CODE (shift);
18218 /* Convert any shift by 0 to a rotate, to simplify below code. */
18222 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18223 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18225 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18231 /* DImode rotates need rld*. */
18232 if (mode == DImode && code == ROTATE)
18233 return (nb == 63 || ne == 0 || ne == sh);
18235 /* SImode rotates need rlw*. */
18236 if (mode == SImode && code == ROTATE)
18237 return (nb < 32 && ne < 32 && sh < 32);
18239 /* Wrap-around masks are only okay for rotates. */
18243 /* Variable shifts are only okay for rotates. */
18247 /* Don't allow ASHIFT if the mask is wrong for that. */
18248 if (code == ASHIFT && ne < sh)
18251 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18252 if the mask is wrong for that. */
18253 if (nb < 32 && ne < 32 && sh < 32
18254 && !(code == LSHIFTRT && nb >= 32 - sh))
18257 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18258 if the mask is wrong for that. */
18259 if (code == LSHIFTRT)
18261 if (nb == 63 || ne == 0 || ne == sh)
18262 return !(code == LSHIFTRT && nb >= sh);
18267 /* Return the instruction template for a shift with mask in mode MODE, with
18268 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18271 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18275 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18276 gcc_unreachable ();
18278 if (mode == DImode && ne == 0)
18280 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18281 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18282 operands[3] = GEN_INT (63 - nb);
18284 return "rld%I2cl. %0,%1,%2,%3";
18285 return "rld%I2cl %0,%1,%2,%3";
18288 if (mode == DImode && nb == 63)
18290 operands[3] = GEN_INT (63 - ne);
18292 return "rld%I2cr. %0,%1,%2,%3";
18293 return "rld%I2cr %0,%1,%2,%3";
18297 && GET_CODE (operands[4]) != LSHIFTRT
18298 && CONST_INT_P (operands[2])
18299 && ne == INTVAL (operands[2]))
18301 operands[3] = GEN_INT (63 - nb);
18303 return "rld%I2c. %0,%1,%2,%3";
18304 return "rld%I2c %0,%1,%2,%3";
18307 if (nb < 32 && ne < 32)
18309 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18310 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18311 operands[3] = GEN_INT (31 - nb);
18312 operands[4] = GEN_INT (31 - ne);
18313 /* This insn can also be a 64-bit rotate with mask that really makes
18314 it just a shift right (with mask); the %h below are to adjust for
18315 that situation (shift count is >= 32 in that case). */
18317 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18318 return "rlw%I2nm %0,%1,%h2,%3,%4";
18321 gcc_unreachable ();
18324 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18325 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18326 ASHIFT, or LSHIFTRT) in mode MODE. */
18329 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18333 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18336 int n = GET_MODE_PRECISION (mode);
18338 int sh = INTVAL (XEXP (shift, 1));
18339 if (sh < 0 || sh >= n)
18342 rtx_code code = GET_CODE (shift);
18344 /* Convert any shift by 0 to a rotate, to simplify below code. */
18348 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18349 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18351 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18357 /* DImode rotates need rldimi. */
18358 if (mode == DImode && code == ROTATE)
18361 /* SImode rotates need rlwimi. */
18362 if (mode == SImode && code == ROTATE)
18363 return (nb < 32 && ne < 32 && sh < 32);
18365 /* Wrap-around masks are only okay for rotates. */
18369 /* Don't allow ASHIFT if the mask is wrong for that. */
18370 if (code == ASHIFT && ne < sh)
18373 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18374 if the mask is wrong for that. */
18375 if (nb < 32 && ne < 32 && sh < 32
18376 && !(code == LSHIFTRT && nb >= 32 - sh))
18379 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18380 if the mask is wrong for that. */
18381 if (code == LSHIFTRT)
18384 return !(code == LSHIFTRT && nb >= sh);
18389 /* Return the instruction template for an insert with mask in mode MODE, with
18390 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18393 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18397 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18398 gcc_unreachable ();
18400 /* Prefer rldimi because rlwimi is cracked. */
18401 if (TARGET_POWERPC64
18402 && (!dot || mode == DImode)
18403 && GET_CODE (operands[4]) != LSHIFTRT
18404 && ne == INTVAL (operands[2]))
18406 operands[3] = GEN_INT (63 - nb);
18408 return "rldimi. %0,%1,%2,%3";
18409 return "rldimi %0,%1,%2,%3";
18412 if (nb < 32 && ne < 32)
18414 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18415 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18416 operands[3] = GEN_INT (31 - nb);
18417 operands[4] = GEN_INT (31 - ne);
18419 return "rlwimi. %0,%1,%2,%3,%4";
18420 return "rlwimi %0,%1,%2,%3,%4";
18423 gcc_unreachable ();
18426 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18427 using two machine instructions. */
18430 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18432 /* There are two kinds of AND we can handle with two insns:
18433 1) those we can do with two rl* insn;
18436 We do not handle that last case yet. */
18438 /* If there is just one stretch of ones, we can do it. */
18439 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18442 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18443 one insn, we can do the whole thing with two. */
18444 unsigned HOST_WIDE_INT val = INTVAL (c);
18445 unsigned HOST_WIDE_INT bit1 = val & -val;
18446 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18447 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18448 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18449 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18452 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18453 If EXPAND is true, split rotate-and-mask instructions we generate to
18454 their constituent parts as well (this is used during expand); if DOT
18455 is 1, make the last insn a record-form instruction clobbering the
18456 destination GPR and setting the CC reg (from operands[3]); if 2, set
18457 that GPR as well as the CC reg. */
18460 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18462 gcc_assert (!(expand && dot));
18464 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18466 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18467 shift right. This generates better code than doing the masks without
18468 shifts, or shifting first right and then left. */
18470 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18472 gcc_assert (mode == DImode);
18474 int shift = 63 - nb;
18477 rtx tmp1 = gen_reg_rtx (DImode);
18478 rtx tmp2 = gen_reg_rtx (DImode);
18479 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18480 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18481 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18485 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18486 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18487 emit_move_insn (operands[0], tmp);
18488 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18489 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18494 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18495 that does the rest. */
18496 unsigned HOST_WIDE_INT bit1 = val & -val;
18497 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18498 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18499 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18501 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18502 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18504 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18506 /* Two "no-rotate"-and-mask instructions, for SImode. */
18507 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18509 gcc_assert (mode == SImode);
18511 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18512 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18513 emit_move_insn (reg, tmp);
18514 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18515 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18519 gcc_assert (mode == DImode);
18521 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18522 insns; we have to do the first in SImode, because it wraps. */
18523 if (mask2 <= 0xffffffff
18524 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18526 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18527 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18529 rtx reg_low = gen_lowpart (SImode, reg);
18530 emit_move_insn (reg_low, tmp);
18531 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18532 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18536 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18537 at the top end), rotate back and clear the other hole. */
18538 int right = exact_log2 (bit3);
18539 int left = 64 - right;
18541 /* Rotate the mask too. */
18542 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18546 rtx tmp1 = gen_reg_rtx (DImode);
18547 rtx tmp2 = gen_reg_rtx (DImode);
18548 rtx tmp3 = gen_reg_rtx (DImode);
18549 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18550 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18551 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18552 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18556 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18557 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18558 emit_move_insn (operands[0], tmp);
18559 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18560 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18561 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18565 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18566 for lfq and stfq insns iff the registers are hard registers. */
18569 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18571 /* We might have been passed a SUBREG. */
18572 if (!REG_P (reg1) || !REG_P (reg2))
18575 /* We might have been passed non floating point registers. */
18576 if (!FP_REGNO_P (REGNO (reg1))
18577 || !FP_REGNO_P (REGNO (reg2)))
18580 return (REGNO (reg1) == REGNO (reg2) - 1);
18583 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18584 addr1 and addr2 must be in consecutive memory locations
18585 (addr2 == addr1 + 8). */
18588 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18591 unsigned int reg1, reg2;
18592 int offset1, offset2;
18594 /* The mems cannot be volatile. */
18595 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18598 addr1 = XEXP (mem1, 0);
18599 addr2 = XEXP (mem2, 0);
18601 /* Extract an offset (if used) from the first addr. */
18602 if (GET_CODE (addr1) == PLUS)
18604 /* If not a REG, return zero. */
18605 if (!REG_P (XEXP (addr1, 0)))
18609 reg1 = REGNO (XEXP (addr1, 0));
18610 /* The offset must be constant! */
18611 if (!CONST_INT_P (XEXP (addr1, 1)))
18613 offset1 = INTVAL (XEXP (addr1, 1));
18616 else if (!REG_P (addr1))
18620 reg1 = REGNO (addr1);
18621 /* This was a simple (mem (reg)) expression. Offset is 0. */
18625 /* And now for the second addr. */
18626 if (GET_CODE (addr2) == PLUS)
18628 /* If not a REG, return zero. */
18629 if (!REG_P (XEXP (addr2, 0)))
18633 reg2 = REGNO (XEXP (addr2, 0));
18634 /* The offset must be constant. */
18635 if (!CONST_INT_P (XEXP (addr2, 1)))
18637 offset2 = INTVAL (XEXP (addr2, 1));
18640 else if (!REG_P (addr2))
18644 reg2 = REGNO (addr2);
18645 /* This was a simple (mem (reg)) expression. Offset is 0. */
18649 /* Both of these must have the same base register. */
18653 /* The offset for the second addr must be 8 more than the first addr. */
18654 if (offset2 != offset1 + 8)
18657 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18662 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18663 need to use DDmode, in all other cases we can use the same mode. */
18664 static machine_mode
18665 rs6000_secondary_memory_needed_mode (machine_mode mode)
18667 if (lra_in_progress && mode == SDmode)
18672 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18673 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18674 only work on the traditional altivec registers, note if an altivec register
18677 static enum rs6000_reg_type
18678 register_to_reg_type (rtx reg, bool *is_altivec)
18680 HOST_WIDE_INT regno;
18681 enum reg_class rclass;
18683 if (SUBREG_P (reg))
18684 reg = SUBREG_REG (reg);
18687 return NO_REG_TYPE;
18689 regno = REGNO (reg);
18690 if (!HARD_REGISTER_NUM_P (regno))
18692 if (!lra_in_progress && !reload_completed)
18693 return PSEUDO_REG_TYPE;
18695 regno = true_regnum (reg);
18696 if (regno < 0 || !HARD_REGISTER_NUM_P (regno))
18697 return PSEUDO_REG_TYPE;
18700 gcc_assert (regno >= 0);
18702 if (is_altivec && ALTIVEC_REGNO_P (regno))
18703 *is_altivec = true;
18705 rclass = rs6000_regno_regclass[regno];
18706 return reg_class_to_reg_type[(int)rclass];
18709 /* Helper function to return the cost of adding a TOC entry address. */
18712 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18716 if (TARGET_CMODEL != CMODEL_SMALL)
18717 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18720 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18725 /* Helper function for rs6000_secondary_reload to determine whether the memory
18726 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18727 needs reloading. Return negative if the memory is not handled by the memory
18728 helper functions and to try a different reload method, 0 if no additional
18729 instructions are need, and positive to give the extra cost for the
18733 rs6000_secondary_reload_memory (rtx addr,
18734 enum reg_class rclass,
18737 int extra_cost = 0;
18738 rtx reg, and_arg, plus_arg0, plus_arg1;
18739 addr_mask_type addr_mask;
18740 const char *type = NULL;
18741 const char *fail_msg = NULL;
18743 if (GPR_REG_CLASS_P (rclass))
18744 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18746 else if (rclass == FLOAT_REGS)
18747 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18749 else if (rclass == ALTIVEC_REGS)
18750 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18752 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18753 else if (rclass == VSX_REGS)
18754 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18755 & ~RELOAD_REG_AND_M16);
18757 /* If the register allocator hasn't made up its mind yet on the register
18758 class to use, settle on defaults to use. */
18759 else if (rclass == NO_REGS)
18761 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18762 & ~RELOAD_REG_AND_M16);
18764 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18765 addr_mask &= ~(RELOAD_REG_INDEXED
18766 | RELOAD_REG_PRE_INCDEC
18767 | RELOAD_REG_PRE_MODIFY);
18773 /* If the register isn't valid in this register class, just return now. */
18774 if ((addr_mask & RELOAD_REG_VALID) == 0)
18776 if (TARGET_DEBUG_ADDR)
18779 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18780 "not valid in class\n",
18781 GET_MODE_NAME (mode), reg_class_names[rclass]);
18788 switch (GET_CODE (addr))
18790 /* Does the register class supports auto update forms for this mode? We
18791 don't need a scratch register, since the powerpc only supports
18792 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18795 reg = XEXP (addr, 0);
18796 if (!base_reg_operand (addr, GET_MODE (reg)))
18798 fail_msg = "no base register #1";
18802 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18810 reg = XEXP (addr, 0);
18811 plus_arg1 = XEXP (addr, 1);
18812 if (!base_reg_operand (reg, GET_MODE (reg))
18813 || GET_CODE (plus_arg1) != PLUS
18814 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18816 fail_msg = "bad PRE_MODIFY";
18820 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18827 /* Do we need to simulate AND -16 to clear the bottom address bits used
18828 in VMX load/stores? Only allow the AND for vector sizes. */
18830 and_arg = XEXP (addr, 0);
18831 if (GET_MODE_SIZE (mode) != 16
18832 || !CONST_INT_P (XEXP (addr, 1))
18833 || INTVAL (XEXP (addr, 1)) != -16)
18835 fail_msg = "bad Altivec AND #1";
18839 if (rclass != ALTIVEC_REGS)
18841 if (legitimate_indirect_address_p (and_arg, false))
18844 else if (legitimate_indexed_address_p (and_arg, false))
18849 fail_msg = "bad Altivec AND #2";
18857 /* If this is an indirect address, make sure it is a base register. */
18860 if (!legitimate_indirect_address_p (addr, false))
18867 /* If this is an indexed address, make sure the register class can handle
18868 indexed addresses for this mode. */
18870 plus_arg0 = XEXP (addr, 0);
18871 plus_arg1 = XEXP (addr, 1);
18873 /* (plus (plus (reg) (constant)) (constant)) is generated during
18874 push_reload processing, so handle it now. */
18875 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18877 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18884 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18885 push_reload processing, so handle it now. */
18886 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18888 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18891 type = "indexed #2";
18895 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18897 fail_msg = "no base register #2";
18901 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18903 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18904 || !legitimate_indexed_address_p (addr, false))
18911 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18912 && CONST_INT_P (plus_arg1))
18914 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18917 type = "vector d-form offset";
18921 /* Make sure the register class can handle offset addresses. */
18922 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18924 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18927 type = "offset #2";
18933 fail_msg = "bad PLUS";
18940 /* Quad offsets are restricted and can't handle normal addresses. */
18941 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18944 type = "vector d-form lo_sum";
18947 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18949 fail_msg = "bad LO_SUM";
18953 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18960 /* Static addresses need to create a TOC entry. */
18964 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18967 type = "vector d-form lo_sum #2";
18973 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18977 /* TOC references look like offsetable memory. */
18979 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18981 fail_msg = "bad UNSPEC";
18985 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18988 type = "vector d-form lo_sum #3";
18991 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18994 type = "toc reference";
19000 fail_msg = "bad address";
19005 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19007 if (extra_cost < 0)
19009 "rs6000_secondary_reload_memory error: mode = %s, "
19010 "class = %s, addr_mask = '%s', %s\n",
19011 GET_MODE_NAME (mode),
19012 reg_class_names[rclass],
19013 rs6000_debug_addr_mask (addr_mask, false),
19014 (fail_msg != NULL) ? fail_msg : "<bad address>");
19018 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19019 "addr_mask = '%s', extra cost = %d, %s\n",
19020 GET_MODE_NAME (mode),
19021 reg_class_names[rclass],
19022 rs6000_debug_addr_mask (addr_mask, false),
19024 (type) ? type : "<none>");
19032 /* Helper function for rs6000_secondary_reload to return true if a move to a
19033 different register classe is really a simple move. */
19036 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19037 enum rs6000_reg_type from_type,
19040 int size = GET_MODE_SIZE (mode);
19042 /* Add support for various direct moves available. In this function, we only
19043 look at cases where we don't need any extra registers, and one or more
19044 simple move insns are issued. Originally small integers are not allowed
19045 in FPR/VSX registers. Single precision binary floating is not a simple
19046 move because we need to convert to the single precision memory layout.
19047 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19048 need special direct move handling, which we do not support yet. */
19049 if (TARGET_DIRECT_MOVE
19050 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19051 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19053 if (TARGET_POWERPC64)
19055 /* ISA 2.07: MTVSRD or MVFVSRD. */
19059 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19060 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19064 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19065 if (TARGET_P8_VECTOR)
19067 if (mode == SImode)
19070 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19074 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19075 if (mode == SDmode)
19079 /* Power6+: MFTGPR or MFFGPR. */
19080 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19081 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19082 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19085 /* Move to/from SPR. */
19086 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19087 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19088 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19094 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19095 special direct moves that involve allocating an extra register, return the
19096 insn code of the helper function if there is such a function or
19097 CODE_FOR_nothing if not. */
19100 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19101 enum rs6000_reg_type from_type,
19103 secondary_reload_info *sri,
19107 enum insn_code icode = CODE_FOR_nothing;
19109 int size = GET_MODE_SIZE (mode);
19111 if (TARGET_POWERPC64 && size == 16)
19113 /* Handle moving 128-bit values from GPRs to VSX point registers on
19114 ISA 2.07 (power8, power9) when running in 64-bit mode using
19115 XXPERMDI to glue the two 64-bit values back together. */
19116 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19118 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19119 icode = reg_addr[mode].reload_vsx_gpr;
19122 /* Handle moving 128-bit values from VSX point registers to GPRs on
19123 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19124 bottom 64-bit value. */
19125 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19127 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19128 icode = reg_addr[mode].reload_gpr_vsx;
19132 else if (TARGET_POWERPC64 && mode == SFmode)
19134 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19136 cost = 3; /* xscvdpspn, mfvsrd, and. */
19137 icode = reg_addr[mode].reload_gpr_vsx;
19140 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19142 cost = 2; /* mtvsrz, xscvspdpn. */
19143 icode = reg_addr[mode].reload_vsx_gpr;
19147 else if (!TARGET_POWERPC64 && size == 8)
19149 /* Handle moving 64-bit values from GPRs to floating point registers on
19150 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19151 32-bit values back together. Altivec register classes must be handled
19152 specially since a different instruction is used, and the secondary
19153 reload support requires a single instruction class in the scratch
19154 register constraint. However, right now TFmode is not allowed in
19155 Altivec registers, so the pattern will never match. */
19156 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19158 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19159 icode = reg_addr[mode].reload_fpr_gpr;
19163 if (icode != CODE_FOR_nothing)
19168 sri->icode = icode;
19169 sri->extra_cost = cost;
19176 /* Return whether a move between two register classes can be done either
19177 directly (simple move) or via a pattern that uses a single extra temporary
19178 (using ISA 2.07's direct move in this case. */
19181 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19182 enum rs6000_reg_type from_type,
19184 secondary_reload_info *sri,
19187 /* Fall back to load/store reloads if either type is not a register. */
19188 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19191 /* If we haven't allocated registers yet, assume the move can be done for the
19192 standard register types. */
19193 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19194 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19195 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19198 /* Moves to the same set of registers is a simple move for non-specialized
19200 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19203 /* Check whether a simple move can be done directly. */
19204 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19208 sri->icode = CODE_FOR_nothing;
19209 sri->extra_cost = 0;
19214 /* Now check if we can do it in a few steps. */
19215 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19219 /* Inform reload about cases where moving X with a mode MODE to a register in
19220 RCLASS requires an extra scratch or immediate register. Return the class
19221 needed for the immediate register.
19223 For VSX and Altivec, we may need a register to convert sp+offset into
19226 For misaligned 64-bit gpr loads and stores we need a register to
19227 convert an offset address to indirect. */
19230 rs6000_secondary_reload (bool in_p,
19232 reg_class_t rclass_i,
19234 secondary_reload_info *sri)
19236 enum reg_class rclass = (enum reg_class) rclass_i;
19237 reg_class_t ret = ALL_REGS;
19238 enum insn_code icode;
19239 bool default_p = false;
19240 bool done_p = false;
19242 /* Allow subreg of memory before/during reload. */
19243 bool memory_p = (MEM_P (x)
19244 || (!reload_completed && SUBREG_P (x)
19245 && MEM_P (SUBREG_REG (x))));
19247 sri->icode = CODE_FOR_nothing;
19248 sri->t_icode = CODE_FOR_nothing;
19249 sri->extra_cost = 0;
19251 ? reg_addr[mode].reload_load
19252 : reg_addr[mode].reload_store);
19254 if (REG_P (x) || register_operand (x, mode))
19256 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19257 bool altivec_p = (rclass == ALTIVEC_REGS);
19258 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19261 std::swap (to_type, from_type);
19263 /* Can we do a direct move of some sort? */
19264 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19267 icode = (enum insn_code)sri->icode;
19274 /* Make sure 0.0 is not reloaded or forced into memory. */
19275 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19282 /* If this is a scalar floating point value and we want to load it into the
19283 traditional Altivec registers, do it via a move via a traditional floating
19284 point register, unless we have D-form addressing. Also make sure that
19285 non-zero constants use a FPR. */
19286 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19287 && !mode_supports_vmx_dform (mode)
19288 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19289 && (memory_p || CONST_DOUBLE_P (x)))
19296 /* Handle reload of load/stores if we have reload helper functions. */
19297 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19299 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19302 if (extra_cost >= 0)
19306 if (extra_cost > 0)
19308 sri->extra_cost = extra_cost;
19309 sri->icode = icode;
19314 /* Handle unaligned loads and stores of integer registers. */
19315 if (!done_p && TARGET_POWERPC64
19316 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19318 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19320 rtx addr = XEXP (x, 0);
19321 rtx off = address_offset (addr);
19323 if (off != NULL_RTX)
19325 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19326 unsigned HOST_WIDE_INT offset = INTVAL (off);
19328 /* We need a secondary reload when our legitimate_address_p
19329 says the address is good (as otherwise the entire address
19330 will be reloaded), and the offset is not a multiple of
19331 four or we have an address wrap. Address wrap will only
19332 occur for LO_SUMs since legitimate_offset_address_p
19333 rejects addresses for 16-byte mems that will wrap. */
19334 if (GET_CODE (addr) == LO_SUM
19335 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19336 && ((offset & 3) != 0
19337 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19338 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19339 && (offset & 3) != 0))
19341 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19343 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19344 : CODE_FOR_reload_di_load);
19346 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19347 : CODE_FOR_reload_di_store);
19348 sri->extra_cost = 2;
19359 if (!done_p && !TARGET_POWERPC64
19360 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19362 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19364 rtx addr = XEXP (x, 0);
19365 rtx off = address_offset (addr);
19367 if (off != NULL_RTX)
19369 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19370 unsigned HOST_WIDE_INT offset = INTVAL (off);
19372 /* We need a secondary reload when our legitimate_address_p
19373 says the address is good (as otherwise the entire address
19374 will be reloaded), and we have a wrap.
19376 legitimate_lo_sum_address_p allows LO_SUM addresses to
19377 have any offset so test for wrap in the low 16 bits.
19379 legitimate_offset_address_p checks for the range
19380 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19381 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19382 [0x7ff4,0x7fff] respectively, so test for the
19383 intersection of these ranges, [0x7ffc,0x7fff] and
19384 [0x7ff4,0x7ff7] respectively.
19386 Note that the address we see here may have been
19387 manipulated by legitimize_reload_address. */
19388 if (GET_CODE (addr) == LO_SUM
19389 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19390 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19393 sri->icode = CODE_FOR_reload_si_load;
19395 sri->icode = CODE_FOR_reload_si_store;
19396 sri->extra_cost = 2;
19411 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19413 gcc_assert (ret != ALL_REGS);
19415 if (TARGET_DEBUG_ADDR)
19418 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19420 reg_class_names[ret],
19421 in_p ? "true" : "false",
19422 reg_class_names[rclass],
19423 GET_MODE_NAME (mode));
19425 if (reload_completed)
19426 fputs (", after reload", stderr);
19429 fputs (", done_p not set", stderr);
19432 fputs (", default secondary reload", stderr);
19434 if (sri->icode != CODE_FOR_nothing)
19435 fprintf (stderr, ", reload func = %s, extra cost = %d",
19436 insn_data[sri->icode].name, sri->extra_cost);
19438 else if (sri->extra_cost > 0)
19439 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19441 fputs ("\n", stderr);
19448 /* Better tracing for rs6000_secondary_reload_inner. */
19451 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19456 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19458 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19459 store_p ? "store" : "load");
19462 set = gen_rtx_SET (mem, reg);
19464 set = gen_rtx_SET (reg, mem);
19466 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19467 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19470 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19471 ATTRIBUTE_NORETURN;
19474 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19477 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19478 gcc_unreachable ();
19481 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19482 reload helper functions. These were identified in
19483 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19484 reload, it calls the insns:
19485 reload_<RELOAD:mode>_<P:mptrsize>_store
19486 reload_<RELOAD:mode>_<P:mptrsize>_load
19488 which in turn calls this function, to do whatever is necessary to create
19489 valid addresses. */
19492 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19494 int regno = true_regnum (reg);
19495 machine_mode mode = GET_MODE (reg);
19496 addr_mask_type addr_mask;
19499 rtx op_reg, op0, op1;
19504 if (regno < 0 || !HARD_REGISTER_NUM_P (regno) || !MEM_P (mem)
19505 || !base_reg_operand (scratch, GET_MODE (scratch)))
19506 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19508 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19509 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19511 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19512 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19514 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19515 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19518 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19520 /* Make sure the mode is valid in this register class. */
19521 if ((addr_mask & RELOAD_REG_VALID) == 0)
19522 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19524 if (TARGET_DEBUG_ADDR)
19525 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19527 new_addr = addr = XEXP (mem, 0);
19528 switch (GET_CODE (addr))
19530 /* Does the register class support auto update forms for this mode? If
19531 not, do the update now. We don't need a scratch register, since the
19532 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19535 op_reg = XEXP (addr, 0);
19536 if (!base_reg_operand (op_reg, Pmode))
19537 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19539 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19541 int delta = GET_MODE_SIZE (mode);
19542 if (GET_CODE (addr) == PRE_DEC)
19544 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19550 op0 = XEXP (addr, 0);
19551 op1 = XEXP (addr, 1);
19552 if (!base_reg_operand (op0, Pmode)
19553 || GET_CODE (op1) != PLUS
19554 || !rtx_equal_p (op0, XEXP (op1, 0)))
19555 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19557 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19559 emit_insn (gen_rtx_SET (op0, op1));
19564 /* Do we need to simulate AND -16 to clear the bottom address bits used
19565 in VMX load/stores? */
19567 op0 = XEXP (addr, 0);
19568 op1 = XEXP (addr, 1);
19569 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19571 if (REG_P (op0) || SUBREG_P (op0))
19574 else if (GET_CODE (op1) == PLUS)
19576 emit_insn (gen_rtx_SET (scratch, op1));
19581 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19583 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19584 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19585 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19586 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19587 new_addr = scratch;
19591 /* If this is an indirect address, make sure it is a base register. */
19594 if (!base_reg_operand (addr, GET_MODE (addr)))
19596 emit_insn (gen_rtx_SET (scratch, addr));
19597 new_addr = scratch;
19601 /* If this is an indexed address, make sure the register class can handle
19602 indexed addresses for this mode. */
19604 op0 = XEXP (addr, 0);
19605 op1 = XEXP (addr, 1);
19606 if (!base_reg_operand (op0, Pmode))
19607 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19609 else if (int_reg_operand (op1, Pmode))
19611 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19613 emit_insn (gen_rtx_SET (scratch, addr));
19614 new_addr = scratch;
19618 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19620 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19621 || !quad_address_p (addr, mode, false))
19623 emit_insn (gen_rtx_SET (scratch, addr));
19624 new_addr = scratch;
19628 /* Make sure the register class can handle offset addresses. */
19629 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19631 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19633 emit_insn (gen_rtx_SET (scratch, addr));
19634 new_addr = scratch;
19639 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19644 op0 = XEXP (addr, 0);
19645 op1 = XEXP (addr, 1);
19646 if (!base_reg_operand (op0, Pmode))
19647 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19649 else if (int_reg_operand (op1, Pmode))
19651 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19653 emit_insn (gen_rtx_SET (scratch, addr));
19654 new_addr = scratch;
19658 /* Quad offsets are restricted and can't handle normal addresses. */
19659 else if (mode_supports_dq_form (mode))
19661 emit_insn (gen_rtx_SET (scratch, addr));
19662 new_addr = scratch;
19665 /* Make sure the register class can handle offset addresses. */
19666 else if (legitimate_lo_sum_address_p (mode, addr, false))
19668 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19670 emit_insn (gen_rtx_SET (scratch, addr));
19671 new_addr = scratch;
19676 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19683 rs6000_emit_move (scratch, addr, Pmode);
19684 new_addr = scratch;
19688 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19691 /* Adjust the address if it changed. */
19692 if (addr != new_addr)
19694 mem = replace_equiv_address_nv (mem, new_addr);
19695 if (TARGET_DEBUG_ADDR)
19696 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19699 /* Now create the move. */
19701 emit_insn (gen_rtx_SET (mem, reg));
19703 emit_insn (gen_rtx_SET (reg, mem));
19708 /* Convert reloads involving 64-bit gprs and misaligned offset
19709 addressing, or multiple 32-bit gprs and offsets that are too large,
19710 to use indirect addressing. */
19713 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19715 int regno = true_regnum (reg);
19716 enum reg_class rclass;
19718 rtx scratch_or_premodify = scratch;
19720 if (TARGET_DEBUG_ADDR)
19722 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19723 store_p ? "store" : "load");
19724 fprintf (stderr, "reg:\n");
19726 fprintf (stderr, "mem:\n");
19728 fprintf (stderr, "scratch:\n");
19729 debug_rtx (scratch);
19732 gcc_assert (regno >= 0 && HARD_REGISTER_NUM_P (regno));
19733 gcc_assert (MEM_P (mem));
19734 rclass = REGNO_REG_CLASS (regno);
19735 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19736 addr = XEXP (mem, 0);
19738 if (GET_CODE (addr) == PRE_MODIFY)
19740 gcc_assert (REG_P (XEXP (addr, 0))
19741 && GET_CODE (XEXP (addr, 1)) == PLUS
19742 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19743 scratch_or_premodify = XEXP (addr, 0);
19744 addr = XEXP (addr, 1);
19746 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19748 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19750 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19752 /* Now create the move. */
19754 emit_insn (gen_rtx_SET (mem, reg));
19756 emit_insn (gen_rtx_SET (reg, mem));
19761 /* Given an rtx X being reloaded into a reg required to be
19762 in class CLASS, return the class of reg to actually use.
19763 In general this is just CLASS; but on some machines
19764 in some cases it is preferable to use a more restrictive class.
19766 On the RS/6000, we have to return NO_REGS when we want to reload a
19767 floating-point CONST_DOUBLE to force it to be copied to memory.
19769 We also don't want to reload integer values into floating-point
19770 registers if we can at all help it. In fact, this can
19771 cause reload to die, if it tries to generate a reload of CTR
19772 into a FP register and discovers it doesn't have the memory location
19775 ??? Would it be a good idea to have reload do the converse, that is
19776 try to reload floating modes into FP registers if possible?
19779 static enum reg_class
19780 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19782 machine_mode mode = GET_MODE (x);
19783 bool is_constant = CONSTANT_P (x);
19785 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19786 reload class for it. */
19787 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19788 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19791 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19792 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19795 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19796 the reloading of address expressions using PLUS into floating point
19798 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19802 /* Zero is always allowed in all VSX registers. */
19803 if (x == CONST0_RTX (mode))
19806 /* If this is a vector constant that can be formed with a few Altivec
19807 instructions, we want altivec registers. */
19808 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19809 return ALTIVEC_REGS;
19811 /* If this is an integer constant that can easily be loaded into
19812 vector registers, allow it. */
19813 if (CONST_INT_P (x))
19815 HOST_WIDE_INT value = INTVAL (x);
19817 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19818 2.06 can generate it in the Altivec registers with
19822 if (TARGET_P8_VECTOR)
19824 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19825 return ALTIVEC_REGS;
19830 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19831 a sign extend in the Altivec registers. */
19832 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19833 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19834 return ALTIVEC_REGS;
19837 /* Force constant to memory. */
19841 /* D-form addressing can easily reload the value. */
19842 if (mode_supports_vmx_dform (mode)
19843 || mode_supports_dq_form (mode))
19846 /* If this is a scalar floating point value and we don't have D-form
19847 addressing, prefer the traditional floating point registers so that we
19848 can use D-form (register+offset) addressing. */
19849 if (rclass == VSX_REGS
19850 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19853 /* Prefer the Altivec registers if Altivec is handling the vector
19854 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19856 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19857 || mode == V1TImode)
19858 return ALTIVEC_REGS;
19863 if (is_constant || GET_CODE (x) == PLUS)
19865 if (reg_class_subset_p (GENERAL_REGS, rclass))
19866 return GENERAL_REGS;
19867 if (reg_class_subset_p (BASE_REGS, rclass))
19872 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
19873 return GENERAL_REGS;
19878 /* Debug version of rs6000_preferred_reload_class. */
19879 static enum reg_class
19880 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19882 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19885 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19887 reg_class_names[ret], reg_class_names[rclass],
19888 GET_MODE_NAME (GET_MODE (x)));
19894 /* If we are copying between FP or AltiVec registers and anything else, we need
19895 a memory location. The exception is when we are targeting ppc64 and the
19896 move to/from fpr to gpr instructions are available. Also, under VSX, you
19897 can copy vector registers from the FP register set to the Altivec register
19898 set and vice versa. */
19901 rs6000_secondary_memory_needed (machine_mode mode,
19902 reg_class_t from_class,
19903 reg_class_t to_class)
19905 enum rs6000_reg_type from_type, to_type;
19906 bool altivec_p = ((from_class == ALTIVEC_REGS)
19907 || (to_class == ALTIVEC_REGS));
19909 /* If a simple/direct move is available, we don't need secondary memory */
19910 from_type = reg_class_to_reg_type[(int)from_class];
19911 to_type = reg_class_to_reg_type[(int)to_class];
19913 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19914 (secondary_reload_info *)0, altivec_p))
19917 /* If we have a floating point or vector register class, we need to use
19918 memory to transfer the data. */
19919 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19925 /* Debug version of rs6000_secondary_memory_needed. */
19927 rs6000_debug_secondary_memory_needed (machine_mode mode,
19928 reg_class_t from_class,
19929 reg_class_t to_class)
19931 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19934 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19935 "to_class = %s, mode = %s\n",
19936 ret ? "true" : "false",
19937 reg_class_names[from_class],
19938 reg_class_names[to_class],
19939 GET_MODE_NAME (mode));
19944 /* Return the register class of a scratch register needed to copy IN into
19945 or out of a register in RCLASS in MODE. If it can be done directly,
19946 NO_REGS is returned. */
19948 static enum reg_class
19949 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19954 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19956 && MACHOPIC_INDIRECT
19960 /* We cannot copy a symbolic operand directly into anything
19961 other than BASE_REGS for TARGET_ELF. So indicate that a
19962 register from BASE_REGS is needed as an intermediate
19965 On Darwin, pic addresses require a load from memory, which
19966 needs a base register. */
19967 if (rclass != BASE_REGS
19968 && (SYMBOL_REF_P (in)
19969 || GET_CODE (in) == HIGH
19970 || GET_CODE (in) == LABEL_REF
19971 || GET_CODE (in) == CONST))
19977 regno = REGNO (in);
19978 if (!HARD_REGISTER_NUM_P (regno))
19980 regno = true_regnum (in);
19981 if (!HARD_REGISTER_NUM_P (regno))
19985 else if (SUBREG_P (in))
19987 regno = true_regnum (in);
19988 if (!HARD_REGISTER_NUM_P (regno))
19994 /* If we have VSX register moves, prefer moving scalar values between
19995 Altivec registers and GPR by going via an FPR (and then via memory)
19996 instead of reloading the secondary memory address for Altivec moves. */
19998 && GET_MODE_SIZE (mode) < 16
19999 && !mode_supports_vmx_dform (mode)
20000 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20001 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20002 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20003 && (regno >= 0 && INT_REGNO_P (regno)))))
20006 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20008 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20009 || (regno >= 0 && INT_REGNO_P (regno)))
20012 /* Constants, memory, and VSX registers can go into VSX registers (both the
20013 traditional floating point and the altivec registers). */
20014 if (rclass == VSX_REGS
20015 && (regno == -1 || VSX_REGNO_P (regno)))
20018 /* Constants, memory, and FP registers can go into FP registers. */
20019 if ((regno == -1 || FP_REGNO_P (regno))
20020 && (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
20021 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20023 /* Memory, and AltiVec registers can go into AltiVec registers. */
20024 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20025 && rclass == ALTIVEC_REGS)
20028 /* We can copy among the CR registers. */
20029 if ((rclass == CR_REGS || rclass == CR0_REGS)
20030 && regno >= 0 && CR_REGNO_P (regno))
20033 /* Otherwise, we need GENERAL_REGS. */
20034 return GENERAL_REGS;
20037 /* Debug version of rs6000_secondary_reload_class. */
20038 static enum reg_class
20039 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20040 machine_mode mode, rtx in)
20042 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20044 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20045 "mode = %s, input rtx:\n",
20046 reg_class_names[ret], reg_class_names[rclass],
20047 GET_MODE_NAME (mode));
20053 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20056 rs6000_can_change_mode_class (machine_mode from,
20058 reg_class_t rclass)
20060 unsigned from_size = GET_MODE_SIZE (from);
20061 unsigned to_size = GET_MODE_SIZE (to);
20063 if (from_size != to_size)
20065 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20067 if (reg_classes_intersect_p (xclass, rclass))
20069 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20070 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20071 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20072 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20074 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20075 single register under VSX because the scalar part of the register
20076 is in the upper 64-bits, and not the lower 64-bits. Types like
20077 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20078 IEEE floating point can't overlap, and neither can small
20081 if (to_float128_vector_p && from_float128_vector_p)
20084 else if (to_float128_vector_p || from_float128_vector_p)
20087 /* TDmode in floating-mode registers must always go into a register
20088 pair with the most significant word in the even-numbered register
20089 to match ISA requirements. In little-endian mode, this does not
20090 match subreg numbering, so we cannot allow subregs. */
20091 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20094 if (from_size < 8 || to_size < 8)
20097 if (from_size == 8 && (8 * to_nregs) != to_size)
20100 if (to_size == 8 && (8 * from_nregs) != from_size)
20109 /* Since the VSX register set includes traditional floating point registers
20110 and altivec registers, just check for the size being different instead of
20111 trying to check whether the modes are vector modes. Otherwise it won't
20112 allow say DF and DI to change classes. For types like TFmode and TDmode
20113 that take 2 64-bit registers, rather than a single 128-bit register, don't
20114 allow subregs of those types to other 128 bit types. */
20115 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20117 unsigned num_regs = (from_size + 15) / 16;
20118 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20119 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20122 return (from_size == 8 || from_size == 16);
20125 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20126 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20132 /* Debug version of rs6000_can_change_mode_class. */
20134 rs6000_debug_can_change_mode_class (machine_mode from,
20136 reg_class_t rclass)
20138 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20141 "rs6000_can_change_mode_class, return %s, from = %s, "
20142 "to = %s, rclass = %s\n",
20143 ret ? "true" : "false",
20144 GET_MODE_NAME (from), GET_MODE_NAME (to),
20145 reg_class_names[rclass]);
20150 /* Return a string to do a move operation of 128 bits of data. */
20153 rs6000_output_move_128bit (rtx operands[])
20155 rtx dest = operands[0];
20156 rtx src = operands[1];
20157 machine_mode mode = GET_MODE (dest);
20160 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20161 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20165 dest_regno = REGNO (dest);
20166 dest_gpr_p = INT_REGNO_P (dest_regno);
20167 dest_fp_p = FP_REGNO_P (dest_regno);
20168 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20169 dest_vsx_p = dest_fp_p | dest_vmx_p;
20174 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20179 src_regno = REGNO (src);
20180 src_gpr_p = INT_REGNO_P (src_regno);
20181 src_fp_p = FP_REGNO_P (src_regno);
20182 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20183 src_vsx_p = src_fp_p | src_vmx_p;
20188 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20191 /* Register moves. */
20192 if (dest_regno >= 0 && src_regno >= 0)
20199 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20200 return (WORDS_BIG_ENDIAN
20201 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20202 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20204 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20208 else if (TARGET_VSX && dest_vsx_p)
20211 return "xxlor %x0,%x1,%x1";
20213 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20214 return (WORDS_BIG_ENDIAN
20215 ? "mtvsrdd %x0,%1,%L1"
20216 : "mtvsrdd %x0,%L1,%1");
20218 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20222 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20223 return "vor %0,%1,%1";
20225 else if (dest_fp_p && src_fp_p)
20230 else if (dest_regno >= 0 && MEM_P (src))
20234 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20240 else if (TARGET_ALTIVEC && dest_vmx_p
20241 && altivec_indexed_or_indirect_operand (src, mode))
20242 return "lvx %0,%y1";
20244 else if (TARGET_VSX && dest_vsx_p)
20246 if (mode_supports_dq_form (mode)
20247 && quad_address_p (XEXP (src, 0), mode, true))
20248 return "lxv %x0,%1";
20250 else if (TARGET_P9_VECTOR)
20251 return "lxvx %x0,%y1";
20253 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20254 return "lxvw4x %x0,%y1";
20257 return "lxvd2x %x0,%y1";
20260 else if (TARGET_ALTIVEC && dest_vmx_p)
20261 return "lvx %0,%y1";
20263 else if (dest_fp_p)
20268 else if (src_regno >= 0 && MEM_P (dest))
20272 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20273 return "stq %1,%0";
20278 else if (TARGET_ALTIVEC && src_vmx_p
20279 && altivec_indexed_or_indirect_operand (dest, mode))
20280 return "stvx %1,%y0";
20282 else if (TARGET_VSX && src_vsx_p)
20284 if (mode_supports_dq_form (mode)
20285 && quad_address_p (XEXP (dest, 0), mode, true))
20286 return "stxv %x1,%0";
20288 else if (TARGET_P9_VECTOR)
20289 return "stxvx %x1,%y0";
20291 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20292 return "stxvw4x %x1,%y0";
20295 return "stxvd2x %x1,%y0";
20298 else if (TARGET_ALTIVEC && src_vmx_p)
20299 return "stvx %1,%y0";
20306 else if (dest_regno >= 0
20307 && (CONST_INT_P (src)
20308 || CONST_WIDE_INT_P (src)
20309 || CONST_DOUBLE_P (src)
20310 || GET_CODE (src) == CONST_VECTOR))
20315 else if ((dest_vmx_p && TARGET_ALTIVEC)
20316 || (dest_vsx_p && TARGET_VSX))
20317 return output_vec_const_move (operands);
20320 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20323 /* Validate a 128-bit move. */
20325 rs6000_move_128bit_ok_p (rtx operands[])
20327 machine_mode mode = GET_MODE (operands[0]);
20328 return (gpc_reg_operand (operands[0], mode)
20329 || gpc_reg_operand (operands[1], mode));
20332 /* Return true if a 128-bit move needs to be split. */
20334 rs6000_split_128bit_ok_p (rtx operands[])
20336 if (!reload_completed)
20339 if (!gpr_or_gpr_p (operands[0], operands[1]))
20342 if (quad_load_store_p (operands[0], operands[1]))
20349 /* Given a comparison operation, return the bit number in CCR to test. We
20350 know this is a valid comparison.
20352 SCC_P is 1 if this is for an scc. That means that %D will have been
20353 used instead of %C, so the bits will be in different places.
20355 Return -1 if OP isn't a valid comparison for some reason. */
20358 ccr_bit (rtx op, int scc_p)
20360 enum rtx_code code = GET_CODE (op);
20361 machine_mode cc_mode;
20366 if (!COMPARISON_P (op))
20369 reg = XEXP (op, 0);
20371 if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg)))
20374 cc_mode = GET_MODE (reg);
20375 cc_regnum = REGNO (reg);
20376 base_bit = 4 * (cc_regnum - CR0_REGNO);
20378 validate_condition_mode (code, cc_mode);
20380 /* When generating a sCOND operation, only positive conditions are
20399 return scc_p ? base_bit + 3 : base_bit + 2;
20401 return base_bit + 2;
20402 case GT: case GTU: case UNLE:
20403 return base_bit + 1;
20404 case LT: case LTU: case UNGE:
20406 case ORDERED: case UNORDERED:
20407 return base_bit + 3;
20410 /* If scc, we will have done a cror to put the bit in the
20411 unordered position. So test that bit. For integer, this is ! LT
20412 unless this is an scc insn. */
20413 return scc_p ? base_bit + 3 : base_bit;
20416 return scc_p ? base_bit + 3 : base_bit + 1;
20423 /* Return the GOT register. */
20426 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20428 /* The second flow pass currently (June 1999) can't update
20429 regs_ever_live without disturbing other parts of the compiler, so
20430 update it here to make the prolog/epilogue code happy. */
20431 if (!can_create_pseudo_p ()
20432 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20433 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20435 crtl->uses_pic_offset_table = 1;
20437 return pic_offset_table_rtx;
20440 static rs6000_stack_t stack_info;
20442 /* Function to init struct machine_function.
20443 This will be called, via a pointer variable,
20444 from push_function_context. */
20446 static struct machine_function *
20447 rs6000_init_machine_status (void)
20449 stack_info.reload_completed = 0;
20450 return ggc_cleared_alloc<machine_function> ();
20453 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20455 /* Write out a function code label. */
20458 rs6000_output_function_entry (FILE *file, const char *fname)
20460 if (fname[0] != '.')
20462 switch (DEFAULT_ABI)
20465 gcc_unreachable ();
20471 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20481 RS6000_OUTPUT_BASENAME (file, fname);
20484 /* Print an operand. Recognize special options, documented below. */
20487 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20488 only introduced by the linker, when applying the sda21
20490 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20491 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20493 #define SMALL_DATA_RELOC "sda21"
20494 #define SMALL_DATA_REG 0
20498 print_operand (FILE *file, rtx x, int code)
20501 unsigned HOST_WIDE_INT uval;
20505 /* %a is output_address. */
20507 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20511 /* Like 'J' but get to the GT bit only. */
20512 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20514 output_operand_lossage ("invalid %%D value");
20518 /* Bit 1 is GT bit. */
20519 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20521 /* Add one for shift count in rlinm for scc. */
20522 fprintf (file, "%d", i + 1);
20526 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20529 output_operand_lossage ("invalid %%e value");
20534 if ((uval & 0xffff) == 0 && uval != 0)
20539 /* X is a CR register. Print the number of the EQ bit of the CR */
20540 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20541 output_operand_lossage ("invalid %%E value");
20543 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20547 /* X is a CR register. Print the shift count needed to move it
20548 to the high-order four bits. */
20549 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20550 output_operand_lossage ("invalid %%f value");
20552 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20556 /* Similar, but print the count for the rotate in the opposite
20558 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20559 output_operand_lossage ("invalid %%F value");
20561 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20565 /* X is a constant integer. If it is negative, print "m",
20566 otherwise print "z". This is to make an aze or ame insn. */
20567 if (!CONST_INT_P (x))
20568 output_operand_lossage ("invalid %%G value");
20569 else if (INTVAL (x) >= 0)
20576 /* If constant, output low-order five bits. Otherwise, write
20579 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20581 print_operand (file, x, 0);
20585 /* If constant, output low-order six bits. Otherwise, write
20588 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20590 print_operand (file, x, 0);
20594 /* Print `i' if this is a constant, else nothing. */
20600 /* Write the bit number in CCR for jump. */
20601 i = ccr_bit (x, 0);
20603 output_operand_lossage ("invalid %%j code");
20605 fprintf (file, "%d", i);
20609 /* Similar, but add one for shift count in rlinm for scc and pass
20610 scc flag to `ccr_bit'. */
20611 i = ccr_bit (x, 1);
20613 output_operand_lossage ("invalid %%J code");
20615 /* If we want bit 31, write a shift count of zero, not 32. */
20616 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20620 /* X must be a constant. Write the 1's complement of the
20623 output_operand_lossage ("invalid %%k value");
20625 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20629 /* X must be a symbolic constant on ELF. Write an
20630 expression suitable for an 'addi' that adds in the low 16
20631 bits of the MEM. */
20632 if (GET_CODE (x) == CONST)
20634 if (GET_CODE (XEXP (x, 0)) != PLUS
20635 || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
20636 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20637 || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20638 output_operand_lossage ("invalid %%K value");
20640 print_operand_address (file, x);
20641 fputs ("@l", file);
20644 /* %l is output_asm_label. */
20647 /* Write second word of DImode or DFmode reference. Works on register
20648 or non-indexed memory only. */
20650 fputs (reg_names[REGNO (x) + 1], file);
20651 else if (MEM_P (x))
20653 machine_mode mode = GET_MODE (x);
20654 /* Handle possible auto-increment. Since it is pre-increment and
20655 we have already done it, we can just use an offset of word. */
20656 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20657 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20658 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20660 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20661 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20664 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20668 if (small_data_operand (x, GET_MODE (x)))
20669 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20670 reg_names[SMALL_DATA_REG]);
20674 case 'N': /* Unused */
20675 /* Write the number of elements in the vector times 4. */
20676 if (GET_CODE (x) != PARALLEL)
20677 output_operand_lossage ("invalid %%N value");
20679 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20682 case 'O': /* Unused */
20683 /* Similar, but subtract 1 first. */
20684 if (GET_CODE (x) != PARALLEL)
20685 output_operand_lossage ("invalid %%O value");
20687 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20691 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20694 || (i = exact_log2 (INTVAL (x))) < 0)
20695 output_operand_lossage ("invalid %%p value");
20697 fprintf (file, "%d", i);
20701 /* The operand must be an indirect memory reference. The result
20702 is the register name. */
20703 if (!MEM_P (x) || !REG_P (XEXP (x, 0))
20704 || REGNO (XEXP (x, 0)) >= 32)
20705 output_operand_lossage ("invalid %%P value");
20707 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20711 /* This outputs the logical code corresponding to a boolean
20712 expression. The expression may have one or both operands
20713 negated (if one, only the first one). For condition register
20714 logical operations, it will also treat the negated
20715 CR codes as NOTs, but not handle NOTs of them. */
20717 const char *const *t = 0;
20719 enum rtx_code code = GET_CODE (x);
20720 static const char * const tbl[3][3] = {
20721 { "and", "andc", "nor" },
20722 { "or", "orc", "nand" },
20723 { "xor", "eqv", "xor" } };
20727 else if (code == IOR)
20729 else if (code == XOR)
20732 output_operand_lossage ("invalid %%q value");
20734 if (GET_CODE (XEXP (x, 0)) != NOT)
20738 if (GET_CODE (XEXP (x, 1)) == NOT)
20749 if (! TARGET_MFCRF)
20755 /* X is a CR register. Print the mask for `mtcrf'. */
20756 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20757 output_operand_lossage ("invalid %%R value");
20759 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20763 /* Low 5 bits of 32 - value */
20765 output_operand_lossage ("invalid %%s value");
20767 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20771 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20772 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20774 output_operand_lossage ("invalid %%t value");
20778 /* Bit 3 is OV bit. */
20779 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20781 /* If we want bit 31, write a shift count of zero, not 32. */
20782 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20786 /* Print the symbolic name of a branch target register. */
20787 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20788 x = XVECEXP (x, 0, 0);
20789 if (!REG_P (x) || (REGNO (x) != LR_REGNO
20790 && REGNO (x) != CTR_REGNO))
20791 output_operand_lossage ("invalid %%T value");
20792 else if (REGNO (x) == LR_REGNO)
20793 fputs ("lr", file);
20795 fputs ("ctr", file);
20799 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20800 for use in unsigned operand. */
20803 output_operand_lossage ("invalid %%u value");
20808 if ((uval & 0xffff) == 0)
20811 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20815 /* High-order 16 bits of constant for use in signed operand. */
20817 output_operand_lossage ("invalid %%v value");
20819 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20820 (INTVAL (x) >> 16) & 0xffff);
20824 /* Print `u' if this has an auto-increment or auto-decrement. */
20826 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20827 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20828 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20833 /* Print the trap code for this operand. */
20834 switch (GET_CODE (x))
20837 fputs ("eq", file); /* 4 */
20840 fputs ("ne", file); /* 24 */
20843 fputs ("lt", file); /* 16 */
20846 fputs ("le", file); /* 20 */
20849 fputs ("gt", file); /* 8 */
20852 fputs ("ge", file); /* 12 */
20855 fputs ("llt", file); /* 2 */
20858 fputs ("lle", file); /* 6 */
20861 fputs ("lgt", file); /* 1 */
20864 fputs ("lge", file); /* 5 */
20867 output_operand_lossage ("invalid %%V value");
20872 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20875 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20876 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20878 print_operand (file, x, 0);
20882 /* X is a FPR or Altivec register used in a VSX context. */
20883 if (!REG_P (x) || !VSX_REGNO_P (REGNO (x)))
20884 output_operand_lossage ("invalid %%x value");
20887 int reg = REGNO (x);
20888 int vsx_reg = (FP_REGNO_P (reg)
20890 : reg - FIRST_ALTIVEC_REGNO + 32);
20892 #ifdef TARGET_REGNAMES
20893 if (TARGET_REGNAMES)
20894 fprintf (file, "%%vs%d", vsx_reg);
20897 fprintf (file, "%d", vsx_reg);
20903 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20904 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20905 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20910 /* Like 'L', for third word of TImode/PTImode */
20912 fputs (reg_names[REGNO (x) + 2], file);
20913 else if (MEM_P (x))
20915 machine_mode mode = GET_MODE (x);
20916 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20917 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20918 output_address (mode, plus_constant (Pmode,
20919 XEXP (XEXP (x, 0), 0), 8));
20920 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20921 output_address (mode, plus_constant (Pmode,
20922 XEXP (XEXP (x, 0), 0), 8));
20924 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20925 if (small_data_operand (x, GET_MODE (x)))
20926 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20927 reg_names[SMALL_DATA_REG]);
20932 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20933 x = XVECEXP (x, 0, 1);
20934 /* X is a SYMBOL_REF. Write out the name preceded by a
20935 period and without any trailing data in brackets. Used for function
20936 names. If we are configured for System V (or the embedded ABI) on
20937 the PowerPC, do not emit the period, since those systems do not use
20938 TOCs and the like. */
20939 if (!SYMBOL_REF_P (x))
20941 output_operand_lossage ("invalid %%z value");
20945 /* For macho, check to see if we need a stub. */
20948 const char *name = XSTR (x, 0);
20950 if (darwin_emit_branch_islands
20951 && MACHOPIC_INDIRECT
20952 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20953 name = machopic_indirection_name (x, /*stub_p=*/true);
20955 assemble_name (file, name);
20957 else if (!DOT_SYMBOLS)
20958 assemble_name (file, XSTR (x, 0));
20960 rs6000_output_function_entry (file, XSTR (x, 0));
20964 /* Like 'L', for last word of TImode/PTImode. */
20966 fputs (reg_names[REGNO (x) + 3], file);
20967 else if (MEM_P (x))
20969 machine_mode mode = GET_MODE (x);
20970 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20971 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20972 output_address (mode, plus_constant (Pmode,
20973 XEXP (XEXP (x, 0), 0), 12));
20974 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20975 output_address (mode, plus_constant (Pmode,
20976 XEXP (XEXP (x, 0), 0), 12));
20978 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20979 if (small_data_operand (x, GET_MODE (x)))
20980 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20981 reg_names[SMALL_DATA_REG]);
20985 /* Print AltiVec memory operand. */
20990 gcc_assert (MEM_P (x));
20994 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20995 && GET_CODE (tmp) == AND
20996 && CONST_INT_P (XEXP (tmp, 1))
20997 && INTVAL (XEXP (tmp, 1)) == -16)
20998 tmp = XEXP (tmp, 0);
20999 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21000 && GET_CODE (tmp) == PRE_MODIFY)
21001 tmp = XEXP (tmp, 1);
21003 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21006 if (GET_CODE (tmp) != PLUS
21007 || !REG_P (XEXP (tmp, 0))
21008 || !REG_P (XEXP (tmp, 1)))
21010 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21014 if (REGNO (XEXP (tmp, 0)) == 0)
21015 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21016 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21018 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21019 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21026 fprintf (file, "%s", reg_names[REGNO (x)]);
21027 else if (MEM_P (x))
21029 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21030 know the width from the mode. */
21031 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21032 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21033 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21034 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21035 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21036 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21037 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21038 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21040 output_address (GET_MODE (x), XEXP (x, 0));
21042 else if (toc_relative_expr_p (x, false,
21043 &tocrel_base_oac, &tocrel_offset_oac))
21044 /* This hack along with a corresponding hack in
21045 rs6000_output_addr_const_extra arranges to output addends
21046 where the assembler expects to find them. eg.
21047 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21048 without this hack would be output as "x@toc+4". We
21050 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21051 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
21052 output_addr_const (file, XVECEXP (x, 0, 0));
21053 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
21054 output_addr_const (file, XVECEXP (x, 0, 1));
21056 output_addr_const (file, x);
21060 if (const char *name = get_some_local_dynamic_name ())
21061 assemble_name (file, name);
21063 output_operand_lossage ("'%%&' used without any "
21064 "local dynamic TLS references");
21068 output_operand_lossage ("invalid %%xn code");
21072 /* Print the address of an operand. */
21075 print_operand_address (FILE *file, rtx x)
21078 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21079 else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
21080 || GET_CODE (x) == LABEL_REF)
21082 output_addr_const (file, x);
21083 if (small_data_operand (x, GET_MODE (x)))
21084 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21085 reg_names[SMALL_DATA_REG]);
21087 gcc_assert (!TARGET_TOC);
21089 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21090 && REG_P (XEXP (x, 1)))
21092 if (REGNO (XEXP (x, 0)) == 0)
21093 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21094 reg_names[ REGNO (XEXP (x, 0)) ]);
21096 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21097 reg_names[ REGNO (XEXP (x, 1)) ]);
21099 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21100 && CONST_INT_P (XEXP (x, 1)))
21101 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21102 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21104 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21105 && CONSTANT_P (XEXP (x, 1)))
21107 fprintf (file, "lo16(");
21108 output_addr_const (file, XEXP (x, 1));
21109 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21113 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21114 && CONSTANT_P (XEXP (x, 1)))
21116 output_addr_const (file, XEXP (x, 1));
21117 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21120 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21122 /* This hack along with a corresponding hack in
21123 rs6000_output_addr_const_extra arranges to output addends
21124 where the assembler expects to find them. eg.
21126 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21127 without this hack would be output as "x@toc+8@l(9)". We
21128 want "x+8@toc@l(9)". */
21129 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21130 if (GET_CODE (x) == LO_SUM)
21131 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21133 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21136 output_addr_const (file, x);
21139 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21142 rs6000_output_addr_const_extra (FILE *file, rtx x)
21144 if (GET_CODE (x) == UNSPEC)
21145 switch (XINT (x, 1))
21147 case UNSPEC_TOCREL:
21148 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x, 0, 0))
21149 && REG_P (XVECEXP (x, 0, 1))
21150 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21151 output_addr_const (file, XVECEXP (x, 0, 0));
21152 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21154 if (INTVAL (tocrel_offset_oac) >= 0)
21155 fprintf (file, "+");
21156 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21158 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21161 assemble_name (file, toc_label_name);
21164 else if (TARGET_ELF)
21165 fputs ("@toc", file);
21169 case UNSPEC_MACHOPIC_OFFSET:
21170 output_addr_const (file, XVECEXP (x, 0, 0));
21172 machopic_output_function_base_name (file);
21179 /* Target hook for assembling integer objects. The PowerPC version has
21180 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21181 is defined. It also needs to handle DI-mode objects on 64-bit
21185 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21187 #ifdef RELOCATABLE_NEEDS_FIXUP
21188 /* Special handling for SI values. */
21189 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21191 static int recurse = 0;
21193 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21194 the .fixup section. Since the TOC section is already relocated, we
21195 don't need to mark it here. We used to skip the text section, but it
21196 should never be valid for relocated addresses to be placed in the text
21198 if (DEFAULT_ABI == ABI_V4
21199 && (TARGET_RELOCATABLE || flag_pic > 1)
21200 && in_section != toc_section
21202 && !CONST_SCALAR_INT_P (x)
21208 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21210 ASM_OUTPUT_LABEL (asm_out_file, buf);
21211 fprintf (asm_out_file, "\t.long\t(");
21212 output_addr_const (asm_out_file, x);
21213 fprintf (asm_out_file, ")@fixup\n");
21214 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21215 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21216 fprintf (asm_out_file, "\t.long\t");
21217 assemble_name (asm_out_file, buf);
21218 fprintf (asm_out_file, "\n\t.previous\n");
21222 /* Remove initial .'s to turn a -mcall-aixdesc function
21223 address into the address of the descriptor, not the function
21225 else if (SYMBOL_REF_P (x)
21226 && XSTR (x, 0)[0] == '.'
21227 && DEFAULT_ABI == ABI_AIX)
21229 const char *name = XSTR (x, 0);
21230 while (*name == '.')
21233 fprintf (asm_out_file, "\t.long\t%s\n", name);
21237 #endif /* RELOCATABLE_NEEDS_FIXUP */
21238 return default_assemble_integer (x, size, aligned_p);
21241 /* Return a template string for assembly to emit when making an
21242 external call. FUNOP is the call mem argument operand number. */
21244 static const char *
21245 rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
21247 /* -Wformat-overflow workaround, without which gcc thinks that %u
21248 might produce 10 digits. */
21249 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21253 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21255 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21256 sprintf (arg, "(%%%u@tlsgd)", funop + 1);
21257 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21258 sprintf (arg, "(%%&@tlsld)");
21260 gcc_unreachable ();
21263 /* The magic 32768 offset here corresponds to the offset of
21264 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21266 sprintf (z, "%%z%u%s", funop,
21267 (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == 2
21270 static char str[32]; /* 2 spare */
21271 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21272 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21273 sibcall ? "" : "\n\tnop");
21274 else if (DEFAULT_ABI == ABI_V4)
21275 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21276 flag_pic ? "@plt" : "");
21278 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21279 else if (DEFAULT_ABI == ABI_DARWIN)
21281 /* The cookie is in operand func+2. */
21282 gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
21283 int cookie = INTVAL (operands[funop + 2]);
21284 if (cookie & CALL_LONG)
21286 tree funname = get_identifier (XSTR (operands[funop], 0));
21287 tree labelname = get_prev_label (funname);
21288 gcc_checking_assert (labelname && !sibcall);
21290 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21291 instruction will reach 'foo', otherwise link as 'bl L42'".
21292 "L42" should be a 'branch island', that will do a far jump to
21293 'foo'. Branch islands are generated in
21294 macho_branch_islands(). */
21295 sprintf (str, "jbsr %%z%u,%.10s", funop,
21296 IDENTIFIER_POINTER (labelname));
21299 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21301 sprintf (str, "b%s %s%s", sibcall ? "" : "l", z, arg);
21305 gcc_unreachable ();
21310 rs6000_call_template (rtx *operands, unsigned int funop)
21312 return rs6000_call_template_1 (operands, funop, false);
21316 rs6000_sibcall_template (rtx *operands, unsigned int funop)
21318 return rs6000_call_template_1 (operands, funop, true);
21321 /* As above, for indirect calls. */
21323 static const char *
21324 rs6000_indirect_call_template_1 (rtx *operands, unsigned int funop,
21327 /* -Wformat-overflow workaround, without which gcc thinks that %u
21328 might produce 10 digits. Note that -Wformat-overflow will not
21329 currently warn here for str[], so do not rely on a warning to
21330 ensure str[] is correctly sized. */
21331 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21333 /* Currently, funop is either 0 or 1. The maximum string is always
21334 a !speculate 64-bit __tls_get_addr call.
21338 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21339 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21341 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21342 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21349 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21350 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21352 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21353 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21360 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21361 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21363 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21364 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21368 static char str[160]; /* 8 spare */
21370 const char *ptrload = TARGET_64BIT ? "d" : "wz";
21372 if (DEFAULT_ABI == ABI_AIX)
21375 ptrload, funop + 2);
21377 /* We don't need the extra code to stop indirect call speculation if
21379 bool speculate = (TARGET_MACHO
21380 || rs6000_speculate_indirect_jumps
21381 || (REG_P (operands[funop])
21382 && REGNO (operands[funop]) == LR_REGNO));
21384 if (TARGET_PLTSEQ && GET_CODE (operands[funop]) == UNSPEC)
21386 const char *rel64 = TARGET_64BIT ? "64" : "";
21389 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21391 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21392 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21394 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21395 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21398 gcc_unreachable ();
21401 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21402 && flag_pic == 2 ? "+32768" : "");
21406 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21407 tls, rel64, funop, addend);
21408 s += sprintf (s, "crset 2\n\t");
21411 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21412 tls, rel64, funop, addend);
21414 else if (!speculate)
21415 s += sprintf (s, "crset 2\n\t");
21417 if (DEFAULT_ABI == ABI_AIX)
21423 funop, ptrload, funop + 3);
21428 funop, ptrload, funop + 3);
21430 else if (DEFAULT_ABI == ABI_ELFv2)
21436 funop, ptrload, funop + 2);
21441 funop, ptrload, funop + 2);
21448 funop, sibcall ? "" : "l");
21452 funop, sibcall ? "" : "l", sibcall ? "\n\tb $" : "");
21458 rs6000_indirect_call_template (rtx *operands, unsigned int funop)
21460 return rs6000_indirect_call_template_1 (operands, funop, false);
21464 rs6000_indirect_sibcall_template (rtx *operands, unsigned int funop)
21466 return rs6000_indirect_call_template_1 (operands, funop, true);
21470 /* Output indirect call insns.
21471 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21473 rs6000_pltseq_template (rtx *operands, int which)
21475 const char *rel64 = TARGET_64BIT ? "64" : "";
21478 if (TARGET_TLS_MARKERS && GET_CODE (operands[3]) == UNSPEC)
21480 if (XINT (operands[3], 1) == UNSPEC_TLSGD)
21481 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21483 else if (XINT (operands[3], 1) == UNSPEC_TLSLD)
21484 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21487 gcc_unreachable ();
21490 gcc_assert (DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4);
21491 static char str[96]; /* 15 spare */
21492 const char *off = WORDS_BIG_ENDIAN ? "+2" : "";
21493 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21494 && flag_pic == 2 ? "+32768" : "");
21499 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21501 tls, rel64, TARGET_64BIT ? "d 2,24(1)" : "w 2,12(1)");
21504 if (DEFAULT_ABI == ABI_V4 && !flag_pic)
21506 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21511 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21513 tls, off, rel64, addend);
21517 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21519 tls, off, rel64, TARGET_64BIT ? "_DS" : "", addend,
21520 TARGET_64BIT ? "d" : "wz");
21524 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21526 tls, rel64, addend);
21529 gcc_unreachable ();
21535 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21536 /* Emit an assembler directive to set symbol visibility for DECL to
21537 VISIBILITY_TYPE. */
21540 rs6000_assemble_visibility (tree decl, int vis)
21545 /* Functions need to have their entry point symbol visibility set as
21546 well as their descriptor symbol visibility. */
21547 if (DEFAULT_ABI == ABI_AIX
21549 && TREE_CODE (decl) == FUNCTION_DECL)
21551 static const char * const visibility_types[] = {
21552 NULL, "protected", "hidden", "internal"
21555 const char *name, *type;
21557 name = ((* targetm.strip_name_encoding)
21558 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21559 type = visibility_types[vis];
21561 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21562 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21565 default_assemble_visibility (decl, vis);
21570 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21572 /* Reversal of FP compares takes care -- an ordered compare
21573 becomes an unordered compare and vice versa. */
21574 if (mode == CCFPmode
21575 && (!flag_finite_math_only
21576 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21577 || code == UNEQ || code == LTGT))
21578 return reverse_condition_maybe_unordered (code);
21580 return reverse_condition (code);
21583 /* Generate a compare for CODE. Return a brand-new rtx that
21584 represents the result of the compare. */
21587 rs6000_generate_compare (rtx cmp, machine_mode mode)
21589 machine_mode comp_mode;
21590 rtx compare_result;
21591 enum rtx_code code = GET_CODE (cmp);
21592 rtx op0 = XEXP (cmp, 0);
21593 rtx op1 = XEXP (cmp, 1);
21595 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21596 comp_mode = CCmode;
21597 else if (FLOAT_MODE_P (mode))
21598 comp_mode = CCFPmode;
21599 else if (code == GTU || code == LTU
21600 || code == GEU || code == LEU)
21601 comp_mode = CCUNSmode;
21602 else if ((code == EQ || code == NE)
21603 && unsigned_reg_p (op0)
21604 && (unsigned_reg_p (op1)
21605 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21606 /* These are unsigned values, perhaps there will be a later
21607 ordering compare that can be shared with this one. */
21608 comp_mode = CCUNSmode;
21610 comp_mode = CCmode;
21612 /* If we have an unsigned compare, make sure we don't have a signed value as
21614 if (comp_mode == CCUNSmode && CONST_INT_P (op1)
21615 && INTVAL (op1) < 0)
21617 op0 = copy_rtx_if_shared (op0);
21618 op1 = force_reg (GET_MODE (op0), op1);
21619 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21622 /* First, the compare. */
21623 compare_result = gen_reg_rtx (comp_mode);
21625 /* IEEE 128-bit support in VSX registers when we do not have hardware
21627 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21629 rtx libfunc = NULL_RTX;
21630 bool check_nan = false;
21637 libfunc = optab_libfunc (eq_optab, mode);
21642 libfunc = optab_libfunc (ge_optab, mode);
21647 libfunc = optab_libfunc (le_optab, mode);
21652 libfunc = optab_libfunc (unord_optab, mode);
21653 code = (code == UNORDERED) ? NE : EQ;
21659 libfunc = optab_libfunc (ge_optab, mode);
21660 code = (code == UNGE) ? GE : GT;
21666 libfunc = optab_libfunc (le_optab, mode);
21667 code = (code == UNLE) ? LE : LT;
21673 libfunc = optab_libfunc (eq_optab, mode);
21674 code = (code = UNEQ) ? EQ : NE;
21678 gcc_unreachable ();
21681 gcc_assert (libfunc);
21684 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21685 SImode, op0, mode, op1, mode);
21687 /* The library signals an exception for signalling NaNs, so we need to
21688 handle isgreater, etc. by first checking isordered. */
21691 rtx ne_rtx, normal_dest, unord_dest;
21692 rtx unord_func = optab_libfunc (unord_optab, mode);
21693 rtx join_label = gen_label_rtx ();
21694 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21695 rtx unord_cmp = gen_reg_rtx (comp_mode);
21698 /* Test for either value being a NaN. */
21699 gcc_assert (unord_func);
21700 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21701 SImode, op0, mode, op1, mode);
21703 /* Set value (0) if either value is a NaN, and jump to the join
21705 dest = gen_reg_rtx (SImode);
21706 emit_move_insn (dest, const1_rtx);
21707 emit_insn (gen_rtx_SET (unord_cmp,
21708 gen_rtx_COMPARE (comp_mode, unord_dest,
21711 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21712 emit_jump_insn (gen_rtx_SET (pc_rtx,
21713 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21717 /* Do the normal comparison, knowing that the values are not
21719 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21720 SImode, op0, mode, op1, mode);
21722 emit_insn (gen_cstoresi4 (dest,
21723 gen_rtx_fmt_ee (code, SImode, normal_dest,
21725 normal_dest, const0_rtx));
21727 /* Join NaN and non-Nan paths. Compare dest against 0. */
21728 emit_label (join_label);
21732 emit_insn (gen_rtx_SET (compare_result,
21733 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21738 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21739 CLOBBERs to match cmptf_internal2 pattern. */
21740 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21741 && FLOAT128_IBM_P (GET_MODE (op0))
21742 && TARGET_HARD_FLOAT)
21743 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21745 gen_rtx_SET (compare_result,
21746 gen_rtx_COMPARE (comp_mode, op0, op1)),
21747 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21748 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21749 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21750 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21751 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21752 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21753 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21754 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21755 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21756 else if (GET_CODE (op1) == UNSPEC
21757 && XINT (op1, 1) == UNSPEC_SP_TEST)
21759 rtx op1b = XVECEXP (op1, 0, 0);
21760 comp_mode = CCEQmode;
21761 compare_result = gen_reg_rtx (CCEQmode);
21763 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21765 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21768 emit_insn (gen_rtx_SET (compare_result,
21769 gen_rtx_COMPARE (comp_mode, op0, op1)));
21772 /* Some kinds of FP comparisons need an OR operation;
21773 under flag_finite_math_only we don't bother. */
21774 if (FLOAT_MODE_P (mode)
21775 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21776 && !flag_finite_math_only
21777 && (code == LE || code == GE
21778 || code == UNEQ || code == LTGT
21779 || code == UNGT || code == UNLT))
21781 enum rtx_code or1, or2;
21782 rtx or1_rtx, or2_rtx, compare2_rtx;
21783 rtx or_result = gen_reg_rtx (CCEQmode);
21787 case LE: or1 = LT; or2 = EQ; break;
21788 case GE: or1 = GT; or2 = EQ; break;
21789 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21790 case LTGT: or1 = LT; or2 = GT; break;
21791 case UNGT: or1 = UNORDERED; or2 = GT; break;
21792 case UNLT: or1 = UNORDERED; or2 = LT; break;
21793 default: gcc_unreachable ();
21795 validate_condition_mode (or1, comp_mode);
21796 validate_condition_mode (or2, comp_mode);
21797 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21798 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21799 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21800 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21802 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21804 compare_result = or_result;
21808 validate_condition_mode (code, GET_MODE (compare_result));
21810 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21814 /* Return the diagnostic message string if the binary operation OP is
21815 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21818 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21822 machine_mode mode1 = TYPE_MODE (type1);
21823 machine_mode mode2 = TYPE_MODE (type2);
21825 /* For complex modes, use the inner type. */
21826 if (COMPLEX_MODE_P (mode1))
21827 mode1 = GET_MODE_INNER (mode1);
21829 if (COMPLEX_MODE_P (mode2))
21830 mode2 = GET_MODE_INNER (mode2);
21832 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21833 double to intermix unless -mfloat128-convert. */
21834 if (mode1 == mode2)
21837 if (!TARGET_FLOAT128_CVT)
21839 if ((mode1 == KFmode && mode2 == IFmode)
21840 || (mode1 == IFmode && mode2 == KFmode))
21841 return N_("__float128 and __ibm128 cannot be used in the same "
21844 if (TARGET_IEEEQUAD
21845 && ((mode1 == IFmode && mode2 == TFmode)
21846 || (mode1 == TFmode && mode2 == IFmode)))
21847 return N_("__ibm128 and long double cannot be used in the same "
21850 if (!TARGET_IEEEQUAD
21851 && ((mode1 == KFmode && mode2 == TFmode)
21852 || (mode1 == TFmode && mode2 == KFmode)))
21853 return N_("__float128 and long double cannot be used in the same "
21861 /* Expand floating point conversion to/from __float128 and __ibm128. */
21864 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21866 machine_mode dest_mode = GET_MODE (dest);
21867 machine_mode src_mode = GET_MODE (src);
21868 convert_optab cvt = unknown_optab;
21869 bool do_move = false;
21870 rtx libfunc = NULL_RTX;
21872 typedef rtx (*rtx_2func_t) (rtx, rtx);
21873 rtx_2func_t hw_convert = (rtx_2func_t)0;
21877 rtx_2func_t from_df;
21878 rtx_2func_t from_sf;
21879 rtx_2func_t from_si_sign;
21880 rtx_2func_t from_si_uns;
21881 rtx_2func_t from_di_sign;
21882 rtx_2func_t from_di_uns;
21885 rtx_2func_t to_si_sign;
21886 rtx_2func_t to_si_uns;
21887 rtx_2func_t to_di_sign;
21888 rtx_2func_t to_di_uns;
21889 } hw_conversions[2] = {
21890 /* convertions to/from KFmode */
21892 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21893 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21894 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21895 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21896 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21897 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21898 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21899 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21900 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21901 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21902 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21903 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21906 /* convertions to/from TFmode */
21908 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21909 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21910 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21911 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21912 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21913 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21914 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21915 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21916 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21917 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21918 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21919 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21923 if (dest_mode == src_mode)
21924 gcc_unreachable ();
21926 /* Eliminate memory operations. */
21928 src = force_reg (src_mode, src);
21932 rtx tmp = gen_reg_rtx (dest_mode);
21933 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21934 rs6000_emit_move (dest, tmp, dest_mode);
21938 /* Convert to IEEE 128-bit floating point. */
21939 if (FLOAT128_IEEE_P (dest_mode))
21941 if (dest_mode == KFmode)
21943 else if (dest_mode == TFmode)
21946 gcc_unreachable ();
21952 hw_convert = hw_conversions[kf_or_tf].from_df;
21957 hw_convert = hw_conversions[kf_or_tf].from_sf;
21963 if (FLOAT128_IBM_P (src_mode))
21972 cvt = ufloat_optab;
21973 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21977 cvt = sfloat_optab;
21978 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21985 cvt = ufloat_optab;
21986 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21990 cvt = sfloat_optab;
21991 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21996 gcc_unreachable ();
22000 /* Convert from IEEE 128-bit floating point. */
22001 else if (FLOAT128_IEEE_P (src_mode))
22003 if (src_mode == KFmode)
22005 else if (src_mode == TFmode)
22008 gcc_unreachable ();
22014 hw_convert = hw_conversions[kf_or_tf].to_df;
22019 hw_convert = hw_conversions[kf_or_tf].to_sf;
22025 if (FLOAT128_IBM_P (dest_mode))
22035 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22040 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22048 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22053 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22058 gcc_unreachable ();
22062 /* Both IBM format. */
22063 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22067 gcc_unreachable ();
22069 /* Handle conversion between TFmode/KFmode/IFmode. */
22071 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
22073 /* Handle conversion if we have hardware support. */
22074 else if (TARGET_FLOAT128_HW && hw_convert)
22075 emit_insn ((hw_convert) (dest, src));
22077 /* Call an external function to do the conversion. */
22078 else if (cvt != unknown_optab)
22080 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22081 gcc_assert (libfunc != NULL_RTX);
22083 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22086 gcc_assert (dest2 != NULL_RTX);
22087 if (!rtx_equal_p (dest, dest2))
22088 emit_move_insn (dest, dest2);
22092 gcc_unreachable ();
22098 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22099 can be used as that dest register. Return the dest register. */
22102 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22104 if (op2 == const0_rtx)
22107 if (GET_CODE (scratch) == SCRATCH)
22108 scratch = gen_reg_rtx (mode);
22110 if (logical_operand (op2, mode))
22111 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22113 emit_insn (gen_rtx_SET (scratch,
22114 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22120 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22123 machine_mode op_mode;
22124 enum rtx_code cond_code;
22125 rtx result = operands[0];
22127 condition_rtx = rs6000_generate_compare (operands[1], mode);
22128 cond_code = GET_CODE (condition_rtx);
22130 if (cond_code == NE
22131 || cond_code == GE || cond_code == LE
22132 || cond_code == GEU || cond_code == LEU
22133 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22135 rtx not_result = gen_reg_rtx (CCEQmode);
22136 rtx not_op, rev_cond_rtx;
22137 machine_mode cc_mode;
22139 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22141 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22142 SImode, XEXP (condition_rtx, 0), const0_rtx);
22143 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22144 emit_insn (gen_rtx_SET (not_result, not_op));
22145 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22148 op_mode = GET_MODE (XEXP (operands[1], 0));
22149 if (op_mode == VOIDmode)
22150 op_mode = GET_MODE (XEXP (operands[1], 1));
22152 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22154 PUT_MODE (condition_rtx, DImode);
22155 convert_move (result, condition_rtx, 0);
22159 PUT_MODE (condition_rtx, SImode);
22160 emit_insn (gen_rtx_SET (result, condition_rtx));
22164 /* Emit a branch of kind CODE to location LOC. */
22167 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22169 rtx condition_rtx, loc_ref;
22171 condition_rtx = rs6000_generate_compare (operands[0], mode);
22172 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22173 emit_jump_insn (gen_rtx_SET (pc_rtx,
22174 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22175 loc_ref, pc_rtx)));
22178 /* Return the string to output a conditional branch to LABEL, which is
22179 the operand template of the label, or NULL if the branch is really a
22180 conditional return.
22182 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22183 condition code register and its mode specifies what kind of
22184 comparison we made.
22186 REVERSED is nonzero if we should reverse the sense of the comparison.
22188 INSN is the insn. */
22191 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22193 static char string[64];
22194 enum rtx_code code = GET_CODE (op);
22195 rtx cc_reg = XEXP (op, 0);
22196 machine_mode mode = GET_MODE (cc_reg);
22197 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22198 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22199 int really_reversed = reversed ^ need_longbranch;
22205 validate_condition_mode (code, mode);
22207 /* Work out which way this really branches. We could use
22208 reverse_condition_maybe_unordered here always but this
22209 makes the resulting assembler clearer. */
22210 if (really_reversed)
22212 /* Reversal of FP compares takes care -- an ordered compare
22213 becomes an unordered compare and vice versa. */
22214 if (mode == CCFPmode)
22215 code = reverse_condition_maybe_unordered (code);
22217 code = reverse_condition (code);
22222 /* Not all of these are actually distinct opcodes, but
22223 we distinguish them for clarity of the resulting assembler. */
22224 case NE: case LTGT:
22225 ccode = "ne"; break;
22226 case EQ: case UNEQ:
22227 ccode = "eq"; break;
22229 ccode = "ge"; break;
22230 case GT: case GTU: case UNGT:
22231 ccode = "gt"; break;
22233 ccode = "le"; break;
22234 case LT: case LTU: case UNLT:
22235 ccode = "lt"; break;
22236 case UNORDERED: ccode = "un"; break;
22237 case ORDERED: ccode = "nu"; break;
22238 case UNGE: ccode = "nl"; break;
22239 case UNLE: ccode = "ng"; break;
22241 gcc_unreachable ();
22244 /* Maybe we have a guess as to how likely the branch is. */
22246 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22247 if (note != NULL_RTX)
22249 /* PROB is the difference from 50%. */
22250 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22251 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22253 /* Only hint for highly probable/improbable branches on newer cpus when
22254 we have real profile data, as static prediction overrides processor
22255 dynamic prediction. For older cpus we may as well always hint, but
22256 assume not taken for branches that are very close to 50% as a
22257 mispredicted taken branch is more expensive than a
22258 mispredicted not-taken branch. */
22259 if (rs6000_always_hint
22260 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22261 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22262 && br_prob_note_reliable_p (note)))
22264 if (abs (prob) > REG_BR_PROB_BASE / 20
22265 && ((prob > 0) ^ need_longbranch))
22273 s += sprintf (s, "b%slr%s ", ccode, pred);
22275 s += sprintf (s, "b%s%s ", ccode, pred);
22277 /* We need to escape any '%' characters in the reg_names string.
22278 Assume they'd only be the first character.... */
22279 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22281 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22285 /* If the branch distance was too far, we may have to use an
22286 unconditional branch to go the distance. */
22287 if (need_longbranch)
22288 s += sprintf (s, ",$+8\n\tb %s", label);
22290 s += sprintf (s, ",%s", label);
22296 /* Return insn for VSX or Altivec comparisons. */
22299 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22302 machine_mode mode = GET_MODE (op0);
22310 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22321 mask = gen_reg_rtx (mode);
22322 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22329 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22330 DMODE is expected destination mode. This is a recursive function. */
22333 rs6000_emit_vector_compare (enum rtx_code rcode,
22335 machine_mode dmode)
22338 bool swap_operands = false;
22339 bool try_again = false;
22341 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22342 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22344 /* See if the comparison works as is. */
22345 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22353 swap_operands = true;
22358 swap_operands = true;
22366 /* Invert condition and try again.
22367 e.g., A != B becomes ~(A==B). */
22369 enum rtx_code rev_code;
22370 enum insn_code nor_code;
22373 rev_code = reverse_condition_maybe_unordered (rcode);
22374 if (rev_code == UNKNOWN)
22377 nor_code = optab_handler (one_cmpl_optab, dmode);
22378 if (nor_code == CODE_FOR_nothing)
22381 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22385 mask = gen_reg_rtx (dmode);
22386 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22394 /* Try GT/GTU/LT/LTU OR EQ */
22397 enum insn_code ior_code;
22398 enum rtx_code new_code;
22419 gcc_unreachable ();
22422 ior_code = optab_handler (ior_optab, dmode);
22423 if (ior_code == CODE_FOR_nothing)
22426 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22430 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22434 mask = gen_reg_rtx (dmode);
22435 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22446 std::swap (op0, op1);
22448 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22453 /* You only get two chances. */
22457 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22458 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22459 operands for the relation operation COND. */
22462 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22463 rtx cond, rtx cc_op0, rtx cc_op1)
22465 machine_mode dest_mode = GET_MODE (dest);
22466 machine_mode mask_mode = GET_MODE (cc_op0);
22467 enum rtx_code rcode = GET_CODE (cond);
22468 machine_mode cc_mode = CCmode;
22471 bool invert_move = false;
22473 if (VECTOR_UNIT_NONE_P (dest_mode))
22476 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22477 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22481 /* Swap operands if we can, and fall back to doing the operation as
22482 specified, and doing a NOR to invert the test. */
22488 /* Invert condition and try again.
22489 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22490 invert_move = true;
22491 rcode = reverse_condition_maybe_unordered (rcode);
22492 if (rcode == UNKNOWN)
22498 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22500 /* Invert condition to avoid compound test. */
22501 invert_move = true;
22502 rcode = reverse_condition (rcode);
22510 /* Mark unsigned tests with CCUNSmode. */
22511 cc_mode = CCUNSmode;
22513 /* Invert condition to avoid compound test if necessary. */
22514 if (rcode == GEU || rcode == LEU)
22516 invert_move = true;
22517 rcode = reverse_condition (rcode);
22525 /* Get the vector mask for the given relational operations. */
22526 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22532 std::swap (op_true, op_false);
22534 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22535 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22536 && (GET_CODE (op_true) == CONST_VECTOR
22537 || GET_CODE (op_false) == CONST_VECTOR))
22539 rtx constant_0 = CONST0_RTX (dest_mode);
22540 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22542 if (op_true == constant_m1 && op_false == constant_0)
22544 emit_move_insn (dest, mask);
22548 else if (op_true == constant_0 && op_false == constant_m1)
22550 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22554 /* If we can't use the vector comparison directly, perhaps we can use
22555 the mask for the true or false fields, instead of loading up a
22557 if (op_true == constant_m1)
22560 if (op_false == constant_0)
22564 if (!REG_P (op_true) && !SUBREG_P (op_true))
22565 op_true = force_reg (dest_mode, op_true);
22567 if (!REG_P (op_false) && !SUBREG_P (op_false))
22568 op_false = force_reg (dest_mode, op_false);
22570 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22571 CONST0_RTX (dest_mode));
22572 emit_insn (gen_rtx_SET (dest,
22573 gen_rtx_IF_THEN_ELSE (dest_mode,
22580 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22581 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22582 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22583 hardware has no such operation. */
22586 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22588 enum rtx_code code = GET_CODE (op);
22589 rtx op0 = XEXP (op, 0);
22590 rtx op1 = XEXP (op, 1);
22591 machine_mode compare_mode = GET_MODE (op0);
22592 machine_mode result_mode = GET_MODE (dest);
22593 bool max_p = false;
22595 if (result_mode != compare_mode)
22598 if (code == GE || code == GT)
22600 else if (code == LE || code == LT)
22605 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22608 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22614 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22618 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22619 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22620 operands of the last comparison is nonzero/true, FALSE_COND if it is
22621 zero/false. Return 0 if the hardware has no such operation. */
22624 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22626 enum rtx_code code = GET_CODE (op);
22627 rtx op0 = XEXP (op, 0);
22628 rtx op1 = XEXP (op, 1);
22629 machine_mode result_mode = GET_MODE (dest);
22634 if (!can_create_pseudo_p ())
22647 code = swap_condition (code);
22648 std::swap (op0, op1);
22655 /* Generate: [(parallel [(set (dest)
22656 (if_then_else (op (cmp1) (cmp2))
22659 (clobber (scratch))])]. */
22661 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22662 cmove_rtx = gen_rtx_SET (dest,
22663 gen_rtx_IF_THEN_ELSE (result_mode,
22668 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22669 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22670 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22675 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22676 operands of the last comparison is nonzero/true, FALSE_COND if it
22677 is zero/false. Return 0 if the hardware has no such operation. */
22680 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22682 enum rtx_code code = GET_CODE (op);
22683 rtx op0 = XEXP (op, 0);
22684 rtx op1 = XEXP (op, 1);
22685 machine_mode compare_mode = GET_MODE (op0);
22686 machine_mode result_mode = GET_MODE (dest);
22688 bool is_against_zero;
22690 /* These modes should always match. */
22691 if (GET_MODE (op1) != compare_mode
22692 /* In the isel case however, we can use a compare immediate, so
22693 op1 may be a small constant. */
22694 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22696 if (GET_MODE (true_cond) != result_mode)
22698 if (GET_MODE (false_cond) != result_mode)
22701 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22702 if (TARGET_P9_MINMAX
22703 && (compare_mode == SFmode || compare_mode == DFmode)
22704 && (result_mode == SFmode || result_mode == DFmode))
22706 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22709 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22713 /* Don't allow using floating point comparisons for integer results for
22715 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22718 /* First, work out if the hardware can do this at all, or
22719 if it's too slow.... */
22720 if (!FLOAT_MODE_P (compare_mode))
22723 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22727 is_against_zero = op1 == CONST0_RTX (compare_mode);
22729 /* A floating-point subtract might overflow, underflow, or produce
22730 an inexact result, thus changing the floating-point flags, so it
22731 can't be generated if we care about that. It's safe if one side
22732 of the construct is zero, since then no subtract will be
22734 if (SCALAR_FLOAT_MODE_P (compare_mode)
22735 && flag_trapping_math && ! is_against_zero)
22738 /* Eliminate half of the comparisons by switching operands, this
22739 makes the remaining code simpler. */
22740 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22741 || code == LTGT || code == LT || code == UNLE)
22743 code = reverse_condition_maybe_unordered (code);
22745 true_cond = false_cond;
22749 /* UNEQ and LTGT take four instructions for a comparison with zero,
22750 it'll probably be faster to use a branch here too. */
22751 if (code == UNEQ && HONOR_NANS (compare_mode))
22754 /* We're going to try to implement comparisons by performing
22755 a subtract, then comparing against zero. Unfortunately,
22756 Inf - Inf is NaN which is not zero, and so if we don't
22757 know that the operand is finite and the comparison
22758 would treat EQ different to UNORDERED, we can't do it. */
22759 if (HONOR_INFINITIES (compare_mode)
22760 && code != GT && code != UNGE
22761 && (!CONST_DOUBLE_P (op1)
22762 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22763 /* Constructs of the form (a OP b ? a : b) are safe. */
22764 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22765 || (! rtx_equal_p (op0, true_cond)
22766 && ! rtx_equal_p (op1, true_cond))))
22769 /* At this point we know we can use fsel. */
22771 /* Reduce the comparison to a comparison against zero. */
22772 if (! is_against_zero)
22774 temp = gen_reg_rtx (compare_mode);
22775 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22777 op1 = CONST0_RTX (compare_mode);
22780 /* If we don't care about NaNs we can reduce some of the comparisons
22781 down to faster ones. */
22782 if (! HONOR_NANS (compare_mode))
22788 true_cond = false_cond;
22801 /* Now, reduce everything down to a GE. */
22808 temp = gen_reg_rtx (compare_mode);
22809 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22814 temp = gen_reg_rtx (compare_mode);
22815 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22820 temp = gen_reg_rtx (compare_mode);
22821 emit_insn (gen_rtx_SET (temp,
22822 gen_rtx_NEG (compare_mode,
22823 gen_rtx_ABS (compare_mode, op0))));
22828 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22829 temp = gen_reg_rtx (result_mode);
22830 emit_insn (gen_rtx_SET (temp,
22831 gen_rtx_IF_THEN_ELSE (result_mode,
22832 gen_rtx_GE (VOIDmode,
22834 true_cond, false_cond)));
22835 false_cond = true_cond;
22838 temp = gen_reg_rtx (compare_mode);
22839 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22844 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22845 temp = gen_reg_rtx (result_mode);
22846 emit_insn (gen_rtx_SET (temp,
22847 gen_rtx_IF_THEN_ELSE (result_mode,
22848 gen_rtx_GE (VOIDmode,
22850 true_cond, false_cond)));
22851 true_cond = false_cond;
22854 temp = gen_reg_rtx (compare_mode);
22855 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22860 gcc_unreachable ();
22863 emit_insn (gen_rtx_SET (dest,
22864 gen_rtx_IF_THEN_ELSE (result_mode,
22865 gen_rtx_GE (VOIDmode,
22867 true_cond, false_cond)));
22871 /* Same as above, but for ints (isel). */
22874 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22876 rtx condition_rtx, cr;
22877 machine_mode mode = GET_MODE (dest);
22878 enum rtx_code cond_code;
22879 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22882 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22885 /* We still have to do the compare, because isel doesn't do a
22886 compare, it just looks at the CRx bits set by a previous compare
22888 condition_rtx = rs6000_generate_compare (op, mode);
22889 cond_code = GET_CODE (condition_rtx);
22890 cr = XEXP (condition_rtx, 0);
22891 signedp = GET_MODE (cr) == CCmode;
22893 isel_func = (mode == SImode
22894 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22895 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22899 case LT: case GT: case LTU: case GTU: case EQ:
22900 /* isel handles these directly. */
22904 /* We need to swap the sense of the comparison. */
22906 std::swap (false_cond, true_cond);
22907 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22912 false_cond = force_reg (mode, false_cond);
22913 if (true_cond != const0_rtx)
22914 true_cond = force_reg (mode, true_cond);
22916 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22922 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22924 machine_mode mode = GET_MODE (op0);
22928 /* VSX/altivec have direct min/max insns. */
22929 if ((code == SMAX || code == SMIN)
22930 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22931 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22933 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22937 if (code == SMAX || code == SMIN)
22942 if (code == SMAX || code == UMAX)
22943 target = emit_conditional_move (dest, c, op0, op1, mode,
22944 op0, op1, mode, 0);
22946 target = emit_conditional_move (dest, c, op0, op1, mode,
22947 op1, op0, mode, 0);
22948 gcc_assert (target);
22949 if (target != dest)
22950 emit_move_insn (dest, target);
22953 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22954 COND is true. Mark the jump as unlikely to be taken. */
22957 emit_unlikely_jump (rtx cond, rtx label)
22959 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22960 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22961 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22964 /* A subroutine of the atomic operation splitters. Emit a load-locked
22965 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22966 the zero_extend operation. */
22969 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22971 rtx (*fn) (rtx, rtx) = NULL;
22976 fn = gen_load_lockedqi;
22979 fn = gen_load_lockedhi;
22982 if (GET_MODE (mem) == QImode)
22983 fn = gen_load_lockedqi_si;
22984 else if (GET_MODE (mem) == HImode)
22985 fn = gen_load_lockedhi_si;
22987 fn = gen_load_lockedsi;
22990 fn = gen_load_lockeddi;
22993 fn = gen_load_lockedti;
22996 gcc_unreachable ();
22998 emit_insn (fn (reg, mem));
23001 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23002 instruction in MODE. */
23005 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23007 rtx (*fn) (rtx, rtx, rtx) = NULL;
23012 fn = gen_store_conditionalqi;
23015 fn = gen_store_conditionalhi;
23018 fn = gen_store_conditionalsi;
23021 fn = gen_store_conditionaldi;
23024 fn = gen_store_conditionalti;
23027 gcc_unreachable ();
23030 /* Emit sync before stwcx. to address PPC405 Erratum. */
23031 if (PPC405_ERRATUM77)
23032 emit_insn (gen_hwsync ());
23034 emit_insn (fn (res, mem, val));
23037 /* Expand barriers before and after a load_locked/store_cond sequence. */
23040 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23042 rtx addr = XEXP (mem, 0);
23044 if (!legitimate_indirect_address_p (addr, reload_completed)
23045 && !legitimate_indexed_address_p (addr, reload_completed))
23047 addr = force_reg (Pmode, addr);
23048 mem = replace_equiv_address_nv (mem, addr);
23053 case MEMMODEL_RELAXED:
23054 case MEMMODEL_CONSUME:
23055 case MEMMODEL_ACQUIRE:
23057 case MEMMODEL_RELEASE:
23058 case MEMMODEL_ACQ_REL:
23059 emit_insn (gen_lwsync ());
23061 case MEMMODEL_SEQ_CST:
23062 emit_insn (gen_hwsync ());
23065 gcc_unreachable ();
23071 rs6000_post_atomic_barrier (enum memmodel model)
23075 case MEMMODEL_RELAXED:
23076 case MEMMODEL_CONSUME:
23077 case MEMMODEL_RELEASE:
23079 case MEMMODEL_ACQUIRE:
23080 case MEMMODEL_ACQ_REL:
23081 case MEMMODEL_SEQ_CST:
23082 emit_insn (gen_isync ());
23085 gcc_unreachable ();
23089 /* A subroutine of the various atomic expanders. For sub-word operations,
23090 we must adjust things to operate on SImode. Given the original MEM,
23091 return a new aligned memory. Also build and return the quantities by
23092 which to shift and mask. */
23095 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23097 rtx addr, align, shift, mask, mem;
23098 HOST_WIDE_INT shift_mask;
23099 machine_mode mode = GET_MODE (orig_mem);
23101 /* For smaller modes, we have to implement this via SImode. */
23102 shift_mask = (mode == QImode ? 0x18 : 0x10);
23104 addr = XEXP (orig_mem, 0);
23105 addr = force_reg (GET_MODE (addr), addr);
23107 /* Aligned memory containing subword. Generate a new memory. We
23108 do not want any of the existing MEM_ATTR data, as we're now
23109 accessing memory outside the original object. */
23110 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23111 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23112 mem = gen_rtx_MEM (SImode, align);
23113 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23114 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23115 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23117 /* Shift amount for subword relative to aligned word. */
23118 shift = gen_reg_rtx (SImode);
23119 addr = gen_lowpart (SImode, addr);
23120 rtx tmp = gen_reg_rtx (SImode);
23121 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23122 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23123 if (BYTES_BIG_ENDIAN)
23124 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23125 shift, 1, OPTAB_LIB_WIDEN);
23128 /* Mask for insertion. */
23129 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23130 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23136 /* A subroutine of the various atomic expanders. For sub-word operands,
23137 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23140 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23144 x = gen_reg_rtx (SImode);
23145 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23146 gen_rtx_NOT (SImode, mask),
23149 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23154 /* A subroutine of the various atomic expanders. For sub-word operands,
23155 extract WIDE to NARROW via SHIFT. */
23158 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23160 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23161 wide, 1, OPTAB_LIB_WIDEN);
23162 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23165 /* Expand an atomic compare and swap operation. */
23168 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23170 rtx boolval, retval, mem, oldval, newval, cond;
23171 rtx label1, label2, x, mask, shift;
23172 machine_mode mode, orig_mode;
23173 enum memmodel mod_s, mod_f;
23176 boolval = operands[0];
23177 retval = operands[1];
23179 oldval = operands[3];
23180 newval = operands[4];
23181 is_weak = (INTVAL (operands[5]) != 0);
23182 mod_s = memmodel_base (INTVAL (operands[6]));
23183 mod_f = memmodel_base (INTVAL (operands[7]));
23184 orig_mode = mode = GET_MODE (mem);
23186 mask = shift = NULL_RTX;
23187 if (mode == QImode || mode == HImode)
23189 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23190 lwarx and shift/mask operations. With power8, we need to do the
23191 comparison in SImode, but the store is still done in QI/HImode. */
23192 oldval = convert_modes (SImode, mode, oldval, 1);
23194 if (!TARGET_SYNC_HI_QI)
23196 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23198 /* Shift and mask OLDVAL into position with the word. */
23199 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23200 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23202 /* Shift and mask NEWVAL into position within the word. */
23203 newval = convert_modes (SImode, mode, newval, 1);
23204 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23205 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23208 /* Prepare to adjust the return value. */
23209 retval = gen_reg_rtx (SImode);
23212 else if (reg_overlap_mentioned_p (retval, oldval))
23213 oldval = copy_to_reg (oldval);
23215 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23216 oldval = copy_to_mode_reg (mode, oldval);
23218 if (reg_overlap_mentioned_p (retval, newval))
23219 newval = copy_to_reg (newval);
23221 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23226 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23227 emit_label (XEXP (label1, 0));
23229 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23231 emit_load_locked (mode, retval, mem);
23235 x = expand_simple_binop (SImode, AND, retval, mask,
23236 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23238 cond = gen_reg_rtx (CCmode);
23239 /* If we have TImode, synthesize a comparison. */
23240 if (mode != TImode)
23241 x = gen_rtx_COMPARE (CCmode, x, oldval);
23244 rtx xor1_result = gen_reg_rtx (DImode);
23245 rtx xor2_result = gen_reg_rtx (DImode);
23246 rtx or_result = gen_reg_rtx (DImode);
23247 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23248 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23249 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23250 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23252 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23253 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23254 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23255 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23258 emit_insn (gen_rtx_SET (cond, x));
23260 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23261 emit_unlikely_jump (x, label2);
23265 x = rs6000_mask_atomic_subword (retval, newval, mask);
23267 emit_store_conditional (orig_mode, cond, mem, x);
23271 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23272 emit_unlikely_jump (x, label1);
23275 if (!is_mm_relaxed (mod_f))
23276 emit_label (XEXP (label2, 0));
23278 rs6000_post_atomic_barrier (mod_s);
23280 if (is_mm_relaxed (mod_f))
23281 emit_label (XEXP (label2, 0));
23284 rs6000_finish_atomic_subword (operands[1], retval, shift);
23285 else if (mode != GET_MODE (operands[1]))
23286 convert_move (operands[1], retval, 1);
23288 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23289 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23290 emit_insn (gen_rtx_SET (boolval, x));
23293 /* Expand an atomic exchange operation. */
23296 rs6000_expand_atomic_exchange (rtx operands[])
23298 rtx retval, mem, val, cond;
23300 enum memmodel model;
23301 rtx label, x, mask, shift;
23303 retval = operands[0];
23306 model = memmodel_base (INTVAL (operands[3]));
23307 mode = GET_MODE (mem);
23309 mask = shift = NULL_RTX;
23310 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23312 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23314 /* Shift and mask VAL into position with the word. */
23315 val = convert_modes (SImode, mode, val, 1);
23316 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23317 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23319 /* Prepare to adjust the return value. */
23320 retval = gen_reg_rtx (SImode);
23324 mem = rs6000_pre_atomic_barrier (mem, model);
23326 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23327 emit_label (XEXP (label, 0));
23329 emit_load_locked (mode, retval, mem);
23333 x = rs6000_mask_atomic_subword (retval, val, mask);
23335 cond = gen_reg_rtx (CCmode);
23336 emit_store_conditional (mode, cond, mem, x);
23338 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23339 emit_unlikely_jump (x, label);
23341 rs6000_post_atomic_barrier (model);
23344 rs6000_finish_atomic_subword (operands[0], retval, shift);
23347 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23348 to perform. MEM is the memory on which to operate. VAL is the second
23349 operand of the binary operator. BEFORE and AFTER are optional locations to
23350 return the value of MEM either before of after the operation. MODEL_RTX
23351 is a CONST_INT containing the memory model to use. */
23354 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23355 rtx orig_before, rtx orig_after, rtx model_rtx)
23357 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23358 machine_mode mode = GET_MODE (mem);
23359 machine_mode store_mode = mode;
23360 rtx label, x, cond, mask, shift;
23361 rtx before = orig_before, after = orig_after;
23363 mask = shift = NULL_RTX;
23364 /* On power8, we want to use SImode for the operation. On previous systems,
23365 use the operation in a subword and shift/mask to get the proper byte or
23367 if (mode == QImode || mode == HImode)
23369 if (TARGET_SYNC_HI_QI)
23371 val = convert_modes (SImode, mode, val, 1);
23373 /* Prepare to adjust the return value. */
23374 before = gen_reg_rtx (SImode);
23376 after = gen_reg_rtx (SImode);
23381 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23383 /* Shift and mask VAL into position with the word. */
23384 val = convert_modes (SImode, mode, val, 1);
23385 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23386 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23392 /* We've already zero-extended VAL. That is sufficient to
23393 make certain that it does not affect other bits. */
23398 /* If we make certain that all of the other bits in VAL are
23399 set, that will be sufficient to not affect other bits. */
23400 x = gen_rtx_NOT (SImode, mask);
23401 x = gen_rtx_IOR (SImode, x, val);
23402 emit_insn (gen_rtx_SET (val, x));
23409 /* These will all affect bits outside the field and need
23410 adjustment via MASK within the loop. */
23414 gcc_unreachable ();
23417 /* Prepare to adjust the return value. */
23418 before = gen_reg_rtx (SImode);
23420 after = gen_reg_rtx (SImode);
23421 store_mode = mode = SImode;
23425 mem = rs6000_pre_atomic_barrier (mem, model);
23427 label = gen_label_rtx ();
23428 emit_label (label);
23429 label = gen_rtx_LABEL_REF (VOIDmode, label);
23431 if (before == NULL_RTX)
23432 before = gen_reg_rtx (mode);
23434 emit_load_locked (mode, before, mem);
23438 x = expand_simple_binop (mode, AND, before, val,
23439 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23440 after = expand_simple_unop (mode, NOT, x, after, 1);
23444 after = expand_simple_binop (mode, code, before, val,
23445 after, 1, OPTAB_LIB_WIDEN);
23451 x = expand_simple_binop (SImode, AND, after, mask,
23452 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23453 x = rs6000_mask_atomic_subword (before, x, mask);
23455 else if (store_mode != mode)
23456 x = convert_modes (store_mode, mode, x, 1);
23458 cond = gen_reg_rtx (CCmode);
23459 emit_store_conditional (store_mode, cond, mem, x);
23461 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23462 emit_unlikely_jump (x, label);
23464 rs6000_post_atomic_barrier (model);
23468 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23469 then do the calcuations in a SImode register. */
23471 rs6000_finish_atomic_subword (orig_before, before, shift);
23473 rs6000_finish_atomic_subword (orig_after, after, shift);
23475 else if (store_mode != mode)
23477 /* QImode/HImode on machines with lbarx/lharx where we do the native
23478 operation and then do the calcuations in a SImode register. */
23480 convert_move (orig_before, before, 1);
23482 convert_move (orig_after, after, 1);
23484 else if (orig_after && after != orig_after)
23485 emit_move_insn (orig_after, after);
23488 /* Emit instructions to move SRC to DST. Called by splitters for
23489 multi-register moves. It will emit at most one instruction for
23490 each register that is accessed; that is, it won't emit li/lis pairs
23491 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23495 rs6000_split_multireg_move (rtx dst, rtx src)
23497 /* The register number of the first register being moved. */
23499 /* The mode that is to be moved. */
23501 /* The mode that the move is being done in, and its size. */
23502 machine_mode reg_mode;
23504 /* The number of registers that will be moved. */
23507 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23508 mode = GET_MODE (dst);
23509 nregs = hard_regno_nregs (reg, mode);
23510 if (FP_REGNO_P (reg))
23511 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23512 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23513 else if (ALTIVEC_REGNO_P (reg))
23514 reg_mode = V16QImode;
23516 reg_mode = word_mode;
23517 reg_mode_size = GET_MODE_SIZE (reg_mode);
23519 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23521 /* TDmode residing in FP registers is special, since the ISA requires that
23522 the lower-numbered word of a register pair is always the most significant
23523 word, even in little-endian mode. This does not match the usual subreg
23524 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23525 the appropriate constituent registers "by hand" in little-endian mode.
23527 Note we do not need to check for destructive overlap here since TDmode
23528 can only reside in even/odd register pairs. */
23529 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23534 for (i = 0; i < nregs; i++)
23536 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23537 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23539 p_src = simplify_gen_subreg (reg_mode, src, mode,
23540 i * reg_mode_size);
23542 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23543 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23545 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23546 i * reg_mode_size);
23548 emit_insn (gen_rtx_SET (p_dst, p_src));
23554 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23556 /* Move register range backwards, if we might have destructive
23559 for (i = nregs - 1; i >= 0; i--)
23560 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23561 i * reg_mode_size),
23562 simplify_gen_subreg (reg_mode, src, mode,
23563 i * reg_mode_size)));
23569 bool used_update = false;
23570 rtx restore_basereg = NULL_RTX;
23572 if (MEM_P (src) && INT_REGNO_P (reg))
23576 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23577 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23580 breg = XEXP (XEXP (src, 0), 0);
23581 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23582 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23583 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23584 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23585 src = replace_equiv_address (src, breg);
23587 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23589 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23591 rtx basereg = XEXP (XEXP (src, 0), 0);
23594 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23595 emit_insn (gen_rtx_SET (ndst,
23596 gen_rtx_MEM (reg_mode,
23598 used_update = true;
23601 emit_insn (gen_rtx_SET (basereg,
23602 XEXP (XEXP (src, 0), 1)));
23603 src = replace_equiv_address (src, basereg);
23607 rtx basereg = gen_rtx_REG (Pmode, reg);
23608 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23609 src = replace_equiv_address (src, basereg);
23613 breg = XEXP (src, 0);
23614 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23615 breg = XEXP (breg, 0);
23617 /* If the base register we are using to address memory is
23618 also a destination reg, then change that register last. */
23620 && REGNO (breg) >= REGNO (dst)
23621 && REGNO (breg) < REGNO (dst) + nregs)
23622 j = REGNO (breg) - REGNO (dst);
23624 else if (MEM_P (dst) && INT_REGNO_P (reg))
23628 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23629 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23632 breg = XEXP (XEXP (dst, 0), 0);
23633 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23634 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23635 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23637 /* We have to update the breg before doing the store.
23638 Use store with update, if available. */
23642 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23643 emit_insn (TARGET_32BIT
23644 ? (TARGET_POWERPC64
23645 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23646 : gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
23647 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23648 used_update = true;
23651 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23652 dst = replace_equiv_address (dst, breg);
23654 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23655 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23657 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23659 rtx basereg = XEXP (XEXP (dst, 0), 0);
23662 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23663 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23666 used_update = true;
23669 emit_insn (gen_rtx_SET (basereg,
23670 XEXP (XEXP (dst, 0), 1)));
23671 dst = replace_equiv_address (dst, basereg);
23675 rtx basereg = XEXP (XEXP (dst, 0), 0);
23676 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23677 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23679 && REG_P (offsetreg)
23680 && REGNO (basereg) != REGNO (offsetreg));
23681 if (REGNO (basereg) == 0)
23683 rtx tmp = offsetreg;
23684 offsetreg = basereg;
23687 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23688 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23689 dst = replace_equiv_address (dst, basereg);
23692 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23693 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23696 for (i = 0; i < nregs; i++)
23698 /* Calculate index to next subword. */
23703 /* If compiler already emitted move of first word by
23704 store with update, no need to do anything. */
23705 if (j == 0 && used_update)
23708 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23709 j * reg_mode_size),
23710 simplify_gen_subreg (reg_mode, src, mode,
23711 j * reg_mode_size)));
23713 if (restore_basereg != NULL_RTX)
23714 emit_insn (restore_basereg);
23719 /* This page contains routines that are used to determine what the
23720 function prologue and epilogue code will do and write them out. */
23722 /* Determine whether the REG is really used. */
23725 save_reg_p (int reg)
23727 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23729 /* When calling eh_return, we must return true for all the cases
23730 where conditional_register_usage marks the PIC offset reg
23731 call used or fixed. */
23732 if (crtl->calls_eh_return
23733 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23734 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23735 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23738 /* We need to mark the PIC offset register live for the same
23739 conditions as it is set up in rs6000_emit_prologue, or
23740 otherwise it won't be saved before we clobber it. */
23741 if (TARGET_TOC && TARGET_MINIMAL_TOC
23742 && !constant_pool_empty_p ())
23745 if (DEFAULT_ABI == ABI_V4
23746 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
23747 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
23750 if (DEFAULT_ABI == ABI_DARWIN
23751 && flag_pic && crtl->uses_pic_offset_table)
23755 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23758 /* Return the first fixed-point register that is required to be
23759 saved. 32 if none. */
23762 first_reg_to_save (void)
23766 /* Find lowest numbered live register. */
23767 for (first_reg = 13; first_reg <= 31; first_reg++)
23768 if (save_reg_p (first_reg))
23774 /* Similar, for FP regs. */
23777 first_fp_reg_to_save (void)
23781 /* Find lowest numbered live register. */
23782 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23783 if (save_reg_p (first_reg))
23789 /* Similar, for AltiVec regs. */
23792 first_altivec_reg_to_save (void)
23796 /* Stack frame remains as is unless we are in AltiVec ABI. */
23797 if (! TARGET_ALTIVEC_ABI)
23798 return LAST_ALTIVEC_REGNO + 1;
23800 /* On Darwin, the unwind routines are compiled without
23801 TARGET_ALTIVEC, and use save_world to save/restore the
23802 altivec registers when necessary. */
23803 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23804 && ! TARGET_ALTIVEC)
23805 return FIRST_ALTIVEC_REGNO + 20;
23807 /* Find lowest numbered live register. */
23808 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23809 if (save_reg_p (i))
23815 /* Return a 32-bit mask of the AltiVec registers we need to set in
23816 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23817 the 32-bit word is 0. */
23819 static unsigned int
23820 compute_vrsave_mask (void)
23822 unsigned int i, mask = 0;
23824 /* On Darwin, the unwind routines are compiled without
23825 TARGET_ALTIVEC, and use save_world to save/restore the
23826 call-saved altivec registers when necessary. */
23827 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23828 && ! TARGET_ALTIVEC)
23831 /* First, find out if we use _any_ altivec registers. */
23832 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23833 if (df_regs_ever_live_p (i))
23834 mask |= ALTIVEC_REG_BIT (i);
23839 /* Next, remove the argument registers from the set. These must
23840 be in the VRSAVE mask set by the caller, so we don't need to add
23841 them in again. More importantly, the mask we compute here is
23842 used to generate CLOBBERs in the set_vrsave insn, and we do not
23843 wish the argument registers to die. */
23844 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23845 mask &= ~ALTIVEC_REG_BIT (i);
23847 /* Similarly, remove the return value from the set. */
23850 diddle_return_value (is_altivec_return_reg, &yes);
23852 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23858 /* For a very restricted set of circumstances, we can cut down the
23859 size of prologues/epilogues by calling our own save/restore-the-world
23863 compute_save_world_info (rs6000_stack_t *info)
23865 info->world_save_p = 1;
23867 = (WORLD_SAVE_P (info)
23868 && DEFAULT_ABI == ABI_DARWIN
23869 && !cfun->has_nonlocal_label
23870 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23871 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23872 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23873 && info->cr_save_p);
23875 /* This will not work in conjunction with sibcalls. Make sure there
23876 are none. (This check is expensive, but seldom executed.) */
23877 if (WORLD_SAVE_P (info))
23880 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23881 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23883 info->world_save_p = 0;
23888 if (WORLD_SAVE_P (info))
23890 /* Even if we're not touching VRsave, make sure there's room on the
23891 stack for it, if it looks like we're calling SAVE_WORLD, which
23892 will attempt to save it. */
23893 info->vrsave_size = 4;
23895 /* If we are going to save the world, we need to save the link register too. */
23896 info->lr_save_p = 1;
23898 /* "Save" the VRsave register too if we're saving the world. */
23899 if (info->vrsave_mask == 0)
23900 info->vrsave_mask = compute_vrsave_mask ();
23902 /* Because the Darwin register save/restore routines only handle
23903 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23905 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23906 && (info->first_altivec_reg_save
23907 >= FIRST_SAVED_ALTIVEC_REGNO));
23915 is_altivec_return_reg (rtx reg, void *xyes)
23917 bool *yes = (bool *) xyes;
23918 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23923 /* Return whether REG is a global user reg or has been specifed by
23924 -ffixed-REG. We should not restore these, and so cannot use
23925 lmw or out-of-line restore functions if there are any. We also
23926 can't save them (well, emit frame notes for them), because frame
23927 unwinding during exception handling will restore saved registers. */
23930 fixed_reg_p (int reg)
23932 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23933 backend sets it, overriding anything the user might have given. */
23934 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23935 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23936 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23937 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23940 return fixed_regs[reg];
23943 /* Determine the strategy for savings/restoring registers. */
23946 SAVE_MULTIPLE = 0x1,
23947 SAVE_INLINE_GPRS = 0x2,
23948 SAVE_INLINE_FPRS = 0x4,
23949 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23950 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23951 SAVE_INLINE_VRS = 0x20,
23952 REST_MULTIPLE = 0x100,
23953 REST_INLINE_GPRS = 0x200,
23954 REST_INLINE_FPRS = 0x400,
23955 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23956 REST_INLINE_VRS = 0x1000
23960 rs6000_savres_strategy (rs6000_stack_t *info,
23961 bool using_static_chain_p)
23965 /* Select between in-line and out-of-line save and restore of regs.
23966 First, all the obvious cases where we don't use out-of-line. */
23967 if (crtl->calls_eh_return
23968 || cfun->machine->ra_need_lr)
23969 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23970 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23971 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23973 if (info->first_gp_reg_save == 32)
23974 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23976 if (info->first_fp_reg_save == 64)
23977 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23979 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23980 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23982 /* Define cutoff for using out-of-line functions to save registers. */
23983 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23985 if (!optimize_size)
23987 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23988 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23989 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23993 /* Prefer out-of-line restore if it will exit. */
23994 if (info->first_fp_reg_save > 61)
23995 strategy |= SAVE_INLINE_FPRS;
23996 if (info->first_gp_reg_save > 29)
23998 if (info->first_fp_reg_save == 64)
23999 strategy |= SAVE_INLINE_GPRS;
24001 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24003 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24004 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24007 else if (DEFAULT_ABI == ABI_DARWIN)
24009 if (info->first_fp_reg_save > 60)
24010 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24011 if (info->first_gp_reg_save > 29)
24012 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24013 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24017 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24018 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24019 || info->first_fp_reg_save > 61)
24020 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24021 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24022 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24025 /* Don't bother to try to save things out-of-line if r11 is occupied
24026 by the static chain. It would require too much fiddling and the
24027 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24028 pointer on Darwin, and AIX uses r1 or r12. */
24029 if (using_static_chain_p
24030 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24031 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24033 | SAVE_INLINE_VRS);
24035 /* Don't ever restore fixed regs. That means we can't use the
24036 out-of-line register restore functions if a fixed reg is in the
24037 range of regs restored. */
24038 if (!(strategy & REST_INLINE_FPRS))
24039 for (int i = info->first_fp_reg_save; i < 64; i++)
24042 strategy |= REST_INLINE_FPRS;
24046 /* We can only use the out-of-line routines to restore fprs if we've
24047 saved all the registers from first_fp_reg_save in the prologue.
24048 Otherwise, we risk loading garbage. Of course, if we have saved
24049 out-of-line then we know we haven't skipped any fprs. */
24050 if ((strategy & SAVE_INLINE_FPRS)
24051 && !(strategy & REST_INLINE_FPRS))
24052 for (int i = info->first_fp_reg_save; i < 64; i++)
24053 if (!save_reg_p (i))
24055 strategy |= REST_INLINE_FPRS;
24059 /* Similarly, for altivec regs. */
24060 if (!(strategy & REST_INLINE_VRS))
24061 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24064 strategy |= REST_INLINE_VRS;
24068 if ((strategy & SAVE_INLINE_VRS)
24069 && !(strategy & REST_INLINE_VRS))
24070 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24071 if (!save_reg_p (i))
24073 strategy |= REST_INLINE_VRS;
24077 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24078 saved is an out-of-line save or restore. Set up the value for
24079 the next test (excluding out-of-line gprs). */
24080 bool lr_save_p = (info->lr_save_p
24081 || !(strategy & SAVE_INLINE_FPRS)
24082 || !(strategy & SAVE_INLINE_VRS)
24083 || !(strategy & REST_INLINE_FPRS)
24084 || !(strategy & REST_INLINE_VRS));
24086 if (TARGET_MULTIPLE
24087 && !TARGET_POWERPC64
24088 && info->first_gp_reg_save < 31
24089 && !(flag_shrink_wrap
24090 && flag_shrink_wrap_separate
24091 && optimize_function_for_speed_p (cfun)))
24094 for (int i = info->first_gp_reg_save; i < 32; i++)
24095 if (save_reg_p (i))
24099 /* Don't use store multiple if only one reg needs to be
24100 saved. This can occur for example when the ABI_V4 pic reg
24101 (r30) needs to be saved to make calls, but r31 is not
24103 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24106 /* Prefer store multiple for saves over out-of-line
24107 routines, since the store-multiple instruction will
24108 always be smaller. */
24109 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24111 /* The situation is more complicated with load multiple.
24112 We'd prefer to use the out-of-line routines for restores,
24113 since the "exit" out-of-line routines can handle the
24114 restore of LR and the frame teardown. However if doesn't
24115 make sense to use the out-of-line routine if that is the
24116 only reason we'd need to save LR, and we can't use the
24117 "exit" out-of-line gpr restore if we have saved some
24118 fprs; In those cases it is advantageous to use load
24119 multiple when available. */
24120 if (info->first_fp_reg_save != 64 || !lr_save_p)
24121 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24125 /* Using the "exit" out-of-line routine does not improve code size
24126 if using it would require lr to be saved and if only saving one
24128 else if (!lr_save_p && info->first_gp_reg_save > 29)
24129 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24131 /* Don't ever restore fixed regs. */
24132 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24133 for (int i = info->first_gp_reg_save; i < 32; i++)
24134 if (fixed_reg_p (i))
24136 strategy |= REST_INLINE_GPRS;
24137 strategy &= ~REST_MULTIPLE;
24141 /* We can only use load multiple or the out-of-line routines to
24142 restore gprs if we've saved all the registers from
24143 first_gp_reg_save. Otherwise, we risk loading garbage.
24144 Of course, if we have saved out-of-line or used stmw then we know
24145 we haven't skipped any gprs. */
24146 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24147 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24148 for (int i = info->first_gp_reg_save; i < 32; i++)
24149 if (!save_reg_p (i))
24151 strategy |= REST_INLINE_GPRS;
24152 strategy &= ~REST_MULTIPLE;
24156 if (TARGET_ELF && TARGET_64BIT)
24158 if (!(strategy & SAVE_INLINE_FPRS))
24159 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24160 else if (!(strategy & SAVE_INLINE_GPRS)
24161 && info->first_fp_reg_save == 64)
24162 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24164 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24165 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24167 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24168 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24173 /* Calculate the stack information for the current function. This is
24174 complicated by having two separate calling sequences, the AIX calling
24175 sequence and the V.4 calling sequence.
24177 AIX (and Darwin/Mac OS X) stack frames look like:
24179 SP----> +---------------------------------------+
24180 | back chain to caller | 0 0
24181 +---------------------------------------+
24182 | saved CR | 4 8 (8-11)
24183 +---------------------------------------+
24185 +---------------------------------------+
24186 | reserved for compilers | 12 24
24187 +---------------------------------------+
24188 | reserved for binders | 16 32
24189 +---------------------------------------+
24190 | saved TOC pointer | 20 40
24191 +---------------------------------------+
24192 | Parameter save area (+padding*) (P) | 24 48
24193 +---------------------------------------+
24194 | Alloca space (A) | 24+P etc.
24195 +---------------------------------------+
24196 | Local variable space (L) | 24+P+A
24197 +---------------------------------------+
24198 | Float/int conversion temporary (X) | 24+P+A+L
24199 +---------------------------------------+
24200 | Save area for AltiVec registers (W) | 24+P+A+L+X
24201 +---------------------------------------+
24202 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24203 +---------------------------------------+
24204 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24205 +---------------------------------------+
24206 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24207 +---------------------------------------+
24208 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24209 +---------------------------------------+
24210 old SP->| back chain to caller's caller |
24211 +---------------------------------------+
24213 * If the alloca area is present, the parameter save area is
24214 padded so that the former starts 16-byte aligned.
24216 The required alignment for AIX configurations is two words (i.e., 8
24219 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24221 SP----> +---------------------------------------+
24222 | Back chain to caller | 0
24223 +---------------------------------------+
24224 | Save area for CR | 8
24225 +---------------------------------------+
24227 +---------------------------------------+
24228 | Saved TOC pointer | 24
24229 +---------------------------------------+
24230 | Parameter save area (+padding*) (P) | 32
24231 +---------------------------------------+
24232 | Alloca space (A) | 32+P
24233 +---------------------------------------+
24234 | Local variable space (L) | 32+P+A
24235 +---------------------------------------+
24236 | Save area for AltiVec registers (W) | 32+P+A+L
24237 +---------------------------------------+
24238 | AltiVec alignment padding (Y) | 32+P+A+L+W
24239 +---------------------------------------+
24240 | Save area for GP registers (G) | 32+P+A+L+W+Y
24241 +---------------------------------------+
24242 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24243 +---------------------------------------+
24244 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24245 +---------------------------------------+
24247 * If the alloca area is present, the parameter save area is
24248 padded so that the former starts 16-byte aligned.
24250 V.4 stack frames look like:
24252 SP----> +---------------------------------------+
24253 | back chain to caller | 0
24254 +---------------------------------------+
24255 | caller's saved LR | 4
24256 +---------------------------------------+
24257 | Parameter save area (+padding*) (P) | 8
24258 +---------------------------------------+
24259 | Alloca space (A) | 8+P
24260 +---------------------------------------+
24261 | Varargs save area (V) | 8+P+A
24262 +---------------------------------------+
24263 | Local variable space (L) | 8+P+A+V
24264 +---------------------------------------+
24265 | Float/int conversion temporary (X) | 8+P+A+V+L
24266 +---------------------------------------+
24267 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24268 +---------------------------------------+
24269 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24270 +---------------------------------------+
24271 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24272 +---------------------------------------+
24273 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24274 +---------------------------------------+
24275 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24276 +---------------------------------------+
24277 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24278 +---------------------------------------+
24279 old SP->| back chain to caller's caller |
24280 +---------------------------------------+
24282 * If the alloca area is present and the required alignment is
24283 16 bytes, the parameter save area is padded so that the
24284 alloca area starts 16-byte aligned.
24286 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24287 given. (But note below and in sysv4.h that we require only 8 and
24288 may round up the size of our stack frame anyways. The historical
24289 reason is early versions of powerpc-linux which didn't properly
24290 align the stack at program startup. A happy side-effect is that
24291 -mno-eabi libraries can be used with -meabi programs.)
24293 The EABI configuration defaults to the V.4 layout. However,
24294 the stack alignment requirements may differ. If -mno-eabi is not
24295 given, the required stack alignment is 8 bytes; if -mno-eabi is
24296 given, the required alignment is 16 bytes. (But see V.4 comment
24299 #ifndef ABI_STACK_BOUNDARY
24300 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24303 static rs6000_stack_t *
24304 rs6000_stack_info (void)
24306 /* We should never be called for thunks, we are not set up for that. */
24307 gcc_assert (!cfun->is_thunk);
24309 rs6000_stack_t *info = &stack_info;
24310 int reg_size = TARGET_32BIT ? 4 : 8;
24315 HOST_WIDE_INT non_fixed_size;
24316 bool using_static_chain_p;
24318 if (reload_completed && info->reload_completed)
24321 memset (info, 0, sizeof (*info));
24322 info->reload_completed = reload_completed;
24324 /* Select which calling sequence. */
24325 info->abi = DEFAULT_ABI;
24327 /* Calculate which registers need to be saved & save area size. */
24328 info->first_gp_reg_save = first_reg_to_save ();
24329 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24330 even if it currently looks like we won't. Reload may need it to
24331 get at a constant; if so, it will have already created a constant
24332 pool entry for it. */
24333 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24334 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24335 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24336 && crtl->uses_const_pool
24337 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24338 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24340 first_gp = info->first_gp_reg_save;
24342 info->gp_size = reg_size * (32 - first_gp);
24344 info->first_fp_reg_save = first_fp_reg_to_save ();
24345 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24347 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24348 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24349 - info->first_altivec_reg_save);
24351 /* Does this function call anything? */
24352 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24354 /* Determine if we need to save the condition code registers. */
24355 if (save_reg_p (CR2_REGNO)
24356 || save_reg_p (CR3_REGNO)
24357 || save_reg_p (CR4_REGNO))
24359 info->cr_save_p = 1;
24360 if (DEFAULT_ABI == ABI_V4)
24361 info->cr_size = reg_size;
24364 /* If the current function calls __builtin_eh_return, then we need
24365 to allocate stack space for registers that will hold data for
24366 the exception handler. */
24367 if (crtl->calls_eh_return)
24370 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24373 ehrd_size = i * UNITS_PER_WORD;
24378 /* In the ELFv2 ABI, we also need to allocate space for separate
24379 CR field save areas if the function calls __builtin_eh_return. */
24380 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24382 /* This hard-codes that we have three call-saved CR fields. */
24383 ehcr_size = 3 * reg_size;
24384 /* We do *not* use the regular CR save mechanism. */
24385 info->cr_save_p = 0;
24390 /* Determine various sizes. */
24391 info->reg_size = reg_size;
24392 info->fixed_size = RS6000_SAVE_AREA;
24393 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24394 if (cfun->calls_alloca)
24396 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24397 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24399 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24400 TARGET_ALTIVEC ? 16 : 8);
24401 if (FRAME_GROWS_DOWNWARD)
24403 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24404 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24405 - (info->fixed_size + info->vars_size + info->parm_size);
24407 if (TARGET_ALTIVEC_ABI)
24408 info->vrsave_mask = compute_vrsave_mask ();
24410 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24411 info->vrsave_size = 4;
24413 compute_save_world_info (info);
24415 /* Calculate the offsets. */
24416 switch (DEFAULT_ABI)
24420 gcc_unreachable ();
24425 info->fp_save_offset = -info->fp_size;
24426 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24428 if (TARGET_ALTIVEC_ABI)
24430 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24432 /* Align stack so vector save area is on a quadword boundary.
24433 The padding goes above the vectors. */
24434 if (info->altivec_size != 0)
24435 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24437 info->altivec_save_offset = info->vrsave_save_offset
24438 - info->altivec_padding_size
24439 - info->altivec_size;
24440 gcc_assert (info->altivec_size == 0
24441 || info->altivec_save_offset % 16 == 0);
24443 /* Adjust for AltiVec case. */
24444 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24447 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24449 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24450 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24451 info->lr_save_offset = 2*reg_size;
24455 info->fp_save_offset = -info->fp_size;
24456 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24457 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24459 if (TARGET_ALTIVEC_ABI)
24461 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24463 /* Align stack so vector save area is on a quadword boundary. */
24464 if (info->altivec_size != 0)
24465 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24467 info->altivec_save_offset = info->vrsave_save_offset
24468 - info->altivec_padding_size
24469 - info->altivec_size;
24471 /* Adjust for AltiVec case. */
24472 info->ehrd_offset = info->altivec_save_offset;
24475 info->ehrd_offset = info->cr_save_offset;
24477 info->ehrd_offset -= ehrd_size;
24478 info->lr_save_offset = reg_size;
24481 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24482 info->save_size = RS6000_ALIGN (info->fp_size
24484 + info->altivec_size
24485 + info->altivec_padding_size
24489 + info->vrsave_size,
24492 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24494 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24495 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24497 /* Determine if we need to save the link register. */
24499 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24501 && !TARGET_PROFILE_KERNEL)
24502 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24503 #ifdef TARGET_RELOCATABLE
24504 || (DEFAULT_ABI == ABI_V4
24505 && (TARGET_RELOCATABLE || flag_pic > 1)
24506 && !constant_pool_empty_p ())
24508 || rs6000_ra_ever_killed ())
24509 info->lr_save_p = 1;
24511 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24512 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24513 && call_used_regs[STATIC_CHAIN_REGNUM]);
24514 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24516 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24517 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24518 || !(info->savres_strategy & SAVE_INLINE_VRS)
24519 || !(info->savres_strategy & REST_INLINE_GPRS)
24520 || !(info->savres_strategy & REST_INLINE_FPRS)
24521 || !(info->savres_strategy & REST_INLINE_VRS))
24522 info->lr_save_p = 1;
24524 if (info->lr_save_p)
24525 df_set_regs_ever_live (LR_REGNO, true);
24527 /* Determine if we need to allocate any stack frame:
24529 For AIX we need to push the stack if a frame pointer is needed
24530 (because the stack might be dynamically adjusted), if we are
24531 debugging, if we make calls, or if the sum of fp_save, gp_save,
24532 and local variables are more than the space needed to save all
24533 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24534 + 18*8 = 288 (GPR13 reserved).
24536 For V.4 we don't have the stack cushion that AIX uses, but assume
24537 that the debugger can handle stackless frames. */
24542 else if (DEFAULT_ABI == ABI_V4)
24543 info->push_p = non_fixed_size != 0;
24545 else if (frame_pointer_needed)
24548 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24552 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24558 debug_stack_info (rs6000_stack_t *info)
24560 const char *abi_string;
24563 info = rs6000_stack_info ();
24565 fprintf (stderr, "\nStack information for function %s:\n",
24566 ((current_function_decl && DECL_NAME (current_function_decl))
24567 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24572 default: abi_string = "Unknown"; break;
24573 case ABI_NONE: abi_string = "NONE"; break;
24574 case ABI_AIX: abi_string = "AIX"; break;
24575 case ABI_ELFv2: abi_string = "ELFv2"; break;
24576 case ABI_DARWIN: abi_string = "Darwin"; break;
24577 case ABI_V4: abi_string = "V.4"; break;
24580 fprintf (stderr, "\tABI = %5s\n", abi_string);
24582 if (TARGET_ALTIVEC_ABI)
24583 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24585 if (info->first_gp_reg_save != 32)
24586 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24588 if (info->first_fp_reg_save != 64)
24589 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24591 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24592 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24593 info->first_altivec_reg_save);
24595 if (info->lr_save_p)
24596 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24598 if (info->cr_save_p)
24599 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24601 if (info->vrsave_mask)
24602 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24605 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24608 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24611 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24614 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24616 if (info->altivec_size)
24617 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24618 info->altivec_save_offset);
24620 if (info->vrsave_size)
24621 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24622 info->vrsave_save_offset);
24624 if (info->lr_save_p)
24625 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24627 if (info->cr_save_p)
24628 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24630 if (info->varargs_save_offset)
24631 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24633 if (info->total_size)
24634 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24637 if (info->vars_size)
24638 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24641 if (info->parm_size)
24642 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24644 if (info->fixed_size)
24645 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24648 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24651 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24653 if (info->altivec_size)
24654 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24656 if (info->vrsave_size)
24657 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24659 if (info->altivec_padding_size)
24660 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24661 info->altivec_padding_size);
24664 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24666 if (info->save_size)
24667 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24669 if (info->reg_size != 4)
24670 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24672 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24674 if (info->abi == ABI_DARWIN)
24675 fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
24677 fprintf (stderr, "\n");
24681 rs6000_return_addr (int count, rtx frame)
24683 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24684 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24686 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24688 cfun->machine->ra_needs_full_frame = 1;
24691 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24692 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24693 frame = stack_pointer_rtx;
24694 rtx prev_frame_addr = memory_address (Pmode, frame);
24695 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24696 rtx lr_save_off = plus_constant (Pmode,
24697 prev_frame, RETURN_ADDRESS_OFFSET);
24698 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24699 return gen_rtx_MEM (Pmode, lr_save_addr);
24702 cfun->machine->ra_need_lr = 1;
24703 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24706 /* Say whether a function is a candidate for sibcall handling or not. */
24709 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24713 /* The sibcall epilogue may clobber the static chain register.
24714 ??? We could work harder and avoid that, but it's probably
24715 not worth the hassle in practice. */
24716 if (CALL_EXPR_STATIC_CHAIN (exp))
24720 fntype = TREE_TYPE (decl);
24722 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24724 /* We can't do it if the called function has more vector parameters
24725 than the current function; there's nowhere to put the VRsave code. */
24726 if (TARGET_ALTIVEC_ABI
24727 && TARGET_ALTIVEC_VRSAVE
24728 && !(decl && decl == current_function_decl))
24730 function_args_iterator args_iter;
24734 /* Functions with vector parameters are required to have a
24735 prototype, so the argument type info must be available
24737 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24738 if (TREE_CODE (type) == VECTOR_TYPE
24739 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24742 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24743 if (TREE_CODE (type) == VECTOR_TYPE
24744 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24751 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24752 functions, because the callee may have a different TOC pointer to
24753 the caller and there's no way to ensure we restore the TOC when
24754 we return. With the secure-plt SYSV ABI we can't make non-local
24755 calls when -fpic/PIC because the plt call stubs use r30. */
24756 if (DEFAULT_ABI == ABI_DARWIN
24757 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24759 && !DECL_EXTERNAL (decl)
24760 && !DECL_WEAK (decl)
24761 && (*targetm.binds_local_p) (decl))
24762 || (DEFAULT_ABI == ABI_V4
24763 && (!TARGET_SECURE_PLT
24766 && (*targetm.binds_local_p) (decl)))))
24768 tree attr_list = TYPE_ATTRIBUTES (fntype);
24770 if (!lookup_attribute ("longcall", attr_list)
24771 || lookup_attribute ("shortcall", attr_list))
24779 rs6000_ra_ever_killed (void)
24785 if (cfun->is_thunk)
24788 if (cfun->machine->lr_save_state)
24789 return cfun->machine->lr_save_state - 1;
24791 /* regs_ever_live has LR marked as used if any sibcalls are present,
24792 but this should not force saving and restoring in the
24793 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24794 clobbers LR, so that is inappropriate. */
24796 /* Also, the prologue can generate a store into LR that
24797 doesn't really count, like this:
24800 bcl to set PIC register
24804 When we're called from the epilogue, we need to avoid counting
24805 this as a store. */
24807 push_topmost_sequence ();
24808 top = get_insns ();
24809 pop_topmost_sequence ();
24810 reg = gen_rtx_REG (Pmode, LR_REGNO);
24812 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24818 if (!SIBLING_CALL_P (insn))
24821 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24823 else if (set_of (reg, insn) != NULL_RTX
24824 && !prologue_epilogue_contains (insn))
24831 /* Emit instructions needed to load the TOC register.
24832 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24833 a constant pool; or for SVR4 -fpic. */
24836 rs6000_emit_load_toc_table (int fromprolog)
24839 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24841 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24844 rtx lab, tmp1, tmp2, got;
24846 lab = gen_label_rtx ();
24847 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24848 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24851 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24855 got = rs6000_got_sym ();
24856 tmp1 = tmp2 = dest;
24859 tmp1 = gen_reg_rtx (Pmode);
24860 tmp2 = gen_reg_rtx (Pmode);
24862 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24863 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24864 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24865 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24867 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24869 emit_insn (gen_load_toc_v4_pic_si ());
24870 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24872 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24875 rtx temp0 = (fromprolog
24876 ? gen_rtx_REG (Pmode, 0)
24877 : gen_reg_rtx (Pmode));
24883 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24884 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24886 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24887 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24889 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24890 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24891 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24897 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24899 lab = gen_label_rtx ();
24900 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24901 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24902 if (TARGET_LINK_STACK)
24903 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24904 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24906 emit_insn (gen_addsi3 (dest, temp0, dest));
24908 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24910 /* This is for AIX code running in non-PIC ELF32. */
24911 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24914 emit_insn (gen_elf_high (dest, realsym));
24915 emit_insn (gen_elf_low (dest, dest, realsym));
24919 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24922 emit_insn (gen_load_toc_aix_si (dest));
24924 emit_insn (gen_load_toc_aix_di (dest));
24928 /* Emit instructions to restore the link register after determining where
24929 its value has been stored. */
24932 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24934 rs6000_stack_t *info = rs6000_stack_info ();
24937 operands[0] = source;
24938 operands[1] = scratch;
24940 if (info->lr_save_p)
24942 rtx frame_rtx = stack_pointer_rtx;
24943 HOST_WIDE_INT sp_offset = 0;
24946 if (frame_pointer_needed
24947 || cfun->calls_alloca
24948 || info->total_size > 32767)
24950 tmp = gen_frame_mem (Pmode, frame_rtx);
24951 emit_move_insn (operands[1], tmp);
24952 frame_rtx = operands[1];
24954 else if (info->push_p)
24955 sp_offset = info->total_size;
24957 tmp = plus_constant (Pmode, frame_rtx,
24958 info->lr_save_offset + sp_offset);
24959 tmp = gen_frame_mem (Pmode, tmp);
24960 emit_move_insn (tmp, operands[0]);
24963 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24965 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24966 state of lr_save_p so any change from here on would be a bug. In
24967 particular, stop rs6000_ra_ever_killed from considering the SET
24968 of lr we may have added just above. */
24969 cfun->machine->lr_save_state = info->lr_save_p + 1;
24972 static GTY(()) alias_set_type set = -1;
24975 get_TOC_alias_set (void)
24978 set = new_alias_set ();
24982 /* This returns nonzero if the current function uses the TOC. This is
24983 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24984 is generated by the ABI_V4 load_toc_* patterns.
24985 Return 2 instead of 1 if the load_toc_* pattern is in the function
24986 partition that doesn't start the function. */
24994 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24998 rtx pat = PATTERN (insn);
25001 if (GET_CODE (pat) == PARALLEL)
25002 for (i = 0; i < XVECLEN (pat, 0); i++)
25004 rtx sub = XVECEXP (pat, 0, i);
25005 if (GET_CODE (sub) == USE)
25007 sub = XEXP (sub, 0);
25008 if (GET_CODE (sub) == UNSPEC
25009 && XINT (sub, 1) == UNSPEC_TOC)
25014 else if (crtl->has_bb_partition
25016 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25024 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25026 rtx tocrel, tocreg, hi;
25028 if (TARGET_DEBUG_ADDR)
25030 if (SYMBOL_REF_P (symbol))
25031 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25035 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25036 GET_RTX_NAME (GET_CODE (symbol)));
25037 debug_rtx (symbol);
25041 if (!can_create_pseudo_p ())
25042 df_set_regs_ever_live (TOC_REGISTER, true);
25044 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25045 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25046 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25049 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25050 if (largetoc_reg != NULL)
25052 emit_move_insn (largetoc_reg, hi);
25055 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25058 /* Issue assembly directives that create a reference to the given DWARF
25059 FRAME_TABLE_LABEL from the current function section. */
25061 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25063 fprintf (asm_out_file, "\t.ref %s\n",
25064 (* targetm.strip_name_encoding) (frame_table_label));
25067 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25068 and the change to the stack pointer. */
25071 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25078 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25079 if (hard_frame_needed)
25080 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25081 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25082 || (hard_frame_needed
25083 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25086 p = rtvec_alloc (i);
25089 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25090 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25093 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25096 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25097 and set the appropriate attributes for the generated insn. Return the
25098 first insn which adjusts the stack pointer or the last insn before
25099 the stack adjustment loop.
25101 SIZE_INT is used to create the CFI note for the allocation.
25103 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25104 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25106 ORIG_SP contains the backchain value that must be stored at *sp. */
25109 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25113 rtx size_rtx = GEN_INT (-size_int);
25114 if (size_int > 32767)
25116 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25117 /* Need a note here so that try_split doesn't get confused. */
25118 if (get_last_insn () == NULL_RTX)
25119 emit_note (NOTE_INSN_DELETED);
25120 insn = emit_move_insn (tmp_reg, size_rtx);
25121 try_split (PATTERN (insn), insn, 0);
25122 size_rtx = tmp_reg;
25126 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25131 insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
25135 rtx par = PATTERN (insn);
25136 gcc_assert (GET_CODE (par) == PARALLEL);
25137 rtx set = XVECEXP (par, 0, 0);
25138 gcc_assert (GET_CODE (set) == SET);
25139 rtx mem = SET_DEST (set);
25140 gcc_assert (MEM_P (mem));
25141 MEM_NOTRAP_P (mem) = 1;
25142 set_mem_alias_set (mem, get_frame_alias_set ());
25144 RTX_FRAME_RELATED_P (insn) = 1;
25145 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25146 gen_rtx_SET (stack_pointer_rtx,
25147 gen_rtx_PLUS (Pmode,
25149 GEN_INT (-size_int))));
25151 /* Emit a blockage to ensure the allocation/probing insns are
25152 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25153 note for similar reasons. */
25154 if (flag_stack_clash_protection)
25156 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25157 emit_insn (gen_blockage ());
25163 static HOST_WIDE_INT
25164 get_stack_clash_protection_probe_interval (void)
25166 return (HOST_WIDE_INT_1U
25167 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25170 static HOST_WIDE_INT
25171 get_stack_clash_protection_guard_size (void)
25173 return (HOST_WIDE_INT_1U
25174 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25177 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25178 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25180 COPY_REG, if non-null, should contain a copy of the original
25181 stack pointer at exit from this function.
25183 This is subtly different than the Ada probing in that it tries hard to
25184 prevent attacks that jump the stack guard. Thus it is never allowed to
25185 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25186 space without a suitable probe. */
25188 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25191 rtx orig_sp = copy_reg;
25193 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25195 /* Round the size down to a multiple of PROBE_INTERVAL. */
25196 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25198 /* If explicitly requested,
25199 or the rounded size is not the same as the original size
25200 or the the rounded size is greater than a page,
25201 then we will need a copy of the original stack pointer. */
25202 if (rounded_size != orig_size
25203 || rounded_size > probe_interval
25206 /* If the caller did not request a copy of the incoming stack
25207 pointer, then we use r0 to hold the copy. */
25209 orig_sp = gen_rtx_REG (Pmode, 0);
25210 emit_move_insn (orig_sp, stack_pointer_rtx);
25213 /* There's three cases here.
25215 One is a single probe which is the most common and most efficiently
25216 implemented as it does not have to have a copy of the original
25217 stack pointer if there are no residuals.
25219 Second is unrolled allocation/probes which we use if there's just
25220 a few of them. It needs to save the original stack pointer into a
25221 temporary for use as a source register in the allocation/probe.
25223 Last is a loop. This is the most uncommon case and least efficient. */
25224 rtx_insn *retval = NULL;
25225 if (rounded_size == probe_interval)
25227 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25229 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25231 else if (rounded_size <= 8 * probe_interval)
25233 /* The ABI requires using the store with update insns to allocate
25234 space and store the backchain into the stack
25236 So we save the current stack pointer into a temporary, then
25237 emit the store-with-update insns to store the saved stack pointer
25238 into the right location in each new page. */
25239 for (int i = 0; i < rounded_size; i += probe_interval)
25242 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25244 /* Save the first stack adjustment in RETVAL. */
25249 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25253 /* Compute the ending address. */
25255 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25256 rtx rs = GEN_INT (-rounded_size);
25258 if (add_operand (rs, Pmode))
25259 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25262 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25263 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25264 stack_pointer_rtx));
25265 /* Describe the effect of INSN to the CFI engine. */
25266 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25267 gen_rtx_SET (end_addr,
25268 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25271 RTX_FRAME_RELATED_P (insn) = 1;
25273 /* Emit the loop. */
25275 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25276 stack_pointer_rtx, orig_sp,
25279 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25280 stack_pointer_rtx, orig_sp,
25282 RTX_FRAME_RELATED_P (retval) = 1;
25283 /* Describe the effect of INSN to the CFI engine. */
25284 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25285 gen_rtx_SET (stack_pointer_rtx, end_addr));
25287 /* Emit a blockage to ensure the allocation/probing insns are
25288 not optimized, combined, removed, etc. Other cases handle this
25289 within their call to rs6000_emit_allocate_stack_1. */
25290 emit_insn (gen_blockage ());
25292 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25295 if (orig_size != rounded_size)
25297 /* Allocate (and implicitly probe) any residual space. */
25298 HOST_WIDE_INT residual = orig_size - rounded_size;
25300 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25302 /* If the residual was the only allocation, then we can return the
25303 allocating insn. */
25311 /* Emit the correct code for allocating stack space, as insns.
25312 If COPY_REG, make sure a copy of the old frame is left there.
25313 The generated code may use hard register 0 as a temporary. */
25316 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25319 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25320 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25321 rtx todec = gen_int_mode (-size, Pmode);
25323 if (INTVAL (todec) != -size)
25325 warning (0, "stack frame too large");
25326 emit_insn (gen_trap ());
25330 if (crtl->limit_stack)
25332 if (REG_P (stack_limit_rtx)
25333 && REGNO (stack_limit_rtx) > 1
25334 && REGNO (stack_limit_rtx) <= 31)
25337 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25340 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25342 else if (SYMBOL_REF_P (stack_limit_rtx)
25344 && DEFAULT_ABI == ABI_V4
25347 rtx toload = gen_rtx_CONST (VOIDmode,
25348 gen_rtx_PLUS (Pmode,
25352 emit_insn (gen_elf_high (tmp_reg, toload));
25353 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25354 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25358 warning (0, "stack limit expression is not supported");
25361 if (flag_stack_clash_protection)
25363 if (size < get_stack_clash_protection_guard_size ())
25364 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25367 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25370 /* If we asked for a copy with an offset, then we still need add in
25372 if (copy_reg && copy_off)
25373 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25381 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25383 emit_move_insn (copy_reg, stack_reg);
25386 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25387 it now and set the alias set/attributes. The above gen_*_update
25388 calls will generate a PARALLEL with the MEM set being the first
25390 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25394 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25396 #if PROBE_INTERVAL > 32768
25397 #error Cannot use indexed addressing mode for stack probing
25400 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25401 inclusive. These are offsets from the current stack pointer. */
25404 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25406 /* See if we have a constant small number of probes to generate. If so,
25407 that's the easy case. */
25408 if (first + size <= 32768)
25412 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25413 it exceeds SIZE. If only one probe is needed, this will not
25414 generate any code. Then probe at FIRST + SIZE. */
25415 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25416 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25419 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25423 /* Otherwise, do the same as above, but in a loop. Note that we must be
25424 extra careful with variables wrapping around because we might be at
25425 the very top (or the very bottom) of the address space and we have
25426 to be able to handle this case properly; in particular, we use an
25427 equality test for the loop condition. */
25430 HOST_WIDE_INT rounded_size;
25431 rtx r12 = gen_rtx_REG (Pmode, 12);
25432 rtx r0 = gen_rtx_REG (Pmode, 0);
25434 /* Sanity check for the addressing mode we're going to use. */
25435 gcc_assert (first <= 32768);
25437 /* Step 1: round SIZE to the previous multiple of the interval. */
25439 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25442 /* Step 2: compute initial and final value of the loop counter. */
25444 /* TEST_ADDR = SP + FIRST. */
25445 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25448 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25449 if (rounded_size > 32768)
25451 emit_move_insn (r0, GEN_INT (-rounded_size));
25452 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25455 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25459 /* Step 3: the loop
25463 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25466 while (TEST_ADDR != LAST_ADDR)
25468 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25469 until it is equal to ROUNDED_SIZE. */
25472 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25474 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25477 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25478 that SIZE is equal to ROUNDED_SIZE. */
25480 if (size != rounded_size)
25481 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25485 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25486 addresses, not offsets. */
25488 static const char *
25489 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25491 static int labelno = 0;
25495 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25498 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25500 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25502 xops[1] = GEN_INT (-PROBE_INTERVAL);
25503 output_asm_insn ("addi %0,%0,%1", xops);
25505 /* Probe at TEST_ADDR. */
25506 xops[1] = gen_rtx_REG (Pmode, 0);
25507 output_asm_insn ("stw %1,0(%0)", xops);
25509 /* Test if TEST_ADDR == LAST_ADDR. */
25512 output_asm_insn ("cmpd 0,%0,%1", xops);
25514 output_asm_insn ("cmpw 0,%0,%1", xops);
25517 fputs ("\tbne 0,", asm_out_file);
25518 assemble_name_raw (asm_out_file, loop_lab);
25519 fputc ('\n', asm_out_file);
25524 /* This function is called when rs6000_frame_related is processing
25525 SETs within a PARALLEL, and returns whether the REGNO save ought to
25526 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25527 for out-of-line register save functions, store multiple, and the
25528 Darwin world_save. They may contain registers that don't really
25532 interesting_frame_related_regno (unsigned int regno)
25534 /* Saves apparently of r0 are actually saving LR. It doesn't make
25535 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25536 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25537 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25538 as frame related. */
25541 /* If we see CR2 then we are here on a Darwin world save. Saves of
25542 CR2 signify the whole CR is being saved. This is a long-standing
25543 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25544 that CR needs to be saved. */
25545 if (regno == CR2_REGNO)
25547 /* Omit frame info for any user-defined global regs. If frame info
25548 is supplied for them, frame unwinding will restore a user reg.
25549 Also omit frame info for any reg we don't need to save, as that
25550 bloats frame info and can cause problems with shrink wrapping.
25551 Since global regs won't be seen as needing to be saved, both of
25552 these conditions are covered by save_reg_p. */
25553 return save_reg_p (regno);
25556 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25557 addresses, not offsets.
25559 REG2 contains the backchain that must be stored into *sp at each allocation.
25561 This is subtly different than the Ada probing above in that it tries hard
25562 to prevent attacks that jump the stack guard. Thus, it is never allowed
25563 to allocate more than PROBE_INTERVAL bytes of stack space without a
25566 static const char *
25567 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25569 static int labelno = 0;
25573 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25575 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25577 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25579 /* This allocates and probes. */
25582 xops[2] = GEN_INT (-probe_interval);
25584 output_asm_insn ("stdu %1,%2(%0)", xops);
25586 output_asm_insn ("stwu %1,%2(%0)", xops);
25588 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25592 output_asm_insn ("cmpd 0,%0,%1", xops);
25594 output_asm_insn ("cmpw 0,%0,%1", xops);
25596 fputs ("\tbne 0,", asm_out_file);
25597 assemble_name_raw (asm_out_file, loop_lab);
25598 fputc ('\n', asm_out_file);
25603 /* Wrapper around the output_probe_stack_range routines. */
25605 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25607 if (flag_stack_clash_protection)
25608 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25610 return output_probe_stack_range_1 (reg1, reg3);
25613 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25614 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25615 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25616 deduce these equivalences by itself so it wasn't necessary to hold
25617 its hand so much. Don't be tempted to always supply d2_f_d_e with
25618 the actual cfa register, ie. r31 when we are using a hard frame
25619 pointer. That fails when saving regs off r1, and sched moves the
25620 r31 setup past the reg saves. */
25623 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25624 rtx reg2, rtx repl2)
25628 if (REGNO (reg) == STACK_POINTER_REGNUM)
25630 gcc_checking_assert (val == 0);
25634 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25637 rtx pat = PATTERN (insn);
25638 if (!repl && !reg2)
25640 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25641 if (GET_CODE (pat) == PARALLEL)
25642 for (int i = 0; i < XVECLEN (pat, 0); i++)
25643 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25645 rtx set = XVECEXP (pat, 0, i);
25647 if (!REG_P (SET_SRC (set))
25648 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25649 RTX_FRAME_RELATED_P (set) = 1;
25651 RTX_FRAME_RELATED_P (insn) = 1;
25655 /* We expect that 'pat' is either a SET or a PARALLEL containing
25656 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25657 are important so they all have to be marked RTX_FRAME_RELATED_P.
25658 Call simplify_replace_rtx on the SETs rather than the whole insn
25659 so as to leave the other stuff alone (for example USE of r12). */
25661 set_used_flags (pat);
25662 if (GET_CODE (pat) == SET)
25665 pat = simplify_replace_rtx (pat, reg, repl);
25667 pat = simplify_replace_rtx (pat, reg2, repl2);
25669 else if (GET_CODE (pat) == PARALLEL)
25671 pat = shallow_copy_rtx (pat);
25672 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25674 for (int i = 0; i < XVECLEN (pat, 0); i++)
25675 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25677 rtx set = XVECEXP (pat, 0, i);
25680 set = simplify_replace_rtx (set, reg, repl);
25682 set = simplify_replace_rtx (set, reg2, repl2);
25683 XVECEXP (pat, 0, i) = set;
25685 if (!REG_P (SET_SRC (set))
25686 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25687 RTX_FRAME_RELATED_P (set) = 1;
25691 gcc_unreachable ();
25693 RTX_FRAME_RELATED_P (insn) = 1;
25694 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25699 /* Returns an insn that has a vrsave set operation with the
25700 appropriate CLOBBERs. */
25703 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25706 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25707 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25710 = gen_rtx_SET (vrsave,
25711 gen_rtx_UNSPEC_VOLATILE (SImode,
25712 gen_rtvec (2, reg, vrsave),
25713 UNSPECV_SET_VRSAVE));
25717 /* We need to clobber the registers in the mask so the scheduler
25718 does not move sets to VRSAVE before sets of AltiVec registers.
25720 However, if the function receives nonlocal gotos, reload will set
25721 all call saved registers live. We will end up with:
25723 (set (reg 999) (mem))
25724 (parallel [ (set (reg vrsave) (unspec blah))
25725 (clobber (reg 999))])
25727 The clobber will cause the store into reg 999 to be dead, and
25728 flow will attempt to delete an epilogue insn. In this case, we
25729 need an unspec use/set of the register. */
25731 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25732 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25734 if (!epiloguep || call_used_regs [i])
25735 clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
25738 rtx reg = gen_rtx_REG (V4SImode, i);
25741 = gen_rtx_SET (reg,
25742 gen_rtx_UNSPEC (V4SImode,
25743 gen_rtvec (1, reg), 27));
25747 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25749 for (i = 0; i < nclobs; ++i)
25750 XVECEXP (insn, 0, i) = clobs[i];
25756 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25760 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25761 mem = gen_frame_mem (GET_MODE (reg), addr);
25762 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25766 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25768 return gen_frame_set (reg, frame_reg, offset, false);
25772 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25774 return gen_frame_set (reg, frame_reg, offset, true);
25777 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25778 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25781 emit_frame_save (rtx frame_reg, machine_mode mode,
25782 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25786 /* Some cases that need register indexed addressing. */
25787 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25788 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25790 reg = gen_rtx_REG (mode, regno);
25791 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25792 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25793 NULL_RTX, NULL_RTX);
25796 /* Emit an offset memory reference suitable for a frame store, while
25797 converting to a valid addressing mode. */
25800 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25802 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25805 #ifndef TARGET_FIX_AND_CONTINUE
25806 #define TARGET_FIX_AND_CONTINUE 0
25809 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25810 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25811 #define LAST_SAVRES_REGISTER 31
25812 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25823 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25825 /* Temporary holding space for an out-of-line register save/restore
25827 static char savres_routine_name[30];
25829 /* Return the name for an out-of-line register save/restore routine.
25830 We are saving/restoring GPRs if GPR is true. */
25833 rs6000_savres_routine_name (int regno, int sel)
25835 const char *prefix = "";
25836 const char *suffix = "";
25838 /* Different targets are supposed to define
25839 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25840 routine name could be defined with:
25842 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25844 This is a nice idea in practice, but in reality, things are
25845 complicated in several ways:
25847 - ELF targets have save/restore routines for GPRs.
25849 - PPC64 ELF targets have routines for save/restore of GPRs that
25850 differ in what they do with the link register, so having a set
25851 prefix doesn't work. (We only use one of the save routines at
25852 the moment, though.)
25854 - PPC32 elf targets have "exit" versions of the restore routines
25855 that restore the link register and can save some extra space.
25856 These require an extra suffix. (There are also "tail" versions
25857 of the restore routines and "GOT" versions of the save routines,
25858 but we don't generate those at present. Same problems apply,
25861 We deal with all this by synthesizing our own prefix/suffix and
25862 using that for the simple sprintf call shown above. */
25863 if (DEFAULT_ABI == ABI_V4)
25868 if ((sel & SAVRES_REG) == SAVRES_GPR)
25869 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25870 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25871 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25872 else if ((sel & SAVRES_REG) == SAVRES_VR)
25873 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25877 if ((sel & SAVRES_LR))
25880 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25882 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25883 /* No out-of-line save/restore routines for GPRs on AIX. */
25884 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25888 if ((sel & SAVRES_REG) == SAVRES_GPR)
25889 prefix = ((sel & SAVRES_SAVE)
25890 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25891 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25892 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25894 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25895 if ((sel & SAVRES_LR))
25896 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25900 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25901 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25904 else if ((sel & SAVRES_REG) == SAVRES_VR)
25905 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25910 if (DEFAULT_ABI == ABI_DARWIN)
25912 /* The Darwin approach is (slightly) different, in order to be
25913 compatible with code generated by the system toolchain. There is a
25914 single symbol for the start of save sequence, and the code here
25915 embeds an offset into that code on the basis of the first register
25917 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25918 if ((sel & SAVRES_REG) == SAVRES_GPR)
25919 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25920 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25921 (regno - 13) * 4, prefix, regno);
25922 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25923 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25924 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25925 else if ((sel & SAVRES_REG) == SAVRES_VR)
25926 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25927 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25932 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25934 return savres_routine_name;
25937 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25938 We are saving/restoring GPRs if GPR is true. */
25941 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25943 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25944 ? info->first_gp_reg_save
25945 : (sel & SAVRES_REG) == SAVRES_FPR
25946 ? info->first_fp_reg_save - 32
25947 : (sel & SAVRES_REG) == SAVRES_VR
25948 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25953 /* Don't generate bogus routine names. */
25954 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25955 && regno <= LAST_SAVRES_REGISTER
25956 && select >= 0 && select <= 12);
25958 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25964 name = rs6000_savres_routine_name (regno, sel);
25966 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25967 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25968 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25974 /* Emit a sequence of insns, including a stack tie if needed, for
25975 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25976 reset the stack pointer, but move the base of the frame into
25977 reg UPDT_REGNO for use by out-of-line register restore routines. */
25980 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25981 unsigned updt_regno)
25983 /* If there is nothing to do, don't do anything. */
25984 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25987 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25989 /* This blockage is needed so that sched doesn't decide to move
25990 the sp change before the register restores. */
25991 if (DEFAULT_ABI == ABI_V4)
25992 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25993 GEN_INT (frame_off)));
25995 /* If we are restoring registers out-of-line, we will be using the
25996 "exit" variants of the restore routines, which will reset the
25997 stack for us. But we do need to point updt_reg into the
25998 right place for those routines. */
25999 if (frame_off != 0)
26000 return emit_insn (gen_add3_insn (updt_reg_rtx,
26001 frame_reg_rtx, GEN_INT (frame_off)));
26003 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26008 /* Return the register number used as a pointer by out-of-line
26009 save/restore functions. */
26011 static inline unsigned
26012 ptr_regno_for_savres (int sel)
26014 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26015 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26016 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26019 /* Construct a parallel rtx describing the effect of a call to an
26020 out-of-line register save/restore routine, and emit the insn
26021 or jump_insn as appropriate. */
26024 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26025 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26026 machine_mode reg_mode, int sel)
26029 int offset, start_reg, end_reg, n_regs, use_reg;
26030 int reg_size = GET_MODE_SIZE (reg_mode);
26037 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26038 ? info->first_gp_reg_save
26039 : (sel & SAVRES_REG) == SAVRES_FPR
26040 ? info->first_fp_reg_save
26041 : (sel & SAVRES_REG) == SAVRES_VR
26042 ? info->first_altivec_reg_save
26044 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26046 : (sel & SAVRES_REG) == SAVRES_FPR
26048 : (sel & SAVRES_REG) == SAVRES_VR
26049 ? LAST_ALTIVEC_REGNO + 1
26051 n_regs = end_reg - start_reg;
26052 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26053 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26056 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26057 RTVEC_ELT (p, offset++) = ret_rtx;
26059 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
26061 sym = rs6000_savres_routine_sym (info, sel);
26062 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26064 use_reg = ptr_regno_for_savres (sel);
26065 if ((sel & SAVRES_REG) == SAVRES_VR)
26067 /* Vector regs are saved/restored using [reg+reg] addressing. */
26068 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
26069 RTVEC_ELT (p, offset++)
26070 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26073 RTVEC_ELT (p, offset++)
26074 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26076 for (i = 0; i < end_reg - start_reg; i++)
26077 RTVEC_ELT (p, i + offset)
26078 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26079 frame_reg_rtx, save_area_offset + reg_size * i,
26080 (sel & SAVRES_SAVE) != 0);
26082 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26083 RTVEC_ELT (p, i + offset)
26084 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26086 par = gen_rtx_PARALLEL (VOIDmode, p);
26088 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26090 insn = emit_jump_insn (par);
26091 JUMP_LABEL (insn) = ret_rtx;
26094 insn = emit_insn (par);
26098 /* Emit prologue code to store CR fields that need to be saved into REG. This
26099 function should only be called when moving the non-volatile CRs to REG, it
26100 is not a general purpose routine to move the entire set of CRs to REG.
26101 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26105 rs6000_emit_prologue_move_from_cr (rtx reg)
26107 /* Only the ELFv2 ABI allows storing only selected fields. */
26108 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26110 int i, cr_reg[8], count = 0;
26112 /* Collect CR fields that must be saved. */
26113 for (i = 0; i < 8; i++)
26114 if (save_reg_p (CR0_REGNO + i))
26115 cr_reg[count++] = i;
26117 /* If it's just a single one, use mfcrf. */
26120 rtvec p = rtvec_alloc (1);
26121 rtvec r = rtvec_alloc (2);
26122 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26123 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26125 = gen_rtx_SET (reg,
26126 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26128 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26132 /* ??? It might be better to handle count == 2 / 3 cases here
26133 as well, using logical operations to combine the values. */
26136 emit_insn (gen_prologue_movesi_from_cr (reg));
26139 /* Return whether the split-stack arg pointer (r12) is used. */
26142 split_stack_arg_pointer_used_p (void)
26144 /* If the pseudo holding the arg pointer is no longer a pseudo,
26145 then the arg pointer is used. */
26146 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26147 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26148 || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
26151 /* Unfortunately we also need to do some code scanning, since
26152 r12 may have been substituted for the pseudo. */
26154 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26155 FOR_BB_INSNS (bb, insn)
26156 if (NONDEBUG_INSN_P (insn))
26158 /* A call destroys r12. */
26163 FOR_EACH_INSN_USE (use, insn)
26165 rtx x = DF_REF_REG (use);
26166 if (REG_P (x) && REGNO (x) == 12)
26170 FOR_EACH_INSN_DEF (def, insn)
26172 rtx x = DF_REF_REG (def);
26173 if (REG_P (x) && REGNO (x) == 12)
26177 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26180 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26183 rs6000_global_entry_point_prologue_needed_p (void)
26185 /* Only needed for the ELFv2 ABI. */
26186 if (DEFAULT_ABI != ABI_ELFv2)
26189 /* With -msingle-pic-base, we assume the whole program shares the same
26190 TOC, so no global entry point prologues are needed anywhere. */
26191 if (TARGET_SINGLE_PIC_BASE)
26194 /* PC-relative functions never generate a global entry point prologue. */
26195 if (rs6000_pcrel_p (cfun))
26198 /* Ensure we have a global entry point for thunks. ??? We could
26199 avoid that if the target routine doesn't need a global entry point,
26200 but we do not know whether this is the case at this point. */
26201 if (cfun->is_thunk)
26204 /* For regular functions, rs6000_emit_prologue sets this flag if the
26205 routine ever uses the TOC pointer. */
26206 return cfun->machine->r2_setup_needed;
26209 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26211 rs6000_get_separate_components (void)
26213 rs6000_stack_t *info = rs6000_stack_info ();
26215 if (WORLD_SAVE_P (info))
26218 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26219 && !(info->savres_strategy & REST_MULTIPLE));
26221 /* Component 0 is the save/restore of LR (done via GPR0).
26222 Component 2 is the save of the TOC (GPR2).
26223 Components 13..31 are the save/restore of GPR13..GPR31.
26224 Components 46..63 are the save/restore of FPR14..FPR31. */
26226 cfun->machine->n_components = 64;
26228 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26229 bitmap_clear (components);
26231 int reg_size = TARGET_32BIT ? 4 : 8;
26232 int fp_reg_size = 8;
26234 /* The GPRs we need saved to the frame. */
26235 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26236 && (info->savres_strategy & REST_INLINE_GPRS))
26238 int offset = info->gp_save_offset;
26240 offset += info->total_size;
26242 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26244 if (IN_RANGE (offset, -0x8000, 0x7fff)
26245 && save_reg_p (regno))
26246 bitmap_set_bit (components, regno);
26248 offset += reg_size;
26252 /* Don't mess with the hard frame pointer. */
26253 if (frame_pointer_needed)
26254 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26256 /* Don't mess with the fixed TOC register. */
26257 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26258 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26259 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26260 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26262 /* The FPRs we need saved to the frame. */
26263 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26264 && (info->savres_strategy & REST_INLINE_FPRS))
26266 int offset = info->fp_save_offset;
26268 offset += info->total_size;
26270 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26272 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26273 bitmap_set_bit (components, regno);
26275 offset += fp_reg_size;
26279 /* Optimize LR save and restore if we can. This is component 0. Any
26280 out-of-line register save/restore routines need LR. */
26281 if (info->lr_save_p
26282 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26283 && (info->savres_strategy & SAVE_INLINE_GPRS)
26284 && (info->savres_strategy & REST_INLINE_GPRS)
26285 && (info->savres_strategy & SAVE_INLINE_FPRS)
26286 && (info->savres_strategy & REST_INLINE_FPRS)
26287 && (info->savres_strategy & SAVE_INLINE_VRS)
26288 && (info->savres_strategy & REST_INLINE_VRS))
26290 int offset = info->lr_save_offset;
26292 offset += info->total_size;
26293 if (IN_RANGE (offset, -0x8000, 0x7fff))
26294 bitmap_set_bit (components, 0);
26297 /* Optimize saving the TOC. This is component 2. */
26298 if (cfun->machine->save_toc_in_prologue)
26299 bitmap_set_bit (components, 2);
26304 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26306 rs6000_components_for_bb (basic_block bb)
26308 rs6000_stack_t *info = rs6000_stack_info ();
26310 bitmap in = DF_LIVE_IN (bb);
26311 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26312 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26314 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26315 bitmap_clear (components);
26317 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26320 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26321 if (bitmap_bit_p (in, regno)
26322 || bitmap_bit_p (gen, regno)
26323 || bitmap_bit_p (kill, regno))
26324 bitmap_set_bit (components, regno);
26327 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26328 if (bitmap_bit_p (in, regno)
26329 || bitmap_bit_p (gen, regno)
26330 || bitmap_bit_p (kill, regno))
26331 bitmap_set_bit (components, regno);
26333 /* The link register. */
26334 if (bitmap_bit_p (in, LR_REGNO)
26335 || bitmap_bit_p (gen, LR_REGNO)
26336 || bitmap_bit_p (kill, LR_REGNO))
26337 bitmap_set_bit (components, 0);
26339 /* The TOC save. */
26340 if (bitmap_bit_p (in, TOC_REGNUM)
26341 || bitmap_bit_p (gen, TOC_REGNUM)
26342 || bitmap_bit_p (kill, TOC_REGNUM))
26343 bitmap_set_bit (components, 2);
26348 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26350 rs6000_disqualify_components (sbitmap components, edge e,
26351 sbitmap edge_components, bool /*is_prologue*/)
26353 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26354 live where we want to place that code. */
26355 if (bitmap_bit_p (edge_components, 0)
26356 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26359 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26360 "on entry to bb %d\n", e->dest->index);
26361 bitmap_clear_bit (components, 0);
26365 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26367 rs6000_emit_prologue_components (sbitmap components)
26369 rs6000_stack_t *info = rs6000_stack_info ();
26370 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26371 ? HARD_FRAME_POINTER_REGNUM
26372 : STACK_POINTER_REGNUM);
26374 machine_mode reg_mode = Pmode;
26375 int reg_size = TARGET_32BIT ? 4 : 8;
26376 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26377 int fp_reg_size = 8;
26379 /* Prologue for LR. */
26380 if (bitmap_bit_p (components, 0))
26382 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26383 rtx reg = gen_rtx_REG (reg_mode, 0);
26384 rtx_insn *insn = emit_move_insn (reg, lr);
26385 RTX_FRAME_RELATED_P (insn) = 1;
26386 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26388 int offset = info->lr_save_offset;
26390 offset += info->total_size;
26392 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26393 RTX_FRAME_RELATED_P (insn) = 1;
26394 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26395 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26398 /* Prologue for TOC. */
26399 if (bitmap_bit_p (components, 2))
26401 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26402 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26403 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26406 /* Prologue for the GPRs. */
26407 int offset = info->gp_save_offset;
26409 offset += info->total_size;
26411 for (int i = info->first_gp_reg_save; i < 32; i++)
26413 if (bitmap_bit_p (components, i))
26415 rtx reg = gen_rtx_REG (reg_mode, i);
26416 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26417 RTX_FRAME_RELATED_P (insn) = 1;
26418 rtx set = copy_rtx (single_set (insn));
26419 add_reg_note (insn, REG_CFA_OFFSET, set);
26422 offset += reg_size;
26425 /* Prologue for the FPRs. */
26426 offset = info->fp_save_offset;
26428 offset += info->total_size;
26430 for (int i = info->first_fp_reg_save; i < 64; i++)
26432 if (bitmap_bit_p (components, i))
26434 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26435 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26436 RTX_FRAME_RELATED_P (insn) = 1;
26437 rtx set = copy_rtx (single_set (insn));
26438 add_reg_note (insn, REG_CFA_OFFSET, set);
26441 offset += fp_reg_size;
26445 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26447 rs6000_emit_epilogue_components (sbitmap components)
26449 rs6000_stack_t *info = rs6000_stack_info ();
26450 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26451 ? HARD_FRAME_POINTER_REGNUM
26452 : STACK_POINTER_REGNUM);
26454 machine_mode reg_mode = Pmode;
26455 int reg_size = TARGET_32BIT ? 4 : 8;
26457 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26458 int fp_reg_size = 8;
26460 /* Epilogue for the FPRs. */
26461 int offset = info->fp_save_offset;
26463 offset += info->total_size;
26465 for (int i = info->first_fp_reg_save; i < 64; i++)
26467 if (bitmap_bit_p (components, i))
26469 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26470 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26471 RTX_FRAME_RELATED_P (insn) = 1;
26472 add_reg_note (insn, REG_CFA_RESTORE, reg);
26475 offset += fp_reg_size;
26478 /* Epilogue for the GPRs. */
26479 offset = info->gp_save_offset;
26481 offset += info->total_size;
26483 for (int i = info->first_gp_reg_save; i < 32; i++)
26485 if (bitmap_bit_p (components, i))
26487 rtx reg = gen_rtx_REG (reg_mode, i);
26488 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26489 RTX_FRAME_RELATED_P (insn) = 1;
26490 add_reg_note (insn, REG_CFA_RESTORE, reg);
26493 offset += reg_size;
26496 /* Epilogue for LR. */
26497 if (bitmap_bit_p (components, 0))
26499 int offset = info->lr_save_offset;
26501 offset += info->total_size;
26503 rtx reg = gen_rtx_REG (reg_mode, 0);
26504 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26506 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26507 insn = emit_move_insn (lr, reg);
26508 RTX_FRAME_RELATED_P (insn) = 1;
26509 add_reg_note (insn, REG_CFA_RESTORE, lr);
26513 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26515 rs6000_set_handled_components (sbitmap components)
26517 rs6000_stack_t *info = rs6000_stack_info ();
26519 for (int i = info->first_gp_reg_save; i < 32; i++)
26520 if (bitmap_bit_p (components, i))
26521 cfun->machine->gpr_is_wrapped_separately[i] = true;
26523 for (int i = info->first_fp_reg_save; i < 64; i++)
26524 if (bitmap_bit_p (components, i))
26525 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26527 if (bitmap_bit_p (components, 0))
26528 cfun->machine->lr_is_wrapped_separately = true;
26530 if (bitmap_bit_p (components, 2))
26531 cfun->machine->toc_is_wrapped_separately = true;
26534 /* VRSAVE is a bit vector representing which AltiVec registers
26535 are used. The OS uses this to determine which vector
26536 registers to save on a context switch. We need to save
26537 VRSAVE on the stack frame, add whatever AltiVec registers we
26538 used in this function, and do the corresponding magic in the
26541 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26542 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26544 /* Get VRSAVE into a GPR. */
26545 rtx reg = gen_rtx_REG (SImode, save_regno);
26546 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26548 emit_insn (gen_get_vrsave_internal (reg));
26550 emit_insn (gen_rtx_SET (reg, vrsave));
26553 int offset = info->vrsave_save_offset + frame_off;
26554 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26556 /* Include the registers in the mask. */
26557 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26559 emit_insn (generate_set_vrsave (reg, info, 0));
26562 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26563 called, it left the arg pointer to the old stack in r29. Otherwise, the
26564 arg pointer is the top of the current frame. */
26566 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26567 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26569 cfun->machine->split_stack_argp_used = true;
26573 rtx r12 = gen_rtx_REG (Pmode, 12);
26574 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26575 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26576 emit_insn_before (set_r12, sp_adjust);
26578 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26580 rtx r12 = gen_rtx_REG (Pmode, 12);
26581 if (frame_off == 0)
26582 emit_move_insn (r12, frame_reg_rtx);
26584 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26589 rtx r12 = gen_rtx_REG (Pmode, 12);
26590 rtx r29 = gen_rtx_REG (Pmode, 29);
26591 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26592 rtx not_more = gen_label_rtx ();
26595 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26596 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26597 gen_rtx_LABEL_REF (VOIDmode, not_more),
26599 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26600 JUMP_LABEL (jump) = not_more;
26601 LABEL_NUSES (not_more) += 1;
26602 emit_move_insn (r12, r29);
26603 emit_label (not_more);
26607 /* Emit function prologue as insns. */
26610 rs6000_emit_prologue (void)
26612 rs6000_stack_t *info = rs6000_stack_info ();
26613 machine_mode reg_mode = Pmode;
26614 int reg_size = TARGET_32BIT ? 4 : 8;
26615 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26616 int fp_reg_size = 8;
26617 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26618 rtx frame_reg_rtx = sp_reg_rtx;
26619 unsigned int cr_save_regno;
26620 rtx cr_save_rtx = NULL_RTX;
26623 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26624 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26625 && call_used_regs[STATIC_CHAIN_REGNUM]);
26626 int using_split_stack = (flag_split_stack
26627 && (lookup_attribute ("no_split_stack",
26628 DECL_ATTRIBUTES (cfun->decl))
26631 /* Offset to top of frame for frame_reg and sp respectively. */
26632 HOST_WIDE_INT frame_off = 0;
26633 HOST_WIDE_INT sp_off = 0;
26634 /* sp_adjust is the stack adjusting instruction, tracked so that the
26635 insn setting up the split-stack arg pointer can be emitted just
26636 prior to it, when r12 is not used here for other purposes. */
26637 rtx_insn *sp_adjust = 0;
26640 /* Track and check usage of r0, r11, r12. */
26641 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26642 #define START_USE(R) do \
26644 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26645 reg_inuse |= 1 << (R); \
26647 #define END_USE(R) do \
26649 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26650 reg_inuse &= ~(1 << (R)); \
26652 #define NOT_INUSE(R) do \
26654 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26657 #define START_USE(R) do {} while (0)
26658 #define END_USE(R) do {} while (0)
26659 #define NOT_INUSE(R) do {} while (0)
26662 if (DEFAULT_ABI == ABI_ELFv2
26663 && !TARGET_SINGLE_PIC_BASE)
26665 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26667 /* With -mminimal-toc we may generate an extra use of r2 below. */
26668 if (TARGET_TOC && TARGET_MINIMAL_TOC
26669 && !constant_pool_empty_p ())
26670 cfun->machine->r2_setup_needed = true;
26674 if (flag_stack_usage_info)
26675 current_function_static_stack_size = info->total_size;
26677 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26679 HOST_WIDE_INT size = info->total_size;
26681 if (crtl->is_leaf && !cfun->calls_alloca)
26683 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26684 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26685 size - get_stack_check_protect ());
26688 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26691 if (TARGET_FIX_AND_CONTINUE)
26693 /* gdb on darwin arranges to forward a function from the old
26694 address by modifying the first 5 instructions of the function
26695 to branch to the overriding function. This is necessary to
26696 permit function pointers that point to the old function to
26697 actually forward to the new function. */
26698 emit_insn (gen_nop ());
26699 emit_insn (gen_nop ());
26700 emit_insn (gen_nop ());
26701 emit_insn (gen_nop ());
26702 emit_insn (gen_nop ());
26705 /* Handle world saves specially here. */
26706 if (WORLD_SAVE_P (info))
26713 /* save_world expects lr in r0. */
26714 reg0 = gen_rtx_REG (Pmode, 0);
26715 if (info->lr_save_p)
26717 insn = emit_move_insn (reg0,
26718 gen_rtx_REG (Pmode, LR_REGNO));
26719 RTX_FRAME_RELATED_P (insn) = 1;
26722 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26723 assumptions about the offsets of various bits of the stack
26725 gcc_assert (info->gp_save_offset == -220
26726 && info->fp_save_offset == -144
26727 && info->lr_save_offset == 8
26728 && info->cr_save_offset == 4
26731 && (!crtl->calls_eh_return
26732 || info->ehrd_offset == -432)
26733 && info->vrsave_save_offset == -224
26734 && info->altivec_save_offset == -416);
26736 treg = gen_rtx_REG (SImode, 11);
26737 emit_move_insn (treg, GEN_INT (-info->total_size));
26739 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26740 in R11. It also clobbers R12, so beware! */
26742 /* Preserve CR2 for save_world prologues */
26744 sz += 32 - info->first_gp_reg_save;
26745 sz += 64 - info->first_fp_reg_save;
26746 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26747 p = rtvec_alloc (sz);
26749 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
26750 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26751 gen_rtx_SYMBOL_REF (Pmode,
26753 /* We do floats first so that the instruction pattern matches
26755 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26757 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26758 info->first_fp_reg_save + i),
26760 info->fp_save_offset + frame_off + 8 * i);
26761 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26763 = gen_frame_store (gen_rtx_REG (V4SImode,
26764 info->first_altivec_reg_save + i),
26766 info->altivec_save_offset + frame_off + 16 * i);
26767 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26769 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26771 info->gp_save_offset + frame_off + reg_size * i);
26773 /* CR register traditionally saved as CR2. */
26775 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26776 frame_reg_rtx, info->cr_save_offset + frame_off);
26777 /* Explain about use of R0. */
26778 if (info->lr_save_p)
26780 = gen_frame_store (reg0,
26781 frame_reg_rtx, info->lr_save_offset + frame_off);
26782 /* Explain what happens to the stack pointer. */
26784 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26785 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26788 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26789 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26790 treg, GEN_INT (-info->total_size));
26791 sp_off = frame_off = info->total_size;
26794 strategy = info->savres_strategy;
26796 /* For V.4, update stack before we do any saving and set back pointer. */
26797 if (! WORLD_SAVE_P (info)
26799 && (DEFAULT_ABI == ABI_V4
26800 || crtl->calls_eh_return))
26802 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26803 || !(strategy & SAVE_INLINE_GPRS)
26804 || !(strategy & SAVE_INLINE_VRS));
26805 int ptr_regno = -1;
26806 rtx ptr_reg = NULL_RTX;
26809 if (info->total_size < 32767)
26810 frame_off = info->total_size;
26813 else if (info->cr_save_p
26815 || info->first_fp_reg_save < 64
26816 || info->first_gp_reg_save < 32
26817 || info->altivec_size != 0
26818 || info->vrsave_size != 0
26819 || crtl->calls_eh_return)
26823 /* The prologue won't be saving any regs so there is no need
26824 to set up a frame register to access any frame save area.
26825 We also won't be using frame_off anywhere below, but set
26826 the correct value anyway to protect against future
26827 changes to this function. */
26828 frame_off = info->total_size;
26830 if (ptr_regno != -1)
26832 /* Set up the frame offset to that needed by the first
26833 out-of-line save function. */
26834 START_USE (ptr_regno);
26835 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26836 frame_reg_rtx = ptr_reg;
26837 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26838 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26839 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26840 ptr_off = info->gp_save_offset + info->gp_size;
26841 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26842 ptr_off = info->altivec_save_offset + info->altivec_size;
26843 frame_off = -ptr_off;
26845 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26847 if (REGNO (frame_reg_rtx) == 12)
26849 sp_off = info->total_size;
26850 if (frame_reg_rtx != sp_reg_rtx)
26851 rs6000_emit_stack_tie (frame_reg_rtx, false);
26854 /* If we use the link register, get it into r0. */
26855 if (!WORLD_SAVE_P (info) && info->lr_save_p
26856 && !cfun->machine->lr_is_wrapped_separately)
26858 rtx addr, reg, mem;
26860 reg = gen_rtx_REG (Pmode, 0);
26862 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26863 RTX_FRAME_RELATED_P (insn) = 1;
26865 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26866 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26868 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26869 GEN_INT (info->lr_save_offset + frame_off));
26870 mem = gen_rtx_MEM (Pmode, addr);
26871 /* This should not be of rs6000_sr_alias_set, because of
26872 __builtin_return_address. */
26874 insn = emit_move_insn (mem, reg);
26875 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26876 NULL_RTX, NULL_RTX);
26881 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26882 r12 will be needed by out-of-line gpr save. */
26883 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26884 && !(strategy & (SAVE_INLINE_GPRS
26885 | SAVE_NOINLINE_GPRS_SAVES_LR))
26887 if (!WORLD_SAVE_P (info)
26889 && REGNO (frame_reg_rtx) != cr_save_regno
26890 && !(using_static_chain_p && cr_save_regno == 11)
26891 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26893 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26894 START_USE (cr_save_regno);
26895 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26898 /* Do any required saving of fpr's. If only one or two to save, do
26899 it ourselves. Otherwise, call function. */
26900 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26902 int offset = info->fp_save_offset + frame_off;
26903 for (int i = info->first_fp_reg_save; i < 64; i++)
26906 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26907 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26908 sp_off - frame_off);
26910 offset += fp_reg_size;
26913 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26915 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26916 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26917 unsigned ptr_regno = ptr_regno_for_savres (sel);
26918 rtx ptr_reg = frame_reg_rtx;
26920 if (REGNO (frame_reg_rtx) == ptr_regno)
26921 gcc_checking_assert (frame_off == 0);
26924 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26925 NOT_INUSE (ptr_regno);
26926 emit_insn (gen_add3_insn (ptr_reg,
26927 frame_reg_rtx, GEN_INT (frame_off)));
26929 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26930 info->fp_save_offset,
26931 info->lr_save_offset,
26933 rs6000_frame_related (insn, ptr_reg, sp_off,
26934 NULL_RTX, NULL_RTX);
26939 /* Save GPRs. This is done as a PARALLEL if we are using
26940 the store-multiple instructions. */
26941 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26943 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26944 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26945 unsigned ptr_regno = ptr_regno_for_savres (sel);
26946 rtx ptr_reg = frame_reg_rtx;
26947 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26948 int end_save = info->gp_save_offset + info->gp_size;
26951 if (ptr_regno == 12)
26954 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26956 /* Need to adjust r11 (r12) if we saved any FPRs. */
26957 if (end_save + frame_off != 0)
26959 rtx offset = GEN_INT (end_save + frame_off);
26962 frame_off = -end_save;
26964 NOT_INUSE (ptr_regno);
26965 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26967 else if (!ptr_set_up)
26969 NOT_INUSE (ptr_regno);
26970 emit_move_insn (ptr_reg, frame_reg_rtx);
26972 ptr_off = -end_save;
26973 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26974 info->gp_save_offset + ptr_off,
26975 info->lr_save_offset + ptr_off,
26977 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26978 NULL_RTX, NULL_RTX);
26982 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26986 p = rtvec_alloc (32 - info->first_gp_reg_save);
26987 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26989 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26991 info->gp_save_offset + frame_off + reg_size * i);
26992 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26993 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26994 NULL_RTX, NULL_RTX);
26996 else if (!WORLD_SAVE_P (info))
26998 int offset = info->gp_save_offset + frame_off;
26999 for (int i = info->first_gp_reg_save; i < 32; i++)
27002 && !cfun->machine->gpr_is_wrapped_separately[i])
27003 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27004 sp_off - frame_off);
27006 offset += reg_size;
27010 if (crtl->calls_eh_return)
27017 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27018 if (regno == INVALID_REGNUM)
27022 p = rtvec_alloc (i);
27026 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27027 if (regno == INVALID_REGNUM)
27031 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27033 info->ehrd_offset + sp_off + reg_size * (int) i);
27034 RTVEC_ELT (p, i) = set;
27035 RTX_FRAME_RELATED_P (set) = 1;
27038 insn = emit_insn (gen_blockage ());
27039 RTX_FRAME_RELATED_P (insn) = 1;
27040 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27043 /* In AIX ABI we need to make sure r2 is really saved. */
27044 if (TARGET_AIX && crtl->calls_eh_return)
27046 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27047 rtx join_insn, note;
27048 rtx_insn *save_insn;
27049 long toc_restore_insn;
27051 tmp_reg = gen_rtx_REG (Pmode, 11);
27052 tmp_reg_si = gen_rtx_REG (SImode, 11);
27053 if (using_static_chain_p)
27056 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27060 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27061 /* Peek at instruction to which this function returns. If it's
27062 restoring r2, then we know we've already saved r2. We can't
27063 unconditionally save r2 because the value we have will already
27064 be updated if we arrived at this function via a plt call or
27065 toc adjusting stub. */
27066 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27067 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27068 + RS6000_TOC_SAVE_SLOT);
27069 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27070 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27071 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27072 validate_condition_mode (EQ, CCUNSmode);
27073 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27074 emit_insn (gen_rtx_SET (compare_result,
27075 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27076 toc_save_done = gen_label_rtx ();
27077 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27078 gen_rtx_EQ (VOIDmode, compare_result,
27080 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27082 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27083 JUMP_LABEL (jump) = toc_save_done;
27084 LABEL_NUSES (toc_save_done) += 1;
27086 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27087 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27088 sp_off - frame_off);
27090 emit_label (toc_save_done);
27092 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27093 have a CFG that has different saves along different paths.
27094 Move the note to a dummy blockage insn, which describes that
27095 R2 is unconditionally saved after the label. */
27096 /* ??? An alternate representation might be a special insn pattern
27097 containing both the branch and the store. That might let the
27098 code that minimizes the number of DW_CFA_advance opcodes better
27099 freedom in placing the annotations. */
27100 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27102 remove_note (save_insn, note);
27104 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27105 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27106 RTX_FRAME_RELATED_P (save_insn) = 0;
27108 join_insn = emit_insn (gen_blockage ());
27109 REG_NOTES (join_insn) = note;
27110 RTX_FRAME_RELATED_P (join_insn) = 1;
27112 if (using_static_chain_p)
27114 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27121 /* Save CR if we use any that must be preserved. */
27122 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27124 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27125 GEN_INT (info->cr_save_offset + frame_off));
27126 rtx mem = gen_frame_mem (SImode, addr);
27128 /* If we didn't copy cr before, do so now using r0. */
27129 if (cr_save_rtx == NULL_RTX)
27132 cr_save_rtx = gen_rtx_REG (SImode, 0);
27133 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27136 /* Saving CR requires a two-instruction sequence: one instruction
27137 to move the CR to a general-purpose register, and a second
27138 instruction that stores the GPR to memory.
27140 We do not emit any DWARF CFI records for the first of these,
27141 because we cannot properly represent the fact that CR is saved in
27142 a register. One reason is that we cannot express that multiple
27143 CR fields are saved; another reason is that on 64-bit, the size
27144 of the CR register in DWARF (4 bytes) differs from the size of
27145 a general-purpose register.
27147 This means if any intervening instruction were to clobber one of
27148 the call-saved CR fields, we'd have incorrect CFI. To prevent
27149 this from happening, we mark the store to memory as a use of
27150 those CR fields, which prevents any such instruction from being
27151 scheduled in between the two instructions. */
27156 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27157 for (i = 0; i < 8; i++)
27158 if (save_reg_p (CR0_REGNO + i))
27159 crsave_v[n_crsave++]
27160 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27162 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27163 gen_rtvec_v (n_crsave, crsave_v)));
27164 END_USE (REGNO (cr_save_rtx));
27166 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27167 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27168 so we need to construct a frame expression manually. */
27169 RTX_FRAME_RELATED_P (insn) = 1;
27171 /* Update address to be stack-pointer relative, like
27172 rs6000_frame_related would do. */
27173 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27174 GEN_INT (info->cr_save_offset + sp_off));
27175 mem = gen_frame_mem (SImode, addr);
27177 if (DEFAULT_ABI == ABI_ELFv2)
27179 /* In the ELFv2 ABI we generate separate CFI records for each
27180 CR field that was actually saved. They all point to the
27181 same 32-bit stack slot. */
27185 for (i = 0; i < 8; i++)
27186 if (save_reg_p (CR0_REGNO + i))
27189 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27191 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27195 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27196 gen_rtx_PARALLEL (VOIDmode,
27197 gen_rtvec_v (n_crframe, crframe)));
27201 /* In other ABIs, by convention, we use a single CR regnum to
27202 represent the fact that all call-saved CR fields are saved.
27203 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27204 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27205 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27209 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27210 *separate* slots if the routine calls __builtin_eh_return, so
27211 that they can be independently restored by the unwinder. */
27212 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27214 int i, cr_off = info->ehcr_offset;
27217 /* ??? We might get better performance by using multiple mfocrf
27219 crsave = gen_rtx_REG (SImode, 0);
27220 emit_insn (gen_prologue_movesi_from_cr (crsave));
27222 for (i = 0; i < 8; i++)
27223 if (!call_used_regs[CR0_REGNO + i])
27225 rtvec p = rtvec_alloc (2);
27227 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27229 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27231 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27233 RTX_FRAME_RELATED_P (insn) = 1;
27234 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27235 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27236 sp_reg_rtx, cr_off + sp_off));
27238 cr_off += reg_size;
27242 /* If we are emitting stack probes, but allocate no stack, then
27243 just note that in the dump file. */
27244 if (flag_stack_clash_protection
27247 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27249 /* Update stack and set back pointer unless this is V.4,
27250 for which it was done previously. */
27251 if (!WORLD_SAVE_P (info) && info->push_p
27252 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27254 rtx ptr_reg = NULL;
27257 /* If saving altivec regs we need to be able to address all save
27258 locations using a 16-bit offset. */
27259 if ((strategy & SAVE_INLINE_VRS) == 0
27260 || (info->altivec_size != 0
27261 && (info->altivec_save_offset + info->altivec_size - 16
27262 + info->total_size - frame_off) > 32767)
27263 || (info->vrsave_size != 0
27264 && (info->vrsave_save_offset
27265 + info->total_size - frame_off) > 32767))
27267 int sel = SAVRES_SAVE | SAVRES_VR;
27268 unsigned ptr_regno = ptr_regno_for_savres (sel);
27270 if (using_static_chain_p
27271 && ptr_regno == STATIC_CHAIN_REGNUM)
27273 if (REGNO (frame_reg_rtx) != ptr_regno)
27274 START_USE (ptr_regno);
27275 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27276 frame_reg_rtx = ptr_reg;
27277 ptr_off = info->altivec_save_offset + info->altivec_size;
27278 frame_off = -ptr_off;
27280 else if (REGNO (frame_reg_rtx) == 1)
27281 frame_off = info->total_size;
27282 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27284 if (REGNO (frame_reg_rtx) == 12)
27286 sp_off = info->total_size;
27287 if (frame_reg_rtx != sp_reg_rtx)
27288 rs6000_emit_stack_tie (frame_reg_rtx, false);
27291 /* Set frame pointer, if needed. */
27292 if (frame_pointer_needed)
27294 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27296 RTX_FRAME_RELATED_P (insn) = 1;
27299 /* Save AltiVec registers if needed. Save here because the red zone does
27300 not always include AltiVec registers. */
27301 if (!WORLD_SAVE_P (info)
27302 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27304 int end_save = info->altivec_save_offset + info->altivec_size;
27306 /* Oddly, the vector save/restore functions point r0 at the end
27307 of the save area, then use r11 or r12 to load offsets for
27308 [reg+reg] addressing. */
27309 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27310 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27311 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27313 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27315 if (scratch_regno == 12)
27317 if (end_save + frame_off != 0)
27319 rtx offset = GEN_INT (end_save + frame_off);
27321 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27324 emit_move_insn (ptr_reg, frame_reg_rtx);
27326 ptr_off = -end_save;
27327 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27328 info->altivec_save_offset + ptr_off,
27329 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27330 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27331 NULL_RTX, NULL_RTX);
27332 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27334 /* The oddity mentioned above clobbered our frame reg. */
27335 emit_move_insn (frame_reg_rtx, ptr_reg);
27336 frame_off = ptr_off;
27339 else if (!WORLD_SAVE_P (info)
27340 && info->altivec_size != 0)
27344 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27345 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27347 rtx areg, savereg, mem;
27348 HOST_WIDE_INT offset;
27350 offset = (info->altivec_save_offset + frame_off
27351 + 16 * (i - info->first_altivec_reg_save));
27353 savereg = gen_rtx_REG (V4SImode, i);
27355 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27357 mem = gen_frame_mem (V4SImode,
27358 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27359 GEN_INT (offset)));
27360 insn = emit_insn (gen_rtx_SET (mem, savereg));
27366 areg = gen_rtx_REG (Pmode, 0);
27367 emit_move_insn (areg, GEN_INT (offset));
27369 /* AltiVec addressing mode is [reg+reg]. */
27370 mem = gen_frame_mem (V4SImode,
27371 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27373 /* Rather than emitting a generic move, force use of the stvx
27374 instruction, which we always want on ISA 2.07 (power8) systems.
27375 In particular we don't want xxpermdi/stxvd2x for little
27377 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27380 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27381 areg, GEN_INT (offset));
27385 /* VRSAVE is a bit vector representing which AltiVec registers
27386 are used. The OS uses this to determine which vector
27387 registers to save on a context switch. We need to save
27388 VRSAVE on the stack frame, add whatever AltiVec registers we
27389 used in this function, and do the corresponding magic in the
27392 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27394 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27395 be using r12 as frame_reg_rtx and r11 as the static chain
27396 pointer for nested functions. */
27397 int save_regno = 12;
27398 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27399 && !using_static_chain_p)
27401 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27404 if (using_static_chain_p)
27407 NOT_INUSE (save_regno);
27409 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27412 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27413 if (!TARGET_SINGLE_PIC_BASE
27414 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27415 && !constant_pool_empty_p ())
27416 || (DEFAULT_ABI == ABI_V4
27417 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27418 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27420 /* If emit_load_toc_table will use the link register, we need to save
27421 it. We use R12 for this purpose because emit_load_toc_table
27422 can use register 0. This allows us to use a plain 'blr' to return
27423 from the procedure more often. */
27424 int save_LR_around_toc_setup = (TARGET_ELF
27425 && DEFAULT_ABI == ABI_V4
27427 && ! info->lr_save_p
27428 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27429 if (save_LR_around_toc_setup)
27431 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27432 rtx tmp = gen_rtx_REG (Pmode, 12);
27435 insn = emit_move_insn (tmp, lr);
27436 RTX_FRAME_RELATED_P (insn) = 1;
27438 rs6000_emit_load_toc_table (TRUE);
27440 insn = emit_move_insn (lr, tmp);
27441 add_reg_note (insn, REG_CFA_RESTORE, lr);
27442 RTX_FRAME_RELATED_P (insn) = 1;
27445 rs6000_emit_load_toc_table (TRUE);
27449 if (!TARGET_SINGLE_PIC_BASE
27450 && DEFAULT_ABI == ABI_DARWIN
27451 && flag_pic && crtl->uses_pic_offset_table)
27453 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27454 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27456 /* Save and restore LR locally around this call (in R0). */
27457 if (!info->lr_save_p)
27458 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27460 emit_insn (gen_load_macho_picbase (src));
27462 emit_move_insn (gen_rtx_REG (Pmode,
27463 RS6000_PIC_OFFSET_TABLE_REGNUM),
27466 if (!info->lr_save_p)
27467 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27471 /* If we need to, save the TOC register after doing the stack setup.
27472 Do not emit eh frame info for this save. The unwinder wants info,
27473 conceptually attached to instructions in this function, about
27474 register values in the caller of this function. This R2 may have
27475 already been changed from the value in the caller.
27476 We don't attempt to write accurate DWARF EH frame info for R2
27477 because code emitted by gcc for a (non-pointer) function call
27478 doesn't save and restore R2. Instead, R2 is managed out-of-line
27479 by a linker generated plt call stub when the function resides in
27480 a shared library. This behavior is costly to describe in DWARF,
27481 both in terms of the size of DWARF info and the time taken in the
27482 unwinder to interpret it. R2 changes, apart from the
27483 calls_eh_return case earlier in this function, are handled by
27484 linux-unwind.h frob_update_context. */
27485 if (rs6000_save_toc_in_prologue_p ()
27486 && !cfun->machine->toc_is_wrapped_separately)
27488 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27489 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27492 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27493 if (using_split_stack && split_stack_arg_pointer_used_p ())
27494 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27497 /* Output .extern statements for the save/restore routines we use. */
27500 rs6000_output_savres_externs (FILE *file)
27502 rs6000_stack_t *info = rs6000_stack_info ();
27504 if (TARGET_DEBUG_STACK)
27505 debug_stack_info (info);
27507 /* Write .extern for any function we will call to save and restore
27509 if (info->first_fp_reg_save < 64
27514 int regno = info->first_fp_reg_save - 32;
27516 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27518 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27519 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27520 name = rs6000_savres_routine_name (regno, sel);
27521 fprintf (file, "\t.extern %s\n", name);
27523 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27525 bool lr = (info->savres_strategy
27526 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27527 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27528 name = rs6000_savres_routine_name (regno, sel);
27529 fprintf (file, "\t.extern %s\n", name);
27534 /* Write function prologue. */
27537 rs6000_output_function_prologue (FILE *file)
27539 if (!cfun->is_thunk)
27541 rs6000_output_savres_externs (file);
27542 #ifdef USING_ELFOS_H
27543 const char *curr_machine = rs6000_machine_from_flags ();
27544 if (rs6000_machine != curr_machine)
27546 rs6000_machine = curr_machine;
27547 emit_asm_machine ();
27552 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27553 immediately after the global entry point label. */
27554 if (rs6000_global_entry_point_prologue_needed_p ())
27556 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27557 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27559 if (TARGET_CMODEL != CMODEL_LARGE)
27561 /* In the small and medium code models, we assume the TOC is less
27562 2 GB away from the text section, so it can be computed via the
27563 following two-instruction sequence. */
27566 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27567 fprintf (file, "0:\taddis 2,12,.TOC.-");
27568 assemble_name (file, buf);
27569 fprintf (file, "@ha\n");
27570 fprintf (file, "\taddi 2,2,.TOC.-");
27571 assemble_name (file, buf);
27572 fprintf (file, "@l\n");
27576 /* In the large code model, we allow arbitrary offsets between the
27577 TOC and the text section, so we have to load the offset from
27578 memory. The data field is emitted directly before the global
27579 entry point in rs6000_elf_declare_function_name. */
27582 #ifdef HAVE_AS_ENTRY_MARKERS
27583 /* If supported by the linker, emit a marker relocation. If the
27584 total code size of the final executable or shared library
27585 happens to fit into 2 GB after all, the linker will replace
27586 this code sequence with the sequence for the small or medium
27588 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27590 fprintf (file, "\tld 2,");
27591 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27592 assemble_name (file, buf);
27593 fprintf (file, "-");
27594 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27595 assemble_name (file, buf);
27596 fprintf (file, "(12)\n");
27597 fprintf (file, "\tadd 2,2,12\n");
27600 fputs ("\t.localentry\t", file);
27601 assemble_name (file, name);
27602 fputs (",.-", file);
27603 assemble_name (file, name);
27604 fputs ("\n", file);
27607 else if (rs6000_pcrel_p (cfun))
27609 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27610 /* All functions compiled to use PC-relative addressing will
27611 have a .localentry value of 0 or 1. For now we set it to
27612 1 all the time, indicating that the function may clobber
27613 the TOC register r2. Later we may optimize this by setting
27614 it to 0 if the function is a leaf and does not clobber r2. */
27615 fputs ("\t.localentry\t", file);
27616 assemble_name (file, name);
27617 fputs (",1\n", file);
27620 /* Output -mprofile-kernel code. This needs to be done here instead of
27621 in output_function_profile since it must go after the ELFv2 ABI
27622 local entry point. */
27623 if (TARGET_PROFILE_KERNEL && crtl->profile)
27625 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27626 gcc_assert (!TARGET_32BIT);
27628 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27630 /* In the ELFv2 ABI we have no compiler stack word. It must be
27631 the resposibility of _mcount to preserve the static chain
27632 register if required. */
27633 if (DEFAULT_ABI != ABI_ELFv2
27634 && cfun->static_chain_decl != NULL)
27636 asm_fprintf (file, "\tstd %s,24(%s)\n",
27637 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27638 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27639 asm_fprintf (file, "\tld %s,24(%s)\n",
27640 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27643 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27646 rs6000_pic_labelno++;
27649 /* -mprofile-kernel code calls mcount before the function prolog,
27650 so a profiled leaf function should stay a leaf function. */
27652 rs6000_keep_leaf_when_profiled ()
27654 return TARGET_PROFILE_KERNEL;
27657 /* Non-zero if vmx regs are restored before the frame pop, zero if
27658 we restore after the pop when possible. */
27659 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27661 /* Restoring cr is a two step process: loading a reg from the frame
27662 save, then moving the reg to cr. For ABI_V4 we must let the
27663 unwinder know that the stack location is no longer valid at or
27664 before the stack deallocation, but we can't emit a cfa_restore for
27665 cr at the stack deallocation like we do for other registers.
27666 The trouble is that it is possible for the move to cr to be
27667 scheduled after the stack deallocation. So say exactly where cr
27668 is located on each of the two insns. */
27671 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27673 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27674 rtx reg = gen_rtx_REG (SImode, regno);
27675 rtx_insn *insn = emit_move_insn (reg, mem);
27677 if (!exit_func && DEFAULT_ABI == ABI_V4)
27679 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27680 rtx set = gen_rtx_SET (reg, cr);
27682 add_reg_note (insn, REG_CFA_REGISTER, set);
27683 RTX_FRAME_RELATED_P (insn) = 1;
27688 /* Reload CR from REG. */
27691 restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func)
27696 if (using_mfcr_multiple)
27698 for (i = 0; i < 8; i++)
27699 if (save_reg_p (CR0_REGNO + i))
27701 gcc_assert (count);
27704 if (using_mfcr_multiple && count > 1)
27710 p = rtvec_alloc (count);
27713 for (i = 0; i < 8; i++)
27714 if (save_reg_p (CR0_REGNO + i))
27716 rtvec r = rtvec_alloc (2);
27717 RTVEC_ELT (r, 0) = reg;
27718 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27719 RTVEC_ELT (p, ndx) =
27720 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27721 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27724 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27725 gcc_assert (ndx == count);
27727 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27728 CR field separately. */
27729 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27731 for (i = 0; i < 8; i++)
27732 if (save_reg_p (CR0_REGNO + i))
27733 add_reg_note (insn, REG_CFA_RESTORE,
27734 gen_rtx_REG (SImode, CR0_REGNO + i));
27736 RTX_FRAME_RELATED_P (insn) = 1;
27740 for (i = 0; i < 8; i++)
27741 if (save_reg_p (CR0_REGNO + i))
27743 rtx insn = emit_insn (gen_movsi_to_cr_one
27744 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27746 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27747 CR field separately, attached to the insn that in fact
27748 restores this particular CR field. */
27749 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27751 add_reg_note (insn, REG_CFA_RESTORE,
27752 gen_rtx_REG (SImode, CR0_REGNO + i));
27754 RTX_FRAME_RELATED_P (insn) = 1;
27758 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27759 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27760 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27762 rtx_insn *insn = get_last_insn ();
27763 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27765 add_reg_note (insn, REG_CFA_RESTORE, cr);
27766 RTX_FRAME_RELATED_P (insn) = 1;
27770 /* Like cr, the move to lr instruction can be scheduled after the
27771 stack deallocation, but unlike cr, its stack frame save is still
27772 valid. So we only need to emit the cfa_restore on the correct
27776 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27778 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27779 rtx reg = gen_rtx_REG (Pmode, regno);
27781 emit_move_insn (reg, mem);
27785 restore_saved_lr (int regno, bool exit_func)
27787 rtx reg = gen_rtx_REG (Pmode, regno);
27788 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27789 rtx_insn *insn = emit_move_insn (lr, reg);
27791 if (!exit_func && flag_shrink_wrap)
27793 add_reg_note (insn, REG_CFA_RESTORE, lr);
27794 RTX_FRAME_RELATED_P (insn) = 1;
27799 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27801 if (DEFAULT_ABI == ABI_ELFv2)
27804 for (i = 0; i < 8; i++)
27805 if (save_reg_p (CR0_REGNO + i))
27807 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27808 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27812 else if (info->cr_save_p)
27813 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27814 gen_rtx_REG (SImode, CR2_REGNO),
27817 if (info->lr_save_p)
27818 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27819 gen_rtx_REG (Pmode, LR_REGNO),
27821 return cfa_restores;
27824 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27825 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27826 below stack pointer not cloberred by signals. */
27829 offset_below_red_zone_p (HOST_WIDE_INT offset)
27831 return offset < (DEFAULT_ABI == ABI_V4
27833 : TARGET_32BIT ? -220 : -288);
27836 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27839 emit_cfa_restores (rtx cfa_restores)
27841 rtx_insn *insn = get_last_insn ();
27842 rtx *loc = ®_NOTES (insn);
27845 loc = &XEXP (*loc, 1);
27846 *loc = cfa_restores;
27847 RTX_FRAME_RELATED_P (insn) = 1;
27850 /* Emit function epilogue as insns. */
27853 rs6000_emit_epilogue (enum epilogue_type epilogue_type)
27855 HOST_WIDE_INT frame_off = 0;
27856 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27857 rtx frame_reg_rtx = sp_reg_rtx;
27858 rtx cfa_restores = NULL_RTX;
27860 rtx cr_save_reg = NULL_RTX;
27861 machine_mode reg_mode = Pmode;
27862 int reg_size = TARGET_32BIT ? 4 : 8;
27863 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27864 int fp_reg_size = 8;
27866 unsigned ptr_regno;
27868 rs6000_stack_t *info = rs6000_stack_info ();
27870 if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return)
27871 epilogue_type = EPILOGUE_TYPE_EH_RETURN;
27873 int strategy = info->savres_strategy;
27874 bool using_load_multiple = !!(strategy & REST_MULTIPLE);
27875 bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS);
27876 bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS);
27877 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
27879 restoring_GPRs_inline = true;
27880 restoring_FPRs_inline = true;
27883 bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27884 || rs6000_tune == PROCESSOR_PPC603
27885 || rs6000_tune == PROCESSOR_PPC750
27888 /* Restore via the backchain when we have a large frame, since this
27889 is more efficient than an addis, addi pair. The second condition
27890 here will not trigger at the moment; We don't actually need a
27891 frame pointer for alloca, but the generic parts of the compiler
27892 give us one anyway. */
27893 bool use_backchain_to_restore_sp
27894 = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767
27895 || (cfun->calls_alloca && !frame_pointer_needed));
27897 bool restore_lr = (info->lr_save_p
27898 && (restoring_FPRs_inline
27899 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27900 && (restoring_GPRs_inline
27901 || info->first_fp_reg_save < 64)
27902 && !cfun->machine->lr_is_wrapped_separately);
27905 if (WORLD_SAVE_P (info))
27907 gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL);
27909 /* eh_rest_world_r10 will return to the location saved in the LR
27910 stack slot (which is not likely to be our caller.)
27911 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27912 rest_world is similar, except any R10 parameter is ignored.
27913 The exception-handling stuff that was here in 2.95 is no
27914 longer necessary. */
27918 + 32 - info->first_gp_reg_save
27919 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27920 + 63 + 1 - info->first_fp_reg_save);
27923 switch (epilogue_type)
27925 case EPILOGUE_TYPE_NORMAL:
27926 rname = ggc_strdup ("*rest_world");
27929 case EPILOGUE_TYPE_EH_RETURN:
27930 rname = ggc_strdup ("*eh_rest_world_r10");
27934 gcc_unreachable ();
27938 RTVEC_ELT (p, j++) = ret_rtx;
27940 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname));
27941 /* The instruction pattern requires a clobber here;
27942 it is shared with the restVEC helper. */
27943 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11);
27946 /* CR register traditionally saved as CR2. */
27947 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27949 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27950 if (flag_shrink_wrap)
27952 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27953 gen_rtx_REG (Pmode, LR_REGNO),
27955 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27960 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27962 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27964 = gen_frame_load (reg,
27965 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27966 if (flag_shrink_wrap
27967 && save_reg_p (info->first_gp_reg_save + i))
27968 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27970 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27972 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27974 = gen_frame_load (reg,
27975 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27976 if (flag_shrink_wrap
27977 && save_reg_p (info->first_altivec_reg_save + i))
27978 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27980 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27982 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27983 info->first_fp_reg_save + i);
27985 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27986 if (flag_shrink_wrap
27987 && save_reg_p (info->first_fp_reg_save + i))
27988 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27990 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0);
27991 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12);
27992 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7);
27993 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8);
27995 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27996 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27998 if (flag_shrink_wrap)
28000 REG_NOTES (insn) = cfa_restores;
28001 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28002 RTX_FRAME_RELATED_P (insn) = 1;
28007 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28009 frame_off = info->total_size;
28011 /* Restore AltiVec registers if we must do so before adjusting the
28013 if (info->altivec_size != 0
28014 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28015 || (DEFAULT_ABI != ABI_V4
28016 && offset_below_red_zone_p (info->altivec_save_offset))))
28019 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28021 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28022 if (use_backchain_to_restore_sp)
28024 int frame_regno = 11;
28026 if ((strategy & REST_INLINE_VRS) == 0)
28028 /* Of r11 and r12, select the one not clobbered by an
28029 out-of-line restore function for the frame register. */
28030 frame_regno = 11 + 12 - scratch_regno;
28032 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28033 emit_move_insn (frame_reg_rtx,
28034 gen_rtx_MEM (Pmode, sp_reg_rtx));
28037 else if (frame_pointer_needed)
28038 frame_reg_rtx = hard_frame_pointer_rtx;
28040 if ((strategy & REST_INLINE_VRS) == 0)
28042 int end_save = info->altivec_save_offset + info->altivec_size;
28044 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28045 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28047 if (end_save + frame_off != 0)
28049 rtx offset = GEN_INT (end_save + frame_off);
28051 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28054 emit_move_insn (ptr_reg, frame_reg_rtx);
28056 ptr_off = -end_save;
28057 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28058 info->altivec_save_offset + ptr_off,
28059 0, V4SImode, SAVRES_VR);
28063 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28064 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28066 rtx addr, areg, mem, insn;
28067 rtx reg = gen_rtx_REG (V4SImode, i);
28068 HOST_WIDE_INT offset
28069 = (info->altivec_save_offset + frame_off
28070 + 16 * (i - info->first_altivec_reg_save));
28072 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28074 mem = gen_frame_mem (V4SImode,
28075 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28076 GEN_INT (offset)));
28077 insn = gen_rtx_SET (reg, mem);
28081 areg = gen_rtx_REG (Pmode, 0);
28082 emit_move_insn (areg, GEN_INT (offset));
28084 /* AltiVec addressing mode is [reg+reg]. */
28085 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28086 mem = gen_frame_mem (V4SImode, addr);
28088 /* Rather than emitting a generic move, force use of the
28089 lvx instruction, which we always want. In particular we
28090 don't want lxvd2x/xxpermdi for little endian. */
28091 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28094 (void) emit_insn (insn);
28098 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28099 if (((strategy & REST_INLINE_VRS) == 0
28100 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28101 && (flag_shrink_wrap
28102 || (offset_below_red_zone_p
28103 (info->altivec_save_offset
28104 + 16 * (i - info->first_altivec_reg_save))))
28107 rtx reg = gen_rtx_REG (V4SImode, i);
28108 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28112 /* Restore VRSAVE if we must do so before adjusting the stack. */
28113 if (info->vrsave_size != 0
28114 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28115 || (DEFAULT_ABI != ABI_V4
28116 && offset_below_red_zone_p (info->vrsave_save_offset))))
28120 if (frame_reg_rtx == sp_reg_rtx)
28122 if (use_backchain_to_restore_sp)
28124 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28125 emit_move_insn (frame_reg_rtx,
28126 gen_rtx_MEM (Pmode, sp_reg_rtx));
28129 else if (frame_pointer_needed)
28130 frame_reg_rtx = hard_frame_pointer_rtx;
28133 reg = gen_rtx_REG (SImode, 12);
28134 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28135 info->vrsave_save_offset + frame_off));
28137 emit_insn (generate_set_vrsave (reg, info, 1));
28141 /* If we have a large stack frame, restore the old stack pointer
28142 using the backchain. */
28143 if (use_backchain_to_restore_sp)
28145 if (frame_reg_rtx == sp_reg_rtx)
28147 /* Under V.4, don't reset the stack pointer until after we're done
28148 loading the saved registers. */
28149 if (DEFAULT_ABI == ABI_V4)
28150 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28152 insn = emit_move_insn (frame_reg_rtx,
28153 gen_rtx_MEM (Pmode, sp_reg_rtx));
28156 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28157 && DEFAULT_ABI == ABI_V4)
28158 /* frame_reg_rtx has been set up by the altivec restore. */
28162 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28163 frame_reg_rtx = sp_reg_rtx;
28166 /* If we have a frame pointer, we can restore the old stack pointer
28168 else if (frame_pointer_needed)
28170 frame_reg_rtx = sp_reg_rtx;
28171 if (DEFAULT_ABI == ABI_V4)
28172 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28173 /* Prevent reordering memory accesses against stack pointer restore. */
28174 else if (cfun->calls_alloca
28175 || offset_below_red_zone_p (-info->total_size))
28176 rs6000_emit_stack_tie (frame_reg_rtx, true);
28178 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28179 GEN_INT (info->total_size)));
28182 else if (info->push_p
28183 && DEFAULT_ABI != ABI_V4
28184 && epilogue_type != EPILOGUE_TYPE_EH_RETURN)
28186 /* Prevent reordering memory accesses against stack pointer restore. */
28187 if (cfun->calls_alloca
28188 || offset_below_red_zone_p (-info->total_size))
28189 rs6000_emit_stack_tie (frame_reg_rtx, false);
28190 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28191 GEN_INT (info->total_size)));
28194 if (insn && frame_reg_rtx == sp_reg_rtx)
28198 REG_NOTES (insn) = cfa_restores;
28199 cfa_restores = NULL_RTX;
28201 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28202 RTX_FRAME_RELATED_P (insn) = 1;
28205 /* Restore AltiVec registers if we have not done so already. */
28206 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28207 && info->altivec_size != 0
28208 && (DEFAULT_ABI == ABI_V4
28209 || !offset_below_red_zone_p (info->altivec_save_offset)))
28213 if ((strategy & REST_INLINE_VRS) == 0)
28215 int end_save = info->altivec_save_offset + info->altivec_size;
28217 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28218 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28219 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28221 if (end_save + frame_off != 0)
28223 rtx offset = GEN_INT (end_save + frame_off);
28225 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28228 emit_move_insn (ptr_reg, frame_reg_rtx);
28230 ptr_off = -end_save;
28231 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28232 info->altivec_save_offset + ptr_off,
28233 0, V4SImode, SAVRES_VR);
28234 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28236 /* Frame reg was clobbered by out-of-line save. Restore it
28237 from ptr_reg, and if we are calling out-of-line gpr or
28238 fpr restore set up the correct pointer and offset. */
28239 unsigned newptr_regno = 1;
28240 if (!restoring_GPRs_inline)
28242 bool lr = info->gp_save_offset + info->gp_size == 0;
28243 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28244 newptr_regno = ptr_regno_for_savres (sel);
28245 end_save = info->gp_save_offset + info->gp_size;
28247 else if (!restoring_FPRs_inline)
28249 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28250 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28251 newptr_regno = ptr_regno_for_savres (sel);
28252 end_save = info->fp_save_offset + info->fp_size;
28255 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28256 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28258 if (end_save + ptr_off != 0)
28260 rtx offset = GEN_INT (end_save + ptr_off);
28262 frame_off = -end_save;
28264 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28267 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28272 frame_off = ptr_off;
28273 emit_move_insn (frame_reg_rtx, ptr_reg);
28279 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28280 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28282 rtx addr, areg, mem, insn;
28283 rtx reg = gen_rtx_REG (V4SImode, i);
28284 HOST_WIDE_INT offset
28285 = (info->altivec_save_offset + frame_off
28286 + 16 * (i - info->first_altivec_reg_save));
28288 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28290 mem = gen_frame_mem (V4SImode,
28291 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28292 GEN_INT (offset)));
28293 insn = gen_rtx_SET (reg, mem);
28297 areg = gen_rtx_REG (Pmode, 0);
28298 emit_move_insn (areg, GEN_INT (offset));
28300 /* AltiVec addressing mode is [reg+reg]. */
28301 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28302 mem = gen_frame_mem (V4SImode, addr);
28304 /* Rather than emitting a generic move, force use of the
28305 lvx instruction, which we always want. In particular we
28306 don't want lxvd2x/xxpermdi for little endian. */
28307 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28310 (void) emit_insn (insn);
28314 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28315 if (((strategy & REST_INLINE_VRS) == 0
28316 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28317 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28320 rtx reg = gen_rtx_REG (V4SImode, i);
28321 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28325 /* Restore VRSAVE if we have not done so already. */
28326 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28327 && info->vrsave_size != 0
28328 && (DEFAULT_ABI == ABI_V4
28329 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28333 reg = gen_rtx_REG (SImode, 12);
28334 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28335 info->vrsave_save_offset + frame_off));
28337 emit_insn (generate_set_vrsave (reg, info, 1));
28340 /* If we exit by an out-of-line restore function on ABI_V4 then that
28341 function will deallocate the stack, so we don't need to worry
28342 about the unwinder restoring cr from an invalid stack frame
28344 bool exit_func = (!restoring_FPRs_inline
28345 || (!restoring_GPRs_inline
28346 && info->first_fp_reg_save == 64));
28348 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28349 *separate* slots if the routine calls __builtin_eh_return, so
28350 that they can be independently restored by the unwinder. */
28351 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28353 int i, cr_off = info->ehcr_offset;
28355 for (i = 0; i < 8; i++)
28356 if (!call_used_regs[CR0_REGNO + i])
28358 rtx reg = gen_rtx_REG (SImode, 0);
28359 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28360 cr_off + frame_off));
28362 insn = emit_insn (gen_movsi_to_cr_one
28363 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28365 if (!exit_func && flag_shrink_wrap)
28367 add_reg_note (insn, REG_CFA_RESTORE,
28368 gen_rtx_REG (SImode, CR0_REGNO + i));
28370 RTX_FRAME_RELATED_P (insn) = 1;
28373 cr_off += reg_size;
28377 /* Get the old lr if we saved it. If we are restoring registers
28378 out-of-line, then the out-of-line routines can do this for us. */
28379 if (restore_lr && restoring_GPRs_inline)
28380 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28382 /* Get the old cr if we saved it. */
28383 if (info->cr_save_p)
28385 unsigned cr_save_regno = 12;
28387 if (!restoring_GPRs_inline)
28389 /* Ensure we don't use the register used by the out-of-line
28390 gpr register restore below. */
28391 bool lr = info->gp_save_offset + info->gp_size == 0;
28392 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28393 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28395 if (gpr_ptr_regno == 12)
28396 cr_save_regno = 11;
28397 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28399 else if (REGNO (frame_reg_rtx) == 12)
28400 cr_save_regno = 11;
28402 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28403 info->cr_save_offset + frame_off,
28407 /* Set LR here to try to overlap restores below. */
28408 if (restore_lr && restoring_GPRs_inline)
28409 restore_saved_lr (0, exit_func);
28411 /* Load exception handler data registers, if needed. */
28412 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28414 unsigned int i, regno;
28418 rtx reg = gen_rtx_REG (reg_mode, 2);
28419 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28420 frame_off + RS6000_TOC_SAVE_SLOT));
28427 regno = EH_RETURN_DATA_REGNO (i);
28428 if (regno == INVALID_REGNUM)
28431 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28432 info->ehrd_offset + frame_off
28433 + reg_size * (int) i);
28435 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28439 /* Restore GPRs. This is done as a PARALLEL if we are using
28440 the load-multiple instructions. */
28441 if (!restoring_GPRs_inline)
28443 /* We are jumping to an out-of-line function. */
28445 int end_save = info->gp_save_offset + info->gp_size;
28446 bool can_use_exit = end_save == 0;
28447 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28450 /* Emit stack reset code if we need it. */
28451 ptr_regno = ptr_regno_for_savres (sel);
28452 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28454 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28455 else if (end_save + frame_off != 0)
28456 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28457 GEN_INT (end_save + frame_off)));
28458 else if (REGNO (frame_reg_rtx) != ptr_regno)
28459 emit_move_insn (ptr_reg, frame_reg_rtx);
28460 if (REGNO (frame_reg_rtx) == ptr_regno)
28461 frame_off = -end_save;
28463 if (can_use_exit && info->cr_save_p)
28464 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28466 ptr_off = -end_save;
28467 rs6000_emit_savres_rtx (info, ptr_reg,
28468 info->gp_save_offset + ptr_off,
28469 info->lr_save_offset + ptr_off,
28472 else if (using_load_multiple)
28475 p = rtvec_alloc (32 - info->first_gp_reg_save);
28476 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28478 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28480 info->gp_save_offset + frame_off + reg_size * i);
28481 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28485 int offset = info->gp_save_offset + frame_off;
28486 for (i = info->first_gp_reg_save; i < 32; i++)
28489 && !cfun->machine->gpr_is_wrapped_separately[i])
28491 rtx reg = gen_rtx_REG (reg_mode, i);
28492 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28495 offset += reg_size;
28499 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28501 /* If the frame pointer was used then we can't delay emitting
28502 a REG_CFA_DEF_CFA note. This must happen on the insn that
28503 restores the frame pointer, r31. We may have already emitted
28504 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28505 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28506 be harmless if emitted. */
28507 if (frame_pointer_needed)
28509 insn = get_last_insn ();
28510 add_reg_note (insn, REG_CFA_DEF_CFA,
28511 plus_constant (Pmode, frame_reg_rtx, frame_off));
28512 RTX_FRAME_RELATED_P (insn) = 1;
28515 /* Set up cfa_restores. We always need these when
28516 shrink-wrapping. If not shrink-wrapping then we only need
28517 the cfa_restore when the stack location is no longer valid.
28518 The cfa_restores must be emitted on or before the insn that
28519 invalidates the stack, and of course must not be emitted
28520 before the insn that actually does the restore. The latter
28521 is why it is a bad idea to emit the cfa_restores as a group
28522 on the last instruction here that actually does a restore:
28523 That insn may be reordered with respect to others doing
28525 if (flag_shrink_wrap
28526 && !restoring_GPRs_inline
28527 && info->first_fp_reg_save == 64)
28528 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28530 for (i = info->first_gp_reg_save; i < 32; i++)
28532 && !cfun->machine->gpr_is_wrapped_separately[i])
28534 rtx reg = gen_rtx_REG (reg_mode, i);
28535 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28539 if (!restoring_GPRs_inline
28540 && info->first_fp_reg_save == 64)
28542 /* We are jumping to an out-of-line function. */
28544 emit_cfa_restores (cfa_restores);
28548 if (restore_lr && !restoring_GPRs_inline)
28550 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28551 restore_saved_lr (0, exit_func);
28554 /* Restore fpr's if we need to do it without calling a function. */
28555 if (restoring_FPRs_inline)
28557 int offset = info->fp_save_offset + frame_off;
28558 for (i = info->first_fp_reg_save; i < 64; i++)
28561 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28563 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28564 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28565 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28566 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28570 offset += fp_reg_size;
28574 /* If we saved cr, restore it here. Just those that were used. */
28575 if (info->cr_save_p)
28576 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28578 /* If this is V.4, unwind the stack pointer after all of the loads
28579 have been done, or set up r11 if we are restoring fp out of line. */
28581 if (!restoring_FPRs_inline)
28583 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28584 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28585 ptr_regno = ptr_regno_for_savres (sel);
28588 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28589 if (REGNO (frame_reg_rtx) == ptr_regno)
28592 if (insn && restoring_FPRs_inline)
28596 REG_NOTES (insn) = cfa_restores;
28597 cfa_restores = NULL_RTX;
28599 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28600 RTX_FRAME_RELATED_P (insn) = 1;
28603 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28605 rtx sa = EH_RETURN_STACKADJ_RTX;
28606 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28609 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline)
28613 /* We can't hang the cfa_restores off a simple return,
28614 since the shrink-wrap code sometimes uses an existing
28615 return. This means there might be a path from
28616 pre-prologue code to this return, and dwarf2cfi code
28617 wants the eh_frame unwinder state to be the same on
28618 all paths to any point. So we need to emit the
28619 cfa_restores before the return. For -m64 we really
28620 don't need epilogue cfa_restores at all, except for
28621 this irritating dwarf2cfi with shrink-wrap
28622 requirement; The stack red-zone means eh_frame info
28623 from the prologue telling the unwinder to restore
28624 from the stack is perfectly good right to the end of
28626 emit_insn (gen_blockage ());
28627 emit_cfa_restores (cfa_restores);
28628 cfa_restores = NULL_RTX;
28631 emit_jump_insn (targetm.gen_simple_return ());
28634 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline)
28636 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28637 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28639 RTVEC_ELT (p, elt++) = ret_rtx;
28641 RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
28643 /* We have to restore more than two FP registers, so branch to the
28644 restore function. It will return to our caller. */
28649 if (flag_shrink_wrap)
28650 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28652 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28653 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28654 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28655 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28657 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28659 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28661 RTVEC_ELT (p, elt++)
28662 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28663 if (flag_shrink_wrap
28664 && save_reg_p (info->first_fp_reg_save + i))
28665 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28668 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28673 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28674 /* Ensure the cfa_restores are hung off an insn that won't
28675 be reordered above other restores. */
28676 emit_insn (gen_blockage ());
28678 emit_cfa_restores (cfa_restores);
28682 /* Write function epilogue. */
28685 rs6000_output_function_epilogue (FILE *file)
28688 macho_branch_islands ();
28691 rtx_insn *insn = get_last_insn ();
28692 rtx_insn *deleted_debug_label = NULL;
28694 /* Mach-O doesn't support labels at the end of objects, so if
28695 it looks like we might want one, take special action.
28697 First, collect any sequence of deleted debug labels. */
28700 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28702 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28703 notes only, instead set their CODE_LABEL_NUMBER to -1,
28704 otherwise there would be code generation differences
28705 in between -g and -g0. */
28706 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28707 deleted_debug_label = insn;
28708 insn = PREV_INSN (insn);
28711 /* Second, if we have:
28714 then this needs to be detected, so skip past the barrier. */
28716 if (insn && BARRIER_P (insn))
28717 insn = PREV_INSN (insn);
28719 /* Up to now we've only seen notes or barriers. */
28724 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28725 /* Trailing label: <barrier>. */
28726 fputs ("\tnop\n", file);
28729 /* Lastly, see if we have a completely empty function body. */
28730 while (insn && ! INSN_P (insn))
28731 insn = PREV_INSN (insn);
28732 /* If we don't find any insns, we've got an empty function body;
28733 I.e. completely empty - without a return or branch. This is
28734 taken as the case where a function body has been removed
28735 because it contains an inline __builtin_unreachable(). GCC
28736 states that reaching __builtin_unreachable() means UB so we're
28737 not obliged to do anything special; however, we want
28738 non-zero-sized function bodies. To meet this, and help the
28739 user out, let's trap the case. */
28741 fputs ("\ttrap\n", file);
28744 else if (deleted_debug_label)
28745 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28746 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28747 CODE_LABEL_NUMBER (insn) = -1;
28751 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28754 We don't output a traceback table if -finhibit-size-directive was
28755 used. The documentation for -finhibit-size-directive reads
28756 ``don't output a @code{.size} assembler directive, or anything
28757 else that would cause trouble if the function is split in the
28758 middle, and the two halves are placed at locations far apart in
28759 memory.'' The traceback table has this property, since it
28760 includes the offset from the start of the function to the
28761 traceback table itself.
28763 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28764 different traceback table. */
28765 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28766 && ! flag_inhibit_size_directive
28767 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28769 const char *fname = NULL;
28770 const char *language_string = lang_hooks.name;
28771 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28773 int optional_tbtab;
28774 rs6000_stack_t *info = rs6000_stack_info ();
28776 if (rs6000_traceback == traceback_full)
28777 optional_tbtab = 1;
28778 else if (rs6000_traceback == traceback_part)
28779 optional_tbtab = 0;
28781 optional_tbtab = !optimize_size && !TARGET_ELF;
28783 if (optional_tbtab)
28785 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28786 while (*fname == '.') /* V.4 encodes . in the name */
28789 /* Need label immediately before tbtab, so we can compute
28790 its offset from the function start. */
28791 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28792 ASM_OUTPUT_LABEL (file, fname);
28795 /* The .tbtab pseudo-op can only be used for the first eight
28796 expressions, since it can't handle the possibly variable
28797 length fields that follow. However, if you omit the optional
28798 fields, the assembler outputs zeros for all optional fields
28799 anyways, giving each variable length field is minimum length
28800 (as defined in sys/debug.h). Thus we cannot use the .tbtab
28801 pseudo-op at all. */
28803 /* An all-zero word flags the start of the tbtab, for debuggers
28804 that have to find it by searching forward from the entry
28805 point or from the current pc. */
28806 fputs ("\t.long 0\n", file);
28808 /* Tbtab format type. Use format type 0. */
28809 fputs ("\t.byte 0,", file);
28811 /* Language type. Unfortunately, there does not seem to be any
28812 official way to discover the language being compiled, so we
28813 use language_string.
28814 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28815 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28816 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28817 numbers either, so for now use 0. */
28819 || ! strcmp (language_string, "GNU GIMPLE")
28820 || ! strcmp (language_string, "GNU Go")
28821 || ! strcmp (language_string, "GNU D")
28822 || ! strcmp (language_string, "libgccjit"))
28824 else if (! strcmp (language_string, "GNU F77")
28825 || lang_GNU_Fortran ())
28827 else if (! strcmp (language_string, "GNU Ada"))
28829 else if (lang_GNU_CXX ()
28830 || ! strcmp (language_string, "GNU Objective-C++"))
28832 else if (! strcmp (language_string, "GNU Java"))
28834 else if (! strcmp (language_string, "GNU Objective-C"))
28837 gcc_unreachable ();
28838 fprintf (file, "%d,", i);
28840 /* 8 single bit fields: global linkage (not set for C extern linkage,
28841 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28842 from start of procedure stored in tbtab, internal function, function
28843 has controlled storage, function has no toc, function uses fp,
28844 function logs/aborts fp operations. */
28845 /* Assume that fp operations are used if any fp reg must be saved. */
28846 fprintf (file, "%d,",
28847 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28849 /* 6 bitfields: function is interrupt handler, name present in
28850 proc table, function calls alloca, on condition directives
28851 (controls stack walks, 3 bits), saves condition reg, saves
28853 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28854 set up as a frame pointer, even when there is no alloca call. */
28855 fprintf (file, "%d,",
28856 ((optional_tbtab << 6)
28857 | ((optional_tbtab & frame_pointer_needed) << 5)
28858 | (info->cr_save_p << 1)
28859 | (info->lr_save_p)));
28861 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28863 fprintf (file, "%d,",
28864 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28866 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28867 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28869 if (optional_tbtab)
28871 /* Compute the parameter info from the function decl argument
28874 int next_parm_info_bit = 31;
28876 for (decl = DECL_ARGUMENTS (current_function_decl);
28877 decl; decl = DECL_CHAIN (decl))
28879 rtx parameter = DECL_INCOMING_RTL (decl);
28880 machine_mode mode = GET_MODE (parameter);
28882 if (REG_P (parameter))
28884 if (SCALAR_FLOAT_MODE_P (mode))
28907 gcc_unreachable ();
28910 /* If only one bit will fit, don't or in this entry. */
28911 if (next_parm_info_bit > 0)
28912 parm_info |= (bits << (next_parm_info_bit - 1));
28913 next_parm_info_bit -= 2;
28917 fixed_parms += ((GET_MODE_SIZE (mode)
28918 + (UNITS_PER_WORD - 1))
28920 next_parm_info_bit -= 1;
28926 /* Number of fixed point parameters. */
28927 /* This is actually the number of words of fixed point parameters; thus
28928 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28929 fprintf (file, "%d,", fixed_parms);
28931 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28933 /* This is actually the number of fp registers that hold parameters;
28934 and thus the maximum value is 13. */
28935 /* Set parameters on stack bit if parameters are not in their original
28936 registers, regardless of whether they are on the stack? Xlc
28937 seems to set the bit when not optimizing. */
28938 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28940 if (optional_tbtab)
28942 /* Optional fields follow. Some are variable length. */
28944 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28945 float, 11 double float. */
28946 /* There is an entry for each parameter in a register, in the order
28947 that they occur in the parameter list. Any intervening arguments
28948 on the stack are ignored. If the list overflows a long (max
28949 possible length 34 bits) then completely leave off all elements
28951 /* Only emit this long if there was at least one parameter. */
28952 if (fixed_parms || float_parms)
28953 fprintf (file, "\t.long %d\n", parm_info);
28955 /* Offset from start of code to tb table. */
28956 fputs ("\t.long ", file);
28957 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28958 RS6000_OUTPUT_BASENAME (file, fname);
28960 rs6000_output_function_entry (file, fname);
28963 /* Interrupt handler mask. */
28964 /* Omit this long, since we never set the interrupt handler bit
28967 /* Number of CTL (controlled storage) anchors. */
28968 /* Omit this long, since the has_ctl bit is never set above. */
28970 /* Displacement into stack of each CTL anchor. */
28971 /* Omit this list of longs, because there are no CTL anchors. */
28973 /* Length of function name. */
28976 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28978 /* Function name. */
28979 assemble_string (fname, strlen (fname));
28981 /* Register for alloca automatic storage; this is always reg 31.
28982 Only emit this if the alloca bit was set above. */
28983 if (frame_pointer_needed)
28984 fputs ("\t.byte 31\n", file);
28986 fputs ("\t.align 2\n", file);
28990 /* Arrange to define .LCTOC1 label, if not already done. */
28994 if (!toc_initialized)
28996 switch_to_section (toc_section);
28997 switch_to_section (current_function_section ());
29002 /* -fsplit-stack support. */
29004 /* A SYMBOL_REF for __morestack. */
29005 static GTY(()) rtx morestack_ref;
29008 gen_add3_const (rtx rt, rtx ra, long c)
29011 return gen_adddi3 (rt, ra, GEN_INT (c));
29013 return gen_addsi3 (rt, ra, GEN_INT (c));
29016 /* Emit -fsplit-stack prologue, which goes before the regular function
29017 prologue (at local entry point in the case of ELFv2). */
29020 rs6000_expand_split_stack_prologue (void)
29022 rs6000_stack_t *info = rs6000_stack_info ();
29023 unsigned HOST_WIDE_INT allocate;
29024 long alloc_hi, alloc_lo;
29025 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29028 gcc_assert (flag_split_stack && reload_completed);
29033 if (global_regs[29])
29035 error ("%qs uses register r29", "%<-fsplit-stack%>");
29036 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29037 "conflicts with %qD", global_regs_decl[29]);
29040 allocate = info->total_size;
29041 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29043 sorry ("Stack frame larger than 2G is not supported for "
29044 "%<-fsplit-stack%>");
29047 if (morestack_ref == NULL_RTX)
29049 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29050 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29051 | SYMBOL_FLAG_FUNCTION);
29054 r0 = gen_rtx_REG (Pmode, 0);
29055 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29056 r12 = gen_rtx_REG (Pmode, 12);
29057 emit_insn (gen_load_split_stack_limit (r0));
29058 /* Always emit two insns here to calculate the requested stack,
29059 so that the linker can edit them when adjusting size for calling
29060 non-split-stack code. */
29061 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29062 alloc_lo = -allocate - alloc_hi;
29065 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29067 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29069 emit_insn (gen_nop ());
29073 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29074 emit_insn (gen_nop ());
29077 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29078 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29079 ok_label = gen_label_rtx ();
29080 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29081 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29082 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29084 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29085 JUMP_LABEL (insn) = ok_label;
29086 /* Mark the jump as very likely to be taken. */
29087 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29089 lr = gen_rtx_REG (Pmode, LR_REGNO);
29090 insn = emit_move_insn (r0, lr);
29091 RTX_FRAME_RELATED_P (insn) = 1;
29092 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29093 RTX_FRAME_RELATED_P (insn) = 1;
29095 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29096 const0_rtx, const0_rtx));
29097 call_fusage = NULL_RTX;
29098 use_reg (&call_fusage, r12);
29099 /* Say the call uses r0, even though it doesn't, to stop regrename
29100 from twiddling with the insns saving lr, trashing args for cfun.
29101 The insns restoring lr are similarly protected by making
29102 split_stack_return use r0. */
29103 use_reg (&call_fusage, r0);
29104 add_function_usage_to (insn, call_fusage);
29105 /* Indicate that this function can't jump to non-local gotos. */
29106 make_reg_eh_region_note_nothrow_nononlocal (insn);
29107 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29108 insn = emit_move_insn (lr, r0);
29109 add_reg_note (insn, REG_CFA_RESTORE, lr);
29110 RTX_FRAME_RELATED_P (insn) = 1;
29111 emit_insn (gen_split_stack_return ());
29113 emit_label (ok_label);
29114 LABEL_NUSES (ok_label) = 1;
29117 /* Return the internal arg pointer used for function incoming
29118 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29119 to copy it to a pseudo in order for it to be preserved over calls
29120 and suchlike. We'd really like to use a pseudo here for the
29121 internal arg pointer but data-flow analysis is not prepared to
29122 accept pseudos as live at the beginning of a function. */
29125 rs6000_internal_arg_pointer (void)
29127 if (flag_split_stack
29128 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29132 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29136 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29137 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29139 /* Put the pseudo initialization right after the note at the
29140 beginning of the function. */
29141 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29142 gen_rtx_REG (Pmode, 12));
29143 push_topmost_sequence ();
29144 emit_insn_after (pat, get_insns ());
29145 pop_topmost_sequence ();
29147 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29148 FIRST_PARM_OFFSET (current_function_decl));
29149 return copy_to_reg (ret);
29151 return virtual_incoming_args_rtx;
29154 /* We may have to tell the dataflow pass that the split stack prologue
29155 is initializing a register. */
29158 rs6000_live_on_entry (bitmap regs)
29160 if (flag_split_stack)
29161 bitmap_set_bit (regs, 12);
29164 /* Emit -fsplit-stack dynamic stack allocation space check. */
29167 rs6000_split_stack_space_check (rtx size, rtx label)
29169 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29170 rtx limit = gen_reg_rtx (Pmode);
29171 rtx requested = gen_reg_rtx (Pmode);
29172 rtx cmp = gen_reg_rtx (CCUNSmode);
29175 emit_insn (gen_load_split_stack_limit (limit));
29176 if (CONST_INT_P (size))
29177 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29180 size = force_reg (Pmode, size);
29181 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29183 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29184 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29185 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29186 gen_rtx_LABEL_REF (VOIDmode, label),
29188 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29189 JUMP_LABEL (jump) = label;
29192 /* A C compound statement that outputs the assembler code for a thunk
29193 function, used to implement C++ virtual function calls with
29194 multiple inheritance. The thunk acts as a wrapper around a virtual
29195 function, adjusting the implicit object parameter before handing
29196 control off to the real function.
29198 First, emit code to add the integer DELTA to the location that
29199 contains the incoming first argument. Assume that this argument
29200 contains a pointer, and is the one used to pass the `this' pointer
29201 in C++. This is the incoming argument *before* the function
29202 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29203 values of all other incoming arguments.
29205 After the addition, emit code to jump to FUNCTION, which is a
29206 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29207 not touch the return address. Hence returning from FUNCTION will
29208 return to whoever called the current `thunk'.
29210 The effect must be as if FUNCTION had been called directly with the
29211 adjusted first argument. This macro is responsible for emitting
29212 all of the code for a thunk function; output_function_prologue()
29213 and output_function_epilogue() are not invoked.
29215 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29216 been extracted from it.) It might possibly be useful on some
29217 targets, but probably not.
29219 If you do not define this macro, the target-independent code in the
29220 C++ frontend will generate a less efficient heavyweight thunk that
29221 calls FUNCTION instead of jumping to it. The generic approach does
29222 not support varargs. */
29225 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29226 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29229 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
29230 rtx this_rtx, funexp;
29233 reload_completed = 1;
29234 epilogue_completed = 1;
29236 /* Mark the end of the (empty) prologue. */
29237 emit_note (NOTE_INSN_PROLOGUE_END);
29239 /* Find the "this" pointer. If the function returns a structure,
29240 the structure return pointer is in r3. */
29241 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29242 this_rtx = gen_rtx_REG (Pmode, 4);
29244 this_rtx = gen_rtx_REG (Pmode, 3);
29246 /* Apply the constant offset, if required. */
29248 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29250 /* Apply the offset from the vtable, if required. */
29253 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29254 rtx tmp = gen_rtx_REG (Pmode, 12);
29256 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29257 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29259 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29260 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29264 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29266 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29268 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29271 /* Generate a tail call to the target function. */
29272 if (!TREE_USED (function))
29274 assemble_external (function);
29275 TREE_USED (function) = 1;
29277 funexp = XEXP (DECL_RTL (function), 0);
29278 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29281 if (MACHOPIC_INDIRECT)
29282 funexp = machopic_indirect_call_target (funexp);
29285 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29286 generate sibcall RTL explicitly. */
29287 insn = emit_call_insn (
29288 gen_rtx_PARALLEL (VOIDmode,
29290 gen_rtx_CALL (VOIDmode,
29291 funexp, const0_rtx),
29292 gen_rtx_USE (VOIDmode, const0_rtx),
29293 simple_return_rtx)));
29294 SIBLING_CALL_P (insn) = 1;
29297 /* Run just enough of rest_of_compilation to get the insns emitted.
29298 There's not really enough bulk here to make other passes such as
29299 instruction scheduling worth while. Note that use_thunk calls
29300 assemble_start_function and assemble_end_function. */
29301 insn = get_insns ();
29302 shorten_branches (insn);
29303 assemble_start_function (thunk_fndecl, fnname);
29304 final_start_function (insn, file, 1);
29305 final (insn, file, 1);
29306 final_end_function ();
29307 assemble_end_function (thunk_fndecl, fnname);
29309 reload_completed = 0;
29310 epilogue_completed = 0;
29313 /* A quick summary of the various types of 'constant-pool tables'
29316 Target Flags Name One table per
29317 AIX (none) AIX TOC object file
29318 AIX -mfull-toc AIX TOC object file
29319 AIX -mminimal-toc AIX minimal TOC translation unit
29320 SVR4/EABI (none) SVR4 SDATA object file
29321 SVR4/EABI -fpic SVR4 pic object file
29322 SVR4/EABI -fPIC SVR4 PIC translation unit
29323 SVR4/EABI -mrelocatable EABI TOC function
29324 SVR4/EABI -maix AIX TOC object file
29325 SVR4/EABI -maix -mminimal-toc
29326 AIX minimal TOC translation unit
29328 Name Reg. Set by entries contains:
29329 made by addrs? fp? sum?
29331 AIX TOC 2 crt0 as Y option option
29332 AIX minimal TOC 30 prolog gcc Y Y option
29333 SVR4 SDATA 13 crt0 gcc N Y N
29334 SVR4 pic 30 prolog ld Y not yet N
29335 SVR4 PIC 30 prolog gcc Y option option
29336 EABI TOC 30 prolog gcc Y option option
29340 /* Hash functions for the hash table. */
29343 rs6000_hash_constant (rtx k)
29345 enum rtx_code code = GET_CODE (k);
29346 machine_mode mode = GET_MODE (k);
29347 unsigned result = (code << 3) ^ mode;
29348 const char *format;
29351 format = GET_RTX_FORMAT (code);
29352 flen = strlen (format);
29358 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29360 case CONST_WIDE_INT:
29363 flen = CONST_WIDE_INT_NUNITS (k);
29364 for (i = 0; i < flen; i++)
29365 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29370 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29380 for (; fidx < flen; fidx++)
29381 switch (format[fidx])
29386 const char *str = XSTR (k, fidx);
29387 len = strlen (str);
29388 result = result * 613 + len;
29389 for (i = 0; i < len; i++)
29390 result = result * 613 + (unsigned) str[i];
29395 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29399 result = result * 613 + (unsigned) XINT (k, fidx);
29402 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29403 result = result * 613 + (unsigned) XWINT (k, fidx);
29407 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29408 result = result * 613 + (unsigned) (XWINT (k, fidx)
29415 gcc_unreachable ();
29422 toc_hasher::hash (toc_hash_struct *thc)
29424 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29427 /* Compare H1 and H2 for equivalence. */
29430 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29435 if (h1->key_mode != h2->key_mode)
29438 return rtx_equal_p (r1, r2);
29441 /* These are the names given by the C++ front-end to vtables, and
29442 vtable-like objects. Ideally, this logic should not be here;
29443 instead, there should be some programmatic way of inquiring as
29444 to whether or not an object is a vtable. */
29446 #define VTABLE_NAME_P(NAME) \
29447 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29448 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29449 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29450 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29451 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29453 #ifdef NO_DOLLAR_IN_LABEL
29454 /* Return a GGC-allocated character string translating dollar signs in
29455 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29458 rs6000_xcoff_strip_dollar (const char *name)
29464 q = (const char *) strchr (name, '$');
29466 if (q == 0 || q == name)
29469 len = strlen (name);
29470 strip = XALLOCAVEC (char, len + 1);
29471 strcpy (strip, name);
29472 p = strip + (q - name);
29476 p = strchr (p + 1, '$');
29479 return ggc_alloc_string (strip, len);
29484 rs6000_output_symbol_ref (FILE *file, rtx x)
29486 const char *name = XSTR (x, 0);
29488 /* Currently C++ toc references to vtables can be emitted before it
29489 is decided whether the vtable is public or private. If this is
29490 the case, then the linker will eventually complain that there is
29491 a reference to an unknown section. Thus, for vtables only,
29492 we emit the TOC reference to reference the identifier and not the
29494 if (VTABLE_NAME_P (name))
29496 RS6000_OUTPUT_BASENAME (file, name);
29499 assemble_name (file, name);
29502 /* Output a TOC entry. We derive the entry name from what is being
29506 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29509 const char *name = buf;
29511 HOST_WIDE_INT offset = 0;
29513 gcc_assert (!TARGET_NO_TOC);
29515 /* When the linker won't eliminate them, don't output duplicate
29516 TOC entries (this happens on AIX if there is any kind of TOC,
29517 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29519 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29521 struct toc_hash_struct *h;
29523 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29524 time because GGC is not initialized at that point. */
29525 if (toc_hash_table == NULL)
29526 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29528 h = ggc_alloc<toc_hash_struct> ();
29530 h->key_mode = mode;
29531 h->labelno = labelno;
29533 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29534 if (*found == NULL)
29536 else /* This is indeed a duplicate.
29537 Set this label equal to that label. */
29539 fputs ("\t.set ", file);
29540 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29541 fprintf (file, "%d,", labelno);
29542 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29543 fprintf (file, "%d\n", ((*found)->labelno));
29546 if (TARGET_XCOFF && SYMBOL_REF_P (x)
29547 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29548 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29550 fputs ("\t.set ", file);
29551 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29552 fprintf (file, "%d,", labelno);
29553 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29554 fprintf (file, "%d\n", ((*found)->labelno));
29561 /* If we're going to put a double constant in the TOC, make sure it's
29562 aligned properly when strict alignment is on. */
29563 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29564 && STRICT_ALIGNMENT
29565 && GET_MODE_BITSIZE (mode) >= 64
29566 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29567 ASM_OUTPUT_ALIGN (file, 3);
29570 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29572 /* Handle FP constants specially. Note that if we have a minimal
29573 TOC, things we put here aren't actually in the TOC, so we can allow
29575 if (CONST_DOUBLE_P (x)
29576 && (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29577 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29581 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29582 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29584 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29588 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29589 fputs (DOUBLE_INT_ASM_OP, file);
29591 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29592 k[0] & 0xffffffff, k[1] & 0xffffffff,
29593 k[2] & 0xffffffff, k[3] & 0xffffffff);
29594 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29595 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29596 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29597 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29598 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29603 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29604 fputs ("\t.long ", file);
29606 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29607 k[0] & 0xffffffff, k[1] & 0xffffffff,
29608 k[2] & 0xffffffff, k[3] & 0xffffffff);
29609 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29610 k[0] & 0xffffffff, k[1] & 0xffffffff,
29611 k[2] & 0xffffffff, k[3] & 0xffffffff);
29615 else if (CONST_DOUBLE_P (x)
29616 && (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29620 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29621 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29623 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29627 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29628 fputs (DOUBLE_INT_ASM_OP, file);
29630 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29631 k[0] & 0xffffffff, k[1] & 0xffffffff);
29632 fprintf (file, "0x%lx%08lx\n",
29633 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29634 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29639 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29640 fputs ("\t.long ", file);
29642 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29643 k[0] & 0xffffffff, k[1] & 0xffffffff);
29644 fprintf (file, "0x%lx,0x%lx\n",
29645 k[0] & 0xffffffff, k[1] & 0xffffffff);
29649 else if (CONST_DOUBLE_P (x)
29650 && (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29654 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29655 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29657 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29661 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29662 fputs (DOUBLE_INT_ASM_OP, file);
29664 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29665 if (WORDS_BIG_ENDIAN)
29666 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29668 fprintf (file, "0x%lx\n", l & 0xffffffff);
29673 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29674 fputs ("\t.long ", file);
29676 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29677 fprintf (file, "0x%lx\n", l & 0xffffffff);
29681 else if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
29683 unsigned HOST_WIDE_INT low;
29684 HOST_WIDE_INT high;
29686 low = INTVAL (x) & 0xffffffff;
29687 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29689 /* TOC entries are always Pmode-sized, so when big-endian
29690 smaller integer constants in the TOC need to be padded.
29691 (This is still a win over putting the constants in
29692 a separate constant pool, because then we'd have
29693 to have both a TOC entry _and_ the actual constant.)
29695 For a 32-bit target, CONST_INT values are loaded and shifted
29696 entirely within `low' and can be stored in one TOC entry. */
29698 /* It would be easy to make this work, but it doesn't now. */
29699 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29701 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29704 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29705 high = (HOST_WIDE_INT) low >> 32;
29711 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29712 fputs (DOUBLE_INT_ASM_OP, file);
29714 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29715 (long) high & 0xffffffff, (long) low & 0xffffffff);
29716 fprintf (file, "0x%lx%08lx\n",
29717 (long) high & 0xffffffff, (long) low & 0xffffffff);
29722 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29724 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29725 fputs ("\t.long ", file);
29727 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29728 (long) high & 0xffffffff, (long) low & 0xffffffff);
29729 fprintf (file, "0x%lx,0x%lx\n",
29730 (long) high & 0xffffffff, (long) low & 0xffffffff);
29734 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29735 fputs ("\t.long ", file);
29737 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29738 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29744 if (GET_CODE (x) == CONST)
29746 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29747 && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
29749 base = XEXP (XEXP (x, 0), 0);
29750 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29753 switch (GET_CODE (base))
29756 name = XSTR (base, 0);
29760 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29761 CODE_LABEL_NUMBER (XEXP (base, 0)));
29765 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29769 gcc_unreachable ();
29772 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29773 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29776 fputs ("\t.tc ", file);
29777 RS6000_OUTPUT_BASENAME (file, name);
29780 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29782 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29784 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29785 after other TOC symbols, reducing overflow of small TOC access
29786 to [TC] symbols. */
29787 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29788 ? "[TE]," : "[TC],", file);
29791 /* Currently C++ toc references to vtables can be emitted before it
29792 is decided whether the vtable is public or private. If this is
29793 the case, then the linker will eventually complain that there is
29794 a TOC reference to an unknown section. Thus, for vtables only,
29795 we emit the TOC reference to reference the symbol and not the
29797 if (VTABLE_NAME_P (name))
29799 RS6000_OUTPUT_BASENAME (file, name);
29801 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29802 else if (offset > 0)
29803 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29806 output_addr_const (file, x);
29809 if (TARGET_XCOFF && SYMBOL_REF_P (base))
29811 switch (SYMBOL_REF_TLS_MODEL (base))
29815 case TLS_MODEL_LOCAL_EXEC:
29816 fputs ("@le", file);
29818 case TLS_MODEL_INITIAL_EXEC:
29819 fputs ("@ie", file);
29821 /* Use global-dynamic for local-dynamic. */
29822 case TLS_MODEL_GLOBAL_DYNAMIC:
29823 case TLS_MODEL_LOCAL_DYNAMIC:
29825 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29826 fputs ("\t.tc .", file);
29827 RS6000_OUTPUT_BASENAME (file, name);
29828 fputs ("[TC],", file);
29829 output_addr_const (file, x);
29830 fputs ("@m", file);
29833 gcc_unreachable ();
29841 /* Output an assembler pseudo-op to write an ASCII string of N characters
29842 starting at P to FILE.
29844 On the RS/6000, we have to do this using the .byte operation and
29845 write out special characters outside the quoted string.
29846 Also, the assembler is broken; very long strings are truncated,
29847 so we must artificially break them up early. */
29850 output_ascii (FILE *file, const char *p, int n)
29853 int i, count_string;
29854 const char *for_string = "\t.byte \"";
29855 const char *for_decimal = "\t.byte ";
29856 const char *to_close = NULL;
29859 for (i = 0; i < n; i++)
29862 if (c >= ' ' && c < 0177)
29865 fputs (for_string, file);
29868 /* Write two quotes to get one. */
29876 for_decimal = "\"\n\t.byte ";
29880 if (count_string >= 512)
29882 fputs (to_close, file);
29884 for_string = "\t.byte \"";
29885 for_decimal = "\t.byte ";
29893 fputs (for_decimal, file);
29894 fprintf (file, "%d", c);
29896 for_string = "\n\t.byte \"";
29897 for_decimal = ", ";
29903 /* Now close the string if we have written one. Then end the line. */
29905 fputs (to_close, file);
29908 /* Generate a unique section name for FILENAME for a section type
29909 represented by SECTION_DESC. Output goes into BUF.
29911 SECTION_DESC can be any string, as long as it is different for each
29912 possible section type.
29914 We name the section in the same manner as xlc. The name begins with an
29915 underscore followed by the filename (after stripping any leading directory
29916 names) with the last period replaced by the string SECTION_DESC. If
29917 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29921 rs6000_gen_section_name (char **buf, const char *filename,
29922 const char *section_desc)
29924 const char *q, *after_last_slash, *last_period = 0;
29928 after_last_slash = filename;
29929 for (q = filename; *q; q++)
29932 after_last_slash = q + 1;
29933 else if (*q == '.')
29937 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29938 *buf = (char *) xmalloc (len);
29943 for (q = after_last_slash; *q; q++)
29945 if (q == last_period)
29947 strcpy (p, section_desc);
29948 p += strlen (section_desc);
29952 else if (ISALNUM (*q))
29956 if (last_period == 0)
29957 strcpy (p, section_desc);
29962 /* Emit profile function. */
29965 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29967 /* Non-standard profiling for kernels, which just saves LR then calls
29968 _mcount without worrying about arg saves. The idea is to change
29969 the function prologue as little as possible as it isn't easy to
29970 account for arg save/restore code added just for _mcount. */
29971 if (TARGET_PROFILE_KERNEL)
29974 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29976 #ifndef NO_PROFILE_COUNTERS
29977 # define NO_PROFILE_COUNTERS 0
29979 if (NO_PROFILE_COUNTERS)
29980 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29981 LCT_NORMAL, VOIDmode);
29985 const char *label_name;
29988 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29989 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29990 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29992 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29993 LCT_NORMAL, VOIDmode, fun, Pmode);
29996 else if (DEFAULT_ABI == ABI_DARWIN)
29998 const char *mcount_name = RS6000_MCOUNT;
29999 int caller_addr_regno = LR_REGNO;
30001 /* Be conservative and always set this, at least for now. */
30002 crtl->uses_pic_offset_table = 1;
30005 /* For PIC code, set up a stub and collect the caller's address
30006 from r0, which is where the prologue puts it. */
30007 if (MACHOPIC_INDIRECT
30008 && crtl->uses_pic_offset_table)
30009 caller_addr_regno = 0;
30011 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30012 LCT_NORMAL, VOIDmode,
30013 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30017 /* Write function profiler code. */
30020 output_function_profiler (FILE *file, int labelno)
30024 switch (DEFAULT_ABI)
30027 gcc_unreachable ();
30032 warning (0, "no profiling of 64-bit code for this ABI");
30035 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30036 fprintf (file, "\tmflr %s\n", reg_names[0]);
30037 if (NO_PROFILE_COUNTERS)
30039 asm_fprintf (file, "\tstw %s,4(%s)\n",
30040 reg_names[0], reg_names[1]);
30042 else if (TARGET_SECURE_PLT && flag_pic)
30044 if (TARGET_LINK_STACK)
30047 get_ppc476_thunk_name (name);
30048 asm_fprintf (file, "\tbl %s\n", name);
30051 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30052 asm_fprintf (file, "\tstw %s,4(%s)\n",
30053 reg_names[0], reg_names[1]);
30054 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30055 asm_fprintf (file, "\taddis %s,%s,",
30056 reg_names[12], reg_names[12]);
30057 assemble_name (file, buf);
30058 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30059 assemble_name (file, buf);
30060 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30062 else if (flag_pic == 1)
30064 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30065 asm_fprintf (file, "\tstw %s,4(%s)\n",
30066 reg_names[0], reg_names[1]);
30067 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30068 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30069 assemble_name (file, buf);
30070 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30072 else if (flag_pic > 1)
30074 asm_fprintf (file, "\tstw %s,4(%s)\n",
30075 reg_names[0], reg_names[1]);
30076 /* Now, we need to get the address of the label. */
30077 if (TARGET_LINK_STACK)
30080 get_ppc476_thunk_name (name);
30081 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30082 assemble_name (file, buf);
30083 fputs ("-.\n1:", file);
30084 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30085 asm_fprintf (file, "\taddi %s,%s,4\n",
30086 reg_names[11], reg_names[11]);
30090 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30091 assemble_name (file, buf);
30092 fputs ("-.\n1:", file);
30093 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30095 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30096 reg_names[0], reg_names[11]);
30097 asm_fprintf (file, "\tadd %s,%s,%s\n",
30098 reg_names[0], reg_names[0], reg_names[11]);
30102 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30103 assemble_name (file, buf);
30104 fputs ("@ha\n", file);
30105 asm_fprintf (file, "\tstw %s,4(%s)\n",
30106 reg_names[0], reg_names[1]);
30107 asm_fprintf (file, "\tla %s,", reg_names[0]);
30108 assemble_name (file, buf);
30109 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30112 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30113 fprintf (file, "\tbl %s%s\n",
30114 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30120 /* Don't do anything, done in output_profile_hook (). */
30127 /* The following variable value is the last issued insn. */
30129 static rtx_insn *last_scheduled_insn;
30131 /* The following variable helps to balance issuing of load and
30132 store instructions */
30134 static int load_store_pendulum;
30136 /* The following variable helps pair divide insns during scheduling. */
30137 static int divide_cnt;
30138 /* The following variable helps pair and alternate vector and vector load
30139 insns during scheduling. */
30140 static int vec_pairing;
30143 /* Power4 load update and store update instructions are cracked into a
30144 load or store and an integer insn which are executed in the same cycle.
30145 Branches have their own dispatch slot which does not count against the
30146 GCC issue rate, but it changes the program flow so there are no other
30147 instructions to issue in this cycle. */
30150 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30152 last_scheduled_insn = insn;
30153 if (GET_CODE (PATTERN (insn)) == USE
30154 || GET_CODE (PATTERN (insn)) == CLOBBER)
30156 cached_can_issue_more = more;
30157 return cached_can_issue_more;
30160 if (insn_terminates_group_p (insn, current_group))
30162 cached_can_issue_more = 0;
30163 return cached_can_issue_more;
30166 /* If no reservation, but reach here */
30167 if (recog_memoized (insn) < 0)
30170 if (rs6000_sched_groups)
30172 if (is_microcoded_insn (insn))
30173 cached_can_issue_more = 0;
30174 else if (is_cracked_insn (insn))
30175 cached_can_issue_more = more > 2 ? more - 2 : 0;
30177 cached_can_issue_more = more - 1;
30179 return cached_can_issue_more;
30182 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30185 cached_can_issue_more = more - 1;
30186 return cached_can_issue_more;
30190 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30192 int r = rs6000_variable_issue_1 (insn, more);
30194 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30198 /* Adjust the cost of a scheduling dependency. Return the new cost of
30199 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30202 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30205 enum attr_type attr_type;
30207 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30214 /* Data dependency; DEP_INSN writes a register that INSN reads
30215 some cycles later. */
30217 /* Separate a load from a narrower, dependent store. */
30218 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
30219 || rs6000_tune == PROCESSOR_FUTURE)
30220 && GET_CODE (PATTERN (insn)) == SET
30221 && GET_CODE (PATTERN (dep_insn)) == SET
30222 && MEM_P (XEXP (PATTERN (insn), 1))
30223 && MEM_P (XEXP (PATTERN (dep_insn), 0))
30224 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30225 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30228 attr_type = get_attr_type (insn);
30233 /* Tell the first scheduling pass about the latency between
30234 a mtctr and bctr (and mtlr and br/blr). The first
30235 scheduling pass will not know about this latency since
30236 the mtctr instruction, which has the latency associated
30237 to it, will be generated by reload. */
30240 /* Leave some extra cycles between a compare and its
30241 dependent branch, to inhibit expensive mispredicts. */
30242 if ((rs6000_tune == PROCESSOR_PPC603
30243 || rs6000_tune == PROCESSOR_PPC604
30244 || rs6000_tune == PROCESSOR_PPC604e
30245 || rs6000_tune == PROCESSOR_PPC620
30246 || rs6000_tune == PROCESSOR_PPC630
30247 || rs6000_tune == PROCESSOR_PPC750
30248 || rs6000_tune == PROCESSOR_PPC7400
30249 || rs6000_tune == PROCESSOR_PPC7450
30250 || rs6000_tune == PROCESSOR_PPCE5500
30251 || rs6000_tune == PROCESSOR_PPCE6500
30252 || rs6000_tune == PROCESSOR_POWER4
30253 || rs6000_tune == PROCESSOR_POWER5
30254 || rs6000_tune == PROCESSOR_POWER7
30255 || rs6000_tune == PROCESSOR_POWER8
30256 || rs6000_tune == PROCESSOR_POWER9
30257 || rs6000_tune == PROCESSOR_FUTURE
30258 || rs6000_tune == PROCESSOR_CELL)
30259 && recog_memoized (dep_insn)
30260 && (INSN_CODE (dep_insn) >= 0))
30262 switch (get_attr_type (dep_insn))
30265 case TYPE_FPCOMPARE:
30266 case TYPE_CR_LOGICAL:
30270 if (get_attr_dot (dep_insn) == DOT_YES)
30275 if (get_attr_dot (dep_insn) == DOT_YES
30276 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30287 if ((rs6000_tune == PROCESSOR_POWER6)
30288 && recog_memoized (dep_insn)
30289 && (INSN_CODE (dep_insn) >= 0))
30292 if (GET_CODE (PATTERN (insn)) != SET)
30293 /* If this happens, we have to extend this to schedule
30294 optimally. Return default for now. */
30297 /* Adjust the cost for the case where the value written
30298 by a fixed point operation is used as the address
30299 gen value on a store. */
30300 switch (get_attr_type (dep_insn))
30305 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30306 return get_attr_sign_extend (dep_insn)
30307 == SIGN_EXTEND_YES ? 6 : 4;
30312 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30313 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30323 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30331 if (get_attr_update (dep_insn) == UPDATE_YES
30332 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30338 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30344 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30345 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30355 if ((rs6000_tune == PROCESSOR_POWER6)
30356 && recog_memoized (dep_insn)
30357 && (INSN_CODE (dep_insn) >= 0))
30360 /* Adjust the cost for the case where the value written
30361 by a fixed point instruction is used within the address
30362 gen portion of a subsequent load(u)(x) */
30363 switch (get_attr_type (dep_insn))
30368 if (set_to_load_agen (dep_insn, insn))
30369 return get_attr_sign_extend (dep_insn)
30370 == SIGN_EXTEND_YES ? 6 : 4;
30375 if (set_to_load_agen (dep_insn, insn))
30376 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30386 if (set_to_load_agen (dep_insn, insn))
30394 if (get_attr_update (dep_insn) == UPDATE_YES
30395 && set_to_load_agen (dep_insn, insn))
30401 if (set_to_load_agen (dep_insn, insn))
30407 if (set_to_load_agen (dep_insn, insn))
30408 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30418 if ((rs6000_tune == PROCESSOR_POWER6)
30419 && get_attr_update (insn) == UPDATE_NO
30420 && recog_memoized (dep_insn)
30421 && (INSN_CODE (dep_insn) >= 0)
30422 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30429 /* Fall out to return default cost. */
30433 case REG_DEP_OUTPUT:
30434 /* Output dependency; DEP_INSN writes a register that INSN writes some
30436 if ((rs6000_tune == PROCESSOR_POWER6)
30437 && recog_memoized (dep_insn)
30438 && (INSN_CODE (dep_insn) >= 0))
30440 attr_type = get_attr_type (insn);
30445 case TYPE_FPSIMPLE:
30446 if (get_attr_type (dep_insn) == TYPE_FP
30447 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30451 if (get_attr_update (insn) == UPDATE_NO
30452 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30459 /* Fall through, no cost for output dependency. */
30463 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30468 gcc_unreachable ();
30474 /* Debug version of rs6000_adjust_cost. */
30477 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30478 int cost, unsigned int dw)
30480 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30488 default: dep = "unknown depencency"; break;
30489 case REG_DEP_TRUE: dep = "data dependency"; break;
30490 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30491 case REG_DEP_ANTI: dep = "anti depencency"; break;
30495 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30496 "%s, insn:\n", ret, cost, dep);
30504 /* The function returns a true if INSN is microcoded.
30505 Return false otherwise. */
30508 is_microcoded_insn (rtx_insn *insn)
30510 if (!insn || !NONDEBUG_INSN_P (insn)
30511 || GET_CODE (PATTERN (insn)) == USE
30512 || GET_CODE (PATTERN (insn)) == CLOBBER)
30515 if (rs6000_tune == PROCESSOR_CELL)
30516 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30518 if (rs6000_sched_groups
30519 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30521 enum attr_type type = get_attr_type (insn);
30522 if ((type == TYPE_LOAD
30523 && get_attr_update (insn) == UPDATE_YES
30524 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30525 || ((type == TYPE_LOAD || type == TYPE_STORE)
30526 && get_attr_update (insn) == UPDATE_YES
30527 && get_attr_indexed (insn) == INDEXED_YES)
30528 || type == TYPE_MFCR)
30535 /* The function returns true if INSN is cracked into 2 instructions
30536 by the processor (and therefore occupies 2 issue slots). */
30539 is_cracked_insn (rtx_insn *insn)
30541 if (!insn || !NONDEBUG_INSN_P (insn)
30542 || GET_CODE (PATTERN (insn)) == USE
30543 || GET_CODE (PATTERN (insn)) == CLOBBER)
30546 if (rs6000_sched_groups
30547 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30549 enum attr_type type = get_attr_type (insn);
30550 if ((type == TYPE_LOAD
30551 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30552 && get_attr_update (insn) == UPDATE_NO)
30553 || (type == TYPE_LOAD
30554 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30555 && get_attr_update (insn) == UPDATE_YES
30556 && get_attr_indexed (insn) == INDEXED_NO)
30557 || (type == TYPE_STORE
30558 && get_attr_update (insn) == UPDATE_YES
30559 && get_attr_indexed (insn) == INDEXED_NO)
30560 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30561 && get_attr_update (insn) == UPDATE_YES)
30562 || (type == TYPE_CR_LOGICAL
30563 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30564 || (type == TYPE_EXTS
30565 && get_attr_dot (insn) == DOT_YES)
30566 || (type == TYPE_SHIFT
30567 && get_attr_dot (insn) == DOT_YES
30568 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30569 || (type == TYPE_MUL
30570 && get_attr_dot (insn) == DOT_YES)
30571 || type == TYPE_DIV
30572 || (type == TYPE_INSERT
30573 && get_attr_size (insn) == SIZE_32))
30580 /* The function returns true if INSN can be issued only from
30581 the branch slot. */
30584 is_branch_slot_insn (rtx_insn *insn)
30586 if (!insn || !NONDEBUG_INSN_P (insn)
30587 || GET_CODE (PATTERN (insn)) == USE
30588 || GET_CODE (PATTERN (insn)) == CLOBBER)
30591 if (rs6000_sched_groups)
30593 enum attr_type type = get_attr_type (insn);
30594 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30602 /* The function returns true if out_inst sets a value that is
30603 used in the address generation computation of in_insn */
30605 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30607 rtx out_set, in_set;
30609 /* For performance reasons, only handle the simple case where
30610 both loads are a single_set. */
30611 out_set = single_set (out_insn);
30614 in_set = single_set (in_insn);
30616 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30622 /* Try to determine base/offset/size parts of the given MEM.
30623 Return true if successful, false if all the values couldn't
30626 This function only looks for REG or REG+CONST address forms.
30627 REG+REG address form will return false. */
30630 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30631 HOST_WIDE_INT *size)
30634 if MEM_SIZE_KNOWN_P (mem)
30635 *size = MEM_SIZE (mem);
30639 addr_rtx = (XEXP (mem, 0));
30640 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30641 addr_rtx = XEXP (addr_rtx, 1);
30644 while (GET_CODE (addr_rtx) == PLUS
30645 && CONST_INT_P (XEXP (addr_rtx, 1)))
30647 *offset += INTVAL (XEXP (addr_rtx, 1));
30648 addr_rtx = XEXP (addr_rtx, 0);
30650 if (!REG_P (addr_rtx))
30657 /* The function returns true if the target storage location of
30658 mem1 is adjacent to the target storage location of mem2 */
30659 /* Return 1 if memory locations are adjacent. */
30662 adjacent_mem_locations (rtx mem1, rtx mem2)
30665 HOST_WIDE_INT off1, size1, off2, size2;
30667 if (get_memref_parts (mem1, ®1, &off1, &size1)
30668 && get_memref_parts (mem2, ®2, &off2, &size2))
30669 return ((REGNO (reg1) == REGNO (reg2))
30670 && ((off1 + size1 == off2)
30671 || (off2 + size2 == off1)));
30676 /* This function returns true if it can be determined that the two MEM
30677 locations overlap by at least 1 byte based on base reg/offset/size. */
30680 mem_locations_overlap (rtx mem1, rtx mem2)
30683 HOST_WIDE_INT off1, size1, off2, size2;
30685 if (get_memref_parts (mem1, ®1, &off1, &size1)
30686 && get_memref_parts (mem2, ®2, &off2, &size2))
30687 return ((REGNO (reg1) == REGNO (reg2))
30688 && (((off1 <= off2) && (off1 + size1 > off2))
30689 || ((off2 <= off1) && (off2 + size2 > off1))));
30694 /* A C statement (sans semicolon) to update the integer scheduling
30695 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30696 INSN earlier, reduce the priority to execute INSN later. Do not
30697 define this macro if you do not need to adjust the scheduling
30698 priorities of insns. */
30701 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30703 rtx load_mem, str_mem;
30704 /* On machines (like the 750) which have asymmetric integer units,
30705 where one integer unit can do multiply and divides and the other
30706 can't, reduce the priority of multiply/divide so it is scheduled
30707 before other integer operations. */
30710 if (! INSN_P (insn))
30713 if (GET_CODE (PATTERN (insn)) == USE)
30716 switch (rs6000_tune) {
30717 case PROCESSOR_PPC750:
30718 switch (get_attr_type (insn))
30725 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30726 priority, priority);
30727 if (priority >= 0 && priority < 0x01000000)
30734 if (insn_must_be_first_in_group (insn)
30735 && reload_completed
30736 && current_sched_info->sched_max_insns_priority
30737 && rs6000_sched_restricted_insns_priority)
30740 /* Prioritize insns that can be dispatched only in the first
30742 if (rs6000_sched_restricted_insns_priority == 1)
30743 /* Attach highest priority to insn. This means that in
30744 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30745 precede 'priority' (critical path) considerations. */
30746 return current_sched_info->sched_max_insns_priority;
30747 else if (rs6000_sched_restricted_insns_priority == 2)
30748 /* Increase priority of insn by a minimal amount. This means that in
30749 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30750 considerations precede dispatch-slot restriction considerations. */
30751 return (priority + 1);
30754 if (rs6000_tune == PROCESSOR_POWER6
30755 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30756 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30757 /* Attach highest priority to insn if the scheduler has just issued two
30758 stores and this instruction is a load, or two loads and this instruction
30759 is a store. Power6 wants loads and stores scheduled alternately
30761 return current_sched_info->sched_max_insns_priority;
30766 /* Return true if the instruction is nonpipelined on the Cell. */
30768 is_nonpipeline_insn (rtx_insn *insn)
30770 enum attr_type type;
30771 if (!insn || !NONDEBUG_INSN_P (insn)
30772 || GET_CODE (PATTERN (insn)) == USE
30773 || GET_CODE (PATTERN (insn)) == CLOBBER)
30776 type = get_attr_type (insn);
30777 if (type == TYPE_MUL
30778 || type == TYPE_DIV
30779 || type == TYPE_SDIV
30780 || type == TYPE_DDIV
30781 || type == TYPE_SSQRT
30782 || type == TYPE_DSQRT
30783 || type == TYPE_MFCR
30784 || type == TYPE_MFCRF
30785 || type == TYPE_MFJMPR)
30793 /* Return how many instructions the machine can issue per cycle. */
30796 rs6000_issue_rate (void)
30798 /* Unless scheduling for register pressure, use issue rate of 1 for
30799 first scheduling pass to decrease degradation. */
30800 if (!reload_completed && !flag_sched_pressure)
30803 switch (rs6000_tune) {
30804 case PROCESSOR_RS64A:
30805 case PROCESSOR_PPC601: /* ? */
30806 case PROCESSOR_PPC7450:
30808 case PROCESSOR_PPC440:
30809 case PROCESSOR_PPC603:
30810 case PROCESSOR_PPC750:
30811 case PROCESSOR_PPC7400:
30812 case PROCESSOR_PPC8540:
30813 case PROCESSOR_PPC8548:
30814 case PROCESSOR_CELL:
30815 case PROCESSOR_PPCE300C2:
30816 case PROCESSOR_PPCE300C3:
30817 case PROCESSOR_PPCE500MC:
30818 case PROCESSOR_PPCE500MC64:
30819 case PROCESSOR_PPCE5500:
30820 case PROCESSOR_PPCE6500:
30821 case PROCESSOR_TITAN:
30823 case PROCESSOR_PPC476:
30824 case PROCESSOR_PPC604:
30825 case PROCESSOR_PPC604e:
30826 case PROCESSOR_PPC620:
30827 case PROCESSOR_PPC630:
30829 case PROCESSOR_POWER4:
30830 case PROCESSOR_POWER5:
30831 case PROCESSOR_POWER6:
30832 case PROCESSOR_POWER7:
30834 case PROCESSOR_POWER8:
30836 case PROCESSOR_POWER9:
30837 case PROCESSOR_FUTURE:
30844 /* Return how many instructions to look ahead for better insn
30848 rs6000_use_sched_lookahead (void)
30850 switch (rs6000_tune)
30852 case PROCESSOR_PPC8540:
30853 case PROCESSOR_PPC8548:
30856 case PROCESSOR_CELL:
30857 return (reload_completed ? 8 : 0);
30864 /* We are choosing insn from the ready queue. Return zero if INSN can be
30867 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30869 if (ready_index == 0)
30872 if (rs6000_tune != PROCESSOR_CELL)
30875 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30877 if (!reload_completed
30878 || is_nonpipeline_insn (insn)
30879 || is_microcoded_insn (insn))
30885 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30886 and return true. */
30889 find_mem_ref (rtx pat, rtx *mem_ref)
30894 /* stack_tie does not produce any real memory traffic. */
30895 if (tie_operand (pat, VOIDmode))
30904 /* Recursively process the pattern. */
30905 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30907 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30911 if (find_mem_ref (XEXP (pat, i), mem_ref))
30914 else if (fmt[i] == 'E')
30915 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30917 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30925 /* Determine if PAT is a PATTERN of a load insn. */
30928 is_load_insn1 (rtx pat, rtx *load_mem)
30930 if (!pat || pat == NULL_RTX)
30933 if (GET_CODE (pat) == SET)
30934 return find_mem_ref (SET_SRC (pat), load_mem);
30936 if (GET_CODE (pat) == PARALLEL)
30940 for (i = 0; i < XVECLEN (pat, 0); i++)
30941 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30948 /* Determine if INSN loads from memory. */
30951 is_load_insn (rtx insn, rtx *load_mem)
30953 if (!insn || !INSN_P (insn))
30959 return is_load_insn1 (PATTERN (insn), load_mem);
30962 /* Determine if PAT is a PATTERN of a store insn. */
30965 is_store_insn1 (rtx pat, rtx *str_mem)
30967 if (!pat || pat == NULL_RTX)
30970 if (GET_CODE (pat) == SET)
30971 return find_mem_ref (SET_DEST (pat), str_mem);
30973 if (GET_CODE (pat) == PARALLEL)
30977 for (i = 0; i < XVECLEN (pat, 0); i++)
30978 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30985 /* Determine if INSN stores to memory. */
30988 is_store_insn (rtx insn, rtx *str_mem)
30990 if (!insn || !INSN_P (insn))
30993 return is_store_insn1 (PATTERN (insn), str_mem);
30996 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30999 is_power9_pairable_vec_type (enum attr_type type)
31003 case TYPE_VECSIMPLE:
31004 case TYPE_VECCOMPLEX:
31008 case TYPE_VECFLOAT:
31010 case TYPE_VECDOUBLE:
31018 /* Returns whether the dependence between INSN and NEXT is considered
31019 costly by the given target. */
31022 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31026 rtx load_mem, str_mem;
31028 /* If the flag is not enabled - no dependence is considered costly;
31029 allow all dependent insns in the same group.
31030 This is the most aggressive option. */
31031 if (rs6000_sched_costly_dep == no_dep_costly)
31034 /* If the flag is set to 1 - a dependence is always considered costly;
31035 do not allow dependent instructions in the same group.
31036 This is the most conservative option. */
31037 if (rs6000_sched_costly_dep == all_deps_costly)
31040 insn = DEP_PRO (dep);
31041 next = DEP_CON (dep);
31043 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31044 && is_load_insn (next, &load_mem)
31045 && is_store_insn (insn, &str_mem))
31046 /* Prevent load after store in the same group. */
31049 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31050 && is_load_insn (next, &load_mem)
31051 && is_store_insn (insn, &str_mem)
31052 && DEP_TYPE (dep) == REG_DEP_TRUE
31053 && mem_locations_overlap(str_mem, load_mem))
31054 /* Prevent load after store in the same group if it is a true
31058 /* The flag is set to X; dependences with latency >= X are considered costly,
31059 and will not be scheduled in the same group. */
31060 if (rs6000_sched_costly_dep <= max_dep_latency
31061 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31067 /* Return the next insn after INSN that is found before TAIL is reached,
31068 skipping any "non-active" insns - insns that will not actually occupy
31069 an issue slot. Return NULL_RTX if such an insn is not found. */
31072 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31074 if (insn == NULL_RTX || insn == tail)
31079 insn = NEXT_INSN (insn);
31080 if (insn == NULL_RTX || insn == tail)
31084 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31085 || (NONJUMP_INSN_P (insn)
31086 && GET_CODE (PATTERN (insn)) != USE
31087 && GET_CODE (PATTERN (insn)) != CLOBBER
31088 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31094 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31097 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31102 enum attr_type type, type2;
31104 type = get_attr_type (last_scheduled_insn);
31106 /* Try to issue fixed point divides back-to-back in pairs so they will be
31107 routed to separate execution units and execute in parallel. */
31108 if (type == TYPE_DIV && divide_cnt == 0)
31110 /* First divide has been scheduled. */
31113 /* Scan the ready list looking for another divide, if found move it
31114 to the end of the list so it is chosen next. */
31118 if (recog_memoized (ready[pos]) >= 0
31119 && get_attr_type (ready[pos]) == TYPE_DIV)
31122 for (i = pos; i < lastpos; i++)
31123 ready[i] = ready[i + 1];
31124 ready[lastpos] = tmp;
31132 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31135 /* The best dispatch throughput for vector and vector load insns can be
31136 achieved by interleaving a vector and vector load such that they'll
31137 dispatch to the same superslice. If this pairing cannot be achieved
31138 then it is best to pair vector insns together and vector load insns
31141 To aid in this pairing, vec_pairing maintains the current state with
31142 the following values:
31144 0 : Initial state, no vecload/vector pairing has been started.
31146 1 : A vecload or vector insn has been issued and a candidate for
31147 pairing has been found and moved to the end of the ready
31149 if (type == TYPE_VECLOAD)
31151 /* Issued a vecload. */
31152 if (vec_pairing == 0)
31154 int vecload_pos = -1;
31155 /* We issued a single vecload, look for a vector insn to pair it
31156 with. If one isn't found, try to pair another vecload. */
31160 if (recog_memoized (ready[pos]) >= 0)
31162 type2 = get_attr_type (ready[pos]);
31163 if (is_power9_pairable_vec_type (type2))
31165 /* Found a vector insn to pair with, move it to the
31166 end of the ready list so it is scheduled next. */
31168 for (i = pos; i < lastpos; i++)
31169 ready[i] = ready[i + 1];
31170 ready[lastpos] = tmp;
31172 return cached_can_issue_more;
31174 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31175 /* Remember position of first vecload seen. */
31180 if (vecload_pos >= 0)
31182 /* Didn't find a vector to pair with but did find a vecload,
31183 move it to the end of the ready list. */
31184 tmp = ready[vecload_pos];
31185 for (i = vecload_pos; i < lastpos; i++)
31186 ready[i] = ready[i + 1];
31187 ready[lastpos] = tmp;
31189 return cached_can_issue_more;
31193 else if (is_power9_pairable_vec_type (type))
31195 /* Issued a vector operation. */
31196 if (vec_pairing == 0)
31199 /* We issued a single vector insn, look for a vecload to pair it
31200 with. If one isn't found, try to pair another vector. */
31204 if (recog_memoized (ready[pos]) >= 0)
31206 type2 = get_attr_type (ready[pos]);
31207 if (type2 == TYPE_VECLOAD)
31209 /* Found a vecload insn to pair with, move it to the
31210 end of the ready list so it is scheduled next. */
31212 for (i = pos; i < lastpos; i++)
31213 ready[i] = ready[i + 1];
31214 ready[lastpos] = tmp;
31216 return cached_can_issue_more;
31218 else if (is_power9_pairable_vec_type (type2)
31220 /* Remember position of first vector insn seen. */
31227 /* Didn't find a vecload to pair with but did find a vector
31228 insn, move it to the end of the ready list. */
31229 tmp = ready[vec_pos];
31230 for (i = vec_pos; i < lastpos; i++)
31231 ready[i] = ready[i + 1];
31232 ready[lastpos] = tmp;
31234 return cached_can_issue_more;
31239 /* We've either finished a vec/vecload pair, couldn't find an insn to
31240 continue the current pair, or the last insn had nothing to do with
31241 with pairing. In any case, reset the state. */
31245 return cached_can_issue_more;
31248 /* We are about to begin issuing insns for this clock cycle. */
31251 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31252 rtx_insn **ready ATTRIBUTE_UNUSED,
31253 int *pn_ready ATTRIBUTE_UNUSED,
31254 int clock_var ATTRIBUTE_UNUSED)
31256 int n_ready = *pn_ready;
31259 fprintf (dump, "// rs6000_sched_reorder :\n");
31261 /* Reorder the ready list, if the second to last ready insn
31262 is a nonepipeline insn. */
31263 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31265 if (is_nonpipeline_insn (ready[n_ready - 1])
31266 && (recog_memoized (ready[n_ready - 2]) > 0))
31267 /* Simply swap first two insns. */
31268 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31271 if (rs6000_tune == PROCESSOR_POWER6)
31272 load_store_pendulum = 0;
31274 return rs6000_issue_rate ();
31277 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31280 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31281 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31284 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31286 /* For Power6, we need to handle some special cases to try and keep the
31287 store queue from overflowing and triggering expensive flushes.
31289 This code monitors how load and store instructions are being issued
31290 and skews the ready list one way or the other to increase the likelihood
31291 that a desired instruction is issued at the proper time.
31293 A couple of things are done. First, we maintain a "load_store_pendulum"
31294 to track the current state of load/store issue.
31296 - If the pendulum is at zero, then no loads or stores have been
31297 issued in the current cycle so we do nothing.
31299 - If the pendulum is 1, then a single load has been issued in this
31300 cycle and we attempt to locate another load in the ready list to
31303 - If the pendulum is -2, then two stores have already been
31304 issued in this cycle, so we increase the priority of the first load
31305 in the ready list to increase it's likelihood of being chosen first
31308 - If the pendulum is -1, then a single store has been issued in this
31309 cycle and we attempt to locate another store in the ready list to
31310 issue with it, preferring a store to an adjacent memory location to
31311 facilitate store pairing in the store queue.
31313 - If the pendulum is 2, then two loads have already been
31314 issued in this cycle, so we increase the priority of the first store
31315 in the ready list to increase it's likelihood of being chosen first
31318 - If the pendulum < -2 or > 2, then do nothing.
31320 Note: This code covers the most common scenarios. There exist non
31321 load/store instructions which make use of the LSU and which
31322 would need to be accounted for to strictly model the behavior
31323 of the machine. Those instructions are currently unaccounted
31324 for to help minimize compile time overhead of this code.
31326 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31331 rtx load_mem, str_mem;
31333 if (is_store_insn (last_scheduled_insn, &str_mem))
31334 /* Issuing a store, swing the load_store_pendulum to the left */
31335 load_store_pendulum--;
31336 else if (is_load_insn (last_scheduled_insn, &load_mem))
31337 /* Issuing a load, swing the load_store_pendulum to the right */
31338 load_store_pendulum++;
31340 return cached_can_issue_more;
31342 /* If the pendulum is balanced, or there is only one instruction on
31343 the ready list, then all is well, so return. */
31344 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31345 return cached_can_issue_more;
31347 if (load_store_pendulum == 1)
31349 /* A load has been issued in this cycle. Scan the ready list
31350 for another load to issue with it */
31355 if (is_load_insn (ready[pos], &load_mem))
31357 /* Found a load. Move it to the head of the ready list,
31358 and adjust it's priority so that it is more likely to
31361 for (i=pos; i<*pn_ready-1; i++)
31362 ready[i] = ready[i + 1];
31363 ready[*pn_ready-1] = tmp;
31365 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31366 INSN_PRIORITY (tmp)++;
31372 else if (load_store_pendulum == -2)
31374 /* Two stores have been issued in this cycle. Increase the
31375 priority of the first load in the ready list to favor it for
31376 issuing in the next cycle. */
31381 if (is_load_insn (ready[pos], &load_mem)
31383 && INSN_PRIORITY_KNOWN (ready[pos]))
31385 INSN_PRIORITY (ready[pos])++;
31387 /* Adjust the pendulum to account for the fact that a load
31388 was found and increased in priority. This is to prevent
31389 increasing the priority of multiple loads */
31390 load_store_pendulum--;
31397 else if (load_store_pendulum == -1)
31399 /* A store has been issued in this cycle. Scan the ready list for
31400 another store to issue with it, preferring a store to an adjacent
31402 int first_store_pos = -1;
31408 if (is_store_insn (ready[pos], &str_mem))
31411 /* Maintain the index of the first store found on the
31413 if (first_store_pos == -1)
31414 first_store_pos = pos;
31416 if (is_store_insn (last_scheduled_insn, &str_mem2)
31417 && adjacent_mem_locations (str_mem, str_mem2))
31419 /* Found an adjacent store. Move it to the head of the
31420 ready list, and adjust it's priority so that it is
31421 more likely to stay there */
31423 for (i=pos; i<*pn_ready-1; i++)
31424 ready[i] = ready[i + 1];
31425 ready[*pn_ready-1] = tmp;
31427 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31428 INSN_PRIORITY (tmp)++;
31430 first_store_pos = -1;
31438 if (first_store_pos >= 0)
31440 /* An adjacent store wasn't found, but a non-adjacent store was,
31441 so move the non-adjacent store to the front of the ready
31442 list, and adjust its priority so that it is more likely to
31444 tmp = ready[first_store_pos];
31445 for (i=first_store_pos; i<*pn_ready-1; i++)
31446 ready[i] = ready[i + 1];
31447 ready[*pn_ready-1] = tmp;
31448 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31449 INSN_PRIORITY (tmp)++;
31452 else if (load_store_pendulum == 2)
31454 /* Two loads have been issued in this cycle. Increase the priority
31455 of the first store in the ready list to favor it for issuing in
31461 if (is_store_insn (ready[pos], &str_mem)
31463 && INSN_PRIORITY_KNOWN (ready[pos]))
31465 INSN_PRIORITY (ready[pos])++;
31467 /* Adjust the pendulum to account for the fact that a store
31468 was found and increased in priority. This is to prevent
31469 increasing the priority of multiple stores */
31470 load_store_pendulum++;
31479 /* Do Power9 dependent reordering if necessary. */
31480 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31481 && recog_memoized (last_scheduled_insn) >= 0)
31482 return power9_sched_reorder2 (ready, *pn_ready - 1);
31484 return cached_can_issue_more;
31487 /* Return whether the presence of INSN causes a dispatch group termination
31488 of group WHICH_GROUP.
31490 If WHICH_GROUP == current_group, this function will return true if INSN
31491 causes the termination of the current group (i.e, the dispatch group to
31492 which INSN belongs). This means that INSN will be the last insn in the
31493 group it belongs to.
31495 If WHICH_GROUP == previous_group, this function will return true if INSN
31496 causes the termination of the previous group (i.e, the dispatch group that
31497 precedes the group to which INSN belongs). This means that INSN will be
31498 the first insn in the group it belongs to). */
31501 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31508 first = insn_must_be_first_in_group (insn);
31509 last = insn_must_be_last_in_group (insn);
31514 if (which_group == current_group)
31516 else if (which_group == previous_group)
31524 insn_must_be_first_in_group (rtx_insn *insn)
31526 enum attr_type type;
31530 || DEBUG_INSN_P (insn)
31531 || GET_CODE (PATTERN (insn)) == USE
31532 || GET_CODE (PATTERN (insn)) == CLOBBER)
31535 switch (rs6000_tune)
31537 case PROCESSOR_POWER5:
31538 if (is_cracked_insn (insn))
31541 case PROCESSOR_POWER4:
31542 if (is_microcoded_insn (insn))
31545 if (!rs6000_sched_groups)
31548 type = get_attr_type (insn);
31555 case TYPE_CR_LOGICAL:
31568 case PROCESSOR_POWER6:
31569 type = get_attr_type (insn);
31578 case TYPE_FPCOMPARE:
31589 if (get_attr_dot (insn) == DOT_NO
31590 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31595 if (get_attr_size (insn) == SIZE_32)
31603 if (get_attr_update (insn) == UPDATE_YES)
31611 case PROCESSOR_POWER7:
31612 type = get_attr_type (insn);
31616 case TYPE_CR_LOGICAL:
31630 if (get_attr_dot (insn) == DOT_YES)
31635 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31636 || get_attr_update (insn) == UPDATE_YES)
31643 if (get_attr_update (insn) == UPDATE_YES)
31651 case PROCESSOR_POWER8:
31652 type = get_attr_type (insn);
31656 case TYPE_CR_LOGICAL:
31664 case TYPE_VECSTORE:
31671 if (get_attr_dot (insn) == DOT_YES)
31676 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31677 || get_attr_update (insn) == UPDATE_YES)
31682 if (get_attr_update (insn) == UPDATE_YES
31683 && get_attr_indexed (insn) == INDEXED_YES)
31699 insn_must_be_last_in_group (rtx_insn *insn)
31701 enum attr_type type;
31705 || DEBUG_INSN_P (insn)
31706 || GET_CODE (PATTERN (insn)) == USE
31707 || GET_CODE (PATTERN (insn)) == CLOBBER)
31710 switch (rs6000_tune) {
31711 case PROCESSOR_POWER4:
31712 case PROCESSOR_POWER5:
31713 if (is_microcoded_insn (insn))
31716 if (is_branch_slot_insn (insn))
31720 case PROCESSOR_POWER6:
31721 type = get_attr_type (insn);
31729 case TYPE_FPCOMPARE:
31740 if (get_attr_dot (insn) == DOT_NO
31741 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31746 if (get_attr_size (insn) == SIZE_32)
31754 case PROCESSOR_POWER7:
31755 type = get_attr_type (insn);
31765 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31766 && get_attr_update (insn) == UPDATE_YES)
31771 if (get_attr_update (insn) == UPDATE_YES
31772 && get_attr_indexed (insn) == INDEXED_YES)
31780 case PROCESSOR_POWER8:
31781 type = get_attr_type (insn);
31793 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31794 && get_attr_update (insn) == UPDATE_YES)
31799 if (get_attr_update (insn) == UPDATE_YES
31800 && get_attr_indexed (insn) == INDEXED_YES)
31815 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31816 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31819 is_costly_group (rtx *group_insns, rtx next_insn)
31822 int issue_rate = rs6000_issue_rate ();
31824 for (i = 0; i < issue_rate; i++)
31826 sd_iterator_def sd_it;
31828 rtx insn = group_insns[i];
31833 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31835 rtx next = DEP_CON (dep);
31837 if (next == next_insn
31838 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31846 /* Utility of the function redefine_groups.
31847 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31848 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31849 to keep it "far" (in a separate group) from GROUP_INSNS, following
31850 one of the following schemes, depending on the value of the flag
31851 -minsert_sched_nops = X:
31852 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31853 in order to force NEXT_INSN into a separate group.
31854 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31855 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31856 insertion (has a group just ended, how many vacant issue slots remain in the
31857 last group, and how many dispatch groups were encountered so far). */
31860 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31861 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31866 int issue_rate = rs6000_issue_rate ();
31867 bool end = *group_end;
31870 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31871 return can_issue_more;
31873 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31874 return can_issue_more;
31876 force = is_costly_group (group_insns, next_insn);
31878 return can_issue_more;
31880 if (sched_verbose > 6)
31881 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31882 *group_count ,can_issue_more);
31884 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31887 can_issue_more = 0;
31889 /* Since only a branch can be issued in the last issue_slot, it is
31890 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31891 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31892 in this case the last nop will start a new group and the branch
31893 will be forced to the new group. */
31894 if (can_issue_more && !is_branch_slot_insn (next_insn))
31897 /* Do we have a special group ending nop? */
31898 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31899 || rs6000_tune == PROCESSOR_POWER8)
31901 nop = gen_group_ending_nop ();
31902 emit_insn_before (nop, next_insn);
31903 can_issue_more = 0;
31906 while (can_issue_more > 0)
31909 emit_insn_before (nop, next_insn);
31917 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31919 int n_nops = rs6000_sched_insert_nops;
31921 /* Nops can't be issued from the branch slot, so the effective
31922 issue_rate for nops is 'issue_rate - 1'. */
31923 if (can_issue_more == 0)
31924 can_issue_more = issue_rate;
31926 if (can_issue_more == 0)
31928 can_issue_more = issue_rate - 1;
31931 for (i = 0; i < issue_rate; i++)
31933 group_insns[i] = 0;
31940 emit_insn_before (nop, next_insn);
31941 if (can_issue_more == issue_rate - 1) /* new group begins */
31944 if (can_issue_more == 0)
31946 can_issue_more = issue_rate - 1;
31949 for (i = 0; i < issue_rate; i++)
31951 group_insns[i] = 0;
31957 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31960 /* Is next_insn going to start a new group? */
31963 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31964 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31965 || (can_issue_more < issue_rate &&
31966 insn_terminates_group_p (next_insn, previous_group)));
31967 if (*group_end && end)
31970 if (sched_verbose > 6)
31971 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31972 *group_count, can_issue_more);
31973 return can_issue_more;
31976 return can_issue_more;
31979 /* This function tries to synch the dispatch groups that the compiler "sees"
31980 with the dispatch groups that the processor dispatcher is expected to
31981 form in practice. It tries to achieve this synchronization by forcing the
31982 estimated processor grouping on the compiler (as opposed to the function
31983 'pad_goups' which tries to force the scheduler's grouping on the processor).
31985 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31986 examines the (estimated) dispatch groups that will be formed by the processor
31987 dispatcher. It marks these group boundaries to reflect the estimated
31988 processor grouping, overriding the grouping that the scheduler had marked.
31989 Depending on the value of the flag '-minsert-sched-nops' this function can
31990 force certain insns into separate groups or force a certain distance between
31991 them by inserting nops, for example, if there exists a "costly dependence"
31994 The function estimates the group boundaries that the processor will form as
31995 follows: It keeps track of how many vacant issue slots are available after
31996 each insn. A subsequent insn will start a new group if one of the following
31998 - no more vacant issue slots remain in the current dispatch group.
31999 - only the last issue slot, which is the branch slot, is vacant, but the next
32000 insn is not a branch.
32001 - only the last 2 or less issue slots, including the branch slot, are vacant,
32002 which means that a cracked insn (which occupies two issue slots) can't be
32003 issued in this group.
32004 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32005 start a new group. */
32008 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32011 rtx_insn *insn, *next_insn;
32013 int can_issue_more;
32016 int group_count = 0;
32020 issue_rate = rs6000_issue_rate ();
32021 group_insns = XALLOCAVEC (rtx, issue_rate);
32022 for (i = 0; i < issue_rate; i++)
32024 group_insns[i] = 0;
32026 can_issue_more = issue_rate;
32028 insn = get_next_active_insn (prev_head_insn, tail);
32031 while (insn != NULL_RTX)
32033 slot = (issue_rate - can_issue_more);
32034 group_insns[slot] = insn;
32036 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32037 if (insn_terminates_group_p (insn, current_group))
32038 can_issue_more = 0;
32040 next_insn = get_next_active_insn (insn, tail);
32041 if (next_insn == NULL_RTX)
32042 return group_count + 1;
32044 /* Is next_insn going to start a new group? */
32046 = (can_issue_more == 0
32047 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32048 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32049 || (can_issue_more < issue_rate &&
32050 insn_terminates_group_p (next_insn, previous_group)));
32052 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32053 next_insn, &group_end, can_issue_more,
32059 can_issue_more = 0;
32060 for (i = 0; i < issue_rate; i++)
32062 group_insns[i] = 0;
32066 if (GET_MODE (next_insn) == TImode && can_issue_more)
32067 PUT_MODE (next_insn, VOIDmode);
32068 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32069 PUT_MODE (next_insn, TImode);
32072 if (can_issue_more == 0)
32073 can_issue_more = issue_rate;
32076 return group_count;
32079 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32080 dispatch group boundaries that the scheduler had marked. Pad with nops
32081 any dispatch groups which have vacant issue slots, in order to force the
32082 scheduler's grouping on the processor dispatcher. The function
32083 returns the number of dispatch groups found. */
32086 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32089 rtx_insn *insn, *next_insn;
32092 int can_issue_more;
32094 int group_count = 0;
32096 /* Initialize issue_rate. */
32097 issue_rate = rs6000_issue_rate ();
32098 can_issue_more = issue_rate;
32100 insn = get_next_active_insn (prev_head_insn, tail);
32101 next_insn = get_next_active_insn (insn, tail);
32103 while (insn != NULL_RTX)
32106 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32108 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32110 if (next_insn == NULL_RTX)
32115 /* If the scheduler had marked group termination at this location
32116 (between insn and next_insn), and neither insn nor next_insn will
32117 force group termination, pad the group with nops to force group
32120 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32121 && !insn_terminates_group_p (insn, current_group)
32122 && !insn_terminates_group_p (next_insn, previous_group))
32124 if (!is_branch_slot_insn (next_insn))
32127 while (can_issue_more)
32130 emit_insn_before (nop, next_insn);
32135 can_issue_more = issue_rate;
32140 next_insn = get_next_active_insn (insn, tail);
32143 return group_count;
32146 /* We're beginning a new block. Initialize data structures as necessary. */
32149 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32150 int sched_verbose ATTRIBUTE_UNUSED,
32151 int max_ready ATTRIBUTE_UNUSED)
32153 last_scheduled_insn = NULL;
32154 load_store_pendulum = 0;
32159 /* The following function is called at the end of scheduling BB.
32160 After reload, it inserts nops at insn group bundling. */
32163 rs6000_sched_finish (FILE *dump, int sched_verbose)
32168 fprintf (dump, "=== Finishing schedule.\n");
32170 if (reload_completed && rs6000_sched_groups)
32172 /* Do not run sched_finish hook when selective scheduling enabled. */
32173 if (sel_sched_p ())
32176 if (rs6000_sched_insert_nops == sched_finish_none)
32179 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32180 n_groups = pad_groups (dump, sched_verbose,
32181 current_sched_info->prev_head,
32182 current_sched_info->next_tail);
32184 n_groups = redefine_groups (dump, sched_verbose,
32185 current_sched_info->prev_head,
32186 current_sched_info->next_tail);
32188 if (sched_verbose >= 6)
32190 fprintf (dump, "ngroups = %d\n", n_groups);
32191 print_rtl (dump, current_sched_info->prev_head);
32192 fprintf (dump, "Done finish_sched\n");
32197 struct rs6000_sched_context
32199 short cached_can_issue_more;
32200 rtx_insn *last_scheduled_insn;
32201 int load_store_pendulum;
32206 typedef struct rs6000_sched_context rs6000_sched_context_def;
32207 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32209 /* Allocate store for new scheduling context. */
32211 rs6000_alloc_sched_context (void)
32213 return xmalloc (sizeof (rs6000_sched_context_def));
32216 /* If CLEAN_P is true then initializes _SC with clean data,
32217 and from the global context otherwise. */
32219 rs6000_init_sched_context (void *_sc, bool clean_p)
32221 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32225 sc->cached_can_issue_more = 0;
32226 sc->last_scheduled_insn = NULL;
32227 sc->load_store_pendulum = 0;
32228 sc->divide_cnt = 0;
32229 sc->vec_pairing = 0;
32233 sc->cached_can_issue_more = cached_can_issue_more;
32234 sc->last_scheduled_insn = last_scheduled_insn;
32235 sc->load_store_pendulum = load_store_pendulum;
32236 sc->divide_cnt = divide_cnt;
32237 sc->vec_pairing = vec_pairing;
32241 /* Sets the global scheduling context to the one pointed to by _SC. */
32243 rs6000_set_sched_context (void *_sc)
32245 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32247 gcc_assert (sc != NULL);
32249 cached_can_issue_more = sc->cached_can_issue_more;
32250 last_scheduled_insn = sc->last_scheduled_insn;
32251 load_store_pendulum = sc->load_store_pendulum;
32252 divide_cnt = sc->divide_cnt;
32253 vec_pairing = sc->vec_pairing;
32258 rs6000_free_sched_context (void *_sc)
32260 gcc_assert (_sc != NULL);
32266 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32268 switch (get_attr_type (insn))
32283 /* Length in units of the trampoline for entering a nested function. */
32286 rs6000_trampoline_size (void)
32290 switch (DEFAULT_ABI)
32293 gcc_unreachable ();
32296 ret = (TARGET_32BIT) ? 12 : 24;
32300 gcc_assert (!TARGET_32BIT);
32306 ret = (TARGET_32BIT) ? 40 : 48;
32313 /* Emit RTL insns to initialize the variable parts of a trampoline.
32314 FNADDR is an RTX for the address of the function's pure code.
32315 CXT is an RTX for the static chain value for the function. */
32318 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32320 int regsize = (TARGET_32BIT) ? 4 : 8;
32321 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32322 rtx ctx_reg = force_reg (Pmode, cxt);
32323 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32325 switch (DEFAULT_ABI)
32328 gcc_unreachable ();
32330 /* Under AIX, just build the 3 word function descriptor */
32333 rtx fnmem, fn_reg, toc_reg;
32335 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32336 error ("you cannot take the address of a nested function if you use "
32337 "the %qs option", "-mno-pointers-to-nested-functions");
32339 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32340 fn_reg = gen_reg_rtx (Pmode);
32341 toc_reg = gen_reg_rtx (Pmode);
32343 /* Macro to shorten the code expansions below. */
32344 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32346 m_tramp = replace_equiv_address (m_tramp, addr);
32348 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32349 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32350 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32351 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32352 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32358 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32362 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32363 LCT_NORMAL, VOIDmode,
32365 GEN_INT (rs6000_trampoline_size ()), SImode,
32373 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32374 identifier as an argument, so the front end shouldn't look it up. */
32377 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32379 return is_attribute_p ("altivec", attr_id);
32382 /* Handle the "altivec" attribute. The attribute may have
32383 arguments as follows:
32385 __attribute__((altivec(vector__)))
32386 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32387 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32389 and may appear more than once (e.g., 'vector bool char') in a
32390 given declaration. */
32393 rs6000_handle_altivec_attribute (tree *node,
32394 tree name ATTRIBUTE_UNUSED,
32396 int flags ATTRIBUTE_UNUSED,
32397 bool *no_add_attrs)
32399 tree type = *node, result = NULL_TREE;
32403 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32404 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32405 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32408 while (POINTER_TYPE_P (type)
32409 || TREE_CODE (type) == FUNCTION_TYPE
32410 || TREE_CODE (type) == METHOD_TYPE
32411 || TREE_CODE (type) == ARRAY_TYPE)
32412 type = TREE_TYPE (type);
32414 mode = TYPE_MODE (type);
32416 /* Check for invalid AltiVec type qualifiers. */
32417 if (type == long_double_type_node)
32418 error ("use of %<long double%> in AltiVec types is invalid");
32419 else if (type == boolean_type_node)
32420 error ("use of boolean types in AltiVec types is invalid");
32421 else if (TREE_CODE (type) == COMPLEX_TYPE)
32422 error ("use of %<complex%> in AltiVec types is invalid");
32423 else if (DECIMAL_FLOAT_MODE_P (mode))
32424 error ("use of decimal floating point types in AltiVec types is invalid");
32425 else if (!TARGET_VSX)
32427 if (type == long_unsigned_type_node || type == long_integer_type_node)
32430 error ("use of %<long%> in AltiVec types is invalid for "
32431 "64-bit code without %qs", "-mvsx");
32432 else if (rs6000_warn_altivec_long)
32433 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32436 else if (type == long_long_unsigned_type_node
32437 || type == long_long_integer_type_node)
32438 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32440 else if (type == double_type_node)
32441 error ("use of %<double%> in AltiVec types is invalid without %qs",
32445 switch (altivec_type)
32448 unsigned_p = TYPE_UNSIGNED (type);
32452 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32455 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32458 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32461 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32464 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32466 case E_SFmode: result = V4SF_type_node; break;
32467 case E_DFmode: result = V2DF_type_node; break;
32468 /* If the user says 'vector int bool', we may be handed the 'bool'
32469 attribute _before_ the 'vector' attribute, and so select the
32470 proper type in the 'b' case below. */
32471 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32472 case E_V2DImode: case E_V2DFmode:
32480 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32481 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32482 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32483 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32490 case E_V8HImode: result = pixel_V8HI_type_node;
32496 /* Propagate qualifiers attached to the element type
32497 onto the vector type. */
32498 if (result && result != type && TYPE_QUALS (type))
32499 result = build_qualified_type (result, TYPE_QUALS (type));
32501 *no_add_attrs = true; /* No need to hang on to the attribute. */
32504 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32509 /* AltiVec defines five built-in scalar types that serve as vector
32510 elements; we must teach the compiler how to mangle them. The 128-bit
32511 floating point mangling is target-specific as well. */
32513 static const char *
32514 rs6000_mangle_type (const_tree type)
32516 type = TYPE_MAIN_VARIANT (type);
32518 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32519 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32522 if (type == bool_char_type_node) return "U6__boolc";
32523 if (type == bool_short_type_node) return "U6__bools";
32524 if (type == pixel_type_node) return "u7__pixel";
32525 if (type == bool_int_type_node) return "U6__booli";
32526 if (type == bool_long_long_type_node) return "U6__boolx";
32528 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32530 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32531 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32533 /* For all other types, use the default mangling. */
32537 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32538 struct attribute_spec.handler. */
32541 rs6000_handle_longcall_attribute (tree *node, tree name,
32542 tree args ATTRIBUTE_UNUSED,
32543 int flags ATTRIBUTE_UNUSED,
32544 bool *no_add_attrs)
32546 if (TREE_CODE (*node) != FUNCTION_TYPE
32547 && TREE_CODE (*node) != FIELD_DECL
32548 && TREE_CODE (*node) != TYPE_DECL)
32550 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32552 *no_add_attrs = true;
32558 /* Set longcall attributes on all functions declared when
32559 rs6000_default_long_calls is true. */
32561 rs6000_set_default_type_attributes (tree type)
32563 if (rs6000_default_long_calls
32564 && (TREE_CODE (type) == FUNCTION_TYPE
32565 || TREE_CODE (type) == METHOD_TYPE))
32566 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32568 TYPE_ATTRIBUTES (type));
32571 darwin_set_default_type_attributes (type);
32575 /* Return a reference suitable for calling a function with the
32576 longcall attribute. */
32579 rs6000_longcall_ref (rtx call_ref, rtx arg)
32581 /* System V adds '.' to the internal name, so skip them. */
32582 const char *call_name = XSTR (call_ref, 0);
32583 if (*call_name == '.')
32585 while (*call_name == '.')
32588 tree node = get_identifier (call_name);
32589 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32594 rtx base = const0_rtx;
32596 if (DEFAULT_ABI == ABI_ELFv2)
32598 base = gen_rtx_REG (Pmode, TOC_REGISTER);
32604 base = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
32607 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32608 may be used by a function global entry point. For SysV4, r11
32609 is used by __glink_PLTresolve lazy resolver entry. */
32610 rtx reg = gen_rtx_REG (Pmode, regno);
32611 rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32613 rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg),
32615 emit_insn (gen_rtx_SET (reg, hi));
32616 emit_insn (gen_rtx_SET (reg, lo));
32620 return force_reg (Pmode, call_ref);
32623 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32624 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32627 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32628 struct attribute_spec.handler. */
32630 rs6000_handle_struct_attribute (tree *node, tree name,
32631 tree args ATTRIBUTE_UNUSED,
32632 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32635 if (DECL_P (*node))
32637 if (TREE_CODE (*node) == TYPE_DECL)
32638 type = &TREE_TYPE (*node);
32643 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32644 || TREE_CODE (*type) == UNION_TYPE)))
32646 warning (OPT_Wattributes, "%qE attribute ignored", name);
32647 *no_add_attrs = true;
32650 else if ((is_attribute_p ("ms_struct", name)
32651 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32652 || ((is_attribute_p ("gcc_struct", name)
32653 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32655 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32657 *no_add_attrs = true;
32664 rs6000_ms_bitfield_layout_p (const_tree record_type)
32666 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32667 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32668 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32671 #ifdef USING_ELFOS_H
32673 /* A get_unnamed_section callback, used for switching to toc_section. */
32676 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32678 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32679 && TARGET_MINIMAL_TOC)
32681 if (!toc_initialized)
32683 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32684 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32685 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32686 fprintf (asm_out_file, "\t.tc ");
32687 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32688 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32689 fprintf (asm_out_file, "\n");
32691 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32692 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32693 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32694 fprintf (asm_out_file, " = .+32768\n");
32695 toc_initialized = 1;
32698 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32700 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32702 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32703 if (!toc_initialized)
32705 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32706 toc_initialized = 1;
32711 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32712 if (!toc_initialized)
32714 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32715 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32716 fprintf (asm_out_file, " = .+32768\n");
32717 toc_initialized = 1;
32722 /* Implement TARGET_ASM_INIT_SECTIONS. */
32725 rs6000_elf_asm_init_sections (void)
32728 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32731 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32732 SDATA2_SECTION_ASM_OP);
32735 /* Implement TARGET_SELECT_RTX_SECTION. */
32738 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32739 unsigned HOST_WIDE_INT align)
32741 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32742 return toc_section;
32744 return default_elf_select_rtx_section (mode, x, align);
32747 /* For a SYMBOL_REF, set generic flags and then perform some
32748 target-specific processing.
32750 When the AIX ABI is requested on a non-AIX system, replace the
32751 function name with the real name (with a leading .) rather than the
32752 function descriptor name. This saves a lot of overriding code to
32753 read the prefixes. */
32755 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32757 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32759 default_encode_section_info (decl, rtl, first);
32762 && TREE_CODE (decl) == FUNCTION_DECL
32764 && DEFAULT_ABI == ABI_AIX)
32766 rtx sym_ref = XEXP (rtl, 0);
32767 size_t len = strlen (XSTR (sym_ref, 0));
32768 char *str = XALLOCAVEC (char, len + 2);
32770 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32771 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32776 compare_section_name (const char *section, const char *templ)
32780 len = strlen (templ);
32781 return (strncmp (section, templ, len) == 0
32782 && (section[len] == 0 || section[len] == '.'));
32786 rs6000_elf_in_small_data_p (const_tree decl)
32788 if (rs6000_sdata == SDATA_NONE)
32791 /* We want to merge strings, so we never consider them small data. */
32792 if (TREE_CODE (decl) == STRING_CST)
32795 /* Functions are never in the small data area. */
32796 if (TREE_CODE (decl) == FUNCTION_DECL)
32799 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32801 const char *section = DECL_SECTION_NAME (decl);
32802 if (compare_section_name (section, ".sdata")
32803 || compare_section_name (section, ".sdata2")
32804 || compare_section_name (section, ".gnu.linkonce.s")
32805 || compare_section_name (section, ".sbss")
32806 || compare_section_name (section, ".sbss2")
32807 || compare_section_name (section, ".gnu.linkonce.sb")
32808 || strcmp (section, ".PPC.EMB.sdata0") == 0
32809 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32814 /* If we are told not to put readonly data in sdata, then don't. */
32815 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32816 && !rs6000_readonly_in_sdata)
32819 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32822 && size <= g_switch_value
32823 /* If it's not public, and we're not going to reference it there,
32824 there's no need to put it in the small data section. */
32825 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32832 #endif /* USING_ELFOS_H */
32834 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32837 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32839 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32842 /* Do not place thread-local symbols refs in the object blocks. */
32845 rs6000_use_blocks_for_decl_p (const_tree decl)
32847 return !DECL_THREAD_LOCAL_P (decl);
32850 /* Return a REG that occurs in ADDR with coefficient 1.
32851 ADDR can be effectively incremented by incrementing REG.
32853 r0 is special and we must not select it as an address
32854 register by this routine since our caller will try to
32855 increment the returned register via an "la" instruction. */
32858 find_addr_reg (rtx addr)
32860 while (GET_CODE (addr) == PLUS)
32862 if (REG_P (XEXP (addr, 0))
32863 && REGNO (XEXP (addr, 0)) != 0)
32864 addr = XEXP (addr, 0);
32865 else if (REG_P (XEXP (addr, 1))
32866 && REGNO (XEXP (addr, 1)) != 0)
32867 addr = XEXP (addr, 1);
32868 else if (CONSTANT_P (XEXP (addr, 0)))
32869 addr = XEXP (addr, 1);
32870 else if (CONSTANT_P (XEXP (addr, 1)))
32871 addr = XEXP (addr, 0);
32873 gcc_unreachable ();
32875 gcc_assert (REG_P (addr) && REGNO (addr) != 0);
32880 rs6000_fatal_bad_address (rtx op)
32882 fatal_insn ("bad address", op);
32887 typedef struct branch_island_d {
32888 tree function_name;
32894 static vec<branch_island, va_gc> *branch_islands;
32896 /* Remember to generate a branch island for far calls to the given
32900 add_compiler_branch_island (tree label_name, tree function_name,
32903 branch_island bi = {function_name, label_name, line_number};
32904 vec_safe_push (branch_islands, bi);
32907 /* Generate far-jump branch islands for everything recorded in
32908 branch_islands. Invoked immediately after the last instruction of
32909 the epilogue has been emitted; the branch islands must be appended
32910 to, and contiguous with, the function body. Mach-O stubs are
32911 generated in machopic_output_stub(). */
32914 macho_branch_islands (void)
32918 while (!vec_safe_is_empty (branch_islands))
32920 branch_island *bi = &branch_islands->last ();
32921 const char *label = IDENTIFIER_POINTER (bi->label_name);
32922 const char *name = IDENTIFIER_POINTER (bi->function_name);
32923 char name_buf[512];
32924 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32925 if (name[0] == '*' || name[0] == '&')
32926 strcpy (name_buf, name+1);
32930 strcpy (name_buf+1, name);
32932 strcpy (tmp_buf, "\n");
32933 strcat (tmp_buf, label);
32934 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32935 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32936 dbxout_stabd (N_SLINE, bi->line_number);
32937 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32940 if (TARGET_LINK_STACK)
32943 get_ppc476_thunk_name (name);
32944 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32945 strcat (tmp_buf, name);
32946 strcat (tmp_buf, "\n");
32947 strcat (tmp_buf, label);
32948 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32952 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32953 strcat (tmp_buf, label);
32954 strcat (tmp_buf, "_pic\n");
32955 strcat (tmp_buf, label);
32956 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32959 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32960 strcat (tmp_buf, name_buf);
32961 strcat (tmp_buf, " - ");
32962 strcat (tmp_buf, label);
32963 strcat (tmp_buf, "_pic)\n");
32965 strcat (tmp_buf, "\tmtlr r0\n");
32967 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32968 strcat (tmp_buf, name_buf);
32969 strcat (tmp_buf, " - ");
32970 strcat (tmp_buf, label);
32971 strcat (tmp_buf, "_pic)\n");
32973 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32977 strcat (tmp_buf, ":\n\tlis r12,hi16(");
32978 strcat (tmp_buf, name_buf);
32979 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32980 strcat (tmp_buf, name_buf);
32981 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32983 output_asm_insn (tmp_buf, 0);
32984 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32985 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32986 dbxout_stabd (N_SLINE, bi->line_number);
32987 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32988 branch_islands->pop ();
32992 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32993 already there or not. */
32996 no_previous_def (tree function_name)
33001 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33002 if (function_name == bi->function_name)
33007 /* GET_PREV_LABEL gets the label name from the previous definition of
33011 get_prev_label (tree function_name)
33016 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33017 if (function_name == bi->function_name)
33018 return bi->label_name;
33022 /* Generate PIC and indirect symbol stubs. */
33025 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33027 unsigned int length;
33028 char *symbol_name, *lazy_ptr_name;
33029 char *local_label_0;
33030 static unsigned label = 0;
33032 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33033 symb = (*targetm.strip_name_encoding) (symb);
33036 length = strlen (symb);
33037 symbol_name = XALLOCAVEC (char, length + 32);
33038 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33040 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33041 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33044 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33046 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33050 fprintf (file, "\t.align 5\n");
33052 fprintf (file, "%s:\n", stub);
33053 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33056 local_label_0 = XALLOCAVEC (char, 16);
33057 sprintf (local_label_0, "L%u$spb", label);
33059 fprintf (file, "\tmflr r0\n");
33060 if (TARGET_LINK_STACK)
33063 get_ppc476_thunk_name (name);
33064 fprintf (file, "\tbl %s\n", name);
33065 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33069 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33070 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33072 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33073 lazy_ptr_name, local_label_0);
33074 fprintf (file, "\tmtlr r0\n");
33075 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33076 (TARGET_64BIT ? "ldu" : "lwzu"),
33077 lazy_ptr_name, local_label_0);
33078 fprintf (file, "\tmtctr r12\n");
33079 fprintf (file, "\tbctr\n");
33083 fprintf (file, "\t.align 4\n");
33085 fprintf (file, "%s:\n", stub);
33086 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33088 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33089 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33090 (TARGET_64BIT ? "ldu" : "lwzu"),
33092 fprintf (file, "\tmtctr r12\n");
33093 fprintf (file, "\tbctr\n");
33096 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33097 fprintf (file, "%s:\n", lazy_ptr_name);
33098 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33099 fprintf (file, "%sdyld_stub_binding_helper\n",
33100 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33103 /* Legitimize PIC addresses. If the address is already
33104 position-independent, we return ORIG. Newly generated
33105 position-independent addresses go into a reg. This is REG if non
33106 zero, otherwise we allocate register(s) as necessary. */
33108 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33111 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33116 if (reg == NULL && !reload_completed)
33117 reg = gen_reg_rtx (Pmode);
33119 if (GET_CODE (orig) == CONST)
33123 if (GET_CODE (XEXP (orig, 0)) == PLUS
33124 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33127 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33129 /* Use a different reg for the intermediate value, as
33130 it will be marked UNCHANGING. */
33131 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33132 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33135 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33138 if (CONST_INT_P (offset))
33140 if (SMALL_INT (offset))
33141 return plus_constant (Pmode, base, INTVAL (offset));
33142 else if (!reload_completed)
33143 offset = force_reg (Pmode, offset);
33146 rtx mem = force_const_mem (Pmode, orig);
33147 return machopic_legitimize_pic_address (mem, Pmode, reg);
33150 return gen_rtx_PLUS (Pmode, base, offset);
33153 /* Fall back on generic machopic code. */
33154 return machopic_legitimize_pic_address (orig, mode, reg);
33157 /* Output a .machine directive for the Darwin assembler, and call
33158 the generic start_file routine. */
33161 rs6000_darwin_file_start (void)
33163 static const struct
33167 HOST_WIDE_INT if_set;
33169 { "ppc64", "ppc64", MASK_64BIT },
33170 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33171 { "power4", "ppc970", 0 },
33172 { "G5", "ppc970", 0 },
33173 { "7450", "ppc7450", 0 },
33174 { "7400", "ppc7400", MASK_ALTIVEC },
33175 { "G4", "ppc7400", 0 },
33176 { "750", "ppc750", 0 },
33177 { "740", "ppc750", 0 },
33178 { "G3", "ppc750", 0 },
33179 { "604e", "ppc604e", 0 },
33180 { "604", "ppc604", 0 },
33181 { "603e", "ppc603", 0 },
33182 { "603", "ppc603", 0 },
33183 { "601", "ppc601", 0 },
33184 { NULL, "ppc", 0 } };
33185 const char *cpu_id = "";
33188 rs6000_file_start ();
33189 darwin_file_start ();
33191 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33193 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33194 cpu_id = rs6000_default_cpu;
33196 if (global_options_set.x_rs6000_cpu_index)
33197 cpu_id = processor_target_table[rs6000_cpu_index].name;
33199 /* Look through the mapping array. Pick the first name that either
33200 matches the argument, has a bit set in IF_SET that is also set
33201 in the target flags, or has a NULL name. */
33204 while (mapping[i].arg != NULL
33205 && strcmp (mapping[i].arg, cpu_id) != 0
33206 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33209 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33212 #endif /* TARGET_MACHO */
33216 rs6000_elf_reloc_rw_mask (void)
33220 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33226 /* Record an element in the table of global constructors. SYMBOL is
33227 a SYMBOL_REF of the function to be called; PRIORITY is a number
33228 between 0 and MAX_INIT_PRIORITY.
33230 This differs from default_named_section_asm_out_constructor in
33231 that we have special handling for -mrelocatable. */
33233 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33235 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33237 const char *section = ".ctors";
33240 if (priority != DEFAULT_INIT_PRIORITY)
33242 sprintf (buf, ".ctors.%.5u",
33243 /* Invert the numbering so the linker puts us in the proper
33244 order; constructors are run from right to left, and the
33245 linker sorts in increasing order. */
33246 MAX_INIT_PRIORITY - priority);
33250 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33251 assemble_align (POINTER_SIZE);
33253 if (DEFAULT_ABI == ABI_V4
33254 && (TARGET_RELOCATABLE || flag_pic > 1))
33256 fputs ("\t.long (", asm_out_file);
33257 output_addr_const (asm_out_file, symbol);
33258 fputs (")@fixup\n", asm_out_file);
33261 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33264 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33266 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33268 const char *section = ".dtors";
33271 if (priority != DEFAULT_INIT_PRIORITY)
33273 sprintf (buf, ".dtors.%.5u",
33274 /* Invert the numbering so the linker puts us in the proper
33275 order; constructors are run from right to left, and the
33276 linker sorts in increasing order. */
33277 MAX_INIT_PRIORITY - priority);
33281 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33282 assemble_align (POINTER_SIZE);
33284 if (DEFAULT_ABI == ABI_V4
33285 && (TARGET_RELOCATABLE || flag_pic > 1))
33287 fputs ("\t.long (", asm_out_file);
33288 output_addr_const (asm_out_file, symbol);
33289 fputs (")@fixup\n", asm_out_file);
33292 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33296 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33298 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33300 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33301 ASM_OUTPUT_LABEL (file, name);
33302 fputs (DOUBLE_INT_ASM_OP, file);
33303 rs6000_output_function_entry (file, name);
33304 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33307 fputs ("\t.size\t", file);
33308 assemble_name (file, name);
33309 fputs (",24\n\t.type\t.", file);
33310 assemble_name (file, name);
33311 fputs (",@function\n", file);
33312 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33314 fputs ("\t.globl\t.", file);
33315 assemble_name (file, name);
33320 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33321 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33322 rs6000_output_function_entry (file, name);
33323 fputs (":\n", file);
33328 if (DEFAULT_ABI == ABI_V4
33329 && (TARGET_RELOCATABLE || flag_pic > 1)
33330 && !TARGET_SECURE_PLT
33331 && (!constant_pool_empty_p () || crtl->profile)
33332 && (uses_toc = uses_TOC ()))
33337 switch_to_other_text_partition ();
33338 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33340 fprintf (file, "\t.long ");
33341 assemble_name (file, toc_label_name);
33344 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33345 assemble_name (file, buf);
33348 switch_to_other_text_partition ();
33351 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33352 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33354 if (TARGET_CMODEL == CMODEL_LARGE
33355 && rs6000_global_entry_point_prologue_needed_p ())
33359 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33361 fprintf (file, "\t.quad .TOC.-");
33362 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33363 assemble_name (file, buf);
33367 if (DEFAULT_ABI == ABI_AIX)
33369 const char *desc_name, *orig_name;
33371 orig_name = (*targetm.strip_name_encoding) (name);
33372 desc_name = orig_name;
33373 while (*desc_name == '.')
33376 if (TREE_PUBLIC (decl))
33377 fprintf (file, "\t.globl %s\n", desc_name);
33379 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33380 fprintf (file, "%s:\n", desc_name);
33381 fprintf (file, "\t.long %s\n", orig_name);
33382 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33383 fputs ("\t.long 0\n", file);
33384 fprintf (file, "\t.previous\n");
33386 ASM_OUTPUT_LABEL (file, name);
33389 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33391 rs6000_elf_file_end (void)
33393 #ifdef HAVE_AS_GNU_ATTRIBUTE
33394 /* ??? The value emitted depends on options active at file end.
33395 Assume anyone using #pragma or attributes that might change
33396 options knows what they are doing. */
33397 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33398 && rs6000_passes_float)
33402 if (TARGET_HARD_FLOAT)
33406 if (rs6000_passes_long_double)
33408 if (!TARGET_LONG_DOUBLE_128)
33410 else if (TARGET_IEEEQUAD)
33415 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33417 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33419 if (rs6000_passes_vector)
33420 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33421 (TARGET_ALTIVEC_ABI ? 2 : 1));
33422 if (rs6000_returns_struct)
33423 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33424 aix_struct_return ? 2 : 1);
33427 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33428 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33429 file_end_indicate_exec_stack ();
33432 if (flag_split_stack)
33433 file_end_indicate_split_stack ();
33437 /* We have expanded a CPU builtin, so we need to emit a reference to
33438 the special symbol that LIBC uses to declare it supports the
33439 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33440 switch_to_section (data_section);
33441 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33442 fprintf (asm_out_file, "\t%s %s\n",
33443 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33450 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33451 #define HAVE_XCOFF_DWARF_EXTRAS 0
33454 static enum unwind_info_type
33455 rs6000_xcoff_debug_unwind_info (void)
33461 rs6000_xcoff_asm_output_anchor (rtx symbol)
33465 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33466 SYMBOL_REF_BLOCK_OFFSET (symbol));
33467 fprintf (asm_out_file, "%s", SET_ASM_OP);
33468 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33469 fprintf (asm_out_file, ",");
33470 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33471 fprintf (asm_out_file, "\n");
33475 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33477 fputs (GLOBAL_ASM_OP, stream);
33478 RS6000_OUTPUT_BASENAME (stream, name);
33479 putc ('\n', stream);
33482 /* A get_unnamed_decl callback, used for read-only sections. PTR
33483 points to the section string variable. */
33486 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33488 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33489 *(const char *const *) directive,
33490 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33493 /* Likewise for read-write sections. */
33496 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33498 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33499 *(const char *const *) directive,
33500 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33504 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33506 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33507 *(const char *const *) directive,
33508 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33511 /* A get_unnamed_section callback, used for switching to toc_section. */
33514 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33516 if (TARGET_MINIMAL_TOC)
33518 /* toc_section is always selected at least once from
33519 rs6000_xcoff_file_start, so this is guaranteed to
33520 always be defined once and only once in each file. */
33521 if (!toc_initialized)
33523 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33524 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33525 toc_initialized = 1;
33527 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33528 (TARGET_32BIT ? "" : ",3"));
33531 fputs ("\t.toc\n", asm_out_file);
33534 /* Implement TARGET_ASM_INIT_SECTIONS. */
33537 rs6000_xcoff_asm_init_sections (void)
33539 read_only_data_section
33540 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33541 &xcoff_read_only_section_name);
33543 private_data_section
33544 = get_unnamed_section (SECTION_WRITE,
33545 rs6000_xcoff_output_readwrite_section_asm_op,
33546 &xcoff_private_data_section_name);
33548 read_only_private_data_section
33549 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33550 &xcoff_private_rodata_section_name);
33553 = get_unnamed_section (SECTION_TLS,
33554 rs6000_xcoff_output_tls_section_asm_op,
33555 &xcoff_tls_data_section_name);
33557 tls_private_data_section
33558 = get_unnamed_section (SECTION_TLS,
33559 rs6000_xcoff_output_tls_section_asm_op,
33560 &xcoff_private_data_section_name);
33563 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33565 readonly_data_section = read_only_data_section;
33569 rs6000_xcoff_reloc_rw_mask (void)
33575 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33576 tree decl ATTRIBUTE_UNUSED)
33579 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33581 if (flags & SECTION_EXCLUDE)
33583 else if (flags & SECTION_DEBUG)
33585 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33588 else if (flags & SECTION_CODE)
33590 else if (flags & SECTION_TLS)
33592 else if (flags & SECTION_WRITE)
33597 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33598 (flags & SECTION_CODE) ? "." : "",
33599 name, suffix[smclass], flags & SECTION_ENTSIZE);
33602 #define IN_NAMED_SECTION(DECL) \
33603 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33604 && DECL_SECTION_NAME (DECL) != NULL)
33607 rs6000_xcoff_select_section (tree decl, int reloc,
33608 unsigned HOST_WIDE_INT align)
33610 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33612 if (align > BIGGEST_ALIGNMENT)
33614 resolve_unique_section (decl, reloc, true);
33615 if (IN_NAMED_SECTION (decl))
33616 return get_named_section (decl, NULL, reloc);
33619 if (decl_readonly_section (decl, reloc))
33621 if (TREE_PUBLIC (decl))
33622 return read_only_data_section;
33624 return read_only_private_data_section;
33629 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33631 if (TREE_PUBLIC (decl))
33632 return tls_data_section;
33633 else if (bss_initializer_p (decl))
33635 /* Convert to COMMON to emit in BSS. */
33636 DECL_COMMON (decl) = 1;
33637 return tls_comm_section;
33640 return tls_private_data_section;
33644 if (TREE_PUBLIC (decl))
33645 return data_section;
33647 return private_data_section;
33652 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33656 /* Use select_section for private data and uninitialized data with
33657 alignment <= BIGGEST_ALIGNMENT. */
33658 if (!TREE_PUBLIC (decl)
33659 || DECL_COMMON (decl)
33660 || (DECL_INITIAL (decl) == NULL_TREE
33661 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33662 || DECL_INITIAL (decl) == error_mark_node
33663 || (flag_zero_initialized_in_bss
33664 && initializer_zerop (DECL_INITIAL (decl))))
33667 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33668 name = (*targetm.strip_name_encoding) (name);
33669 set_decl_section_name (decl, name);
33672 /* Select section for constant in constant pool.
33674 On RS/6000, all constants are in the private read-only data area.
33675 However, if this is being placed in the TOC it must be output as a
33679 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33680 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33682 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33683 return toc_section;
33685 return read_only_private_data_section;
33688 /* Remove any trailing [DS] or the like from the symbol name. */
33690 static const char *
33691 rs6000_xcoff_strip_name_encoding (const char *name)
33696 len = strlen (name);
33697 if (name[len - 1] == ']')
33698 return ggc_alloc_string (name, len - 4);
33703 /* Section attributes. AIX is always PIC. */
33705 static unsigned int
33706 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33708 unsigned int align;
33709 unsigned int flags = default_section_type_flags (decl, name, reloc);
33711 /* Align to at least UNIT size. */
33712 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33713 align = MIN_UNITS_PER_WORD;
33715 /* Increase alignment of large objects if not already stricter. */
33716 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33717 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33718 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33720 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33723 /* Output at beginning of assembler file.
33725 Initialize the section names for the RS/6000 at this point.
33727 Specify filename, including full path, to assembler.
33729 We want to go into the TOC section so at least one .toc will be emitted.
33730 Also, in order to output proper .bs/.es pairs, we need at least one static
33731 [RW] section emitted.
33733 Finally, declare mcount when profiling to make the assembler happy. */
33736 rs6000_xcoff_file_start (void)
33738 rs6000_gen_section_name (&xcoff_bss_section_name,
33739 main_input_filename, ".bss_");
33740 rs6000_gen_section_name (&xcoff_private_data_section_name,
33741 main_input_filename, ".rw_");
33742 rs6000_gen_section_name (&xcoff_private_rodata_section_name,
33743 main_input_filename, ".rop_");
33744 rs6000_gen_section_name (&xcoff_read_only_section_name,
33745 main_input_filename, ".ro_");
33746 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33747 main_input_filename, ".tls_");
33748 rs6000_gen_section_name (&xcoff_tbss_section_name,
33749 main_input_filename, ".tbss_[UL]");
33751 fputs ("\t.file\t", asm_out_file);
33752 output_quoted_string (asm_out_file, main_input_filename);
33753 fputc ('\n', asm_out_file);
33754 if (write_symbols != NO_DEBUG)
33755 switch_to_section (private_data_section);
33756 switch_to_section (toc_section);
33757 switch_to_section (text_section);
33759 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33760 rs6000_file_start ();
33763 /* Output at end of assembler file.
33764 On the RS/6000, referencing data should automatically pull in text. */
33767 rs6000_xcoff_file_end (void)
33769 switch_to_section (text_section);
33770 fputs ("_section_.text:\n", asm_out_file);
33771 switch_to_section (data_section);
33772 fputs (TARGET_32BIT
33773 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33777 struct declare_alias_data
33780 bool function_descriptor;
33783 /* Declare alias N. A helper function for for_node_and_aliases. */
33786 rs6000_declare_alias (struct symtab_node *n, void *d)
33788 struct declare_alias_data *data = (struct declare_alias_data *)d;
33789 /* Main symbol is output specially, because varasm machinery does part of
33790 the job for us - we do not need to declare .globl/lglobs and such. */
33791 if (!n->alias || n->weakref)
33794 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33797 /* Prevent assemble_alias from trying to use .set pseudo operation
33798 that does not behave as expected by the middle-end. */
33799 TREE_ASM_WRITTEN (n->decl) = true;
33801 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33802 char *buffer = (char *) alloca (strlen (name) + 2);
33804 int dollar_inside = 0;
33806 strcpy (buffer, name);
33807 p = strchr (buffer, '$');
33811 p = strchr (p + 1, '$');
33813 if (TREE_PUBLIC (n->decl))
33815 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33817 if (dollar_inside) {
33818 if (data->function_descriptor)
33819 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33820 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33822 if (data->function_descriptor)
33824 fputs ("\t.globl .", data->file);
33825 RS6000_OUTPUT_BASENAME (data->file, buffer);
33826 putc ('\n', data->file);
33828 fputs ("\t.globl ", data->file);
33829 RS6000_OUTPUT_BASENAME (data->file, buffer);
33830 putc ('\n', data->file);
33832 #ifdef ASM_WEAKEN_DECL
33833 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33834 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33841 if (data->function_descriptor)
33842 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33843 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33845 if (data->function_descriptor)
33847 fputs ("\t.lglobl .", data->file);
33848 RS6000_OUTPUT_BASENAME (data->file, buffer);
33849 putc ('\n', data->file);
33851 fputs ("\t.lglobl ", data->file);
33852 RS6000_OUTPUT_BASENAME (data->file, buffer);
33853 putc ('\n', data->file);
33855 if (data->function_descriptor)
33856 fputs (".", data->file);
33857 RS6000_OUTPUT_BASENAME (data->file, buffer);
33858 fputs (":\n", data->file);
33863 #ifdef HAVE_GAS_HIDDEN
33864 /* Helper function to calculate visibility of a DECL
33865 and return the value as a const string. */
33867 static const char *
33868 rs6000_xcoff_visibility (tree decl)
33870 static const char * const visibility_types[] = {
33871 "", ",protected", ",hidden", ",internal"
33874 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33875 return visibility_types[vis];
33880 /* This macro produces the initial definition of a function name.
33881 On the RS/6000, we need to place an extra '.' in the function name and
33882 output the function descriptor.
33883 Dollar signs are converted to underscores.
33885 The csect for the function will have already been created when
33886 text_section was selected. We do have to go back to that csect, however.
33888 The third and fourth parameters to the .function pseudo-op (16 and 044)
33889 are placeholders which no longer have any use.
33891 Because AIX assembler's .set command has unexpected semantics, we output
33892 all aliases as alternative labels in front of the definition. */
33895 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33897 char *buffer = (char *) alloca (strlen (name) + 1);
33899 int dollar_inside = 0;
33900 struct declare_alias_data data = {file, false};
33902 strcpy (buffer, name);
33903 p = strchr (buffer, '$');
33907 p = strchr (p + 1, '$');
33909 if (TREE_PUBLIC (decl))
33911 if (!RS6000_WEAK || !DECL_WEAK (decl))
33913 if (dollar_inside) {
33914 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33915 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33917 fputs ("\t.globl .", file);
33918 RS6000_OUTPUT_BASENAME (file, buffer);
33919 #ifdef HAVE_GAS_HIDDEN
33920 fputs (rs6000_xcoff_visibility (decl), file);
33927 if (dollar_inside) {
33928 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33929 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33931 fputs ("\t.lglobl .", file);
33932 RS6000_OUTPUT_BASENAME (file, buffer);
33935 fputs ("\t.csect ", file);
33936 RS6000_OUTPUT_BASENAME (file, buffer);
33937 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33938 RS6000_OUTPUT_BASENAME (file, buffer);
33939 fputs (":\n", file);
33940 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33942 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33943 RS6000_OUTPUT_BASENAME (file, buffer);
33944 fputs (", TOC[tc0], 0\n", file);
33946 switch_to_section (function_section (decl));
33948 RS6000_OUTPUT_BASENAME (file, buffer);
33949 fputs (":\n", file);
33950 data.function_descriptor = true;
33951 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33953 if (!DECL_IGNORED_P (decl))
33955 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33956 xcoffout_declare_function (file, decl, buffer);
33957 else if (write_symbols == DWARF2_DEBUG)
33959 name = (*targetm.strip_name_encoding) (name);
33960 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33967 /* Output assembly language to globalize a symbol from a DECL,
33968 possibly with visibility. */
33971 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33973 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33974 fputs (GLOBAL_ASM_OP, stream);
33975 RS6000_OUTPUT_BASENAME (stream, name);
33976 #ifdef HAVE_GAS_HIDDEN
33977 fputs (rs6000_xcoff_visibility (decl), stream);
33979 putc ('\n', stream);
33982 /* Output assembly language to define a symbol as COMMON from a DECL,
33983 possibly with visibility. */
33986 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33987 tree decl ATTRIBUTE_UNUSED,
33989 unsigned HOST_WIDE_INT size,
33990 unsigned HOST_WIDE_INT align)
33992 unsigned HOST_WIDE_INT align2 = 2;
33995 align2 = floor_log2 (align / BITS_PER_UNIT);
33999 fputs (COMMON_ASM_OP, stream);
34000 RS6000_OUTPUT_BASENAME (stream, name);
34003 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34006 #ifdef HAVE_GAS_HIDDEN
34008 fputs (rs6000_xcoff_visibility (decl), stream);
34010 putc ('\n', stream);
34013 /* This macro produces the initial definition of a object (variable) name.
34014 Because AIX assembler's .set command has unexpected semantics, we output
34015 all aliases as alternative labels in front of the definition. */
34018 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34020 struct declare_alias_data data = {file, false};
34021 RS6000_OUTPUT_BASENAME (file, name);
34022 fputs (":\n", file);
34023 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34027 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34030 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34032 fputs (integer_asm_op (size, FALSE), file);
34033 assemble_name (file, label);
34034 fputs ("-$", file);
34037 /* Output a symbol offset relative to the dbase for the current object.
34038 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34041 __gcc_unwind_dbase is embedded in all executables/libraries through
34042 libgcc/config/rs6000/crtdbase.S. */
34045 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34047 fputs (integer_asm_op (size, FALSE), file);
34048 assemble_name (file, label);
34049 fputs("-__gcc_unwind_dbase", file);
34054 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34058 const char *symname;
34060 default_encode_section_info (decl, rtl, first);
34062 /* Careful not to prod global register variables. */
34065 symbol = XEXP (rtl, 0);
34066 if (!SYMBOL_REF_P (symbol))
34069 flags = SYMBOL_REF_FLAGS (symbol);
34071 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34072 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34074 SYMBOL_REF_FLAGS (symbol) = flags;
34076 /* Append mapping class to extern decls. */
34077 symname = XSTR (symbol, 0);
34078 if (decl /* sync condition with assemble_external () */
34079 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34080 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34081 || TREE_CODE (decl) == FUNCTION_DECL)
34082 && symname[strlen (symname) - 1] != ']')
34084 char *newname = (char *) alloca (strlen (symname) + 5);
34085 strcpy (newname, symname);
34086 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34087 ? "[DS]" : "[UA]"));
34088 XSTR (symbol, 0) = ggc_strdup (newname);
34091 #endif /* HAVE_AS_TLS */
34092 #endif /* TARGET_XCOFF */
34095 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34096 const char *name, const char *val)
34098 fputs ("\t.weak\t", stream);
34099 RS6000_OUTPUT_BASENAME (stream, name);
34100 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34101 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34104 fputs ("[DS]", stream);
34105 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34107 fputs (rs6000_xcoff_visibility (decl), stream);
34109 fputs ("\n\t.weak\t.", stream);
34110 RS6000_OUTPUT_BASENAME (stream, name);
34112 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34114 fputs (rs6000_xcoff_visibility (decl), stream);
34116 fputc ('\n', stream);
34119 #ifdef ASM_OUTPUT_DEF
34120 ASM_OUTPUT_DEF (stream, name, val);
34122 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34123 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34125 fputs ("\t.set\t.", stream);
34126 RS6000_OUTPUT_BASENAME (stream, name);
34127 fputs (",.", stream);
34128 RS6000_OUTPUT_BASENAME (stream, val);
34129 fputc ('\n', stream);
34135 /* Return true if INSN should not be copied. */
34138 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34140 return recog_memoized (insn) >= 0
34141 && get_attr_cannot_copy (insn);
34144 /* Compute a (partial) cost for rtx X. Return true if the complete
34145 cost has been computed, and false if subexpressions should be
34146 scanned. In either case, *TOTAL contains the cost result. */
34149 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34150 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34152 int code = GET_CODE (x);
34156 /* On the RS/6000, if it is valid in the insn, it is free. */
34158 if (((outer_code == SET
34159 || outer_code == PLUS
34160 || outer_code == MINUS)
34161 && (satisfies_constraint_I (x)
34162 || satisfies_constraint_L (x)))
34163 || (outer_code == AND
34164 && (satisfies_constraint_K (x)
34166 ? satisfies_constraint_L (x)
34167 : satisfies_constraint_J (x))))
34168 || ((outer_code == IOR || outer_code == XOR)
34169 && (satisfies_constraint_K (x)
34171 ? satisfies_constraint_L (x)
34172 : satisfies_constraint_J (x))))
34173 || outer_code == ASHIFT
34174 || outer_code == ASHIFTRT
34175 || outer_code == LSHIFTRT
34176 || outer_code == ROTATE
34177 || outer_code == ROTATERT
34178 || outer_code == ZERO_EXTRACT
34179 || (outer_code == MULT
34180 && satisfies_constraint_I (x))
34181 || ((outer_code == DIV || outer_code == UDIV
34182 || outer_code == MOD || outer_code == UMOD)
34183 && exact_log2 (INTVAL (x)) >= 0)
34184 || (outer_code == COMPARE
34185 && (satisfies_constraint_I (x)
34186 || satisfies_constraint_K (x)))
34187 || ((outer_code == EQ || outer_code == NE)
34188 && (satisfies_constraint_I (x)
34189 || satisfies_constraint_K (x)
34191 ? satisfies_constraint_L (x)
34192 : satisfies_constraint_J (x))))
34193 || (outer_code == GTU
34194 && satisfies_constraint_I (x))
34195 || (outer_code == LTU
34196 && satisfies_constraint_P (x)))
34201 else if ((outer_code == PLUS
34202 && reg_or_add_cint_operand (x, VOIDmode))
34203 || (outer_code == MINUS
34204 && reg_or_sub_cint_operand (x, VOIDmode))
34205 || ((outer_code == SET
34206 || outer_code == IOR
34207 || outer_code == XOR)
34209 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34211 *total = COSTS_N_INSNS (1);
34217 case CONST_WIDE_INT:
34221 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34225 /* When optimizing for size, MEM should be slightly more expensive
34226 than generating address, e.g., (plus (reg) (const)).
34227 L1 cache latency is about two instructions. */
34228 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34229 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34230 *total += COSTS_N_INSNS (100);
34239 if (FLOAT_MODE_P (mode))
34240 *total = rs6000_cost->fp;
34242 *total = COSTS_N_INSNS (1);
34246 if (CONST_INT_P (XEXP (x, 1))
34247 && satisfies_constraint_I (XEXP (x, 1)))
34249 if (INTVAL (XEXP (x, 1)) >= -256
34250 && INTVAL (XEXP (x, 1)) <= 255)
34251 *total = rs6000_cost->mulsi_const9;
34253 *total = rs6000_cost->mulsi_const;
34255 else if (mode == SFmode)
34256 *total = rs6000_cost->fp;
34257 else if (FLOAT_MODE_P (mode))
34258 *total = rs6000_cost->dmul;
34259 else if (mode == DImode)
34260 *total = rs6000_cost->muldi;
34262 *total = rs6000_cost->mulsi;
34266 if (mode == SFmode)
34267 *total = rs6000_cost->fp;
34269 *total = rs6000_cost->dmul;
34274 if (FLOAT_MODE_P (mode))
34276 *total = mode == DFmode ? rs6000_cost->ddiv
34277 : rs6000_cost->sdiv;
34284 if (CONST_INT_P (XEXP (x, 1))
34285 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34287 if (code == DIV || code == MOD)
34289 *total = COSTS_N_INSNS (2);
34292 *total = COSTS_N_INSNS (1);
34296 if (GET_MODE (XEXP (x, 1)) == DImode)
34297 *total = rs6000_cost->divdi;
34299 *total = rs6000_cost->divsi;
34301 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34302 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34303 *total += COSTS_N_INSNS (2);
34307 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34311 *total = COSTS_N_INSNS (4);
34315 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34319 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34323 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34326 *total = COSTS_N_INSNS (1);
34330 if (CONST_INT_P (XEXP (x, 1)))
34332 rtx left = XEXP (x, 0);
34333 rtx_code left_code = GET_CODE (left);
34335 /* rotate-and-mask: 1 insn. */
34336 if ((left_code == ROTATE
34337 || left_code == ASHIFT
34338 || left_code == LSHIFTRT)
34339 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34341 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34342 if (!CONST_INT_P (XEXP (left, 1)))
34343 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34344 *total += COSTS_N_INSNS (1);
34348 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34349 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34350 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34351 || (val & 0xffff) == val
34352 || (val & 0xffff0000) == val
34353 || ((val & 0xffff) == 0 && mode == SImode))
34355 *total = rtx_cost (left, mode, AND, 0, speed);
34356 *total += COSTS_N_INSNS (1);
34361 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34363 *total = rtx_cost (left, mode, AND, 0, speed);
34364 *total += COSTS_N_INSNS (2);
34369 *total = COSTS_N_INSNS (1);
34374 *total = COSTS_N_INSNS (1);
34380 *total = COSTS_N_INSNS (1);
34384 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34385 the sign extend and shift separately within the insn. */
34386 if (TARGET_EXTSWSLI && mode == DImode
34387 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34388 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34399 /* Handle mul_highpart. */
34400 if (outer_code == TRUNCATE
34401 && GET_CODE (XEXP (x, 0)) == MULT)
34403 if (mode == DImode)
34404 *total = rs6000_cost->muldi;
34406 *total = rs6000_cost->mulsi;
34409 else if (outer_code == AND)
34412 *total = COSTS_N_INSNS (1);
34417 if (MEM_P (XEXP (x, 0)))
34420 *total = COSTS_N_INSNS (1);
34426 if (!FLOAT_MODE_P (mode))
34428 *total = COSTS_N_INSNS (1);
34434 case UNSIGNED_FLOAT:
34437 case FLOAT_TRUNCATE:
34438 *total = rs6000_cost->fp;
34442 if (mode == DFmode)
34443 *total = rs6000_cost->sfdf_convert;
34445 *total = rs6000_cost->fp;
34449 switch (XINT (x, 1))
34452 *total = rs6000_cost->fp;
34464 *total = COSTS_N_INSNS (1);
34467 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34469 *total = rs6000_cost->fp;
34478 /* Carry bit requires mode == Pmode.
34479 NEG or PLUS already counted so only add one. */
34481 && (outer_code == NEG || outer_code == PLUS))
34483 *total = COSTS_N_INSNS (1);
34491 if (outer_code == SET)
34493 if (XEXP (x, 1) == const0_rtx)
34495 *total = COSTS_N_INSNS (2);
34500 *total = COSTS_N_INSNS (3);
34505 if (outer_code == COMPARE)
34519 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34522 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34523 int opno, int *total, bool speed)
34525 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34528 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34529 "opno = %d, total = %d, speed = %s, x:\n",
34530 ret ? "complete" : "scan inner",
34531 GET_MODE_NAME (mode),
34532 GET_RTX_NAME (outer_code),
34535 speed ? "true" : "false");
34543 rs6000_insn_cost (rtx_insn *insn, bool speed)
34545 if (recog_memoized (insn) < 0)
34549 return get_attr_length (insn);
34551 int cost = get_attr_cost (insn);
34555 int n = get_attr_length (insn) / 4;
34556 enum attr_type type = get_attr_type (insn);
34563 cost = COSTS_N_INSNS (n + 1);
34567 switch (get_attr_size (insn))
34570 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34573 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34576 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34579 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34582 gcc_unreachable ();
34586 switch (get_attr_size (insn))
34589 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34592 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34595 gcc_unreachable ();
34600 cost = n * rs6000_cost->fp;
34603 cost = n * rs6000_cost->dmul;
34606 cost = n * rs6000_cost->sdiv;
34609 cost = n * rs6000_cost->ddiv;
34616 cost = COSTS_N_INSNS (n + 2);
34620 cost = COSTS_N_INSNS (n);
34626 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34629 rs6000_debug_address_cost (rtx x, machine_mode mode,
34630 addr_space_t as, bool speed)
34632 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34634 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34635 ret, speed ? "true" : "false");
34642 /* A C expression returning the cost of moving data from a register of class
34643 CLASS1 to one of CLASS2. */
34646 rs6000_register_move_cost (machine_mode mode,
34647 reg_class_t from, reg_class_t to)
34650 reg_class_t rclass;
34652 if (TARGET_DEBUG_COST)
34655 /* If we have VSX, we can easily move between FPR or Altivec registers,
34656 otherwise we can only easily move within classes.
34657 Do this first so we give best-case answers for union classes
34658 containing both gprs and vsx regs. */
34659 HARD_REG_SET to_vsx, from_vsx;
34660 COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
34661 AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
34662 COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
34663 AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
34664 if (!hard_reg_set_empty_p (to_vsx)
34665 && !hard_reg_set_empty_p (from_vsx)
34667 || hard_reg_set_intersect_p (to_vsx, from_vsx)))
34669 int reg = FIRST_FPR_REGNO;
34671 || (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
34672 && TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
34673 reg = FIRST_ALTIVEC_REGNO;
34674 ret = 2 * hard_regno_nregs (reg, mode);
34677 /* Moves from/to GENERAL_REGS. */
34678 else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
34679 || (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
34681 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34683 if (TARGET_DIRECT_MOVE)
34685 /* Keep the cost for direct moves above that for within
34686 a register class even if the actual processor cost is
34687 comparable. We do this because a direct move insn
34688 can't be a nop, whereas with ideal register
34689 allocation a move within the same class might turn
34690 out to be a nop. */
34691 if (rs6000_tune == PROCESSOR_POWER9
34692 || rs6000_tune == PROCESSOR_FUTURE)
34693 ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34695 ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34696 /* SFmode requires a conversion when moving between gprs
34698 if (mode == SFmode)
34702 ret = (rs6000_memory_move_cost (mode, rclass, false)
34703 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34706 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34708 else if (rclass == CR_REGS)
34711 /* For those processors that have slow LR/CTR moves, make them more
34712 expensive than memory in order to bias spills to memory .*/
34713 else if ((rs6000_tune == PROCESSOR_POWER6
34714 || rs6000_tune == PROCESSOR_POWER7
34715 || rs6000_tune == PROCESSOR_POWER8
34716 || rs6000_tune == PROCESSOR_POWER9)
34717 && reg_class_subset_p (rclass, SPECIAL_REGS))
34718 ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34721 /* A move will cost one instruction per GPR moved. */
34722 ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34725 /* Everything else has to go through GENERAL_REGS. */
34727 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34728 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34730 if (TARGET_DEBUG_COST)
34732 if (dbg_cost_ctrl == 1)
34734 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
34735 ret, GET_MODE_NAME (mode), reg_class_names[from],
34736 reg_class_names[to]);
34743 /* A C expressions returning the cost of moving data of MODE from a register to
34747 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34748 bool in ATTRIBUTE_UNUSED)
34752 if (TARGET_DEBUG_COST)
34755 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34756 ret = 4 * hard_regno_nregs (0, mode);
34757 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34758 || reg_classes_intersect_p (rclass, VSX_REGS)))
34759 ret = 4 * hard_regno_nregs (32, mode);
34760 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34761 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34763 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34765 if (TARGET_DEBUG_COST)
34767 if (dbg_cost_ctrl == 1)
34769 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34770 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34777 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
34779 The register allocator chooses GEN_OR_VSX_REGS for the allocno
34780 class if GENERAL_REGS and VSX_REGS cost is lower than the memory
34781 cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
34782 move cost between GENERAL_REGS and VSX_REGS low.
34784 It might seem reasonable to use a union class. After all, if usage
34785 of vsr is low and gpr high, it might make sense to spill gpr to vsr
34786 rather than memory. However, in cases where register pressure of
34787 both is high, like the cactus_adm spec test, allowing
34788 GEN_OR_VSX_REGS as the allocno class results in bad decisions in
34789 the first scheduling pass. This is partly due to an allocno of
34790 GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
34791 class, which gives too high a pressure for GENERAL_REGS and too low
34792 for VSX_REGS. So, force a choice of the subclass here.
34794 The best class is also the union if GENERAL_REGS and VSX_REGS have
34795 the same cost. In that case we do use GEN_OR_VSX_REGS as the
34796 allocno class, since trying to narrow down the class by regno mode
34797 is prone to error. For example, SImode is allowed in VSX regs and
34798 in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
34799 it would be wrong to choose an allocno of GENERAL_REGS based on
34803 rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
34804 reg_class_t allocno_class,
34805 reg_class_t best_class)
34807 switch (allocno_class)
34809 case GEN_OR_VSX_REGS:
34810 /* best_class must be a subset of allocno_class. */
34811 gcc_checking_assert (best_class == GEN_OR_VSX_REGS
34812 || best_class == GEN_OR_FLOAT_REGS
34813 || best_class == VSX_REGS
34814 || best_class == ALTIVEC_REGS
34815 || best_class == FLOAT_REGS
34816 || best_class == GENERAL_REGS
34817 || best_class == BASE_REGS);
34818 /* Use best_class but choose wider classes when copying from the
34819 wider class to best_class is cheap. This mimics IRA choice
34820 of allocno class. */
34821 if (best_class == BASE_REGS)
34822 return GENERAL_REGS;
34824 && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
34832 return allocno_class;
34835 /* Returns a code for a target-specific builtin that implements
34836 reciprocal of the function, or NULL_TREE if not available. */
34839 rs6000_builtin_reciprocal (tree fndecl)
34841 switch (DECL_FUNCTION_CODE (fndecl))
34843 case VSX_BUILTIN_XVSQRTDP:
34844 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34847 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34849 case VSX_BUILTIN_XVSQRTSP:
34850 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34853 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34860 /* Load up a constant. If the mode is a vector mode, splat the value across
34861 all of the vector elements. */
34864 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34868 if (mode == SFmode || mode == DFmode)
34870 rtx d = const_double_from_real_value (dconst, mode);
34871 reg = force_reg (mode, d);
34873 else if (mode == V4SFmode)
34875 rtx d = const_double_from_real_value (dconst, SFmode);
34876 rtvec v = gen_rtvec (4, d, d, d, d);
34877 reg = gen_reg_rtx (mode);
34878 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34880 else if (mode == V2DFmode)
34882 rtx d = const_double_from_real_value (dconst, DFmode);
34883 rtvec v = gen_rtvec (2, d, d);
34884 reg = gen_reg_rtx (mode);
34885 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34888 gcc_unreachable ();
34893 /* Generate an FMA instruction. */
34896 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34898 machine_mode mode = GET_MODE (target);
34901 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34902 gcc_assert (dst != NULL);
34905 emit_move_insn (target, dst);
34908 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34911 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34913 machine_mode mode = GET_MODE (dst);
34916 /* This is a tad more complicated, since the fnma_optab is for
34917 a different expression: fma(-m1, m2, a), which is the same
34918 thing except in the case of signed zeros.
34920 Fortunately we know that if FMA is supported that FNMSUB is
34921 also supported in the ISA. Just expand it directly. */
34923 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34925 r = gen_rtx_NEG (mode, a);
34926 r = gen_rtx_FMA (mode, m1, m2, r);
34927 r = gen_rtx_NEG (mode, r);
34928 emit_insn (gen_rtx_SET (dst, r));
34931 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34932 add a reg_note saying that this was a division. Support both scalar and
34933 vector divide. Assumes no trapping math and finite arguments. */
34936 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34938 machine_mode mode = GET_MODE (dst);
34939 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34942 /* Low precision estimates guarantee 5 bits of accuracy. High
34943 precision estimates guarantee 14 bits of accuracy. SFmode
34944 requires 23 bits of accuracy. DFmode requires 52 bits of
34945 accuracy. Each pass at least doubles the accuracy, leading
34946 to the following. */
34947 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34948 if (mode == DFmode || mode == V2DFmode)
34951 enum insn_code code = optab_handler (smul_optab, mode);
34952 insn_gen_fn gen_mul = GEN_FCN (code);
34954 gcc_assert (code != CODE_FOR_nothing);
34956 one = rs6000_load_constant_and_splat (mode, dconst1);
34958 /* x0 = 1./d estimate */
34959 x0 = gen_reg_rtx (mode);
34960 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34963 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34966 /* e0 = 1. - d * x0 */
34967 e0 = gen_reg_rtx (mode);
34968 rs6000_emit_nmsub (e0, d, x0, one);
34970 /* x1 = x0 + e0 * x0 */
34971 x1 = gen_reg_rtx (mode);
34972 rs6000_emit_madd (x1, e0, x0, x0);
34974 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34975 ++i, xprev = xnext, eprev = enext) {
34977 /* enext = eprev * eprev */
34978 enext = gen_reg_rtx (mode);
34979 emit_insn (gen_mul (enext, eprev, eprev));
34981 /* xnext = xprev + enext * xprev */
34982 xnext = gen_reg_rtx (mode);
34983 rs6000_emit_madd (xnext, enext, xprev, xprev);
34989 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34991 /* u = n * xprev */
34992 u = gen_reg_rtx (mode);
34993 emit_insn (gen_mul (u, n, xprev));
34995 /* v = n - (d * u) */
34996 v = gen_reg_rtx (mode);
34997 rs6000_emit_nmsub (v, d, u, n);
34999 /* dst = (v * xprev) + u */
35000 rs6000_emit_madd (dst, v, xprev, u);
35003 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35006 /* Goldschmidt's Algorithm for single/double-precision floating point
35007 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35010 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35012 machine_mode mode = GET_MODE (src);
35013 rtx e = gen_reg_rtx (mode);
35014 rtx g = gen_reg_rtx (mode);
35015 rtx h = gen_reg_rtx (mode);
35017 /* Low precision estimates guarantee 5 bits of accuracy. High
35018 precision estimates guarantee 14 bits of accuracy. SFmode
35019 requires 23 bits of accuracy. DFmode requires 52 bits of
35020 accuracy. Each pass at least doubles the accuracy, leading
35021 to the following. */
35022 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35023 if (mode == DFmode || mode == V2DFmode)
35028 enum insn_code code = optab_handler (smul_optab, mode);
35029 insn_gen_fn gen_mul = GEN_FCN (code);
35031 gcc_assert (code != CODE_FOR_nothing);
35033 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35035 /* e = rsqrt estimate */
35036 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35039 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35042 rtx zero = force_reg (mode, CONST0_RTX (mode));
35044 if (mode == SFmode)
35046 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35049 emit_move_insn (e, target);
35053 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35054 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35058 /* g = sqrt estimate. */
35059 emit_insn (gen_mul (g, e, src));
35060 /* h = 1/(2*sqrt) estimate. */
35061 emit_insn (gen_mul (h, e, mhalf));
35067 rtx t = gen_reg_rtx (mode);
35068 rs6000_emit_nmsub (t, g, h, mhalf);
35069 /* Apply correction directly to 1/rsqrt estimate. */
35070 rs6000_emit_madd (dst, e, t, e);
35074 for (i = 0; i < passes; i++)
35076 rtx t1 = gen_reg_rtx (mode);
35077 rtx g1 = gen_reg_rtx (mode);
35078 rtx h1 = gen_reg_rtx (mode);
35080 rs6000_emit_nmsub (t1, g, h, mhalf);
35081 rs6000_emit_madd (g1, g, t1, g);
35082 rs6000_emit_madd (h1, h, t1, h);
35087 /* Multiply by 2 for 1/rsqrt. */
35088 emit_insn (gen_add3_insn (dst, h, h));
35093 rtx t = gen_reg_rtx (mode);
35094 rs6000_emit_nmsub (t, g, h, mhalf);
35095 rs6000_emit_madd (dst, g, t, g);
35101 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35102 (Power7) targets. DST is the target, and SRC is the argument operand. */
35105 rs6000_emit_popcount (rtx dst, rtx src)
35107 machine_mode mode = GET_MODE (dst);
35110 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35111 if (TARGET_POPCNTD)
35113 if (mode == SImode)
35114 emit_insn (gen_popcntdsi2 (dst, src));
35116 emit_insn (gen_popcntddi2 (dst, src));
35120 tmp1 = gen_reg_rtx (mode);
35122 if (mode == SImode)
35124 emit_insn (gen_popcntbsi2 (tmp1, src));
35125 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35127 tmp2 = force_reg (SImode, tmp2);
35128 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35132 emit_insn (gen_popcntbdi2 (tmp1, src));
35133 tmp2 = expand_mult (DImode, tmp1,
35134 GEN_INT ((HOST_WIDE_INT)
35135 0x01010101 << 32 | 0x01010101),
35137 tmp2 = force_reg (DImode, tmp2);
35138 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35143 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35144 target, and SRC is the argument operand. */
35147 rs6000_emit_parity (rtx dst, rtx src)
35149 machine_mode mode = GET_MODE (dst);
35152 tmp = gen_reg_rtx (mode);
35154 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35157 if (mode == SImode)
35159 emit_insn (gen_popcntbsi2 (tmp, src));
35160 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35164 emit_insn (gen_popcntbdi2 (tmp, src));
35165 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35170 if (mode == SImode)
35172 /* Is mult+shift >= shift+xor+shift+xor? */
35173 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35175 rtx tmp1, tmp2, tmp3, tmp4;
35177 tmp1 = gen_reg_rtx (SImode);
35178 emit_insn (gen_popcntbsi2 (tmp1, src));
35180 tmp2 = gen_reg_rtx (SImode);
35181 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35182 tmp3 = gen_reg_rtx (SImode);
35183 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35185 tmp4 = gen_reg_rtx (SImode);
35186 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35187 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35190 rs6000_emit_popcount (tmp, src);
35191 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35195 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35196 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35198 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35200 tmp1 = gen_reg_rtx (DImode);
35201 emit_insn (gen_popcntbdi2 (tmp1, src));
35203 tmp2 = gen_reg_rtx (DImode);
35204 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35205 tmp3 = gen_reg_rtx (DImode);
35206 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35208 tmp4 = gen_reg_rtx (DImode);
35209 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35210 tmp5 = gen_reg_rtx (DImode);
35211 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35213 tmp6 = gen_reg_rtx (DImode);
35214 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35215 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35218 rs6000_emit_popcount (tmp, src);
35219 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35223 /* Expand an Altivec constant permutation for little endian mode.
35224 OP0 and OP1 are the input vectors and TARGET is the output vector.
35225 SEL specifies the constant permutation vector.
35227 There are two issues: First, the two input operands must be
35228 swapped so that together they form a double-wide array in LE
35229 order. Second, the vperm instruction has surprising behavior
35230 in LE mode: it interprets the elements of the source vectors
35231 in BE mode ("left to right") and interprets the elements of
35232 the destination vector in LE mode ("right to left"). To
35233 correct for this, we must subtract each element of the permute
35234 control vector from 31.
35236 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35237 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35238 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35239 serve as the permute control vector. Then, in BE mode,
35243 places the desired result in vr9. However, in LE mode the
35244 vector contents will be
35246 vr10 = 00000003 00000002 00000001 00000000
35247 vr11 = 00000007 00000006 00000005 00000004
35249 The result of the vperm using the same permute control vector is
35251 vr9 = 05000000 07000000 01000000 03000000
35253 That is, the leftmost 4 bytes of vr10 are interpreted as the
35254 source for the rightmost 4 bytes of vr9, and so on.
35256 If we change the permute control vector to
35258 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35266 vr9 = 00000006 00000004 00000002 00000000. */
35269 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35270 const vec_perm_indices &sel)
35274 rtx constv, unspec;
35276 /* Unpack and adjust the constant selector. */
35277 for (i = 0; i < 16; ++i)
35279 unsigned int elt = 31 - (sel[i] & 31);
35280 perm[i] = GEN_INT (elt);
35283 /* Expand to a permute, swapping the inputs and using the
35284 adjusted selector. */
35286 op0 = force_reg (V16QImode, op0);
35288 op1 = force_reg (V16QImode, op1);
35290 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35291 constv = force_reg (V16QImode, constv);
35292 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35294 if (!REG_P (target))
35296 rtx tmp = gen_reg_rtx (V16QImode);
35297 emit_move_insn (tmp, unspec);
35301 emit_move_insn (target, unspec);
35304 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35305 permute control vector. But here it's not a constant, so we must
35306 generate a vector NAND or NOR to do the adjustment. */
35309 altivec_expand_vec_perm_le (rtx operands[4])
35311 rtx notx, iorx, unspec;
35312 rtx target = operands[0];
35313 rtx op0 = operands[1];
35314 rtx op1 = operands[2];
35315 rtx sel = operands[3];
35317 rtx norreg = gen_reg_rtx (V16QImode);
35318 machine_mode mode = GET_MODE (target);
35320 /* Get everything in regs so the pattern matches. */
35322 op0 = force_reg (mode, op0);
35324 op1 = force_reg (mode, op1);
35326 sel = force_reg (V16QImode, sel);
35327 if (!REG_P (target))
35328 tmp = gen_reg_rtx (mode);
35330 if (TARGET_P9_VECTOR)
35332 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35337 /* Invert the selector with a VNAND if available, else a VNOR.
35338 The VNAND is preferred for future fusion opportunities. */
35339 notx = gen_rtx_NOT (V16QImode, sel);
35340 iorx = (TARGET_P8_VECTOR
35341 ? gen_rtx_IOR (V16QImode, notx, notx)
35342 : gen_rtx_AND (V16QImode, notx, notx));
35343 emit_insn (gen_rtx_SET (norreg, iorx));
35345 /* Permute with operands reversed and adjusted selector. */
35346 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35350 /* Copy into target, possibly by way of a register. */
35351 if (!REG_P (target))
35353 emit_move_insn (tmp, unspec);
35357 emit_move_insn (target, unspec);
35360 /* Expand an Altivec constant permutation. Return true if we match
35361 an efficient implementation; false to fall back to VPERM.
35363 OP0 and OP1 are the input vectors and TARGET is the output vector.
35364 SEL specifies the constant permutation vector. */
35367 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35368 const vec_perm_indices &sel)
35370 struct altivec_perm_insn {
35371 HOST_WIDE_INT mask;
35372 enum insn_code impl;
35373 unsigned char perm[16];
35375 static const struct altivec_perm_insn patterns[] = {
35376 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35377 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35378 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35379 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35380 { OPTION_MASK_ALTIVEC,
35381 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35382 : CODE_FOR_altivec_vmrglb_direct),
35383 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35384 { OPTION_MASK_ALTIVEC,
35385 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35386 : CODE_FOR_altivec_vmrglh_direct),
35387 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35388 { OPTION_MASK_ALTIVEC,
35389 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35390 : CODE_FOR_altivec_vmrglw_direct),
35391 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35392 { OPTION_MASK_ALTIVEC,
35393 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35394 : CODE_FOR_altivec_vmrghb_direct),
35395 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35396 { OPTION_MASK_ALTIVEC,
35397 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35398 : CODE_FOR_altivec_vmrghh_direct),
35399 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35400 { OPTION_MASK_ALTIVEC,
35401 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35402 : CODE_FOR_altivec_vmrghw_direct),
35403 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35404 { OPTION_MASK_P8_VECTOR,
35405 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35406 : CODE_FOR_p8_vmrgow_v4sf_direct),
35407 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35408 { OPTION_MASK_P8_VECTOR,
35409 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35410 : CODE_FOR_p8_vmrgew_v4sf_direct),
35411 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35414 unsigned int i, j, elt, which;
35415 unsigned char perm[16];
35419 /* Unpack the constant selector. */
35420 for (i = which = 0; i < 16; ++i)
35423 which |= (elt < 16 ? 1 : 2);
35427 /* Simplify the constant selector based on operands. */
35431 gcc_unreachable ();
35435 if (!rtx_equal_p (op0, op1))
35440 for (i = 0; i < 16; ++i)
35452 /* Look for splat patterns. */
35457 for (i = 0; i < 16; ++i)
35458 if (perm[i] != elt)
35462 if (!BYTES_BIG_ENDIAN)
35464 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35470 for (i = 0; i < 16; i += 2)
35471 if (perm[i] != elt || perm[i + 1] != elt + 1)
35475 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35476 x = gen_reg_rtx (V8HImode);
35477 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35479 emit_move_insn (target, gen_lowpart (V16QImode, x));
35486 for (i = 0; i < 16; i += 4)
35488 || perm[i + 1] != elt + 1
35489 || perm[i + 2] != elt + 2
35490 || perm[i + 3] != elt + 3)
35494 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35495 x = gen_reg_rtx (V4SImode);
35496 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35498 emit_move_insn (target, gen_lowpart (V16QImode, x));
35504 /* Look for merge and pack patterns. */
35505 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35509 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35512 elt = patterns[j].perm[0];
35513 if (perm[0] == elt)
35515 else if (perm[0] == elt + 16)
35519 for (i = 1; i < 16; ++i)
35521 elt = patterns[j].perm[i];
35523 elt = (elt >= 16 ? elt - 16 : elt + 16);
35524 else if (one_vec && elt >= 16)
35526 if (perm[i] != elt)
35531 enum insn_code icode = patterns[j].impl;
35532 machine_mode omode = insn_data[icode].operand[0].mode;
35533 machine_mode imode = insn_data[icode].operand[1].mode;
35535 /* For little-endian, don't use vpkuwum and vpkuhum if the
35536 underlying vector type is not V4SI and V8HI, respectively.
35537 For example, using vpkuwum with a V8HI picks up the even
35538 halfwords (BE numbering) when the even halfwords (LE
35539 numbering) are what we need. */
35540 if (!BYTES_BIG_ENDIAN
35541 && icode == CODE_FOR_altivec_vpkuwum_direct
35543 && GET_MODE (op0) != V4SImode)
35545 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35547 if (!BYTES_BIG_ENDIAN
35548 && icode == CODE_FOR_altivec_vpkuhum_direct
35550 && GET_MODE (op0) != V8HImode)
35552 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35555 /* For little-endian, the two input operands must be swapped
35556 (or swapped back) to ensure proper right-to-left numbering
35558 if (swapped ^ !BYTES_BIG_ENDIAN)
35559 std::swap (op0, op1);
35560 if (imode != V16QImode)
35562 op0 = gen_lowpart (imode, op0);
35563 op1 = gen_lowpart (imode, op1);
35565 if (omode == V16QImode)
35568 x = gen_reg_rtx (omode);
35569 emit_insn (GEN_FCN (icode) (x, op0, op1));
35570 if (omode != V16QImode)
35571 emit_move_insn (target, gen_lowpart (V16QImode, x));
35576 if (!BYTES_BIG_ENDIAN)
35578 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35585 /* Expand a VSX Permute Doubleword constant permutation.
35586 Return true if we match an efficient implementation. */
35589 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35590 unsigned char perm0, unsigned char perm1)
35594 /* If both selectors come from the same operand, fold to single op. */
35595 if ((perm0 & 2) == (perm1 & 2))
35602 /* If both operands are equal, fold to simpler permutation. */
35603 if (rtx_equal_p (op0, op1))
35606 perm1 = (perm1 & 1) + 2;
35608 /* If the first selector comes from the second operand, swap. */
35609 else if (perm0 & 2)
35615 std::swap (op0, op1);
35617 /* If the second selector does not come from the second operand, fail. */
35618 else if ((perm1 & 2) == 0)
35622 if (target != NULL)
35624 machine_mode vmode, dmode;
35627 vmode = GET_MODE (target);
35628 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35629 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35630 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35631 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35632 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35633 emit_insn (gen_rtx_SET (target, x));
35638 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35641 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35642 rtx op1, const vec_perm_indices &sel)
35644 bool testing_p = !target;
35646 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35647 if (TARGET_ALTIVEC && testing_p)
35650 /* Check for ps_merge* or xxpermdi insns. */
35651 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35655 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35656 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35658 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35662 if (TARGET_ALTIVEC)
35664 /* Force the target-independent code to lower to V16QImode. */
35665 if (vmode != V16QImode)
35667 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35674 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35675 OP0 and OP1 are the input vectors and TARGET is the output vector.
35676 PERM specifies the constant permutation vector. */
35679 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35680 machine_mode vmode, const vec_perm_builder &perm)
35682 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35684 emit_move_insn (target, x);
35687 /* Expand an extract even operation. */
35690 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35692 machine_mode vmode = GET_MODE (target);
35693 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35694 vec_perm_builder perm (nelt, nelt, 1);
35696 for (i = 0; i < nelt; i++)
35697 perm.quick_push (i * 2);
35699 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35702 /* Expand a vector interleave operation. */
35705 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35707 machine_mode vmode = GET_MODE (target);
35708 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35709 vec_perm_builder perm (nelt, nelt, 1);
35711 high = (highp ? 0 : nelt / 2);
35712 for (i = 0; i < nelt / 2; i++)
35714 perm.quick_push (i + high);
35715 perm.quick_push (i + nelt + high);
35718 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35721 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35723 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35725 HOST_WIDE_INT hwi_scale (scale);
35726 REAL_VALUE_TYPE r_pow;
35727 rtvec v = rtvec_alloc (2);
35729 rtx scale_vec = gen_reg_rtx (V2DFmode);
35730 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35731 elt = const_double_from_real_value (r_pow, DFmode);
35732 RTVEC_ELT (v, 0) = elt;
35733 RTVEC_ELT (v, 1) = elt;
35734 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35735 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35738 /* Return an RTX representing where to find the function value of a
35739 function returning MODE. */
35741 rs6000_complex_function_value (machine_mode mode)
35743 unsigned int regno;
35745 machine_mode inner = GET_MODE_INNER (mode);
35746 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35748 if (TARGET_FLOAT128_TYPE
35750 || (mode == TCmode && TARGET_IEEEQUAD)))
35751 regno = ALTIVEC_ARG_RETURN;
35753 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35754 regno = FP_ARG_RETURN;
35758 regno = GP_ARG_RETURN;
35760 /* 32-bit is OK since it'll go in r3/r4. */
35761 if (TARGET_32BIT && inner_bytes >= 4)
35762 return gen_rtx_REG (mode, regno);
35765 if (inner_bytes >= 8)
35766 return gen_rtx_REG (mode, regno);
35768 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35770 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35771 GEN_INT (inner_bytes));
35772 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35775 /* Return an rtx describing a return value of MODE as a PARALLEL
35776 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35777 stride REG_STRIDE. */
35780 rs6000_parallel_return (machine_mode mode,
35781 int n_elts, machine_mode elt_mode,
35782 unsigned int regno, unsigned int reg_stride)
35784 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35787 for (i = 0; i < n_elts; i++)
35789 rtx r = gen_rtx_REG (elt_mode, regno);
35790 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35791 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35792 regno += reg_stride;
35798 /* Target hook for TARGET_FUNCTION_VALUE.
35800 An integer value is in r3 and a floating-point value is in fp1,
35801 unless -msoft-float. */
35804 rs6000_function_value (const_tree valtype,
35805 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35806 bool outgoing ATTRIBUTE_UNUSED)
35809 unsigned int regno;
35810 machine_mode elt_mode;
35813 /* Special handling for structs in darwin64. */
35815 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35817 CUMULATIVE_ARGS valcum;
35821 valcum.fregno = FP_ARG_MIN_REG;
35822 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35823 /* Do a trial code generation as if this were going to be passed as
35824 an argument; if any part goes in memory, we return NULL. */
35825 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35828 /* Otherwise fall through to standard ABI rules. */
35831 mode = TYPE_MODE (valtype);
35833 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35834 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35836 int first_reg, n_regs;
35838 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35840 /* _Decimal128 must use even/odd register pairs. */
35841 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35842 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35846 first_reg = ALTIVEC_ARG_RETURN;
35850 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35853 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35854 if (TARGET_32BIT && TARGET_POWERPC64)
35863 int count = GET_MODE_SIZE (mode) / 4;
35864 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35867 if ((INTEGRAL_TYPE_P (valtype)
35868 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35869 || POINTER_TYPE_P (valtype))
35870 mode = TARGET_32BIT ? SImode : DImode;
35872 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35873 /* _Decimal128 must use an even/odd register pair. */
35874 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35875 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35876 && !FLOAT128_VECTOR_P (mode))
35877 regno = FP_ARG_RETURN;
35878 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35879 && targetm.calls.split_complex_arg)
35880 return rs6000_complex_function_value (mode);
35881 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35882 return register is used in both cases, and we won't see V2DImode/V2DFmode
35883 for pure altivec, combine the two cases. */
35884 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35885 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35886 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35887 regno = ALTIVEC_ARG_RETURN;
35889 regno = GP_ARG_RETURN;
35891 return gen_rtx_REG (mode, regno);
35894 /* Define how to find the value returned by a library function
35895 assuming the value has mode MODE. */
35897 rs6000_libcall_value (machine_mode mode)
35899 unsigned int regno;
35901 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35902 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35903 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35905 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35906 /* _Decimal128 must use an even/odd register pair. */
35907 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35908 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35909 regno = FP_ARG_RETURN;
35910 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35911 return register is used in both cases, and we won't see V2DImode/V2DFmode
35912 for pure altivec, combine the two cases. */
35913 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35914 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35915 regno = ALTIVEC_ARG_RETURN;
35916 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35917 return rs6000_complex_function_value (mode);
35919 regno = GP_ARG_RETURN;
35921 return gen_rtx_REG (mode, regno);
35924 /* Compute register pressure classes. We implement the target hook to avoid
35925 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
35926 lead to incorrect estimates of number of available registers and therefor
35927 increased register pressure/spill. */
35929 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35934 pressure_classes[n++] = GENERAL_REGS;
35936 pressure_classes[n++] = VSX_REGS;
35939 if (TARGET_ALTIVEC)
35940 pressure_classes[n++] = ALTIVEC_REGS;
35941 if (TARGET_HARD_FLOAT)
35942 pressure_classes[n++] = FLOAT_REGS;
35944 pressure_classes[n++] = CR_REGS;
35945 pressure_classes[n++] = SPECIAL_REGS;
35950 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35951 Frame pointer elimination is automatically handled.
35953 For the RS/6000, if frame pointer elimination is being done, we would like
35954 to convert ap into fp, not sp.
35956 We need r30 if -mminimal-toc was specified, and there are constant pool
35960 rs6000_can_eliminate (const int from, const int to)
35962 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35963 ? ! frame_pointer_needed
35964 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35965 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35966 || constant_pool_empty_p ()
35970 /* Define the offset between two registers, FROM to be eliminated and its
35971 replacement TO, at the start of a routine. */
35973 rs6000_initial_elimination_offset (int from, int to)
35975 rs6000_stack_t *info = rs6000_stack_info ();
35976 HOST_WIDE_INT offset;
35978 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35979 offset = info->push_p ? 0 : -info->total_size;
35980 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35982 offset = info->push_p ? 0 : -info->total_size;
35983 if (FRAME_GROWS_DOWNWARD)
35984 offset += info->fixed_size + info->vars_size + info->parm_size;
35986 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35987 offset = FRAME_GROWS_DOWNWARD
35988 ? info->fixed_size + info->vars_size + info->parm_size
35990 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35991 offset = info->total_size;
35992 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35993 offset = info->push_p ? info->total_size : 0;
35994 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35997 gcc_unreachable ();
36002 /* Fill in sizes of registers used by unwinder. */
36005 rs6000_init_dwarf_reg_sizes_extra (tree address)
36007 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36010 machine_mode mode = TYPE_MODE (char_type_node);
36011 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36012 rtx mem = gen_rtx_MEM (BLKmode, addr);
36013 rtx value = gen_int_mode (16, mode);
36015 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36016 The unwinder still needs to know the size of Altivec registers. */
36018 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36020 int column = DWARF_REG_TO_UNWIND_COLUMN
36021 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36022 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36024 emit_move_insn (adjust_address (mem, mode, offset), value);
36029 /* Map internal gcc register numbers to debug format register numbers.
36030 FORMAT specifies the type of debug register number to use:
36031 0 -- debug information, except for frame-related sections
36032 1 -- DWARF .debug_frame section
36033 2 -- DWARF .eh_frame section */
36036 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36038 /* On some platforms, we use the standard DWARF register
36039 numbering for .debug_info and .debug_frame. */
36040 if ((format == 0 && write_symbols == DWARF2_DEBUG) || format == 1)
36042 #ifdef RS6000_USE_DWARF_NUMBERING
36045 if (FP_REGNO_P (regno))
36046 return regno - FIRST_FPR_REGNO + 32;
36047 if (ALTIVEC_REGNO_P (regno))
36048 return regno - FIRST_ALTIVEC_REGNO + 1124;
36049 if (regno == LR_REGNO)
36051 if (regno == CTR_REGNO)
36053 if (regno == CA_REGNO)
36054 return 101; /* XER */
36055 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36056 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36057 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36058 to the DWARF reg for CR. */
36059 if (format == 1 && regno == CR2_REGNO)
36061 if (CR_REGNO_P (regno))
36062 return regno - CR0_REGNO + 86;
36063 if (regno == VRSAVE_REGNO)
36065 if (regno == VSCR_REGNO)
36068 /* These do not make much sense. */
36069 if (regno == FRAME_POINTER_REGNUM)
36071 if (regno == ARG_POINTER_REGNUM)
36076 gcc_unreachable ();
36080 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36081 information, and also for .eh_frame. */
36082 /* Translate the regnos to their numbers in GCC 7 (and before). */
36085 if (FP_REGNO_P (regno))
36086 return regno - FIRST_FPR_REGNO + 32;
36087 if (ALTIVEC_REGNO_P (regno))
36088 return regno - FIRST_ALTIVEC_REGNO + 77;
36089 if (regno == LR_REGNO)
36091 if (regno == CTR_REGNO)
36093 if (regno == CA_REGNO)
36094 return 76; /* XER */
36095 if (CR_REGNO_P (regno))
36096 return regno - CR0_REGNO + 68;
36097 if (regno == VRSAVE_REGNO)
36099 if (regno == VSCR_REGNO)
36102 if (regno == FRAME_POINTER_REGNUM)
36104 if (regno == ARG_POINTER_REGNUM)
36109 gcc_unreachable ();
36112 /* target hook eh_return_filter_mode */
36113 static scalar_int_mode
36114 rs6000_eh_return_filter_mode (void)
36116 return TARGET_32BIT ? SImode : word_mode;
36119 /* Target hook for translate_mode_attribute. */
36120 static machine_mode
36121 rs6000_translate_mode_attribute (machine_mode mode)
36123 if ((FLOAT128_IEEE_P (mode)
36124 && ieee128_float_type_node == long_double_type_node)
36125 || (FLOAT128_IBM_P (mode)
36126 && ibm128_float_type_node == long_double_type_node))
36127 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
36131 /* Target hook for scalar_mode_supported_p. */
36133 rs6000_scalar_mode_supported_p (scalar_mode mode)
36135 /* -m32 does not support TImode. This is the default, from
36136 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36137 same ABI as for -m32. But default_scalar_mode_supported_p allows
36138 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36139 for -mpowerpc64. */
36140 if (TARGET_32BIT && mode == TImode)
36143 if (DECIMAL_FLOAT_MODE_P (mode))
36144 return default_decimal_float_supported_p ();
36145 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36148 return default_scalar_mode_supported_p (mode);
36151 /* Target hook for vector_mode_supported_p. */
36153 rs6000_vector_mode_supported_p (machine_mode mode)
36155 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36156 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36158 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36165 /* Target hook for floatn_mode. */
36166 static opt_scalar_float_mode
36167 rs6000_floatn_mode (int n, bool extended)
36177 if (TARGET_FLOAT128_TYPE)
36178 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36180 return opt_scalar_float_mode ();
36183 return opt_scalar_float_mode ();
36186 /* Those are the only valid _FloatNx types. */
36187 gcc_unreachable ();
36201 if (TARGET_FLOAT128_TYPE)
36202 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36204 return opt_scalar_float_mode ();
36207 return opt_scalar_float_mode ();
36213 /* Target hook for c_mode_for_suffix. */
36214 static machine_mode
36215 rs6000_c_mode_for_suffix (char suffix)
36217 if (TARGET_FLOAT128_TYPE)
36219 if (suffix == 'q' || suffix == 'Q')
36220 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36222 /* At the moment, we are not defining a suffix for IBM extended double.
36223 If/when the default for -mabi=ieeelongdouble is changed, and we want
36224 to support __ibm128 constants in legacy library code, we may need to
36225 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36226 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36227 __float80 constants. */
36233 /* Target hook for invalid_arg_for_unprototyped_fn. */
36234 static const char *
36235 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36237 return (!rs6000_darwin64_abi
36239 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36240 && (funcdecl == NULL_TREE
36241 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36242 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36243 ? N_("AltiVec argument passed to unprototyped function")
36247 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36248 setup by using __stack_chk_fail_local hidden function instead of
36249 calling __stack_chk_fail directly. Otherwise it is better to call
36250 __stack_chk_fail directly. */
36252 static tree ATTRIBUTE_UNUSED
36253 rs6000_stack_protect_fail (void)
36255 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36256 ? default_hidden_stack_protect_fail ()
36257 : default_external_stack_protect_fail ();
36260 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36263 static unsigned HOST_WIDE_INT
36264 rs6000_asan_shadow_offset (void)
36266 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36270 /* Mask options that we want to support inside of attribute((target)) and
36271 #pragma GCC target operations. Note, we do not include things like
36272 64/32-bit, endianness, hard/soft floating point, etc. that would have
36273 different calling sequences. */
36275 struct rs6000_opt_mask {
36276 const char *name; /* option name */
36277 HOST_WIDE_INT mask; /* mask to set */
36278 bool invert; /* invert sense of mask */
36279 bool valid_target; /* option is a target option */
36282 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36284 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36285 { "cmpb", OPTION_MASK_CMPB, false, true },
36286 { "crypto", OPTION_MASK_CRYPTO, false, true },
36287 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36288 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36289 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36291 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36292 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36293 { "fprnd", OPTION_MASK_FPRND, false, true },
36294 { "future", OPTION_MASK_FUTURE, false, true },
36295 { "hard-dfp", OPTION_MASK_DFP, false, true },
36296 { "htm", OPTION_MASK_HTM, false, true },
36297 { "isel", OPTION_MASK_ISEL, false, true },
36298 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36299 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36300 { "modulo", OPTION_MASK_MODULO, false, true },
36301 { "mulhw", OPTION_MASK_MULHW, false, true },
36302 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36303 { "pcrel", OPTION_MASK_PCREL, false, true },
36304 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36305 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36306 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36307 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36308 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36309 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36310 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36311 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36312 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36313 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36314 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36315 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36316 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36317 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36318 { "string", 0, false, true },
36319 { "update", OPTION_MASK_NO_UPDATE, true , true },
36320 { "vsx", OPTION_MASK_VSX, false, true },
36321 #ifdef OPTION_MASK_64BIT
36323 { "aix64", OPTION_MASK_64BIT, false, false },
36324 { "aix32", OPTION_MASK_64BIT, true, false },
36326 { "64", OPTION_MASK_64BIT, false, false },
36327 { "32", OPTION_MASK_64BIT, true, false },
36330 #ifdef OPTION_MASK_EABI
36331 { "eabi", OPTION_MASK_EABI, false, false },
36333 #ifdef OPTION_MASK_LITTLE_ENDIAN
36334 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36335 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36337 #ifdef OPTION_MASK_RELOCATABLE
36338 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36340 #ifdef OPTION_MASK_STRICT_ALIGN
36341 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36343 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36344 { "string", 0, false, false },
36347 /* Builtin mask mapping for printing the flags. */
36348 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36350 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36351 { "vsx", RS6000_BTM_VSX, false, false },
36352 { "fre", RS6000_BTM_FRE, false, false },
36353 { "fres", RS6000_BTM_FRES, false, false },
36354 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36355 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36356 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36357 { "cell", RS6000_BTM_CELL, false, false },
36358 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36359 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36360 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36361 { "crypto", RS6000_BTM_CRYPTO, false, false },
36362 { "htm", RS6000_BTM_HTM, false, false },
36363 { "hard-dfp", RS6000_BTM_DFP, false, false },
36364 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36365 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36366 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36367 { "float128", RS6000_BTM_FLOAT128, false, false },
36368 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36371 /* Option variables that we want to support inside attribute((target)) and
36372 #pragma GCC target operations. */
36374 struct rs6000_opt_var {
36375 const char *name; /* option name */
36376 size_t global_offset; /* offset of the option in global_options. */
36377 size_t target_offset; /* offset of the option in target options. */
36380 static struct rs6000_opt_var const rs6000_opt_vars[] =
36383 offsetof (struct gcc_options, x_TARGET_FRIZ),
36384 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36385 { "avoid-indexed-addresses",
36386 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36387 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36389 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36390 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36391 { "optimize-swaps",
36392 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36393 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36394 { "allow-movmisalign",
36395 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36396 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36398 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36399 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36401 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36402 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36403 { "align-branch-targets",
36404 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36405 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36407 offsetof (struct gcc_options, x_tls_markers),
36408 offsetof (struct cl_target_option, x_tls_markers), },
36410 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36411 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36413 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36414 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36415 { "speculate-indirect-jumps",
36416 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36417 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36420 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36421 parsing. Return true if there were no errors. */
36424 rs6000_inner_target_options (tree args, bool attr_p)
36428 if (args == NULL_TREE)
36431 else if (TREE_CODE (args) == STRING_CST)
36433 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36436 while ((q = strtok (p, ",")) != NULL)
36438 bool error_p = false;
36439 bool not_valid_p = false;
36440 const char *cpu_opt = NULL;
36443 if (strncmp (q, "cpu=", 4) == 0)
36445 int cpu_index = rs6000_cpu_name_lookup (q+4);
36446 if (cpu_index >= 0)
36447 rs6000_cpu_index = cpu_index;
36454 else if (strncmp (q, "tune=", 5) == 0)
36456 int tune_index = rs6000_cpu_name_lookup (q+5);
36457 if (tune_index >= 0)
36458 rs6000_tune_index = tune_index;
36468 bool invert = false;
36472 if (strncmp (r, "no-", 3) == 0)
36478 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36479 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36481 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36483 if (!rs6000_opt_masks[i].valid_target)
36484 not_valid_p = true;
36488 rs6000_isa_flags_explicit |= mask;
36490 /* VSX needs altivec, so -mvsx automagically sets
36491 altivec and disables -mavoid-indexed-addresses. */
36494 if (mask == OPTION_MASK_VSX)
36496 mask |= OPTION_MASK_ALTIVEC;
36497 TARGET_AVOID_XFORM = 0;
36501 if (rs6000_opt_masks[i].invert)
36505 rs6000_isa_flags &= ~mask;
36507 rs6000_isa_flags |= mask;
36512 if (error_p && !not_valid_p)
36514 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36515 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36517 size_t j = rs6000_opt_vars[i].global_offset;
36518 *((int *) ((char *)&global_options + j)) = !invert;
36520 not_valid_p = false;
36528 const char *eprefix, *esuffix;
36533 eprefix = "__attribute__((__target__(";
36538 eprefix = "#pragma GCC target ";
36543 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36545 else if (not_valid_p)
36546 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36548 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36553 else if (TREE_CODE (args) == TREE_LIST)
36557 tree value = TREE_VALUE (args);
36560 bool ret2 = rs6000_inner_target_options (value, attr_p);
36564 args = TREE_CHAIN (args);
36566 while (args != NULL_TREE);
36571 error ("attribute %<target%> argument not a string");
36578 /* Print out the target options as a list for -mdebug=target. */
36581 rs6000_debug_target_options (tree args, const char *prefix)
36583 if (args == NULL_TREE)
36584 fprintf (stderr, "%s<NULL>", prefix);
36586 else if (TREE_CODE (args) == STRING_CST)
36588 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36591 while ((q = strtok (p, ",")) != NULL)
36594 fprintf (stderr, "%s\"%s\"", prefix, q);
36599 else if (TREE_CODE (args) == TREE_LIST)
36603 tree value = TREE_VALUE (args);
36606 rs6000_debug_target_options (value, prefix);
36609 args = TREE_CHAIN (args);
36611 while (args != NULL_TREE);
36615 gcc_unreachable ();
36621 /* Hook to validate attribute((target("..."))). */
36624 rs6000_valid_attribute_p (tree fndecl,
36625 tree ARG_UNUSED (name),
36629 struct cl_target_option cur_target;
36632 tree new_target, new_optimize;
36633 tree func_optimize;
36635 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36637 if (TARGET_DEBUG_TARGET)
36639 tree tname = DECL_NAME (fndecl);
36640 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36642 fprintf (stderr, "function: %.*s\n",
36643 (int) IDENTIFIER_LENGTH (tname),
36644 IDENTIFIER_POINTER (tname));
36646 fprintf (stderr, "function: unknown\n");
36648 fprintf (stderr, "args:");
36649 rs6000_debug_target_options (args, " ");
36650 fprintf (stderr, "\n");
36653 fprintf (stderr, "flags: 0x%x\n", flags);
36655 fprintf (stderr, "--------------------\n");
36658 /* attribute((target("default"))) does nothing, beyond
36659 affecting multi-versioning. */
36660 if (TREE_VALUE (args)
36661 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36662 && TREE_CHAIN (args) == NULL_TREE
36663 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36666 old_optimize = build_optimization_node (&global_options);
36667 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36669 /* If the function changed the optimization levels as well as setting target
36670 options, start with the optimizations specified. */
36671 if (func_optimize && func_optimize != old_optimize)
36672 cl_optimization_restore (&global_options,
36673 TREE_OPTIMIZATION (func_optimize));
36675 /* The target attributes may also change some optimization flags, so update
36676 the optimization options if necessary. */
36677 cl_target_option_save (&cur_target, &global_options);
36678 rs6000_cpu_index = rs6000_tune_index = -1;
36679 ret = rs6000_inner_target_options (args, true);
36681 /* Set up any additional state. */
36684 ret = rs6000_option_override_internal (false);
36685 new_target = build_target_option_node (&global_options);
36690 new_optimize = build_optimization_node (&global_options);
36697 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36699 if (old_optimize != new_optimize)
36700 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36703 cl_target_option_restore (&global_options, &cur_target);
36705 if (old_optimize != new_optimize)
36706 cl_optimization_restore (&global_options,
36707 TREE_OPTIMIZATION (old_optimize));
36713 /* Hook to validate the current #pragma GCC target and set the state, and
36714 update the macros based on what was changed. If ARGS is NULL, then
36715 POP_TARGET is used to reset the options. */
36718 rs6000_pragma_target_parse (tree args, tree pop_target)
36720 tree prev_tree = build_target_option_node (&global_options);
36722 struct cl_target_option *prev_opt, *cur_opt;
36723 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36724 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36726 if (TARGET_DEBUG_TARGET)
36728 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36729 fprintf (stderr, "args:");
36730 rs6000_debug_target_options (args, " ");
36731 fprintf (stderr, "\n");
36735 fprintf (stderr, "pop_target:\n");
36736 debug_tree (pop_target);
36739 fprintf (stderr, "pop_target: <NULL>\n");
36741 fprintf (stderr, "--------------------\n");
36746 cur_tree = ((pop_target)
36748 : target_option_default_node);
36749 cl_target_option_restore (&global_options,
36750 TREE_TARGET_OPTION (cur_tree));
36754 rs6000_cpu_index = rs6000_tune_index = -1;
36755 if (!rs6000_inner_target_options (args, false)
36756 || !rs6000_option_override_internal (false)
36757 || (cur_tree = build_target_option_node (&global_options))
36760 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36761 fprintf (stderr, "invalid pragma\n");
36767 target_option_current_node = cur_tree;
36768 rs6000_activate_target_options (target_option_current_node);
36770 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36771 change the macros that are defined. */
36772 if (rs6000_target_modify_macros_ptr)
36774 prev_opt = TREE_TARGET_OPTION (prev_tree);
36775 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36776 prev_flags = prev_opt->x_rs6000_isa_flags;
36778 cur_opt = TREE_TARGET_OPTION (cur_tree);
36779 cur_flags = cur_opt->x_rs6000_isa_flags;
36780 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36782 diff_bumask = (prev_bumask ^ cur_bumask);
36783 diff_flags = (prev_flags ^ cur_flags);
36785 if ((diff_flags != 0) || (diff_bumask != 0))
36787 /* Delete old macros. */
36788 rs6000_target_modify_macros_ptr (false,
36789 prev_flags & diff_flags,
36790 prev_bumask & diff_bumask);
36792 /* Define new macros. */
36793 rs6000_target_modify_macros_ptr (true,
36794 cur_flags & diff_flags,
36795 cur_bumask & diff_bumask);
36803 /* Remember the last target of rs6000_set_current_function. */
36804 static GTY(()) tree rs6000_previous_fndecl;
36806 /* Restore target's globals from NEW_TREE and invalidate the
36807 rs6000_previous_fndecl cache. */
36810 rs6000_activate_target_options (tree new_tree)
36812 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36813 if (TREE_TARGET_GLOBALS (new_tree))
36814 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36815 else if (new_tree == target_option_default_node)
36816 restore_target_globals (&default_target_globals);
36818 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36819 rs6000_previous_fndecl = NULL_TREE;
36822 /* Establish appropriate back-end context for processing the function
36823 FNDECL. The argument might be NULL to indicate processing at top
36824 level, outside of any function scope. */
36826 rs6000_set_current_function (tree fndecl)
36828 if (TARGET_DEBUG_TARGET)
36830 fprintf (stderr, "\n==================== rs6000_set_current_function");
36833 fprintf (stderr, ", fndecl %s (%p)",
36834 (DECL_NAME (fndecl)
36835 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36836 : "<unknown>"), (void *)fndecl);
36838 if (rs6000_previous_fndecl)
36839 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36841 fprintf (stderr, "\n");
36844 /* Only change the context if the function changes. This hook is called
36845 several times in the course of compiling a function, and we don't want to
36846 slow things down too much or call target_reinit when it isn't safe. */
36847 if (fndecl == rs6000_previous_fndecl)
36851 if (rs6000_previous_fndecl == NULL_TREE)
36852 old_tree = target_option_current_node;
36853 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36854 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36856 old_tree = target_option_default_node;
36859 if (fndecl == NULL_TREE)
36861 if (old_tree != target_option_current_node)
36862 new_tree = target_option_current_node;
36864 new_tree = NULL_TREE;
36868 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36869 if (new_tree == NULL_TREE)
36870 new_tree = target_option_default_node;
36873 if (TARGET_DEBUG_TARGET)
36877 fprintf (stderr, "\nnew fndecl target specific options:\n");
36878 debug_tree (new_tree);
36883 fprintf (stderr, "\nold fndecl target specific options:\n");
36884 debug_tree (old_tree);
36887 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36888 fprintf (stderr, "--------------------\n");
36891 if (new_tree && old_tree != new_tree)
36892 rs6000_activate_target_options (new_tree);
36895 rs6000_previous_fndecl = fndecl;
36899 /* Save the current options */
36902 rs6000_function_specific_save (struct cl_target_option *ptr,
36903 struct gcc_options *opts)
36905 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36906 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36909 /* Restore the current options */
36912 rs6000_function_specific_restore (struct gcc_options *opts,
36913 struct cl_target_option *ptr)
36916 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36917 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36918 (void) rs6000_option_override_internal (false);
36921 /* Print the current options */
36924 rs6000_function_specific_print (FILE *file, int indent,
36925 struct cl_target_option *ptr)
36927 rs6000_print_isa_options (file, indent, "Isa options set",
36928 ptr->x_rs6000_isa_flags);
36930 rs6000_print_isa_options (file, indent, "Isa options explicit",
36931 ptr->x_rs6000_isa_flags_explicit);
36934 /* Helper function to print the current isa or misc options on a line. */
36937 rs6000_print_options_internal (FILE *file,
36939 const char *string,
36940 HOST_WIDE_INT flags,
36941 const char *prefix,
36942 const struct rs6000_opt_mask *opts,
36943 size_t num_elements)
36946 size_t start_column = 0;
36948 size_t max_column = 120;
36949 size_t prefix_len = strlen (prefix);
36950 size_t comma_len = 0;
36951 const char *comma = "";
36954 start_column += fprintf (file, "%*s", indent, "");
36958 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36962 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36964 /* Print the various mask options. */
36965 cur_column = start_column;
36966 for (i = 0; i < num_elements; i++)
36968 bool invert = opts[i].invert;
36969 const char *name = opts[i].name;
36970 const char *no_str = "";
36971 HOST_WIDE_INT mask = opts[i].mask;
36972 size_t len = comma_len + prefix_len + strlen (name);
36976 if ((flags & mask) == 0)
36979 len += sizeof ("no-") - 1;
36987 if ((flags & mask) != 0)
36990 len += sizeof ("no-") - 1;
36997 if (cur_column > max_column)
36999 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37000 cur_column = start_column + len;
37004 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37006 comma_len = sizeof (", ") - 1;
37009 fputs ("\n", file);
37012 /* Helper function to print the current isa options on a line. */
37015 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37016 HOST_WIDE_INT flags)
37018 rs6000_print_options_internal (file, indent, string, flags, "-m",
37019 &rs6000_opt_masks[0],
37020 ARRAY_SIZE (rs6000_opt_masks));
37024 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37025 HOST_WIDE_INT flags)
37027 rs6000_print_options_internal (file, indent, string, flags, "",
37028 &rs6000_builtin_mask_names[0],
37029 ARRAY_SIZE (rs6000_builtin_mask_names));
37032 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37033 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37034 -mupper-regs-df, etc.).
37036 If the user used -mno-power8-vector, we need to turn off all of the implicit
37037 ISA 2.07 and 3.0 options that relate to the vector unit.
37039 If the user used -mno-power9-vector, we need to turn off all of the implicit
37040 ISA 3.0 options that relate to the vector unit.
37042 This function does not handle explicit options such as the user specifying
37043 -mdirect-move. These are handled in rs6000_option_override_internal, and
37044 the appropriate error is given if needed.
37046 We return a mask of all of the implicit options that should not be enabled
37049 static HOST_WIDE_INT
37050 rs6000_disable_incompatible_switches (void)
37052 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37055 static const struct {
37056 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37057 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37058 const char *const name; /* name of the switch. */
37060 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37061 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37062 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37065 for (i = 0; i < ARRAY_SIZE (flags); i++)
37067 HOST_WIDE_INT no_flag = flags[i].no_flag;
37069 if ((rs6000_isa_flags & no_flag) == 0
37070 && (rs6000_isa_flags_explicit & no_flag) != 0)
37072 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37073 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37079 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37080 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37082 set_flags &= ~rs6000_opt_masks[j].mask;
37083 error ("%<-mno-%s%> turns off %<-m%s%>",
37085 rs6000_opt_masks[j].name);
37088 gcc_assert (!set_flags);
37091 rs6000_isa_flags &= ~dep_flags;
37092 ignore_masks |= no_flag | dep_flags;
37096 return ignore_masks;
37100 /* Helper function for printing the function name when debugging. */
37102 static const char *
37103 get_decl_name (tree fn)
37110 name = DECL_NAME (fn);
37112 return "<no-name>";
37114 return IDENTIFIER_POINTER (name);
37117 /* Return the clone id of the target we are compiling code for in a target
37118 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37119 the priority list for the target clones (ordered from lowest to
37123 rs6000_clone_priority (tree fndecl)
37125 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37126 HOST_WIDE_INT isa_masks;
37127 int ret = CLONE_DEFAULT;
37128 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37129 const char *attrs_str = NULL;
37131 attrs = TREE_VALUE (TREE_VALUE (attrs));
37132 attrs_str = TREE_STRING_POINTER (attrs);
37134 /* Return priority zero for default function. Return the ISA needed for the
37135 function if it is not the default. */
37136 if (strcmp (attrs_str, "default") != 0)
37138 if (fn_opts == NULL_TREE)
37139 fn_opts = target_option_default_node;
37141 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37142 isa_masks = rs6000_isa_flags;
37144 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37146 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37147 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37151 if (TARGET_DEBUG_TARGET)
37152 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37153 get_decl_name (fndecl), ret);
37158 /* This compares the priority of target features in function DECL1 and DECL2.
37159 It returns positive value if DECL1 is higher priority, negative value if
37160 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37161 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37164 rs6000_compare_version_priority (tree decl1, tree decl2)
37166 int priority1 = rs6000_clone_priority (decl1);
37167 int priority2 = rs6000_clone_priority (decl2);
37168 int ret = priority1 - priority2;
37170 if (TARGET_DEBUG_TARGET)
37171 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37172 get_decl_name (decl1), get_decl_name (decl2), ret);
37177 /* Make a dispatcher declaration for the multi-versioned function DECL.
37178 Calls to DECL function will be replaced with calls to the dispatcher
37179 by the front-end. Returns the decl of the dispatcher function. */
37182 rs6000_get_function_versions_dispatcher (void *decl)
37184 tree fn = (tree) decl;
37185 struct cgraph_node *node = NULL;
37186 struct cgraph_node *default_node = NULL;
37187 struct cgraph_function_version_info *node_v = NULL;
37188 struct cgraph_function_version_info *first_v = NULL;
37190 tree dispatch_decl = NULL;
37192 struct cgraph_function_version_info *default_version_info = NULL;
37193 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37195 if (TARGET_DEBUG_TARGET)
37196 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37197 get_decl_name (fn));
37199 node = cgraph_node::get (fn);
37200 gcc_assert (node != NULL);
37202 node_v = node->function_version ();
37203 gcc_assert (node_v != NULL);
37205 if (node_v->dispatcher_resolver != NULL)
37206 return node_v->dispatcher_resolver;
37208 /* Find the default version and make it the first node. */
37210 /* Go to the beginning of the chain. */
37211 while (first_v->prev != NULL)
37212 first_v = first_v->prev;
37214 default_version_info = first_v;
37215 while (default_version_info != NULL)
37217 const tree decl2 = default_version_info->this_node->decl;
37218 if (is_function_default_version (decl2))
37220 default_version_info = default_version_info->next;
37223 /* If there is no default node, just return NULL. */
37224 if (default_version_info == NULL)
37227 /* Make default info the first node. */
37228 if (first_v != default_version_info)
37230 default_version_info->prev->next = default_version_info->next;
37231 if (default_version_info->next)
37232 default_version_info->next->prev = default_version_info->prev;
37233 first_v->prev = default_version_info;
37234 default_version_info->next = first_v;
37235 default_version_info->prev = NULL;
37238 default_node = default_version_info->this_node;
37240 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37241 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37242 "%<target_clones%> attribute needs GLIBC (2.23 and newer) that "
37243 "exports hardware capability bits");
37246 if (targetm.has_ifunc_p ())
37248 struct cgraph_function_version_info *it_v = NULL;
37249 struct cgraph_node *dispatcher_node = NULL;
37250 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37252 /* Right now, the dispatching is done via ifunc. */
37253 dispatch_decl = make_dispatcher_decl (default_node->decl);
37255 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37256 gcc_assert (dispatcher_node != NULL);
37257 dispatcher_node->dispatcher_function = 1;
37258 dispatcher_version_info
37259 = dispatcher_node->insert_new_function_version ();
37260 dispatcher_version_info->next = default_version_info;
37261 dispatcher_node->definition = 1;
37263 /* Set the dispatcher for all the versions. */
37264 it_v = default_version_info;
37265 while (it_v != NULL)
37267 it_v->dispatcher_resolver = dispatch_decl;
37273 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37274 "multiversioning needs ifunc which is not supported "
37279 return dispatch_decl;
37282 /* Make the resolver function decl to dispatch the versions of a multi-
37283 versioned function, DEFAULT_DECL. Create an empty basic block in the
37284 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37288 make_resolver_func (const tree default_decl,
37289 const tree dispatch_decl,
37290 basic_block *empty_bb)
37292 /* Make the resolver function static. The resolver function returns
37294 tree decl_name = clone_function_name (default_decl, "resolver");
37295 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37296 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37297 tree decl = build_fn_decl (resolver_name, type);
37298 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37300 DECL_NAME (decl) = decl_name;
37301 TREE_USED (decl) = 1;
37302 DECL_ARTIFICIAL (decl) = 1;
37303 DECL_IGNORED_P (decl) = 0;
37304 TREE_PUBLIC (decl) = 0;
37305 DECL_UNINLINABLE (decl) = 1;
37307 /* Resolver is not external, body is generated. */
37308 DECL_EXTERNAL (decl) = 0;
37309 DECL_EXTERNAL (dispatch_decl) = 0;
37311 DECL_CONTEXT (decl) = NULL_TREE;
37312 DECL_INITIAL (decl) = make_node (BLOCK);
37313 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37315 /* Build result decl and add to function_decl. */
37316 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37317 DECL_CONTEXT (t) = decl;
37318 DECL_ARTIFICIAL (t) = 1;
37319 DECL_IGNORED_P (t) = 1;
37320 DECL_RESULT (decl) = t;
37322 gimplify_function_tree (decl);
37323 push_cfun (DECL_STRUCT_FUNCTION (decl));
37324 *empty_bb = init_lowered_empty_function (decl, false,
37325 profile_count::uninitialized ());
37327 cgraph_node::add_new_function (decl, true);
37328 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37332 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37333 DECL_ATTRIBUTES (dispatch_decl)
37334 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37336 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37341 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37342 return a pointer to VERSION_DECL if we are running on a machine that
37343 supports the index CLONE_ISA hardware architecture bits. This function will
37344 be called during version dispatch to decide which function version to
37345 execute. It returns the basic block at the end, to which more conditions
37349 add_condition_to_bb (tree function_decl, tree version_decl,
37350 int clone_isa, basic_block new_bb)
37352 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37354 gcc_assert (new_bb != NULL);
37355 gimple_seq gseq = bb_seq (new_bb);
37358 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37359 build_fold_addr_expr (version_decl));
37360 tree result_var = create_tmp_var (ptr_type_node);
37361 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37362 gimple *return_stmt = gimple_build_return (result_var);
37364 if (clone_isa == CLONE_DEFAULT)
37366 gimple_seq_add_stmt (&gseq, convert_stmt);
37367 gimple_seq_add_stmt (&gseq, return_stmt);
37368 set_bb_seq (new_bb, gseq);
37369 gimple_set_bb (convert_stmt, new_bb);
37370 gimple_set_bb (return_stmt, new_bb);
37375 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37376 tree cond_var = create_tmp_var (bool_int_type_node);
37377 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37378 const char *arg_str = rs6000_clone_map[clone_isa].name;
37379 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37380 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37381 gimple_call_set_lhs (call_cond_stmt, cond_var);
37383 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37384 gimple_set_bb (call_cond_stmt, new_bb);
37385 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37387 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37388 NULL_TREE, NULL_TREE);
37389 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37390 gimple_set_bb (if_else_stmt, new_bb);
37391 gimple_seq_add_stmt (&gseq, if_else_stmt);
37393 gimple_seq_add_stmt (&gseq, convert_stmt);
37394 gimple_seq_add_stmt (&gseq, return_stmt);
37395 set_bb_seq (new_bb, gseq);
37397 basic_block bb1 = new_bb;
37398 edge e12 = split_block (bb1, if_else_stmt);
37399 basic_block bb2 = e12->dest;
37400 e12->flags &= ~EDGE_FALLTHRU;
37401 e12->flags |= EDGE_TRUE_VALUE;
37403 edge e23 = split_block (bb2, return_stmt);
37404 gimple_set_bb (convert_stmt, bb2);
37405 gimple_set_bb (return_stmt, bb2);
37407 basic_block bb3 = e23->dest;
37408 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37411 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37417 /* This function generates the dispatch function for multi-versioned functions.
37418 DISPATCH_DECL is the function which will contain the dispatch logic.
37419 FNDECLS are the function choices for dispatch, and is a tree chain.
37420 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37421 code is generated. */
37424 dispatch_function_versions (tree dispatch_decl,
37426 basic_block *empty_bb)
37430 vec<tree> *fndecls;
37431 tree clones[CLONE_MAX];
37433 if (TARGET_DEBUG_TARGET)
37434 fputs ("dispatch_function_versions, top\n", stderr);
37436 gcc_assert (dispatch_decl != NULL
37437 && fndecls_p != NULL
37438 && empty_bb != NULL);
37440 /* fndecls_p is actually a vector. */
37441 fndecls = static_cast<vec<tree> *> (fndecls_p);
37443 /* At least one more version other than the default. */
37444 gcc_assert (fndecls->length () >= 2);
37446 /* The first version in the vector is the default decl. */
37447 memset ((void *) clones, '\0', sizeof (clones));
37448 clones[CLONE_DEFAULT] = (*fndecls)[0];
37450 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37451 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37452 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37453 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37454 to insert the code here to do the call. */
37456 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37458 int priority = rs6000_clone_priority (ele);
37459 if (!clones[priority])
37460 clones[priority] = ele;
37463 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37466 if (TARGET_DEBUG_TARGET)
37467 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37468 ix, get_decl_name (clones[ix]));
37470 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37477 /* Generate the dispatching code body to dispatch multi-versioned function
37478 DECL. The target hook is called to process the "target" attributes and
37479 provide the code to dispatch the right function at run-time. NODE points
37480 to the dispatcher decl whose body will be created. */
37483 rs6000_generate_version_dispatcher_body (void *node_p)
37486 basic_block empty_bb;
37487 struct cgraph_node *node = (cgraph_node *) node_p;
37488 struct cgraph_function_version_info *ninfo = node->function_version ();
37490 if (ninfo->dispatcher_resolver)
37491 return ninfo->dispatcher_resolver;
37493 /* node is going to be an alias, so remove the finalized bit. */
37494 node->definition = false;
37496 /* The first version in the chain corresponds to the default version. */
37497 ninfo->dispatcher_resolver = resolver
37498 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37500 if (TARGET_DEBUG_TARGET)
37501 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37502 get_decl_name (resolver));
37504 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37505 auto_vec<tree, 2> fn_ver_vec;
37507 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37509 vinfo = vinfo->next)
37511 struct cgraph_node *version = vinfo->this_node;
37512 /* Check for virtual functions here again, as by this time it should
37513 have been determined if this function needs a vtable index or
37514 not. This happens for methods in derived classes that override
37515 virtual methods in base classes but are not explicitly marked as
37517 if (DECL_VINDEX (version->decl))
37518 sorry ("Virtual function multiversioning not supported");
37520 fn_ver_vec.safe_push (version->decl);
37523 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37524 cgraph_edge::rebuild_edges ();
37530 /* Hook to determine if one function can safely inline another. */
37533 rs6000_can_inline_p (tree caller, tree callee)
37536 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37537 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37539 /* If callee has no option attributes, then it is ok to inline. */
37543 /* If caller has no option attributes, but callee does then it is not ok to
37545 else if (!caller_tree)
37550 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37551 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37553 /* Callee's options should a subset of the caller's, i.e. a vsx function
37554 can inline an altivec function but a non-vsx function can't inline a
37556 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37557 == callee_opts->x_rs6000_isa_flags)
37561 if (TARGET_DEBUG_TARGET)
37562 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37563 get_decl_name (caller), get_decl_name (callee),
37564 (ret ? "can" : "cannot"));
37569 /* Allocate a stack temp and fixup the address so it meets the particular
37570 memory requirements (either offetable or REG+REG addressing). */
37573 rs6000_allocate_stack_temp (machine_mode mode,
37574 bool offsettable_p,
37577 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37578 rtx addr = XEXP (stack, 0);
37579 int strict_p = reload_completed;
37581 if (!legitimate_indirect_address_p (addr, strict_p))
37584 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37585 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37587 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37588 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37594 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37595 convert to such a form to deal with memory reference instructions
37596 like STFIWX and LDBRX that only take reg+reg addressing. */
37599 rs6000_force_indexed_or_indirect_mem (rtx x)
37601 machine_mode mode = GET_MODE (x);
37603 gcc_assert (MEM_P (x));
37604 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37606 rtx addr = XEXP (x, 0);
37607 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37609 rtx reg = XEXP (addr, 0);
37610 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37611 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37612 gcc_assert (REG_P (reg));
37613 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37616 else if (GET_CODE (addr) == PRE_MODIFY)
37618 rtx reg = XEXP (addr, 0);
37619 rtx expr = XEXP (addr, 1);
37620 gcc_assert (REG_P (reg));
37621 gcc_assert (GET_CODE (expr) == PLUS);
37622 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37626 x = replace_equiv_address (x, force_reg (Pmode, addr));
37632 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37634 On the RS/6000, all integer constants are acceptable, most won't be valid
37635 for particular insns, though. Only easy FP constants are acceptable. */
37638 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37640 if (TARGET_ELF && tls_referenced_p (x))
37643 if (CONST_DOUBLE_P (x))
37644 return easy_fp_constant (x, mode);
37646 if (GET_CODE (x) == CONST_VECTOR)
37647 return easy_vector_constant (x, mode);
37653 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37656 chain_already_loaded (rtx_insn *last)
37658 for (; last != NULL; last = PREV_INSN (last))
37660 if (NONJUMP_INSN_P (last))
37662 rtx patt = PATTERN (last);
37664 if (GET_CODE (patt) == SET)
37666 rtx lhs = XEXP (patt, 0);
37668 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37676 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37679 rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37681 rtx func = func_desc;
37682 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37683 rtx toc_load = NULL_RTX;
37684 rtx toc_restore = NULL_RTX;
37686 rtx abi_reg = NULL_RTX;
37690 bool is_pltseq_longcall;
37693 tlsarg = global_tlsarg;
37695 /* Handle longcall attributes. */
37696 is_pltseq_longcall = false;
37697 if ((INTVAL (cookie) & CALL_LONG) != 0
37698 && GET_CODE (func_desc) == SYMBOL_REF)
37700 func = rs6000_longcall_ref (func_desc, tlsarg);
37702 is_pltseq_longcall = true;
37705 /* Handle indirect calls. */
37706 if (!SYMBOL_REF_P (func)
37707 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func)))
37709 /* Save the TOC into its reserved slot before the call,
37710 and prepare to restore it after the call. */
37711 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37712 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37713 gen_rtvec (1, stack_toc_offset),
37715 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37717 /* Can we optimize saving the TOC in the prologue or
37718 do we need to do it at every call? */
37719 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37720 cfun->machine->save_toc_in_prologue = true;
37723 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37724 rtx stack_toc_mem = gen_frame_mem (Pmode,
37725 gen_rtx_PLUS (Pmode, stack_ptr,
37726 stack_toc_offset));
37727 MEM_VOLATILE_P (stack_toc_mem) = 1;
37728 if (is_pltseq_longcall)
37730 /* Use USPEC_PLTSEQ here to emit every instruction in an
37731 inline PLT call sequence with a reloc, enabling the
37732 linker to edit the sequence back to a direct call
37733 when that makes sense. */
37734 rtvec v = gen_rtvec (3, toc_reg, func_desc, tlsarg);
37735 rtx mark_toc_reg = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37736 emit_insn (gen_rtx_SET (stack_toc_mem, mark_toc_reg));
37739 emit_move_insn (stack_toc_mem, toc_reg);
37742 if (DEFAULT_ABI == ABI_ELFv2)
37744 /* A function pointer in the ELFv2 ABI is just a plain address, but
37745 the ABI requires it to be loaded into r12 before the call. */
37746 func_addr = gen_rtx_REG (Pmode, 12);
37747 if (!rtx_equal_p (func_addr, func))
37748 emit_move_insn (func_addr, func);
37749 abi_reg = func_addr;
37750 /* Indirect calls via CTR are strongly preferred over indirect
37751 calls via LR, so move the address there. Needed to mark
37752 this insn for linker plt sequence editing too. */
37753 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37754 if (is_pltseq_longcall)
37756 rtvec v = gen_rtvec (3, abi_reg, func_desc, tlsarg);
37757 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37758 emit_insn (gen_rtx_SET (func_addr, mark_func));
37759 v = gen_rtvec (2, func_addr, func_desc);
37760 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37763 emit_move_insn (func_addr, abi_reg);
37767 /* A function pointer under AIX is a pointer to a data area whose
37768 first word contains the actual address of the function, whose
37769 second word contains a pointer to its TOC, and whose third word
37770 contains a value to place in the static chain register (r11).
37771 Note that if we load the static chain, our "trampoline" need
37772 not have any executable code. */
37774 /* Load up address of the actual function. */
37775 func = force_reg (Pmode, func);
37776 func_addr = gen_reg_rtx (Pmode);
37777 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func));
37779 /* Indirect calls via CTR are strongly preferred over indirect
37780 calls via LR, so move the address there. */
37781 rtx ctr_reg = gen_rtx_REG (Pmode, CTR_REGNO);
37782 emit_move_insn (ctr_reg, func_addr);
37783 func_addr = ctr_reg;
37785 /* Prepare to load the TOC of the called function. Note that the
37786 TOC load must happen immediately before the actual call so
37787 that unwinding the TOC registers works correctly. See the
37788 comment in frob_update_context. */
37789 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37790 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37791 gen_rtx_PLUS (Pmode, func,
37793 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37795 /* If we have a static chain, load it up. But, if the call was
37796 originally direct, the 3rd word has not been written since no
37797 trampoline has been built, so we ought not to load it, lest we
37798 override a static chain value. */
37799 if (!(GET_CODE (func_desc) == SYMBOL_REF
37800 && SYMBOL_REF_FUNCTION_P (func_desc))
37801 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37802 && !chain_already_loaded (get_current_sequence ()->next->last))
37804 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37805 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37806 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37807 gen_rtx_PLUS (Pmode, func,
37809 emit_move_insn (sc_reg, func_sc_mem);
37816 /* Direct calls use the TOC: for local calls, the callee will
37817 assume the TOC register is set; for non-local calls, the
37818 PLT stub needs the TOC register. */
37823 /* Create the call. */
37824 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37825 if (value != NULL_RTX)
37826 call[0] = gen_rtx_SET (value, call[0]);
37830 call[n_call++] = toc_load;
37832 call[n_call++] = toc_restore;
37834 call[n_call++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37836 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37837 insn = emit_call_insn (insn);
37839 /* Mention all registers defined by the ABI to hold information
37840 as uses in CALL_INSN_FUNCTION_USAGE. */
37842 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37845 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37848 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37853 gcc_assert (INTVAL (cookie) == 0);
37856 tlsarg = global_tlsarg;
37858 /* Create the call. */
37859 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), tlsarg);
37860 if (value != NULL_RTX)
37861 call[0] = gen_rtx_SET (value, call[0]);
37863 call[1] = simple_return_rtx;
37865 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37866 insn = emit_call_insn (insn);
37868 /* Note use of the TOC register. */
37869 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37872 /* Expand code to perform a call under the SYSV4 ABI. */
37875 rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37877 rtx func = func_desc;
37881 rtx abi_reg = NULL_RTX;
37885 tlsarg = global_tlsarg;
37887 /* Handle longcall attributes. */
37888 if ((INTVAL (cookie) & CALL_LONG) != 0
37889 && GET_CODE (func_desc) == SYMBOL_REF)
37891 func = rs6000_longcall_ref (func_desc, tlsarg);
37892 /* If the longcall was implemented as an inline PLT call using
37893 PLT unspecs then func will be REG:r11. If not, func will be
37894 a pseudo reg. The inline PLT call sequence supports lazy
37895 linking (and longcalls to functions in dlopen'd libraries).
37896 The other style of longcalls don't. The lazy linking entry
37897 to the dynamic symbol resolver requires r11 be the function
37898 address (as it is for linker generated PLT stubs). Ensure
37899 r11 stays valid to the bctrl by marking r11 used by the call. */
37904 /* Handle indirect calls. */
37905 if (GET_CODE (func) != SYMBOL_REF)
37907 func = force_reg (Pmode, func);
37909 /* Indirect calls via CTR are strongly preferred over indirect
37910 calls via LR, so move the address there. That can't be left
37911 to reload because we want to mark every instruction in an
37912 inline PLT call sequence with a reloc, enabling the linker to
37913 edit the sequence back to a direct call when that makes sense. */
37914 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37917 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37918 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37919 emit_insn (gen_rtx_SET (func_addr, mark_func));
37920 v = gen_rtvec (2, func_addr, func_desc);
37921 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37924 emit_move_insn (func_addr, func);
37929 /* Create the call. */
37930 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37931 if (value != NULL_RTX)
37932 call[0] = gen_rtx_SET (value, call[0]);
37934 call[1] = gen_rtx_USE (VOIDmode, cookie);
37936 if (TARGET_SECURE_PLT
37938 && GET_CODE (func_addr) == SYMBOL_REF
37939 && !SYMBOL_REF_LOCAL_P (func_addr))
37940 call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
37942 call[n++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37944 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n, call));
37945 insn = emit_call_insn (insn);
37947 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37950 /* Expand code to perform a sibling call under the SysV4 ABI. */
37953 rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37955 rtx func = func_desc;
37959 rtx abi_reg = NULL_RTX;
37962 tlsarg = global_tlsarg;
37964 /* Handle longcall attributes. */
37965 if ((INTVAL (cookie) & CALL_LONG) != 0
37966 && GET_CODE (func_desc) == SYMBOL_REF)
37968 func = rs6000_longcall_ref (func_desc, tlsarg);
37969 /* If the longcall was implemented as an inline PLT call using
37970 PLT unspecs then func will be REG:r11. If not, func will be
37971 a pseudo reg. The inline PLT call sequence supports lazy
37972 linking (and longcalls to functions in dlopen'd libraries).
37973 The other style of longcalls don't. The lazy linking entry
37974 to the dynamic symbol resolver requires r11 be the function
37975 address (as it is for linker generated PLT stubs). Ensure
37976 r11 stays valid to the bctr by marking r11 used by the call. */
37981 /* Handle indirect calls. */
37982 if (GET_CODE (func) != SYMBOL_REF)
37984 func = force_reg (Pmode, func);
37986 /* Indirect sibcalls must go via CTR. That can't be left to
37987 reload because we want to mark every instruction in an inline
37988 PLT call sequence with a reloc, enabling the linker to edit
37989 the sequence back to a direct call when that makes sense. */
37990 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37993 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37994 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37995 emit_insn (gen_rtx_SET (func_addr, mark_func));
37996 v = gen_rtvec (2, func_addr, func_desc);
37997 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
38000 emit_move_insn (func_addr, func);
38005 /* Create the call. */
38006 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38007 if (value != NULL_RTX)
38008 call[0] = gen_rtx_SET (value, call[0]);
38010 call[1] = gen_rtx_USE (VOIDmode, cookie);
38011 call[2] = simple_return_rtx;
38013 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38014 insn = emit_call_insn (insn);
38016 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38021 /* Expand code to perform a call under the Darwin ABI.
38022 Modulo handling of mlongcall, this is much the same as sysv.
38023 if/when the longcall optimisation is removed, we could drop this
38024 code and use the sysv case (taking care to avoid the tls stuff).
38026 We can use this for sibcalls too, if needed. */
38029 rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
38030 rtx cookie, bool sibcall)
38032 rtx func = func_desc;
38036 int cookie_val = INTVAL (cookie);
38037 bool make_island = false;
38039 /* Handle longcall attributes, there are two cases for Darwin:
38040 1) Newer linkers are capable of synthesising any branch islands needed.
38041 2) We need a helper branch island synthesised by the compiler.
38042 The second case has mostly been retired and we don't use it for m64.
38043 In fact, it's is an optimisation, we could just indirect as sysv does..
38044 ... however, backwards compatibility for now.
38045 If we're going to use this, then we need to keep the CALL_LONG bit set,
38046 so that we can pick up the special insn form later. */
38047 if ((cookie_val & CALL_LONG) != 0
38048 && GET_CODE (func_desc) == SYMBOL_REF)
38050 if (darwin_emit_branch_islands && TARGET_32BIT)
38051 make_island = true; /* Do nothing yet, retain the CALL_LONG flag. */
38054 /* The linker is capable of doing this, but the user explicitly
38055 asked for -mlongcall, so we'll do the 'normal' version. */
38056 func = rs6000_longcall_ref (func_desc, NULL_RTX);
38057 cookie_val &= ~CALL_LONG; /* Handled, zap it. */
38061 /* Handle indirect calls. */
38062 if (GET_CODE (func) != SYMBOL_REF)
38064 func = force_reg (Pmode, func);
38066 /* Indirect calls via CTR are strongly preferred over indirect
38067 calls via LR, and are required for indirect sibcalls, so move
38068 the address there. */
38069 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38070 emit_move_insn (func_addr, func);
38075 /* Create the call. */
38076 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38077 if (value != NULL_RTX)
38078 call[0] = gen_rtx_SET (value, call[0]);
38080 call[1] = gen_rtx_USE (VOIDmode, GEN_INT (cookie_val));
38083 call[2] = simple_return_rtx;
38085 call[2] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38087 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38088 insn = emit_call_insn (insn);
38089 /* Now we have the debug info in the insn, we can set up the branch island
38090 if we're using one. */
38093 tree funname = get_identifier (XSTR (func_desc, 0));
38095 if (no_previous_def (funname))
38097 rtx label_rtx = gen_label_rtx ();
38098 char *label_buf, temp_buf[256];
38099 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
38100 CODE_LABEL_NUMBER (label_rtx));
38101 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
38102 tree labelname = get_identifier (label_buf);
38103 add_compiler_branch_island (labelname, funname,
38104 insn_line ((const rtx_insn*)insn));
38111 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38112 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38115 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, false);
38123 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38124 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38127 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, true);
38134 /* Return whether we need to always update the saved TOC pointer when we update
38135 the stack pointer. */
38138 rs6000_save_toc_in_prologue_p (void)
38140 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38143 /* Return whether we should generate PC-relative code for FNDECL. */
38145 rs6000_fndecl_pcrel_p (const_tree fndecl)
38147 if (DEFAULT_ABI != ABI_ELFv2)
38150 struct cl_target_option *opts = target_opts_for_fn (fndecl);
38152 return ((opts->x_rs6000_isa_flags & OPTION_MASK_PCREL) != 0
38153 && TARGET_CMODEL == CMODEL_MEDIUM);
38156 /* Return whether we should generate PC-relative code for *FN. */
38158 rs6000_pcrel_p (struct function *fn)
38160 if (DEFAULT_ABI != ABI_ELFv2)
38163 /* Optimize usual case. */
38165 return ((rs6000_isa_flags & OPTION_MASK_PCREL) != 0
38166 && TARGET_CMODEL == CMODEL_MEDIUM);
38168 return rs6000_fndecl_pcrel_p (fn->decl);
38171 #ifdef HAVE_GAS_HIDDEN
38172 # define USE_HIDDEN_LINKONCE 1
38174 # define USE_HIDDEN_LINKONCE 0
38177 /* Fills in the label name that should be used for a 476 link stack thunk. */
38180 get_ppc476_thunk_name (char name[32])
38182 gcc_assert (TARGET_LINK_STACK);
38184 if (USE_HIDDEN_LINKONCE)
38185 sprintf (name, "__ppc476.get_thunk");
38187 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38190 /* This function emits the simple thunk routine that is used to preserve
38191 the link stack on the 476 cpu. */
38193 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38195 rs6000_code_end (void)
38200 if (!TARGET_LINK_STACK)
38203 get_ppc476_thunk_name (name);
38205 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38206 build_function_type_list (void_type_node, NULL_TREE));
38207 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38208 NULL_TREE, void_type_node);
38209 TREE_PUBLIC (decl) = 1;
38210 TREE_STATIC (decl) = 1;
38213 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38215 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38216 targetm.asm_out.unique_section (decl, 0);
38217 switch_to_section (get_named_section (decl, NULL, 0));
38218 DECL_WEAK (decl) = 1;
38219 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38220 targetm.asm_out.globalize_label (asm_out_file, name);
38221 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38222 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38227 switch_to_section (text_section);
38228 ASM_OUTPUT_LABEL (asm_out_file, name);
38231 DECL_INITIAL (decl) = make_node (BLOCK);
38232 current_function_decl = decl;
38233 allocate_struct_function (decl, false);
38234 init_function_start (decl);
38235 first_function_block_is_cold = false;
38236 /* Make sure unwind info is emitted for the thunk if needed. */
38237 final_start_function (emit_barrier (), asm_out_file, 1);
38239 fputs ("\tblr\n", asm_out_file);
38241 final_end_function ();
38242 init_insn_lengths ();
38243 free_after_compilation (cfun);
38245 current_function_decl = NULL;
38248 /* Add r30 to hard reg set if the prologue sets it up and it is not
38249 pic_offset_table_rtx. */
38252 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38254 if (!TARGET_SINGLE_PIC_BASE
38256 && TARGET_MINIMAL_TOC
38257 && !constant_pool_empty_p ())
38258 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38259 if (cfun->machine->split_stack_argp_used)
38260 add_to_hard_reg_set (&set->set, Pmode, 12);
38262 /* Make sure the hard reg set doesn't include r2, which was possibly added
38263 via PIC_OFFSET_TABLE_REGNUM. */
38265 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38269 /* Helper function for rs6000_split_logical to emit a logical instruction after
38270 spliting the operation to single GPR registers.
38272 DEST is the destination register.
38273 OP1 and OP2 are the input source registers.
38274 CODE is the base operation (AND, IOR, XOR, NOT).
38275 MODE is the machine mode.
38276 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38277 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38278 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38281 rs6000_split_logical_inner (rtx dest,
38284 enum rtx_code code,
38286 bool complement_final_p,
38287 bool complement_op1_p,
38288 bool complement_op2_p)
38292 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38293 if (op2 && CONST_INT_P (op2)
38294 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38295 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38297 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38298 HOST_WIDE_INT value = INTVAL (op2) & mask;
38300 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38305 emit_insn (gen_rtx_SET (dest, const0_rtx));
38309 else if (value == mask)
38311 if (!rtx_equal_p (dest, op1))
38312 emit_insn (gen_rtx_SET (dest, op1));
38317 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38318 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38319 else if (code == IOR || code == XOR)
38323 if (!rtx_equal_p (dest, op1))
38324 emit_insn (gen_rtx_SET (dest, op1));
38330 if (code == AND && mode == SImode
38331 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38333 emit_insn (gen_andsi3 (dest, op1, op2));
38337 if (complement_op1_p)
38338 op1 = gen_rtx_NOT (mode, op1);
38340 if (complement_op2_p)
38341 op2 = gen_rtx_NOT (mode, op2);
38343 /* For canonical RTL, if only one arm is inverted it is the first. */
38344 if (!complement_op1_p && complement_op2_p)
38345 std::swap (op1, op2);
38347 bool_rtx = ((code == NOT)
38348 ? gen_rtx_NOT (mode, op1)
38349 : gen_rtx_fmt_ee (code, mode, op1, op2));
38351 if (complement_final_p)
38352 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38354 emit_insn (gen_rtx_SET (dest, bool_rtx));
38357 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38358 operations are split immediately during RTL generation to allow for more
38359 optimizations of the AND/IOR/XOR.
38361 OPERANDS is an array containing the destination and two input operands.
38362 CODE is the base operation (AND, IOR, XOR, NOT).
38363 MODE is the machine mode.
38364 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38365 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38366 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38367 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38368 formation of the AND instructions. */
38371 rs6000_split_logical_di (rtx operands[3],
38372 enum rtx_code code,
38373 bool complement_final_p,
38374 bool complement_op1_p,
38375 bool complement_op2_p)
38377 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38378 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38379 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38380 enum hi_lo { hi = 0, lo = 1 };
38381 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38384 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38385 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38386 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38387 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38390 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38393 if (!CONST_INT_P (operands[2]))
38395 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38396 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38400 HOST_WIDE_INT value = INTVAL (operands[2]);
38401 HOST_WIDE_INT value_hi_lo[2];
38403 gcc_assert (!complement_final_p);
38404 gcc_assert (!complement_op1_p);
38405 gcc_assert (!complement_op2_p);
38407 value_hi_lo[hi] = value >> 32;
38408 value_hi_lo[lo] = value & lower_32bits;
38410 for (i = 0; i < 2; i++)
38412 HOST_WIDE_INT sub_value = value_hi_lo[i];
38414 if (sub_value & sign_bit)
38415 sub_value |= upper_32bits;
38417 op2_hi_lo[i] = GEN_INT (sub_value);
38419 /* If this is an AND instruction, check to see if we need to load
38420 the value in a register. */
38421 if (code == AND && sub_value != -1 && sub_value != 0
38422 && !and_operand (op2_hi_lo[i], SImode))
38423 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38428 for (i = 0; i < 2; i++)
38430 /* Split large IOR/XOR operations. */
38431 if ((code == IOR || code == XOR)
38432 && CONST_INT_P (op2_hi_lo[i])
38433 && !complement_final_p
38434 && !complement_op1_p
38435 && !complement_op2_p
38436 && !logical_const_operand (op2_hi_lo[i], SImode))
38438 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38439 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38440 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38441 rtx tmp = gen_reg_rtx (SImode);
38443 /* Make sure the constant is sign extended. */
38444 if ((hi_16bits & sign_bit) != 0)
38445 hi_16bits |= upper_32bits;
38447 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38448 code, SImode, false, false, false);
38450 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38451 code, SImode, false, false, false);
38454 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38455 code, SImode, complement_final_p,
38456 complement_op1_p, complement_op2_p);
38462 /* Split the insns that make up boolean operations operating on multiple GPR
38463 registers. The boolean MD patterns ensure that the inputs either are
38464 exactly the same as the output registers, or there is no overlap.
38466 OPERANDS is an array containing the destination and two input operands.
38467 CODE is the base operation (AND, IOR, XOR, NOT).
38468 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38469 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38470 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38473 rs6000_split_logical (rtx operands[3],
38474 enum rtx_code code,
38475 bool complement_final_p,
38476 bool complement_op1_p,
38477 bool complement_op2_p)
38479 machine_mode mode = GET_MODE (operands[0]);
38480 machine_mode sub_mode;
38482 int sub_size, regno0, regno1, nregs, i;
38484 /* If this is DImode, use the specialized version that can run before
38485 register allocation. */
38486 if (mode == DImode && !TARGET_POWERPC64)
38488 rs6000_split_logical_di (operands, code, complement_final_p,
38489 complement_op1_p, complement_op2_p);
38495 op2 = (code == NOT) ? NULL_RTX : operands[2];
38496 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38497 sub_size = GET_MODE_SIZE (sub_mode);
38498 regno0 = REGNO (op0);
38499 regno1 = REGNO (op1);
38501 gcc_assert (reload_completed);
38502 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38503 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38505 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38506 gcc_assert (nregs > 1);
38508 if (op2 && REG_P (op2))
38509 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38511 for (i = 0; i < nregs; i++)
38513 int offset = i * sub_size;
38514 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38515 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38516 rtx sub_op2 = ((code == NOT)
38518 : simplify_subreg (sub_mode, op2, mode, offset));
38520 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38521 complement_final_p, complement_op1_p,
38529 /* Return true if the peephole2 can combine a load involving a combination of
38530 an addis instruction and a load with an offset that can be fused together on
38534 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38535 rtx addis_value, /* addis value. */
38536 rtx target, /* target register that is loaded. */
38537 rtx mem) /* bottom part of the memory addr. */
38542 /* Validate arguments. */
38543 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38546 if (!base_reg_operand (target, GET_MODE (target)))
38549 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38552 /* Allow sign/zero extension. */
38553 if (GET_CODE (mem) == ZERO_EXTEND
38554 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38555 mem = XEXP (mem, 0);
38560 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38563 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38564 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38567 /* Validate that the register used to load the high value is either the
38568 register being loaded, or we can safely replace its use.
38570 This function is only called from the peephole2 pass and we assume that
38571 there are 2 instructions in the peephole (addis and load), so we want to
38572 check if the target register was not used in the memory address and the
38573 register to hold the addis result is dead after the peephole. */
38574 if (REGNO (addis_reg) != REGNO (target))
38576 if (reg_mentioned_p (target, mem))
38579 if (!peep2_reg_dead_p (2, addis_reg))
38582 /* If the target register being loaded is the stack pointer, we must
38583 avoid loading any other value into it, even temporarily. */
38584 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38588 base_reg = XEXP (addr, 0);
38589 return REGNO (addis_reg) == REGNO (base_reg);
38592 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38593 sequence. We adjust the addis register to use the target register. If the
38594 load sign extends, we adjust the code to do the zero extending load, and an
38595 explicit sign extension later since the fusion only covers zero extending
38599 operands[0] register set with addis (to be replaced with target)
38600 operands[1] value set via addis
38601 operands[2] target register being loaded
38602 operands[3] D-form memory reference using operands[0]. */
38605 expand_fusion_gpr_load (rtx *operands)
38607 rtx addis_value = operands[1];
38608 rtx target = operands[2];
38609 rtx orig_mem = operands[3];
38610 rtx new_addr, new_mem, orig_addr, offset;
38611 enum rtx_code plus_or_lo_sum;
38612 machine_mode target_mode = GET_MODE (target);
38613 machine_mode extend_mode = target_mode;
38614 machine_mode ptr_mode = Pmode;
38615 enum rtx_code extend = UNKNOWN;
38617 if (GET_CODE (orig_mem) == ZERO_EXTEND
38618 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38620 extend = GET_CODE (orig_mem);
38621 orig_mem = XEXP (orig_mem, 0);
38622 target_mode = GET_MODE (orig_mem);
38625 gcc_assert (MEM_P (orig_mem));
38627 orig_addr = XEXP (orig_mem, 0);
38628 plus_or_lo_sum = GET_CODE (orig_addr);
38629 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38631 offset = XEXP (orig_addr, 1);
38632 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38633 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38635 if (extend != UNKNOWN)
38636 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38638 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38639 UNSPEC_FUSION_GPR);
38640 emit_insn (gen_rtx_SET (target, new_mem));
38642 if (extend == SIGN_EXTEND)
38644 int sub_off = ((BYTES_BIG_ENDIAN)
38645 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38648 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38650 emit_insn (gen_rtx_SET (target,
38651 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38657 /* Emit the addis instruction that will be part of a fused instruction
38661 emit_fusion_addis (rtx target, rtx addis_value)
38664 const char *addis_str = NULL;
38666 /* Emit the addis instruction. */
38667 fuse_ops[0] = target;
38668 if (satisfies_constraint_L (addis_value))
38670 fuse_ops[1] = addis_value;
38671 addis_str = "lis %0,%v1";
38674 else if (GET_CODE (addis_value) == PLUS)
38676 rtx op0 = XEXP (addis_value, 0);
38677 rtx op1 = XEXP (addis_value, 1);
38679 if (REG_P (op0) && CONST_INT_P (op1)
38680 && satisfies_constraint_L (op1))
38684 addis_str = "addis %0,%1,%v2";
38688 else if (GET_CODE (addis_value) == HIGH)
38690 rtx value = XEXP (addis_value, 0);
38691 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38693 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38694 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38696 addis_str = "addis %0,%2,%1@toc@ha";
38698 else if (TARGET_XCOFF)
38699 addis_str = "addis %0,%1@u(%2)";
38702 gcc_unreachable ();
38705 else if (GET_CODE (value) == PLUS)
38707 rtx op0 = XEXP (value, 0);
38708 rtx op1 = XEXP (value, 1);
38710 if (GET_CODE (op0) == UNSPEC
38711 && XINT (op0, 1) == UNSPEC_TOCREL
38712 && CONST_INT_P (op1))
38714 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38715 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38718 addis_str = "addis %0,%2,%1+%3@toc@ha";
38720 else if (TARGET_XCOFF)
38721 addis_str = "addis %0,%1+%3@u(%2)";
38724 gcc_unreachable ();
38728 else if (satisfies_constraint_L (value))
38730 fuse_ops[1] = value;
38731 addis_str = "lis %0,%v1";
38734 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38736 fuse_ops[1] = value;
38737 addis_str = "lis %0,%1@ha";
38742 fatal_insn ("Could not generate addis value for fusion", addis_value);
38744 output_asm_insn (addis_str, fuse_ops);
38747 /* Emit a D-form load or store instruction that is the second instruction
38748 of a fusion sequence. */
38751 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38754 char insn_template[80];
38756 fuse_ops[0] = load_reg;
38757 fuse_ops[1] = addis_reg;
38759 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38761 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38762 fuse_ops[2] = offset;
38763 output_asm_insn (insn_template, fuse_ops);
38766 else if (GET_CODE (offset) == UNSPEC
38767 && XINT (offset, 1) == UNSPEC_TOCREL)
38770 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38772 else if (TARGET_XCOFF)
38773 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38776 gcc_unreachable ();
38778 fuse_ops[2] = XVECEXP (offset, 0, 0);
38779 output_asm_insn (insn_template, fuse_ops);
38782 else if (GET_CODE (offset) == PLUS
38783 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38784 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38785 && CONST_INT_P (XEXP (offset, 1)))
38787 rtx tocrel_unspec = XEXP (offset, 0);
38789 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38791 else if (TARGET_XCOFF)
38792 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38795 gcc_unreachable ();
38797 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38798 fuse_ops[3] = XEXP (offset, 1);
38799 output_asm_insn (insn_template, fuse_ops);
38802 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38804 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38806 fuse_ops[2] = offset;
38807 output_asm_insn (insn_template, fuse_ops);
38811 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38816 /* Given an address, convert it into the addis and load offset parts. Addresses
38817 created during the peephole2 process look like:
38818 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38819 (unspec [(...)] UNSPEC_TOCREL)) */
38822 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38826 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38828 hi = XEXP (addr, 0);
38829 lo = XEXP (addr, 1);
38832 gcc_unreachable ();
38838 /* Return a string to fuse an addis instruction with a gpr load to the same
38839 register that we loaded up the addis instruction. The address that is used
38840 is the logical address that was formed during peephole2:
38841 (lo_sum (high) (low-part))
38843 The code is complicated, so we call output_asm_insn directly, and just
38847 emit_fusion_gpr_load (rtx target, rtx mem)
38852 const char *load_str = NULL;
38855 if (GET_CODE (mem) == ZERO_EXTEND)
38856 mem = XEXP (mem, 0);
38858 gcc_assert (REG_P (target) && MEM_P (mem));
38860 addr = XEXP (mem, 0);
38861 fusion_split_address (addr, &addis_value, &load_offset);
38863 /* Now emit the load instruction to the same register. */
38864 mode = GET_MODE (mem);
38882 gcc_assert (TARGET_POWERPC64);
38887 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38890 /* Emit the addis instruction. */
38891 emit_fusion_addis (target, addis_value);
38893 /* Emit the D-form load instruction. */
38894 emit_fusion_load (target, target, load_offset, load_str);
38900 #ifdef RS6000_GLIBC_ATOMIC_FENV
38901 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38902 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38905 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38908 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38910 if (!TARGET_HARD_FLOAT)
38912 #ifdef RS6000_GLIBC_ATOMIC_FENV
38913 if (atomic_hold_decl == NULL_TREE)
38916 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38917 get_identifier ("__atomic_feholdexcept"),
38918 build_function_type_list (void_type_node,
38919 double_ptr_type_node,
38921 TREE_PUBLIC (atomic_hold_decl) = 1;
38922 DECL_EXTERNAL (atomic_hold_decl) = 1;
38925 if (atomic_clear_decl == NULL_TREE)
38928 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38929 get_identifier ("__atomic_feclearexcept"),
38930 build_function_type_list (void_type_node,
38932 TREE_PUBLIC (atomic_clear_decl) = 1;
38933 DECL_EXTERNAL (atomic_clear_decl) = 1;
38936 tree const_double = build_qualified_type (double_type_node,
38938 tree const_double_ptr = build_pointer_type (const_double);
38939 if (atomic_update_decl == NULL_TREE)
38942 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38943 get_identifier ("__atomic_feupdateenv"),
38944 build_function_type_list (void_type_node,
38947 TREE_PUBLIC (atomic_update_decl) = 1;
38948 DECL_EXTERNAL (atomic_update_decl) = 1;
38951 tree fenv_var = create_tmp_var_raw (double_type_node);
38952 TREE_ADDRESSABLE (fenv_var) = 1;
38953 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38955 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38956 *clear = build_call_expr (atomic_clear_decl, 0);
38957 *update = build_call_expr (atomic_update_decl, 1,
38958 fold_convert (const_double_ptr, fenv_addr));
38963 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38964 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38965 tree call_mffs = build_call_expr (mffs, 0);
38967 /* Generates the equivalent of feholdexcept (&fenv_var)
38969 *fenv_var = __builtin_mffs ();
38971 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38972 __builtin_mtfsf (0xff, fenv_hold); */
38974 /* Mask to clear everything except for the rounding modes and non-IEEE
38975 arithmetic flag. */
38976 const unsigned HOST_WIDE_INT hold_exception_mask =
38977 HOST_WIDE_INT_C (0xffffffff00000007);
38979 tree fenv_var = create_tmp_var_raw (double_type_node);
38981 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38983 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38984 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38985 build_int_cst (uint64_type_node,
38986 hold_exception_mask));
38988 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38991 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38992 build_int_cst (unsigned_type_node, 0xff),
38995 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38997 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38999 double fenv_clear = __builtin_mffs ();
39000 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39001 __builtin_mtfsf (0xff, fenv_clear); */
39003 /* Mask to clear everything except for the rounding modes and non-IEEE
39004 arithmetic flag. */
39005 const unsigned HOST_WIDE_INT clear_exception_mask =
39006 HOST_WIDE_INT_C (0xffffffff00000000);
39008 tree fenv_clear = create_tmp_var_raw (double_type_node);
39010 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39012 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39013 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39015 build_int_cst (uint64_type_node,
39016 clear_exception_mask));
39018 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39019 fenv_clear_llu_and);
39021 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39022 build_int_cst (unsigned_type_node, 0xff),
39025 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39027 /* Generates the equivalent of feupdateenv (&fenv_var)
39029 double old_fenv = __builtin_mffs ();
39030 double fenv_update;
39031 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39032 (*(uint64_t*)fenv_var 0x1ff80fff);
39033 __builtin_mtfsf (0xff, fenv_update); */
39035 const unsigned HOST_WIDE_INT update_exception_mask =
39036 HOST_WIDE_INT_C (0xffffffff1fffff00);
39037 const unsigned HOST_WIDE_INT new_exception_mask =
39038 HOST_WIDE_INT_C (0x1ff80fff);
39040 tree old_fenv = create_tmp_var_raw (double_type_node);
39041 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39043 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39044 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39045 build_int_cst (uint64_type_node,
39046 update_exception_mask));
39048 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39049 build_int_cst (uint64_type_node,
39050 new_exception_mask));
39052 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39053 old_llu_and, new_llu_and);
39055 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39058 tree update_mtfsf = build_call_expr (mtfsf, 2,
39059 build_int_cst (unsigned_type_node, 0xff),
39060 fenv_update_mtfsf);
39062 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39066 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39068 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39070 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39071 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39073 /* The destination of the vmrgew instruction layout is:
39074 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39075 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39076 vmrgew instruction will be correct. */
39077 if (BYTES_BIG_ENDIAN)
39079 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39081 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39086 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39087 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39090 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39091 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39093 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39094 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39096 if (BYTES_BIG_ENDIAN)
39097 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39099 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39103 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39105 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39107 rtx_tmp0 = gen_reg_rtx (V2DImode);
39108 rtx_tmp1 = gen_reg_rtx (V2DImode);
39110 /* The destination of the vmrgew instruction layout is:
39111 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39112 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39113 vmrgew instruction will be correct. */
39114 if (BYTES_BIG_ENDIAN)
39116 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39117 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39121 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39122 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39125 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39126 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39128 if (signed_convert)
39130 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39131 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39135 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39136 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39139 if (BYTES_BIG_ENDIAN)
39140 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39142 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39146 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39149 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39151 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39152 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39154 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39155 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39157 rtx_tmp2 = gen_reg_rtx (V4SImode);
39158 rtx_tmp3 = gen_reg_rtx (V4SImode);
39160 if (signed_convert)
39162 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39163 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39167 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39168 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39171 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39174 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39177 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39178 optimization_type opt_type)
39183 return (opt_type == OPTIMIZE_FOR_SPEED
39184 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39191 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39193 static HOST_WIDE_INT
39194 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39196 if (TREE_CODE (exp) == STRING_CST
39197 && (STRICT_ALIGNMENT || !optimize_size))
39198 return MAX (align, BITS_PER_WORD);
39202 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39204 static HOST_WIDE_INT
39205 rs6000_starting_frame_offset (void)
39207 if (FRAME_GROWS_DOWNWARD)
39209 return RS6000_STARTING_FRAME_OFFSET;
39213 /* Create an alias for a mangled name where we have changed the mangling (in
39214 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39215 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39217 #if TARGET_ELF && RS6000_WEAK
39219 rs6000_globalize_decl_name (FILE * stream, tree decl)
39221 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
39223 targetm.asm_out.globalize_label (stream, name);
39225 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
39227 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
39228 const char *old_name;
39230 ieee128_mangling_gcc_8_1 = true;
39231 lang_hooks.set_decl_assembler_name (decl);
39232 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
39233 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
39234 ieee128_mangling_gcc_8_1 = false;
39236 if (strcmp (name, old_name) != 0)
39238 fprintf (stream, "\t.weak %s\n", old_name);
39239 fprintf (stream, "\t.set %s,%s\n", old_name, name);
39246 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39247 function names from <foo>l to <foo>f128 if the default long double type is
39248 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39249 include file switches the names on systems that support long double as IEEE
39250 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39251 In the future, glibc will export names like __ieee128_sinf128 and we can
39252 switch to using those instead of using sinf128, which pollutes the user's
39255 This will switch the names for Fortran math functions as well (which doesn't
39256 use math.h). However, Fortran needs other changes to the compiler and
39257 library before you can switch the real*16 type at compile time.
39259 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39260 only do this if the default is that long double is IBM extended double, and
39261 the user asked for IEEE 128-bit. */
39264 rs6000_mangle_decl_assembler_name (tree decl, tree id)
39266 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
39267 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
39269 size_t len = IDENTIFIER_LENGTH (id);
39270 const char *name = IDENTIFIER_POINTER (id);
39272 if (name[len - 1] == 'l')
39274 bool uses_ieee128_p = false;
39275 tree type = TREE_TYPE (decl);
39276 machine_mode ret_mode = TYPE_MODE (type);
39278 /* See if the function returns a IEEE 128-bit floating point type or
39280 if (ret_mode == TFmode || ret_mode == TCmode)
39281 uses_ieee128_p = true;
39284 function_args_iterator args_iter;
39287 /* See if the function passes a IEEE 128-bit floating point type
39288 or complex type. */
39289 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
39291 machine_mode arg_mode = TYPE_MODE (arg);
39292 if (arg_mode == TFmode || arg_mode == TCmode)
39294 uses_ieee128_p = true;
39300 /* If we passed or returned an IEEE 128-bit floating point type,
39301 change the name. */
39302 if (uses_ieee128_p)
39304 char *name2 = (char *) alloca (len + 4);
39305 memcpy (name2, name, len - 1);
39306 strcpy (name2 + len - 1, "f128");
39307 id = get_identifier (name2);
39316 struct gcc_target targetm = TARGET_INITIALIZER;
39318 #include "gt-rs6000.h"